// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
// Date        : Tue Mar 28 17:13:07 2023
// Host        : TRL running 64-bit Ubuntu 20.04.6 LTS
// Command     : write_verilog -force -mode funcsim
//               /home/sd/workspace_xilinx/XCKU2/XCKU2.gen/sources_1/ip/ddr4_0/ddr4_0_sim_netlist.v
// Design      : ddr4_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xcku060-ffva1156-2-i
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* X_CORE_INFO = "ddr4_v2_2_17,Vivado 2022.2" *) (* dont_touch = "true" *) 
(* NotValidForBitStream *)
module ddr4_0
   (sys_rst,
    c0_sys_clk_p,
    c0_sys_clk_n,
    c0_ddr4_act_n,
    c0_ddr4_adr,
    c0_ddr4_ba,
    c0_ddr4_bg,
    c0_ddr4_cke,
    c0_ddr4_odt,
    c0_ddr4_cs_n,
    c0_ddr4_ck_t,
    c0_ddr4_ck_c,
    c0_ddr4_reset_n,
    c0_ddr4_dm_dbi_n,
    c0_ddr4_dq,
    c0_ddr4_dqs_c,
    c0_ddr4_dqs_t,
    c0_init_calib_complete,
    c0_ddr4_ui_clk,
    c0_ddr4_ui_clk_sync_rst,
    dbg_clk,
    c0_ddr4_app_addr,
    c0_ddr4_app_cmd,
    c0_ddr4_app_en,
    c0_ddr4_app_hi_pri,
    c0_ddr4_app_wdf_data,
    c0_ddr4_app_wdf_end,
    c0_ddr4_app_wdf_mask,
    c0_ddr4_app_wdf_wren,
    c0_ddr4_app_rd_data,
    c0_ddr4_app_rd_data_end,
    c0_ddr4_app_rd_data_valid,
    c0_ddr4_app_rdy,
    c0_ddr4_app_wdf_rdy,
    dbg_bus);
  input sys_rst;
  input c0_sys_clk_p;
  input c0_sys_clk_n;
  output c0_ddr4_act_n;
  output [16:0]c0_ddr4_adr;
  output [1:0]c0_ddr4_ba;
  output [0:0]c0_ddr4_bg;
  output [0:0]c0_ddr4_cke;
  output [0:0]c0_ddr4_odt;
  output [0:0]c0_ddr4_cs_n;
  output [0:0]c0_ddr4_ck_t;
  output [0:0]c0_ddr4_ck_c;
  output c0_ddr4_reset_n;
  inout [7:0]c0_ddr4_dm_dbi_n;
  inout [63:0]c0_ddr4_dq;
  inout [7:0]c0_ddr4_dqs_c;
  inout [7:0]c0_ddr4_dqs_t;
  output c0_init_calib_complete;
  output c0_ddr4_ui_clk;
  output c0_ddr4_ui_clk_sync_rst;
  output dbg_clk;
  input [29:0]c0_ddr4_app_addr;
  input [2:0]c0_ddr4_app_cmd;
  input c0_ddr4_app_en;
  input c0_ddr4_app_hi_pri;
  input [511:0]c0_ddr4_app_wdf_data;
  input c0_ddr4_app_wdf_end;
  input [63:0]c0_ddr4_app_wdf_mask;
  input c0_ddr4_app_wdf_wren;
  output [511:0]c0_ddr4_app_rd_data;
  output c0_ddr4_app_rd_data_end;
  output c0_ddr4_app_rd_data_valid;
  output c0_ddr4_app_rdy;
  output c0_ddr4_app_wdf_rdy;
  output [511:0]dbg_bus;

  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire c0_ddr4_act_n;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [16:0]c0_ddr4_adr;
  wire [29:0]c0_ddr4_app_addr;
  wire [2:0]c0_ddr4_app_cmd;
  wire c0_ddr4_app_en;
  wire c0_ddr4_app_hi_pri;
  wire [511:0]c0_ddr4_app_rd_data;
  wire c0_ddr4_app_rd_data_end;
  wire c0_ddr4_app_rd_data_valid;
  wire c0_ddr4_app_rdy;
  wire [511:0]c0_ddr4_app_wdf_data;
  wire c0_ddr4_app_wdf_end;
  wire [63:0]c0_ddr4_app_wdf_mask;
  wire c0_ddr4_app_wdf_rdy;
  wire c0_ddr4_app_wdf_wren;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [1:0]c0_ddr4_ba;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [0:0]c0_ddr4_bg;
  (* SLEW = "SLOW" *) wire [0:0]c0_ddr4_ck_c;
  (* SLEW = "SLOW" *) wire [0:0]c0_ddr4_ck_t;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [0:0]c0_ddr4_cke;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [0:0]c0_ddr4_cs_n;
  (* DRIVE = "12" *) (* IBUF_LOW_PWR *) wire [7:0]c0_ddr4_dm_dbi_n;
  (* DRIVE = "12" *) (* IBUF_LOW_PWR *) wire [63:0]c0_ddr4_dq;
  (* IBUF_LOW_PWR *) (* SLEW = "SLOW" *) wire [7:0]c0_ddr4_dqs_c;
  (* IBUF_LOW_PWR *) (* SLEW = "SLOW" *) wire [7:0]c0_ddr4_dqs_t;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [0:0]c0_ddr4_odt;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire c0_ddr4_reset_n;
  wire c0_ddr4_ui_clk;
  wire c0_ddr4_ui_clk_sync_rst;
  wire c0_init_calib_complete;
  (* IBUF_LOW_PWR = 0 *) wire c0_sys_clk_n;
  (* IBUF_LOW_PWR = 0 *) wire c0_sys_clk_p;
  wire [511:0]dbg_bus;
  wire dbg_clk;
  wire sys_rst;
  wire NLW_inst_addn_ui_clkout1_UNCONNECTED;
  wire NLW_inst_addn_ui_clkout2_UNCONNECTED;
  wire NLW_inst_addn_ui_clkout3_UNCONNECTED;
  wire NLW_inst_addn_ui_clkout4_UNCONNECTED;
  wire [16:0]NLW_inst_sl_oport0_UNCONNECTED;

  (* ACT_SKEW = "8'b00000000" *) 
  (* ADDR_SKEW = "136'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) 
  (* ADDR_WIDTH = "17" *) 
  (* ADV_USER_REQ = "NONE" *) 
  (* AL = "0" *) 
  (* ALIAS_PAGE = "OFF" *) 
  (* ALIAS_P_CNT = "OFF" *) 
  (* APP_ADDR_WIDTH = "30" *) 
  (* APP_DATA_WIDTH = "512" *) 
  (* APP_MASK_WIDTH = "64" *) 
  (* AUTO_AP_COL_A3 = "OFF" *) 
  (* BANK_GROUP_WIDTH = "1" *) 
  (* BANK_WIDTH = "2" *) 
  (* BA_SKEW = "16'b0000000000000000" *) 
  (* BG_SKEW = "8'b00000000" *) 
  (* BISC_EN = "1" *) 
  (* BURST_MODE = "8" *) 
  (* BYPASS_CAL = "FALSE" *) 
  (* CALIB_HIGH_SPEED = "FALSE" *) 
  (* CAL_DQS_GATE = "FULL" *) 
  (* CAL_DQS_TRACKING = "FULL" *) 
  (* CAL_JITTER = "FULL" *) 
  (* CAL_RDLVL = "FULL" *) 
  (* CAL_RDLVL_COMPLEX = "FULL" *) 
  (* CAL_RDLVL_DBI = "SKIP" *) 
  (* CAL_RD_VREF = "SKIP" *) 
  (* CAL_RD_VREF_PATTERN = "SIMPLE" *) 
  (* CAL_WRITE_LAT = "FULL" *) 
  (* CAL_WRLVL = "FULL" *) 
  (* CAL_WR_DQS_COMPLEX = "FULL" *) 
  (* CAL_WR_DQS_DM_DBI = "FULL" *) 
  (* CAL_WR_DQS_DQ = "FULL" *) 
  (* CAL_WR_VREF = "SKIP" *) 
  (* CAL_WR_VREF_PATTERN = "SIMPLE" *) 
  (* CAS_FIFO_BYPASS = "ON" *) 
  (* CA_MIRROR = "OFF" *) 
  (* CKE_SKEW = "8'b00000000" *) 
  (* CKE_WIDTH = "1" *) 
  (* CK_SKEW = "8'b00000000" *) 
  (* CK_WIDTH = "1" *) 
  (* CLKFBOUT_MULT_MMCM = "17" *) 
  (* CLKIN_PERIOD_MMCM = "14161" *) 
  (* CLKOUT0_DIVIDE_MMCM = "4" *) 
  (* CLKOUT1_DIVIDE_MMCM = "4" *) 
  (* CLKOUT2_DIVIDE_MMCM = "4" *) 
  (* CLKOUT3_DIVIDE_MMCM = "4" *) 
  (* CLKOUT4_DIVIDE_MMCM = "4" *) 
  (* CLKOUT6_DIVIDE_MMCM = "8" *) 
  (* CLKOUTPHY_MODE = "VCO_2X" *) 
  (* COL_WIDTH = "10" *) 
  (* COMPONENT_WIDTH = "16" *) 
  (* CPLX_PAT_LENGTH = "LONG" *) 
  (* CS_SKEW = "8'b00000000" *) 
  (* CS_WIDTH = "1" *) 
  (* C_DEBUG_ENABLED = "0" *) 
  (* C_FAMILY = "kintexu" *) 
  (* C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG" *) 
  (* C_SKEW = "8'b00000000" *) 
  (* C_S_AXI_ADDR_WIDTH = "0" *) 
  (* C_S_AXI_DATA_WIDTH = "0" *) 
  (* C_S_AXI_ID_WIDTH = "0" *) 
  (* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *) 
  (* ControllerType = "ddr4_sdram" *) 
  (* DATA_BUF_OFFSET_WIDTH = "1" *) 
  (* DBYTES = "8" *) 
  (* DDR4_CLAMSHELL = "OFF" *) 
  (* DDR4_DB_DIF_DI = "4'b0000" *) 
  (* DDR4_DB_DIF_ODT = "4'b0011" *) 
  (* DDR4_DB_DIF_VREF = "8'b00011011" *) 
  (* DDR4_DB_HIF_DI = "4'b0001" *) 
  (* DDR4_DB_HIF_RTT_NOM = "4'b0011" *) 
  (* DDR4_DB_HIF_RTT_PARK = "4'b0000" *) 
  (* DDR4_DB_HIF_RTT_WR = "4'b0000" *) 
  (* DDR4_DB_HIF_VREF = "8'b00011011" *) 
  (* DDR4_REG_PARITY_ENABLE = "OFF" *) 
  (* DDR4_REG_RC03 = "13'b0000000110000" *) 
  (* DDR4_REG_RC04 = "13'b0000001000000" *) 
  (* DDR4_REG_RC05 = "13'b0000001010000" *) 
  (* DEBUG_SIGNAL = "Disable" *) 
  (* DEVICE = "xcku060-" *) 
  (* DIVCLK_DIVIDE_MMCM = "1" *) 
  (* DM_DBI = "DM_NODBI" *) 
  (* DM_WIDTH = "8" *) 
  (* DQS_WIDTH = "8" *) 
  (* DQ_WIDTH = "64" *) 
  (* DRAM_TYPE = "DDR4" *) 
  (* DRAM_WIDTH = "16" *) 
  (* EARLY_WR_DATA = "OFF" *) 
  (* ECC = "OFF" *) 
  (* ECC_TEST = "OFF" *) 
  (* ECC_WIDTH = "8" *) 
  (* EXTRA_CMD_DELAY = "0" *) 
  (* FAMILY = "ULTRASCALE" *) 
  (* FPGA = "xcku060-ffva1156-2-i-" *) 
  (* INTERFACE = "NATIVE" *) 
  (* IS_CKE_SHARED = "false" *) 
  (* LIVE_DESIGN = "0" *) 
  (* LRDIMM_MODE = "OFF" *) 
  (* LR_WIDTH = "1" *) 
  (* MCS_ECC_ENABLE = "FALSE" *) 
  (* MC_ERR_ADDR_WIDTH = "52" *) 
  (* MEMORY_CONFIGURATION = "COMPONENT" *) 
  (* MEMORY_DENSITY = "16Gb" *) 
  (* MEMORY_PART = "MT40A1G16RC-062E" *) 
  (* MEMORY_SPEED_GRADE = "062E" *) 
  (* MEMORY_WIDTH = "16" *) 
  (* MEM_ADDR_ORDER = "ROW_COLUMN_BANK" *) 
  (* MEM_CODE = "0" *) 
  (* MEM_CORE_VER = "xilinx.com:ip:mem:1.4" *) 
  (* MIGRATION = "OFF" *) 
  (* MIG_PARAM_CHECKS = "FALSE" *) 
  (* MR0 = "13'b0101101100100" *) 
  (* MR1 = "13'b0001100000001" *) 
  (* MR2 = "13'b0000000011000" *) 
  (* MR3 = "13'b0001000000000" *) 
  (* MR4 = "13'b0000000000000" *) 
  (* MR5 = "13'b0010000000000" *) 
  (* MR6 = "13'b0100000010100" *) 
  (* NOP_ADD_LOW = "1'b0" *) 
  (* NUMREF = "1" *) 
  (* NUM_SLOT = "1" *) 
  (* ODTNOP = "16'b0000000000000000" *) 
  (* ODTRD = "16'b0000000000000000" *) 
  (* ODTRDDEL = "5'b10001" *) 
  (* ODTRDDUR = "4'b0110" *) 
  (* ODTRDODEL = "5'b01001" *) 
  (* ODTRDODUR = "4'b0110" *) 
  (* ODTWR = "16'b0000000000100001" *) 
  (* ODTWRDEL = "5'b01100" *) 
  (* ODTWRDUR = "4'b0110" *) 
  (* ODTWRODEL = "5'b01001" *) 
  (* ODTWRODUR = "4'b0110" *) 
  (* ODT_SKEW = "8'b00000000" *) 
  (* ODT_WIDTH = "1" *) 
  (* ORDERING = "NORM" *) 
  (* PARTIAL_RECONFIG = "Disable" *) 
  (* PAR_SKEW = "8'b00000000" *) 
  (* PAYLOAD_WIDTH = "64" *) 
  (* PER_RD_INTVL = "301" *) 
  (* PER_RD_PERF = "1'b1" *) 
  (* PING_PONG_PHY = "1" *) 
  (* PhyIP_ADDR_WIDTH = "17" *) 
  (* PhyIP_BANK_GROUP_WIDTH = "1" *) 
  (* PhyIP_BANK_WIDTH = "2" *) 
  (* PhyIP_CA_MIRROR = "0" *) 
  (* PhyIP_CKE_WIDTH = "1" *) 
  (* PhyIP_CK_WIDTH = "1" *) 
  (* PhyIP_CLAMSHELL = "false" *) 
  (* PhyIP_CLKFBOUT_MULT = "17" *) 
  (* PhyIP_CLKOUT0_DIVIDE = "4" *) 
  (* PhyIP_CLKOUT1_DIVIDE = "0" *) 
  (* PhyIP_CLKOUT2_DIVIDE = "0" *) 
  (* PhyIP_CLKOUT3_DIVIDE = "0" *) 
  (* PhyIP_CLKOUT4_DIVIDE = "0" *) 
  (* PhyIP_CLKOUTPHY_MODE = "VCO_2X" *) 
  (* PhyIP_CS_WIDTH = "1" *) 
  (* PhyIP_CUSTOM_PART_ATTRIBUTES = "NONE" *) 
  (* PhyIP_CasLatency = "17" *) 
  (* PhyIP_CasWriteLatency = "12" *) 
  (* PhyIP_ChipSelect = "true" *) 
  (* PhyIP_DATABITS_PER_STROBE = "8" *) 
  (* PhyIP_DCI_CASCADE_CUTOFF = "938" *) 
  (* PhyIP_DEBUG_SIGNAL = "Disable" *) 
  (* PhyIP_DIVCLK_DIVIDE = "1" *) 
  (* PhyIP_DM_WIDTH = "8" *) 
  (* PhyIP_DQS_WIDTH = "8" *) 
  (* PhyIP_DQ_WIDTH = "64" *) 
  (* PhyIP_DataMask = "DM_NO_DBI" *) 
  (* PhyIP_DataWidth = "64" *) 
  (* PhyIP_ECC = "false" *) 
  (* PhyIP_EN_PARITY = "false" *) 
  (* PhyIP_Enable_LVAUX = "false" *) 
  (* PhyIP_HR_MIN_FREQ = "0" *) 
  (* PhyIP_IS_FASTER_SPEED_RAM = "No" *) 
  (* PhyIP_IS_FROM_PHY = "1" *) 
  (* PhyIP_InputClockPeriod = "14161" *) 
  (* PhyIP_MEM_DEVICE_WIDTH = "16" *) 
  (* PhyIP_MIN_PERIOD = "750" *) 
  (* PhyIP_MemoryPart = "MT40A1G16RC-062E" *) 
  (* PhyIP_MemoryType = "Components" *) 
  (* PhyIP_MemoryVoltage = "1.2V" *) 
  (* PhyIP_ODT_WIDTH = "1" *) 
  (* PhyIP_PARTIAL_RECONFIG_FLOW_MIG = "false" *) 
  (* PhyIP_PhyClockRatio = "4:1" *) 
  (* PhyIP_Phy_Only = "Complete_Memory_Controller" *) 
  (* PhyIP_RANK_WIDTH = "1" *) 
  (* PhyIP_SAVE_RESTORE = "false" *) 
  (* PhyIP_SELF_REFRESH = "false" *) 
  (* PhyIP_Simulation_Mode = "BFM" *) 
  (* PhyIP_Slot = "Single" *) 
  (* PhyIP_StackHeight = "1" *) 
  (* PhyIP_System_Clock = "Differential" *) 
  (* PhyIP_TimePeriod = "833" *) 
  (* PhyIP_USE_CS_PORT = "true" *) 
  (* PhyIP_USE_DM_PORT = "DM_NO_DBI" *) 
  (* PhyIP_VrefVoltage = "0.84" *) 
  (* PhyIP_isCKEShared = "false" *) 
  (* PhyIP_nCS_PER_RANK = "1" *) 
  (* PhyIP_tCK = "833" *) 
  (* RANKS = "1" *) 
  (* RANK_SLOT = "1" *) 
  (* RANK_WIDTH = "1" *) 
  (* RD_VREF_VAL = "7'b0011111" *) 
  (* REG_CTRL = "OFF" *) 
  (* RESTORE_CRC = "false" *) 
  (* ROW_WIDTH = "17" *) 
  (* RTL_VERSION = "0" *) 
  (* SAVE_RESTORE = "false" *) 
  (* SELF_REFRESH = "false" *) 
  (* SIM_MODE = "FULL" *) 
  (* SLOT0_CONFIG = "8'b00000001" *) 
  (* SLOT0_FUNC_CS = "8'b00000001" *) 
  (* SLOT0_ODD_CS = "8'b00000000" *) 
  (* SLOT1_CONFIG = "8'b00000000" *) 
  (* SLOT1_FUNC_CS = "8'b00000000" *) 
  (* SLOT1_ODD_CS = "8'b00000000" *) 
  (* STARVATION_EN = "1'b1" *) 
  (* STARVE_COUNT_WIDTH = "9" *) 
  (* SYSCLK_TYPE = "DIFFERENTIAL" *) 
  (* S_HEIGHT = "1" *) 
  (* TCQ = "100.000000" *) 
  (* TXN_FIFO_BYPASS = "ON" *) 
  (* TXN_FIFO_PIPE = "OFF" *) 
  (* USE_CS_PORT = "1" *) 
  (* X_MIG_OLYMPUS = "1" *) 
  (* X_ULTRASCALE_IO_FLOW = "xilinx.com:ip:ddr4_phy:2.2" *) 
  (* ZQINTVL = "1200480193" *) 
  (* nCK_PER_CLK = "4" *) 
  (* t200us = "60025" *) 
  (* t500us = "150061" *) 
  (* tCK = "833" *) 
  (* tFAW = "37" *) 
  (* tMOD = "6" *) 
  (* tMRD = "2" *) 
  (* tRAS = "39" *) 
  (* tRCD = "17" *) 
  (* tREFI = "9363" *) 
  (* tRFC = "421" *) 
  (* tRP = "17" *) 
  (* tRRD_L = "8" *) 
  (* tRRD_S = "7" *) 
  (* tRTP = "10" *) 
  (* tRTW = "13" *) 
  (* tWR = "20" *) 
  (* tWTR_L = "10" *) 
  (* tWTR_S = "4" *) 
  (* tXPR = "109" *) 
  (* tZQCS = "128" *) 
  (* tZQINIT = "256" *) 
  ddr4_0_ddr4 inst
       (.addn_ui_clkout1(NLW_inst_addn_ui_clkout1_UNCONNECTED),
        .addn_ui_clkout2(NLW_inst_addn_ui_clkout2_UNCONNECTED),
        .addn_ui_clkout3(NLW_inst_addn_ui_clkout3_UNCONNECTED),
        .addn_ui_clkout4(NLW_inst_addn_ui_clkout4_UNCONNECTED),
        .c0_ddr4_act_n(c0_ddr4_act_n),
        .c0_ddr4_adr(c0_ddr4_adr),
        .c0_ddr4_app_addr(c0_ddr4_app_addr),
        .c0_ddr4_app_cmd(c0_ddr4_app_cmd),
        .c0_ddr4_app_correct_en_i(1'b1),
        .c0_ddr4_app_en(c0_ddr4_app_en),
        .c0_ddr4_app_hi_pri(c0_ddr4_app_hi_pri),
        .c0_ddr4_app_rd_data(c0_ddr4_app_rd_data),
        .c0_ddr4_app_rd_data_end(c0_ddr4_app_rd_data_end),
        .c0_ddr4_app_rd_data_valid(c0_ddr4_app_rd_data_valid),
        .c0_ddr4_app_rdy(c0_ddr4_app_rdy),
        .c0_ddr4_app_wdf_data(c0_ddr4_app_wdf_data),
        .c0_ddr4_app_wdf_end(c0_ddr4_app_wdf_end),
        .c0_ddr4_app_wdf_mask(c0_ddr4_app_wdf_mask),
        .c0_ddr4_app_wdf_rdy(c0_ddr4_app_wdf_rdy),
        .c0_ddr4_app_wdf_wren(c0_ddr4_app_wdf_wren),
        .c0_ddr4_ba(c0_ddr4_ba),
        .c0_ddr4_bg(c0_ddr4_bg),
        .c0_ddr4_ck_c(c0_ddr4_ck_c),
        .c0_ddr4_ck_t(c0_ddr4_ck_t),
        .c0_ddr4_cke(c0_ddr4_cke),
        .c0_ddr4_cs_n(c0_ddr4_cs_n),
        .c0_ddr4_dm_dbi_n(c0_ddr4_dm_dbi_n),
        .c0_ddr4_dq(c0_ddr4_dq),
        .c0_ddr4_dqs_c(c0_ddr4_dqs_c),
        .c0_ddr4_dqs_t(c0_ddr4_dqs_t),
        .c0_ddr4_odt(c0_ddr4_odt),
        .c0_ddr4_reset_n(c0_ddr4_reset_n),
        .c0_ddr4_ui_clk(c0_ddr4_ui_clk),
        .c0_ddr4_ui_clk_sync_rst(c0_ddr4_ui_clk_sync_rst),
        .c0_init_calib_complete(c0_init_calib_complete),
        .c0_sys_clk_n(c0_sys_clk_n),
        .c0_sys_clk_p(c0_sys_clk_p),
        .dbg_bus(dbg_bus),
        .dbg_clk(dbg_clk),
        .sl_iport0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sl_oport0(NLW_inst_sl_oport0_UNCONNECTED[16:0]),
        .sys_rst(sys_rst));
endmodule

(* HW_HANDOFF = "ddr4_0_microblaze_mcs.hwdef" *) (* ORIG_REF_NAME = "bd_9054" *) 
module ddr4_0_bd_9054
   (Clk,
    IO_addr_strobe,
    IO_address,
    IO_byte_enable,
    IO_read_data,
    IO_read_strobe,
    IO_ready,
    IO_write_data,
    IO_write_strobe,
    Reset,
    TRACE_data_access,
    TRACE_data_address,
    TRACE_data_byte_enable,
    TRACE_data_read,
    TRACE_data_write,
    TRACE_data_write_value,
    TRACE_dcache_hit,
    TRACE_dcache_rdy,
    TRACE_dcache_read,
    TRACE_dcache_req,
    TRACE_delay_slot,
    TRACE_ex_piperun,
    TRACE_exception_kind,
    TRACE_exception_taken,
    TRACE_icache_hit,
    TRACE_icache_rdy,
    TRACE_icache_req,
    TRACE_instruction,
    TRACE_jump_hit,
    TRACE_jump_taken,
    TRACE_mb_halted,
    TRACE_mem_piperun,
    TRACE_msr_reg,
    TRACE_new_reg_value,
    TRACE_of_piperun,
    TRACE_pc,
    TRACE_pid_reg,
    TRACE_reg_addr,
    TRACE_reg_write,
    TRACE_valid_instr);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_ASYNC_RESET Reset, CLK_DOMAIN bd_9054_Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input Clk;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE" *) output IO_addr_strobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS" *) output [31:0]IO_address;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE" *) output [3:0]IO_byte_enable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA" *) input [31:0]IO_read_data;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE" *) output IO_read_strobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READY" *) input IO_ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA" *) output [31:0]IO_write_data;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE" *) output IO_write_strobe;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESET, INSERT_VIP 0, POLARITY ACTIVE_HIGH" *) input Reset;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS" *) output TRACE_data_access;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS" *) output [0:31]TRACE_data_address;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE" *) output [0:3]TRACE_data_byte_enable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ" *) output TRACE_data_read;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE" *) output TRACE_data_write;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE" *) output [0:31]TRACE_data_write_value;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT" *) output TRACE_dcache_hit;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY" *) output TRACE_dcache_rdy;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ" *) output TRACE_dcache_read;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ" *) output TRACE_dcache_req;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT" *) output TRACE_delay_slot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN" *) output TRACE_ex_piperun;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND" *) output [0:4]TRACE_exception_kind;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN" *) output TRACE_exception_taken;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT" *) output TRACE_icache_hit;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY" *) output TRACE_icache_rdy;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ" *) output TRACE_icache_req;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION" *) output [0:31]TRACE_instruction;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT" *) output TRACE_jump_hit;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN" *) output TRACE_jump_taken;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED" *) output TRACE_mb_halted;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN" *) output TRACE_mem_piperun;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG" *) output [0:14]TRACE_msr_reg;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE" *) output [0:31]TRACE_new_reg_value;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN" *) output TRACE_of_piperun;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE PC" *) output [0:31]TRACE_pc;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE PID_REG" *) output [0:7]TRACE_pid_reg;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR" *) output [0:4]TRACE_reg_addr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE" *) output TRACE_reg_write;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR" *) output TRACE_valid_instr;

  wire \<const0> ;
  wire Clk;
  wire IO_Rst;
  wire IO_addr_strobe;
  wire [29:2]\^IO_address ;
  wire [31:0]IO_read_data;
  wire IO_ready;
  wire [31:0]IO_write_data;
  wire IO_write_strobe;
  wire LMB_Rst2;
  wire MB_Reset;
  wire Reset;
  wire [0:29]dlmb_ABUS;
  wire dlmb_ADDRSTROBE;
  wire [0:3]dlmb_BE;
  wire [0:31]dlmb_READDBUS;
  wire dlmb_READSTROBE;
  wire dlmb_READY;
  wire [0:31]dlmb_WRITEDBUS;
  wire dlmb_WRITESTROBE;
  wire [17:29]dlmb_port_2_ADDR;
  wire dlmb_port_2_CLK;
  wire [0:31]dlmb_port_2_DIN;
  wire [31:0]dlmb_port_2_DOUT;
  wire dlmb_port_2_EN;
  wire [0:3]dlmb_port_2_WE;
  wire [16:29]dlmb_port_ADDR;
  wire dlmb_port_CLK;
  wire [0:31]dlmb_port_DIN;
  wire [31:0]dlmb_port_DOUT;
  wire dlmb_port_EN;
  wire [0:3]dlmb_port_WE;
  wire [0:29]dlmb_sl_0_ABUS;
  wire dlmb_sl_0_ADDRSTROBE;
  wire [0:3]dlmb_sl_0_BE;
  wire [0:31]dlmb_sl_0_READDBUS;
  wire dlmb_sl_0_READSTROBE;
  wire dlmb_sl_0_READY;
  wire [0:31]dlmb_sl_0_WRITEDBUS;
  wire dlmb_sl_0_WRITESTROBE;
  wire [0:31]dlmb_sl_1_READDBUS;
  wire dlmb_sl_1_READY;
  wire [0:31]dlmb_sl_2_READDBUS;
  wire dlmb_sl_2_READY;
  wire [0:29]ilmb_ABUS;
  wire ilmb_ADDRSTROBE;
  wire [0:31]ilmb_READDBUS;
  wire ilmb_READY;
  wire [17:29]ilmb_port_2_ADDR;
  wire ilmb_port_2_CLK;
  wire [31:0]ilmb_port_2_DOUT;
  wire ilmb_port_2_EN;
  wire [16:29]ilmb_port_ADDR;
  wire ilmb_port_CLK;
  wire [31:0]ilmb_port_DOUT;
  wire ilmb_port_EN;
  wire [0:29]ilmb_sl_0_ABUS;
  wire ilmb_sl_0_ADDRSTROBE;
  wire [0:31]ilmb_sl_0_READDBUS;
  wire ilmb_sl_0_READY;
  wire [0:31]ilmb_sl_1_READDBUS;
  wire ilmb_sl_1_READY;
  wire NLW_dlmb_LMB_CE_UNCONNECTED;
  wire NLW_dlmb_LMB_Rst_UNCONNECTED;
  wire NLW_dlmb_LMB_UE_UNCONNECTED;
  wire NLW_dlmb_LMB_Wait_UNCONNECTED;
  wire [30:31]NLW_dlmb_LMB_ABus_UNCONNECTED;
  wire NLW_dlmb_cntlr_BRAM_Rst_A_UNCONNECTED;
  wire NLW_dlmb_cntlr_Sl_CE_UNCONNECTED;
  wire NLW_dlmb_cntlr_Sl_UE_UNCONNECTED;
  wire NLW_dlmb_cntlr_Sl_Wait_UNCONNECTED;
  wire [0:31]NLW_dlmb_cntlr_BRAM_Addr_A_UNCONNECTED;
  wire NLW_ilmb_LMB_CE_UNCONNECTED;
  wire NLW_ilmb_LMB_ReadStrobe_UNCONNECTED;
  wire NLW_ilmb_LMB_Rst_UNCONNECTED;
  wire NLW_ilmb_LMB_UE_UNCONNECTED;
  wire NLW_ilmb_LMB_Wait_UNCONNECTED;
  wire NLW_ilmb_LMB_WriteStrobe_UNCONNECTED;
  wire [1:31]NLW_ilmb_LMB_ABus_UNCONNECTED;
  wire [0:3]NLW_ilmb_LMB_BE_UNCONNECTED;
  wire [0:31]NLW_ilmb_LMB_WriteDBus_UNCONNECTED;
  wire NLW_ilmb_cntlr_BRAM_Rst_A_UNCONNECTED;
  wire NLW_ilmb_cntlr_Sl_CE_UNCONNECTED;
  wire NLW_ilmb_cntlr_Sl_UE_UNCONNECTED;
  wire NLW_ilmb_cntlr_Sl_Wait_UNCONNECTED;
  wire [0:31]NLW_ilmb_cntlr_BRAM_Addr_A_UNCONNECTED;
  wire [0:31]NLW_ilmb_cntlr_BRAM_Dout_A_UNCONNECTED;
  wire [0:3]NLW_ilmb_cntlr_BRAM_WEN_A_UNCONNECTED;
  wire NLW_iomodule_0_IO_Read_Strobe_UNCONNECTED;
  wire NLW_iomodule_0_Sl_CE_UNCONNECTED;
  wire NLW_iomodule_0_Sl_UE_UNCONNECTED;
  wire NLW_iomodule_0_Sl_Wait_UNCONNECTED;
  wire [31:0]NLW_iomodule_0_IO_Address_UNCONNECTED;
  wire [3:0]NLW_iomodule_0_IO_Byte_Enable_UNCONNECTED;
  wire NLW_lmb_bram_I_rsta_busy_UNCONNECTED;
  wire NLW_lmb_bram_I_rstb_busy_UNCONNECTED;
  wire NLW_microblaze_I_IFetch_UNCONNECTED;
  wire NLW_microblaze_I_Trace_DCache_Hit_UNCONNECTED;
  wire NLW_microblaze_I_Trace_DCache_Rdy_UNCONNECTED;
  wire NLW_microblaze_I_Trace_DCache_Read_UNCONNECTED;
  wire NLW_microblaze_I_Trace_DCache_Req_UNCONNECTED;
  wire NLW_microblaze_I_Trace_Data_Access_UNCONNECTED;
  wire NLW_microblaze_I_Trace_Data_Read_UNCONNECTED;
  wire NLW_microblaze_I_Trace_Data_Write_UNCONNECTED;
  wire NLW_microblaze_I_Trace_Delay_Slot_UNCONNECTED;
  wire NLW_microblaze_I_Trace_EX_PipeRun_UNCONNECTED;
  wire NLW_microblaze_I_Trace_Exception_Taken_UNCONNECTED;
  wire NLW_microblaze_I_Trace_ICache_Hit_UNCONNECTED;
  wire NLW_microblaze_I_Trace_ICache_Rdy_UNCONNECTED;
  wire NLW_microblaze_I_Trace_ICache_Req_UNCONNECTED;
  wire NLW_microblaze_I_Trace_Jump_Hit_UNCONNECTED;
  wire NLW_microblaze_I_Trace_Jump_Taken_UNCONNECTED;
  wire NLW_microblaze_I_Trace_MB_Halted_UNCONNECTED;
  wire NLW_microblaze_I_Trace_MEM_PipeRun_UNCONNECTED;
  wire NLW_microblaze_I_Trace_OF_PipeRun_UNCONNECTED;
  wire NLW_microblaze_I_Trace_Reg_Write_UNCONNECTED;
  wire NLW_microblaze_I_Trace_Valid_Instr_UNCONNECTED;
  wire [30:31]NLW_microblaze_I_Data_Addr_UNCONNECTED;
  wire [1:31]NLW_microblaze_I_Instr_Addr_UNCONNECTED;
  wire [0:1]NLW_microblaze_I_Interrupt_Ack_UNCONNECTED;
  wire [0:31]NLW_microblaze_I_Trace_Data_Address_UNCONNECTED;
  wire [0:3]NLW_microblaze_I_Trace_Data_Byte_Enable_UNCONNECTED;
  wire [0:31]NLW_microblaze_I_Trace_Data_Write_Value_UNCONNECTED;
  wire [0:4]NLW_microblaze_I_Trace_Exception_Kind_UNCONNECTED;
  wire [0:31]NLW_microblaze_I_Trace_Instruction_UNCONNECTED;
  wire [0:14]NLW_microblaze_I_Trace_MSR_Reg_UNCONNECTED;
  wire [0:31]NLW_microblaze_I_Trace_New_Reg_Value_UNCONNECTED;
  wire [0:31]NLW_microblaze_I_Trace_PC_UNCONNECTED;
  wire [0:7]NLW_microblaze_I_Trace_PID_Reg_UNCONNECTED;
  wire [0:4]NLW_microblaze_I_Trace_Reg_Addr_UNCONNECTED;
  wire [0:0]NLW_rst_0_interconnect_aresetn_UNCONNECTED;
  wire [0:0]NLW_rst_0_peripheral_aresetn_UNCONNECTED;
  wire NLW_second_dlmb_cntlr_BRAM_Rst_A_UNCONNECTED;
  wire NLW_second_dlmb_cntlr_Sl_CE_UNCONNECTED;
  wire NLW_second_dlmb_cntlr_Sl_UE_UNCONNECTED;
  wire NLW_second_dlmb_cntlr_Sl_Wait_UNCONNECTED;
  wire [0:31]NLW_second_dlmb_cntlr_BRAM_Addr_A_UNCONNECTED;
  wire NLW_second_ilmb_cntlr_BRAM_Rst_A_UNCONNECTED;
  wire NLW_second_ilmb_cntlr_Sl_CE_UNCONNECTED;
  wire NLW_second_ilmb_cntlr_Sl_UE_UNCONNECTED;
  wire NLW_second_ilmb_cntlr_Sl_Wait_UNCONNECTED;
  wire [0:31]NLW_second_ilmb_cntlr_BRAM_Addr_A_UNCONNECTED;
  wire [0:31]NLW_second_ilmb_cntlr_BRAM_Dout_A_UNCONNECTED;
  wire [0:3]NLW_second_ilmb_cntlr_BRAM_WEN_A_UNCONNECTED;
  wire NLW_second_lmb_bram_I_rsta_busy_UNCONNECTED;
  wire NLW_second_lmb_bram_I_rstb_busy_UNCONNECTED;

  assign IO_address[31] = \<const0> ;
  assign IO_address[30] = \<const0> ;
  assign IO_address[29:2] = \^IO_address [29:2];
  assign IO_address[1] = \<const0> ;
  assign IO_address[0] = \<const0> ;
  assign IO_byte_enable[3] = \<const0> ;
  assign IO_byte_enable[2] = \<const0> ;
  assign IO_byte_enable[1] = \<const0> ;
  assign IO_byte_enable[0] = \<const0> ;
  assign IO_read_strobe = \<const0> ;
  assign TRACE_data_access = \<const0> ;
  assign TRACE_data_address[0] = \<const0> ;
  assign TRACE_data_address[1] = \<const0> ;
  assign TRACE_data_address[2] = \<const0> ;
  assign TRACE_data_address[3] = \<const0> ;
  assign TRACE_data_address[4] = \<const0> ;
  assign TRACE_data_address[5] = \<const0> ;
  assign TRACE_data_address[6] = \<const0> ;
  assign TRACE_data_address[7] = \<const0> ;
  assign TRACE_data_address[8] = \<const0> ;
  assign TRACE_data_address[9] = \<const0> ;
  assign TRACE_data_address[10] = \<const0> ;
  assign TRACE_data_address[11] = \<const0> ;
  assign TRACE_data_address[12] = \<const0> ;
  assign TRACE_data_address[13] = \<const0> ;
  assign TRACE_data_address[14] = \<const0> ;
  assign TRACE_data_address[15] = \<const0> ;
  assign TRACE_data_address[16] = \<const0> ;
  assign TRACE_data_address[17] = \<const0> ;
  assign TRACE_data_address[18] = \<const0> ;
  assign TRACE_data_address[19] = \<const0> ;
  assign TRACE_data_address[20] = \<const0> ;
  assign TRACE_data_address[21] = \<const0> ;
  assign TRACE_data_address[22] = \<const0> ;
  assign TRACE_data_address[23] = \<const0> ;
  assign TRACE_data_address[24] = \<const0> ;
  assign TRACE_data_address[25] = \<const0> ;
  assign TRACE_data_address[26] = \<const0> ;
  assign TRACE_data_address[27] = \<const0> ;
  assign TRACE_data_address[28] = \<const0> ;
  assign TRACE_data_address[29] = \<const0> ;
  assign TRACE_data_address[30] = \<const0> ;
  assign TRACE_data_address[31] = \<const0> ;
  assign TRACE_data_byte_enable[0] = \<const0> ;
  assign TRACE_data_byte_enable[1] = \<const0> ;
  assign TRACE_data_byte_enable[2] = \<const0> ;
  assign TRACE_data_byte_enable[3] = \<const0> ;
  assign TRACE_data_read = \<const0> ;
  assign TRACE_data_write = \<const0> ;
  assign TRACE_data_write_value[0] = \<const0> ;
  assign TRACE_data_write_value[1] = \<const0> ;
  assign TRACE_data_write_value[2] = \<const0> ;
  assign TRACE_data_write_value[3] = \<const0> ;
  assign TRACE_data_write_value[4] = \<const0> ;
  assign TRACE_data_write_value[5] = \<const0> ;
  assign TRACE_data_write_value[6] = \<const0> ;
  assign TRACE_data_write_value[7] = \<const0> ;
  assign TRACE_data_write_value[8] = \<const0> ;
  assign TRACE_data_write_value[9] = \<const0> ;
  assign TRACE_data_write_value[10] = \<const0> ;
  assign TRACE_data_write_value[11] = \<const0> ;
  assign TRACE_data_write_value[12] = \<const0> ;
  assign TRACE_data_write_value[13] = \<const0> ;
  assign TRACE_data_write_value[14] = \<const0> ;
  assign TRACE_data_write_value[15] = \<const0> ;
  assign TRACE_data_write_value[16] = \<const0> ;
  assign TRACE_data_write_value[17] = \<const0> ;
  assign TRACE_data_write_value[18] = \<const0> ;
  assign TRACE_data_write_value[19] = \<const0> ;
  assign TRACE_data_write_value[20] = \<const0> ;
  assign TRACE_data_write_value[21] = \<const0> ;
  assign TRACE_data_write_value[22] = \<const0> ;
  assign TRACE_data_write_value[23] = \<const0> ;
  assign TRACE_data_write_value[24] = \<const0> ;
  assign TRACE_data_write_value[25] = \<const0> ;
  assign TRACE_data_write_value[26] = \<const0> ;
  assign TRACE_data_write_value[27] = \<const0> ;
  assign TRACE_data_write_value[28] = \<const0> ;
  assign TRACE_data_write_value[29] = \<const0> ;
  assign TRACE_data_write_value[30] = \<const0> ;
  assign TRACE_data_write_value[31] = \<const0> ;
  assign TRACE_dcache_hit = \<const0> ;
  assign TRACE_dcache_rdy = \<const0> ;
  assign TRACE_dcache_read = \<const0> ;
  assign TRACE_dcache_req = \<const0> ;
  assign TRACE_delay_slot = \<const0> ;
  assign TRACE_ex_piperun = \<const0> ;
  assign TRACE_exception_kind[0] = \<const0> ;
  assign TRACE_exception_kind[1] = \<const0> ;
  assign TRACE_exception_kind[2] = \<const0> ;
  assign TRACE_exception_kind[3] = \<const0> ;
  assign TRACE_exception_kind[4] = \<const0> ;
  assign TRACE_exception_taken = \<const0> ;
  assign TRACE_icache_hit = \<const0> ;
  assign TRACE_icache_rdy = \<const0> ;
  assign TRACE_icache_req = \<const0> ;
  assign TRACE_instruction[0] = \<const0> ;
  assign TRACE_instruction[1] = \<const0> ;
  assign TRACE_instruction[2] = \<const0> ;
  assign TRACE_instruction[3] = \<const0> ;
  assign TRACE_instruction[4] = \<const0> ;
  assign TRACE_instruction[5] = \<const0> ;
  assign TRACE_instruction[6] = \<const0> ;
  assign TRACE_instruction[7] = \<const0> ;
  assign TRACE_instruction[8] = \<const0> ;
  assign TRACE_instruction[9] = \<const0> ;
  assign TRACE_instruction[10] = \<const0> ;
  assign TRACE_instruction[11] = \<const0> ;
  assign TRACE_instruction[12] = \<const0> ;
  assign TRACE_instruction[13] = \<const0> ;
  assign TRACE_instruction[14] = \<const0> ;
  assign TRACE_instruction[15] = \<const0> ;
  assign TRACE_instruction[16] = \<const0> ;
  assign TRACE_instruction[17] = \<const0> ;
  assign TRACE_instruction[18] = \<const0> ;
  assign TRACE_instruction[19] = \<const0> ;
  assign TRACE_instruction[20] = \<const0> ;
  assign TRACE_instruction[21] = \<const0> ;
  assign TRACE_instruction[22] = \<const0> ;
  assign TRACE_instruction[23] = \<const0> ;
  assign TRACE_instruction[24] = \<const0> ;
  assign TRACE_instruction[25] = \<const0> ;
  assign TRACE_instruction[26] = \<const0> ;
  assign TRACE_instruction[27] = \<const0> ;
  assign TRACE_instruction[28] = \<const0> ;
  assign TRACE_instruction[29] = \<const0> ;
  assign TRACE_instruction[30] = \<const0> ;
  assign TRACE_instruction[31] = \<const0> ;
  assign TRACE_jump_hit = \<const0> ;
  assign TRACE_jump_taken = \<const0> ;
  assign TRACE_mb_halted = \<const0> ;
  assign TRACE_mem_piperun = \<const0> ;
  assign TRACE_msr_reg[0] = \<const0> ;
  assign TRACE_msr_reg[1] = \<const0> ;
  assign TRACE_msr_reg[2] = \<const0> ;
  assign TRACE_msr_reg[3] = \<const0> ;
  assign TRACE_msr_reg[4] = \<const0> ;
  assign TRACE_msr_reg[5] = \<const0> ;
  assign TRACE_msr_reg[6] = \<const0> ;
  assign TRACE_msr_reg[7] = \<const0> ;
  assign TRACE_msr_reg[8] = \<const0> ;
  assign TRACE_msr_reg[9] = \<const0> ;
  assign TRACE_msr_reg[10] = \<const0> ;
  assign TRACE_msr_reg[11] = \<const0> ;
  assign TRACE_msr_reg[12] = \<const0> ;
  assign TRACE_msr_reg[13] = \<const0> ;
  assign TRACE_msr_reg[14] = \<const0> ;
  assign TRACE_new_reg_value[0] = \<const0> ;
  assign TRACE_new_reg_value[1] = \<const0> ;
  assign TRACE_new_reg_value[2] = \<const0> ;
  assign TRACE_new_reg_value[3] = \<const0> ;
  assign TRACE_new_reg_value[4] = \<const0> ;
  assign TRACE_new_reg_value[5] = \<const0> ;
  assign TRACE_new_reg_value[6] = \<const0> ;
  assign TRACE_new_reg_value[7] = \<const0> ;
  assign TRACE_new_reg_value[8] = \<const0> ;
  assign TRACE_new_reg_value[9] = \<const0> ;
  assign TRACE_new_reg_value[10] = \<const0> ;
  assign TRACE_new_reg_value[11] = \<const0> ;
  assign TRACE_new_reg_value[12] = \<const0> ;
  assign TRACE_new_reg_value[13] = \<const0> ;
  assign TRACE_new_reg_value[14] = \<const0> ;
  assign TRACE_new_reg_value[15] = \<const0> ;
  assign TRACE_new_reg_value[16] = \<const0> ;
  assign TRACE_new_reg_value[17] = \<const0> ;
  assign TRACE_new_reg_value[18] = \<const0> ;
  assign TRACE_new_reg_value[19] = \<const0> ;
  assign TRACE_new_reg_value[20] = \<const0> ;
  assign TRACE_new_reg_value[21] = \<const0> ;
  assign TRACE_new_reg_value[22] = \<const0> ;
  assign TRACE_new_reg_value[23] = \<const0> ;
  assign TRACE_new_reg_value[24] = \<const0> ;
  assign TRACE_new_reg_value[25] = \<const0> ;
  assign TRACE_new_reg_value[26] = \<const0> ;
  assign TRACE_new_reg_value[27] = \<const0> ;
  assign TRACE_new_reg_value[28] = \<const0> ;
  assign TRACE_new_reg_value[29] = \<const0> ;
  assign TRACE_new_reg_value[30] = \<const0> ;
  assign TRACE_new_reg_value[31] = \<const0> ;
  assign TRACE_of_piperun = \<const0> ;
  assign TRACE_pc[0] = \<const0> ;
  assign TRACE_pc[1] = \<const0> ;
  assign TRACE_pc[2] = \<const0> ;
  assign TRACE_pc[3] = \<const0> ;
  assign TRACE_pc[4] = \<const0> ;
  assign TRACE_pc[5] = \<const0> ;
  assign TRACE_pc[6] = \<const0> ;
  assign TRACE_pc[7] = \<const0> ;
  assign TRACE_pc[8] = \<const0> ;
  assign TRACE_pc[9] = \<const0> ;
  assign TRACE_pc[10] = \<const0> ;
  assign TRACE_pc[11] = \<const0> ;
  assign TRACE_pc[12] = \<const0> ;
  assign TRACE_pc[13] = \<const0> ;
  assign TRACE_pc[14] = \<const0> ;
  assign TRACE_pc[15] = \<const0> ;
  assign TRACE_pc[16] = \<const0> ;
  assign TRACE_pc[17] = \<const0> ;
  assign TRACE_pc[18] = \<const0> ;
  assign TRACE_pc[19] = \<const0> ;
  assign TRACE_pc[20] = \<const0> ;
  assign TRACE_pc[21] = \<const0> ;
  assign TRACE_pc[22] = \<const0> ;
  assign TRACE_pc[23] = \<const0> ;
  assign TRACE_pc[24] = \<const0> ;
  assign TRACE_pc[25] = \<const0> ;
  assign TRACE_pc[26] = \<const0> ;
  assign TRACE_pc[27] = \<const0> ;
  assign TRACE_pc[28] = \<const0> ;
  assign TRACE_pc[29] = \<const0> ;
  assign TRACE_pc[30] = \<const0> ;
  assign TRACE_pc[31] = \<const0> ;
  assign TRACE_pid_reg[0] = \<const0> ;
  assign TRACE_pid_reg[1] = \<const0> ;
  assign TRACE_pid_reg[2] = \<const0> ;
  assign TRACE_pid_reg[3] = \<const0> ;
  assign TRACE_pid_reg[4] = \<const0> ;
  assign TRACE_pid_reg[5] = \<const0> ;
  assign TRACE_pid_reg[6] = \<const0> ;
  assign TRACE_pid_reg[7] = \<const0> ;
  assign TRACE_reg_addr[0] = \<const0> ;
  assign TRACE_reg_addr[1] = \<const0> ;
  assign TRACE_reg_addr[2] = \<const0> ;
  assign TRACE_reg_addr[3] = \<const0> ;
  assign TRACE_reg_addr[4] = \<const0> ;
  assign TRACE_reg_write = \<const0> ;
  assign TRACE_valid_instr = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* CHECK_LICENSE_TYPE = "bd_9054_dlmb_0,lmb_v10,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "lmb_v10,Vivado 2022.2" *) 
  ddr4_0_bd_9054_dlmb_0 dlmb
       (.LMB_ABus({dlmb_sl_0_ABUS,NLW_dlmb_LMB_ABus_UNCONNECTED[30:31]}),
        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),
        .LMB_BE(dlmb_sl_0_BE),
        .LMB_CE(NLW_dlmb_LMB_CE_UNCONNECTED),
        .LMB_Clk(1'b0),
        .LMB_ReadDBus(dlmb_READDBUS),
        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),
        .LMB_Ready(dlmb_READY),
        .LMB_Rst(NLW_dlmb_LMB_Rst_UNCONNECTED),
        .LMB_UE(NLW_dlmb_LMB_UE_UNCONNECTED),
        .LMB_Wait(NLW_dlmb_LMB_Wait_UNCONNECTED),
        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),
        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),
        .M_ABus({dlmb_ABUS,1'b0,1'b0}),
        .M_AddrStrobe(dlmb_ADDRSTROBE),
        .M_BE(dlmb_BE),
        .M_DBus(dlmb_WRITEDBUS),
        .M_ReadStrobe(dlmb_READSTROBE),
        .M_WriteStrobe(dlmb_WRITESTROBE),
        .SYS_Rst(1'b0),
        .Sl_CE({1'b0,1'b0,1'b0}),
        .Sl_DBus({dlmb_sl_0_READDBUS,dlmb_sl_1_READDBUS,dlmb_sl_2_READDBUS}),
        .Sl_Ready({dlmb_sl_0_READY,dlmb_sl_1_READY,dlmb_sl_2_READY}),
        .Sl_UE({1'b0,1'b0,1'b0}),
        .Sl_Wait({1'b0,1'b0,1'b0}));
  (* BMM_INFO_ADDRESS_SPACE = "byte  0x00000000 32 >  bd_9054 lmb_bram_I bd_9054 second_lmb_bram_I" *) 
  (* CHECK_LICENSE_TYPE = "bd_9054_dlmb_cntlr_0,lmb_bram_if_cntlr,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "lmb_bram_if_cntlr,Vivado 2022.2" *) 
  ddr4_0_bd_9054_dlmb_cntlr_0 dlmb_cntlr
       (.BRAM_Addr_A({NLW_dlmb_cntlr_BRAM_Addr_A_UNCONNECTED[0:15],dlmb_port_ADDR,NLW_dlmb_cntlr_BRAM_Addr_A_UNCONNECTED[30:31]}),
        .BRAM_Clk_A(dlmb_port_CLK),
        .BRAM_Din_A({dlmb_port_DOUT[31],dlmb_port_DOUT[30],dlmb_port_DOUT[29],dlmb_port_DOUT[28],dlmb_port_DOUT[27],dlmb_port_DOUT[26],dlmb_port_DOUT[25],dlmb_port_DOUT[24],dlmb_port_DOUT[23],dlmb_port_DOUT[22],dlmb_port_DOUT[21],dlmb_port_DOUT[20],dlmb_port_DOUT[19],dlmb_port_DOUT[18],dlmb_port_DOUT[17],dlmb_port_DOUT[16],dlmb_port_DOUT[15],dlmb_port_DOUT[14],dlmb_port_DOUT[13],dlmb_port_DOUT[12],dlmb_port_DOUT[11],dlmb_port_DOUT[10],dlmb_port_DOUT[9],dlmb_port_DOUT[8],dlmb_port_DOUT[7],dlmb_port_DOUT[6],dlmb_port_DOUT[5],dlmb_port_DOUT[4],dlmb_port_DOUT[3],dlmb_port_DOUT[2],dlmb_port_DOUT[1],dlmb_port_DOUT[0]}),
        .BRAM_Dout_A(dlmb_port_DIN),
        .BRAM_EN_A(dlmb_port_EN),
        .BRAM_Rst_A(NLW_dlmb_cntlr_BRAM_Rst_A_UNCONNECTED),
        .BRAM_WEN_A(dlmb_port_WE),
        .LMB_ABus({dlmb_sl_0_ABUS[0:1],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dlmb_sl_0_ABUS[15:29],1'b0,1'b0}),
        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),
        .LMB_BE(dlmb_sl_0_BE),
        .LMB_Clk(Clk),
        .LMB_ReadStrobe(1'b0),
        .LMB_Rst(LMB_Rst2),
        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),
        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),
        .Sl_CE(NLW_dlmb_cntlr_Sl_CE_UNCONNECTED),
        .Sl_DBus(dlmb_sl_0_READDBUS),
        .Sl_Ready(dlmb_sl_0_READY),
        .Sl_UE(NLW_dlmb_cntlr_Sl_UE_UNCONNECTED),
        .Sl_Wait(NLW_dlmb_cntlr_Sl_Wait_UNCONNECTED));
  (* CHECK_LICENSE_TYPE = "bd_9054_ilmb_0,lmb_v10,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "lmb_v10,Vivado 2022.2" *) 
  ddr4_0_bd_9054_ilmb_0 ilmb
       (.LMB_ABus({ilmb_sl_0_ABUS,NLW_ilmb_LMB_ABus_UNCONNECTED[30:31]}),
        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),
        .LMB_BE(NLW_ilmb_LMB_BE_UNCONNECTED[0:3]),
        .LMB_CE(NLW_ilmb_LMB_CE_UNCONNECTED),
        .LMB_Clk(1'b0),
        .LMB_ReadDBus(ilmb_READDBUS),
        .LMB_ReadStrobe(NLW_ilmb_LMB_ReadStrobe_UNCONNECTED),
        .LMB_Ready(ilmb_READY),
        .LMB_Rst(NLW_ilmb_LMB_Rst_UNCONNECTED),
        .LMB_UE(NLW_ilmb_LMB_UE_UNCONNECTED),
        .LMB_Wait(NLW_ilmb_LMB_Wait_UNCONNECTED),
        .LMB_WriteDBus(NLW_ilmb_LMB_WriteDBus_UNCONNECTED[0:31]),
        .LMB_WriteStrobe(NLW_ilmb_LMB_WriteStrobe_UNCONNECTED),
        .M_ABus({ilmb_ABUS[0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,ilmb_ABUS[15:29],1'b0,1'b0}),
        .M_AddrStrobe(ilmb_ADDRSTROBE),
        .M_BE({1'b0,1'b0,1'b0,1'b0}),
        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_ReadStrobe(1'b0),
        .M_WriteStrobe(1'b0),
        .SYS_Rst(1'b0),
        .Sl_CE({1'b0,1'b0}),
        .Sl_DBus({ilmb_sl_0_READDBUS,ilmb_sl_1_READDBUS}),
        .Sl_Ready({ilmb_sl_0_READY,ilmb_sl_1_READY}),
        .Sl_UE({1'b0,1'b0}),
        .Sl_Wait({1'b0,1'b0}));
  (* CHECK_LICENSE_TYPE = "bd_9054_ilmb_cntlr_0,lmb_bram_if_cntlr,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "lmb_bram_if_cntlr,Vivado 2022.2" *) 
  ddr4_0_bd_9054_ilmb_cntlr_0 ilmb_cntlr
       (.BRAM_Addr_A({NLW_ilmb_cntlr_BRAM_Addr_A_UNCONNECTED[0:15],ilmb_port_ADDR,NLW_ilmb_cntlr_BRAM_Addr_A_UNCONNECTED[30:31]}),
        .BRAM_Clk_A(ilmb_port_CLK),
        .BRAM_Din_A({ilmb_port_DOUT[31],ilmb_port_DOUT[30],ilmb_port_DOUT[29],ilmb_port_DOUT[28],ilmb_port_DOUT[27],ilmb_port_DOUT[26],ilmb_port_DOUT[25],ilmb_port_DOUT[24],ilmb_port_DOUT[23],ilmb_port_DOUT[22],ilmb_port_DOUT[21],ilmb_port_DOUT[20],ilmb_port_DOUT[19],ilmb_port_DOUT[18],ilmb_port_DOUT[17],ilmb_port_DOUT[16],ilmb_port_DOUT[15],ilmb_port_DOUT[14],ilmb_port_DOUT[13],ilmb_port_DOUT[12],ilmb_port_DOUT[11],ilmb_port_DOUT[10],ilmb_port_DOUT[9],ilmb_port_DOUT[8],ilmb_port_DOUT[7],ilmb_port_DOUT[6],ilmb_port_DOUT[5],ilmb_port_DOUT[4],ilmb_port_DOUT[3],ilmb_port_DOUT[2],ilmb_port_DOUT[1],ilmb_port_DOUT[0]}),
        .BRAM_Dout_A(NLW_ilmb_cntlr_BRAM_Dout_A_UNCONNECTED[0:31]),
        .BRAM_EN_A(ilmb_port_EN),
        .BRAM_Rst_A(NLW_ilmb_cntlr_BRAM_Rst_A_UNCONNECTED),
        .BRAM_WEN_A(NLW_ilmb_cntlr_BRAM_WEN_A_UNCONNECTED[0:3]),
        .LMB_ABus({ilmb_sl_0_ABUS[0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,ilmb_sl_0_ABUS[15:29],1'b0,1'b0}),
        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),
        .LMB_BE({1'b0,1'b0,1'b0,1'b0}),
        .LMB_Clk(Clk),
        .LMB_ReadStrobe(1'b0),
        .LMB_Rst(LMB_Rst2),
        .LMB_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .LMB_WriteStrobe(1'b0),
        .Sl_CE(NLW_ilmb_cntlr_Sl_CE_UNCONNECTED),
        .Sl_DBus(ilmb_sl_0_READDBUS),
        .Sl_Ready(ilmb_sl_0_READY),
        .Sl_UE(NLW_ilmb_cntlr_Sl_UE_UNCONNECTED),
        .Sl_Wait(NLW_ilmb_cntlr_Sl_Wait_UNCONNECTED));
  (* CHECK_LICENSE_TYPE = "bd_9054_iomodule_0_0,iomodule,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "iomodule,Vivado 2022.2" *) 
  ddr4_0_bd_9054_iomodule_0_0 iomodule_0
       (.Clk(Clk),
        .IO_Addr_Strobe(IO_addr_strobe),
        .IO_Address({NLW_iomodule_0_IO_Address_UNCONNECTED[31:30],\^IO_address ,NLW_iomodule_0_IO_Address_UNCONNECTED[1:0]}),
        .IO_Byte_Enable(NLW_iomodule_0_IO_Byte_Enable_UNCONNECTED[3:0]),
        .IO_Read_Data(IO_read_data),
        .IO_Read_Strobe(NLW_iomodule_0_IO_Read_Strobe_UNCONNECTED),
        .IO_Ready(IO_ready),
        .IO_Write_Data(IO_write_data),
        .IO_Write_Strobe(IO_write_strobe),
        .LMB_ABus({dlmb_sl_0_ABUS,1'b0,1'b0}),
        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),
        .LMB_BE({1'b0,1'b0,1'b0,1'b0}),
        .LMB_ReadStrobe(dlmb_sl_0_READSTROBE),
        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),
        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),
        .Rst(IO_Rst),
        .Sl_CE(NLW_iomodule_0_Sl_CE_UNCONNECTED),
        .Sl_DBus(dlmb_sl_1_READDBUS),
        .Sl_Ready(dlmb_sl_1_READY),
        .Sl_UE(NLW_iomodule_0_Sl_UE_UNCONNECTED),
        .Sl_Wait(NLW_iomodule_0_Sl_Wait_UNCONNECTED));
  (* CHECK_LICENSE_TYPE = "bd_9054_lmb_bram_I_0,blk_mem_gen_v8_4_5,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "blk_mem_gen_v8_4_5,Vivado 2022.2" *) 
  ddr4_0_bd_9054_lmb_bram_I_0 lmb_bram_I
       (.addra({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dlmb_port_ADDR[16],dlmb_port_ADDR[17],dlmb_port_ADDR[18],dlmb_port_ADDR[19],dlmb_port_ADDR[20],dlmb_port_ADDR[21],dlmb_port_ADDR[22],dlmb_port_ADDR[23],dlmb_port_ADDR[24],dlmb_port_ADDR[25],dlmb_port_ADDR[26],dlmb_port_ADDR[27],dlmb_port_ADDR[28],dlmb_port_ADDR[29],1'b0,1'b0}),
        .addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,ilmb_port_ADDR[16],ilmb_port_ADDR[17],ilmb_port_ADDR[18],ilmb_port_ADDR[19],ilmb_port_ADDR[20],ilmb_port_ADDR[21],ilmb_port_ADDR[22],ilmb_port_ADDR[23],ilmb_port_ADDR[24],ilmb_port_ADDR[25],ilmb_port_ADDR[26],ilmb_port_ADDR[27],ilmb_port_ADDR[28],ilmb_port_ADDR[29],1'b0,1'b0}),
        .clka(dlmb_port_CLK),
        .clkb(ilmb_port_CLK),
        .dina({dlmb_port_DIN[0],dlmb_port_DIN[1],dlmb_port_DIN[2],dlmb_port_DIN[3],dlmb_port_DIN[4],dlmb_port_DIN[5],dlmb_port_DIN[6],dlmb_port_DIN[7],dlmb_port_DIN[8],dlmb_port_DIN[9],dlmb_port_DIN[10],dlmb_port_DIN[11],dlmb_port_DIN[12],dlmb_port_DIN[13],dlmb_port_DIN[14],dlmb_port_DIN[15],dlmb_port_DIN[16],dlmb_port_DIN[17],dlmb_port_DIN[18],dlmb_port_DIN[19],dlmb_port_DIN[20],dlmb_port_DIN[21],dlmb_port_DIN[22],dlmb_port_DIN[23],dlmb_port_DIN[24],dlmb_port_DIN[25],dlmb_port_DIN[26],dlmb_port_DIN[27],dlmb_port_DIN[28],dlmb_port_DIN[29],dlmb_port_DIN[30],dlmb_port_DIN[31]}),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(dlmb_port_DOUT),
        .doutb(ilmb_port_DOUT),
        .ena(dlmb_port_EN),
        .enb(ilmb_port_EN),
        .rsta(1'b0),
        .rsta_busy(NLW_lmb_bram_I_rsta_busy_UNCONNECTED),
        .rstb(1'b0),
        .rstb_busy(NLW_lmb_bram_I_rstb_busy_UNCONNECTED),
        .wea({dlmb_port_WE[0],dlmb_port_WE[1],dlmb_port_WE[2],dlmb_port_WE[3]}),
        .web({1'b0,1'b0,1'b0,1'b0}));
  (* BMM_INFO_PROCESSOR = "microblaze-le > bd_9054 dlmb_cntlr" *) 
  (* CHECK_LICENSE_TYPE = "bd_9054_microblaze_I_0,MicroBlaze,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "MicroBlaze,Vivado 2022.2" *) 
  ddr4_0_bd_9054_microblaze_I_0 microblaze_I
       (.Byte_Enable(dlmb_BE),
        .Clk(Clk),
        .DCE(1'b0),
        .DReady(dlmb_READY),
        .DUE(1'b0),
        .DWait(1'b0),
        .D_AS(dlmb_ADDRSTROBE),
        .Data_Addr({dlmb_ABUS,NLW_microblaze_I_Data_Addr_UNCONNECTED[30:31]}),
        .Data_Read(dlmb_READDBUS),
        .Data_Write(dlmb_WRITEDBUS),
        .ICE(1'b0),
        .IFetch(NLW_microblaze_I_IFetch_UNCONNECTED),
        .IReady(ilmb_READY),
        .IUE(1'b0),
        .IWAIT(1'b0),
        .I_AS(ilmb_ADDRSTROBE),
        .Instr(ilmb_READDBUS),
        .Instr_Addr({ilmb_ABUS,NLW_microblaze_I_Instr_Addr_UNCONNECTED[30:31]}),
        .Interrupt(1'b0),
        .Interrupt_Ack(NLW_microblaze_I_Interrupt_Ack_UNCONNECTED[0:1]),
        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Read_Strobe(dlmb_READSTROBE),
        .Reset(MB_Reset),
        .Trace_DCache_Hit(NLW_microblaze_I_Trace_DCache_Hit_UNCONNECTED),
        .Trace_DCache_Rdy(NLW_microblaze_I_Trace_DCache_Rdy_UNCONNECTED),
        .Trace_DCache_Read(NLW_microblaze_I_Trace_DCache_Read_UNCONNECTED),
        .Trace_DCache_Req(NLW_microblaze_I_Trace_DCache_Req_UNCONNECTED),
        .Trace_Data_Access(NLW_microblaze_I_Trace_Data_Access_UNCONNECTED),
        .Trace_Data_Address(NLW_microblaze_I_Trace_Data_Address_UNCONNECTED[0:31]),
        .Trace_Data_Byte_Enable(NLW_microblaze_I_Trace_Data_Byte_Enable_UNCONNECTED[0:3]),
        .Trace_Data_Read(NLW_microblaze_I_Trace_Data_Read_UNCONNECTED),
        .Trace_Data_Write(NLW_microblaze_I_Trace_Data_Write_UNCONNECTED),
        .Trace_Data_Write_Value(NLW_microblaze_I_Trace_Data_Write_Value_UNCONNECTED[0:31]),
        .Trace_Delay_Slot(NLW_microblaze_I_Trace_Delay_Slot_UNCONNECTED),
        .Trace_EX_PipeRun(NLW_microblaze_I_Trace_EX_PipeRun_UNCONNECTED),
        .Trace_Exception_Kind(NLW_microblaze_I_Trace_Exception_Kind_UNCONNECTED[0:4]),
        .Trace_Exception_Taken(NLW_microblaze_I_Trace_Exception_Taken_UNCONNECTED),
        .Trace_ICache_Hit(NLW_microblaze_I_Trace_ICache_Hit_UNCONNECTED),
        .Trace_ICache_Rdy(NLW_microblaze_I_Trace_ICache_Rdy_UNCONNECTED),
        .Trace_ICache_Req(NLW_microblaze_I_Trace_ICache_Req_UNCONNECTED),
        .Trace_Instruction(NLW_microblaze_I_Trace_Instruction_UNCONNECTED[0:31]),
        .Trace_Jump_Hit(NLW_microblaze_I_Trace_Jump_Hit_UNCONNECTED),
        .Trace_Jump_Taken(NLW_microblaze_I_Trace_Jump_Taken_UNCONNECTED),
        .Trace_MB_Halted(NLW_microblaze_I_Trace_MB_Halted_UNCONNECTED),
        .Trace_MEM_PipeRun(NLW_microblaze_I_Trace_MEM_PipeRun_UNCONNECTED),
        .Trace_MSR_Reg(NLW_microblaze_I_Trace_MSR_Reg_UNCONNECTED[0:14]),
        .Trace_New_Reg_Value(NLW_microblaze_I_Trace_New_Reg_Value_UNCONNECTED[0:31]),
        .Trace_OF_PipeRun(NLW_microblaze_I_Trace_OF_PipeRun_UNCONNECTED),
        .Trace_PC(NLW_microblaze_I_Trace_PC_UNCONNECTED[0:31]),
        .Trace_PID_Reg(NLW_microblaze_I_Trace_PID_Reg_UNCONNECTED[0:7]),
        .Trace_Reg_Addr(NLW_microblaze_I_Trace_Reg_Addr_UNCONNECTED[0:4]),
        .Trace_Reg_Write(NLW_microblaze_I_Trace_Reg_Write_UNCONNECTED),
        .Trace_Valid_Instr(NLW_microblaze_I_Trace_Valid_Instr_UNCONNECTED),
        .Write_Strobe(dlmb_WRITESTROBE));
  (* CHECK_LICENSE_TYPE = "bd_9054_rst_0_0,proc_sys_reset,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "proc_sys_reset,Vivado 2022.2" *) 
  ddr4_0_bd_9054_rst_0_0 rst_0
       (.aux_reset_in(1'b1),
        .bus_struct_reset(LMB_Rst2),
        .dcm_locked(1'b1),
        .ext_reset_in(Reset),
        .interconnect_aresetn(NLW_rst_0_interconnect_aresetn_UNCONNECTED[0]),
        .mb_debug_sys_rst(1'b0),
        .mb_reset(MB_Reset),
        .peripheral_aresetn(NLW_rst_0_peripheral_aresetn_UNCONNECTED[0]),
        .peripheral_reset(IO_Rst),
        .slowest_sync_clk(Clk));
  (* BMM_INFO_ADDRESS_RANGE = " " *) 
  (* CHECK_LICENSE_TYPE = "bd_9054_second_dlmb_cntlr_0,lmb_bram_if_cntlr,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "lmb_bram_if_cntlr,Vivado 2022.2" *) 
  ddr4_0_bd_9054_second_dlmb_cntlr_0 second_dlmb_cntlr
       (.BRAM_Addr_A({NLW_second_dlmb_cntlr_BRAM_Addr_A_UNCONNECTED[0:16],dlmb_port_2_ADDR,NLW_second_dlmb_cntlr_BRAM_Addr_A_UNCONNECTED[30:31]}),
        .BRAM_Clk_A(dlmb_port_2_CLK),
        .BRAM_Din_A({dlmb_port_2_DOUT[31],dlmb_port_2_DOUT[30],dlmb_port_2_DOUT[29],dlmb_port_2_DOUT[28],dlmb_port_2_DOUT[27],dlmb_port_2_DOUT[26],dlmb_port_2_DOUT[25],dlmb_port_2_DOUT[24],dlmb_port_2_DOUT[23],dlmb_port_2_DOUT[22],dlmb_port_2_DOUT[21],dlmb_port_2_DOUT[20],dlmb_port_2_DOUT[19],dlmb_port_2_DOUT[18],dlmb_port_2_DOUT[17],dlmb_port_2_DOUT[16],dlmb_port_2_DOUT[15],dlmb_port_2_DOUT[14],dlmb_port_2_DOUT[13],dlmb_port_2_DOUT[12],dlmb_port_2_DOUT[11],dlmb_port_2_DOUT[10],dlmb_port_2_DOUT[9],dlmb_port_2_DOUT[8],dlmb_port_2_DOUT[7],dlmb_port_2_DOUT[6],dlmb_port_2_DOUT[5],dlmb_port_2_DOUT[4],dlmb_port_2_DOUT[3],dlmb_port_2_DOUT[2],dlmb_port_2_DOUT[1],dlmb_port_2_DOUT[0]}),
        .BRAM_Dout_A(dlmb_port_2_DIN),
        .BRAM_EN_A(dlmb_port_2_EN),
        .BRAM_Rst_A(NLW_second_dlmb_cntlr_BRAM_Rst_A_UNCONNECTED),
        .BRAM_WEN_A(dlmb_port_2_WE),
        .LMB_ABus({dlmb_sl_0_ABUS[0:1],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dlmb_sl_0_ABUS[15],1'b0,dlmb_sl_0_ABUS[17:29],1'b0,1'b0}),
        .LMB_AddrStrobe(dlmb_sl_0_ADDRSTROBE),
        .LMB_BE(dlmb_sl_0_BE),
        .LMB_Clk(Clk),
        .LMB_ReadStrobe(1'b0),
        .LMB_Rst(LMB_Rst2),
        .LMB_WriteDBus(dlmb_sl_0_WRITEDBUS),
        .LMB_WriteStrobe(dlmb_sl_0_WRITESTROBE),
        .Sl_CE(NLW_second_dlmb_cntlr_Sl_CE_UNCONNECTED),
        .Sl_DBus(dlmb_sl_2_READDBUS),
        .Sl_Ready(dlmb_sl_2_READY),
        .Sl_UE(NLW_second_dlmb_cntlr_Sl_UE_UNCONNECTED),
        .Sl_Wait(NLW_second_dlmb_cntlr_Sl_Wait_UNCONNECTED));
  (* CHECK_LICENSE_TYPE = "bd_9054_second_ilmb_cntlr_0,lmb_bram_if_cntlr,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "lmb_bram_if_cntlr,Vivado 2022.2" *) 
  ddr4_0_bd_9054_second_ilmb_cntlr_0 second_ilmb_cntlr
       (.BRAM_Addr_A({NLW_second_ilmb_cntlr_BRAM_Addr_A_UNCONNECTED[0:16],ilmb_port_2_ADDR,NLW_second_ilmb_cntlr_BRAM_Addr_A_UNCONNECTED[30:31]}),
        .BRAM_Clk_A(ilmb_port_2_CLK),
        .BRAM_Din_A({ilmb_port_2_DOUT[31],ilmb_port_2_DOUT[30],ilmb_port_2_DOUT[29],ilmb_port_2_DOUT[28],ilmb_port_2_DOUT[27],ilmb_port_2_DOUT[26],ilmb_port_2_DOUT[25],ilmb_port_2_DOUT[24],ilmb_port_2_DOUT[23],ilmb_port_2_DOUT[22],ilmb_port_2_DOUT[21],ilmb_port_2_DOUT[20],ilmb_port_2_DOUT[19],ilmb_port_2_DOUT[18],ilmb_port_2_DOUT[17],ilmb_port_2_DOUT[16],ilmb_port_2_DOUT[15],ilmb_port_2_DOUT[14],ilmb_port_2_DOUT[13],ilmb_port_2_DOUT[12],ilmb_port_2_DOUT[11],ilmb_port_2_DOUT[10],ilmb_port_2_DOUT[9],ilmb_port_2_DOUT[8],ilmb_port_2_DOUT[7],ilmb_port_2_DOUT[6],ilmb_port_2_DOUT[5],ilmb_port_2_DOUT[4],ilmb_port_2_DOUT[3],ilmb_port_2_DOUT[2],ilmb_port_2_DOUT[1],ilmb_port_2_DOUT[0]}),
        .BRAM_Dout_A(NLW_second_ilmb_cntlr_BRAM_Dout_A_UNCONNECTED[0:31]),
        .BRAM_EN_A(ilmb_port_2_EN),
        .BRAM_Rst_A(NLW_second_ilmb_cntlr_BRAM_Rst_A_UNCONNECTED),
        .BRAM_WEN_A(NLW_second_ilmb_cntlr_BRAM_WEN_A_UNCONNECTED[0:3]),
        .LMB_ABus({ilmb_sl_0_ABUS[0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,ilmb_sl_0_ABUS[15],1'b0,ilmb_sl_0_ABUS[17:29],1'b0,1'b0}),
        .LMB_AddrStrobe(ilmb_sl_0_ADDRSTROBE),
        .LMB_BE({1'b0,1'b0,1'b0,1'b0}),
        .LMB_Clk(Clk),
        .LMB_ReadStrobe(1'b0),
        .LMB_Rst(LMB_Rst2),
        .LMB_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .LMB_WriteStrobe(1'b0),
        .Sl_CE(NLW_second_ilmb_cntlr_Sl_CE_UNCONNECTED),
        .Sl_DBus(ilmb_sl_1_READDBUS),
        .Sl_Ready(ilmb_sl_1_READY),
        .Sl_UE(NLW_second_ilmb_cntlr_Sl_UE_UNCONNECTED),
        .Sl_Wait(NLW_second_ilmb_cntlr_Sl_Wait_UNCONNECTED));
  (* CHECK_LICENSE_TYPE = "bd_9054_second_lmb_bram_I_0,blk_mem_gen_v8_4_5,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "blk_mem_gen_v8_4_5,Vivado 2022.2" *) 
  ddr4_0_bd_9054_second_lmb_bram_I_0 second_lmb_bram_I
       (.addra({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dlmb_port_2_ADDR[17],dlmb_port_2_ADDR[18],dlmb_port_2_ADDR[19],dlmb_port_2_ADDR[20],dlmb_port_2_ADDR[21],dlmb_port_2_ADDR[22],dlmb_port_2_ADDR[23],dlmb_port_2_ADDR[24],dlmb_port_2_ADDR[25],dlmb_port_2_ADDR[26],dlmb_port_2_ADDR[27],dlmb_port_2_ADDR[28],dlmb_port_2_ADDR[29],1'b0,1'b0}),
        .addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,ilmb_port_2_ADDR[17],ilmb_port_2_ADDR[18],ilmb_port_2_ADDR[19],ilmb_port_2_ADDR[20],ilmb_port_2_ADDR[21],ilmb_port_2_ADDR[22],ilmb_port_2_ADDR[23],ilmb_port_2_ADDR[24],ilmb_port_2_ADDR[25],ilmb_port_2_ADDR[26],ilmb_port_2_ADDR[27],ilmb_port_2_ADDR[28],ilmb_port_2_ADDR[29],1'b0,1'b0}),
        .clka(dlmb_port_2_CLK),
        .clkb(ilmb_port_2_CLK),
        .dina({dlmb_port_2_DIN[0],dlmb_port_2_DIN[1],dlmb_port_2_DIN[2],dlmb_port_2_DIN[3],dlmb_port_2_DIN[4],dlmb_port_2_DIN[5],dlmb_port_2_DIN[6],dlmb_port_2_DIN[7],dlmb_port_2_DIN[8],dlmb_port_2_DIN[9],dlmb_port_2_DIN[10],dlmb_port_2_DIN[11],dlmb_port_2_DIN[12],dlmb_port_2_DIN[13],dlmb_port_2_DIN[14],dlmb_port_2_DIN[15],dlmb_port_2_DIN[16],dlmb_port_2_DIN[17],dlmb_port_2_DIN[18],dlmb_port_2_DIN[19],dlmb_port_2_DIN[20],dlmb_port_2_DIN[21],dlmb_port_2_DIN[22],dlmb_port_2_DIN[23],dlmb_port_2_DIN[24],dlmb_port_2_DIN[25],dlmb_port_2_DIN[26],dlmb_port_2_DIN[27],dlmb_port_2_DIN[28],dlmb_port_2_DIN[29],dlmb_port_2_DIN[30],dlmb_port_2_DIN[31]}),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(dlmb_port_2_DOUT),
        .doutb(ilmb_port_2_DOUT),
        .ena(dlmb_port_2_EN),
        .enb(ilmb_port_2_EN),
        .rsta(1'b0),
        .rsta_busy(NLW_second_lmb_bram_I_rsta_busy_UNCONNECTED),
        .rstb(1'b0),
        .rstb_busy(NLW_second_lmb_bram_I_rstb_busy_UNCONNECTED),
        .wea({dlmb_port_2_WE[0],dlmb_port_2_WE[1],dlmb_port_2_WE[2],dlmb_port_2_WE[3]}),
        .web({1'b0,1'b0,1'b0,1'b0}));
endmodule

(* CHECK_LICENSE_TYPE = "bd_9054_dlmb_0,lmb_v10,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "bd_9054_dlmb_0" *) 
(* X_CORE_INFO = "lmb_v10,Vivado 2022.2" *) 
module ddr4_0_bd_9054_dlmb_0
   (LMB_Clk,
    SYS_Rst,
    LMB_Rst,
    M_ABus,
    M_ReadStrobe,
    M_WriteStrobe,
    M_AddrStrobe,
    M_DBus,
    M_BE,
    Sl_DBus,
    Sl_Ready,
    Sl_Wait,
    Sl_UE,
    Sl_CE,
    LMB_ABus,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_AddrStrobe,
    LMB_ReadDBus,
    LMB_WriteDBus,
    LMB_Ready,
    LMB_Wait,
    LMB_UE,
    LMB_CE,
    LMB_BE);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M, ASSOCIATED_RESET SYS_Rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_9054_Clk, INSERT_VIP 0" *) input LMB_Clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.SYS_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input SYS_Rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M RST, xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_Sl_1 RST, xilinx.com:interface:lmb:1.0 LMB_Sl_2 RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME LMB_Sl_0, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD, XIL_INTERFACENAME LMB_Sl_1, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD, XIL_INTERFACENAME LMB_Sl_2, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD, XIL_INTERFACENAME LMB_M, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD" *) output LMB_Rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M ABUS" *) input [0:31]M_ABus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE" *) input M_ReadStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE" *) input M_WriteStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE" *) input M_AddrStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS" *) input [0:31]M_DBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M BE" *) input [0:3]M_BE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS, xilinx.com:interface:lmb:1.0 LMB_Sl_1 READDBUS, xilinx.com:interface:lmb:1.0 LMB_Sl_2 READDBUS" *) input [0:95]Sl_DBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY, xilinx.com:interface:lmb:1.0 LMB_Sl_1 READY, xilinx.com:interface:lmb:1.0 LMB_Sl_2 READY" *) input [0:2]Sl_Ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT, xilinx.com:interface:lmb:1.0 LMB_Sl_1 WAIT, xilinx.com:interface:lmb:1.0 LMB_Sl_2 WAIT" *) input [0:2]Sl_Wait;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE, xilinx.com:interface:lmb:1.0 LMB_Sl_1 UE, xilinx.com:interface:lmb:1.0 LMB_Sl_2 UE" *) input [0:2]Sl_UE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE, xilinx.com:interface:lmb:1.0 LMB_Sl_1 CE, xilinx.com:interface:lmb:1.0 LMB_Sl_2 CE" *) input [0:2]Sl_CE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS, xilinx.com:interface:lmb:1.0 LMB_Sl_1 ABUS, xilinx.com:interface:lmb:1.0 LMB_Sl_2 ABUS" *) output [0:31]LMB_ABus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE, xilinx.com:interface:lmb:1.0 LMB_Sl_1 READSTROBE, xilinx.com:interface:lmb:1.0 LMB_Sl_2 READSTROBE" *) output LMB_ReadStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE, xilinx.com:interface:lmb:1.0 LMB_Sl_1 WRITESTROBE, xilinx.com:interface:lmb:1.0 LMB_Sl_2 WRITESTROBE" *) output LMB_WriteStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE, xilinx.com:interface:lmb:1.0 LMB_Sl_1 ADDRSTROBE, xilinx.com:interface:lmb:1.0 LMB_Sl_2 ADDRSTROBE" *) output LMB_AddrStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M READDBUS" *) output [0:31]LMB_ReadDBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS, xilinx.com:interface:lmb:1.0 LMB_Sl_1 WRITEDBUS, xilinx.com:interface:lmb:1.0 LMB_Sl_2 WRITEDBUS" *) output [0:31]LMB_WriteDBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M READY" *) output LMB_Ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M WAIT" *) output LMB_Wait;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M UE" *) output LMB_UE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M CE" *) output LMB_CE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE, xilinx.com:interface:lmb:1.0 LMB_Sl_1 BE, xilinx.com:interface:lmb:1.0 LMB_Sl_2 BE" *) output [0:3]LMB_BE;

  wire \<const0> ;
  wire [0:29]\^LMB_ABus ;
  wire LMB_AddrStrobe;
  wire [0:3]LMB_BE;
  wire [0:31]LMB_ReadDBus;
  wire LMB_ReadStrobe;
  wire LMB_Ready;
  wire [0:31]LMB_WriteDBus;
  wire LMB_WriteStrobe;
  wire [0:31]M_ABus;
  wire M_AddrStrobe;
  wire [0:3]M_BE;
  wire [0:31]M_DBus;
  wire M_ReadStrobe;
  wire M_WriteStrobe;
  wire [0:95]Sl_DBus;
  wire [0:2]Sl_Ready;
  wire NLW_U0_LMB_CE_UNCONNECTED;
  wire NLW_U0_LMB_Rst_UNCONNECTED;
  wire NLW_U0_LMB_UE_UNCONNECTED;
  wire NLW_U0_LMB_Wait_UNCONNECTED;
  wire [30:31]NLW_U0_LMB_ABus_UNCONNECTED;

  assign LMB_ABus[0:29] = \^LMB_ABus [0:29];
  assign LMB_ABus[30] = \<const0> ;
  assign LMB_ABus[31] = \<const0> ;
  assign LMB_CE = \<const0> ;
  assign LMB_Rst = \<const0> ;
  assign LMB_UE = \<const0> ;
  assign LMB_Wait = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_EXT_RESET_HIGH = "1" *) 
  (* C_LMB_AWIDTH = "32" *) 
  (* C_LMB_DWIDTH = "32" *) 
  (* C_LMB_NUM_SLAVES = "3" *) 
  (* C_LMB_PROTOCOL = "0" *) 
  ddr4_0_lmb_v10 U0
       (.LMB_ABus({\^LMB_ABus ,NLW_U0_LMB_ABus_UNCONNECTED[30:31]}),
        .LMB_AddrStrobe(LMB_AddrStrobe),
        .LMB_BE(LMB_BE),
        .LMB_CE(NLW_U0_LMB_CE_UNCONNECTED),
        .LMB_Clk(1'b0),
        .LMB_ReadDBus(LMB_ReadDBus),
        .LMB_ReadStrobe(LMB_ReadStrobe),
        .LMB_Ready(LMB_Ready),
        .LMB_Rst(NLW_U0_LMB_Rst_UNCONNECTED),
        .LMB_UE(NLW_U0_LMB_UE_UNCONNECTED),
        .LMB_Wait(NLW_U0_LMB_Wait_UNCONNECTED),
        .LMB_WriteDBus(LMB_WriteDBus),
        .LMB_WriteStrobe(LMB_WriteStrobe),
        .M_ABus({M_ABus[0:29],1'b0,1'b0}),
        .M_AddrStrobe(M_AddrStrobe),
        .M_BE(M_BE),
        .M_DBus(M_DBus),
        .M_ReadStrobe(M_ReadStrobe),
        .M_WriteStrobe(M_WriteStrobe),
        .SYS_Rst(1'b0),
        .Sl_CE({1'b0,1'b0,1'b0}),
        .Sl_DBus(Sl_DBus),
        .Sl_Ready(Sl_Ready),
        .Sl_UE({1'b0,1'b0,1'b0}),
        .Sl_Wait({1'b0,1'b0,1'b0}));
endmodule

(* CHECK_LICENSE_TYPE = "bd_9054_dlmb_cntlr_0,lmb_bram_if_cntlr,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "bd_9054_dlmb_cntlr_0" *) 
(* X_CORE_INFO = "lmb_bram_if_cntlr,Vivado 2022.2" *) 
module ddr4_0_bd_9054_dlmb_cntlr_0
   (LMB_Clk,
    LMB_Rst,
    LMB_ABus,
    LMB_WriteDBus,
    LMB_AddrStrobe,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_BE,
    Sl_DBus,
    Sl_Ready,
    Sl_Wait,
    Sl_UE,
    Sl_CE,
    BRAM_Rst_A,
    BRAM_Clk_A,
    BRAM_Addr_A,
    BRAM_EN_A,
    BRAM_WEN_A,
    BRAM_Dout_A,
    BRAM_Din_A);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_9054_Clk, INSERT_VIP 0" *) input LMB_Clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD" *) input [0:31]LMB_ABus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 65536, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A;

  wire \<const0> ;
  wire [0:31]BRAM_Din_A;
  wire [0:3]BRAM_WEN_A;
  wire [0:31]LMB_ABus;
  wire LMB_AddrStrobe;
  wire [0:3]LMB_BE;
  wire LMB_Clk;
  wire LMB_Rst;
  wire [0:31]LMB_WriteDBus;
  wire LMB_WriteStrobe;
  wire Sl_Ready;

  assign BRAM_Addr_A[0] = \<const0> ;
  assign BRAM_Addr_A[1] = \<const0> ;
  assign BRAM_Addr_A[2] = \<const0> ;
  assign BRAM_Addr_A[3] = \<const0> ;
  assign BRAM_Addr_A[4] = \<const0> ;
  assign BRAM_Addr_A[5] = \<const0> ;
  assign BRAM_Addr_A[6] = \<const0> ;
  assign BRAM_Addr_A[7] = \<const0> ;
  assign BRAM_Addr_A[8] = \<const0> ;
  assign BRAM_Addr_A[9] = \<const0> ;
  assign BRAM_Addr_A[10] = \<const0> ;
  assign BRAM_Addr_A[11] = \<const0> ;
  assign BRAM_Addr_A[12] = \<const0> ;
  assign BRAM_Addr_A[13] = \<const0> ;
  assign BRAM_Addr_A[14] = \<const0> ;
  assign BRAM_Addr_A[15] = \<const0> ;
  assign BRAM_Addr_A[16:29] = LMB_ABus[16:29];
  assign BRAM_Addr_A[30] = \<const0> ;
  assign BRAM_Addr_A[31] = \<const0> ;
  assign BRAM_Clk_A = LMB_Clk;
  assign BRAM_Dout_A[0:31] = LMB_WriteDBus;
  assign BRAM_EN_A = LMB_AddrStrobe;
  assign BRAM_Rst_A = \<const0> ;
  assign Sl_CE = \<const0> ;
  assign Sl_DBus[0:31] = BRAM_Din_A;
  assign Sl_UE = \<const0> ;
  assign Sl_Wait = \<const0> ;
  GND GND
       (.G(\<const0> ));
  ddr4_0_lmb_bram_if_cntlr U0
       (.BRAM_WEN_A(BRAM_WEN_A),
        .LMB_ABus({LMB_ABus[0],LMB_ABus[1],LMB_ABus[15]}),
        .LMB_AddrStrobe(LMB_AddrStrobe),
        .LMB_BE(LMB_BE),
        .LMB_Clk(LMB_Clk),
        .LMB_Rst(LMB_Rst),
        .LMB_WriteStrobe(LMB_WriteStrobe),
        .Sl_Ready(Sl_Ready));
endmodule

(* CHECK_LICENSE_TYPE = "bd_9054_ilmb_0,lmb_v10,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "bd_9054_ilmb_0" *) 
(* X_CORE_INFO = "lmb_v10,Vivado 2022.2" *) 
module ddr4_0_bd_9054_ilmb_0
   (LMB_Clk,
    SYS_Rst,
    LMB_Rst,
    M_ABus,
    M_ReadStrobe,
    M_WriteStrobe,
    M_AddrStrobe,
    M_DBus,
    M_BE,
    Sl_DBus,
    Sl_Ready,
    Sl_Wait,
    Sl_UE,
    Sl_CE,
    LMB_ABus,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_AddrStrobe,
    LMB_ReadDBus,
    LMB_WriteDBus,
    LMB_Ready,
    LMB_Wait,
    LMB_UE,
    LMB_CE,
    LMB_BE);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M, ASSOCIATED_RESET SYS_Rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_9054_Clk, INSERT_VIP 0" *) input LMB_Clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.SYS_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input SYS_Rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_Sl_1 RST, xilinx.com:interface:lmb:1.0 LMB_M RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME LMB_Sl_0, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD, XIL_INTERFACENAME LMB_Sl_1, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD, XIL_INTERFACENAME LMB_M, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_ONLY, PROTOCOL STANDARD" *) output LMB_Rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M ABUS" *) input [0:31]M_ABus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE" *) input M_ReadStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE" *) input M_WriteStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE" *) input M_AddrStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS" *) input [0:31]M_DBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M BE" *) input [0:3]M_BE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS, xilinx.com:interface:lmb:1.0 LMB_Sl_1 READDBUS" *) input [0:63]Sl_DBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY, xilinx.com:interface:lmb:1.0 LMB_Sl_1 READY" *) input [0:1]Sl_Ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT, xilinx.com:interface:lmb:1.0 LMB_Sl_1 WAIT" *) input [0:1]Sl_Wait;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE, xilinx.com:interface:lmb:1.0 LMB_Sl_1 UE" *) input [0:1]Sl_UE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE, xilinx.com:interface:lmb:1.0 LMB_Sl_1 CE" *) input [0:1]Sl_CE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS, xilinx.com:interface:lmb:1.0 LMB_Sl_1 ABUS" *) output [0:31]LMB_ABus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE, xilinx.com:interface:lmb:1.0 LMB_Sl_1 READSTROBE" *) output LMB_ReadStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE, xilinx.com:interface:lmb:1.0 LMB_Sl_1 WRITESTROBE" *) output LMB_WriteStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE, xilinx.com:interface:lmb:1.0 LMB_Sl_1 ADDRSTROBE" *) output LMB_AddrStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M READDBUS" *) output [0:31]LMB_ReadDBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS, xilinx.com:interface:lmb:1.0 LMB_Sl_1 WRITEDBUS" *) output [0:31]LMB_WriteDBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M READY" *) output LMB_Ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M WAIT" *) output LMB_Wait;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M UE" *) output LMB_UE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_M CE" *) output LMB_CE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE, xilinx.com:interface:lmb:1.0 LMB_Sl_1 BE" *) output [0:3]LMB_BE;

  wire \<const0> ;
  wire [0:29]\^LMB_ABus ;
  wire LMB_AddrStrobe;
  wire [0:31]LMB_ReadDBus;
  wire LMB_Ready;
  wire [0:31]M_ABus;
  wire M_AddrStrobe;
  wire [0:63]Sl_DBus;
  wire [0:1]Sl_Ready;
  wire NLW_U0_LMB_CE_UNCONNECTED;
  wire NLW_U0_LMB_ReadStrobe_UNCONNECTED;
  wire NLW_U0_LMB_Rst_UNCONNECTED;
  wire NLW_U0_LMB_UE_UNCONNECTED;
  wire NLW_U0_LMB_Wait_UNCONNECTED;
  wire NLW_U0_LMB_WriteStrobe_UNCONNECTED;
  wire [1:31]NLW_U0_LMB_ABus_UNCONNECTED;
  wire [0:3]NLW_U0_LMB_BE_UNCONNECTED;
  wire [0:31]NLW_U0_LMB_WriteDBus_UNCONNECTED;

  assign LMB_ABus[0] = \^LMB_ABus [0];
  assign LMB_ABus[1] = \<const0> ;
  assign LMB_ABus[2] = \<const0> ;
  assign LMB_ABus[3] = \<const0> ;
  assign LMB_ABus[4] = \<const0> ;
  assign LMB_ABus[5] = \<const0> ;
  assign LMB_ABus[6] = \<const0> ;
  assign LMB_ABus[7] = \<const0> ;
  assign LMB_ABus[8] = \<const0> ;
  assign LMB_ABus[9] = \<const0> ;
  assign LMB_ABus[10] = \<const0> ;
  assign LMB_ABus[11] = \<const0> ;
  assign LMB_ABus[12] = \<const0> ;
  assign LMB_ABus[13] = \<const0> ;
  assign LMB_ABus[14] = \<const0> ;
  assign LMB_ABus[15:29] = \^LMB_ABus [15:29];
  assign LMB_ABus[30] = \<const0> ;
  assign LMB_ABus[31] = \<const0> ;
  assign LMB_BE[0] = \<const0> ;
  assign LMB_BE[1] = \<const0> ;
  assign LMB_BE[2] = \<const0> ;
  assign LMB_BE[3] = \<const0> ;
  assign LMB_CE = \<const0> ;
  assign LMB_ReadStrobe = \<const0> ;
  assign LMB_Rst = \<const0> ;
  assign LMB_UE = \<const0> ;
  assign LMB_Wait = \<const0> ;
  assign LMB_WriteDBus[0] = \<const0> ;
  assign LMB_WriteDBus[1] = \<const0> ;
  assign LMB_WriteDBus[2] = \<const0> ;
  assign LMB_WriteDBus[3] = \<const0> ;
  assign LMB_WriteDBus[4] = \<const0> ;
  assign LMB_WriteDBus[5] = \<const0> ;
  assign LMB_WriteDBus[6] = \<const0> ;
  assign LMB_WriteDBus[7] = \<const0> ;
  assign LMB_WriteDBus[8] = \<const0> ;
  assign LMB_WriteDBus[9] = \<const0> ;
  assign LMB_WriteDBus[10] = \<const0> ;
  assign LMB_WriteDBus[11] = \<const0> ;
  assign LMB_WriteDBus[12] = \<const0> ;
  assign LMB_WriteDBus[13] = \<const0> ;
  assign LMB_WriteDBus[14] = \<const0> ;
  assign LMB_WriteDBus[15] = \<const0> ;
  assign LMB_WriteDBus[16] = \<const0> ;
  assign LMB_WriteDBus[17] = \<const0> ;
  assign LMB_WriteDBus[18] = \<const0> ;
  assign LMB_WriteDBus[19] = \<const0> ;
  assign LMB_WriteDBus[20] = \<const0> ;
  assign LMB_WriteDBus[21] = \<const0> ;
  assign LMB_WriteDBus[22] = \<const0> ;
  assign LMB_WriteDBus[23] = \<const0> ;
  assign LMB_WriteDBus[24] = \<const0> ;
  assign LMB_WriteDBus[25] = \<const0> ;
  assign LMB_WriteDBus[26] = \<const0> ;
  assign LMB_WriteDBus[27] = \<const0> ;
  assign LMB_WriteDBus[28] = \<const0> ;
  assign LMB_WriteDBus[29] = \<const0> ;
  assign LMB_WriteDBus[30] = \<const0> ;
  assign LMB_WriteDBus[31] = \<const0> ;
  assign LMB_WriteStrobe = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_EXT_RESET_HIGH = "1" *) 
  (* C_LMB_AWIDTH = "32" *) 
  (* C_LMB_DWIDTH = "32" *) 
  (* C_LMB_NUM_SLAVES = "2" *) 
  (* C_LMB_PROTOCOL = "0" *) 
  ddr4_0_lmb_v10__parameterized1 U0
       (.LMB_ABus({\^LMB_ABus ,NLW_U0_LMB_ABus_UNCONNECTED[30:31]}),
        .LMB_AddrStrobe(LMB_AddrStrobe),
        .LMB_BE(NLW_U0_LMB_BE_UNCONNECTED[0:3]),
        .LMB_CE(NLW_U0_LMB_CE_UNCONNECTED),
        .LMB_Clk(1'b0),
        .LMB_ReadDBus(LMB_ReadDBus),
        .LMB_ReadStrobe(NLW_U0_LMB_ReadStrobe_UNCONNECTED),
        .LMB_Ready(LMB_Ready),
        .LMB_Rst(NLW_U0_LMB_Rst_UNCONNECTED),
        .LMB_UE(NLW_U0_LMB_UE_UNCONNECTED),
        .LMB_Wait(NLW_U0_LMB_Wait_UNCONNECTED),
        .LMB_WriteDBus(NLW_U0_LMB_WriteDBus_UNCONNECTED[0:31]),
        .LMB_WriteStrobe(NLW_U0_LMB_WriteStrobe_UNCONNECTED),
        .M_ABus({M_ABus[0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,M_ABus[15:29],1'b0,1'b0}),
        .M_AddrStrobe(M_AddrStrobe),
        .M_BE({1'b0,1'b0,1'b0,1'b0}),
        .M_DBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_ReadStrobe(1'b0),
        .M_WriteStrobe(1'b0),
        .SYS_Rst(1'b0),
        .Sl_CE({1'b0,1'b0}),
        .Sl_DBus(Sl_DBus),
        .Sl_Ready(Sl_Ready),
        .Sl_UE({1'b0,1'b0}),
        .Sl_Wait({1'b0,1'b0}));
endmodule

(* CHECK_LICENSE_TYPE = "bd_9054_ilmb_cntlr_0,lmb_bram_if_cntlr,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "bd_9054_ilmb_cntlr_0" *) 
(* X_CORE_INFO = "lmb_bram_if_cntlr,Vivado 2022.2" *) 
module ddr4_0_bd_9054_ilmb_cntlr_0
   (LMB_Clk,
    LMB_Rst,
    LMB_ABus,
    LMB_WriteDBus,
    LMB_AddrStrobe,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_BE,
    Sl_DBus,
    Sl_Ready,
    Sl_Wait,
    Sl_UE,
    Sl_CE,
    BRAM_Rst_A,
    BRAM_Clk_A,
    BRAM_Addr_A,
    BRAM_EN_A,
    BRAM_WEN_A,
    BRAM_Dout_A,
    BRAM_Din_A);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_9054_Clk, INSERT_VIP 0" *) input LMB_Clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD" *) input [0:31]LMB_ABus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 65536, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A;

  wire \<const0> ;
  wire [0:31]BRAM_Din_A;
  wire [0:31]LMB_ABus;
  wire LMB_AddrStrobe;
  wire LMB_Clk;
  wire LMB_Rst;
  wire Sl_Ready;

  assign BRAM_Addr_A[0] = \<const0> ;
  assign BRAM_Addr_A[1] = \<const0> ;
  assign BRAM_Addr_A[2] = \<const0> ;
  assign BRAM_Addr_A[3] = \<const0> ;
  assign BRAM_Addr_A[4] = \<const0> ;
  assign BRAM_Addr_A[5] = \<const0> ;
  assign BRAM_Addr_A[6] = \<const0> ;
  assign BRAM_Addr_A[7] = \<const0> ;
  assign BRAM_Addr_A[8] = \<const0> ;
  assign BRAM_Addr_A[9] = \<const0> ;
  assign BRAM_Addr_A[10] = \<const0> ;
  assign BRAM_Addr_A[11] = \<const0> ;
  assign BRAM_Addr_A[12] = \<const0> ;
  assign BRAM_Addr_A[13] = \<const0> ;
  assign BRAM_Addr_A[14] = \<const0> ;
  assign BRAM_Addr_A[15] = \<const0> ;
  assign BRAM_Addr_A[16:29] = LMB_ABus[16:29];
  assign BRAM_Addr_A[30] = \<const0> ;
  assign BRAM_Addr_A[31] = \<const0> ;
  assign BRAM_Clk_A = LMB_Clk;
  assign BRAM_Dout_A[0] = \<const0> ;
  assign BRAM_Dout_A[1] = \<const0> ;
  assign BRAM_Dout_A[2] = \<const0> ;
  assign BRAM_Dout_A[3] = \<const0> ;
  assign BRAM_Dout_A[4] = \<const0> ;
  assign BRAM_Dout_A[5] = \<const0> ;
  assign BRAM_Dout_A[6] = \<const0> ;
  assign BRAM_Dout_A[7] = \<const0> ;
  assign BRAM_Dout_A[8] = \<const0> ;
  assign BRAM_Dout_A[9] = \<const0> ;
  assign BRAM_Dout_A[10] = \<const0> ;
  assign BRAM_Dout_A[11] = \<const0> ;
  assign BRAM_Dout_A[12] = \<const0> ;
  assign BRAM_Dout_A[13] = \<const0> ;
  assign BRAM_Dout_A[14] = \<const0> ;
  assign BRAM_Dout_A[15] = \<const0> ;
  assign BRAM_Dout_A[16] = \<const0> ;
  assign BRAM_Dout_A[17] = \<const0> ;
  assign BRAM_Dout_A[18] = \<const0> ;
  assign BRAM_Dout_A[19] = \<const0> ;
  assign BRAM_Dout_A[20] = \<const0> ;
  assign BRAM_Dout_A[21] = \<const0> ;
  assign BRAM_Dout_A[22] = \<const0> ;
  assign BRAM_Dout_A[23] = \<const0> ;
  assign BRAM_Dout_A[24] = \<const0> ;
  assign BRAM_Dout_A[25] = \<const0> ;
  assign BRAM_Dout_A[26] = \<const0> ;
  assign BRAM_Dout_A[27] = \<const0> ;
  assign BRAM_Dout_A[28] = \<const0> ;
  assign BRAM_Dout_A[29] = \<const0> ;
  assign BRAM_Dout_A[30] = \<const0> ;
  assign BRAM_Dout_A[31] = \<const0> ;
  assign BRAM_EN_A = LMB_AddrStrobe;
  assign BRAM_Rst_A = \<const0> ;
  assign BRAM_WEN_A[0] = \<const0> ;
  assign BRAM_WEN_A[1] = \<const0> ;
  assign BRAM_WEN_A[2] = \<const0> ;
  assign BRAM_WEN_A[3] = \<const0> ;
  assign Sl_CE = \<const0> ;
  assign Sl_DBus[0:31] = BRAM_Din_A;
  assign Sl_UE = \<const0> ;
  assign Sl_Wait = \<const0> ;
  GND GND
       (.G(\<const0> ));
  ddr4_0_lmb_bram_if_cntlr__parameterized1 U0
       (.LMB_ABus({LMB_ABus[0],LMB_ABus[15]}),
        .LMB_AddrStrobe(LMB_AddrStrobe),
        .LMB_Clk(LMB_Clk),
        .LMB_Rst(LMB_Rst),
        .Sl_Ready(Sl_Ready));
endmodule

(* CHECK_LICENSE_TYPE = "bd_9054_iomodule_0_0,iomodule,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "bd_9054_iomodule_0_0" *) 
(* X_CORE_INFO = "iomodule,Vivado 2022.2" *) 
module ddr4_0_bd_9054_iomodule_0_0
   (Clk,
    Rst,
    IO_Addr_Strobe,
    IO_Read_Strobe,
    IO_Write_Strobe,
    IO_Address,
    IO_Byte_Enable,
    IO_Write_Data,
    IO_Read_Data,
    IO_Ready,
    LMB_ABus,
    LMB_WriteDBus,
    LMB_AddrStrobe,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_BE,
    Sl_DBus,
    Sl_Ready,
    Sl_Wait,
    Sl_UE,
    Sl_CE);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF SLMB, ASSOCIATED_RESET Rst:TMR_Rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_9054_Clk, INSERT_VIP 0" *) input Clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.Rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.Rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) input Rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO_BUS ADDR_STROBE" *) output IO_Addr_Strobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO_BUS READ_STROBE" *) output IO_Read_Strobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO_BUS WRITE_STROBE" *) output IO_Write_Strobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO_BUS ADDRESS" *) output [31:0]IO_Address;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO_BUS BYTE_ENABLE" *) output [3:0]IO_Byte_Enable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO_BUS WRITE_DATA" *) output [31:0]IO_Write_Data;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO_BUS READ_DATA" *) input [31:0]IO_Read_Data;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO_BUS READY" *) input IO_Ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD" *) input [0:31]LMB_ABus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;

  wire \<const0> ;
  wire Clk;
  wire IO_Addr_Strobe;
  wire [29:2]\^IO_Address ;
  wire [31:0]IO_Read_Data;
  wire IO_Ready;
  wire [31:0]IO_Write_Data;
  wire IO_Write_Strobe;
  wire [0:31]LMB_ABus;
  wire LMB_AddrStrobe;
  wire LMB_ReadStrobe;
  wire [0:31]LMB_WriteDBus;
  wire LMB_WriteStrobe;
  wire Rst;
  wire [0:31]Sl_DBus;
  wire Sl_Ready;
  wire NLW_U0_FIT1_Interrupt_UNCONNECTED;
  wire NLW_U0_FIT1_Toggle_UNCONNECTED;
  wire NLW_U0_FIT2_Interrupt_UNCONNECTED;
  wire NLW_U0_FIT2_Toggle_UNCONNECTED;
  wire NLW_U0_FIT3_Interrupt_UNCONNECTED;
  wire NLW_U0_FIT3_Toggle_UNCONNECTED;
  wire NLW_U0_FIT4_Interrupt_UNCONNECTED;
  wire NLW_U0_FIT4_Toggle_UNCONNECTED;
  wire NLW_U0_GPI1_Interrupt_UNCONNECTED;
  wire NLW_U0_GPI2_Interrupt_UNCONNECTED;
  wire NLW_U0_GPI3_Interrupt_UNCONNECTED;
  wire NLW_U0_GPI4_Interrupt_UNCONNECTED;
  wire NLW_U0_INTC_IRQ_UNCONNECTED;
  wire NLW_U0_INTC_IRQ_OUT_UNCONNECTED;
  wire NLW_U0_IO_Read_Strobe_UNCONNECTED;
  wire NLW_U0_PIT1_Interrupt_UNCONNECTED;
  wire NLW_U0_PIT1_Toggle_UNCONNECTED;
  wire NLW_U0_PIT2_Interrupt_UNCONNECTED;
  wire NLW_U0_PIT2_Toggle_UNCONNECTED;
  wire NLW_U0_PIT3_Interrupt_UNCONNECTED;
  wire NLW_U0_PIT3_Toggle_UNCONNECTED;
  wire NLW_U0_PIT4_Interrupt_UNCONNECTED;
  wire NLW_U0_PIT4_Toggle_UNCONNECTED;
  wire NLW_U0_Sl_CE_UNCONNECTED;
  wire NLW_U0_Sl_UE_UNCONNECTED;
  wire NLW_U0_Sl_Wait_UNCONNECTED;
  wire NLW_U0_UART_Interrupt_UNCONNECTED;
  wire NLW_U0_UART_Tx_UNCONNECTED;
  wire [31:0]NLW_U0_GPO1_UNCONNECTED;
  wire [31:0]NLW_U0_GPO2_UNCONNECTED;
  wire [31:0]NLW_U0_GPO3_UNCONNECTED;
  wire [31:0]NLW_U0_GPO4_UNCONNECTED;
  wire [31:0]NLW_U0_INTC_Interrupt_Address_UNCONNECTED;
  wire [31:0]NLW_U0_IO_Address_UNCONNECTED;
  wire [3:0]NLW_U0_IO_Byte_Enable_UNCONNECTED;
  wire [1023:0]NLW_U0_ToVote_UNCONNECTED;

  assign IO_Address[31] = \<const0> ;
  assign IO_Address[30] = \<const0> ;
  assign IO_Address[29:2] = \^IO_Address [29:2];
  assign IO_Address[1] = \<const0> ;
  assign IO_Address[0] = \<const0> ;
  assign IO_Byte_Enable[3] = \<const0> ;
  assign IO_Byte_Enable[2] = \<const0> ;
  assign IO_Byte_Enable[1] = \<const0> ;
  assign IO_Byte_Enable[0] = \<const0> ;
  assign IO_Read_Strobe = \<const0> ;
  assign Sl_CE = \<const0> ;
  assign Sl_UE = \<const0> ;
  assign Sl_Wait = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_AVOID_PRIMITIVES = "0" *) 
  (* C_BASEADDR = "64'b0000000000000000000000000000000010000000000000000000000000000000" *) 
  (* C_FAMILY = "kintexu" *) 
  (* C_FIT1_INTERRUPT = "0" *) 
  (* C_FIT1_No_CLOCKS = "6216" *) 
  (* C_FIT2_INTERRUPT = "0" *) 
  (* C_FIT2_No_CLOCKS = "6216" *) 
  (* C_FIT3_INTERRUPT = "0" *) 
  (* C_FIT3_No_CLOCKS = "6216" *) 
  (* C_FIT4_INTERRUPT = "0" *) 
  (* C_FIT4_No_CLOCKS = "6216" *) 
  (* C_FREQ = "100000000" *) 
  (* C_GPI1_INTERRUPT = "0" *) 
  (* C_GPI1_SIZE = "32" *) 
  (* C_GPI2_INTERRUPT = "0" *) 
  (* C_GPI2_SIZE = "32" *) 
  (* C_GPI3_INTERRUPT = "0" *) 
  (* C_GPI3_SIZE = "32" *) 
  (* C_GPI4_INTERRUPT = "0" *) 
  (* C_GPI4_SIZE = "32" *) 
  (* C_GPO1_INIT = "32'b00000000000000000000000000000000" *) 
  (* C_GPO1_SIZE = "32" *) 
  (* C_GPO2_INIT = "32'b00000000000000000000000000000000" *) 
  (* C_GPO2_SIZE = "32" *) 
  (* C_GPO3_INIT = "32'b00000000000000000000000000000000" *) 
  (* C_GPO3_SIZE = "32" *) 
  (* C_GPO4_INIT = "32'b00000000000000000000000000000000" *) 
  (* C_GPO4_SIZE = "32" *) 
  (* C_HIGHADDR = "64'b0000000000000000000000000000000010000000000000001111111111111111" *) 
  (* C_INSTANCE = "iomodule" *) 
  (* C_INTC_ADDR_WIDTH = "17" *) 
  (* C_INTC_ASYNC_INTR = "16'b1111111111111111" *) 
  (* C_INTC_BASE_VECTORS = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_INTC_HAS_FAST = "1" *) 
  (* C_INTC_INTR_SIZE = "1" *) 
  (* C_INTC_LEVEL_EDGE = "16'b0000000000000000" *) 
  (* C_INTC_NUM_SYNC_FF = "2" *) 
  (* C_INTC_POSITIVE = "16'b1111111111111111" *) 
  (* C_INTC_USE_EXT_INTR = "0" *) 
  (* C_IO_BASEADDR = "64'b0000000000000000000000000000000011000000000000000000000000000000" *) 
  (* C_IO_HIGHADDR = "64'b0000000000000000000000000000000011111111111111111111111111111111" *) 
  (* C_IO_MASK = "64'b0000000000000000000000000000000011000000000000000000000000000000" *) 
  (* C_LMB_AWIDTH = "32" *) 
  (* C_LMB_DWIDTH = "32" *) 
  (* C_LMB_PROTOCOL = "0" *) 
  (* C_MASK = "64'b0000000000000000000000000000000011000000000000000000000000000000" *) 
  (* C_PIT1_INTERRUPT = "0" *) 
  (* C_PIT1_PRESCALER = "0" *) 
  (* C_PIT1_READABLE = "1" *) 
  (* C_PIT1_SIZE = "32" *) 
  (* C_PIT2_INTERRUPT = "0" *) 
  (* C_PIT2_PRESCALER = "0" *) 
  (* C_PIT2_READABLE = "1" *) 
  (* C_PIT2_SIZE = "32" *) 
  (* C_PIT3_INTERRUPT = "0" *) 
  (* C_PIT3_PRESCALER = "0" *) 
  (* C_PIT3_READABLE = "1" *) 
  (* C_PIT3_SIZE = "32" *) 
  (* C_PIT4_INTERRUPT = "0" *) 
  (* C_PIT4_PRESCALER = "0" *) 
  (* C_PIT4_READABLE = "1" *) 
  (* C_PIT4_SIZE = "32" *) 
  (* C_TMR = "0" *) 
  (* C_UART_ASYNC = "0" *) 
  (* C_UART_BAUDRATE = "9600" *) 
  (* C_UART_DATA_BITS = "8" *) 
  (* C_UART_ERROR_INTERRUPT = "0" *) 
  (* C_UART_FREQ = "100000000" *) 
  (* C_UART_NUM_SYNC_FF = "2" *) 
  (* C_UART_ODD_PARITY = "0" *) 
  (* C_UART_PROG_BAUDRATE = "0" *) 
  (* C_UART_RX_INTERRUPT = "0" *) 
  (* C_UART_TX_INTERRUPT = "0" *) 
  (* C_UART_USE_PARITY = "0" *) 
  (* C_USE_CONFIG_RESET = "0" *) 
  (* C_USE_FIT1 = "0" *) 
  (* C_USE_FIT2 = "0" *) 
  (* C_USE_FIT3 = "0" *) 
  (* C_USE_FIT4 = "0" *) 
  (* C_USE_GPI1 = "0" *) 
  (* C_USE_GPI2 = "0" *) 
  (* C_USE_GPI3 = "0" *) 
  (* C_USE_GPI4 = "0" *) 
  (* C_USE_GPO1 = "0" *) 
  (* C_USE_GPO2 = "0" *) 
  (* C_USE_GPO3 = "0" *) 
  (* C_USE_GPO4 = "0" *) 
  (* C_USE_IO_BUS = "1" *) 
  (* C_USE_PIT1 = "0" *) 
  (* C_USE_PIT2 = "0" *) 
  (* C_USE_PIT3 = "0" *) 
  (* C_USE_PIT4 = "0" *) 
  (* C_USE_TMR_DISABLE = "0" *) 
  (* C_USE_UART_RX = "0" *) 
  (* C_USE_UART_TX = "0" *) 
  ddr4_0_iomodule U0
       (.Clk(Clk),
        .Config_Reset(1'b0),
        .FIT1_Interrupt(NLW_U0_FIT1_Interrupt_UNCONNECTED),
        .FIT1_Toggle(NLW_U0_FIT1_Toggle_UNCONNECTED),
        .FIT2_Interrupt(NLW_U0_FIT2_Interrupt_UNCONNECTED),
        .FIT2_Toggle(NLW_U0_FIT2_Toggle_UNCONNECTED),
        .FIT3_Interrupt(NLW_U0_FIT3_Interrupt_UNCONNECTED),
        .FIT3_Toggle(NLW_U0_FIT3_Toggle_UNCONNECTED),
        .FIT4_Interrupt(NLW_U0_FIT4_Interrupt_UNCONNECTED),
        .FIT4_Toggle(NLW_U0_FIT4_Toggle_UNCONNECTED),
        .FromAVote({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .FromBVote({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GPI1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GPI1_Interrupt(NLW_U0_GPI1_Interrupt_UNCONNECTED),
        .GPI2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GPI2_Interrupt(NLW_U0_GPI2_Interrupt_UNCONNECTED),
        .GPI3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GPI3_Interrupt(NLW_U0_GPI3_Interrupt_UNCONNECTED),
        .GPI4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .GPI4_Interrupt(NLW_U0_GPI4_Interrupt_UNCONNECTED),
        .GPO1(NLW_U0_GPO1_UNCONNECTED[31:0]),
        .GPO2(NLW_U0_GPO2_UNCONNECTED[31:0]),
        .GPO3(NLW_U0_GPO3_UNCONNECTED[31:0]),
        .GPO4(NLW_U0_GPO4_UNCONNECTED[31:0]),
        .INTC_IRQ(NLW_U0_INTC_IRQ_UNCONNECTED),
        .INTC_IRQ_OUT(NLW_U0_INTC_IRQ_OUT_UNCONNECTED),
        .INTC_Interrupt(1'b0),
        .INTC_Interrupt_Address(NLW_U0_INTC_Interrupt_Address_UNCONNECTED[31:0]),
        .INTC_Processor_Ack({1'b0,1'b0}),
        .IO_Addr_Strobe(IO_Addr_Strobe),
        .IO_Address({NLW_U0_IO_Address_UNCONNECTED[31:30],\^IO_Address ,NLW_U0_IO_Address_UNCONNECTED[1:0]}),
        .IO_Byte_Enable(NLW_U0_IO_Byte_Enable_UNCONNECTED[3:0]),
        .IO_CE(1'b0),
        .IO_Read_Data(IO_Read_Data),
        .IO_Read_Strobe(NLW_U0_IO_Read_Strobe_UNCONNECTED),
        .IO_Ready(IO_Ready),
        .IO_UE(1'b0),
        .IO_Write_Data(IO_Write_Data),
        .IO_Write_Strobe(IO_Write_Strobe),
        .LMB_ABus({LMB_ABus[0:29],1'b0,1'b0}),
        .LMB_AddrStrobe(LMB_AddrStrobe),
        .LMB_BE({1'b0,1'b0,1'b0,1'b0}),
        .LMB_ReadStrobe(LMB_ReadStrobe),
        .LMB_WriteDBus(LMB_WriteDBus),
        .LMB_WriteStrobe(LMB_WriteStrobe),
        .PIT1_Enable(1'b0),
        .PIT1_Interrupt(NLW_U0_PIT1_Interrupt_UNCONNECTED),
        .PIT1_Toggle(NLW_U0_PIT1_Toggle_UNCONNECTED),
        .PIT2_Enable(1'b0),
        .PIT2_Interrupt(NLW_U0_PIT2_Interrupt_UNCONNECTED),
        .PIT2_Toggle(NLW_U0_PIT2_Toggle_UNCONNECTED),
        .PIT3_Enable(1'b0),
        .PIT3_Interrupt(NLW_U0_PIT3_Interrupt_UNCONNECTED),
        .PIT3_Toggle(NLW_U0_PIT3_Toggle_UNCONNECTED),
        .PIT4_Enable(1'b0),
        .PIT4_Interrupt(NLW_U0_PIT4_Interrupt_UNCONNECTED),
        .PIT4_Toggle(NLW_U0_PIT4_Toggle_UNCONNECTED),
        .Rst(Rst),
        .Sl_CE(NLW_U0_Sl_CE_UNCONNECTED),
        .Sl_DBus(Sl_DBus),
        .Sl_Ready(Sl_Ready),
        .Sl_UE(NLW_U0_Sl_UE_UNCONNECTED),
        .Sl_Wait(NLW_U0_Sl_Wait_UNCONNECTED),
        .TMR_Disable(1'b0),
        .TMR_Rst(1'b0),
        .ToVote(NLW_U0_ToVote_UNCONNECTED[1023:0]),
        .UART_Clk(1'b0),
        .UART_Interrupt(NLW_U0_UART_Interrupt_UNCONNECTED),
        .UART_Rst(1'b0),
        .UART_Rx(1'b0),
        .UART_Tx(NLW_U0_UART_Tx_UNCONNECTED));
endmodule

(* CHECK_LICENSE_TYPE = "bd_9054_lmb_bram_I_0,blk_mem_gen_v8_4_5,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "bd_9054_lmb_bram_I_0" *) 
(* X_CORE_INFO = "blk_mem_gen_v8_4_5,Vivado 2022.2" *) 
module ddr4_0_bd_9054_lmb_bram_I_0
   (clka,
    rsta,
    ena,
    wea,
    addra,
    dina,
    douta,
    clkb,
    rstb,
    enb,
    web,
    addrb,
    dinb,
    doutb,
    rsta_busy,
    rstb_busy);
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1" *) input clka;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) input rsta;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [3:0]wea;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [31:0]addra;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [31:0]dina;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 65536, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1" *) input clkb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) input rstb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) input enb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) input [3:0]web;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [31:0]addrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) input [31:0]dinb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [31:0]doutb;
  output rsta_busy;
  output rstb_busy;

  wire \<const0> ;
  wire [31:0]addra;
  wire [31:0]addrb;
  wire clka;
  wire clkb;
  wire [31:0]dina;
  wire [31:0]douta;
  wire [31:0]doutb;
  wire ena;
  wire enb;
  wire [3:0]wea;
  wire NLW_U0_dbiterr_UNCONNECTED;
  wire NLW_U0_rsta_busy_UNCONNECTED;
  wire NLW_U0_rstb_busy_UNCONNECTED;
  wire NLW_U0_s_axi_arready_UNCONNECTED;
  wire NLW_U0_s_axi_awready_UNCONNECTED;
  wire NLW_U0_s_axi_bvalid_UNCONNECTED;
  wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
  wire NLW_U0_s_axi_rlast_UNCONNECTED;
  wire NLW_U0_s_axi_rvalid_UNCONNECTED;
  wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
  wire NLW_U0_s_axi_wready_UNCONNECTED;
  wire NLW_U0_sbiterr_UNCONNECTED;
  wire [31:0]NLW_U0_rdaddrecc_UNCONNECTED;
  wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
  wire [31:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
  wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED;
  wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;

  assign rsta_busy = \<const0> ;
  assign rstb_busy = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_ADDRA_WIDTH = "32" *) 
  (* C_ADDRB_WIDTH = "32" *) 
  (* C_ALGORITHM = "1" *) 
  (* C_AXI_ID_WIDTH = "4" *) 
  (* C_AXI_SLAVE_TYPE = "0" *) 
  (* C_AXI_TYPE = "1" *) 
  (* C_BYTE_SIZE = "8" *) 
  (* C_COMMON_CLK = "0" *) 
  (* C_COUNT_18K_BRAM = "0" *) 
  (* C_COUNT_36K_BRAM = "16" *) 
  (* C_CTRL_ECC_ALGO = "NONE" *) 
  (* C_DEFAULT_DATA = "0" *) 
  (* C_DISABLE_WARN_BHV_COLL = "0" *) 
  (* C_DISABLE_WARN_BHV_RANGE = "0" *) 
  (* C_ELABORATION_DIR = "./" *) 
  (* C_ENABLE_32BIT_ADDRESS = "1" *) 
  (* C_EN_DEEPSLEEP_PIN = "0" *) 
  (* C_EN_ECC_PIPE = "0" *) 
  (* C_EN_RDADDRA_CHG = "0" *) 
  (* C_EN_RDADDRB_CHG = "0" *) 
  (* C_EN_SAFETY_CKT = "1" *) 
  (* C_EN_SHUTDOWN_PIN = "0" *) 
  (* C_EN_SLEEP_PIN = "0" *) 
  (* C_EST_POWER_SUMMARY = "Estimated Power for IP     :     5.015361 mW" *) 
  (* C_FAMILY = "kintexu" *) 
  (* C_HAS_AXI_ID = "0" *) 
  (* C_HAS_ENA = "1" *) 
  (* C_HAS_ENB = "1" *) 
  (* C_HAS_INJECTERR = "0" *) 
  (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) 
  (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) 
  (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) 
  (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) 
  (* C_HAS_REGCEA = "0" *) 
  (* C_HAS_REGCEB = "0" *) 
  (* C_HAS_RSTA = "1" *) 
  (* C_HAS_RSTB = "1" *) 
  (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) 
  (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) 
  (* C_INITA_VAL = "0" *) 
  (* C_INITB_VAL = "0" *) 
  (* C_INIT_FILE = "bd_9054_lmb_bram_I_0.mem" *) 
  (* C_INIT_FILE_NAME = "no_coe_file_loaded" *) 
  (* C_INTERFACE_TYPE = "0" *) 
  (* C_LOAD_INIT_FILE = "0" *) 
  (* C_MEM_TYPE = "2" *) 
  (* C_MUX_PIPELINE_STAGES = "0" *) 
  (* C_PRIM_TYPE = "1" *) 
  (* C_READ_DEPTH_A = "16384" *) 
  (* C_READ_DEPTH_B = "16384" *) 
  (* C_READ_LATENCY_A = "1" *) 
  (* C_READ_LATENCY_B = "1" *) 
  (* C_READ_WIDTH_A = "32" *) 
  (* C_READ_WIDTH_B = "32" *) 
  (* C_RSTRAM_A = "0" *) 
  (* C_RSTRAM_B = "0" *) 
  (* C_RST_PRIORITY_A = "CE" *) 
  (* C_RST_PRIORITY_B = "CE" *) 
  (* C_SIM_COLLISION_CHECK = "ALL" *) 
  (* C_USE_BRAM_BLOCK = "1" *) 
  (* C_USE_BYTE_WEA = "1" *) 
  (* C_USE_BYTE_WEB = "1" *) 
  (* C_USE_DEFAULT_DATA = "0" *) 
  (* C_USE_ECC = "0" *) 
  (* C_USE_SOFTECC = "0" *) 
  (* C_USE_URAM = "0" *) 
  (* C_WEA_WIDTH = "4" *) 
  (* C_WEB_WIDTH = "4" *) 
  (* C_WRITE_DEPTH_A = "16384" *) 
  (* C_WRITE_DEPTH_B = "16384" *) 
  (* C_WRITE_MODE_A = "WRITE_FIRST" *) 
  (* C_WRITE_MODE_B = "WRITE_FIRST" *) 
  (* C_WRITE_WIDTH_A = "32" *) 
  (* C_WRITE_WIDTH_B = "32" *) 
  (* C_XDEVICEFAMILY = "kintexu" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* is_du_within_envelope = "true" *) 
  ddr4_0_blk_mem_gen_v8_4_5 U0
       (.addra({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,addra[15:2],1'b0,1'b0}),
        .addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,addrb[15:2],1'b0,1'b0}),
        .clka(clka),
        .clkb(clkb),
        .dbiterr(NLW_U0_dbiterr_UNCONNECTED),
        .deepsleep(1'b0),
        .dina(dina),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(douta),
        .doutb(doutb),
        .eccpipece(1'b0),
        .ena(ena),
        .enb(enb),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[31:0]),
        .regcea(1'b0),
        .regceb(1'b0),
        .rsta(1'b0),
        .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
        .rstb(1'b0),
        .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
        .s_aclk(1'b0),
        .s_aresetn(1'b0),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
        .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
        .s_axi_injectdbiterr(1'b0),
        .s_axi_injectsbiterr(1'b0),
        .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[31:0]),
        .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]),
        .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
        .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
        .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wvalid(1'b0),
        .sbiterr(NLW_U0_sbiterr_UNCONNECTED),
        .shutdown(1'b0),
        .sleep(1'b0),
        .wea(wea),
        .web({1'b0,1'b0,1'b0,1'b0}));
endmodule

(* CHECK_LICENSE_TYPE = "bd_9054_microblaze_I_0,MicroBlaze,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "bd_9054_microblaze_I_0" *) 
(* X_CORE_INFO = "MicroBlaze,Vivado 2022.2" *) 
module ddr4_0_bd_9054_microblaze_I_0
   (Clk,
    Reset,
    Interrupt,
    Interrupt_Address,
    Interrupt_Ack,
    Instr_Addr,
    Instr,
    IFetch,
    I_AS,
    IReady,
    IWAIT,
    ICE,
    IUE,
    Data_Addr,
    Data_Read,
    Data_Write,
    D_AS,
    Read_Strobe,
    Write_Strobe,
    DReady,
    DWait,
    DCE,
    DUE,
    Byte_Enable,
    Trace_Instruction,
    Trace_Valid_Instr,
    Trace_PC,
    Trace_Reg_Write,
    Trace_Reg_Addr,
    Trace_MSR_Reg,
    Trace_PID_Reg,
    Trace_New_Reg_Value,
    Trace_Exception_Taken,
    Trace_Exception_Kind,
    Trace_Jump_Taken,
    Trace_Delay_Slot,
    Trace_Data_Address,
    Trace_Data_Write_Value,
    Trace_Data_Byte_Enable,
    Trace_Data_Access,
    Trace_Data_Read,
    Trace_Data_Write,
    Trace_DCache_Req,
    Trace_DCache_Hit,
    Trace_DCache_Rdy,
    Trace_DCache_Read,
    Trace_ICache_Req,
    Trace_ICache_Hit,
    Trace_ICache_Rdy,
    Trace_OF_PipeRun,
    Trace_EX_PipeRun,
    Trace_MEM_PipeRun,
    Trace_MB_Halted,
    Trace_Jump_Hit);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC, ASSOCIATED_RESET Reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_9054_Clk, INSERT_VIP 0" *) input Clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RESET, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) input Reset;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, LOW_LATENCY 0" *) input Interrupt;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS" *) input [0:31]Interrupt_Address;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK" *) output [0:1]Interrupt_Ack;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 ILMB ABUS" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ILMB, ADDR_WIDTH 32, DATA_WIDTH 32, PROTOCOL STANDARD, READ_WRITE_MODE READ_ONLY" *) output [0:31]Instr_Addr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 ILMB READDBUS" *) input [0:31]Instr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 ILMB READSTROBE" *) output IFetch;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE" *) output I_AS;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 ILMB READY" *) input IReady;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 ILMB WAIT" *) input IWAIT;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 ILMB CE" *) input ICE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 ILMB UE" *) input IUE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 DLMB ABUS" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DLMB, ADDR_WIDTH 32, DATA_WIDTH 32, PROTOCOL STANDARD, READ_WRITE_MODE READ_WRITE" *) output [0:31]Data_Addr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 DLMB READDBUS" *) input [0:31]Data_Read;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS" *) output [0:31]Data_Write;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE" *) output D_AS;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 DLMB READSTROBE" *) output Read_Strobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE" *) output Write_Strobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 DLMB READY" *) input DReady;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 DLMB WAIT" *) input DWait;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 DLMB CE" *) input DCE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 DLMB UE" *) input DUE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 DLMB BE" *) output [0:3]Byte_Enable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION" *) output [0:31]Trace_Instruction;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR" *) output Trace_Valid_Instr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE PC" *) output [0:31]Trace_PC;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE" *) output Trace_Reg_Write;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR" *) output [0:4]Trace_Reg_Addr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG" *) output [0:14]Trace_MSR_Reg;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE PID_REG" *) output [0:7]Trace_PID_Reg;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE" *) output [0:31]Trace_New_Reg_Value;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN" *) output Trace_Exception_Taken;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND" *) output [0:4]Trace_Exception_Kind;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN" *) output Trace_Jump_Taken;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT" *) output Trace_Delay_Slot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS" *) output [0:31]Trace_Data_Address;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE" *) output [0:31]Trace_Data_Write_Value;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE" *) output [0:3]Trace_Data_Byte_Enable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS" *) output Trace_Data_Access;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ" *) output Trace_Data_Read;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE" *) output Trace_Data_Write;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ" *) output Trace_DCache_Req;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT" *) output Trace_DCache_Hit;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY" *) output Trace_DCache_Rdy;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ" *) output Trace_DCache_Read;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ" *) output Trace_ICache_Req;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT" *) output Trace_ICache_Hit;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY" *) output Trace_ICache_Rdy;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN" *) output Trace_OF_PipeRun;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN" *) output Trace_EX_PipeRun;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN" *) output Trace_MEM_PipeRun;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED" *) output Trace_MB_Halted;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT" *) output Trace_Jump_Hit;

  wire \<const0> ;
  wire [0:3]Byte_Enable;
  wire Clk;
  wire DReady;
  wire D_AS;
  wire [0:29]\^Data_Addr ;
  wire [0:31]Data_Read;
  wire [0:31]Data_Write;
  wire IReady;
  wire I_AS;
  wire [0:31]Instr;
  wire [0:29]\^Instr_Addr ;
  wire Read_Strobe;
  wire Reset;
  wire Write_Strobe;
  wire NLW_U0_Dbg_ARREADY_UNCONNECTED;
  wire NLW_U0_Dbg_AWREADY_UNCONNECTED;
  wire NLW_U0_Dbg_BVALID_UNCONNECTED;
  wire NLW_U0_Dbg_Continue_UNCONNECTED;
  wire NLW_U0_Dbg_Intr_UNCONNECTED;
  wire NLW_U0_Dbg_RVALID_UNCONNECTED;
  wire NLW_U0_Dbg_TDO_UNCONNECTED;
  wire NLW_U0_Dbg_Trace_Valid_UNCONNECTED;
  wire NLW_U0_Dbg_WREADY_UNCONNECTED;
  wire NLW_U0_Dbg_Wakeup_UNCONNECTED;
  wire NLW_U0_Hibernate_UNCONNECTED;
  wire NLW_U0_IFetch_UNCONNECTED;
  wire NLW_U0_M0_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M0_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M10_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M10_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M11_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M11_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M12_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M12_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M13_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M13_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M14_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M14_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M15_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M15_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M1_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M1_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M2_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M2_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M3_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M3_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M4_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M4_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M5_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M5_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M6_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M6_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M7_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M7_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M8_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M8_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M9_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M9_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_MB_Error_UNCONNECTED;
  wire NLW_U0_MB_Halted_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_ACREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_ARLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_ARVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_AWLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_AWVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_BREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_CDLAST_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_CDVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_CRVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_RACK_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_RREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_WACK_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_WLAST_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_WVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_DP_ARLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_DP_ARVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_DP_AWLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_DP_AWVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_DP_BREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_DP_RREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_DP_WLAST_UNCONNECTED;
  wire NLW_U0_M_AXI_DP_WVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_ACREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_ARLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_ARVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_AWLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_AWVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_BREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_CDLAST_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_CDVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_CRVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_RACK_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_RREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_WACK_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_WLAST_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_WVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_ARLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_ARVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_AWLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_AWVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_BREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_RREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_WLAST_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_WVALID_UNCONNECTED;
  wire NLW_U0_Pause_Ack_UNCONNECTED;
  wire NLW_U0_S0_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S10_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S11_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S12_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S13_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S14_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S15_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S1_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S2_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S3_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S4_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S5_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S6_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S7_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S8_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S9_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_Sleep_UNCONNECTED;
  wire NLW_U0_Suspend_UNCONNECTED;
  wire NLW_U0_Trace_DCache_Hit_UNCONNECTED;
  wire NLW_U0_Trace_DCache_Rdy_UNCONNECTED;
  wire NLW_U0_Trace_DCache_Read_UNCONNECTED;
  wire NLW_U0_Trace_DCache_Req_UNCONNECTED;
  wire NLW_U0_Trace_Data_Access_UNCONNECTED;
  wire NLW_U0_Trace_Data_Read_UNCONNECTED;
  wire NLW_U0_Trace_Data_Write_UNCONNECTED;
  wire NLW_U0_Trace_Delay_Slot_UNCONNECTED;
  wire NLW_U0_Trace_EX_PipeRun_UNCONNECTED;
  wire NLW_U0_Trace_Exception_Taken_UNCONNECTED;
  wire NLW_U0_Trace_ICache_Hit_UNCONNECTED;
  wire NLW_U0_Trace_ICache_Rdy_UNCONNECTED;
  wire NLW_U0_Trace_ICache_Req_UNCONNECTED;
  wire NLW_U0_Trace_Jump_Hit_UNCONNECTED;
  wire NLW_U0_Trace_Jump_Taken_UNCONNECTED;
  wire NLW_U0_Trace_MB_Halted_UNCONNECTED;
  wire NLW_U0_Trace_MEM_PipeRun_UNCONNECTED;
  wire NLW_U0_Trace_OF_PipeRun_UNCONNECTED;
  wire NLW_U0_Trace_Reg_Write_UNCONNECTED;
  wire NLW_U0_Trace_Valid_Instr_UNCONNECTED;
  wire [30:31]NLW_U0_Data_Addr_UNCONNECTED;
  wire [1:0]NLW_U0_Dbg_BRESP_UNCONNECTED;
  wire [31:0]NLW_U0_Dbg_RDATA_UNCONNECTED;
  wire [1:0]NLW_U0_Dbg_RRESP_UNCONNECTED;
  wire [0:35]NLW_U0_Dbg_Trace_Data_UNCONNECTED;
  wire [0:7]NLW_U0_Dbg_Trig_Ack_Out_UNCONNECTED;
  wire [0:7]NLW_U0_Dbg_Trig_In_UNCONNECTED;
  wire [1:31]NLW_U0_Instr_Addr_UNCONNECTED;
  wire [0:1]NLW_U0_Interrupt_Ack_UNCONNECTED;
  wire [0:4095]NLW_U0_LOCKSTEP_Master_Out_UNCONNECTED;
  wire [0:4095]NLW_U0_LOCKSTEP_Out_UNCONNECTED;
  wire [31:0]NLW_U0_M0_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M10_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M11_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M12_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M13_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M14_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M15_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M1_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M2_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M3_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M4_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M5_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M6_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M7_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M8_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M9_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_DC_ARADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DC_ARBAR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DC_ARBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DC_ARCACHE_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DC_ARDOMAIN_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_DC_ARID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_DC_ARLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DC_ARPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DC_ARQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DC_ARSIZE_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DC_ARSNOOP_UNCONNECTED;
  wire [4:0]NLW_U0_M_AXI_DC_ARUSER_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_DC_AWADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DC_AWBAR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DC_AWBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DC_AWCACHE_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DC_AWDOMAIN_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_DC_AWID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_DC_AWLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DC_AWPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DC_AWQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DC_AWSIZE_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DC_AWSNOOP_UNCONNECTED;
  wire [4:0]NLW_U0_M_AXI_DC_AWUSER_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_DC_CDDATA_UNCONNECTED;
  wire [4:0]NLW_U0_M_AXI_DC_CRRESP_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_DC_WDATA_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DC_WSTRB_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_DC_WUSER_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_DP_ARADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DP_ARBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DP_ARCACHE_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_DP_ARID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_DP_ARLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DP_ARPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DP_ARQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DP_ARSIZE_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_DP_AWADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DP_AWBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DP_AWCACHE_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_DP_AWID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_DP_AWLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DP_AWPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DP_AWQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DP_AWSIZE_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_DP_WDATA_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DP_WSTRB_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IC_ARADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IC_ARBAR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IC_ARBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IC_ARCACHE_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IC_ARDOMAIN_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_IC_ARID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_IC_ARLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IC_ARPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IC_ARQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IC_ARSIZE_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IC_ARSNOOP_UNCONNECTED;
  wire [4:0]NLW_U0_M_AXI_IC_ARUSER_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IC_AWADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IC_AWBAR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IC_AWBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IC_AWCACHE_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IC_AWDOMAIN_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_IC_AWID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_IC_AWLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IC_AWPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IC_AWQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IC_AWSIZE_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IC_AWSNOOP_UNCONNECTED;
  wire [4:0]NLW_U0_M_AXI_IC_AWUSER_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IC_CDDATA_UNCONNECTED;
  wire [4:0]NLW_U0_M_AXI_IC_CRRESP_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IC_WDATA_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IC_WSTRB_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_IC_WUSER_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IP_ARADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IP_ARBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IP_ARCACHE_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_IP_ARID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_IP_ARLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IP_ARPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IP_ARQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IP_ARSIZE_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IP_AWADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IP_AWBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IP_AWCACHE_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_IP_AWID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_IP_AWLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IP_AWPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IP_AWQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IP_AWSIZE_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IP_WDATA_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IP_WSTRB_UNCONNECTED;
  wire [255:0]NLW_U0_RAM_DCache_Data_From_UNCONNECTED;
  wire [255:0]NLW_U0_RAM_DCache_Tag_From_UNCONNECTED;
  wire [255:0]NLW_U0_RAM_From_UNCONNECTED;
  wire [255:0]NLW_U0_RAM_ICache_Data_From_UNCONNECTED;
  wire [255:0]NLW_U0_RAM_ICache_Tag_From_UNCONNECTED;
  wire [0:31]NLW_U0_Trace_Data_Address_UNCONNECTED;
  wire [0:3]NLW_U0_Trace_Data_Byte_Enable_UNCONNECTED;
  wire [0:31]NLW_U0_Trace_Data_Write_Value_UNCONNECTED;
  wire [0:4]NLW_U0_Trace_Exception_Kind_UNCONNECTED;
  wire [0:31]NLW_U0_Trace_Instruction_UNCONNECTED;
  wire [0:14]NLW_U0_Trace_MSR_Reg_UNCONNECTED;
  wire [0:31]NLW_U0_Trace_New_Reg_Value_UNCONNECTED;
  wire [0:31]NLW_U0_Trace_PC_UNCONNECTED;
  wire [0:7]NLW_U0_Trace_PID_Reg_UNCONNECTED;
  wire [0:4]NLW_U0_Trace_Reg_Addr_UNCONNECTED;

  assign Data_Addr[0:29] = \^Data_Addr [0:29];
  assign Data_Addr[30] = \<const0> ;
  assign Data_Addr[31] = \<const0> ;
  assign IFetch = \<const0> ;
  assign Instr_Addr[0] = \^Instr_Addr [0];
  assign Instr_Addr[1] = \<const0> ;
  assign Instr_Addr[2] = \<const0> ;
  assign Instr_Addr[3] = \<const0> ;
  assign Instr_Addr[4] = \<const0> ;
  assign Instr_Addr[5] = \<const0> ;
  assign Instr_Addr[6] = \<const0> ;
  assign Instr_Addr[7] = \<const0> ;
  assign Instr_Addr[8] = \<const0> ;
  assign Instr_Addr[9] = \<const0> ;
  assign Instr_Addr[10] = \<const0> ;
  assign Instr_Addr[11] = \<const0> ;
  assign Instr_Addr[12] = \<const0> ;
  assign Instr_Addr[13] = \<const0> ;
  assign Instr_Addr[14] = \<const0> ;
  assign Instr_Addr[15:29] = \^Instr_Addr [15:29];
  assign Instr_Addr[30] = \<const0> ;
  assign Instr_Addr[31] = \<const0> ;
  assign Interrupt_Ack[0] = \<const0> ;
  assign Interrupt_Ack[1] = \<const0> ;
  assign Trace_DCache_Hit = \<const0> ;
  assign Trace_DCache_Rdy = \<const0> ;
  assign Trace_DCache_Read = \<const0> ;
  assign Trace_DCache_Req = \<const0> ;
  assign Trace_Data_Access = \<const0> ;
  assign Trace_Data_Address[0] = \<const0> ;
  assign Trace_Data_Address[1] = \<const0> ;
  assign Trace_Data_Address[2] = \<const0> ;
  assign Trace_Data_Address[3] = \<const0> ;
  assign Trace_Data_Address[4] = \<const0> ;
  assign Trace_Data_Address[5] = \<const0> ;
  assign Trace_Data_Address[6] = \<const0> ;
  assign Trace_Data_Address[7] = \<const0> ;
  assign Trace_Data_Address[8] = \<const0> ;
  assign Trace_Data_Address[9] = \<const0> ;
  assign Trace_Data_Address[10] = \<const0> ;
  assign Trace_Data_Address[11] = \<const0> ;
  assign Trace_Data_Address[12] = \<const0> ;
  assign Trace_Data_Address[13] = \<const0> ;
  assign Trace_Data_Address[14] = \<const0> ;
  assign Trace_Data_Address[15] = \<const0> ;
  assign Trace_Data_Address[16] = \<const0> ;
  assign Trace_Data_Address[17] = \<const0> ;
  assign Trace_Data_Address[18] = \<const0> ;
  assign Trace_Data_Address[19] = \<const0> ;
  assign Trace_Data_Address[20] = \<const0> ;
  assign Trace_Data_Address[21] = \<const0> ;
  assign Trace_Data_Address[22] = \<const0> ;
  assign Trace_Data_Address[23] = \<const0> ;
  assign Trace_Data_Address[24] = \<const0> ;
  assign Trace_Data_Address[25] = \<const0> ;
  assign Trace_Data_Address[26] = \<const0> ;
  assign Trace_Data_Address[27] = \<const0> ;
  assign Trace_Data_Address[28] = \<const0> ;
  assign Trace_Data_Address[29] = \<const0> ;
  assign Trace_Data_Address[30] = \<const0> ;
  assign Trace_Data_Address[31] = \<const0> ;
  assign Trace_Data_Byte_Enable[0] = \<const0> ;
  assign Trace_Data_Byte_Enable[1] = \<const0> ;
  assign Trace_Data_Byte_Enable[2] = \<const0> ;
  assign Trace_Data_Byte_Enable[3] = \<const0> ;
  assign Trace_Data_Read = \<const0> ;
  assign Trace_Data_Write = \<const0> ;
  assign Trace_Data_Write_Value[0] = \<const0> ;
  assign Trace_Data_Write_Value[1] = \<const0> ;
  assign Trace_Data_Write_Value[2] = \<const0> ;
  assign Trace_Data_Write_Value[3] = \<const0> ;
  assign Trace_Data_Write_Value[4] = \<const0> ;
  assign Trace_Data_Write_Value[5] = \<const0> ;
  assign Trace_Data_Write_Value[6] = \<const0> ;
  assign Trace_Data_Write_Value[7] = \<const0> ;
  assign Trace_Data_Write_Value[8] = \<const0> ;
  assign Trace_Data_Write_Value[9] = \<const0> ;
  assign Trace_Data_Write_Value[10] = \<const0> ;
  assign Trace_Data_Write_Value[11] = \<const0> ;
  assign Trace_Data_Write_Value[12] = \<const0> ;
  assign Trace_Data_Write_Value[13] = \<const0> ;
  assign Trace_Data_Write_Value[14] = \<const0> ;
  assign Trace_Data_Write_Value[15] = \<const0> ;
  assign Trace_Data_Write_Value[16] = \<const0> ;
  assign Trace_Data_Write_Value[17] = \<const0> ;
  assign Trace_Data_Write_Value[18] = \<const0> ;
  assign Trace_Data_Write_Value[19] = \<const0> ;
  assign Trace_Data_Write_Value[20] = \<const0> ;
  assign Trace_Data_Write_Value[21] = \<const0> ;
  assign Trace_Data_Write_Value[22] = \<const0> ;
  assign Trace_Data_Write_Value[23] = \<const0> ;
  assign Trace_Data_Write_Value[24] = \<const0> ;
  assign Trace_Data_Write_Value[25] = \<const0> ;
  assign Trace_Data_Write_Value[26] = \<const0> ;
  assign Trace_Data_Write_Value[27] = \<const0> ;
  assign Trace_Data_Write_Value[28] = \<const0> ;
  assign Trace_Data_Write_Value[29] = \<const0> ;
  assign Trace_Data_Write_Value[30] = \<const0> ;
  assign Trace_Data_Write_Value[31] = \<const0> ;
  assign Trace_Delay_Slot = \<const0> ;
  assign Trace_EX_PipeRun = \<const0> ;
  assign Trace_Exception_Kind[0] = \<const0> ;
  assign Trace_Exception_Kind[1] = \<const0> ;
  assign Trace_Exception_Kind[2] = \<const0> ;
  assign Trace_Exception_Kind[3] = \<const0> ;
  assign Trace_Exception_Kind[4] = \<const0> ;
  assign Trace_Exception_Taken = \<const0> ;
  assign Trace_ICache_Hit = \<const0> ;
  assign Trace_ICache_Rdy = \<const0> ;
  assign Trace_ICache_Req = \<const0> ;
  assign Trace_Instruction[0] = \<const0> ;
  assign Trace_Instruction[1] = \<const0> ;
  assign Trace_Instruction[2] = \<const0> ;
  assign Trace_Instruction[3] = \<const0> ;
  assign Trace_Instruction[4] = \<const0> ;
  assign Trace_Instruction[5] = \<const0> ;
  assign Trace_Instruction[6] = \<const0> ;
  assign Trace_Instruction[7] = \<const0> ;
  assign Trace_Instruction[8] = \<const0> ;
  assign Trace_Instruction[9] = \<const0> ;
  assign Trace_Instruction[10] = \<const0> ;
  assign Trace_Instruction[11] = \<const0> ;
  assign Trace_Instruction[12] = \<const0> ;
  assign Trace_Instruction[13] = \<const0> ;
  assign Trace_Instruction[14] = \<const0> ;
  assign Trace_Instruction[15] = \<const0> ;
  assign Trace_Instruction[16] = \<const0> ;
  assign Trace_Instruction[17] = \<const0> ;
  assign Trace_Instruction[18] = \<const0> ;
  assign Trace_Instruction[19] = \<const0> ;
  assign Trace_Instruction[20] = \<const0> ;
  assign Trace_Instruction[21] = \<const0> ;
  assign Trace_Instruction[22] = \<const0> ;
  assign Trace_Instruction[23] = \<const0> ;
  assign Trace_Instruction[24] = \<const0> ;
  assign Trace_Instruction[25] = \<const0> ;
  assign Trace_Instruction[26] = \<const0> ;
  assign Trace_Instruction[27] = \<const0> ;
  assign Trace_Instruction[28] = \<const0> ;
  assign Trace_Instruction[29] = \<const0> ;
  assign Trace_Instruction[30] = \<const0> ;
  assign Trace_Instruction[31] = \<const0> ;
  assign Trace_Jump_Hit = \<const0> ;
  assign Trace_Jump_Taken = \<const0> ;
  assign Trace_MB_Halted = \<const0> ;
  assign Trace_MEM_PipeRun = \<const0> ;
  assign Trace_MSR_Reg[0] = \<const0> ;
  assign Trace_MSR_Reg[1] = \<const0> ;
  assign Trace_MSR_Reg[2] = \<const0> ;
  assign Trace_MSR_Reg[3] = \<const0> ;
  assign Trace_MSR_Reg[4] = \<const0> ;
  assign Trace_MSR_Reg[5] = \<const0> ;
  assign Trace_MSR_Reg[6] = \<const0> ;
  assign Trace_MSR_Reg[7] = \<const0> ;
  assign Trace_MSR_Reg[8] = \<const0> ;
  assign Trace_MSR_Reg[9] = \<const0> ;
  assign Trace_MSR_Reg[10] = \<const0> ;
  assign Trace_MSR_Reg[11] = \<const0> ;
  assign Trace_MSR_Reg[12] = \<const0> ;
  assign Trace_MSR_Reg[13] = \<const0> ;
  assign Trace_MSR_Reg[14] = \<const0> ;
  assign Trace_New_Reg_Value[0] = \<const0> ;
  assign Trace_New_Reg_Value[1] = \<const0> ;
  assign Trace_New_Reg_Value[2] = \<const0> ;
  assign Trace_New_Reg_Value[3] = \<const0> ;
  assign Trace_New_Reg_Value[4] = \<const0> ;
  assign Trace_New_Reg_Value[5] = \<const0> ;
  assign Trace_New_Reg_Value[6] = \<const0> ;
  assign Trace_New_Reg_Value[7] = \<const0> ;
  assign Trace_New_Reg_Value[8] = \<const0> ;
  assign Trace_New_Reg_Value[9] = \<const0> ;
  assign Trace_New_Reg_Value[10] = \<const0> ;
  assign Trace_New_Reg_Value[11] = \<const0> ;
  assign Trace_New_Reg_Value[12] = \<const0> ;
  assign Trace_New_Reg_Value[13] = \<const0> ;
  assign Trace_New_Reg_Value[14] = \<const0> ;
  assign Trace_New_Reg_Value[15] = \<const0> ;
  assign Trace_New_Reg_Value[16] = \<const0> ;
  assign Trace_New_Reg_Value[17] = \<const0> ;
  assign Trace_New_Reg_Value[18] = \<const0> ;
  assign Trace_New_Reg_Value[19] = \<const0> ;
  assign Trace_New_Reg_Value[20] = \<const0> ;
  assign Trace_New_Reg_Value[21] = \<const0> ;
  assign Trace_New_Reg_Value[22] = \<const0> ;
  assign Trace_New_Reg_Value[23] = \<const0> ;
  assign Trace_New_Reg_Value[24] = \<const0> ;
  assign Trace_New_Reg_Value[25] = \<const0> ;
  assign Trace_New_Reg_Value[26] = \<const0> ;
  assign Trace_New_Reg_Value[27] = \<const0> ;
  assign Trace_New_Reg_Value[28] = \<const0> ;
  assign Trace_New_Reg_Value[29] = \<const0> ;
  assign Trace_New_Reg_Value[30] = \<const0> ;
  assign Trace_New_Reg_Value[31] = \<const0> ;
  assign Trace_OF_PipeRun = \<const0> ;
  assign Trace_PC[0] = \<const0> ;
  assign Trace_PC[1] = \<const0> ;
  assign Trace_PC[2] = \<const0> ;
  assign Trace_PC[3] = \<const0> ;
  assign Trace_PC[4] = \<const0> ;
  assign Trace_PC[5] = \<const0> ;
  assign Trace_PC[6] = \<const0> ;
  assign Trace_PC[7] = \<const0> ;
  assign Trace_PC[8] = \<const0> ;
  assign Trace_PC[9] = \<const0> ;
  assign Trace_PC[10] = \<const0> ;
  assign Trace_PC[11] = \<const0> ;
  assign Trace_PC[12] = \<const0> ;
  assign Trace_PC[13] = \<const0> ;
  assign Trace_PC[14] = \<const0> ;
  assign Trace_PC[15] = \<const0> ;
  assign Trace_PC[16] = \<const0> ;
  assign Trace_PC[17] = \<const0> ;
  assign Trace_PC[18] = \<const0> ;
  assign Trace_PC[19] = \<const0> ;
  assign Trace_PC[20] = \<const0> ;
  assign Trace_PC[21] = \<const0> ;
  assign Trace_PC[22] = \<const0> ;
  assign Trace_PC[23] = \<const0> ;
  assign Trace_PC[24] = \<const0> ;
  assign Trace_PC[25] = \<const0> ;
  assign Trace_PC[26] = \<const0> ;
  assign Trace_PC[27] = \<const0> ;
  assign Trace_PC[28] = \<const0> ;
  assign Trace_PC[29] = \<const0> ;
  assign Trace_PC[30] = \<const0> ;
  assign Trace_PC[31] = \<const0> ;
  assign Trace_PID_Reg[0] = \<const0> ;
  assign Trace_PID_Reg[1] = \<const0> ;
  assign Trace_PID_Reg[2] = \<const0> ;
  assign Trace_PID_Reg[3] = \<const0> ;
  assign Trace_PID_Reg[4] = \<const0> ;
  assign Trace_PID_Reg[5] = \<const0> ;
  assign Trace_PID_Reg[6] = \<const0> ;
  assign Trace_PID_Reg[7] = \<const0> ;
  assign Trace_Reg_Addr[0] = \<const0> ;
  assign Trace_Reg_Addr[1] = \<const0> ;
  assign Trace_Reg_Addr[2] = \<const0> ;
  assign Trace_Reg_Addr[3] = \<const0> ;
  assign Trace_Reg_Addr[4] = \<const0> ;
  assign Trace_Reg_Write = \<const0> ;
  assign Trace_Valid_Instr = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_ADDR_TAG_BITS = "17" *) 
  (* C_ALLOW_DCACHE_WR = "1" *) 
  (* C_ALLOW_ICACHE_WR = "1" *) 
  (* C_AREA_OPTIMIZED = "0" *) 
  (* C_ASYNC_INTERRUPT = "1" *) 
  (* C_ASYNC_WAKEUP = "3" *) 
  (* C_AVOID_PRIMITIVES = "0" *) 
  (* C_BASE_VECTORS = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_BRANCH_TARGET_CACHE_SIZE = "0" *) 
  (* C_CACHE_BYTE_SIZE = "8192" *) 
  (* C_DADDR_SIZE = "32" *) 
  (* C_DATA_SIZE = "32" *) 
  (* C_DCACHE_ADDR_TAG = "17" *) 
  (* C_DCACHE_ALWAYS_USED = "1" *) 
  (* C_DCACHE_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_DCACHE_BYTE_SIZE = "8192" *) 
  (* C_DCACHE_DATA_WIDTH = "0" *) 
  (* C_DCACHE_FORCE_TAG_LUTRAM = "0" *) 
  (* C_DCACHE_HIGHADDR = "64'b0000000000000000000000000000000000111111111111111111111111111111" *) 
  (* C_DCACHE_LINE_LEN = "4" *) 
  (* C_DCACHE_USE_WRITEBACK = "0" *) 
  (* C_DCACHE_VICTIMS = "0" *) 
  (* C_DEBUG_COUNTER_WIDTH = "32" *) 
  (* C_DEBUG_ENABLED = "0" *) 
  (* C_DEBUG_EVENT_COUNTERS = "5" *) 
  (* C_DEBUG_EXTERNAL_TRACE = "0" *) 
  (* C_DEBUG_INTERFACE = "0" *) 
  (* C_DEBUG_LATENCY_COUNTERS = "1" *) 
  (* C_DEBUG_PROFILE_SIZE = "0" *) 
  (* C_DEBUG_TRACE_ASYNC_RESET = "0" *) 
  (* C_DEBUG_TRACE_SIZE = "8192" *) 
  (* C_DIV_ZERO_EXCEPTION = "0" *) 
  (* C_DYNAMIC_BUS_SIZING = "0" *) 
  (* C_D_AXI = "0" *) 
  (* C_D_LMB = "1" *) 
  (* C_D_LMB_PROTOCOL = "0" *) 
  (* C_ECC_USE_CE_EXCEPTION = "0" *) 
  (* C_EDGE_IS_POSITIVE = "1" *) 
  (* C_ENDIANNESS = "1" *) 
  (* C_FAMILY = "kintexu" *) 
  (* C_FAULT_TOLERANT = "0" *) 
  (* C_FPU_EXCEPTION = "0" *) 
  (* C_FREQ = "100000000" *) 
  (* C_FSL_EXCEPTION = "0" *) 
  (* C_FSL_LINKS = "0" *) 
  (* C_IADDR_SIZE = "32" *) 
  (* C_ICACHE_ALWAYS_USED = "1" *) 
  (* C_ICACHE_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_ICACHE_DATA_WIDTH = "0" *) 
  (* C_ICACHE_FORCE_TAG_LUTRAM = "0" *) 
  (* C_ICACHE_HIGHADDR = "64'b0000000000000000000000000000000000111111111111111111111111111111" *) 
  (* C_ICACHE_LINE_LEN = "4" *) 
  (* C_ICACHE_STREAMS = "0" *) 
  (* C_ICACHE_VICTIMS = "0" *) 
  (* C_ILL_OPCODE_EXCEPTION = "0" *) 
  (* C_IMPRECISE_EXCEPTIONS = "0" *) 
  (* C_INSTANCE = "bd_9054_microblaze_I_0" *) 
  (* C_INSTR_SIZE = "32" *) 
  (* C_INTERCONNECT = "2" *) 
  (* C_INTERRUPT_IS_EDGE = "0" *) 
  (* C_I_AXI = "0" *) 
  (* C_I_LMB = "1" *) 
  (* C_I_LMB_PROTOCOL = "0" *) 
  (* C_LMB_DATA_SIZE = "32" *) 
  (* C_LOCKSTEP_MASTER = "0" *) 
  (* C_LOCKSTEP_SLAVE = "0" *) 
  (* C_M0_AXIS_DATA_WIDTH = "32" *) 
  (* C_M10_AXIS_DATA_WIDTH = "32" *) 
  (* C_M11_AXIS_DATA_WIDTH = "32" *) 
  (* C_M12_AXIS_DATA_WIDTH = "32" *) 
  (* C_M13_AXIS_DATA_WIDTH = "32" *) 
  (* C_M14_AXIS_DATA_WIDTH = "32" *) 
  (* C_M15_AXIS_DATA_WIDTH = "32" *) 
  (* C_M1_AXIS_DATA_WIDTH = "32" *) 
  (* C_M2_AXIS_DATA_WIDTH = "32" *) 
  (* C_M3_AXIS_DATA_WIDTH = "32" *) 
  (* C_M4_AXIS_DATA_WIDTH = "32" *) 
  (* C_M5_AXIS_DATA_WIDTH = "32" *) 
  (* C_M6_AXIS_DATA_WIDTH = "32" *) 
  (* C_M7_AXIS_DATA_WIDTH = "32" *) 
  (* C_M8_AXIS_DATA_WIDTH = "32" *) 
  (* C_M9_AXIS_DATA_WIDTH = "32" *) 
  (* C_MMU_DTLB_SIZE = "4" *) 
  (* C_MMU_ITLB_SIZE = "2" *) 
  (* C_MMU_PRIVILEGED_INSTR = "0" *) 
  (* C_MMU_TLB_ACCESS = "3" *) 
  (* C_MMU_ZONES = "16" *) 
  (* C_M_AXI_DC_ADDR_WIDTH = "32" *) 
  (* C_M_AXI_DC_ARUSER_WIDTH = "5" *) 
  (* C_M_AXI_DC_AWUSER_WIDTH = "5" *) 
  (* C_M_AXI_DC_BUSER_WIDTH = "1" *) 
  (* C_M_AXI_DC_DATA_WIDTH = "32" *) 
  (* C_M_AXI_DC_EXCLUSIVE_ACCESS = "0" *) 
  (* C_M_AXI_DC_RUSER_WIDTH = "1" *) 
  (* C_M_AXI_DC_THREAD_ID_WIDTH = "1" *) 
  (* C_M_AXI_DC_USER_VALUE = "31" *) 
  (* C_M_AXI_DC_WUSER_WIDTH = "1" *) 
  (* C_M_AXI_DP_ADDR_WIDTH = "32" *) 
  (* C_M_AXI_DP_DATA_WIDTH = "32" *) 
  (* C_M_AXI_DP_EXCLUSIVE_ACCESS = "0" *) 
  (* C_M_AXI_DP_THREAD_ID_WIDTH = "1" *) 
  (* C_M_AXI_D_BUS_EXCEPTION = "0" *) 
  (* C_M_AXI_IC_ADDR_WIDTH = "32" *) 
  (* C_M_AXI_IC_ARUSER_WIDTH = "5" *) 
  (* C_M_AXI_IC_AWUSER_WIDTH = "5" *) 
  (* C_M_AXI_IC_BUSER_WIDTH = "1" *) 
  (* C_M_AXI_IC_DATA_WIDTH = "32" *) 
  (* C_M_AXI_IC_RUSER_WIDTH = "1" *) 
  (* C_M_AXI_IC_THREAD_ID_WIDTH = "1" *) 
  (* C_M_AXI_IC_USER_VALUE = "31" *) 
  (* C_M_AXI_IC_WUSER_WIDTH = "1" *) 
  (* C_M_AXI_IP_ADDR_WIDTH = "32" *) 
  (* C_M_AXI_IP_DATA_WIDTH = "32" *) 
  (* C_M_AXI_IP_THREAD_ID_WIDTH = "1" *) 
  (* C_M_AXI_I_BUS_EXCEPTION = "0" *) 
  (* C_NUMBER_OF_PC_BRK = "1" *) 
  (* C_NUMBER_OF_RD_ADDR_BRK = "0" *) 
  (* C_NUMBER_OF_WR_ADDR_BRK = "0" *) 
  (* C_NUM_SYNC_FF_CLK = "2" *) 
  (* C_NUM_SYNC_FF_CLK_DEBUG = "2" *) 
  (* C_NUM_SYNC_FF_CLK_IRQ = "1" *) 
  (* C_NUM_SYNC_FF_DBG_CLK = "1" *) 
  (* C_NUM_SYNC_FF_DBG_TRACE_CLK = "2" *) 
  (* C_OPCODE_0x0_ILLEGAL = "0" *) 
  (* C_OPTIMIZATION = "0" *) 
  (* C_PC_WIDTH = "17" *) 
  (* C_PIADDR_SIZE = "32" *) 
  (* C_PVR = "0" *) 
  (* C_PVR_USER1 = "8'b00000000" *) 
  (* C_PVR_USER2 = "32'b00000000000000000000000000000000" *) 
  (* C_RESET_MSR = "32'b00000000000000000000000000000000" *) 
  (* C_S0_AXIS_DATA_WIDTH = "32" *) 
  (* C_S10_AXIS_DATA_WIDTH = "32" *) 
  (* C_S11_AXIS_DATA_WIDTH = "32" *) 
  (* C_S12_AXIS_DATA_WIDTH = "32" *) 
  (* C_S13_AXIS_DATA_WIDTH = "32" *) 
  (* C_S14_AXIS_DATA_WIDTH = "32" *) 
  (* C_S15_AXIS_DATA_WIDTH = "32" *) 
  (* C_S1_AXIS_DATA_WIDTH = "32" *) 
  (* C_S2_AXIS_DATA_WIDTH = "32" *) 
  (* C_S3_AXIS_DATA_WIDTH = "32" *) 
  (* C_S4_AXIS_DATA_WIDTH = "32" *) 
  (* C_S5_AXIS_DATA_WIDTH = "32" *) 
  (* C_S6_AXIS_DATA_WIDTH = "32" *) 
  (* C_S7_AXIS_DATA_WIDTH = "32" *) 
  (* C_S8_AXIS_DATA_WIDTH = "32" *) 
  (* C_S9_AXIS_DATA_WIDTH = "32" *) 
  (* C_SCO = "0" *) 
  (* C_TEMPORAL_DEPTH = "0" *) 
  (* C_UNALIGNED_EXCEPTIONS = "0" *) 
  (* C_USE_BARREL = "1" *) 
  (* C_USE_BRANCH_TARGET_CACHE = "0" *) 
  (* C_USE_CONFIG_RESET = "0" *) 
  (* C_USE_DCACHE = "0" *) 
  (* C_USE_DIV = "1" *) 
  (* C_USE_EXTENDED_FSL_INSTR = "0" *) 
  (* C_USE_EXT_BRK = "0" *) 
  (* C_USE_EXT_NM_BRK = "0" *) 
  (* C_USE_FPU = "0" *) 
  (* C_USE_HW_MUL = "1" *) 
  (* C_USE_ICACHE = "0" *) 
  (* C_USE_INTERRUPT = "0" *) 
  (* C_USE_MMU = "0" *) 
  (* C_USE_MSR_INSTR = "0" *) 
  (* C_USE_NON_SECURE = "0" *) 
  (* C_USE_PCMP_INSTR = "1" *) 
  (* C_USE_REORDER_INSTR = "0" *) 
  (* C_USE_STACK_PROTECTION = "0" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* G_TEMPLATE_LIST = "0" *) 
  (* is_du_within_envelope = "true" *) 
  ddr4_0_MicroBlaze U0
       (.Byte_Enable(Byte_Enable),
        .Clk(Clk),
        .Config_Reset(1'b0),
        .DCE(1'b0),
        .DEBUG_ACLK(1'b0),
        .DEBUG_ARESETN(1'b0),
        .DReady(DReady),
        .DUE(1'b0),
        .DWait(1'b0),
        .D_AS(D_AS),
        .Data_Addr({\^Data_Addr ,NLW_U0_Data_Addr_UNCONNECTED[30:31]}),
        .Data_Read(Data_Read),
        .Data_Write(Data_Write),
        .Dbg_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_ARREADY(NLW_U0_Dbg_ARREADY_UNCONNECTED),
        .Dbg_ARVALID(1'b0),
        .Dbg_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_AWREADY(NLW_U0_Dbg_AWREADY_UNCONNECTED),
        .Dbg_AWVALID(1'b0),
        .Dbg_BREADY(1'b0),
        .Dbg_BRESP(NLW_U0_Dbg_BRESP_UNCONNECTED[1:0]),
        .Dbg_BVALID(NLW_U0_Dbg_BVALID_UNCONNECTED),
        .Dbg_Capture(1'b0),
        .Dbg_Clk(1'b0),
        .Dbg_Continue(NLW_U0_Dbg_Continue_UNCONNECTED),
        .Dbg_Disable(1'b0),
        .Dbg_Intr(NLW_U0_Dbg_Intr_UNCONNECTED),
        .Dbg_RDATA(NLW_U0_Dbg_RDATA_UNCONNECTED[31:0]),
        .Dbg_RREADY(1'b0),
        .Dbg_RRESP(NLW_U0_Dbg_RRESP_UNCONNECTED[1:0]),
        .Dbg_RVALID(NLW_U0_Dbg_RVALID_UNCONNECTED),
        .Dbg_Reg_En({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_Shift(1'b0),
        .Dbg_Stop(1'b0),
        .Dbg_TDI(1'b0),
        .Dbg_TDO(NLW_U0_Dbg_TDO_UNCONNECTED),
        .Dbg_Trace_Clk(1'b0),
        .Dbg_Trace_Data(NLW_U0_Dbg_Trace_Data_UNCONNECTED[0:35]),
        .Dbg_Trace_Ready(1'b0),
        .Dbg_Trace_Valid(NLW_U0_Dbg_Trace_Valid_UNCONNECTED),
        .Dbg_Trig_Ack_In({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_Trig_Ack_Out(NLW_U0_Dbg_Trig_Ack_Out_UNCONNECTED[0:7]),
        .Dbg_Trig_In(NLW_U0_Dbg_Trig_In_UNCONNECTED[0:7]),
        .Dbg_Trig_Out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_Update(1'b0),
        .Dbg_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_WREADY(NLW_U0_Dbg_WREADY_UNCONNECTED),
        .Dbg_WVALID(1'b0),
        .Dbg_Wakeup(NLW_U0_Dbg_Wakeup_UNCONNECTED),
        .Debug_Rst(1'b0),
        .Ext_BRK(1'b0),
        .Ext_NM_BRK(1'b0),
        .Hibernate(NLW_U0_Hibernate_UNCONNECTED),
        .ICE(1'b0),
        .IFetch(NLW_U0_IFetch_UNCONNECTED),
        .IReady(IReady),
        .IUE(1'b0),
        .IWAIT(1'b0),
        .I_AS(I_AS),
        .Instr(Instr),
        .Instr_Addr({\^Instr_Addr ,NLW_U0_Instr_Addr_UNCONNECTED[30:31]}),
        .Interrupt(1'b0),
        .Interrupt_Ack(NLW_U0_Interrupt_Ack_UNCONNECTED[0:1]),
        .Interrupt_Address({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .LOCKSTEP_Master_Out(NLW_U0_LOCKSTEP_Master_Out_UNCONNECTED[0:4095]),
        .LOCKSTEP_Out(NLW_U0_LOCKSTEP_Out_UNCONNECTED[0:4095]),
        .LOCKSTEP_Slave_In({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,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1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M0_AXIS_TDATA(NLW_U0_M0_AXIS_TDATA_UNCONNECTED[31:0]),
        .M0_AXIS_TLAST(NLW_U0_M0_AXIS_TLAST_UNCONNECTED),
        .M0_AXIS_TREADY(1'b0),
        .M0_AXIS_TVALID(NLW_U0_M0_AXIS_TVALID_UNCONNECTED),
        .M10_AXIS_TDATA(NLW_U0_M10_AXIS_TDATA_UNCONNECTED[31:0]),
        .M10_AXIS_TLAST(NLW_U0_M10_AXIS_TLAST_UNCONNECTED),
        .M10_AXIS_TREADY(1'b0),
        .M10_AXIS_TVALID(NLW_U0_M10_AXIS_TVALID_UNCONNECTED),
        .M11_AXIS_TDATA(NLW_U0_M11_AXIS_TDATA_UNCONNECTED[31:0]),
        .M11_AXIS_TLAST(NLW_U0_M11_AXIS_TLAST_UNCONNECTED),
        .M11_AXIS_TREADY(1'b0),
        .M11_AXIS_TVALID(NLW_U0_M11_AXIS_TVALID_UNCONNECTED),
        .M12_AXIS_TDATA(NLW_U0_M12_AXIS_TDATA_UNCONNECTED[31:0]),
        .M12_AXIS_TLAST(NLW_U0_M12_AXIS_TLAST_UNCONNECTED),
        .M12_AXIS_TREADY(1'b0),
        .M12_AXIS_TVALID(NLW_U0_M12_AXIS_TVALID_UNCONNECTED),
        .M13_AXIS_TDATA(NLW_U0_M13_AXIS_TDATA_UNCONNECTED[31:0]),
        .M13_AXIS_TLAST(NLW_U0_M13_AXIS_TLAST_UNCONNECTED),
        .M13_AXIS_TREADY(1'b0),
        .M13_AXIS_TVALID(NLW_U0_M13_AXIS_TVALID_UNCONNECTED),
        .M14_AXIS_TDATA(NLW_U0_M14_AXIS_TDATA_UNCONNECTED[31:0]),
        .M14_AXIS_TLAST(NLW_U0_M14_AXIS_TLAST_UNCONNECTED),
        .M14_AXIS_TREADY(1'b0),
        .M14_AXIS_TVALID(NLW_U0_M14_AXIS_TVALID_UNCONNECTED),
        .M15_AXIS_TDATA(NLW_U0_M15_AXIS_TDATA_UNCONNECTED[31:0]),
        .M15_AXIS_TLAST(NLW_U0_M15_AXIS_TLAST_UNCONNECTED),
        .M15_AXIS_TREADY(1'b0),
        .M15_AXIS_TVALID(NLW_U0_M15_AXIS_TVALID_UNCONNECTED),
        .M1_AXIS_TDATA(NLW_U0_M1_AXIS_TDATA_UNCONNECTED[31:0]),
        .M1_AXIS_TLAST(NLW_U0_M1_AXIS_TLAST_UNCONNECTED),
        .M1_AXIS_TREADY(1'b0),
        .M1_AXIS_TVALID(NLW_U0_M1_AXIS_TVALID_UNCONNECTED),
        .M2_AXIS_TDATA(NLW_U0_M2_AXIS_TDATA_UNCONNECTED[31:0]),
        .M2_AXIS_TLAST(NLW_U0_M2_AXIS_TLAST_UNCONNECTED),
        .M2_AXIS_TREADY(1'b0),
        .M2_AXIS_TVALID(NLW_U0_M2_AXIS_TVALID_UNCONNECTED),
        .M3_AXIS_TDATA(NLW_U0_M3_AXIS_TDATA_UNCONNECTED[31:0]),
        .M3_AXIS_TLAST(NLW_U0_M3_AXIS_TLAST_UNCONNECTED),
        .M3_AXIS_TREADY(1'b0),
        .M3_AXIS_TVALID(NLW_U0_M3_AXIS_TVALID_UNCONNECTED),
        .M4_AXIS_TDATA(NLW_U0_M4_AXIS_TDATA_UNCONNECTED[31:0]),
        .M4_AXIS_TLAST(NLW_U0_M4_AXIS_TLAST_UNCONNECTED),
        .M4_AXIS_TREADY(1'b0),
        .M4_AXIS_TVALID(NLW_U0_M4_AXIS_TVALID_UNCONNECTED),
        .M5_AXIS_TDATA(NLW_U0_M5_AXIS_TDATA_UNCONNECTED[31:0]),
        .M5_AXIS_TLAST(NLW_U0_M5_AXIS_TLAST_UNCONNECTED),
        .M5_AXIS_TREADY(1'b0),
        .M5_AXIS_TVALID(NLW_U0_M5_AXIS_TVALID_UNCONNECTED),
        .M6_AXIS_TDATA(NLW_U0_M6_AXIS_TDATA_UNCONNECTED[31:0]),
        .M6_AXIS_TLAST(NLW_U0_M6_AXIS_TLAST_UNCONNECTED),
        .M6_AXIS_TREADY(1'b0),
        .M6_AXIS_TVALID(NLW_U0_M6_AXIS_TVALID_UNCONNECTED),
        .M7_AXIS_TDATA(NLW_U0_M7_AXIS_TDATA_UNCONNECTED[31:0]),
        .M7_AXIS_TLAST(NLW_U0_M7_AXIS_TLAST_UNCONNECTED),
        .M7_AXIS_TREADY(1'b0),
        .M7_AXIS_TVALID(NLW_U0_M7_AXIS_TVALID_UNCONNECTED),
        .M8_AXIS_TDATA(NLW_U0_M8_AXIS_TDATA_UNCONNECTED[31:0]),
        .M8_AXIS_TLAST(NLW_U0_M8_AXIS_TLAST_UNCONNECTED),
        .M8_AXIS_TREADY(1'b0),
        .M8_AXIS_TVALID(NLW_U0_M8_AXIS_TVALID_UNCONNECTED),
        .M9_AXIS_TDATA(NLW_U0_M9_AXIS_TDATA_UNCONNECTED[31:0]),
        .M9_AXIS_TLAST(NLW_U0_M9_AXIS_TLAST_UNCONNECTED),
        .M9_AXIS_TREADY(1'b0),
        .M9_AXIS_TVALID(NLW_U0_M9_AXIS_TVALID_UNCONNECTED),
        .MB_Error(NLW_U0_MB_Error_UNCONNECTED),
        .MB_Halted(NLW_U0_MB_Halted_UNCONNECTED),
        .M_AXI_DC_ACADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_DC_ACPROT({1'b0,1'b0,1'b0}),
        .M_AXI_DC_ACREADY(NLW_U0_M_AXI_DC_ACREADY_UNCONNECTED),
        .M_AXI_DC_ACSNOOP({1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_DC_ACVALID(1'b0),
        .M_AXI_DC_ARADDR(NLW_U0_M_AXI_DC_ARADDR_UNCONNECTED[31:0]),
        .M_AXI_DC_ARBAR(NLW_U0_M_AXI_DC_ARBAR_UNCONNECTED[1:0]),
        .M_AXI_DC_ARBURST(NLW_U0_M_AXI_DC_ARBURST_UNCONNECTED[1:0]),
        .M_AXI_DC_ARCACHE(NLW_U0_M_AXI_DC_ARCACHE_UNCONNECTED[3:0]),
        .M_AXI_DC_ARDOMAIN(NLW_U0_M_AXI_DC_ARDOMAIN_UNCONNECTED[1:0]),
        .M_AXI_DC_ARID(NLW_U0_M_AXI_DC_ARID_UNCONNECTED[0]),
        .M_AXI_DC_ARLEN(NLW_U0_M_AXI_DC_ARLEN_UNCONNECTED[7:0]),
        .M_AXI_DC_ARLOCK(NLW_U0_M_AXI_DC_ARLOCK_UNCONNECTED),
        .M_AXI_DC_ARPROT(NLW_U0_M_AXI_DC_ARPROT_UNCONNECTED[2:0]),
        .M_AXI_DC_ARQOS(NLW_U0_M_AXI_DC_ARQOS_UNCONNECTED[3:0]),
        .M_AXI_DC_ARREADY(1'b0),
        .M_AXI_DC_ARSIZE(NLW_U0_M_AXI_DC_ARSIZE_UNCONNECTED[2:0]),
        .M_AXI_DC_ARSNOOP(NLW_U0_M_AXI_DC_ARSNOOP_UNCONNECTED[3:0]),
        .M_AXI_DC_ARUSER(NLW_U0_M_AXI_DC_ARUSER_UNCONNECTED[4:0]),
        .M_AXI_DC_ARVALID(NLW_U0_M_AXI_DC_ARVALID_UNCONNECTED),
        .M_AXI_DC_AWADDR(NLW_U0_M_AXI_DC_AWADDR_UNCONNECTED[31:0]),
        .M_AXI_DC_AWBAR(NLW_U0_M_AXI_DC_AWBAR_UNCONNECTED[1:0]),
        .M_AXI_DC_AWBURST(NLW_U0_M_AXI_DC_AWBURST_UNCONNECTED[1:0]),
        .M_AXI_DC_AWCACHE(NLW_U0_M_AXI_DC_AWCACHE_UNCONNECTED[3:0]),
        .M_AXI_DC_AWDOMAIN(NLW_U0_M_AXI_DC_AWDOMAIN_UNCONNECTED[1:0]),
        .M_AXI_DC_AWID(NLW_U0_M_AXI_DC_AWID_UNCONNECTED[0]),
        .M_AXI_DC_AWLEN(NLW_U0_M_AXI_DC_AWLEN_UNCONNECTED[7:0]),
        .M_AXI_DC_AWLOCK(NLW_U0_M_AXI_DC_AWLOCK_UNCONNECTED),
        .M_AXI_DC_AWPROT(NLW_U0_M_AXI_DC_AWPROT_UNCONNECTED[2:0]),
        .M_AXI_DC_AWQOS(NLW_U0_M_AXI_DC_AWQOS_UNCONNECTED[3:0]),
        .M_AXI_DC_AWREADY(1'b0),
        .M_AXI_DC_AWSIZE(NLW_U0_M_AXI_DC_AWSIZE_UNCONNECTED[2:0]),
        .M_AXI_DC_AWSNOOP(NLW_U0_M_AXI_DC_AWSNOOP_UNCONNECTED[2:0]),
        .M_AXI_DC_AWUSER(NLW_U0_M_AXI_DC_AWUSER_UNCONNECTED[4:0]),
        .M_AXI_DC_AWVALID(NLW_U0_M_AXI_DC_AWVALID_UNCONNECTED),
        .M_AXI_DC_BID(1'b0),
        .M_AXI_DC_BREADY(NLW_U0_M_AXI_DC_BREADY_UNCONNECTED),
        .M_AXI_DC_BRESP({1'b0,1'b0}),
        .M_AXI_DC_BUSER(1'b0),
        .M_AXI_DC_BVALID(1'b0),
        .M_AXI_DC_CDDATA(NLW_U0_M_AXI_DC_CDDATA_UNCONNECTED[31:0]),
        .M_AXI_DC_CDLAST(NLW_U0_M_AXI_DC_CDLAST_UNCONNECTED),
        .M_AXI_DC_CDREADY(1'b0),
        .M_AXI_DC_CDVALID(NLW_U0_M_AXI_DC_CDVALID_UNCONNECTED),
        .M_AXI_DC_CRREADY(1'b0),
        .M_AXI_DC_CRRESP(NLW_U0_M_AXI_DC_CRRESP_UNCONNECTED[4:0]),
        .M_AXI_DC_CRVALID(NLW_U0_M_AXI_DC_CRVALID_UNCONNECTED),
        .M_AXI_DC_RACK(NLW_U0_M_AXI_DC_RACK_UNCONNECTED),
        .M_AXI_DC_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_DC_RID(1'b0),
        .M_AXI_DC_RLAST(1'b0),
        .M_AXI_DC_RREADY(NLW_U0_M_AXI_DC_RREADY_UNCONNECTED),
        .M_AXI_DC_RRESP({1'b0,1'b0}),
        .M_AXI_DC_RUSER(1'b0),
        .M_AXI_DC_RVALID(1'b0),
        .M_AXI_DC_WACK(NLW_U0_M_AXI_DC_WACK_UNCONNECTED),
        .M_AXI_DC_WDATA(NLW_U0_M_AXI_DC_WDATA_UNCONNECTED[31:0]),
        .M_AXI_DC_WLAST(NLW_U0_M_AXI_DC_WLAST_UNCONNECTED),
        .M_AXI_DC_WREADY(1'b0),
        .M_AXI_DC_WSTRB(NLW_U0_M_AXI_DC_WSTRB_UNCONNECTED[3:0]),
        .M_AXI_DC_WUSER(NLW_U0_M_AXI_DC_WUSER_UNCONNECTED[0]),
        .M_AXI_DC_WVALID(NLW_U0_M_AXI_DC_WVALID_UNCONNECTED),
        .M_AXI_DP_ARADDR(NLW_U0_M_AXI_DP_ARADDR_UNCONNECTED[31:0]),
        .M_AXI_DP_ARBURST(NLW_U0_M_AXI_DP_ARBURST_UNCONNECTED[1:0]),
        .M_AXI_DP_ARCACHE(NLW_U0_M_AXI_DP_ARCACHE_UNCONNECTED[3:0]),
        .M_AXI_DP_ARID(NLW_U0_M_AXI_DP_ARID_UNCONNECTED[0]),
        .M_AXI_DP_ARLEN(NLW_U0_M_AXI_DP_ARLEN_UNCONNECTED[7:0]),
        .M_AXI_DP_ARLOCK(NLW_U0_M_AXI_DP_ARLOCK_UNCONNECTED),
        .M_AXI_DP_ARPROT(NLW_U0_M_AXI_DP_ARPROT_UNCONNECTED[2:0]),
        .M_AXI_DP_ARQOS(NLW_U0_M_AXI_DP_ARQOS_UNCONNECTED[3:0]),
        .M_AXI_DP_ARREADY(1'b0),
        .M_AXI_DP_ARSIZE(NLW_U0_M_AXI_DP_ARSIZE_UNCONNECTED[2:0]),
        .M_AXI_DP_ARVALID(NLW_U0_M_AXI_DP_ARVALID_UNCONNECTED),
        .M_AXI_DP_AWADDR(NLW_U0_M_AXI_DP_AWADDR_UNCONNECTED[31:0]),
        .M_AXI_DP_AWBURST(NLW_U0_M_AXI_DP_AWBURST_UNCONNECTED[1:0]),
        .M_AXI_DP_AWCACHE(NLW_U0_M_AXI_DP_AWCACHE_UNCONNECTED[3:0]),
        .M_AXI_DP_AWID(NLW_U0_M_AXI_DP_AWID_UNCONNECTED[0]),
        .M_AXI_DP_AWLEN(NLW_U0_M_AXI_DP_AWLEN_UNCONNECTED[7:0]),
        .M_AXI_DP_AWLOCK(NLW_U0_M_AXI_DP_AWLOCK_UNCONNECTED),
        .M_AXI_DP_AWPROT(NLW_U0_M_AXI_DP_AWPROT_UNCONNECTED[2:0]),
        .M_AXI_DP_AWQOS(NLW_U0_M_AXI_DP_AWQOS_UNCONNECTED[3:0]),
        .M_AXI_DP_AWREADY(1'b0),
        .M_AXI_DP_AWSIZE(NLW_U0_M_AXI_DP_AWSIZE_UNCONNECTED[2:0]),
        .M_AXI_DP_AWVALID(NLW_U0_M_AXI_DP_AWVALID_UNCONNECTED),
        .M_AXI_DP_BID(1'b0),
        .M_AXI_DP_BREADY(NLW_U0_M_AXI_DP_BREADY_UNCONNECTED),
        .M_AXI_DP_BRESP({1'b0,1'b0}),
        .M_AXI_DP_BVALID(1'b0),
        .M_AXI_DP_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_DP_RID(1'b0),
        .M_AXI_DP_RLAST(1'b0),
        .M_AXI_DP_RREADY(NLW_U0_M_AXI_DP_RREADY_UNCONNECTED),
        .M_AXI_DP_RRESP({1'b0,1'b0}),
        .M_AXI_DP_RVALID(1'b0),
        .M_AXI_DP_WDATA(NLW_U0_M_AXI_DP_WDATA_UNCONNECTED[31:0]),
        .M_AXI_DP_WLAST(NLW_U0_M_AXI_DP_WLAST_UNCONNECTED),
        .M_AXI_DP_WREADY(1'b0),
        .M_AXI_DP_WSTRB(NLW_U0_M_AXI_DP_WSTRB_UNCONNECTED[3:0]),
        .M_AXI_DP_WVALID(NLW_U0_M_AXI_DP_WVALID_UNCONNECTED),
        .M_AXI_IC_ACADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_IC_ACPROT({1'b0,1'b0,1'b0}),
        .M_AXI_IC_ACREADY(NLW_U0_M_AXI_IC_ACREADY_UNCONNECTED),
        .M_AXI_IC_ACSNOOP({1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_IC_ACVALID(1'b0),
        .M_AXI_IC_ARADDR(NLW_U0_M_AXI_IC_ARADDR_UNCONNECTED[31:0]),
        .M_AXI_IC_ARBAR(NLW_U0_M_AXI_IC_ARBAR_UNCONNECTED[1:0]),
        .M_AXI_IC_ARBURST(NLW_U0_M_AXI_IC_ARBURST_UNCONNECTED[1:0]),
        .M_AXI_IC_ARCACHE(NLW_U0_M_AXI_IC_ARCACHE_UNCONNECTED[3:0]),
        .M_AXI_IC_ARDOMAIN(NLW_U0_M_AXI_IC_ARDOMAIN_UNCONNECTED[1:0]),
        .M_AXI_IC_ARID(NLW_U0_M_AXI_IC_ARID_UNCONNECTED[0]),
        .M_AXI_IC_ARLEN(NLW_U0_M_AXI_IC_ARLEN_UNCONNECTED[7:0]),
        .M_AXI_IC_ARLOCK(NLW_U0_M_AXI_IC_ARLOCK_UNCONNECTED),
        .M_AXI_IC_ARPROT(NLW_U0_M_AXI_IC_ARPROT_UNCONNECTED[2:0]),
        .M_AXI_IC_ARQOS(NLW_U0_M_AXI_IC_ARQOS_UNCONNECTED[3:0]),
        .M_AXI_IC_ARREADY(1'b0),
        .M_AXI_IC_ARSIZE(NLW_U0_M_AXI_IC_ARSIZE_UNCONNECTED[2:0]),
        .M_AXI_IC_ARSNOOP(NLW_U0_M_AXI_IC_ARSNOOP_UNCONNECTED[3:0]),
        .M_AXI_IC_ARUSER(NLW_U0_M_AXI_IC_ARUSER_UNCONNECTED[4:0]),
        .M_AXI_IC_ARVALID(NLW_U0_M_AXI_IC_ARVALID_UNCONNECTED),
        .M_AXI_IC_AWADDR(NLW_U0_M_AXI_IC_AWADDR_UNCONNECTED[31:0]),
        .M_AXI_IC_AWBAR(NLW_U0_M_AXI_IC_AWBAR_UNCONNECTED[1:0]),
        .M_AXI_IC_AWBURST(NLW_U0_M_AXI_IC_AWBURST_UNCONNECTED[1:0]),
        .M_AXI_IC_AWCACHE(NLW_U0_M_AXI_IC_AWCACHE_UNCONNECTED[3:0]),
        .M_AXI_IC_AWDOMAIN(NLW_U0_M_AXI_IC_AWDOMAIN_UNCONNECTED[1:0]),
        .M_AXI_IC_AWID(NLW_U0_M_AXI_IC_AWID_UNCONNECTED[0]),
        .M_AXI_IC_AWLEN(NLW_U0_M_AXI_IC_AWLEN_UNCONNECTED[7:0]),
        .M_AXI_IC_AWLOCK(NLW_U0_M_AXI_IC_AWLOCK_UNCONNECTED),
        .M_AXI_IC_AWPROT(NLW_U0_M_AXI_IC_AWPROT_UNCONNECTED[2:0]),
        .M_AXI_IC_AWQOS(NLW_U0_M_AXI_IC_AWQOS_UNCONNECTED[3:0]),
        .M_AXI_IC_AWREADY(1'b0),
        .M_AXI_IC_AWSIZE(NLW_U0_M_AXI_IC_AWSIZE_UNCONNECTED[2:0]),
        .M_AXI_IC_AWSNOOP(NLW_U0_M_AXI_IC_AWSNOOP_UNCONNECTED[2:0]),
        .M_AXI_IC_AWUSER(NLW_U0_M_AXI_IC_AWUSER_UNCONNECTED[4:0]),
        .M_AXI_IC_AWVALID(NLW_U0_M_AXI_IC_AWVALID_UNCONNECTED),
        .M_AXI_IC_BID(1'b0),
        .M_AXI_IC_BREADY(NLW_U0_M_AXI_IC_BREADY_UNCONNECTED),
        .M_AXI_IC_BRESP({1'b0,1'b0}),
        .M_AXI_IC_BUSER(1'b0),
        .M_AXI_IC_BVALID(1'b0),
        .M_AXI_IC_CDDATA(NLW_U0_M_AXI_IC_CDDATA_UNCONNECTED[31:0]),
        .M_AXI_IC_CDLAST(NLW_U0_M_AXI_IC_CDLAST_UNCONNECTED),
        .M_AXI_IC_CDREADY(1'b0),
        .M_AXI_IC_CDVALID(NLW_U0_M_AXI_IC_CDVALID_UNCONNECTED),
        .M_AXI_IC_CRREADY(1'b0),
        .M_AXI_IC_CRRESP(NLW_U0_M_AXI_IC_CRRESP_UNCONNECTED[4:0]),
        .M_AXI_IC_CRVALID(NLW_U0_M_AXI_IC_CRVALID_UNCONNECTED),
        .M_AXI_IC_RACK(NLW_U0_M_AXI_IC_RACK_UNCONNECTED),
        .M_AXI_IC_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_IC_RID(1'b0),
        .M_AXI_IC_RLAST(1'b0),
        .M_AXI_IC_RREADY(NLW_U0_M_AXI_IC_RREADY_UNCONNECTED),
        .M_AXI_IC_RRESP({1'b0,1'b0}),
        .M_AXI_IC_RUSER(1'b0),
        .M_AXI_IC_RVALID(1'b0),
        .M_AXI_IC_WACK(NLW_U0_M_AXI_IC_WACK_UNCONNECTED),
        .M_AXI_IC_WDATA(NLW_U0_M_AXI_IC_WDATA_UNCONNECTED[31:0]),
        .M_AXI_IC_WLAST(NLW_U0_M_AXI_IC_WLAST_UNCONNECTED),
        .M_AXI_IC_WREADY(1'b0),
        .M_AXI_IC_WSTRB(NLW_U0_M_AXI_IC_WSTRB_UNCONNECTED[3:0]),
        .M_AXI_IC_WUSER(NLW_U0_M_AXI_IC_WUSER_UNCONNECTED[0]),
        .M_AXI_IC_WVALID(NLW_U0_M_AXI_IC_WVALID_UNCONNECTED),
        .M_AXI_IP_ARADDR(NLW_U0_M_AXI_IP_ARADDR_UNCONNECTED[31:0]),
        .M_AXI_IP_ARBURST(NLW_U0_M_AXI_IP_ARBURST_UNCONNECTED[1:0]),
        .M_AXI_IP_ARCACHE(NLW_U0_M_AXI_IP_ARCACHE_UNCONNECTED[3:0]),
        .M_AXI_IP_ARID(NLW_U0_M_AXI_IP_ARID_UNCONNECTED[0]),
        .M_AXI_IP_ARLEN(NLW_U0_M_AXI_IP_ARLEN_UNCONNECTED[7:0]),
        .M_AXI_IP_ARLOCK(NLW_U0_M_AXI_IP_ARLOCK_UNCONNECTED),
        .M_AXI_IP_ARPROT(NLW_U0_M_AXI_IP_ARPROT_UNCONNECTED[2:0]),
        .M_AXI_IP_ARQOS(NLW_U0_M_AXI_IP_ARQOS_UNCONNECTED[3:0]),
        .M_AXI_IP_ARREADY(1'b0),
        .M_AXI_IP_ARSIZE(NLW_U0_M_AXI_IP_ARSIZE_UNCONNECTED[2:0]),
        .M_AXI_IP_ARVALID(NLW_U0_M_AXI_IP_ARVALID_UNCONNECTED),
        .M_AXI_IP_AWADDR(NLW_U0_M_AXI_IP_AWADDR_UNCONNECTED[31:0]),
        .M_AXI_IP_AWBURST(NLW_U0_M_AXI_IP_AWBURST_UNCONNECTED[1:0]),
        .M_AXI_IP_AWCACHE(NLW_U0_M_AXI_IP_AWCACHE_UNCONNECTED[3:0]),
        .M_AXI_IP_AWID(NLW_U0_M_AXI_IP_AWID_UNCONNECTED[0]),
        .M_AXI_IP_AWLEN(NLW_U0_M_AXI_IP_AWLEN_UNCONNECTED[7:0]),
        .M_AXI_IP_AWLOCK(NLW_U0_M_AXI_IP_AWLOCK_UNCONNECTED),
        .M_AXI_IP_AWPROT(NLW_U0_M_AXI_IP_AWPROT_UNCONNECTED[2:0]),
        .M_AXI_IP_AWQOS(NLW_U0_M_AXI_IP_AWQOS_UNCONNECTED[3:0]),
        .M_AXI_IP_AWREADY(1'b0),
        .M_AXI_IP_AWSIZE(NLW_U0_M_AXI_IP_AWSIZE_UNCONNECTED[2:0]),
        .M_AXI_IP_AWVALID(NLW_U0_M_AXI_IP_AWVALID_UNCONNECTED),
        .M_AXI_IP_BID(1'b0),
        .M_AXI_IP_BREADY(NLW_U0_M_AXI_IP_BREADY_UNCONNECTED),
        .M_AXI_IP_BRESP({1'b0,1'b0}),
        .M_AXI_IP_BVALID(1'b0),
        .M_AXI_IP_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_IP_RID(1'b0),
        .M_AXI_IP_RLAST(1'b0),
        .M_AXI_IP_RREADY(NLW_U0_M_AXI_IP_RREADY_UNCONNECTED),
        .M_AXI_IP_RRESP({1'b0,1'b0}),
        .M_AXI_IP_RVALID(1'b0),
        .M_AXI_IP_WDATA(NLW_U0_M_AXI_IP_WDATA_UNCONNECTED[31:0]),
        .M_AXI_IP_WLAST(NLW_U0_M_AXI_IP_WLAST_UNCONNECTED),
        .M_AXI_IP_WREADY(1'b0),
        .M_AXI_IP_WSTRB(NLW_U0_M_AXI_IP_WSTRB_UNCONNECTED[3:0]),
        .M_AXI_IP_WVALID(NLW_U0_M_AXI_IP_WVALID_UNCONNECTED),
        .Mb_Reset(1'b0),
        .Non_Secure({1'b0,1'b0,1'b0,1'b0}),
        .Pause(1'b0),
        .Pause_Ack(NLW_U0_Pause_Ack_UNCONNECTED),
        .RAM_DCache_Data_From(NLW_U0_RAM_DCache_Data_From_UNCONNECTED[255:0]),
        .RAM_DCache_Data_To({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RAM_DCache_Tag_From(NLW_U0_RAM_DCache_Tag_From_UNCONNECTED[255:0]),
        .RAM_DCache_Tag_To({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RAM_From(NLW_U0_RAM_From_UNCONNECTED[255:0]),
        .RAM_ICache_Data_From(NLW_U0_RAM_ICache_Data_From_UNCONNECTED[255:0]),
        .RAM_ICache_Data_To({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RAM_ICache_Tag_From(NLW_U0_RAM_ICache_Tag_From_UNCONNECTED[255:0]),
        .RAM_ICache_Tag_To({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RAM_To({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Read_Strobe(Read_Strobe),
        .Reset(Reset),
        .Reset_Mode({1'b0,1'b0}),
        .S0_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S0_AXIS_TLAST(1'b0),
        .S0_AXIS_TREADY(NLW_U0_S0_AXIS_TREADY_UNCONNECTED),
        .S0_AXIS_TVALID(1'b0),
        .S10_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S10_AXIS_TLAST(1'b0),
        .S10_AXIS_TREADY(NLW_U0_S10_AXIS_TREADY_UNCONNECTED),
        .S10_AXIS_TVALID(1'b0),
        .S11_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S11_AXIS_TLAST(1'b0),
        .S11_AXIS_TREADY(NLW_U0_S11_AXIS_TREADY_UNCONNECTED),
        .S11_AXIS_TVALID(1'b0),
        .S12_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S12_AXIS_TLAST(1'b0),
        .S12_AXIS_TREADY(NLW_U0_S12_AXIS_TREADY_UNCONNECTED),
        .S12_AXIS_TVALID(1'b0),
        .S13_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S13_AXIS_TLAST(1'b0),
        .S13_AXIS_TREADY(NLW_U0_S13_AXIS_TREADY_UNCONNECTED),
        .S13_AXIS_TVALID(1'b0),
        .S14_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S14_AXIS_TLAST(1'b0),
        .S14_AXIS_TREADY(NLW_U0_S14_AXIS_TREADY_UNCONNECTED),
        .S14_AXIS_TVALID(1'b0),
        .S15_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S15_AXIS_TLAST(1'b0),
        .S15_AXIS_TREADY(NLW_U0_S15_AXIS_TREADY_UNCONNECTED),
        .S15_AXIS_TVALID(1'b0),
        .S1_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S1_AXIS_TLAST(1'b0),
        .S1_AXIS_TREADY(NLW_U0_S1_AXIS_TREADY_UNCONNECTED),
        .S1_AXIS_TVALID(1'b0),
        .S2_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S2_AXIS_TLAST(1'b0),
        .S2_AXIS_TREADY(NLW_U0_S2_AXIS_TREADY_UNCONNECTED),
        .S2_AXIS_TVALID(1'b0),
        .S3_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S3_AXIS_TLAST(1'b0),
        .S3_AXIS_TREADY(NLW_U0_S3_AXIS_TREADY_UNCONNECTED),
        .S3_AXIS_TVALID(1'b0),
        .S4_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S4_AXIS_TLAST(1'b0),
        .S4_AXIS_TREADY(NLW_U0_S4_AXIS_TREADY_UNCONNECTED),
        .S4_AXIS_TVALID(1'b0),
        .S5_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S5_AXIS_TLAST(1'b0),
        .S5_AXIS_TREADY(NLW_U0_S5_AXIS_TREADY_UNCONNECTED),
        .S5_AXIS_TVALID(1'b0),
        .S6_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S6_AXIS_TLAST(1'b0),
        .S6_AXIS_TREADY(NLW_U0_S6_AXIS_TREADY_UNCONNECTED),
        .S6_AXIS_TVALID(1'b0),
        .S7_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S7_AXIS_TLAST(1'b0),
        .S7_AXIS_TREADY(NLW_U0_S7_AXIS_TREADY_UNCONNECTED),
        .S7_AXIS_TVALID(1'b0),
        .S8_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S8_AXIS_TLAST(1'b0),
        .S8_AXIS_TREADY(NLW_U0_S8_AXIS_TREADY_UNCONNECTED),
        .S8_AXIS_TVALID(1'b0),
        .S9_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S9_AXIS_TLAST(1'b0),
        .S9_AXIS_TREADY(NLW_U0_S9_AXIS_TREADY_UNCONNECTED),
        .S9_AXIS_TVALID(1'b0),
        .Scan_En(1'b0),
        .Scan_Reset(1'b0),
        .Scan_Reset_Sel(1'b0),
        .Sleep(NLW_U0_Sleep_UNCONNECTED),
        .Suspend(NLW_U0_Suspend_UNCONNECTED),
        .Trace_DCache_Hit(NLW_U0_Trace_DCache_Hit_UNCONNECTED),
        .Trace_DCache_Rdy(NLW_U0_Trace_DCache_Rdy_UNCONNECTED),
        .Trace_DCache_Read(NLW_U0_Trace_DCache_Read_UNCONNECTED),
        .Trace_DCache_Req(NLW_U0_Trace_DCache_Req_UNCONNECTED),
        .Trace_Data_Access(NLW_U0_Trace_Data_Access_UNCONNECTED),
        .Trace_Data_Address(NLW_U0_Trace_Data_Address_UNCONNECTED[0:31]),
        .Trace_Data_Byte_Enable(NLW_U0_Trace_Data_Byte_Enable_UNCONNECTED[0:3]),
        .Trace_Data_Read(NLW_U0_Trace_Data_Read_UNCONNECTED),
        .Trace_Data_Write(NLW_U0_Trace_Data_Write_UNCONNECTED),
        .Trace_Data_Write_Value(NLW_U0_Trace_Data_Write_Value_UNCONNECTED[0:31]),
        .Trace_Delay_Slot(NLW_U0_Trace_Delay_Slot_UNCONNECTED),
        .Trace_EX_PipeRun(NLW_U0_Trace_EX_PipeRun_UNCONNECTED),
        .Trace_Exception_Kind(NLW_U0_Trace_Exception_Kind_UNCONNECTED[0:4]),
        .Trace_Exception_Taken(NLW_U0_Trace_Exception_Taken_UNCONNECTED),
        .Trace_ICache_Hit(NLW_U0_Trace_ICache_Hit_UNCONNECTED),
        .Trace_ICache_Rdy(NLW_U0_Trace_ICache_Rdy_UNCONNECTED),
        .Trace_ICache_Req(NLW_U0_Trace_ICache_Req_UNCONNECTED),
        .Trace_Instruction(NLW_U0_Trace_Instruction_UNCONNECTED[0:31]),
        .Trace_Jump_Hit(NLW_U0_Trace_Jump_Hit_UNCONNECTED),
        .Trace_Jump_Taken(NLW_U0_Trace_Jump_Taken_UNCONNECTED),
        .Trace_MB_Halted(NLW_U0_Trace_MB_Halted_UNCONNECTED),
        .Trace_MEM_PipeRun(NLW_U0_Trace_MEM_PipeRun_UNCONNECTED),
        .Trace_MSR_Reg(NLW_U0_Trace_MSR_Reg_UNCONNECTED[0:14]),
        .Trace_New_Reg_Value(NLW_U0_Trace_New_Reg_Value_UNCONNECTED[0:31]),
        .Trace_OF_PipeRun(NLW_U0_Trace_OF_PipeRun_UNCONNECTED),
        .Trace_PC(NLW_U0_Trace_PC_UNCONNECTED[0:31]),
        .Trace_PID_Reg(NLW_U0_Trace_PID_Reg_UNCONNECTED[0:7]),
        .Trace_Reg_Addr(NLW_U0_Trace_Reg_Addr_UNCONNECTED[0:4]),
        .Trace_Reg_Write(NLW_U0_Trace_Reg_Write_UNCONNECTED),
        .Trace_Valid_Instr(NLW_U0_Trace_Valid_Instr_UNCONNECTED),
        .Wakeup({1'b0,1'b0}),
        .Write_Strobe(Write_Strobe));
endmodule

(* CHECK_LICENSE_TYPE = "bd_9054_rst_0_0,proc_sys_reset,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "bd_9054_rst_0_0" *) 
(* X_CORE_INFO = "proc_sys_reset,Vivado 2022.2" *) 
module ddr4_0_bd_9054_rst_0_0
   (slowest_sync_clk,
    ext_reset_in,
    aux_reset_in,
    mb_debug_sys_rst,
    dcm_locked,
    mb_reset,
    bus_struct_reset,
    peripheral_reset,
    interconnect_aresetn,
    peripheral_aresetn);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_9054_Clk, INSERT_VIP 0" *) input slowest_sync_clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input ext_reset_in;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input aux_reset_in;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input mb_debug_sys_rst;
  input dcm_locked;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) output mb_reset;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]bus_struct_reset;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_reset;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0" *) output [0:0]interconnect_aresetn;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0" *) output [0:0]peripheral_aresetn;

  wire \<const0> ;
  wire [0:0]bus_struct_reset;
  wire ext_reset_in;
  wire mb_reset;
  wire [0:0]peripheral_reset;
  wire slowest_sync_clk;
  wire [0:0]NLW_U0_interconnect_aresetn_UNCONNECTED;
  wire [0:0]NLW_U0_peripheral_aresetn_UNCONNECTED;

  assign interconnect_aresetn[0] = \<const0> ;
  assign peripheral_aresetn[0] = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_AUX_RESET_HIGH = "1'b0" *) 
  (* C_AUX_RST_WIDTH = "4" *) 
  (* C_EXT_RESET_HIGH = "1'b1" *) 
  (* C_EXT_RST_WIDTH = "4" *) 
  (* C_FAMILY = "kintexu" *) 
  (* C_NUM_BUS_RST = "1" *) 
  (* C_NUM_INTERCONNECT_ARESETN = "1" *) 
  (* C_NUM_PERP_ARESETN = "1" *) 
  (* C_NUM_PERP_RST = "1" *) 
  ddr4_0_proc_sys_reset U0
       (.aux_reset_in(1'b1),
        .bus_struct_reset(bus_struct_reset),
        .dcm_locked(1'b1),
        .ext_reset_in(ext_reset_in),
        .interconnect_aresetn(NLW_U0_interconnect_aresetn_UNCONNECTED[0]),
        .mb_debug_sys_rst(1'b0),
        .mb_reset(mb_reset),
        .peripheral_aresetn(NLW_U0_peripheral_aresetn_UNCONNECTED[0]),
        .peripheral_reset(peripheral_reset),
        .slowest_sync_clk(slowest_sync_clk));
endmodule

(* CHECK_LICENSE_TYPE = "bd_9054_second_dlmb_cntlr_0,lmb_bram_if_cntlr,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "bd_9054_second_dlmb_cntlr_0" *) 
(* X_CORE_INFO = "lmb_bram_if_cntlr,Vivado 2022.2" *) 
module ddr4_0_bd_9054_second_dlmb_cntlr_0
   (LMB_Clk,
    LMB_Rst,
    LMB_ABus,
    LMB_WriteDBus,
    LMB_AddrStrobe,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_BE,
    Sl_DBus,
    Sl_Ready,
    Sl_Wait,
    Sl_UE,
    Sl_CE,
    BRAM_Rst_A,
    BRAM_Clk_A,
    BRAM_Addr_A,
    BRAM_EN_A,
    BRAM_WEN_A,
    BRAM_Dout_A,
    BRAM_Din_A);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_9054_Clk, INSERT_VIP 0" *) input LMB_Clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD" *) input [0:31]LMB_ABus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 32768, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A;

  wire \<const0> ;
  wire [0:31]BRAM_Din_A;
  wire [0:3]BRAM_WEN_A;
  wire [0:31]LMB_ABus;
  wire LMB_AddrStrobe;
  wire [0:3]LMB_BE;
  wire LMB_Clk;
  wire LMB_Rst;
  wire [0:31]LMB_WriteDBus;
  wire LMB_WriteStrobe;
  wire Sl_Ready;

  assign BRAM_Addr_A[0] = \<const0> ;
  assign BRAM_Addr_A[1] = \<const0> ;
  assign BRAM_Addr_A[2] = \<const0> ;
  assign BRAM_Addr_A[3] = \<const0> ;
  assign BRAM_Addr_A[4] = \<const0> ;
  assign BRAM_Addr_A[5] = \<const0> ;
  assign BRAM_Addr_A[6] = \<const0> ;
  assign BRAM_Addr_A[7] = \<const0> ;
  assign BRAM_Addr_A[8] = \<const0> ;
  assign BRAM_Addr_A[9] = \<const0> ;
  assign BRAM_Addr_A[10] = \<const0> ;
  assign BRAM_Addr_A[11] = \<const0> ;
  assign BRAM_Addr_A[12] = \<const0> ;
  assign BRAM_Addr_A[13] = \<const0> ;
  assign BRAM_Addr_A[14] = \<const0> ;
  assign BRAM_Addr_A[15] = \<const0> ;
  assign BRAM_Addr_A[16] = \<const0> ;
  assign BRAM_Addr_A[17:29] = LMB_ABus[17:29];
  assign BRAM_Addr_A[30] = \<const0> ;
  assign BRAM_Addr_A[31] = \<const0> ;
  assign BRAM_Clk_A = LMB_Clk;
  assign BRAM_Dout_A[0:31] = LMB_WriteDBus;
  assign BRAM_EN_A = LMB_AddrStrobe;
  assign BRAM_Rst_A = \<const0> ;
  assign Sl_CE = \<const0> ;
  assign Sl_DBus[0:31] = BRAM_Din_A;
  assign Sl_UE = \<const0> ;
  assign Sl_Wait = \<const0> ;
  GND GND
       (.G(\<const0> ));
  ddr4_0_lmb_bram_if_cntlr__parameterized3 U0
       (.BRAM_WEN_A(BRAM_WEN_A),
        .LMB_ABus({LMB_ABus[0],LMB_ABus[1],LMB_ABus[15]}),
        .LMB_AddrStrobe(LMB_AddrStrobe),
        .LMB_BE(LMB_BE),
        .LMB_Clk(LMB_Clk),
        .LMB_Rst(LMB_Rst),
        .LMB_WriteStrobe(LMB_WriteStrobe),
        .Sl_Ready(Sl_Ready));
endmodule

(* CHECK_LICENSE_TYPE = "bd_9054_second_ilmb_cntlr_0,lmb_bram_if_cntlr,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "bd_9054_second_ilmb_cntlr_0" *) 
(* X_CORE_INFO = "lmb_bram_if_cntlr,Vivado 2022.2" *) 
module ddr4_0_bd_9054_second_ilmb_cntlr_0
   (LMB_Clk,
    LMB_Rst,
    LMB_ABus,
    LMB_WriteDBus,
    LMB_AddrStrobe,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_BE,
    Sl_DBus,
    Sl_Ready,
    Sl_Wait,
    Sl_UE,
    Sl_CE,
    BRAM_Rst_A,
    BRAM_Clk_A,
    BRAM_Addr_A,
    BRAM_EN_A,
    BRAM_WEN_A,
    BRAM_Dout_A,
    BRAM_Din_A);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_9054_Clk, INSERT_VIP 0" *) input LMB_Clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0" *) input LMB_Rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, PROTOCOL STANDARD" *) input [0:31]LMB_ABus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 32768, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1" *) output BRAM_Rst_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A;

  wire \<const0> ;
  wire [0:31]BRAM_Din_A;
  wire [0:31]LMB_ABus;
  wire LMB_AddrStrobe;
  wire LMB_Clk;
  wire LMB_Rst;
  wire Sl_Ready;

  assign BRAM_Addr_A[0] = \<const0> ;
  assign BRAM_Addr_A[1] = \<const0> ;
  assign BRAM_Addr_A[2] = \<const0> ;
  assign BRAM_Addr_A[3] = \<const0> ;
  assign BRAM_Addr_A[4] = \<const0> ;
  assign BRAM_Addr_A[5] = \<const0> ;
  assign BRAM_Addr_A[6] = \<const0> ;
  assign BRAM_Addr_A[7] = \<const0> ;
  assign BRAM_Addr_A[8] = \<const0> ;
  assign BRAM_Addr_A[9] = \<const0> ;
  assign BRAM_Addr_A[10] = \<const0> ;
  assign BRAM_Addr_A[11] = \<const0> ;
  assign BRAM_Addr_A[12] = \<const0> ;
  assign BRAM_Addr_A[13] = \<const0> ;
  assign BRAM_Addr_A[14] = \<const0> ;
  assign BRAM_Addr_A[15] = \<const0> ;
  assign BRAM_Addr_A[16] = \<const0> ;
  assign BRAM_Addr_A[17:29] = LMB_ABus[17:29];
  assign BRAM_Addr_A[30] = \<const0> ;
  assign BRAM_Addr_A[31] = \<const0> ;
  assign BRAM_Clk_A = LMB_Clk;
  assign BRAM_Dout_A[0] = \<const0> ;
  assign BRAM_Dout_A[1] = \<const0> ;
  assign BRAM_Dout_A[2] = \<const0> ;
  assign BRAM_Dout_A[3] = \<const0> ;
  assign BRAM_Dout_A[4] = \<const0> ;
  assign BRAM_Dout_A[5] = \<const0> ;
  assign BRAM_Dout_A[6] = \<const0> ;
  assign BRAM_Dout_A[7] = \<const0> ;
  assign BRAM_Dout_A[8] = \<const0> ;
  assign BRAM_Dout_A[9] = \<const0> ;
  assign BRAM_Dout_A[10] = \<const0> ;
  assign BRAM_Dout_A[11] = \<const0> ;
  assign BRAM_Dout_A[12] = \<const0> ;
  assign BRAM_Dout_A[13] = \<const0> ;
  assign BRAM_Dout_A[14] = \<const0> ;
  assign BRAM_Dout_A[15] = \<const0> ;
  assign BRAM_Dout_A[16] = \<const0> ;
  assign BRAM_Dout_A[17] = \<const0> ;
  assign BRAM_Dout_A[18] = \<const0> ;
  assign BRAM_Dout_A[19] = \<const0> ;
  assign BRAM_Dout_A[20] = \<const0> ;
  assign BRAM_Dout_A[21] = \<const0> ;
  assign BRAM_Dout_A[22] = \<const0> ;
  assign BRAM_Dout_A[23] = \<const0> ;
  assign BRAM_Dout_A[24] = \<const0> ;
  assign BRAM_Dout_A[25] = \<const0> ;
  assign BRAM_Dout_A[26] = \<const0> ;
  assign BRAM_Dout_A[27] = \<const0> ;
  assign BRAM_Dout_A[28] = \<const0> ;
  assign BRAM_Dout_A[29] = \<const0> ;
  assign BRAM_Dout_A[30] = \<const0> ;
  assign BRAM_Dout_A[31] = \<const0> ;
  assign BRAM_EN_A = LMB_AddrStrobe;
  assign BRAM_Rst_A = \<const0> ;
  assign BRAM_WEN_A[0] = \<const0> ;
  assign BRAM_WEN_A[1] = \<const0> ;
  assign BRAM_WEN_A[2] = \<const0> ;
  assign BRAM_WEN_A[3] = \<const0> ;
  assign Sl_CE = \<const0> ;
  assign Sl_DBus[0:31] = BRAM_Din_A;
  assign Sl_UE = \<const0> ;
  assign Sl_Wait = \<const0> ;
  GND GND
       (.G(\<const0> ));
  ddr4_0_lmb_bram_if_cntlr__parameterized5 U0
       (.LMB_ABus({LMB_ABus[0],LMB_ABus[15]}),
        .LMB_AddrStrobe(LMB_AddrStrobe),
        .LMB_Clk(LMB_Clk),
        .LMB_Rst(LMB_Rst),
        .Sl_Ready(Sl_Ready));
endmodule

(* CHECK_LICENSE_TYPE = "bd_9054_second_lmb_bram_I_0,blk_mem_gen_v8_4_5,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "bd_9054_second_lmb_bram_I_0" *) 
(* X_CORE_INFO = "blk_mem_gen_v8_4_5,Vivado 2022.2" *) 
module ddr4_0_bd_9054_second_lmb_bram_I_0
   (clka,
    rsta,
    ena,
    wea,
    addra,
    dina,
    douta,
    clkb,
    rstb,
    enb,
    web,
    addrb,
    dinb,
    doutb,
    rsta_busy,
    rstb_busy);
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1" *) input clka;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) input rsta;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [3:0]wea;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [31:0]addra;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [31:0]dina;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 32768, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1" *) input clkb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) input rstb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) input enb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) input [3:0]web;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [31:0]addrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) input [31:0]dinb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [31:0]doutb;
  output rsta_busy;
  output rstb_busy;

  wire \<const0> ;
  wire [31:0]addra;
  wire [31:0]addrb;
  wire clka;
  wire clkb;
  wire [31:0]dina;
  wire [31:0]douta;
  wire [31:0]doutb;
  wire ena;
  wire enb;
  wire [3:0]wea;
  wire NLW_U0_dbiterr_UNCONNECTED;
  wire NLW_U0_rsta_busy_UNCONNECTED;
  wire NLW_U0_rstb_busy_UNCONNECTED;
  wire NLW_U0_s_axi_arready_UNCONNECTED;
  wire NLW_U0_s_axi_awready_UNCONNECTED;
  wire NLW_U0_s_axi_bvalid_UNCONNECTED;
  wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
  wire NLW_U0_s_axi_rlast_UNCONNECTED;
  wire NLW_U0_s_axi_rvalid_UNCONNECTED;
  wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
  wire NLW_U0_s_axi_wready_UNCONNECTED;
  wire NLW_U0_sbiterr_UNCONNECTED;
  wire [31:0]NLW_U0_rdaddrecc_UNCONNECTED;
  wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
  wire [31:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
  wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED;
  wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;

  assign rsta_busy = \<const0> ;
  assign rstb_busy = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_ADDRA_WIDTH = "32" *) 
  (* C_ADDRB_WIDTH = "32" *) 
  (* C_ALGORITHM = "1" *) 
  (* C_AXI_ID_WIDTH = "4" *) 
  (* C_AXI_SLAVE_TYPE = "0" *) 
  (* C_AXI_TYPE = "1" *) 
  (* C_BYTE_SIZE = "8" *) 
  (* C_COMMON_CLK = "0" *) 
  (* C_COUNT_18K_BRAM = "0" *) 
  (* C_COUNT_36K_BRAM = "8" *) 
  (* C_CTRL_ECC_ALGO = "NONE" *) 
  (* C_DEFAULT_DATA = "0" *) 
  (* C_DISABLE_WARN_BHV_COLL = "0" *) 
  (* C_DISABLE_WARN_BHV_RANGE = "0" *) 
  (* C_ELABORATION_DIR = "./" *) 
  (* C_ENABLE_32BIT_ADDRESS = "1" *) 
  (* C_EN_DEEPSLEEP_PIN = "0" *) 
  (* C_EN_ECC_PIPE = "0" *) 
  (* C_EN_RDADDRA_CHG = "0" *) 
  (* C_EN_RDADDRB_CHG = "0" *) 
  (* C_EN_SAFETY_CKT = "1" *) 
  (* C_EN_SHUTDOWN_PIN = "0" *) 
  (* C_EN_SLEEP_PIN = "0" *) 
  (* C_EST_POWER_SUMMARY = "Estimated Power for IP     :     2.839147 mW" *) 
  (* C_FAMILY = "kintexu" *) 
  (* C_HAS_AXI_ID = "0" *) 
  (* C_HAS_ENA = "1" *) 
  (* C_HAS_ENB = "1" *) 
  (* C_HAS_INJECTERR = "0" *) 
  (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) 
  (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) 
  (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) 
  (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) 
  (* C_HAS_REGCEA = "0" *) 
  (* C_HAS_REGCEB = "0" *) 
  (* C_HAS_RSTA = "1" *) 
  (* C_HAS_RSTB = "1" *) 
  (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) 
  (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) 
  (* C_INITA_VAL = "0" *) 
  (* C_INITB_VAL = "0" *) 
  (* C_INIT_FILE = "bd_9054_second_lmb_bram_I_0.mem" *) 
  (* C_INIT_FILE_NAME = "no_coe_file_loaded" *) 
  (* C_INTERFACE_TYPE = "0" *) 
  (* C_LOAD_INIT_FILE = "0" *) 
  (* C_MEM_TYPE = "2" *) 
  (* C_MUX_PIPELINE_STAGES = "0" *) 
  (* C_PRIM_TYPE = "1" *) 
  (* C_READ_DEPTH_A = "8192" *) 
  (* C_READ_DEPTH_B = "8192" *) 
  (* C_READ_LATENCY_A = "1" *) 
  (* C_READ_LATENCY_B = "1" *) 
  (* C_READ_WIDTH_A = "32" *) 
  (* C_READ_WIDTH_B = "32" *) 
  (* C_RSTRAM_A = "0" *) 
  (* C_RSTRAM_B = "0" *) 
  (* C_RST_PRIORITY_A = "CE" *) 
  (* C_RST_PRIORITY_B = "CE" *) 
  (* C_SIM_COLLISION_CHECK = "ALL" *) 
  (* C_USE_BRAM_BLOCK = "1" *) 
  (* C_USE_BYTE_WEA = "1" *) 
  (* C_USE_BYTE_WEB = "1" *) 
  (* C_USE_DEFAULT_DATA = "0" *) 
  (* C_USE_ECC = "0" *) 
  (* C_USE_SOFTECC = "0" *) 
  (* C_USE_URAM = "0" *) 
  (* C_WEA_WIDTH = "4" *) 
  (* C_WEB_WIDTH = "4" *) 
  (* C_WRITE_DEPTH_A = "8192" *) 
  (* C_WRITE_DEPTH_B = "8192" *) 
  (* C_WRITE_MODE_A = "WRITE_FIRST" *) 
  (* C_WRITE_MODE_B = "WRITE_FIRST" *) 
  (* C_WRITE_WIDTH_A = "32" *) 
  (* C_WRITE_WIDTH_B = "32" *) 
  (* C_XDEVICEFAMILY = "kintexu" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* is_du_within_envelope = "true" *) 
  ddr4_0_blk_mem_gen_v8_4_5__parameterized1 U0
       (.addra({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,addra[14:2],1'b0,1'b0}),
        .addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,addrb[14:2],1'b0,1'b0}),
        .clka(clka),
        .clkb(clkb),
        .dbiterr(NLW_U0_dbiterr_UNCONNECTED),
        .deepsleep(1'b0),
        .dina(dina),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(douta),
        .doutb(doutb),
        .eccpipece(1'b0),
        .ena(ena),
        .enb(enb),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[31:0]),
        .regcea(1'b0),
        .regceb(1'b0),
        .rsta(1'b0),
        .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
        .rstb(1'b0),
        .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
        .s_aclk(1'b0),
        .s_aresetn(1'b0),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
        .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
        .s_axi_injectdbiterr(1'b0),
        .s_axi_injectsbiterr(1'b0),
        .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[31:0]),
        .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]),
        .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
        .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
        .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wvalid(1'b0),
        .sbiterr(NLW_U0_sbiterr_UNCONNECTED),
        .shutdown(1'b0),
        .sleep(1'b0),
        .wea(wea),
        .web({1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "cdc_sync" *) 
module ddr4_0_cdc_sync
   (lpf_exr_reg,
    scndry_out,
    lpf_exr,
    p_1_in4_in,
    p_2_in3_in,
    exr_lpf,
    ext_reset_in,
    slowest_sync_clk);
  output lpf_exr_reg;
  output scndry_out;
  input lpf_exr;
  input p_1_in4_in;
  input p_2_in3_in;
  input [0:0]exr_lpf;
  input ext_reset_in;
  input slowest_sync_clk;

  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ;
  wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ;
  wire Q;
  wire [0:0]exr_lpf;
  wire ext_reset_in;
  wire lpf_exr;
  wire lpf_exr_reg;
  wire p_1_in4_in;
  wire p_2_in3_in;
  wire scndry_out;
  wire slowest_sync_clk;

  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(ext_reset_in),
        .Q(Q),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(Q),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d2 ),
        .Q(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3 ),
        .Q(scndry_out),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hEAAAAAA8)) 
    lpf_exr_i_1
       (.I0(lpf_exr),
        .I1(p_1_in4_in),
        .I2(p_2_in3_in),
        .I3(scndry_out),
        .I4(exr_lpf),
        .O(lpf_exr_reg));
endmodule

(* ACT_SKEW = "8'b00000000" *) (* ADDR_SKEW = "136'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* ADDR_WIDTH = "17" *) 
(* ADV_USER_REQ = "NONE" *) (* AL = "0" *) (* ALIAS_PAGE = "OFF" *) 
(* ALIAS_P_CNT = "OFF" *) (* APP_ADDR_WIDTH = "30" *) (* APP_DATA_WIDTH = "512" *) 
(* APP_MASK_WIDTH = "64" *) (* AUTO_AP_COL_A3 = "OFF" *) (* BANK_GROUP_WIDTH = "1" *) 
(* BANK_WIDTH = "2" *) (* BA_SKEW = "16'b0000000000000000" *) (* BG_SKEW = "8'b00000000" *) 
(* BISC_EN = "1" *) (* BURST_MODE = "8" *) (* BYPASS_CAL = "FALSE" *) 
(* CALIB_HIGH_SPEED = "FALSE" *) (* CAL_DQS_GATE = "FULL" *) (* CAL_DQS_TRACKING = "FULL" *) 
(* CAL_JITTER = "FULL" *) (* CAL_RDLVL = "FULL" *) (* CAL_RDLVL_COMPLEX = "FULL" *) 
(* CAL_RDLVL_DBI = "SKIP" *) (* CAL_RD_VREF = "SKIP" *) (* CAL_RD_VREF_PATTERN = "SIMPLE" *) 
(* CAL_WRITE_LAT = "FULL" *) (* CAL_WRLVL = "FULL" *) (* CAL_WR_DQS_COMPLEX = "FULL" *) 
(* CAL_WR_DQS_DM_DBI = "FULL" *) (* CAL_WR_DQS_DQ = "FULL" *) (* CAL_WR_VREF = "SKIP" *) 
(* CAL_WR_VREF_PATTERN = "SIMPLE" *) (* CAS_FIFO_BYPASS = "ON" *) (* CA_MIRROR = "OFF" *) 
(* CKE_SKEW = "8'b00000000" *) (* CKE_WIDTH = "1" *) (* CK_SKEW = "8'b00000000" *) 
(* CK_WIDTH = "1" *) (* CLKFBOUT_MULT_MMCM = "17" *) (* CLKIN_PERIOD_MMCM = "14161" *) 
(* CLKOUT0_DIVIDE_MMCM = "4" *) (* CLKOUT1_DIVIDE_MMCM = "4" *) (* CLKOUT2_DIVIDE_MMCM = "4" *) 
(* CLKOUT3_DIVIDE_MMCM = "4" *) (* CLKOUT4_DIVIDE_MMCM = "4" *) (* CLKOUT6_DIVIDE_MMCM = "8" *) 
(* CLKOUTPHY_MODE = "VCO_2X" *) (* COL_WIDTH = "10" *) (* COMPONENT_WIDTH = "16" *) 
(* CPLX_PAT_LENGTH = "LONG" *) (* CS_SKEW = "8'b00000000" *) (* CS_WIDTH = "1" *) 
(* C_DEBUG_ENABLED = "0" *) (* C_FAMILY = "kintexu" *) (* C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG" *) 
(* C_SKEW = "8'b00000000" *) (* C_S_AXI_ADDR_WIDTH = "0" *) (* C_S_AXI_DATA_WIDTH = "0" *) 
(* C_S_AXI_ID_WIDTH = "0" *) (* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *) (* ControllerType = "ddr4_sdram" *) 
(* DATA_BUF_OFFSET_WIDTH = "1" *) (* DBYTES = "8" *) (* DDR4_CLAMSHELL = "OFF" *) 
(* DDR4_DB_DIF_DI = "4'b0000" *) (* DDR4_DB_DIF_ODT = "4'b0011" *) (* DDR4_DB_DIF_VREF = "8'b00011011" *) 
(* DDR4_DB_HIF_DI = "4'b0001" *) (* DDR4_DB_HIF_RTT_NOM = "4'b0011" *) (* DDR4_DB_HIF_RTT_PARK = "4'b0000" *) 
(* DDR4_DB_HIF_RTT_WR = "4'b0000" *) (* DDR4_DB_HIF_VREF = "8'b00011011" *) (* DDR4_REG_PARITY_ENABLE = "OFF" *) 
(* DDR4_REG_RC03 = "13'b0000000110000" *) (* DDR4_REG_RC04 = "13'b0000001000000" *) (* DDR4_REG_RC05 = "13'b0000001010000" *) 
(* DEBUG_SIGNAL = "Disable" *) (* DEVICE = "xcku060-" *) (* DIVCLK_DIVIDE_MMCM = "1" *) 
(* DM_DBI = "DM_NODBI" *) (* DM_WIDTH = "8" *) (* DQS_WIDTH = "8" *) 
(* DQ_WIDTH = "64" *) (* DRAM_TYPE = "DDR4" *) (* DRAM_WIDTH = "16" *) 
(* EARLY_WR_DATA = "OFF" *) (* ECC = "OFF" *) (* ECC_TEST = "OFF" *) 
(* ECC_WIDTH = "8" *) (* EXTRA_CMD_DELAY = "0" *) (* FAMILY = "ULTRASCALE" *) 
(* FPGA = "xcku060-ffva1156-2-i-" *) (* INTERFACE = "NATIVE" *) (* IS_CKE_SHARED = "false" *) 
(* LIVE_DESIGN = "0" *) (* LRDIMM_MODE = "OFF" *) (* LR_WIDTH = "1" *) 
(* MCS_ECC_ENABLE = "FALSE" *) (* MC_ERR_ADDR_WIDTH = "52" *) (* MEMORY_CONFIGURATION = "COMPONENT" *) 
(* MEMORY_DENSITY = "16Gb" *) (* MEMORY_PART = "MT40A1G16RC-062E" *) (* MEMORY_SPEED_GRADE = "062E" *) 
(* MEMORY_WIDTH = "16" *) (* MEM_ADDR_ORDER = "ROW_COLUMN_BANK" *) (* MEM_CODE = "0" *) 
(* MEM_CORE_VER = "xilinx.com:ip:mem:1.4" *) (* MIGRATION = "OFF" *) (* MIG_PARAM_CHECKS = "FALSE" *) 
(* MR0 = "13'b0101101100100" *) (* MR1 = "13'b0001100000001" *) (* MR2 = "13'b0000000011000" *) 
(* MR3 = "13'b0001000000000" *) (* MR4 = "13'b0000000000000" *) (* MR5 = "13'b0010000000000" *) 
(* MR6 = "13'b0100000010100" *) (* NOP_ADD_LOW = "1'b0" *) (* NUMREF = "1" *) 
(* NUM_SLOT = "1" *) (* ODTNOP = "16'b0000000000000000" *) (* ODTRD = "16'b0000000000000000" *) 
(* ODTRDDEL = "5'b10001" *) (* ODTRDDUR = "4'b0110" *) (* ODTRDODEL = "5'b01001" *) 
(* ODTRDODUR = "4'b0110" *) (* ODTWR = "16'b0000000000100001" *) (* ODTWRDEL = "5'b01100" *) 
(* ODTWRDUR = "4'b0110" *) (* ODTWRODEL = "5'b01001" *) (* ODTWRODUR = "4'b0110" *) 
(* ODT_SKEW = "8'b00000000" *) (* ODT_WIDTH = "1" *) (* ORDERING = "NORM" *) 
(* PARTIAL_RECONFIG = "Disable" *) (* PAR_SKEW = "8'b00000000" *) (* PAYLOAD_WIDTH = "64" *) 
(* PER_RD_INTVL = "301" *) (* PER_RD_PERF = "1'b1" *) (* PING_PONG_PHY = "1" *) 
(* PhyIP_ADDR_WIDTH = "17" *) (* PhyIP_BANK_GROUP_WIDTH = "1" *) (* PhyIP_BANK_WIDTH = "2" *) 
(* PhyIP_CA_MIRROR = "0" *) (* PhyIP_CKE_WIDTH = "1" *) (* PhyIP_CK_WIDTH = "1" *) 
(* PhyIP_CLAMSHELL = "false" *) (* PhyIP_CLKFBOUT_MULT = "17" *) (* PhyIP_CLKOUT0_DIVIDE = "4" *) 
(* PhyIP_CLKOUT1_DIVIDE = "0" *) (* PhyIP_CLKOUT2_DIVIDE = "0" *) (* PhyIP_CLKOUT3_DIVIDE = "0" *) 
(* PhyIP_CLKOUT4_DIVIDE = "0" *) (* PhyIP_CLKOUTPHY_MODE = "VCO_2X" *) (* PhyIP_CS_WIDTH = "1" *) 
(* PhyIP_CUSTOM_PART_ATTRIBUTES = "NONE" *) (* PhyIP_CasLatency = "17" *) (* PhyIP_CasWriteLatency = "12" *) 
(* PhyIP_ChipSelect = "true" *) (* PhyIP_DATABITS_PER_STROBE = "8" *) (* PhyIP_DCI_CASCADE_CUTOFF = "938" *) 
(* PhyIP_DEBUG_SIGNAL = "Disable" *) (* PhyIP_DIVCLK_DIVIDE = "1" *) (* PhyIP_DM_WIDTH = "8" *) 
(* PhyIP_DQS_WIDTH = "8" *) (* PhyIP_DQ_WIDTH = "64" *) (* PhyIP_DataMask = "DM_NO_DBI" *) 
(* PhyIP_DataWidth = "64" *) (* PhyIP_ECC = "false" *) (* PhyIP_EN_PARITY = "false" *) 
(* PhyIP_Enable_LVAUX = "false" *) (* PhyIP_HR_MIN_FREQ = "0" *) (* PhyIP_IS_FASTER_SPEED_RAM = "No" *) 
(* PhyIP_IS_FROM_PHY = "1" *) (* PhyIP_InputClockPeriod = "14161" *) (* PhyIP_MEM_DEVICE_WIDTH = "16" *) 
(* PhyIP_MIN_PERIOD = "750" *) (* PhyIP_MemoryPart = "MT40A1G16RC-062E" *) (* PhyIP_MemoryType = "Components" *) 
(* PhyIP_MemoryVoltage = "1.2V" *) (* PhyIP_ODT_WIDTH = "1" *) (* PhyIP_PARTIAL_RECONFIG_FLOW_MIG = "false" *) 
(* PhyIP_PhyClockRatio = "4:1" *) (* PhyIP_Phy_Only = "Complete_Memory_Controller" *) (* PhyIP_RANK_WIDTH = "1" *) 
(* PhyIP_SAVE_RESTORE = "false" *) (* PhyIP_SELF_REFRESH = "false" *) (* PhyIP_Simulation_Mode = "BFM" *) 
(* PhyIP_Slot = "Single" *) (* PhyIP_StackHeight = "1" *) (* PhyIP_System_Clock = "Differential" *) 
(* PhyIP_TimePeriod = "833" *) (* PhyIP_USE_CS_PORT = "true" *) (* PhyIP_USE_DM_PORT = "DM_NO_DBI" *) 
(* PhyIP_VrefVoltage = "0.84" *) (* PhyIP_isCKEShared = "false" *) (* PhyIP_nCS_PER_RANK = "1" *) 
(* PhyIP_tCK = "833" *) (* RANKS = "1" *) (* RANK_SLOT = "1" *) 
(* RANK_WIDTH = "1" *) (* RD_VREF_VAL = "7'b0011111" *) (* REG_CTRL = "OFF" *) 
(* RESTORE_CRC = "false" *) (* ROW_WIDTH = "17" *) (* RTL_VERSION = "0" *) 
(* SAVE_RESTORE = "false" *) (* SELF_REFRESH = "false" *) (* SIM_MODE = "FULL" *) 
(* SLOT0_CONFIG = "8'b00000001" *) (* SLOT0_FUNC_CS = "8'b00000001" *) (* SLOT0_ODD_CS = "8'b00000000" *) 
(* SLOT1_CONFIG = "8'b00000000" *) (* SLOT1_FUNC_CS = "8'b00000000" *) (* SLOT1_ODD_CS = "8'b00000000" *) 
(* STARVATION_EN = "1'b1" *) (* STARVE_COUNT_WIDTH = "9" *) (* SYSCLK_TYPE = "DIFFERENTIAL" *) 
(* S_HEIGHT = "1" *) (* TCQ = "100.000000" *) (* TXN_FIFO_BYPASS = "ON" *) 
(* TXN_FIFO_PIPE = "OFF" *) (* USE_CS_PORT = "1" *) (* X_MIG_OLYMPUS = "1" *) 
(* X_ULTRASCALE_IO_FLOW = "xilinx.com:ip:ddr4_phy:2.2" *) (* ZQINTVL = "1200480193" *) (* dont_touch = "true" *) 
(* nCK_PER_CLK = "4" *) (* t200us = "60025" *) (* t500us = "150061" *) 
(* tCK = "833" *) (* tFAW = "37" *) (* tMOD = "6" *) 
(* tMRD = "2" *) (* tRAS = "39" *) (* tRCD = "17" *) 
(* tREFI = "9363" *) (* tRFC = "421" *) (* tRP = "17" *) 
(* tRRD_L = "8" *) (* tRRD_S = "7" *) (* tRTP = "10" *) 
(* tRTW = "13" *) (* tWR = "20" *) (* tWTR_L = "10" *) 
(* tWTR_S = "4" *) (* tXPR = "109" *) (* tZQCS = "128" *) 
(* tZQINIT = "256" *) 
module ddr4_0_ddr4
   (sys_rst,
    c0_sys_clk_p,
    c0_sys_clk_n,
    c0_ddr4_act_n,
    c0_ddr4_adr,
    c0_ddr4_ba,
    c0_ddr4_bg,
    c0_ddr4_cke,
    c0_ddr4_odt,
    c0_ddr4_cs_n,
    c0_ddr4_ck_t,
    c0_ddr4_ck_c,
    c0_ddr4_reset_n,
    c0_ddr4_dm_dbi_n,
    c0_ddr4_dq,
    c0_ddr4_dqs_c,
    c0_ddr4_dqs_t,
    c0_init_calib_complete,
    addn_ui_clkout1,
    addn_ui_clkout2,
    addn_ui_clkout3,
    addn_ui_clkout4,
    dbg_clk,
    sl_iport0,
    sl_oport0,
    c0_ddr4_app_correct_en_i,
    c0_ddr4_ui_clk,
    c0_ddr4_ui_clk_sync_rst,
    c0_ddr4_app_addr,
    c0_ddr4_app_cmd,
    c0_ddr4_app_en,
    c0_ddr4_app_hi_pri,
    c0_ddr4_app_wdf_data,
    c0_ddr4_app_wdf_end,
    c0_ddr4_app_wdf_mask,
    c0_ddr4_app_wdf_wren,
    c0_ddr4_app_rd_data,
    c0_ddr4_app_rd_data_end,
    c0_ddr4_app_rd_data_valid,
    c0_ddr4_app_rdy,
    c0_ddr4_app_wdf_rdy,
    dbg_bus);
  input sys_rst;
  input c0_sys_clk_p;
  input c0_sys_clk_n;
  output c0_ddr4_act_n;
  output [16:0]c0_ddr4_adr;
  output [1:0]c0_ddr4_ba;
  output [0:0]c0_ddr4_bg;
  output [0:0]c0_ddr4_cke;
  output [0:0]c0_ddr4_odt;
  output [0:0]c0_ddr4_cs_n;
  output [0:0]c0_ddr4_ck_t;
  output [0:0]c0_ddr4_ck_c;
  output c0_ddr4_reset_n;
  inout [7:0]c0_ddr4_dm_dbi_n;
  inout [63:0]c0_ddr4_dq;
  inout [7:0]c0_ddr4_dqs_c;
  inout [7:0]c0_ddr4_dqs_t;
  output c0_init_calib_complete;
  output addn_ui_clkout1;
  output addn_ui_clkout2;
  output addn_ui_clkout3;
  output addn_ui_clkout4;
  output dbg_clk;
  (* keep = "true" *) input [36:0]sl_iport0;
  (* keep = "true" *) output [16:0]sl_oport0;
  input c0_ddr4_app_correct_en_i;
  output c0_ddr4_ui_clk;
  output c0_ddr4_ui_clk_sync_rst;
  input [29:0]c0_ddr4_app_addr;
  input [2:0]c0_ddr4_app_cmd;
  input c0_ddr4_app_en;
  input c0_ddr4_app_hi_pri;
  input [511:0]c0_ddr4_app_wdf_data;
  input c0_ddr4_app_wdf_end;
  input [63:0]c0_ddr4_app_wdf_mask;
  input c0_ddr4_app_wdf_wren;
  output [511:0]c0_ddr4_app_rd_data;
  output c0_ddr4_app_rd_data_end;
  output c0_ddr4_app_rd_data_valid;
  output c0_ddr4_app_rdy;
  output c0_ddr4_app_wdf_rdy;
  output [511:0]dbg_bus;

  wire addn_ui_clkout1;
  wire addn_ui_clkout2;
  wire addn_ui_clkout3;
  wire addn_ui_clkout4;
  wire c0_ddr4_act_n;
  wire [16:0]c0_ddr4_adr;
  wire [29:0]c0_ddr4_app_addr;
  wire [2:0]c0_ddr4_app_cmd;
  wire c0_ddr4_app_en;
  wire [511:0]c0_ddr4_app_rd_data;
  wire c0_ddr4_app_rd_data_end;
  wire c0_ddr4_app_rd_data_valid;
  wire c0_ddr4_app_rdy;
  wire [511:0]c0_ddr4_app_wdf_data;
  wire c0_ddr4_app_wdf_end;
  wire [63:0]c0_ddr4_app_wdf_mask;
  wire c0_ddr4_app_wdf_rdy;
  wire c0_ddr4_app_wdf_wren;
  wire [1:0]c0_ddr4_ba;
  wire [0:0]c0_ddr4_bg;
  wire [0:0]c0_ddr4_ck_c;
  wire [0:0]c0_ddr4_ck_t;
  wire [0:0]c0_ddr4_cke;
  wire [0:0]c0_ddr4_cs_n;
  wire [7:0]c0_ddr4_dm_dbi_n;
  wire [63:0]c0_ddr4_dq;
  wire [7:0]c0_ddr4_dqs_c;
  wire [7:0]c0_ddr4_dqs_t;
  wire [0:0]c0_ddr4_odt;
  wire c0_ddr4_reset_n;
  wire c0_ddr4_ui_clk;
  wire c0_div_clk_rst;
  wire c0_init_calib_complete;
  wire c0_mmcm_clk_in;
  wire c0_riu_clk;
  wire c0_riu_clk_rst;
  wire c0_sys_clk_n;
  wire c0_sys_clk_p;
  wire [511:0]dbg_bus;
  wire dbg_clk;
  (* RTL_KEEP = "true" *) wire div_clk_rst_r1;
  wire mmcm_lock;
  wire pllGate;
  wire pll_lock;
  wire reset_ub;
  (* RTL_KEEP = "true" *) wire [36:0]sl_iport0;
  (* RTL_KEEP = "true" *) wire [16:0]sl_oport0;
  wire sys_clk_in;
  wire sys_rst;
  wire u_ddr4_infrastructure_n_12;
  wire \u_ddr_cal_top/u_ddr_cal/ub_initDone ;

  assign c0_ddr4_ui_clk_sync_rst = div_clk_rst_r1;
  (* KEEP = "yes" *) 
  FDRE div_clk_rst_r1_reg
       (.C(c0_ddr4_ui_clk),
        .CE(1'b1),
        .D(c0_div_clk_rst),
        .Q(div_clk_rst_r1),
        .R(1'b0));
  ddr4_0_ddr4_v2_2_17_infrastructure u_ddr4_infrastructure
       (.Reset(reset_ub),
        .SR(c0_div_clk_rst),
        .addn_ui_clkout1(addn_ui_clkout1),
        .addn_ui_clkout2(addn_ui_clkout2),
        .addn_ui_clkout3(addn_ui_clkout3),
        .addn_ui_clkout4(addn_ui_clkout4),
        .c0_riu_clk(c0_riu_clk),
        .dbg_clk(dbg_clk),
        .mmcm_clk_in(c0_mmcm_clk_in),
        .mmcm_lock(mmcm_lock),
        .pllGate(pllGate),
        .pll_lock(pll_lock),
        .pllgate_reg_0(u_ddr4_infrastructure_n_12),
        .riu_clk_rst(c0_riu_clk_rst),
        .sys_clk_in(sys_clk_in),
        .sys_rst(sys_rst),
        .u_bufg_divClk_0(c0_ddr4_ui_clk),
        .ub_initDone(\u_ddr_cal_top/u_ddr_cal/ub_initDone ));
  ddr4_0_ddr4_mem_intfc u_ddr4_mem_intfc
       (.CLK(c0_riu_clk),
        .Reset(reset_ub),
        .SR(c0_div_clk_rst),
        .\SYNC[19].sync_reg_reg[1] (c0_ddr4_ui_clk),
        .c0_ddr4_act_n(c0_ddr4_act_n),
        .c0_ddr4_adr(c0_ddr4_adr),
        .c0_ddr4_app_addr(c0_ddr4_app_addr[29:3]),
        .c0_ddr4_app_cmd(c0_ddr4_app_cmd),
        .c0_ddr4_app_en(c0_ddr4_app_en),
        .c0_ddr4_app_rd_data(c0_ddr4_app_rd_data),
        .c0_ddr4_app_rd_data_end(c0_ddr4_app_rd_data_end),
        .c0_ddr4_app_rd_data_valid(c0_ddr4_app_rd_data_valid),
        .c0_ddr4_app_rdy(c0_ddr4_app_rdy),
        .c0_ddr4_app_wdf_data(c0_ddr4_app_wdf_data),
        .c0_ddr4_app_wdf_end(c0_ddr4_app_wdf_end),
        .c0_ddr4_app_wdf_mask(c0_ddr4_app_wdf_mask),
        .c0_ddr4_app_wdf_rdy(c0_ddr4_app_wdf_rdy),
        .c0_ddr4_app_wdf_wren(c0_ddr4_app_wdf_wren),
        .c0_ddr4_ba(c0_ddr4_ba),
        .c0_ddr4_bg(c0_ddr4_bg),
        .c0_ddr4_ck_c(c0_ddr4_ck_c),
        .c0_ddr4_ck_t(c0_ddr4_ck_t),
        .c0_ddr4_cke(c0_ddr4_cke),
        .c0_ddr4_cs_n(c0_ddr4_cs_n),
        .c0_ddr4_dm_dbi_n(c0_ddr4_dm_dbi_n),
        .c0_ddr4_dq(c0_ddr4_dq),
        .c0_ddr4_dqs_c(c0_ddr4_dqs_c),
        .c0_ddr4_dqs_t(c0_ddr4_dqs_t),
        .c0_ddr4_odt(c0_ddr4_odt),
        .c0_ddr4_reset_n(c0_ddr4_reset_n),
        .c0_init_calib_complete(c0_init_calib_complete),
        .c0_sys_clk_n(c0_sys_clk_n),
        .c0_sys_clk_p(c0_sys_clk_p),
        .\calSt_reg[0] (u_ddr4_infrastructure_n_12),
        .dbg_bus(dbg_bus),
        .mmcm_clk_in(c0_mmcm_clk_in),
        .mmcm_lock(mmcm_lock),
        .out(sl_iport0),
        .pllGate(pllGate),
        .pll_lock(pll_lock),
        .riu_clk_rst(c0_riu_clk_rst),
        .sl_oport_o(sl_oport0),
        .sys_clk_in(sys_clk_in),
        .ub_initDone(\u_ddr_cal_top/u_ddr_cal/ub_initDone ));
endmodule

module ddr4_0_ddr4_cal_riu
   (out,
    \io_address_riuclk_reg[21]_0 ,
    D,
    \io_write_data_riuclk_reg[31]_0 ,
    io_write_strobe_riuclk_reg_0,
    LMB_UE_riu,
    LMB_CE_riu,
    \riu2clb_valid_r1_riuclk_reg[19]_0 ,
    ub_rst_out_riuclk,
    CLK,
    Reset,
    riu_clk_rst,
    io_ready_lvl_riuclk_r1_reg_0,
    sample_gts,
    \fab_riu_rst_pipe_reg[0]_0 ,
    io_read_data_riuclk,
    riu_addr_cal,
    riu_nibble_8,
    riu2clb_vld_read_data,
    \riu2clb_valid_r1_riuclk_reg[19]_1 );
  output [31:0]out;
  output \io_address_riuclk_reg[21]_0 ;
  output [0:0]D;
  output [31:0]\io_write_data_riuclk_reg[31]_0 ;
  output [0:0]io_write_strobe_riuclk_reg_0;
  output LMB_UE_riu;
  output LMB_CE_riu;
  output [19:0]\riu2clb_valid_r1_riuclk_reg[19]_0 ;
  output ub_rst_out_riuclk;
  input CLK;
  input Reset;
  input riu_clk_rst;
  input [0:0]io_ready_lvl_riuclk_r1_reg_0;
  input sample_gts;
  input [0:0]\fab_riu_rst_pipe_reg[0]_0 ;
  input [31:0]io_read_data_riuclk;
  input [5:0]riu_addr_cal;
  input [7:0]riu_nibble_8;
  input [15:0]riu2clb_vld_read_data;
  input [19:0]\riu2clb_valid_r1_riuclk_reg[19]_1 ;

  wire CLK;
  (* DONT_TOUCH *) wire [0:0]D;
  (* DONT_TOUCH *) wire LMB_CE_riu;
  (* DONT_TOUCH *) wire LMB_UE_riu;
  wire Reset;
  wire any_clb2riu_wr_en;
  wire any_clb2riu_wr_en0;
  wire any_clb2riu_wr_wait;
  wire any_clb2riu_wr_wait_i_1_n_0;
  wire any_clb2riu_wr_wait_i_2_n_0;
  wire any_clb2riu_wr_wait_i_3_n_0;
  wire any_clb2riu_wr_wait_i_4_n_0;
  wire any_clb2riu_wr_wait_i_5_n_0;
  wire [14:0]fab_riu_rst_pipe;
  wire [0:0]\fab_riu_rst_pipe_reg[0]_0 ;
  wire \fab_riu_rst_pipe_reg_n_0_[15] ;
  wire io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0;
  wire io_addr_strobe_lvl_riuclk_i_2_n_0;
  wire io_addr_strobe_lvl_riuclk_i_3_n_0;
  wire io_addr_strobe_lvl_riuclk_i_4_n_0;
  wire io_addr_strobe_lvl_riuclk_i_5_n_0;
  wire io_addr_strobe_lvl_riuclk_i_6_n_0;
  wire io_addr_strobe_lvl_riuclk_i_7_n_0;
  wire io_addr_strobe_lvl_riuclk_i_8_n_0;
  wire io_addr_strobe_lvl_riuclk_i_9_n_0;
  wire io_addr_strobe_lvl_riuclk_reg0;
  wire io_addr_strobe_riuclk;
  wire io_addr_strobe_ub;
  wire io_addr_strobe_ub_hold;
  wire io_addr_strobe_ub_hold_i_1_n_0;
  wire io_addr_strobe_ub_hold_i_2_n_0;
  wire io_addr_strobe_ub_hold_i_3_n_0;
  wire io_addr_strobe_ub_hold_i_4_n_0;
  wire io_addr_strobe_ub_hold_i_5_n_0;
  wire io_addr_strobe_vld_riuclk;
  wire io_addr_strobe_vld_riuclk_i_1_n_0;
  (* DONT_TOUCH *) wire \io_address_riuclk_reg[21]_0 ;
  wire [29:2]io_address_ub;
  wire [31:0]io_read_data_mux;
  wire [31:0]io_read_data_riuclk;
  wire [31:0]io_read_data_ub;
  wire io_ready_lvl_riuclk_r1;
  wire [0:0]io_ready_lvl_riuclk_r1_reg_0;
  wire io_ready_lvl_riuclk_r2;
  wire io_ready_riuclk;
  wire io_ready_riuclk_i_1_n_0;
  wire io_ready_ub;
  wire io_ready_ub_i_10_n_0;
  wire io_ready_ub_i_11_n_0;
  wire io_ready_ub_i_12_n_0;
  wire io_ready_ub_i_1_n_0;
  wire io_ready_ub_i_2_n_0;
  wire io_ready_ub_i_3_n_0;
  wire io_ready_ub_i_4_n_0;
  wire io_ready_ub_i_5_n_0;
  wire io_ready_ub_i_6_n_0;
  wire io_ready_ub_i_7_n_0;
  wire io_ready_ub_i_8_n_0;
  wire io_ready_ub_i_9_n_0;
  (* DONT_TOUCH *) wire [31:0]\io_write_data_riuclk_reg[31]_0 ;
  wire [31:0]io_write_data_ub;
  (* DONT_TOUCH *) wire [0:0]io_write_strobe_riuclk_reg_0;
  wire io_write_strobe_ub;
  (* DONT_TOUCH *) wire [31:0]out;
  wire [0:0]p_1_out;
  (* DONT_TOUCH *) wire [19:0]\riu2clb_valid_r1_riuclk_reg[19]_0 ;
  wire [19:0]\riu2clb_valid_r1_riuclk_reg[19]_1 ;
  wire [15:0]riu2clb_vld_read_data;
  wire [5:0]riu_addr_cal;
  wire riu_clk_rst;
  (* RTL_KEEP = "true" *) wire riu_clk_rst_r1;
  wire [7:0]riu_nibble_8;
  wire riu_rd_val0;
  wire riu_rd_val_r1_reg_srl3_n_0;
  wire riu_rd_val_r2;
  wire sample_gts;
  wire sample_gts_flag;
  wire sample_gts_flag_i_1_n_0;
  wire sample_gts_flag_i_2_n_0;
  wire sample_gts_riu;
  wire ub_rst_out_riuclk;
  wire ub_rst_out_riuclk_i_1_n_0;
  wire ub_rst_out_riuclk_i_2_n_0;
  wire NLW_mcs0_IO_read_strobe_UNCONNECTED;
  wire NLW_mcs0_TRACE_data_access_UNCONNECTED;
  wire NLW_mcs0_TRACE_data_read_UNCONNECTED;
  wire NLW_mcs0_TRACE_data_write_UNCONNECTED;
  wire NLW_mcs0_TRACE_dcache_hit_UNCONNECTED;
  wire NLW_mcs0_TRACE_dcache_rdy_UNCONNECTED;
  wire NLW_mcs0_TRACE_dcache_read_UNCONNECTED;
  wire NLW_mcs0_TRACE_dcache_req_UNCONNECTED;
  wire NLW_mcs0_TRACE_delay_slot_UNCONNECTED;
  wire NLW_mcs0_TRACE_ex_piperun_UNCONNECTED;
  wire NLW_mcs0_TRACE_exception_taken_UNCONNECTED;
  wire NLW_mcs0_TRACE_icache_hit_UNCONNECTED;
  wire NLW_mcs0_TRACE_icache_rdy_UNCONNECTED;
  wire NLW_mcs0_TRACE_icache_req_UNCONNECTED;
  wire NLW_mcs0_TRACE_jump_hit_UNCONNECTED;
  wire NLW_mcs0_TRACE_jump_taken_UNCONNECTED;
  wire NLW_mcs0_TRACE_mb_halted_UNCONNECTED;
  wire NLW_mcs0_TRACE_mem_piperun_UNCONNECTED;
  wire NLW_mcs0_TRACE_of_piperun_UNCONNECTED;
  wire NLW_mcs0_TRACE_reg_write_UNCONNECTED;
  wire NLW_mcs0_TRACE_valid_instr_UNCONNECTED;
  wire [31:0]NLW_mcs0_IO_address_UNCONNECTED;
  wire [3:0]NLW_mcs0_IO_byte_enable_UNCONNECTED;
  wire [0:31]NLW_mcs0_TRACE_data_address_UNCONNECTED;
  wire [0:3]NLW_mcs0_TRACE_data_byte_enable_UNCONNECTED;
  wire [0:31]NLW_mcs0_TRACE_data_write_value_UNCONNECTED;
  wire [0:4]NLW_mcs0_TRACE_exception_kind_UNCONNECTED;
  wire [0:31]NLW_mcs0_TRACE_instruction_UNCONNECTED;
  wire [0:14]NLW_mcs0_TRACE_msr_reg_UNCONNECTED;
  wire [0:31]NLW_mcs0_TRACE_new_reg_value_UNCONNECTED;
  wire [0:31]NLW_mcs0_TRACE_pc_UNCONNECTED;
  wire [0:7]NLW_mcs0_TRACE_pid_reg_UNCONNECTED;
  wire [0:4]NLW_mcs0_TRACE_reg_addr_UNCONNECTED;

  LUT6 #(
    .INIT(64'h0100000000000000)) 
    any_clb2riu_wr_en_i_1
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_write_strobe_riuclk_reg_0),
        .I5(io_addr_strobe_vld_riuclk),
        .O(any_clb2riu_wr_en0));
  FDRE any_clb2riu_wr_en_reg
       (.C(CLK),
        .CE(1'b1),
        .D(any_clb2riu_wr_en0),
        .Q(any_clb2riu_wr_en),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hABAA)) 
    any_clb2riu_wr_wait_i_1
       (.I0(any_clb2riu_wr_en),
        .I1(io_ready_ub),
        .I2(any_clb2riu_wr_wait_i_2_n_0),
        .I3(any_clb2riu_wr_wait),
        .O(any_clb2riu_wr_wait_i_1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    any_clb2riu_wr_wait_i_2
       (.I0(any_clb2riu_wr_wait_i_3_n_0),
        .I1(any_clb2riu_wr_wait_i_4_n_0),
        .I2(any_clb2riu_wr_wait_i_5_n_0),
        .I3(\riu2clb_valid_r1_riuclk_reg[19]_1 [2]),
        .I4(\riu2clb_valid_r1_riuclk_reg[19]_1 [1]),
        .I5(\riu2clb_valid_r1_riuclk_reg[19]_1 [0]),
        .O(any_clb2riu_wr_wait_i_2_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    any_clb2riu_wr_wait_i_3
       (.I0(\riu2clb_valid_r1_riuclk_reg[19]_1 [11]),
        .I1(\riu2clb_valid_r1_riuclk_reg[19]_1 [12]),
        .I2(\riu2clb_valid_r1_riuclk_reg[19]_1 [9]),
        .I3(\riu2clb_valid_r1_riuclk_reg[19]_1 [10]),
        .I4(\riu2clb_valid_r1_riuclk_reg[19]_1 [14]),
        .I5(\riu2clb_valid_r1_riuclk_reg[19]_1 [13]),
        .O(any_clb2riu_wr_wait_i_3_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    any_clb2riu_wr_wait_i_4
       (.I0(\riu2clb_valid_r1_riuclk_reg[19]_1 [5]),
        .I1(\riu2clb_valid_r1_riuclk_reg[19]_1 [6]),
        .I2(\riu2clb_valid_r1_riuclk_reg[19]_1 [3]),
        .I3(\riu2clb_valid_r1_riuclk_reg[19]_1 [4]),
        .I4(\riu2clb_valid_r1_riuclk_reg[19]_1 [8]),
        .I5(\riu2clb_valid_r1_riuclk_reg[19]_1 [7]),
        .O(any_clb2riu_wr_wait_i_4_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    any_clb2riu_wr_wait_i_5
       (.I0(\riu2clb_valid_r1_riuclk_reg[19]_1 [17]),
        .I1(\riu2clb_valid_r1_riuclk_reg[19]_1 [18]),
        .I2(\riu2clb_valid_r1_riuclk_reg[19]_1 [15]),
        .I3(\riu2clb_valid_r1_riuclk_reg[19]_1 [16]),
        .I4(any_clb2riu_wr_wait),
        .I5(\riu2clb_valid_r1_riuclk_reg[19]_1 [19]),
        .O(any_clb2riu_wr_wait_i_5_n_0));
  FDRE #(
    .INIT(1'b0)) 
    any_clb2riu_wr_wait_reg
       (.C(CLK),
        .CE(1'b1),
        .D(any_clb2riu_wr_wait_i_1_n_0),
        .Q(any_clb2riu_wr_wait),
        .R(Reset));
  LUT2 #(
    .INIT(4'hE)) 
    \fab_riu_rst_pipe[0]_i_1 
       (.I0(riu_clk_rst_r1),
        .I1(\fab_riu_rst_pipe_reg[0]_0 ),
        .O(p_1_out));
  FDRE \fab_riu_rst_pipe_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(p_1_out),
        .Q(fab_riu_rst_pipe[0]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[9]),
        .Q(fab_riu_rst_pipe[10]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[10]),
        .Q(fab_riu_rst_pipe[11]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[11]),
        .Q(fab_riu_rst_pipe[12]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[12]),
        .Q(fab_riu_rst_pipe[13]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[13]),
        .Q(fab_riu_rst_pipe[14]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[14]),
        .Q(\fab_riu_rst_pipe_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[0]),
        .Q(fab_riu_rst_pipe[1]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[1]),
        .Q(fab_riu_rst_pipe[2]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[2]),
        .Q(fab_riu_rst_pipe[3]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[3]),
        .Q(fab_riu_rst_pipe[4]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[4]),
        .Q(fab_riu_rst_pipe[5]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[5]),
        .Q(fab_riu_rst_pipe[6]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[6]),
        .Q(fab_riu_rst_pipe[7]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[7]),
        .Q(fab_riu_rst_pipe[8]),
        .R(1'b0));
  FDRE \fab_riu_rst_pipe_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(fab_riu_rst_pipe[8]),
        .Q(fab_riu_rst_pipe[9]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(out[31]));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(out[30]));
  LUT1 #(
    .INIT(2'h2)) 
    i_2
       (.I0(1'b0),
        .O(out[29]));
  LUT1 #(
    .INIT(2'h2)) 
    i_3
       (.I0(1'b0),
        .O(out[28]));
  LUT1 #(
    .INIT(2'h2)) 
    i_4
       (.I0(1'b0),
        .O(LMB_UE_riu));
  LUT1 #(
    .INIT(2'h2)) 
    i_5
       (.I0(1'b0),
        .O(LMB_CE_riu));
  LUT5 #(
    .INIT(32'h01000000)) 
    io_addr_strobe_clb2riu_riuclk_inferred_i_1
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_addr_strobe_riuclk),
        .O(\io_address_riuclk_reg[21]_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    io_addr_strobe_clb2riu_riuclk_inferred_i_2
       (.I0(out[12]),
        .I1(out[15]),
        .I2(out[16]),
        .I3(out[14]),
        .I4(out[13]),
        .O(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0));
  LUT6 #(
    .INIT(64'hF0F0F0F0F0F0F040)) 
    io_addr_strobe_lvl_riuclk_i_1
       (.I0(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I1(io_addr_strobe_lvl_riuclk_i_3_n_0),
        .I2(io_addr_strobe_vld_riuclk),
        .I3(out[23]),
        .I4(out[22]),
        .I5(out[21]),
        .O(io_addr_strobe_lvl_riuclk_reg0));
  LUT1 #(
    .INIT(2'h1)) 
    io_addr_strobe_lvl_riuclk_i_2
       (.I0(D),
        .O(io_addr_strobe_lvl_riuclk_i_2_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    io_addr_strobe_lvl_riuclk_i_3
       (.I0(io_addr_strobe_lvl_riuclk_i_4_n_0),
        .I1(io_addr_strobe_lvl_riuclk_i_5_n_0),
        .I2(io_addr_strobe_lvl_riuclk_i_6_n_0),
        .I3(io_addr_strobe_lvl_riuclk_i_7_n_0),
        .I4(io_addr_strobe_lvl_riuclk_i_8_n_0),
        .I5(io_addr_strobe_lvl_riuclk_i_9_n_0),
        .O(io_addr_strobe_lvl_riuclk_i_3_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    io_addr_strobe_lvl_riuclk_i_4
       (.I0(out[25]),
        .I1(out[24]),
        .I2(out[27]),
        .I3(out[26]),
        .O(io_addr_strobe_lvl_riuclk_i_4_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    io_addr_strobe_lvl_riuclk_i_5
       (.I0(out[29]),
        .I1(out[28]),
        .I2(out[31]),
        .I3(out[30]),
        .O(io_addr_strobe_lvl_riuclk_i_5_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    io_addr_strobe_lvl_riuclk_i_6
       (.I0(out[9]),
        .I1(out[8]),
        .I2(out[11]),
        .I3(out[10]),
        .O(io_addr_strobe_lvl_riuclk_i_6_n_0));
  LUT4 #(
    .INIT(16'hFFFD)) 
    io_addr_strobe_lvl_riuclk_i_7
       (.I0(out[17]),
        .I1(out[18]),
        .I2(out[20]),
        .I3(out[19]),
        .O(io_addr_strobe_lvl_riuclk_i_7_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    io_addr_strobe_lvl_riuclk_i_8
       (.I0(out[5]),
        .I1(out[4]),
        .I2(out[7]),
        .I3(out[6]),
        .O(io_addr_strobe_lvl_riuclk_i_8_n_0));
  LUT4 #(
    .INIT(16'hFFFD)) 
    io_addr_strobe_lvl_riuclk_i_9
       (.I0(out[1]),
        .I1(out[0]),
        .I2(out[3]),
        .I3(out[2]),
        .O(io_addr_strobe_lvl_riuclk_i_9_n_0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    io_addr_strobe_lvl_riuclk_reg
       (.C(CLK),
        .CE(io_addr_strobe_lvl_riuclk_reg0),
        .D(io_addr_strobe_lvl_riuclk_i_2_n_0),
        .Q(D),
        .R(1'b0));
  FDRE io_addr_strobe_riuclk_reg
       (.C(CLK),
        .CE(1'b1),
        .D(io_addr_strobe_ub),
        .Q(io_addr_strobe_riuclk),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFCAAAAAAA8)) 
    io_addr_strobe_ub_hold_i_1
       (.I0(io_addr_strobe_ub),
        .I1(io_addr_strobe_ub_hold_i_2_n_0),
        .I2(io_addr_strobe_ub_hold_i_3_n_0),
        .I3(io_addr_strobe_ub_hold_i_4_n_0),
        .I4(io_addr_strobe_ub_hold_i_5_n_0),
        .I5(io_addr_strobe_ub_hold),
        .O(io_addr_strobe_ub_hold_i_1_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    io_addr_strobe_ub_hold_i_2
       (.I0(fab_riu_rst_pipe[9]),
        .I1(fab_riu_rst_pipe[8]),
        .I2(fab_riu_rst_pipe[11]),
        .I3(fab_riu_rst_pipe[10]),
        .O(io_addr_strobe_ub_hold_i_2_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    io_addr_strobe_ub_hold_i_3
       (.I0(fab_riu_rst_pipe[13]),
        .I1(fab_riu_rst_pipe[12]),
        .I2(\fab_riu_rst_pipe_reg_n_0_[15] ),
        .I3(fab_riu_rst_pipe[14]),
        .O(io_addr_strobe_ub_hold_i_3_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    io_addr_strobe_ub_hold_i_4
       (.I0(fab_riu_rst_pipe[1]),
        .I1(fab_riu_rst_pipe[0]),
        .I2(fab_riu_rst_pipe[3]),
        .I3(fab_riu_rst_pipe[2]),
        .O(io_addr_strobe_ub_hold_i_4_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    io_addr_strobe_ub_hold_i_5
       (.I0(fab_riu_rst_pipe[5]),
        .I1(fab_riu_rst_pipe[4]),
        .I2(fab_riu_rst_pipe[7]),
        .I3(fab_riu_rst_pipe[6]),
        .O(io_addr_strobe_ub_hold_i_5_n_0));
  FDRE io_addr_strobe_ub_hold_reg
       (.C(CLK),
        .CE(1'b1),
        .D(io_addr_strobe_ub_hold_i_1_n_0),
        .Q(io_addr_strobe_ub_hold),
        .R(Reset));
  LUT6 #(
    .INIT(64'h000000000000000E)) 
    io_addr_strobe_vld_riuclk_i_1
       (.I0(io_addr_strobe_ub_hold),
        .I1(io_addr_strobe_ub),
        .I2(io_addr_strobe_ub_hold_i_2_n_0),
        .I3(io_addr_strobe_ub_hold_i_3_n_0),
        .I4(io_addr_strobe_ub_hold_i_4_n_0),
        .I5(io_addr_strobe_ub_hold_i_5_n_0),
        .O(io_addr_strobe_vld_riuclk_i_1_n_0));
  FDRE io_addr_strobe_vld_riuclk_reg
       (.C(CLK),
        .CE(1'b1),
        .D(io_addr_strobe_vld_riuclk_i_1_n_0),
        .Q(io_addr_strobe_vld_riuclk),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[2]),
        .Q(out[0]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[12]),
        .Q(out[10]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[13]),
        .Q(out[11]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[14]),
        .Q(out[12]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[15]),
        .Q(out[13]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[16]),
        .Q(out[14]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[17]),
        .Q(out[15]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[18]),
        .Q(out[16]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[19]),
        .Q(out[17]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[20]),
        .Q(out[18]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[21]),
        .Q(out[19]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[3]),
        .Q(out[1]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[22]),
        .Q(out[20]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[23]),
        .Q(out[21]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[24]),
        .Q(out[22]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[25]),
        .Q(out[23]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[26]),
        .Q(out[24]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[27]),
        .Q(out[25]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[28]),
        .Q(out[26]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[29]),
        .Q(out[27]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[4]),
        .Q(out[2]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[5]),
        .Q(out[3]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[6]),
        .Q(out[4]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[7]),
        .Q(out[5]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[8]),
        .Q(out[6]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[9]),
        .Q(out[7]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[10]),
        .Q(out[8]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_address_riuclk_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_address_ub[11]),
        .Q(out[9]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[0]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[0]),
        .I5(riu2clb_vld_read_data[0]),
        .O(io_read_data_mux[0]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[10]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[10]),
        .I5(riu2clb_vld_read_data[10]),
        .O(io_read_data_mux[10]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[11]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[11]),
        .I5(riu2clb_vld_read_data[11]),
        .O(io_read_data_mux[11]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[12]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[12]),
        .I5(riu2clb_vld_read_data[12]),
        .O(io_read_data_mux[12]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[13]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[13]),
        .I5(riu2clb_vld_read_data[13]),
        .O(io_read_data_mux[13]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[14]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[14]),
        .I5(riu2clb_vld_read_data[14]),
        .O(io_read_data_mux[14]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[15]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[15]),
        .I5(riu2clb_vld_read_data[15]),
        .O(io_read_data_mux[15]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[16]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[16]),
        .I5(riu_nibble_8[0]),
        .O(io_read_data_mux[16]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[17]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[17]),
        .I5(riu_nibble_8[1]),
        .O(io_read_data_mux[17]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[18]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[18]),
        .I5(riu_nibble_8[2]),
        .O(io_read_data_mux[18]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[19]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[19]),
        .I5(riu_nibble_8[3]),
        .O(io_read_data_mux[19]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[1]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[1]),
        .I5(riu2clb_vld_read_data[1]),
        .O(io_read_data_mux[1]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[20]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[20]),
        .I5(riu_nibble_8[4]),
        .O(io_read_data_mux[20]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[21]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[21]),
        .I5(riu_nibble_8[5]),
        .O(io_read_data_mux[21]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[22]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[22]),
        .I5(riu_nibble_8[6]),
        .O(io_read_data_mux[22]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[23]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[23]),
        .I5(riu_nibble_8[7]),
        .O(io_read_data_mux[23]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[24]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[24]),
        .I5(riu_addr_cal[0]),
        .O(io_read_data_mux[24]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[25]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[25]),
        .I5(riu_addr_cal[1]),
        .O(io_read_data_mux[25]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[26]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[26]),
        .I5(riu_addr_cal[2]),
        .O(io_read_data_mux[26]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[27]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[27]),
        .I5(riu_addr_cal[3]),
        .O(io_read_data_mux[27]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[28]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[28]),
        .I5(riu_addr_cal[4]),
        .O(io_read_data_mux[28]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[29]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[29]),
        .I5(riu_addr_cal[5]),
        .O(io_read_data_mux[29]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[2]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[2]),
        .I5(riu2clb_vld_read_data[2]),
        .O(io_read_data_mux[2]));
  LUT5 #(
    .INIT(32'hFEFF0000)) 
    \io_read_data_ub[30]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[30]),
        .O(io_read_data_mux[30]));
  LUT5 #(
    .INIT(32'hFEFF0000)) 
    \io_read_data_ub[31]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[31]),
        .O(io_read_data_mux[31]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[3]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[3]),
        .I5(riu2clb_vld_read_data[3]),
        .O(io_read_data_mux[3]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[4]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[4]),
        .I5(riu2clb_vld_read_data[4]),
        .O(io_read_data_mux[4]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[5]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[5]),
        .I5(riu2clb_vld_read_data[5]),
        .O(io_read_data_mux[5]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[6]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[6]),
        .I5(riu2clb_vld_read_data[6]),
        .O(io_read_data_mux[6]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[7]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[7]),
        .I5(riu2clb_vld_read_data[7]),
        .O(io_read_data_mux[7]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[8]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[8]),
        .I5(riu2clb_vld_read_data[8]),
        .O(io_read_data_mux[8]));
  LUT6 #(
    .INIT(64'hFFFF0100FEFF0000)) 
    \io_read_data_ub[9]_i_1 
       (.I0(out[21]),
        .I1(out[22]),
        .I2(out[23]),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_read_data_riuclk[9]),
        .I5(riu2clb_vld_read_data[9]),
        .O(io_read_data_mux[9]));
  FDRE \io_read_data_ub_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[0]),
        .Q(io_read_data_ub[0]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[10]),
        .Q(io_read_data_ub[10]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[11]),
        .Q(io_read_data_ub[11]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[12]),
        .Q(io_read_data_ub[12]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[13]),
        .Q(io_read_data_ub[13]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[14]),
        .Q(io_read_data_ub[14]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[15]),
        .Q(io_read_data_ub[15]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[16]),
        .Q(io_read_data_ub[16]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[17]),
        .Q(io_read_data_ub[17]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[18]),
        .Q(io_read_data_ub[18]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[19]),
        .Q(io_read_data_ub[19]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[1]),
        .Q(io_read_data_ub[1]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[20]),
        .Q(io_read_data_ub[20]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[21]),
        .Q(io_read_data_ub[21]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[22]),
        .Q(io_read_data_ub[22]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[23]),
        .Q(io_read_data_ub[23]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[24]),
        .Q(io_read_data_ub[24]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[25]),
        .Q(io_read_data_ub[25]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[26]),
        .Q(io_read_data_ub[26]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[27]),
        .Q(io_read_data_ub[27]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[28]),
        .Q(io_read_data_ub[28]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[29]),
        .Q(io_read_data_ub[29]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[2]),
        .Q(io_read_data_ub[2]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[30]),
        .Q(io_read_data_ub[30]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[31]),
        .Q(io_read_data_ub[31]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[3]),
        .Q(io_read_data_ub[3]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[4]),
        .Q(io_read_data_ub[4]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[5]),
        .Q(io_read_data_ub[5]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[6]),
        .Q(io_read_data_ub[6]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[7]),
        .Q(io_read_data_ub[7]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[8]),
        .Q(io_read_data_ub[8]),
        .R(1'b0));
  FDRE \io_read_data_ub_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_read_data_mux[9]),
        .Q(io_read_data_ub[9]),
        .R(1'b0));
  FDRE io_ready_lvl_riuclk_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(io_ready_lvl_riuclk_r1_reg_0),
        .Q(io_ready_lvl_riuclk_r1),
        .R(1'b0));
  FDRE io_ready_lvl_riuclk_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(io_ready_lvl_riuclk_r1),
        .Q(io_ready_lvl_riuclk_r2),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h6)) 
    io_ready_riuclk_i_1
       (.I0(io_ready_lvl_riuclk_r2),
        .I1(io_ready_lvl_riuclk_r1),
        .O(io_ready_riuclk_i_1_n_0));
  FDRE io_ready_riuclk_reg
       (.C(CLK),
        .CE(1'b1),
        .D(io_ready_riuclk_i_1_n_0),
        .Q(io_ready_riuclk),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFEFFFFFFFEEE)) 
    io_ready_ub_i_1
       (.I0(io_ready_ub_i_2_n_0),
        .I1(io_ready_ub_i_3_n_0),
        .I2(io_ready_ub_i_4_n_0),
        .I3(io_addr_strobe_lvl_riuclk_i_3_n_0),
        .I4(io_ready_ub_i_5_n_0),
        .I5(io_ready_ub_i_6_n_0),
        .O(io_ready_ub_i_1_n_0));
  LUT3 #(
    .INIT(8'h80)) 
    io_ready_ub_i_10
       (.I0(any_clb2riu_wr_wait),
        .I1(\riu2clb_valid_r1_riuclk_reg[19]_1 [1]),
        .I2(\riu2clb_valid_r1_riuclk_reg[19]_1 [0]),
        .O(io_ready_ub_i_10_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    io_ready_ub_i_11
       (.I0(\riu2clb_valid_r1_riuclk_reg[19]_1 [10]),
        .I1(\riu2clb_valid_r1_riuclk_reg[19]_1 [11]),
        .I2(\riu2clb_valid_r1_riuclk_reg[19]_1 [8]),
        .I3(\riu2clb_valid_r1_riuclk_reg[19]_1 [9]),
        .I4(\riu2clb_valid_r1_riuclk_reg[19]_1 [13]),
        .I5(\riu2clb_valid_r1_riuclk_reg[19]_1 [12]),
        .O(io_ready_ub_i_11_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    io_ready_ub_i_12
       (.I0(\riu2clb_valid_r1_riuclk_reg[19]_1 [16]),
        .I1(\riu2clb_valid_r1_riuclk_reg[19]_1 [17]),
        .I2(\riu2clb_valid_r1_riuclk_reg[19]_1 [14]),
        .I3(\riu2clb_valid_r1_riuclk_reg[19]_1 [15]),
        .I4(\riu2clb_valid_r1_riuclk_reg[19]_1 [19]),
        .I5(\riu2clb_valid_r1_riuclk_reg[19]_1 [18]),
        .O(io_ready_ub_i_12_n_0));
  LUT6 #(
    .INIT(64'h040004000F000000)) 
    io_ready_ub_i_2
       (.I0(any_clb2riu_wr_wait),
        .I1(riu_rd_val_r2),
        .I2(io_ready_ub_i_7_n_0),
        .I3(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I4(io_ready_ub_i_8_n_0),
        .I5(sample_gts_flag_i_2_n_0),
        .O(io_ready_ub_i_2_n_0));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    io_ready_ub_i_3
       (.I0(io_ready_ub_i_7_n_0),
        .I1(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .I2(io_ready_ub_i_9_n_0),
        .I3(io_ready_ub_i_10_n_0),
        .I4(io_ready_ub_i_11_n_0),
        .I5(io_ready_ub_i_12_n_0),
        .O(io_ready_ub_i_3_n_0));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    io_ready_ub_i_4
       (.I0(io_ready_riuclk),
        .I1(out[13]),
        .I2(out[14]),
        .I3(out[16]),
        .I4(out[15]),
        .I5(out[12]),
        .O(io_ready_ub_i_4_n_0));
  LUT4 #(
    .INIT(16'hAAA8)) 
    io_ready_ub_i_5
       (.I0(io_ready_riuclk),
        .I1(out[21]),
        .I2(out[22]),
        .I3(out[23]),
        .O(io_ready_ub_i_5_n_0));
  LUT5 #(
    .INIT(32'h00000100)) 
    io_ready_ub_i_6
       (.I0(out[23]),
        .I1(out[22]),
        .I2(out[21]),
        .I3(io_addr_strobe_riuclk),
        .I4(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .O(io_ready_ub_i_6_n_0));
  LUT3 #(
    .INIT(8'hFE)) 
    io_ready_ub_i_7
       (.I0(out[23]),
        .I1(out[22]),
        .I2(out[21]),
        .O(io_ready_ub_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT3 #(
    .INIT(8'h08)) 
    io_ready_ub_i_8
       (.I0(sample_gts_riu),
        .I1(sample_gts_flag),
        .I2(any_clb2riu_wr_wait),
        .O(io_ready_ub_i_8_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    io_ready_ub_i_9
       (.I0(\riu2clb_valid_r1_riuclk_reg[19]_1 [4]),
        .I1(\riu2clb_valid_r1_riuclk_reg[19]_1 [5]),
        .I2(\riu2clb_valid_r1_riuclk_reg[19]_1 [2]),
        .I3(\riu2clb_valid_r1_riuclk_reg[19]_1 [3]),
        .I4(\riu2clb_valid_r1_riuclk_reg[19]_1 [7]),
        .I5(\riu2clb_valid_r1_riuclk_reg[19]_1 [6]),
        .O(io_ready_ub_i_9_n_0));
  FDRE io_ready_ub_reg
       (.C(CLK),
        .CE(1'b1),
        .D(io_ready_ub_i_1_n_0),
        .Q(io_ready_ub),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[0]),
        .Q(\io_write_data_riuclk_reg[31]_0 [0]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[10]),
        .Q(\io_write_data_riuclk_reg[31]_0 [10]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[11]),
        .Q(\io_write_data_riuclk_reg[31]_0 [11]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[12]),
        .Q(\io_write_data_riuclk_reg[31]_0 [12]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[13]),
        .Q(\io_write_data_riuclk_reg[31]_0 [13]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[14]),
        .Q(\io_write_data_riuclk_reg[31]_0 [14]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[15]),
        .Q(\io_write_data_riuclk_reg[31]_0 [15]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[16]),
        .Q(\io_write_data_riuclk_reg[31]_0 [16]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[17]),
        .Q(\io_write_data_riuclk_reg[31]_0 [17]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[18]),
        .Q(\io_write_data_riuclk_reg[31]_0 [18]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[19]),
        .Q(\io_write_data_riuclk_reg[31]_0 [19]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[1]),
        .Q(\io_write_data_riuclk_reg[31]_0 [1]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[20] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[20]),
        .Q(\io_write_data_riuclk_reg[31]_0 [20]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[21] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[21]),
        .Q(\io_write_data_riuclk_reg[31]_0 [21]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[22] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[22]),
        .Q(\io_write_data_riuclk_reg[31]_0 [22]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[23] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[23]),
        .Q(\io_write_data_riuclk_reg[31]_0 [23]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[24] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[24]),
        .Q(\io_write_data_riuclk_reg[31]_0 [24]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[25] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[25]),
        .Q(\io_write_data_riuclk_reg[31]_0 [25]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[26] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[26]),
        .Q(\io_write_data_riuclk_reg[31]_0 [26]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[27] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[27]),
        .Q(\io_write_data_riuclk_reg[31]_0 [27]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[28] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[28]),
        .Q(\io_write_data_riuclk_reg[31]_0 [28]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[29] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[29]),
        .Q(\io_write_data_riuclk_reg[31]_0 [29]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[2]),
        .Q(\io_write_data_riuclk_reg[31]_0 [2]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[30] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[30]),
        .Q(\io_write_data_riuclk_reg[31]_0 [30]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[31] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[31]),
        .Q(\io_write_data_riuclk_reg[31]_0 [31]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[3]),
        .Q(\io_write_data_riuclk_reg[31]_0 [3]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[4]),
        .Q(\io_write_data_riuclk_reg[31]_0 [4]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[5]),
        .Q(\io_write_data_riuclk_reg[31]_0 [5]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[6]),
        .Q(\io_write_data_riuclk_reg[31]_0 [6]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[7]),
        .Q(\io_write_data_riuclk_reg[31]_0 [7]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[8]),
        .Q(\io_write_data_riuclk_reg[31]_0 [8]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \io_write_data_riuclk_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(io_write_data_ub[9]),
        .Q(\io_write_data_riuclk_reg[31]_0 [9]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    io_write_strobe_riuclk_reg
       (.C(CLK),
        .CE(io_addr_strobe_ub),
        .D(io_write_strobe_ub),
        .Q(io_write_strobe_riuclk_reg_0),
        .R(1'b0));
  (* CHECK_LICENSE_TYPE = "ddr4_0_microblaze_mcs,bd_9054,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* x_core_info = "bd_9054,Vivado 2022.2" *) 
  ddr4_0_microblaze_mcs mcs0
       (.Clk(CLK),
        .IO_addr_strobe(io_addr_strobe_ub),
        .IO_address({NLW_mcs0_IO_address_UNCONNECTED[31:30],io_address_ub,NLW_mcs0_IO_address_UNCONNECTED[1:0]}),
        .IO_byte_enable(NLW_mcs0_IO_byte_enable_UNCONNECTED[3:0]),
        .IO_read_data(io_read_data_ub),
        .IO_read_strobe(NLW_mcs0_IO_read_strobe_UNCONNECTED),
        .IO_ready(io_ready_ub),
        .IO_write_data(io_write_data_ub),
        .IO_write_strobe(io_write_strobe_ub),
        .Reset(Reset),
        .TRACE_data_access(NLW_mcs0_TRACE_data_access_UNCONNECTED),
        .TRACE_data_address(NLW_mcs0_TRACE_data_address_UNCONNECTED[0:31]),
        .TRACE_data_byte_enable(NLW_mcs0_TRACE_data_byte_enable_UNCONNECTED[0:3]),
        .TRACE_data_read(NLW_mcs0_TRACE_data_read_UNCONNECTED),
        .TRACE_data_write(NLW_mcs0_TRACE_data_write_UNCONNECTED),
        .TRACE_data_write_value(NLW_mcs0_TRACE_data_write_value_UNCONNECTED[0:31]),
        .TRACE_dcache_hit(NLW_mcs0_TRACE_dcache_hit_UNCONNECTED),
        .TRACE_dcache_rdy(NLW_mcs0_TRACE_dcache_rdy_UNCONNECTED),
        .TRACE_dcache_read(NLW_mcs0_TRACE_dcache_read_UNCONNECTED),
        .TRACE_dcache_req(NLW_mcs0_TRACE_dcache_req_UNCONNECTED),
        .TRACE_delay_slot(NLW_mcs0_TRACE_delay_slot_UNCONNECTED),
        .TRACE_ex_piperun(NLW_mcs0_TRACE_ex_piperun_UNCONNECTED),
        .TRACE_exception_kind(NLW_mcs0_TRACE_exception_kind_UNCONNECTED[0:4]),
        .TRACE_exception_taken(NLW_mcs0_TRACE_exception_taken_UNCONNECTED),
        .TRACE_icache_hit(NLW_mcs0_TRACE_icache_hit_UNCONNECTED),
        .TRACE_icache_rdy(NLW_mcs0_TRACE_icache_rdy_UNCONNECTED),
        .TRACE_icache_req(NLW_mcs0_TRACE_icache_req_UNCONNECTED),
        .TRACE_instruction(NLW_mcs0_TRACE_instruction_UNCONNECTED[0:31]),
        .TRACE_jump_hit(NLW_mcs0_TRACE_jump_hit_UNCONNECTED),
        .TRACE_jump_taken(NLW_mcs0_TRACE_jump_taken_UNCONNECTED),
        .TRACE_mb_halted(NLW_mcs0_TRACE_mb_halted_UNCONNECTED),
        .TRACE_mem_piperun(NLW_mcs0_TRACE_mem_piperun_UNCONNECTED),
        .TRACE_msr_reg(NLW_mcs0_TRACE_msr_reg_UNCONNECTED[0:14]),
        .TRACE_new_reg_value(NLW_mcs0_TRACE_new_reg_value_UNCONNECTED[0:31]),
        .TRACE_of_piperun(NLW_mcs0_TRACE_of_piperun_UNCONNECTED),
        .TRACE_pc(NLW_mcs0_TRACE_pc_UNCONNECTED[0:31]),
        .TRACE_pid_reg(NLW_mcs0_TRACE_pid_reg_UNCONNECTED[0:7]),
        .TRACE_reg_addr(NLW_mcs0_TRACE_reg_addr_UNCONNECTED[0:4]),
        .TRACE_reg_write(NLW_mcs0_TRACE_reg_write_UNCONNECTED),
        .TRACE_valid_instr(NLW_mcs0_TRACE_valid_instr_UNCONNECTED));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [0]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [0]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [10]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [10]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [11]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [11]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [12]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [12]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [13]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [13]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [14]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [14]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [15]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [15]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[16] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [16]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [16]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[17] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [17]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [17]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[18] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [18]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [18]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[19] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [19]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [19]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [1]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [1]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [2]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [2]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [3]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [3]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [4]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [4]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [5]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [5]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [6]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [6]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [7]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [7]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [8]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [8]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \riu2clb_valid_r1_riuclk_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\riu2clb_valid_r1_riuclk_reg[19]_1 [9]),
        .Q(\riu2clb_valid_r1_riuclk_reg[19]_0 [9]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE riu_clk_rst_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(riu_clk_rst),
        .Q(riu_clk_rst_r1),
        .R(1'b0));
  SRL16E riu_rd_val_r1_reg_srl3
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(CLK),
        .D(riu_rd_val0),
        .Q(riu_rd_val_r1_reg_srl3_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    riu_rd_val_r1_reg_srl3_i_1
       (.I0(io_addr_strobe_vld_riuclk),
        .I1(io_write_strobe_riuclk_reg_0),
        .O(riu_rd_val0));
  FDRE riu_rd_val_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(riu_rd_val_r1_reg_srl3_n_0),
        .Q(riu_rd_val_r2),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT4 #(
    .INIT(16'h4F44)) 
    sample_gts_flag_i_1
       (.I0(sample_gts_flag_i_2_n_0),
        .I1(riu_rd_val_r2),
        .I2(sample_gts_riu),
        .I3(sample_gts_flag),
        .O(sample_gts_flag_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    sample_gts_flag_i_2
       (.I0(riu_addr_cal[4]),
        .I1(riu_addr_cal[5]),
        .I2(riu_addr_cal[2]),
        .I3(riu_addr_cal[3]),
        .I4(riu_addr_cal[1]),
        .I5(riu_addr_cal[0]),
        .O(sample_gts_flag_i_2_n_0));
  FDRE sample_gts_flag_reg
       (.C(CLK),
        .CE(1'b1),
        .D(sample_gts_flag_i_1_n_0),
        .Q(sample_gts_flag),
        .R(Reset));
  FDRE sample_gts_riu_reg
       (.C(CLK),
        .CE(1'b1),
        .D(sample_gts),
        .Q(sample_gts_riu),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFB08)) 
    ub_rst_out_riuclk_i_1
       (.I0(\io_write_data_riuclk_reg[31]_0 [0]),
        .I1(ub_rst_out_riuclk_i_2_n_0),
        .I2(io_addr_strobe_lvl_riuclk_i_3_n_0),
        .I3(ub_rst_out_riuclk),
        .O(ub_rst_out_riuclk_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000001000000)) 
    ub_rst_out_riuclk_i_2
       (.I0(out[23]),
        .I1(out[22]),
        .I2(out[21]),
        .I3(io_write_strobe_riuclk_reg_0),
        .I4(io_addr_strobe_riuclk),
        .I5(io_addr_strobe_clb2riu_riuclk_inferred_i_2_n_0),
        .O(ub_rst_out_riuclk_i_2_n_0));
  FDRE ub_rst_out_riuclk_reg
       (.C(CLK),
        .CE(1'b1),
        .D(ub_rst_out_riuclk_i_1_n_0),
        .Q(ub_rst_out_riuclk),
        .R(Reset));
endmodule

module ddr4_0_ddr4_mem_intfc
   (pll_lock,
    sys_clk_in,
    mmcm_clk_in,
    c0_ddr4_act_n,
    c0_ddr4_adr,
    c0_ddr4_ba,
    c0_ddr4_bg,
    c0_ddr4_cke,
    c0_ddr4_odt,
    c0_ddr4_cs_n,
    c0_ddr4_ck_t,
    c0_ddr4_ck_c,
    c0_ddr4_reset_n,
    dbg_bus,
    sl_oport_o,
    c0_init_calib_complete,
    c0_ddr4_app_wdf_rdy,
    c0_ddr4_app_rdy,
    ub_initDone,
    c0_ddr4_app_rd_data_valid,
    c0_ddr4_app_rd_data_end,
    c0_ddr4_app_rd_data,
    c0_ddr4_dm_dbi_n,
    c0_ddr4_dq,
    c0_ddr4_dqs_c,
    c0_ddr4_dqs_t,
    c0_sys_clk_p,
    c0_sys_clk_n,
    mmcm_lock,
    pllGate,
    \SYNC[19].sync_reg_reg[1] ,
    SR,
    CLK,
    riu_clk_rst,
    out,
    Reset,
    c0_ddr4_app_wdf_wren,
    c0_ddr4_app_wdf_end,
    \calSt_reg[0] ,
    c0_ddr4_app_addr,
    c0_ddr4_app_cmd,
    c0_ddr4_app_wdf_data,
    c0_ddr4_app_wdf_mask,
    c0_ddr4_app_en);
  output pll_lock;
  output sys_clk_in;
  output mmcm_clk_in;
  output c0_ddr4_act_n;
  output [16:0]c0_ddr4_adr;
  output [1:0]c0_ddr4_ba;
  output [0:0]c0_ddr4_bg;
  output [0:0]c0_ddr4_cke;
  output [0:0]c0_ddr4_odt;
  output [0:0]c0_ddr4_cs_n;
  output [0:0]c0_ddr4_ck_t;
  output [0:0]c0_ddr4_ck_c;
  output c0_ddr4_reset_n;
  output [511:0]dbg_bus;
  output [16:0]sl_oport_o;
  output c0_init_calib_complete;
  output c0_ddr4_app_wdf_rdy;
  output c0_ddr4_app_rdy;
  output ub_initDone;
  output c0_ddr4_app_rd_data_valid;
  output c0_ddr4_app_rd_data_end;
  output [511:0]c0_ddr4_app_rd_data;
  inout [7:0]c0_ddr4_dm_dbi_n;
  inout [63:0]c0_ddr4_dq;
  inout [7:0]c0_ddr4_dqs_c;
  inout [7:0]c0_ddr4_dqs_t;
  input c0_sys_clk_p;
  input c0_sys_clk_n;
  input mmcm_lock;
  input pllGate;
  input \SYNC[19].sync_reg_reg[1] ;
  input [0:0]SR;
  input CLK;
  input riu_clk_rst;
  input [36:0]out;
  input Reset;
  input c0_ddr4_app_wdf_wren;
  input c0_ddr4_app_wdf_end;
  input \calSt_reg[0] ;
  input [26:0]c0_ddr4_app_addr;
  input [2:0]c0_ddr4_app_cmd;
  input [511:0]c0_ddr4_app_wdf_data;
  input [63:0]c0_ddr4_app_wdf_mask;
  input c0_ddr4_app_en;

  wire CLK;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire LMB_CE_r1;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire LMB_CE_r2;
  wire LMB_CE_riu;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire LMB_UE_r1;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire LMB_UE_r2;
  wire LMB_UE_riu;
  wire Reset;
  wire [0:0]SR;
  wire \SYNC[19].sync_reg_reg[1] ;
  wire accept_ns;
  wire [1:0]bank;
  wire [8:0]bisc_byte;
  wire bisc_complete;
  wire bisc_complete_riuclk;
  wire c0_ddr4_act_n;
  wire [16:0]c0_ddr4_adr;
  wire [26:0]c0_ddr4_app_addr;
  wire [2:0]c0_ddr4_app_cmd;
  wire c0_ddr4_app_en;
  wire [511:0]c0_ddr4_app_rd_data;
  wire c0_ddr4_app_rd_data_end;
  wire c0_ddr4_app_rd_data_valid;
  wire c0_ddr4_app_rdy;
  wire [511:0]c0_ddr4_app_wdf_data;
  wire c0_ddr4_app_wdf_end;
  wire [63:0]c0_ddr4_app_wdf_mask;
  wire c0_ddr4_app_wdf_rdy;
  wire c0_ddr4_app_wdf_wren;
  wire [1:0]c0_ddr4_ba;
  wire [0:0]c0_ddr4_bg;
  wire [0:0]c0_ddr4_ck_c;
  wire [0:0]c0_ddr4_ck_t;
  wire [0:0]c0_ddr4_cke;
  wire [0:0]c0_ddr4_cs_n;
  wire [7:0]c0_ddr4_dm_dbi_n;
  wire [63:0]c0_ddr4_dq;
  wire [7:0]c0_ddr4_dqs_c;
  wire [7:0]c0_ddr4_dqs_t;
  wire [0:0]c0_ddr4_odt;
  wire c0_ddr4_reset_n;
  wire c0_init_calib_complete;
  wire c0_sys_clk_n;
  wire c0_sys_clk_p;
  wire calDone;
  wire \calSt_reg[0] ;
  wire calWrCAS;
  wire [126:113]cal_ADR;
  wire [7:7]cal_BA;
  wire [6:1]cal_CS_n;
  wire [7:0]cal_RESET_n;
  wire [7:7]cal_oe_dis_low;
  wire [7:7]cal_oe_dis_upp;
  wire [63:0]ch0_mcal_DMOut_n;
  wire [511:0]ch0_mcal_DQOut;
  wire [103:0]ch0_mcal_clb2phy_fifo_rden;
  wire [31:0]ch0_mcal_clb2phy_rden_low;
  wire [31:0]ch0_mcal_clb2phy_rden_upp;
  wire [31:28]ch0_mcal_clb2phy_t_b_low;
  wire [31:28]ch0_mcal_clb2phy_t_b_upp;
  wire [103:0]ch1_mcal_clb2phy_fifo_rden;
  wire [2:0]cmd;
  wire [19:0]cmdBuf;
  wire [9:3]col;
  wire [4:0]dBufAdr;
  wire [511:0]dbg_bus;
  wire [23:16]dbg_out_phy;
  wire en_vtc;
  (* DONT_TOUCH *) wire en_vtc_in;
  wire en_vtc_riuclk;
  wire fab_rst_sync;
  wire [3:3]grAccept_ns;
  wire [0:0]group;
  wire io_addr_strobe;
  wire io_addr_strobe_clb2riu_riuclk;
  wire io_addr_strobe_lvl;
  wire io_addr_strobe_lvl_riuclk;
  wire [23:0]io_address;
  wire [31:0]io_address_riuclk;
  wire [31:0]io_read_data;
  wire [31:0]io_read_data_riuclk;
  wire io_ready_lvl;
  wire io_ready_lvl_riuclk;
  wire [31:0]io_write_data;
  wire [31:0]io_write_data_riuclk;
  wire io_write_strobe;
  wire io_write_strobe_riuclk;
  wire mcCasSlot2;
  wire mcRdCAS;
  wire mcWrCAS;
  wire [131:1]mc_ADR;
  wire [15:1]mc_BA;
  wire [7:1]mc_BG;
  wire [7:5]mc_CKE;
  wire [7:7]mc_CS_n;
  wire [7:3]mc_ODT;
  wire [7:0]mcal_ACT_n;
  wire [135:0]mcal_ADR;
  wire [15:0]mcal_BA;
  wire [7:0]mcal_BG;
  wire [7:0]mcal_CS_n;
  wire [63:0]mcal_DMIn_n;
  wire [511:0]mcal_DQIn;
  wire [7:0]mcal_ODT;
  wire [7:0]mcal_PAR;
  wire [55:0]mcal_rd_vref_value;
  wire mmcm_clk_in;
  wire mmcm_lock;
  wire [36:0]out;
  wire [7:7]p_0_in_0;
  wire per_rd_done;
  wire [19:0]phy2clb_fixdly_rdy_low_riuclk;
  wire [19:0]phy2clb_fixdly_rdy_upp_riuclk;
  wire [19:0]phy2clb_phy_rdy_low_riuclk;
  wire [19:0]phy2clb_phy_rdy_upp_riuclk;
  wire [7:0]phy2clb_rd_dq_bits;
  wire phy_ready;
  wire phy_ready_riuclk;
  wire pllGate;
  wire pll_lock;
  wire [3:0]ram_init_addr;
  wire [1:1]ram_init_done_r;
  wire [4:0]rd_data_addr_phy2mc;
  wire rd_data_en_phy2mc;
  wire [511:0]rd_data_phy2mc_xif;
  wire [19:0]riu2clb_valid;
  wire [19:0]riu2clb_valid_r1_riuclk;
  wire [19:0]riu2clb_valid_riuclk;
  wire [15:0]riu2clb_vld_read_data;
  wire [5:0]riu_addr_cal;
  wire riu_clk_rst;
  wire [7:0]riu_nibble_8;
  wire [16:0]row_mc_phy;
  (* DONT_TOUCH *) wire rst_r1;
  wire sample_gts;
  wire [16:0]sl_oport_o;
  wire sys_clk_in;
  wire [8:0]\u_ddr_cal/bramA_do ;
  wire [11:0]\u_ddr_cal/config_rd_data ;
  wire \u_ddr_cal/initDone ;
  wire \u_ddr_cal/u_ddr_cal_addr_decode/a_b_cmd_sel_start ;
  wire \u_ddr_cal/u_ddr_cal_addr_decode/a_b_cmd_sel_start0 ;
  wire [31:0]\u_ddr_cal/u_ddr_cal_addr_decode/addr_dec_to_mb_data ;
  wire \u_ddr_cal/u_ddr_cal_addr_decode/cal_ACT_n_A ;
  wire [31:0]\u_ddr_cal/u_ddr_cal_addr_decode/cal_timer_reg ;
  wire \u_ddr_cal/u_ddr_cal_addr_decode/clear_gt_data_ready_flag ;
  wire \u_ddr_cal/u_ddr_cal_addr_decode/cnt_clr ;
  wire \u_ddr_cal/u_ddr_cal_addr_decode/cnt_clr_access ;
  wire [0:0]\u_ddr_cal/u_ddr_cal_addr_decode/cplx_config0_out ;
  wire [31:1]\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log30 ;
  wire [31:1]\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log74 ;
  wire \u_ddr_cal/u_ddr_cal_addr_decode/gt_data_ready_flag ;
  wire \u_ddr_cal/u_ddr_cal_addr_decode/gt_data_ready_flag_nxt ;
  wire \u_ddr_cal/u_ddr_cal_addr_decode/lrdimm_cmp_clr ;
  wire \u_ddr_cal/u_ddr_cal_addr_decode/lrdimm_cmp_en ;
  wire [7:0]\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1 ;
  wire [48:2]\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 ;
  wire [0:0]\u_ddr_cal/u_ddr_cal_addr_decode/p_1_in ;
  wire \u_ddr_cal/u_ddr_cal_addr_decode/p_52_in ;
  wire [55:6]\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out ;
  wire [47:32]\u_ddr_cal/u_ddr_cal_addr_decode/uppCL00 ;
  wire [47:32]\u_ddr_cal/u_ddr_cal_addr_decode/uppCL10 ;
  wire [47:32]\u_ddr_cal/u_ddr_cal_addr_decode/uppCL20 ;
  wire [47:32]\u_ddr_cal/u_ddr_cal_addr_decode/uppCL30 ;
  wire [11:0]\u_ddr_cal/u_ddr_config_rom/mem ;
  wire \u_ddr_cal/ub_calDone ;
  wire [7:1]\u_ddr_cal/ub_cal_RESET_n ;
  wire \u_ddr_cal/ub_xsdb_rd_en ;
  wire u_ddr_cal_top_n_1000;
  wire u_ddr_cal_top_n_1001;
  wire u_ddr_cal_top_n_1002;
  wire u_ddr_cal_top_n_1003;
  wire u_ddr_cal_top_n_1004;
  wire u_ddr_cal_top_n_1005;
  wire u_ddr_cal_top_n_1008;
  wire u_ddr_cal_top_n_1009;
  wire u_ddr_cal_top_n_1010;
  wire u_ddr_cal_top_n_1011;
  wire u_ddr_cal_top_n_1012;
  wire u_ddr_cal_top_n_1013;
  wire u_ddr_cal_top_n_1016;
  wire u_ddr_cal_top_n_1017;
  wire u_ddr_cal_top_n_1018;
  wire u_ddr_cal_top_n_1019;
  wire u_ddr_cal_top_n_1020;
  wire u_ddr_cal_top_n_1021;
  wire u_ddr_cal_top_n_1024;
  wire u_ddr_cal_top_n_1025;
  wire u_ddr_cal_top_n_1026;
  wire u_ddr_cal_top_n_1027;
  wire u_ddr_cal_top_n_1028;
  wire u_ddr_cal_top_n_1029;
  wire u_ddr_cal_top_n_1032;
  wire u_ddr_cal_top_n_1033;
  wire u_ddr_cal_top_n_1034;
  wire u_ddr_cal_top_n_1035;
  wire u_ddr_cal_top_n_1036;
  wire u_ddr_cal_top_n_1037;
  wire u_ddr_cal_top_n_1040;
  wire u_ddr_cal_top_n_1041;
  wire u_ddr_cal_top_n_1042;
  wire u_ddr_cal_top_n_1043;
  wire u_ddr_cal_top_n_1044;
  wire u_ddr_cal_top_n_1045;
  wire u_ddr_cal_top_n_1048;
  wire u_ddr_cal_top_n_1049;
  wire u_ddr_cal_top_n_1050;
  wire u_ddr_cal_top_n_1051;
  wire u_ddr_cal_top_n_1052;
  wire u_ddr_cal_top_n_1053;
  wire u_ddr_cal_top_n_1056;
  wire u_ddr_cal_top_n_1057;
  wire u_ddr_cal_top_n_1058;
  wire u_ddr_cal_top_n_1059;
  wire u_ddr_cal_top_n_1060;
  wire u_ddr_cal_top_n_1061;
  wire u_ddr_cal_top_n_1064;
  wire u_ddr_cal_top_n_1065;
  wire u_ddr_cal_top_n_1066;
  wire u_ddr_cal_top_n_1067;
  wire u_ddr_cal_top_n_1068;
  wire u_ddr_cal_top_n_1069;
  wire u_ddr_cal_top_n_1072;
  wire u_ddr_cal_top_n_1073;
  wire u_ddr_cal_top_n_1074;
  wire u_ddr_cal_top_n_1075;
  wire u_ddr_cal_top_n_1076;
  wire u_ddr_cal_top_n_1077;
  wire u_ddr_cal_top_n_1080;
  wire u_ddr_cal_top_n_1081;
  wire u_ddr_cal_top_n_1082;
  wire u_ddr_cal_top_n_1083;
  wire u_ddr_cal_top_n_1084;
  wire u_ddr_cal_top_n_1085;
  wire u_ddr_cal_top_n_1088;
  wire u_ddr_cal_top_n_1089;
  wire u_ddr_cal_top_n_1090;
  wire u_ddr_cal_top_n_1091;
  wire u_ddr_cal_top_n_1092;
  wire u_ddr_cal_top_n_1093;
  wire u_ddr_cal_top_n_1096;
  wire u_ddr_cal_top_n_1097;
  wire u_ddr_cal_top_n_1098;
  wire u_ddr_cal_top_n_1099;
  wire u_ddr_cal_top_n_1100;
  wire u_ddr_cal_top_n_1101;
  wire u_ddr_cal_top_n_1104;
  wire u_ddr_cal_top_n_1105;
  wire u_ddr_cal_top_n_1106;
  wire u_ddr_cal_top_n_1107;
  wire u_ddr_cal_top_n_1108;
  wire u_ddr_cal_top_n_1109;
  wire u_ddr_cal_top_n_1112;
  wire u_ddr_cal_top_n_1113;
  wire u_ddr_cal_top_n_1114;
  wire u_ddr_cal_top_n_1115;
  wire u_ddr_cal_top_n_1116;
  wire u_ddr_cal_top_n_1117;
  wire u_ddr_cal_top_n_1120;
  wire u_ddr_cal_top_n_1121;
  wire u_ddr_cal_top_n_1122;
  wire u_ddr_cal_top_n_1123;
  wire u_ddr_cal_top_n_1124;
  wire u_ddr_cal_top_n_1125;
  wire u_ddr_cal_top_n_1128;
  wire u_ddr_cal_top_n_1129;
  wire u_ddr_cal_top_n_1130;
  wire u_ddr_cal_top_n_1131;
  wire u_ddr_cal_top_n_1132;
  wire u_ddr_cal_top_n_1133;
  wire u_ddr_cal_top_n_1136;
  wire u_ddr_cal_top_n_1137;
  wire u_ddr_cal_top_n_1138;
  wire u_ddr_cal_top_n_1139;
  wire u_ddr_cal_top_n_1140;
  wire u_ddr_cal_top_n_1141;
  wire u_ddr_cal_top_n_1144;
  wire u_ddr_cal_top_n_1145;
  wire u_ddr_cal_top_n_1146;
  wire u_ddr_cal_top_n_1147;
  wire u_ddr_cal_top_n_1148;
  wire u_ddr_cal_top_n_1149;
  wire u_ddr_cal_top_n_1152;
  wire u_ddr_cal_top_n_1153;
  wire u_ddr_cal_top_n_1154;
  wire u_ddr_cal_top_n_1155;
  wire u_ddr_cal_top_n_1156;
  wire u_ddr_cal_top_n_1157;
  wire u_ddr_cal_top_n_1160;
  wire u_ddr_cal_top_n_1161;
  wire u_ddr_cal_top_n_1162;
  wire u_ddr_cal_top_n_1163;
  wire u_ddr_cal_top_n_1164;
  wire u_ddr_cal_top_n_1165;
  wire u_ddr_cal_top_n_1168;
  wire u_ddr_cal_top_n_1169;
  wire u_ddr_cal_top_n_1170;
  wire u_ddr_cal_top_n_1171;
  wire u_ddr_cal_top_n_1172;
  wire u_ddr_cal_top_n_1173;
  wire u_ddr_cal_top_n_1176;
  wire u_ddr_cal_top_n_1177;
  wire u_ddr_cal_top_n_1178;
  wire u_ddr_cal_top_n_1179;
  wire u_ddr_cal_top_n_1180;
  wire u_ddr_cal_top_n_1181;
  wire u_ddr_cal_top_n_1184;
  wire u_ddr_cal_top_n_1185;
  wire u_ddr_cal_top_n_1186;
  wire u_ddr_cal_top_n_1187;
  wire u_ddr_cal_top_n_1188;
  wire u_ddr_cal_top_n_1189;
  wire u_ddr_cal_top_n_1192;
  wire u_ddr_cal_top_n_1193;
  wire u_ddr_cal_top_n_1194;
  wire u_ddr_cal_top_n_1195;
  wire u_ddr_cal_top_n_1196;
  wire u_ddr_cal_top_n_1197;
  wire u_ddr_cal_top_n_1200;
  wire u_ddr_cal_top_n_1201;
  wire u_ddr_cal_top_n_1202;
  wire u_ddr_cal_top_n_1203;
  wire u_ddr_cal_top_n_1204;
  wire u_ddr_cal_top_n_1205;
  wire u_ddr_cal_top_n_1208;
  wire u_ddr_cal_top_n_1209;
  wire u_ddr_cal_top_n_1210;
  wire u_ddr_cal_top_n_1211;
  wire u_ddr_cal_top_n_1212;
  wire u_ddr_cal_top_n_1213;
  wire u_ddr_cal_top_n_1216;
  wire u_ddr_cal_top_n_1217;
  wire u_ddr_cal_top_n_1218;
  wire u_ddr_cal_top_n_1219;
  wire u_ddr_cal_top_n_1220;
  wire u_ddr_cal_top_n_1221;
  wire u_ddr_cal_top_n_1224;
  wire u_ddr_cal_top_n_1225;
  wire u_ddr_cal_top_n_1226;
  wire u_ddr_cal_top_n_1227;
  wire u_ddr_cal_top_n_1228;
  wire u_ddr_cal_top_n_1229;
  wire u_ddr_cal_top_n_1232;
  wire u_ddr_cal_top_n_1233;
  wire u_ddr_cal_top_n_1234;
  wire u_ddr_cal_top_n_1235;
  wire u_ddr_cal_top_n_1236;
  wire u_ddr_cal_top_n_1237;
  wire u_ddr_cal_top_n_1240;
  wire u_ddr_cal_top_n_1241;
  wire u_ddr_cal_top_n_1242;
  wire u_ddr_cal_top_n_1243;
  wire u_ddr_cal_top_n_1244;
  wire u_ddr_cal_top_n_1245;
  wire u_ddr_cal_top_n_1248;
  wire u_ddr_cal_top_n_1249;
  wire u_ddr_cal_top_n_1250;
  wire u_ddr_cal_top_n_1251;
  wire u_ddr_cal_top_n_1252;
  wire u_ddr_cal_top_n_1253;
  wire u_ddr_cal_top_n_1256;
  wire u_ddr_cal_top_n_1257;
  wire u_ddr_cal_top_n_1258;
  wire u_ddr_cal_top_n_1259;
  wire u_ddr_cal_top_n_1260;
  wire u_ddr_cal_top_n_1261;
  wire u_ddr_cal_top_n_1264;
  wire u_ddr_cal_top_n_1265;
  wire u_ddr_cal_top_n_1266;
  wire u_ddr_cal_top_n_1267;
  wire u_ddr_cal_top_n_1268;
  wire u_ddr_cal_top_n_1269;
  wire u_ddr_cal_top_n_1272;
  wire u_ddr_cal_top_n_1273;
  wire u_ddr_cal_top_n_1274;
  wire u_ddr_cal_top_n_1275;
  wire u_ddr_cal_top_n_1276;
  wire u_ddr_cal_top_n_1277;
  wire u_ddr_cal_top_n_1280;
  wire u_ddr_cal_top_n_1281;
  wire u_ddr_cal_top_n_1282;
  wire u_ddr_cal_top_n_1283;
  wire u_ddr_cal_top_n_1284;
  wire u_ddr_cal_top_n_1285;
  wire u_ddr_cal_top_n_1288;
  wire u_ddr_cal_top_n_1289;
  wire u_ddr_cal_top_n_1290;
  wire u_ddr_cal_top_n_1291;
  wire u_ddr_cal_top_n_1292;
  wire u_ddr_cal_top_n_1293;
  wire u_ddr_cal_top_n_1296;
  wire u_ddr_cal_top_n_1297;
  wire u_ddr_cal_top_n_1298;
  wire u_ddr_cal_top_n_1299;
  wire u_ddr_cal_top_n_1300;
  wire u_ddr_cal_top_n_1301;
  wire u_ddr_cal_top_n_1304;
  wire u_ddr_cal_top_n_1305;
  wire u_ddr_cal_top_n_1306;
  wire u_ddr_cal_top_n_1307;
  wire u_ddr_cal_top_n_1308;
  wire u_ddr_cal_top_n_1309;
  wire u_ddr_cal_top_n_1312;
  wire u_ddr_cal_top_n_1313;
  wire u_ddr_cal_top_n_1314;
  wire u_ddr_cal_top_n_1315;
  wire u_ddr_cal_top_n_1316;
  wire u_ddr_cal_top_n_1317;
  wire u_ddr_cal_top_n_1320;
  wire u_ddr_cal_top_n_1321;
  wire u_ddr_cal_top_n_1322;
  wire u_ddr_cal_top_n_1323;
  wire u_ddr_cal_top_n_1324;
  wire u_ddr_cal_top_n_1325;
  wire u_ddr_cal_top_n_1328;
  wire u_ddr_cal_top_n_1329;
  wire u_ddr_cal_top_n_1330;
  wire u_ddr_cal_top_n_1331;
  wire u_ddr_cal_top_n_1332;
  wire u_ddr_cal_top_n_1333;
  wire u_ddr_cal_top_n_1336;
  wire u_ddr_cal_top_n_1337;
  wire u_ddr_cal_top_n_1338;
  wire u_ddr_cal_top_n_1339;
  wire u_ddr_cal_top_n_1340;
  wire u_ddr_cal_top_n_1341;
  wire u_ddr_cal_top_n_1344;
  wire u_ddr_cal_top_n_1345;
  wire u_ddr_cal_top_n_1346;
  wire u_ddr_cal_top_n_1347;
  wire u_ddr_cal_top_n_1348;
  wire u_ddr_cal_top_n_1349;
  wire u_ddr_cal_top_n_1352;
  wire u_ddr_cal_top_n_1353;
  wire u_ddr_cal_top_n_1354;
  wire u_ddr_cal_top_n_1355;
  wire u_ddr_cal_top_n_1356;
  wire u_ddr_cal_top_n_1357;
  wire u_ddr_cal_top_n_1360;
  wire u_ddr_cal_top_n_1361;
  wire u_ddr_cal_top_n_1362;
  wire u_ddr_cal_top_n_1363;
  wire u_ddr_cal_top_n_1364;
  wire u_ddr_cal_top_n_1365;
  wire u_ddr_cal_top_n_1368;
  wire u_ddr_cal_top_n_1369;
  wire u_ddr_cal_top_n_1370;
  wire u_ddr_cal_top_n_1371;
  wire u_ddr_cal_top_n_1372;
  wire u_ddr_cal_top_n_1373;
  wire u_ddr_cal_top_n_1376;
  wire u_ddr_cal_top_n_1377;
  wire u_ddr_cal_top_n_1378;
  wire u_ddr_cal_top_n_1379;
  wire u_ddr_cal_top_n_1380;
  wire u_ddr_cal_top_n_1381;
  wire u_ddr_cal_top_n_1384;
  wire u_ddr_cal_top_n_1385;
  wire u_ddr_cal_top_n_1386;
  wire u_ddr_cal_top_n_1387;
  wire u_ddr_cal_top_n_1388;
  wire u_ddr_cal_top_n_1389;
  wire u_ddr_cal_top_n_1392;
  wire u_ddr_cal_top_n_1393;
  wire u_ddr_cal_top_n_1394;
  wire u_ddr_cal_top_n_1395;
  wire u_ddr_cal_top_n_1396;
  wire u_ddr_cal_top_n_1397;
  wire u_ddr_cal_top_n_1400;
  wire u_ddr_cal_top_n_1401;
  wire u_ddr_cal_top_n_1402;
  wire u_ddr_cal_top_n_1403;
  wire u_ddr_cal_top_n_1404;
  wire u_ddr_cal_top_n_1405;
  wire u_ddr_cal_top_n_1408;
  wire u_ddr_cal_top_n_1409;
  wire u_ddr_cal_top_n_1410;
  wire u_ddr_cal_top_n_1411;
  wire u_ddr_cal_top_n_1412;
  wire u_ddr_cal_top_n_1413;
  wire u_ddr_cal_top_n_1416;
  wire u_ddr_cal_top_n_1417;
  wire u_ddr_cal_top_n_1418;
  wire u_ddr_cal_top_n_1419;
  wire u_ddr_cal_top_n_1420;
  wire u_ddr_cal_top_n_1421;
  wire u_ddr_cal_top_n_1424;
  wire u_ddr_cal_top_n_1425;
  wire u_ddr_cal_top_n_1426;
  wire u_ddr_cal_top_n_1427;
  wire u_ddr_cal_top_n_1428;
  wire u_ddr_cal_top_n_1429;
  wire u_ddr_cal_top_n_1432;
  wire u_ddr_cal_top_n_1433;
  wire u_ddr_cal_top_n_1434;
  wire u_ddr_cal_top_n_1435;
  wire u_ddr_cal_top_n_1436;
  wire u_ddr_cal_top_n_1437;
  wire u_ddr_cal_top_n_1440;
  wire u_ddr_cal_top_n_1441;
  wire u_ddr_cal_top_n_1442;
  wire u_ddr_cal_top_n_1443;
  wire u_ddr_cal_top_n_1444;
  wire u_ddr_cal_top_n_1445;
  wire u_ddr_cal_top_n_1448;
  wire u_ddr_cal_top_n_1449;
  wire u_ddr_cal_top_n_1450;
  wire u_ddr_cal_top_n_1451;
  wire u_ddr_cal_top_n_1452;
  wire u_ddr_cal_top_n_1453;
  wire u_ddr_cal_top_n_1456;
  wire u_ddr_cal_top_n_1457;
  wire u_ddr_cal_top_n_1458;
  wire u_ddr_cal_top_n_1459;
  wire u_ddr_cal_top_n_1460;
  wire u_ddr_cal_top_n_1461;
  wire u_ddr_cal_top_n_1464;
  wire u_ddr_cal_top_n_1465;
  wire u_ddr_cal_top_n_1466;
  wire u_ddr_cal_top_n_1467;
  wire u_ddr_cal_top_n_1468;
  wire u_ddr_cal_top_n_1469;
  wire u_ddr_cal_top_n_1472;
  wire u_ddr_cal_top_n_1473;
  wire u_ddr_cal_top_n_1474;
  wire u_ddr_cal_top_n_1475;
  wire u_ddr_cal_top_n_1476;
  wire u_ddr_cal_top_n_1477;
  wire u_ddr_cal_top_n_1480;
  wire u_ddr_cal_top_n_1481;
  wire u_ddr_cal_top_n_1482;
  wire u_ddr_cal_top_n_1483;
  wire u_ddr_cal_top_n_1484;
  wire u_ddr_cal_top_n_1485;
  wire u_ddr_cal_top_n_1488;
  wire u_ddr_cal_top_n_1489;
  wire u_ddr_cal_top_n_1490;
  wire u_ddr_cal_top_n_1491;
  wire u_ddr_cal_top_n_1492;
  wire u_ddr_cal_top_n_1493;
  wire u_ddr_cal_top_n_1496;
  wire u_ddr_cal_top_n_1497;
  wire u_ddr_cal_top_n_1498;
  wire u_ddr_cal_top_n_1499;
  wire u_ddr_cal_top_n_1500;
  wire u_ddr_cal_top_n_1501;
  wire u_ddr_cal_top_n_1504;
  wire u_ddr_cal_top_n_1505;
  wire u_ddr_cal_top_n_1506;
  wire u_ddr_cal_top_n_1507;
  wire u_ddr_cal_top_n_1508;
  wire u_ddr_cal_top_n_1509;
  wire u_ddr_cal_top_n_1512;
  wire u_ddr_cal_top_n_1513;
  wire u_ddr_cal_top_n_1514;
  wire u_ddr_cal_top_n_1515;
  wire u_ddr_cal_top_n_1516;
  wire u_ddr_cal_top_n_1517;
  wire u_ddr_cal_top_n_1520;
  wire u_ddr_cal_top_n_1521;
  wire u_ddr_cal_top_n_1522;
  wire u_ddr_cal_top_n_1523;
  wire u_ddr_cal_top_n_1524;
  wire u_ddr_cal_top_n_1525;
  wire u_ddr_cal_top_n_1528;
  wire u_ddr_cal_top_n_1529;
  wire u_ddr_cal_top_n_1530;
  wire u_ddr_cal_top_n_1531;
  wire u_ddr_cal_top_n_1532;
  wire u_ddr_cal_top_n_1533;
  wire u_ddr_cal_top_n_1536;
  wire u_ddr_cal_top_n_1537;
  wire u_ddr_cal_top_n_1538;
  wire u_ddr_cal_top_n_1539;
  wire u_ddr_cal_top_n_1540;
  wire u_ddr_cal_top_n_1541;
  wire u_ddr_cal_top_n_1544;
  wire u_ddr_cal_top_n_1545;
  wire u_ddr_cal_top_n_1546;
  wire u_ddr_cal_top_n_1547;
  wire u_ddr_cal_top_n_1548;
  wire u_ddr_cal_top_n_1549;
  wire u_ddr_cal_top_n_1552;
  wire u_ddr_cal_top_n_1553;
  wire u_ddr_cal_top_n_1554;
  wire u_ddr_cal_top_n_1555;
  wire u_ddr_cal_top_n_1556;
  wire u_ddr_cal_top_n_1557;
  wire u_ddr_cal_top_n_1560;
  wire u_ddr_cal_top_n_1561;
  wire u_ddr_cal_top_n_1562;
  wire u_ddr_cal_top_n_1563;
  wire u_ddr_cal_top_n_1564;
  wire u_ddr_cal_top_n_1565;
  wire u_ddr_cal_top_n_1568;
  wire u_ddr_cal_top_n_1569;
  wire u_ddr_cal_top_n_1570;
  wire u_ddr_cal_top_n_1571;
  wire u_ddr_cal_top_n_1572;
  wire u_ddr_cal_top_n_1573;
  wire u_ddr_cal_top_n_1576;
  wire u_ddr_cal_top_n_1577;
  wire u_ddr_cal_top_n_1578;
  wire u_ddr_cal_top_n_1579;
  wire u_ddr_cal_top_n_1580;
  wire u_ddr_cal_top_n_1581;
  wire u_ddr_cal_top_n_1584;
  wire u_ddr_cal_top_n_1585;
  wire u_ddr_cal_top_n_1586;
  wire u_ddr_cal_top_n_1587;
  wire u_ddr_cal_top_n_1588;
  wire u_ddr_cal_top_n_1589;
  wire u_ddr_cal_top_n_1592;
  wire u_ddr_cal_top_n_1593;
  wire u_ddr_cal_top_n_1594;
  wire u_ddr_cal_top_n_1595;
  wire u_ddr_cal_top_n_1596;
  wire u_ddr_cal_top_n_1597;
  wire u_ddr_cal_top_n_1600;
  wire u_ddr_cal_top_n_1601;
  wire u_ddr_cal_top_n_1612;
  wire u_ddr_cal_top_n_1613;
  wire u_ddr_cal_top_n_1614;
  wire u_ddr_cal_top_n_1615;
  wire u_ddr_cal_top_n_1616;
  wire u_ddr_cal_top_n_1617;
  wire u_ddr_cal_top_n_1618;
  wire u_ddr_cal_top_n_1619;
  wire u_ddr_cal_top_n_1620;
  wire u_ddr_cal_top_n_1621;
  wire u_ddr_cal_top_n_1622;
  wire u_ddr_cal_top_n_1623;
  wire u_ddr_cal_top_n_1624;
  wire u_ddr_cal_top_n_1625;
  wire u_ddr_cal_top_n_1626;
  wire u_ddr_cal_top_n_1627;
  wire u_ddr_cal_top_n_1628;
  wire u_ddr_cal_top_n_1629;
  wire u_ddr_cal_top_n_1630;
  wire u_ddr_cal_top_n_1631;
  wire u_ddr_cal_top_n_1632;
  wire u_ddr_cal_top_n_1633;
  wire u_ddr_cal_top_n_1634;
  wire u_ddr_cal_top_n_1635;
  wire u_ddr_cal_top_n_1636;
  wire u_ddr_cal_top_n_1637;
  wire u_ddr_cal_top_n_1638;
  wire u_ddr_cal_top_n_1639;
  wire u_ddr_cal_top_n_1640;
  wire u_ddr_cal_top_n_1641;
  wire u_ddr_cal_top_n_1642;
  wire u_ddr_cal_top_n_1643;
  wire u_ddr_cal_top_n_1644;
  wire u_ddr_cal_top_n_1645;
  wire u_ddr_cal_top_n_1646;
  wire u_ddr_cal_top_n_1647;
  wire u_ddr_cal_top_n_1648;
  wire u_ddr_cal_top_n_1649;
  wire u_ddr_cal_top_n_1650;
  wire u_ddr_cal_top_n_1651;
  wire u_ddr_cal_top_n_1652;
  wire u_ddr_cal_top_n_1653;
  wire u_ddr_cal_top_n_1664;
  wire u_ddr_cal_top_n_1665;
  wire u_ddr_cal_top_n_1666;
  wire u_ddr_cal_top_n_1667;
  wire u_ddr_cal_top_n_1722;
  wire u_ddr_cal_top_n_1723;
  wire u_ddr_cal_top_n_1724;
  wire u_ddr_cal_top_n_1725;
  wire u_ddr_cal_top_n_1726;
  wire u_ddr_cal_top_n_1727;
  wire u_ddr_cal_top_n_1728;
  wire u_ddr_cal_top_n_1729;
  wire u_ddr_cal_top_n_1730;
  wire u_ddr_cal_top_n_1731;
  wire u_ddr_cal_top_n_1738;
  wire u_ddr_cal_top_n_1739;
  wire u_ddr_cal_top_n_1740;
  wire u_ddr_cal_top_n_1741;
  wire u_ddr_cal_top_n_1742;
  wire u_ddr_cal_top_n_1743;
  wire u_ddr_cal_top_n_1744;
  wire u_ddr_cal_top_n_1745;
  wire u_ddr_cal_top_n_1746;
  wire u_ddr_cal_top_n_1747;
  wire u_ddr_cal_top_n_1748;
  wire u_ddr_cal_top_n_1749;
  wire u_ddr_cal_top_n_1750;
  wire u_ddr_cal_top_n_1751;
  wire u_ddr_cal_top_n_1752;
  wire u_ddr_cal_top_n_1753;
  wire u_ddr_cal_top_n_1754;
  wire u_ddr_cal_top_n_1755;
  wire u_ddr_cal_top_n_1756;
  wire u_ddr_cal_top_n_1757;
  wire u_ddr_cal_top_n_1758;
  wire u_ddr_cal_top_n_1759;
  wire u_ddr_cal_top_n_1760;
  wire u_ddr_cal_top_n_1761;
  wire u_ddr_cal_top_n_1762;
  wire u_ddr_cal_top_n_1763;
  wire u_ddr_cal_top_n_1764;
  wire u_ddr_cal_top_n_1765;
  wire u_ddr_cal_top_n_1766;
  wire u_ddr_cal_top_n_1767;
  wire u_ddr_cal_top_n_1768;
  wire u_ddr_cal_top_n_1769;
  wire u_ddr_cal_top_n_1770;
  wire u_ddr_cal_top_n_1771;
  wire u_ddr_cal_top_n_1772;
  wire u_ddr_cal_top_n_1773;
  wire u_ddr_cal_top_n_1774;
  wire u_ddr_cal_top_n_1775;
  wire u_ddr_cal_top_n_1776;
  wire u_ddr_cal_top_n_1777;
  wire u_ddr_cal_top_n_1778;
  wire u_ddr_cal_top_n_1779;
  wire u_ddr_cal_top_n_1780;
  wire u_ddr_cal_top_n_1781;
  wire u_ddr_cal_top_n_1782;
  wire u_ddr_cal_top_n_1783;
  wire u_ddr_cal_top_n_1784;
  wire u_ddr_cal_top_n_1785;
  wire u_ddr_cal_top_n_1786;
  wire u_ddr_cal_top_n_1787;
  wire u_ddr_cal_top_n_1788;
  wire u_ddr_cal_top_n_1789;
  wire u_ddr_cal_top_n_1790;
  wire u_ddr_cal_top_n_1791;
  wire u_ddr_cal_top_n_1792;
  wire u_ddr_cal_top_n_1793;
  wire u_ddr_cal_top_n_1794;
  wire u_ddr_cal_top_n_1795;
  wire u_ddr_cal_top_n_1796;
  wire u_ddr_cal_top_n_1797;
  wire u_ddr_cal_top_n_1798;
  wire u_ddr_cal_top_n_1799;
  wire u_ddr_cal_top_n_1800;
  wire u_ddr_cal_top_n_1801;
  wire u_ddr_cal_top_n_1802;
  wire u_ddr_cal_top_n_1803;
  wire u_ddr_cal_top_n_1804;
  wire u_ddr_cal_top_n_1805;
  wire u_ddr_cal_top_n_1806;
  wire u_ddr_cal_top_n_1807;
  wire u_ddr_cal_top_n_1808;
  wire u_ddr_cal_top_n_1809;
  wire u_ddr_cal_top_n_1810;
  wire u_ddr_cal_top_n_1811;
  wire u_ddr_cal_top_n_1812;
  wire u_ddr_cal_top_n_1813;
  wire u_ddr_cal_top_n_1814;
  wire u_ddr_cal_top_n_1815;
  wire u_ddr_cal_top_n_1816;
  wire u_ddr_cal_top_n_1817;
  wire u_ddr_cal_top_n_1818;
  wire u_ddr_cal_top_n_1819;
  wire u_ddr_cal_top_n_1820;
  wire u_ddr_cal_top_n_1821;
  wire u_ddr_cal_top_n_1822;
  wire u_ddr_cal_top_n_1823;
  wire u_ddr_cal_top_n_1824;
  wire u_ddr_cal_top_n_1825;
  wire u_ddr_cal_top_n_1826;
  wire u_ddr_cal_top_n_1827;
  wire u_ddr_cal_top_n_1828;
  wire u_ddr_cal_top_n_1829;
  wire u_ddr_cal_top_n_1830;
  wire u_ddr_cal_top_n_1831;
  wire u_ddr_cal_top_n_1832;
  wire u_ddr_cal_top_n_1833;
  wire u_ddr_cal_top_n_1834;
  wire u_ddr_cal_top_n_1835;
  wire u_ddr_cal_top_n_1836;
  wire u_ddr_cal_top_n_1837;
  wire u_ddr_cal_top_n_1838;
  wire u_ddr_cal_top_n_1839;
  wire u_ddr_cal_top_n_1840;
  wire u_ddr_cal_top_n_1841;
  wire u_ddr_cal_top_n_1842;
  wire u_ddr_cal_top_n_1843;
  wire u_ddr_cal_top_n_1844;
  wire u_ddr_cal_top_n_1845;
  wire u_ddr_cal_top_n_1846;
  wire u_ddr_cal_top_n_1847;
  wire u_ddr_cal_top_n_1848;
  wire u_ddr_cal_top_n_1849;
  wire u_ddr_cal_top_n_1850;
  wire u_ddr_cal_top_n_1851;
  wire u_ddr_cal_top_n_1852;
  wire u_ddr_cal_top_n_1853;
  wire u_ddr_cal_top_n_1854;
  wire u_ddr_cal_top_n_1855;
  wire u_ddr_cal_top_n_1856;
  wire u_ddr_cal_top_n_1857;
  wire u_ddr_cal_top_n_1858;
  wire u_ddr_cal_top_n_1859;
  wire u_ddr_cal_top_n_1860;
  wire u_ddr_cal_top_n_1861;
  wire u_ddr_cal_top_n_1862;
  wire u_ddr_cal_top_n_1863;
  wire u_ddr_cal_top_n_1864;
  wire u_ddr_cal_top_n_1865;
  wire u_ddr_cal_top_n_1866;
  wire u_ddr_cal_top_n_1874;
  wire u_ddr_cal_top_n_1875;
  wire u_ddr_cal_top_n_1876;
  wire u_ddr_cal_top_n_1877;
  wire u_ddr_cal_top_n_1878;
  wire u_ddr_cal_top_n_1879;
  wire u_ddr_cal_top_n_1880;
  wire u_ddr_cal_top_n_1881;
  wire u_ddr_cal_top_n_1882;
  wire u_ddr_cal_top_n_1883;
  wire u_ddr_cal_top_n_1884;
  wire u_ddr_cal_top_n_1886;
  wire u_ddr_cal_top_n_1887;
  wire u_ddr_cal_top_n_1899;
  wire u_ddr_cal_top_n_1900;
  wire u_ddr_cal_top_n_1901;
  wire u_ddr_cal_top_n_1902;
  wire u_ddr_cal_top_n_1903;
  wire u_ddr_cal_top_n_1904;
  wire u_ddr_cal_top_n_1905;
  wire u_ddr_cal_top_n_1906;
  wire u_ddr_cal_top_n_1963;
  wire u_ddr_cal_top_n_1964;
  wire u_ddr_cal_top_n_1965;
  wire u_ddr_cal_top_n_1966;
  wire u_ddr_cal_top_n_2115;
  wire u_ddr_cal_top_n_2116;
  wire u_ddr_cal_top_n_2117;
  wire u_ddr_cal_top_n_2118;
  wire u_ddr_cal_top_n_2119;
  wire u_ddr_cal_top_n_2120;
  wire u_ddr_cal_top_n_2121;
  wire u_ddr_cal_top_n_2122;
  wire u_ddr_cal_top_n_2123;
  wire u_ddr_cal_top_n_2124;
  wire u_ddr_cal_top_n_2125;
  wire u_ddr_cal_top_n_2126;
  wire u_ddr_cal_top_n_2209;
  wire u_ddr_cal_top_n_2210;
  wire u_ddr_cal_top_n_2211;
  wire u_ddr_cal_top_n_756;
  wire u_ddr_cal_top_n_758;
  wire u_ddr_cal_top_n_796;
  wire u_ddr_cal_top_n_798;
  wire u_ddr_cal_top_n_907;
  wire u_ddr_cal_top_n_914;
  wire u_ddr_cal_top_n_915;
  wire u_ddr_cal_top_n_916;
  wire u_ddr_cal_top_n_917;
  wire u_ddr_cal_top_n_918;
  wire u_ddr_cal_top_n_919;
  wire u_ddr_cal_top_n_921;
  wire u_ddr_cal_top_n_922;
  wire u_ddr_cal_top_n_924;
  wire u_ddr_cal_top_n_925;
  wire u_ddr_cal_top_n_926;
  wire u_ddr_cal_top_n_927;
  wire u_ddr_cal_top_n_928;
  wire u_ddr_cal_top_n_929;
  wire u_ddr_cal_top_n_931;
  wire u_ddr_cal_top_n_932;
  wire u_ddr_cal_top_n_934;
  wire u_ddr_cal_top_n_935;
  wire u_ddr_cal_top_n_936;
  wire u_ddr_cal_top_n_937;
  wire u_ddr_cal_top_n_938;
  wire u_ddr_cal_top_n_939;
  wire u_ddr_cal_top_n_941;
  wire u_ddr_cal_top_n_942;
  wire u_ddr_cal_top_n_944;
  wire u_ddr_cal_top_n_945;
  wire u_ddr_cal_top_n_946;
  wire u_ddr_cal_top_n_947;
  wire u_ddr_cal_top_n_948;
  wire u_ddr_cal_top_n_949;
  wire u_ddr_cal_top_n_952;
  wire u_ddr_cal_top_n_953;
  wire u_ddr_cal_top_n_954;
  wire u_ddr_cal_top_n_955;
  wire u_ddr_cal_top_n_956;
  wire u_ddr_cal_top_n_957;
  wire u_ddr_cal_top_n_960;
  wire u_ddr_cal_top_n_961;
  wire u_ddr_cal_top_n_962;
  wire u_ddr_cal_top_n_963;
  wire u_ddr_cal_top_n_964;
  wire u_ddr_cal_top_n_965;
  wire u_ddr_cal_top_n_968;
  wire u_ddr_cal_top_n_969;
  wire u_ddr_cal_top_n_970;
  wire u_ddr_cal_top_n_971;
  wire u_ddr_cal_top_n_972;
  wire u_ddr_cal_top_n_973;
  wire u_ddr_cal_top_n_976;
  wire u_ddr_cal_top_n_977;
  wire u_ddr_cal_top_n_978;
  wire u_ddr_cal_top_n_979;
  wire u_ddr_cal_top_n_980;
  wire u_ddr_cal_top_n_981;
  wire u_ddr_cal_top_n_984;
  wire u_ddr_cal_top_n_985;
  wire u_ddr_cal_top_n_986;
  wire u_ddr_cal_top_n_987;
  wire u_ddr_cal_top_n_988;
  wire u_ddr_cal_top_n_989;
  wire u_ddr_cal_top_n_992;
  wire u_ddr_cal_top_n_993;
  wire u_ddr_cal_top_n_994;
  wire u_ddr_cal_top_n_995;
  wire u_ddr_cal_top_n_996;
  wire u_ddr_cal_top_n_997;
  wire u_ddr_mc_n_0;
  wire u_ddr_mc_n_1;
  wire u_ddr_mc_n_100;
  wire u_ddr_mc_n_101;
  wire u_ddr_mc_n_102;
  wire u_ddr_mc_n_103;
  wire u_ddr_mc_n_104;
  wire u_ddr_mc_n_105;
  wire u_ddr_mc_n_106;
  wire u_ddr_mc_n_107;
  wire u_ddr_mc_n_109;
  wire u_ddr_mc_n_110;
  wire u_ddr_mc_n_111;
  wire u_ddr_mc_n_112;
  wire u_ddr_mc_n_113;
  wire u_ddr_mc_n_114;
  wire u_ddr_mc_n_115;
  wire u_ddr_mc_n_116;
  wire u_ddr_mc_n_117;
  wire u_ddr_mc_n_118;
  wire u_ddr_mc_n_119;
  wire u_ddr_mc_n_120;
  wire u_ddr_mc_n_121;
  wire u_ddr_mc_n_122;
  wire u_ddr_mc_n_123;
  wire u_ddr_mc_n_124;
  wire u_ddr_mc_n_2;
  wire u_ddr_mc_n_3;
  wire u_ddr_mc_n_55;
  wire u_ddr_mc_n_56;
  wire u_ddr_mc_n_57;
  wire u_ddr_mc_n_59;
  wire u_ddr_mc_n_60;
  wire u_ddr_mc_n_61;
  wire u_ddr_mc_n_62;
  wire u_ddr_mc_n_63;
  wire u_ddr_mc_n_64;
  wire u_ddr_mc_n_65;
  wire u_ddr_mc_n_66;
  wire u_ddr_mc_n_67;
  wire u_ddr_mc_n_68;
  wire u_ddr_mc_n_69;
  wire u_ddr_mc_n_70;
  wire u_ddr_mc_n_71;
  wire u_ddr_mc_n_72;
  wire u_ddr_mc_n_73;
  wire u_ddr_mc_n_74;
  wire u_ddr_mc_n_75;
  wire u_ddr_mc_n_76;
  wire u_ddr_mc_n_77;
  wire u_ddr_mc_n_78;
  wire u_ddr_mc_n_96;
  wire u_ddr_mc_n_97;
  wire u_ddr_mc_n_98;
  wire u_ddr_mc_n_99;
  wire [0:0]\u_ddr_mc_pi/u_ddr_mc_write/oe_0_mux_cal ;
  wire [8:5]\u_ddr_mc_pi/u_ddr_mc_write/wrQ_nxt[0]_12 ;
  wire [8:2]\u_ddr_mc_pi/u_ddr_mc_write/wrQ_nxt[1]_13 ;
  wire [8:5]\u_ddr_mc_pi/u_ddr_mc_write/wrQ_reg[1]_11 ;
  wire u_ddr_ui_n_10;
  wire u_ddr_ui_n_100;
  wire u_ddr_ui_n_101;
  wire u_ddr_ui_n_102;
  wire u_ddr_ui_n_103;
  wire u_ddr_ui_n_104;
  wire u_ddr_ui_n_105;
  wire u_ddr_ui_n_1059;
  wire u_ddr_ui_n_106;
  wire u_ddr_ui_n_1066;
  wire u_ddr_ui_n_1067;
  wire u_ddr_ui_n_1068;
  wire u_ddr_ui_n_1069;
  wire u_ddr_ui_n_107;
  wire u_ddr_ui_n_1070;
  wire u_ddr_ui_n_1071;
  wire u_ddr_ui_n_1072;
  wire u_ddr_ui_n_1073;
  wire u_ddr_ui_n_1074;
  wire u_ddr_ui_n_1075;
  wire u_ddr_ui_n_1076;
  wire u_ddr_ui_n_1077;
  wire u_ddr_ui_n_1078;
  wire u_ddr_ui_n_1079;
  wire u_ddr_ui_n_108;
  wire u_ddr_ui_n_1084;
  wire u_ddr_ui_n_109;
  wire u_ddr_ui_n_11;
  wire u_ddr_ui_n_110;
  wire u_ddr_ui_n_111;
  wire u_ddr_ui_n_112;
  wire u_ddr_ui_n_113;
  wire u_ddr_ui_n_114;
  wire u_ddr_ui_n_115;
  wire u_ddr_ui_n_116;
  wire u_ddr_ui_n_117;
  wire u_ddr_ui_n_118;
  wire u_ddr_ui_n_119;
  wire u_ddr_ui_n_12;
  wire u_ddr_ui_n_120;
  wire u_ddr_ui_n_121;
  wire u_ddr_ui_n_122;
  wire u_ddr_ui_n_123;
  wire u_ddr_ui_n_124;
  wire u_ddr_ui_n_125;
  wire u_ddr_ui_n_126;
  wire u_ddr_ui_n_127;
  wire u_ddr_ui_n_128;
  wire u_ddr_ui_n_129;
  wire u_ddr_ui_n_13;
  wire u_ddr_ui_n_130;
  wire u_ddr_ui_n_131;
  wire u_ddr_ui_n_132;
  wire u_ddr_ui_n_133;
  wire u_ddr_ui_n_134;
  wire u_ddr_ui_n_135;
  wire u_ddr_ui_n_136;
  wire u_ddr_ui_n_137;
  wire u_ddr_ui_n_138;
  wire u_ddr_ui_n_139;
  wire u_ddr_ui_n_14;
  wire u_ddr_ui_n_140;
  wire u_ddr_ui_n_141;
  wire u_ddr_ui_n_142;
  wire u_ddr_ui_n_143;
  wire u_ddr_ui_n_144;
  wire u_ddr_ui_n_145;
  wire u_ddr_ui_n_146;
  wire u_ddr_ui_n_147;
  wire u_ddr_ui_n_148;
  wire u_ddr_ui_n_149;
  wire u_ddr_ui_n_15;
  wire u_ddr_ui_n_150;
  wire u_ddr_ui_n_151;
  wire u_ddr_ui_n_152;
  wire u_ddr_ui_n_153;
  wire u_ddr_ui_n_154;
  wire u_ddr_ui_n_155;
  wire u_ddr_ui_n_156;
  wire u_ddr_ui_n_157;
  wire u_ddr_ui_n_158;
  wire u_ddr_ui_n_159;
  wire u_ddr_ui_n_16;
  wire u_ddr_ui_n_160;
  wire u_ddr_ui_n_161;
  wire u_ddr_ui_n_162;
  wire u_ddr_ui_n_163;
  wire u_ddr_ui_n_164;
  wire u_ddr_ui_n_165;
  wire u_ddr_ui_n_166;
  wire u_ddr_ui_n_167;
  wire u_ddr_ui_n_168;
  wire u_ddr_ui_n_169;
  wire u_ddr_ui_n_170;
  wire u_ddr_ui_n_171;
  wire u_ddr_ui_n_172;
  wire u_ddr_ui_n_173;
  wire u_ddr_ui_n_174;
  wire u_ddr_ui_n_175;
  wire u_ddr_ui_n_176;
  wire u_ddr_ui_n_177;
  wire u_ddr_ui_n_178;
  wire u_ddr_ui_n_179;
  wire u_ddr_ui_n_18;
  wire u_ddr_ui_n_180;
  wire u_ddr_ui_n_181;
  wire u_ddr_ui_n_182;
  wire u_ddr_ui_n_183;
  wire u_ddr_ui_n_184;
  wire u_ddr_ui_n_185;
  wire u_ddr_ui_n_186;
  wire u_ddr_ui_n_187;
  wire u_ddr_ui_n_188;
  wire u_ddr_ui_n_189;
  wire u_ddr_ui_n_19;
  wire u_ddr_ui_n_190;
  wire u_ddr_ui_n_191;
  wire u_ddr_ui_n_192;
  wire u_ddr_ui_n_193;
  wire u_ddr_ui_n_194;
  wire u_ddr_ui_n_195;
  wire u_ddr_ui_n_196;
  wire u_ddr_ui_n_197;
  wire u_ddr_ui_n_198;
  wire u_ddr_ui_n_199;
  wire u_ddr_ui_n_2;
  wire u_ddr_ui_n_20;
  wire u_ddr_ui_n_200;
  wire u_ddr_ui_n_201;
  wire u_ddr_ui_n_202;
  wire u_ddr_ui_n_203;
  wire u_ddr_ui_n_204;
  wire u_ddr_ui_n_205;
  wire u_ddr_ui_n_206;
  wire u_ddr_ui_n_207;
  wire u_ddr_ui_n_208;
  wire u_ddr_ui_n_209;
  wire u_ddr_ui_n_21;
  wire u_ddr_ui_n_210;
  wire u_ddr_ui_n_211;
  wire u_ddr_ui_n_212;
  wire u_ddr_ui_n_213;
  wire u_ddr_ui_n_214;
  wire u_ddr_ui_n_215;
  wire u_ddr_ui_n_216;
  wire u_ddr_ui_n_217;
  wire u_ddr_ui_n_218;
  wire u_ddr_ui_n_219;
  wire u_ddr_ui_n_22;
  wire u_ddr_ui_n_220;
  wire u_ddr_ui_n_221;
  wire u_ddr_ui_n_222;
  wire u_ddr_ui_n_223;
  wire u_ddr_ui_n_224;
  wire u_ddr_ui_n_225;
  wire u_ddr_ui_n_226;
  wire u_ddr_ui_n_227;
  wire u_ddr_ui_n_228;
  wire u_ddr_ui_n_229;
  wire u_ddr_ui_n_23;
  wire u_ddr_ui_n_230;
  wire u_ddr_ui_n_231;
  wire u_ddr_ui_n_232;
  wire u_ddr_ui_n_233;
  wire u_ddr_ui_n_234;
  wire u_ddr_ui_n_235;
  wire u_ddr_ui_n_236;
  wire u_ddr_ui_n_237;
  wire u_ddr_ui_n_238;
  wire u_ddr_ui_n_239;
  wire u_ddr_ui_n_24;
  wire u_ddr_ui_n_240;
  wire u_ddr_ui_n_241;
  wire u_ddr_ui_n_242;
  wire u_ddr_ui_n_243;
  wire u_ddr_ui_n_244;
  wire u_ddr_ui_n_245;
  wire u_ddr_ui_n_246;
  wire u_ddr_ui_n_247;
  wire u_ddr_ui_n_248;
  wire u_ddr_ui_n_249;
  wire u_ddr_ui_n_25;
  wire u_ddr_ui_n_250;
  wire u_ddr_ui_n_251;
  wire u_ddr_ui_n_252;
  wire u_ddr_ui_n_253;
  wire u_ddr_ui_n_254;
  wire u_ddr_ui_n_255;
  wire u_ddr_ui_n_256;
  wire u_ddr_ui_n_257;
  wire u_ddr_ui_n_258;
  wire u_ddr_ui_n_259;
  wire u_ddr_ui_n_26;
  wire u_ddr_ui_n_260;
  wire u_ddr_ui_n_261;
  wire u_ddr_ui_n_262;
  wire u_ddr_ui_n_263;
  wire u_ddr_ui_n_264;
  wire u_ddr_ui_n_265;
  wire u_ddr_ui_n_266;
  wire u_ddr_ui_n_267;
  wire u_ddr_ui_n_268;
  wire u_ddr_ui_n_269;
  wire u_ddr_ui_n_27;
  wire u_ddr_ui_n_270;
  wire u_ddr_ui_n_271;
  wire u_ddr_ui_n_272;
  wire u_ddr_ui_n_273;
  wire u_ddr_ui_n_274;
  wire u_ddr_ui_n_275;
  wire u_ddr_ui_n_276;
  wire u_ddr_ui_n_277;
  wire u_ddr_ui_n_278;
  wire u_ddr_ui_n_279;
  wire u_ddr_ui_n_28;
  wire u_ddr_ui_n_280;
  wire u_ddr_ui_n_281;
  wire u_ddr_ui_n_282;
  wire u_ddr_ui_n_283;
  wire u_ddr_ui_n_284;
  wire u_ddr_ui_n_285;
  wire u_ddr_ui_n_286;
  wire u_ddr_ui_n_287;
  wire u_ddr_ui_n_288;
  wire u_ddr_ui_n_289;
  wire u_ddr_ui_n_29;
  wire u_ddr_ui_n_290;
  wire u_ddr_ui_n_291;
  wire u_ddr_ui_n_292;
  wire u_ddr_ui_n_293;
  wire u_ddr_ui_n_294;
  wire u_ddr_ui_n_295;
  wire u_ddr_ui_n_296;
  wire u_ddr_ui_n_297;
  wire u_ddr_ui_n_298;
  wire u_ddr_ui_n_299;
  wire u_ddr_ui_n_3;
  wire u_ddr_ui_n_30;
  wire u_ddr_ui_n_300;
  wire u_ddr_ui_n_301;
  wire u_ddr_ui_n_302;
  wire u_ddr_ui_n_303;
  wire u_ddr_ui_n_304;
  wire u_ddr_ui_n_305;
  wire u_ddr_ui_n_306;
  wire u_ddr_ui_n_307;
  wire u_ddr_ui_n_308;
  wire u_ddr_ui_n_309;
  wire u_ddr_ui_n_31;
  wire u_ddr_ui_n_310;
  wire u_ddr_ui_n_311;
  wire u_ddr_ui_n_312;
  wire u_ddr_ui_n_313;
  wire u_ddr_ui_n_314;
  wire u_ddr_ui_n_315;
  wire u_ddr_ui_n_316;
  wire u_ddr_ui_n_317;
  wire u_ddr_ui_n_318;
  wire u_ddr_ui_n_319;
  wire u_ddr_ui_n_32;
  wire u_ddr_ui_n_320;
  wire u_ddr_ui_n_321;
  wire u_ddr_ui_n_322;
  wire u_ddr_ui_n_323;
  wire u_ddr_ui_n_324;
  wire u_ddr_ui_n_325;
  wire u_ddr_ui_n_326;
  wire u_ddr_ui_n_327;
  wire u_ddr_ui_n_328;
  wire u_ddr_ui_n_329;
  wire u_ddr_ui_n_33;
  wire u_ddr_ui_n_330;
  wire u_ddr_ui_n_331;
  wire u_ddr_ui_n_332;
  wire u_ddr_ui_n_333;
  wire u_ddr_ui_n_334;
  wire u_ddr_ui_n_335;
  wire u_ddr_ui_n_336;
  wire u_ddr_ui_n_337;
  wire u_ddr_ui_n_338;
  wire u_ddr_ui_n_339;
  wire u_ddr_ui_n_34;
  wire u_ddr_ui_n_340;
  wire u_ddr_ui_n_341;
  wire u_ddr_ui_n_342;
  wire u_ddr_ui_n_343;
  wire u_ddr_ui_n_344;
  wire u_ddr_ui_n_345;
  wire u_ddr_ui_n_346;
  wire u_ddr_ui_n_347;
  wire u_ddr_ui_n_348;
  wire u_ddr_ui_n_349;
  wire u_ddr_ui_n_35;
  wire u_ddr_ui_n_350;
  wire u_ddr_ui_n_351;
  wire u_ddr_ui_n_352;
  wire u_ddr_ui_n_353;
  wire u_ddr_ui_n_354;
  wire u_ddr_ui_n_355;
  wire u_ddr_ui_n_356;
  wire u_ddr_ui_n_357;
  wire u_ddr_ui_n_358;
  wire u_ddr_ui_n_359;
  wire u_ddr_ui_n_36;
  wire u_ddr_ui_n_360;
  wire u_ddr_ui_n_361;
  wire u_ddr_ui_n_362;
  wire u_ddr_ui_n_363;
  wire u_ddr_ui_n_364;
  wire u_ddr_ui_n_365;
  wire u_ddr_ui_n_366;
  wire u_ddr_ui_n_367;
  wire u_ddr_ui_n_368;
  wire u_ddr_ui_n_369;
  wire u_ddr_ui_n_37;
  wire u_ddr_ui_n_370;
  wire u_ddr_ui_n_371;
  wire u_ddr_ui_n_372;
  wire u_ddr_ui_n_373;
  wire u_ddr_ui_n_374;
  wire u_ddr_ui_n_375;
  wire u_ddr_ui_n_376;
  wire u_ddr_ui_n_377;
  wire u_ddr_ui_n_378;
  wire u_ddr_ui_n_379;
  wire u_ddr_ui_n_38;
  wire u_ddr_ui_n_380;
  wire u_ddr_ui_n_381;
  wire u_ddr_ui_n_382;
  wire u_ddr_ui_n_383;
  wire u_ddr_ui_n_384;
  wire u_ddr_ui_n_385;
  wire u_ddr_ui_n_386;
  wire u_ddr_ui_n_387;
  wire u_ddr_ui_n_388;
  wire u_ddr_ui_n_389;
  wire u_ddr_ui_n_39;
  wire u_ddr_ui_n_390;
  wire u_ddr_ui_n_391;
  wire u_ddr_ui_n_392;
  wire u_ddr_ui_n_393;
  wire u_ddr_ui_n_394;
  wire u_ddr_ui_n_395;
  wire u_ddr_ui_n_396;
  wire u_ddr_ui_n_397;
  wire u_ddr_ui_n_398;
  wire u_ddr_ui_n_399;
  wire u_ddr_ui_n_4;
  wire u_ddr_ui_n_40;
  wire u_ddr_ui_n_400;
  wire u_ddr_ui_n_401;
  wire u_ddr_ui_n_402;
  wire u_ddr_ui_n_403;
  wire u_ddr_ui_n_404;
  wire u_ddr_ui_n_405;
  wire u_ddr_ui_n_406;
  wire u_ddr_ui_n_407;
  wire u_ddr_ui_n_408;
  wire u_ddr_ui_n_409;
  wire u_ddr_ui_n_41;
  wire u_ddr_ui_n_410;
  wire u_ddr_ui_n_411;
  wire u_ddr_ui_n_412;
  wire u_ddr_ui_n_413;
  wire u_ddr_ui_n_414;
  wire u_ddr_ui_n_415;
  wire u_ddr_ui_n_416;
  wire u_ddr_ui_n_417;
  wire u_ddr_ui_n_418;
  wire u_ddr_ui_n_419;
  wire u_ddr_ui_n_42;
  wire u_ddr_ui_n_420;
  wire u_ddr_ui_n_421;
  wire u_ddr_ui_n_422;
  wire u_ddr_ui_n_423;
  wire u_ddr_ui_n_424;
  wire u_ddr_ui_n_425;
  wire u_ddr_ui_n_426;
  wire u_ddr_ui_n_427;
  wire u_ddr_ui_n_428;
  wire u_ddr_ui_n_429;
  wire u_ddr_ui_n_43;
  wire u_ddr_ui_n_430;
  wire u_ddr_ui_n_431;
  wire u_ddr_ui_n_432;
  wire u_ddr_ui_n_433;
  wire u_ddr_ui_n_434;
  wire u_ddr_ui_n_435;
  wire u_ddr_ui_n_436;
  wire u_ddr_ui_n_437;
  wire u_ddr_ui_n_438;
  wire u_ddr_ui_n_439;
  wire u_ddr_ui_n_44;
  wire u_ddr_ui_n_440;
  wire u_ddr_ui_n_441;
  wire u_ddr_ui_n_442;
  wire u_ddr_ui_n_443;
  wire u_ddr_ui_n_444;
  wire u_ddr_ui_n_445;
  wire u_ddr_ui_n_446;
  wire u_ddr_ui_n_447;
  wire u_ddr_ui_n_448;
  wire u_ddr_ui_n_449;
  wire u_ddr_ui_n_45;
  wire u_ddr_ui_n_450;
  wire u_ddr_ui_n_451;
  wire u_ddr_ui_n_452;
  wire u_ddr_ui_n_453;
  wire u_ddr_ui_n_454;
  wire u_ddr_ui_n_455;
  wire u_ddr_ui_n_456;
  wire u_ddr_ui_n_457;
  wire u_ddr_ui_n_458;
  wire u_ddr_ui_n_459;
  wire u_ddr_ui_n_46;
  wire u_ddr_ui_n_460;
  wire u_ddr_ui_n_461;
  wire u_ddr_ui_n_462;
  wire u_ddr_ui_n_463;
  wire u_ddr_ui_n_464;
  wire u_ddr_ui_n_465;
  wire u_ddr_ui_n_466;
  wire u_ddr_ui_n_467;
  wire u_ddr_ui_n_468;
  wire u_ddr_ui_n_469;
  wire u_ddr_ui_n_47;
  wire u_ddr_ui_n_470;
  wire u_ddr_ui_n_471;
  wire u_ddr_ui_n_472;
  wire u_ddr_ui_n_473;
  wire u_ddr_ui_n_474;
  wire u_ddr_ui_n_475;
  wire u_ddr_ui_n_476;
  wire u_ddr_ui_n_477;
  wire u_ddr_ui_n_478;
  wire u_ddr_ui_n_479;
  wire u_ddr_ui_n_48;
  wire u_ddr_ui_n_480;
  wire u_ddr_ui_n_481;
  wire u_ddr_ui_n_482;
  wire u_ddr_ui_n_483;
  wire u_ddr_ui_n_484;
  wire u_ddr_ui_n_485;
  wire u_ddr_ui_n_486;
  wire u_ddr_ui_n_487;
  wire u_ddr_ui_n_488;
  wire u_ddr_ui_n_489;
  wire u_ddr_ui_n_49;
  wire u_ddr_ui_n_490;
  wire u_ddr_ui_n_491;
  wire u_ddr_ui_n_492;
  wire u_ddr_ui_n_493;
  wire u_ddr_ui_n_494;
  wire u_ddr_ui_n_495;
  wire u_ddr_ui_n_496;
  wire u_ddr_ui_n_497;
  wire u_ddr_ui_n_498;
  wire u_ddr_ui_n_499;
  wire u_ddr_ui_n_5;
  wire u_ddr_ui_n_50;
  wire u_ddr_ui_n_500;
  wire u_ddr_ui_n_501;
  wire u_ddr_ui_n_502;
  wire u_ddr_ui_n_503;
  wire u_ddr_ui_n_504;
  wire u_ddr_ui_n_505;
  wire u_ddr_ui_n_506;
  wire u_ddr_ui_n_507;
  wire u_ddr_ui_n_508;
  wire u_ddr_ui_n_509;
  wire u_ddr_ui_n_51;
  wire u_ddr_ui_n_510;
  wire u_ddr_ui_n_511;
  wire u_ddr_ui_n_512;
  wire u_ddr_ui_n_513;
  wire u_ddr_ui_n_514;
  wire u_ddr_ui_n_515;
  wire u_ddr_ui_n_516;
  wire u_ddr_ui_n_517;
  wire u_ddr_ui_n_518;
  wire u_ddr_ui_n_519;
  wire u_ddr_ui_n_52;
  wire u_ddr_ui_n_520;
  wire u_ddr_ui_n_521;
  wire u_ddr_ui_n_522;
  wire u_ddr_ui_n_523;
  wire u_ddr_ui_n_524;
  wire u_ddr_ui_n_525;
  wire u_ddr_ui_n_526;
  wire u_ddr_ui_n_527;
  wire u_ddr_ui_n_528;
  wire u_ddr_ui_n_529;
  wire u_ddr_ui_n_53;
  wire u_ddr_ui_n_530;
  wire u_ddr_ui_n_531;
  wire u_ddr_ui_n_532;
  wire u_ddr_ui_n_533;
  wire u_ddr_ui_n_534;
  wire u_ddr_ui_n_536;
  wire u_ddr_ui_n_537;
  wire u_ddr_ui_n_538;
  wire u_ddr_ui_n_539;
  wire u_ddr_ui_n_54;
  wire u_ddr_ui_n_540;
  wire u_ddr_ui_n_541;
  wire u_ddr_ui_n_542;
  wire u_ddr_ui_n_543;
  wire u_ddr_ui_n_544;
  wire u_ddr_ui_n_545;
  wire u_ddr_ui_n_546;
  wire u_ddr_ui_n_547;
  wire u_ddr_ui_n_548;
  wire u_ddr_ui_n_549;
  wire u_ddr_ui_n_55;
  wire u_ddr_ui_n_550;
  wire u_ddr_ui_n_551;
  wire u_ddr_ui_n_552;
  wire u_ddr_ui_n_553;
  wire u_ddr_ui_n_554;
  wire u_ddr_ui_n_555;
  wire u_ddr_ui_n_556;
  wire u_ddr_ui_n_557;
  wire u_ddr_ui_n_558;
  wire u_ddr_ui_n_559;
  wire u_ddr_ui_n_56;
  wire u_ddr_ui_n_560;
  wire u_ddr_ui_n_561;
  wire u_ddr_ui_n_562;
  wire u_ddr_ui_n_563;
  wire u_ddr_ui_n_564;
  wire u_ddr_ui_n_565;
  wire u_ddr_ui_n_566;
  wire u_ddr_ui_n_567;
  wire u_ddr_ui_n_568;
  wire u_ddr_ui_n_569;
  wire u_ddr_ui_n_57;
  wire u_ddr_ui_n_570;
  wire u_ddr_ui_n_571;
  wire u_ddr_ui_n_572;
  wire u_ddr_ui_n_573;
  wire u_ddr_ui_n_574;
  wire u_ddr_ui_n_575;
  wire u_ddr_ui_n_576;
  wire u_ddr_ui_n_577;
  wire u_ddr_ui_n_578;
  wire u_ddr_ui_n_579;
  wire u_ddr_ui_n_58;
  wire u_ddr_ui_n_580;
  wire u_ddr_ui_n_581;
  wire u_ddr_ui_n_582;
  wire u_ddr_ui_n_583;
  wire u_ddr_ui_n_584;
  wire u_ddr_ui_n_585;
  wire u_ddr_ui_n_586;
  wire u_ddr_ui_n_587;
  wire u_ddr_ui_n_588;
  wire u_ddr_ui_n_589;
  wire u_ddr_ui_n_59;
  wire u_ddr_ui_n_590;
  wire u_ddr_ui_n_591;
  wire u_ddr_ui_n_592;
  wire u_ddr_ui_n_593;
  wire u_ddr_ui_n_594;
  wire u_ddr_ui_n_595;
  wire u_ddr_ui_n_596;
  wire u_ddr_ui_n_597;
  wire u_ddr_ui_n_598;
  wire u_ddr_ui_n_599;
  wire u_ddr_ui_n_6;
  wire u_ddr_ui_n_60;
  wire u_ddr_ui_n_600;
  wire u_ddr_ui_n_601;
  wire u_ddr_ui_n_602;
  wire u_ddr_ui_n_603;
  wire u_ddr_ui_n_604;
  wire u_ddr_ui_n_605;
  wire u_ddr_ui_n_606;
  wire u_ddr_ui_n_607;
  wire u_ddr_ui_n_608;
  wire u_ddr_ui_n_609;
  wire u_ddr_ui_n_61;
  wire u_ddr_ui_n_610;
  wire u_ddr_ui_n_611;
  wire u_ddr_ui_n_612;
  wire u_ddr_ui_n_613;
  wire u_ddr_ui_n_614;
  wire u_ddr_ui_n_615;
  wire u_ddr_ui_n_616;
  wire u_ddr_ui_n_617;
  wire u_ddr_ui_n_618;
  wire u_ddr_ui_n_619;
  wire u_ddr_ui_n_62;
  wire u_ddr_ui_n_620;
  wire u_ddr_ui_n_621;
  wire u_ddr_ui_n_63;
  wire u_ddr_ui_n_64;
  wire u_ddr_ui_n_65;
  wire u_ddr_ui_n_66;
  wire u_ddr_ui_n_67;
  wire u_ddr_ui_n_68;
  wire u_ddr_ui_n_69;
  wire u_ddr_ui_n_7;
  wire u_ddr_ui_n_70;
  wire u_ddr_ui_n_71;
  wire u_ddr_ui_n_72;
  wire u_ddr_ui_n_73;
  wire u_ddr_ui_n_74;
  wire u_ddr_ui_n_75;
  wire u_ddr_ui_n_76;
  wire u_ddr_ui_n_77;
  wire u_ddr_ui_n_78;
  wire u_ddr_ui_n_79;
  wire u_ddr_ui_n_8;
  wire u_ddr_ui_n_80;
  wire u_ddr_ui_n_81;
  wire u_ddr_ui_n_82;
  wire u_ddr_ui_n_83;
  wire u_ddr_ui_n_84;
  wire u_ddr_ui_n_85;
  wire u_ddr_ui_n_86;
  wire u_ddr_ui_n_87;
  wire u_ddr_ui_n_88;
  wire u_ddr_ui_n_89;
  wire u_ddr_ui_n_9;
  wire u_ddr_ui_n_90;
  wire u_ddr_ui_n_91;
  wire u_ddr_ui_n_92;
  wire u_ddr_ui_n_93;
  wire u_ddr_ui_n_94;
  wire u_ddr_ui_n_95;
  wire u_ddr_ui_n_96;
  wire u_ddr_ui_n_97;
  wire u_ddr_ui_n_98;
  wire u_ddr_ui_n_99;
  wire \u_ddr_ui_rd_data/match4_10_return ;
  wire \u_ddr_ui_rd_data/match4_110_return ;
  wire \u_ddr_ui_rd_data/match4_111_return ;
  wire \u_ddr_ui_rd_data/match4_112_return ;
  wire \u_ddr_ui_rd_data/match4_113_return ;
  wire \u_ddr_ui_rd_data/match4_114_return ;
  wire \u_ddr_ui_rd_data/match4_115_return ;
  wire \u_ddr_ui_rd_data/match4_116_return ;
  wire \u_ddr_ui_rd_data/match4_117_return ;
  wire \u_ddr_ui_rd_data/match4_118_return ;
  wire \u_ddr_ui_rd_data/match4_119_return ;
  wire \u_ddr_ui_rd_data/match4_11_return ;
  wire \u_ddr_ui_rd_data/match4_120_return ;
  wire \u_ddr_ui_rd_data/match4_121_return ;
  wire \u_ddr_ui_rd_data/match4_122_return ;
  wire \u_ddr_ui_rd_data/match4_123_return ;
  wire \u_ddr_ui_rd_data/match4_124_return ;
  wire \u_ddr_ui_rd_data/match4_125_return ;
  wire \u_ddr_ui_rd_data/match4_126_return ;
  wire \u_ddr_ui_rd_data/match4_127_return ;
  wire \u_ddr_ui_rd_data/match4_128_return ;
  wire \u_ddr_ui_rd_data/match4_129_return ;
  wire \u_ddr_ui_rd_data/match4_12_return ;
  wire \u_ddr_ui_rd_data/match4_130_return ;
  wire \u_ddr_ui_rd_data/match4_131_return ;
  wire \u_ddr_ui_rd_data/match4_132_return ;
  wire \u_ddr_ui_rd_data/match4_133_return ;
  wire \u_ddr_ui_rd_data/match4_134_return ;
  wire \u_ddr_ui_rd_data/match4_135_return ;
  wire \u_ddr_ui_rd_data/match4_136_return ;
  wire \u_ddr_ui_rd_data/match4_137_return ;
  wire \u_ddr_ui_rd_data/match4_138_return ;
  wire \u_ddr_ui_rd_data/match4_139_return ;
  wire \u_ddr_ui_rd_data/match4_13_return ;
  wire \u_ddr_ui_rd_data/match4_140_return ;
  wire \u_ddr_ui_rd_data/match4_141_return ;
  wire \u_ddr_ui_rd_data/match4_142_return ;
  wire \u_ddr_ui_rd_data/match4_143_return ;
  wire \u_ddr_ui_rd_data/match4_144_return ;
  wire \u_ddr_ui_rd_data/match4_145_return ;
  wire \u_ddr_ui_rd_data/match4_146_return ;
  wire \u_ddr_ui_rd_data/match4_147_return ;
  wire \u_ddr_ui_rd_data/match4_148_return ;
  wire \u_ddr_ui_rd_data/match4_149_return ;
  wire \u_ddr_ui_rd_data/match4_14_return ;
  wire \u_ddr_ui_rd_data/match4_150_return ;
  wire \u_ddr_ui_rd_data/match4_151_return ;
  wire \u_ddr_ui_rd_data/match4_152_return ;
  wire \u_ddr_ui_rd_data/match4_153_return ;
  wire \u_ddr_ui_rd_data/match4_154_return ;
  wire \u_ddr_ui_rd_data/match4_155_return ;
  wire \u_ddr_ui_rd_data/match4_156_return ;
  wire \u_ddr_ui_rd_data/match4_157_return ;
  wire \u_ddr_ui_rd_data/match4_158_return ;
  wire \u_ddr_ui_rd_data/match4_159_return ;
  wire \u_ddr_ui_rd_data/match4_15_return ;
  wire \u_ddr_ui_rd_data/match4_160_return ;
  wire \u_ddr_ui_rd_data/match4_161_return ;
  wire \u_ddr_ui_rd_data/match4_162_return ;
  wire \u_ddr_ui_rd_data/match4_163_return ;
  wire \u_ddr_ui_rd_data/match4_164_return ;
  wire \u_ddr_ui_rd_data/match4_165_return ;
  wire \u_ddr_ui_rd_data/match4_166_return ;
  wire \u_ddr_ui_rd_data/match4_167_return ;
  wire \u_ddr_ui_rd_data/match4_168_return ;
  wire \u_ddr_ui_rd_data/match4_169_return ;
  wire \u_ddr_ui_rd_data/match4_16_return ;
  wire \u_ddr_ui_rd_data/match4_170_return ;
  wire \u_ddr_ui_rd_data/match4_171_return ;
  wire \u_ddr_ui_rd_data/match4_172_return ;
  wire \u_ddr_ui_rd_data/match4_173_return ;
  wire \u_ddr_ui_rd_data/match4_174_return ;
  wire \u_ddr_ui_rd_data/match4_175_return ;
  wire \u_ddr_ui_rd_data/match4_176_return ;
  wire \u_ddr_ui_rd_data/match4_177_return ;
  wire \u_ddr_ui_rd_data/match4_178_return ;
  wire \u_ddr_ui_rd_data/match4_179_return ;
  wire \u_ddr_ui_rd_data/match4_17_return ;
  wire \u_ddr_ui_rd_data/match4_180_return ;
  wire \u_ddr_ui_rd_data/match4_181_return ;
  wire \u_ddr_ui_rd_data/match4_182_return ;
  wire \u_ddr_ui_rd_data/match4_183_return ;
  wire \u_ddr_ui_rd_data/match4_184_return ;
  wire \u_ddr_ui_rd_data/match4_185_return ;
  wire \u_ddr_ui_rd_data/match4_186_return ;
  wire \u_ddr_ui_rd_data/match4_187_return ;
  wire \u_ddr_ui_rd_data/match4_188_return ;
  wire \u_ddr_ui_rd_data/match4_18_return ;
  wire \u_ddr_ui_rd_data/match4_19_return ;
  wire \u_ddr_ui_rd_data/match4_1_return ;
  wire \u_ddr_ui_rd_data/match6_10_return ;
  wire \u_ddr_ui_rd_data/match6_110_return ;
  wire \u_ddr_ui_rd_data/match6_111_return ;
  wire \u_ddr_ui_rd_data/match6_112_return ;
  wire \u_ddr_ui_rd_data/match6_113_return ;
  wire \u_ddr_ui_rd_data/match6_114_return ;
  wire \u_ddr_ui_rd_data/match6_115_return ;
  wire \u_ddr_ui_rd_data/match6_116_return ;
  wire \u_ddr_ui_rd_data/match6_117_return ;
  wire \u_ddr_ui_rd_data/match6_118_return ;
  wire \u_ddr_ui_rd_data/match6_119_return ;
  wire \u_ddr_ui_rd_data/match6_11_return ;
  wire \u_ddr_ui_rd_data/match6_120_return ;
  wire \u_ddr_ui_rd_data/match6_121_return ;
  wire \u_ddr_ui_rd_data/match6_122_return ;
  wire \u_ddr_ui_rd_data/match6_123_return ;
  wire \u_ddr_ui_rd_data/match6_124_return ;
  wire \u_ddr_ui_rd_data/match6_125_return ;
  wire \u_ddr_ui_rd_data/match6_126_return ;
  wire \u_ddr_ui_rd_data/match6_127_return ;
  wire \u_ddr_ui_rd_data/match6_128_return ;
  wire \u_ddr_ui_rd_data/match6_129_return ;
  wire \u_ddr_ui_rd_data/match6_12_return ;
  wire \u_ddr_ui_rd_data/match6_130_return ;
  wire \u_ddr_ui_rd_data/match6_131_return ;
  wire \u_ddr_ui_rd_data/match6_132_return ;
  wire \u_ddr_ui_rd_data/match6_133_return ;
  wire \u_ddr_ui_rd_data/match6_134_return ;
  wire \u_ddr_ui_rd_data/match6_135_return ;
  wire \u_ddr_ui_rd_data/match6_136_return ;
  wire \u_ddr_ui_rd_data/match6_137_return ;
  wire \u_ddr_ui_rd_data/match6_138_return ;
  wire \u_ddr_ui_rd_data/match6_139_return ;
  wire \u_ddr_ui_rd_data/match6_13_return ;
  wire \u_ddr_ui_rd_data/match6_140_return ;
  wire \u_ddr_ui_rd_data/match6_141_return ;
  wire \u_ddr_ui_rd_data/match6_142_return ;
  wire \u_ddr_ui_rd_data/match6_143_return ;
  wire \u_ddr_ui_rd_data/match6_144_return ;
  wire \u_ddr_ui_rd_data/match6_145_return ;
  wire \u_ddr_ui_rd_data/match6_146_return ;
  wire \u_ddr_ui_rd_data/match6_147_return ;
  wire \u_ddr_ui_rd_data/match6_148_return ;
  wire \u_ddr_ui_rd_data/match6_149_return ;
  wire \u_ddr_ui_rd_data/match6_14_return ;
  wire \u_ddr_ui_rd_data/match6_150_return ;
  wire \u_ddr_ui_rd_data/match6_151_return ;
  wire \u_ddr_ui_rd_data/match6_152_return ;
  wire \u_ddr_ui_rd_data/match6_153_return ;
  wire \u_ddr_ui_rd_data/match6_154_return ;
  wire \u_ddr_ui_rd_data/match6_155_return ;
  wire \u_ddr_ui_rd_data/match6_156_return ;
  wire \u_ddr_ui_rd_data/match6_157_return ;
  wire \u_ddr_ui_rd_data/match6_158_return ;
  wire \u_ddr_ui_rd_data/match6_159_return ;
  wire \u_ddr_ui_rd_data/match6_15_return ;
  wire \u_ddr_ui_rd_data/match6_160_return ;
  wire \u_ddr_ui_rd_data/match6_161_return ;
  wire \u_ddr_ui_rd_data/match6_162_return ;
  wire \u_ddr_ui_rd_data/match6_163_return ;
  wire \u_ddr_ui_rd_data/match6_164_return ;
  wire \u_ddr_ui_rd_data/match6_165_return ;
  wire \u_ddr_ui_rd_data/match6_166_return ;
  wire \u_ddr_ui_rd_data/match6_167_return ;
  wire \u_ddr_ui_rd_data/match6_168_return ;
  wire \u_ddr_ui_rd_data/match6_169_return ;
  wire \u_ddr_ui_rd_data/match6_16_return ;
  wire \u_ddr_ui_rd_data/match6_170_return ;
  wire \u_ddr_ui_rd_data/match6_171_return ;
  wire \u_ddr_ui_rd_data/match6_172_return ;
  wire \u_ddr_ui_rd_data/match6_173_return ;
  wire \u_ddr_ui_rd_data/match6_174_return ;
  wire \u_ddr_ui_rd_data/match6_175_return ;
  wire \u_ddr_ui_rd_data/match6_176_return ;
  wire \u_ddr_ui_rd_data/match6_177_return ;
  wire \u_ddr_ui_rd_data/match6_178_return ;
  wire \u_ddr_ui_rd_data/match6_179_return ;
  wire \u_ddr_ui_rd_data/match6_17_return ;
  wire \u_ddr_ui_rd_data/match6_180_return ;
  wire \u_ddr_ui_rd_data/match6_181_return ;
  wire \u_ddr_ui_rd_data/match6_182_return ;
  wire \u_ddr_ui_rd_data/match6_183_return ;
  wire \u_ddr_ui_rd_data/match6_184_return ;
  wire \u_ddr_ui_rd_data/match6_185_return ;
  wire \u_ddr_ui_rd_data/match6_186_return ;
  wire \u_ddr_ui_rd_data/match6_187_return ;
  wire \u_ddr_ui_rd_data/match6_188_return ;
  wire \u_ddr_ui_rd_data/match6_18_return ;
  wire \u_ddr_ui_rd_data/match6_19_return ;
  wire \u_ddr_ui_rd_data/match6_1_return ;
  wire \u_ddr_ui_rd_data/not_strict_mode.bypass_cpy2 ;
  wire [85:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buf_we_orig ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[0].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[0].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[10].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[10].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[11].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[11].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[12].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[12].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[13].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[13].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[14].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[14].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[15].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[15].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[16].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[16].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[17].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[17].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[18].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[18].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[19].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[19].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[1].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[1].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[20].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[20].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[21].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[21].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[22].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[22].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[23].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[23].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[24].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[24].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[25].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[25].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[26].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[26].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[27].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[27].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[28].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[28].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[29].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[29].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[2].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[2].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[30].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[30].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[31].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[31].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[32].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[32].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[33].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[33].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[34].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[34].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[35].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[35].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[36].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[36].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[37].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[37].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[38].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[38].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[39].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[39].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[3].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[3].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[40].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[40].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[41].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[41].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[42].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[42].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[43].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[43].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[44].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[44].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[45].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[45].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[46].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[46].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[47].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[47].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[48].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[48].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[49].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[49].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[4].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[4].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[50].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[50].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[51].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[51].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[52].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[52].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[53].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[53].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[54].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[54].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[55].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[55].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[56].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[56].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[57].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[57].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[58].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[58].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[59].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[59].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[5].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[5].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[60].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[60].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[61].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[61].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[62].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[62].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[63].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[63].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[64].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[64].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[65].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[65].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[66].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[66].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[67].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[67].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[68].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[68].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[69].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[69].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[6].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[6].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[70].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[70].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[71].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[71].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[72].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[72].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[73].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[73].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[74].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[74].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[75].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[75].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[76].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[76].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[77].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[77].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[78].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[78].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[79].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[79].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[7].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[7].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[80].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[80].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[81].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[81].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[82].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[82].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[83].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[83].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[84].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[84].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[85].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[85].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[8].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[8].addr__0 ;
  wire [2:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[9].addr ;
  wire [1:0]\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[9].addr__0 ;
  wire [1:1]\u_ddr_ui_rd_data/not_strict_mode.rd_status[0]_175 ;
  wire [4:4]\u_ddr_ui_rd_data/rd_buf_index_cpy[19].rd_buf_indx_r_reg[19]_188 ;
  wire \u_ddr_ui_wr_data/pointer_we ;
  wire u_io_addr_sync_n_100;
  wire u_io_addr_sync_n_101;
  wire u_io_addr_sync_n_102;
  wire u_io_addr_sync_n_104;
  wire u_io_addr_sync_n_105;
  wire u_io_addr_sync_n_106;
  wire u_io_addr_sync_n_107;
  wire u_io_addr_sync_n_108;
  wire u_io_addr_sync_n_109;
  wire u_io_addr_sync_n_110;
  wire u_io_addr_sync_n_111;
  wire u_io_addr_sync_n_112;
  wire u_io_addr_sync_n_113;
  wire u_io_addr_sync_n_114;
  wire u_io_addr_sync_n_115;
  wire u_io_addr_sync_n_116;
  wire u_io_addr_sync_n_117;
  wire u_io_addr_sync_n_118;
  wire u_io_addr_sync_n_119;
  wire u_io_addr_sync_n_120;
  wire u_io_addr_sync_n_121;
  wire u_io_addr_sync_n_122;
  wire u_io_addr_sync_n_123;
  wire u_io_addr_sync_n_124;
  wire u_io_addr_sync_n_125;
  wire u_io_addr_sync_n_126;
  wire u_io_addr_sync_n_127;
  wire u_io_addr_sync_n_128;
  wire u_io_addr_sync_n_137;
  wire u_io_addr_sync_n_138;
  wire u_io_addr_sync_n_22;
  wire u_io_addr_sync_n_23;
  wire u_io_addr_sync_n_24;
  wire u_io_addr_sync_n_25;
  wire u_io_addr_sync_n_26;
  wire u_io_addr_sync_n_27;
  wire u_io_addr_sync_n_28;
  wire u_io_addr_sync_n_29;
  wire u_io_addr_sync_n_30;
  wire u_io_addr_sync_n_31;
  wire u_io_addr_sync_n_32;
  wire u_io_addr_sync_n_33;
  wire u_io_addr_sync_n_34;
  wire u_io_addr_sync_n_35;
  wire u_io_addr_sync_n_36;
  wire u_io_addr_sync_n_37;
  wire u_io_addr_sync_n_38;
  wire u_io_addr_sync_n_39;
  wire u_io_addr_sync_n_40;
  wire u_io_addr_sync_n_41;
  wire u_io_addr_sync_n_42;
  wire u_io_addr_sync_n_43;
  wire u_io_addr_sync_n_44;
  wire u_io_addr_sync_n_45;
  wire u_io_addr_sync_n_46;
  wire u_io_addr_sync_n_48;
  wire u_io_addr_sync_n_52;
  wire u_io_addr_sync_n_53;
  wire u_io_addr_sync_n_54;
  wire u_io_addr_sync_n_55;
  wire u_io_addr_sync_n_56;
  wire u_io_addr_sync_n_57;
  wire u_io_addr_sync_n_58;
  wire u_io_addr_sync_n_59;
  wire u_io_addr_sync_n_60;
  wire u_io_addr_sync_n_61;
  wire u_io_addr_sync_n_62;
  wire u_io_addr_sync_n_63;
  wire u_io_addr_sync_n_64;
  wire u_io_addr_sync_n_65;
  wire u_io_addr_sync_n_66;
  wire u_io_addr_sync_n_68;
  wire u_io_addr_sync_n_90;
  wire u_io_addr_sync_n_91;
  wire u_io_addr_sync_n_92;
  wire u_io_addr_sync_n_93;
  wire u_io_addr_sync_n_94;
  wire u_io_addr_sync_n_95;
  wire u_io_addr_sync_n_96;
  wire u_io_addr_sync_n_97;
  wire u_io_addr_sync_n_98;
  wire u_io_addr_sync_n_99;
  wire u_io_write_data_sync_n_100;
  wire u_io_write_data_sync_n_101;
  wire u_io_write_data_sync_n_102;
  wire u_io_write_data_sync_n_103;
  wire u_io_write_data_sync_n_104;
  wire u_io_write_data_sync_n_105;
  wire u_io_write_data_sync_n_32;
  wire u_io_write_data_sync_n_73;
  wire u_io_write_data_sync_n_74;
  wire u_io_write_data_sync_n_75;
  wire u_io_write_data_sync_n_76;
  wire u_io_write_data_sync_n_77;
  wire u_io_write_data_sync_n_78;
  wire u_io_write_data_sync_n_79;
  wire u_io_write_data_sync_n_80;
  wire u_io_write_data_sync_n_81;
  wire u_io_write_data_sync_n_82;
  wire u_io_write_data_sync_n_83;
  wire u_io_write_data_sync_n_84;
  wire u_io_write_data_sync_n_85;
  wire u_io_write_data_sync_n_86;
  wire u_io_write_data_sync_n_87;
  wire u_io_write_data_sync_n_88;
  wire u_io_write_data_sync_n_89;
  wire u_io_write_data_sync_n_90;
  wire u_io_write_data_sync_n_91;
  wire u_io_write_data_sync_n_92;
  wire u_io_write_data_sync_n_93;
  wire u_io_write_data_sync_n_94;
  wire u_io_write_data_sync_n_95;
  wire u_io_write_data_sync_n_96;
  wire u_io_write_data_sync_n_97;
  wire u_io_write_data_sync_n_98;
  wire u_io_write_data_sync_n_99;
  wire u_mig_ddr4_phy_n_24;
  wire ub_initDone;
  wire ub_rst_out_riuclk;
  wire underfill_done_nxt;
  wire useAdr;
  wire winAct;
  wire [4:0]winBuf;
  wire winInjTxn;
  wire winRmw;
  wire [3:0]wrDataAddr;
  wire wrDataEn;
  wire [63:0]wr_data_mask_ni2mc;
  wire [511:0]wr_data_ni2mc;

  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE LMB_CE_r1_reg
       (.C(\SYNC[19].sync_reg_reg[1] ),
        .CE(1'b1),
        .D(LMB_CE_riu),
        .Q(LMB_CE_r1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE LMB_CE_r2_reg
       (.C(\SYNC[19].sync_reg_reg[1] ),
        .CE(1'b1),
        .D(LMB_CE_r1),
        .Q(LMB_CE_r2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE LMB_UE_r1_reg
       (.C(\SYNC[19].sync_reg_reg[1] ),
        .CE(1'b1),
        .D(LMB_UE_riu),
        .Q(LMB_UE_r1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE LMB_UE_r2_reg
       (.C(\SYNC[19].sync_reg_reg[1] ),
        .CE(1'b1),
        .D(LMB_UE_r1),
        .Q(LMB_UE_r2),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE en_vtc_in_reg
       (.C(\SYNC[19].sync_reg_reg[1] ),
        .CE(1'b1),
        .D(en_vtc),
        .Q(en_vtc_in),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE rst_r1_reg
       (.C(\SYNC[19].sync_reg_reg[1] ),
        .CE(1'b1),
        .D(SR),
        .Q(rst_r1),
        .R(1'b0));
  ddr4_0_ddr4_cal_riu u_ddr_cal_riu
       (.CLK(CLK),
        .D(io_addr_strobe_lvl_riuclk),
        .LMB_CE_riu(LMB_CE_riu),
        .LMB_UE_riu(LMB_UE_riu),
        .Reset(Reset),
        .\fab_riu_rst_pipe_reg[0]_0 (fab_rst_sync),
        .\io_address_riuclk_reg[21]_0 (io_addr_strobe_clb2riu_riuclk),
        .io_read_data_riuclk(io_read_data_riuclk),
        .io_ready_lvl_riuclk_r1_reg_0(io_ready_lvl_riuclk),
        .\io_write_data_riuclk_reg[31]_0 (io_write_data_riuclk),
        .io_write_strobe_riuclk_reg_0(io_write_strobe_riuclk),
        .out(io_address_riuclk),
        .\riu2clb_valid_r1_riuclk_reg[19]_0 (riu2clb_valid_r1_riuclk),
        .\riu2clb_valid_r1_riuclk_reg[19]_1 (riu2clb_valid_riuclk),
        .riu2clb_vld_read_data(riu2clb_vld_read_data),
        .riu_addr_cal(riu_addr_cal),
        .riu_clk_rst(riu_clk_rst),
        .riu_nibble_8(riu_nibble_8),
        .sample_gts(sample_gts),
        .ub_rst_out_riuclk(ub_rst_out_riuclk));
  ddr4_0_ddr4_v2_2_17_cal_top u_ddr_cal_top
       (.ADDRA({u_ddr_cal_top_n_2115,u_ddr_cal_top_n_2116,u_ddr_cal_top_n_2117,u_ddr_cal_top_n_2118}),
        .ADDRC(wrDataAddr),
        .ADDRD({u_ddr_cal_top_n_921,u_ddr_cal_top_n_922}),
        .D({rd_data_phy2mc_xif[511],rd_data_phy2mc_xif[503],rd_data_phy2mc_xif[495],rd_data_phy2mc_xif[487],rd_data_phy2mc_xif[479],rd_data_phy2mc_xif[471],rd_data_phy2mc_xif[463],rd_data_phy2mc_xif[455],rd_data_phy2mc_xif[510],rd_data_phy2mc_xif[502],rd_data_phy2mc_xif[494],rd_data_phy2mc_xif[486],rd_data_phy2mc_xif[478],rd_data_phy2mc_xif[470],rd_data_phy2mc_xif[462],rd_data_phy2mc_xif[454],rd_data_phy2mc_xif[509],rd_data_phy2mc_xif[501],rd_data_phy2mc_xif[493],rd_data_phy2mc_xif[485],rd_data_phy2mc_xif[477],rd_data_phy2mc_xif[469],rd_data_phy2mc_xif[461],rd_data_phy2mc_xif[453],rd_data_phy2mc_xif[508],rd_data_phy2mc_xif[500],rd_data_phy2mc_xif[492],rd_data_phy2mc_xif[484],rd_data_phy2mc_xif[476],rd_data_phy2mc_xif[468],rd_data_phy2mc_xif[460],rd_data_phy2mc_xif[452],rd_data_phy2mc_xif[507],rd_data_phy2mc_xif[499],rd_data_phy2mc_xif[491],rd_data_phy2mc_xif[483],rd_data_phy2mc_xif[475],rd_data_phy2mc_xif[467],rd_data_phy2mc_xif[459],rd_data_phy2mc_xif[451],rd_data_phy2mc_xif[506],rd_data_phy2mc_xif[498],rd_data_phy2mc_xif[490],rd_data_phy2mc_xif[482],rd_data_phy2mc_xif[474],rd_data_phy2mc_xif[466],rd_data_phy2mc_xif[458],rd_data_phy2mc_xif[450],rd_data_phy2mc_xif[505],rd_data_phy2mc_xif[497],rd_data_phy2mc_xif[489],rd_data_phy2mc_xif[481],rd_data_phy2mc_xif[473],rd_data_phy2mc_xif[465],rd_data_phy2mc_xif[457],rd_data_phy2mc_xif[449],rd_data_phy2mc_xif[504],rd_data_phy2mc_xif[496],rd_data_phy2mc_xif[488],rd_data_phy2mc_xif[480],rd_data_phy2mc_xif[472],rd_data_phy2mc_xif[464],rd_data_phy2mc_xif[456],rd_data_phy2mc_xif[448:447],rd_data_phy2mc_xif[439],rd_data_phy2mc_xif[431],rd_data_phy2mc_xif[423],rd_data_phy2mc_xif[415],rd_data_phy2mc_xif[407],rd_data_phy2mc_xif[399],rd_data_phy2mc_xif[391],rd_data_phy2mc_xif[446],rd_data_phy2mc_xif[438],rd_data_phy2mc_xif[430],rd_data_phy2mc_xif[422],rd_data_phy2mc_xif[414],rd_data_phy2mc_xif[406],rd_data_phy2mc_xif[398],rd_data_phy2mc_xif[390],rd_data_phy2mc_xif[445],rd_data_phy2mc_xif[437],rd_data_phy2mc_xif[429],rd_data_phy2mc_xif[421],rd_data_phy2mc_xif[413],rd_data_phy2mc_xif[405],rd_data_phy2mc_xif[397],rd_data_phy2mc_xif[389],rd_data_phy2mc_xif[444],rd_data_phy2mc_xif[436],rd_data_phy2mc_xif[428],rd_data_phy2mc_xif[420],rd_data_phy2mc_xif[412],rd_data_phy2mc_xif[404],rd_data_phy2mc_xif[396],rd_data_phy2mc_xif[388],rd_data_phy2mc_xif[443],rd_data_phy2mc_xif[435],rd_data_phy2mc_xif[427],rd_data_phy2mc_xif[419],rd_data_phy2mc_xif[411],rd_data_phy2mc_xif[403],rd_data_phy2mc_xif[395],rd_data_phy2mc_xif[387],rd_data_phy2mc_xif[442],rd_data_phy2mc_xif[434],rd_data_phy2mc_xif[426],rd_data_phy2mc_xif[418],rd_data_phy2mc_xif[410],rd_data_phy2mc_xif[402],rd_data_phy2mc_xif[394],rd_data_phy2mc_xif[386],rd_data_phy2mc_xif[441],rd_data_phy2mc_xif[433],rd_data_phy2mc_xif[425],rd_data_phy2mc_xif[417],rd_data_phy2mc_xif[409],rd_data_phy2mc_xif[401],rd_data_phy2mc_xif[393],rd_data_phy2mc_xif[385],rd_data_phy2mc_xif[440],rd_data_phy2mc_xif[432],rd_data_phy2mc_xif[424],rd_data_phy2mc_xif[416],rd_data_phy2mc_xif[408],rd_data_phy2mc_xif[400],rd_data_phy2mc_xif[392],rd_data_phy2mc_xif[384:383],rd_data_phy2mc_xif[375],rd_data_phy2mc_xif[367],rd_data_phy2mc_xif[359],rd_data_phy2mc_xif[351],rd_data_phy2mc_xif[343],rd_data_phy2mc_xif[335],rd_data_phy2mc_xif[327],rd_data_phy2mc_xif[382],rd_data_phy2mc_xif[374],rd_data_phy2mc_xif[366],rd_data_phy2mc_xif[358],rd_data_phy2mc_xif[350],rd_data_phy2mc_xif[342],rd_data_phy2mc_xif[334],rd_data_phy2mc_xif[326],rd_data_phy2mc_xif[381],rd_data_phy2mc_xif[373],rd_data_phy2mc_xif[365],rd_data_phy2mc_xif[357],rd_data_phy2mc_xif[349],rd_data_phy2mc_xif[341],rd_data_phy2mc_xif[333],rd_data_phy2mc_xif[325],rd_data_phy2mc_xif[380],rd_data_phy2mc_xif[372],rd_data_phy2mc_xif[364],rd_data_phy2mc_xif[356],rd_data_phy2mc_xif[348],rd_data_phy2mc_xif[340],rd_data_phy2mc_xif[332],rd_data_phy2mc_xif[324],rd_data_phy2mc_xif[379],rd_data_phy2mc_xif[371],rd_data_phy2mc_xif[363],rd_data_phy2mc_xif[355],rd_data_phy2mc_xif[347],rd_data_phy2mc_xif[339],rd_data_phy2mc_xif[331],rd_data_phy2mc_xif[323],rd_data_phy2mc_xif[378],rd_data_phy2mc_xif[370],rd_data_phy2mc_xif[362],rd_data_phy2mc_xif[354],rd_data_phy2mc_xif[346],rd_data_phy2mc_xif[338],rd_data_phy2mc_xif[330],rd_data_phy2mc_xif[322],rd_data_phy2mc_xif[377],rd_data_phy2mc_xif[369],rd_data_phy2mc_xif[361],rd_data_phy2mc_xif[353],rd_data_phy2mc_xif[345],rd_data_phy2mc_xif[337],rd_data_phy2mc_xif[329],rd_data_phy2mc_xif[321],rd_data_phy2mc_xif[376],rd_data_phy2mc_xif[368],rd_data_phy2mc_xif[360],rd_data_phy2mc_xif[352],rd_data_phy2mc_xif[344],rd_data_phy2mc_xif[336],rd_data_phy2mc_xif[328],rd_data_phy2mc_xif[320:319],rd_data_phy2mc_xif[311],rd_data_phy2mc_xif[303],rd_data_phy2mc_xif[295],rd_data_phy2mc_xif[287],rd_data_phy2mc_xif[279],rd_data_phy2mc_xif[271],rd_data_phy2mc_xif[263],rd_data_phy2mc_xif[318],rd_data_phy2mc_xif[310],rd_data_phy2mc_xif[302],rd_data_phy2mc_xif[294],rd_data_phy2mc_xif[286],rd_data_phy2mc_xif[278],rd_data_phy2mc_xif[270],rd_data_phy2mc_xif[262],rd_data_phy2mc_xif[317],rd_data_phy2mc_xif[309],rd_data_phy2mc_xif[301],rd_data_phy2mc_xif[293],rd_data_phy2mc_xif[285],rd_data_phy2mc_xif[277],rd_data_phy2mc_xif[269],rd_data_phy2mc_xif[261],rd_data_phy2mc_xif[316],rd_data_phy2mc_xif[308],rd_data_phy2mc_xif[300],rd_data_phy2mc_xif[292],rd_data_phy2mc_xif[284],rd_data_phy2mc_xif[276],rd_data_phy2mc_xif[268],rd_data_phy2mc_xif[260],rd_data_phy2mc_xif[315],rd_data_phy2mc_xif[307],rd_data_phy2mc_xif[299],rd_data_phy2mc_xif[291],rd_data_phy2mc_xif[283],rd_data_phy2mc_xif[275],rd_data_phy2mc_xif[267],rd_data_phy2mc_xif[259],rd_data_phy2mc_xif[314],rd_data_phy2mc_xif[306],rd_data_phy2mc_xif[298],rd_data_phy2mc_xif[290],rd_data_phy2mc_xif[282],rd_data_phy2mc_xif[274],rd_data_phy2mc_xif[266],rd_data_phy2mc_xif[258],rd_data_phy2mc_xif[313],rd_data_phy2mc_xif[305],rd_data_phy2mc_xif[297],rd_data_phy2mc_xif[289],rd_data_phy2mc_xif[281],rd_data_phy2mc_xif[273],rd_data_phy2mc_xif[265],rd_data_phy2mc_xif[257],rd_data_phy2mc_xif[312],rd_data_phy2mc_xif[304],rd_data_phy2mc_xif[296],rd_data_phy2mc_xif[288],rd_data_phy2mc_xif[280],rd_data_phy2mc_xif[272],rd_data_phy2mc_xif[264],rd_data_phy2mc_xif[256:255],rd_data_phy2mc_xif[247],rd_data_phy2mc_xif[239],rd_data_phy2mc_xif[231],rd_data_phy2mc_xif[223],rd_data_phy2mc_xif[215],rd_data_phy2mc_xif[207],rd_data_phy2mc_xif[199],rd_data_phy2mc_xif[254],rd_data_phy2mc_xif[246],rd_data_phy2mc_xif[238],rd_data_phy2mc_xif[230],rd_data_phy2mc_xif[222],rd_data_phy2mc_xif[214],rd_data_phy2mc_xif[206],rd_data_phy2mc_xif[198],rd_data_phy2mc_xif[253],rd_data_phy2mc_xif[245],rd_data_phy2mc_xif[237],rd_data_phy2mc_xif[229],rd_data_phy2mc_xif[221],rd_data_phy2mc_xif[213],rd_data_phy2mc_xif[205],rd_data_phy2mc_xif[197],rd_data_phy2mc_xif[252],rd_data_phy2mc_xif[244],rd_data_phy2mc_xif[236],rd_data_phy2mc_xif[228],rd_data_phy2mc_xif[220],rd_data_phy2mc_xif[212],rd_data_phy2mc_xif[204],rd_data_phy2mc_xif[196],rd_data_phy2mc_xif[251],rd_data_phy2mc_xif[243],rd_data_phy2mc_xif[235],rd_data_phy2mc_xif[227],rd_data_phy2mc_xif[219],rd_data_phy2mc_xif[211],rd_data_phy2mc_xif[203],rd_data_phy2mc_xif[195],rd_data_phy2mc_xif[250],rd_data_phy2mc_xif[242],rd_data_phy2mc_xif[234],rd_data_phy2mc_xif[226],rd_data_phy2mc_xif[218],rd_data_phy2mc_xif[210],rd_data_phy2mc_xif[202],rd_data_phy2mc_xif[194],rd_data_phy2mc_xif[249],rd_data_phy2mc_xif[241],rd_data_phy2mc_xif[233],rd_data_phy2mc_xif[225],rd_data_phy2mc_xif[217],rd_data_phy2mc_xif[209],rd_data_phy2mc_xif[201],rd_data_phy2mc_xif[193],rd_data_phy2mc_xif[248],rd_data_phy2mc_xif[240],rd_data_phy2mc_xif[232],rd_data_phy2mc_xif[224],rd_data_phy2mc_xif[216],rd_data_phy2mc_xif[208],rd_data_phy2mc_xif[200],rd_data_phy2mc_xif[192:191],rd_data_phy2mc_xif[183],rd_data_phy2mc_xif[175],rd_data_phy2mc_xif[167],rd_data_phy2mc_xif[159],rd_data_phy2mc_xif[151],rd_data_phy2mc_xif[143],rd_data_phy2mc_xif[135],rd_data_phy2mc_xif[190],rd_data_phy2mc_xif[182],rd_data_phy2mc_xif[174],rd_data_phy2mc_xif[166],rd_data_phy2mc_xif[158],rd_data_phy2mc_xif[150],rd_data_phy2mc_xif[142],rd_data_phy2mc_xif[134],rd_data_phy2mc_xif[189],rd_data_phy2mc_xif[181],rd_data_phy2mc_xif[173],rd_data_phy2mc_xif[165],rd_data_phy2mc_xif[157],rd_data_phy2mc_xif[149],rd_data_phy2mc_xif[141],rd_data_phy2mc_xif[133],rd_data_phy2mc_xif[188],rd_data_phy2mc_xif[180],rd_data_phy2mc_xif[172],rd_data_phy2mc_xif[164],rd_data_phy2mc_xif[156],rd_data_phy2mc_xif[148],rd_data_phy2mc_xif[140],rd_data_phy2mc_xif[132],rd_data_phy2mc_xif[187],rd_data_phy2mc_xif[179],rd_data_phy2mc_xif[171],rd_data_phy2mc_xif[163],rd_data_phy2mc_xif[155],rd_data_phy2mc_xif[147],rd_data_phy2mc_xif[139],rd_data_phy2mc_xif[131],rd_data_phy2mc_xif[186],rd_data_phy2mc_xif[178],rd_data_phy2mc_xif[170],rd_data_phy2mc_xif[162],rd_data_phy2mc_xif[154],rd_data_phy2mc_xif[146],rd_data_phy2mc_xif[138],rd_data_phy2mc_xif[130],rd_data_phy2mc_xif[185],rd_data_phy2mc_xif[177],rd_data_phy2mc_xif[169],rd_data_phy2mc_xif[161],rd_data_phy2mc_xif[153],rd_data_phy2mc_xif[145],rd_data_phy2mc_xif[137],rd_data_phy2mc_xif[129],rd_data_phy2mc_xif[184],rd_data_phy2mc_xif[176],rd_data_phy2mc_xif[168],rd_data_phy2mc_xif[160],rd_data_phy2mc_xif[152],rd_data_phy2mc_xif[144],rd_data_phy2mc_xif[136],rd_data_phy2mc_xif[128:127],rd_data_phy2mc_xif[119],rd_data_phy2mc_xif[111],rd_data_phy2mc_xif[103],rd_data_phy2mc_xif[95],rd_data_phy2mc_xif[87],rd_data_phy2mc_xif[79],rd_data_phy2mc_xif[71],rd_data_phy2mc_xif[126],rd_data_phy2mc_xif[118],rd_data_phy2mc_xif[110],rd_data_phy2mc_xif[102],rd_data_phy2mc_xif[94],rd_data_phy2mc_xif[86],rd_data_phy2mc_xif[78],rd_data_phy2mc_xif[70],rd_data_phy2mc_xif[125],rd_data_phy2mc_xif[117],rd_data_phy2mc_xif[109],rd_data_phy2mc_xif[101],rd_data_phy2mc_xif[93],rd_data_phy2mc_xif[85],rd_data_phy2mc_xif[77],rd_data_phy2mc_xif[69],rd_data_phy2mc_xif[124],rd_data_phy2mc_xif[116],rd_data_phy2mc_xif[108],rd_data_phy2mc_xif[100],rd_data_phy2mc_xif[92],rd_data_phy2mc_xif[84],rd_data_phy2mc_xif[76],rd_data_phy2mc_xif[68],rd_data_phy2mc_xif[123],rd_data_phy2mc_xif[115],rd_data_phy2mc_xif[107],rd_data_phy2mc_xif[99],rd_data_phy2mc_xif[91],rd_data_phy2mc_xif[83],rd_data_phy2mc_xif[75],rd_data_phy2mc_xif[67],rd_data_phy2mc_xif[122],rd_data_phy2mc_xif[114],rd_data_phy2mc_xif[106],rd_data_phy2mc_xif[98],rd_data_phy2mc_xif[90],rd_data_phy2mc_xif[82],rd_data_phy2mc_xif[74],rd_data_phy2mc_xif[66],rd_data_phy2mc_xif[121],rd_data_phy2mc_xif[113],rd_data_phy2mc_xif[105],rd_data_phy2mc_xif[97],rd_data_phy2mc_xif[89],rd_data_phy2mc_xif[81],rd_data_phy2mc_xif[73],rd_data_phy2mc_xif[65],rd_data_phy2mc_xif[120],rd_data_phy2mc_xif[112],rd_data_phy2mc_xif[104],rd_data_phy2mc_xif[96],rd_data_phy2mc_xif[88],rd_data_phy2mc_xif[80],rd_data_phy2mc_xif[72],rd_data_phy2mc_xif[64:63],rd_data_phy2mc_xif[55],rd_data_phy2mc_xif[47],rd_data_phy2mc_xif[39],rd_data_phy2mc_xif[31],rd_data_phy2mc_xif[23],rd_data_phy2mc_xif[15],rd_data_phy2mc_xif[7],rd_data_phy2mc_xif[62],rd_data_phy2mc_xif[54],rd_data_phy2mc_xif[46],rd_data_phy2mc_xif[38],rd_data_phy2mc_xif[30],rd_data_phy2mc_xif[22],rd_data_phy2mc_xif[14],rd_data_phy2mc_xif[6],rd_data_phy2mc_xif[61],rd_data_phy2mc_xif[53],rd_data_phy2mc_xif[45],rd_data_phy2mc_xif[37],rd_data_phy2mc_xif[29],rd_data_phy2mc_xif[21],rd_data_phy2mc_xif[13],rd_data_phy2mc_xif[5],rd_data_phy2mc_xif[60],rd_data_phy2mc_xif[52],rd_data_phy2mc_xif[44],rd_data_phy2mc_xif[36],rd_data_phy2mc_xif[28],rd_data_phy2mc_xif[20],rd_data_phy2mc_xif[12],rd_data_phy2mc_xif[4],rd_data_phy2mc_xif[59],rd_data_phy2mc_xif[51],rd_data_phy2mc_xif[43],rd_data_phy2mc_xif[35],rd_data_phy2mc_xif[27],rd_data_phy2mc_xif[19],rd_data_phy2mc_xif[11],rd_data_phy2mc_xif[3],rd_data_phy2mc_xif[58],rd_data_phy2mc_xif[50],rd_data_phy2mc_xif[42],rd_data_phy2mc_xif[34],rd_data_phy2mc_xif[26],rd_data_phy2mc_xif[18],rd_data_phy2mc_xif[10],rd_data_phy2mc_xif[2],rd_data_phy2mc_xif[57],rd_data_phy2mc_xif[49],rd_data_phy2mc_xif[41],rd_data_phy2mc_xif[33],rd_data_phy2mc_xif[25],rd_data_phy2mc_xif[17],rd_data_phy2mc_xif[9],rd_data_phy2mc_xif[1],rd_data_phy2mc_xif[56],rd_data_phy2mc_xif[48],rd_data_phy2mc_xif[40],rd_data_phy2mc_xif[32],rd_data_phy2mc_xif[24],rd_data_phy2mc_xif[16],rd_data_phy2mc_xif[8],rd_data_phy2mc_xif[0]}),
        .DOA(\u_ddr_ui_rd_data/not_strict_mode.rd_status[0]_175 ),
        .DOB({u_ddr_ui_n_25,u_ddr_ui_n_26}),
        .DOC({u_ddr_ui_n_27,u_ddr_ui_n_28}),
        .E(u_io_addr_sync_n_116),
        .O({u_io_write_data_sync_n_73,u_io_write_data_sync_n_74,u_io_write_data_sync_n_75,u_io_write_data_sync_n_76,u_io_write_data_sync_n_77,u_io_write_data_sync_n_78,u_io_write_data_sync_n_79,u_io_write_data_sync_n_80}),
        .Q({wr_data_mask_ni2mc,wr_data_ni2mc}),
        .S(u_ddr_cal_top_n_1900),
        .SR(SR),
        .\SYNC[0].sync_reg_reg[1] (u_ddr_cal_top_n_1612),
        .\SYNC[0].sync_reg_reg[1]_0 (u_ddr_cal_top_n_1806),
        .\SYNC[18].sync_reg_reg[1] (u_ddr_cal_top_n_1882),
        .\SYNC[20].sync_reg_reg[1] (u_ddr_cal_top_n_1665),
        .\SYNC[3].sync_reg_reg[1] (u_ddr_cal_top_n_1802),
        .\SYNC[3].sync_reg_reg[1]_0 (u_ddr_cal_top_n_1803),
        .\SYNC[3].sync_reg_reg[1]_1 (u_ddr_cal_top_n_1804),
        .\SYNC[3].sync_reg_reg[1]_10 (u_ddr_cal_top_n_1814),
        .\SYNC[3].sync_reg_reg[1]_11 (u_ddr_cal_top_n_1815),
        .\SYNC[3].sync_reg_reg[1]_12 (u_ddr_cal_top_n_1816),
        .\SYNC[3].sync_reg_reg[1]_13 (u_ddr_cal_top_n_1817),
        .\SYNC[3].sync_reg_reg[1]_14 (u_ddr_cal_top_n_1818),
        .\SYNC[3].sync_reg_reg[1]_15 (u_ddr_cal_top_n_1819),
        .\SYNC[3].sync_reg_reg[1]_16 (u_ddr_cal_top_n_1820),
        .\SYNC[3].sync_reg_reg[1]_17 (u_ddr_cal_top_n_1821),
        .\SYNC[3].sync_reg_reg[1]_18 (u_ddr_cal_top_n_1822),
        .\SYNC[3].sync_reg_reg[1]_19 (u_ddr_cal_top_n_1823),
        .\SYNC[3].sync_reg_reg[1]_2 (u_ddr_cal_top_n_1805),
        .\SYNC[3].sync_reg_reg[1]_20 (u_ddr_cal_top_n_1824),
        .\SYNC[3].sync_reg_reg[1]_21 (u_ddr_cal_top_n_1825),
        .\SYNC[3].sync_reg_reg[1]_22 (u_ddr_cal_top_n_1826),
        .\SYNC[3].sync_reg_reg[1]_23 (u_ddr_cal_top_n_1827),
        .\SYNC[3].sync_reg_reg[1]_24 (u_ddr_cal_top_n_1828),
        .\SYNC[3].sync_reg_reg[1]_25 (u_ddr_cal_top_n_1829),
        .\SYNC[3].sync_reg_reg[1]_26 (u_ddr_cal_top_n_1830),
        .\SYNC[3].sync_reg_reg[1]_27 (u_ddr_cal_top_n_1831),
        .\SYNC[3].sync_reg_reg[1]_28 (u_ddr_cal_top_n_1832),
        .\SYNC[3].sync_reg_reg[1]_29 (u_ddr_cal_top_n_1833),
        .\SYNC[3].sync_reg_reg[1]_3 (u_ddr_cal_top_n_1807),
        .\SYNC[3].sync_reg_reg[1]_30 (u_ddr_cal_top_n_1834),
        .\SYNC[3].sync_reg_reg[1]_31 (u_ddr_cal_top_n_1835),
        .\SYNC[3].sync_reg_reg[1]_32 (u_ddr_cal_top_n_1836),
        .\SYNC[3].sync_reg_reg[1]_33 (u_ddr_cal_top_n_1837),
        .\SYNC[3].sync_reg_reg[1]_34 (u_ddr_cal_top_n_1838),
        .\SYNC[3].sync_reg_reg[1]_35 (u_ddr_cal_top_n_1839),
        .\SYNC[3].sync_reg_reg[1]_36 (u_ddr_cal_top_n_1840),
        .\SYNC[3].sync_reg_reg[1]_37 (u_ddr_cal_top_n_1841),
        .\SYNC[3].sync_reg_reg[1]_38 (u_ddr_cal_top_n_1842),
        .\SYNC[3].sync_reg_reg[1]_39 (u_ddr_cal_top_n_1843),
        .\SYNC[3].sync_reg_reg[1]_4 (u_ddr_cal_top_n_1808),
        .\SYNC[3].sync_reg_reg[1]_40 (u_ddr_cal_top_n_1844),
        .\SYNC[3].sync_reg_reg[1]_41 (u_ddr_cal_top_n_1845),
        .\SYNC[3].sync_reg_reg[1]_42 (u_ddr_cal_top_n_1846),
        .\SYNC[3].sync_reg_reg[1]_43 (u_ddr_cal_top_n_1847),
        .\SYNC[3].sync_reg_reg[1]_44 (u_ddr_cal_top_n_1848),
        .\SYNC[3].sync_reg_reg[1]_45 (u_ddr_cal_top_n_1849),
        .\SYNC[3].sync_reg_reg[1]_5 (u_ddr_cal_top_n_1809),
        .\SYNC[3].sync_reg_reg[1]_6 (u_ddr_cal_top_n_1810),
        .\SYNC[3].sync_reg_reg[1]_7 (u_ddr_cal_top_n_1811),
        .\SYNC[3].sync_reg_reg[1]_8 (u_ddr_cal_top_n_1812),
        .\SYNC[3].sync_reg_reg[1]_9 (u_ddr_cal_top_n_1813),
        .\SYNC[4].sync_reg_reg[1] (u_ddr_cal_top_n_1866),
        .\SYNC[4].sync_reg_reg[1]_0 (u_ddr_cal_top_n_1877),
        .\SYNC[5].sync_reg_reg[1] (u_ddr_cal_top_n_1778),
        .\SYNC[5].sync_reg_reg[1]_0 (u_ddr_cal_top_n_1779),
        .\SYNC[5].sync_reg_reg[1]_1 (u_ddr_cal_top_n_1850),
        .\SYNC[5].sync_reg_reg[1]_10 (u_ddr_cal_top_n_1860),
        .\SYNC[5].sync_reg_reg[1]_11 (u_ddr_cal_top_n_1861),
        .\SYNC[5].sync_reg_reg[1]_12 (u_ddr_cal_top_n_1862),
        .\SYNC[5].sync_reg_reg[1]_13 (u_ddr_cal_top_n_1863),
        .\SYNC[5].sync_reg_reg[1]_14 (u_ddr_cal_top_n_1874),
        .\SYNC[5].sync_reg_reg[1]_15 (u_ddr_cal_top_n_1880),
        .\SYNC[5].sync_reg_reg[1]_16 (u_ddr_cal_top_n_1883),
        .\SYNC[5].sync_reg_reg[1]_17 (u_ddr_cal_top_n_1905),
        .\SYNC[5].sync_reg_reg[1]_2 (u_ddr_cal_top_n_1851),
        .\SYNC[5].sync_reg_reg[1]_3 (u_ddr_cal_top_n_1852),
        .\SYNC[5].sync_reg_reg[1]_4 (u_ddr_cal_top_n_1853),
        .\SYNC[5].sync_reg_reg[1]_5 (u_ddr_cal_top_n_1855),
        .\SYNC[5].sync_reg_reg[1]_6 (u_ddr_cal_top_n_1856),
        .\SYNC[5].sync_reg_reg[1]_7 (u_ddr_cal_top_n_1857),
        .\SYNC[5].sync_reg_reg[1]_8 (u_ddr_cal_top_n_1858),
        .\SYNC[5].sync_reg_reg[1]_9 (u_ddr_cal_top_n_1859),
        .a_b_cmd_sel_start(\u_ddr_cal/u_ddr_cal_addr_decode/a_b_cmd_sel_start ),
        .a_b_cmd_sel_start0(\u_ddr_cal/u_ddr_cal_addr_decode/a_b_cmd_sel_start0 ),
        .a_b_cmd_sel_start_reg(u_io_write_data_sync_n_105),
        .\addr_dec_to_mb_data[0]_i_3 (u_io_addr_sync_n_94),
        .\addr_dec_to_mb_data[31]_i_3 (u_io_addr_sync_n_109),
        .\addr_dec_to_mb_data[4]_i_11 (u_io_addr_sync_n_100),
        .\addr_dec_to_mb_data[6]_i_7 (u_io_addr_sync_n_138),
        .\addr_dec_to_mb_data[6]_i_7_0 (u_io_addr_sync_n_137),
        .\addr_dec_to_mb_data[7]_i_7 (u_io_addr_sync_n_96),
        .\addr_dec_to_mb_data_reg[12] (u_io_addr_sync_n_105),
        .\addr_dec_to_mb_data_reg[14] (u_io_addr_sync_n_102),
        .\addr_dec_to_mb_data_reg[15] (u_io_addr_sync_n_98),
        .\addr_dec_to_mb_data_reg[19] (u_io_addr_sync_n_99),
        .\addr_dec_to_mb_data_reg[20] (u_io_addr_sync_n_125),
        .\addr_dec_to_mb_data_reg[21] (u_io_addr_sync_n_124),
        .\addr_dec_to_mb_data_reg[22] (u_io_addr_sync_n_128),
        .\addr_dec_to_mb_data_reg[23] (u_io_addr_sync_n_127),
        .\addr_dec_to_mb_data_reg[24] (u_io_addr_sync_n_123),
        .\addr_dec_to_mb_data_reg[25] (u_io_addr_sync_n_122),
        .\addr_dec_to_mb_data_reg[26] (u_io_addr_sync_n_121),
        .\addr_dec_to_mb_data_reg[27] (u_io_addr_sync_n_120),
        .\addr_dec_to_mb_data_reg[28] (u_io_addr_sync_n_119),
        .\addr_dec_to_mb_data_reg[29] (u_io_addr_sync_n_104),
        .\addr_dec_to_mb_data_reg[29]_0 (u_io_addr_sync_n_92),
        .\addr_dec_to_mb_data_reg[29]_1 (u_io_addr_sync_n_108),
        .\addr_dec_to_mb_data_reg[29]_2 (u_io_addr_sync_n_90),
        .\addr_dec_to_mb_data_reg[29]_3 (u_io_addr_sync_n_101),
        .\addr_dec_to_mb_data_reg[29]_4 (u_io_addr_sync_n_118),
        .\addr_dec_to_mb_data_reg[30] (u_io_addr_sync_n_95),
        .\addr_dec_to_mb_data_reg[30]_0 (u_io_addr_sync_n_126),
        .\addr_dec_to_mb_data_reg[31] ({\u_ddr_cal/u_ddr_cal_addr_decode/addr_dec_to_mb_data [31],\u_ddr_cal/u_ddr_cal_addr_decode/addr_dec_to_mb_data [19:0]}),
        .\bisc_bit_reg[0] (u_io_addr_sync_n_56),
        .bisc_byte(bisc_byte),
        .calDone(calDone),
        .calDone_gated_reg_0(c0_init_calib_complete),
        .calDone_gated_reg_1(phy_ready),
        .calDone_reg(u_io_addr_sync_n_44),
        .\calSt_reg[0] (\calSt_reg[0] ),
        .calWrCAS(calWrCAS),
        .\cal_ACT_n_A_reg[7] (\u_ddr_cal/u_ddr_cal_addr_decode/cal_ACT_n_A ),
        .\cal_ADR_A_reg[0] (u_ddr_cal_top_n_1726),
        .\cal_ADR_A_reg[0]_0 (u_ddr_cal_top_n_1886),
        .\cal_ADR_A_reg[1] (u_ddr_cal_top_n_1797),
        .\cal_ADR_A_reg[20] (u_ddr_cal_top_n_1787),
        .\cal_ADR_A_reg[21] (u_ddr_cal_top_n_1786),
        .\cal_ADR_A_reg[22] (u_ddr_cal_top_n_1854),
        .\cal_ADR_A_reg[26] (u_ddr_cal_top_n_1783),
        .\cal_ADR_A_reg[27] (u_ddr_cal_top_n_1782),
        .\cal_ADR_A_reg[29] (u_ddr_cal_top_n_1781),
        .\cal_ADR_A_reg[2] (u_ddr_cal_top_n_1881),
        .\cal_ADR_A_reg[30] ({u_ddr_cal_top_n_1766,u_ddr_cal_top_n_1767,u_ddr_cal_top_n_1768,u_ddr_cal_top_n_1769,u_ddr_cal_top_n_1770,u_ddr_cal_top_n_1771,u_ddr_cal_top_n_1772,u_ddr_cal_top_n_1773,u_ddr_cal_top_n_1774,u_ddr_cal_top_n_1775,u_ddr_cal_top_n_1776,u_ddr_cal_top_n_1777}),
        .\cal_ADR_A_reg[31] (u_io_addr_sync_n_27),
        .\cal_ADR_A_reg[3] (u_ddr_cal_top_n_1879),
        .\cal_ADR_A_reg[4] (u_ddr_cal_top_n_1798),
        .\cal_ADR_A_reg[4]_0 (u_ddr_cal_top_n_1875),
        .\cal_ADR_B_reg[10] (u_ddr_cal_top_n_1795),
        .\cal_ADR_B_reg[11] (u_ddr_cal_top_n_1794),
        .\cal_ADR_B_reg[12] (u_ddr_cal_top_n_1724),
        .\cal_ADR_B_reg[13] (u_ddr_cal_top_n_1793),
        .\cal_ADR_B_reg[15] (u_ddr_cal_top_n_1792),
        .\cal_ADR_B_reg[17] (u_ddr_cal_top_n_1790),
        .\cal_ADR_B_reg[18] (u_ddr_cal_top_n_1789),
        .\cal_ADR_B_reg[19] (u_ddr_cal_top_n_1788),
        .\cal_ADR_B_reg[24] (u_ddr_cal_top_n_1785),
        .\cal_ADR_B_reg[25] (u_ddr_cal_top_n_1784),
        .\cal_ADR_B_reg[30] ({u_ddr_cal_top_n_1753,u_ddr_cal_top_n_1754,u_ddr_cal_top_n_1755,u_ddr_cal_top_n_1756,u_ddr_cal_top_n_1757,u_ddr_cal_top_n_1758,u_ddr_cal_top_n_1759,u_ddr_cal_top_n_1760,u_ddr_cal_top_n_1761,u_ddr_cal_top_n_1762,u_ddr_cal_top_n_1763,u_ddr_cal_top_n_1764,u_ddr_cal_top_n_1765}),
        .\cal_ADR_B_reg[31] (u_ddr_cal_top_n_1801),
        .\cal_ADR_B_reg[31]_0 (u_io_addr_sync_n_32),
        .cal_BA(cal_BA),
        .\cal_CAS_A_reg[0] (u_io_addr_sync_n_68),
        .\cal_CS_A_reg[0] (u_ddr_cal_top_n_1666),
        .\cal_CS_A_reg[4] (u_ddr_cal_top_n_1876),
        .\cal_CS_A_reg[5] ({u_ddr_cal_top_n_1748,u_ddr_cal_top_n_1749,u_ddr_cal_top_n_1750,u_ddr_cal_top_n_1751,u_ddr_cal_top_n_1752}),
        .\cal_CS_A_reg[6] (u_ddr_cal_top_n_1653),
        .\cal_CS_A_reg[7] (u_ddr_cal_top_n_1664),
        .\cal_CS_A_reg[7]_0 (u_io_addr_sync_n_25),
        .\cal_CS_B_reg[5] ({u_ddr_cal_top_n_1743,u_ddr_cal_top_n_1744,u_ddr_cal_top_n_1745,u_ddr_cal_top_n_1746,u_ddr_cal_top_n_1747}),
        .\cal_CS_B_reg[7] (u_io_addr_sync_n_23),
        .cal_CS_n({cal_CS_n[6:5],cal_CS_n[2:1]}),
        .\cal_DMOut_n_A_reg[31] (u_io_addr_sync_n_65),
        .\cal_DQOut_A_reg[31] (u_io_addr_sync_n_37),
        .\cal_DQOut_A_reg[63] (u_io_addr_sync_n_36),
        .\cal_DQOut_post_reg[31] (u_io_addr_sync_n_40),
        .\cal_DQOut_post_reg[63] (u_io_addr_sync_n_41),
        .\cal_DQOut_pre_reg[31] (u_io_addr_sync_n_39),
        .\cal_DQOut_pre_reg[63] (u_io_addr_sync_n_38),
        .\cal_DQPat_A_reg[31] (u_io_addr_sync_n_34),
        .\cal_DQPat_A_reg[63] (u_io_addr_sync_n_35),
        .\cal_DQPat_B_reg[31] (u_io_addr_sync_n_42),
        .\cal_DQPat_B_reg[63] (u_io_addr_sync_n_43),
        .\cal_RAS_B_reg[0] (u_io_addr_sync_n_24),
        .\cal_RESET_n_reg[7]_0 (cal_RESET_n),
        .\cal_RST_CKE_ODT_PAR_reg[16] (u_ddr_cal_top_n_1791),
        .\cal_RST_CKE_ODT_PAR_reg[30] ({u_ddr_cal_top_n_1727,u_ddr_cal_top_n_1728,u_ddr_cal_top_n_1729,u_ddr_cal_top_n_1730,u_ddr_cal_top_n_1731,\u_ddr_cal/ub_cal_RESET_n [7:5],\u_ddr_cal/ub_cal_RESET_n [3:1]}),
        .\cal_RST_CKE_ODT_PAR_reg[31] (u_io_addr_sync_n_26),
        .\cal_RST_CKE_ODT_PAR_reg[9] (u_ddr_cal_top_n_1796),
        .\cal_cmp_en_reg[7] (u_io_addr_sync_n_45),
        .\cal_cs_pos_reg[1] (u_io_addr_sync_n_33),
        .\cal_mcal_DMIn_n_reg[63]_0 (mcal_DMIn_n),
        .cal_oe_dis_low(cal_oe_dis_low),
        .\cal_oe_dis_low_reg[7] (u_io_addr_sync_n_113),
        .cal_oe_dis_upp(cal_oe_dis_upp),
        .\cal_oe_dis_upp_reg[7] (u_io_addr_sync_n_114),
        .\cal_seq_a_a_dly_reg[7] (u_io_addr_sync_n_29),
        .\cal_seq_a_b_dly_reg[7] (u_io_addr_sync_n_30),
        .\cal_seq_b_a_dly_reg[7] (u_io_addr_sync_n_31),
        .cal_seq_cnt_gt_0_reg(u_io_write_data_sync_n_32),
        .\cal_seq_cnt_reg[13] (u_ddr_cal_top_n_1799),
        .\cal_seq_cnt_reg[31] ({u_ddr_cal_top_n_1621,u_ddr_cal_top_n_1622,u_ddr_cal_top_n_1623,u_ddr_cal_top_n_1624,u_ddr_cal_top_n_1625,u_ddr_cal_top_n_1626,u_ddr_cal_top_n_1627,u_ddr_cal_top_n_1628,u_ddr_cal_top_n_1629,u_ddr_cal_top_n_1630,u_ddr_cal_top_n_1631,u_ddr_cal_top_n_1632,u_ddr_cal_top_n_1633,u_ddr_cal_top_n_1634,u_ddr_cal_top_n_1635,u_ddr_cal_top_n_1636,u_ddr_cal_top_n_1637,u_ddr_cal_top_n_1638,u_ddr_cal_top_n_1639,u_ddr_cal_top_n_1640,u_ddr_cal_top_n_1641,u_ddr_cal_top_n_1642,u_ddr_cal_top_n_1643,u_ddr_cal_top_n_1644,u_ddr_cal_top_n_1645,u_ddr_cal_top_n_1646,u_ddr_cal_top_n_1647,u_ddr_cal_top_n_1648,u_ddr_cal_top_n_1649,u_ddr_cal_top_n_1650,u_ddr_cal_top_n_1651,u_ddr_cal_top_n_1652}),
        .\cal_seq_rd_cnt_reg[7] ({u_ddr_cal_top_n_1613,u_ddr_cal_top_n_1614,u_ddr_cal_top_n_1615,u_ddr_cal_top_n_1616,u_ddr_cal_top_n_1617,u_ddr_cal_top_n_1618,u_ddr_cal_top_n_1619,u_ddr_cal_top_n_1620}),
        .\cal_seq_reg[2] (u_io_addr_sync_n_48),
        .cal_timer_reg(\u_ddr_cal/u_ddr_cal_addr_decode/cal_timer_reg ),
        .\cal_timer_reg[15] ({u_io_write_data_sync_n_81,u_io_write_data_sync_n_82,u_io_write_data_sync_n_83,u_io_write_data_sync_n_84,u_io_write_data_sync_n_85,u_io_write_data_sync_n_86,u_io_write_data_sync_n_87,u_io_write_data_sync_n_88}),
        .\cal_timer_reg[23] ({u_io_write_data_sync_n_89,u_io_write_data_sync_n_90,u_io_write_data_sync_n_91,u_io_write_data_sync_n_92,u_io_write_data_sync_n_93,u_io_write_data_sync_n_94,u_io_write_data_sync_n_95,u_io_write_data_sync_n_96}),
        .\cal_timer_reg[31] ({u_io_write_data_sync_n_97,u_io_write_data_sync_n_98,u_io_write_data_sync_n_99,u_io_write_data_sync_n_100,u_io_write_data_sync_n_101,u_io_write_data_sync_n_102,u_io_write_data_sync_n_103,u_io_write_data_sync_n_104}),
        .cal_timer_reg_0_sp_1(u_io_addr_sync_n_53),
        .cal_timer_reg_21_sp_1(u_ddr_cal_top_n_1742),
        .cal_timer_reg_24_sp_1(u_ddr_cal_top_n_1741),
        .cal_timer_reg_25_sp_1(u_ddr_cal_top_n_1740),
        .cal_timer_reg_28_sp_1(u_ddr_cal_top_n_1739),
        .cal_timer_reg_29_sp_1(u_ddr_cal_top_n_1738),
        .ch0_mcal_DMOut_n(ch0_mcal_DMOut_n),
        .ch0_mcal_DQOut(ch0_mcal_DQOut),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 (ch1_mcal_clb2phy_fifo_rden),
        .\clb2phy_wrcs0_low_reg[31] (u_io_addr_sync_n_66),
        .clear_gt_data_ready_flag(\u_ddr_cal/u_ddr_cal_addr_decode/clear_gt_data_ready_flag ),
        .clear_gt_data_ready_flag_reg(u_ddr_cal_top_n_758),
        .cmdBuf(cmdBuf),
        .\cmp_byte_reg[2] (u_io_addr_sync_n_28),
        .cnt_clr(\u_ddr_cal/u_ddr_cal_addr_decode/cnt_clr ),
        .cnt_clr_access(\u_ddr_cal/u_ddr_cal_addr_decode/cnt_clr_access ),
        .cnt_clr_reg(u_io_addr_sync_n_111),
        .\cplx_CAS_reg[6] ({cal_ADR[126:125],cal_ADR[122:121],cal_ADR[118:117],cal_ADR[114:113]}),
        .\cplx_config_reg[0] (\u_ddr_cal/u_ddr_cal_addr_decode/cplx_config0_out ),
        .\cplx_config_reg[16] (io_write_strobe),
        .\cplx_config_reg[16]_0 (u_io_addr_sync_n_97),
        .\cplx_config_reg[1] (u_io_addr_sync_n_115),
        .\cplx_error_accum_reg[14] (u_ddr_cal_top_n_1667),
        .\cplx_error_accum_reg[15] (u_ddr_cal_top_n_1722),
        .\cplx_error_accum_reg[19] (u_ddr_cal_top_n_1725),
        .\cplx_error_accum_reg[44] (u_ddr_cal_top_n_1723),
        .\cplx_error_accum_reg[63] ({\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log74 [31:20],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log74 [18:16],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log74 [13],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log74 [11:1],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log30 [31:20],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log30 [18:16],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log30 [13],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log30 [11:1]}),
        .cplx_status(\u_ddr_cal/u_ddr_cal_addr_decode/p_1_in ),
        .\dReg_reg[10] (\SYNC[19].sync_reg_reg[1] ),
        .\delay_cntr_reg[2] ({u_ddr_cal_top_n_1901,u_ddr_cal_top_n_1902}),
        .\dout_o_reg[11] ({\u_ddr_cal/config_rd_data [11:8],\u_ddr_cal/config_rd_data [6:0]}),
        .\dout_o_reg[11]_0 ({\u_ddr_cal/u_ddr_config_rom/mem [11:8],\u_ddr_cal/u_ddr_config_rom/mem [6:0]}),
        .\dout_o_reg[5] (u_ddr_cal_top_n_1887),
        .douta(\u_ddr_cal/bramA_do ),
        .en_vtc(en_vtc),
        .ena(\u_ddr_cal/ub_xsdb_rd_en ),
        .\genblk10[3].cal_DMOut_n_A_r_reg[24] (u_io_addr_sync_n_22),
        .\genblk10[6].cal_DMOut_n_A_r_reg[48] (u_io_addr_sync_n_107),
        .\genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8] (u_ddr_cal_top_n_1865),
        .\genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9] (u_ddr_cal_top_n_1864),
        .gt_data_ready_flag(\u_ddr_cal/u_ddr_cal_addr_decode/gt_data_ready_flag ),
        .gt_data_ready_flag_nxt(\u_ddr_cal/u_ddr_cal_addr_decode/gt_data_ready_flag_nxt ),
        .gt_data_ready_flag_reg(u_ddr_cal_top_n_1884),
        .in0(\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buf_we_orig ),
        .initDone(\u_ddr_cal/initDone ),
        .io_addr_strobe(io_addr_strobe),
        .io_addr_strobe_lvl_r1_reg_0(io_addr_strobe_lvl),
        .io_address({io_address[23:20],io_address[18],io_address[15:0]}),
        .\io_read_data_reg[31] (io_read_data),
        .io_ready_lvl_reg(io_ready_lvl),
        .io_ready_reg(u_io_addr_sync_n_91),
        .io_ready_reg_0(u_io_addr_sync_n_93),
        .io_ready_reg_1(u_io_addr_sync_n_106),
        .io_write_data(io_write_data),
        .lrdimm_cal_mode_reg(u_ddr_cal_top_n_1903),
        .lrdimm_cal_mode_reg_0(u_ddr_cal_top_n_1904),
        .lrdimm_cal_mode_reg_1(u_io_addr_sync_n_55),
        .lrdimm_cmp_clr(\u_ddr_cal/u_ddr_cal_addr_decode/lrdimm_cmp_clr ),
        .lrdimm_cmp_en(\u_ddr_cal/u_ddr_cal_addr_decode/lrdimm_cmp_en ),
        .lrdimm_cmp_en_reg(u_io_addr_sync_n_112),
        .match4_10_return(\u_ddr_ui_rd_data/match4_10_return ),
        .match4_110_return(\u_ddr_ui_rd_data/match4_110_return ),
        .match4_111_return(\u_ddr_ui_rd_data/match4_111_return ),
        .match4_112_return(\u_ddr_ui_rd_data/match4_112_return ),
        .match4_113_return(\u_ddr_ui_rd_data/match4_113_return ),
        .match4_114_return(\u_ddr_ui_rd_data/match4_114_return ),
        .match4_115_return(\u_ddr_ui_rd_data/match4_115_return ),
        .match4_116_return(\u_ddr_ui_rd_data/match4_116_return ),
        .match4_117_return(\u_ddr_ui_rd_data/match4_117_return ),
        .match4_118_return(\u_ddr_ui_rd_data/match4_118_return ),
        .match4_119_return(\u_ddr_ui_rd_data/match4_119_return ),
        .match4_11_return(\u_ddr_ui_rd_data/match4_11_return ),
        .match4_120_return(\u_ddr_ui_rd_data/match4_120_return ),
        .match4_121_return(\u_ddr_ui_rd_data/match4_121_return ),
        .match4_122_return(\u_ddr_ui_rd_data/match4_122_return ),
        .match4_123_return(\u_ddr_ui_rd_data/match4_123_return ),
        .match4_124_return(\u_ddr_ui_rd_data/match4_124_return ),
        .match4_125_return(\u_ddr_ui_rd_data/match4_125_return ),
        .match4_126_return(\u_ddr_ui_rd_data/match4_126_return ),
        .match4_127_return(\u_ddr_ui_rd_data/match4_127_return ),
        .match4_128_return(\u_ddr_ui_rd_data/match4_128_return ),
        .match4_129_return(\u_ddr_ui_rd_data/match4_129_return ),
        .match4_12_return(\u_ddr_ui_rd_data/match4_12_return ),
        .match4_130_return(\u_ddr_ui_rd_data/match4_130_return ),
        .match4_131_return(\u_ddr_ui_rd_data/match4_131_return ),
        .match4_132_return(\u_ddr_ui_rd_data/match4_132_return ),
        .match4_133_return(\u_ddr_ui_rd_data/match4_133_return ),
        .match4_134_return(\u_ddr_ui_rd_data/match4_134_return ),
        .match4_135_return(\u_ddr_ui_rd_data/match4_135_return ),
        .match4_136_return(\u_ddr_ui_rd_data/match4_136_return ),
        .match4_137_return(\u_ddr_ui_rd_data/match4_137_return ),
        .match4_138_return(\u_ddr_ui_rd_data/match4_138_return ),
        .match4_139_return(\u_ddr_ui_rd_data/match4_139_return ),
        .match4_13_return(\u_ddr_ui_rd_data/match4_13_return ),
        .match4_140_return(\u_ddr_ui_rd_data/match4_140_return ),
        .match4_141_return(\u_ddr_ui_rd_data/match4_141_return ),
        .match4_142_return(\u_ddr_ui_rd_data/match4_142_return ),
        .match4_143_return(\u_ddr_ui_rd_data/match4_143_return ),
        .match4_144_return(\u_ddr_ui_rd_data/match4_144_return ),
        .match4_145_return(\u_ddr_ui_rd_data/match4_145_return ),
        .match4_146_return(\u_ddr_ui_rd_data/match4_146_return ),
        .match4_147_return(\u_ddr_ui_rd_data/match4_147_return ),
        .match4_148_return(\u_ddr_ui_rd_data/match4_148_return ),
        .match4_149_return(\u_ddr_ui_rd_data/match4_149_return ),
        .match4_14_return(\u_ddr_ui_rd_data/match4_14_return ),
        .match4_150_return(\u_ddr_ui_rd_data/match4_150_return ),
        .match4_151_return(\u_ddr_ui_rd_data/match4_151_return ),
        .match4_152_return(\u_ddr_ui_rd_data/match4_152_return ),
        .match4_153_return(\u_ddr_ui_rd_data/match4_153_return ),
        .match4_154_return(\u_ddr_ui_rd_data/match4_154_return ),
        .match4_155_return(\u_ddr_ui_rd_data/match4_155_return ),
        .match4_156_return(\u_ddr_ui_rd_data/match4_156_return ),
        .match4_157_return(\u_ddr_ui_rd_data/match4_157_return ),
        .match4_158_return(\u_ddr_ui_rd_data/match4_158_return ),
        .match4_159_return(\u_ddr_ui_rd_data/match4_159_return ),
        .match4_15_return(\u_ddr_ui_rd_data/match4_15_return ),
        .match4_160_return(\u_ddr_ui_rd_data/match4_160_return ),
        .match4_161_return(\u_ddr_ui_rd_data/match4_161_return ),
        .match4_162_return(\u_ddr_ui_rd_data/match4_162_return ),
        .match4_163_return(\u_ddr_ui_rd_data/match4_163_return ),
        .match4_164_return(\u_ddr_ui_rd_data/match4_164_return ),
        .match4_165_return(\u_ddr_ui_rd_data/match4_165_return ),
        .match4_166_return(\u_ddr_ui_rd_data/match4_166_return ),
        .match4_167_return(\u_ddr_ui_rd_data/match4_167_return ),
        .match4_168_return(\u_ddr_ui_rd_data/match4_168_return ),
        .match4_169_return(\u_ddr_ui_rd_data/match4_169_return ),
        .match4_16_return(\u_ddr_ui_rd_data/match4_16_return ),
        .match4_170_return(\u_ddr_ui_rd_data/match4_170_return ),
        .match4_171_return(\u_ddr_ui_rd_data/match4_171_return ),
        .match4_172_return(\u_ddr_ui_rd_data/match4_172_return ),
        .match4_173_return(\u_ddr_ui_rd_data/match4_173_return ),
        .match4_174_return(\u_ddr_ui_rd_data/match4_174_return ),
        .match4_175_return(\u_ddr_ui_rd_data/match4_175_return ),
        .match4_176_return(\u_ddr_ui_rd_data/match4_176_return ),
        .match4_177_return(\u_ddr_ui_rd_data/match4_177_return ),
        .match4_178_return(\u_ddr_ui_rd_data/match4_178_return ),
        .match4_179_return(\u_ddr_ui_rd_data/match4_179_return ),
        .match4_17_return(\u_ddr_ui_rd_data/match4_17_return ),
        .match4_180_return(\u_ddr_ui_rd_data/match4_180_return ),
        .match4_181_return(\u_ddr_ui_rd_data/match4_181_return ),
        .match4_182_return(\u_ddr_ui_rd_data/match4_182_return ),
        .match4_183_return(\u_ddr_ui_rd_data/match4_183_return ),
        .match4_184_return(\u_ddr_ui_rd_data/match4_184_return ),
        .match4_185_return(\u_ddr_ui_rd_data/match4_185_return ),
        .match4_186_return(\u_ddr_ui_rd_data/match4_186_return ),
        .match4_187_return(\u_ddr_ui_rd_data/match4_187_return ),
        .match4_188_return(\u_ddr_ui_rd_data/match4_188_return ),
        .match4_18_return(\u_ddr_ui_rd_data/match4_18_return ),
        .match4_19_return(\u_ddr_ui_rd_data/match4_19_return ),
        .match4_1_return(\u_ddr_ui_rd_data/match4_1_return ),
        .match6_10_return(\u_ddr_ui_rd_data/match6_10_return ),
        .match6_110_return(\u_ddr_ui_rd_data/match6_110_return ),
        .match6_111_return(\u_ddr_ui_rd_data/match6_111_return ),
        .match6_112_return(\u_ddr_ui_rd_data/match6_112_return ),
        .match6_113_return(\u_ddr_ui_rd_data/match6_113_return ),
        .match6_114_return(\u_ddr_ui_rd_data/match6_114_return ),
        .match6_115_return(\u_ddr_ui_rd_data/match6_115_return ),
        .match6_116_return(\u_ddr_ui_rd_data/match6_116_return ),
        .match6_117_return(\u_ddr_ui_rd_data/match6_117_return ),
        .match6_118_return(\u_ddr_ui_rd_data/match6_118_return ),
        .match6_119_return(\u_ddr_ui_rd_data/match6_119_return ),
        .match6_11_return(\u_ddr_ui_rd_data/match6_11_return ),
        .match6_120_return(\u_ddr_ui_rd_data/match6_120_return ),
        .match6_121_return(\u_ddr_ui_rd_data/match6_121_return ),
        .match6_122_return(\u_ddr_ui_rd_data/match6_122_return ),
        .match6_123_return(\u_ddr_ui_rd_data/match6_123_return ),
        .match6_124_return(\u_ddr_ui_rd_data/match6_124_return ),
        .match6_125_return(\u_ddr_ui_rd_data/match6_125_return ),
        .match6_126_return(\u_ddr_ui_rd_data/match6_126_return ),
        .match6_127_return(\u_ddr_ui_rd_data/match6_127_return ),
        .match6_128_return(\u_ddr_ui_rd_data/match6_128_return ),
        .match6_129_return(\u_ddr_ui_rd_data/match6_129_return ),
        .match6_12_return(\u_ddr_ui_rd_data/match6_12_return ),
        .match6_130_return(\u_ddr_ui_rd_data/match6_130_return ),
        .match6_131_return(\u_ddr_ui_rd_data/match6_131_return ),
        .match6_132_return(\u_ddr_ui_rd_data/match6_132_return ),
        .match6_133_return(\u_ddr_ui_rd_data/match6_133_return ),
        .match6_134_return(\u_ddr_ui_rd_data/match6_134_return ),
        .match6_135_return(\u_ddr_ui_rd_data/match6_135_return ),
        .match6_136_return(\u_ddr_ui_rd_data/match6_136_return ),
        .match6_137_return(\u_ddr_ui_rd_data/match6_137_return ),
        .match6_138_return(\u_ddr_ui_rd_data/match6_138_return ),
        .match6_139_return(\u_ddr_ui_rd_data/match6_139_return ),
        .match6_13_return(\u_ddr_ui_rd_data/match6_13_return ),
        .match6_140_return(\u_ddr_ui_rd_data/match6_140_return ),
        .match6_141_return(\u_ddr_ui_rd_data/match6_141_return ),
        .match6_142_return(\u_ddr_ui_rd_data/match6_142_return ),
        .match6_143_return(\u_ddr_ui_rd_data/match6_143_return ),
        .match6_144_return(\u_ddr_ui_rd_data/match6_144_return ),
        .match6_145_return(\u_ddr_ui_rd_data/match6_145_return ),
        .match6_146_return(\u_ddr_ui_rd_data/match6_146_return ),
        .match6_147_return(\u_ddr_ui_rd_data/match6_147_return ),
        .match6_148_return(\u_ddr_ui_rd_data/match6_148_return ),
        .match6_149_return(\u_ddr_ui_rd_data/match6_149_return ),
        .match6_14_return(\u_ddr_ui_rd_data/match6_14_return ),
        .match6_150_return(\u_ddr_ui_rd_data/match6_150_return ),
        .match6_151_return(\u_ddr_ui_rd_data/match6_151_return ),
        .match6_152_return(\u_ddr_ui_rd_data/match6_152_return ),
        .match6_153_return(\u_ddr_ui_rd_data/match6_153_return ),
        .match6_154_return(\u_ddr_ui_rd_data/match6_154_return ),
        .match6_155_return(\u_ddr_ui_rd_data/match6_155_return ),
        .match6_156_return(\u_ddr_ui_rd_data/match6_156_return ),
        .match6_157_return(\u_ddr_ui_rd_data/match6_157_return ),
        .match6_158_return(\u_ddr_ui_rd_data/match6_158_return ),
        .match6_159_return(\u_ddr_ui_rd_data/match6_159_return ),
        .match6_15_return(\u_ddr_ui_rd_data/match6_15_return ),
        .match6_160_return(\u_ddr_ui_rd_data/match6_160_return ),
        .match6_161_return(\u_ddr_ui_rd_data/match6_161_return ),
        .match6_162_return(\u_ddr_ui_rd_data/match6_162_return ),
        .match6_163_return(\u_ddr_ui_rd_data/match6_163_return ),
        .match6_164_return(\u_ddr_ui_rd_data/match6_164_return ),
        .match6_165_return(\u_ddr_ui_rd_data/match6_165_return ),
        .match6_166_return(\u_ddr_ui_rd_data/match6_166_return ),
        .match6_167_return(\u_ddr_ui_rd_data/match6_167_return ),
        .match6_168_return(\u_ddr_ui_rd_data/match6_168_return ),
        .match6_169_return(\u_ddr_ui_rd_data/match6_169_return ),
        .match6_16_return(\u_ddr_ui_rd_data/match6_16_return ),
        .match6_170_return(\u_ddr_ui_rd_data/match6_170_return ),
        .match6_171_return(\u_ddr_ui_rd_data/match6_171_return ),
        .match6_172_return(\u_ddr_ui_rd_data/match6_172_return ),
        .match6_173_return(\u_ddr_ui_rd_data/match6_173_return ),
        .match6_174_return(\u_ddr_ui_rd_data/match6_174_return ),
        .match6_175_return(\u_ddr_ui_rd_data/match6_175_return ),
        .match6_176_return(\u_ddr_ui_rd_data/match6_176_return ),
        .match6_177_return(\u_ddr_ui_rd_data/match6_177_return ),
        .match6_178_return(\u_ddr_ui_rd_data/match6_178_return ),
        .match6_179_return(\u_ddr_ui_rd_data/match6_179_return ),
        .match6_17_return(\u_ddr_ui_rd_data/match6_17_return ),
        .match6_180_return(\u_ddr_ui_rd_data/match6_180_return ),
        .match6_181_return(\u_ddr_ui_rd_data/match6_181_return ),
        .match6_182_return(\u_ddr_ui_rd_data/match6_182_return ),
        .match6_183_return(\u_ddr_ui_rd_data/match6_183_return ),
        .match6_184_return(\u_ddr_ui_rd_data/match6_184_return ),
        .match6_185_return(\u_ddr_ui_rd_data/match6_185_return ),
        .match6_186_return(\u_ddr_ui_rd_data/match6_186_return ),
        .match6_187_return(\u_ddr_ui_rd_data/match6_187_return ),
        .match6_188_return(\u_ddr_ui_rd_data/match6_188_return ),
        .match6_18_return(\u_ddr_ui_rd_data/match6_18_return ),
        .match6_19_return(\u_ddr_ui_rd_data/match6_19_return ),
        .match6_1_return(\u_ddr_ui_rd_data/match6_1_return ),
        .\max_rd_lat_reg[5] (u_io_addr_sync_n_54),
        .mcCasSlot2(mcCasSlot2),
        .mcRdCAS(mcRdCAS),
        .mcWrCAS(mcWrCAS),
        .mc_ADR({mc_ADR[131],mc_ADR[123],mc_ADR[115],mc_ADR[109],mc_ADR[107],mc_ADR[99],mc_ADR[91],mc_ADR[85],mc_ADR[83],mc_ADR[81],mc_ADR[77],mc_ADR[75],mc_ADR[73],mc_ADR[69],mc_ADR[67],mc_ADR[65],mc_ADR[61],mc_ADR[59],mc_ADR[57],mc_ADR[53],mc_ADR[51],mc_ADR[49],mc_ADR[45],mc_ADR[43],mc_ADR[41],mc_ADR[37],mc_ADR[35],mc_ADR[33],mc_ADR[29],mc_ADR[27],mc_ADR[25],mc_ADR[19],mc_ADR[11],mc_ADR[5],mc_ADR[3],mc_ADR[1]}),
        .\mc_ADR7_reg[16]_0 ({u_ddr_mc_n_73,u_ddr_mc_n_74,u_ddr_mc_n_75,mc_ADR[111],mc_ADR[87]}),
        .mc_BA({mc_BA[15],mc_BA[13],mc_BA[11],mc_BA[9],mc_BA[7],mc_BA[5],mc_BA[1]}),
        .mc_BG({mc_BG[7],mc_BG[5],mc_BG[1]}),
        .mc_CKE({mc_CKE[7],mc_CKE[5]}),
        .mc_CS_n(mc_CS_n),
        .mc_ODT({mc_ODT[7],mc_ODT[3]}),
        .mcal_ACT_n(mcal_ACT_n),
        .mcal_ADR({mcal_ADR[135:110],mcal_ADR[108],mcal_ADR[104:102],mcal_ADR[100],mcal_ADR[96:94],mcal_ADR[92],mcal_ADR[88:86],mcal_ADR[84],mcal_ADR[82],mcal_ADR[80:78],mcal_ADR[76],mcal_ADR[74],mcal_ADR[72:70],mcal_ADR[68],mcal_ADR[66],mcal_ADR[64:62],mcal_ADR[60],mcal_ADR[58],mcal_ADR[56:54],mcal_ADR[52],mcal_ADR[50],mcal_ADR[48:46],mcal_ADR[44],mcal_ADR[42],mcal_ADR[40:38],mcal_ADR[36],mcal_ADR[34],mcal_ADR[32:30],mcal_ADR[28],mcal_ADR[26],mcal_ADR[24:22],mcal_ADR[20],mcal_ADR[16:14],mcal_ADR[12],mcal_ADR[8:6],mcal_ADR[4],mcal_ADR[2],mcal_ADR[0]}),
        .\mcal_ADR_dly_reg[0][126]_0 ({u_ddr_mc_n_60,u_ddr_mc_n_61,u_ddr_mc_n_62,u_ddr_mc_n_63,u_ddr_mc_n_64,u_ddr_mc_n_65,u_ddr_mc_n_66,u_ddr_mc_n_67}),
        .\mcal_BA_dly_reg[0][15]_0 ({mcal_BA[15:14],mcal_BA[12],mcal_BA[10],mcal_BA[8:6],mcal_BA[4],mcal_BA[2],mcal_BA[0]}),
        .\mcal_BA_dly_reg[0][4]_0 (u_ddr_mc_n_59),
        .\mcal_BG_dly_reg[0][4]_0 (u_ddr_mc_n_55),
        .\mcal_BG_dly_reg[0][7]_0 ({mcal_BG[7:6],mcal_BG[4],mcal_BG[2],mcal_BG[0]}),
        .\mcal_CKE_dly_reg[0][7]_0 ({dbg_out_phy[23:22],dbg_out_phy[16]}),
        .\mcal_CS_n_dly_reg[0][6]_0 ({u_ddr_mc_n_68,u_ddr_mc_n_69,u_ddr_mc_n_70,u_ddr_mc_n_71}),
        .\mcal_CS_n_dly_reg[0][7]_0 (mcal_CS_n),
        .\mcal_DMIn_bit_r1_reg[7] ({\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1 [7:6],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1 [4:0]}),
        .mcal_DQIn(mcal_DQIn),
        .\mcal_DQIn_byte_r1_reg[31] (u_ddr_cal_top_n_1780),
        .\mcal_DQIn_byte_r1_reg[48] ({\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [48],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [41:40],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [37],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [34],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [16],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [9:8],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [5],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [2]}),
        .\mcal_ODT_dly_reg[0][7]_0 ({mcal_ODT[7:6],mcal_ODT[4],mcal_ODT[2],mcal_ODT[0]}),
        .\mcal_ODT_dly_reg[0][7]_1 ({u_ddr_mc_n_56,u_ddr_mc_n_57}),
        .\mcal_PAR_dly_reg[0][1]_0 (u_ddr_mc_n_78),
        .\mcal_PAR_dly_reg[0][3]_0 (u_ddr_mc_n_77),
        .\mcal_PAR_dly_reg[0][5]_0 (u_ddr_mc_n_76),
        .\mcal_PAR_dly_reg[0][7]_0 (mcal_PAR),
        .\mcal_PAR_dly_reg[0][7]_1 (u_ddr_mc_n_72),
        .\mcal_clb2phy_fifo_rden_reg[103]_0 (ch0_mcal_clb2phy_fifo_rden),
        .mcal_rd_vref_value(mcal_rd_vref_value),
        .mem_reg_bram_0(u_ddr_cal_top_n_1800),
        .\not_strict_mode.app_rd_data_end_reg ({\u_ddr_ui_rd_data/rd_buf_index_cpy[19].rd_buf_indx_r_reg[19]_188 ,ram_init_addr}),
        .\not_strict_mode.bypass_cpy2 (\u_ddr_ui_rd_data/not_strict_mode.bypass_cpy2 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ({u_ddr_ui_n_23,u_ddr_ui_n_24}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[0].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[0].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] ({u_ddr_ui_n_87,u_ddr_ui_n_88}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] ({u_ddr_ui_n_85,u_ddr_ui_n_86}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ({u_ddr_ui_n_83,u_ddr_ui_n_84}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[10].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[10].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] ({u_ddr_ui_n_93,u_ddr_ui_n_94}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] ({u_ddr_ui_n_91,u_ddr_ui_n_92}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ({u_ddr_ui_n_89,u_ddr_ui_n_90}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[11].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[11].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] ({u_ddr_ui_n_99,u_ddr_ui_n_100}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] ({u_ddr_ui_n_97,u_ddr_ui_n_98}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ({u_ddr_ui_n_95,u_ddr_ui_n_96}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[12].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[12].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] ({u_ddr_ui_n_105,u_ddr_ui_n_106}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] ({u_ddr_ui_n_103,u_ddr_ui_n_104}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ({u_ddr_ui_n_101,u_ddr_ui_n_102}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[13].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[13].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] ({u_ddr_ui_n_111,u_ddr_ui_n_112}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] ({u_ddr_ui_n_109,u_ddr_ui_n_110}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ({u_ddr_ui_n_107,u_ddr_ui_n_108}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[14].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[14].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] ({u_ddr_ui_n_117,u_ddr_ui_n_118}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] ({u_ddr_ui_n_115,u_ddr_ui_n_116}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ({u_ddr_ui_n_113,u_ddr_ui_n_114}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[15].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[15].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ({u_ddr_ui_n_119,u_ddr_ui_n_120}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[16].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[16].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] ({u_ddr_ui_n_123,u_ddr_ui_n_124}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] ({u_ddr_ui_n_121,u_ddr_ui_n_122}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] ({u_ddr_ui_n_129,u_ddr_ui_n_130}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] ({u_ddr_ui_n_127,u_ddr_ui_n_128}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ({u_ddr_ui_n_125,u_ddr_ui_n_126}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[17].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[17].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] ({u_ddr_ui_n_135,u_ddr_ui_n_136}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] ({u_ddr_ui_n_133,u_ddr_ui_n_134}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ({u_ddr_ui_n_131,u_ddr_ui_n_132}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[18].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[18].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] ({u_ddr_ui_n_141,u_ddr_ui_n_142}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] ({u_ddr_ui_n_139,u_ddr_ui_n_140}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ({u_ddr_ui_n_137,u_ddr_ui_n_138}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[19].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[19].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ({u_ddr_ui_n_29,u_ddr_ui_n_30}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[1].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[1].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] ({u_ddr_ui_n_33,u_ddr_ui_n_34}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] ({u_ddr_ui_n_31,u_ddr_ui_n_32}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] ({u_ddr_ui_n_147,u_ddr_ui_n_148}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] ({u_ddr_ui_n_145,u_ddr_ui_n_146}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ({u_ddr_ui_n_143,u_ddr_ui_n_144}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[20].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[20].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] ({u_ddr_ui_n_153,u_ddr_ui_n_154}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] ({u_ddr_ui_n_151,u_ddr_ui_n_152}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ({u_ddr_ui_n_149,u_ddr_ui_n_150}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[21].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[21].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] ({u_ddr_ui_n_159,u_ddr_ui_n_160}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] ({u_ddr_ui_n_157,u_ddr_ui_n_158}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ({u_ddr_ui_n_155,u_ddr_ui_n_156}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[22].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[22].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] ({u_ddr_ui_n_165,u_ddr_ui_n_166}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] ({u_ddr_ui_n_163,u_ddr_ui_n_164}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ({u_ddr_ui_n_161,u_ddr_ui_n_162}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[23].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[23].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] ({u_ddr_ui_n_171,u_ddr_ui_n_172}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] ({u_ddr_ui_n_169,u_ddr_ui_n_170}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ({u_ddr_ui_n_167,u_ddr_ui_n_168}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[24].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[24].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] ({u_ddr_ui_n_177,u_ddr_ui_n_178}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] ({u_ddr_ui_n_175,u_ddr_ui_n_176}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ({u_ddr_ui_n_173,u_ddr_ui_n_174}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[25].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[25].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] ({u_ddr_ui_n_183,u_ddr_ui_n_184}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] ({u_ddr_ui_n_181,u_ddr_ui_n_182}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ({u_ddr_ui_n_179,u_ddr_ui_n_180}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[26].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[26].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] ({u_ddr_ui_n_189,u_ddr_ui_n_190}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] ({u_ddr_ui_n_187,u_ddr_ui_n_188}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ({u_ddr_ui_n_185,u_ddr_ui_n_186}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[27].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[27].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] ({u_ddr_ui_n_195,u_ddr_ui_n_196}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] ({u_ddr_ui_n_193,u_ddr_ui_n_194}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ({u_ddr_ui_n_191,u_ddr_ui_n_192}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[28].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[28].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] ({u_ddr_ui_n_201,u_ddr_ui_n_202}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] ({u_ddr_ui_n_199,u_ddr_ui_n_200}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ({u_ddr_ui_n_197,u_ddr_ui_n_198}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[29].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[29].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] ({u_ddr_ui_n_39,u_ddr_ui_n_40}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] ({u_ddr_ui_n_37,u_ddr_ui_n_38}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ({u_ddr_ui_n_35,u_ddr_ui_n_36}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[2].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[2].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] ({u_ddr_ui_n_207,u_ddr_ui_n_208}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] ({u_ddr_ui_n_205,u_ddr_ui_n_206}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ({u_ddr_ui_n_203,u_ddr_ui_n_204}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[30].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[30].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] ({u_ddr_ui_n_213,u_ddr_ui_n_214}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] ({u_ddr_ui_n_211,u_ddr_ui_n_212}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ({u_ddr_ui_n_209,u_ddr_ui_n_210}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[31].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[31].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] ({u_ddr_ui_n_219,u_ddr_ui_n_220}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] ({u_ddr_ui_n_217,u_ddr_ui_n_218}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ({u_ddr_ui_n_215,u_ddr_ui_n_216}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[32].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[32].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] ({u_ddr_ui_n_225,u_ddr_ui_n_226}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] ({u_ddr_ui_n_223,u_ddr_ui_n_224}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ({u_ddr_ui_n_221,u_ddr_ui_n_222}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[33].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[33].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] ({u_ddr_ui_n_231,u_ddr_ui_n_232}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] ({u_ddr_ui_n_229,u_ddr_ui_n_230}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ({u_ddr_ui_n_227,u_ddr_ui_n_228}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[34].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[34].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] ({u_ddr_ui_n_237,u_ddr_ui_n_238}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] ({u_ddr_ui_n_235,u_ddr_ui_n_236}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ({u_ddr_ui_n_233,u_ddr_ui_n_234}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[35].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[35].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] ({u_ddr_ui_n_243,u_ddr_ui_n_244}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] ({u_ddr_ui_n_241,u_ddr_ui_n_242}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ({u_ddr_ui_n_239,u_ddr_ui_n_240}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[36].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[36].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] ({u_ddr_ui_n_249,u_ddr_ui_n_250}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] ({u_ddr_ui_n_247,u_ddr_ui_n_248}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ({u_ddr_ui_n_245,u_ddr_ui_n_246}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[37].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[37].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] ({u_ddr_ui_n_255,u_ddr_ui_n_256}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] ({u_ddr_ui_n_253,u_ddr_ui_n_254}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ({u_ddr_ui_n_251,u_ddr_ui_n_252}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[38].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[38].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] ({u_ddr_ui_n_261,u_ddr_ui_n_262}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] ({u_ddr_ui_n_259,u_ddr_ui_n_260}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ({u_ddr_ui_n_257,u_ddr_ui_n_258}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[39].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[39].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] ({u_ddr_ui_n_45,u_ddr_ui_n_46}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] ({u_ddr_ui_n_43,u_ddr_ui_n_44}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ({u_ddr_ui_n_41,u_ddr_ui_n_42}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[3].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[3].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] ({u_ddr_ui_n_267,u_ddr_ui_n_268}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] ({u_ddr_ui_n_265,u_ddr_ui_n_266}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ({u_ddr_ui_n_263,u_ddr_ui_n_264}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[40].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[40].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] ({u_ddr_ui_n_273,u_ddr_ui_n_274}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] ({u_ddr_ui_n_271,u_ddr_ui_n_272}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ({u_ddr_ui_n_269,u_ddr_ui_n_270}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[41].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[41].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] ({u_ddr_ui_n_279,u_ddr_ui_n_280}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] ({u_ddr_ui_n_277,u_ddr_ui_n_278}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ({u_ddr_ui_n_275,u_ddr_ui_n_276}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[42].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[42].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] ({u_ddr_ui_n_285,u_ddr_ui_n_286}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] ({u_ddr_ui_n_283,u_ddr_ui_n_284}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ({u_ddr_ui_n_281,u_ddr_ui_n_282}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[43].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[43].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] ({u_ddr_ui_n_291,u_ddr_ui_n_292}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] ({u_ddr_ui_n_289,u_ddr_ui_n_290}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ({u_ddr_ui_n_287,u_ddr_ui_n_288}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[44].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[44].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] ({u_ddr_ui_n_297,u_ddr_ui_n_298}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] ({u_ddr_ui_n_295,u_ddr_ui_n_296}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ({u_ddr_ui_n_293,u_ddr_ui_n_294}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[45].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[45].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] ({u_ddr_ui_n_303,u_ddr_ui_n_304}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] ({u_ddr_ui_n_301,u_ddr_ui_n_302}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ({u_ddr_ui_n_299,u_ddr_ui_n_300}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[46].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[46].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] ({u_ddr_ui_n_309,u_ddr_ui_n_310}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] ({u_ddr_ui_n_307,u_ddr_ui_n_308}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ({u_ddr_ui_n_305,u_ddr_ui_n_306}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[47].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[47].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] ({u_ddr_ui_n_315,u_ddr_ui_n_316}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] ({u_ddr_ui_n_313,u_ddr_ui_n_314}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ({u_ddr_ui_n_311,u_ddr_ui_n_312}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[48].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[48].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] ({u_ddr_ui_n_321,u_ddr_ui_n_322}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] ({u_ddr_ui_n_319,u_ddr_ui_n_320}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ({u_ddr_ui_n_317,u_ddr_ui_n_318}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[49].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[49].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] ({u_ddr_ui_n_51,u_ddr_ui_n_52}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] ({u_ddr_ui_n_49,u_ddr_ui_n_50}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ({u_ddr_ui_n_47,u_ddr_ui_n_48}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[4].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[4].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] ({u_ddr_ui_n_327,u_ddr_ui_n_328}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] ({u_ddr_ui_n_325,u_ddr_ui_n_326}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ({u_ddr_ui_n_323,u_ddr_ui_n_324}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[50].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[50].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] ({u_ddr_ui_n_333,u_ddr_ui_n_334}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] ({u_ddr_ui_n_331,u_ddr_ui_n_332}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ({u_ddr_ui_n_329,u_ddr_ui_n_330}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[51].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[51].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] ({u_ddr_ui_n_339,u_ddr_ui_n_340}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] ({u_ddr_ui_n_337,u_ddr_ui_n_338}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ({u_ddr_ui_n_335,u_ddr_ui_n_336}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[52].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[52].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] ({u_ddr_ui_n_345,u_ddr_ui_n_346}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] ({u_ddr_ui_n_343,u_ddr_ui_n_344}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ({u_ddr_ui_n_341,u_ddr_ui_n_342}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[53].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[53].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] ({u_ddr_ui_n_351,u_ddr_ui_n_352}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] ({u_ddr_ui_n_349,u_ddr_ui_n_350}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ({u_ddr_ui_n_347,u_ddr_ui_n_348}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[54].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[54].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] ({u_ddr_ui_n_357,u_ddr_ui_n_358}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] ({u_ddr_ui_n_355,u_ddr_ui_n_356}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ({u_ddr_ui_n_353,u_ddr_ui_n_354}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[55].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[55].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] ({u_ddr_ui_n_363,u_ddr_ui_n_364}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] ({u_ddr_ui_n_361,u_ddr_ui_n_362}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ({u_ddr_ui_n_359,u_ddr_ui_n_360}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[56].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[56].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] ({u_ddr_ui_n_369,u_ddr_ui_n_370}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] ({u_ddr_ui_n_367,u_ddr_ui_n_368}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ({u_ddr_ui_n_365,u_ddr_ui_n_366}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[57].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[57].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] ({u_ddr_ui_n_375,u_ddr_ui_n_376}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] ({u_ddr_ui_n_373,u_ddr_ui_n_374}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ({u_ddr_ui_n_371,u_ddr_ui_n_372}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[58].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[58].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] ({u_ddr_ui_n_381,u_ddr_ui_n_382}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] ({u_ddr_ui_n_379,u_ddr_ui_n_380}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ({u_ddr_ui_n_377,u_ddr_ui_n_378}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[59].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[59].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] ({u_ddr_ui_n_57,u_ddr_ui_n_58}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] ({u_ddr_ui_n_55,u_ddr_ui_n_56}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ({u_ddr_ui_n_53,u_ddr_ui_n_54}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[5].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[5].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] ({u_ddr_ui_n_387,u_ddr_ui_n_388}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] ({u_ddr_ui_n_385,u_ddr_ui_n_386}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ({u_ddr_ui_n_383,u_ddr_ui_n_384}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[60].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[60].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] ({u_ddr_ui_n_393,u_ddr_ui_n_394}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] ({u_ddr_ui_n_391,u_ddr_ui_n_392}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ({u_ddr_ui_n_389,u_ddr_ui_n_390}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[61].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[61].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] ({u_ddr_ui_n_399,u_ddr_ui_n_400}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] ({u_ddr_ui_n_397,u_ddr_ui_n_398}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ({u_ddr_ui_n_395,u_ddr_ui_n_396}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[62].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[62].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] ({u_ddr_ui_n_405,u_ddr_ui_n_406}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] ({u_ddr_ui_n_403,u_ddr_ui_n_404}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ({u_ddr_ui_n_401,u_ddr_ui_n_402}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[63].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[63].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] ({u_ddr_ui_n_411,u_ddr_ui_n_412}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] ({u_ddr_ui_n_409,u_ddr_ui_n_410}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ({u_ddr_ui_n_407,u_ddr_ui_n_408}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[64].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[64].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] ({u_ddr_ui_n_417,u_ddr_ui_n_418}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] ({u_ddr_ui_n_415,u_ddr_ui_n_416}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ({u_ddr_ui_n_413,u_ddr_ui_n_414}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[65].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[65].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] ({u_ddr_ui_n_423,u_ddr_ui_n_424}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] ({u_ddr_ui_n_421,u_ddr_ui_n_422}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ({u_ddr_ui_n_419,u_ddr_ui_n_420}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[66].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[66].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] ({u_ddr_ui_n_429,u_ddr_ui_n_430}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] ({u_ddr_ui_n_427,u_ddr_ui_n_428}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ({u_ddr_ui_n_425,u_ddr_ui_n_426}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[67].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[67].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] ({u_ddr_ui_n_435,u_ddr_ui_n_436}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] ({u_ddr_ui_n_433,u_ddr_ui_n_434}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ({u_ddr_ui_n_431,u_ddr_ui_n_432}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[68].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[68].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] ({u_ddr_ui_n_441,u_ddr_ui_n_442}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] ({u_ddr_ui_n_439,u_ddr_ui_n_440}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ({u_ddr_ui_n_437,u_ddr_ui_n_438}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[69].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[69].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] ({u_ddr_ui_n_63,u_ddr_ui_n_64}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] ({u_ddr_ui_n_61,u_ddr_ui_n_62}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ({u_ddr_ui_n_59,u_ddr_ui_n_60}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[6].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[6].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] ({u_ddr_ui_n_447,u_ddr_ui_n_448}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] ({u_ddr_ui_n_445,u_ddr_ui_n_446}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ({u_ddr_ui_n_443,u_ddr_ui_n_444}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[70].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[70].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] ({u_ddr_ui_n_453,u_ddr_ui_n_454}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] ({u_ddr_ui_n_451,u_ddr_ui_n_452}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ({u_ddr_ui_n_449,u_ddr_ui_n_450}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[71].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[71].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] ({u_ddr_ui_n_459,u_ddr_ui_n_460}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] ({u_ddr_ui_n_457,u_ddr_ui_n_458}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ({u_ddr_ui_n_455,u_ddr_ui_n_456}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[72].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[72].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] ({u_ddr_ui_n_465,u_ddr_ui_n_466}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] ({u_ddr_ui_n_463,u_ddr_ui_n_464}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ({u_ddr_ui_n_461,u_ddr_ui_n_462}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[73].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[73].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] ({u_ddr_ui_n_471,u_ddr_ui_n_472}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] ({u_ddr_ui_n_469,u_ddr_ui_n_470}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ({u_ddr_ui_n_467,u_ddr_ui_n_468}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[74].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[74].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] ({u_ddr_ui_n_477,u_ddr_ui_n_478}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] ({u_ddr_ui_n_475,u_ddr_ui_n_476}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ({u_ddr_ui_n_473,u_ddr_ui_n_474}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[75].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[75].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] ({u_ddr_ui_n_483,u_ddr_ui_n_484}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] ({u_ddr_ui_n_481,u_ddr_ui_n_482}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ({u_ddr_ui_n_479,u_ddr_ui_n_480}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[76].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[76].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] ({u_ddr_ui_n_489,u_ddr_ui_n_490}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] ({u_ddr_ui_n_487,u_ddr_ui_n_488}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ({u_ddr_ui_n_485,u_ddr_ui_n_486}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[77].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[77].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] ({u_ddr_ui_n_495,u_ddr_ui_n_496}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] ({u_ddr_ui_n_493,u_ddr_ui_n_494}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ({u_ddr_ui_n_491,u_ddr_ui_n_492}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[78].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[78].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] ({u_ddr_ui_n_501,u_ddr_ui_n_502}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] ({u_ddr_ui_n_499,u_ddr_ui_n_500}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ({u_ddr_ui_n_497,u_ddr_ui_n_498}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[79].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[79].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] ({u_ddr_ui_n_69,u_ddr_ui_n_70}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] ({u_ddr_ui_n_67,u_ddr_ui_n_68}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ({u_ddr_ui_n_65,u_ddr_ui_n_66}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[7].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[7].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] ({u_ddr_ui_n_507,u_ddr_ui_n_508}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] ({u_ddr_ui_n_505,u_ddr_ui_n_506}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ({u_ddr_ui_n_503,u_ddr_ui_n_504}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[80].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[80].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] ({u_ddr_ui_n_513,u_ddr_ui_n_514}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] ({u_ddr_ui_n_511,u_ddr_ui_n_512}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ({u_ddr_ui_n_509,u_ddr_ui_n_510}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[81].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[81].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] ({u_ddr_ui_n_519,u_ddr_ui_n_520}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] ({u_ddr_ui_n_517,u_ddr_ui_n_518}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ({u_ddr_ui_n_515,u_ddr_ui_n_516}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[82].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[82].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] ({u_ddr_ui_n_525,u_ddr_ui_n_526}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] ({u_ddr_ui_n_523,u_ddr_ui_n_524}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ({u_ddr_ui_n_521,u_ddr_ui_n_522}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[83].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[83].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] ({u_ddr_ui_n_531,u_ddr_ui_n_532}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] ({u_ddr_ui_n_529,u_ddr_ui_n_530}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ({u_ddr_ui_n_527,u_ddr_ui_n_528}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[84].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[84].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ({u_ddr_ui_n_536,u_ddr_ui_n_537,u_ddr_ui_n_538,u_ddr_ui_n_539,u_ddr_ui_n_540,u_ddr_ui_n_541,u_ddr_ui_n_542,u_ddr_ui_n_543,u_ddr_ui_n_544,u_ddr_ui_n_545,u_ddr_ui_n_546,u_ddr_ui_n_547,u_ddr_ui_n_548,u_ddr_ui_n_549,u_ddr_ui_n_550,u_ddr_ui_n_551,u_ddr_ui_n_552,u_ddr_ui_n_553,u_ddr_ui_n_554,u_ddr_ui_n_555,u_ddr_ui_n_556,u_ddr_ui_n_557,u_ddr_ui_n_558,u_ddr_ui_n_559,u_ddr_ui_n_560,u_ddr_ui_n_561,u_ddr_ui_n_562,u_ddr_ui_n_563,u_ddr_ui_n_564,u_ddr_ui_n_565,u_ddr_ui_n_566,u_ddr_ui_n_567,u_ddr_ui_n_568,u_ddr_ui_n_569,u_ddr_ui_n_570,u_ddr_ui_n_571,u_ddr_ui_n_572,u_ddr_ui_n_573,u_ddr_ui_n_574,u_ddr_ui_n_575,u_ddr_ui_n_576,u_ddr_ui_n_577,u_ddr_ui_n_578,u_ddr_ui_n_579,u_ddr_ui_n_580,u_ddr_ui_n_581,u_ddr_ui_n_582,u_ddr_ui_n_583,u_ddr_ui_n_584,u_ddr_ui_n_585,u_ddr_ui_n_586,u_ddr_ui_n_587,u_ddr_ui_n_588,u_ddr_ui_n_589,u_ddr_ui_n_590,u_ddr_ui_n_591,u_ddr_ui_n_592,u_ddr_ui_n_593,u_ddr_ui_n_594,u_ddr_ui_n_595,u_ddr_ui_n_596,u_ddr_ui_n_597,u_ddr_ui_n_598,u_ddr_ui_n_599,u_ddr_ui_n_600,u_ddr_ui_n_601,u_ddr_ui_n_602,u_ddr_ui_n_603,u_ddr_ui_n_604,u_ddr_ui_n_605,u_ddr_ui_n_606,u_ddr_ui_n_607,u_ddr_ui_n_608,u_ddr_ui_n_609,u_ddr_ui_n_610,u_ddr_ui_n_611,u_ddr_ui_n_612,u_ddr_ui_n_613,u_ddr_ui_n_614,u_ddr_ui_n_615,u_ddr_ui_n_616,u_ddr_ui_n_617,u_ddr_ui_n_618,u_ddr_ui_n_619,u_ddr_ui_n_620,u_ddr_ui_n_621}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ({u_ddr_ui_n_533,u_ddr_ui_n_534}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[85].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[85].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] ({u_ddr_ui_n_75,u_ddr_ui_n_76}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] ({u_ddr_ui_n_73,u_ddr_ui_n_74}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ({u_ddr_ui_n_71,u_ddr_ui_n_72}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[8].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[8].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] ({u_ddr_ui_n_81,u_ddr_ui_n_82}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] ({u_ddr_ui_n_79,u_ddr_ui_n_80}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ({u_ddr_ui_n_77,u_ddr_ui_n_78}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[9].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[9].addr }),
        .\not_strict_mode.status_ram_0.RAM32M0 (u_ddr_cal_top_n_907),
        .\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] ({u_ddr_ui_n_18,u_ddr_ui_n_19,u_ddr_ui_n_20,u_ddr_ui_n_21,u_ddr_ui_n_22}),
        .\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] ({u_ddr_ui_n_2,u_ddr_ui_n_3,u_ddr_ui_n_4,u_ddr_ui_n_5,u_ddr_ui_n_6}),
        .\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] ({u_ddr_ui_n_7,u_ddr_ui_n_8,u_ddr_ui_n_9,u_ddr_ui_n_10,u_ddr_ui_n_11}),
        .\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] ({u_ddr_ui_n_12,u_ddr_ui_n_13,u_ddr_ui_n_14,u_ddr_ui_n_15,u_ddr_ui_n_16}),
        .oe_0_mux_cal(\u_ddr_mc_pi/u_ddr_mc_write/oe_0_mux_cal ),
        .\oe_low_reg[3] (ch0_mcal_clb2phy_t_b_low),
        .\oe_upp_reg[3] (ch0_mcal_clb2phy_t_b_upp),
        .out(out),
        .p_0_in(p_0_in_0),
        .p_52_in(\u_ddr_cal/u_ddr_cal_addr_decode/p_52_in ),
        .per_rd_done(per_rd_done),
        .pllGate(pllGate),
        .pointer_we(\u_ddr_ui_wr_data/pointer_we ),
        .\rams[1].RAM32M0 (ram_init_done_r),
        .rdCAS_reg(u_ddr_cal_top_n_798),
        .\rdDataAddr_reg[4] (rd_data_addr_phy2mc),
        .\rdDataAddr_reg[4]_0 (u_ddr_cal_top_n_2209),
        .\rdDataAddr_reg[4]_1 (u_ddr_cal_top_n_2210),
        .\rdDataAddr_reg[4]_2 (u_ddr_cal_top_n_2211),
        .\rdDataAddr_reg[4]_rep__0 ({u_ddr_cal_top_n_931,u_ddr_cal_top_n_932}),
        .\rdDataAddr_reg[4]_rep__1 ({u_ddr_cal_top_n_941,u_ddr_cal_top_n_942}),
        .\rdData_reg[101]_0 ({u_ddr_cal_top_n_1048,u_ddr_cal_top_n_1049,u_ddr_cal_top_n_1050,u_ddr_cal_top_n_1051,u_ddr_cal_top_n_1052,u_ddr_cal_top_n_1053}),
        .\rdData_reg[107]_0 ({u_ddr_cal_top_n_1056,u_ddr_cal_top_n_1057,u_ddr_cal_top_n_1058,u_ddr_cal_top_n_1059,u_ddr_cal_top_n_1060,u_ddr_cal_top_n_1061}),
        .\rdData_reg[113]_0 ({u_ddr_cal_top_n_1064,u_ddr_cal_top_n_1065,u_ddr_cal_top_n_1066,u_ddr_cal_top_n_1067,u_ddr_cal_top_n_1068,u_ddr_cal_top_n_1069}),
        .\rdData_reg[119]_0 ({u_ddr_cal_top_n_1072,u_ddr_cal_top_n_1073,u_ddr_cal_top_n_1074,u_ddr_cal_top_n_1075,u_ddr_cal_top_n_1076,u_ddr_cal_top_n_1077}),
        .\rdData_reg[11]_0 ({u_ddr_cal_top_n_924,u_ddr_cal_top_n_925,u_ddr_cal_top_n_926,u_ddr_cal_top_n_927,u_ddr_cal_top_n_928,u_ddr_cal_top_n_929}),
        .\rdData_reg[125]_0 ({u_ddr_cal_top_n_1080,u_ddr_cal_top_n_1081,u_ddr_cal_top_n_1082,u_ddr_cal_top_n_1083,u_ddr_cal_top_n_1084,u_ddr_cal_top_n_1085}),
        .\rdData_reg[131]_0 ({u_ddr_cal_top_n_1088,u_ddr_cal_top_n_1089,u_ddr_cal_top_n_1090,u_ddr_cal_top_n_1091,u_ddr_cal_top_n_1092,u_ddr_cal_top_n_1093}),
        .\rdData_reg[137]_0 ({u_ddr_cal_top_n_1096,u_ddr_cal_top_n_1097,u_ddr_cal_top_n_1098,u_ddr_cal_top_n_1099,u_ddr_cal_top_n_1100,u_ddr_cal_top_n_1101}),
        .\rdData_reg[143]_0 ({u_ddr_cal_top_n_1104,u_ddr_cal_top_n_1105,u_ddr_cal_top_n_1106,u_ddr_cal_top_n_1107,u_ddr_cal_top_n_1108,u_ddr_cal_top_n_1109}),
        .\rdData_reg[149]_0 ({u_ddr_cal_top_n_1112,u_ddr_cal_top_n_1113,u_ddr_cal_top_n_1114,u_ddr_cal_top_n_1115,u_ddr_cal_top_n_1116,u_ddr_cal_top_n_1117}),
        .\rdData_reg[155]_0 ({u_ddr_cal_top_n_1120,u_ddr_cal_top_n_1121,u_ddr_cal_top_n_1122,u_ddr_cal_top_n_1123,u_ddr_cal_top_n_1124,u_ddr_cal_top_n_1125}),
        .\rdData_reg[161]_0 ({u_ddr_cal_top_n_1128,u_ddr_cal_top_n_1129,u_ddr_cal_top_n_1130,u_ddr_cal_top_n_1131,u_ddr_cal_top_n_1132,u_ddr_cal_top_n_1133}),
        .\rdData_reg[167]_0 ({u_ddr_cal_top_n_1136,u_ddr_cal_top_n_1137,u_ddr_cal_top_n_1138,u_ddr_cal_top_n_1139,u_ddr_cal_top_n_1140,u_ddr_cal_top_n_1141}),
        .\rdData_reg[173]_0 ({u_ddr_cal_top_n_1144,u_ddr_cal_top_n_1145,u_ddr_cal_top_n_1146,u_ddr_cal_top_n_1147,u_ddr_cal_top_n_1148,u_ddr_cal_top_n_1149}),
        .\rdData_reg[179]_0 ({u_ddr_cal_top_n_1152,u_ddr_cal_top_n_1153,u_ddr_cal_top_n_1154,u_ddr_cal_top_n_1155,u_ddr_cal_top_n_1156,u_ddr_cal_top_n_1157}),
        .\rdData_reg[17]_0 ({u_ddr_cal_top_n_934,u_ddr_cal_top_n_935,u_ddr_cal_top_n_936,u_ddr_cal_top_n_937,u_ddr_cal_top_n_938,u_ddr_cal_top_n_939}),
        .\rdData_reg[185]_0 ({u_ddr_cal_top_n_1160,u_ddr_cal_top_n_1161,u_ddr_cal_top_n_1162,u_ddr_cal_top_n_1163,u_ddr_cal_top_n_1164,u_ddr_cal_top_n_1165}),
        .\rdData_reg[191]_0 ({u_ddr_cal_top_n_1168,u_ddr_cal_top_n_1169,u_ddr_cal_top_n_1170,u_ddr_cal_top_n_1171,u_ddr_cal_top_n_1172,u_ddr_cal_top_n_1173}),
        .\rdData_reg[197]_0 ({u_ddr_cal_top_n_1176,u_ddr_cal_top_n_1177,u_ddr_cal_top_n_1178,u_ddr_cal_top_n_1179,u_ddr_cal_top_n_1180,u_ddr_cal_top_n_1181}),
        .\rdData_reg[203]_0 ({u_ddr_cal_top_n_1184,u_ddr_cal_top_n_1185,u_ddr_cal_top_n_1186,u_ddr_cal_top_n_1187,u_ddr_cal_top_n_1188,u_ddr_cal_top_n_1189}),
        .\rdData_reg[209]_0 ({u_ddr_cal_top_n_1192,u_ddr_cal_top_n_1193,u_ddr_cal_top_n_1194,u_ddr_cal_top_n_1195,u_ddr_cal_top_n_1196,u_ddr_cal_top_n_1197}),
        .\rdData_reg[215]_0 ({u_ddr_cal_top_n_1200,u_ddr_cal_top_n_1201,u_ddr_cal_top_n_1202,u_ddr_cal_top_n_1203,u_ddr_cal_top_n_1204,u_ddr_cal_top_n_1205}),
        .\rdData_reg[221]_0 ({u_ddr_cal_top_n_1208,u_ddr_cal_top_n_1209,u_ddr_cal_top_n_1210,u_ddr_cal_top_n_1211,u_ddr_cal_top_n_1212,u_ddr_cal_top_n_1213}),
        .\rdData_reg[227]_0 ({u_ddr_cal_top_n_1216,u_ddr_cal_top_n_1217,u_ddr_cal_top_n_1218,u_ddr_cal_top_n_1219,u_ddr_cal_top_n_1220,u_ddr_cal_top_n_1221}),
        .\rdData_reg[233]_0 ({u_ddr_cal_top_n_1224,u_ddr_cal_top_n_1225,u_ddr_cal_top_n_1226,u_ddr_cal_top_n_1227,u_ddr_cal_top_n_1228,u_ddr_cal_top_n_1229}),
        .\rdData_reg[239]_0 ({u_ddr_cal_top_n_1232,u_ddr_cal_top_n_1233,u_ddr_cal_top_n_1234,u_ddr_cal_top_n_1235,u_ddr_cal_top_n_1236,u_ddr_cal_top_n_1237}),
        .\rdData_reg[23]_0 ({u_ddr_cal_top_n_944,u_ddr_cal_top_n_945,u_ddr_cal_top_n_946,u_ddr_cal_top_n_947,u_ddr_cal_top_n_948,u_ddr_cal_top_n_949}),
        .\rdData_reg[245]_0 ({u_ddr_cal_top_n_1240,u_ddr_cal_top_n_1241,u_ddr_cal_top_n_1242,u_ddr_cal_top_n_1243,u_ddr_cal_top_n_1244,u_ddr_cal_top_n_1245}),
        .\rdData_reg[251]_0 ({u_ddr_cal_top_n_1248,u_ddr_cal_top_n_1249,u_ddr_cal_top_n_1250,u_ddr_cal_top_n_1251,u_ddr_cal_top_n_1252,u_ddr_cal_top_n_1253}),
        .\rdData_reg[257]_0 ({u_ddr_cal_top_n_1256,u_ddr_cal_top_n_1257,u_ddr_cal_top_n_1258,u_ddr_cal_top_n_1259,u_ddr_cal_top_n_1260,u_ddr_cal_top_n_1261}),
        .\rdData_reg[263]_0 ({u_ddr_cal_top_n_1264,u_ddr_cal_top_n_1265,u_ddr_cal_top_n_1266,u_ddr_cal_top_n_1267,u_ddr_cal_top_n_1268,u_ddr_cal_top_n_1269}),
        .\rdData_reg[269]_0 ({u_ddr_cal_top_n_1272,u_ddr_cal_top_n_1273,u_ddr_cal_top_n_1274,u_ddr_cal_top_n_1275,u_ddr_cal_top_n_1276,u_ddr_cal_top_n_1277}),
        .\rdData_reg[275]_0 ({u_ddr_cal_top_n_1280,u_ddr_cal_top_n_1281,u_ddr_cal_top_n_1282,u_ddr_cal_top_n_1283,u_ddr_cal_top_n_1284,u_ddr_cal_top_n_1285}),
        .\rdData_reg[281]_0 ({u_ddr_cal_top_n_1288,u_ddr_cal_top_n_1289,u_ddr_cal_top_n_1290,u_ddr_cal_top_n_1291,u_ddr_cal_top_n_1292,u_ddr_cal_top_n_1293}),
        .\rdData_reg[287]_0 ({u_ddr_cal_top_n_1296,u_ddr_cal_top_n_1297,u_ddr_cal_top_n_1298,u_ddr_cal_top_n_1299,u_ddr_cal_top_n_1300,u_ddr_cal_top_n_1301}),
        .\rdData_reg[293]_0 ({u_ddr_cal_top_n_1304,u_ddr_cal_top_n_1305,u_ddr_cal_top_n_1306,u_ddr_cal_top_n_1307,u_ddr_cal_top_n_1308,u_ddr_cal_top_n_1309}),
        .\rdData_reg[299]_0 ({u_ddr_cal_top_n_1312,u_ddr_cal_top_n_1313,u_ddr_cal_top_n_1314,u_ddr_cal_top_n_1315,u_ddr_cal_top_n_1316,u_ddr_cal_top_n_1317}),
        .\rdData_reg[29]_0 ({u_ddr_cal_top_n_952,u_ddr_cal_top_n_953,u_ddr_cal_top_n_954,u_ddr_cal_top_n_955,u_ddr_cal_top_n_956,u_ddr_cal_top_n_957}),
        .\rdData_reg[305]_0 ({u_ddr_cal_top_n_1320,u_ddr_cal_top_n_1321,u_ddr_cal_top_n_1322,u_ddr_cal_top_n_1323,u_ddr_cal_top_n_1324,u_ddr_cal_top_n_1325}),
        .\rdData_reg[311]_0 ({u_ddr_cal_top_n_1328,u_ddr_cal_top_n_1329,u_ddr_cal_top_n_1330,u_ddr_cal_top_n_1331,u_ddr_cal_top_n_1332,u_ddr_cal_top_n_1333}),
        .\rdData_reg[317]_0 ({u_ddr_cal_top_n_1336,u_ddr_cal_top_n_1337,u_ddr_cal_top_n_1338,u_ddr_cal_top_n_1339,u_ddr_cal_top_n_1340,u_ddr_cal_top_n_1341}),
        .\rdData_reg[323]_0 ({u_ddr_cal_top_n_1344,u_ddr_cal_top_n_1345,u_ddr_cal_top_n_1346,u_ddr_cal_top_n_1347,u_ddr_cal_top_n_1348,u_ddr_cal_top_n_1349}),
        .\rdData_reg[329]_0 ({u_ddr_cal_top_n_1352,u_ddr_cal_top_n_1353,u_ddr_cal_top_n_1354,u_ddr_cal_top_n_1355,u_ddr_cal_top_n_1356,u_ddr_cal_top_n_1357}),
        .\rdData_reg[335]_0 ({u_ddr_cal_top_n_1360,u_ddr_cal_top_n_1361,u_ddr_cal_top_n_1362,u_ddr_cal_top_n_1363,u_ddr_cal_top_n_1364,u_ddr_cal_top_n_1365}),
        .\rdData_reg[341]_0 ({u_ddr_cal_top_n_1368,u_ddr_cal_top_n_1369,u_ddr_cal_top_n_1370,u_ddr_cal_top_n_1371,u_ddr_cal_top_n_1372,u_ddr_cal_top_n_1373}),
        .\rdData_reg[347]_0 ({u_ddr_cal_top_n_1376,u_ddr_cal_top_n_1377,u_ddr_cal_top_n_1378,u_ddr_cal_top_n_1379,u_ddr_cal_top_n_1380,u_ddr_cal_top_n_1381}),
        .\rdData_reg[353]_0 ({u_ddr_cal_top_n_1384,u_ddr_cal_top_n_1385,u_ddr_cal_top_n_1386,u_ddr_cal_top_n_1387,u_ddr_cal_top_n_1388,u_ddr_cal_top_n_1389}),
        .\rdData_reg[359]_0 ({u_ddr_cal_top_n_1392,u_ddr_cal_top_n_1393,u_ddr_cal_top_n_1394,u_ddr_cal_top_n_1395,u_ddr_cal_top_n_1396,u_ddr_cal_top_n_1397}),
        .\rdData_reg[35]_0 ({u_ddr_cal_top_n_960,u_ddr_cal_top_n_961,u_ddr_cal_top_n_962,u_ddr_cal_top_n_963,u_ddr_cal_top_n_964,u_ddr_cal_top_n_965}),
        .\rdData_reg[365]_0 ({u_ddr_cal_top_n_1400,u_ddr_cal_top_n_1401,u_ddr_cal_top_n_1402,u_ddr_cal_top_n_1403,u_ddr_cal_top_n_1404,u_ddr_cal_top_n_1405}),
        .\rdData_reg[371]_0 ({u_ddr_cal_top_n_1408,u_ddr_cal_top_n_1409,u_ddr_cal_top_n_1410,u_ddr_cal_top_n_1411,u_ddr_cal_top_n_1412,u_ddr_cal_top_n_1413}),
        .\rdData_reg[377]_0 ({u_ddr_cal_top_n_1416,u_ddr_cal_top_n_1417,u_ddr_cal_top_n_1418,u_ddr_cal_top_n_1419,u_ddr_cal_top_n_1420,u_ddr_cal_top_n_1421}),
        .\rdData_reg[383]_0 ({u_ddr_cal_top_n_1424,u_ddr_cal_top_n_1425,u_ddr_cal_top_n_1426,u_ddr_cal_top_n_1427,u_ddr_cal_top_n_1428,u_ddr_cal_top_n_1429}),
        .\rdData_reg[389]_0 ({u_ddr_cal_top_n_1432,u_ddr_cal_top_n_1433,u_ddr_cal_top_n_1434,u_ddr_cal_top_n_1435,u_ddr_cal_top_n_1436,u_ddr_cal_top_n_1437}),
        .\rdData_reg[395]_0 ({u_ddr_cal_top_n_1440,u_ddr_cal_top_n_1441,u_ddr_cal_top_n_1442,u_ddr_cal_top_n_1443,u_ddr_cal_top_n_1444,u_ddr_cal_top_n_1445}),
        .\rdData_reg[401]_0 ({u_ddr_cal_top_n_1448,u_ddr_cal_top_n_1449,u_ddr_cal_top_n_1450,u_ddr_cal_top_n_1451,u_ddr_cal_top_n_1452,u_ddr_cal_top_n_1453}),
        .\rdData_reg[407]_0 ({u_ddr_cal_top_n_1456,u_ddr_cal_top_n_1457,u_ddr_cal_top_n_1458,u_ddr_cal_top_n_1459,u_ddr_cal_top_n_1460,u_ddr_cal_top_n_1461}),
        .\rdData_reg[413]_0 ({u_ddr_cal_top_n_1464,u_ddr_cal_top_n_1465,u_ddr_cal_top_n_1466,u_ddr_cal_top_n_1467,u_ddr_cal_top_n_1468,u_ddr_cal_top_n_1469}),
        .\rdData_reg[419]_0 ({u_ddr_cal_top_n_1472,u_ddr_cal_top_n_1473,u_ddr_cal_top_n_1474,u_ddr_cal_top_n_1475,u_ddr_cal_top_n_1476,u_ddr_cal_top_n_1477}),
        .\rdData_reg[41]_0 ({u_ddr_cal_top_n_968,u_ddr_cal_top_n_969,u_ddr_cal_top_n_970,u_ddr_cal_top_n_971,u_ddr_cal_top_n_972,u_ddr_cal_top_n_973}),
        .\rdData_reg[425]_0 ({u_ddr_cal_top_n_1480,u_ddr_cal_top_n_1481,u_ddr_cal_top_n_1482,u_ddr_cal_top_n_1483,u_ddr_cal_top_n_1484,u_ddr_cal_top_n_1485}),
        .\rdData_reg[431]_0 ({u_ddr_cal_top_n_1488,u_ddr_cal_top_n_1489,u_ddr_cal_top_n_1490,u_ddr_cal_top_n_1491,u_ddr_cal_top_n_1492,u_ddr_cal_top_n_1493}),
        .\rdData_reg[437]_0 ({u_ddr_cal_top_n_1496,u_ddr_cal_top_n_1497,u_ddr_cal_top_n_1498,u_ddr_cal_top_n_1499,u_ddr_cal_top_n_1500,u_ddr_cal_top_n_1501}),
        .\rdData_reg[443]_0 ({u_ddr_cal_top_n_1504,u_ddr_cal_top_n_1505,u_ddr_cal_top_n_1506,u_ddr_cal_top_n_1507,u_ddr_cal_top_n_1508,u_ddr_cal_top_n_1509}),
        .\rdData_reg[449]_0 ({u_ddr_cal_top_n_1512,u_ddr_cal_top_n_1513,u_ddr_cal_top_n_1514,u_ddr_cal_top_n_1515,u_ddr_cal_top_n_1516,u_ddr_cal_top_n_1517}),
        .\rdData_reg[455]_0 ({u_ddr_cal_top_n_1520,u_ddr_cal_top_n_1521,u_ddr_cal_top_n_1522,u_ddr_cal_top_n_1523,u_ddr_cal_top_n_1524,u_ddr_cal_top_n_1525}),
        .\rdData_reg[461]_0 ({u_ddr_cal_top_n_1528,u_ddr_cal_top_n_1529,u_ddr_cal_top_n_1530,u_ddr_cal_top_n_1531,u_ddr_cal_top_n_1532,u_ddr_cal_top_n_1533}),
        .\rdData_reg[467]_0 ({u_ddr_cal_top_n_1536,u_ddr_cal_top_n_1537,u_ddr_cal_top_n_1538,u_ddr_cal_top_n_1539,u_ddr_cal_top_n_1540,u_ddr_cal_top_n_1541}),
        .\rdData_reg[473]_0 ({u_ddr_cal_top_n_1544,u_ddr_cal_top_n_1545,u_ddr_cal_top_n_1546,u_ddr_cal_top_n_1547,u_ddr_cal_top_n_1548,u_ddr_cal_top_n_1549}),
        .\rdData_reg[479]_0 ({u_ddr_cal_top_n_1552,u_ddr_cal_top_n_1553,u_ddr_cal_top_n_1554,u_ddr_cal_top_n_1555,u_ddr_cal_top_n_1556,u_ddr_cal_top_n_1557}),
        .\rdData_reg[47]_0 ({u_ddr_cal_top_n_976,u_ddr_cal_top_n_977,u_ddr_cal_top_n_978,u_ddr_cal_top_n_979,u_ddr_cal_top_n_980,u_ddr_cal_top_n_981}),
        .\rdData_reg[485]_0 ({u_ddr_cal_top_n_1560,u_ddr_cal_top_n_1561,u_ddr_cal_top_n_1562,u_ddr_cal_top_n_1563,u_ddr_cal_top_n_1564,u_ddr_cal_top_n_1565}),
        .\rdData_reg[491]_0 ({u_ddr_cal_top_n_1568,u_ddr_cal_top_n_1569,u_ddr_cal_top_n_1570,u_ddr_cal_top_n_1571,u_ddr_cal_top_n_1572,u_ddr_cal_top_n_1573}),
        .\rdData_reg[497]_0 ({u_ddr_cal_top_n_1576,u_ddr_cal_top_n_1577,u_ddr_cal_top_n_1578,u_ddr_cal_top_n_1579,u_ddr_cal_top_n_1580,u_ddr_cal_top_n_1581}),
        .\rdData_reg[503]_0 ({u_ddr_cal_top_n_1584,u_ddr_cal_top_n_1585,u_ddr_cal_top_n_1586,u_ddr_cal_top_n_1587,u_ddr_cal_top_n_1588,u_ddr_cal_top_n_1589}),
        .\rdData_reg[509]_0 ({u_ddr_cal_top_n_1592,u_ddr_cal_top_n_1593,u_ddr_cal_top_n_1594,u_ddr_cal_top_n_1595,u_ddr_cal_top_n_1596,u_ddr_cal_top_n_1597}),
        .\rdData_reg[511]_0 ({u_ddr_cal_top_n_1600,u_ddr_cal_top_n_1601}),
        .\rdData_reg[53]_0 ({u_ddr_cal_top_n_984,u_ddr_cal_top_n_985,u_ddr_cal_top_n_986,u_ddr_cal_top_n_987,u_ddr_cal_top_n_988,u_ddr_cal_top_n_989}),
        .\rdData_reg[59]_0 ({u_ddr_cal_top_n_992,u_ddr_cal_top_n_993,u_ddr_cal_top_n_994,u_ddr_cal_top_n_995,u_ddr_cal_top_n_996,u_ddr_cal_top_n_997}),
        .\rdData_reg[5]_0 ({u_ddr_cal_top_n_914,u_ddr_cal_top_n_915,u_ddr_cal_top_n_916,u_ddr_cal_top_n_917,u_ddr_cal_top_n_918,u_ddr_cal_top_n_919}),
        .\rdData_reg[65]_0 ({u_ddr_cal_top_n_1000,u_ddr_cal_top_n_1001,u_ddr_cal_top_n_1002,u_ddr_cal_top_n_1003,u_ddr_cal_top_n_1004,u_ddr_cal_top_n_1005}),
        .\rdData_reg[71]_0 ({u_ddr_cal_top_n_1008,u_ddr_cal_top_n_1009,u_ddr_cal_top_n_1010,u_ddr_cal_top_n_1011,u_ddr_cal_top_n_1012,u_ddr_cal_top_n_1013}),
        .\rdData_reg[77]_0 ({u_ddr_cal_top_n_1016,u_ddr_cal_top_n_1017,u_ddr_cal_top_n_1018,u_ddr_cal_top_n_1019,u_ddr_cal_top_n_1020,u_ddr_cal_top_n_1021}),
        .\rdData_reg[83]_0 ({u_ddr_cal_top_n_1024,u_ddr_cal_top_n_1025,u_ddr_cal_top_n_1026,u_ddr_cal_top_n_1027,u_ddr_cal_top_n_1028,u_ddr_cal_top_n_1029}),
        .\rdData_reg[89]_0 ({u_ddr_cal_top_n_1032,u_ddr_cal_top_n_1033,u_ddr_cal_top_n_1034,u_ddr_cal_top_n_1035,u_ddr_cal_top_n_1036,u_ddr_cal_top_n_1037}),
        .\rdData_reg[95]_0 ({u_ddr_cal_top_n_1040,u_ddr_cal_top_n_1041,u_ddr_cal_top_n_1042,u_ddr_cal_top_n_1043,u_ddr_cal_top_n_1044,u_ddr_cal_top_n_1045}),
        .rd_data_en_phy2mc(rd_data_en_phy2mc),
        .rd_vref_value0_out({\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [55],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [48],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [41],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [34],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [27],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [20],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [13],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [6]}),
        .\rd_vref_value_reg[42] (u_ddr_cal_top_n_1906),
        .\rd_vref_value_reg[43] (u_ddr_cal_top_n_1963),
        .\rd_vref_value_reg[44] (u_ddr_cal_top_n_1964),
        .\rd_vref_value_reg[45] (u_ddr_cal_top_n_1965),
        .\rd_vref_value_reg[46] (u_ddr_cal_top_n_1878),
        .\rd_vref_value_reg[48] (u_ddr_cal_top_n_1966),
        .\read_lat_fifo_in_reg[6] ({winInjTxn,winRmw,winBuf}),
        .rst_r1_reg_0(u_ddr_cal_top_n_756),
        .rst_r1_reg_1(u_ddr_cal_top_n_1899),
        .sample_gts(sample_gts),
        .sl_oport_o(sl_oport_o),
        .stop_gate_tracking_ack_reg(u_ddr_cal_top_n_796),
        .stop_gate_tracking_ack_reg_0(u_io_addr_sync_n_110),
        .\traffic_instr_nxt_instr_r1_reg[5] (u_io_addr_sync_n_46),
        .ub_calDone(\u_ddr_cal/ub_calDone ),
        .ub_initDone_reg(ub_initDone),
        .ub_ready_reg(u_io_addr_sync_n_52),
        .underfill_done_nxt(underfill_done_nxt),
        .\uppCL0_reg[47] ({\u_ddr_cal/u_ddr_cal_addr_decode/uppCL00 [47:42],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL00 [37:36],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL00 [33:32]}),
        .\uppCL1_reg[47] ({\u_ddr_cal/u_ddr_cal_addr_decode/uppCL10 [47:42],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL10 [37:36],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL10 [33:32]}),
        .\uppCL2_reg[47] ({\u_ddr_cal/u_ddr_cal_addr_decode/uppCL20 [47:42],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL20 [37:36],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL20 [33:32]}),
        .\uppCL3_reg[42] ({u_io_addr_sync_n_57,u_io_addr_sync_n_58,u_io_addr_sync_n_59,u_io_addr_sync_n_60,u_io_addr_sync_n_61,u_io_addr_sync_n_62,u_io_addr_sync_n_63,u_io_addr_sync_n_64}),
        .\uppCL3_reg[47] ({\u_ddr_cal/u_ddr_cal_addr_decode/uppCL30 [47:42],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL30 [37:36],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL30 [33:32]}),
        .winAct(winAct),
        .\wrQ_reg[0][0] (wrDataEn),
        .\wrQ_reg[0][5]_rep (u_ddr_mc_n_99),
        .\wrQ_reg[0][5]_rep__0 (u_ddr_mc_n_100),
        .\wrQ_reg[0][5]_rep__1 (u_ddr_mc_n_101),
        .\wrQ_reg[0][6]_rep (u_ddr_mc_n_102),
        .\wrQ_reg[0][6]_rep__0 (u_ddr_mc_n_103),
        .\wrQ_reg[0][6]_rep__1 (u_ddr_mc_n_104),
        .\wrQ_reg[0][7]_rep (u_ddr_mc_n_96),
        .\wrQ_reg[0][7]_rep__0 (u_ddr_mc_n_97),
        .\wrQ_reg[0][7]_rep__1 (u_ddr_mc_n_98),
        .\wrQ_reg[0][8] (\u_ddr_mc_pi/u_ddr_mc_write/wrQ_nxt[0]_12 ),
        .\wrQ_reg[0][8]_rep (u_ddr_mc_n_105),
        .\wrQ_reg[0][8]_rep__0 ({u_ddr_cal_top_n_2119,u_ddr_cal_top_n_2120,u_ddr_cal_top_n_2121,u_ddr_cal_top_n_2122}),
        .\wrQ_reg[0][8]_rep__0_0 (u_ddr_mc_n_106),
        .\wrQ_reg[0][8]_rep__1 ({u_ddr_cal_top_n_2123,u_ddr_cal_top_n_2124,u_ddr_cal_top_n_2125,u_ddr_cal_top_n_2126}),
        .\wrQ_reg[0][8]_rep__1_0 (u_ddr_mc_n_107),
        .\wrQ_reg[1][8] (\u_ddr_mc_pi/u_ddr_mc_write/wrQ_reg[1]_11 ),
        .\wrQ_reg[1][8]_0 ({\u_ddr_mc_pi/u_ddr_mc_write/wrQ_nxt[1]_13 [8:5],\u_ddr_mc_pi/u_ddr_mc_write/wrQ_nxt[1]_13 [2]}),
        .xsdb_wr_en_reg(u_io_addr_sync_n_117));
  ddr4_0_ddr4_v2_2_17_mc u_ddr_mc
       (.SR(SR),
        .accept_ns(accept_ns),
        .accept_reg(u_ddr_mc_n_1),
        .accept_reg_0(u_ddr_mc_n_2),
        .accept_reg_1(u_ddr_mc_n_3),
        .accept_reg_2(grAccept_ns),
        .accept_reg_3(u_ddr_ui_n_1084),
        .bank(bank),
        .\buf_fifo_reg[0][0] (u_ddr_mc_n_115),
        .\buf_fifo_reg[0][0]_0 (u_ddr_mc_n_120),
        .\buf_fifo_reg[0][1] (u_ddr_mc_n_116),
        .\buf_fifo_reg[0][1]_0 (u_ddr_mc_n_121),
        .\buf_fifo_reg[0][2] (u_ddr_mc_n_122),
        .\buf_fifo_reg[0][3] (u_ddr_mc_n_118),
        .\buf_fifo_reg[0][4] (u_ddr_mc_n_114),
        .\buf_fifo_reg[0][4]_0 (u_ddr_mc_n_124),
        .\buf_fifo_reg[1][0] (u_ddr_ui_n_1059),
        .\buf_fifo_reg[1][0]_0 (u_ddr_ui_n_1070),
        .\buf_fifo_reg[1][0]_1 (u_ddr_ui_n_1075),
        .\buf_fifo_reg[1][1] (u_ddr_ui_n_1066),
        .\buf_fifo_reg[1][1]_0 (u_ddr_ui_n_1071),
        .\buf_fifo_reg[1][1]_1 (u_ddr_ui_n_1076),
        .\buf_fifo_reg[1][2] (u_ddr_ui_n_1067),
        .\buf_fifo_reg[1][2]_0 (u_ddr_ui_n_1072),
        .\buf_fifo_reg[1][2]_1 (u_ddr_ui_n_1077),
        .\buf_fifo_reg[1][3] (u_ddr_ui_n_1068),
        .\buf_fifo_reg[1][3]_0 (u_ddr_ui_n_1073),
        .\buf_fifo_reg[1][3]_1 (u_ddr_ui_n_1078),
        .\buf_fifo_reg[1][4] (u_ddr_ui_n_1069),
        .\buf_fifo_reg[1][4]_0 (u_ddr_ui_n_1074),
        .\buf_fifo_reg[1][4]_1 (u_ddr_ui_n_1079),
        .\buf_fifo_reg[2][0] (u_ddr_mc_n_110),
        .\buf_fifo_reg[2][1] (u_ddr_mc_n_111),
        .\buf_fifo_reg[2][2] (u_ddr_mc_n_112),
        .\buf_fifo_reg[2][2]_0 (u_ddr_mc_n_117),
        .\buf_fifo_reg[2][3] (u_ddr_mc_n_113),
        .\buf_fifo_reg[2][3]_0 (u_ddr_mc_n_123),
        .\buf_fifo_reg[2][4] (u_ddr_mc_n_119),
        .calDone(calDone),
        .calDone_reg(u_ddr_mc_n_72),
        .calDone_reg_0(u_ddr_mc_n_76),
        .calDone_reg_1(u_ddr_mc_n_77),
        .calDone_reg_2(u_ddr_mc_n_78),
        .calDone_reg_3({\u_ddr_mc_pi/u_ddr_mc_write/wrQ_nxt[1]_13 [8:5],\u_ddr_mc_pi/u_ddr_mc_write/wrQ_nxt[1]_13 [2]}),
        .calWrCAS(calWrCAS),
        .cal_BA(cal_BA),
        .cal_CS_n({cal_CS_n[6:5],cal_CS_n[2:1]}),
        .cmd(cmd),
        .cmdBuf(cmdBuf),
        .cmdInjTxn_reg({winInjTxn,winRmw,winBuf}),
        .col(col),
        .dBufAdr(dBufAdr),
        .group(group),
        .gt_data_ready_flag(\u_ddr_cal/u_ddr_cal_addr_decode/gt_data_ready_flag ),
        .gt_data_ready_flag_nxt(\u_ddr_cal/u_ddr_cal_addr_decode/gt_data_ready_flag_nxt ),
        .gt_data_ready_flag_reg(u_ddr_cal_top_n_758),
        .mcCasSlot2(mcCasSlot2),
        .mcRdCAS(mcRdCAS),
        .mcWrCAS(mcWrCAS),
        .mc_ADR({mc_ADR[131],mc_ADR[123],mc_ADR[115],mc_ADR[111],mc_ADR[109],mc_ADR[107],mc_ADR[99],mc_ADR[91],mc_ADR[87],mc_ADR[85],mc_ADR[83],mc_ADR[81],mc_ADR[77],mc_ADR[75],mc_ADR[73],mc_ADR[69],mc_ADR[67],mc_ADR[65],mc_ADR[61],mc_ADR[59],mc_ADR[57],mc_ADR[53],mc_ADR[51],mc_ADR[49],mc_ADR[45],mc_ADR[43],mc_ADR[41],mc_ADR[37],mc_ADR[35],mc_ADR[33],mc_ADR[29],mc_ADR[27],mc_ADR[25],mc_ADR[19],mc_ADR[11],mc_ADR[5],mc_ADR[3],mc_ADR[1]}),
        .mc_BA({mc_BA[15],mc_BA[13],mc_BA[11],mc_BA[9],mc_BA[7],mc_BA[5],mc_BA[1]}),
        .mc_BG({mc_BG[7],mc_BG[5],mc_BG[1]}),
        .mc_CKE({mc_CKE[7],mc_CKE[5]}),
        .mc_CS_n(mc_CS_n),
        .mc_ODT({mc_ODT[7],mc_ODT[3]}),
        .\mcal_ADR_dly_reg[0][126] ({cal_ADR[126:125],cal_ADR[122:121],cal_ADR[118:117],cal_ADR[114:113]}),
        .\mcal_ODT_dly_reg[0][7] (u_ddr_cal_top_n_798),
        .oe_0_mux_cal(\u_ddr_mc_pi/u_ddr_mc_write/oe_0_mux_cal ),
        .p_0_in(p_0_in_0),
        .per_rd_done(per_rd_done),
        .periodic_config_gap_enable_reg(c0_init_calib_complete),
        .periodic_read_or_ref_block_reg(u_ddr_mc_n_0),
        .row_mc_phy(row_mc_phy),
        .\txn_fifo_wptr_reg[0] (u_ddr_mc_n_109),
        .um_sreIss_reg({u_ddr_mc_n_73,u_ddr_mc_n_74,u_ddr_mc_n_75}),
        .um_sreIss_reg_0(\SYNC[19].sync_reg_reg[1] ),
        .underfill_done_nxt(underfill_done_nxt),
        .underfill_done_reg(u_ddr_cal_top_n_2209),
        .underfill_done_reg_0(u_ddr_cal_top_n_2210),
        .underfill_done_reg_1(u_ddr_cal_top_n_2211),
        .useAdr(useAdr),
        .winAct(winAct),
        .winAct_reg(u_ddr_mc_n_55),
        .\winPort_reg[0] (u_ddr_mc_n_59),
        .winRead_reg({u_ddr_mc_n_56,u_ddr_mc_n_57}),
        .winRead_reg_0({u_ddr_mc_n_60,u_ddr_mc_n_61,u_ddr_mc_n_62,u_ddr_mc_n_63,u_ddr_mc_n_64,u_ddr_mc_n_65,u_ddr_mc_n_66,u_ddr_mc_n_67}),
        .winRead_reg_1({u_ddr_mc_n_68,u_ddr_mc_n_69,u_ddr_mc_n_70,u_ddr_mc_n_71}),
        .wrCAS_reg(\u_ddr_mc_pi/u_ddr_mc_write/wrQ_nxt[0]_12 ),
        .wrCAS_reg_0(u_ddr_mc_n_96),
        .wrCAS_reg_1(u_ddr_mc_n_97),
        .wrCAS_reg_10(u_ddr_mc_n_106),
        .wrCAS_reg_11(u_ddr_mc_n_107),
        .wrCAS_reg_2(u_ddr_mc_n_98),
        .wrCAS_reg_3(u_ddr_mc_n_99),
        .wrCAS_reg_4(u_ddr_mc_n_100),
        .wrCAS_reg_5(u_ddr_mc_n_101),
        .wrCAS_reg_6(u_ddr_mc_n_102),
        .wrCAS_reg_7(u_ddr_mc_n_103),
        .wrCAS_reg_8(u_ddr_mc_n_104),
        .wrCAS_reg_9(u_ddr_mc_n_105),
        .\wrQ_reg[0][8]_rep__1 (\u_ddr_mc_pi/u_ddr_mc_write/wrQ_reg[1]_11 ));
  ddr4_0_ddr4_v2_2_17_ui u_ddr_ui
       (.ADDRA({u_ddr_cal_top_n_2115,u_ddr_cal_top_n_2116,u_ddr_cal_top_n_2117,u_ddr_cal_top_n_2118}),
        .ADDRC(wrDataAddr),
        .ADDRD({u_ddr_cal_top_n_921,u_ddr_cal_top_n_922,rd_data_addr_phy2mc[2:0]}),
        .D({rd_data_phy2mc_xif[511],rd_data_phy2mc_xif[503],rd_data_phy2mc_xif[495],rd_data_phy2mc_xif[487],rd_data_phy2mc_xif[479],rd_data_phy2mc_xif[471],rd_data_phy2mc_xif[463],rd_data_phy2mc_xif[455],rd_data_phy2mc_xif[510],rd_data_phy2mc_xif[502],rd_data_phy2mc_xif[494],rd_data_phy2mc_xif[486],rd_data_phy2mc_xif[478],rd_data_phy2mc_xif[470],rd_data_phy2mc_xif[462],rd_data_phy2mc_xif[454],rd_data_phy2mc_xif[509],rd_data_phy2mc_xif[501],rd_data_phy2mc_xif[493],rd_data_phy2mc_xif[485],rd_data_phy2mc_xif[477],rd_data_phy2mc_xif[469],rd_data_phy2mc_xif[461],rd_data_phy2mc_xif[453],rd_data_phy2mc_xif[508],rd_data_phy2mc_xif[500],rd_data_phy2mc_xif[492],rd_data_phy2mc_xif[484],rd_data_phy2mc_xif[476],rd_data_phy2mc_xif[468],rd_data_phy2mc_xif[460],rd_data_phy2mc_xif[452],rd_data_phy2mc_xif[507],rd_data_phy2mc_xif[499],rd_data_phy2mc_xif[491],rd_data_phy2mc_xif[483],rd_data_phy2mc_xif[475],rd_data_phy2mc_xif[467],rd_data_phy2mc_xif[459],rd_data_phy2mc_xif[451],rd_data_phy2mc_xif[506],rd_data_phy2mc_xif[498],rd_data_phy2mc_xif[490],rd_data_phy2mc_xif[482],rd_data_phy2mc_xif[474],rd_data_phy2mc_xif[466],rd_data_phy2mc_xif[458],rd_data_phy2mc_xif[450],rd_data_phy2mc_xif[505],rd_data_phy2mc_xif[497],rd_data_phy2mc_xif[489],rd_data_phy2mc_xif[481],rd_data_phy2mc_xif[473],rd_data_phy2mc_xif[465],rd_data_phy2mc_xif[457],rd_data_phy2mc_xif[449],rd_data_phy2mc_xif[504],rd_data_phy2mc_xif[496],rd_data_phy2mc_xif[488],rd_data_phy2mc_xif[480],rd_data_phy2mc_xif[472],rd_data_phy2mc_xif[464],rd_data_phy2mc_xif[456],rd_data_phy2mc_xif[448:447],rd_data_phy2mc_xif[439],rd_data_phy2mc_xif[431],rd_data_phy2mc_xif[423],rd_data_phy2mc_xif[415],rd_data_phy2mc_xif[407],rd_data_phy2mc_xif[399],rd_data_phy2mc_xif[391],rd_data_phy2mc_xif[446],rd_data_phy2mc_xif[438],rd_data_phy2mc_xif[430],rd_data_phy2mc_xif[422],rd_data_phy2mc_xif[414],rd_data_phy2mc_xif[406],rd_data_phy2mc_xif[398],rd_data_phy2mc_xif[390],rd_data_phy2mc_xif[445],rd_data_phy2mc_xif[437],rd_data_phy2mc_xif[429],rd_data_phy2mc_xif[421],rd_data_phy2mc_xif[413],rd_data_phy2mc_xif[405],rd_data_phy2mc_xif[397],rd_data_phy2mc_xif[389],rd_data_phy2mc_xif[444],rd_data_phy2mc_xif[436],rd_data_phy2mc_xif[428],rd_data_phy2mc_xif[420],rd_data_phy2mc_xif[412],rd_data_phy2mc_xif[404],rd_data_phy2mc_xif[396],rd_data_phy2mc_xif[388],rd_data_phy2mc_xif[443],rd_data_phy2mc_xif[435],rd_data_phy2mc_xif[427],rd_data_phy2mc_xif[419],rd_data_phy2mc_xif[411],rd_data_phy2mc_xif[403],rd_data_phy2mc_xif[395],rd_data_phy2mc_xif[387],rd_data_phy2mc_xif[442],rd_data_phy2mc_xif[434],rd_data_phy2mc_xif[426],rd_data_phy2mc_xif[418],rd_data_phy2mc_xif[410],rd_data_phy2mc_xif[402],rd_data_phy2mc_xif[394],rd_data_phy2mc_xif[386],rd_data_phy2mc_xif[441],rd_data_phy2mc_xif[433],rd_data_phy2mc_xif[425],rd_data_phy2mc_xif[417],rd_data_phy2mc_xif[409],rd_data_phy2mc_xif[401],rd_data_phy2mc_xif[393],rd_data_phy2mc_xif[385],rd_data_phy2mc_xif[440],rd_data_phy2mc_xif[432],rd_data_phy2mc_xif[424],rd_data_phy2mc_xif[416],rd_data_phy2mc_xif[408],rd_data_phy2mc_xif[400],rd_data_phy2mc_xif[392],rd_data_phy2mc_xif[384:383],rd_data_phy2mc_xif[375],rd_data_phy2mc_xif[367],rd_data_phy2mc_xif[359],rd_data_phy2mc_xif[351],rd_data_phy2mc_xif[343],rd_data_phy2mc_xif[335],rd_data_phy2mc_xif[327],rd_data_phy2mc_xif[382],rd_data_phy2mc_xif[374],rd_data_phy2mc_xif[366],rd_data_phy2mc_xif[358],rd_data_phy2mc_xif[350],rd_data_phy2mc_xif[342],rd_data_phy2mc_xif[334],rd_data_phy2mc_xif[326],rd_data_phy2mc_xif[381],rd_data_phy2mc_xif[373],rd_data_phy2mc_xif[365],rd_data_phy2mc_xif[357],rd_data_phy2mc_xif[349],rd_data_phy2mc_xif[341],rd_data_phy2mc_xif[333],rd_data_phy2mc_xif[325],rd_data_phy2mc_xif[380],rd_data_phy2mc_xif[372],rd_data_phy2mc_xif[364],rd_data_phy2mc_xif[356],rd_data_phy2mc_xif[348],rd_data_phy2mc_xif[340],rd_data_phy2mc_xif[332],rd_data_phy2mc_xif[324],rd_data_phy2mc_xif[379],rd_data_phy2mc_xif[371],rd_data_phy2mc_xif[363],rd_data_phy2mc_xif[355],rd_data_phy2mc_xif[347],rd_data_phy2mc_xif[339],rd_data_phy2mc_xif[331],rd_data_phy2mc_xif[323],rd_data_phy2mc_xif[378],rd_data_phy2mc_xif[370],rd_data_phy2mc_xif[362],rd_data_phy2mc_xif[354],rd_data_phy2mc_xif[346],rd_data_phy2mc_xif[338],rd_data_phy2mc_xif[330],rd_data_phy2mc_xif[322],rd_data_phy2mc_xif[377],rd_data_phy2mc_xif[369],rd_data_phy2mc_xif[361],rd_data_phy2mc_xif[353],rd_data_phy2mc_xif[345],rd_data_phy2mc_xif[337],rd_data_phy2mc_xif[329],rd_data_phy2mc_xif[321],rd_data_phy2mc_xif[376],rd_data_phy2mc_xif[368],rd_data_phy2mc_xif[360],rd_data_phy2mc_xif[352],rd_data_phy2mc_xif[344],rd_data_phy2mc_xif[336],rd_data_phy2mc_xif[328],rd_data_phy2mc_xif[320:319],rd_data_phy2mc_xif[311],rd_data_phy2mc_xif[303],rd_data_phy2mc_xif[295],rd_data_phy2mc_xif[287],rd_data_phy2mc_xif[279],rd_data_phy2mc_xif[271],rd_data_phy2mc_xif[263],rd_data_phy2mc_xif[318],rd_data_phy2mc_xif[310],rd_data_phy2mc_xif[302],rd_data_phy2mc_xif[294],rd_data_phy2mc_xif[286],rd_data_phy2mc_xif[278],rd_data_phy2mc_xif[270],rd_data_phy2mc_xif[262],rd_data_phy2mc_xif[317],rd_data_phy2mc_xif[309],rd_data_phy2mc_xif[301],rd_data_phy2mc_xif[293],rd_data_phy2mc_xif[285],rd_data_phy2mc_xif[277],rd_data_phy2mc_xif[269],rd_data_phy2mc_xif[261],rd_data_phy2mc_xif[316],rd_data_phy2mc_xif[308],rd_data_phy2mc_xif[300],rd_data_phy2mc_xif[292],rd_data_phy2mc_xif[284],rd_data_phy2mc_xif[276],rd_data_phy2mc_xif[268],rd_data_phy2mc_xif[260],rd_data_phy2mc_xif[315],rd_data_phy2mc_xif[307],rd_data_phy2mc_xif[299],rd_data_phy2mc_xif[291],rd_data_phy2mc_xif[283],rd_data_phy2mc_xif[275],rd_data_phy2mc_xif[267],rd_data_phy2mc_xif[259],rd_data_phy2mc_xif[314],rd_data_phy2mc_xif[306],rd_data_phy2mc_xif[298],rd_data_phy2mc_xif[290],rd_data_phy2mc_xif[282],rd_data_phy2mc_xif[274],rd_data_phy2mc_xif[266],rd_data_phy2mc_xif[258],rd_data_phy2mc_xif[313],rd_data_phy2mc_xif[305],rd_data_phy2mc_xif[297],rd_data_phy2mc_xif[289],rd_data_phy2mc_xif[281],rd_data_phy2mc_xif[273],rd_data_phy2mc_xif[265],rd_data_phy2mc_xif[257],rd_data_phy2mc_xif[312],rd_data_phy2mc_xif[304],rd_data_phy2mc_xif[296],rd_data_phy2mc_xif[288],rd_data_phy2mc_xif[280],rd_data_phy2mc_xif[272],rd_data_phy2mc_xif[264],rd_data_phy2mc_xif[256:255],rd_data_phy2mc_xif[247],rd_data_phy2mc_xif[239],rd_data_phy2mc_xif[231],rd_data_phy2mc_xif[223],rd_data_phy2mc_xif[215],rd_data_phy2mc_xif[207],rd_data_phy2mc_xif[199],rd_data_phy2mc_xif[254],rd_data_phy2mc_xif[246],rd_data_phy2mc_xif[238],rd_data_phy2mc_xif[230],rd_data_phy2mc_xif[222],rd_data_phy2mc_xif[214],rd_data_phy2mc_xif[206],rd_data_phy2mc_xif[198],rd_data_phy2mc_xif[253],rd_data_phy2mc_xif[245],rd_data_phy2mc_xif[237],rd_data_phy2mc_xif[229],rd_data_phy2mc_xif[221],rd_data_phy2mc_xif[213],rd_data_phy2mc_xif[205],rd_data_phy2mc_xif[197],rd_data_phy2mc_xif[252],rd_data_phy2mc_xif[244],rd_data_phy2mc_xif[236],rd_data_phy2mc_xif[228],rd_data_phy2mc_xif[220],rd_data_phy2mc_xif[212],rd_data_phy2mc_xif[204],rd_data_phy2mc_xif[196],rd_data_phy2mc_xif[251],rd_data_phy2mc_xif[243],rd_data_phy2mc_xif[235],rd_data_phy2mc_xif[227],rd_data_phy2mc_xif[219],rd_data_phy2mc_xif[211],rd_data_phy2mc_xif[203],rd_data_phy2mc_xif[195],rd_data_phy2mc_xif[250],rd_data_phy2mc_xif[242],rd_data_phy2mc_xif[234],rd_data_phy2mc_xif[226],rd_data_phy2mc_xif[218],rd_data_phy2mc_xif[210],rd_data_phy2mc_xif[202],rd_data_phy2mc_xif[194],rd_data_phy2mc_xif[249],rd_data_phy2mc_xif[241],rd_data_phy2mc_xif[233],rd_data_phy2mc_xif[225],rd_data_phy2mc_xif[217],rd_data_phy2mc_xif[209],rd_data_phy2mc_xif[201],rd_data_phy2mc_xif[193],rd_data_phy2mc_xif[248],rd_data_phy2mc_xif[240],rd_data_phy2mc_xif[232],rd_data_phy2mc_xif[224],rd_data_phy2mc_xif[216],rd_data_phy2mc_xif[208],rd_data_phy2mc_xif[200],rd_data_phy2mc_xif[192:191],rd_data_phy2mc_xif[183],rd_data_phy2mc_xif[175],rd_data_phy2mc_xif[167],rd_data_phy2mc_xif[159],rd_data_phy2mc_xif[151],rd_data_phy2mc_xif[143],rd_data_phy2mc_xif[135],rd_data_phy2mc_xif[190],rd_data_phy2mc_xif[182],rd_data_phy2mc_xif[174],rd_data_phy2mc_xif[166],rd_data_phy2mc_xif[158],rd_data_phy2mc_xif[150],rd_data_phy2mc_xif[142],rd_data_phy2mc_xif[134],rd_data_phy2mc_xif[189],rd_data_phy2mc_xif[181],rd_data_phy2mc_xif[173],rd_data_phy2mc_xif[165],rd_data_phy2mc_xif[157],rd_data_phy2mc_xif[149],rd_data_phy2mc_xif[141],rd_data_phy2mc_xif[133],rd_data_phy2mc_xif[188],rd_data_phy2mc_xif[180],rd_data_phy2mc_xif[172],rd_data_phy2mc_xif[164],rd_data_phy2mc_xif[156],rd_data_phy2mc_xif[148],rd_data_phy2mc_xif[140],rd_data_phy2mc_xif[132],rd_data_phy2mc_xif[187],rd_data_phy2mc_xif[179],rd_data_phy2mc_xif[171],rd_data_phy2mc_xif[163],rd_data_phy2mc_xif[155],rd_data_phy2mc_xif[147],rd_data_phy2mc_xif[139],rd_data_phy2mc_xif[131],rd_data_phy2mc_xif[186],rd_data_phy2mc_xif[178],rd_data_phy2mc_xif[170],rd_data_phy2mc_xif[162],rd_data_phy2mc_xif[154],rd_data_phy2mc_xif[146],rd_data_phy2mc_xif[138],rd_data_phy2mc_xif[130],rd_data_phy2mc_xif[185],rd_data_phy2mc_xif[177],rd_data_phy2mc_xif[169],rd_data_phy2mc_xif[161],rd_data_phy2mc_xif[153],rd_data_phy2mc_xif[145],rd_data_phy2mc_xif[137],rd_data_phy2mc_xif[129],rd_data_phy2mc_xif[184],rd_data_phy2mc_xif[176],rd_data_phy2mc_xif[168],rd_data_phy2mc_xif[160],rd_data_phy2mc_xif[152],rd_data_phy2mc_xif[144],rd_data_phy2mc_xif[136],rd_data_phy2mc_xif[128:127],rd_data_phy2mc_xif[119],rd_data_phy2mc_xif[111],rd_data_phy2mc_xif[103],rd_data_phy2mc_xif[95],rd_data_phy2mc_xif[87],rd_data_phy2mc_xif[79],rd_data_phy2mc_xif[71],rd_data_phy2mc_xif[126],rd_data_phy2mc_xif[118],rd_data_phy2mc_xif[110],rd_data_phy2mc_xif[102],rd_data_phy2mc_xif[94],rd_data_phy2mc_xif[86],rd_data_phy2mc_xif[78],rd_data_phy2mc_xif[70],rd_data_phy2mc_xif[125],rd_data_phy2mc_xif[117],rd_data_phy2mc_xif[109],rd_data_phy2mc_xif[101],rd_data_phy2mc_xif[93],rd_data_phy2mc_xif[85],rd_data_phy2mc_xif[77],rd_data_phy2mc_xif[69],rd_data_phy2mc_xif[124],rd_data_phy2mc_xif[116],rd_data_phy2mc_xif[108],rd_data_phy2mc_xif[100],rd_data_phy2mc_xif[92],rd_data_phy2mc_xif[84],rd_data_phy2mc_xif[76],rd_data_phy2mc_xif[68],rd_data_phy2mc_xif[123],rd_data_phy2mc_xif[115],rd_data_phy2mc_xif[107],rd_data_phy2mc_xif[99],rd_data_phy2mc_xif[91],rd_data_phy2mc_xif[83],rd_data_phy2mc_xif[75],rd_data_phy2mc_xif[67],rd_data_phy2mc_xif[122],rd_data_phy2mc_xif[114],rd_data_phy2mc_xif[106],rd_data_phy2mc_xif[98],rd_data_phy2mc_xif[90],rd_data_phy2mc_xif[82],rd_data_phy2mc_xif[74],rd_data_phy2mc_xif[66],rd_data_phy2mc_xif[121],rd_data_phy2mc_xif[113],rd_data_phy2mc_xif[105],rd_data_phy2mc_xif[97],rd_data_phy2mc_xif[89],rd_data_phy2mc_xif[81],rd_data_phy2mc_xif[73],rd_data_phy2mc_xif[65],rd_data_phy2mc_xif[120],rd_data_phy2mc_xif[112],rd_data_phy2mc_xif[104],rd_data_phy2mc_xif[96],rd_data_phy2mc_xif[88],rd_data_phy2mc_xif[80],rd_data_phy2mc_xif[72],rd_data_phy2mc_xif[64:63],rd_data_phy2mc_xif[55],rd_data_phy2mc_xif[47],rd_data_phy2mc_xif[39],rd_data_phy2mc_xif[31],rd_data_phy2mc_xif[23],rd_data_phy2mc_xif[15],rd_data_phy2mc_xif[7],rd_data_phy2mc_xif[62],rd_data_phy2mc_xif[54],rd_data_phy2mc_xif[46],rd_data_phy2mc_xif[38],rd_data_phy2mc_xif[30],rd_data_phy2mc_xif[22],rd_data_phy2mc_xif[14],rd_data_phy2mc_xif[6],rd_data_phy2mc_xif[61],rd_data_phy2mc_xif[53],rd_data_phy2mc_xif[45],rd_data_phy2mc_xif[37],rd_data_phy2mc_xif[29],rd_data_phy2mc_xif[21],rd_data_phy2mc_xif[13],rd_data_phy2mc_xif[5],rd_data_phy2mc_xif[60],rd_data_phy2mc_xif[52],rd_data_phy2mc_xif[44],rd_data_phy2mc_xif[36],rd_data_phy2mc_xif[28],rd_data_phy2mc_xif[20],rd_data_phy2mc_xif[12],rd_data_phy2mc_xif[4],rd_data_phy2mc_xif[59],rd_data_phy2mc_xif[51],rd_data_phy2mc_xif[43],rd_data_phy2mc_xif[35],rd_data_phy2mc_xif[27],rd_data_phy2mc_xif[19],rd_data_phy2mc_xif[11],rd_data_phy2mc_xif[3],rd_data_phy2mc_xif[58],rd_data_phy2mc_xif[50],rd_data_phy2mc_xif[42],rd_data_phy2mc_xif[34],rd_data_phy2mc_xif[26],rd_data_phy2mc_xif[18],rd_data_phy2mc_xif[10],rd_data_phy2mc_xif[2],rd_data_phy2mc_xif[57],rd_data_phy2mc_xif[49],rd_data_phy2mc_xif[41],rd_data_phy2mc_xif[33],rd_data_phy2mc_xif[25],rd_data_phy2mc_xif[17],rd_data_phy2mc_xif[9],rd_data_phy2mc_xif[1],rd_data_phy2mc_xif[56],rd_data_phy2mc_xif[48],rd_data_phy2mc_xif[40],rd_data_phy2mc_xif[32],rd_data_phy2mc_xif[24],rd_data_phy2mc_xif[16],rd_data_phy2mc_xif[8],rd_data_phy2mc_xif[0]}),
        .DOA(\u_ddr_ui_rd_data/not_strict_mode.rd_status[0]_175 ),
        .DOB({u_ddr_ui_n_25,u_ddr_ui_n_26}),
        .DOC({u_ddr_ui_n_27,u_ddr_ui_n_28}),
        .E(c0_ddr4_app_rdy),
        .Q({u_ddr_ui_n_2,u_ddr_ui_n_3,u_ddr_ui_n_4,u_ddr_ui_n_5,u_ddr_ui_n_6}),
        .SR(SR),
        .accept_ns(accept_ns),
        .accept_reg(u_ddr_ui_n_1059),
        .accept_reg_0(u_ddr_ui_n_1066),
        .accept_reg_1(u_ddr_ui_n_1067),
        .accept_reg_10(u_ddr_ui_n_1076),
        .accept_reg_11(u_ddr_ui_n_1077),
        .accept_reg_12(u_ddr_ui_n_1078),
        .accept_reg_13(u_ddr_ui_n_1079),
        .accept_reg_14(c0_init_calib_complete),
        .accept_reg_15(u_ddr_mc_n_0),
        .accept_reg_16(u_ddr_mc_n_109),
        .accept_reg_2(u_ddr_ui_n_1068),
        .accept_reg_3(u_ddr_ui_n_1069),
        .accept_reg_4(u_ddr_ui_n_1070),
        .accept_reg_5(u_ddr_ui_n_1071),
        .accept_reg_6(u_ddr_ui_n_1072),
        .accept_reg_7(u_ddr_ui_n_1073),
        .accept_reg_8(u_ddr_ui_n_1074),
        .accept_reg_9(u_ddr_ui_n_1075),
        .bank(bank),
        .\buf_fifo_reg[1][0] (u_ddr_mc_n_120),
        .\buf_fifo_reg[1][0]_0 (u_ddr_mc_n_115),
        .\buf_fifo_reg[1][0]_1 (u_ddr_mc_n_110),
        .\buf_fifo_reg[1][1] (u_ddr_mc_n_121),
        .\buf_fifo_reg[1][1]_0 (u_ddr_mc_n_116),
        .\buf_fifo_reg[1][1]_1 (u_ddr_mc_n_111),
        .\buf_fifo_reg[1][2] (u_ddr_mc_n_122),
        .\buf_fifo_reg[1][2]_0 (u_ddr_mc_n_117),
        .\buf_fifo_reg[1][2]_1 (u_ddr_mc_n_112),
        .\buf_fifo_reg[1][3] (u_ddr_mc_n_123),
        .\buf_fifo_reg[1][3]_0 (u_ddr_mc_n_118),
        .\buf_fifo_reg[1][3]_1 (u_ddr_mc_n_113),
        .\buf_fifo_reg[1][4] (u_ddr_mc_n_3),
        .\buf_fifo_reg[1][4]_0 (u_ddr_mc_n_124),
        .\buf_fifo_reg[1][4]_1 (u_ddr_mc_n_2),
        .\buf_fifo_reg[1][4]_2 (u_ddr_mc_n_119),
        .\buf_fifo_reg[1][4]_3 (u_ddr_mc_n_1),
        .\buf_fifo_reg[1][4]_4 (u_ddr_mc_n_114),
        .c0_ddr4_app_addr(c0_ddr4_app_addr),
        .c0_ddr4_app_cmd(c0_ddr4_app_cmd),
        .c0_ddr4_app_en(c0_ddr4_app_en),
        .c0_ddr4_app_rd_data(c0_ddr4_app_rd_data),
        .c0_ddr4_app_rd_data_end(c0_ddr4_app_rd_data_end),
        .c0_ddr4_app_rd_data_valid(c0_ddr4_app_rd_data_valid),
        .c0_ddr4_app_wdf_data(c0_ddr4_app_wdf_data),
        .c0_ddr4_app_wdf_end(c0_ddr4_app_wdf_end),
        .c0_ddr4_app_wdf_mask(c0_ddr4_app_wdf_mask),
        .c0_ddr4_app_wdf_rdy(c0_ddr4_app_wdf_rdy),
        .c0_ddr4_app_wdf_wren(c0_ddr4_app_wdf_wren),
        .calDone_gated_reg(grAccept_ns),
        .cmd(cmd),
        .col(col),
        .dBufAdr(dBufAdr),
        .group(group),
        .in0(\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buf_we_orig ),
        .match4_10_return(\u_ddr_ui_rd_data/match4_10_return ),
        .match4_110_return(\u_ddr_ui_rd_data/match4_110_return ),
        .match4_111_return(\u_ddr_ui_rd_data/match4_111_return ),
        .match4_112_return(\u_ddr_ui_rd_data/match4_112_return ),
        .match4_113_return(\u_ddr_ui_rd_data/match4_113_return ),
        .match4_114_return(\u_ddr_ui_rd_data/match4_114_return ),
        .match4_115_return(\u_ddr_ui_rd_data/match4_115_return ),
        .match4_116_return(\u_ddr_ui_rd_data/match4_116_return ),
        .match4_117_return(\u_ddr_ui_rd_data/match4_117_return ),
        .match4_118_return(\u_ddr_ui_rd_data/match4_118_return ),
        .match4_119_return(\u_ddr_ui_rd_data/match4_119_return ),
        .match4_11_return(\u_ddr_ui_rd_data/match4_11_return ),
        .match4_120_return(\u_ddr_ui_rd_data/match4_120_return ),
        .match4_121_return(\u_ddr_ui_rd_data/match4_121_return ),
        .match4_122_return(\u_ddr_ui_rd_data/match4_122_return ),
        .match4_123_return(\u_ddr_ui_rd_data/match4_123_return ),
        .match4_124_return(\u_ddr_ui_rd_data/match4_124_return ),
        .match4_125_return(\u_ddr_ui_rd_data/match4_125_return ),
        .match4_126_return(\u_ddr_ui_rd_data/match4_126_return ),
        .match4_127_return(\u_ddr_ui_rd_data/match4_127_return ),
        .match4_128_return(\u_ddr_ui_rd_data/match4_128_return ),
        .match4_129_return(\u_ddr_ui_rd_data/match4_129_return ),
        .match4_12_return(\u_ddr_ui_rd_data/match4_12_return ),
        .match4_130_return(\u_ddr_ui_rd_data/match4_130_return ),
        .match4_131_return(\u_ddr_ui_rd_data/match4_131_return ),
        .match4_132_return(\u_ddr_ui_rd_data/match4_132_return ),
        .match4_133_return(\u_ddr_ui_rd_data/match4_133_return ),
        .match4_134_return(\u_ddr_ui_rd_data/match4_134_return ),
        .match4_135_return(\u_ddr_ui_rd_data/match4_135_return ),
        .match4_136_return(\u_ddr_ui_rd_data/match4_136_return ),
        .match4_137_return(\u_ddr_ui_rd_data/match4_137_return ),
        .match4_138_return(\u_ddr_ui_rd_data/match4_138_return ),
        .match4_139_return(\u_ddr_ui_rd_data/match4_139_return ),
        .match4_13_return(\u_ddr_ui_rd_data/match4_13_return ),
        .match4_140_return(\u_ddr_ui_rd_data/match4_140_return ),
        .match4_141_return(\u_ddr_ui_rd_data/match4_141_return ),
        .match4_142_return(\u_ddr_ui_rd_data/match4_142_return ),
        .match4_143_return(\u_ddr_ui_rd_data/match4_143_return ),
        .match4_144_return(\u_ddr_ui_rd_data/match4_144_return ),
        .match4_145_return(\u_ddr_ui_rd_data/match4_145_return ),
        .match4_146_return(\u_ddr_ui_rd_data/match4_146_return ),
        .match4_147_return(\u_ddr_ui_rd_data/match4_147_return ),
        .match4_148_return(\u_ddr_ui_rd_data/match4_148_return ),
        .match4_149_return(\u_ddr_ui_rd_data/match4_149_return ),
        .match4_14_return(\u_ddr_ui_rd_data/match4_14_return ),
        .match4_150_return(\u_ddr_ui_rd_data/match4_150_return ),
        .match4_151_return(\u_ddr_ui_rd_data/match4_151_return ),
        .match4_152_return(\u_ddr_ui_rd_data/match4_152_return ),
        .match4_153_return(\u_ddr_ui_rd_data/match4_153_return ),
        .match4_154_return(\u_ddr_ui_rd_data/match4_154_return ),
        .match4_155_return(\u_ddr_ui_rd_data/match4_155_return ),
        .match4_156_return(\u_ddr_ui_rd_data/match4_156_return ),
        .match4_157_return(\u_ddr_ui_rd_data/match4_157_return ),
        .match4_158_return(\u_ddr_ui_rd_data/match4_158_return ),
        .match4_159_return(\u_ddr_ui_rd_data/match4_159_return ),
        .match4_15_return(\u_ddr_ui_rd_data/match4_15_return ),
        .match4_160_return(\u_ddr_ui_rd_data/match4_160_return ),
        .match4_161_return(\u_ddr_ui_rd_data/match4_161_return ),
        .match4_162_return(\u_ddr_ui_rd_data/match4_162_return ),
        .match4_163_return(\u_ddr_ui_rd_data/match4_163_return ),
        .match4_164_return(\u_ddr_ui_rd_data/match4_164_return ),
        .match4_165_return(\u_ddr_ui_rd_data/match4_165_return ),
        .match4_166_return(\u_ddr_ui_rd_data/match4_166_return ),
        .match4_167_return(\u_ddr_ui_rd_data/match4_167_return ),
        .match4_168_return(\u_ddr_ui_rd_data/match4_168_return ),
        .match4_169_return(\u_ddr_ui_rd_data/match4_169_return ),
        .match4_16_return(\u_ddr_ui_rd_data/match4_16_return ),
        .match4_170_return(\u_ddr_ui_rd_data/match4_170_return ),
        .match4_171_return(\u_ddr_ui_rd_data/match4_171_return ),
        .match4_172_return(\u_ddr_ui_rd_data/match4_172_return ),
        .match4_173_return(\u_ddr_ui_rd_data/match4_173_return ),
        .match4_174_return(\u_ddr_ui_rd_data/match4_174_return ),
        .match4_175_return(\u_ddr_ui_rd_data/match4_175_return ),
        .match4_176_return(\u_ddr_ui_rd_data/match4_176_return ),
        .match4_177_return(\u_ddr_ui_rd_data/match4_177_return ),
        .match4_178_return(\u_ddr_ui_rd_data/match4_178_return ),
        .match4_179_return(\u_ddr_ui_rd_data/match4_179_return ),
        .match4_17_return(\u_ddr_ui_rd_data/match4_17_return ),
        .match4_180_return(\u_ddr_ui_rd_data/match4_180_return ),
        .match4_181_return(\u_ddr_ui_rd_data/match4_181_return ),
        .match4_182_return(\u_ddr_ui_rd_data/match4_182_return ),
        .match4_183_return(\u_ddr_ui_rd_data/match4_183_return ),
        .match4_184_return(\u_ddr_ui_rd_data/match4_184_return ),
        .match4_185_return(\u_ddr_ui_rd_data/match4_185_return ),
        .match4_186_return(\u_ddr_ui_rd_data/match4_186_return ),
        .match4_187_return(\u_ddr_ui_rd_data/match4_187_return ),
        .match4_188_return(\u_ddr_ui_rd_data/match4_188_return ),
        .match4_18_return(\u_ddr_ui_rd_data/match4_18_return ),
        .match4_19_return(\u_ddr_ui_rd_data/match4_19_return ),
        .match4_1_return(\u_ddr_ui_rd_data/match4_1_return ),
        .match6_10_return(\u_ddr_ui_rd_data/match6_10_return ),
        .match6_110_return(\u_ddr_ui_rd_data/match6_110_return ),
        .match6_111_return(\u_ddr_ui_rd_data/match6_111_return ),
        .match6_112_return(\u_ddr_ui_rd_data/match6_112_return ),
        .match6_113_return(\u_ddr_ui_rd_data/match6_113_return ),
        .match6_114_return(\u_ddr_ui_rd_data/match6_114_return ),
        .match6_115_return(\u_ddr_ui_rd_data/match6_115_return ),
        .match6_116_return(\u_ddr_ui_rd_data/match6_116_return ),
        .match6_117_return(\u_ddr_ui_rd_data/match6_117_return ),
        .match6_118_return(\u_ddr_ui_rd_data/match6_118_return ),
        .match6_119_return(\u_ddr_ui_rd_data/match6_119_return ),
        .match6_11_return(\u_ddr_ui_rd_data/match6_11_return ),
        .match6_120_return(\u_ddr_ui_rd_data/match6_120_return ),
        .match6_121_return(\u_ddr_ui_rd_data/match6_121_return ),
        .match6_122_return(\u_ddr_ui_rd_data/match6_122_return ),
        .match6_123_return(\u_ddr_ui_rd_data/match6_123_return ),
        .match6_124_return(\u_ddr_ui_rd_data/match6_124_return ),
        .match6_125_return(\u_ddr_ui_rd_data/match6_125_return ),
        .match6_126_return(\u_ddr_ui_rd_data/match6_126_return ),
        .match6_127_return(\u_ddr_ui_rd_data/match6_127_return ),
        .match6_128_return(\u_ddr_ui_rd_data/match6_128_return ),
        .match6_129_return(\u_ddr_ui_rd_data/match6_129_return ),
        .match6_12_return(\u_ddr_ui_rd_data/match6_12_return ),
        .match6_130_return(\u_ddr_ui_rd_data/match6_130_return ),
        .match6_131_return(\u_ddr_ui_rd_data/match6_131_return ),
        .match6_132_return(\u_ddr_ui_rd_data/match6_132_return ),
        .match6_133_return(\u_ddr_ui_rd_data/match6_133_return ),
        .match6_134_return(\u_ddr_ui_rd_data/match6_134_return ),
        .match6_135_return(\u_ddr_ui_rd_data/match6_135_return ),
        .match6_136_return(\u_ddr_ui_rd_data/match6_136_return ),
        .match6_137_return(\u_ddr_ui_rd_data/match6_137_return ),
        .match6_138_return(\u_ddr_ui_rd_data/match6_138_return ),
        .match6_139_return(\u_ddr_ui_rd_data/match6_139_return ),
        .match6_13_return(\u_ddr_ui_rd_data/match6_13_return ),
        .match6_140_return(\u_ddr_ui_rd_data/match6_140_return ),
        .match6_141_return(\u_ddr_ui_rd_data/match6_141_return ),
        .match6_142_return(\u_ddr_ui_rd_data/match6_142_return ),
        .match6_143_return(\u_ddr_ui_rd_data/match6_143_return ),
        .match6_144_return(\u_ddr_ui_rd_data/match6_144_return ),
        .match6_145_return(\u_ddr_ui_rd_data/match6_145_return ),
        .match6_146_return(\u_ddr_ui_rd_data/match6_146_return ),
        .match6_147_return(\u_ddr_ui_rd_data/match6_147_return ),
        .match6_148_return(\u_ddr_ui_rd_data/match6_148_return ),
        .match6_149_return(\u_ddr_ui_rd_data/match6_149_return ),
        .match6_14_return(\u_ddr_ui_rd_data/match6_14_return ),
        .match6_150_return(\u_ddr_ui_rd_data/match6_150_return ),
        .match6_151_return(\u_ddr_ui_rd_data/match6_151_return ),
        .match6_152_return(\u_ddr_ui_rd_data/match6_152_return ),
        .match6_153_return(\u_ddr_ui_rd_data/match6_153_return ),
        .match6_154_return(\u_ddr_ui_rd_data/match6_154_return ),
        .match6_155_return(\u_ddr_ui_rd_data/match6_155_return ),
        .match6_156_return(\u_ddr_ui_rd_data/match6_156_return ),
        .match6_157_return(\u_ddr_ui_rd_data/match6_157_return ),
        .match6_158_return(\u_ddr_ui_rd_data/match6_158_return ),
        .match6_159_return(\u_ddr_ui_rd_data/match6_159_return ),
        .match6_15_return(\u_ddr_ui_rd_data/match6_15_return ),
        .match6_160_return(\u_ddr_ui_rd_data/match6_160_return ),
        .match6_161_return(\u_ddr_ui_rd_data/match6_161_return ),
        .match6_162_return(\u_ddr_ui_rd_data/match6_162_return ),
        .match6_163_return(\u_ddr_ui_rd_data/match6_163_return ),
        .match6_164_return(\u_ddr_ui_rd_data/match6_164_return ),
        .match6_165_return(\u_ddr_ui_rd_data/match6_165_return ),
        .match6_166_return(\u_ddr_ui_rd_data/match6_166_return ),
        .match6_167_return(\u_ddr_ui_rd_data/match6_167_return ),
        .match6_168_return(\u_ddr_ui_rd_data/match6_168_return ),
        .match6_169_return(\u_ddr_ui_rd_data/match6_169_return ),
        .match6_16_return(\u_ddr_ui_rd_data/match6_16_return ),
        .match6_170_return(\u_ddr_ui_rd_data/match6_170_return ),
        .match6_171_return(\u_ddr_ui_rd_data/match6_171_return ),
        .match6_172_return(\u_ddr_ui_rd_data/match6_172_return ),
        .match6_173_return(\u_ddr_ui_rd_data/match6_173_return ),
        .match6_174_return(\u_ddr_ui_rd_data/match6_174_return ),
        .match6_175_return(\u_ddr_ui_rd_data/match6_175_return ),
        .match6_176_return(\u_ddr_ui_rd_data/match6_176_return ),
        .match6_177_return(\u_ddr_ui_rd_data/match6_177_return ),
        .match6_178_return(\u_ddr_ui_rd_data/match6_178_return ),
        .match6_179_return(\u_ddr_ui_rd_data/match6_179_return ),
        .match6_17_return(\u_ddr_ui_rd_data/match6_17_return ),
        .match6_180_return(\u_ddr_ui_rd_data/match6_180_return ),
        .match6_181_return(\u_ddr_ui_rd_data/match6_181_return ),
        .match6_182_return(\u_ddr_ui_rd_data/match6_182_return ),
        .match6_183_return(\u_ddr_ui_rd_data/match6_183_return ),
        .match6_184_return(\u_ddr_ui_rd_data/match6_184_return ),
        .match6_185_return(\u_ddr_ui_rd_data/match6_185_return ),
        .match6_186_return(\u_ddr_ui_rd_data/match6_186_return ),
        .match6_187_return(\u_ddr_ui_rd_data/match6_187_return ),
        .match6_188_return(\u_ddr_ui_rd_data/match6_188_return ),
        .match6_18_return(\u_ddr_ui_rd_data/match6_18_return ),
        .match6_19_return(\u_ddr_ui_rd_data/match6_19_return ),
        .match6_1_return(\u_ddr_ui_rd_data/match6_1_return ),
        .\not_strict_mode.app_rd_data_end_reg (u_ddr_cal_top_n_907),
        .\not_strict_mode.bypass_cpy2 (\u_ddr_ui_rd_data/not_strict_mode.bypass_cpy2 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0 ({u_ddr_ui_n_23,u_ddr_ui_n_24}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ({u_ddr_cal_top_n_914,u_ddr_cal_top_n_915,u_ddr_cal_top_n_916,u_ddr_cal_top_n_917,u_ddr_cal_top_n_918,u_ddr_cal_top_n_919}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[0].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[0].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0 ({u_ddr_ui_n_83,u_ddr_ui_n_84}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_0 ({u_ddr_ui_n_85,u_ddr_ui_n_86}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_1 ({u_ddr_ui_n_87,u_ddr_ui_n_88}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ({u_ddr_cal_top_n_1000,u_ddr_cal_top_n_1001,u_ddr_cal_top_n_1002,u_ddr_cal_top_n_1003,u_ddr_cal_top_n_1004,u_ddr_cal_top_n_1005}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[10].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[10].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0 ({u_ddr_ui_n_89,u_ddr_ui_n_90}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_0 ({u_ddr_ui_n_91,u_ddr_ui_n_92}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_1 ({u_ddr_ui_n_93,u_ddr_ui_n_94}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ({u_ddr_cal_top_n_1008,u_ddr_cal_top_n_1009,u_ddr_cal_top_n_1010,u_ddr_cal_top_n_1011,u_ddr_cal_top_n_1012,u_ddr_cal_top_n_1013}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[11].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[11].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0 ({u_ddr_ui_n_95,u_ddr_ui_n_96}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_0 ({u_ddr_ui_n_97,u_ddr_ui_n_98}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_1 ({u_ddr_ui_n_99,u_ddr_ui_n_100}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ({u_ddr_cal_top_n_1016,u_ddr_cal_top_n_1017,u_ddr_cal_top_n_1018,u_ddr_cal_top_n_1019,u_ddr_cal_top_n_1020,u_ddr_cal_top_n_1021}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[12].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[12].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0 ({u_ddr_ui_n_101,u_ddr_ui_n_102}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_0 ({u_ddr_ui_n_103,u_ddr_ui_n_104}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_1 ({u_ddr_ui_n_105,u_ddr_ui_n_106}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ({u_ddr_cal_top_n_1024,u_ddr_cal_top_n_1025,u_ddr_cal_top_n_1026,u_ddr_cal_top_n_1027,u_ddr_cal_top_n_1028,u_ddr_cal_top_n_1029}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[13].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[13].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0 ({u_ddr_ui_n_107,u_ddr_ui_n_108}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_0 ({u_ddr_ui_n_109,u_ddr_ui_n_110}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_1 ({u_ddr_ui_n_111,u_ddr_ui_n_112}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ({u_ddr_cal_top_n_1032,u_ddr_cal_top_n_1033,u_ddr_cal_top_n_1034,u_ddr_cal_top_n_1035,u_ddr_cal_top_n_1036,u_ddr_cal_top_n_1037}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[14].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[14].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0 ({u_ddr_ui_n_113,u_ddr_ui_n_114}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_0 ({u_ddr_ui_n_115,u_ddr_ui_n_116}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_1 ({u_ddr_ui_n_117,u_ddr_ui_n_118}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ({u_ddr_cal_top_n_1040,u_ddr_cal_top_n_1041,u_ddr_cal_top_n_1042,u_ddr_cal_top_n_1043,u_ddr_cal_top_n_1044,u_ddr_cal_top_n_1045}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[15].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[15].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0 ({u_ddr_ui_n_119,u_ddr_ui_n_120}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_0 ({u_ddr_ui_n_121,u_ddr_ui_n_122}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_1 ({u_ddr_ui_n_123,u_ddr_ui_n_124}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ({u_ddr_cal_top_n_1048,u_ddr_cal_top_n_1049,u_ddr_cal_top_n_1050,u_ddr_cal_top_n_1051,u_ddr_cal_top_n_1052,u_ddr_cal_top_n_1053}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[16].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[16].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0 ({u_ddr_ui_n_125,u_ddr_ui_n_126}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_0 ({u_ddr_ui_n_127,u_ddr_ui_n_128}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_1 ({u_ddr_ui_n_129,u_ddr_ui_n_130}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ({u_ddr_cal_top_n_1056,u_ddr_cal_top_n_1057,u_ddr_cal_top_n_1058,u_ddr_cal_top_n_1059,u_ddr_cal_top_n_1060,u_ddr_cal_top_n_1061}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[17].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[17].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0 ({u_ddr_ui_n_131,u_ddr_ui_n_132}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_0 ({u_ddr_ui_n_133,u_ddr_ui_n_134}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_1 ({u_ddr_ui_n_135,u_ddr_ui_n_136}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ({u_ddr_cal_top_n_1064,u_ddr_cal_top_n_1065,u_ddr_cal_top_n_1066,u_ddr_cal_top_n_1067,u_ddr_cal_top_n_1068,u_ddr_cal_top_n_1069}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[18].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[18].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0 ({u_ddr_ui_n_137,u_ddr_ui_n_138}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_0 ({u_ddr_ui_n_139,u_ddr_ui_n_140}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_1 ({u_ddr_ui_n_141,u_ddr_ui_n_142}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ({u_ddr_cal_top_n_1072,u_ddr_cal_top_n_1073,u_ddr_cal_top_n_1074,u_ddr_cal_top_n_1075,u_ddr_cal_top_n_1076,u_ddr_cal_top_n_1077}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[19].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[19].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0 ({u_ddr_ui_n_29,u_ddr_ui_n_30}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_0 ({u_ddr_ui_n_31,u_ddr_ui_n_32}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_1 ({u_ddr_ui_n_33,u_ddr_ui_n_34}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ({u_ddr_cal_top_n_924,u_ddr_cal_top_n_925,u_ddr_cal_top_n_926,u_ddr_cal_top_n_927,u_ddr_cal_top_n_928,u_ddr_cal_top_n_929}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[1].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[1].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0 ({u_ddr_ui_n_143,u_ddr_ui_n_144}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_0 ({u_ddr_ui_n_145,u_ddr_ui_n_146}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_1 ({u_ddr_ui_n_147,u_ddr_ui_n_148}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ({u_ddr_cal_top_n_1080,u_ddr_cal_top_n_1081,u_ddr_cal_top_n_1082,u_ddr_cal_top_n_1083,u_ddr_cal_top_n_1084,u_ddr_cal_top_n_1085}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[20].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[20].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0 ({u_ddr_ui_n_149,u_ddr_ui_n_150}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_0 ({u_ddr_ui_n_151,u_ddr_ui_n_152}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_1 ({u_ddr_ui_n_153,u_ddr_ui_n_154}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ({u_ddr_cal_top_n_1088,u_ddr_cal_top_n_1089,u_ddr_cal_top_n_1090,u_ddr_cal_top_n_1091,u_ddr_cal_top_n_1092,u_ddr_cal_top_n_1093}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[21].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[21].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0 ({u_ddr_ui_n_155,u_ddr_ui_n_156}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_0 ({u_ddr_ui_n_157,u_ddr_ui_n_158}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_1 ({u_ddr_ui_n_159,u_ddr_ui_n_160}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ({u_ddr_cal_top_n_1096,u_ddr_cal_top_n_1097,u_ddr_cal_top_n_1098,u_ddr_cal_top_n_1099,u_ddr_cal_top_n_1100,u_ddr_cal_top_n_1101}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[22].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[22].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0 ({u_ddr_ui_n_161,u_ddr_ui_n_162}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_0 ({u_ddr_ui_n_163,u_ddr_ui_n_164}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_1 ({u_ddr_ui_n_165,u_ddr_ui_n_166}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ({u_ddr_cal_top_n_1104,u_ddr_cal_top_n_1105,u_ddr_cal_top_n_1106,u_ddr_cal_top_n_1107,u_ddr_cal_top_n_1108,u_ddr_cal_top_n_1109}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[23].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[23].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0 ({u_ddr_ui_n_167,u_ddr_ui_n_168}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_0 ({u_ddr_ui_n_169,u_ddr_ui_n_170}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_1 ({u_ddr_ui_n_171,u_ddr_ui_n_172}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ({u_ddr_cal_top_n_1112,u_ddr_cal_top_n_1113,u_ddr_cal_top_n_1114,u_ddr_cal_top_n_1115,u_ddr_cal_top_n_1116,u_ddr_cal_top_n_1117}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[24].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[24].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0 ({u_ddr_ui_n_173,u_ddr_ui_n_174}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_0 ({u_ddr_ui_n_175,u_ddr_ui_n_176}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_1 ({u_ddr_ui_n_177,u_ddr_ui_n_178}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ({u_ddr_cal_top_n_1120,u_ddr_cal_top_n_1121,u_ddr_cal_top_n_1122,u_ddr_cal_top_n_1123,u_ddr_cal_top_n_1124,u_ddr_cal_top_n_1125}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[25].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[25].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0 ({u_ddr_ui_n_179,u_ddr_ui_n_180}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_0 ({u_ddr_ui_n_181,u_ddr_ui_n_182}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_1 ({u_ddr_ui_n_183,u_ddr_ui_n_184}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ({u_ddr_cal_top_n_1128,u_ddr_cal_top_n_1129,u_ddr_cal_top_n_1130,u_ddr_cal_top_n_1131,u_ddr_cal_top_n_1132,u_ddr_cal_top_n_1133}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[26].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[26].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0 ({u_ddr_ui_n_185,u_ddr_ui_n_186}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_0 ({u_ddr_ui_n_187,u_ddr_ui_n_188}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_1 ({u_ddr_ui_n_189,u_ddr_ui_n_190}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ({u_ddr_cal_top_n_1136,u_ddr_cal_top_n_1137,u_ddr_cal_top_n_1138,u_ddr_cal_top_n_1139,u_ddr_cal_top_n_1140,u_ddr_cal_top_n_1141}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[27].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[27].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0 ({u_ddr_ui_n_191,u_ddr_ui_n_192}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_0 ({u_ddr_ui_n_193,u_ddr_ui_n_194}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_1 ({u_ddr_ui_n_195,u_ddr_ui_n_196}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ({u_ddr_cal_top_n_1144,u_ddr_cal_top_n_1145,u_ddr_cal_top_n_1146,u_ddr_cal_top_n_1147,u_ddr_cal_top_n_1148,u_ddr_cal_top_n_1149}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[28].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[28].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0 ({u_ddr_ui_n_197,u_ddr_ui_n_198}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_0 ({u_ddr_ui_n_199,u_ddr_ui_n_200}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_1 ({u_ddr_ui_n_201,u_ddr_ui_n_202}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ({u_ddr_cal_top_n_1152,u_ddr_cal_top_n_1153,u_ddr_cal_top_n_1154,u_ddr_cal_top_n_1155,u_ddr_cal_top_n_1156,u_ddr_cal_top_n_1157}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[29].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[29].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0 ({u_ddr_ui_n_35,u_ddr_ui_n_36}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_0 ({u_ddr_ui_n_37,u_ddr_ui_n_38}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_1 ({u_ddr_ui_n_39,u_ddr_ui_n_40}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ({u_ddr_cal_top_n_934,u_ddr_cal_top_n_935,u_ddr_cal_top_n_936,u_ddr_cal_top_n_937,u_ddr_cal_top_n_938,u_ddr_cal_top_n_939}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[2].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[2].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0 ({u_ddr_ui_n_203,u_ddr_ui_n_204}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_0 ({u_ddr_ui_n_205,u_ddr_ui_n_206}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_1 ({u_ddr_ui_n_207,u_ddr_ui_n_208}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ({u_ddr_cal_top_n_1160,u_ddr_cal_top_n_1161,u_ddr_cal_top_n_1162,u_ddr_cal_top_n_1163,u_ddr_cal_top_n_1164,u_ddr_cal_top_n_1165}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[30].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[30].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0 ({u_ddr_ui_n_209,u_ddr_ui_n_210}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_0 ({u_ddr_ui_n_211,u_ddr_ui_n_212}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_1 ({u_ddr_ui_n_213,u_ddr_ui_n_214}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ({u_ddr_cal_top_n_1168,u_ddr_cal_top_n_1169,u_ddr_cal_top_n_1170,u_ddr_cal_top_n_1171,u_ddr_cal_top_n_1172,u_ddr_cal_top_n_1173}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[31].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[31].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0 ({u_ddr_ui_n_215,u_ddr_ui_n_216}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_0 ({u_ddr_ui_n_217,u_ddr_ui_n_218}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_1 ({u_ddr_ui_n_219,u_ddr_ui_n_220}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ({u_ddr_cal_top_n_1176,u_ddr_cal_top_n_1177,u_ddr_cal_top_n_1178,u_ddr_cal_top_n_1179,u_ddr_cal_top_n_1180,u_ddr_cal_top_n_1181}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[32].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[32].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0 ({u_ddr_ui_n_221,u_ddr_ui_n_222}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_0 ({u_ddr_ui_n_223,u_ddr_ui_n_224}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_1 ({u_ddr_ui_n_225,u_ddr_ui_n_226}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ({u_ddr_cal_top_n_1184,u_ddr_cal_top_n_1185,u_ddr_cal_top_n_1186,u_ddr_cal_top_n_1187,u_ddr_cal_top_n_1188,u_ddr_cal_top_n_1189}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[33].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[33].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0 ({u_ddr_ui_n_227,u_ddr_ui_n_228}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_0 ({u_ddr_ui_n_229,u_ddr_ui_n_230}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_1 ({u_ddr_ui_n_231,u_ddr_ui_n_232}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ({u_ddr_cal_top_n_1192,u_ddr_cal_top_n_1193,u_ddr_cal_top_n_1194,u_ddr_cal_top_n_1195,u_ddr_cal_top_n_1196,u_ddr_cal_top_n_1197}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[34].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[34].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0 ({u_ddr_ui_n_233,u_ddr_ui_n_234}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_0 ({u_ddr_ui_n_235,u_ddr_ui_n_236}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_1 ({u_ddr_ui_n_237,u_ddr_ui_n_238}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ({u_ddr_cal_top_n_1200,u_ddr_cal_top_n_1201,u_ddr_cal_top_n_1202,u_ddr_cal_top_n_1203,u_ddr_cal_top_n_1204,u_ddr_cal_top_n_1205}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[35].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[35].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0 ({u_ddr_ui_n_239,u_ddr_ui_n_240}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_0 ({u_ddr_ui_n_241,u_ddr_ui_n_242}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_1 ({u_ddr_ui_n_243,u_ddr_ui_n_244}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ({u_ddr_cal_top_n_1208,u_ddr_cal_top_n_1209,u_ddr_cal_top_n_1210,u_ddr_cal_top_n_1211,u_ddr_cal_top_n_1212,u_ddr_cal_top_n_1213}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[36].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[36].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0 ({u_ddr_ui_n_245,u_ddr_ui_n_246}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_0 ({u_ddr_ui_n_247,u_ddr_ui_n_248}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_1 ({u_ddr_ui_n_249,u_ddr_ui_n_250}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ({u_ddr_cal_top_n_1216,u_ddr_cal_top_n_1217,u_ddr_cal_top_n_1218,u_ddr_cal_top_n_1219,u_ddr_cal_top_n_1220,u_ddr_cal_top_n_1221}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[37].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[37].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0 ({u_ddr_ui_n_251,u_ddr_ui_n_252}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_0 ({u_ddr_ui_n_253,u_ddr_ui_n_254}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_1 ({u_ddr_ui_n_255,u_ddr_ui_n_256}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ({u_ddr_cal_top_n_1224,u_ddr_cal_top_n_1225,u_ddr_cal_top_n_1226,u_ddr_cal_top_n_1227,u_ddr_cal_top_n_1228,u_ddr_cal_top_n_1229}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[38].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[38].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0 ({u_ddr_ui_n_257,u_ddr_ui_n_258}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_0 ({u_ddr_ui_n_259,u_ddr_ui_n_260}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_1 ({u_ddr_ui_n_261,u_ddr_ui_n_262}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ({u_ddr_cal_top_n_1232,u_ddr_cal_top_n_1233,u_ddr_cal_top_n_1234,u_ddr_cal_top_n_1235,u_ddr_cal_top_n_1236,u_ddr_cal_top_n_1237}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[39].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[39].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0 ({u_ddr_ui_n_41,u_ddr_ui_n_42}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_0 ({u_ddr_ui_n_43,u_ddr_ui_n_44}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_1 ({u_ddr_ui_n_45,u_ddr_ui_n_46}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ({u_ddr_cal_top_n_944,u_ddr_cal_top_n_945,u_ddr_cal_top_n_946,u_ddr_cal_top_n_947,u_ddr_cal_top_n_948,u_ddr_cal_top_n_949}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[3].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[3].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0 ({u_ddr_ui_n_263,u_ddr_ui_n_264}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_0 ({u_ddr_ui_n_265,u_ddr_ui_n_266}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_1 ({u_ddr_ui_n_267,u_ddr_ui_n_268}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ({u_ddr_cal_top_n_1240,u_ddr_cal_top_n_1241,u_ddr_cal_top_n_1242,u_ddr_cal_top_n_1243,u_ddr_cal_top_n_1244,u_ddr_cal_top_n_1245}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[40].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[40].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0 ({u_ddr_ui_n_269,u_ddr_ui_n_270}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_0 ({u_ddr_ui_n_271,u_ddr_ui_n_272}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_1 ({u_ddr_ui_n_273,u_ddr_ui_n_274}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ({u_ddr_cal_top_n_1248,u_ddr_cal_top_n_1249,u_ddr_cal_top_n_1250,u_ddr_cal_top_n_1251,u_ddr_cal_top_n_1252,u_ddr_cal_top_n_1253}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[41].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[41].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0 ({u_ddr_ui_n_275,u_ddr_ui_n_276}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_0 ({u_ddr_ui_n_277,u_ddr_ui_n_278}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_1 ({u_ddr_ui_n_279,u_ddr_ui_n_280}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ({u_ddr_cal_top_n_1256,u_ddr_cal_top_n_1257,u_ddr_cal_top_n_1258,u_ddr_cal_top_n_1259,u_ddr_cal_top_n_1260,u_ddr_cal_top_n_1261}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[42].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[42].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0 ({u_ddr_ui_n_281,u_ddr_ui_n_282}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_0 ({u_ddr_ui_n_283,u_ddr_ui_n_284}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_1 ({u_ddr_ui_n_285,u_ddr_ui_n_286}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ({u_ddr_cal_top_n_1264,u_ddr_cal_top_n_1265,u_ddr_cal_top_n_1266,u_ddr_cal_top_n_1267,u_ddr_cal_top_n_1268,u_ddr_cal_top_n_1269}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[43].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[43].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0 ({u_ddr_ui_n_287,u_ddr_ui_n_288}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_0 ({u_ddr_ui_n_289,u_ddr_ui_n_290}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_1 ({u_ddr_ui_n_291,u_ddr_ui_n_292}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ({u_ddr_cal_top_n_1272,u_ddr_cal_top_n_1273,u_ddr_cal_top_n_1274,u_ddr_cal_top_n_1275,u_ddr_cal_top_n_1276,u_ddr_cal_top_n_1277}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[44].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[44].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0 ({u_ddr_ui_n_293,u_ddr_ui_n_294}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_0 ({u_ddr_ui_n_295,u_ddr_ui_n_296}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_1 ({u_ddr_ui_n_297,u_ddr_ui_n_298}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ({u_ddr_cal_top_n_1280,u_ddr_cal_top_n_1281,u_ddr_cal_top_n_1282,u_ddr_cal_top_n_1283,u_ddr_cal_top_n_1284,u_ddr_cal_top_n_1285}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[45].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[45].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0 ({u_ddr_ui_n_299,u_ddr_ui_n_300}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_0 ({u_ddr_ui_n_301,u_ddr_ui_n_302}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_1 ({u_ddr_ui_n_303,u_ddr_ui_n_304}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ({u_ddr_cal_top_n_1288,u_ddr_cal_top_n_1289,u_ddr_cal_top_n_1290,u_ddr_cal_top_n_1291,u_ddr_cal_top_n_1292,u_ddr_cal_top_n_1293}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[46].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[46].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0 ({u_ddr_ui_n_305,u_ddr_ui_n_306}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_0 ({u_ddr_ui_n_307,u_ddr_ui_n_308}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_1 ({u_ddr_ui_n_309,u_ddr_ui_n_310}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ({u_ddr_cal_top_n_1296,u_ddr_cal_top_n_1297,u_ddr_cal_top_n_1298,u_ddr_cal_top_n_1299,u_ddr_cal_top_n_1300,u_ddr_cal_top_n_1301}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[47].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[47].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0 ({u_ddr_ui_n_311,u_ddr_ui_n_312}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_0 ({u_ddr_ui_n_313,u_ddr_ui_n_314}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_1 ({u_ddr_ui_n_315,u_ddr_ui_n_316}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ({u_ddr_cal_top_n_1304,u_ddr_cal_top_n_1305,u_ddr_cal_top_n_1306,u_ddr_cal_top_n_1307,u_ddr_cal_top_n_1308,u_ddr_cal_top_n_1309}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[48].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[48].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0 ({u_ddr_ui_n_317,u_ddr_ui_n_318}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_0 ({u_ddr_ui_n_319,u_ddr_ui_n_320}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_1 ({u_ddr_ui_n_321,u_ddr_ui_n_322}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ({u_ddr_cal_top_n_1312,u_ddr_cal_top_n_1313,u_ddr_cal_top_n_1314,u_ddr_cal_top_n_1315,u_ddr_cal_top_n_1316,u_ddr_cal_top_n_1317}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[49].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[49].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0 ({u_ddr_ui_n_47,u_ddr_ui_n_48}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_0 ({u_ddr_ui_n_49,u_ddr_ui_n_50}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_1 ({u_ddr_ui_n_51,u_ddr_ui_n_52}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_2 ({u_ddr_cal_top_n_931,u_ddr_cal_top_n_932}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ({u_ddr_cal_top_n_952,u_ddr_cal_top_n_953,u_ddr_cal_top_n_954,u_ddr_cal_top_n_955,u_ddr_cal_top_n_956,u_ddr_cal_top_n_957}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[4].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[4].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0 ({u_ddr_ui_n_323,u_ddr_ui_n_324}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_0 ({u_ddr_ui_n_325,u_ddr_ui_n_326}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_1 ({u_ddr_ui_n_327,u_ddr_ui_n_328}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ({u_ddr_cal_top_n_1320,u_ddr_cal_top_n_1321,u_ddr_cal_top_n_1322,u_ddr_cal_top_n_1323,u_ddr_cal_top_n_1324,u_ddr_cal_top_n_1325}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[50].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[50].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0 ({u_ddr_ui_n_329,u_ddr_ui_n_330}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_0 ({u_ddr_ui_n_331,u_ddr_ui_n_332}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_1 ({u_ddr_ui_n_333,u_ddr_ui_n_334}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ({u_ddr_cal_top_n_1328,u_ddr_cal_top_n_1329,u_ddr_cal_top_n_1330,u_ddr_cal_top_n_1331,u_ddr_cal_top_n_1332,u_ddr_cal_top_n_1333}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[51].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[51].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0 ({u_ddr_ui_n_335,u_ddr_ui_n_336}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_0 ({u_ddr_ui_n_337,u_ddr_ui_n_338}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_1 ({u_ddr_ui_n_339,u_ddr_ui_n_340}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ({u_ddr_cal_top_n_1336,u_ddr_cal_top_n_1337,u_ddr_cal_top_n_1338,u_ddr_cal_top_n_1339,u_ddr_cal_top_n_1340,u_ddr_cal_top_n_1341}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[52].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[52].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0 ({u_ddr_ui_n_341,u_ddr_ui_n_342}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_0 ({u_ddr_ui_n_343,u_ddr_ui_n_344}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_1 ({u_ddr_ui_n_345,u_ddr_ui_n_346}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ({u_ddr_cal_top_n_1344,u_ddr_cal_top_n_1345,u_ddr_cal_top_n_1346,u_ddr_cal_top_n_1347,u_ddr_cal_top_n_1348,u_ddr_cal_top_n_1349}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[53].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[53].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0 ({u_ddr_ui_n_347,u_ddr_ui_n_348}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_0 ({u_ddr_ui_n_349,u_ddr_ui_n_350}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_1 ({u_ddr_ui_n_351,u_ddr_ui_n_352}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ({u_ddr_cal_top_n_1352,u_ddr_cal_top_n_1353,u_ddr_cal_top_n_1354,u_ddr_cal_top_n_1355,u_ddr_cal_top_n_1356,u_ddr_cal_top_n_1357}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[54].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[54].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0 ({u_ddr_ui_n_353,u_ddr_ui_n_354}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_0 ({u_ddr_ui_n_355,u_ddr_ui_n_356}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_1 ({u_ddr_ui_n_357,u_ddr_ui_n_358}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ({u_ddr_cal_top_n_1360,u_ddr_cal_top_n_1361,u_ddr_cal_top_n_1362,u_ddr_cal_top_n_1363,u_ddr_cal_top_n_1364,u_ddr_cal_top_n_1365}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[55].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[55].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0 ({u_ddr_ui_n_359,u_ddr_ui_n_360}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_0 ({u_ddr_ui_n_361,u_ddr_ui_n_362}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_1 ({u_ddr_ui_n_363,u_ddr_ui_n_364}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ({u_ddr_cal_top_n_1368,u_ddr_cal_top_n_1369,u_ddr_cal_top_n_1370,u_ddr_cal_top_n_1371,u_ddr_cal_top_n_1372,u_ddr_cal_top_n_1373}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[56].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[56].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0 ({u_ddr_ui_n_365,u_ddr_ui_n_366}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_0 ({u_ddr_ui_n_367,u_ddr_ui_n_368}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_1 ({u_ddr_ui_n_369,u_ddr_ui_n_370}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ({u_ddr_cal_top_n_1376,u_ddr_cal_top_n_1377,u_ddr_cal_top_n_1378,u_ddr_cal_top_n_1379,u_ddr_cal_top_n_1380,u_ddr_cal_top_n_1381}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[57].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[57].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0 ({u_ddr_ui_n_371,u_ddr_ui_n_372}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_0 ({u_ddr_ui_n_373,u_ddr_ui_n_374}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_1 ({u_ddr_ui_n_375,u_ddr_ui_n_376}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ({u_ddr_cal_top_n_1384,u_ddr_cal_top_n_1385,u_ddr_cal_top_n_1386,u_ddr_cal_top_n_1387,u_ddr_cal_top_n_1388,u_ddr_cal_top_n_1389}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[58].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[58].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0 ({u_ddr_ui_n_377,u_ddr_ui_n_378}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_0 ({u_ddr_ui_n_379,u_ddr_ui_n_380}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_1 ({u_ddr_ui_n_381,u_ddr_ui_n_382}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ({u_ddr_cal_top_n_1392,u_ddr_cal_top_n_1393,u_ddr_cal_top_n_1394,u_ddr_cal_top_n_1395,u_ddr_cal_top_n_1396,u_ddr_cal_top_n_1397}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[59].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[59].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0 ({u_ddr_ui_n_53,u_ddr_ui_n_54}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_0 ({u_ddr_ui_n_55,u_ddr_ui_n_56}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_1 ({u_ddr_ui_n_57,u_ddr_ui_n_58}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_2 ({u_ddr_cal_top_n_941,u_ddr_cal_top_n_942}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ({u_ddr_cal_top_n_960,u_ddr_cal_top_n_961,u_ddr_cal_top_n_962,u_ddr_cal_top_n_963,u_ddr_cal_top_n_964,u_ddr_cal_top_n_965}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[5].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[5].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0 ({u_ddr_ui_n_383,u_ddr_ui_n_384}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_0 ({u_ddr_ui_n_385,u_ddr_ui_n_386}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_1 ({u_ddr_ui_n_387,u_ddr_ui_n_388}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ({u_ddr_cal_top_n_1400,u_ddr_cal_top_n_1401,u_ddr_cal_top_n_1402,u_ddr_cal_top_n_1403,u_ddr_cal_top_n_1404,u_ddr_cal_top_n_1405}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[60].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[60].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0 ({u_ddr_ui_n_389,u_ddr_ui_n_390}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_0 ({u_ddr_ui_n_391,u_ddr_ui_n_392}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_1 ({u_ddr_ui_n_393,u_ddr_ui_n_394}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ({u_ddr_cal_top_n_1408,u_ddr_cal_top_n_1409,u_ddr_cal_top_n_1410,u_ddr_cal_top_n_1411,u_ddr_cal_top_n_1412,u_ddr_cal_top_n_1413}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[61].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[61].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0 ({u_ddr_ui_n_395,u_ddr_ui_n_396}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_0 ({u_ddr_ui_n_397,u_ddr_ui_n_398}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_1 ({u_ddr_ui_n_399,u_ddr_ui_n_400}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ({u_ddr_cal_top_n_1416,u_ddr_cal_top_n_1417,u_ddr_cal_top_n_1418,u_ddr_cal_top_n_1419,u_ddr_cal_top_n_1420,u_ddr_cal_top_n_1421}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[62].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[62].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0 ({u_ddr_ui_n_401,u_ddr_ui_n_402}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_0 ({u_ddr_ui_n_403,u_ddr_ui_n_404}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_1 ({u_ddr_ui_n_405,u_ddr_ui_n_406}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ({u_ddr_cal_top_n_1424,u_ddr_cal_top_n_1425,u_ddr_cal_top_n_1426,u_ddr_cal_top_n_1427,u_ddr_cal_top_n_1428,u_ddr_cal_top_n_1429}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[63].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[63].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0 ({u_ddr_ui_n_407,u_ddr_ui_n_408}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_0 ({u_ddr_ui_n_409,u_ddr_ui_n_410}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_1 ({u_ddr_ui_n_411,u_ddr_ui_n_412}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ({u_ddr_cal_top_n_1432,u_ddr_cal_top_n_1433,u_ddr_cal_top_n_1434,u_ddr_cal_top_n_1435,u_ddr_cal_top_n_1436,u_ddr_cal_top_n_1437}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[64].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[64].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0 ({u_ddr_ui_n_413,u_ddr_ui_n_414}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_0 ({u_ddr_ui_n_415,u_ddr_ui_n_416}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_1 ({u_ddr_ui_n_417,u_ddr_ui_n_418}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ({u_ddr_cal_top_n_1440,u_ddr_cal_top_n_1441,u_ddr_cal_top_n_1442,u_ddr_cal_top_n_1443,u_ddr_cal_top_n_1444,u_ddr_cal_top_n_1445}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[65].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[65].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0 ({u_ddr_ui_n_419,u_ddr_ui_n_420}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_0 ({u_ddr_ui_n_421,u_ddr_ui_n_422}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_1 ({u_ddr_ui_n_423,u_ddr_ui_n_424}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ({u_ddr_cal_top_n_1448,u_ddr_cal_top_n_1449,u_ddr_cal_top_n_1450,u_ddr_cal_top_n_1451,u_ddr_cal_top_n_1452,u_ddr_cal_top_n_1453}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[66].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[66].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0 ({u_ddr_ui_n_425,u_ddr_ui_n_426}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_0 ({u_ddr_ui_n_427,u_ddr_ui_n_428}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_1 ({u_ddr_ui_n_429,u_ddr_ui_n_430}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ({u_ddr_cal_top_n_1456,u_ddr_cal_top_n_1457,u_ddr_cal_top_n_1458,u_ddr_cal_top_n_1459,u_ddr_cal_top_n_1460,u_ddr_cal_top_n_1461}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[67].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[67].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0 ({u_ddr_ui_n_431,u_ddr_ui_n_432}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_0 ({u_ddr_ui_n_433,u_ddr_ui_n_434}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_1 ({u_ddr_ui_n_435,u_ddr_ui_n_436}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ({u_ddr_cal_top_n_1464,u_ddr_cal_top_n_1465,u_ddr_cal_top_n_1466,u_ddr_cal_top_n_1467,u_ddr_cal_top_n_1468,u_ddr_cal_top_n_1469}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[68].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[68].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0 ({u_ddr_ui_n_437,u_ddr_ui_n_438}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_0 ({u_ddr_ui_n_439,u_ddr_ui_n_440}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_1 ({u_ddr_ui_n_441,u_ddr_ui_n_442}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ({u_ddr_cal_top_n_1472,u_ddr_cal_top_n_1473,u_ddr_cal_top_n_1474,u_ddr_cal_top_n_1475,u_ddr_cal_top_n_1476,u_ddr_cal_top_n_1477}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[69].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[69].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0 ({u_ddr_ui_n_59,u_ddr_ui_n_60}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_0 ({u_ddr_ui_n_61,u_ddr_ui_n_62}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_1 ({u_ddr_ui_n_63,u_ddr_ui_n_64}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ({u_ddr_cal_top_n_968,u_ddr_cal_top_n_969,u_ddr_cal_top_n_970,u_ddr_cal_top_n_971,u_ddr_cal_top_n_972,u_ddr_cal_top_n_973}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[6].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[6].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0 ({u_ddr_ui_n_443,u_ddr_ui_n_444}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_0 ({u_ddr_ui_n_445,u_ddr_ui_n_446}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_1 ({u_ddr_ui_n_447,u_ddr_ui_n_448}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ({u_ddr_cal_top_n_1480,u_ddr_cal_top_n_1481,u_ddr_cal_top_n_1482,u_ddr_cal_top_n_1483,u_ddr_cal_top_n_1484,u_ddr_cal_top_n_1485}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[70].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[70].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0 ({u_ddr_ui_n_449,u_ddr_ui_n_450}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_0 ({u_ddr_ui_n_451,u_ddr_ui_n_452}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_1 ({u_ddr_ui_n_453,u_ddr_ui_n_454}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ({u_ddr_cal_top_n_1488,u_ddr_cal_top_n_1489,u_ddr_cal_top_n_1490,u_ddr_cal_top_n_1491,u_ddr_cal_top_n_1492,u_ddr_cal_top_n_1493}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[71].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[71].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0 ({u_ddr_ui_n_455,u_ddr_ui_n_456}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_0 ({u_ddr_ui_n_457,u_ddr_ui_n_458}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_1 ({u_ddr_ui_n_459,u_ddr_ui_n_460}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ({u_ddr_cal_top_n_1496,u_ddr_cal_top_n_1497,u_ddr_cal_top_n_1498,u_ddr_cal_top_n_1499,u_ddr_cal_top_n_1500,u_ddr_cal_top_n_1501}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[72].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[72].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0 ({u_ddr_ui_n_461,u_ddr_ui_n_462}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_0 ({u_ddr_ui_n_463,u_ddr_ui_n_464}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_1 ({u_ddr_ui_n_465,u_ddr_ui_n_466}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ({u_ddr_cal_top_n_1504,u_ddr_cal_top_n_1505,u_ddr_cal_top_n_1506,u_ddr_cal_top_n_1507,u_ddr_cal_top_n_1508,u_ddr_cal_top_n_1509}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[73].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[73].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0 ({u_ddr_ui_n_467,u_ddr_ui_n_468}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_0 ({u_ddr_ui_n_469,u_ddr_ui_n_470}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_1 ({u_ddr_ui_n_471,u_ddr_ui_n_472}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ({u_ddr_cal_top_n_1512,u_ddr_cal_top_n_1513,u_ddr_cal_top_n_1514,u_ddr_cal_top_n_1515,u_ddr_cal_top_n_1516,u_ddr_cal_top_n_1517}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[74].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[74].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0 ({u_ddr_ui_n_473,u_ddr_ui_n_474}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_0 ({u_ddr_ui_n_475,u_ddr_ui_n_476}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_1 ({u_ddr_ui_n_477,u_ddr_ui_n_478}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ({u_ddr_cal_top_n_1520,u_ddr_cal_top_n_1521,u_ddr_cal_top_n_1522,u_ddr_cal_top_n_1523,u_ddr_cal_top_n_1524,u_ddr_cal_top_n_1525}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[75].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[75].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0 ({u_ddr_ui_n_479,u_ddr_ui_n_480}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_0 ({u_ddr_ui_n_481,u_ddr_ui_n_482}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_1 ({u_ddr_ui_n_483,u_ddr_ui_n_484}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ({u_ddr_cal_top_n_1528,u_ddr_cal_top_n_1529,u_ddr_cal_top_n_1530,u_ddr_cal_top_n_1531,u_ddr_cal_top_n_1532,u_ddr_cal_top_n_1533}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[76].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[76].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0 ({u_ddr_ui_n_485,u_ddr_ui_n_486}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_0 ({u_ddr_ui_n_487,u_ddr_ui_n_488}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_1 ({u_ddr_ui_n_489,u_ddr_ui_n_490}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ({u_ddr_cal_top_n_1536,u_ddr_cal_top_n_1537,u_ddr_cal_top_n_1538,u_ddr_cal_top_n_1539,u_ddr_cal_top_n_1540,u_ddr_cal_top_n_1541}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[77].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[77].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0 ({u_ddr_ui_n_491,u_ddr_ui_n_492}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_0 ({u_ddr_ui_n_493,u_ddr_ui_n_494}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_1 ({u_ddr_ui_n_495,u_ddr_ui_n_496}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ({u_ddr_cal_top_n_1544,u_ddr_cal_top_n_1545,u_ddr_cal_top_n_1546,u_ddr_cal_top_n_1547,u_ddr_cal_top_n_1548,u_ddr_cal_top_n_1549}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[78].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[78].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0 ({u_ddr_ui_n_497,u_ddr_ui_n_498}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_0 ({u_ddr_ui_n_499,u_ddr_ui_n_500}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_1 ({u_ddr_ui_n_501,u_ddr_ui_n_502}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ({u_ddr_cal_top_n_1552,u_ddr_cal_top_n_1553,u_ddr_cal_top_n_1554,u_ddr_cal_top_n_1555,u_ddr_cal_top_n_1556,u_ddr_cal_top_n_1557}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[79].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[79].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0 ({u_ddr_ui_n_65,u_ddr_ui_n_66}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_0 ({u_ddr_ui_n_67,u_ddr_ui_n_68}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_1 ({u_ddr_ui_n_69,u_ddr_ui_n_70}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ({u_ddr_cal_top_n_976,u_ddr_cal_top_n_977,u_ddr_cal_top_n_978,u_ddr_cal_top_n_979,u_ddr_cal_top_n_980,u_ddr_cal_top_n_981}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[7].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[7].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0 ({u_ddr_ui_n_503,u_ddr_ui_n_504}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_0 ({u_ddr_ui_n_505,u_ddr_ui_n_506}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_1 ({u_ddr_ui_n_507,u_ddr_ui_n_508}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ({u_ddr_cal_top_n_1560,u_ddr_cal_top_n_1561,u_ddr_cal_top_n_1562,u_ddr_cal_top_n_1563,u_ddr_cal_top_n_1564,u_ddr_cal_top_n_1565}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[80].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[80].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0 ({u_ddr_ui_n_509,u_ddr_ui_n_510}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_0 ({u_ddr_ui_n_511,u_ddr_ui_n_512}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_1 ({u_ddr_ui_n_513,u_ddr_ui_n_514}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ({u_ddr_cal_top_n_1568,u_ddr_cal_top_n_1569,u_ddr_cal_top_n_1570,u_ddr_cal_top_n_1571,u_ddr_cal_top_n_1572,u_ddr_cal_top_n_1573}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[81].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[81].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0 ({u_ddr_ui_n_515,u_ddr_ui_n_516}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_0 ({u_ddr_ui_n_517,u_ddr_ui_n_518}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_1 ({u_ddr_ui_n_519,u_ddr_ui_n_520}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ({u_ddr_cal_top_n_1576,u_ddr_cal_top_n_1577,u_ddr_cal_top_n_1578,u_ddr_cal_top_n_1579,u_ddr_cal_top_n_1580,u_ddr_cal_top_n_1581}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[82].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[82].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0 ({u_ddr_ui_n_521,u_ddr_ui_n_522}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_0 ({u_ddr_ui_n_523,u_ddr_ui_n_524}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_1 ({u_ddr_ui_n_525,u_ddr_ui_n_526}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ({u_ddr_cal_top_n_1584,u_ddr_cal_top_n_1585,u_ddr_cal_top_n_1586,u_ddr_cal_top_n_1587,u_ddr_cal_top_n_1588,u_ddr_cal_top_n_1589}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[83].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[83].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0 ({u_ddr_ui_n_527,u_ddr_ui_n_528}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_0 ({u_ddr_ui_n_529,u_ddr_ui_n_530}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_1 ({u_ddr_ui_n_531,u_ddr_ui_n_532}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ({u_ddr_cal_top_n_1592,u_ddr_cal_top_n_1593,u_ddr_cal_top_n_1594,u_ddr_cal_top_n_1595,u_ddr_cal_top_n_1596,u_ddr_cal_top_n_1597}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[84].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[84].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ({u_ddr_ui_n_533,u_ddr_ui_n_534}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ({u_ddr_cal_top_n_1600,u_ddr_cal_top_n_1601}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] ({u_ddr_ui_n_536,u_ddr_ui_n_537,u_ddr_ui_n_538,u_ddr_ui_n_539,u_ddr_ui_n_540,u_ddr_ui_n_541,u_ddr_ui_n_542,u_ddr_ui_n_543,u_ddr_ui_n_544,u_ddr_ui_n_545,u_ddr_ui_n_546,u_ddr_ui_n_547,u_ddr_ui_n_548,u_ddr_ui_n_549,u_ddr_ui_n_550,u_ddr_ui_n_551,u_ddr_ui_n_552,u_ddr_ui_n_553,u_ddr_ui_n_554,u_ddr_ui_n_555,u_ddr_ui_n_556,u_ddr_ui_n_557,u_ddr_ui_n_558,u_ddr_ui_n_559,u_ddr_ui_n_560,u_ddr_ui_n_561,u_ddr_ui_n_562,u_ddr_ui_n_563,u_ddr_ui_n_564,u_ddr_ui_n_565,u_ddr_ui_n_566,u_ddr_ui_n_567,u_ddr_ui_n_568,u_ddr_ui_n_569,u_ddr_ui_n_570,u_ddr_ui_n_571,u_ddr_ui_n_572,u_ddr_ui_n_573,u_ddr_ui_n_574,u_ddr_ui_n_575,u_ddr_ui_n_576,u_ddr_ui_n_577,u_ddr_ui_n_578,u_ddr_ui_n_579,u_ddr_ui_n_580,u_ddr_ui_n_581,u_ddr_ui_n_582,u_ddr_ui_n_583,u_ddr_ui_n_584,u_ddr_ui_n_585,u_ddr_ui_n_586,u_ddr_ui_n_587,u_ddr_ui_n_588,u_ddr_ui_n_589,u_ddr_ui_n_590,u_ddr_ui_n_591,u_ddr_ui_n_592,u_ddr_ui_n_593,u_ddr_ui_n_594,u_ddr_ui_n_595,u_ddr_ui_n_596,u_ddr_ui_n_597,u_ddr_ui_n_598,u_ddr_ui_n_599,u_ddr_ui_n_600,u_ddr_ui_n_601,u_ddr_ui_n_602,u_ddr_ui_n_603,u_ddr_ui_n_604,u_ddr_ui_n_605,u_ddr_ui_n_606,u_ddr_ui_n_607,u_ddr_ui_n_608,u_ddr_ui_n_609,u_ddr_ui_n_610,u_ddr_ui_n_611,u_ddr_ui_n_612,u_ddr_ui_n_613,u_ddr_ui_n_614,u_ddr_ui_n_615,u_ddr_ui_n_616,u_ddr_ui_n_617,u_ddr_ui_n_618,u_ddr_ui_n_619,u_ddr_ui_n_620,u_ddr_ui_n_621}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[85].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[85].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0 ({u_ddr_ui_n_71,u_ddr_ui_n_72}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_0 ({u_ddr_ui_n_73,u_ddr_ui_n_74}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_1 ({u_ddr_ui_n_75,u_ddr_ui_n_76}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ({u_ddr_cal_top_n_984,u_ddr_cal_top_n_985,u_ddr_cal_top_n_986,u_ddr_cal_top_n_987,u_ddr_cal_top_n_988,u_ddr_cal_top_n_989}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[8].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[8].addr }),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0 ({u_ddr_ui_n_77,u_ddr_ui_n_78}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_0 ({u_ddr_ui_n_79,u_ddr_ui_n_80}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_1 ({u_ddr_ui_n_81,u_ddr_ui_n_82}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ({u_ddr_cal_top_n_992,u_ddr_cal_top_n_993,u_ddr_cal_top_n_994,u_ddr_cal_top_n_995,u_ddr_cal_top_n_996,u_ddr_cal_top_n_997}),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4] ({\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[9].addr__0 ,\u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[9].addr }),
        .\not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[4] (rd_data_addr_phy2mc[4:3]),
        .\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4] ({u_ddr_ui_n_18,u_ddr_ui_n_19,u_ddr_ui_n_20,u_ddr_ui_n_21,u_ddr_ui_n_22}),
        .\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4] ({u_ddr_ui_n_7,u_ddr_ui_n_8,u_ddr_ui_n_9,u_ddr_ui_n_10,u_ddr_ui_n_11}),
        .\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4] ({u_ddr_ui_n_12,u_ddr_ui_n_13,u_ddr_ui_n_14,u_ddr_ui_n_15,u_ddr_ui_n_16}),
        .out(ram_init_done_r),
        .periodic_read_or_ref_block_reg(u_ddr_ui_n_1084),
        .pointer_we(\u_ddr_ui_wr_data/pointer_we ),
        .\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4] ({\u_ddr_ui_rd_data/rd_buf_index_cpy[19].rd_buf_indx_r_reg[19]_188 ,ram_init_addr}),
        .rd_data_en_phy2mc(rd_data_en_phy2mc),
        .\rd_data_indx_r_reg[3] (\SYNC[19].sync_reg_reg[1] ),
        .\rd_data_indx_r_reg[3]_0 (wrDataEn),
        .row_mc_phy(row_mc_phy),
        .useAdr(useAdr),
        .\wr_buf_out_data_reg[575] ({wr_data_mask_ni2mc,wr_data_ni2mc}),
        .\wr_buffer_ram[40].RAM32M0 ({u_ddr_cal_top_n_2119,u_ddr_cal_top_n_2120,u_ddr_cal_top_n_2121,u_ddr_cal_top_n_2122}),
        .\wr_buffer_ram[8].RAM32M0 ({u_ddr_cal_top_n_2123,u_ddr_cal_top_n_2124,u_ddr_cal_top_n_2125,u_ddr_cal_top_n_2126}));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized4 u_en_vtc_sync
       (.CLK(CLK),
        .D(en_vtc_in),
        .out(en_vtc_riuclk));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized4_0 u_fab_rst_sync
       (.CLK(CLK),
        .D(rst_r1),
        .out(fab_rst_sync));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized9 u_io_addr_strobe_lvl_sync
       (.D(io_addr_strobe_lvl_riuclk),
        .\SYNC[0].sync_reg_reg[1]_0 (\SYNC[19].sync_reg_reg[1] ),
        .out(io_addr_strobe_lvl));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized8 u_io_addr_sync
       (.E(u_io_addr_sync_n_116),
        .\SYNC[0].sync_reg_reg[1]_0 (u_io_addr_sync_n_22),
        .\SYNC[0].sync_reg_reg[1]_1 (u_io_addr_sync_n_25),
        .\SYNC[0].sync_reg_reg[1]_2 (u_io_addr_sync_n_107),
        .\SYNC[0].sync_reg_reg[1]_3 (u_io_addr_sync_n_109),
        .\SYNC[0].sync_reg_reg[1]_4 (u_io_addr_sync_n_112),
        .\SYNC[0].sync_reg_reg[1]_5 (u_io_addr_sync_n_113),
        .\SYNC[0].sync_reg_reg[1]_6 (u_io_addr_sync_n_114),
        .\SYNC[0].sync_reg_reg[1]_7 (u_io_addr_sync_n_138),
        .\SYNC[0].sync_reg_reg[1]_8 ({\u_ddr_cal/u_ddr_config_rom/mem [11:8],\u_ddr_cal/u_ddr_config_rom/mem [6:0]}),
        .\SYNC[10].sync_reg_reg[1]_0 (u_io_addr_sync_n_46),
        .\SYNC[12].sync_reg_reg[1]_0 (u_io_addr_sync_n_90),
        .\SYNC[12].sync_reg_reg[1]_1 (u_io_addr_sync_n_94),
        .\SYNC[12].sync_reg_reg[1]_2 (u_io_addr_sync_n_100),
        .\SYNC[17].sync_reg_reg[1]_0 (u_io_addr_sync_n_26),
        .\SYNC[17].sync_reg_reg[1]_1 (u_io_addr_sync_n_44),
        .\SYNC[17].sync_reg_reg[1]_2 (u_io_addr_sync_n_54),
        .\SYNC[17].sync_reg_reg[1]_3 (u_io_addr_sync_n_97),
        .\SYNC[17].sync_reg_reg[1]_4 (u_io_addr_sync_n_98),
        .\SYNC[18].sync_reg_reg[1]_0 (u_io_addr_sync_n_28),
        .\SYNC[18].sync_reg_reg[1]_1 (u_io_addr_sync_n_45),
        .\SYNC[18].sync_reg_reg[1]_2 (u_io_addr_sync_n_96),
        .\SYNC[18].sync_reg_reg[1]_3 (u_io_addr_sync_n_102),
        .\SYNC[19].sync_reg_reg[1]_0 (u_io_addr_sync_n_29),
        .\SYNC[19].sync_reg_reg[1]_1 (u_io_addr_sync_n_48),
        .\SYNC[1].sync_reg_reg[1]_0 (u_io_addr_sync_n_32),
        .\SYNC[1].sync_reg_reg[1]_1 (u_io_addr_sync_n_33),
        .\SYNC[1].sync_reg_reg[1]_2 ({u_io_addr_sync_n_57,u_io_addr_sync_n_58,u_io_addr_sync_n_59,u_io_addr_sync_n_60,u_io_addr_sync_n_61,u_io_addr_sync_n_62,u_io_addr_sync_n_63,u_io_addr_sync_n_64}),
        .\SYNC[1].sync_reg_reg[1]_3 (u_io_addr_sync_n_137),
        .\SYNC[20].sync_reg_reg[1]_0 (u_io_addr_sync_n_27),
        .\SYNC[20].sync_reg_reg[1]_1 (\u_ddr_cal/u_ddr_cal_addr_decode/cplx_config0_out ),
        .\SYNC[20].sync_reg_reg[1]_2 (u_io_addr_sync_n_105),
        .\SYNC[20].sync_reg_reg[1]_3 (u_io_addr_sync_n_120),
        .\SYNC[20].sync_reg_reg[1]_4 (u_io_addr_sync_n_121),
        .\SYNC[20].sync_reg_reg[1]_5 (u_io_addr_sync_n_122),
        .\SYNC[20].sync_reg_reg[1]_6 (u_io_addr_sync_n_123),
        .\SYNC[20].sync_reg_reg[1]_7 (u_io_addr_sync_n_125),
        .\SYNC[21].sync_reg_reg[1]_0 (u_io_addr_sync_n_66),
        .\SYNC[21].sync_reg_reg[1]_1 (u_io_addr_sync_n_68),
        .\SYNC[21].sync_reg_reg[1]_2 (u_io_addr_sync_n_101),
        .\SYNC[21].sync_reg_reg[1]_3 (u_io_addr_sync_n_108),
        .\SYNC[22].sync_reg_reg[1]_0 (u_io_addr_sync_n_91),
        .\SYNC[23].sync_reg_reg[1]_0 ({io_address[23:20],io_address[18],io_address[15:0]}),
        .\SYNC[23].sync_reg_reg[1]_1 (u_io_addr_sync_n_55),
        .\SYNC[23].sync_reg_reg[1]_2 (u_io_addr_sync_n_93),
        .\SYNC[24].sync_reg_reg[1]_0 (u_io_addr_sync_n_39),
        .\SYNC[24].sync_reg_reg[1]_1 (u_io_addr_sync_n_40),
        .\SYNC[2].sync_reg_reg[1]_0 (u_io_addr_sync_n_30),
        .\SYNC[31].sync_reg_reg[0]_0 (io_address_riuclk),
        .\SYNC[31].sync_reg_reg[1]_0 (\SYNC[19].sync_reg_reg[1] ),
        .\SYNC[3].sync_reg_reg[1]_0 (u_io_addr_sync_n_52),
        .\SYNC[3].sync_reg_reg[1]_1 (u_io_addr_sync_n_53),
        .\SYNC[3].sync_reg_reg[1]_2 (u_io_addr_sync_n_104),
        .\SYNC[4].sync_reg_reg[1]_0 (u_io_addr_sync_n_34),
        .\SYNC[4].sync_reg_reg[1]_1 (u_io_addr_sync_n_35),
        .\SYNC[4].sync_reg_reg[1]_2 (u_io_addr_sync_n_42),
        .\SYNC[4].sync_reg_reg[1]_3 (u_io_addr_sync_n_43),
        .\SYNC[4].sync_reg_reg[1]_4 (u_io_addr_sync_n_65),
        .\SYNC[4].sync_reg_reg[1]_5 (u_io_addr_sync_n_92),
        .\SYNC[4].sync_reg_reg[1]_6 (u_io_addr_sync_n_110),
        .\SYNC[6].sync_reg_reg[1]_0 (u_io_addr_sync_n_36),
        .\SYNC[6].sync_reg_reg[1]_1 (u_io_addr_sync_n_37),
        .\SYNC[6].sync_reg_reg[1]_2 (u_io_addr_sync_n_38),
        .\SYNC[8].sync_reg_reg[1]_0 (u_io_addr_sync_n_24),
        .\SYNC[8].sync_reg_reg[1]_1 (u_io_addr_sync_n_31),
        .\SYNC[8].sync_reg_reg[1]_2 (u_io_addr_sync_n_118),
        .\SYNC[8].sync_reg_reg[1]_3 (u_io_addr_sync_n_119),
        .\SYNC[8].sync_reg_reg[1]_4 (u_io_addr_sync_n_124),
        .\SYNC[9].sync_reg_reg[1]_0 (u_io_addr_sync_n_23),
        .\SYNC[9].sync_reg_reg[1]_1 (u_io_addr_sync_n_95),
        .\SYNC[9].sync_reg_reg[1]_2 (u_io_addr_sync_n_99),
        .\SYNC[9].sync_reg_reg[1]_3 (u_io_addr_sync_n_106),
        .a_b_cmd_sel_start0(\u_ddr_cal/u_ddr_cal_addr_decode/a_b_cmd_sel_start0 ),
        .\addr_dec_to_mb_data[0]_i_21_0 (u_ddr_cal_top_n_1666),
        .\addr_dec_to_mb_data[0]_i_21_1 (bisc_complete),
        .\addr_dec_to_mb_data[0]_i_6_0 (u_ddr_cal_top_n_1906),
        .\addr_dec_to_mb_data[0]_i_6_1 (u_ddr_cal_top_n_1806),
        .\addr_dec_to_mb_data[0]_i_6_2 (u_ddr_cal_top_n_1886),
        .\addr_dec_to_mb_data[0]_i_6_3 (u_ddr_cal_top_n_1884),
        .\addr_dec_to_mb_data[10]_i_4_0 (u_ddr_cal_top_n_1811),
        .\addr_dec_to_mb_data[10]_i_4_1 (u_ddr_cal_top_n_1835),
        .\addr_dec_to_mb_data[11]_i_3_0 ({\u_ddr_cal/config_rd_data [11:8],\u_ddr_cal/config_rd_data [6:0]}),
        .\addr_dec_to_mb_data[11]_i_4_0 (u_ddr_cal_top_n_1808),
        .\addr_dec_to_mb_data[11]_i_4_1 (u_ddr_cal_top_n_1832),
        .\addr_dec_to_mb_data[12]_i_4_0 (u_ddr_cal_top_n_1813),
        .\addr_dec_to_mb_data[12]_i_4_1 (u_ddr_cal_top_n_1837),
        .\addr_dec_to_mb_data[13]_i_2_0 (u_ddr_cal_top_n_1810),
        .\addr_dec_to_mb_data[13]_i_2_1 (u_ddr_cal_top_n_1834),
        .\addr_dec_to_mb_data[16]_i_2_0 (u_ddr_cal_top_n_1819),
        .\addr_dec_to_mb_data[16]_i_2_1 (u_ddr_cal_top_n_1842),
        .\addr_dec_to_mb_data[17]_i_2_0 (u_ddr_cal_top_n_1816),
        .\addr_dec_to_mb_data[17]_i_2_1 (u_ddr_cal_top_n_1839),
        .\addr_dec_to_mb_data[18]_i_2_0 (u_ddr_cal_top_n_1818),
        .\addr_dec_to_mb_data[18]_i_2_1 (u_ddr_cal_top_n_1841),
        .\addr_dec_to_mb_data[19]_i_2_0 (u_ddr_cal_top_n_1815),
        .\addr_dec_to_mb_data[19]_i_2_1 (u_ddr_cal_top_n_1838),
        .\addr_dec_to_mb_data[1]_i_2_0 (u_ddr_cal_top_n_1797),
        .\addr_dec_to_mb_data[1]_i_3_0 (u_ddr_cal_top_n_1963),
        .\addr_dec_to_mb_data[1]_i_5_0 (u_ddr_cal_top_n_1828),
        .\addr_dec_to_mb_data[1]_i_5_1 (u_ddr_cal_top_n_1803),
        .\addr_dec_to_mb_data[20]_i_2_0 (u_ddr_cal_top_n_1843),
        .\addr_dec_to_mb_data[20]_i_2_1 (u_ddr_cal_top_n_1817),
        .\addr_dec_to_mb_data[21]_i_2_0 (u_ddr_cal_top_n_1814),
        .\addr_dec_to_mb_data[21]_i_2_1 (u_ddr_cal_top_n_1840),
        .\addr_dec_to_mb_data[22]_i_3_0 (u_ddr_cal_top_n_1854),
        .\addr_dec_to_mb_data[24]_i_2_0 (u_ddr_cal_top_n_1848),
        .\addr_dec_to_mb_data[24]_i_2_1 (u_ddr_cal_top_n_1824),
        .\addr_dec_to_mb_data[25]_i_2_0 (u_ddr_cal_top_n_1845),
        .\addr_dec_to_mb_data[25]_i_2_1 (u_ddr_cal_top_n_1821),
        .\addr_dec_to_mb_data[26]_i_2_0 (u_ddr_cal_top_n_1847),
        .\addr_dec_to_mb_data[26]_i_2_1 (u_ddr_cal_top_n_1823),
        .\addr_dec_to_mb_data[27]_i_2_0 (u_ddr_cal_top_n_1844),
        .\addr_dec_to_mb_data[27]_i_2_1 (u_ddr_cal_top_n_1820),
        .\addr_dec_to_mb_data[28]_i_2_0 (u_ddr_cal_top_n_1825),
        .\addr_dec_to_mb_data[28]_i_2_1 (u_ddr_cal_top_n_1849),
        .\addr_dec_to_mb_data[29]_i_2_0 (u_ddr_cal_top_n_1822),
        .\addr_dec_to_mb_data[29]_i_2_1 (u_ddr_cal_top_n_1846),
        .\addr_dec_to_mb_data[2]_i_11_0 (u_ddr_cal_top_n_1881),
        .\addr_dec_to_mb_data[2]_i_4_0 (u_ddr_cal_top_n_1964),
        .\addr_dec_to_mb_data[2]_i_4_1 (u_ddr_cal_top_n_1880),
        .\addr_dec_to_mb_data[2]_i_6_0 (u_ddr_cal_top_n_1829),
        .\addr_dec_to_mb_data[2]_i_6_1 (u_ddr_cal_top_n_1805),
        .\addr_dec_to_mb_data[2]_i_6_2 ({u_ddr_cal_top_n_1901,u_ddr_cal_top_n_1902}),
        .\addr_dec_to_mb_data[30]_i_6_0 ({u_ddr_cal_top_n_1727,u_ddr_cal_top_n_1728,u_ddr_cal_top_n_1729,u_ddr_cal_top_n_1730,u_ddr_cal_top_n_1731,\u_ddr_cal/ub_cal_RESET_n [7:5],\u_ddr_cal/ub_cal_RESET_n [3:1]}),
        .\addr_dec_to_mb_data[30]_i_6_1 ({u_ddr_cal_top_n_1753,u_ddr_cal_top_n_1754,u_ddr_cal_top_n_1755,u_ddr_cal_top_n_1756,u_ddr_cal_top_n_1757,u_ddr_cal_top_n_1758,u_ddr_cal_top_n_1759,u_ddr_cal_top_n_1760,u_ddr_cal_top_n_1761,u_ddr_cal_top_n_1762,u_ddr_cal_top_n_1763,u_ddr_cal_top_n_1764,u_ddr_cal_top_n_1765}),
        .\addr_dec_to_mb_data[30]_i_6_2 ({u_ddr_cal_top_n_1766,u_ddr_cal_top_n_1767,u_ddr_cal_top_n_1768,u_ddr_cal_top_n_1769,u_ddr_cal_top_n_1770,u_ddr_cal_top_n_1771,u_ddr_cal_top_n_1772,u_ddr_cal_top_n_1773,u_ddr_cal_top_n_1774,u_ddr_cal_top_n_1775,u_ddr_cal_top_n_1776,u_ddr_cal_top_n_1777}),
        .\addr_dec_to_mb_data[31]_i_3_0 ({u_ddr_cal_top_n_1621,u_ddr_cal_top_n_1622,u_ddr_cal_top_n_1623,u_ddr_cal_top_n_1624,u_ddr_cal_top_n_1625,u_ddr_cal_top_n_1626,u_ddr_cal_top_n_1627,u_ddr_cal_top_n_1628,u_ddr_cal_top_n_1629,u_ddr_cal_top_n_1630,u_ddr_cal_top_n_1631,u_ddr_cal_top_n_1632,u_ddr_cal_top_n_1633,u_ddr_cal_top_n_1634,u_ddr_cal_top_n_1635,u_ddr_cal_top_n_1636,u_ddr_cal_top_n_1637,u_ddr_cal_top_n_1638,u_ddr_cal_top_n_1639,u_ddr_cal_top_n_1640,u_ddr_cal_top_n_1641,u_ddr_cal_top_n_1642,u_ddr_cal_top_n_1643,u_ddr_cal_top_n_1644,u_ddr_cal_top_n_1645,u_ddr_cal_top_n_1646,u_ddr_cal_top_n_1647,u_ddr_cal_top_n_1648,u_ddr_cal_top_n_1649,u_ddr_cal_top_n_1650,u_ddr_cal_top_n_1651,u_ddr_cal_top_n_1652}),
        .\addr_dec_to_mb_data[31]_i_9_0 ({\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log74 [31:20],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log74 [18:16],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log74 [13],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log74 [11:1],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log30 [31:20],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log30 [18:16],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log30 [13],\u_ddr_cal/u_ddr_cal_addr_decode/cplx_err_log30 [11:1]}),
        .\addr_dec_to_mb_data[3]_i_10_0 (u_ddr_cal_top_n_1802),
        .\addr_dec_to_mb_data[3]_i_10_1 (u_ddr_cal_top_n_1827),
        .\addr_dec_to_mb_data[3]_i_13_0 (u_ddr_cal_top_n_1965),
        .\addr_dec_to_mb_data[3]_i_3_0 (u_ddr_cal_top_n_1879),
        .\addr_dec_to_mb_data[4]_i_10_0 (u_ddr_cal_top_n_1878),
        .\addr_dec_to_mb_data[4]_i_11_0 (u_ddr_cal_top_n_1875),
        .\addr_dec_to_mb_data[4]_i_3_0 (u_ddr_cal_top_n_1877),
        .\addr_dec_to_mb_data[4]_i_3_1 (u_ddr_cal_top_n_1807),
        .\addr_dec_to_mb_data[4]_i_3_2 (u_ddr_cal_top_n_1831),
        .\addr_dec_to_mb_data[4]_i_3_3 (u_ddr_cal_top_n_1798),
        .\addr_dec_to_mb_data[5]_i_2_0 (u_ddr_cal_top_n_1887),
        .\addr_dec_to_mb_data[5]_i_2_1 (u_ddr_cal_top_n_1804),
        .\addr_dec_to_mb_data[5]_i_2_2 (u_ddr_cal_top_n_1826),
        .\addr_dec_to_mb_data[5]_i_6_0 ({u_ddr_cal_top_n_1748,u_ddr_cal_top_n_1749,u_ddr_cal_top_n_1750,u_ddr_cal_top_n_1751,u_ddr_cal_top_n_1752}),
        .\addr_dec_to_mb_data[5]_i_6_1 ({u_ddr_cal_top_n_1743,u_ddr_cal_top_n_1744,u_ddr_cal_top_n_1745,u_ddr_cal_top_n_1746,u_ddr_cal_top_n_1747}),
        .\addr_dec_to_mb_data[6]_i_4_0 (u_ddr_cal_top_n_1966),
        .\addr_dec_to_mb_data[7]_i_15_0 ({u_ddr_cal_top_n_1613,u_ddr_cal_top_n_1614,u_ddr_cal_top_n_1615,u_ddr_cal_top_n_1616,u_ddr_cal_top_n_1617,u_ddr_cal_top_n_1618,u_ddr_cal_top_n_1619,u_ddr_cal_top_n_1620}),
        .\addr_dec_to_mb_data[7]_i_5_0 ({\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1 [7:6],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DMIn_bit_r1 [4:0]}),
        .\addr_dec_to_mb_data[8]_i_4_0 (u_ddr_cal_top_n_1812),
        .\addr_dec_to_mb_data[8]_i_4_1 (u_ddr_cal_top_n_1836),
        .\addr_dec_to_mb_data[8]_i_8_0 (u_ddr_cal_top_n_1800),
        .\addr_dec_to_mb_data[9]_i_3_0 (u_ddr_cal_top_n_1809),
        .\addr_dec_to_mb_data[9]_i_3_1 (u_ddr_cal_top_n_1833),
        .\addr_dec_to_mb_data[9]_i_4_0 (u_ddr_cal_top_n_1796),
        .\addr_dec_to_mb_data_reg[0] (u_ddr_cal_top_n_1665),
        .\addr_dec_to_mb_data_reg[0]_0 (u_ddr_cal_top_n_1883),
        .\addr_dec_to_mb_data_reg[0]_1 (u_ddr_cal_top_n_1726),
        .\addr_dec_to_mb_data_reg[10] (u_ddr_cal_top_n_1863),
        .\addr_dec_to_mb_data_reg[10]_0 (u_ddr_cal_top_n_1795),
        .\addr_dec_to_mb_data_reg[11] (u_ddr_cal_top_n_1862),
        .\addr_dec_to_mb_data_reg[11]_0 (u_ddr_cal_top_n_1794),
        .\addr_dec_to_mb_data_reg[12] (u_ddr_cal_top_n_1723),
        .\addr_dec_to_mb_data_reg[12]_0 (u_ddr_cal_top_n_1861),
        .\addr_dec_to_mb_data_reg[12]_1 (u_ddr_cal_top_n_1724),
        .\addr_dec_to_mb_data_reg[13] (u_ddr_cal_top_n_1860),
        .\addr_dec_to_mb_data_reg[13]_0 (u_ddr_cal_top_n_1793),
        .\addr_dec_to_mb_data_reg[14] (u_ddr_cal_top_n_1778),
        .\addr_dec_to_mb_data_reg[14]_0 (u_ddr_cal_top_n_1667),
        .\addr_dec_to_mb_data_reg[15] (u_ddr_cal_top_n_1722),
        .\addr_dec_to_mb_data_reg[15]_0 (u_ddr_cal_top_n_1779),
        .\addr_dec_to_mb_data_reg[15]_1 (u_ddr_cal_top_n_1792),
        .\addr_dec_to_mb_data_reg[16] ({\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [48],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [41:40],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [37],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [34],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [16],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [9:8],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [5],\u_ddr_cal/u_ddr_cal_addr_decode/mcal_DQIn_byte_r1 [2]}),
        .\addr_dec_to_mb_data_reg[16]_0 (u_ddr_cal_top_n_1903),
        .\addr_dec_to_mb_data_reg[16]_1 (u_ddr_cal_top_n_1791),
        .\addr_dec_to_mb_data_reg[17] (u_ddr_cal_top_n_1859),
        .\addr_dec_to_mb_data_reg[17]_0 (u_ddr_cal_top_n_1790),
        .\addr_dec_to_mb_data_reg[18] (u_ddr_cal_top_n_1858),
        .\addr_dec_to_mb_data_reg[18]_0 (u_ddr_cal_top_n_1789),
        .\addr_dec_to_mb_data_reg[19] (u_ddr_cal_top_n_1725),
        .\addr_dec_to_mb_data_reg[19]_0 (u_ddr_cal_top_n_1857),
        .\addr_dec_to_mb_data_reg[19]_1 (u_ddr_cal_top_n_1788),
        .\addr_dec_to_mb_data_reg[1] (u_ddr_cal_top_n_1882),
        .\addr_dec_to_mb_data_reg[20] (u_ddr_cal_top_n_1856),
        .\addr_dec_to_mb_data_reg[20]_0 (u_ddr_cal_top_n_1787),
        .\addr_dec_to_mb_data_reg[21] (u_ddr_cal_top_n_1786),
        .\addr_dec_to_mb_data_reg[21]_0 (u_ddr_cal_top_n_1742),
        .\addr_dec_to_mb_data_reg[22] (u_ddr_cal_top_n_1855),
        .\addr_dec_to_mb_data_reg[23] (u_ddr_cal_top_n_1853),
        .\addr_dec_to_mb_data_reg[24] (u_ddr_cal_top_n_1785),
        .\addr_dec_to_mb_data_reg[24]_0 (u_ddr_cal_top_n_1741),
        .\addr_dec_to_mb_data_reg[25] (u_ddr_cal_top_n_1784),
        .\addr_dec_to_mb_data_reg[25]_0 (u_ddr_cal_top_n_1740),
        .\addr_dec_to_mb_data_reg[26] (u_ddr_cal_top_n_1852),
        .\addr_dec_to_mb_data_reg[26]_0 (u_ddr_cal_top_n_1783),
        .\addr_dec_to_mb_data_reg[27] (u_ddr_cal_top_n_1851),
        .\addr_dec_to_mb_data_reg[27]_0 (u_ddr_cal_top_n_1782),
        .\addr_dec_to_mb_data_reg[28] (u_ddr_cal_top_n_1739),
        .\addr_dec_to_mb_data_reg[29] (u_ddr_cal_top_n_1781),
        .\addr_dec_to_mb_data_reg[29]_0 (u_ddr_cal_top_n_1738),
        .\addr_dec_to_mb_data_reg[2] (phy_ready),
        .\addr_dec_to_mb_data_reg[30] (u_ddr_cal_top_n_1850),
        .\addr_dec_to_mb_data_reg[31] (u_ddr_cal_top_n_1780),
        .\addr_dec_to_mb_data_reg[31]_0 (u_ddr_cal_top_n_1801),
        .\addr_dec_to_mb_data_reg[3] (u_ddr_cal_top_n_1905),
        .\addr_dec_to_mb_data_reg[4] (u_ddr_cal_top_n_1876),
        .\addr_dec_to_mb_data_reg[4]_0 (u_ddr_cal_top_n_1874),
        .\addr_dec_to_mb_data_reg[5] (u_ddr_cal_top_n_1866),
        .\addr_dec_to_mb_data_reg[5]_0 (u_ddr_cal_top_n_1904),
        .\addr_dec_to_mb_data_reg[6] (u_ddr_cal_top_n_1653),
        .\addr_dec_to_mb_data_reg[7] (u_ddr_cal_top_n_1664),
        .\addr_dec_to_mb_data_reg[8] (u_ddr_cal_top_n_1865),
        .\addr_dec_to_mb_data_reg[9] (u_ddr_cal_top_n_1864),
        .\cal_DQOut_post_reg[31] (u_ddr_cal_top_n_1612),
        .\cal_cs_pos_reg[1] (u_ddr_cal_top_n_1899),
        .cal_oe_dis_low(cal_oe_dis_low),
        .cal_oe_dis_upp(cal_oe_dis_upp),
        .cal_timer_reg({\u_ddr_cal/u_ddr_cal_addr_decode/cal_timer_reg [31:30],\u_ddr_cal/u_ddr_cal_addr_decode/cal_timer_reg [27:26],\u_ddr_cal/u_ddr_cal_addr_decode/cal_timer_reg [23:22],\u_ddr_cal/u_ddr_cal_addr_decode/cal_timer_reg [20:0]}),
        .\cal_timer_reg[30] (u_io_addr_sync_n_126),
        .\cal_timer_reg[31] ({\u_ddr_cal/u_ddr_cal_addr_decode/addr_dec_to_mb_data [31],\u_ddr_cal/u_ddr_cal_addr_decode/addr_dec_to_mb_data [19:0]}),
        .cal_timer_reg_22_sp_1(u_io_addr_sync_n_128),
        .cal_timer_reg_23_sp_1(u_io_addr_sync_n_127),
        .clear_gt_data_ready_flag(\u_ddr_cal/u_ddr_cal_addr_decode/clear_gt_data_ready_flag ),
        .cnt_clr(\u_ddr_cal/u_ddr_cal_addr_decode/cnt_clr ),
        .cnt_clr_access(\u_ddr_cal/u_ddr_cal_addr_decode/cnt_clr_access ),
        .cnt_clr_reg(u_io_addr_sync_n_111),
        .cplx_status(\u_ddr_cal/u_ddr_cal_addr_decode/p_1_in ),
        .douta(\u_ddr_cal/bramA_do ),
        .ena(\u_ddr_cal/ub_xsdb_rd_en ),
        .gt_data_ready_flag(\u_ddr_cal/u_ddr_cal_addr_decode/gt_data_ready_flag ),
        .initDone(\u_ddr_cal/initDone ),
        .io_addr_strobe(io_addr_strobe),
        .io_addr_strobe_reg(u_io_addr_sync_n_56),
        .io_addr_strobe_reg_0(u_io_addr_sync_n_115),
        .io_write_data({io_write_data[4],io_write_data[0]}),
        .lrdimm_cmp_clr(\u_ddr_cal/u_ddr_cal_addr_decode/lrdimm_cmp_clr ),
        .lrdimm_cmp_en(\u_ddr_cal/u_ddr_cal_addr_decode/lrdimm_cmp_en ),
        .out(io_write_strobe),
        .p_52_in(\u_ddr_cal/u_ddr_cal_addr_decode/p_52_in ),
        .phy2clb_rd_dq_bits(phy2clb_rd_dq_bits),
        .rd_vref_value0_out({\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [55],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [48],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [41],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [34],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [27],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [20],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [13],\u_ddr_cal/u_ddr_cal_addr_decode/rd_vref_value0_out [6]}),
        .riu2clb_valid(riu2clb_valid),
        .rst_r1_reg(u_io_addr_sync_n_41),
        .rst_r1_reg_0(\u_ddr_cal/u_ddr_cal_addr_decode/cal_ACT_n_A ),
        .rst_r1_reg_1(u_io_addr_sync_n_117),
        .stop_gate_tracking_ack_reg(u_ddr_cal_top_n_796),
        .ub_calDone(\u_ddr_cal/ub_calDone ),
        .xsdb_wr_en_reg(u_ddr_cal_top_n_756));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized5 u_io_read_data_sync
       (.CLK(CLK),
        .\SYNC[31].sync_reg_reg[0]_0 (io_read_data),
        .io_read_data_riuclk(io_read_data_riuclk));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized6 u_io_ready_lvl_sync
       (.CLK(CLK),
        .D(io_ready_lvl),
        .out(io_ready_lvl_riuclk));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized8_1 u_io_write_data_sync
       (.O({u_io_write_data_sync_n_73,u_io_write_data_sync_n_74,u_io_write_data_sync_n_75,u_io_write_data_sync_n_76,u_io_write_data_sync_n_77,u_io_write_data_sync_n_78,u_io_write_data_sync_n_79,u_io_write_data_sync_n_80}),
        .S(u_ddr_cal_top_n_1900),
        .\SYNC[0].sync_reg_reg[1]_0 (u_io_write_data_sync_n_105),
        .\SYNC[13].sync_reg_reg[1]_0 ({\u_ddr_cal/u_ddr_cal_addr_decode/uppCL10 [47:42],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL10 [37:36],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL10 [33:32]}),
        .\SYNC[15].sync_reg_reg[1]_0 ({u_io_write_data_sync_n_81,u_io_write_data_sync_n_82,u_io_write_data_sync_n_83,u_io_write_data_sync_n_84,u_io_write_data_sync_n_85,u_io_write_data_sync_n_86,u_io_write_data_sync_n_87,u_io_write_data_sync_n_88}),
        .\SYNC[21].sync_reg_reg[1]_0 ({\u_ddr_cal/u_ddr_cal_addr_decode/uppCL20 [47:42],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL20 [37:36],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL20 [33:32]}),
        .\SYNC[23].sync_reg_reg[1]_0 ({u_io_write_data_sync_n_89,u_io_write_data_sync_n_90,u_io_write_data_sync_n_91,u_io_write_data_sync_n_92,u_io_write_data_sync_n_93,u_io_write_data_sync_n_94,u_io_write_data_sync_n_95,u_io_write_data_sync_n_96}),
        .\SYNC[29].sync_reg_reg[1]_0 ({\u_ddr_cal/u_ddr_cal_addr_decode/uppCL30 [47:42],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL30 [37:36],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL30 [33:32]}),
        .\SYNC[30].sync_reg_reg[1]_0 (\SYNC[19].sync_reg_reg[1] ),
        .\SYNC[31].sync_reg_reg[0]_0 (io_write_data_riuclk),
        .\SYNC[31].sync_reg_reg[1]_0 ({u_io_write_data_sync_n_97,u_io_write_data_sync_n_98,u_io_write_data_sync_n_99,u_io_write_data_sync_n_100,u_io_write_data_sync_n_101,u_io_write_data_sync_n_102,u_io_write_data_sync_n_103,u_io_write_data_sync_n_104}),
        .\SYNC[5].sync_reg_reg[1]_0 ({\u_ddr_cal/u_ddr_cal_addr_decode/uppCL00 [47:42],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL00 [37:36],\u_ddr_cal/u_ddr_cal_addr_decode/uppCL00 [33:32]}),
        .a_b_cmd_sel_start(\u_ddr_cal/u_ddr_cal_addr_decode/a_b_cmd_sel_start ),
        .a_b_cmd_sel_start0(\u_ddr_cal/u_ddr_cal_addr_decode/a_b_cmd_sel_start0 ),
        .cal_seq_cnt_gt_0_reg(u_ddr_cal_top_n_1799),
        .cal_timer_reg(\u_ddr_cal/u_ddr_cal_addr_decode/cal_timer_reg ),
        .cal_timer_reg_31_sp_1(u_io_addr_sync_n_53),
        .cnt_clr(\u_ddr_cal/u_ddr_cal_addr_decode/cnt_clr ),
        .cnt_clr_reg(u_io_write_data_sync_n_32),
        .io_write_data(io_write_data),
        .\uppCL0_reg[32] (u_ddr_cal_top_n_1829),
        .\uppCL0_reg[33] (u_ddr_cal_top_n_1827),
        .\uppCL0_reg[36] (u_ddr_cal_top_n_1830),
        .\uppCL0_reg[37] (u_ddr_cal_top_n_1828),
        .\uppCL0_reg[46] (u_ddr_cal_top_n_1831),
        .\uppCL0_reg[47] (u_ddr_cal_top_n_1826),
        .\uppCL1_reg[32] (u_ddr_cal_top_n_1835),
        .\uppCL1_reg[33] (u_ddr_cal_top_n_1832),
        .\uppCL1_reg[36] (u_ddr_cal_top_n_1836),
        .\uppCL1_reg[37] (u_ddr_cal_top_n_1833),
        .\uppCL1_reg[46] (u_ddr_cal_top_n_1837),
        .\uppCL1_reg[47] (u_ddr_cal_top_n_1834),
        .\uppCL2_reg[32] (u_ddr_cal_top_n_1841),
        .\uppCL2_reg[33] (u_ddr_cal_top_n_1838),
        .\uppCL2_reg[36] (u_ddr_cal_top_n_1842),
        .\uppCL2_reg[37] (u_ddr_cal_top_n_1839),
        .\uppCL2_reg[46] (u_ddr_cal_top_n_1843),
        .\uppCL2_reg[47] (u_ddr_cal_top_n_1840),
        .\uppCL3_reg[32] (u_ddr_cal_top_n_1847),
        .\uppCL3_reg[33] (u_ddr_cal_top_n_1844),
        .\uppCL3_reg[36] (u_ddr_cal_top_n_1848),
        .\uppCL3_reg[37] (u_ddr_cal_top_n_1845),
        .\uppCL3_reg[44] (io_address[1:0]),
        .\uppCL3_reg[46] (u_ddr_cal_top_n_1849),
        .\uppCL3_reg[47] (u_ddr_cal_top_n_1846));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized9_2 u_io_write_strobe_sync
       (.D(io_write_strobe_riuclk),
        .\SYNC[0].sync_reg_reg[0]_0 (\SYNC[19].sync_reg_reg[1] ),
        .io_addr_strobe(io_addr_strobe),
        .out(io_write_strobe),
        .p_52_in(\u_ddr_cal/u_ddr_cal_addr_decode/p_52_in ));
  (* CHECK_LICENSE_TYPE = "phy1,dummy_model,{}" *) 
  (* DowngradeIPIdentifiedWarnings = "yes" *) 
  (* PROBE_PROHIBIT = "TRUE" *) 
  ddr4_0_phy u_mig_ddr4_phy
       (.bisc_byte(bisc_byte),
        .bisc_complete_riuclk(bisc_complete_riuclk),
        .cal_RESET_n(cal_RESET_n),
        .ch0_mcal_DMOut_n(ch0_mcal_DMOut_n),
        .ch0_mcal_DQOut(ch0_mcal_DQOut),
        .ch0_mcal_DQSOut({1'b0,1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden),
        .ch0_mcal_clb2phy_odt_low({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch0_mcal_clb2phy_odt_upp({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch0_mcal_clb2phy_rdcs0_low({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch0_mcal_clb2phy_rdcs0_upp({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch0_mcal_clb2phy_rdcs1_low({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch0_mcal_clb2phy_rdcs1_upp({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .ch0_mcal_clb2phy_t_b_low({ch0_mcal_clb2phy_t_b_low,ch0_mcal_clb2phy_t_b_low,ch0_mcal_clb2phy_t_b_low,ch0_mcal_clb2phy_t_b_low,ch0_mcal_clb2phy_t_b_low,ch0_mcal_clb2phy_t_b_low,ch0_mcal_clb2phy_t_b_low,ch0_mcal_clb2phy_t_b_low}),
        .ch0_mcal_clb2phy_t_b_upp({ch0_mcal_clb2phy_t_b_upp,ch0_mcal_clb2phy_t_b_upp,ch0_mcal_clb2phy_t_b_upp,ch0_mcal_clb2phy_t_b_upp,ch0_mcal_clb2phy_t_b_upp,ch0_mcal_clb2phy_t_b_upp,ch0_mcal_clb2phy_t_b_upp,ch0_mcal_clb2phy_t_b_upp}),
        .ch0_mcal_clb2phy_wrcs0_low({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch0_mcal_clb2phy_wrcs0_upp({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch0_mcal_clb2phy_wrcs1_low({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch0_mcal_clb2phy_wrcs1_upp({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_DMOut_n({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_DQOut({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_DQSOut({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_fifo_rden(ch1_mcal_clb2phy_fifo_rden),
        .ch1_mcal_clb2phy_odt_low({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_odt_upp({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_rdcs0_low({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_rdcs0_upp({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_rdcs1_low({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_rdcs1_upp({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_rden_low({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_rden_upp({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_t_b_low({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_t_b_upp({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_wrcs0_low({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_wrcs0_upp({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_wrcs1_low({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ch1_mcal_clb2phy_wrcs1_upp({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .dbg_bus(dbg_bus),
        .ddr4_act_n(c0_ddr4_act_n),
        .ddr4_adr(c0_ddr4_adr),
        .ddr4_ba(c0_ddr4_ba),
        .ddr4_bg(c0_ddr4_bg),
        .ddr4_c(u_mig_ddr4_phy_n_24),
        .ddr4_ck_c(c0_ddr4_ck_c),
        .ddr4_ck_t(c0_ddr4_ck_t),
        .ddr4_cke(c0_ddr4_cke),
        .ddr4_cs_n(c0_ddr4_cs_n),
        .ddr4_dm_dbi_n(c0_ddr4_dm_dbi_n),
        .ddr4_dq(c0_ddr4_dq),
        .ddr4_dqs_c(c0_ddr4_dqs_c),
        .ddr4_dqs_t(c0_ddr4_dqs_t),
        .ddr4_odt(c0_ddr4_odt),
        .ddr4_reset_n(c0_ddr4_reset_n),
        .div_clk(\SYNC[19].sync_reg_reg[1] ),
        .div_clk_rst(SR),
        .en_vtc_riuclk(en_vtc_riuclk),
        .io_addr_strobe_clb2riu_riuclk(io_addr_strobe_clb2riu_riuclk),
        .io_address_riuclk(io_address_riuclk),
        .io_write_data_riuclk(io_write_data_riuclk),
        .io_write_strobe_riuclk(io_write_strobe_riuclk),
        .mcal_ACT_n(mcal_ACT_n),
        .mcal_ADR({mcal_ADR[135:110],mcal_ADR[110],mcal_ADR[108],mcal_ADR[108],mcal_ADR[110],mcal_ADR[110],mcal_ADR[104:102],mcal_ADR[102],mcal_ADR[100],mcal_ADR[100],mcal_ADR[102],mcal_ADR[102],mcal_ADR[96:94],mcal_ADR[94],mcal_ADR[92],mcal_ADR[92],mcal_ADR[94],mcal_ADR[94],mcal_ADR[88:86],mcal_ADR[86],mcal_ADR[84],mcal_ADR[84],mcal_ADR[82],mcal_ADR[82],mcal_ADR[80:78],mcal_ADR[78],mcal_ADR[76],mcal_ADR[76],mcal_ADR[74],mcal_ADR[74],mcal_ADR[72:70],mcal_ADR[70],mcal_ADR[68],mcal_ADR[68],mcal_ADR[66],mcal_ADR[66],mcal_ADR[64:62],mcal_ADR[62],mcal_ADR[60],mcal_ADR[60],mcal_ADR[58],mcal_ADR[58],mcal_ADR[56:54],mcal_ADR[54],mcal_ADR[52],mcal_ADR[52],mcal_ADR[50],mcal_ADR[50],mcal_ADR[48:46],mcal_ADR[46],mcal_ADR[44],mcal_ADR[44],mcal_ADR[42],mcal_ADR[42],mcal_ADR[40:38],mcal_ADR[38],mcal_ADR[36],mcal_ADR[36],mcal_ADR[34],mcal_ADR[34],mcal_ADR[32:30],mcal_ADR[30],mcal_ADR[28],mcal_ADR[28],mcal_ADR[26],mcal_ADR[26],mcal_ADR[24:22],mcal_ADR[22],mcal_ADR[20],mcal_ADR[20],mcal_ADR[22],mcal_ADR[22],mcal_ADR[16:14],mcal_ADR[14],mcal_ADR[12],mcal_ADR[12],mcal_ADR[14],mcal_ADR[14],mcal_ADR[8:6],mcal_ADR[6],mcal_ADR[4],mcal_ADR[4],mcal_ADR[2],mcal_ADR[2],mcal_ADR[0]}),
        .mcal_BA({mcal_BA[15:14],mcal_BA[14],mcal_BA[12],mcal_BA[12],mcal_BA[10],mcal_BA[10],mcal_BA[8:6],mcal_BA[6],mcal_BA[4],mcal_BA[4],mcal_BA[2],mcal_BA[2],mcal_BA[0]}),
        .mcal_BG({mcal_BG[7:6],mcal_BG[6],mcal_BG[4],mcal_BG[4],mcal_BG[2],mcal_BG[2],mcal_BG[0]}),
        .mcal_C({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .mcal_CAS_n({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .mcal_CKE({dbg_out_phy[23:22],dbg_out_phy[22],dbg_out_phy[22],dbg_out_phy[22],dbg_out_phy[22],dbg_out_phy[22],dbg_out_phy[16]}),
        .mcal_CK_c({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1,1'b0}),
        .mcal_CK_t({1'b0,1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
        .mcal_CS_n(mcal_CS_n),
        .mcal_DMIn_n(mcal_DMIn_n),
        .mcal_DQIn(mcal_DQIn),
        .mcal_ODT({mcal_ODT[7:6],mcal_ODT[6],mcal_ODT[4],mcal_ODT[4],mcal_ODT[2],mcal_ODT[2],mcal_ODT[0]}),
        .mcal_PAR(mcal_PAR),
        .mcal_RAS_n({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .mcal_WE_n({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .mcal_rd_vref_value(mcal_rd_vref_value),
        .mmcm_clk_in(mmcm_clk_in),
        .mmcm_lock(mmcm_lock),
        .phy2clb_fixdly_rdy_low_riuclk(phy2clb_fixdly_rdy_low_riuclk),
        .phy2clb_fixdly_rdy_upp_riuclk(phy2clb_fixdly_rdy_upp_riuclk),
        .phy2clb_phy_rdy_low_riuclk(phy2clb_phy_rdy_low_riuclk),
        .phy2clb_phy_rdy_upp_riuclk(phy2clb_phy_rdy_upp_riuclk),
        .phy2clb_rd_dq_bits(phy2clb_rd_dq_bits),
        .phy_ready_riuclk(phy_ready_riuclk),
        .pllGate(pllGate),
        .pll_lock(pll_lock),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk),
        .riu2clb_vld_read_data(riu2clb_vld_read_data),
        .riu_addr_cal(riu_addr_cal),
        .riu_clk(CLK),
        .riu_clk_rst(riu_clk_rst),
        .riu_nibble_8(riu_nibble_8),
        .sys_clk_in(sys_clk_in),
        .sys_clk_n(c0_sys_clk_n),
        .sys_clk_p(c0_sys_clk_p),
        .ub_rst_out_riuclk(ub_rst_out_riuclk));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized4_3 u_phy2clb_bisc_complete_sync
       (.D(bisc_complete_riuclk),
        .\SYNC[0].sync_reg_reg[1]_0 (\SYNC[19].sync_reg_reg[1] ),
        .out(bisc_complete));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized7 u_phy2clb_fixdly_rdy_low
       (.\SYNC[19].sync_reg_reg[1]_0 (\SYNC[19].sync_reg_reg[1] ),
        .phy2clb_fixdly_rdy_low_riuclk(phy2clb_fixdly_rdy_low_riuclk));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized7_4 u_phy2clb_fixdly_rdy_upp
       (.\SYNC[19].sync_reg_reg[1]_0 (\SYNC[19].sync_reg_reg[1] ),
        .phy2clb_fixdly_rdy_upp_riuclk(phy2clb_fixdly_rdy_upp_riuclk));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized7_5 u_phy2clb_phy_rdy_low
       (.\SYNC[19].sync_reg_reg[1]_0 (\SYNC[19].sync_reg_reg[1] ),
        .phy2clb_phy_rdy_low_riuclk(phy2clb_phy_rdy_low_riuclk));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized7_6 u_phy2clb_phy_rdy_upp
       (.\SYNC[19].sync_reg_reg[1]_0 (\SYNC[19].sync_reg_reg[1] ),
        .phy2clb_phy_rdy_upp_riuclk(phy2clb_phy_rdy_upp_riuclk));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized4_7 u_phy2clb_phy_ready_sync
       (.D(phy_ready_riuclk),
        .\SYNC[0].sync_reg_reg[0]_0 (\SYNC[19].sync_reg_reg[1] ),
        .out(phy_ready));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized7_8 u_riu2clb_valid_sync
       (.\SYNC[19].sync_reg_reg[0]_0 (riu2clb_valid_r1_riuclk),
        .\SYNC[19].sync_reg_reg[1]_0 (\SYNC[19].sync_reg_reg[1] ),
        .riu2clb_valid(riu2clb_valid));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_iob" *) 
module ddr4_0_ddr4_phy_v2_2_0_iob
   (iob2phy_d_in_byte,
    \genBuf[1].genblk1.OBUF ,
    iob_pin,
    phy2iob_odt_out_byte,
    phy2iob_q_out_byte,
    phy2iob_t,
    mcal_rd_vref_value);
  output [79:0]iob2phy_d_in_byte;
  output [25:0]\genBuf[1].genblk1.OBUF ;
  inout [87:0]iob_pin;
  input [71:0]phy2iob_odt_out_byte;
  input [104:0]phy2iob_q_out_byte;
  input [79:0]phy2iob_t;
  input [55:0]mcal_rd_vref_value;

  wire [25:0]\genBuf[1].genblk1.OBUF ;
  wire [79:0]iob2phy_d_in_byte;
  wire [87:0]iob_pin;
  wire [55:0]mcal_rd_vref_value;
  wire [71:0]phy2iob_odt_out_byte;
  wire [104:0]phy2iob_q_out_byte;
  wire [79:0]phy2iob_t;

  ddr4_0_ddr4_phy_v2_2_0_iob_byte \genByte[0].u_ddr_iob_byte 
       (.\genBuf[1].genblk1.OBUF_0 (\genBuf[1].genblk1.OBUF [0]),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[9:0]),
        .iob_pin(iob_pin[10:0]),
        .mcal_rd_vref_value(mcal_rd_vref_value[6:0]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[8:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[10:0]),
        .phy2iob_t(phy2iob_t[9:0]));
  ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized0 \genByte[1].u_ddr_iob_byte 
       (.\genBuf[12].genblk1.OBUF_0 (\genBuf[1].genblk1.OBUF [11:1]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[20:11]));
  ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized1 \genByte[2].u_ddr_iob_byte 
       (.\genBuf[12].genblk1.OBUF_0 (\genBuf[1].genblk1.OBUF [24:12]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[33:21]));
  ddr4_0_ddr4_phy_v2_2_0_iob_byte_659 \genByte[3].u_ddr_iob_byte 
       (.\genBuf[1].genblk1.OBUF_0 (\genBuf[1].genblk1.OBUF [25]),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[19:10]),
        .iob_pin(iob_pin[21:11]),
        .mcal_rd_vref_value(mcal_rd_vref_value[13:7]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[17:9]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[44:34]),
        .phy2iob_t(phy2iob_t[19:10]));
  ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized2 \genByte[4].u_ddr_iob_byte 
       (.iob2phy_d_in_byte(iob2phy_d_in_byte[29:20]),
        .iob_pin(iob_pin[32:22]),
        .mcal_rd_vref_value(mcal_rd_vref_value[20:14]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[26:18]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[54:45]),
        .phy2iob_t(phy2iob_t[29:20]));
  ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized2_660 \genByte[5].u_ddr_iob_byte 
       (.iob2phy_d_in_byte(iob2phy_d_in_byte[39:30]),
        .iob_pin(iob_pin[43:33]),
        .mcal_rd_vref_value(mcal_rd_vref_value[27:21]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[35:27]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[64:55]),
        .phy2iob_t(phy2iob_t[39:30]));
  ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized2_661 \genByte[6].u_ddr_iob_byte 
       (.iob2phy_d_in_byte(iob2phy_d_in_byte[49:40]),
        .iob_pin(iob_pin[54:44]),
        .mcal_rd_vref_value(mcal_rd_vref_value[34:28]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[44:36]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[74:65]),
        .phy2iob_t(phy2iob_t[49:40]));
  ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized2_662 \genByte[7].u_ddr_iob_byte 
       (.iob2phy_d_in_byte(iob2phy_d_in_byte[59:50]),
        .iob_pin(iob_pin[65:55]),
        .mcal_rd_vref_value(mcal_rd_vref_value[41:35]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[53:45]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[84:75]),
        .phy2iob_t(phy2iob_t[59:50]));
  ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized2_663 \genByte[8].u_ddr_iob_byte 
       (.iob2phy_d_in_byte(iob2phy_d_in_byte[69:60]),
        .iob_pin(iob_pin[76:66]),
        .mcal_rd_vref_value(mcal_rd_vref_value[48:42]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[62:54]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[94:85]),
        .phy2iob_t(phy2iob_t[69:60]));
  ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized2_664 \genByte[9].u_ddr_iob_byte 
       (.iob2phy_d_in_byte(iob2phy_d_in_byte[79:70]),
        .iob_pin(iob_pin[87:77]),
        .mcal_rd_vref_value(mcal_rd_vref_value[55:49]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[71:63]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[104:95]),
        .phy2iob_t(phy2iob_t[79:70]));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_iob_byte" *) 
module ddr4_0_ddr4_phy_v2_2_0_iob_byte
   (iob2phy_d_in_byte,
    \genBuf[1].genblk1.OBUF_0 ,
    iob_pin,
    phy2iob_odt_out_byte,
    phy2iob_q_out_byte,
    phy2iob_t,
    mcal_rd_vref_value);
  output [9:0]iob2phy_d_in_byte;
  output [0:0]\genBuf[1].genblk1.OBUF_0 ;
  inout [10:0]iob_pin;
  input [8:0]phy2iob_odt_out_byte;
  input [10:0]phy2iob_q_out_byte;
  input [9:0]phy2iob_t;
  input [6:0]mcal_rd_vref_value;

  wire Vref;
  wire [0:0]\genBuf[1].genblk1.OBUF_0 ;
  wire [9:0]iob2phy_d_in_byte;
  wire [10:0]iob_pin;
  wire [6:0]mcal_rd_vref_value;
  wire [8:0]phy2iob_odt_out_byte;
  wire [10:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;

  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[0].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[0]),
        .I(phy2iob_q_out_byte[0]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[0]),
        .O(iob2phy_d_in_byte[0]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[0]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[10].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[7]),
        .I(phy2iob_q_out_byte[9]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[9]),
        .O(iob2phy_d_in_byte[8]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[8]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[11].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[8]),
        .I(phy2iob_q_out_byte[10]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[10]),
        .O(iob2phy_d_in_byte[9]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[9]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[1].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[1]),
        .O(\genBuf[1].genblk1.OBUF_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[2].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[1]),
        .I(phy2iob_q_out_byte[2]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[1]),
        .O(iob2phy_d_in_byte[1]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[1]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[3].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[2]),
        .I(phy2iob_q_out_byte[3]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[2]),
        .O(iob2phy_d_in_byte[2]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[2]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[4].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[3]),
        .I(phy2iob_q_out_byte[4]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[3]),
        .O(iob2phy_d_in_byte[3]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[3]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[5].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[4]),
        .I(phy2iob_q_out_byte[5]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[4]),
        .O(iob2phy_d_in_byte[4]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[4]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS #(
    .DIFF_TERM("FALSE"),
    .IOSTANDARD("DEFAULT")) 
    \genBuf[6].IO_BUFDS 
       (.I(phy2iob_q_out_byte[6]),
        .IO(iob_pin[5]),
        .IOB(iob_pin[6]),
        .O(iob2phy_d_in_byte[5]),
        .T(phy2iob_t[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[8].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[5]),
        .I(phy2iob_q_out_byte[7]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[7]),
        .O(iob2phy_d_in_byte[6]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[6]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[9].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[6]),
        .I(phy2iob_q_out_byte[8]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[8]),
        .O(iob2phy_d_in_byte[7]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[7]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  HPIO_VREF #(
    .VREF_CNTR("FABRIC_RANGE1")) 
    \genVref.u_hpio_vref 
       (.FABRIC_VREF_TUNE(mcal_rd_vref_value),
        .VREF(Vref));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_iob_byte" *) 
module ddr4_0_ddr4_phy_v2_2_0_iob_byte_659
   (iob2phy_d_in_byte,
    \genBuf[1].genblk1.OBUF_0 ,
    iob_pin,
    phy2iob_odt_out_byte,
    phy2iob_q_out_byte,
    phy2iob_t,
    mcal_rd_vref_value);
  output [9:0]iob2phy_d_in_byte;
  output [0:0]\genBuf[1].genblk1.OBUF_0 ;
  inout [10:0]iob_pin;
  input [8:0]phy2iob_odt_out_byte;
  input [10:0]phy2iob_q_out_byte;
  input [9:0]phy2iob_t;
  input [6:0]mcal_rd_vref_value;

  wire Vref;
  wire [0:0]\genBuf[1].genblk1.OBUF_0 ;
  wire [9:0]iob2phy_d_in_byte;
  wire [10:0]iob_pin;
  wire [6:0]mcal_rd_vref_value;
  wire [8:0]phy2iob_odt_out_byte;
  wire [10:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;

  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[0].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[0]),
        .I(phy2iob_q_out_byte[0]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[0]),
        .O(iob2phy_d_in_byte[0]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[0]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[10].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[7]),
        .I(phy2iob_q_out_byte[9]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[9]),
        .O(iob2phy_d_in_byte[8]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[8]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[11].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[8]),
        .I(phy2iob_q_out_byte[10]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[10]),
        .O(iob2phy_d_in_byte[9]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[9]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[1].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[1]),
        .O(\genBuf[1].genblk1.OBUF_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[2].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[1]),
        .I(phy2iob_q_out_byte[2]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[1]),
        .O(iob2phy_d_in_byte[1]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[1]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[3].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[2]),
        .I(phy2iob_q_out_byte[3]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[2]),
        .O(iob2phy_d_in_byte[2]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[2]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[4].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[3]),
        .I(phy2iob_q_out_byte[4]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[3]),
        .O(iob2phy_d_in_byte[3]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[3]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[5].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[4]),
        .I(phy2iob_q_out_byte[5]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[4]),
        .O(iob2phy_d_in_byte[4]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[4]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS #(
    .DIFF_TERM("FALSE"),
    .IOSTANDARD("DEFAULT")) 
    \genBuf[6].IO_BUFDS 
       (.I(phy2iob_q_out_byte[6]),
        .IO(iob_pin[5]),
        .IOB(iob_pin[6]),
        .O(iob2phy_d_in_byte[5]),
        .T(phy2iob_t[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[8].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[5]),
        .I(phy2iob_q_out_byte[7]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[7]),
        .O(iob2phy_d_in_byte[6]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[6]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[9].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[6]),
        .I(phy2iob_q_out_byte[8]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[8]),
        .O(iob2phy_d_in_byte[7]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[7]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  HPIO_VREF #(
    .VREF_CNTR("FABRIC_RANGE1")) 
    \genVref.u_hpio_vref 
       (.FABRIC_VREF_TUNE(mcal_rd_vref_value),
        .VREF(Vref));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_iob_byte" *) 
module ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized0
   (\genBuf[12].genblk1.OBUF_0 ,
    phy2iob_q_out_byte);
  output [10:0]\genBuf[12].genblk1.OBUF_0 ;
  input [9:0]phy2iob_q_out_byte;

  wire [10:0]\genBuf[12].genblk1.OBUF_0 ;
  wire [9:0]phy2iob_q_out_byte;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[0].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[0]),
        .O(\genBuf[12].genblk1.OBUF_0 [0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[10].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[7]),
        .O(\genBuf[12].genblk1.OBUF_0 [8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[11].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[8]),
        .O(\genBuf[12].genblk1.OBUF_0 [9]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[12].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[9]),
        .O(\genBuf[12].genblk1.OBUF_0 [10]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[1].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[1]),
        .O(\genBuf[12].genblk1.OBUF_0 [1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[2].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[2]),
        .O(\genBuf[12].genblk1.OBUF_0 [2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[3].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[3]),
        .O(\genBuf[12].genblk1.OBUF_0 [3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[4].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[4]),
        .O(\genBuf[12].genblk1.OBUF_0 [4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[5].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[5]),
        .O(\genBuf[12].genblk1.OBUF_0 [5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  (* XILINX_LEGACY_PRIM = "OBUFDS" *) 
  OBUFDS #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[6].OBUFDS 
       (.I(phy2iob_q_out_byte[6]),
        .O(\genBuf[12].genblk1.OBUF_0 [6]),
        .OB(\genBuf[12].genblk1.OBUF_0 [7]));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_iob_byte" *) 
module ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized1
   (\genBuf[12].genblk1.OBUF_0 ,
    phy2iob_q_out_byte);
  output [12:0]\genBuf[12].genblk1.OBUF_0 ;
  input [12:0]phy2iob_q_out_byte;

  wire [12:0]\genBuf[12].genblk1.OBUF_0 ;
  wire [12:0]phy2iob_q_out_byte;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[0].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[0]),
        .O(\genBuf[12].genblk1.OBUF_0 [0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[10].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[10]),
        .O(\genBuf[12].genblk1.OBUF_0 [10]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[11].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[11]),
        .O(\genBuf[12].genblk1.OBUF_0 [11]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[12].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[12]),
        .O(\genBuf[12].genblk1.OBUF_0 [12]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[1].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[1]),
        .O(\genBuf[12].genblk1.OBUF_0 [1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[2].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[2]),
        .O(\genBuf[12].genblk1.OBUF_0 [2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[3].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[3]),
        .O(\genBuf[12].genblk1.OBUF_0 [3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[4].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[4]),
        .O(\genBuf[12].genblk1.OBUF_0 [4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[5].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[5]),
        .O(\genBuf[12].genblk1.OBUF_0 [5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[6].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[6]),
        .O(\genBuf[12].genblk1.OBUF_0 [6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[7].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[7]),
        .O(\genBuf[12].genblk1.OBUF_0 [7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[8].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[8]),
        .O(\genBuf[12].genblk1.OBUF_0 [8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \genBuf[9].genblk1.OBUF 
       (.I(phy2iob_q_out_byte[9]),
        .O(\genBuf[12].genblk1.OBUF_0 [9]));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_iob_byte" *) 
module ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized2
   (iob2phy_d_in_byte,
    iob_pin,
    phy2iob_odt_out_byte,
    phy2iob_q_out_byte,
    phy2iob_t,
    mcal_rd_vref_value);
  output [9:0]iob2phy_d_in_byte;
  inout [10:0]iob_pin;
  input [8:0]phy2iob_odt_out_byte;
  input [9:0]phy2iob_q_out_byte;
  input [9:0]phy2iob_t;
  input [6:0]mcal_rd_vref_value;

  wire Vref;
  wire [9:0]iob2phy_d_in_byte;
  wire [10:0]iob_pin;
  wire [6:0]mcal_rd_vref_value;
  wire [8:0]phy2iob_odt_out_byte;
  wire [9:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;

  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[0].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[0]),
        .I(phy2iob_q_out_byte[0]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[0]),
        .O(iob2phy_d_in_byte[0]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[0]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[10].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[7]),
        .I(phy2iob_q_out_byte[8]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[9]),
        .O(iob2phy_d_in_byte[8]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[8]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[11].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[8]),
        .I(phy2iob_q_out_byte[9]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[10]),
        .O(iob2phy_d_in_byte[9]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[9]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[2].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[1]),
        .I(phy2iob_q_out_byte[1]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[1]),
        .O(iob2phy_d_in_byte[1]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[1]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[3].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[2]),
        .I(phy2iob_q_out_byte[2]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[2]),
        .O(iob2phy_d_in_byte[2]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[2]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[4].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[3]),
        .I(phy2iob_q_out_byte[3]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[3]),
        .O(iob2phy_d_in_byte[3]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[3]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[5].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[4]),
        .I(phy2iob_q_out_byte[4]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[4]),
        .O(iob2phy_d_in_byte[4]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[4]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS #(
    .DIFF_TERM("FALSE"),
    .IOSTANDARD("DEFAULT")) 
    \genBuf[6].IO_BUFDS 
       (.I(phy2iob_q_out_byte[5]),
        .IO(iob_pin[5]),
        .IOB(iob_pin[6]),
        .O(iob2phy_d_in_byte[5]),
        .T(phy2iob_t[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[8].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[5]),
        .I(phy2iob_q_out_byte[6]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[7]),
        .O(iob2phy_d_in_byte[6]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[6]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[9].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[6]),
        .I(phy2iob_q_out_byte[7]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[8]),
        .O(iob2phy_d_in_byte[7]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[7]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  HPIO_VREF #(
    .VREF_CNTR("FABRIC_RANGE1")) 
    \genVref.u_hpio_vref 
       (.FABRIC_VREF_TUNE(mcal_rd_vref_value),
        .VREF(Vref));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_iob_byte" *) 
module ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized2_660
   (iob2phy_d_in_byte,
    iob_pin,
    phy2iob_odt_out_byte,
    phy2iob_q_out_byte,
    phy2iob_t,
    mcal_rd_vref_value);
  output [9:0]iob2phy_d_in_byte;
  inout [10:0]iob_pin;
  input [8:0]phy2iob_odt_out_byte;
  input [9:0]phy2iob_q_out_byte;
  input [9:0]phy2iob_t;
  input [6:0]mcal_rd_vref_value;

  wire Vref;
  wire [9:0]iob2phy_d_in_byte;
  wire [10:0]iob_pin;
  wire [6:0]mcal_rd_vref_value;
  wire [8:0]phy2iob_odt_out_byte;
  wire [9:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;

  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[0].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[0]),
        .I(phy2iob_q_out_byte[0]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[0]),
        .O(iob2phy_d_in_byte[0]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[0]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[10].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[7]),
        .I(phy2iob_q_out_byte[8]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[9]),
        .O(iob2phy_d_in_byte[8]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[8]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[11].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[8]),
        .I(phy2iob_q_out_byte[9]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[10]),
        .O(iob2phy_d_in_byte[9]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[9]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[2].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[1]),
        .I(phy2iob_q_out_byte[1]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[1]),
        .O(iob2phy_d_in_byte[1]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[1]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[3].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[2]),
        .I(phy2iob_q_out_byte[2]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[2]),
        .O(iob2phy_d_in_byte[2]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[2]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[4].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[3]),
        .I(phy2iob_q_out_byte[3]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[3]),
        .O(iob2phy_d_in_byte[3]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[3]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[5].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[4]),
        .I(phy2iob_q_out_byte[4]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[4]),
        .O(iob2phy_d_in_byte[4]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[4]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS #(
    .DIFF_TERM("FALSE"),
    .IOSTANDARD("DEFAULT")) 
    \genBuf[6].IO_BUFDS 
       (.I(phy2iob_q_out_byte[5]),
        .IO(iob_pin[5]),
        .IOB(iob_pin[6]),
        .O(iob2phy_d_in_byte[5]),
        .T(phy2iob_t[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[8].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[5]),
        .I(phy2iob_q_out_byte[6]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[7]),
        .O(iob2phy_d_in_byte[6]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[6]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[9].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[6]),
        .I(phy2iob_q_out_byte[7]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[8]),
        .O(iob2phy_d_in_byte[7]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[7]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  HPIO_VREF #(
    .VREF_CNTR("FABRIC_RANGE1")) 
    \genVref.u_hpio_vref 
       (.FABRIC_VREF_TUNE(mcal_rd_vref_value),
        .VREF(Vref));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_iob_byte" *) 
module ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized2_661
   (iob2phy_d_in_byte,
    iob_pin,
    phy2iob_odt_out_byte,
    phy2iob_q_out_byte,
    phy2iob_t,
    mcal_rd_vref_value);
  output [9:0]iob2phy_d_in_byte;
  inout [10:0]iob_pin;
  input [8:0]phy2iob_odt_out_byte;
  input [9:0]phy2iob_q_out_byte;
  input [9:0]phy2iob_t;
  input [6:0]mcal_rd_vref_value;

  wire Vref;
  wire [9:0]iob2phy_d_in_byte;
  wire [10:0]iob_pin;
  wire [6:0]mcal_rd_vref_value;
  wire [8:0]phy2iob_odt_out_byte;
  wire [9:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;

  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[0].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[0]),
        .I(phy2iob_q_out_byte[0]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[0]),
        .O(iob2phy_d_in_byte[0]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[0]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[10].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[7]),
        .I(phy2iob_q_out_byte[8]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[9]),
        .O(iob2phy_d_in_byte[8]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[8]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[11].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[8]),
        .I(phy2iob_q_out_byte[9]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[10]),
        .O(iob2phy_d_in_byte[9]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[9]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[2].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[1]),
        .I(phy2iob_q_out_byte[1]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[1]),
        .O(iob2phy_d_in_byte[1]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[1]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[3].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[2]),
        .I(phy2iob_q_out_byte[2]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[2]),
        .O(iob2phy_d_in_byte[2]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[2]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[4].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[3]),
        .I(phy2iob_q_out_byte[3]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[3]),
        .O(iob2phy_d_in_byte[3]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[3]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[5].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[4]),
        .I(phy2iob_q_out_byte[4]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[4]),
        .O(iob2phy_d_in_byte[4]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[4]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS #(
    .DIFF_TERM("FALSE"),
    .IOSTANDARD("DEFAULT")) 
    \genBuf[6].IO_BUFDS 
       (.I(phy2iob_q_out_byte[5]),
        .IO(iob_pin[5]),
        .IOB(iob_pin[6]),
        .O(iob2phy_d_in_byte[5]),
        .T(phy2iob_t[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[8].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[5]),
        .I(phy2iob_q_out_byte[6]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[7]),
        .O(iob2phy_d_in_byte[6]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[6]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[9].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[6]),
        .I(phy2iob_q_out_byte[7]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[8]),
        .O(iob2phy_d_in_byte[7]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[7]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  HPIO_VREF #(
    .VREF_CNTR("FABRIC_RANGE1")) 
    \genVref.u_hpio_vref 
       (.FABRIC_VREF_TUNE(mcal_rd_vref_value),
        .VREF(Vref));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_iob_byte" *) 
module ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized2_662
   (iob2phy_d_in_byte,
    iob_pin,
    phy2iob_odt_out_byte,
    phy2iob_q_out_byte,
    phy2iob_t,
    mcal_rd_vref_value);
  output [9:0]iob2phy_d_in_byte;
  inout [10:0]iob_pin;
  input [8:0]phy2iob_odt_out_byte;
  input [9:0]phy2iob_q_out_byte;
  input [9:0]phy2iob_t;
  input [6:0]mcal_rd_vref_value;

  wire Vref;
  wire [9:0]iob2phy_d_in_byte;
  wire [10:0]iob_pin;
  wire [6:0]mcal_rd_vref_value;
  wire [8:0]phy2iob_odt_out_byte;
  wire [9:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;

  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[0].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[0]),
        .I(phy2iob_q_out_byte[0]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[0]),
        .O(iob2phy_d_in_byte[0]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[0]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[10].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[7]),
        .I(phy2iob_q_out_byte[8]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[9]),
        .O(iob2phy_d_in_byte[8]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[8]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[11].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[8]),
        .I(phy2iob_q_out_byte[9]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[10]),
        .O(iob2phy_d_in_byte[9]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[9]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[2].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[1]),
        .I(phy2iob_q_out_byte[1]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[1]),
        .O(iob2phy_d_in_byte[1]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[1]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[3].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[2]),
        .I(phy2iob_q_out_byte[2]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[2]),
        .O(iob2phy_d_in_byte[2]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[2]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[4].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[3]),
        .I(phy2iob_q_out_byte[3]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[3]),
        .O(iob2phy_d_in_byte[3]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[3]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[5].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[4]),
        .I(phy2iob_q_out_byte[4]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[4]),
        .O(iob2phy_d_in_byte[4]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[4]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS #(
    .DIFF_TERM("FALSE"),
    .IOSTANDARD("DEFAULT")) 
    \genBuf[6].IO_BUFDS 
       (.I(phy2iob_q_out_byte[5]),
        .IO(iob_pin[5]),
        .IOB(iob_pin[6]),
        .O(iob2phy_d_in_byte[5]),
        .T(phy2iob_t[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[8].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[5]),
        .I(phy2iob_q_out_byte[6]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[7]),
        .O(iob2phy_d_in_byte[6]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[6]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[9].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[6]),
        .I(phy2iob_q_out_byte[7]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[8]),
        .O(iob2phy_d_in_byte[7]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[7]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  HPIO_VREF #(
    .VREF_CNTR("FABRIC_RANGE1")) 
    \genVref.u_hpio_vref 
       (.FABRIC_VREF_TUNE(mcal_rd_vref_value),
        .VREF(Vref));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_iob_byte" *) 
module ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized2_663
   (iob2phy_d_in_byte,
    iob_pin,
    phy2iob_odt_out_byte,
    phy2iob_q_out_byte,
    phy2iob_t,
    mcal_rd_vref_value);
  output [9:0]iob2phy_d_in_byte;
  inout [10:0]iob_pin;
  input [8:0]phy2iob_odt_out_byte;
  input [9:0]phy2iob_q_out_byte;
  input [9:0]phy2iob_t;
  input [6:0]mcal_rd_vref_value;

  wire Vref;
  wire [9:0]iob2phy_d_in_byte;
  wire [10:0]iob_pin;
  wire [6:0]mcal_rd_vref_value;
  wire [8:0]phy2iob_odt_out_byte;
  wire [9:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;

  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[0].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[0]),
        .I(phy2iob_q_out_byte[0]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[0]),
        .O(iob2phy_d_in_byte[0]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[0]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[10].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[7]),
        .I(phy2iob_q_out_byte[8]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[9]),
        .O(iob2phy_d_in_byte[8]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[8]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[11].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[8]),
        .I(phy2iob_q_out_byte[9]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[10]),
        .O(iob2phy_d_in_byte[9]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[9]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[2].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[1]),
        .I(phy2iob_q_out_byte[1]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[1]),
        .O(iob2phy_d_in_byte[1]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[1]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[3].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[2]),
        .I(phy2iob_q_out_byte[2]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[2]),
        .O(iob2phy_d_in_byte[2]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[2]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[4].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[3]),
        .I(phy2iob_q_out_byte[3]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[3]),
        .O(iob2phy_d_in_byte[3]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[3]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[5].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[4]),
        .I(phy2iob_q_out_byte[4]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[4]),
        .O(iob2phy_d_in_byte[4]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[4]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS #(
    .DIFF_TERM("FALSE"),
    .IOSTANDARD("DEFAULT")) 
    \genBuf[6].IO_BUFDS 
       (.I(phy2iob_q_out_byte[5]),
        .IO(iob_pin[5]),
        .IOB(iob_pin[6]),
        .O(iob2phy_d_in_byte[5]),
        .T(phy2iob_t[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[8].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[5]),
        .I(phy2iob_q_out_byte[6]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[7]),
        .O(iob2phy_d_in_byte[6]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[6]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[9].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[6]),
        .I(phy2iob_q_out_byte[7]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[8]),
        .O(iob2phy_d_in_byte[7]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[7]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  HPIO_VREF #(
    .VREF_CNTR("FABRIC_RANGE1")) 
    \genVref.u_hpio_vref 
       (.FABRIC_VREF_TUNE(mcal_rd_vref_value),
        .VREF(Vref));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_iob_byte" *) 
module ddr4_0_ddr4_phy_v2_2_0_iob_byte__parameterized2_664
   (iob2phy_d_in_byte,
    iob_pin,
    phy2iob_odt_out_byte,
    phy2iob_q_out_byte,
    phy2iob_t,
    mcal_rd_vref_value);
  output [9:0]iob2phy_d_in_byte;
  inout [10:0]iob_pin;
  input [8:0]phy2iob_odt_out_byte;
  input [9:0]phy2iob_q_out_byte;
  input [9:0]phy2iob_t;
  input [6:0]mcal_rd_vref_value;

  wire Vref;
  wire [9:0]iob2phy_d_in_byte;
  wire [10:0]iob_pin;
  wire [6:0]mcal_rd_vref_value;
  wire [8:0]phy2iob_odt_out_byte;
  wire [9:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;

  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[0].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[0]),
        .I(phy2iob_q_out_byte[0]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[0]),
        .O(iob2phy_d_in_byte[0]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[0]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[10].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[7]),
        .I(phy2iob_q_out_byte[8]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[9]),
        .O(iob2phy_d_in_byte[8]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[8]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[11].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[8]),
        .I(phy2iob_q_out_byte[9]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[10]),
        .O(iob2phy_d_in_byte[9]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[9]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[2].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[1]),
        .I(phy2iob_q_out_byte[1]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[1]),
        .O(iob2phy_d_in_byte[1]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[1]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[3].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[2]),
        .I(phy2iob_q_out_byte[2]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[2]),
        .O(iob2phy_d_in_byte[2]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[2]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[4].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[3]),
        .I(phy2iob_q_out_byte[3]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[3]),
        .O(iob2phy_d_in_byte[3]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[3]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[5].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[4]),
        .I(phy2iob_q_out_byte[4]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[4]),
        .O(iob2phy_d_in_byte[4]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[4]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS #(
    .DIFF_TERM("FALSE"),
    .IOSTANDARD("DEFAULT")) 
    \genBuf[6].IO_BUFDS 
       (.I(phy2iob_q_out_byte[5]),
        .IO(iob_pin[5]),
        .IOB(iob_pin[6]),
        .O(iob2phy_d_in_byte[5]),
        .T(phy2iob_t[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[8].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[5]),
        .I(phy2iob_q_out_byte[6]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[7]),
        .O(iob2phy_d_in_byte[6]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[6]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFE3 #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_INPUT_BUFFER_OFFSET(0),
    .USE_IBUFDISABLE("FALSE")) 
    \genBuf[9].genblk1_1.IOBUF 
       (.DCITERMDISABLE(phy2iob_odt_out_byte[6]),
        .I(phy2iob_q_out_byte[7]),
        .IBUFDISABLE(1'b0),
        .IO(iob_pin[8]),
        .O(iob2phy_d_in_byte[7]),
        .OSC({1'b0,1'b0,1'b0,1'b0}),
        .OSC_EN(1'b0),
        .T(phy2iob_t[7]),
        .VREF(Vref));
  (* BOX_TYPE = "PRIMITIVE" *) 
  HPIO_VREF #(
    .VREF_CNTR("FABRIC_RANGE1")) 
    \genVref.u_hpio_vref 
       (.FABRIC_VREF_TUNE(mcal_rd_vref_value),
        .VREF(Vref));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_pll" *) 
module ddr4_0_ddr4_phy_v2_2_0_pll
   (sys_clk_in,
    mmcm_clk_in,
    pll_clk,
    pll_lock,
    sys_clk_p,
    sys_clk_n,
    div_clk,
    pllGate,
    out,
    ub_rst_out_riuclk,
    mmcm_lock);
  output sys_clk_in;
  output mmcm_clk_in;
  output [2:0]pll_clk;
  output pll_lock;
  input sys_clk_p;
  input sys_clk_n;
  input div_clk;
  input pllGate;
  input out;
  input ub_rst_out_riuclk;
  input mmcm_lock;

  wire clkphyout_en;
  wire clkphyout_en_i_1_n_0;
  wire div_clk;
  wire mmcm_clk_in;
  wire mmcm_lock;
  wire out;
  wire pllGate;
  wire [2:0]pll_clk;
  wire pll_lock;
  wire [2:0]pll_lock_i;
  wire rst_pll;
  wire sys_clk_in;
  wire sys_clk_n;
  wire sys_clk_p;
  wire ub_rst_out_riuclk;
  wire \NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_CLKFBIN_UNCONNECTED ;
  wire \NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_CLKFBOUT_UNCONNECTED ;
  wire \NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT0_UNCONNECTED ;
  wire \NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT0B_UNCONNECTED ;
  wire \NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT1_UNCONNECTED ;
  wire \NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT1B_UNCONNECTED ;
  wire \NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_DRDY_UNCONNECTED ;
  wire [15:0]\NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_DO_UNCONNECTED ;
  wire \NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_CLKFBIN_UNCONNECTED ;
  wire \NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_CLKFBOUT_UNCONNECTED ;
  wire \NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT0_UNCONNECTED ;
  wire \NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT0B_UNCONNECTED ;
  wire \NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT1_UNCONNECTED ;
  wire \NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT1B_UNCONNECTED ;
  wire \NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_DRDY_UNCONNECTED ;
  wire [15:0]\NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_DO_UNCONNECTED ;
  wire \NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_CLKFBIN_UNCONNECTED ;
  wire \NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_CLKFBOUT_UNCONNECTED ;
  wire \NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT0_UNCONNECTED ;
  wire \NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT0B_UNCONNECTED ;
  wire \NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT1_UNCONNECTED ;
  wire \NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT1B_UNCONNECTED ;
  wire \NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_DRDY_UNCONNECTED ;
  wire [15:0]\NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_DO_UNCONNECTED ;

  LUT3 #(
    .INIT(8'h0E)) 
    clkphyout_en_i_1
       (.I0(clkphyout_en),
        .I1(pllGate),
        .I2(out),
        .O(clkphyout_en_i_1_n_0));
  FDRE clkphyout_en_reg
       (.C(div_clk),
        .CE(1'b1),
        .D(clkphyout_en_i_1_n_0),
        .Q(clkphyout_en),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  (* IBUF_DELAY_VALUE = "0" *) 
  (* IFD_DELAY_VALUE = "AUTO" *) 
  IBUFDS #(
    .CCIO_EN_M("TRUE"),
    .CCIO_EN_S("TRUE"),
    .DIFF_TERM("FALSE"),
    .IOSTANDARD("DEFAULT")) 
    \diff_input_clk.u_ibufg_sys_clk 
       (.I(sys_clk_p),
        .IB(sys_clk_n),
        .O(sys_clk_in));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "BUFG" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  BUFGCE #(
    .CE_TYPE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE")) 
    \gen_bufg_backbone.u__bufg_backbone 
       (.CE(1'b1),
        .I(sys_clk_in),
        .O(mmcm_clk_in));
  LUT3 #(
    .INIT(8'h80)) 
    pll_lock_INST_0
       (.I0(pll_lock_i[0]),
        .I1(pll_lock_i[2]),
        .I2(pll_lock_i[1]),
        .O(pll_lock));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  PLLE3_ADV #(
    .CLKFBOUT_MULT(4),
    .CLKFBOUT_PHASE(90.000000),
    .CLKIN_PERIOD(3.332000),
    .CLKOUT0_DIVIDE(1),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT1_DIVIDE(1),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUTPHY_MODE("VCO_2X"),
    .COMPENSATION("INTERNAL"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKFBIN_INVERTED(1'b0),
    .IS_CLKIN_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .REF_JITTER(0.010000),
    .STARTUP_WAIT("FALSE")) 
    \plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER 
       (.CLKFBIN(\NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_CLKFBIN_UNCONNECTED ),
        .CLKFBOUT(\NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_CLKFBOUT_UNCONNECTED ),
        .CLKIN(div_clk),
        .CLKOUT0(\NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT0_UNCONNECTED ),
        .CLKOUT0B(\NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT0B_UNCONNECTED ),
        .CLKOUT1(\NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT1_UNCONNECTED ),
        .CLKOUT1B(\NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT1B_UNCONNECTED ),
        .CLKOUTPHY(pll_clk[0]),
        .CLKOUTPHYEN(clkphyout_en),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(\NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_DO_UNCONNECTED [15:0]),
        .DRDY(\NLW_plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_DRDY_UNCONNECTED ),
        .DWE(1'b0),
        .LOCKED(pll_lock_i[0]),
        .PWRDWN(1'b0),
        .RST(rst_pll));
  LUT2 #(
    .INIT(4'hB)) 
    \plle_loop[0].gen_plle3.PLLE3_BASE_INST_OTHER_i_1 
       (.I0(ub_rst_out_riuclk),
        .I1(mmcm_lock),
        .O(rst_pll));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  PLLE3_ADV #(
    .CLKFBOUT_MULT(4),
    .CLKFBOUT_PHASE(90.000000),
    .CLKIN_PERIOD(3.332000),
    .CLKOUT0_DIVIDE(1),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT1_DIVIDE(1),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUTPHY_MODE("VCO_2X"),
    .COMPENSATION("INTERNAL"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKFBIN_INVERTED(1'b0),
    .IS_CLKIN_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .REF_JITTER(0.010000),
    .STARTUP_WAIT("FALSE")) 
    \plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER 
       (.CLKFBIN(\NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_CLKFBIN_UNCONNECTED ),
        .CLKFBOUT(\NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_CLKFBOUT_UNCONNECTED ),
        .CLKIN(div_clk),
        .CLKOUT0(\NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT0_UNCONNECTED ),
        .CLKOUT0B(\NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT0B_UNCONNECTED ),
        .CLKOUT1(\NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT1_UNCONNECTED ),
        .CLKOUT1B(\NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT1B_UNCONNECTED ),
        .CLKOUTPHY(pll_clk[1]),
        .CLKOUTPHYEN(clkphyout_en),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(\NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_DO_UNCONNECTED [15:0]),
        .DRDY(\NLW_plle_loop[1].gen_plle3.PLLE3_BASE_INST_OTHER_DRDY_UNCONNECTED ),
        .DWE(1'b0),
        .LOCKED(pll_lock_i[1]),
        .PWRDWN(1'b0),
        .RST(rst_pll));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  PLLE3_ADV #(
    .CLKFBOUT_MULT(4),
    .CLKFBOUT_PHASE(90.000000),
    .CLKIN_PERIOD(3.332000),
    .CLKOUT0_DIVIDE(1),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT1_DIVIDE(1),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUTPHY_MODE("VCO_2X"),
    .COMPENSATION("INTERNAL"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKFBIN_INVERTED(1'b0),
    .IS_CLKIN_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .REF_JITTER(0.010000),
    .STARTUP_WAIT("FALSE")) 
    \plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER 
       (.CLKFBIN(\NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_CLKFBIN_UNCONNECTED ),
        .CLKFBOUT(\NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_CLKFBOUT_UNCONNECTED ),
        .CLKIN(div_clk),
        .CLKOUT0(\NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT0_UNCONNECTED ),
        .CLKOUT0B(\NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT0B_UNCONNECTED ),
        .CLKOUT1(\NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT1_UNCONNECTED ),
        .CLKOUT1B(\NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_CLKOUT1B_UNCONNECTED ),
        .CLKOUTPHY(pll_clk[2]),
        .CLKOUTPHYEN(clkphyout_en),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(\NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_DO_UNCONNECTED [15:0]),
        .DRDY(\NLW_plle_loop[2].gen_plle3.PLLE3_BASE_INST_OTHER_DRDY_UNCONNECTED ),
        .DWE(1'b0),
        .LOCKED(pll_lock_i[2]),
        .PWRDWN(1'b0),
        .RST(rst_pll));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy
   (phy2iob_q_out_byte,
    phy2iob_t,
    mcal_DMIn_n,
    mcal_DQIn,
    D,
    xiphy_control,
    phy2iob_odt_out_byte,
    xiphy_control_0,
    xiphy_control_1,
    riu2clb_valid_riuclk,
    xiphy_riu_or,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    clb2phy_wr_dq0,
    clb2phy_wr_dq1,
    ch0_mcal_DQOut,
    clb2phy_wr_dq6,
    en_vtc_riuclk,
    pll_clk,
    riu_clk,
    Q,
    SR,
    xiphy_control_2,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_3,
    xiphy_control_4,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    u_lut1_clb2riu_wr_en,
    mcal_ADR,
    clb2phy_t_b_low,
    mcal_BA,
    mcal_BG,
    mcal_CS_n,
    mcal_CKE);
  output [104:0]phy2iob_q_out_byte;
  output [79:0]phy2iob_t;
  output [63:0]mcal_DMIn_n;
  output [511:0]mcal_DQIn;
  output [9:0]D;
  output [9:0]xiphy_control;
  output [71:0]phy2iob_odt_out_byte;
  output [9:0]xiphy_control_0;
  output [9:0]xiphy_control_1;
  output [9:0]riu2clb_valid_riuclk;
  output [159:0]xiphy_riu_or;
  input [79:0]iob2phy_d_in_byte;
  input div_clk;
  input [81:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [79:0]clb2phy_wr_dq0;
  input [31:0]clb2phy_wr_dq1;
  input [511:0]ch0_mcal_DQOut;
  input [23:0]clb2phy_wr_dq6;
  input en_vtc_riuclk;
  input [2:0]pll_clk;
  input riu_clk;
  input [9:0]Q;
  input [0:0]SR;
  input [15:0]xiphy_control_2;
  input [31:0]ch0_mcal_clb2phy_rdcs0_low;
  input [31:0]ch0_mcal_clb2phy_rdcs1_low;
  input [31:0]ch0_mcal_clb2phy_rden_low;
  input [31:0]ch0_mcal_clb2phy_wrcs0_low;
  input [31:0]ch0_mcal_clb2phy_wrcs1_low;
  input [31:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_3;
  input [9:0]xiphy_control_4;
  input [31:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [31:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [31:0]ch0_mcal_clb2phy_rden_upp;
  input [31:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [31:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [31:0]ch0_mcal_clb2phy_t_b_upp;
  input [9:0]u_lut1_clb2riu_wr_en;
  input [95:0]mcal_ADR;
  input [3:0]clb2phy_t_b_low;
  input [15:0]mcal_BA;
  input [7:0]mcal_BG;
  input [7:0]mcal_CS_n;
  input [7:0]mcal_CKE;

  wire [9:0]D;
  wire [9:0]Q;
  wire [0:0]SR;
  wire [511:0]ch0_mcal_DQOut;
  wire [81:0]ch0_mcal_clb2phy_fifo_rden;
  wire [31:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [31:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [31:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [31:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [31:0]ch0_mcal_clb2phy_rden_low;
  wire [31:0]ch0_mcal_clb2phy_rden_upp;
  wire [31:0]ch0_mcal_clb2phy_t_b_low;
  wire [31:0]ch0_mcal_clb2phy_t_b_upp;
  wire [31:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [31:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [31:0]ch0_mcal_clb2phy_wrcs1_low;
  wire [31:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire [3:0]clb2phy_t_b_low;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [79:0]clb2phy_wr_dq0;
  wire [31:0]clb2phy_wr_dq1;
  wire [23:0]clb2phy_wr_dq6;
  wire div_clk;
  wire en_vtc_riuclk;
  wire [79:0]iob2phy_d_in_byte;
  wire [95:0]mcal_ADR;
  wire [15:0]mcal_BA;
  wire [7:0]mcal_BG;
  wire [7:0]mcal_CKE;
  wire [7:0]mcal_CS_n;
  wire [63:0]mcal_DMIn_n;
  wire [511:0]mcal_DQIn;
  wire [71:0]phy2iob_odt_out_byte;
  wire [104:0]phy2iob_q_out_byte;
  wire [79:0]phy2iob_t;
  wire [2:0]pll_clk;
  wire [9:0]riu2clb_valid_riuclk;
  wire riu_clk;
  wire [9:0]u_lut1_clb2riu_wr_en;
  wire [9:0]xiphy_control;
  wire [9:0]xiphy_control_0;
  wire [9:0]xiphy_control_1;
  wire [15:0]xiphy_control_2;
  wire [5:0]xiphy_control_3;
  wire [9:0]xiphy_control_4;
  wire [159:0]xiphy_riu_or;

  ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper \byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper 
       (.D(D[0]),
        .Q(Q[0]),
        .SR(SR),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[63:0]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[10:0]),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low[3:0]),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp[3:0]),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low[3:0]),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp[3:0]),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[3:0]),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[3:0]),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low[3:0]),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp[3:0]),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low[3:0]),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp[3:0]),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low[3:0]),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp[3:0]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0[7:0]),
        .clb2phy_wr_dq1(clb2phy_wr_dq1[7:0]),
        .clb2phy_wr_dq6(clb2phy_wr_dq6[23:16]),
        .div_clk(div_clk),
        .en_vtc_riuclk(en_vtc_riuclk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[9:0]),
        .mcal_DMIn_n(mcal_DMIn_n[7:0]),
        .mcal_DQIn(mcal_DQIn[63:0]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[8:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[10:0]),
        .phy2iob_t(phy2iob_t[9:0]),
        .pll_clk(pll_clk[0]),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk[0]),
        .riu_clk(riu_clk),
        .u_lut1_clb2riu_wr_en_0(u_lut1_clb2riu_wr_en[0]),
        .xiphy_control(xiphy_control[0]),
        .xiphy_control_0(xiphy_control_0[0]),
        .xiphy_control_1(xiphy_control_1[0]),
        .xiphy_control_2(xiphy_control_2),
        .xiphy_control_3(xiphy_control_3),
        .xiphy_control_4(xiphy_control_4[0]),
        .xiphy_riu_or(xiphy_riu_or[15:0]));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized0 \byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper 
       (.D(D[1]),
        .Q(Q[1]),
        .SR(SR),
        .clb2phy_t_b_low(clb2phy_t_b_low),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0[15:8]),
        .clb2phy_wr_dq1(clb2phy_wr_dq1[15:8]),
        .clb2phy_wr_dq6(clb2phy_wr_dq6[7:0]),
        .div_clk(div_clk),
        .en_vtc_riuclk(en_vtc_riuclk),
        .mcal_ADR(mcal_ADR[55:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[20:11]),
        .pll_clk(pll_clk[0]),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk[1]),
        .riu_clk(riu_clk),
        .u_lut1_clb2riu_wr_en_0(u_lut1_clb2riu_wr_en[1]),
        .xiphy_control(xiphy_control[1]),
        .xiphy_control_0(xiphy_control_0[1]),
        .xiphy_control_1(xiphy_control_1[1]),
        .xiphy_control_2(xiphy_control_2),
        .xiphy_control_3(xiphy_control_3),
        .xiphy_control_4(xiphy_control_4[1]),
        .xiphy_riu_or(xiphy_riu_or[31:16]));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized1 \byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper 
       (.D(D[2]),
        .Q(Q[2]),
        .SR(SR),
        .clb2phy_t_b_low(clb2phy_t_b_low),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0[23:16]),
        .clb2phy_wr_dq1(clb2phy_wr_dq1[23:16]),
        .clb2phy_wr_dq6(clb2phy_wr_dq6[15:8]),
        .div_clk(div_clk),
        .en_vtc_riuclk(en_vtc_riuclk),
        .mcal_ADR(mcal_ADR[95:56]),
        .mcal_BA(mcal_BA),
        .mcal_BG(mcal_BG),
        .mcal_CKE(mcal_CKE),
        .mcal_CS_n(mcal_CS_n),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[33:21]),
        .pll_clk(pll_clk[0]),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk[2]),
        .riu_clk(riu_clk),
        .u_lut1_clb2riu_wr_en_0(u_lut1_clb2riu_wr_en[2]),
        .xiphy_control(xiphy_control[2]),
        .xiphy_control_0(xiphy_control_0[2]),
        .xiphy_control_1(xiphy_control_1[2]),
        .xiphy_control_2(xiphy_control_2),
        .xiphy_control_3(xiphy_control_3),
        .xiphy_control_4(xiphy_control_4[2]),
        .xiphy_riu_or(xiphy_riu_or[47:32]));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper_665 \byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper 
       (.D(D[3]),
        .Q(Q[3]),
        .SR(SR),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[127:64]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[21:11]),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low[7:4]),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp[7:4]),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low[7:4]),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp[7:4]),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[7:4]),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[7:4]),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low[7:4]),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp[7:4]),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low[7:4]),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp[7:4]),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low[7:4]),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp[7:4]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0[31:24]),
        .clb2phy_wr_dq1(clb2phy_wr_dq1[31:24]),
        .clb2phy_wr_dq6(clb2phy_wr_dq6[23:16]),
        .div_clk(div_clk),
        .en_vtc_riuclk(en_vtc_riuclk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[19:10]),
        .mcal_DMIn_n(mcal_DMIn_n[15:8]),
        .mcal_DQIn(mcal_DQIn[127:64]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[17:9]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[44:34]),
        .phy2iob_t(phy2iob_t[19:10]),
        .pll_clk(pll_clk[0]),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk[3]),
        .riu_clk(riu_clk),
        .u_lut1_clb2riu_wr_en_0(u_lut1_clb2riu_wr_en[3]),
        .xiphy_control(xiphy_control[3]),
        .xiphy_control_0(xiphy_control_0[3]),
        .xiphy_control_1(xiphy_control_1[3]),
        .xiphy_control_2(xiphy_control_2),
        .xiphy_control_3(xiphy_control_3),
        .xiphy_control_4(xiphy_control_4[3]),
        .xiphy_riu_or(xiphy_riu_or[63:48]));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized2 \byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper 
       (.D(D[4]),
        .Q(Q[4]),
        .SR(SR),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[191:128]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[31:22]),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low[11:8]),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp[11:8]),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low[11:8]),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp[11:8]),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[11:8]),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[11:8]),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low[11:8]),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp[11:8]),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low[11:8]),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp[11:8]),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low[11:8]),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp[11:8]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0[39:32]),
        .clb2phy_wr_dq6(clb2phy_wr_dq6[23:16]),
        .div_clk(div_clk),
        .en_vtc_riuclk(en_vtc_riuclk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[29:20]),
        .mcal_DMIn_n(mcal_DMIn_n[23:16]),
        .mcal_DQIn(mcal_DQIn[191:128]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[26:18]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[54:45]),
        .phy2iob_t(phy2iob_t[29:20]),
        .pll_clk(pll_clk[1]),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk[4]),
        .riu_clk(riu_clk),
        .u_lut1_clb2riu_wr_en_0(u_lut1_clb2riu_wr_en[4]),
        .xiphy_control(xiphy_control[4]),
        .xiphy_control_0(xiphy_control_0[4]),
        .xiphy_control_1(xiphy_control_1[4]),
        .xiphy_control_2(xiphy_control_2),
        .xiphy_control_3(xiphy_control_3),
        .xiphy_control_4(xiphy_control_4[4]),
        .xiphy_riu_or(xiphy_riu_or[79:64]));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized2_666 \byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper 
       (.D(D[5]),
        .Q(Q[5]),
        .SR(SR),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[255:192]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[41:32]),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low[15:12]),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp[15:12]),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low[15:12]),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp[15:12]),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[15:12]),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[15:12]),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low[15:12]),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp[15:12]),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low[15:12]),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp[15:12]),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low[15:12]),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp[15:12]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0[47:40]),
        .clb2phy_wr_dq6(clb2phy_wr_dq6[23:16]),
        .div_clk(div_clk),
        .en_vtc_riuclk(en_vtc_riuclk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[39:30]),
        .mcal_DMIn_n(mcal_DMIn_n[31:24]),
        .mcal_DQIn(mcal_DQIn[255:192]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[35:27]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[64:55]),
        .phy2iob_t(phy2iob_t[39:30]),
        .pll_clk(pll_clk[1]),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk[5]),
        .riu_clk(riu_clk),
        .u_lut1_clb2riu_wr_en_0(u_lut1_clb2riu_wr_en[5]),
        .xiphy_control(xiphy_control[5]),
        .xiphy_control_0(xiphy_control_0[5]),
        .xiphy_control_1(xiphy_control_1[5]),
        .xiphy_control_2(xiphy_control_2),
        .xiphy_control_3(xiphy_control_3),
        .xiphy_control_4(xiphy_control_4[5]),
        .xiphy_riu_or(xiphy_riu_or[95:80]));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized2_667 \byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper 
       (.D(D[6]),
        .Q(Q[6]),
        .SR(SR),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[319:256]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[51:42]),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low[19:16]),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp[19:16]),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low[19:16]),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp[19:16]),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[19:16]),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[19:16]),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low[19:16]),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp[19:16]),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low[19:16]),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp[19:16]),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low[19:16]),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp[19:16]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0[55:48]),
        .clb2phy_wr_dq6(clb2phy_wr_dq6[23:16]),
        .div_clk(div_clk),
        .en_vtc_riuclk(en_vtc_riuclk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[49:40]),
        .mcal_DMIn_n(mcal_DMIn_n[39:32]),
        .mcal_DQIn(mcal_DQIn[319:256]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[44:36]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[74:65]),
        .phy2iob_t(phy2iob_t[49:40]),
        .pll_clk(pll_clk[1]),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk[6]),
        .riu_clk(riu_clk),
        .u_lut1_clb2riu_wr_en_0(u_lut1_clb2riu_wr_en[6]),
        .xiphy_control(xiphy_control[6]),
        .xiphy_control_0(xiphy_control_0[6]),
        .xiphy_control_1(xiphy_control_1[6]),
        .xiphy_control_2(xiphy_control_2),
        .xiphy_control_3(xiphy_control_3),
        .xiphy_control_4(xiphy_control_4[6]),
        .xiphy_riu_or(xiphy_riu_or[111:96]));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized2_668 \byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper 
       (.D(D[7]),
        .Q(Q[7]),
        .SR(SR),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[383:320]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[61:52]),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low[23:20]),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp[23:20]),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low[23:20]),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp[23:20]),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[23:20]),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[23:20]),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low[23:20]),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp[23:20]),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low[23:20]),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp[23:20]),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low[23:20]),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp[23:20]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0[63:56]),
        .clb2phy_wr_dq6(clb2phy_wr_dq6[23:16]),
        .div_clk(div_clk),
        .en_vtc_riuclk(en_vtc_riuclk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[59:50]),
        .mcal_DMIn_n(mcal_DMIn_n[47:40]),
        .mcal_DQIn(mcal_DQIn[383:320]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[53:45]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[84:75]),
        .phy2iob_t(phy2iob_t[59:50]),
        .pll_clk(pll_clk[1]),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk[7]),
        .riu_clk(riu_clk),
        .u_lut1_clb2riu_wr_en_0(u_lut1_clb2riu_wr_en[7]),
        .xiphy_control(xiphy_control[7]),
        .xiphy_control_0(xiphy_control_0[7]),
        .xiphy_control_1(xiphy_control_1[7]),
        .xiphy_control_2(xiphy_control_2),
        .xiphy_control_3(xiphy_control_3),
        .xiphy_control_4(xiphy_control_4[7]),
        .xiphy_riu_or(xiphy_riu_or[127:112]));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized2_669 \byte_num[8].xiphy_byte_wrapper.u_xiphy_byte_wrapper 
       (.D(D[8]),
        .Q(Q[8]),
        .SR(SR),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[447:384]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[71:62]),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low[27:24]),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp[27:24]),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low[27:24]),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp[27:24]),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[27:24]),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[27:24]),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low[27:24]),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp[27:24]),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low[27:24]),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp[27:24]),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low[27:24]),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp[27:24]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0[71:64]),
        .clb2phy_wr_dq6(clb2phy_wr_dq6[23:16]),
        .div_clk(div_clk),
        .en_vtc_riuclk(en_vtc_riuclk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[69:60]),
        .mcal_DMIn_n(mcal_DMIn_n[55:48]),
        .mcal_DQIn(mcal_DQIn[447:384]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[62:54]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[94:85]),
        .phy2iob_t(phy2iob_t[69:60]),
        .pll_clk(pll_clk[2]),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk[8]),
        .riu_clk(riu_clk),
        .u_lut1_clb2riu_wr_en_0(u_lut1_clb2riu_wr_en[8]),
        .xiphy_control(xiphy_control[8]),
        .xiphy_control_0(xiphy_control_0[8]),
        .xiphy_control_1(xiphy_control_1[8]),
        .xiphy_control_2(xiphy_control_2),
        .xiphy_control_3(xiphy_control_3),
        .xiphy_control_4(xiphy_control_4[8]),
        .xiphy_riu_or(xiphy_riu_or[143:128]));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized2_670 \byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper 
       (.D(D[9]),
        .Q(Q[9]),
        .SR(SR),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[511:448]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[81:72]),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low[31:28]),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp[31:28]),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low[31:28]),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp[31:28]),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[31:28]),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[31:28]),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low[31:28]),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp[31:28]),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low[31:28]),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp[31:28]),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low[31:28]),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp[31:28]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0[79:72]),
        .clb2phy_wr_dq6(clb2phy_wr_dq6[23:16]),
        .div_clk(div_clk),
        .en_vtc_riuclk(en_vtc_riuclk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[79:70]),
        .mcal_DMIn_n(mcal_DMIn_n[63:56]),
        .mcal_DQIn(mcal_DQIn[511:448]),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[71:63]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[104:95]),
        .phy2iob_t(phy2iob_t[79:70]),
        .pll_clk(pll_clk[2]),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk[9]),
        .riu_clk(riu_clk),
        .u_lut1_clb2riu_wr_en_0(u_lut1_clb2riu_wr_en[9]),
        .xiphy_control(xiphy_control[9]),
        .xiphy_control_0(xiphy_control_0[9]),
        .xiphy_control_1(xiphy_control_1[9]),
        .xiphy_control_2(xiphy_control_2),
        .xiphy_control_3(xiphy_control_3),
        .xiphy_control_4(xiphy_control_4[9]),
        .xiphy_riu_or(xiphy_riu_or[159:144]));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DMIn_n,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq0);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DMIn_n;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq0;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq0),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DMIn_n),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_671
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_672
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_673
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_674
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_675
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_676
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_677
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_678
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_680
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DMIn_n,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq0);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DMIn_n;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq0;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq0),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DMIn_n),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_681
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_682
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_683
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_684
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_686
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_687
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_688
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_689
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_695
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DMIn_n,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq0);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DMIn_n;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq0;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq0),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DMIn_n),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_696
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_697
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_698
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_699
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_701
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_702
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_703
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_704
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_710
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DMIn_n,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq0);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DMIn_n;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq0;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq0),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DMIn_n),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_711
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_712
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_713
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_714
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_716
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_717
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_718
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_719
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_725
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DMIn_n,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq0);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DMIn_n;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq0;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq0),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DMIn_n),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_726
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_727
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_728
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_729
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_731
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_732
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_733
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_734
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_740
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DMIn_n,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq0);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DMIn_n;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq0;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq0),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DMIn_n),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_741
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_742
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_743
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_744
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_746
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_747
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_748
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_749
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_755
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DMIn_n,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq0);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DMIn_n;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq0;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq0),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DMIn_n),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_756
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_757
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_758
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_759
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_761
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_762
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_763
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_764
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_802
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DMIn_n,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq0);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DMIn_n;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq0;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq0),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DMIn_n),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_804
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_805
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_806
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_807
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_809
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_810
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_811
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_812
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    mcal_DQIn,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    ch0_mcal_DQOut);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  output [7:0]mcal_DQIn;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]ch0_mcal_DQOut;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [7:0]ch0_mcal_DQOut;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DQIn;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("FALSE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(ch0_mcal_DQOut),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q(mcal_DQIn),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b1),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT1,
    TX_BIT_CTRL_OUT1,
    clb2phy_wr_dq1);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT1;
  input [39:0]TX_BIT_CTRL_OUT1;
  input [7:0]clb2phy_wr_dq1;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT1;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT1;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq1;
  wire div_clk;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq1),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT1),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT1),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_771
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT1,
    TX_BIT_CTRL_OUT1,
    clb2phy_wr_dq1);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT1;
  input [39:0]TX_BIT_CTRL_OUT1;
  input [7:0]clb2phy_wr_dq1;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT1;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT1;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq1;
  wire div_clk;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq1),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT1),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT1),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_772
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    mcal_ADR);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]mcal_ADR;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_ADR;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_ADR),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_773
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    mcal_ADR);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]mcal_ADR;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_ADR;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_ADR),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_774
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    mcal_ADR);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]mcal_ADR;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_ADR;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_ADR),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_775
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    mcal_ADR);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]mcal_ADR;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_ADR;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_ADR),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_777
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT1,
    TX_BIT_CTRL_OUT1,
    mcal_ADR);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT1;
  input [39:0]TX_BIT_CTRL_OUT1;
  input [7:0]mcal_ADR;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT1;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT1;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_ADR;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_ADR),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT1),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT1),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_778
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    mcal_BA);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]mcal_BA;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_BA;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_BA),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_779
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    mcal_BA);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]mcal_BA;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_BA;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_BA),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_780
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    mcal_BG);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]mcal_BG;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_BG;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_BG),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_781
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    mcal_CS_n);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]mcal_CS_n;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_CS_n;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_CS_n),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_782
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT6,
    TX_BIT_CTRL_OUT6,
    mcal_CKE);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT6;
  input [39:0]TX_BIT_CTRL_OUT6;
  input [7:0]mcal_CKE;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT6;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT6;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_CKE;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_CKE),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT6),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT6),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_788
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT1,
    TX_BIT_CTRL_OUT1,
    clb2phy_wr_dq1);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT1;
  input [39:0]TX_BIT_CTRL_OUT1;
  input [7:0]clb2phy_wr_dq1;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT1;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT1;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq1;
  wire div_clk;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq1),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT1),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT1),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_789
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT2,
    mcal_ADR);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT2;
  input [39:0]TX_BIT_CTRL_OUT2;
  input [7:0]mcal_ADR;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_ADR;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_ADR),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_790
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT3,
    mcal_ADR);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT3;
  input [39:0]TX_BIT_CTRL_OUT3;
  input [7:0]mcal_ADR;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_ADR;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_ADR),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_791
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    mcal_ADR);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]mcal_ADR;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_ADR;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_ADR),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_792
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    mcal_ADR);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]mcal_ADR;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_ADR;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_ADR),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_794
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT4,
    mcal_ADR);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT4;
  input [39:0]TX_BIT_CTRL_OUT4;
  input [7:0]mcal_ADR;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_ADR;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_ADR),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_795
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT5,
    mcal_ADR);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT5;
  input [39:0]TX_BIT_CTRL_OUT5;
  input [7:0]mcal_ADR;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_ADR;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_ADR),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_796
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT6,
    TX_BIT_CTRL_OUT6,
    mcal_ADR);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT6;
  input [39:0]TX_BIT_CTRL_OUT6;
  input [7:0]mcal_ADR;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT6;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT6;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire div_clk;
  wire [7:0]mcal_ADR;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(mcal_ADR),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT6),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT6),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_803
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT1,
    TX_BIT_CTRL_OUT1,
    clb2phy_wr_dq1);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT1;
  input [39:0]TX_BIT_CTRL_OUT1;
  input [7:0]clb2phy_wr_dq1;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT1;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT1;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq1;
  wire div_clk;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq1),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT1),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT1),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq6);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq6;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq6;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA_AND_CLOCK"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq6),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_685
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq6);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq6;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq6;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA_AND_CLOCK"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq6),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_700
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq6);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq6;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq6;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA_AND_CLOCK"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq6),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_715
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq6);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq6;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq6;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA_AND_CLOCK"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq6),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_730
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq6);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq6;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq6;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA_AND_CLOCK"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq6),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_745
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq6);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq6;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq6;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA_AND_CLOCK"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq6),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_760
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq6);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq6;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq6;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA_AND_CLOCK"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq6),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_770
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq0);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq0;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire div_clk;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA_AND_CLOCK"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq0),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_776
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq6);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq6;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq6;
  wire div_clk;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA_AND_CLOCK"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq6),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_787
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_0,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq0);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_0;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq0;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire div_clk;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_0;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA_AND_CLOCK"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq0),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_0),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_793
   (phy2iob_q_out_byte,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    div_clk,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq6);
  output [0:0]phy2iob_q_out_byte;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq6;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq6;
  wire div_clk;
  wire [0:0]phy2iob_q_out_byte;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_3;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA_AND_CLOCK"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq6),
        .DATAIN(1'b0),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(1'b0),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(xiphy_rxtx_bitslice_n_3));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_bitslice_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_808
   (phy2iob_q_out_byte,
    phy2iob_t,
    RX_BIT_CTRL_OUT,
    TX_BIT_CTRL_OUT,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    tristate_q_1,
    RX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT0,
    clb2phy_wr_dq6);
  output [0:0]phy2iob_q_out_byte;
  output [0:0]phy2iob_t;
  output [39:0]RX_BIT_CTRL_OUT;
  output [39:0]TX_BIT_CTRL_OUT;
  input [0:0]iob2phy_d_in_byte;
  input div_clk;
  input [0:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input tristate_q_1;
  input [39:0]RX_BIT_CTRL_OUT0;
  input [39:0]TX_BIT_CTRL_OUT0;
  input [7:0]clb2phy_wr_dq6;

  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [0:0]ch0_mcal_clb2phy_fifo_rden;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq6;
  wire div_clk;
  wire [0:0]iob2phy_d_in_byte;
  wire [0:0]phy2iob_q_out_byte;
  wire [0:0]phy2iob_t;
  wire tristate_q_1;
  wire xiphy_rxtx_bitslice_n_0;
  wire xiphy_rxtx_bitslice_n_1;
  wire xiphy_rxtx_bitslice_n_100;
  wire xiphy_rxtx_bitslice_n_101;
  wire xiphy_rxtx_bitslice_n_102;
  wire xiphy_rxtx_bitslice_n_103;
  wire xiphy_rxtx_bitslice_n_104;
  wire xiphy_rxtx_bitslice_n_105;
  wire xiphy_rxtx_bitslice_n_106;
  wire xiphy_rxtx_bitslice_n_107;
  wire xiphy_rxtx_bitslice_n_108;
  wire xiphy_rxtx_bitslice_n_109;
  wire xiphy_rxtx_bitslice_n_84;
  wire xiphy_rxtx_bitslice_n_85;
  wire xiphy_rxtx_bitslice_n_86;
  wire xiphy_rxtx_bitslice_n_87;
  wire xiphy_rxtx_bitslice_n_88;
  wire xiphy_rxtx_bitslice_n_89;
  wire xiphy_rxtx_bitslice_n_90;
  wire xiphy_rxtx_bitslice_n_91;
  wire xiphy_rxtx_bitslice_n_92;
  wire xiphy_rxtx_bitslice_n_93;
  wire xiphy_rxtx_bitslice_n_94;
  wire xiphy_rxtx_bitslice_n_95;
  wire xiphy_rxtx_bitslice_n_96;
  wire xiphy_rxtx_bitslice_n_97;
  wire xiphy_rxtx_bitslice_n_98;
  wire xiphy_rxtx_bitslice_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RXTX_BITSLICE #(
    .ENABLE_PRE_EMPHASIS("TRUE"),
    .FIFO_SYNC_MODE("FALSE"),
    .INIT(1'b1),
    .IS_RX_CLK_INVERTED(1'b0),
    .IS_RX_RST_DLY_INVERTED(1'b0),
    .IS_RX_RST_INVERTED(1'b0),
    .IS_TX_CLK_INVERTED(1'b0),
    .IS_TX_RST_DLY_INVERTED(1'b0),
    .IS_TX_RST_INVERTED(1'b0),
    .LOOPBACK("FALSE"),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .RX_DATA_TYPE("DATA_AND_CLOCK"),
    .RX_DATA_WIDTH(8),
    .RX_DELAY_FORMAT("TIME"),
    .RX_DELAY_TYPE("FIXED"),
    .RX_DELAY_VALUE(0),
    .RX_REFCLK_FREQUENCY(300.000000),
    .RX_UPDATE_MODE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .TBYTE_CTL("TBYTE_IN"),
    .TX_DATA_WIDTH(8),
    .TX_DELAY_FORMAT("TIME"),
    .TX_DELAY_TYPE("FIXED"),
    .TX_DELAY_VALUE(0),
    .TX_OUTPUT_PHASE_90("TRUE"),
    .TX_REFCLK_FREQUENCY(300.000000),
    .TX_UPDATE_MODE("ASYNC")) 
    xiphy_rxtx_bitslice
       (.D(clb2phy_wr_dq6),
        .DATAIN(iob2phy_d_in_byte),
        .FIFO_EMPTY(xiphy_rxtx_bitslice_n_0),
        .FIFO_RD_CLK(div_clk),
        .FIFO_RD_EN(ch0_mcal_clb2phy_fifo_rden),
        .FIFO_WRCLK_OUT(xiphy_rxtx_bitslice_n_1),
        .O(phy2iob_q_out_byte),
        .Q({xiphy_rxtx_bitslice_n_84,xiphy_rxtx_bitslice_n_85,xiphy_rxtx_bitslice_n_86,xiphy_rxtx_bitslice_n_87,xiphy_rxtx_bitslice_n_88,xiphy_rxtx_bitslice_n_89,xiphy_rxtx_bitslice_n_90,xiphy_rxtx_bitslice_n_91}),
        .RX_BIT_CTRL_IN(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT),
        .RX_CE(1'b0),
        .RX_CLK(1'b1),
        .RX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_92,xiphy_rxtx_bitslice_n_93,xiphy_rxtx_bitslice_n_94,xiphy_rxtx_bitslice_n_95,xiphy_rxtx_bitslice_n_96,xiphy_rxtx_bitslice_n_97,xiphy_rxtx_bitslice_n_98,xiphy_rxtx_bitslice_n_99,xiphy_rxtx_bitslice_n_100}),
        .RX_EN_VTC(1'b1),
        .RX_INC(1'b0),
        .RX_LOAD(1'b0),
        .RX_RST(clb2phy_tristate_odelay_rst),
        .RX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T(1'b0),
        .TBYTE_IN(tristate_q_1),
        .TX_BIT_CTRL_IN(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT),
        .TX_CE(1'b0),
        .TX_CLK(1'b1),
        .TX_CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_CNTVALUEOUT({xiphy_rxtx_bitslice_n_101,xiphy_rxtx_bitslice_n_102,xiphy_rxtx_bitslice_n_103,xiphy_rxtx_bitslice_n_104,xiphy_rxtx_bitslice_n_105,xiphy_rxtx_bitslice_n_106,xiphy_rxtx_bitslice_n_107,xiphy_rxtx_bitslice_n_108,xiphy_rxtx_bitslice_n_109}),
        .TX_EN_VTC(1'b1),
        .TX_INC(1'b0),
        .TX_LOAD(1'b0),
        .TX_RST(clb2phy_tristate_odelay_rst),
        .TX_RST_DLY(clb2phy_tristate_odelay_rst),
        .T_OUT(phy2iob_t));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_byte_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper
   (phy2iob_q_out_byte,
    phy2iob_t,
    mcal_DMIn_n,
    mcal_DQIn,
    D,
    xiphy_control,
    phy2iob_odt_out_byte,
    xiphy_control_0,
    xiphy_control_1,
    riu2clb_valid_riuclk,
    xiphy_riu_or,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    clb2phy_wr_dq0,
    clb2phy_wr_dq1,
    ch0_mcal_DQOut,
    clb2phy_wr_dq6,
    en_vtc_riuclk,
    pll_clk,
    riu_clk,
    Q,
    SR,
    xiphy_control_2,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_3,
    xiphy_control_4,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    u_lut1_clb2riu_wr_en_0);
  output [10:0]phy2iob_q_out_byte;
  output [9:0]phy2iob_t;
  output [7:0]mcal_DMIn_n;
  output [63:0]mcal_DQIn;
  output [0:0]D;
  output [0:0]xiphy_control;
  output [8:0]phy2iob_odt_out_byte;
  output [0:0]xiphy_control_0;
  output [0:0]xiphy_control_1;
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or;
  input [9:0]iob2phy_d_in_byte;
  input div_clk;
  input [10:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [7:0]clb2phy_wr_dq0;
  input [7:0]clb2phy_wr_dq1;
  input [63:0]ch0_mcal_DQOut;
  input [7:0]clb2phy_wr_dq6;
  input en_vtc_riuclk;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input [0:0]SR;
  input [15:0]xiphy_control_2;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_3;
  input [0:0]xiphy_control_4;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [0:0]u_lut1_clb2riu_wr_en_0;

  wire [0:0]D;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [63:0]ch0_mcal_DQOut;
  wire [10:0]ch0_mcal_clb2phy_fifo_rden;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire [7:0]clb2phy_wr_dq1;
  wire [7:0]clb2phy_wr_dq6;
  wire clb2riu_wr_en_lut;
  wire div_clk;
  wire en_vtc_riuclk;
  wire [9:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [63:0]mcal_DQIn;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [8:0]phy2iob_odt_out_byte;
  wire [10:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;
  wire [0:0]pll_clk;
  wire [15:0]\riu2clb_rd_data_array[0]_37 ;
  wire [15:0]\riu2clb_rd_data_array[1]_49 ;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [39:0]\rx_bit_ctrl_in0[0]_1 ;
  wire [39:0]\rx_bit_ctrl_in0[1]_13 ;
  wire [39:0]\rx_bit_ctrl_in1[0]_3 ;
  wire [39:0]\rx_bit_ctrl_in2[0]_5 ;
  wire [39:0]\rx_bit_ctrl_in2[1]_15 ;
  wire [39:0]\rx_bit_ctrl_in3[0]_7 ;
  wire [39:0]\rx_bit_ctrl_in3[1]_17 ;
  wire [39:0]\rx_bit_ctrl_in4[0]_9 ;
  wire [39:0]\rx_bit_ctrl_in4[1]_19 ;
  wire [39:0]\rx_bit_ctrl_in5[0]_11 ;
  wire [39:0]\rx_bit_ctrl_in5[1]_21 ;
  wire [39:0]\rx_bit_ctrl_out0[0]_36 ;
  wire [39:0]\rx_bit_ctrl_out0[1]_48 ;
  wire [39:0]\rx_bit_ctrl_out1[0]_35 ;
  wire [39:0]\rx_bit_ctrl_out2[0]_34 ;
  wire [39:0]\rx_bit_ctrl_out2[1]_47 ;
  wire [39:0]\rx_bit_ctrl_out3[0]_33 ;
  wire [39:0]\rx_bit_ctrl_out3[1]_46 ;
  wire [39:0]\rx_bit_ctrl_out4[0]_32 ;
  wire [39:0]\rx_bit_ctrl_out4[1]_45 ;
  wire [39:0]\rx_bit_ctrl_out5[0]_31 ;
  wire [39:0]\rx_bit_ctrl_out5[1]_44 ;
  wire tristate_q_0;
  wire tristate_q_1;
  wire [39:0]\tx_bit_ctrl_in0[0]_0 ;
  wire [39:0]\tx_bit_ctrl_in0[1]_12 ;
  wire [39:0]\tx_bit_ctrl_in1[0]_2 ;
  wire [39:0]\tx_bit_ctrl_in2[0]_4 ;
  wire [39:0]\tx_bit_ctrl_in2[1]_14 ;
  wire [39:0]\tx_bit_ctrl_in3[0]_6 ;
  wire [39:0]\tx_bit_ctrl_in3[1]_16 ;
  wire [39:0]\tx_bit_ctrl_in4[0]_8 ;
  wire [39:0]\tx_bit_ctrl_in4[1]_18 ;
  wire [39:0]\tx_bit_ctrl_in5[0]_10 ;
  wire [39:0]\tx_bit_ctrl_in5[1]_20 ;
  wire [39:0]\tx_bit_ctrl_in_tri[0]_22 ;
  wire [39:0]\tx_bit_ctrl_in_tri[1]_23 ;
  wire [39:0]\tx_bit_ctrl_out0[0]_30 ;
  wire [39:0]\tx_bit_ctrl_out0[1]_43 ;
  wire [39:0]\tx_bit_ctrl_out1[0]_29 ;
  wire [39:0]\tx_bit_ctrl_out2[0]_28 ;
  wire [39:0]\tx_bit_ctrl_out2[1]_42 ;
  wire [39:0]\tx_bit_ctrl_out3[0]_27 ;
  wire [39:0]\tx_bit_ctrl_out3[1]_41 ;
  wire [39:0]\tx_bit_ctrl_out4[0]_26 ;
  wire [39:0]\tx_bit_ctrl_out4[1]_40 ;
  wire [39:0]\tx_bit_ctrl_out5[0]_25 ;
  wire [39:0]\tx_bit_ctrl_out5[1]_39 ;
  wire [39:0]\tx_bit_ctrl_out_tri[0]_24 ;
  wire [39:0]\tx_bit_ctrl_out_tri[1]_38 ;
  wire [0:0]u_lut1_clb2riu_wr_en_0;
  wire [0:0]xiphy_control;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [15:0]xiphy_control_2;
  wire [5:0]xiphy_control_3;
  wire [0:0]xiphy_control_4;
  wire [15:0]xiphy_riu_or;

  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_802 \I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_1 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_36 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_0 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_30 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[0]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[0]),
        .mcal_DMIn_n(mcal_DMIn_n),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[0]),
        .phy2iob_t(phy2iob_t[0]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_803 \I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in1[0]_3 ),
        .RX_BIT_CTRL_OUT1(\rx_bit_ctrl_out1[0]_35 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in1[0]_2 ),
        .TX_BIT_CTRL_OUT1(\tx_bit_ctrl_out1[0]_29 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[1]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq1(clb2phy_wr_dq1),
        .div_clk(div_clk),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[1]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_804 \I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[0]_5 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_34 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[0]_4 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_28 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[7:0]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[2]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[1]),
        .mcal_DQIn(mcal_DQIn[7:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[2]),
        .phy2iob_t(phy2iob_t[1]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_805 \I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[0]_7 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_33 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[0]_6 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_27 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[15:8]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[3]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[2]),
        .mcal_DQIn(mcal_DQIn[15:8]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[3]),
        .phy2iob_t(phy2iob_t[2]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_806 \I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[0]_9 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_32 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[0]_8 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_26 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[23:16]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[4]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[3]),
        .mcal_DQIn(mcal_DQIn[23:16]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[4]),
        .phy2iob_t(phy2iob_t[3]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_807 \I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[0]_11 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_31 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[0]_10 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_25 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[31:24]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[5]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[4]),
        .mcal_DQIn(mcal_DQIn[31:24]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[5]),
        .phy2iob_t(phy2iob_t[4]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_808 \I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_13 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_48 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_12 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_43 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[6]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq6(clb2phy_wr_dq6),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[5]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[6]),
        .phy2iob_t(phy2iob_t[5]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_809 \I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[1]_15 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_47 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[1]_14 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_42 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[39:32]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[7]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[6]),
        .mcal_DQIn(mcal_DQIn[39:32]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[7]),
        .phy2iob_t(phy2iob_t[6]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_810 \I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[1]_17 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_46 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[1]_16 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_41 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[47:40]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[8]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[7]),
        .mcal_DQIn(mcal_DQIn[47:40]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[8]),
        .phy2iob_t(phy2iob_t[7]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_811 \I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[1]_19 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_45 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[1]_18 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_40 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[55:48]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[9]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[8]),
        .mcal_DQIn(mcal_DQIn[55:48]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[9]),
        .phy2iob_t(phy2iob_t[8]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_812 \I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[1]_21 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_44 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[1]_20 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_39 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[63:56]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[10]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[9]),
        .mcal_DQIn(mcal_DQIn[63:56]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[10]),
        .phy2iob_t(phy2iob_t[9]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_813 \I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_22 ),
        .D(D),
        .Q(Q),
        .RIU_RD_DATA(\riu2clb_rd_data_array[0]_37 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_1 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_36 ),
        .RX_BIT_CTRL_OUT1(\rx_bit_ctrl_out1[0]_35 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_34 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_33 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_32 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_31 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_0 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_30 ),
        .TX_BIT_CTRL_OUT1(\tx_bit_ctrl_out1[0]_29 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_28 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_27 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_26 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_25 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_24 ),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[4:0]),
        .pll_clk(pll_clk),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control),
        .xiphy_control_1(xiphy_control_2),
        .xiphy_control_10(\tx_bit_ctrl_in4[0]_8 ),
        .xiphy_control_11(\tx_bit_ctrl_in5[0]_10 ),
        .xiphy_control_12(xiphy_control_3),
        .xiphy_control_2(\rx_bit_ctrl_in1[0]_3 ),
        .xiphy_control_3(\rx_bit_ctrl_in2[0]_5 ),
        .xiphy_control_4(\rx_bit_ctrl_in3[0]_7 ),
        .xiphy_control_5(\rx_bit_ctrl_in4[0]_9 ),
        .xiphy_control_6(\rx_bit_ctrl_in5[0]_11 ),
        .xiphy_control_7(\tx_bit_ctrl_in1[0]_2 ),
        .xiphy_control_8(\tx_bit_ctrl_in2[0]_4 ),
        .xiphy_control_9(\tx_bit_ctrl_in3[0]_6 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_814 \I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_23 ),
        .RIU_RD_DATA(\riu2clb_rd_data_array[1]_49 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_13 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_48 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_47 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_46 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_45 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_44 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_12 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_43 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_42 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_41 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_40 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_39 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_38 ),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[8:5]),
        .pll_clk(pll_clk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control_0),
        .xiphy_control_1(xiphy_control_1),
        .xiphy_control_10(\tx_bit_ctrl_in4[1]_18 ),
        .xiphy_control_11(\tx_bit_ctrl_in5[1]_20 ),
        .xiphy_control_12(xiphy_control_3),
        .xiphy_control_2(xiphy_control_4),
        .xiphy_control_3(xiphy_control_2),
        .xiphy_control_4(\rx_bit_ctrl_in2[1]_15 ),
        .xiphy_control_5(\rx_bit_ctrl_in3[1]_17 ),
        .xiphy_control_6(\rx_bit_ctrl_in4[1]_19 ),
        .xiphy_control_7(\rx_bit_ctrl_in5[1]_21 ),
        .xiphy_control_8(\tx_bit_ctrl_in2[1]_14 ),
        .xiphy_control_9(\tx_bit_ctrl_in3[1]_16 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_815 \I_TRISTATE[0].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_22 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_24 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_816 \I_TRISTATE[1].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_23 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_38 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_1(tristate_q_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* DONT_TOUCH *) 
  LUT1 #(
    .INIT(2'h2)) 
    u_lut1_clb2riu_wr_en
       (.I0(u_lut1_clb2riu_wr_en_0),
        .O(clb2riu_wr_en_lut));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_817 u_xiphy_riuor
       (.RIU_RD_DATA(\riu2clb_rd_data_array[0]_37 ),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .xiphy_riu_or_0(xiphy_riu_or),
        .xiphy_riu_or_1(\riu2clb_rd_data_array[1]_49 ));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_byte_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper_665
   (phy2iob_q_out_byte,
    phy2iob_t,
    mcal_DMIn_n,
    mcal_DQIn,
    D,
    xiphy_control,
    phy2iob_odt_out_byte,
    xiphy_control_0,
    xiphy_control_1,
    riu2clb_valid_riuclk,
    xiphy_riu_or,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    clb2phy_wr_dq0,
    clb2phy_wr_dq1,
    ch0_mcal_DQOut,
    clb2phy_wr_dq6,
    en_vtc_riuclk,
    pll_clk,
    riu_clk,
    Q,
    SR,
    xiphy_control_2,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_3,
    xiphy_control_4,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    u_lut1_clb2riu_wr_en_0);
  output [10:0]phy2iob_q_out_byte;
  output [9:0]phy2iob_t;
  output [7:0]mcal_DMIn_n;
  output [63:0]mcal_DQIn;
  output [0:0]D;
  output [0:0]xiphy_control;
  output [8:0]phy2iob_odt_out_byte;
  output [0:0]xiphy_control_0;
  output [0:0]xiphy_control_1;
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or;
  input [9:0]iob2phy_d_in_byte;
  input div_clk;
  input [10:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [7:0]clb2phy_wr_dq0;
  input [7:0]clb2phy_wr_dq1;
  input [63:0]ch0_mcal_DQOut;
  input [7:0]clb2phy_wr_dq6;
  input en_vtc_riuclk;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input [0:0]SR;
  input [15:0]xiphy_control_2;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_3;
  input [0:0]xiphy_control_4;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [0:0]u_lut1_clb2riu_wr_en_0;

  wire [0:0]D;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [63:0]ch0_mcal_DQOut;
  wire [10:0]ch0_mcal_clb2phy_fifo_rden;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire [7:0]clb2phy_wr_dq1;
  wire [7:0]clb2phy_wr_dq6;
  wire clb2riu_wr_en_lut;
  wire div_clk;
  wire en_vtc_riuclk;
  wire [9:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [63:0]mcal_DQIn;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [8:0]phy2iob_odt_out_byte;
  wire [10:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;
  wire [0:0]pll_clk;
  wire [15:0]\riu2clb_rd_data_array[0]_191 ;
  wire [15:0]\riu2clb_rd_data_array[1]_203 ;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [39:0]\rx_bit_ctrl_in0[0]_155 ;
  wire [39:0]\rx_bit_ctrl_in0[1]_167 ;
  wire [39:0]\rx_bit_ctrl_in1[0]_157 ;
  wire [39:0]\rx_bit_ctrl_in2[0]_159 ;
  wire [39:0]\rx_bit_ctrl_in2[1]_169 ;
  wire [39:0]\rx_bit_ctrl_in3[0]_161 ;
  wire [39:0]\rx_bit_ctrl_in3[1]_171 ;
  wire [39:0]\rx_bit_ctrl_in4[0]_163 ;
  wire [39:0]\rx_bit_ctrl_in4[1]_173 ;
  wire [39:0]\rx_bit_ctrl_in5[0]_165 ;
  wire [39:0]\rx_bit_ctrl_in5[1]_175 ;
  wire [39:0]\rx_bit_ctrl_out0[0]_190 ;
  wire [39:0]\rx_bit_ctrl_out0[1]_202 ;
  wire [39:0]\rx_bit_ctrl_out1[0]_189 ;
  wire [39:0]\rx_bit_ctrl_out2[0]_188 ;
  wire [39:0]\rx_bit_ctrl_out2[1]_201 ;
  wire [39:0]\rx_bit_ctrl_out3[0]_187 ;
  wire [39:0]\rx_bit_ctrl_out3[1]_200 ;
  wire [39:0]\rx_bit_ctrl_out4[0]_186 ;
  wire [39:0]\rx_bit_ctrl_out4[1]_199 ;
  wire [39:0]\rx_bit_ctrl_out5[0]_185 ;
  wire [39:0]\rx_bit_ctrl_out5[1]_198 ;
  wire tristate_q_0;
  wire tristate_q_1;
  wire [39:0]\tx_bit_ctrl_in0[0]_154 ;
  wire [39:0]\tx_bit_ctrl_in0[1]_166 ;
  wire [39:0]\tx_bit_ctrl_in1[0]_156 ;
  wire [39:0]\tx_bit_ctrl_in2[0]_158 ;
  wire [39:0]\tx_bit_ctrl_in2[1]_168 ;
  wire [39:0]\tx_bit_ctrl_in3[0]_160 ;
  wire [39:0]\tx_bit_ctrl_in3[1]_170 ;
  wire [39:0]\tx_bit_ctrl_in4[0]_162 ;
  wire [39:0]\tx_bit_ctrl_in4[1]_172 ;
  wire [39:0]\tx_bit_ctrl_in5[0]_164 ;
  wire [39:0]\tx_bit_ctrl_in5[1]_174 ;
  wire [39:0]\tx_bit_ctrl_in_tri[0]_176 ;
  wire [39:0]\tx_bit_ctrl_in_tri[1]_177 ;
  wire [39:0]\tx_bit_ctrl_out0[0]_184 ;
  wire [39:0]\tx_bit_ctrl_out0[1]_197 ;
  wire [39:0]\tx_bit_ctrl_out1[0]_183 ;
  wire [39:0]\tx_bit_ctrl_out2[0]_182 ;
  wire [39:0]\tx_bit_ctrl_out2[1]_196 ;
  wire [39:0]\tx_bit_ctrl_out3[0]_181 ;
  wire [39:0]\tx_bit_ctrl_out3[1]_195 ;
  wire [39:0]\tx_bit_ctrl_out4[0]_180 ;
  wire [39:0]\tx_bit_ctrl_out4[1]_194 ;
  wire [39:0]\tx_bit_ctrl_out5[0]_179 ;
  wire [39:0]\tx_bit_ctrl_out5[1]_193 ;
  wire [39:0]\tx_bit_ctrl_out_tri[0]_178 ;
  wire [39:0]\tx_bit_ctrl_out_tri[1]_192 ;
  wire [0:0]u_lut1_clb2riu_wr_en_0;
  wire [0:0]xiphy_control;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [15:0]xiphy_control_2;
  wire [5:0]xiphy_control_3;
  wire [0:0]xiphy_control_4;
  wire [15:0]xiphy_riu_or;

  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_755 \I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_155 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_190 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_154 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_184 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[0]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[0]),
        .mcal_DMIn_n(mcal_DMIn_n),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[0]),
        .phy2iob_t(phy2iob_t[0]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0 \I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in1[0]_157 ),
        .RX_BIT_CTRL_OUT1(\rx_bit_ctrl_out1[0]_189 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in1[0]_156 ),
        .TX_BIT_CTRL_OUT1(\tx_bit_ctrl_out1[0]_183 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[1]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq1(clb2phy_wr_dq1),
        .div_clk(div_clk),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[1]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_756 \I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[0]_159 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_188 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[0]_158 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_182 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[7:0]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[2]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[1]),
        .mcal_DQIn(mcal_DQIn[7:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[2]),
        .phy2iob_t(phy2iob_t[1]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_757 \I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[0]_161 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_187 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[0]_160 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_181 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[15:8]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[3]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[2]),
        .mcal_DQIn(mcal_DQIn[15:8]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[3]),
        .phy2iob_t(phy2iob_t[2]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_758 \I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[0]_163 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_186 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[0]_162 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_180 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[23:16]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[4]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[3]),
        .mcal_DQIn(mcal_DQIn[23:16]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[4]),
        .phy2iob_t(phy2iob_t[3]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_759 \I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[0]_165 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_185 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[0]_164 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_179 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[31:24]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[5]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[4]),
        .mcal_DQIn(mcal_DQIn[31:24]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[5]),
        .phy2iob_t(phy2iob_t[4]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_760 \I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_167 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_202 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_166 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_197 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[6]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq6(clb2phy_wr_dq6),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[5]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[6]),
        .phy2iob_t(phy2iob_t[5]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_761 \I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[1]_169 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_201 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[1]_168 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_196 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[39:32]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[7]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[6]),
        .mcal_DQIn(mcal_DQIn[39:32]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[7]),
        .phy2iob_t(phy2iob_t[6]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_762 \I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[1]_171 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_200 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[1]_170 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_195 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[47:40]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[8]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[7]),
        .mcal_DQIn(mcal_DQIn[47:40]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[8]),
        .phy2iob_t(phy2iob_t[7]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_763 \I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[1]_173 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_199 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[1]_172 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_194 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[55:48]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[9]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[8]),
        .mcal_DQIn(mcal_DQIn[55:48]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[9]),
        .phy2iob_t(phy2iob_t[8]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_764 \I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[1]_175 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_198 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[1]_174 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_193 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[63:56]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[10]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[9]),
        .mcal_DQIn(mcal_DQIn[63:56]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[10]),
        .phy2iob_t(phy2iob_t[9]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_765 \I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_176 ),
        .D(D),
        .Q(Q),
        .RIU_RD_DATA(\riu2clb_rd_data_array[0]_191 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_155 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_190 ),
        .RX_BIT_CTRL_OUT1(\rx_bit_ctrl_out1[0]_189 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_188 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_187 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_186 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_185 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_154 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_184 ),
        .TX_BIT_CTRL_OUT1(\tx_bit_ctrl_out1[0]_183 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_182 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_181 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_180 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_179 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_178 ),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[4:0]),
        .pll_clk(pll_clk),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control),
        .xiphy_control_1(xiphy_control_2),
        .xiphy_control_10(\tx_bit_ctrl_in4[0]_162 ),
        .xiphy_control_11(\tx_bit_ctrl_in5[0]_164 ),
        .xiphy_control_12(xiphy_control_3),
        .xiphy_control_2(\rx_bit_ctrl_in1[0]_157 ),
        .xiphy_control_3(\rx_bit_ctrl_in2[0]_159 ),
        .xiphy_control_4(\rx_bit_ctrl_in3[0]_161 ),
        .xiphy_control_5(\rx_bit_ctrl_in4[0]_163 ),
        .xiphy_control_6(\rx_bit_ctrl_in5[0]_165 ),
        .xiphy_control_7(\tx_bit_ctrl_in1[0]_156 ),
        .xiphy_control_8(\tx_bit_ctrl_in2[0]_158 ),
        .xiphy_control_9(\tx_bit_ctrl_in3[0]_160 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_766 \I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_177 ),
        .RIU_RD_DATA(\riu2clb_rd_data_array[1]_203 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_167 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_202 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_201 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_200 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_199 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_198 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_166 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_197 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_196 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_195 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_194 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_193 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_192 ),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[8:5]),
        .pll_clk(pll_clk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control_0),
        .xiphy_control_1(xiphy_control_1),
        .xiphy_control_10(\tx_bit_ctrl_in4[1]_172 ),
        .xiphy_control_11(\tx_bit_ctrl_in5[1]_174 ),
        .xiphy_control_12(xiphy_control_3),
        .xiphy_control_2(xiphy_control_4),
        .xiphy_control_3(xiphy_control_2),
        .xiphy_control_4(\rx_bit_ctrl_in2[1]_169 ),
        .xiphy_control_5(\rx_bit_ctrl_in3[1]_171 ),
        .xiphy_control_6(\rx_bit_ctrl_in4[1]_173 ),
        .xiphy_control_7(\rx_bit_ctrl_in5[1]_175 ),
        .xiphy_control_8(\tx_bit_ctrl_in2[1]_168 ),
        .xiphy_control_9(\tx_bit_ctrl_in3[1]_170 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_767 \I_TRISTATE[0].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_176 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_178 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_768 \I_TRISTATE[1].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_177 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_192 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_1(tristate_q_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* DONT_TOUCH *) 
  LUT1 #(
    .INIT(2'h2)) 
    u_lut1_clb2riu_wr_en
       (.I0(u_lut1_clb2riu_wr_en_0),
        .O(clb2riu_wr_en_lut));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_769 u_xiphy_riuor
       (.RIU_RD_DATA(\riu2clb_rd_data_array[0]_191 ),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .xiphy_riu_or_0(xiphy_riu_or),
        .xiphy_riu_or_1(\riu2clb_rd_data_array[1]_203 ));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_byte_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized0
   (phy2iob_q_out_byte,
    D,
    xiphy_control,
    xiphy_control_0,
    xiphy_control_1,
    riu2clb_valid_riuclk,
    xiphy_riu_or,
    div_clk,
    clb2phy_tristate_odelay_rst,
    clb2phy_wr_dq0,
    clb2phy_wr_dq1,
    mcal_ADR,
    clb2phy_wr_dq6,
    en_vtc_riuclk,
    pll_clk,
    riu_clk,
    Q,
    SR,
    xiphy_control_2,
    clb2phy_t_b_low,
    xiphy_control_3,
    xiphy_control_4,
    u_lut1_clb2riu_wr_en_0);
  output [9:0]phy2iob_q_out_byte;
  output [0:0]D;
  output [0:0]xiphy_control;
  output [0:0]xiphy_control_0;
  output [0:0]xiphy_control_1;
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [7:0]clb2phy_wr_dq0;
  input [7:0]clb2phy_wr_dq1;
  input [55:0]mcal_ADR;
  input [7:0]clb2phy_wr_dq6;
  input en_vtc_riuclk;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input [0:0]SR;
  input [15:0]xiphy_control_2;
  input [3:0]clb2phy_t_b_low;
  input [5:0]xiphy_control_3;
  input [0:0]xiphy_control_4;
  input [0:0]u_lut1_clb2riu_wr_en_0;

  wire [0:0]D;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [3:0]clb2phy_t_b_low;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire [7:0]clb2phy_wr_dq1;
  wire [7:0]clb2phy_wr_dq6;
  wire clb2riu_wr_en_lut;
  wire div_clk;
  wire en_vtc_riuclk;
  wire [55:0]mcal_ADR;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [9:0]phy2iob_q_out_byte;
  wire [0:0]pll_clk;
  wire [15:0]\riu2clb_rd_data_array[0]_85 ;
  wire [15:0]\riu2clb_rd_data_array[1]_95 ;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [39:0]\rx_bit_ctrl_in0[0]_51 ;
  wire [39:0]\rx_bit_ctrl_in0[1]_63 ;
  wire [39:0]\rx_bit_ctrl_in1[0]_53 ;
  wire [39:0]\rx_bit_ctrl_in2[0]_55 ;
  wire [39:0]\rx_bit_ctrl_in3[0]_57 ;
  wire [39:0]\rx_bit_ctrl_in4[0]_59 ;
  wire [39:0]\rx_bit_ctrl_in4[1]_65 ;
  wire [39:0]\rx_bit_ctrl_in5[0]_61 ;
  wire [39:0]\rx_bit_ctrl_in5[1]_67 ;
  wire [39:0]\rx_bit_ctrl_in6[1]_69 ;
  wire [39:0]\rx_bit_ctrl_out0[0]_84 ;
  wire [39:0]\rx_bit_ctrl_out0[1]_94 ;
  wire [39:0]\rx_bit_ctrl_out1[0]_83 ;
  wire [39:0]\rx_bit_ctrl_out2[0]_82 ;
  wire [39:0]\rx_bit_ctrl_out3[0]_81 ;
  wire [39:0]\rx_bit_ctrl_out4[0]_80 ;
  wire [39:0]\rx_bit_ctrl_out4[1]_93 ;
  wire [39:0]\rx_bit_ctrl_out5[0]_79 ;
  wire [39:0]\rx_bit_ctrl_out5[1]_92 ;
  wire [39:0]\rx_bit_ctrl_out6[1]_91 ;
  wire tristate_q_0;
  wire tristate_q_1;
  wire [39:0]\tx_bit_ctrl_in0[0]_50 ;
  wire [39:0]\tx_bit_ctrl_in0[1]_62 ;
  wire [39:0]\tx_bit_ctrl_in1[0]_52 ;
  wire [39:0]\tx_bit_ctrl_in2[0]_54 ;
  wire [39:0]\tx_bit_ctrl_in3[0]_56 ;
  wire [39:0]\tx_bit_ctrl_in4[0]_58 ;
  wire [39:0]\tx_bit_ctrl_in4[1]_64 ;
  wire [39:0]\tx_bit_ctrl_in5[0]_60 ;
  wire [39:0]\tx_bit_ctrl_in5[1]_66 ;
  wire [39:0]\tx_bit_ctrl_in6[1]_68 ;
  wire [39:0]\tx_bit_ctrl_in_tri[0]_70 ;
  wire [39:0]\tx_bit_ctrl_in_tri[1]_71 ;
  wire [39:0]\tx_bit_ctrl_out0[0]_78 ;
  wire [39:0]\tx_bit_ctrl_out0[1]_90 ;
  wire [39:0]\tx_bit_ctrl_out1[0]_77 ;
  wire [39:0]\tx_bit_ctrl_out2[0]_76 ;
  wire [39:0]\tx_bit_ctrl_out3[0]_75 ;
  wire [39:0]\tx_bit_ctrl_out4[0]_74 ;
  wire [39:0]\tx_bit_ctrl_out4[1]_89 ;
  wire [39:0]\tx_bit_ctrl_out5[0]_73 ;
  wire [39:0]\tx_bit_ctrl_out5[1]_88 ;
  wire [39:0]\tx_bit_ctrl_out6[1]_87 ;
  wire [39:0]\tx_bit_ctrl_out_tri[0]_72 ;
  wire [39:0]\tx_bit_ctrl_out_tri[1]_86 ;
  wire [0:0]u_lut1_clb2riu_wr_en_0;
  wire [0:0]xiphy_control;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [15:0]xiphy_control_2;
  wire [5:0]xiphy_control_3;
  wire [0:0]xiphy_control_4;
  wire [15:0]xiphy_riu_or;

  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_787 \I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_51 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_84 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_50 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_78 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0),
        .div_clk(div_clk),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[0]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_788 \I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in1[0]_53 ),
        .RX_BIT_CTRL_OUT1(\rx_bit_ctrl_out1[0]_83 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in1[0]_52 ),
        .TX_BIT_CTRL_OUT1(\tx_bit_ctrl_out1[0]_77 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq1(clb2phy_wr_dq1),
        .div_clk(div_clk),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[1]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_789 \I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[0]_55 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_82 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[0]_54 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_76 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_ADR(mcal_ADR[7:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[2]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_790 \I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[0]_57 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_81 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[0]_56 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_75 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_ADR(mcal_ADR[15:8]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[3]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_791 \I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[0]_59 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_80 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[0]_58 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_74 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_ADR(mcal_ADR[23:16]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[4]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_792 \I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[0]_61 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_79 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[0]_60 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_73 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_ADR(mcal_ADR[31:24]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[5]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_793 \I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_63 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_94 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_62 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_90 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq6(clb2phy_wr_dq6),
        .div_clk(div_clk),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[6]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_794 \I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[1]_65 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_93 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[1]_64 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_89 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_ADR(mcal_ADR[39:32]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[7]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_795 \I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[1]_67 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_92 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[1]_66 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_88 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_ADR(mcal_ADR[47:40]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[8]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_796 \I_BITSLICE_UPPER[6].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in6[1]_69 ),
        .RX_BIT_CTRL_OUT6(\rx_bit_ctrl_out6[1]_91 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in6[1]_68 ),
        .TX_BIT_CTRL_OUT6(\tx_bit_ctrl_out6[1]_87 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_ADR(mcal_ADR[55:48]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[9]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized1_797 \I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_70 ),
        .D(D),
        .Q(Q),
        .RIU_RD_DATA(\riu2clb_rd_data_array[0]_85 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_51 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_84 ),
        .RX_BIT_CTRL_OUT1(\rx_bit_ctrl_out1[0]_83 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_82 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_81 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_80 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_79 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_50 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_78 ),
        .TX_BIT_CTRL_OUT1(\tx_bit_ctrl_out1[0]_77 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_76 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_75 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_74 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_73 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_72 ),
        .clb2phy_t_b_low(clb2phy_t_b_low),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .pll_clk(pll_clk),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control),
        .xiphy_control_1(xiphy_control_2),
        .xiphy_control_10(\tx_bit_ctrl_in4[0]_58 ),
        .xiphy_control_11(\tx_bit_ctrl_in5[0]_60 ),
        .xiphy_control_12(xiphy_control_3),
        .xiphy_control_2(\rx_bit_ctrl_in1[0]_53 ),
        .xiphy_control_3(\rx_bit_ctrl_in2[0]_55 ),
        .xiphy_control_4(\rx_bit_ctrl_in3[0]_57 ),
        .xiphy_control_5(\rx_bit_ctrl_in4[0]_59 ),
        .xiphy_control_6(\rx_bit_ctrl_in5[0]_61 ),
        .xiphy_control_7(\tx_bit_ctrl_in1[0]_52 ),
        .xiphy_control_8(\tx_bit_ctrl_in2[0]_54 ),
        .xiphy_control_9(\tx_bit_ctrl_in3[0]_56 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized1_798 \I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_71 ),
        .RIU_RD_DATA(\riu2clb_rd_data_array[1]_95 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_63 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_94 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_93 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_92 ),
        .RX_BIT_CTRL_OUT6(\rx_bit_ctrl_out6[1]_91 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_62 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_90 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_89 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_88 ),
        .TX_BIT_CTRL_OUT6(\tx_bit_ctrl_out6[1]_87 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_86 ),
        .clb2phy_t_b_low(clb2phy_t_b_low),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .pll_clk(pll_clk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control_0),
        .xiphy_control_1(xiphy_control_1),
        .xiphy_control_10(xiphy_control_3),
        .xiphy_control_2(xiphy_control_4),
        .xiphy_control_3(xiphy_control_2),
        .xiphy_control_4(\rx_bit_ctrl_in4[1]_65 ),
        .xiphy_control_5(\rx_bit_ctrl_in5[1]_67 ),
        .xiphy_control_6(\rx_bit_ctrl_in6[1]_69 ),
        .xiphy_control_7(\tx_bit_ctrl_in4[1]_64 ),
        .xiphy_control_8(\tx_bit_ctrl_in5[1]_66 ),
        .xiphy_control_9(\tx_bit_ctrl_in6[1]_68 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_799 \I_TRISTATE[0].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_70 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_72 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_800 \I_TRISTATE[1].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_71 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_86 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_1(tristate_q_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* DONT_TOUCH *) 
  LUT1 #(
    .INIT(2'h2)) 
    u_lut1_clb2riu_wr_en
       (.I0(u_lut1_clb2riu_wr_en_0),
        .O(clb2riu_wr_en_lut));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_801 u_xiphy_riuor
       (.RIU_RD_DATA(\riu2clb_rd_data_array[0]_85 ),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .xiphy_riu_or_0(xiphy_riu_or),
        .xiphy_riu_or_1(\riu2clb_rd_data_array[1]_95 ));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_byte_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized1
   (phy2iob_q_out_byte,
    D,
    xiphy_control,
    xiphy_control_0,
    xiphy_control_1,
    riu2clb_valid_riuclk,
    xiphy_riu_or,
    div_clk,
    clb2phy_tristate_odelay_rst,
    clb2phy_wr_dq0,
    clb2phy_wr_dq1,
    mcal_ADR,
    clb2phy_wr_dq6,
    mcal_BA,
    mcal_BG,
    mcal_CS_n,
    mcal_CKE,
    en_vtc_riuclk,
    pll_clk,
    riu_clk,
    Q,
    SR,
    xiphy_control_2,
    clb2phy_t_b_low,
    xiphy_control_3,
    xiphy_control_4,
    u_lut1_clb2riu_wr_en_0);
  output [12:0]phy2iob_q_out_byte;
  output [0:0]D;
  output [0:0]xiphy_control;
  output [0:0]xiphy_control_0;
  output [0:0]xiphy_control_1;
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or;
  input div_clk;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [7:0]clb2phy_wr_dq0;
  input [7:0]clb2phy_wr_dq1;
  input [39:0]mcal_ADR;
  input [7:0]clb2phy_wr_dq6;
  input [15:0]mcal_BA;
  input [7:0]mcal_BG;
  input [7:0]mcal_CS_n;
  input [7:0]mcal_CKE;
  input en_vtc_riuclk;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input [0:0]SR;
  input [15:0]xiphy_control_2;
  input [3:0]clb2phy_t_b_low;
  input [5:0]xiphy_control_3;
  input [0:0]xiphy_control_4;
  input [0:0]u_lut1_clb2riu_wr_en_0;

  wire [0:0]D;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [3:0]clb2phy_t_b_low;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire [7:0]clb2phy_wr_dq1;
  wire [7:0]clb2phy_wr_dq6;
  wire clb2riu_wr_en_lut;
  wire div_clk;
  wire en_vtc_riuclk;
  wire [39:0]mcal_ADR;
  wire [15:0]mcal_BA;
  wire [7:0]mcal_BG;
  wire [7:0]mcal_CKE;
  wire [7:0]mcal_CS_n;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [12:0]phy2iob_q_out_byte;
  wire [0:0]pll_clk;
  wire [15:0]\riu2clb_rd_data_array[0]_137 ;
  wire [15:0]\riu2clb_rd_data_array[1]_153 ;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [39:0]\rx_bit_ctrl_in0[0]_97 ;
  wire [39:0]\rx_bit_ctrl_in0[1]_109 ;
  wire [39:0]\rx_bit_ctrl_in1[0]_99 ;
  wire [39:0]\rx_bit_ctrl_in1[1]_111 ;
  wire [39:0]\rx_bit_ctrl_in2[0]_101 ;
  wire [39:0]\rx_bit_ctrl_in2[1]_113 ;
  wire [39:0]\rx_bit_ctrl_in3[0]_103 ;
  wire [39:0]\rx_bit_ctrl_in3[1]_115 ;
  wire [39:0]\rx_bit_ctrl_in4[0]_105 ;
  wire [39:0]\rx_bit_ctrl_in4[1]_117 ;
  wire [39:0]\rx_bit_ctrl_in5[0]_107 ;
  wire [39:0]\rx_bit_ctrl_in5[1]_119 ;
  wire [39:0]\rx_bit_ctrl_in6[1]_121 ;
  wire [39:0]\rx_bit_ctrl_out0[0]_136 ;
  wire [39:0]\rx_bit_ctrl_out0[1]_152 ;
  wire [39:0]\rx_bit_ctrl_out1[0]_135 ;
  wire [39:0]\rx_bit_ctrl_out1[1]_151 ;
  wire [39:0]\rx_bit_ctrl_out2[0]_134 ;
  wire [39:0]\rx_bit_ctrl_out2[1]_150 ;
  wire [39:0]\rx_bit_ctrl_out3[0]_133 ;
  wire [39:0]\rx_bit_ctrl_out3[1]_149 ;
  wire [39:0]\rx_bit_ctrl_out4[0]_132 ;
  wire [39:0]\rx_bit_ctrl_out4[1]_148 ;
  wire [39:0]\rx_bit_ctrl_out5[0]_131 ;
  wire [39:0]\rx_bit_ctrl_out5[1]_147 ;
  wire [39:0]\rx_bit_ctrl_out6[1]_146 ;
  wire tristate_q_0;
  wire tristate_q_1;
  wire [39:0]\tx_bit_ctrl_in0[0]_96 ;
  wire [39:0]\tx_bit_ctrl_in0[1]_108 ;
  wire [39:0]\tx_bit_ctrl_in1[0]_98 ;
  wire [39:0]\tx_bit_ctrl_in1[1]_110 ;
  wire [39:0]\tx_bit_ctrl_in2[0]_100 ;
  wire [39:0]\tx_bit_ctrl_in2[1]_112 ;
  wire [39:0]\tx_bit_ctrl_in3[0]_102 ;
  wire [39:0]\tx_bit_ctrl_in3[1]_114 ;
  wire [39:0]\tx_bit_ctrl_in4[0]_104 ;
  wire [39:0]\tx_bit_ctrl_in4[1]_116 ;
  wire [39:0]\tx_bit_ctrl_in5[0]_106 ;
  wire [39:0]\tx_bit_ctrl_in5[1]_118 ;
  wire [39:0]\tx_bit_ctrl_in6[1]_120 ;
  wire [39:0]\tx_bit_ctrl_in_tri[0]_122 ;
  wire [39:0]\tx_bit_ctrl_in_tri[1]_123 ;
  wire [39:0]\tx_bit_ctrl_out0[0]_130 ;
  wire [39:0]\tx_bit_ctrl_out0[1]_145 ;
  wire [39:0]\tx_bit_ctrl_out1[0]_129 ;
  wire [39:0]\tx_bit_ctrl_out1[1]_144 ;
  wire [39:0]\tx_bit_ctrl_out2[0]_128 ;
  wire [39:0]\tx_bit_ctrl_out2[1]_143 ;
  wire [39:0]\tx_bit_ctrl_out3[0]_127 ;
  wire [39:0]\tx_bit_ctrl_out3[1]_142 ;
  wire [39:0]\tx_bit_ctrl_out4[0]_126 ;
  wire [39:0]\tx_bit_ctrl_out4[1]_141 ;
  wire [39:0]\tx_bit_ctrl_out5[0]_125 ;
  wire [39:0]\tx_bit_ctrl_out5[1]_140 ;
  wire [39:0]\tx_bit_ctrl_out6[1]_139 ;
  wire [39:0]\tx_bit_ctrl_out_tri[0]_124 ;
  wire [39:0]\tx_bit_ctrl_out_tri[1]_138 ;
  wire [0:0]u_lut1_clb2riu_wr_en_0;
  wire [0:0]xiphy_control;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [15:0]xiphy_control_2;
  wire [5:0]xiphy_control_3;
  wire [0:0]xiphy_control_4;
  wire [15:0]xiphy_riu_or;

  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_770 \I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_97 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_136 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_96 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_130 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0),
        .div_clk(div_clk),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[0]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_771 \I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in1[0]_99 ),
        .RX_BIT_CTRL_OUT1(\rx_bit_ctrl_out1[0]_135 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in1[0]_98 ),
        .TX_BIT_CTRL_OUT1(\tx_bit_ctrl_out1[0]_129 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq1(clb2phy_wr_dq1),
        .div_clk(div_clk),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[1]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_772 \I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[0]_101 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_134 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[0]_100 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_128 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_ADR(mcal_ADR[7:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[2]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_773 \I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[0]_103 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_133 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[0]_102 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_127 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_ADR(mcal_ADR[15:8]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[3]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_774 \I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[0]_105 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_132 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[0]_104 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_126 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_ADR(mcal_ADR[23:16]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[4]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_775 \I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[0]_107 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_131 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[0]_106 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_125 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_ADR(mcal_ADR[31:24]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[5]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_776 \I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_109 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_152 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_108 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_145 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq6(clb2phy_wr_dq6),
        .div_clk(div_clk),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[6]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_777 \I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in1[1]_111 ),
        .RX_BIT_CTRL_OUT1(\rx_bit_ctrl_out1[1]_151 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in1[1]_110 ),
        .TX_BIT_CTRL_OUT1(\tx_bit_ctrl_out1[1]_144 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_ADR(mcal_ADR[39:32]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[7]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_778 \I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[1]_113 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_150 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[1]_112 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_143 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_BA(mcal_BA[7:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[8]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_779 \I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[1]_115 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_149 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[1]_114 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_142 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_BA(mcal_BA[15:8]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[9]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_780 \I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[1]_117 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_148 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[1]_116 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_141 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_BG(mcal_BG),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[10]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_781 \I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[1]_119 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_147 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[1]_118 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_140 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_CS_n(mcal_CS_n),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[11]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized0_782 \I_BITSLICE_UPPER[6].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in6[1]_121 ),
        .RX_BIT_CTRL_OUT6(\rx_bit_ctrl_out6[1]_146 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in6[1]_120 ),
        .TX_BIT_CTRL_OUT6(\tx_bit_ctrl_out6[1]_139 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .mcal_CKE(mcal_CKE),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[12]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized1 \I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_122 ),
        .D(D),
        .Q(Q),
        .RIU_RD_DATA(\riu2clb_rd_data_array[0]_137 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_97 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_136 ),
        .RX_BIT_CTRL_OUT1(\rx_bit_ctrl_out1[0]_135 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_134 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_133 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_132 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_131 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_96 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_130 ),
        .TX_BIT_CTRL_OUT1(\tx_bit_ctrl_out1[0]_129 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_128 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_127 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_126 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_125 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_124 ),
        .clb2phy_t_b_low(clb2phy_t_b_low),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .pll_clk(pll_clk),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control),
        .xiphy_control_1(xiphy_control_2),
        .xiphy_control_10(\tx_bit_ctrl_in4[0]_104 ),
        .xiphy_control_11(\tx_bit_ctrl_in5[0]_106 ),
        .xiphy_control_12(xiphy_control_3),
        .xiphy_control_2(\rx_bit_ctrl_in1[0]_99 ),
        .xiphy_control_3(\rx_bit_ctrl_in2[0]_101 ),
        .xiphy_control_4(\rx_bit_ctrl_in3[0]_103 ),
        .xiphy_control_5(\rx_bit_ctrl_in4[0]_105 ),
        .xiphy_control_6(\rx_bit_ctrl_in5[0]_107 ),
        .xiphy_control_7(\tx_bit_ctrl_in1[0]_98 ),
        .xiphy_control_8(\tx_bit_ctrl_in2[0]_100 ),
        .xiphy_control_9(\tx_bit_ctrl_in3[0]_102 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized1_783 \I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_123 ),
        .RIU_RD_DATA(\riu2clb_rd_data_array[1]_153 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_109 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_152 ),
        .RX_BIT_CTRL_OUT1(\rx_bit_ctrl_out1[1]_151 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_150 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_149 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_148 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_147 ),
        .RX_BIT_CTRL_OUT6(\rx_bit_ctrl_out6[1]_146 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_108 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_145 ),
        .TX_BIT_CTRL_OUT1(\tx_bit_ctrl_out1[1]_144 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_143 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_142 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_141 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_140 ),
        .TX_BIT_CTRL_OUT6(\tx_bit_ctrl_out6[1]_139 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_138 ),
        .clb2phy_t_b_low(clb2phy_t_b_low),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .pll_clk(pll_clk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control_0),
        .xiphy_control_1(xiphy_control_1),
        .xiphy_control_10(\tx_bit_ctrl_in1[1]_110 ),
        .xiphy_control_11(\tx_bit_ctrl_in2[1]_112 ),
        .xiphy_control_12(\tx_bit_ctrl_in3[1]_114 ),
        .xiphy_control_13(\tx_bit_ctrl_in4[1]_116 ),
        .xiphy_control_14(\tx_bit_ctrl_in5[1]_118 ),
        .xiphy_control_15(\tx_bit_ctrl_in6[1]_120 ),
        .xiphy_control_16(xiphy_control_3),
        .xiphy_control_2(xiphy_control_4),
        .xiphy_control_3(xiphy_control_2),
        .xiphy_control_4(\rx_bit_ctrl_in1[1]_111 ),
        .xiphy_control_5(\rx_bit_ctrl_in2[1]_113 ),
        .xiphy_control_6(\rx_bit_ctrl_in3[1]_115 ),
        .xiphy_control_7(\rx_bit_ctrl_in4[1]_117 ),
        .xiphy_control_8(\rx_bit_ctrl_in5[1]_119 ),
        .xiphy_control_9(\rx_bit_ctrl_in6[1]_121 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_784 \I_TRISTATE[0].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_122 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_124 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_785 \I_TRISTATE[1].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_123 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_138 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_1(tristate_q_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* DONT_TOUCH *) 
  LUT1 #(
    .INIT(2'h2)) 
    u_lut1_clb2riu_wr_en
       (.I0(u_lut1_clb2riu_wr_en_0),
        .O(clb2riu_wr_en_lut));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_786 u_xiphy_riuor
       (.RIU_RD_DATA(\riu2clb_rd_data_array[0]_137 ),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .xiphy_riu_or_0(xiphy_riu_or),
        .xiphy_riu_or_1(\riu2clb_rd_data_array[1]_153 ));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_byte_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized2
   (phy2iob_q_out_byte,
    phy2iob_t,
    mcal_DMIn_n,
    mcal_DQIn,
    D,
    xiphy_control,
    phy2iob_odt_out_byte,
    xiphy_control_0,
    xiphy_control_1,
    riu2clb_valid_riuclk,
    xiphy_riu_or,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    clb2phy_wr_dq0,
    ch0_mcal_DQOut,
    clb2phy_wr_dq6,
    en_vtc_riuclk,
    pll_clk,
    riu_clk,
    Q,
    SR,
    xiphy_control_2,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_3,
    xiphy_control_4,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    u_lut1_clb2riu_wr_en_0);
  output [9:0]phy2iob_q_out_byte;
  output [9:0]phy2iob_t;
  output [7:0]mcal_DMIn_n;
  output [63:0]mcal_DQIn;
  output [0:0]D;
  output [0:0]xiphy_control;
  output [8:0]phy2iob_odt_out_byte;
  output [0:0]xiphy_control_0;
  output [0:0]xiphy_control_1;
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or;
  input [9:0]iob2phy_d_in_byte;
  input div_clk;
  input [9:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [7:0]clb2phy_wr_dq0;
  input [63:0]ch0_mcal_DQOut;
  input [7:0]clb2phy_wr_dq6;
  input en_vtc_riuclk;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input [0:0]SR;
  input [15:0]xiphy_control_2;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_3;
  input [0:0]xiphy_control_4;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [0:0]u_lut1_clb2riu_wr_en_0;

  wire [0:0]D;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [63:0]ch0_mcal_DQOut;
  wire [9:0]ch0_mcal_clb2phy_fifo_rden;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire [7:0]clb2phy_wr_dq6;
  wire clb2riu_wr_en_lut;
  wire div_clk;
  wire en_vtc_riuclk;
  wire [9:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [63:0]mcal_DQIn;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [8:0]phy2iob_odt_out_byte;
  wire [9:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;
  wire [0:0]pll_clk;
  wire [15:0]\riu2clb_rd_data_array[0]_237 ;
  wire [15:0]\riu2clb_rd_data_array[1]_249 ;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [39:0]\rx_bit_ctrl_in0[0]_205 ;
  wire [39:0]\rx_bit_ctrl_in0[1]_215 ;
  wire [39:0]\rx_bit_ctrl_in2[0]_207 ;
  wire [39:0]\rx_bit_ctrl_in2[1]_217 ;
  wire [39:0]\rx_bit_ctrl_in3[0]_209 ;
  wire [39:0]\rx_bit_ctrl_in3[1]_219 ;
  wire [39:0]\rx_bit_ctrl_in4[0]_211 ;
  wire [39:0]\rx_bit_ctrl_in4[1]_221 ;
  wire [39:0]\rx_bit_ctrl_in5[0]_213 ;
  wire [39:0]\rx_bit_ctrl_in5[1]_223 ;
  wire [39:0]\rx_bit_ctrl_out0[0]_236 ;
  wire [39:0]\rx_bit_ctrl_out0[1]_248 ;
  wire [39:0]\rx_bit_ctrl_out2[0]_235 ;
  wire [39:0]\rx_bit_ctrl_out2[1]_247 ;
  wire [39:0]\rx_bit_ctrl_out3[0]_234 ;
  wire [39:0]\rx_bit_ctrl_out3[1]_246 ;
  wire [39:0]\rx_bit_ctrl_out4[0]_233 ;
  wire [39:0]\rx_bit_ctrl_out4[1]_245 ;
  wire [39:0]\rx_bit_ctrl_out5[0]_232 ;
  wire [39:0]\rx_bit_ctrl_out5[1]_244 ;
  wire tristate_q_0;
  wire tristate_q_1;
  wire [39:0]\tx_bit_ctrl_in0[0]_204 ;
  wire [39:0]\tx_bit_ctrl_in0[1]_214 ;
  wire [39:0]\tx_bit_ctrl_in2[0]_206 ;
  wire [39:0]\tx_bit_ctrl_in2[1]_216 ;
  wire [39:0]\tx_bit_ctrl_in3[0]_208 ;
  wire [39:0]\tx_bit_ctrl_in3[1]_218 ;
  wire [39:0]\tx_bit_ctrl_in4[0]_210 ;
  wire [39:0]\tx_bit_ctrl_in4[1]_220 ;
  wire [39:0]\tx_bit_ctrl_in5[0]_212 ;
  wire [39:0]\tx_bit_ctrl_in5[1]_222 ;
  wire [39:0]\tx_bit_ctrl_in_tri[0]_224 ;
  wire [39:0]\tx_bit_ctrl_in_tri[1]_225 ;
  wire [39:0]\tx_bit_ctrl_out0[0]_231 ;
  wire [39:0]\tx_bit_ctrl_out0[1]_243 ;
  wire [39:0]\tx_bit_ctrl_out2[0]_230 ;
  wire [39:0]\tx_bit_ctrl_out2[1]_242 ;
  wire [39:0]\tx_bit_ctrl_out3[0]_229 ;
  wire [39:0]\tx_bit_ctrl_out3[1]_241 ;
  wire [39:0]\tx_bit_ctrl_out4[0]_228 ;
  wire [39:0]\tx_bit_ctrl_out4[1]_240 ;
  wire [39:0]\tx_bit_ctrl_out5[0]_227 ;
  wire [39:0]\tx_bit_ctrl_out5[1]_239 ;
  wire [39:0]\tx_bit_ctrl_out_tri[0]_226 ;
  wire [39:0]\tx_bit_ctrl_out_tri[1]_238 ;
  wire [0:0]u_lut1_clb2riu_wr_en_0;
  wire [0:0]xiphy_control;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [15:0]xiphy_control_2;
  wire [5:0]xiphy_control_3;
  wire [0:0]xiphy_control_4;
  wire [15:0]xiphy_riu_or;

  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_740 \I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_205 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_236 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_204 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_231 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[0]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[0]),
        .mcal_DMIn_n(mcal_DMIn_n),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[0]),
        .phy2iob_t(phy2iob_t[0]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_741 \I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[0]_207 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_235 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[0]_206 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_230 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[7:0]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[1]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[1]),
        .mcal_DQIn(mcal_DQIn[7:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[1]),
        .phy2iob_t(phy2iob_t[1]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_742 \I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[0]_209 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_234 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[0]_208 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_229 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[15:8]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[2]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[2]),
        .mcal_DQIn(mcal_DQIn[15:8]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[2]),
        .phy2iob_t(phy2iob_t[2]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_743 \I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[0]_211 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_233 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[0]_210 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_228 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[23:16]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[3]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[3]),
        .mcal_DQIn(mcal_DQIn[23:16]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[3]),
        .phy2iob_t(phy2iob_t[3]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_744 \I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[0]_213 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_232 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[0]_212 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_227 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[31:24]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[4]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[4]),
        .mcal_DQIn(mcal_DQIn[31:24]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[4]),
        .phy2iob_t(phy2iob_t[4]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_745 \I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_215 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_248 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_214 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_243 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[5]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq6(clb2phy_wr_dq6),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[5]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[5]),
        .phy2iob_t(phy2iob_t[5]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_746 \I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[1]_217 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_247 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[1]_216 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_242 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[39:32]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[6]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[6]),
        .mcal_DQIn(mcal_DQIn[39:32]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[6]),
        .phy2iob_t(phy2iob_t[6]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_747 \I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[1]_219 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_246 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[1]_218 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_241 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[47:40]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[7]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[7]),
        .mcal_DQIn(mcal_DQIn[47:40]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[7]),
        .phy2iob_t(phy2iob_t[7]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_748 \I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[1]_221 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_245 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[1]_220 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_240 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[55:48]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[8]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[8]),
        .mcal_DQIn(mcal_DQIn[55:48]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[8]),
        .phy2iob_t(phy2iob_t[8]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_749 \I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[1]_223 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_244 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[1]_222 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_239 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[63:56]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[9]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[9]),
        .mcal_DQIn(mcal_DQIn[63:56]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[9]),
        .phy2iob_t(phy2iob_t[9]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_750 \I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_224 ),
        .D(D),
        .Q(Q),
        .RIU_RD_DATA(\riu2clb_rd_data_array[0]_237 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_205 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_236 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_235 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_234 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_233 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_232 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_204 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_231 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_230 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_229 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_228 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_227 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_226 ),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[4:0]),
        .pll_clk(pll_clk),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control),
        .xiphy_control_1(xiphy_control_2),
        .xiphy_control_10(xiphy_control_3),
        .xiphy_control_2(\rx_bit_ctrl_in2[0]_207 ),
        .xiphy_control_3(\rx_bit_ctrl_in3[0]_209 ),
        .xiphy_control_4(\rx_bit_ctrl_in4[0]_211 ),
        .xiphy_control_5(\rx_bit_ctrl_in5[0]_213 ),
        .xiphy_control_6(\tx_bit_ctrl_in2[0]_206 ),
        .xiphy_control_7(\tx_bit_ctrl_in3[0]_208 ),
        .xiphy_control_8(\tx_bit_ctrl_in4[0]_210 ),
        .xiphy_control_9(\tx_bit_ctrl_in5[0]_212 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_751 \I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_225 ),
        .RIU_RD_DATA(\riu2clb_rd_data_array[1]_249 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_215 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_248 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_247 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_246 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_245 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_244 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_214 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_243 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_242 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_241 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_240 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_239 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_238 ),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[8:5]),
        .pll_clk(pll_clk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control_0),
        .xiphy_control_1(xiphy_control_1),
        .xiphy_control_10(\tx_bit_ctrl_in4[1]_220 ),
        .xiphy_control_11(\tx_bit_ctrl_in5[1]_222 ),
        .xiphy_control_12(xiphy_control_3),
        .xiphy_control_2(xiphy_control_4),
        .xiphy_control_3(xiphy_control_2),
        .xiphy_control_4(\rx_bit_ctrl_in2[1]_217 ),
        .xiphy_control_5(\rx_bit_ctrl_in3[1]_219 ),
        .xiphy_control_6(\rx_bit_ctrl_in4[1]_221 ),
        .xiphy_control_7(\rx_bit_ctrl_in5[1]_223 ),
        .xiphy_control_8(\tx_bit_ctrl_in2[1]_216 ),
        .xiphy_control_9(\tx_bit_ctrl_in3[1]_218 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_752 \I_TRISTATE[0].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_224 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_226 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_753 \I_TRISTATE[1].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_225 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_238 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_1(tristate_q_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* DONT_TOUCH *) 
  LUT1 #(
    .INIT(2'h2)) 
    u_lut1_clb2riu_wr_en
       (.I0(u_lut1_clb2riu_wr_en_0),
        .O(clb2riu_wr_en_lut));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_754 u_xiphy_riuor
       (.RIU_RD_DATA(\riu2clb_rd_data_array[0]_237 ),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .xiphy_riu_or_0(xiphy_riu_or),
        .xiphy_riu_or_1(\riu2clb_rd_data_array[1]_249 ));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_byte_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized2_666
   (phy2iob_q_out_byte,
    phy2iob_t,
    mcal_DMIn_n,
    mcal_DQIn,
    D,
    xiphy_control,
    phy2iob_odt_out_byte,
    xiphy_control_0,
    xiphy_control_1,
    riu2clb_valid_riuclk,
    xiphy_riu_or,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    clb2phy_wr_dq0,
    ch0_mcal_DQOut,
    clb2phy_wr_dq6,
    en_vtc_riuclk,
    pll_clk,
    riu_clk,
    Q,
    SR,
    xiphy_control_2,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_3,
    xiphy_control_4,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    u_lut1_clb2riu_wr_en_0);
  output [9:0]phy2iob_q_out_byte;
  output [9:0]phy2iob_t;
  output [7:0]mcal_DMIn_n;
  output [63:0]mcal_DQIn;
  output [0:0]D;
  output [0:0]xiphy_control;
  output [8:0]phy2iob_odt_out_byte;
  output [0:0]xiphy_control_0;
  output [0:0]xiphy_control_1;
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or;
  input [9:0]iob2phy_d_in_byte;
  input div_clk;
  input [9:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [7:0]clb2phy_wr_dq0;
  input [63:0]ch0_mcal_DQOut;
  input [7:0]clb2phy_wr_dq6;
  input en_vtc_riuclk;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input [0:0]SR;
  input [15:0]xiphy_control_2;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_3;
  input [0:0]xiphy_control_4;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [0:0]u_lut1_clb2riu_wr_en_0;

  wire [0:0]D;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [63:0]ch0_mcal_DQOut;
  wire [9:0]ch0_mcal_clb2phy_fifo_rden;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire [7:0]clb2phy_wr_dq6;
  wire clb2riu_wr_en_lut;
  wire div_clk;
  wire en_vtc_riuclk;
  wire [9:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [63:0]mcal_DQIn;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [8:0]phy2iob_odt_out_byte;
  wire [9:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;
  wire [0:0]pll_clk;
  wire [15:0]\riu2clb_rd_data_array[0]_283 ;
  wire [15:0]\riu2clb_rd_data_array[1]_295 ;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [39:0]\rx_bit_ctrl_in0[0]_251 ;
  wire [39:0]\rx_bit_ctrl_in0[1]_261 ;
  wire [39:0]\rx_bit_ctrl_in2[0]_253 ;
  wire [39:0]\rx_bit_ctrl_in2[1]_263 ;
  wire [39:0]\rx_bit_ctrl_in3[0]_255 ;
  wire [39:0]\rx_bit_ctrl_in3[1]_265 ;
  wire [39:0]\rx_bit_ctrl_in4[0]_257 ;
  wire [39:0]\rx_bit_ctrl_in4[1]_267 ;
  wire [39:0]\rx_bit_ctrl_in5[0]_259 ;
  wire [39:0]\rx_bit_ctrl_in5[1]_269 ;
  wire [39:0]\rx_bit_ctrl_out0[0]_282 ;
  wire [39:0]\rx_bit_ctrl_out0[1]_294 ;
  wire [39:0]\rx_bit_ctrl_out2[0]_281 ;
  wire [39:0]\rx_bit_ctrl_out2[1]_293 ;
  wire [39:0]\rx_bit_ctrl_out3[0]_280 ;
  wire [39:0]\rx_bit_ctrl_out3[1]_292 ;
  wire [39:0]\rx_bit_ctrl_out4[0]_279 ;
  wire [39:0]\rx_bit_ctrl_out4[1]_291 ;
  wire [39:0]\rx_bit_ctrl_out5[0]_278 ;
  wire [39:0]\rx_bit_ctrl_out5[1]_290 ;
  wire tristate_q_0;
  wire tristate_q_1;
  wire [39:0]\tx_bit_ctrl_in0[0]_250 ;
  wire [39:0]\tx_bit_ctrl_in0[1]_260 ;
  wire [39:0]\tx_bit_ctrl_in2[0]_252 ;
  wire [39:0]\tx_bit_ctrl_in2[1]_262 ;
  wire [39:0]\tx_bit_ctrl_in3[0]_254 ;
  wire [39:0]\tx_bit_ctrl_in3[1]_264 ;
  wire [39:0]\tx_bit_ctrl_in4[0]_256 ;
  wire [39:0]\tx_bit_ctrl_in4[1]_266 ;
  wire [39:0]\tx_bit_ctrl_in5[0]_258 ;
  wire [39:0]\tx_bit_ctrl_in5[1]_268 ;
  wire [39:0]\tx_bit_ctrl_in_tri[0]_270 ;
  wire [39:0]\tx_bit_ctrl_in_tri[1]_271 ;
  wire [39:0]\tx_bit_ctrl_out0[0]_277 ;
  wire [39:0]\tx_bit_ctrl_out0[1]_289 ;
  wire [39:0]\tx_bit_ctrl_out2[0]_276 ;
  wire [39:0]\tx_bit_ctrl_out2[1]_288 ;
  wire [39:0]\tx_bit_ctrl_out3[0]_275 ;
  wire [39:0]\tx_bit_ctrl_out3[1]_287 ;
  wire [39:0]\tx_bit_ctrl_out4[0]_274 ;
  wire [39:0]\tx_bit_ctrl_out4[1]_286 ;
  wire [39:0]\tx_bit_ctrl_out5[0]_273 ;
  wire [39:0]\tx_bit_ctrl_out5[1]_285 ;
  wire [39:0]\tx_bit_ctrl_out_tri[0]_272 ;
  wire [39:0]\tx_bit_ctrl_out_tri[1]_284 ;
  wire [0:0]u_lut1_clb2riu_wr_en_0;
  wire [0:0]xiphy_control;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [15:0]xiphy_control_2;
  wire [5:0]xiphy_control_3;
  wire [0:0]xiphy_control_4;
  wire [15:0]xiphy_riu_or;

  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_725 \I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_251 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_282 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_250 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_277 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[0]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[0]),
        .mcal_DMIn_n(mcal_DMIn_n),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[0]),
        .phy2iob_t(phy2iob_t[0]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_726 \I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[0]_253 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_281 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[0]_252 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_276 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[7:0]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[1]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[1]),
        .mcal_DQIn(mcal_DQIn[7:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[1]),
        .phy2iob_t(phy2iob_t[1]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_727 \I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[0]_255 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_280 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[0]_254 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_275 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[15:8]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[2]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[2]),
        .mcal_DQIn(mcal_DQIn[15:8]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[2]),
        .phy2iob_t(phy2iob_t[2]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_728 \I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[0]_257 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_279 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[0]_256 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_274 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[23:16]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[3]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[3]),
        .mcal_DQIn(mcal_DQIn[23:16]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[3]),
        .phy2iob_t(phy2iob_t[3]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_729 \I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[0]_259 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_278 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[0]_258 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_273 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[31:24]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[4]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[4]),
        .mcal_DQIn(mcal_DQIn[31:24]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[4]),
        .phy2iob_t(phy2iob_t[4]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_730 \I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_261 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_294 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_260 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_289 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[5]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq6(clb2phy_wr_dq6),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[5]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[5]),
        .phy2iob_t(phy2iob_t[5]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_731 \I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[1]_263 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_293 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[1]_262 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_288 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[39:32]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[6]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[6]),
        .mcal_DQIn(mcal_DQIn[39:32]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[6]),
        .phy2iob_t(phy2iob_t[6]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_732 \I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[1]_265 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_292 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[1]_264 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_287 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[47:40]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[7]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[7]),
        .mcal_DQIn(mcal_DQIn[47:40]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[7]),
        .phy2iob_t(phy2iob_t[7]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_733 \I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[1]_267 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_291 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[1]_266 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_286 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[55:48]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[8]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[8]),
        .mcal_DQIn(mcal_DQIn[55:48]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[8]),
        .phy2iob_t(phy2iob_t[8]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_734 \I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[1]_269 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_290 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[1]_268 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_285 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[63:56]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[9]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[9]),
        .mcal_DQIn(mcal_DQIn[63:56]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[9]),
        .phy2iob_t(phy2iob_t[9]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_735 \I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_270 ),
        .D(D),
        .Q(Q),
        .RIU_RD_DATA(\riu2clb_rd_data_array[0]_283 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_251 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_282 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_281 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_280 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_279 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_278 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_250 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_277 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_276 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_275 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_274 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_273 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_272 ),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[4:0]),
        .pll_clk(pll_clk),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control),
        .xiphy_control_1(xiphy_control_2),
        .xiphy_control_10(xiphy_control_3),
        .xiphy_control_2(\rx_bit_ctrl_in2[0]_253 ),
        .xiphy_control_3(\rx_bit_ctrl_in3[0]_255 ),
        .xiphy_control_4(\rx_bit_ctrl_in4[0]_257 ),
        .xiphy_control_5(\rx_bit_ctrl_in5[0]_259 ),
        .xiphy_control_6(\tx_bit_ctrl_in2[0]_252 ),
        .xiphy_control_7(\tx_bit_ctrl_in3[0]_254 ),
        .xiphy_control_8(\tx_bit_ctrl_in4[0]_256 ),
        .xiphy_control_9(\tx_bit_ctrl_in5[0]_258 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_736 \I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_271 ),
        .RIU_RD_DATA(\riu2clb_rd_data_array[1]_295 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_261 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_294 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_293 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_292 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_291 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_290 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_260 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_289 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_288 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_287 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_286 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_285 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_284 ),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[8:5]),
        .pll_clk(pll_clk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control_0),
        .xiphy_control_1(xiphy_control_1),
        .xiphy_control_10(\tx_bit_ctrl_in4[1]_266 ),
        .xiphy_control_11(\tx_bit_ctrl_in5[1]_268 ),
        .xiphy_control_12(xiphy_control_3),
        .xiphy_control_2(xiphy_control_4),
        .xiphy_control_3(xiphy_control_2),
        .xiphy_control_4(\rx_bit_ctrl_in2[1]_263 ),
        .xiphy_control_5(\rx_bit_ctrl_in3[1]_265 ),
        .xiphy_control_6(\rx_bit_ctrl_in4[1]_267 ),
        .xiphy_control_7(\rx_bit_ctrl_in5[1]_269 ),
        .xiphy_control_8(\tx_bit_ctrl_in2[1]_262 ),
        .xiphy_control_9(\tx_bit_ctrl_in3[1]_264 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_737 \I_TRISTATE[0].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_270 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_272 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_738 \I_TRISTATE[1].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_271 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_284 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_1(tristate_q_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* DONT_TOUCH *) 
  LUT1 #(
    .INIT(2'h2)) 
    u_lut1_clb2riu_wr_en
       (.I0(u_lut1_clb2riu_wr_en_0),
        .O(clb2riu_wr_en_lut));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_739 u_xiphy_riuor
       (.RIU_RD_DATA(\riu2clb_rd_data_array[0]_283 ),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .xiphy_riu_or_0(xiphy_riu_or),
        .xiphy_riu_or_1(\riu2clb_rd_data_array[1]_295 ));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_byte_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized2_667
   (phy2iob_q_out_byte,
    phy2iob_t,
    mcal_DMIn_n,
    mcal_DQIn,
    D,
    xiphy_control,
    phy2iob_odt_out_byte,
    xiphy_control_0,
    xiphy_control_1,
    riu2clb_valid_riuclk,
    xiphy_riu_or,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    clb2phy_wr_dq0,
    ch0_mcal_DQOut,
    clb2phy_wr_dq6,
    en_vtc_riuclk,
    pll_clk,
    riu_clk,
    Q,
    SR,
    xiphy_control_2,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_3,
    xiphy_control_4,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    u_lut1_clb2riu_wr_en_0);
  output [9:0]phy2iob_q_out_byte;
  output [9:0]phy2iob_t;
  output [7:0]mcal_DMIn_n;
  output [63:0]mcal_DQIn;
  output [0:0]D;
  output [0:0]xiphy_control;
  output [8:0]phy2iob_odt_out_byte;
  output [0:0]xiphy_control_0;
  output [0:0]xiphy_control_1;
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or;
  input [9:0]iob2phy_d_in_byte;
  input div_clk;
  input [9:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [7:0]clb2phy_wr_dq0;
  input [63:0]ch0_mcal_DQOut;
  input [7:0]clb2phy_wr_dq6;
  input en_vtc_riuclk;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input [0:0]SR;
  input [15:0]xiphy_control_2;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_3;
  input [0:0]xiphy_control_4;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [0:0]u_lut1_clb2riu_wr_en_0;

  wire [0:0]D;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [63:0]ch0_mcal_DQOut;
  wire [9:0]ch0_mcal_clb2phy_fifo_rden;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire [7:0]clb2phy_wr_dq6;
  wire clb2riu_wr_en_lut;
  wire div_clk;
  wire en_vtc_riuclk;
  wire [9:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [63:0]mcal_DQIn;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [8:0]phy2iob_odt_out_byte;
  wire [9:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;
  wire [0:0]pll_clk;
  wire [15:0]\riu2clb_rd_data_array[0]_329 ;
  wire [15:0]\riu2clb_rd_data_array[1]_341 ;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [39:0]\rx_bit_ctrl_in0[0]_297 ;
  wire [39:0]\rx_bit_ctrl_in0[1]_307 ;
  wire [39:0]\rx_bit_ctrl_in2[0]_299 ;
  wire [39:0]\rx_bit_ctrl_in2[1]_309 ;
  wire [39:0]\rx_bit_ctrl_in3[0]_301 ;
  wire [39:0]\rx_bit_ctrl_in3[1]_311 ;
  wire [39:0]\rx_bit_ctrl_in4[0]_303 ;
  wire [39:0]\rx_bit_ctrl_in4[1]_313 ;
  wire [39:0]\rx_bit_ctrl_in5[0]_305 ;
  wire [39:0]\rx_bit_ctrl_in5[1]_315 ;
  wire [39:0]\rx_bit_ctrl_out0[0]_328 ;
  wire [39:0]\rx_bit_ctrl_out0[1]_340 ;
  wire [39:0]\rx_bit_ctrl_out2[0]_327 ;
  wire [39:0]\rx_bit_ctrl_out2[1]_339 ;
  wire [39:0]\rx_bit_ctrl_out3[0]_326 ;
  wire [39:0]\rx_bit_ctrl_out3[1]_338 ;
  wire [39:0]\rx_bit_ctrl_out4[0]_325 ;
  wire [39:0]\rx_bit_ctrl_out4[1]_337 ;
  wire [39:0]\rx_bit_ctrl_out5[0]_324 ;
  wire [39:0]\rx_bit_ctrl_out5[1]_336 ;
  wire tristate_q_0;
  wire tristate_q_1;
  wire [39:0]\tx_bit_ctrl_in0[0]_296 ;
  wire [39:0]\tx_bit_ctrl_in0[1]_306 ;
  wire [39:0]\tx_bit_ctrl_in2[0]_298 ;
  wire [39:0]\tx_bit_ctrl_in2[1]_308 ;
  wire [39:0]\tx_bit_ctrl_in3[0]_300 ;
  wire [39:0]\tx_bit_ctrl_in3[1]_310 ;
  wire [39:0]\tx_bit_ctrl_in4[0]_302 ;
  wire [39:0]\tx_bit_ctrl_in4[1]_312 ;
  wire [39:0]\tx_bit_ctrl_in5[0]_304 ;
  wire [39:0]\tx_bit_ctrl_in5[1]_314 ;
  wire [39:0]\tx_bit_ctrl_in_tri[0]_316 ;
  wire [39:0]\tx_bit_ctrl_in_tri[1]_317 ;
  wire [39:0]\tx_bit_ctrl_out0[0]_323 ;
  wire [39:0]\tx_bit_ctrl_out0[1]_335 ;
  wire [39:0]\tx_bit_ctrl_out2[0]_322 ;
  wire [39:0]\tx_bit_ctrl_out2[1]_334 ;
  wire [39:0]\tx_bit_ctrl_out3[0]_321 ;
  wire [39:0]\tx_bit_ctrl_out3[1]_333 ;
  wire [39:0]\tx_bit_ctrl_out4[0]_320 ;
  wire [39:0]\tx_bit_ctrl_out4[1]_332 ;
  wire [39:0]\tx_bit_ctrl_out5[0]_319 ;
  wire [39:0]\tx_bit_ctrl_out5[1]_331 ;
  wire [39:0]\tx_bit_ctrl_out_tri[0]_318 ;
  wire [39:0]\tx_bit_ctrl_out_tri[1]_330 ;
  wire [0:0]u_lut1_clb2riu_wr_en_0;
  wire [0:0]xiphy_control;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [15:0]xiphy_control_2;
  wire [5:0]xiphy_control_3;
  wire [0:0]xiphy_control_4;
  wire [15:0]xiphy_riu_or;

  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_710 \I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_297 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_328 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_296 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_323 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[0]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[0]),
        .mcal_DMIn_n(mcal_DMIn_n),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[0]),
        .phy2iob_t(phy2iob_t[0]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_711 \I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[0]_299 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_327 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[0]_298 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_322 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[7:0]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[1]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[1]),
        .mcal_DQIn(mcal_DQIn[7:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[1]),
        .phy2iob_t(phy2iob_t[1]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_712 \I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[0]_301 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_326 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[0]_300 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_321 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[15:8]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[2]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[2]),
        .mcal_DQIn(mcal_DQIn[15:8]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[2]),
        .phy2iob_t(phy2iob_t[2]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_713 \I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[0]_303 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_325 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[0]_302 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_320 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[23:16]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[3]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[3]),
        .mcal_DQIn(mcal_DQIn[23:16]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[3]),
        .phy2iob_t(phy2iob_t[3]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_714 \I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[0]_305 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_324 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[0]_304 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_319 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[31:24]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[4]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[4]),
        .mcal_DQIn(mcal_DQIn[31:24]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[4]),
        .phy2iob_t(phy2iob_t[4]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_715 \I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_307 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_340 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_306 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_335 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[5]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq6(clb2phy_wr_dq6),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[5]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[5]),
        .phy2iob_t(phy2iob_t[5]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_716 \I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[1]_309 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_339 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[1]_308 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_334 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[39:32]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[6]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[6]),
        .mcal_DQIn(mcal_DQIn[39:32]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[6]),
        .phy2iob_t(phy2iob_t[6]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_717 \I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[1]_311 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_338 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[1]_310 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_333 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[47:40]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[7]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[7]),
        .mcal_DQIn(mcal_DQIn[47:40]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[7]),
        .phy2iob_t(phy2iob_t[7]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_718 \I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[1]_313 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_337 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[1]_312 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_332 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[55:48]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[8]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[8]),
        .mcal_DQIn(mcal_DQIn[55:48]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[8]),
        .phy2iob_t(phy2iob_t[8]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_719 \I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[1]_315 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_336 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[1]_314 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_331 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[63:56]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[9]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[9]),
        .mcal_DQIn(mcal_DQIn[63:56]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[9]),
        .phy2iob_t(phy2iob_t[9]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_720 \I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_316 ),
        .D(D),
        .Q(Q),
        .RIU_RD_DATA(\riu2clb_rd_data_array[0]_329 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_297 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_328 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_327 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_326 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_325 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_324 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_296 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_323 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_322 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_321 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_320 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_319 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_318 ),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[4:0]),
        .pll_clk(pll_clk),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control),
        .xiphy_control_1(xiphy_control_2),
        .xiphy_control_10(xiphy_control_3),
        .xiphy_control_2(\rx_bit_ctrl_in2[0]_299 ),
        .xiphy_control_3(\rx_bit_ctrl_in3[0]_301 ),
        .xiphy_control_4(\rx_bit_ctrl_in4[0]_303 ),
        .xiphy_control_5(\rx_bit_ctrl_in5[0]_305 ),
        .xiphy_control_6(\tx_bit_ctrl_in2[0]_298 ),
        .xiphy_control_7(\tx_bit_ctrl_in3[0]_300 ),
        .xiphy_control_8(\tx_bit_ctrl_in4[0]_302 ),
        .xiphy_control_9(\tx_bit_ctrl_in5[0]_304 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_721 \I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_317 ),
        .RIU_RD_DATA(\riu2clb_rd_data_array[1]_341 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_307 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_340 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_339 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_338 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_337 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_336 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_306 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_335 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_334 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_333 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_332 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_331 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_330 ),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[8:5]),
        .pll_clk(pll_clk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control_0),
        .xiphy_control_1(xiphy_control_1),
        .xiphy_control_10(\tx_bit_ctrl_in4[1]_312 ),
        .xiphy_control_11(\tx_bit_ctrl_in5[1]_314 ),
        .xiphy_control_12(xiphy_control_3),
        .xiphy_control_2(xiphy_control_4),
        .xiphy_control_3(xiphy_control_2),
        .xiphy_control_4(\rx_bit_ctrl_in2[1]_309 ),
        .xiphy_control_5(\rx_bit_ctrl_in3[1]_311 ),
        .xiphy_control_6(\rx_bit_ctrl_in4[1]_313 ),
        .xiphy_control_7(\rx_bit_ctrl_in5[1]_315 ),
        .xiphy_control_8(\tx_bit_ctrl_in2[1]_308 ),
        .xiphy_control_9(\tx_bit_ctrl_in3[1]_310 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_722 \I_TRISTATE[0].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_316 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_318 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_723 \I_TRISTATE[1].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_317 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_330 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_1(tristate_q_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* DONT_TOUCH *) 
  LUT1 #(
    .INIT(2'h2)) 
    u_lut1_clb2riu_wr_en
       (.I0(u_lut1_clb2riu_wr_en_0),
        .O(clb2riu_wr_en_lut));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_724 u_xiphy_riuor
       (.RIU_RD_DATA(\riu2clb_rd_data_array[0]_329 ),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .xiphy_riu_or_0(xiphy_riu_or),
        .xiphy_riu_or_1(\riu2clb_rd_data_array[1]_341 ));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_byte_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized2_668
   (phy2iob_q_out_byte,
    phy2iob_t,
    mcal_DMIn_n,
    mcal_DQIn,
    D,
    xiphy_control,
    phy2iob_odt_out_byte,
    xiphy_control_0,
    xiphy_control_1,
    riu2clb_valid_riuclk,
    xiphy_riu_or,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    clb2phy_wr_dq0,
    ch0_mcal_DQOut,
    clb2phy_wr_dq6,
    en_vtc_riuclk,
    pll_clk,
    riu_clk,
    Q,
    SR,
    xiphy_control_2,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_3,
    xiphy_control_4,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    u_lut1_clb2riu_wr_en_0);
  output [9:0]phy2iob_q_out_byte;
  output [9:0]phy2iob_t;
  output [7:0]mcal_DMIn_n;
  output [63:0]mcal_DQIn;
  output [0:0]D;
  output [0:0]xiphy_control;
  output [8:0]phy2iob_odt_out_byte;
  output [0:0]xiphy_control_0;
  output [0:0]xiphy_control_1;
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or;
  input [9:0]iob2phy_d_in_byte;
  input div_clk;
  input [9:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [7:0]clb2phy_wr_dq0;
  input [63:0]ch0_mcal_DQOut;
  input [7:0]clb2phy_wr_dq6;
  input en_vtc_riuclk;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input [0:0]SR;
  input [15:0]xiphy_control_2;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_3;
  input [0:0]xiphy_control_4;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [0:0]u_lut1_clb2riu_wr_en_0;

  wire [0:0]D;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [63:0]ch0_mcal_DQOut;
  wire [9:0]ch0_mcal_clb2phy_fifo_rden;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire [7:0]clb2phy_wr_dq6;
  wire clb2riu_wr_en_lut;
  wire div_clk;
  wire en_vtc_riuclk;
  wire [9:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [63:0]mcal_DQIn;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [8:0]phy2iob_odt_out_byte;
  wire [9:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;
  wire [0:0]pll_clk;
  wire [15:0]\riu2clb_rd_data_array[0]_375 ;
  wire [15:0]\riu2clb_rd_data_array[1]_387 ;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [39:0]\rx_bit_ctrl_in0[0]_343 ;
  wire [39:0]\rx_bit_ctrl_in0[1]_353 ;
  wire [39:0]\rx_bit_ctrl_in2[0]_345 ;
  wire [39:0]\rx_bit_ctrl_in2[1]_355 ;
  wire [39:0]\rx_bit_ctrl_in3[0]_347 ;
  wire [39:0]\rx_bit_ctrl_in3[1]_357 ;
  wire [39:0]\rx_bit_ctrl_in4[0]_349 ;
  wire [39:0]\rx_bit_ctrl_in4[1]_359 ;
  wire [39:0]\rx_bit_ctrl_in5[0]_351 ;
  wire [39:0]\rx_bit_ctrl_in5[1]_361 ;
  wire [39:0]\rx_bit_ctrl_out0[0]_374 ;
  wire [39:0]\rx_bit_ctrl_out0[1]_386 ;
  wire [39:0]\rx_bit_ctrl_out2[0]_373 ;
  wire [39:0]\rx_bit_ctrl_out2[1]_385 ;
  wire [39:0]\rx_bit_ctrl_out3[0]_372 ;
  wire [39:0]\rx_bit_ctrl_out3[1]_384 ;
  wire [39:0]\rx_bit_ctrl_out4[0]_371 ;
  wire [39:0]\rx_bit_ctrl_out4[1]_383 ;
  wire [39:0]\rx_bit_ctrl_out5[0]_370 ;
  wire [39:0]\rx_bit_ctrl_out5[1]_382 ;
  wire tristate_q_0;
  wire tristate_q_1;
  wire [39:0]\tx_bit_ctrl_in0[0]_342 ;
  wire [39:0]\tx_bit_ctrl_in0[1]_352 ;
  wire [39:0]\tx_bit_ctrl_in2[0]_344 ;
  wire [39:0]\tx_bit_ctrl_in2[1]_354 ;
  wire [39:0]\tx_bit_ctrl_in3[0]_346 ;
  wire [39:0]\tx_bit_ctrl_in3[1]_356 ;
  wire [39:0]\tx_bit_ctrl_in4[0]_348 ;
  wire [39:0]\tx_bit_ctrl_in4[1]_358 ;
  wire [39:0]\tx_bit_ctrl_in5[0]_350 ;
  wire [39:0]\tx_bit_ctrl_in5[1]_360 ;
  wire [39:0]\tx_bit_ctrl_in_tri[0]_362 ;
  wire [39:0]\tx_bit_ctrl_in_tri[1]_363 ;
  wire [39:0]\tx_bit_ctrl_out0[0]_369 ;
  wire [39:0]\tx_bit_ctrl_out0[1]_381 ;
  wire [39:0]\tx_bit_ctrl_out2[0]_368 ;
  wire [39:0]\tx_bit_ctrl_out2[1]_380 ;
  wire [39:0]\tx_bit_ctrl_out3[0]_367 ;
  wire [39:0]\tx_bit_ctrl_out3[1]_379 ;
  wire [39:0]\tx_bit_ctrl_out4[0]_366 ;
  wire [39:0]\tx_bit_ctrl_out4[1]_378 ;
  wire [39:0]\tx_bit_ctrl_out5[0]_365 ;
  wire [39:0]\tx_bit_ctrl_out5[1]_377 ;
  wire [39:0]\tx_bit_ctrl_out_tri[0]_364 ;
  wire [39:0]\tx_bit_ctrl_out_tri[1]_376 ;
  wire [0:0]u_lut1_clb2riu_wr_en_0;
  wire [0:0]xiphy_control;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [15:0]xiphy_control_2;
  wire [5:0]xiphy_control_3;
  wire [0:0]xiphy_control_4;
  wire [15:0]xiphy_riu_or;

  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_695 \I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_343 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_374 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_342 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_369 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[0]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[0]),
        .mcal_DMIn_n(mcal_DMIn_n),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[0]),
        .phy2iob_t(phy2iob_t[0]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_696 \I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[0]_345 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_373 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[0]_344 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_368 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[7:0]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[1]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[1]),
        .mcal_DQIn(mcal_DQIn[7:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[1]),
        .phy2iob_t(phy2iob_t[1]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_697 \I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[0]_347 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_372 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[0]_346 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_367 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[15:8]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[2]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[2]),
        .mcal_DQIn(mcal_DQIn[15:8]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[2]),
        .phy2iob_t(phy2iob_t[2]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_698 \I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[0]_349 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_371 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[0]_348 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_366 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[23:16]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[3]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[3]),
        .mcal_DQIn(mcal_DQIn[23:16]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[3]),
        .phy2iob_t(phy2iob_t[3]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_699 \I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[0]_351 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_370 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[0]_350 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_365 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[31:24]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[4]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[4]),
        .mcal_DQIn(mcal_DQIn[31:24]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[4]),
        .phy2iob_t(phy2iob_t[4]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_700 \I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_353 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_386 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_352 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_381 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[5]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq6(clb2phy_wr_dq6),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[5]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[5]),
        .phy2iob_t(phy2iob_t[5]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_701 \I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[1]_355 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_385 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[1]_354 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_380 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[39:32]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[6]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[6]),
        .mcal_DQIn(mcal_DQIn[39:32]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[6]),
        .phy2iob_t(phy2iob_t[6]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_702 \I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[1]_357 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_384 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[1]_356 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_379 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[47:40]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[7]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[7]),
        .mcal_DQIn(mcal_DQIn[47:40]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[7]),
        .phy2iob_t(phy2iob_t[7]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_703 \I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[1]_359 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_383 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[1]_358 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_378 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[55:48]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[8]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[8]),
        .mcal_DQIn(mcal_DQIn[55:48]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[8]),
        .phy2iob_t(phy2iob_t[8]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_704 \I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[1]_361 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_382 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[1]_360 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_377 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[63:56]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[9]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[9]),
        .mcal_DQIn(mcal_DQIn[63:56]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[9]),
        .phy2iob_t(phy2iob_t[9]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_705 \I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_362 ),
        .D(D),
        .Q(Q),
        .RIU_RD_DATA(\riu2clb_rd_data_array[0]_375 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_343 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_374 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_373 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_372 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_371 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_370 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_342 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_369 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_368 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_367 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_366 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_365 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_364 ),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[4:0]),
        .pll_clk(pll_clk),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control),
        .xiphy_control_1(xiphy_control_2),
        .xiphy_control_10(xiphy_control_3),
        .xiphy_control_2(\rx_bit_ctrl_in2[0]_345 ),
        .xiphy_control_3(\rx_bit_ctrl_in3[0]_347 ),
        .xiphy_control_4(\rx_bit_ctrl_in4[0]_349 ),
        .xiphy_control_5(\rx_bit_ctrl_in5[0]_351 ),
        .xiphy_control_6(\tx_bit_ctrl_in2[0]_344 ),
        .xiphy_control_7(\tx_bit_ctrl_in3[0]_346 ),
        .xiphy_control_8(\tx_bit_ctrl_in4[0]_348 ),
        .xiphy_control_9(\tx_bit_ctrl_in5[0]_350 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_706 \I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_363 ),
        .RIU_RD_DATA(\riu2clb_rd_data_array[1]_387 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_353 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_386 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_385 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_384 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_383 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_382 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_352 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_381 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_380 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_379 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_378 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_377 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_376 ),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[8:5]),
        .pll_clk(pll_clk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control_0),
        .xiphy_control_1(xiphy_control_1),
        .xiphy_control_10(\tx_bit_ctrl_in4[1]_358 ),
        .xiphy_control_11(\tx_bit_ctrl_in5[1]_360 ),
        .xiphy_control_12(xiphy_control_3),
        .xiphy_control_2(xiphy_control_4),
        .xiphy_control_3(xiphy_control_2),
        .xiphy_control_4(\rx_bit_ctrl_in2[1]_355 ),
        .xiphy_control_5(\rx_bit_ctrl_in3[1]_357 ),
        .xiphy_control_6(\rx_bit_ctrl_in4[1]_359 ),
        .xiphy_control_7(\rx_bit_ctrl_in5[1]_361 ),
        .xiphy_control_8(\tx_bit_ctrl_in2[1]_354 ),
        .xiphy_control_9(\tx_bit_ctrl_in3[1]_356 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_707 \I_TRISTATE[0].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_362 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_364 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_708 \I_TRISTATE[1].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_363 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_376 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_1(tristate_q_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* DONT_TOUCH *) 
  LUT1 #(
    .INIT(2'h2)) 
    u_lut1_clb2riu_wr_en
       (.I0(u_lut1_clb2riu_wr_en_0),
        .O(clb2riu_wr_en_lut));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_709 u_xiphy_riuor
       (.RIU_RD_DATA(\riu2clb_rd_data_array[0]_375 ),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .xiphy_riu_or_0(xiphy_riu_or),
        .xiphy_riu_or_1(\riu2clb_rd_data_array[1]_387 ));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_byte_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized2_669
   (phy2iob_q_out_byte,
    phy2iob_t,
    mcal_DMIn_n,
    mcal_DQIn,
    D,
    xiphy_control,
    phy2iob_odt_out_byte,
    xiphy_control_0,
    xiphy_control_1,
    riu2clb_valid_riuclk,
    xiphy_riu_or,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    clb2phy_wr_dq0,
    ch0_mcal_DQOut,
    clb2phy_wr_dq6,
    en_vtc_riuclk,
    pll_clk,
    riu_clk,
    Q,
    SR,
    xiphy_control_2,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_3,
    xiphy_control_4,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    u_lut1_clb2riu_wr_en_0);
  output [9:0]phy2iob_q_out_byte;
  output [9:0]phy2iob_t;
  output [7:0]mcal_DMIn_n;
  output [63:0]mcal_DQIn;
  output [0:0]D;
  output [0:0]xiphy_control;
  output [8:0]phy2iob_odt_out_byte;
  output [0:0]xiphy_control_0;
  output [0:0]xiphy_control_1;
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or;
  input [9:0]iob2phy_d_in_byte;
  input div_clk;
  input [9:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [7:0]clb2phy_wr_dq0;
  input [63:0]ch0_mcal_DQOut;
  input [7:0]clb2phy_wr_dq6;
  input en_vtc_riuclk;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input [0:0]SR;
  input [15:0]xiphy_control_2;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_3;
  input [0:0]xiphy_control_4;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [0:0]u_lut1_clb2riu_wr_en_0;

  wire [0:0]D;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [63:0]ch0_mcal_DQOut;
  wire [9:0]ch0_mcal_clb2phy_fifo_rden;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire [7:0]clb2phy_wr_dq6;
  wire clb2riu_wr_en_lut;
  wire div_clk;
  wire en_vtc_riuclk;
  wire [9:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [63:0]mcal_DQIn;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [8:0]phy2iob_odt_out_byte;
  wire [9:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;
  wire [0:0]pll_clk;
  wire [15:0]\riu2clb_rd_data_array[0]_421 ;
  wire [15:0]\riu2clb_rd_data_array[1]_433 ;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [39:0]\rx_bit_ctrl_in0[0]_389 ;
  wire [39:0]\rx_bit_ctrl_in0[1]_399 ;
  wire [39:0]\rx_bit_ctrl_in2[0]_391 ;
  wire [39:0]\rx_bit_ctrl_in2[1]_401 ;
  wire [39:0]\rx_bit_ctrl_in3[0]_393 ;
  wire [39:0]\rx_bit_ctrl_in3[1]_403 ;
  wire [39:0]\rx_bit_ctrl_in4[0]_395 ;
  wire [39:0]\rx_bit_ctrl_in4[1]_405 ;
  wire [39:0]\rx_bit_ctrl_in5[0]_397 ;
  wire [39:0]\rx_bit_ctrl_in5[1]_407 ;
  wire [39:0]\rx_bit_ctrl_out0[0]_420 ;
  wire [39:0]\rx_bit_ctrl_out0[1]_432 ;
  wire [39:0]\rx_bit_ctrl_out2[0]_419 ;
  wire [39:0]\rx_bit_ctrl_out2[1]_431 ;
  wire [39:0]\rx_bit_ctrl_out3[0]_418 ;
  wire [39:0]\rx_bit_ctrl_out3[1]_430 ;
  wire [39:0]\rx_bit_ctrl_out4[0]_417 ;
  wire [39:0]\rx_bit_ctrl_out4[1]_429 ;
  wire [39:0]\rx_bit_ctrl_out5[0]_416 ;
  wire [39:0]\rx_bit_ctrl_out5[1]_428 ;
  wire tristate_q_0;
  wire tristate_q_1;
  wire [39:0]\tx_bit_ctrl_in0[0]_388 ;
  wire [39:0]\tx_bit_ctrl_in0[1]_398 ;
  wire [39:0]\tx_bit_ctrl_in2[0]_390 ;
  wire [39:0]\tx_bit_ctrl_in2[1]_400 ;
  wire [39:0]\tx_bit_ctrl_in3[0]_392 ;
  wire [39:0]\tx_bit_ctrl_in3[1]_402 ;
  wire [39:0]\tx_bit_ctrl_in4[0]_394 ;
  wire [39:0]\tx_bit_ctrl_in4[1]_404 ;
  wire [39:0]\tx_bit_ctrl_in5[0]_396 ;
  wire [39:0]\tx_bit_ctrl_in5[1]_406 ;
  wire [39:0]\tx_bit_ctrl_in_tri[0]_408 ;
  wire [39:0]\tx_bit_ctrl_in_tri[1]_409 ;
  wire [39:0]\tx_bit_ctrl_out0[0]_415 ;
  wire [39:0]\tx_bit_ctrl_out0[1]_427 ;
  wire [39:0]\tx_bit_ctrl_out2[0]_414 ;
  wire [39:0]\tx_bit_ctrl_out2[1]_426 ;
  wire [39:0]\tx_bit_ctrl_out3[0]_413 ;
  wire [39:0]\tx_bit_ctrl_out3[1]_425 ;
  wire [39:0]\tx_bit_ctrl_out4[0]_412 ;
  wire [39:0]\tx_bit_ctrl_out4[1]_424 ;
  wire [39:0]\tx_bit_ctrl_out5[0]_411 ;
  wire [39:0]\tx_bit_ctrl_out5[1]_423 ;
  wire [39:0]\tx_bit_ctrl_out_tri[0]_410 ;
  wire [39:0]\tx_bit_ctrl_out_tri[1]_422 ;
  wire [0:0]u_lut1_clb2riu_wr_en_0;
  wire [0:0]xiphy_control;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [15:0]xiphy_control_2;
  wire [5:0]xiphy_control_3;
  wire [0:0]xiphy_control_4;
  wire [15:0]xiphy_riu_or;

  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_680 \I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_389 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_420 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_388 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_415 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[0]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[0]),
        .mcal_DMIn_n(mcal_DMIn_n),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[0]),
        .phy2iob_t(phy2iob_t[0]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_681 \I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[0]_391 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_419 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[0]_390 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_414 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[7:0]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[1]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[1]),
        .mcal_DQIn(mcal_DQIn[7:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[1]),
        .phy2iob_t(phy2iob_t[1]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_682 \I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[0]_393 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_418 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[0]_392 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_413 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[15:8]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[2]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[2]),
        .mcal_DQIn(mcal_DQIn[15:8]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[2]),
        .phy2iob_t(phy2iob_t[2]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_683 \I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[0]_395 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_417 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[0]_394 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_412 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[23:16]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[3]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[3]),
        .mcal_DQIn(mcal_DQIn[23:16]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[3]),
        .phy2iob_t(phy2iob_t[3]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_684 \I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[0]_397 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_416 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[0]_396 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_411 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[31:24]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[4]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[4]),
        .mcal_DQIn(mcal_DQIn[31:24]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[4]),
        .phy2iob_t(phy2iob_t[4]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1_685 \I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_399 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_432 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_398 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_427 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[5]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq6(clb2phy_wr_dq6),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[5]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[5]),
        .phy2iob_t(phy2iob_t[5]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_686 \I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[1]_401 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_431 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[1]_400 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_426 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[39:32]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[6]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[6]),
        .mcal_DQIn(mcal_DQIn[39:32]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[6]),
        .phy2iob_t(phy2iob_t[6]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_687 \I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[1]_403 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_430 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[1]_402 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_425 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[47:40]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[7]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[7]),
        .mcal_DQIn(mcal_DQIn[47:40]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[7]),
        .phy2iob_t(phy2iob_t[7]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_688 \I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[1]_405 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_429 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[1]_404 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_424 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[55:48]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[8]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[8]),
        .mcal_DQIn(mcal_DQIn[55:48]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[8]),
        .phy2iob_t(phy2iob_t[8]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_689 \I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[1]_407 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_428 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[1]_406 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_423 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[63:56]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[9]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[9]),
        .mcal_DQIn(mcal_DQIn[63:56]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[9]),
        .phy2iob_t(phy2iob_t[9]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_690 \I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_408 ),
        .D(D),
        .Q(Q),
        .RIU_RD_DATA(\riu2clb_rd_data_array[0]_421 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_389 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_420 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_419 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_418 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_417 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_416 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_388 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_415 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_414 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_413 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_412 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_411 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_410 ),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[4:0]),
        .pll_clk(pll_clk),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control),
        .xiphy_control_1(xiphy_control_2),
        .xiphy_control_10(xiphy_control_3),
        .xiphy_control_2(\rx_bit_ctrl_in2[0]_391 ),
        .xiphy_control_3(\rx_bit_ctrl_in3[0]_393 ),
        .xiphy_control_4(\rx_bit_ctrl_in4[0]_395 ),
        .xiphy_control_5(\rx_bit_ctrl_in5[0]_397 ),
        .xiphy_control_6(\tx_bit_ctrl_in2[0]_390 ),
        .xiphy_control_7(\tx_bit_ctrl_in3[0]_392 ),
        .xiphy_control_8(\tx_bit_ctrl_in4[0]_394 ),
        .xiphy_control_9(\tx_bit_ctrl_in5[0]_396 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_691 \I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_409 ),
        .RIU_RD_DATA(\riu2clb_rd_data_array[1]_433 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_399 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_432 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_431 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_430 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_429 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_428 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_398 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_427 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_426 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_425 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_424 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_423 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_422 ),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[8:5]),
        .pll_clk(pll_clk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control_0),
        .xiphy_control_1(xiphy_control_1),
        .xiphy_control_10(\tx_bit_ctrl_in4[1]_404 ),
        .xiphy_control_11(\tx_bit_ctrl_in5[1]_406 ),
        .xiphy_control_12(xiphy_control_3),
        .xiphy_control_2(xiphy_control_4),
        .xiphy_control_3(xiphy_control_2),
        .xiphy_control_4(\rx_bit_ctrl_in2[1]_401 ),
        .xiphy_control_5(\rx_bit_ctrl_in3[1]_403 ),
        .xiphy_control_6(\rx_bit_ctrl_in4[1]_405 ),
        .xiphy_control_7(\rx_bit_ctrl_in5[1]_407 ),
        .xiphy_control_8(\tx_bit_ctrl_in2[1]_400 ),
        .xiphy_control_9(\tx_bit_ctrl_in3[1]_402 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_692 \I_TRISTATE[0].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_408 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_410 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_693 \I_TRISTATE[1].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_409 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_422 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_1(tristate_q_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* DONT_TOUCH *) 
  LUT1 #(
    .INIT(2'h2)) 
    u_lut1_clb2riu_wr_en
       (.I0(u_lut1_clb2riu_wr_en_0),
        .O(clb2riu_wr_en_lut));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_694 u_xiphy_riuor
       (.RIU_RD_DATA(\riu2clb_rd_data_array[0]_421 ),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .xiphy_riu_or_0(xiphy_riu_or),
        .xiphy_riu_or_1(\riu2clb_rd_data_array[1]_433 ));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_byte_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_byte_wrapper__parameterized2_670
   (phy2iob_q_out_byte,
    phy2iob_t,
    mcal_DMIn_n,
    mcal_DQIn,
    D,
    xiphy_control,
    phy2iob_odt_out_byte,
    xiphy_control_0,
    xiphy_control_1,
    riu2clb_valid_riuclk,
    xiphy_riu_or,
    iob2phy_d_in_byte,
    div_clk,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_tristate_odelay_rst,
    clb2phy_wr_dq0,
    ch0_mcal_DQOut,
    clb2phy_wr_dq6,
    en_vtc_riuclk,
    pll_clk,
    riu_clk,
    Q,
    SR,
    xiphy_control_2,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_3,
    xiphy_control_4,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    u_lut1_clb2riu_wr_en_0);
  output [9:0]phy2iob_q_out_byte;
  output [9:0]phy2iob_t;
  output [7:0]mcal_DMIn_n;
  output [63:0]mcal_DQIn;
  output [0:0]D;
  output [0:0]xiphy_control;
  output [8:0]phy2iob_odt_out_byte;
  output [0:0]xiphy_control_0;
  output [0:0]xiphy_control_1;
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or;
  input [9:0]iob2phy_d_in_byte;
  input div_clk;
  input [9:0]ch0_mcal_clb2phy_fifo_rden;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [7:0]clb2phy_wr_dq0;
  input [63:0]ch0_mcal_DQOut;
  input [7:0]clb2phy_wr_dq6;
  input en_vtc_riuclk;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input [0:0]SR;
  input [15:0]xiphy_control_2;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_3;
  input [0:0]xiphy_control_4;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [0:0]u_lut1_clb2riu_wr_en_0;

  wire [0:0]D;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [63:0]ch0_mcal_DQOut;
  wire [9:0]ch0_mcal_clb2phy_fifo_rden;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire [7:0]clb2phy_wr_dq0;
  wire [7:0]clb2phy_wr_dq6;
  wire clb2riu_wr_en_lut;
  wire div_clk;
  wire en_vtc_riuclk;
  wire [9:0]iob2phy_d_in_byte;
  wire [7:0]mcal_DMIn_n;
  wire [63:0]mcal_DQIn;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [8:0]phy2iob_odt_out_byte;
  wire [9:0]phy2iob_q_out_byte;
  wire [9:0]phy2iob_t;
  wire [0:0]pll_clk;
  wire [15:0]\riu2clb_rd_data_array[0]_467 ;
  wire [15:0]\riu2clb_rd_data_array[1]_479 ;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [39:0]\rx_bit_ctrl_in0[0]_435 ;
  wire [39:0]\rx_bit_ctrl_in0[1]_445 ;
  wire [39:0]\rx_bit_ctrl_in2[0]_437 ;
  wire [39:0]\rx_bit_ctrl_in2[1]_447 ;
  wire [39:0]\rx_bit_ctrl_in3[0]_439 ;
  wire [39:0]\rx_bit_ctrl_in3[1]_449 ;
  wire [39:0]\rx_bit_ctrl_in4[0]_441 ;
  wire [39:0]\rx_bit_ctrl_in4[1]_451 ;
  wire [39:0]\rx_bit_ctrl_in5[0]_443 ;
  wire [39:0]\rx_bit_ctrl_in5[1]_453 ;
  wire [39:0]\rx_bit_ctrl_out0[0]_466 ;
  wire [39:0]\rx_bit_ctrl_out0[1]_478 ;
  wire [39:0]\rx_bit_ctrl_out2[0]_465 ;
  wire [39:0]\rx_bit_ctrl_out2[1]_477 ;
  wire [39:0]\rx_bit_ctrl_out3[0]_464 ;
  wire [39:0]\rx_bit_ctrl_out3[1]_476 ;
  wire [39:0]\rx_bit_ctrl_out4[0]_463 ;
  wire [39:0]\rx_bit_ctrl_out4[1]_475 ;
  wire [39:0]\rx_bit_ctrl_out5[0]_462 ;
  wire [39:0]\rx_bit_ctrl_out5[1]_474 ;
  wire tristate_q_0;
  wire tristate_q_1;
  wire [39:0]\tx_bit_ctrl_in0[0]_434 ;
  wire [39:0]\tx_bit_ctrl_in0[1]_444 ;
  wire [39:0]\tx_bit_ctrl_in2[0]_436 ;
  wire [39:0]\tx_bit_ctrl_in2[1]_446 ;
  wire [39:0]\tx_bit_ctrl_in3[0]_438 ;
  wire [39:0]\tx_bit_ctrl_in3[1]_448 ;
  wire [39:0]\tx_bit_ctrl_in4[0]_440 ;
  wire [39:0]\tx_bit_ctrl_in4[1]_450 ;
  wire [39:0]\tx_bit_ctrl_in5[0]_442 ;
  wire [39:0]\tx_bit_ctrl_in5[1]_452 ;
  wire [39:0]\tx_bit_ctrl_in_tri[0]_454 ;
  wire [39:0]\tx_bit_ctrl_in_tri[1]_455 ;
  wire [39:0]\tx_bit_ctrl_out0[0]_461 ;
  wire [39:0]\tx_bit_ctrl_out0[1]_473 ;
  wire [39:0]\tx_bit_ctrl_out2[0]_460 ;
  wire [39:0]\tx_bit_ctrl_out2[1]_472 ;
  wire [39:0]\tx_bit_ctrl_out3[0]_459 ;
  wire [39:0]\tx_bit_ctrl_out3[1]_471 ;
  wire [39:0]\tx_bit_ctrl_out4[0]_458 ;
  wire [39:0]\tx_bit_ctrl_out4[1]_470 ;
  wire [39:0]\tx_bit_ctrl_out5[0]_457 ;
  wire [39:0]\tx_bit_ctrl_out5[1]_469 ;
  wire [39:0]\tx_bit_ctrl_out_tri[0]_456 ;
  wire [39:0]\tx_bit_ctrl_out_tri[1]_468 ;
  wire [0:0]u_lut1_clb2riu_wr_en_0;
  wire [0:0]xiphy_control;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [15:0]xiphy_control_2;
  wire [5:0]xiphy_control_3;
  wire [0:0]xiphy_control_4;
  wire [15:0]xiphy_riu_or;

  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper \I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_435 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_466 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_434 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_461 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[0]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq0(clb2phy_wr_dq0),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[0]),
        .mcal_DMIn_n(mcal_DMIn_n),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[0]),
        .phy2iob_t(phy2iob_t[0]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_671 \I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[0]_437 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_465 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[0]_436 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_460 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[7:0]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[1]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[1]),
        .mcal_DQIn(mcal_DQIn[7:0]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[1]),
        .phy2iob_t(phy2iob_t[1]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_672 \I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[0]_439 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_464 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[0]_438 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_459 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[15:8]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[2]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[2]),
        .mcal_DQIn(mcal_DQIn[15:8]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[2]),
        .phy2iob_t(phy2iob_t[2]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_673 \I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[0]_441 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_463 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[0]_440 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_458 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[23:16]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[3]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[3]),
        .mcal_DQIn(mcal_DQIn[23:16]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[3]),
        .phy2iob_t(phy2iob_t[3]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_674 \I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[0]_443 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_462 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[0]_442 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_457 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[31:24]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[4]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[4]),
        .mcal_DQIn(mcal_DQIn[31:24]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[4]),
        .phy2iob_t(phy2iob_t[4]),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper__parameterized1 \I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_445 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_478 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_444 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_473 ),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[5]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .clb2phy_wr_dq6(clb2phy_wr_dq6),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[5]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[5]),
        .phy2iob_t(phy2iob_t[5]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_675 \I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in2[1]_447 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_477 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in2[1]_446 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_472 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[39:32]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[6]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[6]),
        .mcal_DQIn(mcal_DQIn[39:32]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[6]),
        .phy2iob_t(phy2iob_t[6]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_676 \I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in3[1]_449 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_476 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in3[1]_448 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_471 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[47:40]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[7]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[7]),
        .mcal_DQIn(mcal_DQIn[47:40]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[7]),
        .phy2iob_t(phy2iob_t[7]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_677 \I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in4[1]_451 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_475 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in4[1]_450 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_470 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[55:48]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[8]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[8]),
        .mcal_DQIn(mcal_DQIn[55:48]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[8]),
        .phy2iob_t(phy2iob_t[8]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_bitslice_wrapper_678 \I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper 
       (.RX_BIT_CTRL_OUT(\rx_bit_ctrl_in5[1]_453 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_474 ),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in5[1]_452 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_469 ),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[63:56]),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden[9]),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .div_clk(div_clk),
        .iob2phy_d_in_byte(iob2phy_d_in_byte[9]),
        .mcal_DQIn(mcal_DQIn[63:56]),
        .phy2iob_q_out_byte(phy2iob_q_out_byte[9]),
        .phy2iob_t(phy2iob_t[9]),
        .tristate_q_1(tristate_q_1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper \I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_454 ),
        .D(D),
        .Q(Q),
        .RIU_RD_DATA(\riu2clb_rd_data_array[0]_467 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[0]_435 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[0]_466 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[0]_465 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[0]_464 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[0]_463 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[0]_462 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[0]_434 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[0]_461 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[0]_460 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[0]_459 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[0]_458 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[0]_457 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_456 ),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[4:0]),
        .pll_clk(pll_clk),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control),
        .xiphy_control_1(xiphy_control_2),
        .xiphy_control_10(xiphy_control_3),
        .xiphy_control_2(\rx_bit_ctrl_in2[0]_437 ),
        .xiphy_control_3(\rx_bit_ctrl_in3[0]_439 ),
        .xiphy_control_4(\rx_bit_ctrl_in4[0]_441 ),
        .xiphy_control_5(\rx_bit_ctrl_in5[0]_443 ),
        .xiphy_control_6(\tx_bit_ctrl_in2[0]_436 ),
        .xiphy_control_7(\tx_bit_ctrl_in3[0]_438 ),
        .xiphy_control_8(\tx_bit_ctrl_in4[0]_440 ),
        .xiphy_control_9(\tx_bit_ctrl_in5[0]_442 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0 \I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_455 ),
        .RIU_RD_DATA(\riu2clb_rd_data_array[1]_479 ),
        .RX_BIT_CTRL_OUT(\rx_bit_ctrl_in0[1]_445 ),
        .RX_BIT_CTRL_OUT0(\rx_bit_ctrl_out0[1]_478 ),
        .RX_BIT_CTRL_OUT2(\rx_bit_ctrl_out2[1]_477 ),
        .RX_BIT_CTRL_OUT3(\rx_bit_ctrl_out3[1]_476 ),
        .RX_BIT_CTRL_OUT4(\rx_bit_ctrl_out4[1]_475 ),
        .RX_BIT_CTRL_OUT5(\rx_bit_ctrl_out5[1]_474 ),
        .SR(SR),
        .TX_BIT_CTRL_OUT(\tx_bit_ctrl_in0[1]_444 ),
        .TX_BIT_CTRL_OUT0(\tx_bit_ctrl_out0[1]_473 ),
        .TX_BIT_CTRL_OUT2(\tx_bit_ctrl_out2[1]_472 ),
        .TX_BIT_CTRL_OUT3(\tx_bit_ctrl_out3[1]_471 ),
        .TX_BIT_CTRL_OUT4(\tx_bit_ctrl_out4[1]_470 ),
        .TX_BIT_CTRL_OUT5(\tx_bit_ctrl_out5[1]_469 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_468 ),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp),
        .clb2riu_wr_en_lut(clb2riu_wr_en_lut),
        .en_vtc_riuclk(en_vtc_riuclk),
        .ndqs_gt_out_0(ndqs_gt_out_0),
        .ndqs_gt_out_1(ndqs_gt_out_1),
        .pdqs_gt_out_0(pdqs_gt_out_0),
        .pdqs_gt_out_1(pdqs_gt_out_1),
        .phy2iob_odt_out_byte(phy2iob_odt_out_byte[8:5]),
        .pll_clk(pll_clk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .riu_clk(riu_clk),
        .xiphy_control_0(xiphy_control_0),
        .xiphy_control_1(xiphy_control_1),
        .xiphy_control_10(\tx_bit_ctrl_in4[1]_450 ),
        .xiphy_control_11(\tx_bit_ctrl_in5[1]_452 ),
        .xiphy_control_12(xiphy_control_3),
        .xiphy_control_2(xiphy_control_4),
        .xiphy_control_3(xiphy_control_2),
        .xiphy_control_4(\rx_bit_ctrl_in2[1]_447 ),
        .xiphy_control_5(\rx_bit_ctrl_in3[1]_449 ),
        .xiphy_control_6(\rx_bit_ctrl_in4[1]_451 ),
        .xiphy_control_7(\rx_bit_ctrl_in5[1]_453 ),
        .xiphy_control_8(\tx_bit_ctrl_in2[1]_446 ),
        .xiphy_control_9(\tx_bit_ctrl_in3[1]_448 ));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper \I_TRISTATE[0].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[0]_454 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[0]_456 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_0(tristate_q_0));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_679 \I_TRISTATE[1].GEN_TRISTATE.u_xiphy_tristate 
       (.BIT_CTRL_OUT(\tx_bit_ctrl_in_tri[1]_455 ),
        .TX_BIT_CTRL_OUT_TRI(\tx_bit_ctrl_out_tri[1]_468 ),
        .clb2phy_tristate_odelay_rst(clb2phy_tristate_odelay_rst),
        .tristate_q_1(tristate_q_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* DONT_TOUCH *) 
  LUT1 #(
    .INIT(2'h2)) 
    u_lut1_clb2riu_wr_en
       (.I0(u_lut1_clb2riu_wr_en_0),
        .O(clb2riu_wr_en_lut));
  ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper u_xiphy_riuor
       (.RIU_RD_DATA(\riu2clb_rd_data_array[0]_467 ),
        .riu2clb_valid_low(riu2clb_valid_low),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk),
        .riu2clb_valid_upp(riu2clb_valid_upp),
        .xiphy_riu_or_0(xiphy_riu_or),
        .xiphy_riu_or_1(\riu2clb_rd_data_array[1]_479 ));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper
   (D,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    riu2clb_valid_low,
    xiphy_control_0,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    pll_clk,
    riu_clk,
    Q,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_1,
    RX_BIT_CTRL_OUT,
    xiphy_control_2,
    xiphy_control_3,
    xiphy_control_4,
    xiphy_control_5,
    TX_BIT_CTRL_OUT,
    xiphy_control_6,
    xiphy_control_7,
    xiphy_control_8,
    xiphy_control_9,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_10);
  output [0:0]D;
  output ndqs_gt_out_0;
  output pdqs_gt_out_0;
  output riu2clb_valid_low;
  output [0:0]xiphy_control_0;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [4:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_1;
  input pdqs_gt_out_1;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_1;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_2;
  input [39:0]xiphy_control_3;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_10;

  wire [39:0]BIT_CTRL_OUT;
  wire [0:0]D;
  wire [0:0]Q;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [4:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_low;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [15:0]xiphy_control_1;
  wire [5:0]xiphy_control_10;
  wire [39:0]xiphy_control_2;
  wire [39:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("TRUE"),
    .EN_OTHER_PCLK("TRUE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(D),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte[4:1],xiphy_control_n_628,phy2iob_odt_out_byte[0]}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_1),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_0),
        .PCLK_NIBBLE_IN(pdqs_gt_out_1),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_0),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_low),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_low),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_low),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_low),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_low),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_10),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(Q),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_low),
        .RIU_WR_DATA(xiphy_control_1),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_2),
        .RX_BIT_CTRL_IN3(xiphy_control_3),
        .RX_BIT_CTRL_IN4(xiphy_control_4),
        .RX_BIT_CTRL_IN5(xiphy_control_5),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_low),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_6),
        .TX_BIT_CTRL_IN3(xiphy_control_7),
        .TX_BIT_CTRL_IN4(xiphy_control_8),
        .TX_BIT_CTRL_IN5(xiphy_control_9),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_690
   (D,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    riu2clb_valid_low,
    xiphy_control_0,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    pll_clk,
    riu_clk,
    Q,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_1,
    RX_BIT_CTRL_OUT,
    xiphy_control_2,
    xiphy_control_3,
    xiphy_control_4,
    xiphy_control_5,
    TX_BIT_CTRL_OUT,
    xiphy_control_6,
    xiphy_control_7,
    xiphy_control_8,
    xiphy_control_9,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_10);
  output [0:0]D;
  output ndqs_gt_out_0;
  output pdqs_gt_out_0;
  output riu2clb_valid_low;
  output [0:0]xiphy_control_0;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [4:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_1;
  input pdqs_gt_out_1;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_1;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_2;
  input [39:0]xiphy_control_3;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_10;

  wire [39:0]BIT_CTRL_OUT;
  wire [0:0]D;
  wire [0:0]Q;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [4:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_low;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [15:0]xiphy_control_1;
  wire [5:0]xiphy_control_10;
  wire [39:0]xiphy_control_2;
  wire [39:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("TRUE"),
    .EN_OTHER_PCLK("TRUE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(D),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte[4:1],xiphy_control_n_628,phy2iob_odt_out_byte[0]}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_1),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_0),
        .PCLK_NIBBLE_IN(pdqs_gt_out_1),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_0),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_low),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_low),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_low),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_low),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_low),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_10),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(Q),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_low),
        .RIU_WR_DATA(xiphy_control_1),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_2),
        .RX_BIT_CTRL_IN3(xiphy_control_3),
        .RX_BIT_CTRL_IN4(xiphy_control_4),
        .RX_BIT_CTRL_IN5(xiphy_control_5),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_low),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_6),
        .TX_BIT_CTRL_IN3(xiphy_control_7),
        .TX_BIT_CTRL_IN4(xiphy_control_8),
        .TX_BIT_CTRL_IN5(xiphy_control_9),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_705
   (D,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    riu2clb_valid_low,
    xiphy_control_0,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    pll_clk,
    riu_clk,
    Q,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_1,
    RX_BIT_CTRL_OUT,
    xiphy_control_2,
    xiphy_control_3,
    xiphy_control_4,
    xiphy_control_5,
    TX_BIT_CTRL_OUT,
    xiphy_control_6,
    xiphy_control_7,
    xiphy_control_8,
    xiphy_control_9,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_10);
  output [0:0]D;
  output ndqs_gt_out_0;
  output pdqs_gt_out_0;
  output riu2clb_valid_low;
  output [0:0]xiphy_control_0;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [4:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_1;
  input pdqs_gt_out_1;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_1;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_2;
  input [39:0]xiphy_control_3;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_10;

  wire [39:0]BIT_CTRL_OUT;
  wire [0:0]D;
  wire [0:0]Q;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [4:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_low;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [15:0]xiphy_control_1;
  wire [5:0]xiphy_control_10;
  wire [39:0]xiphy_control_2;
  wire [39:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("TRUE"),
    .EN_OTHER_PCLK("TRUE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(D),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte[4:1],xiphy_control_n_628,phy2iob_odt_out_byte[0]}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_1),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_0),
        .PCLK_NIBBLE_IN(pdqs_gt_out_1),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_0),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_low),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_low),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_low),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_low),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_low),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_10),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(Q),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_low),
        .RIU_WR_DATA(xiphy_control_1),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_2),
        .RX_BIT_CTRL_IN3(xiphy_control_3),
        .RX_BIT_CTRL_IN4(xiphy_control_4),
        .RX_BIT_CTRL_IN5(xiphy_control_5),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_low),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_6),
        .TX_BIT_CTRL_IN3(xiphy_control_7),
        .TX_BIT_CTRL_IN4(xiphy_control_8),
        .TX_BIT_CTRL_IN5(xiphy_control_9),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_720
   (D,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    riu2clb_valid_low,
    xiphy_control_0,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    pll_clk,
    riu_clk,
    Q,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_1,
    RX_BIT_CTRL_OUT,
    xiphy_control_2,
    xiphy_control_3,
    xiphy_control_4,
    xiphy_control_5,
    TX_BIT_CTRL_OUT,
    xiphy_control_6,
    xiphy_control_7,
    xiphy_control_8,
    xiphy_control_9,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_10);
  output [0:0]D;
  output ndqs_gt_out_0;
  output pdqs_gt_out_0;
  output riu2clb_valid_low;
  output [0:0]xiphy_control_0;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [4:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_1;
  input pdqs_gt_out_1;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_1;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_2;
  input [39:0]xiphy_control_3;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_10;

  wire [39:0]BIT_CTRL_OUT;
  wire [0:0]D;
  wire [0:0]Q;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [4:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_low;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [15:0]xiphy_control_1;
  wire [5:0]xiphy_control_10;
  wire [39:0]xiphy_control_2;
  wire [39:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("TRUE"),
    .EN_OTHER_PCLK("TRUE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(D),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte[4:1],xiphy_control_n_628,phy2iob_odt_out_byte[0]}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_1),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_0),
        .PCLK_NIBBLE_IN(pdqs_gt_out_1),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_0),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_low),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_low),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_low),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_low),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_low),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_10),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(Q),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_low),
        .RIU_WR_DATA(xiphy_control_1),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_2),
        .RX_BIT_CTRL_IN3(xiphy_control_3),
        .RX_BIT_CTRL_IN4(xiphy_control_4),
        .RX_BIT_CTRL_IN5(xiphy_control_5),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_low),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_6),
        .TX_BIT_CTRL_IN3(xiphy_control_7),
        .TX_BIT_CTRL_IN4(xiphy_control_8),
        .TX_BIT_CTRL_IN5(xiphy_control_9),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_735
   (D,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    riu2clb_valid_low,
    xiphy_control_0,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    pll_clk,
    riu_clk,
    Q,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_1,
    RX_BIT_CTRL_OUT,
    xiphy_control_2,
    xiphy_control_3,
    xiphy_control_4,
    xiphy_control_5,
    TX_BIT_CTRL_OUT,
    xiphy_control_6,
    xiphy_control_7,
    xiphy_control_8,
    xiphy_control_9,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_10);
  output [0:0]D;
  output ndqs_gt_out_0;
  output pdqs_gt_out_0;
  output riu2clb_valid_low;
  output [0:0]xiphy_control_0;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [4:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_1;
  input pdqs_gt_out_1;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_1;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_2;
  input [39:0]xiphy_control_3;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_10;

  wire [39:0]BIT_CTRL_OUT;
  wire [0:0]D;
  wire [0:0]Q;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [4:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_low;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [15:0]xiphy_control_1;
  wire [5:0]xiphy_control_10;
  wire [39:0]xiphy_control_2;
  wire [39:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("TRUE"),
    .EN_OTHER_PCLK("TRUE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(D),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte[4:1],xiphy_control_n_628,phy2iob_odt_out_byte[0]}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_1),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_0),
        .PCLK_NIBBLE_IN(pdqs_gt_out_1),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_0),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_low),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_low),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_low),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_low),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_low),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_10),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(Q),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_low),
        .RIU_WR_DATA(xiphy_control_1),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_2),
        .RX_BIT_CTRL_IN3(xiphy_control_3),
        .RX_BIT_CTRL_IN4(xiphy_control_4),
        .RX_BIT_CTRL_IN5(xiphy_control_5),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_low),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_6),
        .TX_BIT_CTRL_IN3(xiphy_control_7),
        .TX_BIT_CTRL_IN4(xiphy_control_8),
        .TX_BIT_CTRL_IN5(xiphy_control_9),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_750
   (D,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    riu2clb_valid_low,
    xiphy_control_0,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    pll_clk,
    riu_clk,
    Q,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_1,
    RX_BIT_CTRL_OUT,
    xiphy_control_2,
    xiphy_control_3,
    xiphy_control_4,
    xiphy_control_5,
    TX_BIT_CTRL_OUT,
    xiphy_control_6,
    xiphy_control_7,
    xiphy_control_8,
    xiphy_control_9,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_10);
  output [0:0]D;
  output ndqs_gt_out_0;
  output pdqs_gt_out_0;
  output riu2clb_valid_low;
  output [0:0]xiphy_control_0;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [4:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_1;
  input pdqs_gt_out_1;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_1;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_2;
  input [39:0]xiphy_control_3;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_10;

  wire [39:0]BIT_CTRL_OUT;
  wire [0:0]D;
  wire [0:0]Q;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [4:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_low;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [15:0]xiphy_control_1;
  wire [5:0]xiphy_control_10;
  wire [39:0]xiphy_control_2;
  wire [39:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("TRUE"),
    .EN_OTHER_PCLK("TRUE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(D),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte[4:1],xiphy_control_n_628,phy2iob_odt_out_byte[0]}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_1),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_0),
        .PCLK_NIBBLE_IN(pdqs_gt_out_1),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_0),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_low),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_low),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_low),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_low),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_low),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_10),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(Q),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_low),
        .RIU_WR_DATA(xiphy_control_1),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_2),
        .RX_BIT_CTRL_IN3(xiphy_control_3),
        .RX_BIT_CTRL_IN4(xiphy_control_4),
        .RX_BIT_CTRL_IN5(xiphy_control_5),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_low),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_6),
        .TX_BIT_CTRL_IN3(xiphy_control_7),
        .TX_BIT_CTRL_IN4(xiphy_control_8),
        .TX_BIT_CTRL_IN5(xiphy_control_9),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_765
   (D,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    riu2clb_valid_low,
    xiphy_control_0,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT1,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT1,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    pll_clk,
    riu_clk,
    Q,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_1,
    RX_BIT_CTRL_OUT,
    xiphy_control_2,
    xiphy_control_3,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    TX_BIT_CTRL_OUT,
    xiphy_control_7,
    xiphy_control_8,
    xiphy_control_9,
    xiphy_control_10,
    xiphy_control_11,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_12);
  output [0:0]D;
  output ndqs_gt_out_0;
  output pdqs_gt_out_0;
  output riu2clb_valid_low;
  output [0:0]xiphy_control_0;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT1;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT1;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [4:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_1;
  input pdqs_gt_out_1;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_1;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_2;
  input [39:0]xiphy_control_3;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_7;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_12;

  wire [39:0]BIT_CTRL_OUT;
  wire [0:0]D;
  wire [0:0]Q;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT1;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT1;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [4:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_low;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [15:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [5:0]xiphy_control_12;
  wire [39:0]xiphy_control_2;
  wire [39:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("TRUE"),
    .EN_OTHER_PCLK("TRUE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(D),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte[4:1],xiphy_control_n_628,phy2iob_odt_out_byte[0]}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_1),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_0),
        .PCLK_NIBBLE_IN(pdqs_gt_out_1),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_0),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_low),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_low),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_low),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_low),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_low),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_12),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(Q),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_low),
        .RIU_WR_DATA(xiphy_control_1),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1(xiphy_control_2),
        .RX_BIT_CTRL_IN2(xiphy_control_3),
        .RX_BIT_CTRL_IN3(xiphy_control_4),
        .RX_BIT_CTRL_IN4(xiphy_control_5),
        .RX_BIT_CTRL_IN5(xiphy_control_6),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1(RX_BIT_CTRL_OUT1),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_low),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1(xiphy_control_7),
        .TX_BIT_CTRL_IN2(xiphy_control_8),
        .TX_BIT_CTRL_IN3(xiphy_control_9),
        .TX_BIT_CTRL_IN4(xiphy_control_10),
        .TX_BIT_CTRL_IN5(xiphy_control_11),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1(TX_BIT_CTRL_OUT1),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper_813
   (D,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    riu2clb_valid_low,
    xiphy_control_0,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT1,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT1,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    pll_clk,
    riu_clk,
    Q,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_1,
    RX_BIT_CTRL_OUT,
    xiphy_control_2,
    xiphy_control_3,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    TX_BIT_CTRL_OUT,
    xiphy_control_7,
    xiphy_control_8,
    xiphy_control_9,
    xiphy_control_10,
    xiphy_control_11,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    xiphy_control_12);
  output [0:0]D;
  output ndqs_gt_out_0;
  output pdqs_gt_out_0;
  output riu2clb_valid_low;
  output [0:0]xiphy_control_0;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT1;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT1;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [4:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_1;
  input pdqs_gt_out_1;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_1;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_2;
  input [39:0]xiphy_control_3;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_7;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_low;
  input [3:0]ch0_mcal_clb2phy_rdcs1_low;
  input [3:0]ch0_mcal_clb2phy_rden_low;
  input [3:0]ch0_mcal_clb2phy_wrcs0_low;
  input [3:0]ch0_mcal_clb2phy_wrcs1_low;
  input [3:0]ch0_mcal_clb2phy_t_b_low;
  input [5:0]xiphy_control_12;

  wire [39:0]BIT_CTRL_OUT;
  wire [0:0]D;
  wire [0:0]Q;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT1;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT1;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [3:0]ch0_mcal_clb2phy_t_b_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_low;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [4:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_low;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [15:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [5:0]xiphy_control_12;
  wire [39:0]xiphy_control_2;
  wire [39:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("TRUE"),
    .EN_OTHER_PCLK("TRUE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(D),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte[4:1],xiphy_control_n_628,phy2iob_odt_out_byte[0]}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_1),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_0),
        .PCLK_NIBBLE_IN(pdqs_gt_out_1),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_0),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_low),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_low),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_low),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_low),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_low),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_12),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(Q),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_low),
        .RIU_WR_DATA(xiphy_control_1),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1(xiphy_control_2),
        .RX_BIT_CTRL_IN2(xiphy_control_3),
        .RX_BIT_CTRL_IN3(xiphy_control_4),
        .RX_BIT_CTRL_IN4(xiphy_control_5),
        .RX_BIT_CTRL_IN5(xiphy_control_6),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1(RX_BIT_CTRL_OUT1),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_low),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1(xiphy_control_7),
        .TX_BIT_CTRL_IN2(xiphy_control_8),
        .TX_BIT_CTRL_IN3(xiphy_control_9),
        .TX_BIT_CTRL_IN4(xiphy_control_10),
        .TX_BIT_CTRL_IN5(xiphy_control_11),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1(TX_BIT_CTRL_OUT1),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0
   (xiphy_control_0,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    riu2clb_valid_upp,
    xiphy_control_1,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    pll_clk,
    riu_clk,
    xiphy_control_2,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_3,
    RX_BIT_CTRL_OUT,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    xiphy_control_7,
    TX_BIT_CTRL_OUT,
    xiphy_control_8,
    xiphy_control_9,
    xiphy_control_10,
    xiphy_control_11,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    xiphy_control_12);
  output [0:0]xiphy_control_0;
  output ndqs_gt_out_1;
  output pdqs_gt_out_1;
  output riu2clb_valid_upp;
  output [0:0]xiphy_control_1;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [3:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_0;
  input pdqs_gt_out_0;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]xiphy_control_2;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_3;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [5:0]xiphy_control_12;

  wire [39:0]BIT_CTRL_OUT;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [3:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [5:0]xiphy_control_12;
  wire [0:0]xiphy_control_2;
  wire [15:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_629;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("FALSE"),
    .EN_OTHER_PCLK("FALSE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(xiphy_control_0),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte,xiphy_control_n_628,xiphy_control_n_629}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_0),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_1),
        .PCLK_NIBBLE_IN(pdqs_gt_out_0),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_1),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_upp),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_upp),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_upp),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_upp),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_upp),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_12),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(xiphy_control_2),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_upp),
        .RIU_WR_DATA(xiphy_control_3),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_4),
        .RX_BIT_CTRL_IN3(xiphy_control_5),
        .RX_BIT_CTRL_IN4(xiphy_control_6),
        .RX_BIT_CTRL_IN5(xiphy_control_7),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_upp),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_8),
        .TX_BIT_CTRL_IN3(xiphy_control_9),
        .TX_BIT_CTRL_IN4(xiphy_control_10),
        .TX_BIT_CTRL_IN5(xiphy_control_11),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_691
   (xiphy_control_0,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    riu2clb_valid_upp,
    xiphy_control_1,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    pll_clk,
    riu_clk,
    xiphy_control_2,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_3,
    RX_BIT_CTRL_OUT,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    xiphy_control_7,
    TX_BIT_CTRL_OUT,
    xiphy_control_8,
    xiphy_control_9,
    xiphy_control_10,
    xiphy_control_11,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    xiphy_control_12);
  output [0:0]xiphy_control_0;
  output ndqs_gt_out_1;
  output pdqs_gt_out_1;
  output riu2clb_valid_upp;
  output [0:0]xiphy_control_1;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [3:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_0;
  input pdqs_gt_out_0;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]xiphy_control_2;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_3;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [5:0]xiphy_control_12;

  wire [39:0]BIT_CTRL_OUT;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [3:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [5:0]xiphy_control_12;
  wire [0:0]xiphy_control_2;
  wire [15:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_629;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("FALSE"),
    .EN_OTHER_PCLK("FALSE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(xiphy_control_0),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte,xiphy_control_n_628,xiphy_control_n_629}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_0),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_1),
        .PCLK_NIBBLE_IN(pdqs_gt_out_0),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_1),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_upp),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_upp),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_upp),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_upp),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_upp),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_12),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(xiphy_control_2),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_upp),
        .RIU_WR_DATA(xiphy_control_3),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_4),
        .RX_BIT_CTRL_IN3(xiphy_control_5),
        .RX_BIT_CTRL_IN4(xiphy_control_6),
        .RX_BIT_CTRL_IN5(xiphy_control_7),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_upp),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_8),
        .TX_BIT_CTRL_IN3(xiphy_control_9),
        .TX_BIT_CTRL_IN4(xiphy_control_10),
        .TX_BIT_CTRL_IN5(xiphy_control_11),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_706
   (xiphy_control_0,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    riu2clb_valid_upp,
    xiphy_control_1,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    pll_clk,
    riu_clk,
    xiphy_control_2,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_3,
    RX_BIT_CTRL_OUT,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    xiphy_control_7,
    TX_BIT_CTRL_OUT,
    xiphy_control_8,
    xiphy_control_9,
    xiphy_control_10,
    xiphy_control_11,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    xiphy_control_12);
  output [0:0]xiphy_control_0;
  output ndqs_gt_out_1;
  output pdqs_gt_out_1;
  output riu2clb_valid_upp;
  output [0:0]xiphy_control_1;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [3:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_0;
  input pdqs_gt_out_0;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]xiphy_control_2;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_3;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [5:0]xiphy_control_12;

  wire [39:0]BIT_CTRL_OUT;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [3:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [5:0]xiphy_control_12;
  wire [0:0]xiphy_control_2;
  wire [15:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_629;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("FALSE"),
    .EN_OTHER_PCLK("FALSE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(xiphy_control_0),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte,xiphy_control_n_628,xiphy_control_n_629}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_0),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_1),
        .PCLK_NIBBLE_IN(pdqs_gt_out_0),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_1),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_upp),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_upp),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_upp),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_upp),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_upp),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_12),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(xiphy_control_2),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_upp),
        .RIU_WR_DATA(xiphy_control_3),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_4),
        .RX_BIT_CTRL_IN3(xiphy_control_5),
        .RX_BIT_CTRL_IN4(xiphy_control_6),
        .RX_BIT_CTRL_IN5(xiphy_control_7),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_upp),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_8),
        .TX_BIT_CTRL_IN3(xiphy_control_9),
        .TX_BIT_CTRL_IN4(xiphy_control_10),
        .TX_BIT_CTRL_IN5(xiphy_control_11),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_721
   (xiphy_control_0,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    riu2clb_valid_upp,
    xiphy_control_1,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    pll_clk,
    riu_clk,
    xiphy_control_2,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_3,
    RX_BIT_CTRL_OUT,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    xiphy_control_7,
    TX_BIT_CTRL_OUT,
    xiphy_control_8,
    xiphy_control_9,
    xiphy_control_10,
    xiphy_control_11,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    xiphy_control_12);
  output [0:0]xiphy_control_0;
  output ndqs_gt_out_1;
  output pdqs_gt_out_1;
  output riu2clb_valid_upp;
  output [0:0]xiphy_control_1;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [3:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_0;
  input pdqs_gt_out_0;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]xiphy_control_2;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_3;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [5:0]xiphy_control_12;

  wire [39:0]BIT_CTRL_OUT;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [3:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [5:0]xiphy_control_12;
  wire [0:0]xiphy_control_2;
  wire [15:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_629;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("FALSE"),
    .EN_OTHER_PCLK("FALSE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(xiphy_control_0),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte,xiphy_control_n_628,xiphy_control_n_629}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_0),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_1),
        .PCLK_NIBBLE_IN(pdqs_gt_out_0),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_1),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_upp),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_upp),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_upp),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_upp),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_upp),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_12),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(xiphy_control_2),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_upp),
        .RIU_WR_DATA(xiphy_control_3),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_4),
        .RX_BIT_CTRL_IN3(xiphy_control_5),
        .RX_BIT_CTRL_IN4(xiphy_control_6),
        .RX_BIT_CTRL_IN5(xiphy_control_7),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_upp),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_8),
        .TX_BIT_CTRL_IN3(xiphy_control_9),
        .TX_BIT_CTRL_IN4(xiphy_control_10),
        .TX_BIT_CTRL_IN5(xiphy_control_11),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_736
   (xiphy_control_0,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    riu2clb_valid_upp,
    xiphy_control_1,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    pll_clk,
    riu_clk,
    xiphy_control_2,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_3,
    RX_BIT_CTRL_OUT,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    xiphy_control_7,
    TX_BIT_CTRL_OUT,
    xiphy_control_8,
    xiphy_control_9,
    xiphy_control_10,
    xiphy_control_11,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    xiphy_control_12);
  output [0:0]xiphy_control_0;
  output ndqs_gt_out_1;
  output pdqs_gt_out_1;
  output riu2clb_valid_upp;
  output [0:0]xiphy_control_1;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [3:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_0;
  input pdqs_gt_out_0;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]xiphy_control_2;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_3;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [5:0]xiphy_control_12;

  wire [39:0]BIT_CTRL_OUT;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [3:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [5:0]xiphy_control_12;
  wire [0:0]xiphy_control_2;
  wire [15:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_629;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("FALSE"),
    .EN_OTHER_PCLK("FALSE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(xiphy_control_0),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte,xiphy_control_n_628,xiphy_control_n_629}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_0),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_1),
        .PCLK_NIBBLE_IN(pdqs_gt_out_0),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_1),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_upp),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_upp),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_upp),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_upp),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_upp),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_12),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(xiphy_control_2),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_upp),
        .RIU_WR_DATA(xiphy_control_3),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_4),
        .RX_BIT_CTRL_IN3(xiphy_control_5),
        .RX_BIT_CTRL_IN4(xiphy_control_6),
        .RX_BIT_CTRL_IN5(xiphy_control_7),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_upp),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_8),
        .TX_BIT_CTRL_IN3(xiphy_control_9),
        .TX_BIT_CTRL_IN4(xiphy_control_10),
        .TX_BIT_CTRL_IN5(xiphy_control_11),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_751
   (xiphy_control_0,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    riu2clb_valid_upp,
    xiphy_control_1,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    pll_clk,
    riu_clk,
    xiphy_control_2,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_3,
    RX_BIT_CTRL_OUT,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    xiphy_control_7,
    TX_BIT_CTRL_OUT,
    xiphy_control_8,
    xiphy_control_9,
    xiphy_control_10,
    xiphy_control_11,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    xiphy_control_12);
  output [0:0]xiphy_control_0;
  output ndqs_gt_out_1;
  output pdqs_gt_out_1;
  output riu2clb_valid_upp;
  output [0:0]xiphy_control_1;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [3:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_0;
  input pdqs_gt_out_0;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]xiphy_control_2;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_3;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [5:0]xiphy_control_12;

  wire [39:0]BIT_CTRL_OUT;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [3:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [5:0]xiphy_control_12;
  wire [0:0]xiphy_control_2;
  wire [15:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_629;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("FALSE"),
    .EN_OTHER_PCLK("FALSE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(xiphy_control_0),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte,xiphy_control_n_628,xiphy_control_n_629}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_0),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_1),
        .PCLK_NIBBLE_IN(pdqs_gt_out_0),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_1),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_upp),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_upp),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_upp),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_upp),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_upp),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_12),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(xiphy_control_2),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_upp),
        .RIU_WR_DATA(xiphy_control_3),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_4),
        .RX_BIT_CTRL_IN3(xiphy_control_5),
        .RX_BIT_CTRL_IN4(xiphy_control_6),
        .RX_BIT_CTRL_IN5(xiphy_control_7),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_upp),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_8),
        .TX_BIT_CTRL_IN3(xiphy_control_9),
        .TX_BIT_CTRL_IN4(xiphy_control_10),
        .TX_BIT_CTRL_IN5(xiphy_control_11),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_766
   (xiphy_control_0,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    riu2clb_valid_upp,
    xiphy_control_1,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    pll_clk,
    riu_clk,
    xiphy_control_2,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_3,
    RX_BIT_CTRL_OUT,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    xiphy_control_7,
    TX_BIT_CTRL_OUT,
    xiphy_control_8,
    xiphy_control_9,
    xiphy_control_10,
    xiphy_control_11,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    xiphy_control_12);
  output [0:0]xiphy_control_0;
  output ndqs_gt_out_1;
  output pdqs_gt_out_1;
  output riu2clb_valid_upp;
  output [0:0]xiphy_control_1;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [3:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_0;
  input pdqs_gt_out_0;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]xiphy_control_2;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_3;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [5:0]xiphy_control_12;

  wire [39:0]BIT_CTRL_OUT;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [3:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [5:0]xiphy_control_12;
  wire [0:0]xiphy_control_2;
  wire [15:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_629;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("FALSE"),
    .EN_OTHER_PCLK("FALSE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(xiphy_control_0),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte,xiphy_control_n_628,xiphy_control_n_629}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_0),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_1),
        .PCLK_NIBBLE_IN(pdqs_gt_out_0),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_1),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_upp),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_upp),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_upp),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_upp),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_upp),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_12),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(xiphy_control_2),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_upp),
        .RIU_WR_DATA(xiphy_control_3),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_4),
        .RX_BIT_CTRL_IN3(xiphy_control_5),
        .RX_BIT_CTRL_IN4(xiphy_control_6),
        .RX_BIT_CTRL_IN5(xiphy_control_7),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_upp),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_8),
        .TX_BIT_CTRL_IN3(xiphy_control_9),
        .TX_BIT_CTRL_IN4(xiphy_control_10),
        .TX_BIT_CTRL_IN5(xiphy_control_11),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized0_814
   (xiphy_control_0,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    riu2clb_valid_upp,
    xiphy_control_1,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    phy2iob_odt_out_byte,
    en_vtc_riuclk,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    pll_clk,
    riu_clk,
    xiphy_control_2,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_3,
    RX_BIT_CTRL_OUT,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    xiphy_control_7,
    TX_BIT_CTRL_OUT,
    xiphy_control_8,
    xiphy_control_9,
    xiphy_control_10,
    xiphy_control_11,
    BIT_CTRL_OUT,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    xiphy_control_12);
  output [0:0]xiphy_control_0;
  output ndqs_gt_out_1;
  output pdqs_gt_out_1;
  output riu2clb_valid_upp;
  output [0:0]xiphy_control_1;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  output [3:0]phy2iob_odt_out_byte;
  input en_vtc_riuclk;
  input ndqs_gt_out_0;
  input pdqs_gt_out_0;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]xiphy_control_2;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_3;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [3:0]ch0_mcal_clb2phy_rden_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [3:0]ch0_mcal_clb2phy_t_b_upp;
  input [5:0]xiphy_control_12;

  wire [39:0]BIT_CTRL_OUT;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire [3:0]ch0_mcal_clb2phy_t_b_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [3:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [3:0]phy2iob_odt_out_byte;
  wire [0:0]pll_clk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [5:0]xiphy_control_12;
  wire [0:0]xiphy_control_2;
  wire [15:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_628;
  wire xiphy_control_n_629;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("TRUE"),
    .EN_OTHER_NCLK("FALSE"),
    .EN_OTHER_PCLK("FALSE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_90"),
    .RX_CLK_PHASE_P("SHIFT_90"),
    .RX_GATING("ENABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("ENABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(xiphy_control_0),
        .DYN_DCI({xiphy_control_n_623,phy2iob_odt_out_byte,xiphy_control_n_628,xiphy_control_n_629}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_0),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_1),
        .PCLK_NIBBLE_IN(pdqs_gt_out_0),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_1),
        .PHY_RDCS0(ch0_mcal_clb2phy_rdcs0_upp),
        .PHY_RDCS1(ch0_mcal_clb2phy_rdcs1_upp),
        .PHY_RDEN(ch0_mcal_clb2phy_rden_upp),
        .PHY_WRCS0(ch0_mcal_clb2phy_wrcs0_upp),
        .PHY_WRCS1(ch0_mcal_clb2phy_wrcs1_upp),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_12),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(xiphy_control_2),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_upp),
        .RIU_WR_DATA(xiphy_control_3),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2(xiphy_control_4),
        .RX_BIT_CTRL_IN3(xiphy_control_5),
        .RX_BIT_CTRL_IN4(xiphy_control_6),
        .RX_BIT_CTRL_IN5(xiphy_control_7),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(ch0_mcal_clb2phy_t_b_upp),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2(xiphy_control_8),
        .TX_BIT_CTRL_IN3(xiphy_control_9),
        .TX_BIT_CTRL_IN4(xiphy_control_10),
        .TX_BIT_CTRL_IN5(xiphy_control_11),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized1
   (D,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    riu2clb_valid_low,
    xiphy_control_0,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT1,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT1,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    en_vtc_riuclk,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    pll_clk,
    riu_clk,
    Q,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_1,
    RX_BIT_CTRL_OUT,
    xiphy_control_2,
    xiphy_control_3,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    TX_BIT_CTRL_OUT,
    xiphy_control_7,
    xiphy_control_8,
    xiphy_control_9,
    xiphy_control_10,
    xiphy_control_11,
    BIT_CTRL_OUT,
    clb2phy_t_b_low,
    xiphy_control_12);
  output [0:0]D;
  output ndqs_gt_out_0;
  output pdqs_gt_out_0;
  output riu2clb_valid_low;
  output [0:0]xiphy_control_0;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT1;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT1;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  input en_vtc_riuclk;
  input ndqs_gt_out_1;
  input pdqs_gt_out_1;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_1;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_2;
  input [39:0]xiphy_control_3;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_7;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]clb2phy_t_b_low;
  input [5:0]xiphy_control_12;

  wire [39:0]BIT_CTRL_OUT;
  wire [0:0]D;
  wire [0:0]Q;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT1;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT1;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]clb2phy_t_b_low;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [0:0]pll_clk;
  wire riu2clb_valid_low;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [15:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [5:0]xiphy_control_12;
  wire [39:0]xiphy_control_2;
  wire [39:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_624;
  wire xiphy_control_n_625;
  wire xiphy_control_n_626;
  wire xiphy_control_n_627;
  wire xiphy_control_n_628;
  wire xiphy_control_n_629;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("FALSE"),
    .EN_OTHER_NCLK("FALSE"),
    .EN_OTHER_PCLK("FALSE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_0"),
    .RX_CLK_PHASE_P("SHIFT_0"),
    .RX_GATING("DISABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("DISABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(D),
        .DYN_DCI({xiphy_control_n_623,xiphy_control_n_624,xiphy_control_n_625,xiphy_control_n_626,xiphy_control_n_627,xiphy_control_n_628,xiphy_control_n_629}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_1),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_0),
        .PCLK_NIBBLE_IN(pdqs_gt_out_1),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_0),
        .PHY_RDCS0({1'b0,1'b0,1'b0,1'b0}),
        .PHY_RDCS1({1'b0,1'b0,1'b0,1'b0}),
        .PHY_RDEN({1'b0,1'b0,1'b0,1'b0}),
        .PHY_WRCS0({1'b0,1'b0,1'b0,1'b0}),
        .PHY_WRCS1({1'b0,1'b0,1'b0,1'b0}),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_12),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(Q),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_low),
        .RIU_WR_DATA(xiphy_control_1),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1(xiphy_control_2),
        .RX_BIT_CTRL_IN2(xiphy_control_3),
        .RX_BIT_CTRL_IN3(xiphy_control_4),
        .RX_BIT_CTRL_IN4(xiphy_control_5),
        .RX_BIT_CTRL_IN5(xiphy_control_6),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1(RX_BIT_CTRL_OUT1),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(clb2phy_t_b_low),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1(xiphy_control_7),
        .TX_BIT_CTRL_IN2(xiphy_control_8),
        .TX_BIT_CTRL_IN3(xiphy_control_9),
        .TX_BIT_CTRL_IN4(xiphy_control_10),
        .TX_BIT_CTRL_IN5(xiphy_control_11),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1(TX_BIT_CTRL_OUT1),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized1_783
   (xiphy_control_0,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    riu2clb_valid_upp,
    xiphy_control_1,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT1,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    RX_BIT_CTRL_OUT6,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT1,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT6,
    TX_BIT_CTRL_OUT_TRI,
    en_vtc_riuclk,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    pll_clk,
    riu_clk,
    xiphy_control_2,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_3,
    RX_BIT_CTRL_OUT,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    xiphy_control_7,
    xiphy_control_8,
    xiphy_control_9,
    TX_BIT_CTRL_OUT,
    xiphy_control_10,
    xiphy_control_11,
    xiphy_control_12,
    xiphy_control_13,
    xiphy_control_14,
    xiphy_control_15,
    BIT_CTRL_OUT,
    clb2phy_t_b_low,
    xiphy_control_16);
  output [0:0]xiphy_control_0;
  output ndqs_gt_out_1;
  output pdqs_gt_out_1;
  output riu2clb_valid_upp;
  output [0:0]xiphy_control_1;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT1;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]RX_BIT_CTRL_OUT6;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT1;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT6;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  input en_vtc_riuclk;
  input ndqs_gt_out_0;
  input pdqs_gt_out_0;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]xiphy_control_2;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_3;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]xiphy_control_7;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]xiphy_control_12;
  input [39:0]xiphy_control_13;
  input [39:0]xiphy_control_14;
  input [39:0]xiphy_control_15;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]clb2phy_t_b_low;
  input [5:0]xiphy_control_16;

  wire [39:0]BIT_CTRL_OUT;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT1;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]RX_BIT_CTRL_OUT6;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT1;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT6;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]clb2phy_t_b_low;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [0:0]pll_clk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [39:0]xiphy_control_12;
  wire [39:0]xiphy_control_13;
  wire [39:0]xiphy_control_14;
  wire [39:0]xiphy_control_15;
  wire [5:0]xiphy_control_16;
  wire [0:0]xiphy_control_2;
  wire [15:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_623;
  wire xiphy_control_n_624;
  wire xiphy_control_n_625;
  wire xiphy_control_n_626;
  wire xiphy_control_n_627;
  wire xiphy_control_n_628;
  wire xiphy_control_n_629;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("FALSE"),
    .EN_OTHER_NCLK("FALSE"),
    .EN_OTHER_PCLK("FALSE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_0"),
    .RX_CLK_PHASE_P("SHIFT_0"),
    .RX_GATING("DISABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("DISABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(xiphy_control_0),
        .DYN_DCI({xiphy_control_n_623,xiphy_control_n_624,xiphy_control_n_625,xiphy_control_n_626,xiphy_control_n_627,xiphy_control_n_628,xiphy_control_n_629}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_0),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_1),
        .PCLK_NIBBLE_IN(pdqs_gt_out_0),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_1),
        .PHY_RDCS0({1'b0,1'b0,1'b0,1'b0}),
        .PHY_RDCS1({1'b0,1'b0,1'b0,1'b0}),
        .PHY_RDEN({1'b0,1'b0,1'b0,1'b0}),
        .PHY_WRCS0({1'b0,1'b0,1'b0,1'b0}),
        .PHY_WRCS1({1'b0,1'b0,1'b0,1'b0}),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_16),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(xiphy_control_2),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_upp),
        .RIU_WR_DATA(xiphy_control_3),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1(xiphy_control_4),
        .RX_BIT_CTRL_IN2(xiphy_control_5),
        .RX_BIT_CTRL_IN3(xiphy_control_6),
        .RX_BIT_CTRL_IN4(xiphy_control_7),
        .RX_BIT_CTRL_IN5(xiphy_control_8),
        .RX_BIT_CTRL_IN6(xiphy_control_9),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1(RX_BIT_CTRL_OUT1),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6(RX_BIT_CTRL_OUT6),
        .TBYTE_IN(clb2phy_t_b_low),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1(xiphy_control_10),
        .TX_BIT_CTRL_IN2(xiphy_control_11),
        .TX_BIT_CTRL_IN3(xiphy_control_12),
        .TX_BIT_CTRL_IN4(xiphy_control_13),
        .TX_BIT_CTRL_IN5(xiphy_control_14),
        .TX_BIT_CTRL_IN6(xiphy_control_15),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1(TX_BIT_CTRL_OUT1),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6(TX_BIT_CTRL_OUT6),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized1_797
   (D,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    riu2clb_valid_low,
    xiphy_control_0,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT1,
    RX_BIT_CTRL_OUT2,
    RX_BIT_CTRL_OUT3,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT1,
    TX_BIT_CTRL_OUT2,
    TX_BIT_CTRL_OUT3,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT_TRI,
    en_vtc_riuclk,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    pll_clk,
    riu_clk,
    Q,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_1,
    RX_BIT_CTRL_OUT,
    xiphy_control_2,
    xiphy_control_3,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    TX_BIT_CTRL_OUT,
    xiphy_control_7,
    xiphy_control_8,
    xiphy_control_9,
    xiphy_control_10,
    xiphy_control_11,
    BIT_CTRL_OUT,
    clb2phy_t_b_low,
    xiphy_control_12);
  output [0:0]D;
  output ndqs_gt_out_0;
  output pdqs_gt_out_0;
  output riu2clb_valid_low;
  output [0:0]xiphy_control_0;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT1;
  output [39:0]RX_BIT_CTRL_OUT2;
  output [39:0]RX_BIT_CTRL_OUT3;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT1;
  output [39:0]TX_BIT_CTRL_OUT2;
  output [39:0]TX_BIT_CTRL_OUT3;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  input en_vtc_riuclk;
  input ndqs_gt_out_1;
  input pdqs_gt_out_1;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]Q;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_1;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_2;
  input [39:0]xiphy_control_3;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_7;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]xiphy_control_10;
  input [39:0]xiphy_control_11;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]clb2phy_t_b_low;
  input [5:0]xiphy_control_12;

  wire [39:0]BIT_CTRL_OUT;
  wire [0:0]D;
  wire [0:0]Q;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT1;
  wire [39:0]RX_BIT_CTRL_OUT2;
  wire [39:0]RX_BIT_CTRL_OUT3;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT1;
  wire [39:0]TX_BIT_CTRL_OUT2;
  wire [39:0]TX_BIT_CTRL_OUT3;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]clb2phy_t_b_low;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [0:0]pll_clk;
  wire riu2clb_valid_low;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [15:0]xiphy_control_1;
  wire [39:0]xiphy_control_10;
  wire [39:0]xiphy_control_11;
  wire [5:0]xiphy_control_12;
  wire [39:0]xiphy_control_2;
  wire [39:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_263;
  wire xiphy_control_n_264;
  wire xiphy_control_n_265;
  wire xiphy_control_n_266;
  wire xiphy_control_n_267;
  wire xiphy_control_n_268;
  wire xiphy_control_n_269;
  wire xiphy_control_n_270;
  wire xiphy_control_n_271;
  wire xiphy_control_n_272;
  wire xiphy_control_n_273;
  wire xiphy_control_n_274;
  wire xiphy_control_n_275;
  wire xiphy_control_n_276;
  wire xiphy_control_n_277;
  wire xiphy_control_n_278;
  wire xiphy_control_n_279;
  wire xiphy_control_n_280;
  wire xiphy_control_n_281;
  wire xiphy_control_n_282;
  wire xiphy_control_n_283;
  wire xiphy_control_n_284;
  wire xiphy_control_n_285;
  wire xiphy_control_n_286;
  wire xiphy_control_n_287;
  wire xiphy_control_n_288;
  wire xiphy_control_n_289;
  wire xiphy_control_n_290;
  wire xiphy_control_n_291;
  wire xiphy_control_n_292;
  wire xiphy_control_n_293;
  wire xiphy_control_n_294;
  wire xiphy_control_n_295;
  wire xiphy_control_n_296;
  wire xiphy_control_n_297;
  wire xiphy_control_n_298;
  wire xiphy_control_n_299;
  wire xiphy_control_n_300;
  wire xiphy_control_n_301;
  wire xiphy_control_n_302;
  wire xiphy_control_n_543;
  wire xiphy_control_n_544;
  wire xiphy_control_n_545;
  wire xiphy_control_n_546;
  wire xiphy_control_n_547;
  wire xiphy_control_n_548;
  wire xiphy_control_n_549;
  wire xiphy_control_n_550;
  wire xiphy_control_n_551;
  wire xiphy_control_n_552;
  wire xiphy_control_n_553;
  wire xiphy_control_n_554;
  wire xiphy_control_n_555;
  wire xiphy_control_n_556;
  wire xiphy_control_n_557;
  wire xiphy_control_n_558;
  wire xiphy_control_n_559;
  wire xiphy_control_n_560;
  wire xiphy_control_n_561;
  wire xiphy_control_n_562;
  wire xiphy_control_n_563;
  wire xiphy_control_n_564;
  wire xiphy_control_n_565;
  wire xiphy_control_n_566;
  wire xiphy_control_n_567;
  wire xiphy_control_n_568;
  wire xiphy_control_n_569;
  wire xiphy_control_n_570;
  wire xiphy_control_n_571;
  wire xiphy_control_n_572;
  wire xiphy_control_n_573;
  wire xiphy_control_n_574;
  wire xiphy_control_n_575;
  wire xiphy_control_n_576;
  wire xiphy_control_n_577;
  wire xiphy_control_n_578;
  wire xiphy_control_n_579;
  wire xiphy_control_n_580;
  wire xiphy_control_n_581;
  wire xiphy_control_n_582;
  wire xiphy_control_n_623;
  wire xiphy_control_n_624;
  wire xiphy_control_n_625;
  wire xiphy_control_n_626;
  wire xiphy_control_n_627;
  wire xiphy_control_n_628;
  wire xiphy_control_n_629;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("FALSE"),
    .EN_OTHER_NCLK("FALSE"),
    .EN_OTHER_PCLK("FALSE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_0"),
    .RX_CLK_PHASE_P("SHIFT_0"),
    .RX_GATING("DISABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("DISABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(D),
        .DYN_DCI({xiphy_control_n_623,xiphy_control_n_624,xiphy_control_n_625,xiphy_control_n_626,xiphy_control_n_627,xiphy_control_n_628,xiphy_control_n_629}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_1),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_0),
        .PCLK_NIBBLE_IN(pdqs_gt_out_1),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_0),
        .PHY_RDCS0({1'b0,1'b0,1'b0,1'b0}),
        .PHY_RDCS1({1'b0,1'b0,1'b0,1'b0}),
        .PHY_RDEN({1'b0,1'b0,1'b0,1'b0}),
        .PHY_WRCS0({1'b0,1'b0,1'b0,1'b0}),
        .PHY_WRCS1({1'b0,1'b0,1'b0,1'b0}),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_12),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(Q),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_low),
        .RIU_WR_DATA(xiphy_control_1),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1(xiphy_control_2),
        .RX_BIT_CTRL_IN2(xiphy_control_3),
        .RX_BIT_CTRL_IN3(xiphy_control_4),
        .RX_BIT_CTRL_IN4(xiphy_control_5),
        .RX_BIT_CTRL_IN5(xiphy_control_6),
        .RX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1(RX_BIT_CTRL_OUT1),
        .RX_BIT_CTRL_OUT2(RX_BIT_CTRL_OUT2),
        .RX_BIT_CTRL_OUT3(RX_BIT_CTRL_OUT3),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6({xiphy_control_n_263,xiphy_control_n_264,xiphy_control_n_265,xiphy_control_n_266,xiphy_control_n_267,xiphy_control_n_268,xiphy_control_n_269,xiphy_control_n_270,xiphy_control_n_271,xiphy_control_n_272,xiphy_control_n_273,xiphy_control_n_274,xiphy_control_n_275,xiphy_control_n_276,xiphy_control_n_277,xiphy_control_n_278,xiphy_control_n_279,xiphy_control_n_280,xiphy_control_n_281,xiphy_control_n_282,xiphy_control_n_283,xiphy_control_n_284,xiphy_control_n_285,xiphy_control_n_286,xiphy_control_n_287,xiphy_control_n_288,xiphy_control_n_289,xiphy_control_n_290,xiphy_control_n_291,xiphy_control_n_292,xiphy_control_n_293,xiphy_control_n_294,xiphy_control_n_295,xiphy_control_n_296,xiphy_control_n_297,xiphy_control_n_298,xiphy_control_n_299,xiphy_control_n_300,xiphy_control_n_301,xiphy_control_n_302}),
        .TBYTE_IN(clb2phy_t_b_low),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1(xiphy_control_7),
        .TX_BIT_CTRL_IN2(xiphy_control_8),
        .TX_BIT_CTRL_IN3(xiphy_control_9),
        .TX_BIT_CTRL_IN4(xiphy_control_10),
        .TX_BIT_CTRL_IN5(xiphy_control_11),
        .TX_BIT_CTRL_IN6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1(TX_BIT_CTRL_OUT1),
        .TX_BIT_CTRL_OUT2(TX_BIT_CTRL_OUT2),
        .TX_BIT_CTRL_OUT3(TX_BIT_CTRL_OUT3),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6({xiphy_control_n_543,xiphy_control_n_544,xiphy_control_n_545,xiphy_control_n_546,xiphy_control_n_547,xiphy_control_n_548,xiphy_control_n_549,xiphy_control_n_550,xiphy_control_n_551,xiphy_control_n_552,xiphy_control_n_553,xiphy_control_n_554,xiphy_control_n_555,xiphy_control_n_556,xiphy_control_n_557,xiphy_control_n_558,xiphy_control_n_559,xiphy_control_n_560,xiphy_control_n_561,xiphy_control_n_562,xiphy_control_n_563,xiphy_control_n_564,xiphy_control_n_565,xiphy_control_n_566,xiphy_control_n_567,xiphy_control_n_568,xiphy_control_n_569,xiphy_control_n_570,xiphy_control_n_571,xiphy_control_n_572,xiphy_control_n_573,xiphy_control_n_574,xiphy_control_n_575,xiphy_control_n_576,xiphy_control_n_577,xiphy_control_n_578,xiphy_control_n_579,xiphy_control_n_580,xiphy_control_n_581,xiphy_control_n_582}),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_control_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_control_wrapper__parameterized1_798
   (xiphy_control_0,
    ndqs_gt_out_1,
    pdqs_gt_out_1,
    riu2clb_valid_upp,
    xiphy_control_1,
    RIU_RD_DATA,
    RX_BIT_CTRL_OUT0,
    RX_BIT_CTRL_OUT4,
    RX_BIT_CTRL_OUT5,
    RX_BIT_CTRL_OUT6,
    TX_BIT_CTRL_OUT0,
    TX_BIT_CTRL_OUT4,
    TX_BIT_CTRL_OUT5,
    TX_BIT_CTRL_OUT6,
    TX_BIT_CTRL_OUT_TRI,
    en_vtc_riuclk,
    ndqs_gt_out_0,
    pdqs_gt_out_0,
    pll_clk,
    riu_clk,
    xiphy_control_2,
    clb2riu_wr_en_lut,
    SR,
    xiphy_control_3,
    RX_BIT_CTRL_OUT,
    xiphy_control_4,
    xiphy_control_5,
    xiphy_control_6,
    TX_BIT_CTRL_OUT,
    xiphy_control_7,
    xiphy_control_8,
    xiphy_control_9,
    BIT_CTRL_OUT,
    clb2phy_t_b_low,
    xiphy_control_10);
  output [0:0]xiphy_control_0;
  output ndqs_gt_out_1;
  output pdqs_gt_out_1;
  output riu2clb_valid_upp;
  output [0:0]xiphy_control_1;
  output [15:0]RIU_RD_DATA;
  output [39:0]RX_BIT_CTRL_OUT0;
  output [39:0]RX_BIT_CTRL_OUT4;
  output [39:0]RX_BIT_CTRL_OUT5;
  output [39:0]RX_BIT_CTRL_OUT6;
  output [39:0]TX_BIT_CTRL_OUT0;
  output [39:0]TX_BIT_CTRL_OUT4;
  output [39:0]TX_BIT_CTRL_OUT5;
  output [39:0]TX_BIT_CTRL_OUT6;
  output [39:0]TX_BIT_CTRL_OUT_TRI;
  input en_vtc_riuclk;
  input ndqs_gt_out_0;
  input pdqs_gt_out_0;
  input [0:0]pll_clk;
  input riu_clk;
  input [0:0]xiphy_control_2;
  input clb2riu_wr_en_lut;
  input [0:0]SR;
  input [15:0]xiphy_control_3;
  input [39:0]RX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_4;
  input [39:0]xiphy_control_5;
  input [39:0]xiphy_control_6;
  input [39:0]TX_BIT_CTRL_OUT;
  input [39:0]xiphy_control_7;
  input [39:0]xiphy_control_8;
  input [39:0]xiphy_control_9;
  input [39:0]BIT_CTRL_OUT;
  input [3:0]clb2phy_t_b_low;
  input [5:0]xiphy_control_10;

  wire [39:0]BIT_CTRL_OUT;
  wire [15:0]RIU_RD_DATA;
  wire [39:0]RX_BIT_CTRL_OUT;
  wire [39:0]RX_BIT_CTRL_OUT0;
  wire [39:0]RX_BIT_CTRL_OUT4;
  wire [39:0]RX_BIT_CTRL_OUT5;
  wire [39:0]RX_BIT_CTRL_OUT6;
  wire [0:0]SR;
  wire [39:0]TX_BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT0;
  wire [39:0]TX_BIT_CTRL_OUT4;
  wire [39:0]TX_BIT_CTRL_OUT5;
  wire [39:0]TX_BIT_CTRL_OUT6;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [3:0]clb2phy_t_b_low;
  wire clb2riu_wr_en_lut;
  wire en_vtc_riuclk;
  wire ndqs_gt_out_0;
  wire ndqs_gt_out_1;
  wire pdqs_gt_out_0;
  wire pdqs_gt_out_1;
  wire [0:0]pll_clk;
  wire riu2clb_valid_upp;
  wire riu_clk;
  wire [0:0]xiphy_control_0;
  wire [0:0]xiphy_control_1;
  wire [5:0]xiphy_control_10;
  wire [0:0]xiphy_control_2;
  wire [15:0]xiphy_control_3;
  wire [39:0]xiphy_control_4;
  wire [39:0]xiphy_control_5;
  wire [39:0]xiphy_control_6;
  wire [39:0]xiphy_control_7;
  wire [39:0]xiphy_control_8;
  wire [39:0]xiphy_control_9;
  wire xiphy_control_n_0;
  wire xiphy_control_n_1;
  wire xiphy_control_n_100;
  wire xiphy_control_n_101;
  wire xiphy_control_n_102;
  wire xiphy_control_n_103;
  wire xiphy_control_n_104;
  wire xiphy_control_n_105;
  wire xiphy_control_n_106;
  wire xiphy_control_n_107;
  wire xiphy_control_n_108;
  wire xiphy_control_n_109;
  wire xiphy_control_n_110;
  wire xiphy_control_n_111;
  wire xiphy_control_n_112;
  wire xiphy_control_n_113;
  wire xiphy_control_n_114;
  wire xiphy_control_n_115;
  wire xiphy_control_n_116;
  wire xiphy_control_n_117;
  wire xiphy_control_n_118;
  wire xiphy_control_n_119;
  wire xiphy_control_n_120;
  wire xiphy_control_n_121;
  wire xiphy_control_n_122;
  wire xiphy_control_n_123;
  wire xiphy_control_n_124;
  wire xiphy_control_n_125;
  wire xiphy_control_n_126;
  wire xiphy_control_n_127;
  wire xiphy_control_n_128;
  wire xiphy_control_n_129;
  wire xiphy_control_n_130;
  wire xiphy_control_n_131;
  wire xiphy_control_n_132;
  wire xiphy_control_n_133;
  wire xiphy_control_n_134;
  wire xiphy_control_n_135;
  wire xiphy_control_n_136;
  wire xiphy_control_n_137;
  wire xiphy_control_n_138;
  wire xiphy_control_n_139;
  wire xiphy_control_n_140;
  wire xiphy_control_n_141;
  wire xiphy_control_n_142;
  wire xiphy_control_n_143;
  wire xiphy_control_n_144;
  wire xiphy_control_n_145;
  wire xiphy_control_n_146;
  wire xiphy_control_n_147;
  wire xiphy_control_n_148;
  wire xiphy_control_n_149;
  wire xiphy_control_n_150;
  wire xiphy_control_n_151;
  wire xiphy_control_n_152;
  wire xiphy_control_n_153;
  wire xiphy_control_n_154;
  wire xiphy_control_n_155;
  wire xiphy_control_n_156;
  wire xiphy_control_n_157;
  wire xiphy_control_n_158;
  wire xiphy_control_n_159;
  wire xiphy_control_n_160;
  wire xiphy_control_n_161;
  wire xiphy_control_n_162;
  wire xiphy_control_n_163;
  wire xiphy_control_n_164;
  wire xiphy_control_n_165;
  wire xiphy_control_n_166;
  wire xiphy_control_n_167;
  wire xiphy_control_n_168;
  wire xiphy_control_n_169;
  wire xiphy_control_n_170;
  wire xiphy_control_n_171;
  wire xiphy_control_n_172;
  wire xiphy_control_n_173;
  wire xiphy_control_n_174;
  wire xiphy_control_n_175;
  wire xiphy_control_n_176;
  wire xiphy_control_n_177;
  wire xiphy_control_n_178;
  wire xiphy_control_n_179;
  wire xiphy_control_n_180;
  wire xiphy_control_n_181;
  wire xiphy_control_n_182;
  wire xiphy_control_n_343;
  wire xiphy_control_n_344;
  wire xiphy_control_n_345;
  wire xiphy_control_n_346;
  wire xiphy_control_n_347;
  wire xiphy_control_n_348;
  wire xiphy_control_n_349;
  wire xiphy_control_n_350;
  wire xiphy_control_n_351;
  wire xiphy_control_n_352;
  wire xiphy_control_n_353;
  wire xiphy_control_n_354;
  wire xiphy_control_n_355;
  wire xiphy_control_n_356;
  wire xiphy_control_n_357;
  wire xiphy_control_n_358;
  wire xiphy_control_n_359;
  wire xiphy_control_n_360;
  wire xiphy_control_n_361;
  wire xiphy_control_n_362;
  wire xiphy_control_n_363;
  wire xiphy_control_n_364;
  wire xiphy_control_n_365;
  wire xiphy_control_n_366;
  wire xiphy_control_n_367;
  wire xiphy_control_n_368;
  wire xiphy_control_n_369;
  wire xiphy_control_n_370;
  wire xiphy_control_n_371;
  wire xiphy_control_n_372;
  wire xiphy_control_n_373;
  wire xiphy_control_n_374;
  wire xiphy_control_n_375;
  wire xiphy_control_n_376;
  wire xiphy_control_n_377;
  wire xiphy_control_n_378;
  wire xiphy_control_n_379;
  wire xiphy_control_n_380;
  wire xiphy_control_n_381;
  wire xiphy_control_n_382;
  wire xiphy_control_n_383;
  wire xiphy_control_n_384;
  wire xiphy_control_n_385;
  wire xiphy_control_n_386;
  wire xiphy_control_n_387;
  wire xiphy_control_n_388;
  wire xiphy_control_n_389;
  wire xiphy_control_n_390;
  wire xiphy_control_n_391;
  wire xiphy_control_n_392;
  wire xiphy_control_n_393;
  wire xiphy_control_n_394;
  wire xiphy_control_n_395;
  wire xiphy_control_n_396;
  wire xiphy_control_n_397;
  wire xiphy_control_n_398;
  wire xiphy_control_n_399;
  wire xiphy_control_n_400;
  wire xiphy_control_n_401;
  wire xiphy_control_n_402;
  wire xiphy_control_n_403;
  wire xiphy_control_n_404;
  wire xiphy_control_n_405;
  wire xiphy_control_n_406;
  wire xiphy_control_n_407;
  wire xiphy_control_n_408;
  wire xiphy_control_n_409;
  wire xiphy_control_n_410;
  wire xiphy_control_n_411;
  wire xiphy_control_n_412;
  wire xiphy_control_n_413;
  wire xiphy_control_n_414;
  wire xiphy_control_n_415;
  wire xiphy_control_n_416;
  wire xiphy_control_n_417;
  wire xiphy_control_n_418;
  wire xiphy_control_n_419;
  wire xiphy_control_n_420;
  wire xiphy_control_n_421;
  wire xiphy_control_n_422;
  wire xiphy_control_n_423;
  wire xiphy_control_n_424;
  wire xiphy_control_n_425;
  wire xiphy_control_n_426;
  wire xiphy_control_n_427;
  wire xiphy_control_n_428;
  wire xiphy_control_n_429;
  wire xiphy_control_n_430;
  wire xiphy_control_n_431;
  wire xiphy_control_n_432;
  wire xiphy_control_n_433;
  wire xiphy_control_n_434;
  wire xiphy_control_n_435;
  wire xiphy_control_n_436;
  wire xiphy_control_n_437;
  wire xiphy_control_n_438;
  wire xiphy_control_n_439;
  wire xiphy_control_n_440;
  wire xiphy_control_n_441;
  wire xiphy_control_n_442;
  wire xiphy_control_n_443;
  wire xiphy_control_n_444;
  wire xiphy_control_n_445;
  wire xiphy_control_n_446;
  wire xiphy_control_n_447;
  wire xiphy_control_n_448;
  wire xiphy_control_n_449;
  wire xiphy_control_n_450;
  wire xiphy_control_n_451;
  wire xiphy_control_n_452;
  wire xiphy_control_n_453;
  wire xiphy_control_n_454;
  wire xiphy_control_n_455;
  wire xiphy_control_n_456;
  wire xiphy_control_n_457;
  wire xiphy_control_n_458;
  wire xiphy_control_n_459;
  wire xiphy_control_n_460;
  wire xiphy_control_n_461;
  wire xiphy_control_n_462;
  wire xiphy_control_n_623;
  wire xiphy_control_n_624;
  wire xiphy_control_n_625;
  wire xiphy_control_n_626;
  wire xiphy_control_n_627;
  wire xiphy_control_n_628;
  wire xiphy_control_n_629;
  wire xiphy_control_n_63;
  wire xiphy_control_n_64;
  wire xiphy_control_n_65;
  wire xiphy_control_n_66;
  wire xiphy_control_n_67;
  wire xiphy_control_n_68;
  wire xiphy_control_n_69;
  wire xiphy_control_n_70;
  wire xiphy_control_n_71;
  wire xiphy_control_n_72;
  wire xiphy_control_n_73;
  wire xiphy_control_n_74;
  wire xiphy_control_n_75;
  wire xiphy_control_n_76;
  wire xiphy_control_n_77;
  wire xiphy_control_n_78;
  wire xiphy_control_n_79;
  wire xiphy_control_n_80;
  wire xiphy_control_n_81;
  wire xiphy_control_n_82;
  wire xiphy_control_n_83;
  wire xiphy_control_n_84;
  wire xiphy_control_n_85;
  wire xiphy_control_n_86;
  wire xiphy_control_n_87;
  wire xiphy_control_n_88;
  wire xiphy_control_n_89;
  wire xiphy_control_n_90;
  wire xiphy_control_n_91;
  wire xiphy_control_n_92;
  wire xiphy_control_n_93;
  wire xiphy_control_n_94;
  wire xiphy_control_n_95;
  wire xiphy_control_n_96;
  wire xiphy_control_n_97;
  wire xiphy_control_n_98;
  wire xiphy_control_n_99;

  (* BOX_TYPE = "PRIMITIVE" *) 
  BITSLICE_CONTROL #(
    .CTRL_CLK("EXTERNAL"),
    .DIV_MODE("DIV4"),
    .EN_CLK_TO_EXT_NORTH("DISABLE"),
    .EN_CLK_TO_EXT_SOUTH("DISABLE"),
    .EN_DYN_ODLY_MODE("FALSE"),
    .EN_OTHER_NCLK("FALSE"),
    .EN_OTHER_PCLK("FALSE"),
    .IDLY_VT_TRACK("TRUE"),
    .INV_RXCLK("FALSE"),
    .ODLY_VT_TRACK("TRUE"),
    .QDLY_VT_TRACK("TRUE"),
    .READ_IDLE_COUNT(6'h1F),
    .REFCLK_SRC("PLLCLK"),
    .ROUNDING_FACTOR(16),
    .RXGATE_EXTEND("FALSE"),
    .RX_CLK_PHASE_N("SHIFT_0"),
    .RX_CLK_PHASE_P("SHIFT_0"),
    .RX_GATING("DISABLE"),
    .SELF_CALIBRATE("ENABLE"),
    .SERIAL_MODE("FALSE"),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_SPEEDUP("FAST"),
    .SIM_VERSION(2.000000),
    .TX_GATING("DISABLE")) 
    xiphy_control
       (.CLK_FROM_EXT(1'b1),
        .CLK_TO_EXT_NORTH(xiphy_control_n_0),
        .CLK_TO_EXT_SOUTH(xiphy_control_n_1),
        .DLY_RDY(xiphy_control_0),
        .DYN_DCI({xiphy_control_n_623,xiphy_control_n_624,xiphy_control_n_625,xiphy_control_n_626,xiphy_control_n_627,xiphy_control_n_628,xiphy_control_n_629}),
        .EN_VTC(en_vtc_riuclk),
        .NCLK_NIBBLE_IN(ndqs_gt_out_0),
        .NCLK_NIBBLE_OUT(ndqs_gt_out_1),
        .PCLK_NIBBLE_IN(pdqs_gt_out_0),
        .PCLK_NIBBLE_OUT(pdqs_gt_out_1),
        .PHY_RDCS0({1'b0,1'b0,1'b0,1'b0}),
        .PHY_RDCS1({1'b0,1'b0,1'b0,1'b0}),
        .PHY_RDEN({1'b0,1'b0,1'b0,1'b0}),
        .PHY_WRCS0({1'b0,1'b0,1'b0,1'b0}),
        .PHY_WRCS1({1'b0,1'b0,1'b0,1'b0}),
        .PLL_CLK(pll_clk),
        .REFCLK(1'b0),
        .RIU_ADDR(xiphy_control_10),
        .RIU_CLK(riu_clk),
        .RIU_NIBBLE_SEL(xiphy_control_2),
        .RIU_RD_DATA(RIU_RD_DATA),
        .RIU_VALID(riu2clb_valid_upp),
        .RIU_WR_DATA(xiphy_control_3),
        .RIU_WR_EN(clb2riu_wr_en_lut),
        .RST(SR),
        .RX_BIT_CTRL_IN0(RX_BIT_CTRL_OUT),
        .RX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .RX_BIT_CTRL_IN4(xiphy_control_4),
        .RX_BIT_CTRL_IN5(xiphy_control_5),
        .RX_BIT_CTRL_IN6(xiphy_control_6),
        .RX_BIT_CTRL_OUT0(RX_BIT_CTRL_OUT0),
        .RX_BIT_CTRL_OUT1({xiphy_control_n_63,xiphy_control_n_64,xiphy_control_n_65,xiphy_control_n_66,xiphy_control_n_67,xiphy_control_n_68,xiphy_control_n_69,xiphy_control_n_70,xiphy_control_n_71,xiphy_control_n_72,xiphy_control_n_73,xiphy_control_n_74,xiphy_control_n_75,xiphy_control_n_76,xiphy_control_n_77,xiphy_control_n_78,xiphy_control_n_79,xiphy_control_n_80,xiphy_control_n_81,xiphy_control_n_82,xiphy_control_n_83,xiphy_control_n_84,xiphy_control_n_85,xiphy_control_n_86,xiphy_control_n_87,xiphy_control_n_88,xiphy_control_n_89,xiphy_control_n_90,xiphy_control_n_91,xiphy_control_n_92,xiphy_control_n_93,xiphy_control_n_94,xiphy_control_n_95,xiphy_control_n_96,xiphy_control_n_97,xiphy_control_n_98,xiphy_control_n_99,xiphy_control_n_100,xiphy_control_n_101,xiphy_control_n_102}),
        .RX_BIT_CTRL_OUT2({xiphy_control_n_103,xiphy_control_n_104,xiphy_control_n_105,xiphy_control_n_106,xiphy_control_n_107,xiphy_control_n_108,xiphy_control_n_109,xiphy_control_n_110,xiphy_control_n_111,xiphy_control_n_112,xiphy_control_n_113,xiphy_control_n_114,xiphy_control_n_115,xiphy_control_n_116,xiphy_control_n_117,xiphy_control_n_118,xiphy_control_n_119,xiphy_control_n_120,xiphy_control_n_121,xiphy_control_n_122,xiphy_control_n_123,xiphy_control_n_124,xiphy_control_n_125,xiphy_control_n_126,xiphy_control_n_127,xiphy_control_n_128,xiphy_control_n_129,xiphy_control_n_130,xiphy_control_n_131,xiphy_control_n_132,xiphy_control_n_133,xiphy_control_n_134,xiphy_control_n_135,xiphy_control_n_136,xiphy_control_n_137,xiphy_control_n_138,xiphy_control_n_139,xiphy_control_n_140,xiphy_control_n_141,xiphy_control_n_142}),
        .RX_BIT_CTRL_OUT3({xiphy_control_n_143,xiphy_control_n_144,xiphy_control_n_145,xiphy_control_n_146,xiphy_control_n_147,xiphy_control_n_148,xiphy_control_n_149,xiphy_control_n_150,xiphy_control_n_151,xiphy_control_n_152,xiphy_control_n_153,xiphy_control_n_154,xiphy_control_n_155,xiphy_control_n_156,xiphy_control_n_157,xiphy_control_n_158,xiphy_control_n_159,xiphy_control_n_160,xiphy_control_n_161,xiphy_control_n_162,xiphy_control_n_163,xiphy_control_n_164,xiphy_control_n_165,xiphy_control_n_166,xiphy_control_n_167,xiphy_control_n_168,xiphy_control_n_169,xiphy_control_n_170,xiphy_control_n_171,xiphy_control_n_172,xiphy_control_n_173,xiphy_control_n_174,xiphy_control_n_175,xiphy_control_n_176,xiphy_control_n_177,xiphy_control_n_178,xiphy_control_n_179,xiphy_control_n_180,xiphy_control_n_181,xiphy_control_n_182}),
        .RX_BIT_CTRL_OUT4(RX_BIT_CTRL_OUT4),
        .RX_BIT_CTRL_OUT5(RX_BIT_CTRL_OUT5),
        .RX_BIT_CTRL_OUT6(RX_BIT_CTRL_OUT6),
        .TBYTE_IN(clb2phy_t_b_low),
        .TX_BIT_CTRL_IN0(TX_BIT_CTRL_OUT),
        .TX_BIT_CTRL_IN1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .TX_BIT_CTRL_IN4(xiphy_control_7),
        .TX_BIT_CTRL_IN5(xiphy_control_8),
        .TX_BIT_CTRL_IN6(xiphy_control_9),
        .TX_BIT_CTRL_IN_TRI(BIT_CTRL_OUT),
        .TX_BIT_CTRL_OUT0(TX_BIT_CTRL_OUT0),
        .TX_BIT_CTRL_OUT1({xiphy_control_n_343,xiphy_control_n_344,xiphy_control_n_345,xiphy_control_n_346,xiphy_control_n_347,xiphy_control_n_348,xiphy_control_n_349,xiphy_control_n_350,xiphy_control_n_351,xiphy_control_n_352,xiphy_control_n_353,xiphy_control_n_354,xiphy_control_n_355,xiphy_control_n_356,xiphy_control_n_357,xiphy_control_n_358,xiphy_control_n_359,xiphy_control_n_360,xiphy_control_n_361,xiphy_control_n_362,xiphy_control_n_363,xiphy_control_n_364,xiphy_control_n_365,xiphy_control_n_366,xiphy_control_n_367,xiphy_control_n_368,xiphy_control_n_369,xiphy_control_n_370,xiphy_control_n_371,xiphy_control_n_372,xiphy_control_n_373,xiphy_control_n_374,xiphy_control_n_375,xiphy_control_n_376,xiphy_control_n_377,xiphy_control_n_378,xiphy_control_n_379,xiphy_control_n_380,xiphy_control_n_381,xiphy_control_n_382}),
        .TX_BIT_CTRL_OUT2({xiphy_control_n_383,xiphy_control_n_384,xiphy_control_n_385,xiphy_control_n_386,xiphy_control_n_387,xiphy_control_n_388,xiphy_control_n_389,xiphy_control_n_390,xiphy_control_n_391,xiphy_control_n_392,xiphy_control_n_393,xiphy_control_n_394,xiphy_control_n_395,xiphy_control_n_396,xiphy_control_n_397,xiphy_control_n_398,xiphy_control_n_399,xiphy_control_n_400,xiphy_control_n_401,xiphy_control_n_402,xiphy_control_n_403,xiphy_control_n_404,xiphy_control_n_405,xiphy_control_n_406,xiphy_control_n_407,xiphy_control_n_408,xiphy_control_n_409,xiphy_control_n_410,xiphy_control_n_411,xiphy_control_n_412,xiphy_control_n_413,xiphy_control_n_414,xiphy_control_n_415,xiphy_control_n_416,xiphy_control_n_417,xiphy_control_n_418,xiphy_control_n_419,xiphy_control_n_420,xiphy_control_n_421,xiphy_control_n_422}),
        .TX_BIT_CTRL_OUT3({xiphy_control_n_423,xiphy_control_n_424,xiphy_control_n_425,xiphy_control_n_426,xiphy_control_n_427,xiphy_control_n_428,xiphy_control_n_429,xiphy_control_n_430,xiphy_control_n_431,xiphy_control_n_432,xiphy_control_n_433,xiphy_control_n_434,xiphy_control_n_435,xiphy_control_n_436,xiphy_control_n_437,xiphy_control_n_438,xiphy_control_n_439,xiphy_control_n_440,xiphy_control_n_441,xiphy_control_n_442,xiphy_control_n_443,xiphy_control_n_444,xiphy_control_n_445,xiphy_control_n_446,xiphy_control_n_447,xiphy_control_n_448,xiphy_control_n_449,xiphy_control_n_450,xiphy_control_n_451,xiphy_control_n_452,xiphy_control_n_453,xiphy_control_n_454,xiphy_control_n_455,xiphy_control_n_456,xiphy_control_n_457,xiphy_control_n_458,xiphy_control_n_459,xiphy_control_n_460,xiphy_control_n_461,xiphy_control_n_462}),
        .TX_BIT_CTRL_OUT4(TX_BIT_CTRL_OUT4),
        .TX_BIT_CTRL_OUT5(TX_BIT_CTRL_OUT5),
        .TX_BIT_CTRL_OUT6(TX_BIT_CTRL_OUT6),
        .TX_BIT_CTRL_OUT_TRI(TX_BIT_CTRL_OUT_TRI),
        .VTC_RDY(xiphy_control_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_riuor_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper
   (riu2clb_valid_riuclk,
    xiphy_riu_or_0,
    riu2clb_valid_low,
    riu2clb_valid_upp,
    RIU_RD_DATA,
    xiphy_riu_or_1);
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or_0;
  input riu2clb_valid_low;
  input riu2clb_valid_upp;
  input [15:0]RIU_RD_DATA;
  input [15:0]xiphy_riu_or_1;

  wire [15:0]RIU_RD_DATA;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire [15:0]xiphy_riu_or_0;
  wire [15:0]xiphy_riu_or_1;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RIU_OR #(
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000)) 
    xiphy_riu_or
       (.RIU_RD_DATA(xiphy_riu_or_0),
        .RIU_RD_DATA_LOW(RIU_RD_DATA),
        .RIU_RD_DATA_UPP(xiphy_riu_or_1),
        .RIU_RD_VALID(riu2clb_valid_riuclk),
        .RIU_RD_VALID_LOW(riu2clb_valid_low),
        .RIU_RD_VALID_UPP(riu2clb_valid_upp));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_riuor_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_694
   (riu2clb_valid_riuclk,
    xiphy_riu_or_0,
    riu2clb_valid_low,
    riu2clb_valid_upp,
    RIU_RD_DATA,
    xiphy_riu_or_1);
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or_0;
  input riu2clb_valid_low;
  input riu2clb_valid_upp;
  input [15:0]RIU_RD_DATA;
  input [15:0]xiphy_riu_or_1;

  wire [15:0]RIU_RD_DATA;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire [15:0]xiphy_riu_or_0;
  wire [15:0]xiphy_riu_or_1;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RIU_OR #(
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000)) 
    xiphy_riu_or
       (.RIU_RD_DATA(xiphy_riu_or_0),
        .RIU_RD_DATA_LOW(RIU_RD_DATA),
        .RIU_RD_DATA_UPP(xiphy_riu_or_1),
        .RIU_RD_VALID(riu2clb_valid_riuclk),
        .RIU_RD_VALID_LOW(riu2clb_valid_low),
        .RIU_RD_VALID_UPP(riu2clb_valid_upp));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_riuor_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_709
   (riu2clb_valid_riuclk,
    xiphy_riu_or_0,
    riu2clb_valid_low,
    riu2clb_valid_upp,
    RIU_RD_DATA,
    xiphy_riu_or_1);
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or_0;
  input riu2clb_valid_low;
  input riu2clb_valid_upp;
  input [15:0]RIU_RD_DATA;
  input [15:0]xiphy_riu_or_1;

  wire [15:0]RIU_RD_DATA;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire [15:0]xiphy_riu_or_0;
  wire [15:0]xiphy_riu_or_1;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RIU_OR #(
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000)) 
    xiphy_riu_or
       (.RIU_RD_DATA(xiphy_riu_or_0),
        .RIU_RD_DATA_LOW(RIU_RD_DATA),
        .RIU_RD_DATA_UPP(xiphy_riu_or_1),
        .RIU_RD_VALID(riu2clb_valid_riuclk),
        .RIU_RD_VALID_LOW(riu2clb_valid_low),
        .RIU_RD_VALID_UPP(riu2clb_valid_upp));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_riuor_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_724
   (riu2clb_valid_riuclk,
    xiphy_riu_or_0,
    riu2clb_valid_low,
    riu2clb_valid_upp,
    RIU_RD_DATA,
    xiphy_riu_or_1);
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or_0;
  input riu2clb_valid_low;
  input riu2clb_valid_upp;
  input [15:0]RIU_RD_DATA;
  input [15:0]xiphy_riu_or_1;

  wire [15:0]RIU_RD_DATA;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire [15:0]xiphy_riu_or_0;
  wire [15:0]xiphy_riu_or_1;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RIU_OR #(
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000)) 
    xiphy_riu_or
       (.RIU_RD_DATA(xiphy_riu_or_0),
        .RIU_RD_DATA_LOW(RIU_RD_DATA),
        .RIU_RD_DATA_UPP(xiphy_riu_or_1),
        .RIU_RD_VALID(riu2clb_valid_riuclk),
        .RIU_RD_VALID_LOW(riu2clb_valid_low),
        .RIU_RD_VALID_UPP(riu2clb_valid_upp));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_riuor_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_739
   (riu2clb_valid_riuclk,
    xiphy_riu_or_0,
    riu2clb_valid_low,
    riu2clb_valid_upp,
    RIU_RD_DATA,
    xiphy_riu_or_1);
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or_0;
  input riu2clb_valid_low;
  input riu2clb_valid_upp;
  input [15:0]RIU_RD_DATA;
  input [15:0]xiphy_riu_or_1;

  wire [15:0]RIU_RD_DATA;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire [15:0]xiphy_riu_or_0;
  wire [15:0]xiphy_riu_or_1;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RIU_OR #(
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000)) 
    xiphy_riu_or
       (.RIU_RD_DATA(xiphy_riu_or_0),
        .RIU_RD_DATA_LOW(RIU_RD_DATA),
        .RIU_RD_DATA_UPP(xiphy_riu_or_1),
        .RIU_RD_VALID(riu2clb_valid_riuclk),
        .RIU_RD_VALID_LOW(riu2clb_valid_low),
        .RIU_RD_VALID_UPP(riu2clb_valid_upp));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_riuor_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_754
   (riu2clb_valid_riuclk,
    xiphy_riu_or_0,
    riu2clb_valid_low,
    riu2clb_valid_upp,
    RIU_RD_DATA,
    xiphy_riu_or_1);
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or_0;
  input riu2clb_valid_low;
  input riu2clb_valid_upp;
  input [15:0]RIU_RD_DATA;
  input [15:0]xiphy_riu_or_1;

  wire [15:0]RIU_RD_DATA;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire [15:0]xiphy_riu_or_0;
  wire [15:0]xiphy_riu_or_1;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RIU_OR #(
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000)) 
    xiphy_riu_or
       (.RIU_RD_DATA(xiphy_riu_or_0),
        .RIU_RD_DATA_LOW(RIU_RD_DATA),
        .RIU_RD_DATA_UPP(xiphy_riu_or_1),
        .RIU_RD_VALID(riu2clb_valid_riuclk),
        .RIU_RD_VALID_LOW(riu2clb_valid_low),
        .RIU_RD_VALID_UPP(riu2clb_valid_upp));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_riuor_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_769
   (riu2clb_valid_riuclk,
    xiphy_riu_or_0,
    riu2clb_valid_low,
    riu2clb_valid_upp,
    RIU_RD_DATA,
    xiphy_riu_or_1);
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or_0;
  input riu2clb_valid_low;
  input riu2clb_valid_upp;
  input [15:0]RIU_RD_DATA;
  input [15:0]xiphy_riu_or_1;

  wire [15:0]RIU_RD_DATA;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire [15:0]xiphy_riu_or_0;
  wire [15:0]xiphy_riu_or_1;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RIU_OR #(
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000)) 
    xiphy_riu_or
       (.RIU_RD_DATA(xiphy_riu_or_0),
        .RIU_RD_DATA_LOW(RIU_RD_DATA),
        .RIU_RD_DATA_UPP(xiphy_riu_or_1),
        .RIU_RD_VALID(riu2clb_valid_riuclk),
        .RIU_RD_VALID_LOW(riu2clb_valid_low),
        .RIU_RD_VALID_UPP(riu2clb_valid_upp));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_riuor_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_786
   (riu2clb_valid_riuclk,
    xiphy_riu_or_0,
    riu2clb_valid_low,
    riu2clb_valid_upp,
    RIU_RD_DATA,
    xiphy_riu_or_1);
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or_0;
  input riu2clb_valid_low;
  input riu2clb_valid_upp;
  input [15:0]RIU_RD_DATA;
  input [15:0]xiphy_riu_or_1;

  wire [15:0]RIU_RD_DATA;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire [15:0]xiphy_riu_or_0;
  wire [15:0]xiphy_riu_or_1;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RIU_OR #(
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000)) 
    xiphy_riu_or
       (.RIU_RD_DATA(xiphy_riu_or_0),
        .RIU_RD_DATA_LOW(RIU_RD_DATA),
        .RIU_RD_DATA_UPP(xiphy_riu_or_1),
        .RIU_RD_VALID(riu2clb_valid_riuclk),
        .RIU_RD_VALID_LOW(riu2clb_valid_low),
        .RIU_RD_VALID_UPP(riu2clb_valid_upp));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_riuor_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_801
   (riu2clb_valid_riuclk,
    xiphy_riu_or_0,
    riu2clb_valid_low,
    riu2clb_valid_upp,
    RIU_RD_DATA,
    xiphy_riu_or_1);
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or_0;
  input riu2clb_valid_low;
  input riu2clb_valid_upp;
  input [15:0]RIU_RD_DATA;
  input [15:0]xiphy_riu_or_1;

  wire [15:0]RIU_RD_DATA;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire [15:0]xiphy_riu_or_0;
  wire [15:0]xiphy_riu_or_1;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RIU_OR #(
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000)) 
    xiphy_riu_or
       (.RIU_RD_DATA(xiphy_riu_or_0),
        .RIU_RD_DATA_LOW(RIU_RD_DATA),
        .RIU_RD_DATA_UPP(xiphy_riu_or_1),
        .RIU_RD_VALID(riu2clb_valid_riuclk),
        .RIU_RD_VALID_LOW(riu2clb_valid_low),
        .RIU_RD_VALID_UPP(riu2clb_valid_upp));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_riuor_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_riuor_wrapper_817
   (riu2clb_valid_riuclk,
    xiphy_riu_or_0,
    riu2clb_valid_low,
    riu2clb_valid_upp,
    RIU_RD_DATA,
    xiphy_riu_or_1);
  output [0:0]riu2clb_valid_riuclk;
  output [15:0]xiphy_riu_or_0;
  input riu2clb_valid_low;
  input riu2clb_valid_upp;
  input [15:0]RIU_RD_DATA;
  input [15:0]xiphy_riu_or_1;

  wire [15:0]RIU_RD_DATA;
  wire riu2clb_valid_low;
  wire [0:0]riu2clb_valid_riuclk;
  wire riu2clb_valid_upp;
  wire [15:0]xiphy_riu_or_0;
  wire [15:0]xiphy_riu_or_1;

  (* BOX_TYPE = "PRIMITIVE" *) 
  RIU_OR #(
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000)) 
    xiphy_riu_or
       (.RIU_RD_DATA(xiphy_riu_or_0),
        .RIU_RD_DATA_LOW(RIU_RD_DATA),
        .RIU_RD_DATA_UPP(xiphy_riu_or_1),
        .RIU_RD_VALID(riu2clb_valid_riuclk),
        .RIU_RD_VALID_LOW(riu2clb_valid_low),
        .RIU_RD_VALID_UPP(riu2clb_valid_upp));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper
   (tristate_q_0,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_0;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_0;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_679
   (tristate_q_1,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_1;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_1;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_692
   (tristate_q_0,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_0;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_0;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_693
   (tristate_q_1,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_1;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_1;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_707
   (tristate_q_0,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_0;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_0;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_708
   (tristate_q_1,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_1;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_1;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_722
   (tristate_q_0,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_0;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_0;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_723
   (tristate_q_1,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_1;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_1;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_737
   (tristate_q_0,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_0;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_0;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_738
   (tristate_q_1,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_1;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_1;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_752
   (tristate_q_0,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_0;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_0;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_753
   (tristate_q_1,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_1;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_1;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_767
   (tristate_q_0,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_0;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_0;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_768
   (tristate_q_1,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_1;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_1;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_784
   (tristate_q_0,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_0;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_0;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_785
   (tristate_q_1,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_1;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_1;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_799
   (tristate_q_0,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_0;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_0;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_800
   (tristate_q_1,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_1;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_1;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_1));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_815
   (tristate_q_0,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_0;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_0;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_0));
endmodule

(* ORIG_REF_NAME = "ddr4_phy_v2_2_0_xiphy_tristate_wrapper" *) 
module ddr4_0_ddr4_phy_v2_2_0_xiphy_tristate_wrapper_816
   (tristate_q_1,
    BIT_CTRL_OUT,
    clb2phy_tristate_odelay_rst,
    TX_BIT_CTRL_OUT_TRI);
  output tristate_q_1;
  output [39:0]BIT_CTRL_OUT;
  input [0:0]clb2phy_tristate_odelay_rst;
  input [39:0]TX_BIT_CTRL_OUT_TRI;

  wire [39:0]BIT_CTRL_OUT;
  wire [39:0]TX_BIT_CTRL_OUT_TRI;
  wire [0:0]clb2phy_tristate_odelay_rst;
  wire tristate_q_1;
  wire xiphy_bitslice_write_n_41;
  wire xiphy_bitslice_write_n_42;
  wire xiphy_bitslice_write_n_43;
  wire xiphy_bitslice_write_n_44;
  wire xiphy_bitslice_write_n_45;
  wire xiphy_bitslice_write_n_46;
  wire xiphy_bitslice_write_n_47;
  wire xiphy_bitslice_write_n_48;
  wire xiphy_bitslice_write_n_49;

  (* BOX_TYPE = "PRIMITIVE" *) 
  TX_BITSLICE_TRI #(
    .DATA_WIDTH(8),
    .DELAY_FORMAT("TIME"),
    .DELAY_TYPE("FIXED"),
    .DELAY_VALUE(0),
    .INIT(1'b1),
    .IS_CLK_INVERTED(1'b0),
    .IS_RST_DLY_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .NATIVE_ODELAY_BYPASS("FALSE"),
    .OUTPUT_PHASE_90("TRUE"),
    .REFCLK_FREQUENCY(300.000000),
    .SIM_DEVICE("ULTRASCALE"),
    .SIM_VERSION(2.000000),
    .UPDATE_MODE("ASYNC")) 
    xiphy_bitslice_write
       (.BIT_CTRL_IN(TX_BIT_CTRL_OUT_TRI),
        .BIT_CTRL_OUT(BIT_CTRL_OUT),
        .CE(1'b0),
        .CLK(1'b1),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT({xiphy_bitslice_write_n_41,xiphy_bitslice_write_n_42,xiphy_bitslice_write_n_43,xiphy_bitslice_write_n_44,xiphy_bitslice_write_n_45,xiphy_bitslice_write_n_46,xiphy_bitslice_write_n_47,xiphy_bitslice_write_n_48,xiphy_bitslice_write_n_49}),
        .EN_VTC(1'b1),
        .INC(1'b0),
        .LOAD(1'b0),
        .RST(clb2phy_tristate_odelay_rst),
        .RST_DLY(clb2phy_tristate_odelay_rst),
        .TRI_OUT(tristate_q_1));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_bram_tdp" *) 
module ddr4_0_ddr4_v2_2_17_bram_tdp
   (doutb,
    douta,
    clka,
    enb,
    ena,
    addrb,
    addra,
    dinb,
    dina,
    web,
    wea);
  output [8:0]doutb;
  output [8:0]douta;
  input clka;
  input enb;
  input ena;
  input [11:0]addrb;
  input [11:0]addra;
  input [8:0]dinb;
  input [8:0]dina;
  input web;
  input wea;

  wire [11:0]addra;
  wire [11:0]addrb;
  wire clka;
  wire [8:0]dina;
  wire [8:0]dinb;
  wire [8:0]douta;
  wire [8:0]doutb;
  wire ena;
  wire enb;
  wire wea;
  wire web;
  wire NLW_mem_reg_bram_0_CASOUTDBITERR_UNCONNECTED;
  wire NLW_mem_reg_bram_0_CASOUTSBITERR_UNCONNECTED;
  wire NLW_mem_reg_bram_0_DBITERR_UNCONNECTED;
  wire NLW_mem_reg_bram_0_SBITERR_UNCONNECTED;
  wire [31:0]NLW_mem_reg_bram_0_CASDOUTA_UNCONNECTED;
  wire [31:0]NLW_mem_reg_bram_0_CASDOUTB_UNCONNECTED;
  wire [3:0]NLW_mem_reg_bram_0_CASDOUTPA_UNCONNECTED;
  wire [3:0]NLW_mem_reg_bram_0_CASDOUTPB_UNCONNECTED;
  wire [31:8]NLW_mem_reg_bram_0_DOUTADOUT_UNCONNECTED;
  wire [31:8]NLW_mem_reg_bram_0_DOUTBDOUT_UNCONNECTED;
  wire [3:1]NLW_mem_reg_bram_0_DOUTPADOUTP_UNCONNECTED;
  wire [3:1]NLW_mem_reg_bram_0_DOUTPBDOUTP_UNCONNECTED;
  wire [7:0]NLW_mem_reg_bram_0_ECCPARITY_UNCONNECTED;
  wire [8:0]NLW_mem_reg_bram_0_RDADDRECC_UNCONNECTED;

  (* \MEM.PORTA.DATA_BIT_LAYOUT  = "p1_d8" *) 
  (* \MEM.PORTB.DATA_BIT_LAYOUT  = "p1_d8" *) 
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-7 {cell *THIS*}}" *) 
  (* RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE" *) 
  (* RTL_RAM_BITS = "36864" *) 
  (* RTL_RAM_NAME = "inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/DDR_XSDB_BRAM/mem_inst/gen_mem[0].inst/mem_reg_bram_0" *) 
  (* RTL_RAM_TYPE = "RAM_TDP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "4095" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "8" *) 
  RAMB36E2 #(
    .CASCADE_ORDER_A("NONE"),
    .CASCADE_ORDER_B("NONE"),
    .CLOCK_DOMAINS("COMMON"),
    .DOA_REG(1),
    .DOB_REG(1),
    .ENADDRENA("FALSE"),
    .ENADDRENB("FALSE"),
    .EN_ECC_PIPE("FALSE"),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
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    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .RDADDRCHANGEA("FALSE"),
    .RDADDRCHANGEB("FALSE"),
    .READ_WIDTH_A(9),
    .READ_WIDTH_B(9),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SLEEP_ASYNC("FALSE"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("WRITE_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(9),
    .WRITE_WIDTH_B(9)) 
    mem_reg_bram_0
       (.ADDRARDADDR({addrb,1'b0,1'b0,1'b0}),
        .ADDRBWRADDR({addra,1'b0,1'b0,1'b0}),
        .ADDRENA(1'b1),
        .ADDRENB(1'b1),
        .CASDIMUXA(1'b0),
        .CASDIMUXB(1'b0),
        .CASDINA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CASDINB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CASDINPA({1'b0,1'b0,1'b0,1'b0}),
        .CASDINPB({1'b0,1'b0,1'b0,1'b0}),
        .CASDOMUXA(1'b0),
        .CASDOMUXB(1'b0),
        .CASDOMUXEN_A(1'b1),
        .CASDOMUXEN_B(1'b1),
        .CASDOUTA(NLW_mem_reg_bram_0_CASDOUTA_UNCONNECTED[31:0]),
        .CASDOUTB(NLW_mem_reg_bram_0_CASDOUTB_UNCONNECTED[31:0]),
        .CASDOUTPA(NLW_mem_reg_bram_0_CASDOUTPA_UNCONNECTED[3:0]),
        .CASDOUTPB(NLW_mem_reg_bram_0_CASDOUTPB_UNCONNECTED[3:0]),
        .CASINDBITERR(1'b0),
        .CASINSBITERR(1'b0),
        .CASOREGIMUXA(1'b0),
        .CASOREGIMUXB(1'b0),
        .CASOREGIMUXEN_A(1'b1),
        .CASOREGIMUXEN_B(1'b1),
        .CASOUTDBITERR(NLW_mem_reg_bram_0_CASOUTDBITERR_UNCONNECTED),
        .CASOUTSBITERR(NLW_mem_reg_bram_0_CASOUTSBITERR_UNCONNECTED),
        .CLKARDCLK(clka),
        .CLKBWRCLK(clka),
        .DBITERR(NLW_mem_reg_bram_0_DBITERR_UNCONNECTED),
        .DINADIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb[7:0]}),
        .DINBDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
        .DINPADINP({1'b0,1'b0,1'b0,dinb[8]}),
        .DINPBDINP({1'b0,1'b0,1'b0,dina[8]}),
        .DOUTADOUT({NLW_mem_reg_bram_0_DOUTADOUT_UNCONNECTED[31:8],doutb[7:0]}),
        .DOUTBDOUT({NLW_mem_reg_bram_0_DOUTBDOUT_UNCONNECTED[31:8],douta[7:0]}),
        .DOUTPADOUTP({NLW_mem_reg_bram_0_DOUTPADOUTP_UNCONNECTED[3:1],doutb[8]}),
        .DOUTPBDOUTP({NLW_mem_reg_bram_0_DOUTPBDOUTP_UNCONNECTED[3:1],douta[8]}),
        .ECCPARITY(NLW_mem_reg_bram_0_ECCPARITY_UNCONNECTED[7:0]),
        .ECCPIPECE(1'b1),
        .ENARDEN(enb),
        .ENBWREN(ena),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(NLW_mem_reg_bram_0_RDADDRECC_UNCONNECTED[8:0]),
        .REGCEAREGCE(enb),
        .REGCEB(ena),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(NLW_mem_reg_bram_0_SBITERR_UNCONNECTED),
        .SLEEP(1'b0),
        .WEA({web,web,web,web}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,wea,wea,wea,wea}));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal" *) 
module ddr4_0_ddr4_v2_2_17_cal
   (sl_oport_o,
    douta,
    calDone_reg_0,
    calDone_reg_1,
    initDone,
    cnt_clr_reg,
    rst_r1_reg_0,
    lrdimm_cmp_en_reg,
    clear_gt_data_ready_flag_reg,
    gt_data_ready_flag,
    io_ready_lvl_reg,
    D,
    ub_initDone_reg,
    en_vtc,
    calRdCAS,
    cal_clear_fifo_rden,
    wrCAS_reg,
    cal_timer_reg,
    stop_gate_tracking_ack_reg,
    a_b_cmd_sel_start_reg,
    cal_oe_dis_low,
    cal_oe_dis_upp,
    rdCAS_reg,
    \cplx_CAS_reg[6] ,
    \cal_RAS_pre_reg[1] ,
    \cal_RAS_pre_reg[2] ,
    \cplx_RAS_reg[6] ,
    \cplx_RAS_reg[6]_0 ,
    \cal_ACT_n_pre_reg[7] ,
    cal_CS_n,
    \init_cal_BA_reg[15]_0 ,
    \cal_RST_CKE_ODT_PAR_reg[16] ,
    ub_ready_reg,
    winAct_reg,
    cplx_cal_reg,
    calDone_i,
    mcalRdCAS,
    mcalCasSlot,
    mcalRank,
    calDone_reg_2,
    \init_cal_BA_reg[7]_0 ,
    calDone_reg_3,
    \init_cal_BG_reg[7]_0 ,
    calDone_reg_4,
    DQOut,
    DMOut,
    calDone_reg_5,
    calDone_reg_6,
    calDone_reg_7,
    calDone_reg_8,
    calDone_reg_9,
    calDone_reg_10,
    calDone_reg_11,
    calDone_reg_12,
    \wrQ_nxt[1]_13 ,
    calDone_reg_13,
    \uppCL0_reg[38]_0 ,
    \uppCL0_reg[45]_0 ,
    \uppCL0_reg[38]_1 ,
    \uppCL0_reg[36]_0 ,
    \uppCL1_reg[38]_0 ,
    \uppCL1_reg[45]_0 ,
    \uppCL1_reg[38]_1 ,
    \uppCL1_reg[36]_0 ,
    \uppCL2_reg[38]_0 ,
    \uppCL2_reg[45]_0 ,
    \uppCL2_reg[38]_1 ,
    \uppCL2_reg[36]_0 ,
    \uppCL3_reg[38]_0 ,
    \uppCL3_reg[45]_0 ,
    \uppCL3_reg[38]_1 ,
    \uppCL3_reg[36]_0 ,
    \uppCL0_reg[20]_0 ,
    \uppCL0_reg[20]_1 ,
    \uppCL0_reg[18]_0 ,
    \uppCL1_reg[20]_0 ,
    \uppCL1_reg[20]_1 ,
    \uppCL1_reg[18]_0 ,
    \uppCL2_reg[20]_0 ,
    \uppCL2_reg[20]_1 ,
    \uppCL2_reg[18]_0 ,
    \uppCL3_reg[20]_0 ,
    \uppCL3_reg[20]_1 ,
    \uppCL3_reg[18]_0 ,
    \uppCL0_reg[14]_0 ,
    \uppCL0_reg[14]_1 ,
    \uppCL0_reg[12]_0 ,
    \uppCL1_reg[14]_0 ,
    \uppCL1_reg[14]_1 ,
    \uppCL1_reg[12]_0 ,
    \uppCL2_reg[14]_0 ,
    \uppCL2_reg[14]_1 ,
    \uppCL2_reg[12]_0 ,
    \uppCL3_reg[14]_0 ,
    \uppCL3_reg[14]_1 ,
    \uppCL3_reg[12]_0 ,
    \uppCL0_reg[26]_0 ,
    \uppCL0_reg[26]_1 ,
    \uppCL0_reg[24]_0 ,
    \uppCL1_reg[26]_0 ,
    \uppCL1_reg[26]_1 ,
    \uppCL1_reg[24]_0 ,
    \uppCL2_reg[26]_0 ,
    \uppCL2_reg[26]_1 ,
    \uppCL2_reg[24]_0 ,
    \uppCL3_reg[26]_0 ,
    \uppCL3_reg[26]_1 ,
    \uppCL3_reg[24]_0 ,
    \uppCL3_reg[38]_2 ,
    \uppCL2_reg[38]_2 ,
    \uppCL1_reg[38]_2 ,
    \uppCL0_reg[38]_2 ,
    \uppCL3_reg[26]_2 ,
    \uppCL2_reg[26]_2 ,
    \uppCL1_reg[26]_2 ,
    \uppCL0_reg[26]_2 ,
    \uppCL3_reg[20]_2 ,
    \uppCL2_reg[20]_2 ,
    \uppCL1_reg[20]_2 ,
    \uppCL0_reg[20]_2 ,
    \uppCL3_reg[14]_2 ,
    \uppCL2_reg[14]_2 ,
    \uppCL1_reg[14]_2 ,
    \uppCL0_reg[14]_2 ,
    \uppCL0_reg[8]_0 ,
    \uppCL0_reg[8]_1 ,
    \uppCL0_reg[6]_0 ,
    \uppCL1_reg[8]_0 ,
    \uppCL1_reg[8]_1 ,
    \uppCL1_reg[6]_0 ,
    \uppCL2_reg[8]_0 ,
    \uppCL2_reg[8]_1 ,
    \uppCL2_reg[6]_0 ,
    \uppCL3_reg[8]_0 ,
    \uppCL3_reg[8]_1 ,
    \uppCL3_reg[6]_0 ,
    \uppCL0_reg[44]_0 ,
    \uppCL0_reg[44]_1 ,
    \uppCL0_reg[42]_0 ,
    \uppCL1_reg[44]_0 ,
    \uppCL1_reg[44]_1 ,
    \uppCL1_reg[42]_0 ,
    \uppCL2_reg[44]_0 ,
    \uppCL2_reg[44]_1 ,
    \uppCL2_reg[42]_0 ,
    \uppCL3_reg[44]_0 ,
    \uppCL3_reg[44]_1 ,
    \uppCL3_reg[42]_0 ,
    \uppCL1_reg[44]_2 ,
    \uppCL0_reg[44]_2 ,
    \uppCL3_reg[44]_2 ,
    \uppCL2_reg[44]_2 ,
    \uppCL1_reg[8]_2 ,
    \uppCL0_reg[8]_2 ,
    \uppCL3_reg[8]_2 ,
    \uppCL2_reg[8]_2 ,
    \lowCL0_reg[44]_0 ,
    \lowCL0_reg[44]_1 ,
    \lowCL0_reg[42]_0 ,
    \lowCL1_reg[44]_0 ,
    \lowCL1_reg[44]_1 ,
    \lowCL1_reg[42]_0 ,
    \lowCL2_reg[44]_0 ,
    \lowCL2_reg[44]_1 ,
    \lowCL2_reg[42]_0 ,
    \lowCL3_reg[44]_0 ,
    \lowCL3_reg[44]_1 ,
    \lowCL3_reg[42]_0 ,
    \uppCL0_reg[2]_0 ,
    \uppCL0_reg[2]_1 ,
    \uppCL0_reg[0]_0 ,
    \uppCL1_reg[2]_0 ,
    \uppCL1_reg[2]_1 ,
    \uppCL1_reg[0]_0 ,
    \uppCL2_reg[2]_0 ,
    \uppCL2_reg[2]_1 ,
    \uppCL2_reg[0]_0 ,
    \uppCL3_reg[2]_0 ,
    \uppCL3_reg[2]_1 ,
    \uppCL3_reg[0]_0 ,
    \uppCL0_reg[32]_0 ,
    \uppCL0_reg[32]_1 ,
    \uppCL0_reg[30]_0 ,
    \uppCL1_reg[32]_0 ,
    \uppCL1_reg[32]_1 ,
    \uppCL1_reg[30]_0 ,
    \uppCL2_reg[32]_0 ,
    \uppCL2_reg[32]_1 ,
    \uppCL2_reg[30]_0 ,
    \uppCL3_reg[32]_0 ,
    \uppCL3_reg[32]_1 ,
    \uppCL3_reg[30]_0 ,
    \lowCL3_reg[44]_2 ,
    \lowCL2_reg[44]_2 ,
    \lowCL1_reg[44]_2 ,
    \lowCL0_reg[44]_2 ,
    \uppCL3_reg[32]_2 ,
    \uppCL2_reg[32]_2 ,
    \uppCL1_reg[32]_2 ,
    \uppCL0_reg[32]_2 ,
    \uppCL3_reg[2]_2 ,
    \uppCL2_reg[2]_2 ,
    \uppCL1_reg[2]_2 ,
    \uppCL0_reg[2]_2 ,
    \lowCL0_reg[32]_0 ,
    \lowCL0_reg[32]_1 ,
    \lowCL0_reg[30]_0 ,
    \lowCL1_reg[32]_0 ,
    \lowCL1_reg[32]_1 ,
    \lowCL1_reg[30]_0 ,
    \lowCL2_reg[32]_0 ,
    \lowCL2_reg[32]_1 ,
    \lowCL2_reg[30]_0 ,
    \lowCL3_reg[32]_0 ,
    \lowCL3_reg[32]_1 ,
    \lowCL3_reg[30]_0 ,
    \lowCL0_reg[26]_0 ,
    \lowCL0_reg[26]_1 ,
    \lowCL0_reg[24]_0 ,
    \lowCL1_reg[26]_0 ,
    \lowCL1_reg[26]_1 ,
    \lowCL1_reg[24]_0 ,
    \lowCL2_reg[26]_0 ,
    \lowCL2_reg[26]_1 ,
    \lowCL2_reg[24]_0 ,
    \lowCL3_reg[26]_0 ,
    \lowCL3_reg[26]_1 ,
    \lowCL3_reg[24]_0 ,
    \lowCL0_reg[38]_0 ,
    \lowCL0_reg[38]_1 ,
    \lowCL0_reg[36]_0 ,
    \lowCL1_reg[38]_0 ,
    \lowCL1_reg[38]_1 ,
    \lowCL1_reg[36]_0 ,
    \lowCL2_reg[38]_0 ,
    \lowCL2_reg[38]_1 ,
    \lowCL2_reg[36]_0 ,
    \lowCL3_reg[38]_0 ,
    \lowCL3_reg[38]_1 ,
    \lowCL3_reg[36]_0 ,
    \lowCL3_reg[38]_2 ,
    \lowCL2_reg[38]_2 ,
    \lowCL1_reg[38]_2 ,
    \lowCL0_reg[38]_2 ,
    \lowCL3_reg[32]_2 ,
    \lowCL2_reg[32]_2 ,
    \lowCL1_reg[32]_2 ,
    \lowCL0_reg[32]_2 ,
    \lowCL3_reg[26]_2 ,
    \lowCL2_reg[26]_2 ,
    \lowCL1_reg[26]_2 ,
    \lowCL0_reg[26]_2 ,
    \lowCL0_reg[20]_0 ,
    \lowCL0_reg[20]_1 ,
    \lowCL0_reg[18]_0 ,
    \lowCL1_reg[20]_0 ,
    \lowCL1_reg[20]_1 ,
    \lowCL1_reg[18]_0 ,
    \lowCL2_reg[20]_0 ,
    \lowCL2_reg[20]_1 ,
    \lowCL2_reg[18]_0 ,
    \lowCL3_reg[20]_0 ,
    \lowCL3_reg[20]_1 ,
    \lowCL3_reg[18]_0 ,
    \lowCL0_reg[14]_0 ,
    \lowCL0_reg[14]_1 ,
    \lowCL0_reg[12]_0 ,
    \lowCL1_reg[14]_0 ,
    \lowCL1_reg[14]_1 ,
    \lowCL1_reg[12]_0 ,
    \lowCL2_reg[14]_0 ,
    \lowCL2_reg[14]_1 ,
    \lowCL2_reg[12]_0 ,
    \lowCL3_reg[14]_0 ,
    \lowCL3_reg[14]_1 ,
    \lowCL3_reg[12]_0 ,
    \lowCL0_reg[8]_0 ,
    \lowCL0_reg[8]_1 ,
    \lowCL0_reg[6]_0 ,
    \lowCL1_reg[8]_0 ,
    \lowCL1_reg[8]_1 ,
    \lowCL1_reg[6]_0 ,
    \lowCL2_reg[8]_0 ,
    \lowCL2_reg[8]_1 ,
    \lowCL2_reg[6]_0 ,
    \lowCL3_reg[8]_0 ,
    \lowCL3_reg[8]_1 ,
    \lowCL3_reg[6]_0 ,
    \lowCL0_reg[2]_0 ,
    \lowCL0_reg[2]_1 ,
    \lowCL0_reg[0]_0 ,
    \lowCL1_reg[2]_0 ,
    \lowCL1_reg[2]_1 ,
    \lowCL1_reg[0]_0 ,
    \lowCL2_reg[2]_0 ,
    \lowCL2_reg[2]_1 ,
    \lowCL2_reg[0]_0 ,
    \lowCL3_reg[2]_0 ,
    \lowCL3_reg[2]_1 ,
    \lowCL3_reg[0]_0 ,
    \lowCL3_reg[20]_2 ,
    \lowCL2_reg[20]_2 ,
    \lowCL1_reg[20]_2 ,
    \lowCL0_reg[20]_2 ,
    \lowCL3_reg[14]_2 ,
    \lowCL2_reg[14]_2 ,
    \lowCL1_reg[14]_2 ,
    \lowCL0_reg[14]_2 ,
    \lowCL3_reg[8]_2 ,
    \lowCL2_reg[8]_2 ,
    \lowCL1_reg[8]_2 ,
    \lowCL0_reg[8]_2 ,
    \lowCL3_reg[2]_2 ,
    \lowCL2_reg[2]_2 ,
    \lowCL1_reg[2]_2 ,
    \lowCL0_reg[2]_2 ,
    \SYNC[0].sync_reg_reg[1] ,
    \cal_seq_rd_cnt_reg[7] ,
    \cal_seq_cnt_reg[31] ,
    \cal_CS_A_reg[6] ,
    \cal_CS_A_reg[7] ,
    \SYNC[20].sync_reg_reg[1] ,
    \cal_CS_A_reg[0] ,
    \cplx_error_accum_reg[14] ,
    \cplx_error_accum_reg[15] ,
    \cplx_error_accum_reg[44] ,
    \cal_ADR_B_reg[12] ,
    \cplx_error_accum_reg[19] ,
    \cal_ADR_A_reg[0] ,
    cal_timer_reg_29_sp_1,
    cal_timer_reg_28_sp_1,
    cal_timer_reg_25_sp_1,
    cal_timer_reg_24_sp_1,
    cal_timer_reg_21_sp_1,
    \cal_CS_B_reg[5] ,
    \cal_CS_A_reg[5] ,
    \cal_ADR_B_reg[30] ,
    \cal_ADR_A_reg[30] ,
    \SYNC[5].sync_reg_reg[1] ,
    \SYNC[5].sync_reg_reg[1]_0 ,
    \mcal_DQIn_byte_r1_reg[31] ,
    \cal_ADR_A_reg[29] ,
    \cal_ADR_A_reg[27] ,
    \cal_ADR_A_reg[26] ,
    \cal_ADR_B_reg[25] ,
    \cal_ADR_B_reg[24] ,
    \cal_ADR_A_reg[21] ,
    \cal_ADR_A_reg[20] ,
    \cal_ADR_B_reg[19] ,
    \cal_ADR_B_reg[18] ,
    \cal_ADR_B_reg[17] ,
    \cal_RST_CKE_ODT_PAR_reg[16]_0 ,
    \cal_ADR_B_reg[15] ,
    \cal_ADR_B_reg[13] ,
    \cal_ADR_B_reg[11] ,
    \cal_ADR_B_reg[10] ,
    \cal_RST_CKE_ODT_PAR_reg[9] ,
    \cal_ADR_A_reg[1] ,
    \cal_RST_CKE_ODT_PAR_reg[30] ,
    \cal_ADR_A_reg[4] ,
    \cal_seq_cnt_reg[13] ,
    mem_reg_bram_0,
    \cal_ADR_B_reg[31] ,
    \SYNC[3].sync_reg_reg[1] ,
    \SYNC[3].sync_reg_reg[1]_0 ,
    \SYNC[3].sync_reg_reg[1]_1 ,
    \SYNC[3].sync_reg_reg[1]_2 ,
    \SYNC[0].sync_reg_reg[1]_0 ,
    \SYNC[3].sync_reg_reg[1]_3 ,
    \SYNC[3].sync_reg_reg[1]_4 ,
    \SYNC[3].sync_reg_reg[1]_5 ,
    \SYNC[3].sync_reg_reg[1]_6 ,
    \SYNC[3].sync_reg_reg[1]_7 ,
    \SYNC[3].sync_reg_reg[1]_8 ,
    \SYNC[3].sync_reg_reg[1]_9 ,
    \SYNC[3].sync_reg_reg[1]_10 ,
    \SYNC[3].sync_reg_reg[1]_11 ,
    \SYNC[3].sync_reg_reg[1]_12 ,
    \SYNC[3].sync_reg_reg[1]_13 ,
    \SYNC[3].sync_reg_reg[1]_14 ,
    \SYNC[3].sync_reg_reg[1]_15 ,
    \SYNC[3].sync_reg_reg[1]_16 ,
    \SYNC[3].sync_reg_reg[1]_17 ,
    \SYNC[3].sync_reg_reg[1]_18 ,
    \SYNC[3].sync_reg_reg[1]_19 ,
    \SYNC[3].sync_reg_reg[1]_20 ,
    \SYNC[3].sync_reg_reg[1]_21 ,
    \SYNC[3].sync_reg_reg[1]_22 ,
    \SYNC[3].sync_reg_reg[1]_23 ,
    \SYNC[3].sync_reg_reg[1]_24 ,
    \SYNC[3].sync_reg_reg[1]_25 ,
    \SYNC[3].sync_reg_reg[1]_26 ,
    \SYNC[3].sync_reg_reg[1]_27 ,
    \SYNC[3].sync_reg_reg[1]_28 ,
    \SYNC[3].sync_reg_reg[1]_29 ,
    \SYNC[3].sync_reg_reg[1]_30 ,
    \SYNC[3].sync_reg_reg[1]_31 ,
    \SYNC[3].sync_reg_reg[1]_32 ,
    \SYNC[3].sync_reg_reg[1]_33 ,
    \SYNC[3].sync_reg_reg[1]_34 ,
    \SYNC[3].sync_reg_reg[1]_35 ,
    \SYNC[3].sync_reg_reg[1]_36 ,
    \SYNC[3].sync_reg_reg[1]_37 ,
    \SYNC[3].sync_reg_reg[1]_38 ,
    \SYNC[3].sync_reg_reg[1]_39 ,
    \SYNC[3].sync_reg_reg[1]_40 ,
    \SYNC[3].sync_reg_reg[1]_41 ,
    \SYNC[3].sync_reg_reg[1]_42 ,
    \SYNC[3].sync_reg_reg[1]_43 ,
    \SYNC[3].sync_reg_reg[1]_44 ,
    \SYNC[3].sync_reg_reg[1]_45 ,
    \SYNC[5].sync_reg_reg[1]_1 ,
    \SYNC[5].sync_reg_reg[1]_2 ,
    \SYNC[5].sync_reg_reg[1]_3 ,
    \SYNC[5].sync_reg_reg[1]_4 ,
    \cal_ADR_A_reg[22] ,
    \SYNC[5].sync_reg_reg[1]_5 ,
    \SYNC[5].sync_reg_reg[1]_6 ,
    \SYNC[5].sync_reg_reg[1]_7 ,
    \SYNC[5].sync_reg_reg[1]_8 ,
    \SYNC[5].sync_reg_reg[1]_9 ,
    \SYNC[5].sync_reg_reg[1]_10 ,
    \SYNC[5].sync_reg_reg[1]_11 ,
    \SYNC[5].sync_reg_reg[1]_12 ,
    \SYNC[5].sync_reg_reg[1]_13 ,
    \genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9] ,
    \genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8] ,
    \SYNC[4].sync_reg_reg[1] ,
    \SYNC[5].sync_reg_reg[1]_14 ,
    \cal_ADR_A_reg[4]_0 ,
    \cal_CS_A_reg[4] ,
    \SYNC[4].sync_reg_reg[1]_0 ,
    \rd_vref_value_reg[46] ,
    \mcal_DMIn_bit_r1_reg[7] ,
    \cal_ADR_A_reg[3] ,
    \SYNC[5].sync_reg_reg[1]_15 ,
    \cal_ADR_A_reg[2] ,
    \SYNC[18].sync_reg_reg[1] ,
    \SYNC[5].sync_reg_reg[1]_16 ,
    gt_data_ready_flag_reg,
    cplx_status,
    \cal_ADR_A_reg[0]_0 ,
    \dout_o_reg[5] ,
    \dout_o_reg[11] ,
    rst_r1_reg_1,
    S,
    \delay_cntr_reg[2] ,
    lrdimm_cal_mode_reg,
    lrdimm_cal_mode_reg_0,
    \SYNC[5].sync_reg_reg[1]_17 ,
    \rd_vref_value_reg[42] ,
    mcal_rd_vref_value,
    \rd_vref_value_reg[43] ,
    \rd_vref_value_reg[44] ,
    \rd_vref_value_reg[45] ,
    \rd_vref_value_reg[48] ,
    in0,
    \rsMask_reg[7][18] ,
    rst_r1_reg_2,
    \wosp_reg[1] ,
    \wosp_reg[2]_rep ,
    \wosp_reg[2]_rep_0 ,
    \wosp_reg[1]_0 ,
    \wosp_reg[2]_rep__2 ,
    \wosp_reg[2]_rep__1 ,
    \wosp_reg[2]_rep__1_0 ,
    \wosp_reg[2]_rep__1_1 ,
    \wosp_reg[2]_rep__1_2 ,
    \wosp_reg[2]_rep__1_3 ,
    \wosp_reg[2]_rep__1_4 ,
    \wosp_reg[2]_rep__1_5 ,
    \wosp_reg[2]_rep__1_6 ,
    \wosp_reg[2]_rep__1_7 ,
    \wosp_reg[2]_rep__1_8 ,
    \wosp_reg[2]_rep__1_9 ,
    \wosp_reg[2]_rep__1_10 ,
    \wosp_reg[2]_rep__2_0 ,
    \wosp_reg[2]_rep__1_11 ,
    \wosp_reg[2]_rep__2_1 ,
    \wosp_reg[2]_rep__2_2 ,
    \wosp_reg[2]_rep__2_3 ,
    \wosp_reg[2]_rep__2_4 ,
    \wosp_reg[2]_rep__2_5 ,
    \wosp_reg[2]_rep__2_6 ,
    \wosp_reg[2]_rep__2_7 ,
    \wosp_reg[2]_rep__2_8 ,
    \wosp_reg[2]_rep__2_9 ,
    \wosp_reg[2]_rep__2_10 ,
    \wosp_reg[1]_1 ,
    \wosp_reg[1]_2 ,
    \wosp_reg[1]_3 ,
    \wosp_reg[1]_4 ,
    \wosp_reg[1]_5 ,
    \wosp_reg[1]_6 ,
    \wosp_reg[1]_7 ,
    \wosp_reg[1]_8 ,
    \wosp_reg[1]_9 ,
    \wosp_reg[1]_10 ,
    \wosp_reg[1]_11 ,
    \wosp_reg[1]_12 ,
    \wosp_reg[1]_13 ,
    \wosp_reg[1]_14 ,
    \wosp_reg[1]_15 ,
    \wosp_reg[1]_16 ,
    \wosp_reg[1]_17 ,
    \wosp_reg[2]_rep_1 ,
    \wosp_reg[2]_rep_2 ,
    \wosp_reg[1]_18 ,
    \wosp_reg[2]_rep__3 ,
    \wosp_reg[2]_rep__2_11 ,
    \wosp_reg[2]_rep__2_12 ,
    \wosp_reg[2]_rep__2_13 ,
    \wosp_reg[2]_rep__2_14 ,
    \wosp_reg[2]_rep__2_15 ,
    \wosp_reg[2]_rep__2_16 ,
    \wosp_reg[2]_rep__2_17 ,
    \wosp_reg[2]_rep__2_18 ,
    \wosp_reg[2]_rep__2_19 ,
    \wosp_reg[2]_rep__2_20 ,
    \wosp_reg[2]_rep__2_21 ,
    \wosp_reg[2]_rep__2_22 ,
    \wosp_reg[2]_rep__2_23 ,
    \wosp_reg[2]_rep__2_24 ,
    \wosp_reg[2]_rep__2_25 ,
    \wosp_reg[2]_rep__2_26 ,
    \wosp_reg[2]_rep__2_27 ,
    \wosp_reg[2]_rep__2_28 ,
    \wosp_reg[2]_rep__2_29 ,
    \wosp_reg[2]_rep__2_30 ,
    \wosp_reg[2]_rep__2_31 ,
    \wosp_reg[2]_rep__2_32 ,
    \wosp_reg[2]_rep__2_33 ,
    \wosp_reg[2]_rep__2_34 ,
    \wosp_reg[1]_19 ,
    \wosp_reg[1]_20 ,
    \wosp_reg[1]_21 ,
    \wosp_reg[1]_22 ,
    \wosp_reg[1]_23 ,
    \wosp_reg[1]_24 ,
    \wosp_reg[1]_25 ,
    \wosp_reg[1]_26 ,
    \wosp_reg[1]_27 ,
    \wosp_reg[1]_28 ,
    \wosp_reg[1]_29 ,
    \wosp_reg[1]_30 ,
    \wosp_reg[1]_31 ,
    \wosp_reg[1]_32 ,
    \wosp_reg[1]_33 ,
    \wosp_reg[1]_34 ,
    \wosp_reg[1]_35 ,
    \wosp_reg[2]_rep_3 ,
    \wosp_reg[2]_rep_4 ,
    \wosp_reg[1]_36 ,
    \wosp_reg[2]_rep__3_0 ,
    \wosp_reg[2]_rep__3_1 ,
    \wosp_reg[2]_rep__3_2 ,
    \wosp_reg[2]_rep__3_3 ,
    \wosp_reg[2]_rep__3_4 ,
    \wosp_reg[2]_rep__3_5 ,
    \wosp_reg[2]_rep__3_6 ,
    \wosp_reg[2]_rep__3_7 ,
    \wosp_reg[2]_rep__3_8 ,
    \wosp_reg[2]_rep__3_9 ,
    \wosp_reg[2]_rep__3_10 ,
    \wosp_reg[2]_rep__3_11 ,
    \wosp_reg[2]_rep__3_12 ,
    \wosp_reg[2]_rep__3_13 ,
    \wosp_reg[2]_rep__3_14 ,
    \wosp_reg[2]_rep__3_15 ,
    \wosp_reg[2]_rep__3_16 ,
    \wosp_reg[2]_rep__3_17 ,
    \wosp_reg[2]_rep__3_18 ,
    \wosp_reg[2]_rep__3_19 ,
    \wosp_reg[2]_rep__3_20 ,
    \wosp_reg[2]_rep__3_21 ,
    \wosp_reg[2]_rep__3_22 ,
    \wosp_reg[2]_rep__3_23 ,
    \wosp_reg[2]_rep__3_24 ,
    \wosp_reg[1]_37 ,
    \wosp_reg[1]_38 ,
    \wosp_reg[1]_39 ,
    \wosp_reg[1]_40 ,
    \wosp_reg[1]_41 ,
    \wosp_reg[1]_42 ,
    \wosp_reg[1]_43 ,
    \wosp_reg[1]_44 ,
    \wosp_reg[1]_45 ,
    \wosp_reg[1]_46 ,
    \wosp_reg[1]_47 ,
    \wosp_reg[1]_48 ,
    \wosp_reg[1]_49 ,
    \wosp_reg[1]_50 ,
    \wosp_reg[1]_51 ,
    \wosp_reg[1]_52 ,
    \wosp_reg[1]_53 ,
    \wosp_reg[2]_rep__0 ,
    \wosp_reg[2]_rep__0_0 ,
    \wosp_reg[1]_54 ,
    \wosp_reg[2]_rep__4 ,
    \wosp_reg[2]_rep__3_25 ,
    \wosp_reg[2]_rep__3_26 ,
    \wosp_reg[2]_rep__3_27 ,
    \wosp_reg[2]_rep__3_28 ,
    \wosp_reg[2]_rep__3_29 ,
    \wosp_reg[2]_rep__3_30 ,
    \wosp_reg[2]_rep__3_31 ,
    \wosp_reg[2]_rep__3_32 ,
    \wosp_reg[2]_rep__3_33 ,
    \wosp_reg[2]_rep__4_0 ,
    \wosp_reg[2]_rep__4_1 ,
    \wosp_reg[2]_rep__4_2 ,
    \wosp_reg[2]_rep__4_3 ,
    \wosp_reg[2]_rep__4_4 ,
    \wosp_reg[2]_rep__4_5 ,
    \wosp_reg[2]_rep__4_6 ,
    \wosp_reg[2]_rep__4_7 ,
    \wosp_reg[2]_rep__4_8 ,
    \wosp_reg[2]_rep__4_9 ,
    \wosp_reg[2]_rep__4_10 ,
    \wosp_reg[2]_rep__4_11 ,
    \wosp_reg[2]_rep__4_12 ,
    \wosp_reg[2]_rep__4_13 ,
    \wosp_reg[2]_rep__4_14 ,
    \wosp_reg[1]_55 ,
    \wosp_reg[1]_56 ,
    \wosp_reg[1]_57 ,
    \wosp_reg[1]_58 ,
    \wosp_reg[1]_59 ,
    \wosp_reg[1]_60 ,
    \wosp_reg[1]_61 ,
    \wosp_reg[1]_62 ,
    \wosp_reg[1]_63 ,
    \wosp_reg[1]_64 ,
    \wosp_reg[1]_65 ,
    \wosp_reg[1]_66 ,
    \wosp_reg[1]_67 ,
    \wosp_reg[1]_68 ,
    \wosp_reg[1]_69 ,
    \wosp_reg[1]_70 ,
    \wosp_reg[1]_71 ,
    \wosp_reg[2]_rep__0_1 ,
    \wosp_reg[2]_rep__0_2 ,
    \wosp_reg[1]_72 ,
    \wosp_reg[2]_rep__5 ,
    \wosp_reg[2]_rep__4_15 ,
    \wosp_reg[2]_rep__4_16 ,
    \wosp_reg[2]_rep__4_17 ,
    \wosp_reg[2]_rep__4_18 ,
    \wosp_reg[2]_rep__4_19 ,
    \wosp_reg[2]_rep__4_20 ,
    \wosp_reg[2]_rep__4_21 ,
    \wosp_reg[2]_rep__4_22 ,
    \wosp_reg[2]_rep__4_23 ,
    \wosp_reg[2]_rep__4_24 ,
    \wosp_reg[2]_rep__4_25 ,
    \wosp_reg[2]_rep__4_26 ,
    \wosp_reg[2]_rep__4_27 ,
    \wosp_reg[2]_rep__4_28 ,
    \wosp_reg[2]_rep__4_29 ,
    \wosp_reg[2]_rep__4_30 ,
    \wosp_reg[2]_rep__4_31 ,
    \wosp_reg[2]_rep__4_32 ,
    \wosp_reg[2]_rep__5_0 ,
    \wosp_reg[2]_rep__4_33 ,
    \wosp_reg[2]_rep__5_1 ,
    \wosp_reg[2]_rep__5_2 ,
    \wosp_reg[2]_rep__5_3 ,
    \wosp_reg[2]_rep__5_4 ,
    \wosp_reg[1]_73 ,
    \wosp_reg[1]_74 ,
    \wosp_reg[1]_75 ,
    \wosp_reg[1]_76 ,
    \wosp_reg[1]_77 ,
    \wosp_reg[1]_78 ,
    \wosp_reg[1]_79 ,
    \wosp_reg[1]_80 ,
    \wosp_reg[1]_81 ,
    \wosp_reg[1]_82 ,
    \wosp_reg[1]_83 ,
    \wosp_reg[1]_84 ,
    \wosp_reg[1]_85 ,
    \wosp_reg[1]_86 ,
    \wosp_reg[1]_87 ,
    \wosp_reg[1]_88 ,
    \wosp_reg[1]_89 ,
    \wosp_reg[2]_rep__0_3 ,
    \wosp_reg[2]_rep__0_4 ,
    \wosp_reg[1]_90 ,
    \wosp_reg[2]_rep__5_5 ,
    \wosp_reg[2]_rep__5_6 ,
    \wosp_reg[2]_rep__5_7 ,
    \wosp_reg[2]_rep__5_8 ,
    \wosp_reg[2]_rep__5_9 ,
    \wosp_reg[2]_rep__5_10 ,
    \wosp_reg[2]_rep__5_11 ,
    \wosp_reg[2]_rep__5_12 ,
    \wosp_reg[2]_rep__5_13 ,
    \wosp_reg[2]_rep__5_14 ,
    \wosp_reg[2]_rep__5_15 ,
    \wosp_reg[2]_rep__5_16 ,
    \wosp_reg[2]_rep__5_17 ,
    \wosp_reg[2]_rep__5_18 ,
    \wosp_reg[2]_rep__5_19 ,
    \wosp_reg[2]_rep__5_20 ,
    \wosp_reg[2]_rep__5_21 ,
    \wosp_reg[2]_rep__5_22 ,
    \wosp_reg[2]_rep__5_23 ,
    \wosp_reg[2]_rep__5_24 ,
    \wosp_reg[2]_rep__5_25 ,
    \wosp_reg[2]_rep__5_26 ,
    \wosp_reg[2]_rep__5_27 ,
    \wosp_reg[2]_rep__5_28 ,
    \wosp_reg[2]_rep__5_29 ,
    \wosp_reg[1]_91 ,
    \wosp_reg[1]_92 ,
    \wosp_reg[1]_93 ,
    \wosp_reg[1]_94 ,
    \wosp_reg[1]_95 ,
    \wosp_reg[1]_96 ,
    \wosp_reg[1]_97 ,
    \wosp_reg[1]_98 ,
    \wosp_reg[1]_99 ,
    \wosp_reg[1]_100 ,
    \wosp_reg[1]_101 ,
    \wosp_reg[1]_102 ,
    \wosp_reg[1]_103 ,
    \wosp_reg[1]_104 ,
    \wosp_reg[1]_105 ,
    \wosp_reg[1]_106 ,
    \wosp_reg[1]_107 ,
    \wosp_reg[2]_rep__1_12 ,
    \wosp_reg[2]_rep__1_13 ,
    \wosp_reg[1]_108 ,
    \wosp_reg[2]_rep__6 ,
    \wosp_reg[2]_rep__5_30 ,
    \wosp_reg[2]_rep__5_31 ,
    \wosp_reg[2]_rep__5_32 ,
    \wosp_reg[2]_rep__6_0 ,
    \wosp_reg[2]_rep__5_33 ,
    \wosp_reg[2]_rep__6_1 ,
    \wosp_reg[2]_rep__6_2 ,
    \wosp_reg[2]_rep__6_3 ,
    \wosp_reg[2]_rep__6_4 ,
    \wosp_reg[2]_rep__6_5 ,
    \wosp_reg[2]_rep__6_6 ,
    \wosp_reg[2]_rep__6_7 ,
    \wosp_reg[2]_rep__6_8 ,
    \wosp_reg[2]_rep__6_9 ,
    \wosp_reg[2]_rep__6_10 ,
    \wosp_reg[2]_rep__6_11 ,
    \wosp_reg[2]_rep__6_12 ,
    \wosp_reg[2]_rep__6_13 ,
    \wosp_reg[2]_rep__6_14 ,
    \wosp_reg[2]_rep__6_15 ,
    \wosp_reg[2]_rep__6_16 ,
    \wosp_reg[2]_rep__6_17 ,
    \wosp_reg[2]_rep__6_18 ,
    \wosp_reg[2]_rep__6_19 ,
    \wosp_reg[1]_109 ,
    \wosp_reg[1]_110 ,
    \wosp_reg[1]_111 ,
    \wosp_reg[1]_112 ,
    \wosp_reg[1]_113 ,
    \wosp_reg[1]_114 ,
    \wosp_reg[1]_115 ,
    \wosp_reg[1]_116 ,
    \wosp_reg[1]_117 ,
    \wosp_reg[1]_118 ,
    \wosp_reg[1]_119 ,
    \wosp_reg[1]_120 ,
    \wosp_reg[1]_121 ,
    \wosp_reg[1]_122 ,
    \wosp_reg[1]_123 ,
    \wosp_reg[1]_124 ,
    \wosp_reg[1]_125 ,
    \wosp_reg[2] ,
    \wosp_reg[2]_0 ,
    \wosp_reg[1]_126 ,
    \wosp_reg[2]_rep__6_20 ,
    \wosp_reg[2]_rep__7 ,
    \wosp_reg[2]_rep__7_0 ,
    \wosp_reg[2]_rep__6_21 ,
    \wosp_reg[2]_rep__6_22 ,
    \wosp_reg[2]_rep__6_23 ,
    \wosp_reg[2]_rep__6_24 ,
    \wosp_reg[2]_rep__6_25 ,
    \wosp_reg[2]_rep__6_26 ,
    \wosp_reg[2]_rep__6_27 ,
    \wosp_reg[2]_rep__6_28 ,
    \wosp_reg[2]_rep__6_29 ,
    \wosp_reg[2]_rep__6_30 ,
    \wosp_reg[2]_rep__6_31 ,
    \wosp_reg[2]_rep__6_32 ,
    \wosp_reg[2]_rep__6_33 ,
    \wosp_reg[2]_rep__6_34 ,
    \wosp_reg[2]_rep__6_35 ,
    \wosp_reg[2]_rep__6_36 ,
    \wosp_reg[2]_rep__6_37 ,
    \wosp_reg[2]_rep__6_38 ,
    \wosp_reg[2]_rep__6_39 ,
    \wosp_reg[2]_rep__6_40 ,
    \wosp_reg[2]_rep__6_41 ,
    \wosp_reg[2]_rep__6_42 ,
    \wosp_reg[1]_127 ,
    \wosp_reg[1]_128 ,
    \wosp_reg[1]_129 ,
    \wosp_reg[1]_130 ,
    \wosp_reg[1]_131 ,
    \wosp_reg[1]_132 ,
    \wosp_reg[1]_133 ,
    \wosp_reg[1]_134 ,
    \wosp_reg[1]_135 ,
    \wosp_reg[1]_136 ,
    \wosp_reg[1]_137 ,
    \wosp_reg[1]_138 ,
    \wosp_reg[1]_139 ,
    \wosp_reg[1]_140 ,
    \wosp_reg[1]_141 ,
    \wosp_reg[1]_142 ,
    rst_r1_reg_3,
    rst_r1_reg_4,
    rst_r1_reg_5,
    rst_r1_reg_6,
    rst_r1_reg_7,
    rst_r1_reg_8,
    rst_r1_reg_9,
    rst_r1_reg_10,
    rst_r1_reg_11,
    rst_r1_reg_12,
    rst_r1_reg_13,
    rst_r1_reg_14,
    rst_r1_reg_15,
    \uppCL0_reg[8]_3 ,
    \uppCL0_reg[7]_0 ,
    \uppCL0_reg[8]_4 ,
    \uppCL0_reg[7]_1 ,
    \uppCL0_reg[8]_5 ,
    rs2mask0__0,
    \uppCL0_reg[9]_0 ,
    \uppCL0_reg[7]_2 ,
    \uppCL1_reg[8]_3 ,
    \uppCL1_reg[7]_0 ,
    \uppCL1_reg[8]_4 ,
    \uppCL1_reg[7]_1 ,
    \uppCL1_reg[8]_5 ,
    \uppCL1_reg[7]_2 ,
    \uppCL1_reg[7]_3 ,
    \uppCL1_reg[9]_0 ,
    \uppCL1_reg[7]_4 ,
    \uppCL1_reg[7]_5 ,
    \uppCL1_reg[8]_6 ,
    \uppCL2_reg[8]_3 ,
    \uppCL2_reg[7]_0 ,
    \uppCL2_reg[8]_4 ,
    \uppCL2_reg[7]_1 ,
    \uppCL2_reg[8]_5 ,
    \uppCL2_reg[7]_2 ,
    \uppCL2_reg[7]_3 ,
    \uppCL2_reg[9]_0 ,
    \uppCL2_reg[7]_4 ,
    \uppCL2_reg[7]_5 ,
    \uppCL2_reg[8]_6 ,
    \uppCL3_reg[8]_3 ,
    \uppCL3_reg[7]_0 ,
    \uppCL3_reg[8]_4 ,
    \uppCL3_reg[7]_1 ,
    \uppCL3_reg[8]_5 ,
    \uppCL3_reg[7]_2 ,
    \uppCL3_reg[7]_3 ,
    \uppCL3_reg[9]_0 ,
    \uppCL3_reg[7]_4 ,
    \uppCL3_reg[7]_5 ,
    \uppCL3_reg[8]_6 ,
    \uppCL0_reg[44]_3 ,
    \uppCL0_reg[43]_0 ,
    \uppCL0_reg[44]_4 ,
    \uppCL0_reg[43]_1 ,
    \uppCL0_reg[44]_5 ,
    rs2mask0__0_0,
    \uppCL0_reg[45]_1 ,
    \uppCL0_reg[43]_2 ,
    \uppCL1_reg[44]_3 ,
    \uppCL1_reg[43]_0 ,
    \uppCL1_reg[44]_4 ,
    \uppCL1_reg[43]_1 ,
    \uppCL1_reg[44]_5 ,
    \uppCL1_reg[43]_2 ,
    \uppCL1_reg[43]_3 ,
    \uppCL1_reg[45]_1 ,
    \uppCL1_reg[43]_4 ,
    \uppCL1_reg[43]_5 ,
    \uppCL1_reg[44]_6 ,
    \uppCL2_reg[44]_3 ,
    \uppCL2_reg[43]_0 ,
    \uppCL2_reg[44]_4 ,
    \uppCL2_reg[43]_1 ,
    \uppCL2_reg[44]_5 ,
    \uppCL2_reg[43]_2 ,
    \uppCL2_reg[43]_3 ,
    \uppCL2_reg[45]_1 ,
    \uppCL2_reg[43]_4 ,
    \uppCL2_reg[43]_5 ,
    \uppCL2_reg[44]_6 ,
    \uppCL3_reg[44]_3 ,
    \uppCL3_reg[43]_0 ,
    \uppCL3_reg[44]_4 ,
    \uppCL3_reg[43]_1 ,
    \uppCL3_reg[44]_5 ,
    \uppCL3_reg[43]_2 ,
    \uppCL3_reg[43]_3 ,
    \uppCL3_reg[45]_1 ,
    \uppCL3_reg[43]_4 ,
    \uppCL3_reg[43]_5 ,
    \uppCL3_reg[44]_6 ,
    \mcal_DQIn_byte_r1_reg[48] ,
    \io_read_data_reg[31] ,
    bisc_byte,
    \cal_RST_CKE_ODT_PAR_reg[7] ,
    \blk1.(null)[0].diff ,
    \uppCL0_reg[38]_3 ,
    rs2mask0,
    \uppCL0_reg[38]_4 ,
    \uppCL0_reg[37]_0 ,
    \uppCL0_reg[38]_5 ,
    \uppCL0_reg[37]_1 ,
    \uppCL0_reg[38]_6 ,
    \uppCL0_reg[39]_0 ,
    \uppCL0_reg[37]_2 ,
    \uppCL1_reg[37]_0 ,
    \uppCL1_reg[37]_1 ,
    \uppCL1_reg[38]_3 ,
    \uppCL1_reg[37]_2 ,
    \uppCL1_reg[38]_4 ,
    \uppCL1_reg[37]_3 ,
    \uppCL1_reg[38]_5 ,
    \uppCL1_reg[37]_4 ,
    \uppCL1_reg[38]_6 ,
    \uppCL1_reg[37]_5 ,
    \uppCL1_reg[37]_6 ,
    \uppCL1_reg[39]_0 ,
    \uppCL1_reg[37]_7 ,
    \uppCL1_reg[37]_8 ,
    \uppCL1_reg[38]_7 ,
    \uppCL2_reg[37]_0 ,
    \uppCL2_reg[37]_1 ,
    \uppCL2_reg[38]_3 ,
    \uppCL2_reg[37]_2 ,
    \uppCL2_reg[38]_4 ,
    \uppCL2_reg[37]_3 ,
    \uppCL2_reg[38]_5 ,
    \uppCL2_reg[37]_4 ,
    \uppCL2_reg[38]_6 ,
    \uppCL2_reg[37]_5 ,
    \uppCL2_reg[37]_6 ,
    \uppCL2_reg[39]_0 ,
    \uppCL2_reg[37]_7 ,
    \uppCL2_reg[37]_8 ,
    \uppCL2_reg[38]_7 ,
    \uppCL3_reg[37]_0 ,
    \uppCL3_reg[37]_1 ,
    \uppCL3_reg[38]_3 ,
    \uppCL3_reg[37]_2 ,
    \uppCL3_reg[38]_4 ,
    \uppCL3_reg[37]_3 ,
    \uppCL3_reg[38]_5 ,
    \uppCL3_reg[37]_4 ,
    \uppCL3_reg[38]_6 ,
    \uppCL3_reg[37]_5 ,
    \uppCL3_reg[37]_6 ,
    \uppCL3_reg[39]_0 ,
    \uppCL3_reg[37]_7 ,
    \uppCL3_reg[37]_8 ,
    \uppCL3_reg[38]_7 ,
    \blk1.(null)[0].diff_1 ,
    \uppCL0_reg[20]_3 ,
    rs2mask0_2,
    \uppCL0_reg[20]_4 ,
    \uppCL0_reg[19]_0 ,
    \uppCL0_reg[20]_5 ,
    \uppCL0_reg[19]_1 ,
    \uppCL0_reg[20]_6 ,
    \uppCL0_reg[21]_0 ,
    \uppCL0_reg[19]_2 ,
    \uppCL1_reg[19]_0 ,
    \uppCL1_reg[19]_1 ,
    \uppCL1_reg[20]_3 ,
    \uppCL1_reg[19]_2 ,
    \uppCL1_reg[20]_4 ,
    \uppCL1_reg[19]_3 ,
    \uppCL1_reg[20]_5 ,
    \uppCL1_reg[19]_4 ,
    \uppCL1_reg[20]_6 ,
    \uppCL1_reg[19]_5 ,
    \uppCL1_reg[19]_6 ,
    \uppCL1_reg[21]_0 ,
    \uppCL1_reg[19]_7 ,
    \uppCL1_reg[19]_8 ,
    \uppCL1_reg[20]_7 ,
    \uppCL2_reg[19]_0 ,
    \uppCL2_reg[19]_1 ,
    \uppCL2_reg[20]_3 ,
    \uppCL2_reg[19]_2 ,
    \uppCL2_reg[20]_4 ,
    \uppCL2_reg[19]_3 ,
    \uppCL2_reg[20]_5 ,
    \uppCL2_reg[19]_4 ,
    \uppCL2_reg[20]_6 ,
    \uppCL2_reg[19]_5 ,
    \uppCL2_reg[19]_6 ,
    \uppCL2_reg[21]_0 ,
    \uppCL2_reg[19]_7 ,
    \uppCL2_reg[19]_8 ,
    \uppCL2_reg[20]_7 ,
    \uppCL3_reg[19]_0 ,
    \uppCL3_reg[19]_1 ,
    \uppCL3_reg[20]_3 ,
    \uppCL3_reg[19]_2 ,
    \uppCL3_reg[20]_4 ,
    \uppCL3_reg[19]_3 ,
    \uppCL3_reg[20]_5 ,
    \uppCL3_reg[19]_4 ,
    \uppCL3_reg[20]_6 ,
    \uppCL3_reg[19]_5 ,
    \uppCL3_reg[19]_6 ,
    \uppCL3_reg[21]_0 ,
    \uppCL3_reg[19]_7 ,
    \uppCL3_reg[19]_8 ,
    \uppCL3_reg[20]_7 ,
    \blk1.(null)[0].diff_3 ,
    \uppCL0_reg[14]_3 ,
    rs2mask0_4,
    \uppCL0_reg[14]_4 ,
    \uppCL0_reg[13]_0 ,
    \uppCL0_reg[14]_5 ,
    \uppCL0_reg[13]_1 ,
    \uppCL0_reg[14]_6 ,
    \uppCL0_reg[15]_0 ,
    \uppCL0_reg[13]_2 ,
    \uppCL1_reg[13]_0 ,
    \uppCL1_reg[13]_1 ,
    \uppCL1_reg[14]_3 ,
    \uppCL1_reg[13]_2 ,
    \uppCL1_reg[14]_4 ,
    \uppCL1_reg[13]_3 ,
    \uppCL1_reg[14]_5 ,
    \uppCL1_reg[13]_4 ,
    \uppCL1_reg[14]_6 ,
    \uppCL1_reg[13]_5 ,
    \uppCL1_reg[13]_6 ,
    \uppCL1_reg[15]_0 ,
    \uppCL1_reg[13]_7 ,
    \uppCL1_reg[13]_8 ,
    \uppCL1_reg[14]_7 ,
    \uppCL2_reg[13]_0 ,
    \uppCL2_reg[13]_1 ,
    \uppCL2_reg[14]_3 ,
    \uppCL2_reg[13]_2 ,
    \uppCL2_reg[14]_4 ,
    \uppCL2_reg[13]_3 ,
    \uppCL2_reg[14]_5 ,
    \uppCL2_reg[13]_4 ,
    \uppCL2_reg[14]_6 ,
    \uppCL2_reg[13]_5 ,
    \uppCL2_reg[13]_6 ,
    \uppCL2_reg[15]_0 ,
    \uppCL2_reg[13]_7 ,
    \uppCL2_reg[13]_8 ,
    \uppCL2_reg[14]_7 ,
    \uppCL3_reg[13]_0 ,
    \uppCL3_reg[13]_1 ,
    \uppCL3_reg[14]_3 ,
    \uppCL3_reg[13]_2 ,
    \uppCL3_reg[14]_4 ,
    \uppCL3_reg[13]_3 ,
    \uppCL3_reg[14]_5 ,
    \uppCL3_reg[13]_4 ,
    \uppCL3_reg[14]_6 ,
    \uppCL3_reg[13]_5 ,
    \uppCL3_reg[13]_6 ,
    \uppCL3_reg[15]_0 ,
    \uppCL3_reg[13]_7 ,
    \uppCL3_reg[13]_8 ,
    \uppCL3_reg[14]_7 ,
    \blk1.(null)[0].diff_5 ,
    \uppCL0_reg[26]_3 ,
    rs2mask0_6,
    \uppCL0_reg[26]_4 ,
    \uppCL0_reg[25]_0 ,
    \uppCL0_reg[26]_5 ,
    \uppCL0_reg[25]_1 ,
    \uppCL0_reg[26]_6 ,
    \uppCL0_reg[27]_0 ,
    \uppCL0_reg[25]_2 ,
    \uppCL1_reg[25]_0 ,
    \uppCL1_reg[25]_1 ,
    \uppCL1_reg[26]_3 ,
    \uppCL1_reg[25]_2 ,
    \uppCL1_reg[26]_4 ,
    \uppCL1_reg[25]_3 ,
    \uppCL1_reg[26]_5 ,
    \uppCL1_reg[25]_4 ,
    \uppCL1_reg[26]_6 ,
    \uppCL1_reg[25]_5 ,
    \uppCL1_reg[25]_6 ,
    \uppCL1_reg[27]_0 ,
    \uppCL1_reg[25]_7 ,
    \uppCL1_reg[25]_8 ,
    \uppCL1_reg[26]_7 ,
    \uppCL2_reg[25]_0 ,
    \uppCL2_reg[25]_1 ,
    \uppCL2_reg[26]_3 ,
    \uppCL2_reg[25]_2 ,
    \uppCL2_reg[26]_4 ,
    \uppCL2_reg[25]_3 ,
    \uppCL2_reg[26]_5 ,
    \uppCL2_reg[25]_4 ,
    \uppCL2_reg[26]_6 ,
    \uppCL2_reg[25]_5 ,
    \uppCL2_reg[25]_6 ,
    \uppCL2_reg[27]_0 ,
    \uppCL2_reg[25]_7 ,
    \uppCL2_reg[25]_8 ,
    \uppCL2_reg[26]_7 ,
    \uppCL3_reg[25]_0 ,
    \uppCL3_reg[25]_1 ,
    \uppCL3_reg[26]_3 ,
    \uppCL3_reg[25]_2 ,
    \uppCL3_reg[26]_4 ,
    \uppCL3_reg[25]_3 ,
    \uppCL3_reg[26]_5 ,
    \uppCL3_reg[25]_4 ,
    \uppCL3_reg[26]_6 ,
    \uppCL3_reg[25]_5 ,
    \uppCL3_reg[25]_6 ,
    \uppCL3_reg[27]_0 ,
    \uppCL3_reg[25]_7 ,
    \uppCL3_reg[25]_8 ,
    \uppCL3_reg[26]_7 ,
    \blk1.(null)[0].diff_7 ,
    \lowCL0_reg[44]_3 ,
    rs2mask0_8,
    \lowCL0_reg[44]_4 ,
    \lowCL0_reg[43]_0 ,
    \lowCL0_reg[44]_5 ,
    \lowCL0_reg[43]_1 ,
    \lowCL0_reg[44]_6 ,
    \lowCL0_reg[45]_0 ,
    \lowCL0_reg[43]_2 ,
    \lowCL1_reg[43]_0 ,
    \lowCL1_reg[43]_1 ,
    \lowCL1_reg[44]_3 ,
    \lowCL1_reg[43]_2 ,
    \lowCL1_reg[44]_4 ,
    \lowCL1_reg[43]_3 ,
    \lowCL1_reg[44]_5 ,
    \lowCL1_reg[43]_4 ,
    \lowCL1_reg[44]_6 ,
    \lowCL1_reg[43]_5 ,
    \lowCL1_reg[43]_6 ,
    \lowCL1_reg[45]_0 ,
    \lowCL1_reg[43]_7 ,
    \lowCL1_reg[43]_8 ,
    \lowCL1_reg[44]_7 ,
    \lowCL2_reg[43]_0 ,
    \lowCL2_reg[43]_1 ,
    \lowCL2_reg[44]_3 ,
    \lowCL2_reg[43]_2 ,
    \lowCL2_reg[44]_4 ,
    \lowCL2_reg[43]_3 ,
    \lowCL2_reg[44]_5 ,
    \lowCL2_reg[43]_4 ,
    \lowCL2_reg[44]_6 ,
    \lowCL2_reg[43]_5 ,
    \lowCL2_reg[43]_6 ,
    \lowCL2_reg[45]_0 ,
    \lowCL2_reg[43]_7 ,
    \lowCL2_reg[43]_8 ,
    \lowCL2_reg[44]_7 ,
    \lowCL3_reg[43]_0 ,
    \lowCL3_reg[43]_1 ,
    \lowCL3_reg[44]_3 ,
    \lowCL3_reg[43]_2 ,
    \lowCL3_reg[44]_4 ,
    \lowCL3_reg[43]_3 ,
    \lowCL3_reg[44]_5 ,
    \lowCL3_reg[43]_4 ,
    \lowCL3_reg[44]_6 ,
    \lowCL3_reg[43]_5 ,
    \lowCL3_reg[43]_6 ,
    \lowCL3_reg[45]_0 ,
    \lowCL3_reg[43]_7 ,
    \lowCL3_reg[43]_8 ,
    \lowCL3_reg[44]_7 ,
    \blk1.(null)[0].diff_9 ,
    \uppCL0_reg[2]_3 ,
    rs2mask0_10,
    \uppCL0_reg[2]_4 ,
    \uppCL0_reg[1]_0 ,
    \uppCL0_reg[2]_5 ,
    \uppCL0_reg[1]_1 ,
    \uppCL0_reg[2]_6 ,
    \uppCL0_reg[3]_0 ,
    \uppCL0_reg[1]_2 ,
    \uppCL1_reg[1]_0 ,
    \uppCL1_reg[1]_1 ,
    \uppCL1_reg[2]_3 ,
    \uppCL1_reg[1]_2 ,
    \uppCL1_reg[2]_4 ,
    \uppCL1_reg[1]_3 ,
    \uppCL1_reg[2]_5 ,
    \uppCL1_reg[1]_4 ,
    \uppCL1_reg[2]_6 ,
    \uppCL1_reg[1]_5 ,
    \uppCL1_reg[1]_6 ,
    \uppCL1_reg[3]_0 ,
    \uppCL1_reg[1]_7 ,
    \uppCL1_reg[1]_8 ,
    \uppCL1_reg[2]_7 ,
    \uppCL2_reg[1]_0 ,
    \uppCL2_reg[1]_1 ,
    \uppCL2_reg[2]_3 ,
    \uppCL2_reg[1]_2 ,
    \uppCL2_reg[2]_4 ,
    \uppCL2_reg[1]_3 ,
    \uppCL2_reg[2]_5 ,
    \uppCL2_reg[1]_4 ,
    \uppCL2_reg[2]_6 ,
    \uppCL2_reg[1]_5 ,
    \uppCL2_reg[1]_6 ,
    \uppCL2_reg[3]_0 ,
    \uppCL2_reg[1]_7 ,
    \uppCL2_reg[1]_8 ,
    \uppCL2_reg[2]_7 ,
    \uppCL3_reg[1]_0 ,
    \uppCL3_reg[1]_1 ,
    \uppCL3_reg[2]_3 ,
    \uppCL3_reg[1]_2 ,
    \uppCL3_reg[2]_4 ,
    \uppCL3_reg[1]_3 ,
    \uppCL3_reg[2]_5 ,
    \uppCL3_reg[1]_4 ,
    \uppCL3_reg[2]_6 ,
    \uppCL3_reg[1]_5 ,
    \uppCL3_reg[1]_6 ,
    \uppCL3_reg[3]_0 ,
    \uppCL3_reg[1]_7 ,
    \uppCL3_reg[1]_8 ,
    \uppCL3_reg[2]_7 ,
    \blk1.(null)[0].diff_11 ,
    \uppCL0_reg[32]_3 ,
    rs2mask0_12,
    \uppCL0_reg[32]_4 ,
    \uppCL0_reg[31]_0 ,
    \uppCL0_reg[32]_5 ,
    \uppCL0_reg[31]_1 ,
    \uppCL0_reg[32]_6 ,
    \uppCL0_reg[33]_0 ,
    \uppCL0_reg[31]_2 ,
    \uppCL1_reg[31]_0 ,
    \uppCL1_reg[31]_1 ,
    \uppCL1_reg[32]_3 ,
    \uppCL1_reg[31]_2 ,
    \uppCL1_reg[32]_4 ,
    \uppCL1_reg[31]_3 ,
    \uppCL1_reg[32]_5 ,
    \uppCL1_reg[31]_4 ,
    \uppCL1_reg[32]_6 ,
    \uppCL1_reg[31]_5 ,
    \uppCL1_reg[31]_6 ,
    \uppCL1_reg[33]_0 ,
    \uppCL1_reg[31]_7 ,
    \uppCL1_reg[31]_8 ,
    \uppCL1_reg[32]_7 ,
    \uppCL2_reg[31]_0 ,
    \uppCL2_reg[31]_1 ,
    \uppCL2_reg[32]_3 ,
    \uppCL2_reg[31]_2 ,
    \uppCL2_reg[32]_4 ,
    \uppCL2_reg[31]_3 ,
    \uppCL2_reg[32]_5 ,
    \uppCL2_reg[31]_4 ,
    \uppCL2_reg[32]_6 ,
    \uppCL2_reg[31]_5 ,
    \uppCL2_reg[31]_6 ,
    \uppCL2_reg[33]_0 ,
    \uppCL2_reg[31]_7 ,
    \uppCL2_reg[31]_8 ,
    \uppCL2_reg[32]_7 ,
    \uppCL3_reg[31]_0 ,
    \uppCL3_reg[31]_1 ,
    \uppCL3_reg[32]_3 ,
    \uppCL3_reg[31]_2 ,
    \uppCL3_reg[32]_4 ,
    \uppCL3_reg[31]_3 ,
    \uppCL3_reg[32]_5 ,
    \uppCL3_reg[31]_4 ,
    \uppCL3_reg[32]_6 ,
    \uppCL3_reg[31]_5 ,
    \uppCL3_reg[31]_6 ,
    \uppCL3_reg[33]_0 ,
    \uppCL3_reg[31]_7 ,
    \uppCL3_reg[31]_8 ,
    \uppCL3_reg[32]_7 ,
    \blk1.(null)[0].diff_13 ,
    \lowCL0_reg[32]_3 ,
    rs2mask0_14,
    \lowCL0_reg[32]_4 ,
    \lowCL0_reg[31]_0 ,
    \lowCL0_reg[32]_5 ,
    \lowCL0_reg[31]_1 ,
    \lowCL0_reg[32]_6 ,
    \lowCL0_reg[33]_0 ,
    \lowCL0_reg[31]_2 ,
    \lowCL1_reg[31]_0 ,
    \lowCL1_reg[31]_1 ,
    \lowCL1_reg[32]_3 ,
    \lowCL1_reg[31]_2 ,
    \lowCL1_reg[32]_4 ,
    \lowCL1_reg[31]_3 ,
    \lowCL1_reg[32]_5 ,
    \lowCL1_reg[31]_4 ,
    \lowCL1_reg[32]_6 ,
    \lowCL1_reg[31]_5 ,
    \lowCL1_reg[31]_6 ,
    \lowCL1_reg[33]_0 ,
    \lowCL1_reg[31]_7 ,
    \lowCL1_reg[31]_8 ,
    \lowCL1_reg[32]_7 ,
    \lowCL2_reg[31]_0 ,
    \lowCL2_reg[31]_1 ,
    \lowCL2_reg[32]_3 ,
    \lowCL2_reg[31]_2 ,
    \lowCL2_reg[32]_4 ,
    \lowCL2_reg[31]_3 ,
    \lowCL2_reg[32]_5 ,
    \lowCL2_reg[31]_4 ,
    \lowCL2_reg[32]_6 ,
    \lowCL2_reg[31]_5 ,
    \lowCL2_reg[31]_6 ,
    \lowCL2_reg[33]_0 ,
    \lowCL2_reg[31]_7 ,
    \lowCL2_reg[31]_8 ,
    \lowCL2_reg[32]_7 ,
    \lowCL3_reg[31]_0 ,
    \lowCL3_reg[31]_1 ,
    \lowCL3_reg[32]_3 ,
    \lowCL3_reg[31]_2 ,
    \lowCL3_reg[32]_4 ,
    \lowCL3_reg[31]_3 ,
    \lowCL3_reg[32]_5 ,
    \lowCL3_reg[31]_4 ,
    \lowCL3_reg[32]_6 ,
    \lowCL3_reg[31]_5 ,
    \lowCL3_reg[31]_6 ,
    \lowCL3_reg[33]_0 ,
    \lowCL3_reg[31]_7 ,
    \lowCL3_reg[31]_8 ,
    \lowCL3_reg[32]_7 ,
    \blk1.(null)[0].diff_15 ,
    \lowCL0_reg[26]_3 ,
    rs2mask0_16,
    \lowCL0_reg[26]_4 ,
    \lowCL0_reg[25]_0 ,
    \lowCL0_reg[26]_5 ,
    \lowCL0_reg[25]_1 ,
    \lowCL0_reg[26]_6 ,
    \lowCL0_reg[27]_0 ,
    \lowCL0_reg[25]_2 ,
    \lowCL1_reg[25]_0 ,
    \lowCL1_reg[25]_1 ,
    \lowCL1_reg[26]_3 ,
    \lowCL1_reg[25]_2 ,
    \lowCL1_reg[26]_4 ,
    \lowCL1_reg[25]_3 ,
    \lowCL1_reg[26]_5 ,
    \lowCL1_reg[25]_4 ,
    \lowCL1_reg[26]_6 ,
    \lowCL1_reg[25]_5 ,
    \lowCL1_reg[25]_6 ,
    \lowCL1_reg[27]_0 ,
    \lowCL1_reg[25]_7 ,
    \lowCL1_reg[25]_8 ,
    \lowCL1_reg[26]_7 ,
    \lowCL2_reg[25]_0 ,
    \lowCL2_reg[25]_1 ,
    \lowCL2_reg[26]_3 ,
    \lowCL2_reg[25]_2 ,
    \lowCL2_reg[26]_4 ,
    \lowCL2_reg[25]_3 ,
    \lowCL2_reg[26]_5 ,
    \lowCL2_reg[25]_4 ,
    \lowCL2_reg[26]_6 ,
    \lowCL2_reg[25]_5 ,
    \lowCL2_reg[25]_6 ,
    \lowCL2_reg[27]_0 ,
    \lowCL2_reg[25]_7 ,
    \lowCL2_reg[25]_8 ,
    \lowCL2_reg[26]_7 ,
    \lowCL3_reg[25]_0 ,
    \lowCL3_reg[25]_1 ,
    \lowCL3_reg[26]_3 ,
    \lowCL3_reg[25]_2 ,
    \lowCL3_reg[26]_4 ,
    \lowCL3_reg[25]_3 ,
    \lowCL3_reg[26]_5 ,
    \lowCL3_reg[25]_4 ,
    \lowCL3_reg[26]_6 ,
    \lowCL3_reg[25]_5 ,
    \lowCL3_reg[25]_6 ,
    \lowCL3_reg[27]_0 ,
    \lowCL3_reg[25]_7 ,
    \lowCL3_reg[25]_8 ,
    \lowCL3_reg[26]_7 ,
    \blk1.(null)[0].diff_17 ,
    \lowCL0_reg[38]_3 ,
    rs2mask0_18,
    \lowCL0_reg[38]_4 ,
    \lowCL0_reg[37]_0 ,
    \lowCL0_reg[38]_5 ,
    \lowCL0_reg[37]_1 ,
    \lowCL0_reg[38]_6 ,
    \lowCL0_reg[39]_0 ,
    \lowCL0_reg[37]_2 ,
    \lowCL1_reg[37]_0 ,
    \lowCL1_reg[37]_1 ,
    \lowCL1_reg[38]_3 ,
    \lowCL1_reg[37]_2 ,
    \lowCL1_reg[38]_4 ,
    \lowCL1_reg[37]_3 ,
    \lowCL1_reg[38]_5 ,
    \lowCL1_reg[37]_4 ,
    \lowCL1_reg[38]_6 ,
    \lowCL1_reg[37]_5 ,
    \lowCL1_reg[37]_6 ,
    \lowCL1_reg[39]_0 ,
    \lowCL1_reg[37]_7 ,
    \lowCL1_reg[37]_8 ,
    \lowCL1_reg[38]_7 ,
    \lowCL2_reg[37]_0 ,
    \lowCL2_reg[37]_1 ,
    \lowCL2_reg[38]_3 ,
    \lowCL2_reg[37]_2 ,
    \lowCL2_reg[38]_4 ,
    \lowCL2_reg[37]_3 ,
    \lowCL2_reg[38]_5 ,
    \lowCL2_reg[37]_4 ,
    \lowCL2_reg[38]_6 ,
    \lowCL2_reg[37]_5 ,
    \lowCL2_reg[37]_6 ,
    \lowCL2_reg[39]_0 ,
    \lowCL2_reg[37]_7 ,
    \lowCL2_reg[37]_8 ,
    \lowCL2_reg[38]_7 ,
    \lowCL3_reg[37]_0 ,
    \lowCL3_reg[37]_1 ,
    \lowCL3_reg[38]_3 ,
    \lowCL3_reg[37]_2 ,
    \lowCL3_reg[38]_4 ,
    \lowCL3_reg[37]_3 ,
    \lowCL3_reg[38]_5 ,
    \lowCL3_reg[37]_4 ,
    \lowCL3_reg[38]_6 ,
    \lowCL3_reg[37]_5 ,
    \lowCL3_reg[37]_6 ,
    \lowCL3_reg[39]_0 ,
    \lowCL3_reg[37]_7 ,
    \lowCL3_reg[37]_8 ,
    \lowCL3_reg[38]_7 ,
    \blk1.(null)[0].diff_19 ,
    \lowCL0_reg[20]_3 ,
    rs2mask0_20,
    \lowCL0_reg[20]_4 ,
    \lowCL0_reg[19]_0 ,
    \lowCL0_reg[20]_5 ,
    \lowCL0_reg[19]_1 ,
    \lowCL0_reg[20]_6 ,
    \lowCL0_reg[21]_0 ,
    \lowCL0_reg[19]_2 ,
    \lowCL1_reg[19]_0 ,
    \lowCL1_reg[19]_1 ,
    \lowCL1_reg[20]_3 ,
    \lowCL1_reg[19]_2 ,
    \lowCL1_reg[20]_4 ,
    \lowCL1_reg[19]_3 ,
    \lowCL1_reg[20]_5 ,
    \lowCL1_reg[19]_4 ,
    \lowCL1_reg[20]_6 ,
    \lowCL1_reg[19]_5 ,
    \lowCL1_reg[19]_6 ,
    \lowCL1_reg[21]_0 ,
    \lowCL1_reg[19]_7 ,
    \lowCL1_reg[19]_8 ,
    \lowCL1_reg[20]_7 ,
    \lowCL2_reg[19]_0 ,
    \lowCL2_reg[19]_1 ,
    \lowCL2_reg[20]_3 ,
    \lowCL2_reg[19]_2 ,
    \lowCL2_reg[20]_4 ,
    \lowCL2_reg[19]_3 ,
    \lowCL2_reg[20]_5 ,
    \lowCL2_reg[19]_4 ,
    \lowCL2_reg[20]_6 ,
    \lowCL2_reg[19]_5 ,
    \lowCL2_reg[19]_6 ,
    \lowCL2_reg[21]_0 ,
    \lowCL2_reg[19]_7 ,
    \lowCL2_reg[19]_8 ,
    \lowCL2_reg[20]_7 ,
    \lowCL3_reg[19]_0 ,
    \lowCL3_reg[19]_1 ,
    \lowCL3_reg[20]_3 ,
    \lowCL3_reg[19]_2 ,
    \lowCL3_reg[20]_4 ,
    \lowCL3_reg[19]_3 ,
    \lowCL3_reg[20]_5 ,
    \lowCL3_reg[19]_4 ,
    \lowCL3_reg[20]_6 ,
    \lowCL3_reg[19]_5 ,
    \lowCL3_reg[19]_6 ,
    \lowCL3_reg[21]_0 ,
    \lowCL3_reg[19]_7 ,
    \lowCL3_reg[19]_8 ,
    \lowCL3_reg[20]_7 ,
    \blk1.(null)[0].diff_21 ,
    \lowCL0_reg[14]_3 ,
    rs2mask0_22,
    \lowCL0_reg[14]_4 ,
    \lowCL0_reg[13]_0 ,
    \lowCL0_reg[14]_5 ,
    \lowCL0_reg[13]_1 ,
    \lowCL0_reg[14]_6 ,
    \lowCL0_reg[15]_0 ,
    \lowCL0_reg[13]_2 ,
    \lowCL1_reg[13]_0 ,
    \lowCL1_reg[13]_1 ,
    \lowCL1_reg[14]_3 ,
    \lowCL1_reg[13]_2 ,
    \lowCL1_reg[14]_4 ,
    \lowCL1_reg[13]_3 ,
    \lowCL1_reg[14]_5 ,
    \lowCL1_reg[13]_4 ,
    \lowCL1_reg[14]_6 ,
    \lowCL1_reg[13]_5 ,
    \lowCL1_reg[13]_6 ,
    \lowCL1_reg[15]_0 ,
    \lowCL1_reg[13]_7 ,
    \lowCL1_reg[13]_8 ,
    \lowCL1_reg[14]_7 ,
    \lowCL2_reg[13]_0 ,
    \lowCL2_reg[13]_1 ,
    \lowCL2_reg[14]_3 ,
    \lowCL2_reg[13]_2 ,
    \lowCL2_reg[14]_4 ,
    \lowCL2_reg[13]_3 ,
    \lowCL2_reg[14]_5 ,
    \lowCL2_reg[13]_4 ,
    \lowCL2_reg[14]_6 ,
    \lowCL2_reg[13]_5 ,
    \lowCL2_reg[13]_6 ,
    \lowCL2_reg[15]_0 ,
    \lowCL2_reg[13]_7 ,
    \lowCL2_reg[13]_8 ,
    \lowCL2_reg[14]_7 ,
    \lowCL3_reg[13]_0 ,
    \lowCL3_reg[13]_1 ,
    \lowCL3_reg[14]_3 ,
    \lowCL3_reg[13]_2 ,
    \lowCL3_reg[14]_4 ,
    \lowCL3_reg[13]_3 ,
    \lowCL3_reg[14]_5 ,
    \lowCL3_reg[13]_4 ,
    \lowCL3_reg[14]_6 ,
    \lowCL3_reg[13]_5 ,
    \lowCL3_reg[13]_6 ,
    \lowCL3_reg[15]_0 ,
    \lowCL3_reg[13]_7 ,
    \lowCL3_reg[13]_8 ,
    \lowCL3_reg[14]_7 ,
    \blk1.(null)[0].diff_23 ,
    \lowCL0_reg[8]_3 ,
    rs2mask0_24,
    \lowCL0_reg[8]_4 ,
    \lowCL0_reg[7]_0 ,
    \lowCL0_reg[8]_5 ,
    \lowCL0_reg[7]_1 ,
    \lowCL0_reg[8]_6 ,
    \lowCL0_reg[9]_0 ,
    \lowCL0_reg[7]_2 ,
    \lowCL1_reg[7]_0 ,
    \lowCL1_reg[7]_1 ,
    \lowCL1_reg[8]_3 ,
    \lowCL1_reg[7]_2 ,
    \lowCL1_reg[8]_4 ,
    \lowCL1_reg[7]_3 ,
    \lowCL1_reg[8]_5 ,
    \lowCL1_reg[7]_4 ,
    \lowCL1_reg[8]_6 ,
    \lowCL1_reg[7]_5 ,
    \lowCL1_reg[7]_6 ,
    \lowCL1_reg[9]_0 ,
    \lowCL1_reg[7]_7 ,
    \lowCL1_reg[7]_8 ,
    \lowCL1_reg[8]_7 ,
    \lowCL2_reg[7]_0 ,
    \lowCL2_reg[7]_1 ,
    \lowCL2_reg[8]_3 ,
    \lowCL2_reg[7]_2 ,
    \lowCL2_reg[8]_4 ,
    \lowCL2_reg[7]_3 ,
    \lowCL2_reg[8]_5 ,
    \lowCL2_reg[7]_4 ,
    \lowCL2_reg[8]_6 ,
    \lowCL2_reg[7]_5 ,
    \lowCL2_reg[7]_6 ,
    \lowCL2_reg[9]_0 ,
    \lowCL2_reg[7]_7 ,
    \lowCL2_reg[7]_8 ,
    \lowCL2_reg[8]_7 ,
    \lowCL3_reg[7]_0 ,
    \lowCL3_reg[7]_1 ,
    \lowCL3_reg[8]_3 ,
    \lowCL3_reg[7]_2 ,
    \lowCL3_reg[8]_4 ,
    \lowCL3_reg[7]_3 ,
    \lowCL3_reg[8]_5 ,
    \lowCL3_reg[7]_4 ,
    \lowCL3_reg[8]_6 ,
    \lowCL3_reg[7]_5 ,
    \lowCL3_reg[7]_6 ,
    \lowCL3_reg[9]_0 ,
    \lowCL3_reg[7]_7 ,
    \lowCL3_reg[7]_8 ,
    \lowCL3_reg[8]_7 ,
    \blk1.(null)[0].diff_25 ,
    \lowCL0_reg[2]_3 ,
    rs2mask0_26,
    \lowCL0_reg[2]_4 ,
    \lowCL0_reg[1]_0 ,
    \lowCL0_reg[2]_5 ,
    \lowCL0_reg[1]_1 ,
    \lowCL0_reg[2]_6 ,
    \lowCL0_reg[3]_0 ,
    \lowCL0_reg[1]_2 ,
    \lowCL1_reg[1]_0 ,
    \lowCL1_reg[1]_1 ,
    \lowCL1_reg[2]_3 ,
    \lowCL1_reg[1]_2 ,
    \lowCL1_reg[2]_4 ,
    \lowCL1_reg[1]_3 ,
    \lowCL1_reg[2]_5 ,
    \lowCL1_reg[1]_4 ,
    \lowCL1_reg[2]_6 ,
    \lowCL1_reg[1]_5 ,
    \lowCL1_reg[1]_6 ,
    \lowCL1_reg[3]_0 ,
    \lowCL1_reg[1]_7 ,
    \lowCL1_reg[1]_8 ,
    \lowCL1_reg[2]_7 ,
    \lowCL2_reg[1]_0 ,
    \lowCL2_reg[1]_1 ,
    \lowCL2_reg[2]_3 ,
    \lowCL2_reg[1]_2 ,
    \lowCL2_reg[2]_4 ,
    \lowCL2_reg[1]_3 ,
    \lowCL2_reg[2]_5 ,
    \lowCL2_reg[1]_4 ,
    \lowCL2_reg[2]_6 ,
    \lowCL2_reg[1]_5 ,
    \lowCL2_reg[1]_6 ,
    \lowCL2_reg[3]_0 ,
    \lowCL2_reg[1]_7 ,
    \lowCL2_reg[1]_8 ,
    \lowCL2_reg[2]_7 ,
    \lowCL3_reg[1]_0 ,
    \lowCL3_reg[1]_1 ,
    \lowCL3_reg[2]_3 ,
    \lowCL3_reg[1]_2 ,
    \lowCL3_reg[2]_4 ,
    \lowCL3_reg[1]_3 ,
    \lowCL3_reg[2]_5 ,
    \lowCL3_reg[1]_4 ,
    \lowCL3_reg[2]_6 ,
    \lowCL3_reg[1]_5 ,
    \lowCL3_reg[1]_6 ,
    \lowCL3_reg[3]_0 ,
    \lowCL3_reg[1]_7 ,
    \lowCL3_reg[1]_8 ,
    \lowCL3_reg[2]_7 ,
    read_lat_shift_cal_dq_valid_nxt,
    \blk1.(null)[0].diff_27 ,
    \uppCL0_reg[8]_6 ,
    \uppCL1_reg[7]_6 ,
    \uppCL1_reg[7]_7 ,
    \uppCL1_reg[8]_7 ,
    \uppCL2_reg[7]_6 ,
    \uppCL2_reg[7]_7 ,
    \uppCL2_reg[8]_7 ,
    \uppCL3_reg[7]_6 ,
    \uppCL3_reg[7]_7 ,
    \uppCL3_reg[8]_7 ,
    \blk1.(null)[0].diff_28 ,
    \uppCL0_reg[44]_6 ,
    \uppCL1_reg[43]_6 ,
    \uppCL1_reg[43]_7 ,
    \uppCL1_reg[44]_7 ,
    \uppCL2_reg[43]_6 ,
    \uppCL2_reg[43]_7 ,
    \uppCL2_reg[44]_7 ,
    \uppCL3_reg[43]_6 ,
    \uppCL3_reg[43]_7 ,
    \uppCL3_reg[44]_7 ,
    \cplx_error_accum_reg[63] ,
    out,
    \SYNC[0].sync_reg_reg[1]_1 ,
    ena,
    io_address,
    SR,
    io_addr_strobe_r1_reg,
    calDone_reg_14,
    io_write_data,
    lrdimm_cmp_clr,
    lrdimm_cal_mode_reg_1,
    p_52_in,
    clear_gt_data_ready_flag,
    gt_data_ready_flag_nxt,
    ub_ready_reg_0,
    E,
    wren_reg,
    \clb2phy_wrcs0_low_reg[31] ,
    O,
    \cal_timer_reg[15] ,
    \cal_timer_reg[23] ,
    \cal_timer_reg[31] ,
    stop_gate_tracking_ack_reg_0,
    cnt_clr_reg_0,
    a_b_cmd_sel_start_reg_0,
    lrdimm_cmp_en_reg_0,
    cal_seq_cnt_gt_0_reg,
    xsdb_wr_en_reg,
    \cal_oe_dis_low_reg[7] ,
    \cal_oe_dis_upp_reg[7] ,
    pllGate,
    \calSt_reg[0]_0 ,
    Q,
    mc_BA,
    mc_CKE7,
    mc_CKE,
    mc_ODT,
    mc_ODT7,
    winAct,
    mc_CS_n,
    mc_CS_n7,
    calDone_gated_reg,
    mcRdCAS,
    mcCasSlot2,
    \mcal_ADR_dly_reg[0][135] ,
    mc_ADR,
    \mcal_ADR_dly_reg[0][128] ,
    mc_BG,
    p_1_in,
    \mcal_PAR_dly_reg[0][5] ,
    \mcal_PAR_dly_reg[0][3] ,
    \mcal_PAR_dly_reg[0][1] ,
    \mcal_PAR_dly_reg[0][7] ,
    \mcal_PAR_dly_reg[0][0] ,
    \dReg_reg[15] ,
    mcWrCAS,
    \wrQ_reg[1][0] ,
    \rsMask_reg[1]_71 ,
    \rsMask_reg[3]_73 ,
    \rsMask_reg[1]_79 ,
    \rsMask_reg[3]_81 ,
    \cplx_config_reg[16] ,
    \cplx_config_reg[16]_0 ,
    cnt_clr_access,
    a_b_cmd_sel_start0,
    cal_timer_reg_0_sp_1,
    \addr_dec_to_mb_data[7]_i_7 ,
    io_ready_reg,
    \addr_dec_to_mb_data_reg[15] ,
    \addr_dec_to_mb_data_reg[19] ,
    \addr_dec_to_mb_data_reg[12] ,
    \addr_dec_to_mb_data[0]_i_3 ,
    io_ready_reg_0,
    io_ready_reg_1,
    \addr_dec_to_mb_data_reg[29] ,
    \addr_dec_to_mb_data_reg[29]_0 ,
    \addr_dec_to_mb_data_reg[14] ,
    \addr_dec_to_mb_data_reg[29]_1 ,
    \addr_dec_to_mb_data_reg[29]_2 ,
    \addr_dec_to_mb_data_reg[29]_3 ,
    \addr_dec_to_mb_data[4]_i_11 ,
    \dqin_valid_shift_reg[0] ,
    \addr_dec_to_mb_data[31]_i_3 ,
    wrDataEn_pi,
    rdDataEn_pi,
    \addr_dec_to_mb_data[6]_i_7 ,
    \addr_dec_to_mb_data[6]_i_7_0 ,
    \rsMask_reg[7]_77 ,
    \rsMask_reg[5]_75 ,
    \rsMask_reg[7]_85 ,
    \rsMask_reg[5]_83 ,
    \rdEn_reg[29] ,
    \rdEn_reg[29]_0 ,
    \rdEn_reg[28] ,
    wosp,
    \dReg_reg[9] ,
    wrDataVal,
    \dReg_reg[9]_0 ,
    \dReg_reg[11] ,
    \dReg_reg[10] ,
    \dReg_reg[9]_1 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[8] ,
    \dReg_reg[8]_0 ,
    \rdEn_reg[29]_1 ,
    \rdEn_reg[28]_0 ,
    \rdEn_reg[29]_2 ,
    \rdEn_reg[28]_1 ,
    \rdEn_reg[29]_3 ,
    \rdEn_reg[28]_2 ,
    \rdEn_reg[29]_4 ,
    \rdEn_reg[28]_3 ,
    \rdEn_reg[29]_5 ,
    \rdEn_reg[28]_4 ,
    \rdEn_reg[29]_6 ,
    \rdEn_reg[28]_5 ,
    \rdEn_reg[29]_7 ,
    \rdEn_reg[28]_6 ,
    \rdEn_reg[29]_8 ,
    \rdEn_reg[28]_7 ,
    \rdEn_reg[29]_9 ,
    \rdEn_reg[28]_8 ,
    \rdEn_reg[29]_10 ,
    \rdEn_reg[28]_9 ,
    \rdEn_reg[29]_11 ,
    \rdEn_reg[28]_10 ,
    \rdEn_reg[29]_12 ,
    \rdEn_reg[28]_11 ,
    \rdEn_reg[29]_13 ,
    \rdEn_reg[28]_12 ,
    \dout_o_reg[11]_0 ,
    \cal_seq_reg[2] ,
    \mcal_DQIn_r_reg[511] ,
    \cal_cmp_en_reg[7] ,
    \cal_DQPat_A_reg[63] ,
    \cal_DQPat_A_reg[31] ,
    \cal_DQPat_B_reg[63] ,
    \cal_DQPat_B_reg[31] ,
    \cmp_byte_reg[2] ,
    \cal_cs_pos_reg[1] ,
    \cplx_config_reg[0] ,
    \cplx_config_reg[1] ,
    \cal_seq_a_b_dly_reg[7] ,
    \cal_seq_a_a_dly_reg[7] ,
    \cal_seq_b_a_dly_reg[7] ,
    \cal_RST_CKE_ODT_PAR_reg[31] ,
    \traffic_instr_nxt_instr_r1_reg[5] ,
    \uppCL3_reg[42]_1 ,
    \uppCL0_reg[47] ,
    \uppCL1_reg[47] ,
    \uppCL2_reg[47] ,
    \uppCL3_reg[47] ,
    \cal_CS_A_reg[7]_0 ,
    \cal_CS_B_reg[7] ,
    \mcal_DMIn_n_r_reg[63] ,
    \cal_ADR_A_reg[31] ,
    \cal_ADR_B_reg[31]_0 ,
    \addr_dec_to_mb_data_reg[31] ,
    \addr_dec_to_mb_data_reg[30] ,
    \addr_dec_to_mb_data_reg[30]_0 ,
    \addr_dec_to_mb_data_reg[29]_4 ,
    \addr_dec_to_mb_data_reg[28] ,
    \addr_dec_to_mb_data_reg[27] ,
    \addr_dec_to_mb_data_reg[26] ,
    \addr_dec_to_mb_data_reg[25] ,
    \addr_dec_to_mb_data_reg[24] ,
    \addr_dec_to_mb_data_reg[23] ,
    \addr_dec_to_mb_data_reg[22] ,
    \addr_dec_to_mb_data_reg[21] ,
    \addr_dec_to_mb_data_reg[20] ,
    \bisc_bit_reg[0] ,
    \cal_DQOut_A_reg[63] ,
    \cal_DQOut_A_reg[31] ,
    \cal_DQOut_pre_reg[63] ,
    \cal_DQOut_pre_reg[31] ,
    \cal_DQOut_post_reg[63] ,
    \cal_DQOut_post_reg[31] ,
    \cal_DMOut_n_A_reg[31] ,
    \genblk10[3].cal_DMOut_n_A_r_reg[24] ,
    \genblk10[6].cal_DMOut_n_A_r_reg[48] ,
    \cal_CAS_A_reg[0] ,
    \cal_RAS_B_reg[0] ,
    \cal_ACT_n_A_reg[7] ,
    \max_rd_lat_reg[5]_0 ,
    rd_vref_value0_out,
    \mc_clb2phy_fifo_rden_nxt[103]_i_3_0 );
  output [16:0]sl_oport_o;
  output [8:0]douta;
  output calDone_reg_0;
  output calDone_reg_1;
  output initDone;
  output cnt_clr_reg;
  output rst_r1_reg_0;
  output lrdimm_cmp_en_reg;
  output clear_gt_data_ready_flag_reg;
  output gt_data_ready_flag;
  output [0:0]io_ready_lvl_reg;
  output [0:0]D;
  output ub_initDone_reg;
  output en_vtc;
  output calRdCAS;
  output cal_clear_fifo_rden;
  output wrCAS_reg;
  output [31:0]cal_timer_reg;
  output stop_gate_tracking_ack_reg;
  output a_b_cmd_sel_start_reg;
  output [0:0]cal_oe_dis_low;
  output [0:0]cal_oe_dis_upp;
  output rdCAS_reg;
  output [7:0]\cplx_CAS_reg[6] ;
  output \cal_RAS_pre_reg[1] ;
  output \cal_RAS_pre_reg[2] ;
  output \cplx_RAS_reg[6] ;
  output \cplx_RAS_reg[6]_0 ;
  output [5:0]\cal_ACT_n_pre_reg[7] ;
  output [3:0]cal_CS_n;
  output [8:0]\init_cal_BA_reg[15]_0 ;
  output [2:0]\cal_RST_CKE_ODT_PAR_reg[16] ;
  output [2:0]ub_ready_reg;
  output [1:0]winAct_reg;
  output [3:0]cplx_cal_reg;
  output calDone_i;
  output mcalRdCAS;
  output [0:0]mcalCasSlot;
  output [1:0]mcalRank;
  output [76:0]calDone_reg_2;
  output \init_cal_BA_reg[7]_0 ;
  output [3:0]calDone_reg_3;
  output \init_cal_BG_reg[7]_0 ;
  output [7:0]calDone_reg_4;
  output [511:0]DQOut;
  output [63:0]DMOut;
  output calDone_reg_5;
  output calDone_reg_6;
  output calDone_reg_7;
  output calDone_reg_8;
  output calDone_reg_9;
  output calDone_reg_10;
  output calDone_reg_11;
  output calDone_reg_12;
  output [0:0]\wrQ_nxt[1]_13 ;
  output calDone_reg_13;
  output \uppCL0_reg[38]_0 ;
  output [5:0]\uppCL0_reg[45]_0 ;
  output \uppCL0_reg[38]_1 ;
  output \uppCL0_reg[36]_0 ;
  output \uppCL1_reg[38]_0 ;
  output [5:0]\uppCL1_reg[45]_0 ;
  output \uppCL1_reg[38]_1 ;
  output \uppCL1_reg[36]_0 ;
  output \uppCL2_reg[38]_0 ;
  output [5:0]\uppCL2_reg[45]_0 ;
  output \uppCL2_reg[38]_1 ;
  output \uppCL2_reg[36]_0 ;
  output \uppCL3_reg[38]_0 ;
  output [5:0]\uppCL3_reg[45]_0 ;
  output \uppCL3_reg[38]_1 ;
  output \uppCL3_reg[36]_0 ;
  output \uppCL0_reg[20]_0 ;
  output \uppCL0_reg[20]_1 ;
  output \uppCL0_reg[18]_0 ;
  output \uppCL1_reg[20]_0 ;
  output \uppCL1_reg[20]_1 ;
  output \uppCL1_reg[18]_0 ;
  output \uppCL2_reg[20]_0 ;
  output \uppCL2_reg[20]_1 ;
  output \uppCL2_reg[18]_0 ;
  output \uppCL3_reg[20]_0 ;
  output \uppCL3_reg[20]_1 ;
  output \uppCL3_reg[18]_0 ;
  output \uppCL0_reg[14]_0 ;
  output \uppCL0_reg[14]_1 ;
  output \uppCL0_reg[12]_0 ;
  output \uppCL1_reg[14]_0 ;
  output \uppCL1_reg[14]_1 ;
  output \uppCL1_reg[12]_0 ;
  output \uppCL2_reg[14]_0 ;
  output \uppCL2_reg[14]_1 ;
  output \uppCL2_reg[12]_0 ;
  output \uppCL3_reg[14]_0 ;
  output \uppCL3_reg[14]_1 ;
  output \uppCL3_reg[12]_0 ;
  output \uppCL0_reg[26]_0 ;
  output \uppCL0_reg[26]_1 ;
  output \uppCL0_reg[24]_0 ;
  output \uppCL1_reg[26]_0 ;
  output \uppCL1_reg[26]_1 ;
  output \uppCL1_reg[24]_0 ;
  output \uppCL2_reg[26]_0 ;
  output \uppCL2_reg[26]_1 ;
  output \uppCL2_reg[24]_0 ;
  output \uppCL3_reg[26]_0 ;
  output \uppCL3_reg[26]_1 ;
  output \uppCL3_reg[24]_0 ;
  output \uppCL3_reg[38]_2 ;
  output \uppCL2_reg[38]_2 ;
  output \uppCL1_reg[38]_2 ;
  output \uppCL0_reg[38]_2 ;
  output \uppCL3_reg[26]_2 ;
  output \uppCL2_reg[26]_2 ;
  output \uppCL1_reg[26]_2 ;
  output \uppCL0_reg[26]_2 ;
  output \uppCL3_reg[20]_2 ;
  output \uppCL2_reg[20]_2 ;
  output \uppCL1_reg[20]_2 ;
  output \uppCL0_reg[20]_2 ;
  output \uppCL3_reg[14]_2 ;
  output \uppCL2_reg[14]_2 ;
  output \uppCL1_reg[14]_2 ;
  output \uppCL0_reg[14]_2 ;
  output \uppCL0_reg[8]_0 ;
  output \uppCL0_reg[8]_1 ;
  output \uppCL0_reg[6]_0 ;
  output \uppCL1_reg[8]_0 ;
  output \uppCL1_reg[8]_1 ;
  output \uppCL1_reg[6]_0 ;
  output \uppCL2_reg[8]_0 ;
  output \uppCL2_reg[8]_1 ;
  output \uppCL2_reg[6]_0 ;
  output \uppCL3_reg[8]_0 ;
  output \uppCL3_reg[8]_1 ;
  output \uppCL3_reg[6]_0 ;
  output \uppCL0_reg[44]_0 ;
  output \uppCL0_reg[44]_1 ;
  output \uppCL0_reg[42]_0 ;
  output \uppCL1_reg[44]_0 ;
  output \uppCL1_reg[44]_1 ;
  output \uppCL1_reg[42]_0 ;
  output \uppCL2_reg[44]_0 ;
  output \uppCL2_reg[44]_1 ;
  output \uppCL2_reg[42]_0 ;
  output \uppCL3_reg[44]_0 ;
  output \uppCL3_reg[44]_1 ;
  output \uppCL3_reg[42]_0 ;
  output \uppCL1_reg[44]_2 ;
  output \uppCL0_reg[44]_2 ;
  output \uppCL3_reg[44]_2 ;
  output \uppCL2_reg[44]_2 ;
  output \uppCL1_reg[8]_2 ;
  output \uppCL0_reg[8]_2 ;
  output \uppCL3_reg[8]_2 ;
  output \uppCL2_reg[8]_2 ;
  output \lowCL0_reg[44]_0 ;
  output \lowCL0_reg[44]_1 ;
  output \lowCL0_reg[42]_0 ;
  output \lowCL1_reg[44]_0 ;
  output \lowCL1_reg[44]_1 ;
  output \lowCL1_reg[42]_0 ;
  output \lowCL2_reg[44]_0 ;
  output \lowCL2_reg[44]_1 ;
  output \lowCL2_reg[42]_0 ;
  output \lowCL3_reg[44]_0 ;
  output \lowCL3_reg[44]_1 ;
  output \lowCL3_reg[42]_0 ;
  output \uppCL0_reg[2]_0 ;
  output \uppCL0_reg[2]_1 ;
  output \uppCL0_reg[0]_0 ;
  output \uppCL1_reg[2]_0 ;
  output \uppCL1_reg[2]_1 ;
  output \uppCL1_reg[0]_0 ;
  output \uppCL2_reg[2]_0 ;
  output \uppCL2_reg[2]_1 ;
  output \uppCL2_reg[0]_0 ;
  output \uppCL3_reg[2]_0 ;
  output \uppCL3_reg[2]_1 ;
  output \uppCL3_reg[0]_0 ;
  output \uppCL0_reg[32]_0 ;
  output \uppCL0_reg[32]_1 ;
  output \uppCL0_reg[30]_0 ;
  output \uppCL1_reg[32]_0 ;
  output \uppCL1_reg[32]_1 ;
  output \uppCL1_reg[30]_0 ;
  output \uppCL2_reg[32]_0 ;
  output \uppCL2_reg[32]_1 ;
  output \uppCL2_reg[30]_0 ;
  output \uppCL3_reg[32]_0 ;
  output \uppCL3_reg[32]_1 ;
  output \uppCL3_reg[30]_0 ;
  output \lowCL3_reg[44]_2 ;
  output \lowCL2_reg[44]_2 ;
  output \lowCL1_reg[44]_2 ;
  output \lowCL0_reg[44]_2 ;
  output \uppCL3_reg[32]_2 ;
  output \uppCL2_reg[32]_2 ;
  output \uppCL1_reg[32]_2 ;
  output \uppCL0_reg[32]_2 ;
  output \uppCL3_reg[2]_2 ;
  output \uppCL2_reg[2]_2 ;
  output \uppCL1_reg[2]_2 ;
  output \uppCL0_reg[2]_2 ;
  output \lowCL0_reg[32]_0 ;
  output \lowCL0_reg[32]_1 ;
  output \lowCL0_reg[30]_0 ;
  output \lowCL1_reg[32]_0 ;
  output \lowCL1_reg[32]_1 ;
  output \lowCL1_reg[30]_0 ;
  output \lowCL2_reg[32]_0 ;
  output \lowCL2_reg[32]_1 ;
  output \lowCL2_reg[30]_0 ;
  output \lowCL3_reg[32]_0 ;
  output \lowCL3_reg[32]_1 ;
  output \lowCL3_reg[30]_0 ;
  output \lowCL0_reg[26]_0 ;
  output \lowCL0_reg[26]_1 ;
  output \lowCL0_reg[24]_0 ;
  output \lowCL1_reg[26]_0 ;
  output \lowCL1_reg[26]_1 ;
  output \lowCL1_reg[24]_0 ;
  output \lowCL2_reg[26]_0 ;
  output \lowCL2_reg[26]_1 ;
  output \lowCL2_reg[24]_0 ;
  output \lowCL3_reg[26]_0 ;
  output \lowCL3_reg[26]_1 ;
  output \lowCL3_reg[24]_0 ;
  output \lowCL0_reg[38]_0 ;
  output \lowCL0_reg[38]_1 ;
  output \lowCL0_reg[36]_0 ;
  output \lowCL1_reg[38]_0 ;
  output \lowCL1_reg[38]_1 ;
  output \lowCL1_reg[36]_0 ;
  output \lowCL2_reg[38]_0 ;
  output \lowCL2_reg[38]_1 ;
  output \lowCL2_reg[36]_0 ;
  output \lowCL3_reg[38]_0 ;
  output \lowCL3_reg[38]_1 ;
  output \lowCL3_reg[36]_0 ;
  output \lowCL3_reg[38]_2 ;
  output \lowCL2_reg[38]_2 ;
  output \lowCL1_reg[38]_2 ;
  output \lowCL0_reg[38]_2 ;
  output \lowCL3_reg[32]_2 ;
  output \lowCL2_reg[32]_2 ;
  output \lowCL1_reg[32]_2 ;
  output \lowCL0_reg[32]_2 ;
  output \lowCL3_reg[26]_2 ;
  output \lowCL2_reg[26]_2 ;
  output \lowCL1_reg[26]_2 ;
  output \lowCL0_reg[26]_2 ;
  output \lowCL0_reg[20]_0 ;
  output \lowCL0_reg[20]_1 ;
  output \lowCL0_reg[18]_0 ;
  output \lowCL1_reg[20]_0 ;
  output \lowCL1_reg[20]_1 ;
  output \lowCL1_reg[18]_0 ;
  output \lowCL2_reg[20]_0 ;
  output \lowCL2_reg[20]_1 ;
  output \lowCL2_reg[18]_0 ;
  output \lowCL3_reg[20]_0 ;
  output \lowCL3_reg[20]_1 ;
  output \lowCL3_reg[18]_0 ;
  output \lowCL0_reg[14]_0 ;
  output \lowCL0_reg[14]_1 ;
  output \lowCL0_reg[12]_0 ;
  output \lowCL1_reg[14]_0 ;
  output \lowCL1_reg[14]_1 ;
  output \lowCL1_reg[12]_0 ;
  output \lowCL2_reg[14]_0 ;
  output \lowCL2_reg[14]_1 ;
  output \lowCL2_reg[12]_0 ;
  output \lowCL3_reg[14]_0 ;
  output \lowCL3_reg[14]_1 ;
  output \lowCL3_reg[12]_0 ;
  output \lowCL0_reg[8]_0 ;
  output \lowCL0_reg[8]_1 ;
  output \lowCL0_reg[6]_0 ;
  output \lowCL1_reg[8]_0 ;
  output \lowCL1_reg[8]_1 ;
  output \lowCL1_reg[6]_0 ;
  output \lowCL2_reg[8]_0 ;
  output \lowCL2_reg[8]_1 ;
  output \lowCL2_reg[6]_0 ;
  output \lowCL3_reg[8]_0 ;
  output \lowCL3_reg[8]_1 ;
  output \lowCL3_reg[6]_0 ;
  output \lowCL0_reg[2]_0 ;
  output \lowCL0_reg[2]_1 ;
  output \lowCL0_reg[0]_0 ;
  output \lowCL1_reg[2]_0 ;
  output \lowCL1_reg[2]_1 ;
  output \lowCL1_reg[0]_0 ;
  output \lowCL2_reg[2]_0 ;
  output \lowCL2_reg[2]_1 ;
  output \lowCL2_reg[0]_0 ;
  output \lowCL3_reg[2]_0 ;
  output \lowCL3_reg[2]_1 ;
  output \lowCL3_reg[0]_0 ;
  output \lowCL3_reg[20]_2 ;
  output \lowCL2_reg[20]_2 ;
  output \lowCL1_reg[20]_2 ;
  output \lowCL0_reg[20]_2 ;
  output \lowCL3_reg[14]_2 ;
  output \lowCL2_reg[14]_2 ;
  output \lowCL1_reg[14]_2 ;
  output \lowCL0_reg[14]_2 ;
  output \lowCL3_reg[8]_2 ;
  output \lowCL2_reg[8]_2 ;
  output \lowCL1_reg[8]_2 ;
  output \lowCL0_reg[8]_2 ;
  output \lowCL3_reg[2]_2 ;
  output \lowCL2_reg[2]_2 ;
  output \lowCL1_reg[2]_2 ;
  output \lowCL0_reg[2]_2 ;
  output \SYNC[0].sync_reg_reg[1] ;
  output [7:0]\cal_seq_rd_cnt_reg[7] ;
  output [31:0]\cal_seq_cnt_reg[31] ;
  output \cal_CS_A_reg[6] ;
  output \cal_CS_A_reg[7] ;
  output \SYNC[20].sync_reg_reg[1] ;
  output \cal_CS_A_reg[0] ;
  output \cplx_error_accum_reg[14] ;
  output \cplx_error_accum_reg[15] ;
  output \cplx_error_accum_reg[44] ;
  output \cal_ADR_B_reg[12] ;
  output \cplx_error_accum_reg[19] ;
  output \cal_ADR_A_reg[0] ;
  output cal_timer_reg_29_sp_1;
  output cal_timer_reg_28_sp_1;
  output cal_timer_reg_25_sp_1;
  output cal_timer_reg_24_sp_1;
  output cal_timer_reg_21_sp_1;
  output [4:0]\cal_CS_B_reg[5] ;
  output [4:0]\cal_CS_A_reg[5] ;
  output [12:0]\cal_ADR_B_reg[30] ;
  output [11:0]\cal_ADR_A_reg[30] ;
  output \SYNC[5].sync_reg_reg[1] ;
  output \SYNC[5].sync_reg_reg[1]_0 ;
  output \mcal_DQIn_byte_r1_reg[31] ;
  output \cal_ADR_A_reg[29] ;
  output \cal_ADR_A_reg[27] ;
  output \cal_ADR_A_reg[26] ;
  output \cal_ADR_B_reg[25] ;
  output \cal_ADR_B_reg[24] ;
  output \cal_ADR_A_reg[21] ;
  output \cal_ADR_A_reg[20] ;
  output \cal_ADR_B_reg[19] ;
  output \cal_ADR_B_reg[18] ;
  output \cal_ADR_B_reg[17] ;
  output \cal_RST_CKE_ODT_PAR_reg[16]_0 ;
  output \cal_ADR_B_reg[15] ;
  output \cal_ADR_B_reg[13] ;
  output \cal_ADR_B_reg[11] ;
  output \cal_ADR_B_reg[10] ;
  output \cal_RST_CKE_ODT_PAR_reg[9] ;
  output \cal_ADR_A_reg[1] ;
  output [10:0]\cal_RST_CKE_ODT_PAR_reg[30] ;
  output \cal_ADR_A_reg[4] ;
  output \cal_seq_cnt_reg[13] ;
  output mem_reg_bram_0;
  output \cal_ADR_B_reg[31] ;
  output \SYNC[3].sync_reg_reg[1] ;
  output \SYNC[3].sync_reg_reg[1]_0 ;
  output \SYNC[3].sync_reg_reg[1]_1 ;
  output \SYNC[3].sync_reg_reg[1]_2 ;
  output \SYNC[0].sync_reg_reg[1]_0 ;
  output \SYNC[3].sync_reg_reg[1]_3 ;
  output \SYNC[3].sync_reg_reg[1]_4 ;
  output \SYNC[3].sync_reg_reg[1]_5 ;
  output \SYNC[3].sync_reg_reg[1]_6 ;
  output \SYNC[3].sync_reg_reg[1]_7 ;
  output \SYNC[3].sync_reg_reg[1]_8 ;
  output \SYNC[3].sync_reg_reg[1]_9 ;
  output \SYNC[3].sync_reg_reg[1]_10 ;
  output \SYNC[3].sync_reg_reg[1]_11 ;
  output \SYNC[3].sync_reg_reg[1]_12 ;
  output \SYNC[3].sync_reg_reg[1]_13 ;
  output \SYNC[3].sync_reg_reg[1]_14 ;
  output \SYNC[3].sync_reg_reg[1]_15 ;
  output \SYNC[3].sync_reg_reg[1]_16 ;
  output \SYNC[3].sync_reg_reg[1]_17 ;
  output \SYNC[3].sync_reg_reg[1]_18 ;
  output \SYNC[3].sync_reg_reg[1]_19 ;
  output \SYNC[3].sync_reg_reg[1]_20 ;
  output \SYNC[3].sync_reg_reg[1]_21 ;
  output \SYNC[3].sync_reg_reg[1]_22 ;
  output \SYNC[3].sync_reg_reg[1]_23 ;
  output \SYNC[3].sync_reg_reg[1]_24 ;
  output \SYNC[3].sync_reg_reg[1]_25 ;
  output \SYNC[3].sync_reg_reg[1]_26 ;
  output \SYNC[3].sync_reg_reg[1]_27 ;
  output \SYNC[3].sync_reg_reg[1]_28 ;
  output \SYNC[3].sync_reg_reg[1]_29 ;
  output \SYNC[3].sync_reg_reg[1]_30 ;
  output \SYNC[3].sync_reg_reg[1]_31 ;
  output \SYNC[3].sync_reg_reg[1]_32 ;
  output \SYNC[3].sync_reg_reg[1]_33 ;
  output \SYNC[3].sync_reg_reg[1]_34 ;
  output \SYNC[3].sync_reg_reg[1]_35 ;
  output \SYNC[3].sync_reg_reg[1]_36 ;
  output \SYNC[3].sync_reg_reg[1]_37 ;
  output \SYNC[3].sync_reg_reg[1]_38 ;
  output \SYNC[3].sync_reg_reg[1]_39 ;
  output \SYNC[3].sync_reg_reg[1]_40 ;
  output \SYNC[3].sync_reg_reg[1]_41 ;
  output \SYNC[3].sync_reg_reg[1]_42 ;
  output \SYNC[3].sync_reg_reg[1]_43 ;
  output \SYNC[3].sync_reg_reg[1]_44 ;
  output \SYNC[3].sync_reg_reg[1]_45 ;
  output \SYNC[5].sync_reg_reg[1]_1 ;
  output \SYNC[5].sync_reg_reg[1]_2 ;
  output \SYNC[5].sync_reg_reg[1]_3 ;
  output \SYNC[5].sync_reg_reg[1]_4 ;
  output \cal_ADR_A_reg[22] ;
  output \SYNC[5].sync_reg_reg[1]_5 ;
  output \SYNC[5].sync_reg_reg[1]_6 ;
  output \SYNC[5].sync_reg_reg[1]_7 ;
  output \SYNC[5].sync_reg_reg[1]_8 ;
  output \SYNC[5].sync_reg_reg[1]_9 ;
  output \SYNC[5].sync_reg_reg[1]_10 ;
  output \SYNC[5].sync_reg_reg[1]_11 ;
  output \SYNC[5].sync_reg_reg[1]_12 ;
  output \SYNC[5].sync_reg_reg[1]_13 ;
  output \genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9] ;
  output \genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8] ;
  output \SYNC[4].sync_reg_reg[1] ;
  output \SYNC[5].sync_reg_reg[1]_14 ;
  output \cal_ADR_A_reg[4]_0 ;
  output \cal_CS_A_reg[4] ;
  output \SYNC[4].sync_reg_reg[1]_0 ;
  output \rd_vref_value_reg[46] ;
  output [6:0]\mcal_DMIn_bit_r1_reg[7] ;
  output \cal_ADR_A_reg[3] ;
  output \SYNC[5].sync_reg_reg[1]_15 ;
  output \cal_ADR_A_reg[2] ;
  output \SYNC[18].sync_reg_reg[1] ;
  output \SYNC[5].sync_reg_reg[1]_16 ;
  output gt_data_ready_flag_reg;
  output [0:0]cplx_status;
  output \cal_ADR_A_reg[0]_0 ;
  output \dout_o_reg[5] ;
  output [10:0]\dout_o_reg[11] ;
  output rst_r1_reg_1;
  output [0:0]S;
  output [1:0]\delay_cntr_reg[2] ;
  output lrdimm_cal_mode_reg;
  output lrdimm_cal_mode_reg_0;
  output \SYNC[5].sync_reg_reg[1]_17 ;
  output \rd_vref_value_reg[42] ;
  output [55:0]mcal_rd_vref_value;
  output \rd_vref_value_reg[43] ;
  output \rd_vref_value_reg[44] ;
  output \rd_vref_value_reg[45] ;
  output \rd_vref_value_reg[48] ;
  output [1:0]in0;
  output [1:0]\rsMask_reg[7][18] ;
  output [1:0]rst_r1_reg_2;
  output \wosp_reg[1] ;
  output [1:0]\wosp_reg[2]_rep ;
  output \wosp_reg[2]_rep_0 ;
  output \wosp_reg[1]_0 ;
  output \wosp_reg[2]_rep__2 ;
  output [1:0]\wosp_reg[2]_rep__1 ;
  output \wosp_reg[2]_rep__1_0 ;
  output \wosp_reg[2]_rep__1_1 ;
  output [1:0]\wosp_reg[2]_rep__1_2 ;
  output \wosp_reg[2]_rep__1_3 ;
  output \wosp_reg[2]_rep__1_4 ;
  output [1:0]\wosp_reg[2]_rep__1_5 ;
  output \wosp_reg[2]_rep__1_6 ;
  output \wosp_reg[2]_rep__1_7 ;
  output [1:0]\wosp_reg[2]_rep__1_8 ;
  output \wosp_reg[2]_rep__1_9 ;
  output \wosp_reg[2]_rep__1_10 ;
  output [1:0]\wosp_reg[2]_rep__2_0 ;
  output \wosp_reg[2]_rep__1_11 ;
  output \wosp_reg[2]_rep__2_1 ;
  output [1:0]\wosp_reg[2]_rep__2_2 ;
  output \wosp_reg[2]_rep__2_3 ;
  output \wosp_reg[2]_rep__2_4 ;
  output [1:0]\wosp_reg[2]_rep__2_5 ;
  output \wosp_reg[2]_rep__2_6 ;
  output \wosp_reg[2]_rep__2_7 ;
  output [1:0]\wosp_reg[2]_rep__2_8 ;
  output \wosp_reg[2]_rep__2_9 ;
  output \wosp_reg[2]_rep__2_10 ;
  output \wosp_reg[1]_1 ;
  output \wosp_reg[1]_2 ;
  output \wosp_reg[1]_3 ;
  output \wosp_reg[1]_4 ;
  output \wosp_reg[1]_5 ;
  output \wosp_reg[1]_6 ;
  output \wosp_reg[1]_7 ;
  output \wosp_reg[1]_8 ;
  output \wosp_reg[1]_9 ;
  output \wosp_reg[1]_10 ;
  output \wosp_reg[1]_11 ;
  output \wosp_reg[1]_12 ;
  output \wosp_reg[1]_13 ;
  output \wosp_reg[1]_14 ;
  output \wosp_reg[1]_15 ;
  output \wosp_reg[1]_16 ;
  output \wosp_reg[1]_17 ;
  output [1:0]\wosp_reg[2]_rep_1 ;
  output \wosp_reg[2]_rep_2 ;
  output \wosp_reg[1]_18 ;
  output \wosp_reg[2]_rep__3 ;
  output [1:0]\wosp_reg[2]_rep__2_11 ;
  output \wosp_reg[2]_rep__2_12 ;
  output \wosp_reg[2]_rep__2_13 ;
  output [1:0]\wosp_reg[2]_rep__2_14 ;
  output \wosp_reg[2]_rep__2_15 ;
  output \wosp_reg[2]_rep__2_16 ;
  output [1:0]\wosp_reg[2]_rep__2_17 ;
  output \wosp_reg[2]_rep__2_18 ;
  output \wosp_reg[2]_rep__2_19 ;
  output [1:0]\wosp_reg[2]_rep__2_20 ;
  output \wosp_reg[2]_rep__2_21 ;
  output \wosp_reg[2]_rep__2_22 ;
  output [1:0]\wosp_reg[2]_rep__2_23 ;
  output \wosp_reg[2]_rep__2_24 ;
  output \wosp_reg[2]_rep__2_25 ;
  output [1:0]\wosp_reg[2]_rep__2_26 ;
  output \wosp_reg[2]_rep__2_27 ;
  output \wosp_reg[2]_rep__2_28 ;
  output [1:0]\wosp_reg[2]_rep__2_29 ;
  output \wosp_reg[2]_rep__2_30 ;
  output \wosp_reg[2]_rep__2_31 ;
  output [1:0]\wosp_reg[2]_rep__2_32 ;
  output \wosp_reg[2]_rep__2_33 ;
  output \wosp_reg[2]_rep__2_34 ;
  output \wosp_reg[1]_19 ;
  output \wosp_reg[1]_20 ;
  output \wosp_reg[1]_21 ;
  output \wosp_reg[1]_22 ;
  output \wosp_reg[1]_23 ;
  output \wosp_reg[1]_24 ;
  output \wosp_reg[1]_25 ;
  output \wosp_reg[1]_26 ;
  output \wosp_reg[1]_27 ;
  output \wosp_reg[1]_28 ;
  output \wosp_reg[1]_29 ;
  output \wosp_reg[1]_30 ;
  output \wosp_reg[1]_31 ;
  output \wosp_reg[1]_32 ;
  output \wosp_reg[1]_33 ;
  output \wosp_reg[1]_34 ;
  output \wosp_reg[1]_35 ;
  output [1:0]\wosp_reg[2]_rep_3 ;
  output \wosp_reg[2]_rep_4 ;
  output \wosp_reg[1]_36 ;
  output \wosp_reg[2]_rep__3_0 ;
  output [1:0]\wosp_reg[2]_rep__3_1 ;
  output \wosp_reg[2]_rep__3_2 ;
  output \wosp_reg[2]_rep__3_3 ;
  output [1:0]\wosp_reg[2]_rep__3_4 ;
  output \wosp_reg[2]_rep__3_5 ;
  output \wosp_reg[2]_rep__3_6 ;
  output [1:0]\wosp_reg[2]_rep__3_7 ;
  output \wosp_reg[2]_rep__3_8 ;
  output \wosp_reg[2]_rep__3_9 ;
  output [1:0]\wosp_reg[2]_rep__3_10 ;
  output \wosp_reg[2]_rep__3_11 ;
  output \wosp_reg[2]_rep__3_12 ;
  output [1:0]\wosp_reg[2]_rep__3_13 ;
  output \wosp_reg[2]_rep__3_14 ;
  output \wosp_reg[2]_rep__3_15 ;
  output [1:0]\wosp_reg[2]_rep__3_16 ;
  output \wosp_reg[2]_rep__3_17 ;
  output \wosp_reg[2]_rep__3_18 ;
  output [1:0]\wosp_reg[2]_rep__3_19 ;
  output \wosp_reg[2]_rep__3_20 ;
  output \wosp_reg[2]_rep__3_21 ;
  output [1:0]\wosp_reg[2]_rep__3_22 ;
  output \wosp_reg[2]_rep__3_23 ;
  output \wosp_reg[2]_rep__3_24 ;
  output \wosp_reg[1]_37 ;
  output \wosp_reg[1]_38 ;
  output \wosp_reg[1]_39 ;
  output \wosp_reg[1]_40 ;
  output \wosp_reg[1]_41 ;
  output \wosp_reg[1]_42 ;
  output \wosp_reg[1]_43 ;
  output \wosp_reg[1]_44 ;
  output \wosp_reg[1]_45 ;
  output \wosp_reg[1]_46 ;
  output \wosp_reg[1]_47 ;
  output \wosp_reg[1]_48 ;
  output \wosp_reg[1]_49 ;
  output \wosp_reg[1]_50 ;
  output \wosp_reg[1]_51 ;
  output \wosp_reg[1]_52 ;
  output \wosp_reg[1]_53 ;
  output [1:0]\wosp_reg[2]_rep__0 ;
  output \wosp_reg[2]_rep__0_0 ;
  output \wosp_reg[1]_54 ;
  output \wosp_reg[2]_rep__4 ;
  output [1:0]\wosp_reg[2]_rep__3_25 ;
  output \wosp_reg[2]_rep__3_26 ;
  output \wosp_reg[2]_rep__3_27 ;
  output [1:0]\wosp_reg[2]_rep__3_28 ;
  output \wosp_reg[2]_rep__3_29 ;
  output \wosp_reg[2]_rep__3_30 ;
  output [1:0]\wosp_reg[2]_rep__3_31 ;
  output \wosp_reg[2]_rep__3_32 ;
  output \wosp_reg[2]_rep__3_33 ;
  output [1:0]\wosp_reg[2]_rep__4_0 ;
  output \wosp_reg[2]_rep__4_1 ;
  output \wosp_reg[2]_rep__4_2 ;
  output [1:0]\wosp_reg[2]_rep__4_3 ;
  output \wosp_reg[2]_rep__4_4 ;
  output \wosp_reg[2]_rep__4_5 ;
  output [1:0]\wosp_reg[2]_rep__4_6 ;
  output \wosp_reg[2]_rep__4_7 ;
  output \wosp_reg[2]_rep__4_8 ;
  output [1:0]\wosp_reg[2]_rep__4_9 ;
  output \wosp_reg[2]_rep__4_10 ;
  output \wosp_reg[2]_rep__4_11 ;
  output [1:0]\wosp_reg[2]_rep__4_12 ;
  output \wosp_reg[2]_rep__4_13 ;
  output \wosp_reg[2]_rep__4_14 ;
  output \wosp_reg[1]_55 ;
  output \wosp_reg[1]_56 ;
  output \wosp_reg[1]_57 ;
  output \wosp_reg[1]_58 ;
  output \wosp_reg[1]_59 ;
  output \wosp_reg[1]_60 ;
  output \wosp_reg[1]_61 ;
  output \wosp_reg[1]_62 ;
  output \wosp_reg[1]_63 ;
  output \wosp_reg[1]_64 ;
  output \wosp_reg[1]_65 ;
  output \wosp_reg[1]_66 ;
  output \wosp_reg[1]_67 ;
  output \wosp_reg[1]_68 ;
  output \wosp_reg[1]_69 ;
  output \wosp_reg[1]_70 ;
  output \wosp_reg[1]_71 ;
  output [1:0]\wosp_reg[2]_rep__0_1 ;
  output \wosp_reg[2]_rep__0_2 ;
  output \wosp_reg[1]_72 ;
  output \wosp_reg[2]_rep__5 ;
  output [1:0]\wosp_reg[2]_rep__4_15 ;
  output \wosp_reg[2]_rep__4_16 ;
  output \wosp_reg[2]_rep__4_17 ;
  output [1:0]\wosp_reg[2]_rep__4_18 ;
  output \wosp_reg[2]_rep__4_19 ;
  output \wosp_reg[2]_rep__4_20 ;
  output [1:0]\wosp_reg[2]_rep__4_21 ;
  output \wosp_reg[2]_rep__4_22 ;
  output \wosp_reg[2]_rep__4_23 ;
  output [1:0]\wosp_reg[2]_rep__4_24 ;
  output \wosp_reg[2]_rep__4_25 ;
  output \wosp_reg[2]_rep__4_26 ;
  output [1:0]\wosp_reg[2]_rep__4_27 ;
  output \wosp_reg[2]_rep__4_28 ;
  output \wosp_reg[2]_rep__4_29 ;
  output [1:0]\wosp_reg[2]_rep__4_30 ;
  output \wosp_reg[2]_rep__4_31 ;
  output \wosp_reg[2]_rep__4_32 ;
  output [1:0]\wosp_reg[2]_rep__5_0 ;
  output \wosp_reg[2]_rep__4_33 ;
  output \wosp_reg[2]_rep__5_1 ;
  output [1:0]\wosp_reg[2]_rep__5_2 ;
  output \wosp_reg[2]_rep__5_3 ;
  output \wosp_reg[2]_rep__5_4 ;
  output \wosp_reg[1]_73 ;
  output \wosp_reg[1]_74 ;
  output \wosp_reg[1]_75 ;
  output \wosp_reg[1]_76 ;
  output \wosp_reg[1]_77 ;
  output \wosp_reg[1]_78 ;
  output \wosp_reg[1]_79 ;
  output \wosp_reg[1]_80 ;
  output \wosp_reg[1]_81 ;
  output \wosp_reg[1]_82 ;
  output \wosp_reg[1]_83 ;
  output \wosp_reg[1]_84 ;
  output \wosp_reg[1]_85 ;
  output \wosp_reg[1]_86 ;
  output \wosp_reg[1]_87 ;
  output \wosp_reg[1]_88 ;
  output \wosp_reg[1]_89 ;
  output [1:0]\wosp_reg[2]_rep__0_3 ;
  output \wosp_reg[2]_rep__0_4 ;
  output \wosp_reg[1]_90 ;
  output \wosp_reg[2]_rep__5_5 ;
  output [1:0]\wosp_reg[2]_rep__5_6 ;
  output \wosp_reg[2]_rep__5_7 ;
  output \wosp_reg[2]_rep__5_8 ;
  output [1:0]\wosp_reg[2]_rep__5_9 ;
  output \wosp_reg[2]_rep__5_10 ;
  output \wosp_reg[2]_rep__5_11 ;
  output [1:0]\wosp_reg[2]_rep__5_12 ;
  output \wosp_reg[2]_rep__5_13 ;
  output \wosp_reg[2]_rep__5_14 ;
  output [1:0]\wosp_reg[2]_rep__5_15 ;
  output \wosp_reg[2]_rep__5_16 ;
  output \wosp_reg[2]_rep__5_17 ;
  output [1:0]\wosp_reg[2]_rep__5_18 ;
  output \wosp_reg[2]_rep__5_19 ;
  output \wosp_reg[2]_rep__5_20 ;
  output [1:0]\wosp_reg[2]_rep__5_21 ;
  output \wosp_reg[2]_rep__5_22 ;
  output \wosp_reg[2]_rep__5_23 ;
  output [1:0]\wosp_reg[2]_rep__5_24 ;
  output \wosp_reg[2]_rep__5_25 ;
  output \wosp_reg[2]_rep__5_26 ;
  output [1:0]\wosp_reg[2]_rep__5_27 ;
  output \wosp_reg[2]_rep__5_28 ;
  output \wosp_reg[2]_rep__5_29 ;
  output \wosp_reg[1]_91 ;
  output \wosp_reg[1]_92 ;
  output \wosp_reg[1]_93 ;
  output \wosp_reg[1]_94 ;
  output \wosp_reg[1]_95 ;
  output \wosp_reg[1]_96 ;
  output \wosp_reg[1]_97 ;
  output \wosp_reg[1]_98 ;
  output \wosp_reg[1]_99 ;
  output \wosp_reg[1]_100 ;
  output \wosp_reg[1]_101 ;
  output \wosp_reg[1]_102 ;
  output \wosp_reg[1]_103 ;
  output \wosp_reg[1]_104 ;
  output \wosp_reg[1]_105 ;
  output \wosp_reg[1]_106 ;
  output \wosp_reg[1]_107 ;
  output [1:0]\wosp_reg[2]_rep__1_12 ;
  output \wosp_reg[2]_rep__1_13 ;
  output \wosp_reg[1]_108 ;
  output \wosp_reg[2]_rep__6 ;
  output [1:0]\wosp_reg[2]_rep__5_30 ;
  output \wosp_reg[2]_rep__5_31 ;
  output \wosp_reg[2]_rep__5_32 ;
  output [1:0]\wosp_reg[2]_rep__6_0 ;
  output \wosp_reg[2]_rep__5_33 ;
  output \wosp_reg[2]_rep__6_1 ;
  output [1:0]\wosp_reg[2]_rep__6_2 ;
  output \wosp_reg[2]_rep__6_3 ;
  output \wosp_reg[2]_rep__6_4 ;
  output [1:0]\wosp_reg[2]_rep__6_5 ;
  output \wosp_reg[2]_rep__6_6 ;
  output \wosp_reg[2]_rep__6_7 ;
  output [1:0]\wosp_reg[2]_rep__6_8 ;
  output \wosp_reg[2]_rep__6_9 ;
  output \wosp_reg[2]_rep__6_10 ;
  output [1:0]\wosp_reg[2]_rep__6_11 ;
  output \wosp_reg[2]_rep__6_12 ;
  output \wosp_reg[2]_rep__6_13 ;
  output [1:0]\wosp_reg[2]_rep__6_14 ;
  output \wosp_reg[2]_rep__6_15 ;
  output \wosp_reg[2]_rep__6_16 ;
  output [1:0]\wosp_reg[2]_rep__6_17 ;
  output \wosp_reg[2]_rep__6_18 ;
  output \wosp_reg[2]_rep__6_19 ;
  output \wosp_reg[1]_109 ;
  output \wosp_reg[1]_110 ;
  output \wosp_reg[1]_111 ;
  output \wosp_reg[1]_112 ;
  output \wosp_reg[1]_113 ;
  output \wosp_reg[1]_114 ;
  output \wosp_reg[1]_115 ;
  output \wosp_reg[1]_116 ;
  output \wosp_reg[1]_117 ;
  output \wosp_reg[1]_118 ;
  output \wosp_reg[1]_119 ;
  output \wosp_reg[1]_120 ;
  output \wosp_reg[1]_121 ;
  output \wosp_reg[1]_122 ;
  output \wosp_reg[1]_123 ;
  output \wosp_reg[1]_124 ;
  output \wosp_reg[1]_125 ;
  output [1:0]\wosp_reg[2] ;
  output \wosp_reg[2]_0 ;
  output \wosp_reg[1]_126 ;
  output \wosp_reg[2]_rep__6_20 ;
  output [1:0]\wosp_reg[2]_rep__7 ;
  output \wosp_reg[2]_rep__7_0 ;
  output \wosp_reg[2]_rep__6_21 ;
  output [1:0]\wosp_reg[2]_rep__6_22 ;
  output \wosp_reg[2]_rep__6_23 ;
  output \wosp_reg[2]_rep__6_24 ;
  output [1:0]\wosp_reg[2]_rep__6_25 ;
  output \wosp_reg[2]_rep__6_26 ;
  output \wosp_reg[2]_rep__6_27 ;
  output [1:0]\wosp_reg[2]_rep__6_28 ;
  output \wosp_reg[2]_rep__6_29 ;
  output \wosp_reg[2]_rep__6_30 ;
  output [1:0]\wosp_reg[2]_rep__6_31 ;
  output \wosp_reg[2]_rep__6_32 ;
  output \wosp_reg[2]_rep__6_33 ;
  output [1:0]\wosp_reg[2]_rep__6_34 ;
  output \wosp_reg[2]_rep__6_35 ;
  output \wosp_reg[2]_rep__6_36 ;
  output [1:0]\wosp_reg[2]_rep__6_37 ;
  output \wosp_reg[2]_rep__6_38 ;
  output \wosp_reg[2]_rep__6_39 ;
  output [1:0]\wosp_reg[2]_rep__6_40 ;
  output \wosp_reg[2]_rep__6_41 ;
  output \wosp_reg[2]_rep__6_42 ;
  output \wosp_reg[1]_127 ;
  output \wosp_reg[1]_128 ;
  output \wosp_reg[1]_129 ;
  output \wosp_reg[1]_130 ;
  output \wosp_reg[1]_131 ;
  output \wosp_reg[1]_132 ;
  output \wosp_reg[1]_133 ;
  output \wosp_reg[1]_134 ;
  output \wosp_reg[1]_135 ;
  output \wosp_reg[1]_136 ;
  output \wosp_reg[1]_137 ;
  output \wosp_reg[1]_138 ;
  output \wosp_reg[1]_139 ;
  output \wosp_reg[1]_140 ;
  output \wosp_reg[1]_141 ;
  output \wosp_reg[1]_142 ;
  output [1:0]rst_r1_reg_3;
  output [1:0]rst_r1_reg_4;
  output [1:0]rst_r1_reg_5;
  output [1:0]rst_r1_reg_6;
  output [1:0]rst_r1_reg_7;
  output [1:0]rst_r1_reg_8;
  output [1:0]rst_r1_reg_9;
  output [1:0]rst_r1_reg_10;
  output [1:0]rst_r1_reg_11;
  output [1:0]rst_r1_reg_12;
  output [1:0]rst_r1_reg_13;
  output [1:0]rst_r1_reg_14;
  output [1:0]rst_r1_reg_15;
  output \uppCL0_reg[8]_3 ;
  output \uppCL0_reg[7]_0 ;
  output \uppCL0_reg[8]_4 ;
  output \uppCL0_reg[7]_1 ;
  output \uppCL0_reg[8]_5 ;
  output [3:0]rs2mask0__0;
  output \uppCL0_reg[9]_0 ;
  output \uppCL0_reg[7]_2 ;
  output \uppCL1_reg[8]_3 ;
  output \uppCL1_reg[7]_0 ;
  output \uppCL1_reg[8]_4 ;
  output \uppCL1_reg[7]_1 ;
  output \uppCL1_reg[8]_5 ;
  output \uppCL1_reg[7]_2 ;
  output \uppCL1_reg[7]_3 ;
  output \uppCL1_reg[9]_0 ;
  output \uppCL1_reg[7]_4 ;
  output \uppCL1_reg[7]_5 ;
  output \uppCL1_reg[8]_6 ;
  output \uppCL2_reg[8]_3 ;
  output \uppCL2_reg[7]_0 ;
  output \uppCL2_reg[8]_4 ;
  output \uppCL2_reg[7]_1 ;
  output \uppCL2_reg[8]_5 ;
  output \uppCL2_reg[7]_2 ;
  output \uppCL2_reg[7]_3 ;
  output \uppCL2_reg[9]_0 ;
  output \uppCL2_reg[7]_4 ;
  output \uppCL2_reg[7]_5 ;
  output \uppCL2_reg[8]_6 ;
  output \uppCL3_reg[8]_3 ;
  output \uppCL3_reg[7]_0 ;
  output \uppCL3_reg[8]_4 ;
  output \uppCL3_reg[7]_1 ;
  output \uppCL3_reg[8]_5 ;
  output \uppCL3_reg[7]_2 ;
  output \uppCL3_reg[7]_3 ;
  output \uppCL3_reg[9]_0 ;
  output \uppCL3_reg[7]_4 ;
  output \uppCL3_reg[7]_5 ;
  output \uppCL3_reg[8]_6 ;
  output \uppCL0_reg[44]_3 ;
  output \uppCL0_reg[43]_0 ;
  output \uppCL0_reg[44]_4 ;
  output \uppCL0_reg[43]_1 ;
  output \uppCL0_reg[44]_5 ;
  output [3:0]rs2mask0__0_0;
  output \uppCL0_reg[45]_1 ;
  output \uppCL0_reg[43]_2 ;
  output \uppCL1_reg[44]_3 ;
  output \uppCL1_reg[43]_0 ;
  output \uppCL1_reg[44]_4 ;
  output \uppCL1_reg[43]_1 ;
  output \uppCL1_reg[44]_5 ;
  output \uppCL1_reg[43]_2 ;
  output \uppCL1_reg[43]_3 ;
  output \uppCL1_reg[45]_1 ;
  output \uppCL1_reg[43]_4 ;
  output \uppCL1_reg[43]_5 ;
  output \uppCL1_reg[44]_6 ;
  output \uppCL2_reg[44]_3 ;
  output \uppCL2_reg[43]_0 ;
  output \uppCL2_reg[44]_4 ;
  output \uppCL2_reg[43]_1 ;
  output \uppCL2_reg[44]_5 ;
  output \uppCL2_reg[43]_2 ;
  output \uppCL2_reg[43]_3 ;
  output \uppCL2_reg[45]_1 ;
  output \uppCL2_reg[43]_4 ;
  output \uppCL2_reg[43]_5 ;
  output \uppCL2_reg[44]_6 ;
  output \uppCL3_reg[44]_3 ;
  output \uppCL3_reg[43]_0 ;
  output \uppCL3_reg[44]_4 ;
  output \uppCL3_reg[43]_1 ;
  output \uppCL3_reg[44]_5 ;
  output \uppCL3_reg[43]_2 ;
  output \uppCL3_reg[43]_3 ;
  output \uppCL3_reg[45]_1 ;
  output \uppCL3_reg[43]_4 ;
  output \uppCL3_reg[43]_5 ;
  output \uppCL3_reg[44]_6 ;
  output [9:0]\mcal_DQIn_byte_r1_reg[48] ;
  output [31:0]\io_read_data_reg[31] ;
  output [8:0]bisc_byte;
  output [7:0]\cal_RST_CKE_ODT_PAR_reg[7] ;
  output [1:0]\blk1.(null)[0].diff ;
  output [2:0]\uppCL0_reg[38]_3 ;
  output [4:0]rs2mask0;
  output \uppCL0_reg[38]_4 ;
  output \uppCL0_reg[37]_0 ;
  output \uppCL0_reg[38]_5 ;
  output \uppCL0_reg[37]_1 ;
  output \uppCL0_reg[38]_6 ;
  output \uppCL0_reg[39]_0 ;
  output \uppCL0_reg[37]_2 ;
  output \uppCL1_reg[37]_0 ;
  output \uppCL1_reg[37]_1 ;
  output [2:0]\uppCL1_reg[38]_3 ;
  output [0:0]\uppCL1_reg[37]_2 ;
  output \uppCL1_reg[38]_4 ;
  output \uppCL1_reg[37]_3 ;
  output \uppCL1_reg[38]_5 ;
  output \uppCL1_reg[37]_4 ;
  output \uppCL1_reg[38]_6 ;
  output \uppCL1_reg[37]_5 ;
  output \uppCL1_reg[37]_6 ;
  output \uppCL1_reg[39]_0 ;
  output \uppCL1_reg[37]_7 ;
  output \uppCL1_reg[37]_8 ;
  output \uppCL1_reg[38]_7 ;
  output \uppCL2_reg[37]_0 ;
  output \uppCL2_reg[37]_1 ;
  output [2:0]\uppCL2_reg[38]_3 ;
  output [0:0]\uppCL2_reg[37]_2 ;
  output \uppCL2_reg[38]_4 ;
  output \uppCL2_reg[37]_3 ;
  output \uppCL2_reg[38]_5 ;
  output \uppCL2_reg[37]_4 ;
  output \uppCL2_reg[38]_6 ;
  output \uppCL2_reg[37]_5 ;
  output \uppCL2_reg[37]_6 ;
  output \uppCL2_reg[39]_0 ;
  output \uppCL2_reg[37]_7 ;
  output \uppCL2_reg[37]_8 ;
  output \uppCL2_reg[38]_7 ;
  output \uppCL3_reg[37]_0 ;
  output \uppCL3_reg[37]_1 ;
  output [2:0]\uppCL3_reg[38]_3 ;
  output [0:0]\uppCL3_reg[37]_2 ;
  output \uppCL3_reg[38]_4 ;
  output \uppCL3_reg[37]_3 ;
  output \uppCL3_reg[38]_5 ;
  output \uppCL3_reg[37]_4 ;
  output \uppCL3_reg[38]_6 ;
  output \uppCL3_reg[37]_5 ;
  output \uppCL3_reg[37]_6 ;
  output \uppCL3_reg[39]_0 ;
  output \uppCL3_reg[37]_7 ;
  output \uppCL3_reg[37]_8 ;
  output \uppCL3_reg[38]_7 ;
  output [1:0]\blk1.(null)[0].diff_1 ;
  output [2:0]\uppCL0_reg[20]_3 ;
  output [4:0]rs2mask0_2;
  output \uppCL0_reg[20]_4 ;
  output \uppCL0_reg[19]_0 ;
  output \uppCL0_reg[20]_5 ;
  output \uppCL0_reg[19]_1 ;
  output \uppCL0_reg[20]_6 ;
  output \uppCL0_reg[21]_0 ;
  output \uppCL0_reg[19]_2 ;
  output \uppCL1_reg[19]_0 ;
  output \uppCL1_reg[19]_1 ;
  output [2:0]\uppCL1_reg[20]_3 ;
  output [0:0]\uppCL1_reg[19]_2 ;
  output \uppCL1_reg[20]_4 ;
  output \uppCL1_reg[19]_3 ;
  output \uppCL1_reg[20]_5 ;
  output \uppCL1_reg[19]_4 ;
  output \uppCL1_reg[20]_6 ;
  output \uppCL1_reg[19]_5 ;
  output \uppCL1_reg[19]_6 ;
  output \uppCL1_reg[21]_0 ;
  output \uppCL1_reg[19]_7 ;
  output \uppCL1_reg[19]_8 ;
  output \uppCL1_reg[20]_7 ;
  output \uppCL2_reg[19]_0 ;
  output \uppCL2_reg[19]_1 ;
  output [2:0]\uppCL2_reg[20]_3 ;
  output [0:0]\uppCL2_reg[19]_2 ;
  output \uppCL2_reg[20]_4 ;
  output \uppCL2_reg[19]_3 ;
  output \uppCL2_reg[20]_5 ;
  output \uppCL2_reg[19]_4 ;
  output \uppCL2_reg[20]_6 ;
  output \uppCL2_reg[19]_5 ;
  output \uppCL2_reg[19]_6 ;
  output \uppCL2_reg[21]_0 ;
  output \uppCL2_reg[19]_7 ;
  output \uppCL2_reg[19]_8 ;
  output \uppCL2_reg[20]_7 ;
  output \uppCL3_reg[19]_0 ;
  output \uppCL3_reg[19]_1 ;
  output [2:0]\uppCL3_reg[20]_3 ;
  output [0:0]\uppCL3_reg[19]_2 ;
  output \uppCL3_reg[20]_4 ;
  output \uppCL3_reg[19]_3 ;
  output \uppCL3_reg[20]_5 ;
  output \uppCL3_reg[19]_4 ;
  output \uppCL3_reg[20]_6 ;
  output \uppCL3_reg[19]_5 ;
  output \uppCL3_reg[19]_6 ;
  output \uppCL3_reg[21]_0 ;
  output \uppCL3_reg[19]_7 ;
  output \uppCL3_reg[19]_8 ;
  output \uppCL3_reg[20]_7 ;
  output [1:0]\blk1.(null)[0].diff_3 ;
  output [2:0]\uppCL0_reg[14]_3 ;
  output [4:0]rs2mask0_4;
  output \uppCL0_reg[14]_4 ;
  output \uppCL0_reg[13]_0 ;
  output \uppCL0_reg[14]_5 ;
  output \uppCL0_reg[13]_1 ;
  output \uppCL0_reg[14]_6 ;
  output \uppCL0_reg[15]_0 ;
  output \uppCL0_reg[13]_2 ;
  output \uppCL1_reg[13]_0 ;
  output \uppCL1_reg[13]_1 ;
  output [2:0]\uppCL1_reg[14]_3 ;
  output [0:0]\uppCL1_reg[13]_2 ;
  output \uppCL1_reg[14]_4 ;
  output \uppCL1_reg[13]_3 ;
  output \uppCL1_reg[14]_5 ;
  output \uppCL1_reg[13]_4 ;
  output \uppCL1_reg[14]_6 ;
  output \uppCL1_reg[13]_5 ;
  output \uppCL1_reg[13]_6 ;
  output \uppCL1_reg[15]_0 ;
  output \uppCL1_reg[13]_7 ;
  output \uppCL1_reg[13]_8 ;
  output \uppCL1_reg[14]_7 ;
  output \uppCL2_reg[13]_0 ;
  output \uppCL2_reg[13]_1 ;
  output [2:0]\uppCL2_reg[14]_3 ;
  output [0:0]\uppCL2_reg[13]_2 ;
  output \uppCL2_reg[14]_4 ;
  output \uppCL2_reg[13]_3 ;
  output \uppCL2_reg[14]_5 ;
  output \uppCL2_reg[13]_4 ;
  output \uppCL2_reg[14]_6 ;
  output \uppCL2_reg[13]_5 ;
  output \uppCL2_reg[13]_6 ;
  output \uppCL2_reg[15]_0 ;
  output \uppCL2_reg[13]_7 ;
  output \uppCL2_reg[13]_8 ;
  output \uppCL2_reg[14]_7 ;
  output \uppCL3_reg[13]_0 ;
  output \uppCL3_reg[13]_1 ;
  output [2:0]\uppCL3_reg[14]_3 ;
  output [0:0]\uppCL3_reg[13]_2 ;
  output \uppCL3_reg[14]_4 ;
  output \uppCL3_reg[13]_3 ;
  output \uppCL3_reg[14]_5 ;
  output \uppCL3_reg[13]_4 ;
  output \uppCL3_reg[14]_6 ;
  output \uppCL3_reg[13]_5 ;
  output \uppCL3_reg[13]_6 ;
  output \uppCL3_reg[15]_0 ;
  output \uppCL3_reg[13]_7 ;
  output \uppCL3_reg[13]_8 ;
  output \uppCL3_reg[14]_7 ;
  output [1:0]\blk1.(null)[0].diff_5 ;
  output [2:0]\uppCL0_reg[26]_3 ;
  output [4:0]rs2mask0_6;
  output \uppCL0_reg[26]_4 ;
  output \uppCL0_reg[25]_0 ;
  output \uppCL0_reg[26]_5 ;
  output \uppCL0_reg[25]_1 ;
  output \uppCL0_reg[26]_6 ;
  output \uppCL0_reg[27]_0 ;
  output \uppCL0_reg[25]_2 ;
  output \uppCL1_reg[25]_0 ;
  output \uppCL1_reg[25]_1 ;
  output [2:0]\uppCL1_reg[26]_3 ;
  output [0:0]\uppCL1_reg[25]_2 ;
  output \uppCL1_reg[26]_4 ;
  output \uppCL1_reg[25]_3 ;
  output \uppCL1_reg[26]_5 ;
  output \uppCL1_reg[25]_4 ;
  output \uppCL1_reg[26]_6 ;
  output \uppCL1_reg[25]_5 ;
  output \uppCL1_reg[25]_6 ;
  output \uppCL1_reg[27]_0 ;
  output \uppCL1_reg[25]_7 ;
  output \uppCL1_reg[25]_8 ;
  output \uppCL1_reg[26]_7 ;
  output \uppCL2_reg[25]_0 ;
  output \uppCL2_reg[25]_1 ;
  output [2:0]\uppCL2_reg[26]_3 ;
  output [0:0]\uppCL2_reg[25]_2 ;
  output \uppCL2_reg[26]_4 ;
  output \uppCL2_reg[25]_3 ;
  output \uppCL2_reg[26]_5 ;
  output \uppCL2_reg[25]_4 ;
  output \uppCL2_reg[26]_6 ;
  output \uppCL2_reg[25]_5 ;
  output \uppCL2_reg[25]_6 ;
  output \uppCL2_reg[27]_0 ;
  output \uppCL2_reg[25]_7 ;
  output \uppCL2_reg[25]_8 ;
  output \uppCL2_reg[26]_7 ;
  output \uppCL3_reg[25]_0 ;
  output \uppCL3_reg[25]_1 ;
  output [2:0]\uppCL3_reg[26]_3 ;
  output [0:0]\uppCL3_reg[25]_2 ;
  output \uppCL3_reg[26]_4 ;
  output \uppCL3_reg[25]_3 ;
  output \uppCL3_reg[26]_5 ;
  output \uppCL3_reg[25]_4 ;
  output \uppCL3_reg[26]_6 ;
  output \uppCL3_reg[25]_5 ;
  output \uppCL3_reg[25]_6 ;
  output \uppCL3_reg[27]_0 ;
  output \uppCL3_reg[25]_7 ;
  output \uppCL3_reg[25]_8 ;
  output \uppCL3_reg[26]_7 ;
  output [1:0]\blk1.(null)[0].diff_7 ;
  output [2:0]\lowCL0_reg[44]_3 ;
  output [4:0]rs2mask0_8;
  output \lowCL0_reg[44]_4 ;
  output \lowCL0_reg[43]_0 ;
  output \lowCL0_reg[44]_5 ;
  output \lowCL0_reg[43]_1 ;
  output \lowCL0_reg[44]_6 ;
  output \lowCL0_reg[45]_0 ;
  output \lowCL0_reg[43]_2 ;
  output \lowCL1_reg[43]_0 ;
  output \lowCL1_reg[43]_1 ;
  output [2:0]\lowCL1_reg[44]_3 ;
  output [0:0]\lowCL1_reg[43]_2 ;
  output \lowCL1_reg[44]_4 ;
  output \lowCL1_reg[43]_3 ;
  output \lowCL1_reg[44]_5 ;
  output \lowCL1_reg[43]_4 ;
  output \lowCL1_reg[44]_6 ;
  output \lowCL1_reg[43]_5 ;
  output \lowCL1_reg[43]_6 ;
  output \lowCL1_reg[45]_0 ;
  output \lowCL1_reg[43]_7 ;
  output \lowCL1_reg[43]_8 ;
  output \lowCL1_reg[44]_7 ;
  output \lowCL2_reg[43]_0 ;
  output \lowCL2_reg[43]_1 ;
  output [2:0]\lowCL2_reg[44]_3 ;
  output [0:0]\lowCL2_reg[43]_2 ;
  output \lowCL2_reg[44]_4 ;
  output \lowCL2_reg[43]_3 ;
  output \lowCL2_reg[44]_5 ;
  output \lowCL2_reg[43]_4 ;
  output \lowCL2_reg[44]_6 ;
  output \lowCL2_reg[43]_5 ;
  output \lowCL2_reg[43]_6 ;
  output \lowCL2_reg[45]_0 ;
  output \lowCL2_reg[43]_7 ;
  output \lowCL2_reg[43]_8 ;
  output \lowCL2_reg[44]_7 ;
  output \lowCL3_reg[43]_0 ;
  output \lowCL3_reg[43]_1 ;
  output [2:0]\lowCL3_reg[44]_3 ;
  output [0:0]\lowCL3_reg[43]_2 ;
  output \lowCL3_reg[44]_4 ;
  output \lowCL3_reg[43]_3 ;
  output \lowCL3_reg[44]_5 ;
  output \lowCL3_reg[43]_4 ;
  output \lowCL3_reg[44]_6 ;
  output \lowCL3_reg[43]_5 ;
  output \lowCL3_reg[43]_6 ;
  output \lowCL3_reg[45]_0 ;
  output \lowCL3_reg[43]_7 ;
  output \lowCL3_reg[43]_8 ;
  output \lowCL3_reg[44]_7 ;
  output [1:0]\blk1.(null)[0].diff_9 ;
  output [2:0]\uppCL0_reg[2]_3 ;
  output [4:0]rs2mask0_10;
  output \uppCL0_reg[2]_4 ;
  output \uppCL0_reg[1]_0 ;
  output \uppCL0_reg[2]_5 ;
  output \uppCL0_reg[1]_1 ;
  output \uppCL0_reg[2]_6 ;
  output \uppCL0_reg[3]_0 ;
  output \uppCL0_reg[1]_2 ;
  output \uppCL1_reg[1]_0 ;
  output \uppCL1_reg[1]_1 ;
  output [2:0]\uppCL1_reg[2]_3 ;
  output [0:0]\uppCL1_reg[1]_2 ;
  output \uppCL1_reg[2]_4 ;
  output \uppCL1_reg[1]_3 ;
  output \uppCL1_reg[2]_5 ;
  output \uppCL1_reg[1]_4 ;
  output \uppCL1_reg[2]_6 ;
  output \uppCL1_reg[1]_5 ;
  output \uppCL1_reg[1]_6 ;
  output \uppCL1_reg[3]_0 ;
  output \uppCL1_reg[1]_7 ;
  output \uppCL1_reg[1]_8 ;
  output \uppCL1_reg[2]_7 ;
  output \uppCL2_reg[1]_0 ;
  output \uppCL2_reg[1]_1 ;
  output [2:0]\uppCL2_reg[2]_3 ;
  output [0:0]\uppCL2_reg[1]_2 ;
  output \uppCL2_reg[2]_4 ;
  output \uppCL2_reg[1]_3 ;
  output \uppCL2_reg[2]_5 ;
  output \uppCL2_reg[1]_4 ;
  output \uppCL2_reg[2]_6 ;
  output \uppCL2_reg[1]_5 ;
  output \uppCL2_reg[1]_6 ;
  output \uppCL2_reg[3]_0 ;
  output \uppCL2_reg[1]_7 ;
  output \uppCL2_reg[1]_8 ;
  output \uppCL2_reg[2]_7 ;
  output \uppCL3_reg[1]_0 ;
  output \uppCL3_reg[1]_1 ;
  output [2:0]\uppCL3_reg[2]_3 ;
  output [0:0]\uppCL3_reg[1]_2 ;
  output \uppCL3_reg[2]_4 ;
  output \uppCL3_reg[1]_3 ;
  output \uppCL3_reg[2]_5 ;
  output \uppCL3_reg[1]_4 ;
  output \uppCL3_reg[2]_6 ;
  output \uppCL3_reg[1]_5 ;
  output \uppCL3_reg[1]_6 ;
  output \uppCL3_reg[3]_0 ;
  output \uppCL3_reg[1]_7 ;
  output \uppCL3_reg[1]_8 ;
  output \uppCL3_reg[2]_7 ;
  output [1:0]\blk1.(null)[0].diff_11 ;
  output [2:0]\uppCL0_reg[32]_3 ;
  output [4:0]rs2mask0_12;
  output \uppCL0_reg[32]_4 ;
  output \uppCL0_reg[31]_0 ;
  output \uppCL0_reg[32]_5 ;
  output \uppCL0_reg[31]_1 ;
  output \uppCL0_reg[32]_6 ;
  output \uppCL0_reg[33]_0 ;
  output \uppCL0_reg[31]_2 ;
  output \uppCL1_reg[31]_0 ;
  output \uppCL1_reg[31]_1 ;
  output [2:0]\uppCL1_reg[32]_3 ;
  output [0:0]\uppCL1_reg[31]_2 ;
  output \uppCL1_reg[32]_4 ;
  output \uppCL1_reg[31]_3 ;
  output \uppCL1_reg[32]_5 ;
  output \uppCL1_reg[31]_4 ;
  output \uppCL1_reg[32]_6 ;
  output \uppCL1_reg[31]_5 ;
  output \uppCL1_reg[31]_6 ;
  output \uppCL1_reg[33]_0 ;
  output \uppCL1_reg[31]_7 ;
  output \uppCL1_reg[31]_8 ;
  output \uppCL1_reg[32]_7 ;
  output \uppCL2_reg[31]_0 ;
  output \uppCL2_reg[31]_1 ;
  output [2:0]\uppCL2_reg[32]_3 ;
  output [0:0]\uppCL2_reg[31]_2 ;
  output \uppCL2_reg[32]_4 ;
  output \uppCL2_reg[31]_3 ;
  output \uppCL2_reg[32]_5 ;
  output \uppCL2_reg[31]_4 ;
  output \uppCL2_reg[32]_6 ;
  output \uppCL2_reg[31]_5 ;
  output \uppCL2_reg[31]_6 ;
  output \uppCL2_reg[33]_0 ;
  output \uppCL2_reg[31]_7 ;
  output \uppCL2_reg[31]_8 ;
  output \uppCL2_reg[32]_7 ;
  output \uppCL3_reg[31]_0 ;
  output \uppCL3_reg[31]_1 ;
  output [2:0]\uppCL3_reg[32]_3 ;
  output [0:0]\uppCL3_reg[31]_2 ;
  output \uppCL3_reg[32]_4 ;
  output \uppCL3_reg[31]_3 ;
  output \uppCL3_reg[32]_5 ;
  output \uppCL3_reg[31]_4 ;
  output \uppCL3_reg[32]_6 ;
  output \uppCL3_reg[31]_5 ;
  output \uppCL3_reg[31]_6 ;
  output \uppCL3_reg[33]_0 ;
  output \uppCL3_reg[31]_7 ;
  output \uppCL3_reg[31]_8 ;
  output \uppCL3_reg[32]_7 ;
  output [1:0]\blk1.(null)[0].diff_13 ;
  output [2:0]\lowCL0_reg[32]_3 ;
  output [4:0]rs2mask0_14;
  output \lowCL0_reg[32]_4 ;
  output \lowCL0_reg[31]_0 ;
  output \lowCL0_reg[32]_5 ;
  output \lowCL0_reg[31]_1 ;
  output \lowCL0_reg[32]_6 ;
  output \lowCL0_reg[33]_0 ;
  output \lowCL0_reg[31]_2 ;
  output \lowCL1_reg[31]_0 ;
  output \lowCL1_reg[31]_1 ;
  output [2:0]\lowCL1_reg[32]_3 ;
  output [0:0]\lowCL1_reg[31]_2 ;
  output \lowCL1_reg[32]_4 ;
  output \lowCL1_reg[31]_3 ;
  output \lowCL1_reg[32]_5 ;
  output \lowCL1_reg[31]_4 ;
  output \lowCL1_reg[32]_6 ;
  output \lowCL1_reg[31]_5 ;
  output \lowCL1_reg[31]_6 ;
  output \lowCL1_reg[33]_0 ;
  output \lowCL1_reg[31]_7 ;
  output \lowCL1_reg[31]_8 ;
  output \lowCL1_reg[32]_7 ;
  output \lowCL2_reg[31]_0 ;
  output \lowCL2_reg[31]_1 ;
  output [2:0]\lowCL2_reg[32]_3 ;
  output [0:0]\lowCL2_reg[31]_2 ;
  output \lowCL2_reg[32]_4 ;
  output \lowCL2_reg[31]_3 ;
  output \lowCL2_reg[32]_5 ;
  output \lowCL2_reg[31]_4 ;
  output \lowCL2_reg[32]_6 ;
  output \lowCL2_reg[31]_5 ;
  output \lowCL2_reg[31]_6 ;
  output \lowCL2_reg[33]_0 ;
  output \lowCL2_reg[31]_7 ;
  output \lowCL2_reg[31]_8 ;
  output \lowCL2_reg[32]_7 ;
  output \lowCL3_reg[31]_0 ;
  output \lowCL3_reg[31]_1 ;
  output [2:0]\lowCL3_reg[32]_3 ;
  output [0:0]\lowCL3_reg[31]_2 ;
  output \lowCL3_reg[32]_4 ;
  output \lowCL3_reg[31]_3 ;
  output \lowCL3_reg[32]_5 ;
  output \lowCL3_reg[31]_4 ;
  output \lowCL3_reg[32]_6 ;
  output \lowCL3_reg[31]_5 ;
  output \lowCL3_reg[31]_6 ;
  output \lowCL3_reg[33]_0 ;
  output \lowCL3_reg[31]_7 ;
  output \lowCL3_reg[31]_8 ;
  output \lowCL3_reg[32]_7 ;
  output [1:0]\blk1.(null)[0].diff_15 ;
  output [2:0]\lowCL0_reg[26]_3 ;
  output [4:0]rs2mask0_16;
  output \lowCL0_reg[26]_4 ;
  output \lowCL0_reg[25]_0 ;
  output \lowCL0_reg[26]_5 ;
  output \lowCL0_reg[25]_1 ;
  output \lowCL0_reg[26]_6 ;
  output \lowCL0_reg[27]_0 ;
  output \lowCL0_reg[25]_2 ;
  output \lowCL1_reg[25]_0 ;
  output \lowCL1_reg[25]_1 ;
  output [2:0]\lowCL1_reg[26]_3 ;
  output [0:0]\lowCL1_reg[25]_2 ;
  output \lowCL1_reg[26]_4 ;
  output \lowCL1_reg[25]_3 ;
  output \lowCL1_reg[26]_5 ;
  output \lowCL1_reg[25]_4 ;
  output \lowCL1_reg[26]_6 ;
  output \lowCL1_reg[25]_5 ;
  output \lowCL1_reg[25]_6 ;
  output \lowCL1_reg[27]_0 ;
  output \lowCL1_reg[25]_7 ;
  output \lowCL1_reg[25]_8 ;
  output \lowCL1_reg[26]_7 ;
  output \lowCL2_reg[25]_0 ;
  output \lowCL2_reg[25]_1 ;
  output [2:0]\lowCL2_reg[26]_3 ;
  output [0:0]\lowCL2_reg[25]_2 ;
  output \lowCL2_reg[26]_4 ;
  output \lowCL2_reg[25]_3 ;
  output \lowCL2_reg[26]_5 ;
  output \lowCL2_reg[25]_4 ;
  output \lowCL2_reg[26]_6 ;
  output \lowCL2_reg[25]_5 ;
  output \lowCL2_reg[25]_6 ;
  output \lowCL2_reg[27]_0 ;
  output \lowCL2_reg[25]_7 ;
  output \lowCL2_reg[25]_8 ;
  output \lowCL2_reg[26]_7 ;
  output \lowCL3_reg[25]_0 ;
  output \lowCL3_reg[25]_1 ;
  output [2:0]\lowCL3_reg[26]_3 ;
  output [0:0]\lowCL3_reg[25]_2 ;
  output \lowCL3_reg[26]_4 ;
  output \lowCL3_reg[25]_3 ;
  output \lowCL3_reg[26]_5 ;
  output \lowCL3_reg[25]_4 ;
  output \lowCL3_reg[26]_6 ;
  output \lowCL3_reg[25]_5 ;
  output \lowCL3_reg[25]_6 ;
  output \lowCL3_reg[27]_0 ;
  output \lowCL3_reg[25]_7 ;
  output \lowCL3_reg[25]_8 ;
  output \lowCL3_reg[26]_7 ;
  output [1:0]\blk1.(null)[0].diff_17 ;
  output [2:0]\lowCL0_reg[38]_3 ;
  output [4:0]rs2mask0_18;
  output \lowCL0_reg[38]_4 ;
  output \lowCL0_reg[37]_0 ;
  output \lowCL0_reg[38]_5 ;
  output \lowCL0_reg[37]_1 ;
  output \lowCL0_reg[38]_6 ;
  output \lowCL0_reg[39]_0 ;
  output \lowCL0_reg[37]_2 ;
  output \lowCL1_reg[37]_0 ;
  output \lowCL1_reg[37]_1 ;
  output [2:0]\lowCL1_reg[38]_3 ;
  output [0:0]\lowCL1_reg[37]_2 ;
  output \lowCL1_reg[38]_4 ;
  output \lowCL1_reg[37]_3 ;
  output \lowCL1_reg[38]_5 ;
  output \lowCL1_reg[37]_4 ;
  output \lowCL1_reg[38]_6 ;
  output \lowCL1_reg[37]_5 ;
  output \lowCL1_reg[37]_6 ;
  output \lowCL1_reg[39]_0 ;
  output \lowCL1_reg[37]_7 ;
  output \lowCL1_reg[37]_8 ;
  output \lowCL1_reg[38]_7 ;
  output \lowCL2_reg[37]_0 ;
  output \lowCL2_reg[37]_1 ;
  output [2:0]\lowCL2_reg[38]_3 ;
  output [0:0]\lowCL2_reg[37]_2 ;
  output \lowCL2_reg[38]_4 ;
  output \lowCL2_reg[37]_3 ;
  output \lowCL2_reg[38]_5 ;
  output \lowCL2_reg[37]_4 ;
  output \lowCL2_reg[38]_6 ;
  output \lowCL2_reg[37]_5 ;
  output \lowCL2_reg[37]_6 ;
  output \lowCL2_reg[39]_0 ;
  output \lowCL2_reg[37]_7 ;
  output \lowCL2_reg[37]_8 ;
  output \lowCL2_reg[38]_7 ;
  output \lowCL3_reg[37]_0 ;
  output \lowCL3_reg[37]_1 ;
  output [2:0]\lowCL3_reg[38]_3 ;
  output [0:0]\lowCL3_reg[37]_2 ;
  output \lowCL3_reg[38]_4 ;
  output \lowCL3_reg[37]_3 ;
  output \lowCL3_reg[38]_5 ;
  output \lowCL3_reg[37]_4 ;
  output \lowCL3_reg[38]_6 ;
  output \lowCL3_reg[37]_5 ;
  output \lowCL3_reg[37]_6 ;
  output \lowCL3_reg[39]_0 ;
  output \lowCL3_reg[37]_7 ;
  output \lowCL3_reg[37]_8 ;
  output \lowCL3_reg[38]_7 ;
  output [1:0]\blk1.(null)[0].diff_19 ;
  output [2:0]\lowCL0_reg[20]_3 ;
  output [4:0]rs2mask0_20;
  output \lowCL0_reg[20]_4 ;
  output \lowCL0_reg[19]_0 ;
  output \lowCL0_reg[20]_5 ;
  output \lowCL0_reg[19]_1 ;
  output \lowCL0_reg[20]_6 ;
  output \lowCL0_reg[21]_0 ;
  output \lowCL0_reg[19]_2 ;
  output \lowCL1_reg[19]_0 ;
  output \lowCL1_reg[19]_1 ;
  output [2:0]\lowCL1_reg[20]_3 ;
  output [0:0]\lowCL1_reg[19]_2 ;
  output \lowCL1_reg[20]_4 ;
  output \lowCL1_reg[19]_3 ;
  output \lowCL1_reg[20]_5 ;
  output \lowCL1_reg[19]_4 ;
  output \lowCL1_reg[20]_6 ;
  output \lowCL1_reg[19]_5 ;
  output \lowCL1_reg[19]_6 ;
  output \lowCL1_reg[21]_0 ;
  output \lowCL1_reg[19]_7 ;
  output \lowCL1_reg[19]_8 ;
  output \lowCL1_reg[20]_7 ;
  output \lowCL2_reg[19]_0 ;
  output \lowCL2_reg[19]_1 ;
  output [2:0]\lowCL2_reg[20]_3 ;
  output [0:0]\lowCL2_reg[19]_2 ;
  output \lowCL2_reg[20]_4 ;
  output \lowCL2_reg[19]_3 ;
  output \lowCL2_reg[20]_5 ;
  output \lowCL2_reg[19]_4 ;
  output \lowCL2_reg[20]_6 ;
  output \lowCL2_reg[19]_5 ;
  output \lowCL2_reg[19]_6 ;
  output \lowCL2_reg[21]_0 ;
  output \lowCL2_reg[19]_7 ;
  output \lowCL2_reg[19]_8 ;
  output \lowCL2_reg[20]_7 ;
  output \lowCL3_reg[19]_0 ;
  output \lowCL3_reg[19]_1 ;
  output [2:0]\lowCL3_reg[20]_3 ;
  output [0:0]\lowCL3_reg[19]_2 ;
  output \lowCL3_reg[20]_4 ;
  output \lowCL3_reg[19]_3 ;
  output \lowCL3_reg[20]_5 ;
  output \lowCL3_reg[19]_4 ;
  output \lowCL3_reg[20]_6 ;
  output \lowCL3_reg[19]_5 ;
  output \lowCL3_reg[19]_6 ;
  output \lowCL3_reg[21]_0 ;
  output \lowCL3_reg[19]_7 ;
  output \lowCL3_reg[19]_8 ;
  output \lowCL3_reg[20]_7 ;
  output [1:0]\blk1.(null)[0].diff_21 ;
  output [2:0]\lowCL0_reg[14]_3 ;
  output [4:0]rs2mask0_22;
  output \lowCL0_reg[14]_4 ;
  output \lowCL0_reg[13]_0 ;
  output \lowCL0_reg[14]_5 ;
  output \lowCL0_reg[13]_1 ;
  output \lowCL0_reg[14]_6 ;
  output \lowCL0_reg[15]_0 ;
  output \lowCL0_reg[13]_2 ;
  output \lowCL1_reg[13]_0 ;
  output \lowCL1_reg[13]_1 ;
  output [2:0]\lowCL1_reg[14]_3 ;
  output [0:0]\lowCL1_reg[13]_2 ;
  output \lowCL1_reg[14]_4 ;
  output \lowCL1_reg[13]_3 ;
  output \lowCL1_reg[14]_5 ;
  output \lowCL1_reg[13]_4 ;
  output \lowCL1_reg[14]_6 ;
  output \lowCL1_reg[13]_5 ;
  output \lowCL1_reg[13]_6 ;
  output \lowCL1_reg[15]_0 ;
  output \lowCL1_reg[13]_7 ;
  output \lowCL1_reg[13]_8 ;
  output \lowCL1_reg[14]_7 ;
  output \lowCL2_reg[13]_0 ;
  output \lowCL2_reg[13]_1 ;
  output [2:0]\lowCL2_reg[14]_3 ;
  output [0:0]\lowCL2_reg[13]_2 ;
  output \lowCL2_reg[14]_4 ;
  output \lowCL2_reg[13]_3 ;
  output \lowCL2_reg[14]_5 ;
  output \lowCL2_reg[13]_4 ;
  output \lowCL2_reg[14]_6 ;
  output \lowCL2_reg[13]_5 ;
  output \lowCL2_reg[13]_6 ;
  output \lowCL2_reg[15]_0 ;
  output \lowCL2_reg[13]_7 ;
  output \lowCL2_reg[13]_8 ;
  output \lowCL2_reg[14]_7 ;
  output \lowCL3_reg[13]_0 ;
  output \lowCL3_reg[13]_1 ;
  output [2:0]\lowCL3_reg[14]_3 ;
  output [0:0]\lowCL3_reg[13]_2 ;
  output \lowCL3_reg[14]_4 ;
  output \lowCL3_reg[13]_3 ;
  output \lowCL3_reg[14]_5 ;
  output \lowCL3_reg[13]_4 ;
  output \lowCL3_reg[14]_6 ;
  output \lowCL3_reg[13]_5 ;
  output \lowCL3_reg[13]_6 ;
  output \lowCL3_reg[15]_0 ;
  output \lowCL3_reg[13]_7 ;
  output \lowCL3_reg[13]_8 ;
  output \lowCL3_reg[14]_7 ;
  output [1:0]\blk1.(null)[0].diff_23 ;
  output [2:0]\lowCL0_reg[8]_3 ;
  output [4:0]rs2mask0_24;
  output \lowCL0_reg[8]_4 ;
  output \lowCL0_reg[7]_0 ;
  output \lowCL0_reg[8]_5 ;
  output \lowCL0_reg[7]_1 ;
  output \lowCL0_reg[8]_6 ;
  output \lowCL0_reg[9]_0 ;
  output \lowCL0_reg[7]_2 ;
  output \lowCL1_reg[7]_0 ;
  output \lowCL1_reg[7]_1 ;
  output [2:0]\lowCL1_reg[8]_3 ;
  output [0:0]\lowCL1_reg[7]_2 ;
  output \lowCL1_reg[8]_4 ;
  output \lowCL1_reg[7]_3 ;
  output \lowCL1_reg[8]_5 ;
  output \lowCL1_reg[7]_4 ;
  output \lowCL1_reg[8]_6 ;
  output \lowCL1_reg[7]_5 ;
  output \lowCL1_reg[7]_6 ;
  output \lowCL1_reg[9]_0 ;
  output \lowCL1_reg[7]_7 ;
  output \lowCL1_reg[7]_8 ;
  output \lowCL1_reg[8]_7 ;
  output \lowCL2_reg[7]_0 ;
  output \lowCL2_reg[7]_1 ;
  output [2:0]\lowCL2_reg[8]_3 ;
  output [0:0]\lowCL2_reg[7]_2 ;
  output \lowCL2_reg[8]_4 ;
  output \lowCL2_reg[7]_3 ;
  output \lowCL2_reg[8]_5 ;
  output \lowCL2_reg[7]_4 ;
  output \lowCL2_reg[8]_6 ;
  output \lowCL2_reg[7]_5 ;
  output \lowCL2_reg[7]_6 ;
  output \lowCL2_reg[9]_0 ;
  output \lowCL2_reg[7]_7 ;
  output \lowCL2_reg[7]_8 ;
  output \lowCL2_reg[8]_7 ;
  output \lowCL3_reg[7]_0 ;
  output \lowCL3_reg[7]_1 ;
  output [2:0]\lowCL3_reg[8]_3 ;
  output [0:0]\lowCL3_reg[7]_2 ;
  output \lowCL3_reg[8]_4 ;
  output \lowCL3_reg[7]_3 ;
  output \lowCL3_reg[8]_5 ;
  output \lowCL3_reg[7]_4 ;
  output \lowCL3_reg[8]_6 ;
  output \lowCL3_reg[7]_5 ;
  output \lowCL3_reg[7]_6 ;
  output \lowCL3_reg[9]_0 ;
  output \lowCL3_reg[7]_7 ;
  output \lowCL3_reg[7]_8 ;
  output \lowCL3_reg[8]_7 ;
  output [1:0]\blk1.(null)[0].diff_25 ;
  output [2:0]\lowCL0_reg[2]_3 ;
  output [4:0]rs2mask0_26;
  output \lowCL0_reg[2]_4 ;
  output \lowCL0_reg[1]_0 ;
  output \lowCL0_reg[2]_5 ;
  output \lowCL0_reg[1]_1 ;
  output \lowCL0_reg[2]_6 ;
  output \lowCL0_reg[3]_0 ;
  output \lowCL0_reg[1]_2 ;
  output \lowCL1_reg[1]_0 ;
  output \lowCL1_reg[1]_1 ;
  output [2:0]\lowCL1_reg[2]_3 ;
  output [0:0]\lowCL1_reg[1]_2 ;
  output \lowCL1_reg[2]_4 ;
  output \lowCL1_reg[1]_3 ;
  output \lowCL1_reg[2]_5 ;
  output \lowCL1_reg[1]_4 ;
  output \lowCL1_reg[2]_6 ;
  output \lowCL1_reg[1]_5 ;
  output \lowCL1_reg[1]_6 ;
  output \lowCL1_reg[3]_0 ;
  output \lowCL1_reg[1]_7 ;
  output \lowCL1_reg[1]_8 ;
  output \lowCL1_reg[2]_7 ;
  output \lowCL2_reg[1]_0 ;
  output \lowCL2_reg[1]_1 ;
  output [2:0]\lowCL2_reg[2]_3 ;
  output [0:0]\lowCL2_reg[1]_2 ;
  output \lowCL2_reg[2]_4 ;
  output \lowCL2_reg[1]_3 ;
  output \lowCL2_reg[2]_5 ;
  output \lowCL2_reg[1]_4 ;
  output \lowCL2_reg[2]_6 ;
  output \lowCL2_reg[1]_5 ;
  output \lowCL2_reg[1]_6 ;
  output \lowCL2_reg[3]_0 ;
  output \lowCL2_reg[1]_7 ;
  output \lowCL2_reg[1]_8 ;
  output \lowCL2_reg[2]_7 ;
  output \lowCL3_reg[1]_0 ;
  output \lowCL3_reg[1]_1 ;
  output [2:0]\lowCL3_reg[2]_3 ;
  output [0:0]\lowCL3_reg[1]_2 ;
  output \lowCL3_reg[2]_4 ;
  output \lowCL3_reg[1]_3 ;
  output \lowCL3_reg[2]_5 ;
  output \lowCL3_reg[1]_4 ;
  output \lowCL3_reg[2]_6 ;
  output \lowCL3_reg[1]_5 ;
  output \lowCL3_reg[1]_6 ;
  output \lowCL3_reg[3]_0 ;
  output \lowCL3_reg[1]_7 ;
  output \lowCL3_reg[1]_8 ;
  output \lowCL3_reg[2]_7 ;
  output read_lat_shift_cal_dq_valid_nxt;
  output [1:0]\blk1.(null)[0].diff_27 ;
  output [2:0]\uppCL0_reg[8]_6 ;
  output \uppCL1_reg[7]_6 ;
  output \uppCL1_reg[7]_7 ;
  output [2:0]\uppCL1_reg[8]_7 ;
  output \uppCL2_reg[7]_6 ;
  output \uppCL2_reg[7]_7 ;
  output [2:0]\uppCL2_reg[8]_7 ;
  output \uppCL3_reg[7]_6 ;
  output \uppCL3_reg[7]_7 ;
  output [2:0]\uppCL3_reg[8]_7 ;
  output [1:0]\blk1.(null)[0].diff_28 ;
  output [2:0]\uppCL0_reg[44]_6 ;
  output \uppCL1_reg[43]_6 ;
  output \uppCL1_reg[43]_7 ;
  output [2:0]\uppCL1_reg[44]_7 ;
  output \uppCL2_reg[43]_6 ;
  output \uppCL2_reg[43]_7 ;
  output [2:0]\uppCL2_reg[44]_7 ;
  output \uppCL3_reg[43]_6 ;
  output \uppCL3_reg[43]_7 ;
  output [2:0]\uppCL3_reg[44]_7 ;
  output [53:0]\cplx_error_accum_reg[63] ;
  input [36:0]out;
  input \SYNC[0].sync_reg_reg[1]_1 ;
  input ena;
  input [20:0]io_address;
  input [0:0]SR;
  input io_addr_strobe_r1_reg;
  input calDone_reg_14;
  input [31:0]io_write_data;
  input lrdimm_cmp_clr;
  input lrdimm_cal_mode_reg_1;
  input p_52_in;
  input clear_gt_data_ready_flag;
  input gt_data_ready_flag_nxt;
  input ub_ready_reg_0;
  input [0:0]E;
  input wren_reg;
  input \clb2phy_wrcs0_low_reg[31] ;
  input [7:0]O;
  input [7:0]\cal_timer_reg[15] ;
  input [7:0]\cal_timer_reg[23] ;
  input [7:0]\cal_timer_reg[31] ;
  input stop_gate_tracking_ack_reg_0;
  input cnt_clr_reg_0;
  input a_b_cmd_sel_start_reg_0;
  input lrdimm_cmp_en_reg_0;
  input cal_seq_cnt_gt_0_reg;
  input [0:0]xsdb_wr_en_reg;
  input \cal_oe_dis_low_reg[7] ;
  input \cal_oe_dis_upp_reg[7] ;
  input pllGate;
  input \calSt_reg[0]_0 ;
  input [1:0]Q;
  input [6:0]mc_BA;
  input mc_CKE7;
  input [1:0]mc_CKE;
  input [0:0]mc_ODT;
  input mc_ODT7;
  input winAct;
  input [0:0]mc_CS_n;
  input mc_CS_n7;
  input [0:0]calDone_gated_reg;
  input mcRdCAS;
  input mcCasSlot2;
  input [4:0]\mcal_ADR_dly_reg[0][135] ;
  input [35:0]mc_ADR;
  input [4:0]\mcal_ADR_dly_reg[0][128] ;
  input [2:0]mc_BG;
  input [0:0]p_1_in;
  input \mcal_PAR_dly_reg[0][5] ;
  input \mcal_PAR_dly_reg[0][3] ;
  input \mcal_PAR_dly_reg[0][1] ;
  input \mcal_PAR_dly_reg[0][7] ;
  input \mcal_PAR_dly_reg[0][0] ;
  input [575:0]\dReg_reg[15] ;
  input mcWrCAS;
  input \wrQ_reg[1][0] ;
  input [1:0]\rsMask_reg[1]_71 ;
  input [1:0]\rsMask_reg[3]_73 ;
  input [1:0]\rsMask_reg[1]_79 ;
  input [1:0]\rsMask_reg[3]_81 ;
  input [0:0]\cplx_config_reg[16] ;
  input \cplx_config_reg[16]_0 ;
  input cnt_clr_access;
  input a_b_cmd_sel_start0;
  input cal_timer_reg_0_sp_1;
  input \addr_dec_to_mb_data[7]_i_7 ;
  input io_ready_reg;
  input \addr_dec_to_mb_data_reg[15] ;
  input \addr_dec_to_mb_data_reg[19] ;
  input \addr_dec_to_mb_data_reg[12] ;
  input \addr_dec_to_mb_data[0]_i_3 ;
  input io_ready_reg_0;
  input io_ready_reg_1;
  input \addr_dec_to_mb_data_reg[29] ;
  input \addr_dec_to_mb_data_reg[29]_0 ;
  input \addr_dec_to_mb_data_reg[14] ;
  input \addr_dec_to_mb_data_reg[29]_1 ;
  input \addr_dec_to_mb_data_reg[29]_2 ;
  input \addr_dec_to_mb_data_reg[29]_3 ;
  input \addr_dec_to_mb_data[4]_i_11 ;
  input [0:0]\dqin_valid_shift_reg[0] ;
  input \addr_dec_to_mb_data[31]_i_3 ;
  input wrDataEn_pi;
  input rdDataEn_pi;
  input \addr_dec_to_mb_data[6]_i_7 ;
  input \addr_dec_to_mb_data[6]_i_7_0 ;
  input [1:0]\rsMask_reg[7]_77 ;
  input [1:0]\rsMask_reg[5]_75 ;
  input [1:0]\rsMask_reg[7]_85 ;
  input [1:0]\rsMask_reg[5]_83 ;
  input \rdEn_reg[29] ;
  input \rdEn_reg[29]_0 ;
  input \rdEn_reg[28] ;
  input [2:1]wosp;
  input \dReg_reg[9] ;
  input wrDataVal;
  input \dReg_reg[9]_0 ;
  input \dReg_reg[11] ;
  input \dReg_reg[10] ;
  input \dReg_reg[9]_1 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[8] ;
  input \dReg_reg[8]_0 ;
  input \rdEn_reg[29]_1 ;
  input \rdEn_reg[28]_0 ;
  input \rdEn_reg[29]_2 ;
  input \rdEn_reg[28]_1 ;
  input \rdEn_reg[29]_3 ;
  input \rdEn_reg[28]_2 ;
  input \rdEn_reg[29]_4 ;
  input \rdEn_reg[28]_3 ;
  input \rdEn_reg[29]_5 ;
  input \rdEn_reg[28]_4 ;
  input \rdEn_reg[29]_6 ;
  input \rdEn_reg[28]_5 ;
  input \rdEn_reg[29]_7 ;
  input \rdEn_reg[28]_6 ;
  input \rdEn_reg[29]_8 ;
  input \rdEn_reg[28]_7 ;
  input \rdEn_reg[29]_9 ;
  input \rdEn_reg[28]_8 ;
  input \rdEn_reg[29]_10 ;
  input \rdEn_reg[28]_9 ;
  input \rdEn_reg[29]_11 ;
  input \rdEn_reg[28]_10 ;
  input \rdEn_reg[29]_12 ;
  input \rdEn_reg[28]_11 ;
  input \rdEn_reg[29]_13 ;
  input \rdEn_reg[28]_12 ;
  input [10:0]\dout_o_reg[11]_0 ;
  input [0:0]\cal_seq_reg[2] ;
  input [511:0]\mcal_DQIn_r_reg[511] ;
  input [0:0]\cal_cmp_en_reg[7] ;
  input \cal_DQPat_A_reg[63] ;
  input \cal_DQPat_A_reg[31] ;
  input \cal_DQPat_B_reg[63] ;
  input \cal_DQPat_B_reg[31] ;
  input [0:0]\cmp_byte_reg[2] ;
  input [0:0]\cal_cs_pos_reg[1] ;
  input [0:0]\cplx_config_reg[0] ;
  input \cplx_config_reg[1] ;
  input [0:0]\cal_seq_a_b_dly_reg[7] ;
  input [0:0]\cal_seq_a_a_dly_reg[7] ;
  input [0:0]\cal_seq_b_a_dly_reg[7] ;
  input [0:0]\cal_RST_CKE_ODT_PAR_reg[31] ;
  input [0:0]\traffic_instr_nxt_instr_r1_reg[5] ;
  input [7:0]\uppCL3_reg[42]_1 ;
  input [9:0]\uppCL0_reg[47] ;
  input [9:0]\uppCL1_reg[47] ;
  input [9:0]\uppCL2_reg[47] ;
  input [9:0]\uppCL3_reg[47] ;
  input [0:0]\cal_CS_A_reg[7]_0 ;
  input [0:0]\cal_CS_B_reg[7] ;
  input [63:0]\mcal_DMIn_n_r_reg[63] ;
  input [0:0]\cal_ADR_A_reg[31] ;
  input [0:0]\cal_ADR_B_reg[31]_0 ;
  input [20:0]\addr_dec_to_mb_data_reg[31] ;
  input \addr_dec_to_mb_data_reg[30] ;
  input \addr_dec_to_mb_data_reg[30]_0 ;
  input \addr_dec_to_mb_data_reg[29]_4 ;
  input \addr_dec_to_mb_data_reg[28] ;
  input \addr_dec_to_mb_data_reg[27] ;
  input \addr_dec_to_mb_data_reg[26] ;
  input \addr_dec_to_mb_data_reg[25] ;
  input \addr_dec_to_mb_data_reg[24] ;
  input \addr_dec_to_mb_data_reg[23] ;
  input \addr_dec_to_mb_data_reg[22] ;
  input \addr_dec_to_mb_data_reg[21] ;
  input \addr_dec_to_mb_data_reg[20] ;
  input [0:0]\bisc_bit_reg[0] ;
  input \cal_DQOut_A_reg[63] ;
  input \cal_DQOut_A_reg[31] ;
  input \cal_DQOut_pre_reg[63] ;
  input \cal_DQOut_pre_reg[31] ;
  input \cal_DQOut_post_reg[63] ;
  input \cal_DQOut_post_reg[31] ;
  input [0:0]\cal_DMOut_n_A_reg[31] ;
  input [0:0]\genblk10[3].cal_DMOut_n_A_r_reg[24] ;
  input [0:0]\genblk10[6].cal_DMOut_n_A_r_reg[48] ;
  input [0:0]\cal_CAS_A_reg[0] ;
  input [0:0]\cal_RAS_B_reg[0] ;
  input [0:0]\cal_ACT_n_A_reg[7] ;
  input [0:0]\max_rd_lat_reg[5]_0 ;
  input [7:0]rd_vref_value0_out;
  input [31:0]\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 ;

  wire [0:0]D;
  wire DDR_XSDB_BRAM_n_10;
  wire DDR_XSDB_BRAM_n_11;
  wire DDR_XSDB_BRAM_n_12;
  wire DDR_XSDB_BRAM_n_13;
  wire DDR_XSDB_BRAM_n_14;
  wire DDR_XSDB_BRAM_n_15;
  wire DDR_XSDB_BRAM_n_16;
  wire DDR_XSDB_BRAM_n_17;
  wire DDR_XSDB_BRAM_n_9;
  wire [63:0]DMOut;
  wire [511:0]DQOut;
  wire [0:0]E;
  wire [7:0]O;
  wire [1:0]Q;
  wire [0:0]S;
  wire [0:0]SR;
  wire \SYNC[0].sync_reg_reg[1] ;
  wire \SYNC[0].sync_reg_reg[1]_0 ;
  wire \SYNC[0].sync_reg_reg[1]_1 ;
  wire \SYNC[18].sync_reg_reg[1] ;
  wire \SYNC[20].sync_reg_reg[1] ;
  wire \SYNC[3].sync_reg_reg[1] ;
  wire \SYNC[3].sync_reg_reg[1]_0 ;
  wire \SYNC[3].sync_reg_reg[1]_1 ;
  wire \SYNC[3].sync_reg_reg[1]_10 ;
  wire \SYNC[3].sync_reg_reg[1]_11 ;
  wire \SYNC[3].sync_reg_reg[1]_12 ;
  wire \SYNC[3].sync_reg_reg[1]_13 ;
  wire \SYNC[3].sync_reg_reg[1]_14 ;
  wire \SYNC[3].sync_reg_reg[1]_15 ;
  wire \SYNC[3].sync_reg_reg[1]_16 ;
  wire \SYNC[3].sync_reg_reg[1]_17 ;
  wire \SYNC[3].sync_reg_reg[1]_18 ;
  wire \SYNC[3].sync_reg_reg[1]_19 ;
  wire \SYNC[3].sync_reg_reg[1]_2 ;
  wire \SYNC[3].sync_reg_reg[1]_20 ;
  wire \SYNC[3].sync_reg_reg[1]_21 ;
  wire \SYNC[3].sync_reg_reg[1]_22 ;
  wire \SYNC[3].sync_reg_reg[1]_23 ;
  wire \SYNC[3].sync_reg_reg[1]_24 ;
  wire \SYNC[3].sync_reg_reg[1]_25 ;
  wire \SYNC[3].sync_reg_reg[1]_26 ;
  wire \SYNC[3].sync_reg_reg[1]_27 ;
  wire \SYNC[3].sync_reg_reg[1]_28 ;
  wire \SYNC[3].sync_reg_reg[1]_29 ;
  wire \SYNC[3].sync_reg_reg[1]_3 ;
  wire \SYNC[3].sync_reg_reg[1]_30 ;
  wire \SYNC[3].sync_reg_reg[1]_31 ;
  wire \SYNC[3].sync_reg_reg[1]_32 ;
  wire \SYNC[3].sync_reg_reg[1]_33 ;
  wire \SYNC[3].sync_reg_reg[1]_34 ;
  wire \SYNC[3].sync_reg_reg[1]_35 ;
  wire \SYNC[3].sync_reg_reg[1]_36 ;
  wire \SYNC[3].sync_reg_reg[1]_37 ;
  wire \SYNC[3].sync_reg_reg[1]_38 ;
  wire \SYNC[3].sync_reg_reg[1]_39 ;
  wire \SYNC[3].sync_reg_reg[1]_4 ;
  wire \SYNC[3].sync_reg_reg[1]_40 ;
  wire \SYNC[3].sync_reg_reg[1]_41 ;
  wire \SYNC[3].sync_reg_reg[1]_42 ;
  wire \SYNC[3].sync_reg_reg[1]_43 ;
  wire \SYNC[3].sync_reg_reg[1]_44 ;
  wire \SYNC[3].sync_reg_reg[1]_45 ;
  wire \SYNC[3].sync_reg_reg[1]_5 ;
  wire \SYNC[3].sync_reg_reg[1]_6 ;
  wire \SYNC[3].sync_reg_reg[1]_7 ;
  wire \SYNC[3].sync_reg_reg[1]_8 ;
  wire \SYNC[3].sync_reg_reg[1]_9 ;
  wire \SYNC[4].sync_reg_reg[1] ;
  wire \SYNC[4].sync_reg_reg[1]_0 ;
  wire \SYNC[5].sync_reg_reg[1] ;
  wire \SYNC[5].sync_reg_reg[1]_0 ;
  wire \SYNC[5].sync_reg_reg[1]_1 ;
  wire \SYNC[5].sync_reg_reg[1]_10 ;
  wire \SYNC[5].sync_reg_reg[1]_11 ;
  wire \SYNC[5].sync_reg_reg[1]_12 ;
  wire \SYNC[5].sync_reg_reg[1]_13 ;
  wire \SYNC[5].sync_reg_reg[1]_14 ;
  wire \SYNC[5].sync_reg_reg[1]_15 ;
  wire \SYNC[5].sync_reg_reg[1]_16 ;
  wire \SYNC[5].sync_reg_reg[1]_17 ;
  wire \SYNC[5].sync_reg_reg[1]_2 ;
  wire \SYNC[5].sync_reg_reg[1]_3 ;
  wire \SYNC[5].sync_reg_reg[1]_4 ;
  wire \SYNC[5].sync_reg_reg[1]_5 ;
  wire \SYNC[5].sync_reg_reg[1]_6 ;
  wire \SYNC[5].sync_reg_reg[1]_7 ;
  wire \SYNC[5].sync_reg_reg[1]_8 ;
  wire \SYNC[5].sync_reg_reg[1]_9 ;
  wire a_b_cmd_sel_start0;
  wire a_b_cmd_sel_start_reg;
  wire a_b_cmd_sel_start_reg_0;
  wire \addr_dec_to_mb_data[0]_i_3 ;
  wire \addr_dec_to_mb_data[31]_i_3 ;
  wire \addr_dec_to_mb_data[4]_i_11 ;
  wire \addr_dec_to_mb_data[6]_i_7 ;
  wire \addr_dec_to_mb_data[6]_i_7_0 ;
  wire \addr_dec_to_mb_data[7]_i_7 ;
  wire \addr_dec_to_mb_data_reg[12] ;
  wire \addr_dec_to_mb_data_reg[14] ;
  wire \addr_dec_to_mb_data_reg[15] ;
  wire \addr_dec_to_mb_data_reg[19] ;
  wire \addr_dec_to_mb_data_reg[20] ;
  wire \addr_dec_to_mb_data_reg[21] ;
  wire \addr_dec_to_mb_data_reg[22] ;
  wire \addr_dec_to_mb_data_reg[23] ;
  wire \addr_dec_to_mb_data_reg[24] ;
  wire \addr_dec_to_mb_data_reg[25] ;
  wire \addr_dec_to_mb_data_reg[26] ;
  wire \addr_dec_to_mb_data_reg[27] ;
  wire \addr_dec_to_mb_data_reg[28] ;
  wire \addr_dec_to_mb_data_reg[29] ;
  wire \addr_dec_to_mb_data_reg[29]_0 ;
  wire \addr_dec_to_mb_data_reg[29]_1 ;
  wire \addr_dec_to_mb_data_reg[29]_2 ;
  wire \addr_dec_to_mb_data_reg[29]_3 ;
  wire \addr_dec_to_mb_data_reg[29]_4 ;
  wire \addr_dec_to_mb_data_reg[30] ;
  wire \addr_dec_to_mb_data_reg[30]_0 ;
  wire [20:0]\addr_dec_to_mb_data_reg[31] ;
  wire [0:0]\bisc_bit_reg[0] ;
  wire [8:0]bisc_byte;
  wire [1:0]\blk1.(null)[0].diff ;
  wire [1:0]\blk1.(null)[0].diff_1 ;
  wire [1:0]\blk1.(null)[0].diff_11 ;
  wire [1:0]\blk1.(null)[0].diff_13 ;
  wire [1:0]\blk1.(null)[0].diff_15 ;
  wire [1:0]\blk1.(null)[0].diff_17 ;
  wire [1:0]\blk1.(null)[0].diff_19 ;
  wire [1:0]\blk1.(null)[0].diff_21 ;
  wire [1:0]\blk1.(null)[0].diff_23 ;
  wire [1:0]\blk1.(null)[0].diff_25 ;
  wire [1:0]\blk1.(null)[0].diff_27 ;
  wire [1:0]\blk1.(null)[0].diff_28 ;
  wire [1:0]\blk1.(null)[0].diff_3 ;
  wire [1:0]\blk1.(null)[0].diff_5 ;
  wire [1:0]\blk1.(null)[0].diff_7 ;
  wire [1:0]\blk1.(null)[0].diff_9 ;
  wire [15:0]bramB_addr;
  wire [8:0]bramB_di;
  wire bramB_en;
  wire bramB_en_stch;
  wire bramB_rdy;
  wire bramB_we;
  wire [0:0]calDone_gated_reg;
  wire calDone_i;
  wire calDone_reg_0;
  wire calDone_reg_1;
  wire calDone_reg_10;
  wire calDone_reg_11;
  wire calDone_reg_12;
  wire calDone_reg_13;
  wire calDone_reg_14;
  wire [76:0]calDone_reg_2;
  wire [3:0]calDone_reg_3;
  wire [7:0]calDone_reg_4;
  wire calDone_reg_5;
  wire calDone_reg_6;
  wire calDone_reg_7;
  wire calDone_reg_8;
  wire calDone_reg_9;
  wire calRdCAS;
  wire \calSt[0]_i_1_n_0 ;
  wire \calSt[1]_i_1_n_0 ;
  wire \calSt[2]_i_1_n_0 ;
  wire \calSt[3]_i_1_n_0 ;
  wire \calSt[3]_i_2_n_0 ;
  wire \calSt[3]_i_4_n_0 ;
  wire \calSt[3]_i_5_n_0 ;
  wire \calSt[3]_i_6_n_0 ;
  wire \calSt[3]_i_7_n_0 ;
  wire \calSt_reg[0]_0 ;
  wire \calSt_reg_n_0_[0] ;
  wire \calSt_reg_n_0_[1] ;
  wire \calSt_reg_n_0_[2] ;
  wire \calSt_reg_n_0_[3] ;
  wire [0:0]\cal_ACT_n_A_reg[7] ;
  wire [5:0]\cal_ACT_n_pre_reg[7] ;
  wire \cal_ADR_A_reg[0] ;
  wire \cal_ADR_A_reg[0]_0 ;
  wire \cal_ADR_A_reg[1] ;
  wire \cal_ADR_A_reg[20] ;
  wire \cal_ADR_A_reg[21] ;
  wire \cal_ADR_A_reg[22] ;
  wire \cal_ADR_A_reg[26] ;
  wire \cal_ADR_A_reg[27] ;
  wire \cal_ADR_A_reg[29] ;
  wire \cal_ADR_A_reg[2] ;
  wire [11:0]\cal_ADR_A_reg[30] ;
  wire [0:0]\cal_ADR_A_reg[31] ;
  wire \cal_ADR_A_reg[3] ;
  wire \cal_ADR_A_reg[4] ;
  wire \cal_ADR_A_reg[4]_0 ;
  wire \cal_ADR_B_reg[10] ;
  wire \cal_ADR_B_reg[11] ;
  wire \cal_ADR_B_reg[12] ;
  wire \cal_ADR_B_reg[13] ;
  wire \cal_ADR_B_reg[15] ;
  wire \cal_ADR_B_reg[17] ;
  wire \cal_ADR_B_reg[18] ;
  wire \cal_ADR_B_reg[19] ;
  wire \cal_ADR_B_reg[24] ;
  wire \cal_ADR_B_reg[25] ;
  wire [12:0]\cal_ADR_B_reg[30] ;
  wire \cal_ADR_B_reg[31] ;
  wire [0:0]\cal_ADR_B_reg[31]_0 ;
  wire [0:0]\cal_CAS_A_reg[0] ;
  wire \cal_CS_A_reg[0] ;
  wire \cal_CS_A_reg[4] ;
  wire [4:0]\cal_CS_A_reg[5] ;
  wire \cal_CS_A_reg[6] ;
  wire \cal_CS_A_reg[7] ;
  wire [0:0]\cal_CS_A_reg[7]_0 ;
  wire [4:0]\cal_CS_B_reg[5] ;
  wire [0:0]\cal_CS_B_reg[7] ;
  wire [3:0]cal_CS_n;
  wire [0:0]\cal_DMOut_n_A_reg[31] ;
  wire \cal_DQOut_A_reg[31] ;
  wire \cal_DQOut_A_reg[63] ;
  wire \cal_DQOut_post_reg[31] ;
  wire \cal_DQOut_post_reg[63] ;
  wire \cal_DQOut_pre_reg[31] ;
  wire \cal_DQOut_pre_reg[63] ;
  wire \cal_DQPat_A_reg[31] ;
  wire \cal_DQPat_A_reg[63] ;
  wire \cal_DQPat_B_reg[31] ;
  wire \cal_DQPat_B_reg[63] ;
  wire [0:0]\cal_RAS_B_reg[0] ;
  wire \cal_RAS_pre_reg[1] ;
  wire \cal_RAS_pre_reg[2] ;
  wire [2:0]\cal_RST_CKE_ODT_PAR_reg[16] ;
  wire \cal_RST_CKE_ODT_PAR_reg[16]_0 ;
  wire [10:0]\cal_RST_CKE_ODT_PAR_reg[30] ;
  wire [0:0]\cal_RST_CKE_ODT_PAR_reg[31] ;
  wire [7:0]\cal_RST_CKE_ODT_PAR_reg[7] ;
  wire \cal_RST_CKE_ODT_PAR_reg[9] ;
  wire cal_clear_fifo_rden;
  wire [0:0]\cal_cmp_en_reg[7] ;
  wire [0:0]\cal_cs_pos_reg[1] ;
  wire [0:0]cal_oe_dis_low;
  wire \cal_oe_dis_low_reg[7] ;
  wire [0:0]cal_oe_dis_upp;
  wire \cal_oe_dis_upp_reg[7] ;
  wire [0:0]\cal_seq_a_a_dly_reg[7] ;
  wire [0:0]\cal_seq_a_b_dly_reg[7] ;
  wire [0:0]\cal_seq_b_a_dly_reg[7] ;
  wire cal_seq_cnt_gt_0_reg;
  wire \cal_seq_cnt_reg[13] ;
  wire [31:0]\cal_seq_cnt_reg[31] ;
  wire [7:0]\cal_seq_rd_cnt_reg[7] ;
  wire [0:0]\cal_seq_reg[2] ;
  wire [31:0]cal_timer_reg;
  wire [7:0]\cal_timer_reg[15] ;
  wire [7:0]\cal_timer_reg[23] ;
  wire [7:0]\cal_timer_reg[31] ;
  wire cal_timer_reg_0_sn_1;
  wire cal_timer_reg_21_sn_1;
  wire cal_timer_reg_24_sn_1;
  wire cal_timer_reg_25_sn_1;
  wire cal_timer_reg_28_sn_1;
  wire cal_timer_reg_29_sn_1;
  wire caldone_r;
  wire \clb2phy_wrcs0_low_reg[31] ;
  wire clear_gt_data_ready_flag;
  wire clear_gt_data_ready_flag_reg;
  wire [0:0]\cmp_byte_reg[2] ;
  wire [4:0]cmr_cnt;
  wire \cmr_cnt[0]_i_1_n_0 ;
  wire \cmr_cnt[1]_i_1_n_0 ;
  wire \cmr_cnt[2]_i_1_n_0 ;
  wire \cmr_cnt[3]_i_1_n_0 ;
  wire \cmr_cnt[4]_i_2_n_0 ;
  wire \cmr_cnt[4]_i_3_n_0 ;
  wire cnt_clr_access;
  wire cnt_clr_reg;
  wire cnt_clr_reg_0;
  wire [17:0]cntr;
  wire \cntr[0]_i_1_n_0 ;
  wire \cntr[10]_i_1_n_0 ;
  wire \cntr[10]_i_2_n_0 ;
  wire \cntr[11]_i_1_n_0 ;
  wire \cntr[12]_i_1_n_0 ;
  wire \cntr[13]_i_1_n_0 ;
  wire \cntr[14]_i_1_n_0 ;
  wire \cntr[15]_i_1_n_0 ;
  wire \cntr[16]_i_10_n_0 ;
  wire \cntr[16]_i_1_n_0 ;
  wire \cntr[16]_i_3_n_0 ;
  wire \cntr[16]_i_4_n_0 ;
  wire \cntr[16]_i_5_n_0 ;
  wire \cntr[16]_i_6_n_0 ;
  wire \cntr[16]_i_7_n_0 ;
  wire \cntr[16]_i_8_n_0 ;
  wire \cntr[16]_i_9_n_0 ;
  wire \cntr[17]_i_2_n_0 ;
  wire \cntr[17]_i_4_n_0 ;
  wire \cntr[1]_i_1_n_0 ;
  wire \cntr[2]_i_1_n_0 ;
  wire \cntr[3]_i_1_n_0 ;
  wire \cntr[4]_i_1_n_0 ;
  wire \cntr[5]_i_1_n_0 ;
  wire \cntr[6]_i_1_n_0 ;
  wire \cntr[7]_i_1_n_0 ;
  wire \cntr[8]_i_10_n_0 ;
  wire \cntr[8]_i_1_n_0 ;
  wire \cntr[8]_i_3_n_0 ;
  wire \cntr[8]_i_4_n_0 ;
  wire \cntr[8]_i_5_n_0 ;
  wire \cntr[8]_i_6_n_0 ;
  wire \cntr[8]_i_7_n_0 ;
  wire \cntr[8]_i_8_n_0 ;
  wire \cntr[8]_i_9_n_0 ;
  wire \cntr[9]_i_1_n_0 ;
  wire \cntr_reg[16]_i_2_n_0 ;
  wire \cntr_reg[16]_i_2_n_1 ;
  wire \cntr_reg[16]_i_2_n_2 ;
  wire \cntr_reg[16]_i_2_n_3 ;
  wire \cntr_reg[16]_i_2_n_4 ;
  wire \cntr_reg[16]_i_2_n_5 ;
  wire \cntr_reg[16]_i_2_n_6 ;
  wire \cntr_reg[16]_i_2_n_7 ;
  wire \cntr_reg[8]_i_2_n_0 ;
  wire \cntr_reg[8]_i_2_n_1 ;
  wire \cntr_reg[8]_i_2_n_2 ;
  wire \cntr_reg[8]_i_2_n_3 ;
  wire \cntr_reg[8]_i_2_n_4 ;
  wire \cntr_reg[8]_i_2_n_5 ;
  wire \cntr_reg[8]_i_2_n_6 ;
  wire \cntr_reg[8]_i_2_n_7 ;
  wire [7:0]\cplx_CAS_reg[6] ;
  wire \cplx_RAS_reg[6] ;
  wire \cplx_RAS_reg[6]_0 ;
  wire [3:0]cplx_cal_reg;
  wire [0:0]\cplx_config_reg[0] ;
  wire [0:0]\cplx_config_reg[16] ;
  wire \cplx_config_reg[16]_0 ;
  wire \cplx_config_reg[1] ;
  wire \cplx_error_accum_reg[14] ;
  wire \cplx_error_accum_reg[15] ;
  wire \cplx_error_accum_reg[19] ;
  wire \cplx_error_accum_reg[44] ;
  wire [53:0]\cplx_error_accum_reg[63] ;
  wire [0:0]cplx_status;
  wire cs_mask_int;
  wire \cs_mask_int[0]_i_1_n_0 ;
  wire \cs_mask_int_reg_n_0_[0] ;
  wire \dReg_reg[10] ;
  wire \dReg_reg[11] ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [575:0]\dReg_reg[15] ;
  wire \dReg_reg[8] ;
  wire \dReg_reg[8]_0 ;
  wire \dReg_reg[9] ;
  wire \dReg_reg[9]_0 ;
  wire \dReg_reg[9]_1 ;
  wire [17:1]data1;
  wire [1:0]\delay_cntr_reg[2] ;
  wire [10:0]\dout_o_reg[11] ;
  wire [10:0]\dout_o_reg[11]_0 ;
  wire \dout_o_reg[5] ;
  wire [8:0]douta;
  wire [0:0]\dqin_valid_shift_reg[0] ;
  wire en_vtc;
  wire ena;
  wire [0:0]\genblk10[3].cal_DMOut_n_A_r_reg[24] ;
  wire [0:0]\genblk10[6].cal_DMOut_n_A_r_reg[48] ;
  wire \genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8] ;
  wire \genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9] ;
  wire gt_data_ready_flag;
  wire gt_data_ready_flag_nxt;
  wire gt_data_ready_flag_reg;
  wire [1:0]in0;
  wire initDone;
  wire initDone_i_1_n_0;
  wire \init_cal_ADR[103]_i_3_n_0 ;
  wire \init_cal_ADR[23]_i_2_n_0 ;
  wire \init_cal_ADR[31]_i_2_n_0 ;
  wire \init_cal_ADR[39]_i_2_n_0 ;
  wire \init_cal_ADR[47]_i_2_n_0 ;
  wire \init_cal_ADR[55]_i_2_n_0 ;
  wire \init_cal_ADR[71]_i_2_n_0 ;
  wire \init_cal_ADR[79]_i_2_n_0 ;
  wire \init_cal_ADR[7]_i_2_n_0 ;
  wire \init_cal_ADR[87]_i_1_n_0 ;
  wire \init_cal_ADR[87]_i_2_n_0 ;
  wire \init_cal_ADR_reg_n_0_[103] ;
  wire \init_cal_ADR_reg_n_0_[116] ;
  wire \init_cal_ADR_reg_n_0_[132] ;
  wire \init_cal_ADR_reg_n_0_[135] ;
  wire \init_cal_ADR_reg_n_0_[15] ;
  wire \init_cal_ADR_reg_n_0_[23] ;
  wire \init_cal_ADR_reg_n_0_[31] ;
  wire \init_cal_ADR_reg_n_0_[39] ;
  wire \init_cal_ADR_reg_n_0_[47] ;
  wire \init_cal_ADR_reg_n_0_[55] ;
  wire \init_cal_ADR_reg_n_0_[63] ;
  wire \init_cal_ADR_reg_n_0_[71] ;
  wire \init_cal_ADR_reg_n_0_[79] ;
  wire \init_cal_ADR_reg_n_0_[7] ;
  wire \init_cal_ADR_reg_n_0_[87] ;
  wire \init_cal_ADR_reg_n_0_[95] ;
  wire [15:7]init_cal_BA;
  wire \init_cal_BA[15]_i_1_n_0 ;
  wire \init_cal_BA[7]_i_1_n_0 ;
  wire [8:0]\init_cal_BA_reg[15]_0 ;
  wire \init_cal_BA_reg[7]_0 ;
  wire [7:7]init_cal_BG;
  wire \init_cal_BG[7]_i_1_n_0 ;
  wire \init_cal_BG_reg[7]_0 ;
  wire [7:7]init_cal_CKE;
  wire \init_cal_CKE[7]_i_1_n_0 ;
  wire [4:4]init_cal_CS_n;
  wire \init_cal_CS_n[4]_i_1_n_0 ;
  wire [7:7]init_cal_RESET_n;
  wire \init_cal_RESET_n[7]_i_2_n_0 ;
  wire io_addr_strobe_r1_reg;
  wire [20:0]io_address;
  wire [31:0]\io_read_data_reg[31] ;
  wire [0:0]io_ready_lvl_reg;
  wire io_ready_reg;
  wire io_ready_reg_0;
  wire io_ready_reg_1;
  wire [31:0]io_write_data;
  wire [45:0]lowCL0;
  wire \lowCL0_reg[0]_0 ;
  wire \lowCL0_reg[12]_0 ;
  wire \lowCL0_reg[13]_0 ;
  wire \lowCL0_reg[13]_1 ;
  wire \lowCL0_reg[13]_2 ;
  wire \lowCL0_reg[14]_0 ;
  wire \lowCL0_reg[14]_1 ;
  wire \lowCL0_reg[14]_2 ;
  wire [2:0]\lowCL0_reg[14]_3 ;
  wire \lowCL0_reg[14]_4 ;
  wire \lowCL0_reg[14]_5 ;
  wire \lowCL0_reg[14]_6 ;
  wire \lowCL0_reg[15]_0 ;
  wire \lowCL0_reg[18]_0 ;
  wire \lowCL0_reg[19]_0 ;
  wire \lowCL0_reg[19]_1 ;
  wire \lowCL0_reg[19]_2 ;
  wire \lowCL0_reg[1]_0 ;
  wire \lowCL0_reg[1]_1 ;
  wire \lowCL0_reg[1]_2 ;
  wire \lowCL0_reg[20]_0 ;
  wire \lowCL0_reg[20]_1 ;
  wire \lowCL0_reg[20]_2 ;
  wire [2:0]\lowCL0_reg[20]_3 ;
  wire \lowCL0_reg[20]_4 ;
  wire \lowCL0_reg[20]_5 ;
  wire \lowCL0_reg[20]_6 ;
  wire \lowCL0_reg[21]_0 ;
  wire \lowCL0_reg[24]_0 ;
  wire \lowCL0_reg[25]_0 ;
  wire \lowCL0_reg[25]_1 ;
  wire \lowCL0_reg[25]_2 ;
  wire \lowCL0_reg[26]_0 ;
  wire \lowCL0_reg[26]_1 ;
  wire \lowCL0_reg[26]_2 ;
  wire [2:0]\lowCL0_reg[26]_3 ;
  wire \lowCL0_reg[26]_4 ;
  wire \lowCL0_reg[26]_5 ;
  wire \lowCL0_reg[26]_6 ;
  wire \lowCL0_reg[27]_0 ;
  wire \lowCL0_reg[2]_0 ;
  wire \lowCL0_reg[2]_1 ;
  wire \lowCL0_reg[2]_2 ;
  wire [2:0]\lowCL0_reg[2]_3 ;
  wire \lowCL0_reg[2]_4 ;
  wire \lowCL0_reg[2]_5 ;
  wire \lowCL0_reg[2]_6 ;
  wire \lowCL0_reg[30]_0 ;
  wire \lowCL0_reg[31]_0 ;
  wire \lowCL0_reg[31]_1 ;
  wire \lowCL0_reg[31]_2 ;
  wire \lowCL0_reg[32]_0 ;
  wire \lowCL0_reg[32]_1 ;
  wire \lowCL0_reg[32]_2 ;
  wire [2:0]\lowCL0_reg[32]_3 ;
  wire \lowCL0_reg[32]_4 ;
  wire \lowCL0_reg[32]_5 ;
  wire \lowCL0_reg[32]_6 ;
  wire \lowCL0_reg[33]_0 ;
  wire \lowCL0_reg[36]_0 ;
  wire \lowCL0_reg[37]_0 ;
  wire \lowCL0_reg[37]_1 ;
  wire \lowCL0_reg[37]_2 ;
  wire \lowCL0_reg[38]_0 ;
  wire \lowCL0_reg[38]_1 ;
  wire \lowCL0_reg[38]_2 ;
  wire [2:0]\lowCL0_reg[38]_3 ;
  wire \lowCL0_reg[38]_4 ;
  wire \lowCL0_reg[38]_5 ;
  wire \lowCL0_reg[38]_6 ;
  wire \lowCL0_reg[39]_0 ;
  wire \lowCL0_reg[3]_0 ;
  wire \lowCL0_reg[42]_0 ;
  wire \lowCL0_reg[43]_0 ;
  wire \lowCL0_reg[43]_1 ;
  wire \lowCL0_reg[43]_2 ;
  wire \lowCL0_reg[44]_0 ;
  wire \lowCL0_reg[44]_1 ;
  wire \lowCL0_reg[44]_2 ;
  wire [2:0]\lowCL0_reg[44]_3 ;
  wire \lowCL0_reg[44]_4 ;
  wire \lowCL0_reg[44]_5 ;
  wire \lowCL0_reg[44]_6 ;
  wire \lowCL0_reg[45]_0 ;
  wire \lowCL0_reg[6]_0 ;
  wire \lowCL0_reg[7]_0 ;
  wire \lowCL0_reg[7]_1 ;
  wire \lowCL0_reg[7]_2 ;
  wire \lowCL0_reg[8]_0 ;
  wire \lowCL0_reg[8]_1 ;
  wire \lowCL0_reg[8]_2 ;
  wire [2:0]\lowCL0_reg[8]_3 ;
  wire \lowCL0_reg[8]_4 ;
  wire \lowCL0_reg[8]_5 ;
  wire \lowCL0_reg[8]_6 ;
  wire \lowCL0_reg[9]_0 ;
  wire [45:0]lowCL1;
  wire \lowCL1_reg[0]_0 ;
  wire \lowCL1_reg[12]_0 ;
  wire \lowCL1_reg[13]_0 ;
  wire \lowCL1_reg[13]_1 ;
  wire [0:0]\lowCL1_reg[13]_2 ;
  wire \lowCL1_reg[13]_3 ;
  wire \lowCL1_reg[13]_4 ;
  wire \lowCL1_reg[13]_5 ;
  wire \lowCL1_reg[13]_6 ;
  wire \lowCL1_reg[13]_7 ;
  wire \lowCL1_reg[13]_8 ;
  wire \lowCL1_reg[14]_0 ;
  wire \lowCL1_reg[14]_1 ;
  wire \lowCL1_reg[14]_2 ;
  wire [2:0]\lowCL1_reg[14]_3 ;
  wire \lowCL1_reg[14]_4 ;
  wire \lowCL1_reg[14]_5 ;
  wire \lowCL1_reg[14]_6 ;
  wire \lowCL1_reg[14]_7 ;
  wire \lowCL1_reg[15]_0 ;
  wire \lowCL1_reg[18]_0 ;
  wire \lowCL1_reg[19]_0 ;
  wire \lowCL1_reg[19]_1 ;
  wire [0:0]\lowCL1_reg[19]_2 ;
  wire \lowCL1_reg[19]_3 ;
  wire \lowCL1_reg[19]_4 ;
  wire \lowCL1_reg[19]_5 ;
  wire \lowCL1_reg[19]_6 ;
  wire \lowCL1_reg[19]_7 ;
  wire \lowCL1_reg[19]_8 ;
  wire \lowCL1_reg[1]_0 ;
  wire \lowCL1_reg[1]_1 ;
  wire [0:0]\lowCL1_reg[1]_2 ;
  wire \lowCL1_reg[1]_3 ;
  wire \lowCL1_reg[1]_4 ;
  wire \lowCL1_reg[1]_5 ;
  wire \lowCL1_reg[1]_6 ;
  wire \lowCL1_reg[1]_7 ;
  wire \lowCL1_reg[1]_8 ;
  wire \lowCL1_reg[20]_0 ;
  wire \lowCL1_reg[20]_1 ;
  wire \lowCL1_reg[20]_2 ;
  wire [2:0]\lowCL1_reg[20]_3 ;
  wire \lowCL1_reg[20]_4 ;
  wire \lowCL1_reg[20]_5 ;
  wire \lowCL1_reg[20]_6 ;
  wire \lowCL1_reg[20]_7 ;
  wire \lowCL1_reg[21]_0 ;
  wire \lowCL1_reg[24]_0 ;
  wire \lowCL1_reg[25]_0 ;
  wire \lowCL1_reg[25]_1 ;
  wire [0:0]\lowCL1_reg[25]_2 ;
  wire \lowCL1_reg[25]_3 ;
  wire \lowCL1_reg[25]_4 ;
  wire \lowCL1_reg[25]_5 ;
  wire \lowCL1_reg[25]_6 ;
  wire \lowCL1_reg[25]_7 ;
  wire \lowCL1_reg[25]_8 ;
  wire \lowCL1_reg[26]_0 ;
  wire \lowCL1_reg[26]_1 ;
  wire \lowCL1_reg[26]_2 ;
  wire [2:0]\lowCL1_reg[26]_3 ;
  wire \lowCL1_reg[26]_4 ;
  wire \lowCL1_reg[26]_5 ;
  wire \lowCL1_reg[26]_6 ;
  wire \lowCL1_reg[26]_7 ;
  wire \lowCL1_reg[27]_0 ;
  wire \lowCL1_reg[2]_0 ;
  wire \lowCL1_reg[2]_1 ;
  wire \lowCL1_reg[2]_2 ;
  wire [2:0]\lowCL1_reg[2]_3 ;
  wire \lowCL1_reg[2]_4 ;
  wire \lowCL1_reg[2]_5 ;
  wire \lowCL1_reg[2]_6 ;
  wire \lowCL1_reg[2]_7 ;
  wire \lowCL1_reg[30]_0 ;
  wire \lowCL1_reg[31]_0 ;
  wire \lowCL1_reg[31]_1 ;
  wire [0:0]\lowCL1_reg[31]_2 ;
  wire \lowCL1_reg[31]_3 ;
  wire \lowCL1_reg[31]_4 ;
  wire \lowCL1_reg[31]_5 ;
  wire \lowCL1_reg[31]_6 ;
  wire \lowCL1_reg[31]_7 ;
  wire \lowCL1_reg[31]_8 ;
  wire \lowCL1_reg[32]_0 ;
  wire \lowCL1_reg[32]_1 ;
  wire \lowCL1_reg[32]_2 ;
  wire [2:0]\lowCL1_reg[32]_3 ;
  wire \lowCL1_reg[32]_4 ;
  wire \lowCL1_reg[32]_5 ;
  wire \lowCL1_reg[32]_6 ;
  wire \lowCL1_reg[32]_7 ;
  wire \lowCL1_reg[33]_0 ;
  wire \lowCL1_reg[36]_0 ;
  wire \lowCL1_reg[37]_0 ;
  wire \lowCL1_reg[37]_1 ;
  wire [0:0]\lowCL1_reg[37]_2 ;
  wire \lowCL1_reg[37]_3 ;
  wire \lowCL1_reg[37]_4 ;
  wire \lowCL1_reg[37]_5 ;
  wire \lowCL1_reg[37]_6 ;
  wire \lowCL1_reg[37]_7 ;
  wire \lowCL1_reg[37]_8 ;
  wire \lowCL1_reg[38]_0 ;
  wire \lowCL1_reg[38]_1 ;
  wire \lowCL1_reg[38]_2 ;
  wire [2:0]\lowCL1_reg[38]_3 ;
  wire \lowCL1_reg[38]_4 ;
  wire \lowCL1_reg[38]_5 ;
  wire \lowCL1_reg[38]_6 ;
  wire \lowCL1_reg[38]_7 ;
  wire \lowCL1_reg[39]_0 ;
  wire \lowCL1_reg[3]_0 ;
  wire \lowCL1_reg[42]_0 ;
  wire \lowCL1_reg[43]_0 ;
  wire \lowCL1_reg[43]_1 ;
  wire [0:0]\lowCL1_reg[43]_2 ;
  wire \lowCL1_reg[43]_3 ;
  wire \lowCL1_reg[43]_4 ;
  wire \lowCL1_reg[43]_5 ;
  wire \lowCL1_reg[43]_6 ;
  wire \lowCL1_reg[43]_7 ;
  wire \lowCL1_reg[43]_8 ;
  wire \lowCL1_reg[44]_0 ;
  wire \lowCL1_reg[44]_1 ;
  wire \lowCL1_reg[44]_2 ;
  wire [2:0]\lowCL1_reg[44]_3 ;
  wire \lowCL1_reg[44]_4 ;
  wire \lowCL1_reg[44]_5 ;
  wire \lowCL1_reg[44]_6 ;
  wire \lowCL1_reg[44]_7 ;
  wire \lowCL1_reg[45]_0 ;
  wire \lowCL1_reg[6]_0 ;
  wire \lowCL1_reg[7]_0 ;
  wire \lowCL1_reg[7]_1 ;
  wire [0:0]\lowCL1_reg[7]_2 ;
  wire \lowCL1_reg[7]_3 ;
  wire \lowCL1_reg[7]_4 ;
  wire \lowCL1_reg[7]_5 ;
  wire \lowCL1_reg[7]_6 ;
  wire \lowCL1_reg[7]_7 ;
  wire \lowCL1_reg[7]_8 ;
  wire \lowCL1_reg[8]_0 ;
  wire \lowCL1_reg[8]_1 ;
  wire \lowCL1_reg[8]_2 ;
  wire [2:0]\lowCL1_reg[8]_3 ;
  wire \lowCL1_reg[8]_4 ;
  wire \lowCL1_reg[8]_5 ;
  wire \lowCL1_reg[8]_6 ;
  wire \lowCL1_reg[8]_7 ;
  wire \lowCL1_reg[9]_0 ;
  wire [45:0]lowCL2;
  wire \lowCL2_reg[0]_0 ;
  wire \lowCL2_reg[12]_0 ;
  wire \lowCL2_reg[13]_0 ;
  wire \lowCL2_reg[13]_1 ;
  wire [0:0]\lowCL2_reg[13]_2 ;
  wire \lowCL2_reg[13]_3 ;
  wire \lowCL2_reg[13]_4 ;
  wire \lowCL2_reg[13]_5 ;
  wire \lowCL2_reg[13]_6 ;
  wire \lowCL2_reg[13]_7 ;
  wire \lowCL2_reg[13]_8 ;
  wire \lowCL2_reg[14]_0 ;
  wire \lowCL2_reg[14]_1 ;
  wire \lowCL2_reg[14]_2 ;
  wire [2:0]\lowCL2_reg[14]_3 ;
  wire \lowCL2_reg[14]_4 ;
  wire \lowCL2_reg[14]_5 ;
  wire \lowCL2_reg[14]_6 ;
  wire \lowCL2_reg[14]_7 ;
  wire \lowCL2_reg[15]_0 ;
  wire \lowCL2_reg[18]_0 ;
  wire \lowCL2_reg[19]_0 ;
  wire \lowCL2_reg[19]_1 ;
  wire [0:0]\lowCL2_reg[19]_2 ;
  wire \lowCL2_reg[19]_3 ;
  wire \lowCL2_reg[19]_4 ;
  wire \lowCL2_reg[19]_5 ;
  wire \lowCL2_reg[19]_6 ;
  wire \lowCL2_reg[19]_7 ;
  wire \lowCL2_reg[19]_8 ;
  wire \lowCL2_reg[1]_0 ;
  wire \lowCL2_reg[1]_1 ;
  wire [0:0]\lowCL2_reg[1]_2 ;
  wire \lowCL2_reg[1]_3 ;
  wire \lowCL2_reg[1]_4 ;
  wire \lowCL2_reg[1]_5 ;
  wire \lowCL2_reg[1]_6 ;
  wire \lowCL2_reg[1]_7 ;
  wire \lowCL2_reg[1]_8 ;
  wire \lowCL2_reg[20]_0 ;
  wire \lowCL2_reg[20]_1 ;
  wire \lowCL2_reg[20]_2 ;
  wire [2:0]\lowCL2_reg[20]_3 ;
  wire \lowCL2_reg[20]_4 ;
  wire \lowCL2_reg[20]_5 ;
  wire \lowCL2_reg[20]_6 ;
  wire \lowCL2_reg[20]_7 ;
  wire \lowCL2_reg[21]_0 ;
  wire \lowCL2_reg[24]_0 ;
  wire \lowCL2_reg[25]_0 ;
  wire \lowCL2_reg[25]_1 ;
  wire [0:0]\lowCL2_reg[25]_2 ;
  wire \lowCL2_reg[25]_3 ;
  wire \lowCL2_reg[25]_4 ;
  wire \lowCL2_reg[25]_5 ;
  wire \lowCL2_reg[25]_6 ;
  wire \lowCL2_reg[25]_7 ;
  wire \lowCL2_reg[25]_8 ;
  wire \lowCL2_reg[26]_0 ;
  wire \lowCL2_reg[26]_1 ;
  wire \lowCL2_reg[26]_2 ;
  wire [2:0]\lowCL2_reg[26]_3 ;
  wire \lowCL2_reg[26]_4 ;
  wire \lowCL2_reg[26]_5 ;
  wire \lowCL2_reg[26]_6 ;
  wire \lowCL2_reg[26]_7 ;
  wire \lowCL2_reg[27]_0 ;
  wire \lowCL2_reg[2]_0 ;
  wire \lowCL2_reg[2]_1 ;
  wire \lowCL2_reg[2]_2 ;
  wire [2:0]\lowCL2_reg[2]_3 ;
  wire \lowCL2_reg[2]_4 ;
  wire \lowCL2_reg[2]_5 ;
  wire \lowCL2_reg[2]_6 ;
  wire \lowCL2_reg[2]_7 ;
  wire \lowCL2_reg[30]_0 ;
  wire \lowCL2_reg[31]_0 ;
  wire \lowCL2_reg[31]_1 ;
  wire [0:0]\lowCL2_reg[31]_2 ;
  wire \lowCL2_reg[31]_3 ;
  wire \lowCL2_reg[31]_4 ;
  wire \lowCL2_reg[31]_5 ;
  wire \lowCL2_reg[31]_6 ;
  wire \lowCL2_reg[31]_7 ;
  wire \lowCL2_reg[31]_8 ;
  wire \lowCL2_reg[32]_0 ;
  wire \lowCL2_reg[32]_1 ;
  wire \lowCL2_reg[32]_2 ;
  wire [2:0]\lowCL2_reg[32]_3 ;
  wire \lowCL2_reg[32]_4 ;
  wire \lowCL2_reg[32]_5 ;
  wire \lowCL2_reg[32]_6 ;
  wire \lowCL2_reg[32]_7 ;
  wire \lowCL2_reg[33]_0 ;
  wire \lowCL2_reg[36]_0 ;
  wire \lowCL2_reg[37]_0 ;
  wire \lowCL2_reg[37]_1 ;
  wire [0:0]\lowCL2_reg[37]_2 ;
  wire \lowCL2_reg[37]_3 ;
  wire \lowCL2_reg[37]_4 ;
  wire \lowCL2_reg[37]_5 ;
  wire \lowCL2_reg[37]_6 ;
  wire \lowCL2_reg[37]_7 ;
  wire \lowCL2_reg[37]_8 ;
  wire \lowCL2_reg[38]_0 ;
  wire \lowCL2_reg[38]_1 ;
  wire \lowCL2_reg[38]_2 ;
  wire [2:0]\lowCL2_reg[38]_3 ;
  wire \lowCL2_reg[38]_4 ;
  wire \lowCL2_reg[38]_5 ;
  wire \lowCL2_reg[38]_6 ;
  wire \lowCL2_reg[38]_7 ;
  wire \lowCL2_reg[39]_0 ;
  wire \lowCL2_reg[3]_0 ;
  wire \lowCL2_reg[42]_0 ;
  wire \lowCL2_reg[43]_0 ;
  wire \lowCL2_reg[43]_1 ;
  wire [0:0]\lowCL2_reg[43]_2 ;
  wire \lowCL2_reg[43]_3 ;
  wire \lowCL2_reg[43]_4 ;
  wire \lowCL2_reg[43]_5 ;
  wire \lowCL2_reg[43]_6 ;
  wire \lowCL2_reg[43]_7 ;
  wire \lowCL2_reg[43]_8 ;
  wire \lowCL2_reg[44]_0 ;
  wire \lowCL2_reg[44]_1 ;
  wire \lowCL2_reg[44]_2 ;
  wire [2:0]\lowCL2_reg[44]_3 ;
  wire \lowCL2_reg[44]_4 ;
  wire \lowCL2_reg[44]_5 ;
  wire \lowCL2_reg[44]_6 ;
  wire \lowCL2_reg[44]_7 ;
  wire \lowCL2_reg[45]_0 ;
  wire \lowCL2_reg[6]_0 ;
  wire \lowCL2_reg[7]_0 ;
  wire \lowCL2_reg[7]_1 ;
  wire [0:0]\lowCL2_reg[7]_2 ;
  wire \lowCL2_reg[7]_3 ;
  wire \lowCL2_reg[7]_4 ;
  wire \lowCL2_reg[7]_5 ;
  wire \lowCL2_reg[7]_6 ;
  wire \lowCL2_reg[7]_7 ;
  wire \lowCL2_reg[7]_8 ;
  wire \lowCL2_reg[8]_0 ;
  wire \lowCL2_reg[8]_1 ;
  wire \lowCL2_reg[8]_2 ;
  wire [2:0]\lowCL2_reg[8]_3 ;
  wire \lowCL2_reg[8]_4 ;
  wire \lowCL2_reg[8]_5 ;
  wire \lowCL2_reg[8]_6 ;
  wire \lowCL2_reg[8]_7 ;
  wire \lowCL2_reg[9]_0 ;
  wire [45:0]lowCL3;
  wire \lowCL3_reg[0]_0 ;
  wire \lowCL3_reg[12]_0 ;
  wire \lowCL3_reg[13]_0 ;
  wire \lowCL3_reg[13]_1 ;
  wire [0:0]\lowCL3_reg[13]_2 ;
  wire \lowCL3_reg[13]_3 ;
  wire \lowCL3_reg[13]_4 ;
  wire \lowCL3_reg[13]_5 ;
  wire \lowCL3_reg[13]_6 ;
  wire \lowCL3_reg[13]_7 ;
  wire \lowCL3_reg[13]_8 ;
  wire \lowCL3_reg[14]_0 ;
  wire \lowCL3_reg[14]_1 ;
  wire \lowCL3_reg[14]_2 ;
  wire [2:0]\lowCL3_reg[14]_3 ;
  wire \lowCL3_reg[14]_4 ;
  wire \lowCL3_reg[14]_5 ;
  wire \lowCL3_reg[14]_6 ;
  wire \lowCL3_reg[14]_7 ;
  wire \lowCL3_reg[15]_0 ;
  wire \lowCL3_reg[18]_0 ;
  wire \lowCL3_reg[19]_0 ;
  wire \lowCL3_reg[19]_1 ;
  wire [0:0]\lowCL3_reg[19]_2 ;
  wire \lowCL3_reg[19]_3 ;
  wire \lowCL3_reg[19]_4 ;
  wire \lowCL3_reg[19]_5 ;
  wire \lowCL3_reg[19]_6 ;
  wire \lowCL3_reg[19]_7 ;
  wire \lowCL3_reg[19]_8 ;
  wire \lowCL3_reg[1]_0 ;
  wire \lowCL3_reg[1]_1 ;
  wire [0:0]\lowCL3_reg[1]_2 ;
  wire \lowCL3_reg[1]_3 ;
  wire \lowCL3_reg[1]_4 ;
  wire \lowCL3_reg[1]_5 ;
  wire \lowCL3_reg[1]_6 ;
  wire \lowCL3_reg[1]_7 ;
  wire \lowCL3_reg[1]_8 ;
  wire \lowCL3_reg[20]_0 ;
  wire \lowCL3_reg[20]_1 ;
  wire \lowCL3_reg[20]_2 ;
  wire [2:0]\lowCL3_reg[20]_3 ;
  wire \lowCL3_reg[20]_4 ;
  wire \lowCL3_reg[20]_5 ;
  wire \lowCL3_reg[20]_6 ;
  wire \lowCL3_reg[20]_7 ;
  wire \lowCL3_reg[21]_0 ;
  wire \lowCL3_reg[24]_0 ;
  wire \lowCL3_reg[25]_0 ;
  wire \lowCL3_reg[25]_1 ;
  wire [0:0]\lowCL3_reg[25]_2 ;
  wire \lowCL3_reg[25]_3 ;
  wire \lowCL3_reg[25]_4 ;
  wire \lowCL3_reg[25]_5 ;
  wire \lowCL3_reg[25]_6 ;
  wire \lowCL3_reg[25]_7 ;
  wire \lowCL3_reg[25]_8 ;
  wire \lowCL3_reg[26]_0 ;
  wire \lowCL3_reg[26]_1 ;
  wire \lowCL3_reg[26]_2 ;
  wire [2:0]\lowCL3_reg[26]_3 ;
  wire \lowCL3_reg[26]_4 ;
  wire \lowCL3_reg[26]_5 ;
  wire \lowCL3_reg[26]_6 ;
  wire \lowCL3_reg[26]_7 ;
  wire \lowCL3_reg[27]_0 ;
  wire \lowCL3_reg[2]_0 ;
  wire \lowCL3_reg[2]_1 ;
  wire \lowCL3_reg[2]_2 ;
  wire [2:0]\lowCL3_reg[2]_3 ;
  wire \lowCL3_reg[2]_4 ;
  wire \lowCL3_reg[2]_5 ;
  wire \lowCL3_reg[2]_6 ;
  wire \lowCL3_reg[2]_7 ;
  wire \lowCL3_reg[30]_0 ;
  wire \lowCL3_reg[31]_0 ;
  wire \lowCL3_reg[31]_1 ;
  wire [0:0]\lowCL3_reg[31]_2 ;
  wire \lowCL3_reg[31]_3 ;
  wire \lowCL3_reg[31]_4 ;
  wire \lowCL3_reg[31]_5 ;
  wire \lowCL3_reg[31]_6 ;
  wire \lowCL3_reg[31]_7 ;
  wire \lowCL3_reg[31]_8 ;
  wire \lowCL3_reg[32]_0 ;
  wire \lowCL3_reg[32]_1 ;
  wire \lowCL3_reg[32]_2 ;
  wire [2:0]\lowCL3_reg[32]_3 ;
  wire \lowCL3_reg[32]_4 ;
  wire \lowCL3_reg[32]_5 ;
  wire \lowCL3_reg[32]_6 ;
  wire \lowCL3_reg[32]_7 ;
  wire \lowCL3_reg[33]_0 ;
  wire \lowCL3_reg[36]_0 ;
  wire \lowCL3_reg[37]_0 ;
  wire \lowCL3_reg[37]_1 ;
  wire [0:0]\lowCL3_reg[37]_2 ;
  wire \lowCL3_reg[37]_3 ;
  wire \lowCL3_reg[37]_4 ;
  wire \lowCL3_reg[37]_5 ;
  wire \lowCL3_reg[37]_6 ;
  wire \lowCL3_reg[37]_7 ;
  wire \lowCL3_reg[37]_8 ;
  wire \lowCL3_reg[38]_0 ;
  wire \lowCL3_reg[38]_1 ;
  wire \lowCL3_reg[38]_2 ;
  wire [2:0]\lowCL3_reg[38]_3 ;
  wire \lowCL3_reg[38]_4 ;
  wire \lowCL3_reg[38]_5 ;
  wire \lowCL3_reg[38]_6 ;
  wire \lowCL3_reg[38]_7 ;
  wire \lowCL3_reg[39]_0 ;
  wire \lowCL3_reg[3]_0 ;
  wire \lowCL3_reg[42]_0 ;
  wire \lowCL3_reg[43]_0 ;
  wire \lowCL3_reg[43]_1 ;
  wire [0:0]\lowCL3_reg[43]_2 ;
  wire \lowCL3_reg[43]_3 ;
  wire \lowCL3_reg[43]_4 ;
  wire \lowCL3_reg[43]_5 ;
  wire \lowCL3_reg[43]_6 ;
  wire \lowCL3_reg[43]_7 ;
  wire \lowCL3_reg[43]_8 ;
  wire \lowCL3_reg[44]_0 ;
  wire \lowCL3_reg[44]_1 ;
  wire \lowCL3_reg[44]_2 ;
  wire [2:0]\lowCL3_reg[44]_3 ;
  wire \lowCL3_reg[44]_4 ;
  wire \lowCL3_reg[44]_5 ;
  wire \lowCL3_reg[44]_6 ;
  wire \lowCL3_reg[44]_7 ;
  wire \lowCL3_reg[45]_0 ;
  wire \lowCL3_reg[6]_0 ;
  wire \lowCL3_reg[7]_0 ;
  wire \lowCL3_reg[7]_1 ;
  wire [0:0]\lowCL3_reg[7]_2 ;
  wire \lowCL3_reg[7]_3 ;
  wire \lowCL3_reg[7]_4 ;
  wire \lowCL3_reg[7]_5 ;
  wire \lowCL3_reg[7]_6 ;
  wire \lowCL3_reg[7]_7 ;
  wire \lowCL3_reg[7]_8 ;
  wire \lowCL3_reg[8]_0 ;
  wire \lowCL3_reg[8]_1 ;
  wire \lowCL3_reg[8]_2 ;
  wire [2:0]\lowCL3_reg[8]_3 ;
  wire \lowCL3_reg[8]_4 ;
  wire \lowCL3_reg[8]_5 ;
  wire \lowCL3_reg[8]_6 ;
  wire \lowCL3_reg[8]_7 ;
  wire \lowCL3_reg[9]_0 ;
  wire lrdimm_cal_mode_reg;
  wire lrdimm_cal_mode_reg_0;
  wire lrdimm_cal_mode_reg_1;
  wire lrdimm_cmp_clr;
  wire lrdimm_cmp_en_reg;
  wire lrdimm_cmp_en_reg_0;
  wire [5:0]max_rd_lat;
  wire [0:0]\max_rd_lat_reg[5]_0 ;
  wire mcCasSlot2;
  wire mcRdCAS;
  wire mcWrCAS;
  wire [35:0]mc_ADR;
  wire [6:0]mc_BA;
  wire [2:0]mc_BG;
  wire [1:0]mc_CKE;
  wire mc_CKE7;
  wire [0:0]mc_CS_n;
  wire mc_CS_n7;
  wire [0:0]mc_ODT;
  wire mc_ODT7;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_11_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_12_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_13_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_14_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_15_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_16_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_17_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_18_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_19_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_20_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_21_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_22_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_23_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_24_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_2_n_0 ;
  wire [31:0]\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_3_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_5_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_6_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_7_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_8_n_0 ;
  wire \mc_clb2phy_fifo_rden_nxt[103]_i_9_n_0 ;
  wire [0:0]mcalCasSlot;
  wire [1:0]mcalRank;
  wire mcalRdCAS;
  wire [4:0]\mcal_ADR_dly_reg[0][128] ;
  wire [4:0]\mcal_ADR_dly_reg[0][135] ;
  wire [6:0]\mcal_DMIn_bit_r1_reg[7] ;
  wire [63:0]\mcal_DMIn_n_r_reg[63] ;
  wire \mcal_DQIn_byte_r1_reg[31] ;
  wire [9:0]\mcal_DQIn_byte_r1_reg[48] ;
  wire [511:0]\mcal_DQIn_r_reg[511] ;
  wire \mcal_PAR_dly[0][0]_i_2_n_0 ;
  wire \mcal_PAR_dly_reg[0][0] ;
  wire \mcal_PAR_dly_reg[0][1] ;
  wire \mcal_PAR_dly_reg[0][3] ;
  wire \mcal_PAR_dly_reg[0][5] ;
  wire \mcal_PAR_dly_reg[0][7] ;
  wire [55:0]mcal_rd_vref_value;
  wire mem_reg_bram_0;
  wire [36:0]out;
  wire [111:111]p_0_in1_in;
  wire [0:0]p_1_in;
  wire [132:7]p_2_out;
  wire p_52_in;
  wire pllGate;
  wire rdCAS_reg;
  wire rdDataEn_pi;
  wire \rdEn_reg[28] ;
  wire \rdEn_reg[28]_0 ;
  wire \rdEn_reg[28]_1 ;
  wire \rdEn_reg[28]_10 ;
  wire \rdEn_reg[28]_11 ;
  wire \rdEn_reg[28]_12 ;
  wire \rdEn_reg[28]_2 ;
  wire \rdEn_reg[28]_3 ;
  wire \rdEn_reg[28]_4 ;
  wire \rdEn_reg[28]_5 ;
  wire \rdEn_reg[28]_6 ;
  wire \rdEn_reg[28]_7 ;
  wire \rdEn_reg[28]_8 ;
  wire \rdEn_reg[28]_9 ;
  wire \rdEn_reg[29] ;
  wire \rdEn_reg[29]_0 ;
  wire \rdEn_reg[29]_1 ;
  wire \rdEn_reg[29]_10 ;
  wire \rdEn_reg[29]_11 ;
  wire \rdEn_reg[29]_12 ;
  wire \rdEn_reg[29]_13 ;
  wire \rdEn_reg[29]_2 ;
  wire \rdEn_reg[29]_3 ;
  wire \rdEn_reg[29]_4 ;
  wire \rdEn_reg[29]_5 ;
  wire \rdEn_reg[29]_6 ;
  wire \rdEn_reg[29]_7 ;
  wire \rdEn_reg[29]_8 ;
  wire \rdEn_reg[29]_9 ;
  wire [7:0]rd_vref_value0_out;
  wire \rd_vref_value_reg[42] ;
  wire \rd_vref_value_reg[43] ;
  wire \rd_vref_value_reg[44] ;
  wire \rd_vref_value_reg[45] ;
  wire \rd_vref_value_reg[46] ;
  wire \rd_vref_value_reg[48] ;
  wire read_lat_shift_cal_dq_valid_nxt;
  wire [3:0]retSt;
  wire \retSt[0]_i_1_n_0 ;
  wire \retSt[1]_i_1_n_0 ;
  wire \retSt[2]_i_1_n_0 ;
  wire \retSt[3]_i_2_n_0 ;
  wire \retSt[3]_i_3_n_0 ;
  wire [4:0]rs2mask0;
  wire [4:0]rs2mask0_10;
  wire [4:0]rs2mask0_12;
  wire [4:0]rs2mask0_14;
  wire [4:0]rs2mask0_16;
  wire [4:0]rs2mask0_18;
  wire [4:0]rs2mask0_2;
  wire [4:0]rs2mask0_20;
  wire [4:0]rs2mask0_22;
  wire [4:0]rs2mask0_24;
  wire [4:0]rs2mask0_26;
  wire [4:0]rs2mask0_4;
  wire [4:0]rs2mask0_6;
  wire [4:0]rs2mask0_8;
  wire [3:0]rs2mask0__0;
  wire [3:0]rs2mask0__0_0;
  wire [1:0]\rsMask_reg[1]_71 ;
  wire [1:0]\rsMask_reg[1]_79 ;
  wire [1:0]\rsMask_reg[3]_73 ;
  wire [1:0]\rsMask_reg[3]_81 ;
  wire [1:0]\rsMask_reg[5]_75 ;
  wire [1:0]\rsMask_reg[5]_83 ;
  wire [1:0]\rsMask_reg[7][18] ;
  wire [1:0]\rsMask_reg[7]_77 ;
  wire [1:0]\rsMask_reg[7]_85 ;
  (* RTL_KEEP = "true" *) wire rst_r1;
  wire rst_r1_reg_0;
  wire rst_r1_reg_1;
  wire [1:0]rst_r1_reg_10;
  wire [1:0]rst_r1_reg_11;
  wire [1:0]rst_r1_reg_12;
  wire [1:0]rst_r1_reg_13;
  wire [1:0]rst_r1_reg_14;
  wire [1:0]rst_r1_reg_15;
  wire [1:0]rst_r1_reg_2;
  wire [1:0]rst_r1_reg_3;
  wire [1:0]rst_r1_reg_4;
  wire [1:0]rst_r1_reg_5;
  wire [1:0]rst_r1_reg_6;
  wire [1:0]rst_r1_reg_7;
  wire [1:0]rst_r1_reg_8;
  wire [1:0]rst_r1_reg_9;
  wire [15:0]s_daddr;
  wire s_dclk;
  wire s_den;
  wire [15:0]s_di;
  wire [8:0]s_do;
  wire s_drdy;
  wire s_dwe;
  wire [16:0]sl_oport_o;
  wire stop_gate_tracking_ack_reg;
  wire stop_gate_tracking_ack_reg_0;
  wire t1;
  wire t2;
  wire [0:0]\traffic_instr_nxt_instr_r1_reg[5] ;
  wire u_ddr_cal_addr_decode_n_50;
  wire u_ddr_cal_addr_decode_n_51;
  wire u_ddr_cal_addr_decode_n_52;
  wire [3:2]\u_ddr_mc_pi/u_ddr_mc_read/read_lat_shift_rptr__8 ;
  wire ub_initDone_reg;
  wire [45:0]ub_lowCL0;
  wire [45:0]ub_lowCL1;
  wire [45:0]ub_lowCL2;
  wire [45:0]ub_lowCL3;
  wire [5:0]ub_max_rd_lat;
  wire [2:0]ub_ready_reg;
  wire ub_ready_reg_0;
  wire [45:0]ub_uppCL0;
  wire [45:0]ub_uppCL1;
  wire [45:0]ub_uppCL2;
  wire [45:0]ub_uppCL3;
  wire [8:0]ub_xsdb_wr_data;
  wire ub_xsdb_wr_en;
  wire [42:0]uppCL0;
  wire \uppCL0_reg[0]_0 ;
  wire \uppCL0_reg[12]_0 ;
  wire \uppCL0_reg[13]_0 ;
  wire \uppCL0_reg[13]_1 ;
  wire \uppCL0_reg[13]_2 ;
  wire \uppCL0_reg[14]_0 ;
  wire \uppCL0_reg[14]_1 ;
  wire \uppCL0_reg[14]_2 ;
  wire [2:0]\uppCL0_reg[14]_3 ;
  wire \uppCL0_reg[14]_4 ;
  wire \uppCL0_reg[14]_5 ;
  wire \uppCL0_reg[14]_6 ;
  wire \uppCL0_reg[15]_0 ;
  wire \uppCL0_reg[18]_0 ;
  wire \uppCL0_reg[19]_0 ;
  wire \uppCL0_reg[19]_1 ;
  wire \uppCL0_reg[19]_2 ;
  wire \uppCL0_reg[1]_0 ;
  wire \uppCL0_reg[1]_1 ;
  wire \uppCL0_reg[1]_2 ;
  wire \uppCL0_reg[20]_0 ;
  wire \uppCL0_reg[20]_1 ;
  wire \uppCL0_reg[20]_2 ;
  wire [2:0]\uppCL0_reg[20]_3 ;
  wire \uppCL0_reg[20]_4 ;
  wire \uppCL0_reg[20]_5 ;
  wire \uppCL0_reg[20]_6 ;
  wire \uppCL0_reg[21]_0 ;
  wire \uppCL0_reg[24]_0 ;
  wire \uppCL0_reg[25]_0 ;
  wire \uppCL0_reg[25]_1 ;
  wire \uppCL0_reg[25]_2 ;
  wire \uppCL0_reg[26]_0 ;
  wire \uppCL0_reg[26]_1 ;
  wire \uppCL0_reg[26]_2 ;
  wire [2:0]\uppCL0_reg[26]_3 ;
  wire \uppCL0_reg[26]_4 ;
  wire \uppCL0_reg[26]_5 ;
  wire \uppCL0_reg[26]_6 ;
  wire \uppCL0_reg[27]_0 ;
  wire \uppCL0_reg[2]_0 ;
  wire \uppCL0_reg[2]_1 ;
  wire \uppCL0_reg[2]_2 ;
  wire [2:0]\uppCL0_reg[2]_3 ;
  wire \uppCL0_reg[2]_4 ;
  wire \uppCL0_reg[2]_5 ;
  wire \uppCL0_reg[2]_6 ;
  wire \uppCL0_reg[30]_0 ;
  wire \uppCL0_reg[31]_0 ;
  wire \uppCL0_reg[31]_1 ;
  wire \uppCL0_reg[31]_2 ;
  wire \uppCL0_reg[32]_0 ;
  wire \uppCL0_reg[32]_1 ;
  wire \uppCL0_reg[32]_2 ;
  wire [2:0]\uppCL0_reg[32]_3 ;
  wire \uppCL0_reg[32]_4 ;
  wire \uppCL0_reg[32]_5 ;
  wire \uppCL0_reg[32]_6 ;
  wire \uppCL0_reg[33]_0 ;
  wire \uppCL0_reg[36]_0 ;
  wire \uppCL0_reg[37]_0 ;
  wire \uppCL0_reg[37]_1 ;
  wire \uppCL0_reg[37]_2 ;
  wire \uppCL0_reg[38]_0 ;
  wire \uppCL0_reg[38]_1 ;
  wire \uppCL0_reg[38]_2 ;
  wire [2:0]\uppCL0_reg[38]_3 ;
  wire \uppCL0_reg[38]_4 ;
  wire \uppCL0_reg[38]_5 ;
  wire \uppCL0_reg[38]_6 ;
  wire \uppCL0_reg[39]_0 ;
  wire \uppCL0_reg[3]_0 ;
  wire \uppCL0_reg[42]_0 ;
  wire \uppCL0_reg[43]_0 ;
  wire \uppCL0_reg[43]_1 ;
  wire \uppCL0_reg[43]_2 ;
  wire \uppCL0_reg[44]_0 ;
  wire \uppCL0_reg[44]_1 ;
  wire \uppCL0_reg[44]_2 ;
  wire \uppCL0_reg[44]_3 ;
  wire \uppCL0_reg[44]_4 ;
  wire \uppCL0_reg[44]_5 ;
  wire [2:0]\uppCL0_reg[44]_6 ;
  wire [5:0]\uppCL0_reg[45]_0 ;
  wire \uppCL0_reg[45]_1 ;
  wire [9:0]\uppCL0_reg[47] ;
  wire \uppCL0_reg[6]_0 ;
  wire \uppCL0_reg[7]_0 ;
  wire \uppCL0_reg[7]_1 ;
  wire \uppCL0_reg[7]_2 ;
  wire \uppCL0_reg[8]_0 ;
  wire \uppCL0_reg[8]_1 ;
  wire \uppCL0_reg[8]_2 ;
  wire \uppCL0_reg[8]_3 ;
  wire \uppCL0_reg[8]_4 ;
  wire \uppCL0_reg[8]_5 ;
  wire [2:0]\uppCL0_reg[8]_6 ;
  wire \uppCL0_reg[9]_0 ;
  wire [42:0]uppCL1;
  wire \uppCL1_reg[0]_0 ;
  wire \uppCL1_reg[12]_0 ;
  wire \uppCL1_reg[13]_0 ;
  wire \uppCL1_reg[13]_1 ;
  wire [0:0]\uppCL1_reg[13]_2 ;
  wire \uppCL1_reg[13]_3 ;
  wire \uppCL1_reg[13]_4 ;
  wire \uppCL1_reg[13]_5 ;
  wire \uppCL1_reg[13]_6 ;
  wire \uppCL1_reg[13]_7 ;
  wire \uppCL1_reg[13]_8 ;
  wire \uppCL1_reg[14]_0 ;
  wire \uppCL1_reg[14]_1 ;
  wire \uppCL1_reg[14]_2 ;
  wire [2:0]\uppCL1_reg[14]_3 ;
  wire \uppCL1_reg[14]_4 ;
  wire \uppCL1_reg[14]_5 ;
  wire \uppCL1_reg[14]_6 ;
  wire \uppCL1_reg[14]_7 ;
  wire \uppCL1_reg[15]_0 ;
  wire \uppCL1_reg[18]_0 ;
  wire \uppCL1_reg[19]_0 ;
  wire \uppCL1_reg[19]_1 ;
  wire [0:0]\uppCL1_reg[19]_2 ;
  wire \uppCL1_reg[19]_3 ;
  wire \uppCL1_reg[19]_4 ;
  wire \uppCL1_reg[19]_5 ;
  wire \uppCL1_reg[19]_6 ;
  wire \uppCL1_reg[19]_7 ;
  wire \uppCL1_reg[19]_8 ;
  wire \uppCL1_reg[1]_0 ;
  wire \uppCL1_reg[1]_1 ;
  wire [0:0]\uppCL1_reg[1]_2 ;
  wire \uppCL1_reg[1]_3 ;
  wire \uppCL1_reg[1]_4 ;
  wire \uppCL1_reg[1]_5 ;
  wire \uppCL1_reg[1]_6 ;
  wire \uppCL1_reg[1]_7 ;
  wire \uppCL1_reg[1]_8 ;
  wire \uppCL1_reg[20]_0 ;
  wire \uppCL1_reg[20]_1 ;
  wire \uppCL1_reg[20]_2 ;
  wire [2:0]\uppCL1_reg[20]_3 ;
  wire \uppCL1_reg[20]_4 ;
  wire \uppCL1_reg[20]_5 ;
  wire \uppCL1_reg[20]_6 ;
  wire \uppCL1_reg[20]_7 ;
  wire \uppCL1_reg[21]_0 ;
  wire \uppCL1_reg[24]_0 ;
  wire \uppCL1_reg[25]_0 ;
  wire \uppCL1_reg[25]_1 ;
  wire [0:0]\uppCL1_reg[25]_2 ;
  wire \uppCL1_reg[25]_3 ;
  wire \uppCL1_reg[25]_4 ;
  wire \uppCL1_reg[25]_5 ;
  wire \uppCL1_reg[25]_6 ;
  wire \uppCL1_reg[25]_7 ;
  wire \uppCL1_reg[25]_8 ;
  wire \uppCL1_reg[26]_0 ;
  wire \uppCL1_reg[26]_1 ;
  wire \uppCL1_reg[26]_2 ;
  wire [2:0]\uppCL1_reg[26]_3 ;
  wire \uppCL1_reg[26]_4 ;
  wire \uppCL1_reg[26]_5 ;
  wire \uppCL1_reg[26]_6 ;
  wire \uppCL1_reg[26]_7 ;
  wire \uppCL1_reg[27]_0 ;
  wire \uppCL1_reg[2]_0 ;
  wire \uppCL1_reg[2]_1 ;
  wire \uppCL1_reg[2]_2 ;
  wire [2:0]\uppCL1_reg[2]_3 ;
  wire \uppCL1_reg[2]_4 ;
  wire \uppCL1_reg[2]_5 ;
  wire \uppCL1_reg[2]_6 ;
  wire \uppCL1_reg[2]_7 ;
  wire \uppCL1_reg[30]_0 ;
  wire \uppCL1_reg[31]_0 ;
  wire \uppCL1_reg[31]_1 ;
  wire [0:0]\uppCL1_reg[31]_2 ;
  wire \uppCL1_reg[31]_3 ;
  wire \uppCL1_reg[31]_4 ;
  wire \uppCL1_reg[31]_5 ;
  wire \uppCL1_reg[31]_6 ;
  wire \uppCL1_reg[31]_7 ;
  wire \uppCL1_reg[31]_8 ;
  wire \uppCL1_reg[32]_0 ;
  wire \uppCL1_reg[32]_1 ;
  wire \uppCL1_reg[32]_2 ;
  wire [2:0]\uppCL1_reg[32]_3 ;
  wire \uppCL1_reg[32]_4 ;
  wire \uppCL1_reg[32]_5 ;
  wire \uppCL1_reg[32]_6 ;
  wire \uppCL1_reg[32]_7 ;
  wire \uppCL1_reg[33]_0 ;
  wire \uppCL1_reg[36]_0 ;
  wire \uppCL1_reg[37]_0 ;
  wire \uppCL1_reg[37]_1 ;
  wire [0:0]\uppCL1_reg[37]_2 ;
  wire \uppCL1_reg[37]_3 ;
  wire \uppCL1_reg[37]_4 ;
  wire \uppCL1_reg[37]_5 ;
  wire \uppCL1_reg[37]_6 ;
  wire \uppCL1_reg[37]_7 ;
  wire \uppCL1_reg[37]_8 ;
  wire \uppCL1_reg[38]_0 ;
  wire \uppCL1_reg[38]_1 ;
  wire \uppCL1_reg[38]_2 ;
  wire [2:0]\uppCL1_reg[38]_3 ;
  wire \uppCL1_reg[38]_4 ;
  wire \uppCL1_reg[38]_5 ;
  wire \uppCL1_reg[38]_6 ;
  wire \uppCL1_reg[38]_7 ;
  wire \uppCL1_reg[39]_0 ;
  wire \uppCL1_reg[3]_0 ;
  wire \uppCL1_reg[42]_0 ;
  wire \uppCL1_reg[43]_0 ;
  wire \uppCL1_reg[43]_1 ;
  wire \uppCL1_reg[43]_2 ;
  wire \uppCL1_reg[43]_3 ;
  wire \uppCL1_reg[43]_4 ;
  wire \uppCL1_reg[43]_5 ;
  wire \uppCL1_reg[43]_6 ;
  wire \uppCL1_reg[43]_7 ;
  wire \uppCL1_reg[44]_0 ;
  wire \uppCL1_reg[44]_1 ;
  wire \uppCL1_reg[44]_2 ;
  wire \uppCL1_reg[44]_3 ;
  wire \uppCL1_reg[44]_4 ;
  wire \uppCL1_reg[44]_5 ;
  wire \uppCL1_reg[44]_6 ;
  wire [2:0]\uppCL1_reg[44]_7 ;
  wire [5:0]\uppCL1_reg[45]_0 ;
  wire \uppCL1_reg[45]_1 ;
  wire [9:0]\uppCL1_reg[47] ;
  wire \uppCL1_reg[6]_0 ;
  wire \uppCL1_reg[7]_0 ;
  wire \uppCL1_reg[7]_1 ;
  wire \uppCL1_reg[7]_2 ;
  wire \uppCL1_reg[7]_3 ;
  wire \uppCL1_reg[7]_4 ;
  wire \uppCL1_reg[7]_5 ;
  wire \uppCL1_reg[7]_6 ;
  wire \uppCL1_reg[7]_7 ;
  wire \uppCL1_reg[8]_0 ;
  wire \uppCL1_reg[8]_1 ;
  wire \uppCL1_reg[8]_2 ;
  wire \uppCL1_reg[8]_3 ;
  wire \uppCL1_reg[8]_4 ;
  wire \uppCL1_reg[8]_5 ;
  wire \uppCL1_reg[8]_6 ;
  wire [2:0]\uppCL1_reg[8]_7 ;
  wire \uppCL1_reg[9]_0 ;
  wire [42:0]uppCL2;
  wire \uppCL2_reg[0]_0 ;
  wire \uppCL2_reg[12]_0 ;
  wire \uppCL2_reg[13]_0 ;
  wire \uppCL2_reg[13]_1 ;
  wire [0:0]\uppCL2_reg[13]_2 ;
  wire \uppCL2_reg[13]_3 ;
  wire \uppCL2_reg[13]_4 ;
  wire \uppCL2_reg[13]_5 ;
  wire \uppCL2_reg[13]_6 ;
  wire \uppCL2_reg[13]_7 ;
  wire \uppCL2_reg[13]_8 ;
  wire \uppCL2_reg[14]_0 ;
  wire \uppCL2_reg[14]_1 ;
  wire \uppCL2_reg[14]_2 ;
  wire [2:0]\uppCL2_reg[14]_3 ;
  wire \uppCL2_reg[14]_4 ;
  wire \uppCL2_reg[14]_5 ;
  wire \uppCL2_reg[14]_6 ;
  wire \uppCL2_reg[14]_7 ;
  wire \uppCL2_reg[15]_0 ;
  wire \uppCL2_reg[18]_0 ;
  wire \uppCL2_reg[19]_0 ;
  wire \uppCL2_reg[19]_1 ;
  wire [0:0]\uppCL2_reg[19]_2 ;
  wire \uppCL2_reg[19]_3 ;
  wire \uppCL2_reg[19]_4 ;
  wire \uppCL2_reg[19]_5 ;
  wire \uppCL2_reg[19]_6 ;
  wire \uppCL2_reg[19]_7 ;
  wire \uppCL2_reg[19]_8 ;
  wire \uppCL2_reg[1]_0 ;
  wire \uppCL2_reg[1]_1 ;
  wire [0:0]\uppCL2_reg[1]_2 ;
  wire \uppCL2_reg[1]_3 ;
  wire \uppCL2_reg[1]_4 ;
  wire \uppCL2_reg[1]_5 ;
  wire \uppCL2_reg[1]_6 ;
  wire \uppCL2_reg[1]_7 ;
  wire \uppCL2_reg[1]_8 ;
  wire \uppCL2_reg[20]_0 ;
  wire \uppCL2_reg[20]_1 ;
  wire \uppCL2_reg[20]_2 ;
  wire [2:0]\uppCL2_reg[20]_3 ;
  wire \uppCL2_reg[20]_4 ;
  wire \uppCL2_reg[20]_5 ;
  wire \uppCL2_reg[20]_6 ;
  wire \uppCL2_reg[20]_7 ;
  wire \uppCL2_reg[21]_0 ;
  wire \uppCL2_reg[24]_0 ;
  wire \uppCL2_reg[25]_0 ;
  wire \uppCL2_reg[25]_1 ;
  wire [0:0]\uppCL2_reg[25]_2 ;
  wire \uppCL2_reg[25]_3 ;
  wire \uppCL2_reg[25]_4 ;
  wire \uppCL2_reg[25]_5 ;
  wire \uppCL2_reg[25]_6 ;
  wire \uppCL2_reg[25]_7 ;
  wire \uppCL2_reg[25]_8 ;
  wire \uppCL2_reg[26]_0 ;
  wire \uppCL2_reg[26]_1 ;
  wire \uppCL2_reg[26]_2 ;
  wire [2:0]\uppCL2_reg[26]_3 ;
  wire \uppCL2_reg[26]_4 ;
  wire \uppCL2_reg[26]_5 ;
  wire \uppCL2_reg[26]_6 ;
  wire \uppCL2_reg[26]_7 ;
  wire \uppCL2_reg[27]_0 ;
  wire \uppCL2_reg[2]_0 ;
  wire \uppCL2_reg[2]_1 ;
  wire \uppCL2_reg[2]_2 ;
  wire [2:0]\uppCL2_reg[2]_3 ;
  wire \uppCL2_reg[2]_4 ;
  wire \uppCL2_reg[2]_5 ;
  wire \uppCL2_reg[2]_6 ;
  wire \uppCL2_reg[2]_7 ;
  wire \uppCL2_reg[30]_0 ;
  wire \uppCL2_reg[31]_0 ;
  wire \uppCL2_reg[31]_1 ;
  wire [0:0]\uppCL2_reg[31]_2 ;
  wire \uppCL2_reg[31]_3 ;
  wire \uppCL2_reg[31]_4 ;
  wire \uppCL2_reg[31]_5 ;
  wire \uppCL2_reg[31]_6 ;
  wire \uppCL2_reg[31]_7 ;
  wire \uppCL2_reg[31]_8 ;
  wire \uppCL2_reg[32]_0 ;
  wire \uppCL2_reg[32]_1 ;
  wire \uppCL2_reg[32]_2 ;
  wire [2:0]\uppCL2_reg[32]_3 ;
  wire \uppCL2_reg[32]_4 ;
  wire \uppCL2_reg[32]_5 ;
  wire \uppCL2_reg[32]_6 ;
  wire \uppCL2_reg[32]_7 ;
  wire \uppCL2_reg[33]_0 ;
  wire \uppCL2_reg[36]_0 ;
  wire \uppCL2_reg[37]_0 ;
  wire \uppCL2_reg[37]_1 ;
  wire [0:0]\uppCL2_reg[37]_2 ;
  wire \uppCL2_reg[37]_3 ;
  wire \uppCL2_reg[37]_4 ;
  wire \uppCL2_reg[37]_5 ;
  wire \uppCL2_reg[37]_6 ;
  wire \uppCL2_reg[37]_7 ;
  wire \uppCL2_reg[37]_8 ;
  wire \uppCL2_reg[38]_0 ;
  wire \uppCL2_reg[38]_1 ;
  wire \uppCL2_reg[38]_2 ;
  wire [2:0]\uppCL2_reg[38]_3 ;
  wire \uppCL2_reg[38]_4 ;
  wire \uppCL2_reg[38]_5 ;
  wire \uppCL2_reg[38]_6 ;
  wire \uppCL2_reg[38]_7 ;
  wire \uppCL2_reg[39]_0 ;
  wire \uppCL2_reg[3]_0 ;
  wire \uppCL2_reg[42]_0 ;
  wire \uppCL2_reg[43]_0 ;
  wire \uppCL2_reg[43]_1 ;
  wire \uppCL2_reg[43]_2 ;
  wire \uppCL2_reg[43]_3 ;
  wire \uppCL2_reg[43]_4 ;
  wire \uppCL2_reg[43]_5 ;
  wire \uppCL2_reg[43]_6 ;
  wire \uppCL2_reg[43]_7 ;
  wire \uppCL2_reg[44]_0 ;
  wire \uppCL2_reg[44]_1 ;
  wire \uppCL2_reg[44]_2 ;
  wire \uppCL2_reg[44]_3 ;
  wire \uppCL2_reg[44]_4 ;
  wire \uppCL2_reg[44]_5 ;
  wire \uppCL2_reg[44]_6 ;
  wire [2:0]\uppCL2_reg[44]_7 ;
  wire [5:0]\uppCL2_reg[45]_0 ;
  wire \uppCL2_reg[45]_1 ;
  wire [9:0]\uppCL2_reg[47] ;
  wire \uppCL2_reg[6]_0 ;
  wire \uppCL2_reg[7]_0 ;
  wire \uppCL2_reg[7]_1 ;
  wire \uppCL2_reg[7]_2 ;
  wire \uppCL2_reg[7]_3 ;
  wire \uppCL2_reg[7]_4 ;
  wire \uppCL2_reg[7]_5 ;
  wire \uppCL2_reg[7]_6 ;
  wire \uppCL2_reg[7]_7 ;
  wire \uppCL2_reg[8]_0 ;
  wire \uppCL2_reg[8]_1 ;
  wire \uppCL2_reg[8]_2 ;
  wire \uppCL2_reg[8]_3 ;
  wire \uppCL2_reg[8]_4 ;
  wire \uppCL2_reg[8]_5 ;
  wire \uppCL2_reg[8]_6 ;
  wire [2:0]\uppCL2_reg[8]_7 ;
  wire \uppCL2_reg[9]_0 ;
  wire [42:0]uppCL3;
  wire \uppCL3_reg[0]_0 ;
  wire \uppCL3_reg[12]_0 ;
  wire \uppCL3_reg[13]_0 ;
  wire \uppCL3_reg[13]_1 ;
  wire [0:0]\uppCL3_reg[13]_2 ;
  wire \uppCL3_reg[13]_3 ;
  wire \uppCL3_reg[13]_4 ;
  wire \uppCL3_reg[13]_5 ;
  wire \uppCL3_reg[13]_6 ;
  wire \uppCL3_reg[13]_7 ;
  wire \uppCL3_reg[13]_8 ;
  wire \uppCL3_reg[14]_0 ;
  wire \uppCL3_reg[14]_1 ;
  wire \uppCL3_reg[14]_2 ;
  wire [2:0]\uppCL3_reg[14]_3 ;
  wire \uppCL3_reg[14]_4 ;
  wire \uppCL3_reg[14]_5 ;
  wire \uppCL3_reg[14]_6 ;
  wire \uppCL3_reg[14]_7 ;
  wire \uppCL3_reg[15]_0 ;
  wire \uppCL3_reg[18]_0 ;
  wire \uppCL3_reg[19]_0 ;
  wire \uppCL3_reg[19]_1 ;
  wire [0:0]\uppCL3_reg[19]_2 ;
  wire \uppCL3_reg[19]_3 ;
  wire \uppCL3_reg[19]_4 ;
  wire \uppCL3_reg[19]_5 ;
  wire \uppCL3_reg[19]_6 ;
  wire \uppCL3_reg[19]_7 ;
  wire \uppCL3_reg[19]_8 ;
  wire \uppCL3_reg[1]_0 ;
  wire \uppCL3_reg[1]_1 ;
  wire [0:0]\uppCL3_reg[1]_2 ;
  wire \uppCL3_reg[1]_3 ;
  wire \uppCL3_reg[1]_4 ;
  wire \uppCL3_reg[1]_5 ;
  wire \uppCL3_reg[1]_6 ;
  wire \uppCL3_reg[1]_7 ;
  wire \uppCL3_reg[1]_8 ;
  wire \uppCL3_reg[20]_0 ;
  wire \uppCL3_reg[20]_1 ;
  wire \uppCL3_reg[20]_2 ;
  wire [2:0]\uppCL3_reg[20]_3 ;
  wire \uppCL3_reg[20]_4 ;
  wire \uppCL3_reg[20]_5 ;
  wire \uppCL3_reg[20]_6 ;
  wire \uppCL3_reg[20]_7 ;
  wire \uppCL3_reg[21]_0 ;
  wire \uppCL3_reg[24]_0 ;
  wire \uppCL3_reg[25]_0 ;
  wire \uppCL3_reg[25]_1 ;
  wire [0:0]\uppCL3_reg[25]_2 ;
  wire \uppCL3_reg[25]_3 ;
  wire \uppCL3_reg[25]_4 ;
  wire \uppCL3_reg[25]_5 ;
  wire \uppCL3_reg[25]_6 ;
  wire \uppCL3_reg[25]_7 ;
  wire \uppCL3_reg[25]_8 ;
  wire \uppCL3_reg[26]_0 ;
  wire \uppCL3_reg[26]_1 ;
  wire \uppCL3_reg[26]_2 ;
  wire [2:0]\uppCL3_reg[26]_3 ;
  wire \uppCL3_reg[26]_4 ;
  wire \uppCL3_reg[26]_5 ;
  wire \uppCL3_reg[26]_6 ;
  wire \uppCL3_reg[26]_7 ;
  wire \uppCL3_reg[27]_0 ;
  wire \uppCL3_reg[2]_0 ;
  wire \uppCL3_reg[2]_1 ;
  wire \uppCL3_reg[2]_2 ;
  wire [2:0]\uppCL3_reg[2]_3 ;
  wire \uppCL3_reg[2]_4 ;
  wire \uppCL3_reg[2]_5 ;
  wire \uppCL3_reg[2]_6 ;
  wire \uppCL3_reg[2]_7 ;
  wire \uppCL3_reg[30]_0 ;
  wire \uppCL3_reg[31]_0 ;
  wire \uppCL3_reg[31]_1 ;
  wire [0:0]\uppCL3_reg[31]_2 ;
  wire \uppCL3_reg[31]_3 ;
  wire \uppCL3_reg[31]_4 ;
  wire \uppCL3_reg[31]_5 ;
  wire \uppCL3_reg[31]_6 ;
  wire \uppCL3_reg[31]_7 ;
  wire \uppCL3_reg[31]_8 ;
  wire \uppCL3_reg[32]_0 ;
  wire \uppCL3_reg[32]_1 ;
  wire \uppCL3_reg[32]_2 ;
  wire [2:0]\uppCL3_reg[32]_3 ;
  wire \uppCL3_reg[32]_4 ;
  wire \uppCL3_reg[32]_5 ;
  wire \uppCL3_reg[32]_6 ;
  wire \uppCL3_reg[32]_7 ;
  wire \uppCL3_reg[33]_0 ;
  wire \uppCL3_reg[36]_0 ;
  wire \uppCL3_reg[37]_0 ;
  wire \uppCL3_reg[37]_1 ;
  wire [0:0]\uppCL3_reg[37]_2 ;
  wire \uppCL3_reg[37]_3 ;
  wire \uppCL3_reg[37]_4 ;
  wire \uppCL3_reg[37]_5 ;
  wire \uppCL3_reg[37]_6 ;
  wire \uppCL3_reg[37]_7 ;
  wire \uppCL3_reg[37]_8 ;
  wire \uppCL3_reg[38]_0 ;
  wire \uppCL3_reg[38]_1 ;
  wire \uppCL3_reg[38]_2 ;
  wire [2:0]\uppCL3_reg[38]_3 ;
  wire \uppCL3_reg[38]_4 ;
  wire \uppCL3_reg[38]_5 ;
  wire \uppCL3_reg[38]_6 ;
  wire \uppCL3_reg[38]_7 ;
  wire \uppCL3_reg[39]_0 ;
  wire \uppCL3_reg[3]_0 ;
  wire \uppCL3_reg[42]_0 ;
  wire [7:0]\uppCL3_reg[42]_1 ;
  wire \uppCL3_reg[43]_0 ;
  wire \uppCL3_reg[43]_1 ;
  wire \uppCL3_reg[43]_2 ;
  wire \uppCL3_reg[43]_3 ;
  wire \uppCL3_reg[43]_4 ;
  wire \uppCL3_reg[43]_5 ;
  wire \uppCL3_reg[43]_6 ;
  wire \uppCL3_reg[43]_7 ;
  wire \uppCL3_reg[44]_0 ;
  wire \uppCL3_reg[44]_1 ;
  wire \uppCL3_reg[44]_2 ;
  wire \uppCL3_reg[44]_3 ;
  wire \uppCL3_reg[44]_4 ;
  wire \uppCL3_reg[44]_5 ;
  wire \uppCL3_reg[44]_6 ;
  wire [2:0]\uppCL3_reg[44]_7 ;
  wire [5:0]\uppCL3_reg[45]_0 ;
  wire \uppCL3_reg[45]_1 ;
  wire [9:0]\uppCL3_reg[47] ;
  wire \uppCL3_reg[6]_0 ;
  wire \uppCL3_reg[7]_0 ;
  wire \uppCL3_reg[7]_1 ;
  wire \uppCL3_reg[7]_2 ;
  wire \uppCL3_reg[7]_3 ;
  wire \uppCL3_reg[7]_4 ;
  wire \uppCL3_reg[7]_5 ;
  wire \uppCL3_reg[7]_6 ;
  wire \uppCL3_reg[7]_7 ;
  wire \uppCL3_reg[8]_0 ;
  wire \uppCL3_reg[8]_1 ;
  wire \uppCL3_reg[8]_2 ;
  wire \uppCL3_reg[8]_3 ;
  wire \uppCL3_reg[8]_4 ;
  wire \uppCL3_reg[8]_5 ;
  wire \uppCL3_reg[8]_6 ;
  wire [2:0]\uppCL3_reg[8]_7 ;
  wire \uppCL3_reg[9]_0 ;
  wire winAct;
  wire [1:0]winAct_reg;
  wire [2:1]wosp;
  wire \wosp_reg[1] ;
  wire \wosp_reg[1]_0 ;
  wire \wosp_reg[1]_1 ;
  wire \wosp_reg[1]_10 ;
  wire \wosp_reg[1]_100 ;
  wire \wosp_reg[1]_101 ;
  wire \wosp_reg[1]_102 ;
  wire \wosp_reg[1]_103 ;
  wire \wosp_reg[1]_104 ;
  wire \wosp_reg[1]_105 ;
  wire \wosp_reg[1]_106 ;
  wire \wosp_reg[1]_107 ;
  wire \wosp_reg[1]_108 ;
  wire \wosp_reg[1]_109 ;
  wire \wosp_reg[1]_11 ;
  wire \wosp_reg[1]_110 ;
  wire \wosp_reg[1]_111 ;
  wire \wosp_reg[1]_112 ;
  wire \wosp_reg[1]_113 ;
  wire \wosp_reg[1]_114 ;
  wire \wosp_reg[1]_115 ;
  wire \wosp_reg[1]_116 ;
  wire \wosp_reg[1]_117 ;
  wire \wosp_reg[1]_118 ;
  wire \wosp_reg[1]_119 ;
  wire \wosp_reg[1]_12 ;
  wire \wosp_reg[1]_120 ;
  wire \wosp_reg[1]_121 ;
  wire \wosp_reg[1]_122 ;
  wire \wosp_reg[1]_123 ;
  wire \wosp_reg[1]_124 ;
  wire \wosp_reg[1]_125 ;
  wire \wosp_reg[1]_126 ;
  wire \wosp_reg[1]_127 ;
  wire \wosp_reg[1]_128 ;
  wire \wosp_reg[1]_129 ;
  wire \wosp_reg[1]_13 ;
  wire \wosp_reg[1]_130 ;
  wire \wosp_reg[1]_131 ;
  wire \wosp_reg[1]_132 ;
  wire \wosp_reg[1]_133 ;
  wire \wosp_reg[1]_134 ;
  wire \wosp_reg[1]_135 ;
  wire \wosp_reg[1]_136 ;
  wire \wosp_reg[1]_137 ;
  wire \wosp_reg[1]_138 ;
  wire \wosp_reg[1]_139 ;
  wire \wosp_reg[1]_14 ;
  wire \wosp_reg[1]_140 ;
  wire \wosp_reg[1]_141 ;
  wire \wosp_reg[1]_142 ;
  wire \wosp_reg[1]_15 ;
  wire \wosp_reg[1]_16 ;
  wire \wosp_reg[1]_17 ;
  wire \wosp_reg[1]_18 ;
  wire \wosp_reg[1]_19 ;
  wire \wosp_reg[1]_2 ;
  wire \wosp_reg[1]_20 ;
  wire \wosp_reg[1]_21 ;
  wire \wosp_reg[1]_22 ;
  wire \wosp_reg[1]_23 ;
  wire \wosp_reg[1]_24 ;
  wire \wosp_reg[1]_25 ;
  wire \wosp_reg[1]_26 ;
  wire \wosp_reg[1]_27 ;
  wire \wosp_reg[1]_28 ;
  wire \wosp_reg[1]_29 ;
  wire \wosp_reg[1]_3 ;
  wire \wosp_reg[1]_30 ;
  wire \wosp_reg[1]_31 ;
  wire \wosp_reg[1]_32 ;
  wire \wosp_reg[1]_33 ;
  wire \wosp_reg[1]_34 ;
  wire \wosp_reg[1]_35 ;
  wire \wosp_reg[1]_36 ;
  wire \wosp_reg[1]_37 ;
  wire \wosp_reg[1]_38 ;
  wire \wosp_reg[1]_39 ;
  wire \wosp_reg[1]_4 ;
  wire \wosp_reg[1]_40 ;
  wire \wosp_reg[1]_41 ;
  wire \wosp_reg[1]_42 ;
  wire \wosp_reg[1]_43 ;
  wire \wosp_reg[1]_44 ;
  wire \wosp_reg[1]_45 ;
  wire \wosp_reg[1]_46 ;
  wire \wosp_reg[1]_47 ;
  wire \wosp_reg[1]_48 ;
  wire \wosp_reg[1]_49 ;
  wire \wosp_reg[1]_5 ;
  wire \wosp_reg[1]_50 ;
  wire \wosp_reg[1]_51 ;
  wire \wosp_reg[1]_52 ;
  wire \wosp_reg[1]_53 ;
  wire \wosp_reg[1]_54 ;
  wire \wosp_reg[1]_55 ;
  wire \wosp_reg[1]_56 ;
  wire \wosp_reg[1]_57 ;
  wire \wosp_reg[1]_58 ;
  wire \wosp_reg[1]_59 ;
  wire \wosp_reg[1]_6 ;
  wire \wosp_reg[1]_60 ;
  wire \wosp_reg[1]_61 ;
  wire \wosp_reg[1]_62 ;
  wire \wosp_reg[1]_63 ;
  wire \wosp_reg[1]_64 ;
  wire \wosp_reg[1]_65 ;
  wire \wosp_reg[1]_66 ;
  wire \wosp_reg[1]_67 ;
  wire \wosp_reg[1]_68 ;
  wire \wosp_reg[1]_69 ;
  wire \wosp_reg[1]_7 ;
  wire \wosp_reg[1]_70 ;
  wire \wosp_reg[1]_71 ;
  wire \wosp_reg[1]_72 ;
  wire \wosp_reg[1]_73 ;
  wire \wosp_reg[1]_74 ;
  wire \wosp_reg[1]_75 ;
  wire \wosp_reg[1]_76 ;
  wire \wosp_reg[1]_77 ;
  wire \wosp_reg[1]_78 ;
  wire \wosp_reg[1]_79 ;
  wire \wosp_reg[1]_8 ;
  wire \wosp_reg[1]_80 ;
  wire \wosp_reg[1]_81 ;
  wire \wosp_reg[1]_82 ;
  wire \wosp_reg[1]_83 ;
  wire \wosp_reg[1]_84 ;
  wire \wosp_reg[1]_85 ;
  wire \wosp_reg[1]_86 ;
  wire \wosp_reg[1]_87 ;
  wire \wosp_reg[1]_88 ;
  wire \wosp_reg[1]_89 ;
  wire \wosp_reg[1]_9 ;
  wire \wosp_reg[1]_90 ;
  wire \wosp_reg[1]_91 ;
  wire \wosp_reg[1]_92 ;
  wire \wosp_reg[1]_93 ;
  wire \wosp_reg[1]_94 ;
  wire \wosp_reg[1]_95 ;
  wire \wosp_reg[1]_96 ;
  wire \wosp_reg[1]_97 ;
  wire \wosp_reg[1]_98 ;
  wire \wosp_reg[1]_99 ;
  wire [1:0]\wosp_reg[2] ;
  wire \wosp_reg[2]_0 ;
  wire [1:0]\wosp_reg[2]_rep ;
  wire \wosp_reg[2]_rep_0 ;
  wire [1:0]\wosp_reg[2]_rep_1 ;
  wire \wosp_reg[2]_rep_2 ;
  wire [1:0]\wosp_reg[2]_rep_3 ;
  wire \wosp_reg[2]_rep_4 ;
  wire [1:0]\wosp_reg[2]_rep__0 ;
  wire \wosp_reg[2]_rep__0_0 ;
  wire [1:0]\wosp_reg[2]_rep__0_1 ;
  wire \wosp_reg[2]_rep__0_2 ;
  wire [1:0]\wosp_reg[2]_rep__0_3 ;
  wire \wosp_reg[2]_rep__0_4 ;
  wire [1:0]\wosp_reg[2]_rep__1 ;
  wire \wosp_reg[2]_rep__1_0 ;
  wire \wosp_reg[2]_rep__1_1 ;
  wire \wosp_reg[2]_rep__1_10 ;
  wire \wosp_reg[2]_rep__1_11 ;
  wire [1:0]\wosp_reg[2]_rep__1_12 ;
  wire \wosp_reg[2]_rep__1_13 ;
  wire [1:0]\wosp_reg[2]_rep__1_2 ;
  wire \wosp_reg[2]_rep__1_3 ;
  wire \wosp_reg[2]_rep__1_4 ;
  wire [1:0]\wosp_reg[2]_rep__1_5 ;
  wire \wosp_reg[2]_rep__1_6 ;
  wire \wosp_reg[2]_rep__1_7 ;
  wire [1:0]\wosp_reg[2]_rep__1_8 ;
  wire \wosp_reg[2]_rep__1_9 ;
  wire \wosp_reg[2]_rep__2 ;
  wire [1:0]\wosp_reg[2]_rep__2_0 ;
  wire \wosp_reg[2]_rep__2_1 ;
  wire \wosp_reg[2]_rep__2_10 ;
  wire [1:0]\wosp_reg[2]_rep__2_11 ;
  wire \wosp_reg[2]_rep__2_12 ;
  wire \wosp_reg[2]_rep__2_13 ;
  wire [1:0]\wosp_reg[2]_rep__2_14 ;
  wire \wosp_reg[2]_rep__2_15 ;
  wire \wosp_reg[2]_rep__2_16 ;
  wire [1:0]\wosp_reg[2]_rep__2_17 ;
  wire \wosp_reg[2]_rep__2_18 ;
  wire \wosp_reg[2]_rep__2_19 ;
  wire [1:0]\wosp_reg[2]_rep__2_2 ;
  wire [1:0]\wosp_reg[2]_rep__2_20 ;
  wire \wosp_reg[2]_rep__2_21 ;
  wire \wosp_reg[2]_rep__2_22 ;
  wire [1:0]\wosp_reg[2]_rep__2_23 ;
  wire \wosp_reg[2]_rep__2_24 ;
  wire \wosp_reg[2]_rep__2_25 ;
  wire [1:0]\wosp_reg[2]_rep__2_26 ;
  wire \wosp_reg[2]_rep__2_27 ;
  wire \wosp_reg[2]_rep__2_28 ;
  wire [1:0]\wosp_reg[2]_rep__2_29 ;
  wire \wosp_reg[2]_rep__2_3 ;
  wire \wosp_reg[2]_rep__2_30 ;
  wire \wosp_reg[2]_rep__2_31 ;
  wire [1:0]\wosp_reg[2]_rep__2_32 ;
  wire \wosp_reg[2]_rep__2_33 ;
  wire \wosp_reg[2]_rep__2_34 ;
  wire \wosp_reg[2]_rep__2_4 ;
  wire [1:0]\wosp_reg[2]_rep__2_5 ;
  wire \wosp_reg[2]_rep__2_6 ;
  wire \wosp_reg[2]_rep__2_7 ;
  wire [1:0]\wosp_reg[2]_rep__2_8 ;
  wire \wosp_reg[2]_rep__2_9 ;
  wire \wosp_reg[2]_rep__3 ;
  wire \wosp_reg[2]_rep__3_0 ;
  wire [1:0]\wosp_reg[2]_rep__3_1 ;
  wire [1:0]\wosp_reg[2]_rep__3_10 ;
  wire \wosp_reg[2]_rep__3_11 ;
  wire \wosp_reg[2]_rep__3_12 ;
  wire [1:0]\wosp_reg[2]_rep__3_13 ;
  wire \wosp_reg[2]_rep__3_14 ;
  wire \wosp_reg[2]_rep__3_15 ;
  wire [1:0]\wosp_reg[2]_rep__3_16 ;
  wire \wosp_reg[2]_rep__3_17 ;
  wire \wosp_reg[2]_rep__3_18 ;
  wire [1:0]\wosp_reg[2]_rep__3_19 ;
  wire \wosp_reg[2]_rep__3_2 ;
  wire \wosp_reg[2]_rep__3_20 ;
  wire \wosp_reg[2]_rep__3_21 ;
  wire [1:0]\wosp_reg[2]_rep__3_22 ;
  wire \wosp_reg[2]_rep__3_23 ;
  wire \wosp_reg[2]_rep__3_24 ;
  wire [1:0]\wosp_reg[2]_rep__3_25 ;
  wire \wosp_reg[2]_rep__3_26 ;
  wire \wosp_reg[2]_rep__3_27 ;
  wire [1:0]\wosp_reg[2]_rep__3_28 ;
  wire \wosp_reg[2]_rep__3_29 ;
  wire \wosp_reg[2]_rep__3_3 ;
  wire \wosp_reg[2]_rep__3_30 ;
  wire [1:0]\wosp_reg[2]_rep__3_31 ;
  wire \wosp_reg[2]_rep__3_32 ;
  wire \wosp_reg[2]_rep__3_33 ;
  wire [1:0]\wosp_reg[2]_rep__3_4 ;
  wire \wosp_reg[2]_rep__3_5 ;
  wire \wosp_reg[2]_rep__3_6 ;
  wire [1:0]\wosp_reg[2]_rep__3_7 ;
  wire \wosp_reg[2]_rep__3_8 ;
  wire \wosp_reg[2]_rep__3_9 ;
  wire \wosp_reg[2]_rep__4 ;
  wire [1:0]\wosp_reg[2]_rep__4_0 ;
  wire \wosp_reg[2]_rep__4_1 ;
  wire \wosp_reg[2]_rep__4_10 ;
  wire \wosp_reg[2]_rep__4_11 ;
  wire [1:0]\wosp_reg[2]_rep__4_12 ;
  wire \wosp_reg[2]_rep__4_13 ;
  wire \wosp_reg[2]_rep__4_14 ;
  wire [1:0]\wosp_reg[2]_rep__4_15 ;
  wire \wosp_reg[2]_rep__4_16 ;
  wire \wosp_reg[2]_rep__4_17 ;
  wire [1:0]\wosp_reg[2]_rep__4_18 ;
  wire \wosp_reg[2]_rep__4_19 ;
  wire \wosp_reg[2]_rep__4_2 ;
  wire \wosp_reg[2]_rep__4_20 ;
  wire [1:0]\wosp_reg[2]_rep__4_21 ;
  wire \wosp_reg[2]_rep__4_22 ;
  wire \wosp_reg[2]_rep__4_23 ;
  wire [1:0]\wosp_reg[2]_rep__4_24 ;
  wire \wosp_reg[2]_rep__4_25 ;
  wire \wosp_reg[2]_rep__4_26 ;
  wire [1:0]\wosp_reg[2]_rep__4_27 ;
  wire \wosp_reg[2]_rep__4_28 ;
  wire \wosp_reg[2]_rep__4_29 ;
  wire [1:0]\wosp_reg[2]_rep__4_3 ;
  wire [1:0]\wosp_reg[2]_rep__4_30 ;
  wire \wosp_reg[2]_rep__4_31 ;
  wire \wosp_reg[2]_rep__4_32 ;
  wire \wosp_reg[2]_rep__4_33 ;
  wire \wosp_reg[2]_rep__4_4 ;
  wire \wosp_reg[2]_rep__4_5 ;
  wire [1:0]\wosp_reg[2]_rep__4_6 ;
  wire \wosp_reg[2]_rep__4_7 ;
  wire \wosp_reg[2]_rep__4_8 ;
  wire [1:0]\wosp_reg[2]_rep__4_9 ;
  wire \wosp_reg[2]_rep__5 ;
  wire [1:0]\wosp_reg[2]_rep__5_0 ;
  wire \wosp_reg[2]_rep__5_1 ;
  wire \wosp_reg[2]_rep__5_10 ;
  wire \wosp_reg[2]_rep__5_11 ;
  wire [1:0]\wosp_reg[2]_rep__5_12 ;
  wire \wosp_reg[2]_rep__5_13 ;
  wire \wosp_reg[2]_rep__5_14 ;
  wire [1:0]\wosp_reg[2]_rep__5_15 ;
  wire \wosp_reg[2]_rep__5_16 ;
  wire \wosp_reg[2]_rep__5_17 ;
  wire [1:0]\wosp_reg[2]_rep__5_18 ;
  wire \wosp_reg[2]_rep__5_19 ;
  wire [1:0]\wosp_reg[2]_rep__5_2 ;
  wire \wosp_reg[2]_rep__5_20 ;
  wire [1:0]\wosp_reg[2]_rep__5_21 ;
  wire \wosp_reg[2]_rep__5_22 ;
  wire \wosp_reg[2]_rep__5_23 ;
  wire [1:0]\wosp_reg[2]_rep__5_24 ;
  wire \wosp_reg[2]_rep__5_25 ;
  wire \wosp_reg[2]_rep__5_26 ;
  wire [1:0]\wosp_reg[2]_rep__5_27 ;
  wire \wosp_reg[2]_rep__5_28 ;
  wire \wosp_reg[2]_rep__5_29 ;
  wire \wosp_reg[2]_rep__5_3 ;
  wire [1:0]\wosp_reg[2]_rep__5_30 ;
  wire \wosp_reg[2]_rep__5_31 ;
  wire \wosp_reg[2]_rep__5_32 ;
  wire \wosp_reg[2]_rep__5_33 ;
  wire \wosp_reg[2]_rep__5_4 ;
  wire \wosp_reg[2]_rep__5_5 ;
  wire [1:0]\wosp_reg[2]_rep__5_6 ;
  wire \wosp_reg[2]_rep__5_7 ;
  wire \wosp_reg[2]_rep__5_8 ;
  wire [1:0]\wosp_reg[2]_rep__5_9 ;
  wire \wosp_reg[2]_rep__6 ;
  wire [1:0]\wosp_reg[2]_rep__6_0 ;
  wire \wosp_reg[2]_rep__6_1 ;
  wire \wosp_reg[2]_rep__6_10 ;
  wire [1:0]\wosp_reg[2]_rep__6_11 ;
  wire \wosp_reg[2]_rep__6_12 ;
  wire \wosp_reg[2]_rep__6_13 ;
  wire [1:0]\wosp_reg[2]_rep__6_14 ;
  wire \wosp_reg[2]_rep__6_15 ;
  wire \wosp_reg[2]_rep__6_16 ;
  wire [1:0]\wosp_reg[2]_rep__6_17 ;
  wire \wosp_reg[2]_rep__6_18 ;
  wire \wosp_reg[2]_rep__6_19 ;
  wire [1:0]\wosp_reg[2]_rep__6_2 ;
  wire \wosp_reg[2]_rep__6_20 ;
  wire \wosp_reg[2]_rep__6_21 ;
  wire [1:0]\wosp_reg[2]_rep__6_22 ;
  wire \wosp_reg[2]_rep__6_23 ;
  wire \wosp_reg[2]_rep__6_24 ;
  wire [1:0]\wosp_reg[2]_rep__6_25 ;
  wire \wosp_reg[2]_rep__6_26 ;
  wire \wosp_reg[2]_rep__6_27 ;
  wire [1:0]\wosp_reg[2]_rep__6_28 ;
  wire \wosp_reg[2]_rep__6_29 ;
  wire \wosp_reg[2]_rep__6_3 ;
  wire \wosp_reg[2]_rep__6_30 ;
  wire [1:0]\wosp_reg[2]_rep__6_31 ;
  wire \wosp_reg[2]_rep__6_32 ;
  wire \wosp_reg[2]_rep__6_33 ;
  wire [1:0]\wosp_reg[2]_rep__6_34 ;
  wire \wosp_reg[2]_rep__6_35 ;
  wire \wosp_reg[2]_rep__6_36 ;
  wire [1:0]\wosp_reg[2]_rep__6_37 ;
  wire \wosp_reg[2]_rep__6_38 ;
  wire \wosp_reg[2]_rep__6_39 ;
  wire \wosp_reg[2]_rep__6_4 ;
  wire [1:0]\wosp_reg[2]_rep__6_40 ;
  wire \wosp_reg[2]_rep__6_41 ;
  wire \wosp_reg[2]_rep__6_42 ;
  wire [1:0]\wosp_reg[2]_rep__6_5 ;
  wire \wosp_reg[2]_rep__6_6 ;
  wire \wosp_reg[2]_rep__6_7 ;
  wire [1:0]\wosp_reg[2]_rep__6_8 ;
  wire \wosp_reg[2]_rep__6_9 ;
  wire [1:0]\wosp_reg[2]_rep__7 ;
  wire \wosp_reg[2]_rep__7_0 ;
  wire wrCAS_reg;
  wire wrDataEn_pi;
  wire wrDataVal;
  wire [0:0]\wrQ_nxt[1]_13 ;
  wire \wrQ_reg[1][0] ;
  wire wren_reg;
  wire [0:0]xsdb_wr_en_reg;
  wire NLW_U_XSDB_SLAVE_s_rst_o_UNCONNECTED;
  wire [16:16]NLW_U_XSDB_SLAVE_s_daddr_o_UNCONNECTED;
  wire [7:0]\NLW_cntr_reg[17]_i_3_CO_UNCONNECTED ;
  wire [7:1]\NLW_cntr_reg[17]_i_3_O_UNCONNECTED ;

  assign cal_timer_reg_0_sn_1 = cal_timer_reg_0_sp_1;
  assign cal_timer_reg_21_sp_1 = cal_timer_reg_21_sn_1;
  assign cal_timer_reg_24_sp_1 = cal_timer_reg_24_sn_1;
  assign cal_timer_reg_25_sp_1 = cal_timer_reg_25_sn_1;
  assign cal_timer_reg_28_sp_1 = cal_timer_reg_28_sn_1;
  assign cal_timer_reg_29_sp_1 = cal_timer_reg_29_sn_1;
  (* ABITS = "17" *) 
  (* ADDR_WIDTH = "16" *) 
  (* BABITS = "2" *) 
  (* BGBITS = "1" *) 
  (* BISC_EN = "1" *) 
  (* BITS_PER_BYTE = "8" *) 
  (* CA_MIRROR = "0" *) 
  (* CKEBITS = "1" *) 
  (* CLKFBOUT_MULT_MMCM = "17" *) 
  (* CLKFBOUT_MULT_PLL = "4" *) 
  (* CLKOUT0_DIVIDE_MMCM = "4" *) 
  (* CLKOUT0_DIVIDE_PLL = "1" *) 
  (* COMPLEX_LOOP_CNT = "4" *) 
  (* CSBITS = "1" *) 
  (* DATA_WIDTH = "9" *) 
  (* DBYTES = "8" *) 
  (* DDR4_REG_RC03 = "13'b0000000110000" *) 
  (* DDR4_REG_RC04 = "13'b0000001000000" *) 
  (* DDR4_REG_RC05 = "13'b0000001010000" *) 
  (* DDR4_REG_RC3X = "13'b0001100111001" *) 
  (* DEBUG_MESSAGES = "1'b0" *) 
  (* DIVCLK_DIVIDE_MMCM = "1" *) 
  (* DIVCLK_DIVIDE_PLL = "1" *) 
  (* DM_DBI_SETTING = "3'b001" *) 
  (* DONT_TOUCH *) 
  (* DQBITS = "64" *) 
  (* DQS_GATE = "1" *) 
  (* DQS_SAMPLE_CNT = "20" *) 
  (* DQS_TRACKING = "1" *) 
  (* DRAM_WIDTH = "16" *) 
  (* EXTRA_CMD_DELAY = "0" *) 
  (* INIT = "2304'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010001000000001000000100000000001000000001000000001101000001000000000000000100000010100000000010000000000000000000000000000000000001000000000000000000000011000000000001100000001000000101101100100100111001001010000001000000000110000000000000000000000000000000000000001000000000000000001000000000000000000000000000000100001000000000000000000000000000000000001000101001000000100000000100000000100000010100000000001010100000001001001001001000001001001000110010000010000000001000001001001011010001000000001000000000000000111000000000000000000000000000000000000000000000000000000000000001000000001000000001000001000000010000000001000000000001000000010000000010000000000000000000000010010" *) 
  (* INIT_BRAM0 = "2304'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010001000000001000000100000000001000000001000000001101000001000000000000000100000010100000000010000000000000000000000000000000000001000000000000000000000011000000000001100000001000000101101100100100111001001010000001000000000110000000000000000000000000000000000000001000000000000000001000000000000000000000000000000100001000000000000000000000000000000000001000101001000000100000000100000000100000010100000000001010100000001001001001001000001001001000110010000010000000001000001001001011010001000000001000000000000000111000000000000000000000000000000000000000000000000000000000000001000000001000000001000001000000010000000001000000000001000000010000000010000000000000000000000010010" *) 
  (* IODELAY_QTR_CK_TAP_CNT = "41" *) 
  (* MEM = "DDR4" *) 
  (* MEMORY_CONFIGURATION = "1" *) 
  (* MEMORY_TYPE = "2" *) 
  (* MEMORY_VOLTAGE = "1" *) 
  (* MEM_CODE = "0" *) 
  (* MR0 = "13'b0101101100100" *) 
  (* MR0_0 = "9'b101100100" *) 
  (* MR0_1 = "9'b000000101" *) 
  (* MR1 = "13'b0001100000001" *) 
  (* MR1_0 = "9'b100000001" *) 
  (* MR1_1 = "9'b000000001" *) 
  (* MR2 = "13'b0000000011000" *) 
  (* MR2_0 = "9'b000011000" *) 
  (* MR2_1 = "9'b000000000" *) 
  (* MR3 = "13'b0001000000000" *) 
  (* MR3_0 = "9'b000000000" *) 
  (* MR3_1 = "9'b000000001" *) 
  (* MR4 = "13'b0000000000000" *) 
  (* MR4_0 = "9'b000000000" *) 
  (* MR4_1 = "9'b000000000" *) 
  (* MR5 = "13'b0010000000000" *) 
  (* MR5_0 = "9'b000000000" *) 
  (* MR5_1 = "9'b000000010" *) 
  (* MR6 = "13'b0100000010100" *) 
  (* MR6_0 = "9'b000010100" *) 
  (* MR6_1 = "9'b000000100" *) 
  (* NIBBLE = "16" *) 
  (* NUM_BRAMS = "1" *) 
  (* ODTBITS = "1" *) 
  (* ODTRD = "16'b0000000000000000" *) 
  (* ODTWR = "16'b0000000000100001" *) 
  (* PIPELINE_REG = "1" *) 
  (* RANKS = "1" *) 
  (* RDLVL = "1" *) 
  (* RDLVL_COMPLEX = "1" *) 
  (* RDLVL_DBI = "0" *) 
  (* RDLVL_SAMPLE_CNT = "4" *) 
  (* RD_VREF = "0" *) 
  (* RD_VREF_PATTERN = "2" *) 
  (* REG_CTRL_ON = "0" *) 
  (* RTL_VERSION = "7" *) 
  (* SIZE = "36864" *) 
  (* SLOT0_CONFIG = "8'b00000001" *) 
  (* SLOT0_FUNC_CS = "8'b00000001" *) 
  (* SLOT0_ODD_CS = "8'b00000000" *) 
  (* SLOT1_CONFIG = "8'b00000000" *) 
  (* SLOT1_FUNC_CS = "8'b00000000" *) 
  (* SLOT1_ODD_CS = "8'b00000000" *) 
  (* SLOTS = "0" *) 
  (* SPREAD_SHEET_VERSION = "16'b0000000000000010" *) 
  (* START_ADDRESS = "18" *) 
  (* S_HEIGHT = "1" *) 
  (* USE_CS_PORT = "1" *) 
  (* WRITE_LAT = "1" *) 
  (* WRLVL = "1" *) 
  (* WRLVL_SAMPLE_CNT = "4" *) 
  (* WR_DQS_COMPLEX = "1" *) 
  (* WR_DQS_DM_DBI = "1" *) 
  (* WR_DQS_DQ = "1" *) 
  (* WR_VREF = "0" *) 
  (* WR_VREF_PATTERN = "2" *) 
  (* bram_map = "yes" *) 
  (* mem0_init_0 = "9'b000010010" *) 
  (* mem0_init_1 = "9'b000000000" *) 
  (* mem0_init_10 = "9'b000000001" *) 
  (* mem0_init_100 = "9'b000000000" *) 
  (* mem0_init_101 = "9'b000000000" *) 
  (* mem0_init_102 = "9'b000000000" *) 
  (* mem0_init_103 = "9'b000000000" *) 
  (* mem0_init_104 = "9'b000000000" *) 
  (* mem0_init_105 = "9'b000000000" *) 
  (* mem0_init_106 = "9'b000000000" *) 
  (* mem0_init_107 = "9'b000000000" *) 
  (* mem0_init_108 = "9'b000000000" *) 
  (* mem0_init_109 = "9'b000000000" *) 
  (* mem0_init_11 = "9'b000000001" *) 
  (* mem0_init_110 = "9'b000000000" *) 
  (* mem0_init_111 = "9'b000000000" *) 
  (* mem0_init_112 = "9'b000000000" *) 
  (* mem0_init_113 = "9'b000000000" *) 
  (* mem0_init_114 = "9'b000000000" *) 
  (* mem0_init_115 = "9'b000000000" *) 
  (* mem0_init_116 = "9'b000000000" *) 
  (* mem0_init_117 = "9'b000000000" *) 
  (* mem0_init_118 = "9'b000000000" *) 
  (* mem0_init_119 = "9'b000000000" *) 
  (* mem0_init_12 = "0" *) 
  (* mem0_init_120 = "9'b000000000" *) 
  (* mem0_init_121 = "9'b000000000" *) 
  (* mem0_init_122 = "9'b000000000" *) 
  (* mem0_init_123 = "9'b000000000" *) 
  (* mem0_init_124 = "9'b000000000" *) 
  (* mem0_init_125 = "9'b000000000" *) 
  (* mem0_init_126 = "9'b000000000" *) 
  (* mem0_init_127 = "9'b000000000" *) 
  (* mem0_init_128 = "9'b000000000" *) 
  (* mem0_init_129 = "9'b000000000" *) 
  (* mem0_init_13 = "9'b000000000" *) 
  (* mem0_init_130 = "9'b000000000" *) 
  (* mem0_init_131 = "9'b000000000" *) 
  (* mem0_init_132 = "9'b000000000" *) 
  (* mem0_init_133 = "9'b000000000" *) 
  (* mem0_init_134 = "9'b000000000" *) 
  (* mem0_init_135 = "9'b000000000" *) 
  (* mem0_init_136 = "9'b000000000" *) 
  (* mem0_init_137 = "9'b000000000" *) 
  (* mem0_init_138 = "9'b000000000" *) 
  (* mem0_init_139 = "9'b000000000" *) 
  (* mem0_init_14 = "9'b000000000" *) 
  (* mem0_init_140 = "9'b000000000" *) 
  (* mem0_init_141 = "9'b000000000" *) 
  (* mem0_init_142 = "9'b000000000" *) 
  (* mem0_init_143 = "9'b000000000" *) 
  (* mem0_init_144 = "9'b000000000" *) 
  (* mem0_init_145 = "9'b000000000" *) 
  (* mem0_init_146 = "9'b000000000" *) 
  (* mem0_init_147 = "9'b000000000" *) 
  (* mem0_init_148 = "9'b000000000" *) 
  (* mem0_init_149 = "9'b000000000" *) 
  (* mem0_init_15 = "9'b000000000" *) 
  (* mem0_init_150 = "9'b000000000" *) 
  (* mem0_init_151 = "9'b000000000" *) 
  (* mem0_init_152 = "9'b000000000" *) 
  (* mem0_init_153 = "9'b000000000" *) 
  (* mem0_init_154 = "9'b000000000" *) 
  (* mem0_init_155 = "9'b000000000" *) 
  (* mem0_init_156 = "9'b000000000" *) 
  (* mem0_init_157 = "9'b000000000" *) 
  (* mem0_init_158 = "9'b000000000" *) 
  (* mem0_init_159 = "9'b000000000" *) 
  (* mem0_init_16 = "9'b000000000" *) 
  (* mem0_init_160 = "9'b000000000" *) 
  (* mem0_init_161 = "9'b000000000" *) 
  (* mem0_init_162 = "9'b000000000" *) 
  (* mem0_init_163 = "9'b000000000" *) 
  (* mem0_init_164 = "9'b000000000" *) 
  (* mem0_init_165 = "9'b000000000" *) 
  (* mem0_init_166 = "9'b000000000" *) 
  (* mem0_init_167 = "9'b000000000" *) 
  (* mem0_init_168 = "9'b000000000" *) 
  (* mem0_init_169 = "9'b000000000" *) 
  (* mem0_init_17 = "9'b000000000" *) 
  (* mem0_init_170 = "9'b000000000" *) 
  (* mem0_init_171 = "9'b000000000" *) 
  (* mem0_init_172 = "9'b000000000" *) 
  (* mem0_init_173 = "9'b000000000" *) 
  (* mem0_init_174 = "9'b000000000" *) 
  (* mem0_init_175 = "9'b000000000" *) 
  (* mem0_init_176 = "9'b000000000" *) 
  (* mem0_init_177 = "9'b000000000" *) 
  (* mem0_init_178 = "9'b000000000" *) 
  (* mem0_init_179 = "9'b000000000" *) 
  (* mem0_init_18 = "9'b000000111" *) 
  (* mem0_init_180 = "9'b000000000" *) 
  (* mem0_init_181 = "9'b000000000" *) 
  (* mem0_init_182 = "9'b000000000" *) 
  (* mem0_init_183 = "9'b000000000" *) 
  (* mem0_init_184 = "9'b000000000" *) 
  (* mem0_init_185 = "9'b000000000" *) 
  (* mem0_init_186 = "9'b000000000" *) 
  (* mem0_init_187 = "9'b000000000" *) 
  (* mem0_init_188 = "9'b000000000" *) 
  (* mem0_init_189 = "9'b000000000" *) 
  (* mem0_init_19 = "9'b000000000" *) 
  (* mem0_init_190 = "9'b000000000" *) 
  (* mem0_init_191 = "9'b000000000" *) 
  (* mem0_init_192 = "9'b000000000" *) 
  (* mem0_init_193 = "9'b000000000" *) 
  (* mem0_init_194 = "9'b000000000" *) 
  (* mem0_init_195 = "9'b000000000" *) 
  (* mem0_init_196 = "9'b000000000" *) 
  (* mem0_init_197 = "9'b000000000" *) 
  (* mem0_init_198 = "9'b000000000" *) 
  (* mem0_init_199 = "9'b000000000" *) 
  (* mem0_init_2 = "9'b000000000" *) 
  (* mem0_init_20 = "9'b000000001" *) 
  (* mem0_init_200 = "9'b000000000" *) 
  (* mem0_init_201 = "9'b000000000" *) 
  (* mem0_init_202 = "9'b000000000" *) 
  (* mem0_init_203 = "9'b000000000" *) 
  (* mem0_init_204 = "9'b000000000" *) 
  (* mem0_init_205 = "9'b000000000" *) 
  (* mem0_init_206 = "9'b000000000" *) 
  (* mem0_init_207 = "9'b000000000" *) 
  (* mem0_init_208 = "9'b000000000" *) 
  (* mem0_init_209 = "9'b000000000" *) 
  (* mem0_init_21 = "9'b011010001" *) 
  (* mem0_init_210 = "9'b000000000" *) 
  (* mem0_init_211 = "9'b000000000" *) 
  (* mem0_init_212 = "9'b000000000" *) 
  (* mem0_init_213 = "9'b000000000" *) 
  (* mem0_init_214 = "9'b000000000" *) 
  (* mem0_init_215 = "9'b000000000" *) 
  (* mem0_init_216 = "9'b000000000" *) 
  (* mem0_init_217 = "9'b000000000" *) 
  (* mem0_init_218 = "9'b000000000" *) 
  (* mem0_init_219 = "9'b000000000" *) 
  (* mem0_init_22 = "9'b001001001" *) 
  (* mem0_init_220 = "9'b000000000" *) 
  (* mem0_init_221 = "9'b000000000" *) 
  (* mem0_init_222 = "9'b000000000" *) 
  (* mem0_init_223 = "9'b000000000" *) 
  (* mem0_init_224 = "9'b000000000" *) 
  (* mem0_init_225 = "9'b000000000" *) 
  (* mem0_init_226 = "9'b000000000" *) 
  (* mem0_init_227 = "9'b000000000" *) 
  (* mem0_init_228 = "9'b000000000" *) 
  (* mem0_init_229 = "9'b000000000" *) 
  (* mem0_init_23 = "9'b000001000" *) 
  (* mem0_init_230 = "9'b000000000" *) 
  (* mem0_init_231 = "9'b000000000" *) 
  (* mem0_init_232 = "9'b000000000" *) 
  (* mem0_init_233 = "9'b000000000" *) 
  (* mem0_init_234 = "9'b000000000" *) 
  (* mem0_init_235 = "9'b000000000" *) 
  (* mem0_init_236 = "9'b000000000" *) 
  (* mem0_init_237 = "9'b000000000" *) 
  (* mem0_init_238 = "9'b000000000" *) 
  (* mem0_init_239 = "9'b000000000" *) 
  (* mem0_init_24 = "9'b000010000" *) 
  (* mem0_init_240 = "9'b000000000" *) 
  (* mem0_init_241 = "9'b000000000" *) 
  (* mem0_init_242 = "9'b000000000" *) 
  (* mem0_init_243 = "9'b000000000" *) 
  (* mem0_init_244 = "9'b000000000" *) 
  (* mem0_init_245 = "9'b000000000" *) 
  (* mem0_init_246 = "9'b000000000" *) 
  (* mem0_init_247 = "9'b000000000" *) 
  (* mem0_init_248 = "9'b000000000" *) 
  (* mem0_init_249 = "9'b000000000" *) 
  (* mem0_init_25 = "9'b000110010" *) 
  (* mem0_init_250 = "9'b000000000" *) 
  (* mem0_init_251 = "9'b000000000" *) 
  (* mem0_init_252 = "9'b000000000" *) 
  (* mem0_init_253 = "9'b000000000" *) 
  (* mem0_init_254 = "9'b000000000" *) 
  (* mem0_init_255 = "9'b000000000" *) 
  (* mem0_init_26 = "9'b001001001" *) 
  (* mem0_init_27 = "9'b001001000" *) 
  (* mem0_init_28 = "9'b001001001" *) 
  (* mem0_init_29 = "9'b010100000" *) 
  (* mem0_init_3 = "9'b000000010" *) 
  (* mem0_init_30 = "9'b000000001" *) 
  (* mem0_init_31 = "9'b000010100" *) 
  (* mem0_init_32 = "9'b000000100" *) 
  (* mem0_init_33 = "9'b000000100" *) 
  (* mem0_init_34 = "9'b000000100" *) 
  (* mem0_init_35 = "9'b000101001" *) 
  (* mem0_init_36 = "9'b000000001" *) 
  (* mem0_init_37 = "9'b000000000" *) 
  (* mem0_init_38 = "9'b000000000" *) 
  (* mem0_init_39 = "9'b000000000" *) 
  (* mem0_init_4 = "9'b000000010" *) 
  (* mem0_init_40 = "9'b000100001" *) 
  (* mem0_init_41 = "9'b000000000" *) 
  (* mem0_init_42 = "9'b000000000" *) 
  (* mem0_init_43 = "9'b000000000" *) 
  (* mem0_init_44 = "9'b000000001" *) 
  (* mem0_init_45 = "9'b000000000" *) 
  (* mem0_init_46 = "9'b000000001" *) 
  (* mem0_init_47 = "9'b000000000" *) 
  (* mem0_init_48 = "9'b000000000" *) 
  (* mem0_init_49 = "9'b000000000" *) 
  (* mem0_init_5 = "1" *) 
  (* mem0_init_50 = "9'b000110000" *) 
  (* mem0_init_51 = "9'b001000000" *) 
  (* mem0_init_52 = "9'b001010000" *) 
  (* mem0_init_53 = "9'b100111001" *) 
  (* mem0_init_54 = "9'b101100100" *) 
  (* mem0_init_55 = "9'b000000101" *) 
  (* mem0_init_56 = "9'b100000001" *) 
  (* mem0_init_57 = "9'b000000001" *) 
  (* mem0_init_58 = "9'b000011000" *) 
  (* mem0_init_59 = "9'b000000000" *) 
  (* mem0_init_6 = "9'b000001000" *) 
  (* mem0_init_60 = "9'b000000000" *) 
  (* mem0_init_61 = "9'b000000001" *) 
  (* mem0_init_62 = "9'b000000000" *) 
  (* mem0_init_63 = "9'b000000000" *) 
  (* mem0_init_64 = "9'b000000000" *) 
  (* mem0_init_65 = "9'b000000010" *) 
  (* mem0_init_66 = "9'b000010100" *) 
  (* mem0_init_67 = "9'b000000100" *) 
  (* mem0_init_68 = "9'b000000000" *) 
  (* mem0_init_69 = "9'b101000001" *) 
  (* mem0_init_7 = "9'b000010000" *) 
  (* mem0_init_70 = "9'b000000001" *) 
  (* mem0_init_71 = "9'b000000001" *) 
  (* mem0_init_72 = "9'b000000001" *) 
  (* mem0_init_73 = "9'b000000100" *) 
  (* mem0_init_74 = "9'b000000001" *) 
  (* mem0_init_75 = "9'b000010001" *) 
  (* mem0_init_76 = "9'b000000001" *) 
  (* mem0_init_77 = "9'b000000000" *) 
  (* mem0_init_78 = "9'b000000000" *) 
  (* mem0_init_79 = "9'b000000000" *) 
  (* mem0_init_8 = "9'b000001000" *) 
  (* mem0_init_80 = "9'b000000000" *) 
  (* mem0_init_81 = "9'b000000000" *) 
  (* mem0_init_82 = "9'b000000000" *) 
  (* mem0_init_83 = "9'b000000000" *) 
  (* mem0_init_84 = "9'b000000000" *) 
  (* mem0_init_85 = "9'b000000000" *) 
  (* mem0_init_86 = "9'b000000000" *) 
  (* mem0_init_87 = "9'b000000000" *) 
  (* mem0_init_88 = "9'b000000000" *) 
  (* mem0_init_89 = "9'b000000000" *) 
  (* mem0_init_9 = "9'b000000001" *) 
  (* mem0_init_90 = "9'b000000000" *) 
  (* mem0_init_91 = "9'b000000000" *) 
  (* mem0_init_92 = "9'b000000000" *) 
  (* mem0_init_93 = "9'b000000000" *) 
  (* mem0_init_94 = "9'b000000000" *) 
  (* mem0_init_95 = "9'b000000000" *) 
  (* mem0_init_96 = "9'b000000000" *) 
  (* mem0_init_97 = "9'b000000000" *) 
  (* mem0_init_98 = "9'b000000000" *) 
  (* mem0_init_99 = "9'b000000000" *) 
  (* nCK_PER_CLK = "4" *) 
  (* tCK = "833" *) 
  ddr4_0_ddr4_v2_2_17_cal_xsdb_bram DDR_XSDB_BRAM
       (.addra(io_address[15:0]),
        .addrb(bramB_addr),
        .clka(\SYNC[0].sync_reg_reg[1]_1 ),
        .clkb(\SYNC[0].sync_reg_reg[1]_1 ),
        .dina(ub_xsdb_wr_data),
        .dinb(bramB_di),
        .douta(douta),
        .doutb({DDR_XSDB_BRAM_n_9,DDR_XSDB_BRAM_n_10,DDR_XSDB_BRAM_n_11,DDR_XSDB_BRAM_n_12,DDR_XSDB_BRAM_n_13,DDR_XSDB_BRAM_n_14,DDR_XSDB_BRAM_n_15,DDR_XSDB_BRAM_n_16,DDR_XSDB_BRAM_n_17}),
        .ena(ena),
        .enb(bramB_en_stch),
        .rsta(1'b0),
        .rstb(1'b0),
        .wea(ub_xsdb_wr_en),
        .web(bramB_we));
  (* C_BUILD_REVISION = "0" *) 
  (* C_CORE_INFO1 = "0" *) 
  (* C_CORE_INFO2 = "0" *) 
  (* C_CORE_MAJOR_VER = "3" *) 
  (* C_CORE_MINOR_VER = "0" *) 
  (* C_CORE_TYPE = "16'b0000000000001000" *) 
  (* C_CSE_DRV_VER = "16'b0000000000000010" *) 
  (* C_MAJOR_VERSION = "2017" *) 
  (* C_MINOR_VERSION = "1" *) 
  (* C_NEXT_SLAVE = "16'b0000000000000000" *) 
  (* C_PIPE_IFACE = "1" *) 
  (* C_USE_TEST_REG = "1" *) 
  (* C_XDEVICEFAMILY = "kintexu" *) 
  (* C_XSDB_SLAVE_TYPE = "16'b0000000010000010" *) 
  (* DONT_TOUCH *) 
  ddr4_0_ddr4_v2_2_17_chipscope_xsdb_slave U_XSDB_SLAVE
       (.s_daddr_o({NLW_U_XSDB_SLAVE_s_daddr_o_UNCONNECTED[16],s_daddr}),
        .s_dclk_o(s_dclk),
        .s_den_o(s_den),
        .s_di_o(s_di),
        .s_do_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s_do}),
        .s_drdy_i(s_drdy),
        .s_dwe_o(s_dwe),
        .s_rst_o(NLW_U_XSDB_SLAVE_s_rst_o_UNCONNECTED),
        .sl_iport_i(out),
        .sl_oport_o(sl_oport_o));
  FDRE bramB_rdy_reg
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(t2),
        .Q(bramB_rdy),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1578" *) 
  LUT2 #(
    .INIT(4'h8)) 
    calDone_gated_i_1
       (.I0(calDone_reg_1),
        .I1(calDone_gated_reg),
        .O(calDone_i));
  FDRE calDone_reg
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(caldone_r),
        .Q(calDone_reg_1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1573" *) 
  LUT5 #(
    .INIT(32'hFFFFEFFF)) 
    \calSt[0]_i_1 
       (.I0(\calSt_reg_n_0_[2] ),
        .I1(\calSt_reg_n_0_[3] ),
        .I2(\calSt_reg_n_0_[0] ),
        .I3(\calSt_reg_n_0_[1] ),
        .I4(retSt[0]),
        .O(\calSt[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFEFFF)) 
    \calSt[1]_i_1 
       (.I0(\calSt_reg_n_0_[2] ),
        .I1(\calSt_reg_n_0_[3] ),
        .I2(\calSt_reg_n_0_[0] ),
        .I3(\calSt_reg_n_0_[1] ),
        .I4(retSt[1]),
        .O(\calSt[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \calSt[2]_i_1 
       (.I0(retSt[2]),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .I4(\calSt_reg_n_0_[1] ),
        .O(\calSt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFCFFFFFCFFF3FFFB)) 
    \calSt[3]_i_1 
       (.I0(\calSt_reg[0]_0 ),
        .I1(\calSt_reg_n_0_[0] ),
        .I2(\calSt[3]_i_4_n_0 ),
        .I3(\calSt_reg_n_0_[3] ),
        .I4(\calSt_reg_n_0_[1] ),
        .I5(\calSt_reg_n_0_[2] ),
        .O(\calSt[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \calSt[3]_i_2 
       (.I0(retSt[3]),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .I4(\calSt_reg_n_0_[1] ),
        .O(\calSt[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008000)) 
    \calSt[3]_i_4 
       (.I0(\calSt[3]_i_5_n_0 ),
        .I1(\calSt[3]_i_6_n_0 ),
        .I2(\calSt[3]_i_7_n_0 ),
        .I3(\calSt_reg_n_0_[1] ),
        .I4(\calSt_reg_n_0_[2] ),
        .O(\calSt[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \calSt[3]_i_5 
       (.I0(cntr[14]),
        .I1(cntr[15]),
        .I2(cntr[12]),
        .I3(cntr[13]),
        .I4(cntr[17]),
        .I5(cntr[16]),
        .O(\calSt[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \calSt[3]_i_6 
       (.I0(cntr[2]),
        .I1(cntr[3]),
        .I2(cntr[0]),
        .I3(cntr[1]),
        .I4(cntr[5]),
        .I5(cntr[4]),
        .O(\calSt[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \calSt[3]_i_7 
       (.I0(cntr[8]),
        .I1(cntr[9]),
        .I2(cntr[6]),
        .I3(cntr[7]),
        .I4(cntr[11]),
        .I5(cntr[10]),
        .O(\calSt[3]_i_7_n_0 ));
  FDRE \calSt_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(\calSt[3]_i_1_n_0 ),
        .D(\calSt[0]_i_1_n_0 ),
        .Q(\calSt_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \calSt_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(\calSt[3]_i_1_n_0 ),
        .D(\calSt[1]_i_1_n_0 ),
        .Q(\calSt_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \calSt_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(\calSt[3]_i_1_n_0 ),
        .D(\calSt[2]_i_1_n_0 ),
        .Q(\calSt_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \calSt_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(\calSt[3]_i_1_n_0 ),
        .D(\calSt[3]_i_2_n_0 ),
        .Q(\calSt_reg_n_0_[3] ),
        .R(rst_r1));
  FDRE caldone_r_reg
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(calDone_reg_0),
        .Q(caldone_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1577" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \cmr_cnt[0]_i_1 
       (.I0(cmr_cnt[0]),
        .O(\cmr_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1576" *) 
  LUT5 #(
    .INIT(32'h00DFFF00)) 
    \cmr_cnt[1]_i_1 
       (.I0(cmr_cnt[2]),
        .I1(cmr_cnt[4]),
        .I2(cmr_cnt[3]),
        .I3(cmr_cnt[1]),
        .I4(cmr_cnt[0]),
        .O(\cmr_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1576" *) 
  LUT5 #(
    .INIT(32'h0FF0B0F0)) 
    \cmr_cnt[2]_i_1 
       (.I0(cmr_cnt[4]),
        .I1(cmr_cnt[3]),
        .I2(cmr_cnt[2]),
        .I3(cmr_cnt[0]),
        .I4(cmr_cnt[1]),
        .O(\cmr_cnt[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1572" *) 
  LUT5 #(
    .INIT(32'h38CCCCCC)) 
    \cmr_cnt[3]_i_1 
       (.I0(cmr_cnt[4]),
        .I1(cmr_cnt[3]),
        .I2(cmr_cnt[1]),
        .I3(cmr_cnt[2]),
        .I4(cmr_cnt[0]),
        .O(\cmr_cnt[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0002)) 
    \cmr_cnt[4]_i_1 
       (.I0(\calSt_reg_n_0_[1] ),
        .I1(\calSt_reg_n_0_[0] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[2] ),
        .O(cs_mask_int));
  LUT4 #(
    .INIT(16'h8000)) 
    \cmr_cnt[4]_i_2 
       (.I0(\calSt_reg_n_0_[0] ),
        .I1(\calSt_reg_n_0_[3] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[2] ),
        .O(\cmr_cnt[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1577" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cmr_cnt[4]_i_3 
       (.I0(cmr_cnt[4]),
        .I1(cmr_cnt[3]),
        .I2(cmr_cnt[1]),
        .I3(cmr_cnt[2]),
        .I4(cmr_cnt[0]),
        .O(\cmr_cnt[4]_i_3_n_0 ));
  FDRE \cmr_cnt_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(\cmr_cnt[4]_i_2_n_0 ),
        .D(\cmr_cnt[0]_i_1_n_0 ),
        .Q(cmr_cnt[0]),
        .R(cs_mask_int));
  FDRE \cmr_cnt_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(\cmr_cnt[4]_i_2_n_0 ),
        .D(\cmr_cnt[1]_i_1_n_0 ),
        .Q(cmr_cnt[1]),
        .R(cs_mask_int));
  FDRE \cmr_cnt_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(\cmr_cnt[4]_i_2_n_0 ),
        .D(\cmr_cnt[2]_i_1_n_0 ),
        .Q(cmr_cnt[2]),
        .R(cs_mask_int));
  FDRE \cmr_cnt_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(\cmr_cnt[4]_i_2_n_0 ),
        .D(\cmr_cnt[3]_i_1_n_0 ),
        .Q(cmr_cnt[3]),
        .R(cs_mask_int));
  FDRE \cmr_cnt_reg[4] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(\cmr_cnt[4]_i_2_n_0 ),
        .D(\cmr_cnt[4]_i_3_n_0 ),
        .Q(cmr_cnt[4]),
        .R(cs_mask_int));
  LUT5 #(
    .INIT(32'h0307030F)) 
    \cntr[0]_i_1 
       (.I0(cntr[0]),
        .I1(\calSt_reg_n_0_[1] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[2] ),
        .I4(\calSt_reg_n_0_[0] ),
        .O(\cntr[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAEAAAAAAAAA)) 
    \cntr[10]_i_1 
       (.I0(\cntr[10]_i_2_n_0 ),
        .I1(\calSt_reg_n_0_[1] ),
        .I2(\calSt_reg_n_0_[0] ),
        .I3(\calSt_reg_n_0_[3] ),
        .I4(\calSt_reg_n_0_[2] ),
        .I5(data1[10]),
        .O(\cntr[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000002804)) 
    \cntr[10]_i_2 
       (.I0(cmr_cnt[0]),
        .I1(cmr_cnt[1]),
        .I2(cmr_cnt[3]),
        .I3(cmr_cnt[2]),
        .I4(cmr_cnt[4]),
        .I5(\init_cal_ADR[103]_i_3_n_0 ),
        .O(\cntr[10]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h02030303)) 
    \cntr[11]_i_1 
       (.I0(data1[11]),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .I4(\calSt_reg_n_0_[1] ),
        .O(\cntr[11]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \cntr[12]_i_1 
       (.I0(data1[12]),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .I4(\calSt_reg_n_0_[1] ),
        .O(\cntr[12]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0000008F)) 
    \cntr[13]_i_1 
       (.I0(data1[13]),
        .I1(\calSt_reg_n_0_[0] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[2] ),
        .I4(\calSt_reg_n_0_[3] ),
        .O(\cntr[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1561" *) 
  LUT5 #(
    .INIT(32'h02030303)) 
    \cntr[14]_i_1 
       (.I0(data1[14]),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .I4(\calSt_reg_n_0_[1] ),
        .O(\cntr[14]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0000008F)) 
    \cntr[15]_i_1 
       (.I0(data1[15]),
        .I1(\calSt_reg_n_0_[0] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[2] ),
        .I4(\calSt_reg_n_0_[3] ),
        .O(\cntr[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1560" *) 
  LUT5 #(
    .INIT(32'h02000000)) 
    \cntr[16]_i_1 
       (.I0(data1[16]),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .I4(\calSt_reg_n_0_[1] ),
        .O(\cntr[16]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[16]_i_10 
       (.I0(cntr[9]),
        .O(\cntr[16]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[16]_i_3 
       (.I0(cntr[16]),
        .O(\cntr[16]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[16]_i_4 
       (.I0(cntr[15]),
        .O(\cntr[16]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[16]_i_5 
       (.I0(cntr[14]),
        .O(\cntr[16]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[16]_i_6 
       (.I0(cntr[13]),
        .O(\cntr[16]_i_6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[16]_i_7 
       (.I0(cntr[12]),
        .O(\cntr[16]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[16]_i_8 
       (.I0(cntr[11]),
        .O(\cntr[16]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[16]_i_9 
       (.I0(cntr[10]),
        .O(\cntr[16]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h02030000)) 
    \cntr[17]_i_2 
       (.I0(data1[17]),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .I4(\calSt_reg_n_0_[1] ),
        .O(\cntr[17]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[17]_i_4 
       (.I0(cntr[17]),
        .O(\cntr[17]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30EC3CCC)) 
    \cntr[1]_i_1 
       (.I0(data1[1]),
        .I1(\calSt_reg_n_0_[3] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[2] ),
        .I4(\calSt_reg_n_0_[0] ),
        .O(\cntr[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02030CCC)) 
    \cntr[2]_i_1 
       (.I0(data1[2]),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .I4(\calSt_reg_n_0_[1] ),
        .O(\cntr[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hA05FA057)) 
    \cntr[3]_i_1 
       (.I0(\calSt_reg_n_0_[1] ),
        .I1(\calSt_reg_n_0_[0] ),
        .I2(\calSt_reg_n_0_[2] ),
        .I3(\calSt_reg_n_0_[3] ),
        .I4(data1[3]),
        .O(\cntr[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0000008F)) 
    \cntr[4]_i_1 
       (.I0(data1[4]),
        .I1(\calSt_reg_n_0_[0] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[2] ),
        .I4(\calSt_reg_n_0_[3] ),
        .O(\cntr[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h030B030F)) 
    \cntr[5]_i_1 
       (.I0(data1[5]),
        .I1(\calSt_reg_n_0_[1] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[2] ),
        .I4(\calSt_reg_n_0_[0] ),
        .O(\cntr[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h005500D5)) 
    \cntr[6]_i_1 
       (.I0(\calSt_reg_n_0_[1] ),
        .I1(data1[6]),
        .I2(\calSt_reg_n_0_[0] ),
        .I3(\calSt_reg_n_0_[3] ),
        .I4(\calSt_reg_n_0_[2] ),
        .O(\cntr[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h02000000)) 
    \cntr[7]_i_1 
       (.I0(data1[7]),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .I4(\calSt_reg_n_0_[1] ),
        .O(\cntr[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0200C000)) 
    \cntr[8]_i_1 
       (.I0(data1[8]),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .I4(\calSt_reg_n_0_[1] ),
        .I5(\cntr[10]_i_2_n_0 ),
        .O(\cntr[8]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[8]_i_10 
       (.I0(cntr[1]),
        .O(\cntr[8]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[8]_i_3 
       (.I0(cntr[8]),
        .O(\cntr[8]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[8]_i_4 
       (.I0(cntr[7]),
        .O(\cntr[8]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[8]_i_5 
       (.I0(cntr[6]),
        .O(\cntr[8]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[8]_i_6 
       (.I0(cntr[5]),
        .O(\cntr[8]_i_6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[8]_i_7 
       (.I0(cntr[4]),
        .O(\cntr[8]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[8]_i_8 
       (.I0(cntr[3]),
        .O(\cntr[8]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cntr[8]_i_9 
       (.I0(cntr[2]),
        .O(\cntr[8]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF000F0007)) 
    \cntr[9]_i_1 
       (.I0(\calSt_reg_n_0_[1] ),
        .I1(\calSt_reg_n_0_[0] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[2] ),
        .I4(data1[9]),
        .I5(\cntr[10]_i_2_n_0 ),
        .O(\cntr[9]_i_1_n_0 ));
  FDRE \cntr_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[0]_i_1_n_0 ),
        .Q(cntr[0]),
        .R(1'b0));
  FDRE \cntr_reg[10] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[10]_i_1_n_0 ),
        .Q(cntr[10]),
        .R(1'b0));
  FDRE \cntr_reg[11] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[11]_i_1_n_0 ),
        .Q(cntr[11]),
        .R(1'b0));
  FDRE \cntr_reg[12] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[12]_i_1_n_0 ),
        .Q(cntr[12]),
        .R(1'b0));
  FDRE \cntr_reg[13] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[13]_i_1_n_0 ),
        .Q(cntr[13]),
        .R(1'b0));
  FDRE \cntr_reg[14] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[14]_i_1_n_0 ),
        .Q(cntr[14]),
        .R(1'b0));
  FDRE \cntr_reg[15] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[15]_i_1_n_0 ),
        .Q(cntr[15]),
        .R(1'b0));
  FDRE \cntr_reg[16] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[16]_i_1_n_0 ),
        .Q(cntr[16]),
        .R(1'b0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 \cntr_reg[16]_i_2 
       (.CI(\cntr_reg[8]_i_2_n_0 ),
        .CI_TOP(1'b0),
        .CO({\cntr_reg[16]_i_2_n_0 ,\cntr_reg[16]_i_2_n_1 ,\cntr_reg[16]_i_2_n_2 ,\cntr_reg[16]_i_2_n_3 ,\cntr_reg[16]_i_2_n_4 ,\cntr_reg[16]_i_2_n_5 ,\cntr_reg[16]_i_2_n_6 ,\cntr_reg[16]_i_2_n_7 }),
        .DI(cntr[16:9]),
        .O(data1[16:9]),
        .S({\cntr[16]_i_3_n_0 ,\cntr[16]_i_4_n_0 ,\cntr[16]_i_5_n_0 ,\cntr[16]_i_6_n_0 ,\cntr[16]_i_7_n_0 ,\cntr[16]_i_8_n_0 ,\cntr[16]_i_9_n_0 ,\cntr[16]_i_10_n_0 }));
  FDRE \cntr_reg[17] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[17]_i_2_n_0 ),
        .Q(cntr[17]),
        .R(1'b0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 \cntr_reg[17]_i_3 
       (.CI(\cntr_reg[16]_i_2_n_0 ),
        .CI_TOP(1'b0),
        .CO(\NLW_cntr_reg[17]_i_3_CO_UNCONNECTED [7:0]),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_cntr_reg[17]_i_3_O_UNCONNECTED [7:1],data1[17]}),
        .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\cntr[17]_i_4_n_0 }));
  FDRE \cntr_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[1]_i_1_n_0 ),
        .Q(cntr[1]),
        .R(1'b0));
  FDRE \cntr_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[2]_i_1_n_0 ),
        .Q(cntr[2]),
        .R(1'b0));
  FDRE \cntr_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[3]_i_1_n_0 ),
        .Q(cntr[3]),
        .R(1'b0));
  FDRE \cntr_reg[4] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[4]_i_1_n_0 ),
        .Q(cntr[4]),
        .R(1'b0));
  FDRE \cntr_reg[5] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[5]_i_1_n_0 ),
        .Q(cntr[5]),
        .R(1'b0));
  FDRE \cntr_reg[6] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[6]_i_1_n_0 ),
        .Q(cntr[6]),
        .R(1'b0));
  FDRE \cntr_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[7]_i_1_n_0 ),
        .Q(cntr[7]),
        .R(1'b0));
  FDRE \cntr_reg[8] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[8]_i_1_n_0 ),
        .Q(cntr[8]),
        .R(1'b0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 \cntr_reg[8]_i_2 
       (.CI(cntr[0]),
        .CI_TOP(1'b0),
        .CO({\cntr_reg[8]_i_2_n_0 ,\cntr_reg[8]_i_2_n_1 ,\cntr_reg[8]_i_2_n_2 ,\cntr_reg[8]_i_2_n_3 ,\cntr_reg[8]_i_2_n_4 ,\cntr_reg[8]_i_2_n_5 ,\cntr_reg[8]_i_2_n_6 ,\cntr_reg[8]_i_2_n_7 }),
        .DI(cntr[8:1]),
        .O(data1[8:1]),
        .S({\cntr[8]_i_3_n_0 ,\cntr[8]_i_4_n_0 ,\cntr[8]_i_5_n_0 ,\cntr[8]_i_6_n_0 ,\cntr[8]_i_7_n_0 ,\cntr[8]_i_8_n_0 ,\cntr[8]_i_9_n_0 ,\cntr[8]_i_10_n_0 }));
  FDRE \cntr_reg[9] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_50),
        .D(\cntr[9]_i_1_n_0 ),
        .Q(cntr[9]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hAAAB2AAA)) 
    \cs_mask_int[0]_i_1 
       (.I0(\cs_mask_int_reg_n_0_[0] ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .I4(\calSt_reg_n_0_[1] ),
        .O(\cs_mask_int[0]_i_1_n_0 ));
  FDRE \cs_mask_int_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(\cs_mask_int[0]_i_1_n_0 ),
        .Q(\cs_mask_int_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1575" *) 
  LUT5 #(
    .INIT(32'hFFFF4000)) 
    initDone_i_1
       (.I0(\calSt_reg_n_0_[0] ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[3] ),
        .I4(initDone),
        .O(initDone_i_1_n_0));
  FDRE initDone_reg
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(initDone_i_1_n_0),
        .Q(initDone),
        .R(rst_r1));
  LUT4 #(
    .INIT(16'hBC70)) 
    \init_cal_ADR[103]_i_1 
       (.I0(\calSt_reg_n_0_[0] ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[1] ),
        .O(p_0_in1_in));
  LUT5 #(
    .INIT(32'h00005780)) 
    \init_cal_ADR[103]_i_2 
       (.I0(cmr_cnt[3]),
        .I1(cmr_cnt[1]),
        .I2(cmr_cnt[2]),
        .I3(cmr_cnt[4]),
        .I4(\init_cal_ADR[103]_i_3_n_0 ),
        .O(p_2_out[103]));
  (* SOFT_HLUTNM = "soft_lutpair1560" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \init_cal_ADR[103]_i_3 
       (.I0(\calSt_reg_n_0_[2] ),
        .I1(\calSt_reg_n_0_[1] ),
        .I2(\calSt_reg_n_0_[3] ),
        .O(\init_cal_ADR[103]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1575" *) 
  LUT4 #(
    .INIT(16'h4333)) 
    \init_cal_ADR[116]_i_1 
       (.I0(\calSt_reg_n_0_[0] ),
        .I1(\calSt_reg_n_0_[3] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[2] ),
        .O(p_2_out[116]));
  (* SOFT_HLUTNM = "soft_lutpair1574" *) 
  LUT4 #(
    .INIT(16'h2787)) 
    \init_cal_ADR[132]_i_1 
       (.I0(\calSt_reg_n_0_[2] ),
        .I1(\calSt_reg_n_0_[1] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .O(p_2_out[132]));
  LUT6 #(
    .INIT(64'h0000000001408440)) 
    \init_cal_ADR[15]_i_1 
       (.I0(cmr_cnt[0]),
        .I1(cmr_cnt[1]),
        .I2(cmr_cnt[2]),
        .I3(cmr_cnt[4]),
        .I4(cmr_cnt[3]),
        .I5(\init_cal_ADR[103]_i_3_n_0 ),
        .O(p_2_out[15]));
  (* SOFT_HLUTNM = "soft_lutpair1567" *) 
  LUT5 #(
    .INIT(32'hF300AAAA)) 
    \init_cal_ADR[23]_i_1 
       (.I0(\calSt_reg_n_0_[0] ),
        .I1(\calSt_reg_n_0_[1] ),
        .I2(\init_cal_ADR[23]_i_2_n_0 ),
        .I3(\calSt_reg_n_0_[2] ),
        .I4(\calSt_reg_n_0_[3] ),
        .O(p_2_out[23]));
  (* SOFT_HLUTNM = "soft_lutpair1566" *) 
  LUT5 #(
    .INIT(32'h01400088)) 
    \init_cal_ADR[23]_i_2 
       (.I0(cmr_cnt[4]),
        .I1(cmr_cnt[2]),
        .I2(cmr_cnt[1]),
        .I3(cmr_cnt[3]),
        .I4(cmr_cnt[0]),
        .O(\init_cal_ADR[23]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1571" *) 
  LUT5 #(
    .INIT(32'hD0101010)) 
    \init_cal_ADR[31]_i_1 
       (.I0(\calSt_reg_n_0_[0] ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[3] ),
        .I4(\init_cal_ADR[31]_i_2_n_0 ),
        .O(p_2_out[31]));
  (* SOFT_HLUTNM = "soft_lutpair1572" *) 
  LUT5 #(
    .INIT(32'h09480030)) 
    \init_cal_ADR[31]_i_2 
       (.I0(cmr_cnt[4]),
        .I1(cmr_cnt[0]),
        .I2(cmr_cnt[3]),
        .I3(cmr_cnt[1]),
        .I4(cmr_cnt[2]),
        .O(\init_cal_ADR[31]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1568" *) 
  LUT5 #(
    .INIT(32'h80FFC444)) 
    \init_cal_ADR[39]_i_1 
       (.I0(\calSt_reg_n_0_[2] ),
        .I1(\calSt_reg_n_0_[1] ),
        .I2(\init_cal_ADR[39]_i_2_n_0 ),
        .I3(\calSt_reg_n_0_[3] ),
        .I4(\calSt_reg_n_0_[0] ),
        .O(p_2_out[39]));
  (* SOFT_HLUTNM = "soft_lutpair1569" *) 
  LUT5 #(
    .INIT(32'h44478CCC)) 
    \init_cal_ADR[39]_i_2 
       (.I0(cmr_cnt[4]),
        .I1(cmr_cnt[0]),
        .I2(cmr_cnt[2]),
        .I3(cmr_cnt[1]),
        .I4(cmr_cnt[3]),
        .O(\init_cal_ADR[39]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1579" *) 
  LUT4 #(
    .INIT(16'hB000)) 
    \init_cal_ADR[47]_i_1 
       (.I0(\init_cal_ADR[47]_i_2_n_0 ),
        .I1(\calSt_reg_n_0_[1] ),
        .I2(\calSt_reg_n_0_[2] ),
        .I3(\calSt_reg_n_0_[3] ),
        .O(p_2_out[47]));
  (* SOFT_HLUTNM = "soft_lutpair1565" *) 
  LUT5 #(
    .INIT(32'h044A551A)) 
    \init_cal_ADR[47]_i_2 
       (.I0(cmr_cnt[4]),
        .I1(cmr_cnt[0]),
        .I2(cmr_cnt[3]),
        .I3(cmr_cnt[1]),
        .I4(cmr_cnt[2]),
        .O(\init_cal_ADR[47]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1579" *) 
  LUT4 #(
    .INIT(16'hB000)) 
    \init_cal_ADR[55]_i_1 
       (.I0(\init_cal_ADR[55]_i_2_n_0 ),
        .I1(\calSt_reg_n_0_[1] ),
        .I2(\calSt_reg_n_0_[2] ),
        .I3(\calSt_reg_n_0_[3] ),
        .O(p_2_out[55]));
  (* SOFT_HLUTNM = "soft_lutpair1566" *) 
  LUT5 #(
    .INIT(32'h005A0540)) 
    \init_cal_ADR[55]_i_2 
       (.I0(cmr_cnt[4]),
        .I1(cmr_cnt[0]),
        .I2(cmr_cnt[3]),
        .I3(cmr_cnt[2]),
        .I4(cmr_cnt[1]),
        .O(\init_cal_ADR[55]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000580258)) 
    \init_cal_ADR[63]_i_1 
       (.I0(cmr_cnt[2]),
        .I1(cmr_cnt[1]),
        .I2(cmr_cnt[3]),
        .I3(cmr_cnt[4]),
        .I4(cmr_cnt[0]),
        .I5(\init_cal_ADR[103]_i_3_n_0 ),
        .O(p_2_out[63]));
  (* SOFT_HLUTNM = "soft_lutpair1564" *) 
  LUT5 #(
    .INIT(32'h8F80F0F0)) 
    \init_cal_ADR[71]_i_1 
       (.I0(\calSt_reg_n_0_[3] ),
        .I1(\init_cal_ADR[71]_i_2_n_0 ),
        .I2(\calSt_reg_n_0_[2] ),
        .I3(\calSt_reg_n_0_[0] ),
        .I4(\calSt_reg_n_0_[1] ),
        .O(p_2_out[71]));
  (* SOFT_HLUTNM = "soft_lutpair1565" *) 
  LUT5 #(
    .INIT(32'h20482000)) 
    \init_cal_ADR[71]_i_2 
       (.I0(cmr_cnt[4]),
        .I1(cmr_cnt[3]),
        .I2(cmr_cnt[2]),
        .I3(cmr_cnt[1]),
        .I4(cmr_cnt[0]),
        .O(\init_cal_ADR[71]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hBCCC)) 
    \init_cal_ADR[79]_i_1 
       (.I0(\init_cal_ADR[79]_i_2_n_0 ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[0] ),
        .I3(\calSt_reg_n_0_[1] ),
        .O(p_2_out[79]));
  LUT6 #(
    .INIT(64'h0608420800000000)) 
    \init_cal_ADR[79]_i_2 
       (.I0(cmr_cnt[3]),
        .I1(cmr_cnt[2]),
        .I2(cmr_cnt[1]),
        .I3(cmr_cnt[4]),
        .I4(cmr_cnt[0]),
        .I5(\calSt_reg_n_0_[3] ),
        .O(\init_cal_ADR[79]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1570" *) 
  LUT5 #(
    .INIT(32'hE0202020)) 
    \init_cal_ADR[7]_i_1 
       (.I0(\calSt_reg_n_0_[0] ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[3] ),
        .I4(\init_cal_ADR[7]_i_2_n_0 ),
        .O(p_2_out[7]));
  (* SOFT_HLUTNM = "soft_lutpair1569" *) 
  LUT5 #(
    .INIT(32'h1B580228)) 
    \init_cal_ADR[7]_i_2 
       (.I0(cmr_cnt[4]),
        .I1(cmr_cnt[0]),
        .I2(cmr_cnt[3]),
        .I3(cmr_cnt[1]),
        .I4(cmr_cnt[2]),
        .O(\init_cal_ADR[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hB0CF0F3F80C00030)) 
    \init_cal_ADR[87]_i_1 
       (.I0(\init_cal_ADR[87]_i_2_n_0 ),
        .I1(\calSt_reg_n_0_[0] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[1] ),
        .I4(\calSt_reg_n_0_[2] ),
        .I5(\init_cal_ADR_reg_n_0_[87] ),
        .O(\init_cal_ADR[87]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1562" *) 
  LUT5 #(
    .INIT(32'h1A180000)) 
    \init_cal_ADR[87]_i_2 
       (.I0(cmr_cnt[2]),
        .I1(cmr_cnt[1]),
        .I2(cmr_cnt[3]),
        .I3(cmr_cnt[0]),
        .I4(cmr_cnt[4]),
        .O(\init_cal_ADR[87]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1567" *) 
  LUT4 #(
    .INIT(16'h4F40)) 
    \init_cal_ADR[95]_i_1 
       (.I0(\calSt_reg_n_0_[1] ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[3] ),
        .I3(\calSt_reg_n_0_[0] ),
        .O(p_2_out[95]));
  FDRE \init_cal_ADR_reg[103] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(p_2_out[103]),
        .Q(\init_cal_ADR_reg_n_0_[103] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[116] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(p_2_out[116]),
        .Q(\init_cal_ADR_reg_n_0_[116] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[132] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(p_2_out[132]),
        .Q(\init_cal_ADR_reg_n_0_[132] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[135] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(1'b1),
        .Q(\init_cal_ADR_reg_n_0_[135] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[15] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(p_2_out[15]),
        .Q(\init_cal_ADR_reg_n_0_[15] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[23] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(p_2_out[23]),
        .Q(\init_cal_ADR_reg_n_0_[23] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[31] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(p_2_out[31]),
        .Q(\init_cal_ADR_reg_n_0_[31] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[39] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(p_2_out[39]),
        .Q(\init_cal_ADR_reg_n_0_[39] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[47] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(p_2_out[47]),
        .Q(\init_cal_ADR_reg_n_0_[47] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[55] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(p_2_out[55]),
        .Q(\init_cal_ADR_reg_n_0_[55] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[63] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(p_2_out[63]),
        .Q(\init_cal_ADR_reg_n_0_[63] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[71] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(p_2_out[71]),
        .Q(\init_cal_ADR_reg_n_0_[71] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[79] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(p_2_out[79]),
        .Q(\init_cal_ADR_reg_n_0_[79] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(p_2_out[7]),
        .Q(\init_cal_ADR_reg_n_0_[7] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[87] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(\init_cal_ADR[87]_i_1_n_0 ),
        .Q(\init_cal_ADR_reg_n_0_[87] ),
        .R(rst_r1));
  FDRE \init_cal_ADR_reg[95] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(p_2_out[95]),
        .Q(\init_cal_ADR_reg_n_0_[95] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair1571" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \init_cal_BA[15]_i_1 
       (.I0(\calSt_reg_n_0_[0] ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[1] ),
        .O(\init_cal_BA[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1564" *) 
  LUT4 #(
    .INIT(16'hC131)) 
    \init_cal_BA[7]_i_1 
       (.I0(\calSt_reg_n_0_[2] ),
        .I1(\calSt_reg_n_0_[0] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[3] ),
        .O(\init_cal_BA[7]_i_1_n_0 ));
  FDRE \init_cal_BA_reg[15] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(\init_cal_BA[15]_i_1_n_0 ),
        .Q(init_cal_BA[15]),
        .R(rst_r1));
  FDRE \init_cal_BA_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(\init_cal_BA[7]_i_1_n_0 ),
        .Q(init_cal_BA[7]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair1573" *) 
  LUT3 #(
    .INIT(8'h83)) 
    \init_cal_BG[7]_i_1 
       (.I0(\calSt_reg_n_0_[0] ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[1] ),
        .O(\init_cal_BG[7]_i_1_n_0 ));
  FDRE \init_cal_BG_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(p_0_in1_in),
        .D(\init_cal_BG[7]_i_1_n_0 ),
        .Q(init_cal_BG),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair1574" *) 
  LUT5 #(
    .INIT(32'hFFFF0040)) 
    \init_cal_CKE[7]_i_1 
       (.I0(\calSt_reg_n_0_[1] ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[0] ),
        .I3(\calSt_reg_n_0_[3] ),
        .I4(init_cal_CKE),
        .O(\init_cal_CKE[7]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \init_cal_CKE_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(\init_cal_CKE[7]_i_1_n_0 ),
        .Q(init_cal_CKE),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h157FD57F)) 
    \init_cal_CS_n[4]_i_1 
       (.I0(\cs_mask_int_reg_n_0_[0] ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[3] ),
        .I4(\calSt_reg_n_0_[0] ),
        .O(\init_cal_CS_n[4]_i_1_n_0 ));
  FDSE \init_cal_CS_n_reg[4] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(\init_cal_CS_n[4]_i_1_n_0 ),
        .Q(init_cal_CS_n),
        .S(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair1561" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \init_cal_RESET_n[7]_i_2 
       (.I0(\calSt_reg_n_0_[2] ),
        .I1(\calSt_reg_n_0_[3] ),
        .O(\init_cal_RESET_n[7]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \init_cal_RESET_n_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(u_ddr_cal_addr_decode_n_52),
        .Q(init_cal_RESET_n),
        .R(rst_r1));
  FDSE \lowCL0_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[0]),
        .Q(lowCL0[0]),
        .S(rst_r1));
  FDSE \lowCL0_reg[12] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[12]),
        .Q(lowCL0[12]),
        .S(rst_r1));
  FDRE \lowCL0_reg[13] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[13]),
        .Q(lowCL0[13]),
        .R(rst_r1));
  FDRE \lowCL0_reg[14] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[14]),
        .Q(lowCL0[14]),
        .R(rst_r1));
  FDRE \lowCL0_reg[15] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[15]),
        .Q(lowCL0[15]),
        .R(rst_r1));
  FDSE \lowCL0_reg[18] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[18]),
        .Q(lowCL0[18]),
        .S(rst_r1));
  FDRE \lowCL0_reg[19] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[19]),
        .Q(lowCL0[19]),
        .R(rst_r1));
  FDRE \lowCL0_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[1]),
        .Q(lowCL0[1]),
        .R(rst_r1));
  FDRE \lowCL0_reg[20] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[20]),
        .Q(lowCL0[20]),
        .R(rst_r1));
  FDRE \lowCL0_reg[21] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[21]),
        .Q(lowCL0[21]),
        .R(rst_r1));
  FDSE \lowCL0_reg[24] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[24]),
        .Q(lowCL0[24]),
        .S(rst_r1));
  FDRE \lowCL0_reg[25] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[25]),
        .Q(lowCL0[25]),
        .R(rst_r1));
  FDRE \lowCL0_reg[26] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[26]),
        .Q(lowCL0[26]),
        .R(rst_r1));
  FDRE \lowCL0_reg[27] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[27]),
        .Q(lowCL0[27]),
        .R(rst_r1));
  FDRE \lowCL0_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[2]),
        .Q(lowCL0[2]),
        .R(rst_r1));
  FDSE \lowCL0_reg[30] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[30]),
        .Q(lowCL0[30]),
        .S(rst_r1));
  FDRE \lowCL0_reg[31] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[31]),
        .Q(lowCL0[31]),
        .R(rst_r1));
  FDRE \lowCL0_reg[32] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[32]),
        .Q(lowCL0[32]),
        .R(rst_r1));
  FDRE \lowCL0_reg[33] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[33]),
        .Q(lowCL0[33]),
        .R(rst_r1));
  FDSE \lowCL0_reg[36] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[36]),
        .Q(lowCL0[36]),
        .S(rst_r1));
  FDRE \lowCL0_reg[37] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[37]),
        .Q(lowCL0[37]),
        .R(rst_r1));
  FDRE \lowCL0_reg[38] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[38]),
        .Q(lowCL0[38]),
        .R(rst_r1));
  FDRE \lowCL0_reg[39] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[39]),
        .Q(lowCL0[39]),
        .R(rst_r1));
  FDRE \lowCL0_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[3]),
        .Q(lowCL0[3]),
        .R(rst_r1));
  FDSE \lowCL0_reg[42] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[42]),
        .Q(lowCL0[42]),
        .S(rst_r1));
  FDRE \lowCL0_reg[43] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[43]),
        .Q(lowCL0[43]),
        .R(rst_r1));
  FDRE \lowCL0_reg[44] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[44]),
        .Q(lowCL0[44]),
        .R(rst_r1));
  FDRE \lowCL0_reg[45] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[45]),
        .Q(lowCL0[45]),
        .R(rst_r1));
  FDSE \lowCL0_reg[6] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[6]),
        .Q(lowCL0[6]),
        .S(rst_r1));
  FDRE \lowCL0_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[7]),
        .Q(lowCL0[7]),
        .R(rst_r1));
  FDRE \lowCL0_reg[8] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[8]),
        .Q(lowCL0[8]),
        .R(rst_r1));
  FDRE \lowCL0_reg[9] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL0[9]),
        .Q(lowCL0[9]),
        .R(rst_r1));
  FDSE \lowCL1_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[0]),
        .Q(lowCL1[0]),
        .S(rst_r1));
  FDSE \lowCL1_reg[12] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[12]),
        .Q(lowCL1[12]),
        .S(rst_r1));
  FDRE \lowCL1_reg[13] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[13]),
        .Q(lowCL1[13]),
        .R(rst_r1));
  FDRE \lowCL1_reg[14] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[14]),
        .Q(lowCL1[14]),
        .R(rst_r1));
  FDRE \lowCL1_reg[15] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[15]),
        .Q(lowCL1[15]),
        .R(rst_r1));
  FDSE \lowCL1_reg[18] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[18]),
        .Q(lowCL1[18]),
        .S(rst_r1));
  FDRE \lowCL1_reg[19] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[19]),
        .Q(lowCL1[19]),
        .R(rst_r1));
  FDRE \lowCL1_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[1]),
        .Q(lowCL1[1]),
        .R(rst_r1));
  FDRE \lowCL1_reg[20] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[20]),
        .Q(lowCL1[20]),
        .R(rst_r1));
  FDRE \lowCL1_reg[21] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[21]),
        .Q(lowCL1[21]),
        .R(rst_r1));
  FDSE \lowCL1_reg[24] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[24]),
        .Q(lowCL1[24]),
        .S(rst_r1));
  FDRE \lowCL1_reg[25] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[25]),
        .Q(lowCL1[25]),
        .R(rst_r1));
  FDRE \lowCL1_reg[26] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[26]),
        .Q(lowCL1[26]),
        .R(rst_r1));
  FDRE \lowCL1_reg[27] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[27]),
        .Q(lowCL1[27]),
        .R(rst_r1));
  FDRE \lowCL1_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[2]),
        .Q(lowCL1[2]),
        .R(rst_r1));
  FDSE \lowCL1_reg[30] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[30]),
        .Q(lowCL1[30]),
        .S(rst_r1));
  FDRE \lowCL1_reg[31] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[31]),
        .Q(lowCL1[31]),
        .R(rst_r1));
  FDRE \lowCL1_reg[32] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[32]),
        .Q(lowCL1[32]),
        .R(rst_r1));
  FDRE \lowCL1_reg[33] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[33]),
        .Q(lowCL1[33]),
        .R(rst_r1));
  FDSE \lowCL1_reg[36] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[36]),
        .Q(lowCL1[36]),
        .S(rst_r1));
  FDRE \lowCL1_reg[37] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[37]),
        .Q(lowCL1[37]),
        .R(rst_r1));
  FDRE \lowCL1_reg[38] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[38]),
        .Q(lowCL1[38]),
        .R(rst_r1));
  FDRE \lowCL1_reg[39] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[39]),
        .Q(lowCL1[39]),
        .R(rst_r1));
  FDRE \lowCL1_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[3]),
        .Q(lowCL1[3]),
        .R(rst_r1));
  FDSE \lowCL1_reg[42] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[42]),
        .Q(lowCL1[42]),
        .S(rst_r1));
  FDRE \lowCL1_reg[43] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[43]),
        .Q(lowCL1[43]),
        .R(rst_r1));
  FDRE \lowCL1_reg[44] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[44]),
        .Q(lowCL1[44]),
        .R(rst_r1));
  FDRE \lowCL1_reg[45] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[45]),
        .Q(lowCL1[45]),
        .R(rst_r1));
  FDSE \lowCL1_reg[6] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[6]),
        .Q(lowCL1[6]),
        .S(rst_r1));
  FDRE \lowCL1_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[7]),
        .Q(lowCL1[7]),
        .R(rst_r1));
  FDRE \lowCL1_reg[8] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[8]),
        .Q(lowCL1[8]),
        .R(rst_r1));
  FDRE \lowCL1_reg[9] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL1[9]),
        .Q(lowCL1[9]),
        .R(rst_r1));
  FDSE \lowCL2_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[0]),
        .Q(lowCL2[0]),
        .S(rst_r1));
  FDSE \lowCL2_reg[12] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[12]),
        .Q(lowCL2[12]),
        .S(rst_r1));
  FDRE \lowCL2_reg[13] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[13]),
        .Q(lowCL2[13]),
        .R(rst_r1));
  FDRE \lowCL2_reg[14] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[14]),
        .Q(lowCL2[14]),
        .R(rst_r1));
  FDRE \lowCL2_reg[15] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[15]),
        .Q(lowCL2[15]),
        .R(rst_r1));
  FDSE \lowCL2_reg[18] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[18]),
        .Q(lowCL2[18]),
        .S(rst_r1));
  FDRE \lowCL2_reg[19] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[19]),
        .Q(lowCL2[19]),
        .R(rst_r1));
  FDRE \lowCL2_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[1]),
        .Q(lowCL2[1]),
        .R(rst_r1));
  FDRE \lowCL2_reg[20] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[20]),
        .Q(lowCL2[20]),
        .R(rst_r1));
  FDRE \lowCL2_reg[21] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[21]),
        .Q(lowCL2[21]),
        .R(rst_r1));
  FDSE \lowCL2_reg[24] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[24]),
        .Q(lowCL2[24]),
        .S(rst_r1));
  FDRE \lowCL2_reg[25] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[25]),
        .Q(lowCL2[25]),
        .R(rst_r1));
  FDRE \lowCL2_reg[26] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[26]),
        .Q(lowCL2[26]),
        .R(rst_r1));
  FDRE \lowCL2_reg[27] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[27]),
        .Q(lowCL2[27]),
        .R(rst_r1));
  FDRE \lowCL2_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[2]),
        .Q(lowCL2[2]),
        .R(rst_r1));
  FDSE \lowCL2_reg[30] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[30]),
        .Q(lowCL2[30]),
        .S(rst_r1));
  FDRE \lowCL2_reg[31] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[31]),
        .Q(lowCL2[31]),
        .R(rst_r1));
  FDRE \lowCL2_reg[32] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[32]),
        .Q(lowCL2[32]),
        .R(rst_r1));
  FDRE \lowCL2_reg[33] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[33]),
        .Q(lowCL2[33]),
        .R(rst_r1));
  FDSE \lowCL2_reg[36] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[36]),
        .Q(lowCL2[36]),
        .S(rst_r1));
  FDRE \lowCL2_reg[37] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[37]),
        .Q(lowCL2[37]),
        .R(rst_r1));
  FDRE \lowCL2_reg[38] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[38]),
        .Q(lowCL2[38]),
        .R(rst_r1));
  FDRE \lowCL2_reg[39] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[39]),
        .Q(lowCL2[39]),
        .R(rst_r1));
  FDRE \lowCL2_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[3]),
        .Q(lowCL2[3]),
        .R(rst_r1));
  FDSE \lowCL2_reg[42] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[42]),
        .Q(lowCL2[42]),
        .S(rst_r1));
  FDRE \lowCL2_reg[43] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[43]),
        .Q(lowCL2[43]),
        .R(rst_r1));
  FDRE \lowCL2_reg[44] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[44]),
        .Q(lowCL2[44]),
        .R(rst_r1));
  FDRE \lowCL2_reg[45] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[45]),
        .Q(lowCL2[45]),
        .R(rst_r1));
  FDSE \lowCL2_reg[6] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[6]),
        .Q(lowCL2[6]),
        .S(rst_r1));
  FDRE \lowCL2_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[7]),
        .Q(lowCL2[7]),
        .R(rst_r1));
  FDRE \lowCL2_reg[8] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[8]),
        .Q(lowCL2[8]),
        .R(rst_r1));
  FDRE \lowCL2_reg[9] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL2[9]),
        .Q(lowCL2[9]),
        .R(rst_r1));
  FDSE \lowCL3_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[0]),
        .Q(lowCL3[0]),
        .S(rst_r1));
  FDSE \lowCL3_reg[12] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[12]),
        .Q(lowCL3[12]),
        .S(rst_r1));
  FDRE \lowCL3_reg[13] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[13]),
        .Q(lowCL3[13]),
        .R(rst_r1));
  FDRE \lowCL3_reg[14] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[14]),
        .Q(lowCL3[14]),
        .R(rst_r1));
  FDRE \lowCL3_reg[15] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[15]),
        .Q(lowCL3[15]),
        .R(rst_r1));
  FDSE \lowCL3_reg[18] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[18]),
        .Q(lowCL3[18]),
        .S(rst_r1));
  FDRE \lowCL3_reg[19] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[19]),
        .Q(lowCL3[19]),
        .R(rst_r1));
  FDRE \lowCL3_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[1]),
        .Q(lowCL3[1]),
        .R(rst_r1));
  FDRE \lowCL3_reg[20] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[20]),
        .Q(lowCL3[20]),
        .R(rst_r1));
  FDRE \lowCL3_reg[21] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[21]),
        .Q(lowCL3[21]),
        .R(rst_r1));
  FDSE \lowCL3_reg[24] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[24]),
        .Q(lowCL3[24]),
        .S(rst_r1));
  FDRE \lowCL3_reg[25] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[25]),
        .Q(lowCL3[25]),
        .R(rst_r1));
  FDRE \lowCL3_reg[26] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[26]),
        .Q(lowCL3[26]),
        .R(rst_r1));
  FDRE \lowCL3_reg[27] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[27]),
        .Q(lowCL3[27]),
        .R(rst_r1));
  FDRE \lowCL3_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[2]),
        .Q(lowCL3[2]),
        .R(rst_r1));
  FDSE \lowCL3_reg[30] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[30]),
        .Q(lowCL3[30]),
        .S(rst_r1));
  FDRE \lowCL3_reg[31] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[31]),
        .Q(lowCL3[31]),
        .R(rst_r1));
  FDRE \lowCL3_reg[32] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[32]),
        .Q(lowCL3[32]),
        .R(rst_r1));
  FDRE \lowCL3_reg[33] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[33]),
        .Q(lowCL3[33]),
        .R(rst_r1));
  FDSE \lowCL3_reg[36] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[36]),
        .Q(lowCL3[36]),
        .S(rst_r1));
  FDRE \lowCL3_reg[37] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[37]),
        .Q(lowCL3[37]),
        .R(rst_r1));
  FDRE \lowCL3_reg[38] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[38]),
        .Q(lowCL3[38]),
        .R(rst_r1));
  FDRE \lowCL3_reg[39] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[39]),
        .Q(lowCL3[39]),
        .R(rst_r1));
  FDRE \lowCL3_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[3]),
        .Q(lowCL3[3]),
        .R(rst_r1));
  FDSE \lowCL3_reg[42] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[42]),
        .Q(lowCL3[42]),
        .S(rst_r1));
  FDRE \lowCL3_reg[43] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[43]),
        .Q(lowCL3[43]),
        .R(rst_r1));
  FDRE \lowCL3_reg[44] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[44]),
        .Q(lowCL3[44]),
        .R(rst_r1));
  FDRE \lowCL3_reg[45] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[45]),
        .Q(lowCL3[45]),
        .R(rst_r1));
  FDSE \lowCL3_reg[6] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[6]),
        .Q(lowCL3[6]),
        .S(rst_r1));
  FDRE \lowCL3_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[7]),
        .Q(lowCL3[7]),
        .R(rst_r1));
  FDRE \lowCL3_reg[8] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[8]),
        .Q(lowCL3[8]),
        .R(rst_r1));
  FDRE \lowCL3_reg[9] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_lowCL3[9]),
        .Q(lowCL3[9]),
        .R(rst_r1));
  FDSE \max_rd_lat_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_max_rd_lat[0]),
        .Q(max_rd_lat[0]),
        .S(rst_r1));
  FDSE \max_rd_lat_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_max_rd_lat[1]),
        .Q(max_rd_lat[1]),
        .S(rst_r1));
  FDRE \max_rd_lat_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_max_rd_lat[2]),
        .Q(max_rd_lat[2]),
        .R(rst_r1));
  FDRE \max_rd_lat_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_max_rd_lat[3]),
        .Q(max_rd_lat[3]),
        .R(rst_r1));
  FDSE \max_rd_lat_reg[4] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_max_rd_lat[4]),
        .Q(max_rd_lat[4]),
        .S(rst_r1));
  FDRE \max_rd_lat_reg[5] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_max_rd_lat[5]),
        .Q(max_rd_lat[5]),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_1 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_2_n_0 ),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_n_0 ),
        .I2(\u_ddr_mc_pi/u_ddr_mc_read/read_lat_shift_rptr__8 [3]),
        .I3(\mc_clb2phy_fifo_rden_nxt[103]_i_5_n_0 ),
        .I4(\mc_clb2phy_fifo_rden_nxt[103]_i_6_n_0 ),
        .I5(\mc_clb2phy_fifo_rden_nxt[103]_i_7_n_0 ),
        .O(read_lat_shift_cal_dq_valid_nxt));
  LUT5 #(
    .INIT(32'h55555556)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_10 
       (.I0(max_rd_lat[4]),
        .I1(max_rd_lat[3]),
        .I2(max_rd_lat[0]),
        .I3(max_rd_lat[1]),
        .I4(max_rd_lat[2]),
        .O(\u_ddr_mc_pi/u_ddr_mc_read/read_lat_shift_rptr__8 [2]));
  LUT6 #(
    .INIT(64'h00AC00AC00ACAC00)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_11 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [10]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [8]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[1]),
        .I5(max_rd_lat[0]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAC00AC00AC0000CA)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_12 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [11]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [9]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[0]),
        .I5(max_rd_lat[1]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h00AC00AC00ACAC00)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_13 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [30]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [28]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[1]),
        .I5(max_rd_lat[0]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAC00AC00AC0000CA)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_14 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [31]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [29]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[0]),
        .I5(max_rd_lat[1]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h00AC00AC00ACAC00)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_15 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [26]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [24]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[1]),
        .I5(max_rd_lat[0]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hAC00AC00AC0000CA)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_16 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [27]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [25]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[0]),
        .I5(max_rd_lat[1]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h00AC00AC00ACAC00)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_17 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [6]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [4]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[1]),
        .I5(max_rd_lat[0]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hAC00AC00AC0000CA)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_18 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [7]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [5]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[0]),
        .I5(max_rd_lat[1]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h00AC00AC00ACAC00)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_19 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [2]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [0]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[1]),
        .I5(max_rd_lat[0]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_19_n_0 ));
  LUT5 #(
    .INIT(32'hEFEFEFE0)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_2 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_8_n_0 ),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_9_n_0 ),
        .I2(\u_ddr_mc_pi/u_ddr_mc_read/read_lat_shift_rptr__8 [2]),
        .I3(\mc_clb2phy_fifo_rden_nxt[103]_i_11_n_0 ),
        .I4(\mc_clb2phy_fifo_rden_nxt[103]_i_12_n_0 ),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAC00AC00AC0000CA)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_20 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [3]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [1]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[0]),
        .I5(max_rd_lat[1]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h00AC00AC00ACAC00)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_21 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [22]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [20]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[1]),
        .I5(max_rd_lat[0]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'hAC00AC00AC0000CA)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_22 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [23]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [21]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[0]),
        .I5(max_rd_lat[1]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'h00AC00AC00ACAC00)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_23 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [18]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [16]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[1]),
        .I5(max_rd_lat[0]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'hAC00AC00AC0000CA)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_24 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [19]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [17]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[0]),
        .I5(max_rd_lat[1]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_24_n_0 ));
  LUT5 #(
    .INIT(32'hEFEFEFE0)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_3 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_13_n_0 ),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_14_n_0 ),
        .I2(\u_ddr_mc_pi/u_ddr_mc_read/read_lat_shift_rptr__8 [2]),
        .I3(\mc_clb2phy_fifo_rden_nxt[103]_i_15_n_0 ),
        .I4(\mc_clb2phy_fifo_rden_nxt[103]_i_16_n_0 ),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h55555556AAAAAAAA)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_4 
       (.I0(max_rd_lat[5]),
        .I1(max_rd_lat[2]),
        .I2(max_rd_lat[1]),
        .I3(max_rd_lat[0]),
        .I4(max_rd_lat[3]),
        .I5(max_rd_lat[4]),
        .O(\u_ddr_mc_pi/u_ddr_mc_read/read_lat_shift_rptr__8 [3]));
  LUT6 #(
    .INIT(64'hAAAAAAA800000000)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_5 
       (.I0(max_rd_lat[5]),
        .I1(max_rd_lat[2]),
        .I2(max_rd_lat[1]),
        .I3(max_rd_lat[0]),
        .I4(max_rd_lat[3]),
        .I5(max_rd_lat[4]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hEFEFEFE0)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_6 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_17_n_0 ),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_18_n_0 ),
        .I2(\u_ddr_mc_pi/u_ddr_mc_read/read_lat_shift_rptr__8 [2]),
        .I3(\mc_clb2phy_fifo_rden_nxt[103]_i_19_n_0 ),
        .I4(\mc_clb2phy_fifo_rden_nxt[103]_i_20_n_0 ),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hEFEFEFE0)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_7 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_21_n_0 ),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_22_n_0 ),
        .I2(\u_ddr_mc_pi/u_ddr_mc_read/read_lat_shift_rptr__8 [2]),
        .I3(\mc_clb2phy_fifo_rden_nxt[103]_i_23_n_0 ),
        .I4(\mc_clb2phy_fifo_rden_nxt[103]_i_24_n_0 ),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h00AC00AC00ACAC00)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_8 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [14]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [12]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[1]),
        .I5(max_rd_lat[0]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAC00AC00AC0000CA)) 
    \mc_clb2phy_fifo_rden_nxt[103]_i_9 
       (.I0(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [15]),
        .I1(\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 [13]),
        .I2(max_rd_lat[3]),
        .I3(max_rd_lat[2]),
        .I4(max_rd_lat[0]),
        .I5(max_rd_lat[1]),
        .O(\mc_clb2phy_fifo_rden_nxt[103]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1578" *) 
  LUT4 #(
    .INIT(16'h69FF)) 
    \mcal_PAR_dly[0][0]_i_2 
       (.I0(\mcal_PAR_dly_reg[0][0] ),
        .I1(p_1_in),
        .I2(Q[0]),
        .I3(calDone_reg_1),
        .O(\mcal_PAR_dly[0][0]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \oe_0_mux_cal[0]_i_1 
       (.I0(calDone_reg_1),
        .O(calDone_reg_13));
  (* SOFT_HLUTNM = "soft_lutpair1581" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[0][2]_i_1 
       (.I0(\uppCL0_reg[45]_0 [0]),
        .I1(\uppCL0_reg[45]_0 [1]),
        .I2(\uppCL0_reg[45]_0 [2]),
        .I3(uppCL0[6]),
        .O(\uppCL0_reg[8]_6 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1956" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[0][3]_i_1 
       (.I0(\uppCL0_reg[45]_0 [0]),
        .I1(\uppCL0_reg[45]_0 [1]),
        .I2(\uppCL0_reg[45]_0 [2]),
        .O(\uppCL0_reg[8]_6 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2092" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[0][9]_i_1 
       (.I0(\uppCL0_reg[45]_0 [1]),
        .I1(\uppCL0_reg[45]_0 [2]),
        .O(\uppCL0_reg[8]_6 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1764" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[1][5]_i_1 
       (.I0(\uppCL0_reg[45]_0 [0]),
        .I1(\uppCL0_reg[45]_0 [1]),
        .I2(\uppCL0_reg[45]_0 [2]),
        .O(\blk1.(null)[0].diff_27 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2212" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[1][9]_i_1 
       (.I0(\uppCL0_reg[45]_0 [0]),
        .I1(\uppCL0_reg[45]_0 [1]),
        .O(\blk1.(null)[0].diff_27 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1583" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[2][2]_i_1 
       (.I0(\uppCL1_reg[45]_0 [0]),
        .I1(\uppCL1_reg[45]_0 [1]),
        .I2(\uppCL1_reg[45]_0 [2]),
        .I3(uppCL1[6]),
        .O(\uppCL1_reg[8]_7 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1957" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[2][3]_i_1 
       (.I0(\uppCL1_reg[45]_0 [0]),
        .I1(\uppCL1_reg[45]_0 [1]),
        .I2(\uppCL1_reg[45]_0 [2]),
        .O(\uppCL1_reg[8]_7 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2093" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[2][9]_i_1 
       (.I0(\uppCL1_reg[45]_0 [1]),
        .I1(\uppCL1_reg[45]_0 [2]),
        .O(\uppCL1_reg[8]_7 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1765" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[3][5]_i_1 
       (.I0(\uppCL1_reg[45]_0 [0]),
        .I1(\uppCL1_reg[45]_0 [1]),
        .I2(\uppCL1_reg[45]_0 [2]),
        .O(\uppCL1_reg[7]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2213" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[3][9]_i_1 
       (.I0(\uppCL1_reg[45]_0 [0]),
        .I1(\uppCL1_reg[45]_0 [1]),
        .O(\uppCL1_reg[7]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1585" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[4][2]_i_1 
       (.I0(\uppCL2_reg[45]_0 [0]),
        .I1(\uppCL2_reg[45]_0 [1]),
        .I2(\uppCL2_reg[45]_0 [2]),
        .I3(uppCL2[6]),
        .O(\uppCL2_reg[8]_7 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1958" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[4][3]_i_1 
       (.I0(\uppCL2_reg[45]_0 [0]),
        .I1(\uppCL2_reg[45]_0 [1]),
        .I2(\uppCL2_reg[45]_0 [2]),
        .O(\uppCL2_reg[8]_7 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2094" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[4][9]_i_1 
       (.I0(\uppCL2_reg[45]_0 [1]),
        .I1(\uppCL2_reg[45]_0 [2]),
        .O(\uppCL2_reg[8]_7 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1766" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[5][5]_i_1 
       (.I0(\uppCL2_reg[45]_0 [0]),
        .I1(\uppCL2_reg[45]_0 [1]),
        .I2(\uppCL2_reg[45]_0 [2]),
        .O(\uppCL2_reg[7]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2214" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[5][9]_i_1 
       (.I0(\uppCL2_reg[45]_0 [0]),
        .I1(\uppCL2_reg[45]_0 [1]),
        .O(\uppCL2_reg[7]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1587" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[6][2]_i_1 
       (.I0(\uppCL3_reg[45]_0 [0]),
        .I1(\uppCL3_reg[45]_0 [1]),
        .I2(\uppCL3_reg[45]_0 [2]),
        .I3(uppCL3[6]),
        .O(\uppCL3_reg[8]_7 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1959" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[6][3]_i_1 
       (.I0(\uppCL3_reg[45]_0 [0]),
        .I1(\uppCL3_reg[45]_0 [1]),
        .I2(\uppCL3_reg[45]_0 [2]),
        .O(\uppCL3_reg[8]_7 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2095" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[6][9]_i_1 
       (.I0(\uppCL3_reg[45]_0 [1]),
        .I1(\uppCL3_reg[45]_0 [2]),
        .O(\uppCL3_reg[8]_7 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1767" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[7][5]_i_1 
       (.I0(\uppCL3_reg[45]_0 [0]),
        .I1(\uppCL3_reg[45]_0 [1]),
        .I2(\uppCL3_reg[45]_0 [2]),
        .O(\uppCL3_reg[7]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2215" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rdEn[1].u_ddr_mc_rd_en_upp/rsMask[7][9]_i_1 
       (.I0(\uppCL3_reg[45]_0 [0]),
        .I1(\uppCL3_reg[45]_0 [1]),
        .O(\uppCL3_reg[7]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1589" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[0][2]_i_1 
       (.I0(\uppCL0_reg[45]_0 [3]),
        .I1(\uppCL0_reg[45]_0 [4]),
        .I2(\uppCL0_reg[45]_0 [5]),
        .I3(uppCL0[42]),
        .O(\uppCL0_reg[44]_6 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1960" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[0][3]_i_1 
       (.I0(\uppCL0_reg[45]_0 [3]),
        .I1(\uppCL0_reg[45]_0 [4]),
        .I2(\uppCL0_reg[45]_0 [5]),
        .O(\uppCL0_reg[44]_6 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2096" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[0][9]_i_1 
       (.I0(\uppCL0_reg[45]_0 [4]),
        .I1(\uppCL0_reg[45]_0 [5]),
        .O(\uppCL0_reg[44]_6 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1768" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[1][5]_i_1 
       (.I0(\uppCL0_reg[45]_0 [3]),
        .I1(\uppCL0_reg[45]_0 [4]),
        .I2(\uppCL0_reg[45]_0 [5]),
        .O(\blk1.(null)[0].diff_28 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2216" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[1][9]_i_1 
       (.I0(\uppCL0_reg[45]_0 [3]),
        .I1(\uppCL0_reg[45]_0 [4]),
        .O(\blk1.(null)[0].diff_28 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1591" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[2][2]_i_1 
       (.I0(\uppCL1_reg[45]_0 [3]),
        .I1(\uppCL1_reg[45]_0 [4]),
        .I2(\uppCL1_reg[45]_0 [5]),
        .I3(uppCL1[42]),
        .O(\uppCL1_reg[44]_7 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1961" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[2][3]_i_1 
       (.I0(\uppCL1_reg[45]_0 [3]),
        .I1(\uppCL1_reg[45]_0 [4]),
        .I2(\uppCL1_reg[45]_0 [5]),
        .O(\uppCL1_reg[44]_7 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2097" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[2][9]_i_1 
       (.I0(\uppCL1_reg[45]_0 [4]),
        .I1(\uppCL1_reg[45]_0 [5]),
        .O(\uppCL1_reg[44]_7 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1769" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[3][5]_i_1 
       (.I0(\uppCL1_reg[45]_0 [3]),
        .I1(\uppCL1_reg[45]_0 [4]),
        .I2(\uppCL1_reg[45]_0 [5]),
        .O(\uppCL1_reg[43]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2217" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[3][9]_i_1 
       (.I0(\uppCL1_reg[45]_0 [3]),
        .I1(\uppCL1_reg[45]_0 [4]),
        .O(\uppCL1_reg[43]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1593" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[4][2]_i_1 
       (.I0(\uppCL2_reg[45]_0 [3]),
        .I1(\uppCL2_reg[45]_0 [4]),
        .I2(\uppCL2_reg[45]_0 [5]),
        .I3(uppCL2[42]),
        .O(\uppCL2_reg[44]_7 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1962" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[4][3]_i_1 
       (.I0(\uppCL2_reg[45]_0 [3]),
        .I1(\uppCL2_reg[45]_0 [4]),
        .I2(\uppCL2_reg[45]_0 [5]),
        .O(\uppCL2_reg[44]_7 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2098" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[4][9]_i_1 
       (.I0(\uppCL2_reg[45]_0 [4]),
        .I1(\uppCL2_reg[45]_0 [5]),
        .O(\uppCL2_reg[44]_7 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1770" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[5][5]_i_1 
       (.I0(\uppCL2_reg[45]_0 [3]),
        .I1(\uppCL2_reg[45]_0 [4]),
        .I2(\uppCL2_reg[45]_0 [5]),
        .O(\uppCL2_reg[43]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2218" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[5][9]_i_1 
       (.I0(\uppCL2_reg[45]_0 [3]),
        .I1(\uppCL2_reg[45]_0 [4]),
        .O(\uppCL2_reg[43]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1595" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[6][2]_i_1 
       (.I0(\uppCL3_reg[45]_0 [3]),
        .I1(\uppCL3_reg[45]_0 [4]),
        .I2(\uppCL3_reg[45]_0 [5]),
        .I3(uppCL3[42]),
        .O(\uppCL3_reg[44]_7 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1963" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[6][3]_i_1 
       (.I0(\uppCL3_reg[45]_0 [3]),
        .I1(\uppCL3_reg[45]_0 [4]),
        .I2(\uppCL3_reg[45]_0 [5]),
        .O(\uppCL3_reg[44]_7 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2099" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[6][9]_i_1 
       (.I0(\uppCL3_reg[45]_0 [4]),
        .I1(\uppCL3_reg[45]_0 [5]),
        .O(\uppCL3_reg[44]_7 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1771" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[7][5]_i_1 
       (.I0(\uppCL3_reg[45]_0 [3]),
        .I1(\uppCL3_reg[45]_0 [4]),
        .I2(\uppCL3_reg[45]_0 [5]),
        .O(\uppCL3_reg[43]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2219" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rdEn[7].u_ddr_mc_rd_en_upp/rsMask[7][9]_i_1 
       (.I0(\uppCL3_reg[45]_0 [3]),
        .I1(\uppCL3_reg[45]_0 [4]),
        .O(\uppCL3_reg[43]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1563" *) 
  LUT5 #(
    .INIT(32'h8B3F0F03)) 
    \retSt[0]_i_1 
       (.I0(\retSt[3]_i_3_n_0 ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[0] ),
        .I3(\calSt_reg_n_0_[3] ),
        .I4(\calSt_reg_n_0_[1] ),
        .O(\retSt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1568" *) 
  LUT4 #(
    .INIT(16'hBD2C)) 
    \retSt[1]_i_1 
       (.I0(\calSt_reg_n_0_[3] ),
        .I1(\calSt_reg_n_0_[0] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[2] ),
        .O(\retSt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1570" *) 
  LUT4 #(
    .INIT(16'hBDCC)) 
    \retSt[2]_i_1 
       (.I0(\calSt_reg_n_0_[3] ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[0] ),
        .I3(\calSt_reg_n_0_[1] ),
        .O(\retSt[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1563" *) 
  LUT5 #(
    .INIT(32'hFF803F80)) 
    \retSt[3]_i_2 
       (.I0(\calSt_reg_n_0_[0] ),
        .I1(\calSt_reg_n_0_[2] ),
        .I2(\calSt_reg_n_0_[1] ),
        .I3(\calSt_reg_n_0_[3] ),
        .I4(\retSt[3]_i_3_n_0 ),
        .O(\retSt[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1562" *) 
  LUT5 #(
    .INIT(32'hFDFFFFFF)) 
    \retSt[3]_i_3 
       (.I0(cmr_cnt[3]),
        .I1(cmr_cnt[1]),
        .I2(cmr_cnt[4]),
        .I3(cmr_cnt[0]),
        .I4(cmr_cnt[2]),
        .O(\retSt[3]_i_3_n_0 ));
  FDRE \retSt_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_51),
        .D(\retSt[0]_i_1_n_0 ),
        .Q(retSt[0]),
        .R(rst_r1));
  FDRE \retSt_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_51),
        .D(\retSt[1]_i_1_n_0 ),
        .Q(retSt[1]),
        .R(rst_r1));
  FDRE \retSt_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_51),
        .D(\retSt[2]_i_1_n_0 ),
        .Q(retSt[2]),
        .R(rst_r1));
  FDRE \retSt_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(u_ddr_cal_addr_decode_n_51),
        .D(\retSt[3]_i_2_n_0 ),
        .Q(retSt[3]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair1708" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1 
       (.I0(uppCL0[39]),
        .I1(uppCL0[38]),
        .I2(uppCL0[37]),
        .O(\uppCL0_reg[39]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1712" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__0 
       (.I0(uppCL0[21]),
        .I1(uppCL0[20]),
        .I2(uppCL0[19]),
        .O(\uppCL0_reg[21]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1716" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__1 
       (.I0(uppCL0[15]),
        .I1(uppCL0[14]),
        .I2(uppCL0[13]),
        .O(\uppCL0_reg[15]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1744" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__10 
       (.I0(lowCL0[39]),
        .I1(lowCL0[38]),
        .I2(lowCL0[37]),
        .O(\lowCL0_reg[39]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1748" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__11 
       (.I0(lowCL0[21]),
        .I1(lowCL0[20]),
        .I2(lowCL0[19]),
        .O(\lowCL0_reg[21]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1752" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__12 
       (.I0(lowCL0[15]),
        .I1(lowCL0[14]),
        .I2(lowCL0[13]),
        .O(\lowCL0_reg[15]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1756" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__13 
       (.I0(lowCL0[9]),
        .I1(lowCL0[8]),
        .I2(lowCL0[7]),
        .O(\lowCL0_reg[9]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1760" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__14 
       (.I0(lowCL0[3]),
        .I1(lowCL0[2]),
        .I2(lowCL0[1]),
        .O(\lowCL0_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1720" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__2 
       (.I0(uppCL0[27]),
        .I1(uppCL0[26]),
        .I2(uppCL0[25]),
        .O(\uppCL0_reg[27]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1764" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [2]),
        .I1(\uppCL0_reg[45]_0 [1]),
        .I2(\uppCL0_reg[45]_0 [0]),
        .O(\uppCL0_reg[9]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1768" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [5]),
        .I1(\uppCL0_reg[45]_0 [4]),
        .I2(\uppCL0_reg[45]_0 [3]),
        .O(\uppCL0_reg[45]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1724" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__5 
       (.I0(lowCL0[45]),
        .I1(lowCL0[44]),
        .I2(lowCL0[43]),
        .O(\lowCL0_reg[45]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1728" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__6 
       (.I0(uppCL0[3]),
        .I1(uppCL0[2]),
        .I2(uppCL0[1]),
        .O(\uppCL0_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1732" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__7 
       (.I0(uppCL0[33]),
        .I1(uppCL0[32]),
        .I2(uppCL0[31]),
        .O(\uppCL0_reg[33]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1736" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__8 
       (.I0(lowCL0[33]),
        .I1(lowCL0[32]),
        .I2(lowCL0[31]),
        .O(\lowCL0_reg[33]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1740" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[0][11]_i_1__9 
       (.I0(lowCL0[27]),
        .I1(lowCL0[26]),
        .I2(lowCL0[25]),
        .O(\lowCL0_reg[27]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2028" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2 
       (.I0(uppCL0[38]),
        .I1(uppCL0[37]),
        .O(\uppCL0_reg[38]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2032" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__0 
       (.I0(uppCL0[20]),
        .I1(uppCL0[19]),
        .O(\uppCL0_reg[20]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2036" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__1 
       (.I0(uppCL0[14]),
        .I1(uppCL0[13]),
        .O(\uppCL0_reg[14]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2072" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__10 
       (.I0(lowCL0[38]),
        .I1(lowCL0[37]),
        .O(\lowCL0_reg[38]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2076" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__11 
       (.I0(lowCL0[20]),
        .I1(lowCL0[19]),
        .O(\lowCL0_reg[20]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2080" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__12 
       (.I0(lowCL0[14]),
        .I1(lowCL0[13]),
        .O(\lowCL0_reg[14]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2084" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__13 
       (.I0(lowCL0[8]),
        .I1(lowCL0[7]),
        .O(\lowCL0_reg[8]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2088" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__14 
       (.I0(lowCL0[2]),
        .I1(lowCL0[1]),
        .O(\lowCL0_reg[2]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2040" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__2 
       (.I0(uppCL0[26]),
        .I1(uppCL0[25]),
        .O(\uppCL0_reg[26]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2044" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__3 
       (.I0(\uppCL0_reg[45]_0 [1]),
        .I1(\uppCL0_reg[45]_0 [0]),
        .O(\uppCL0_reg[8]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2048" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__4 
       (.I0(\uppCL0_reg[45]_0 [4]),
        .I1(\uppCL0_reg[45]_0 [3]),
        .O(\uppCL0_reg[44]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2052" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__5 
       (.I0(lowCL0[44]),
        .I1(lowCL0[43]),
        .O(\lowCL0_reg[44]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2056" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__6 
       (.I0(uppCL0[2]),
        .I1(uppCL0[1]),
        .O(\uppCL0_reg[2]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2060" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__7 
       (.I0(uppCL0[32]),
        .I1(uppCL0[31]),
        .O(\uppCL0_reg[32]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2064" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__8 
       (.I0(lowCL0[32]),
        .I1(lowCL0[31]),
        .O(\lowCL0_reg[32]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2068" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[0][11]_i_2__9 
       (.I0(lowCL0[26]),
        .I1(lowCL0[25]),
        .O(\lowCL0_reg[26]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1596" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1 
       (.I0(uppCL0[37]),
        .I1(uppCL0[38]),
        .I2(uppCL0[39]),
        .I3(uppCL0[36]),
        .O(\uppCL0_reg[38]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1604" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__0 
       (.I0(uppCL0[19]),
        .I1(uppCL0[20]),
        .I2(uppCL0[21]),
        .I3(uppCL0[18]),
        .O(\uppCL0_reg[20]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1612" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__1 
       (.I0(uppCL0[13]),
        .I1(uppCL0[14]),
        .I2(uppCL0[15]),
        .I3(uppCL0[12]),
        .O(\uppCL0_reg[14]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1684" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__10 
       (.I0(lowCL0[13]),
        .I1(lowCL0[14]),
        .I2(lowCL0[15]),
        .I3(lowCL0[12]),
        .O(\lowCL0_reg[14]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1692" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__11 
       (.I0(lowCL0[7]),
        .I1(lowCL0[8]),
        .I2(lowCL0[9]),
        .I3(lowCL0[6]),
        .O(\lowCL0_reg[8]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1700" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__12 
       (.I0(lowCL0[1]),
        .I1(lowCL0[2]),
        .I2(lowCL0[3]),
        .I3(lowCL0[0]),
        .O(\lowCL0_reg[2]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1620" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__2 
       (.I0(uppCL0[25]),
        .I1(uppCL0[26]),
        .I2(uppCL0[27]),
        .I3(uppCL0[24]),
        .O(\uppCL0_reg[26]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1628" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__3 
       (.I0(lowCL0[43]),
        .I1(lowCL0[44]),
        .I2(lowCL0[45]),
        .I3(lowCL0[42]),
        .O(\lowCL0_reg[44]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1636" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__4 
       (.I0(uppCL0[1]),
        .I1(uppCL0[2]),
        .I2(uppCL0[3]),
        .I3(uppCL0[0]),
        .O(\uppCL0_reg[2]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1644" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__5 
       (.I0(uppCL0[31]),
        .I1(uppCL0[32]),
        .I2(uppCL0[33]),
        .I3(uppCL0[30]),
        .O(\uppCL0_reg[32]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1652" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__6 
       (.I0(lowCL0[31]),
        .I1(lowCL0[32]),
        .I2(lowCL0[33]),
        .I3(lowCL0[30]),
        .O(\lowCL0_reg[32]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1660" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__7 
       (.I0(lowCL0[25]),
        .I1(lowCL0[26]),
        .I2(lowCL0[27]),
        .I3(lowCL0[24]),
        .O(\lowCL0_reg[26]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1668" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__8 
       (.I0(lowCL0[37]),
        .I1(lowCL0[38]),
        .I2(lowCL0[39]),
        .I3(lowCL0[36]),
        .O(\lowCL0_reg[38]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1676" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[0][2]_i_1__9 
       (.I0(lowCL0[19]),
        .I1(lowCL0[20]),
        .I2(lowCL0[21]),
        .I3(lowCL0[18]),
        .O(\lowCL0_reg[20]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1844" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1 
       (.I0(uppCL0[37]),
        .I1(uppCL0[38]),
        .I2(uppCL0[39]),
        .O(\uppCL0_reg[38]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1852" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__0 
       (.I0(uppCL0[19]),
        .I1(uppCL0[20]),
        .I2(uppCL0[21]),
        .O(\uppCL0_reg[20]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1860" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__1 
       (.I0(uppCL0[13]),
        .I1(uppCL0[14]),
        .I2(uppCL0[15]),
        .O(\uppCL0_reg[14]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1932" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__10 
       (.I0(lowCL0[13]),
        .I1(lowCL0[14]),
        .I2(lowCL0[15]),
        .O(\lowCL0_reg[14]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1940" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__11 
       (.I0(lowCL0[7]),
        .I1(lowCL0[8]),
        .I2(lowCL0[9]),
        .O(\lowCL0_reg[8]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1948" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__12 
       (.I0(lowCL0[1]),
        .I1(lowCL0[2]),
        .I2(lowCL0[3]),
        .O(\lowCL0_reg[2]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1868" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__2 
       (.I0(uppCL0[25]),
        .I1(uppCL0[26]),
        .I2(uppCL0[27]),
        .O(\uppCL0_reg[26]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1876" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__3 
       (.I0(lowCL0[43]),
        .I1(lowCL0[44]),
        .I2(lowCL0[45]),
        .O(\lowCL0_reg[44]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1884" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__4 
       (.I0(uppCL0[1]),
        .I1(uppCL0[2]),
        .I2(uppCL0[3]),
        .O(\uppCL0_reg[2]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1892" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__5 
       (.I0(uppCL0[31]),
        .I1(uppCL0[32]),
        .I2(uppCL0[33]),
        .O(\uppCL0_reg[32]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1900" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__6 
       (.I0(lowCL0[31]),
        .I1(lowCL0[32]),
        .I2(lowCL0[33]),
        .O(\lowCL0_reg[32]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1908" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__7 
       (.I0(lowCL0[25]),
        .I1(lowCL0[26]),
        .I2(lowCL0[27]),
        .O(\lowCL0_reg[26]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1916" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__8 
       (.I0(lowCL0[37]),
        .I1(lowCL0[38]),
        .I2(lowCL0[39]),
        .O(\lowCL0_reg[38]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1924" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[0][3]_i_1__9 
       (.I0(lowCL0[19]),
        .I1(lowCL0[20]),
        .I2(lowCL0[21]),
        .O(\lowCL0_reg[20]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2100" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1 
       (.I0(uppCL0[38]),
        .I1(uppCL0[39]),
        .O(\uppCL0_reg[38]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2108" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__0 
       (.I0(uppCL0[20]),
        .I1(uppCL0[21]),
        .O(\uppCL0_reg[20]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2116" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__1 
       (.I0(uppCL0[14]),
        .I1(uppCL0[15]),
        .O(\uppCL0_reg[14]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2188" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__10 
       (.I0(lowCL0[14]),
        .I1(lowCL0[15]),
        .O(\lowCL0_reg[14]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2196" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__11 
       (.I0(lowCL0[8]),
        .I1(lowCL0[9]),
        .O(\lowCL0_reg[8]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2204" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__12 
       (.I0(lowCL0[2]),
        .I1(lowCL0[3]),
        .O(\lowCL0_reg[2]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2124" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__2 
       (.I0(uppCL0[26]),
        .I1(uppCL0[27]),
        .O(\uppCL0_reg[26]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2132" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__3 
       (.I0(lowCL0[44]),
        .I1(lowCL0[45]),
        .O(\lowCL0_reg[44]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2140" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__4 
       (.I0(uppCL0[2]),
        .I1(uppCL0[3]),
        .O(\uppCL0_reg[2]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2148" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__5 
       (.I0(uppCL0[32]),
        .I1(uppCL0[33]),
        .O(\uppCL0_reg[32]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2156" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__6 
       (.I0(lowCL0[32]),
        .I1(lowCL0[33]),
        .O(\lowCL0_reg[32]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2164" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__7 
       (.I0(lowCL0[26]),
        .I1(lowCL0[27]),
        .O(\lowCL0_reg[26]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2172" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__8 
       (.I0(lowCL0[38]),
        .I1(lowCL0[39]),
        .O(\lowCL0_reg[38]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2180" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[0][9]_i_1__9 
       (.I0(lowCL0[20]),
        .I1(lowCL0[21]),
        .O(\lowCL0_reg[20]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1597" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1 
       (.I0(uppCL0[37]),
        .I1(uppCL0[38]),
        .I2(uppCL0[39]),
        .I3(uppCL0[36]),
        .O(rs2mask0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1605" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__0 
       (.I0(uppCL0[19]),
        .I1(uppCL0[20]),
        .I2(uppCL0[21]),
        .I3(uppCL0[18]),
        .O(rs2mask0_2[2]));
  (* SOFT_HLUTNM = "soft_lutpair1613" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__1 
       (.I0(uppCL0[13]),
        .I1(uppCL0[14]),
        .I2(uppCL0[15]),
        .I3(uppCL0[12]),
        .O(rs2mask0_4[2]));
  (* SOFT_HLUTNM = "soft_lutpair1669" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__10 
       (.I0(lowCL0[37]),
        .I1(lowCL0[38]),
        .I2(lowCL0[39]),
        .I3(lowCL0[36]),
        .O(rs2mask0_18[2]));
  (* SOFT_HLUTNM = "soft_lutpair1677" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__11 
       (.I0(lowCL0[19]),
        .I1(lowCL0[20]),
        .I2(lowCL0[21]),
        .I3(lowCL0[18]),
        .O(rs2mask0_20[2]));
  (* SOFT_HLUTNM = "soft_lutpair1685" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__12 
       (.I0(lowCL0[13]),
        .I1(lowCL0[14]),
        .I2(lowCL0[15]),
        .I3(lowCL0[12]),
        .O(rs2mask0_22[2]));
  (* SOFT_HLUTNM = "soft_lutpair1693" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__13 
       (.I0(lowCL0[7]),
        .I1(lowCL0[8]),
        .I2(lowCL0[9]),
        .I3(lowCL0[6]),
        .O(rs2mask0_24[2]));
  (* SOFT_HLUTNM = "soft_lutpair1701" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__14 
       (.I0(lowCL0[1]),
        .I1(lowCL0[2]),
        .I2(lowCL0[3]),
        .I3(lowCL0[0]),
        .O(rs2mask0_26[2]));
  (* SOFT_HLUTNM = "soft_lutpair1621" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__2 
       (.I0(uppCL0[25]),
        .I1(uppCL0[26]),
        .I2(uppCL0[27]),
        .I3(uppCL0[24]),
        .O(rs2mask0_6[2]));
  (* SOFT_HLUTNM = "soft_lutpair1580" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [0]),
        .I1(\uppCL0_reg[45]_0 [1]),
        .I2(\uppCL0_reg[45]_0 [2]),
        .I3(uppCL0[6]),
        .O(rs2mask0__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1588" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [3]),
        .I1(\uppCL0_reg[45]_0 [4]),
        .I2(\uppCL0_reg[45]_0 [5]),
        .I3(uppCL0[42]),
        .O(rs2mask0__0_0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1629" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__5 
       (.I0(lowCL0[43]),
        .I1(lowCL0[44]),
        .I2(lowCL0[45]),
        .I3(lowCL0[42]),
        .O(rs2mask0_8[2]));
  (* SOFT_HLUTNM = "soft_lutpair1637" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__6 
       (.I0(uppCL0[1]),
        .I1(uppCL0[2]),
        .I2(uppCL0[3]),
        .I3(uppCL0[0]),
        .O(rs2mask0_10[2]));
  (* SOFT_HLUTNM = "soft_lutpair1645" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__7 
       (.I0(uppCL0[31]),
        .I1(uppCL0[32]),
        .I2(uppCL0[33]),
        .I3(uppCL0[30]),
        .O(rs2mask0_12[2]));
  (* SOFT_HLUTNM = "soft_lutpair1653" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__8 
       (.I0(lowCL0[31]),
        .I1(lowCL0[32]),
        .I2(lowCL0[33]),
        .I3(lowCL0[30]),
        .O(rs2mask0_14[2]));
  (* SOFT_HLUTNM = "soft_lutpair1661" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[1][10]_i_1__9 
       (.I0(lowCL0[25]),
        .I1(lowCL0[26]),
        .I2(lowCL0[27]),
        .I3(lowCL0[24]),
        .O(rs2mask0_16[2]));
  (* SOFT_HLUTNM = "soft_lutpair1844" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1 
       (.I0(uppCL0[37]),
        .I1(uppCL0[38]),
        .I2(uppCL0[39]),
        .O(rs2mask0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1852" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__0 
       (.I0(uppCL0[19]),
        .I1(uppCL0[20]),
        .I2(uppCL0[21]),
        .O(rs2mask0_2[3]));
  (* SOFT_HLUTNM = "soft_lutpair1860" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__1 
       (.I0(uppCL0[13]),
        .I1(uppCL0[14]),
        .I2(uppCL0[15]),
        .O(rs2mask0_4[3]));
  (* SOFT_HLUTNM = "soft_lutpair1932" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__10 
       (.I0(lowCL0[13]),
        .I1(lowCL0[14]),
        .I2(lowCL0[15]),
        .O(rs2mask0_22[3]));
  (* SOFT_HLUTNM = "soft_lutpair1940" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__11 
       (.I0(lowCL0[7]),
        .I1(lowCL0[8]),
        .I2(lowCL0[9]),
        .O(rs2mask0_24[3]));
  (* SOFT_HLUTNM = "soft_lutpair1948" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__12 
       (.I0(lowCL0[1]),
        .I1(lowCL0[2]),
        .I2(lowCL0[3]),
        .O(rs2mask0_26[3]));
  (* SOFT_HLUTNM = "soft_lutpair1868" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__2 
       (.I0(uppCL0[25]),
        .I1(uppCL0[26]),
        .I2(uppCL0[27]),
        .O(rs2mask0_6[3]));
  (* SOFT_HLUTNM = "soft_lutpair1876" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__3 
       (.I0(lowCL0[43]),
        .I1(lowCL0[44]),
        .I2(lowCL0[45]),
        .O(rs2mask0_8[3]));
  (* SOFT_HLUTNM = "soft_lutpair1884" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__4 
       (.I0(uppCL0[1]),
        .I1(uppCL0[2]),
        .I2(uppCL0[3]),
        .O(rs2mask0_10[3]));
  (* SOFT_HLUTNM = "soft_lutpair1892" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__5 
       (.I0(uppCL0[31]),
        .I1(uppCL0[32]),
        .I2(uppCL0[33]),
        .O(rs2mask0_12[3]));
  (* SOFT_HLUTNM = "soft_lutpair1900" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__6 
       (.I0(lowCL0[31]),
        .I1(lowCL0[32]),
        .I2(lowCL0[33]),
        .O(rs2mask0_14[3]));
  (* SOFT_HLUTNM = "soft_lutpair1908" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__7 
       (.I0(lowCL0[25]),
        .I1(lowCL0[26]),
        .I2(lowCL0[27]),
        .O(rs2mask0_16[3]));
  (* SOFT_HLUTNM = "soft_lutpair1916" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__8 
       (.I0(lowCL0[37]),
        .I1(lowCL0[38]),
        .I2(lowCL0[39]),
        .O(rs2mask0_18[3]));
  (* SOFT_HLUTNM = "soft_lutpair1924" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[1][11]_i_1__9 
       (.I0(lowCL0[19]),
        .I1(lowCL0[20]),
        .I2(lowCL0[21]),
        .O(rs2mask0_20[3]));
  (* SOFT_HLUTNM = "soft_lutpair1596" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1 
       (.I0(uppCL0[37]),
        .I1(uppCL0[38]),
        .I2(uppCL0[39]),
        .I3(uppCL0[36]),
        .O(rs2mask0[4]));
  (* SOFT_HLUTNM = "soft_lutpair1604" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__0 
       (.I0(uppCL0[19]),
        .I1(uppCL0[20]),
        .I2(uppCL0[21]),
        .I3(uppCL0[18]),
        .O(rs2mask0_2[4]));
  (* SOFT_HLUTNM = "soft_lutpair1612" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__1 
       (.I0(uppCL0[13]),
        .I1(uppCL0[14]),
        .I2(uppCL0[15]),
        .I3(uppCL0[12]),
        .O(rs2mask0_4[4]));
  (* SOFT_HLUTNM = "soft_lutpair1668" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__10 
       (.I0(lowCL0[37]),
        .I1(lowCL0[38]),
        .I2(lowCL0[39]),
        .I3(lowCL0[36]),
        .O(rs2mask0_18[4]));
  (* SOFT_HLUTNM = "soft_lutpair1676" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__11 
       (.I0(lowCL0[19]),
        .I1(lowCL0[20]),
        .I2(lowCL0[21]),
        .I3(lowCL0[18]),
        .O(rs2mask0_20[4]));
  (* SOFT_HLUTNM = "soft_lutpair1684" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__12 
       (.I0(lowCL0[13]),
        .I1(lowCL0[14]),
        .I2(lowCL0[15]),
        .I3(lowCL0[12]),
        .O(rs2mask0_22[4]));
  (* SOFT_HLUTNM = "soft_lutpair1692" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__13 
       (.I0(lowCL0[7]),
        .I1(lowCL0[8]),
        .I2(lowCL0[9]),
        .I3(lowCL0[6]),
        .O(rs2mask0_24[4]));
  (* SOFT_HLUTNM = "soft_lutpair1700" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__14 
       (.I0(lowCL0[1]),
        .I1(lowCL0[2]),
        .I2(lowCL0[3]),
        .I3(lowCL0[0]),
        .O(rs2mask0_26[4]));
  (* SOFT_HLUTNM = "soft_lutpair1620" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__2 
       (.I0(uppCL0[25]),
        .I1(uppCL0[26]),
        .I2(uppCL0[27]),
        .I3(uppCL0[24]),
        .O(rs2mask0_6[4]));
  (* SOFT_HLUTNM = "soft_lutpair1580" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [0]),
        .I1(\uppCL0_reg[45]_0 [1]),
        .I2(\uppCL0_reg[45]_0 [2]),
        .I3(uppCL0[6]),
        .O(rs2mask0__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1588" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [3]),
        .I1(\uppCL0_reg[45]_0 [4]),
        .I2(\uppCL0_reg[45]_0 [5]),
        .I3(uppCL0[42]),
        .O(rs2mask0__0_0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1628" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__5 
       (.I0(lowCL0[43]),
        .I1(lowCL0[44]),
        .I2(lowCL0[45]),
        .I3(lowCL0[42]),
        .O(rs2mask0_8[4]));
  (* SOFT_HLUTNM = "soft_lutpair1636" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__6 
       (.I0(uppCL0[1]),
        .I1(uppCL0[2]),
        .I2(uppCL0[3]),
        .I3(uppCL0[0]),
        .O(rs2mask0_10[4]));
  (* SOFT_HLUTNM = "soft_lutpair1644" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__7 
       (.I0(uppCL0[31]),
        .I1(uppCL0[32]),
        .I2(uppCL0[33]),
        .I3(uppCL0[30]),
        .O(rs2mask0_12[4]));
  (* SOFT_HLUTNM = "soft_lutpair1652" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__8 
       (.I0(lowCL0[31]),
        .I1(lowCL0[32]),
        .I2(lowCL0[33]),
        .I3(lowCL0[30]),
        .O(rs2mask0_14[4]));
  (* SOFT_HLUTNM = "soft_lutpair1660" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[1][12]_i_1__9 
       (.I0(lowCL0[25]),
        .I1(lowCL0[26]),
        .I2(lowCL0[27]),
        .I3(lowCL0[24]),
        .O(rs2mask0_16[4]));
  (* SOFT_HLUTNM = "soft_lutpair1964" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1 
       (.I0(uppCL0[38]),
        .I1(uppCL0[37]),
        .O(\uppCL0_reg[38]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1968" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__0 
       (.I0(uppCL0[20]),
        .I1(uppCL0[19]),
        .O(\uppCL0_reg[20]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1972" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__1 
       (.I0(uppCL0[14]),
        .I1(uppCL0[13]),
        .O(\uppCL0_reg[14]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2008" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__10 
       (.I0(lowCL0[38]),
        .I1(lowCL0[37]),
        .O(\lowCL0_reg[38]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2012" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__11 
       (.I0(lowCL0[20]),
        .I1(lowCL0[19]),
        .O(\lowCL0_reg[20]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2016" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__12 
       (.I0(lowCL0[14]),
        .I1(lowCL0[13]),
        .O(\lowCL0_reg[14]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2020" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__13 
       (.I0(lowCL0[8]),
        .I1(lowCL0[7]),
        .O(\lowCL0_reg[8]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2024" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__14 
       (.I0(lowCL0[2]),
        .I1(lowCL0[1]),
        .O(\lowCL0_reg[2]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1976" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__2 
       (.I0(uppCL0[26]),
        .I1(uppCL0[25]),
        .O(\uppCL0_reg[26]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1956" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [1]),
        .I1(\uppCL0_reg[45]_0 [0]),
        .O(\uppCL0_reg[8]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1960" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [4]),
        .I1(\uppCL0_reg[45]_0 [3]),
        .O(\uppCL0_reg[44]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1988" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__5 
       (.I0(lowCL0[44]),
        .I1(lowCL0[43]),
        .O(\lowCL0_reg[44]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1992" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__6 
       (.I0(uppCL0[2]),
        .I1(uppCL0[1]),
        .O(\uppCL0_reg[2]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1996" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__7 
       (.I0(uppCL0[32]),
        .I1(uppCL0[31]),
        .O(\uppCL0_reg[32]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2000" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__8 
       (.I0(lowCL0[32]),
        .I1(lowCL0[31]),
        .O(\lowCL0_reg[32]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2004" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[1][13]_i_1__9 
       (.I0(lowCL0[26]),
        .I1(lowCL0[25]),
        .O(\lowCL0_reg[26]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1780" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1 
       (.I0(uppCL0[37]),
        .I1(uppCL0[38]),
        .I2(uppCL0[36]),
        .O(\uppCL0_reg[37]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1784" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__0 
       (.I0(uppCL0[19]),
        .I1(uppCL0[20]),
        .I2(uppCL0[18]),
        .O(\uppCL0_reg[19]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1788" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__1 
       (.I0(uppCL0[13]),
        .I1(uppCL0[14]),
        .I2(uppCL0[12]),
        .O(\uppCL0_reg[13]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1816" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__10 
       (.I0(lowCL0[37]),
        .I1(lowCL0[38]),
        .I2(lowCL0[36]),
        .O(\lowCL0_reg[37]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1820" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__11 
       (.I0(lowCL0[19]),
        .I1(lowCL0[20]),
        .I2(lowCL0[18]),
        .O(\lowCL0_reg[19]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1824" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__12 
       (.I0(lowCL0[13]),
        .I1(lowCL0[14]),
        .I2(lowCL0[12]),
        .O(\lowCL0_reg[13]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1828" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__13 
       (.I0(lowCL0[7]),
        .I1(lowCL0[8]),
        .I2(lowCL0[6]),
        .O(\lowCL0_reg[7]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1832" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__14 
       (.I0(lowCL0[1]),
        .I1(lowCL0[2]),
        .I2(lowCL0[0]),
        .O(\lowCL0_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1792" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__2 
       (.I0(uppCL0[25]),
        .I1(uppCL0[26]),
        .I2(uppCL0[24]),
        .O(\uppCL0_reg[25]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1772" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [0]),
        .I1(\uppCL0_reg[45]_0 [1]),
        .I2(uppCL0[6]),
        .O(\uppCL0_reg[7]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1776" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [3]),
        .I1(\uppCL0_reg[45]_0 [4]),
        .I2(uppCL0[42]),
        .O(\uppCL0_reg[43]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1796" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__5 
       (.I0(lowCL0[43]),
        .I1(lowCL0[44]),
        .I2(lowCL0[42]),
        .O(\lowCL0_reg[43]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1800" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__6 
       (.I0(uppCL0[1]),
        .I1(uppCL0[2]),
        .I2(uppCL0[0]),
        .O(\uppCL0_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1804" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__7 
       (.I0(uppCL0[31]),
        .I1(uppCL0[32]),
        .I2(uppCL0[30]),
        .O(\uppCL0_reg[31]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1808" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__8 
       (.I0(lowCL0[31]),
        .I1(lowCL0[32]),
        .I2(lowCL0[30]),
        .O(\lowCL0_reg[31]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1812" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[1][14]_i_1__9 
       (.I0(lowCL0[25]),
        .I1(lowCL0[26]),
        .I2(lowCL0[24]),
        .O(\lowCL0_reg[25]_1 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1 
       (.I0(uppCL0[38]),
        .O(\uppCL0_reg[38]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__0 
       (.I0(uppCL0[26]),
        .O(\uppCL0_reg[26]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__1 
       (.I0(uppCL0[20]),
        .O(\uppCL0_reg[20]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__10 
       (.I0(lowCL0[26]),
        .O(\lowCL0_reg[26]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__11 
       (.I0(lowCL0[20]),
        .O(\lowCL0_reg[20]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__12 
       (.I0(lowCL0[14]),
        .O(\lowCL0_reg[14]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__13 
       (.I0(lowCL0[8]),
        .O(\lowCL0_reg[8]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__14 
       (.I0(lowCL0[2]),
        .O(\lowCL0_reg[2]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__2 
       (.I0(uppCL0[14]),
        .O(\uppCL0_reg[14]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair2216" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [4]),
        .O(\uppCL0_reg[44]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair2212" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [1]),
        .O(\uppCL0_reg[8]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__5 
       (.I0(lowCL0[44]),
        .O(\lowCL0_reg[44]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__6 
       (.I0(uppCL0[32]),
        .O(\uppCL0_reg[32]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__7 
       (.I0(uppCL0[2]),
        .O(\uppCL0_reg[2]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__8 
       (.I0(lowCL0[38]),
        .O(\lowCL0_reg[38]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[1][15]_i_1__9 
       (.I0(lowCL0[32]),
        .O(\lowCL0_reg[32]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1845" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1 
       (.I0(uppCL0[37]),
        .I1(uppCL0[38]),
        .I2(uppCL0[36]),
        .O(\uppCL0_reg[37]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1853" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__0 
       (.I0(uppCL0[19]),
        .I1(uppCL0[20]),
        .I2(uppCL0[18]),
        .O(\uppCL0_reg[19]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1861" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__1 
       (.I0(uppCL0[13]),
        .I1(uppCL0[14]),
        .I2(uppCL0[12]),
        .O(\uppCL0_reg[13]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1917" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__10 
       (.I0(lowCL0[37]),
        .I1(lowCL0[38]),
        .I2(lowCL0[36]),
        .O(\lowCL0_reg[37]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1925" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__11 
       (.I0(lowCL0[19]),
        .I1(lowCL0[20]),
        .I2(lowCL0[18]),
        .O(\lowCL0_reg[19]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1933" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__12 
       (.I0(lowCL0[13]),
        .I1(lowCL0[14]),
        .I2(lowCL0[12]),
        .O(\lowCL0_reg[13]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1941" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__13 
       (.I0(lowCL0[7]),
        .I1(lowCL0[8]),
        .I2(lowCL0[6]),
        .O(\lowCL0_reg[7]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1949" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__14 
       (.I0(lowCL0[1]),
        .I1(lowCL0[2]),
        .I2(lowCL0[0]),
        .O(\lowCL0_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1869" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__2 
       (.I0(uppCL0[25]),
        .I1(uppCL0[26]),
        .I2(uppCL0[24]),
        .O(\uppCL0_reg[25]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1836" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [0]),
        .I1(\uppCL0_reg[45]_0 [1]),
        .I2(uppCL0[6]),
        .O(\uppCL0_reg[7]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1840" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [3]),
        .I1(\uppCL0_reg[45]_0 [4]),
        .I2(uppCL0[42]),
        .O(\uppCL0_reg[43]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1877" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__5 
       (.I0(lowCL0[43]),
        .I1(lowCL0[44]),
        .I2(lowCL0[42]),
        .O(\lowCL0_reg[43]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1885" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__6 
       (.I0(uppCL0[1]),
        .I1(uppCL0[2]),
        .I2(uppCL0[0]),
        .O(\uppCL0_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1893" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__7 
       (.I0(uppCL0[31]),
        .I1(uppCL0[32]),
        .I2(uppCL0[30]),
        .O(\uppCL0_reg[31]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1901" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__8 
       (.I0(lowCL0[31]),
        .I1(lowCL0[32]),
        .I2(lowCL0[30]),
        .O(\lowCL0_reg[31]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1909" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[1][16]_i_1__9 
       (.I0(lowCL0[25]),
        .I1(lowCL0[26]),
        .I2(lowCL0[24]),
        .O(\lowCL0_reg[25]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2101" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1 
       (.I0(uppCL0[38]),
        .I1(uppCL0[37]),
        .O(\uppCL0_reg[38]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2109" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__0 
       (.I0(uppCL0[20]),
        .I1(uppCL0[19]),
        .O(\uppCL0_reg[20]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2117" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__1 
       (.I0(uppCL0[14]),
        .I1(uppCL0[13]),
        .O(\uppCL0_reg[14]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2173" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__10 
       (.I0(lowCL0[38]),
        .I1(lowCL0[37]),
        .O(\lowCL0_reg[38]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2181" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__11 
       (.I0(lowCL0[20]),
        .I1(lowCL0[19]),
        .O(\lowCL0_reg[20]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2189" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__12 
       (.I0(lowCL0[14]),
        .I1(lowCL0[13]),
        .O(\lowCL0_reg[14]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2197" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__13 
       (.I0(lowCL0[8]),
        .I1(lowCL0[7]),
        .O(\lowCL0_reg[8]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2205" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__14 
       (.I0(lowCL0[2]),
        .I1(lowCL0[1]),
        .O(\lowCL0_reg[2]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2125" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__2 
       (.I0(uppCL0[26]),
        .I1(uppCL0[25]),
        .O(\uppCL0_reg[26]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2044" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [1]),
        .I1(\uppCL0_reg[45]_0 [0]),
        .O(\uppCL0_reg[8]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2048" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [4]),
        .I1(\uppCL0_reg[45]_0 [3]),
        .O(\uppCL0_reg[44]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2133" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__5 
       (.I0(lowCL0[44]),
        .I1(lowCL0[43]),
        .O(\lowCL0_reg[44]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2141" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__6 
       (.I0(uppCL0[2]),
        .I1(uppCL0[1]),
        .O(\uppCL0_reg[2]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2149" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__7 
       (.I0(uppCL0[32]),
        .I1(uppCL0[31]),
        .O(\uppCL0_reg[32]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2157" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__8 
       (.I0(lowCL0[32]),
        .I1(lowCL0[31]),
        .O(\lowCL0_reg[32]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2165" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[1][17]_i_1__9 
       (.I0(lowCL0[26]),
        .I1(lowCL0[25]),
        .O(\lowCL0_reg[26]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1780" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1 
       (.I0(uppCL0[38]),
        .I1(uppCL0[36]),
        .I2(uppCL0[37]),
        .O(\uppCL0_reg[38]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1784" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__0 
       (.I0(uppCL0[20]),
        .I1(uppCL0[18]),
        .I2(uppCL0[19]),
        .O(\uppCL0_reg[20]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1788" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__1 
       (.I0(uppCL0[14]),
        .I1(uppCL0[12]),
        .I2(uppCL0[13]),
        .O(\uppCL0_reg[14]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1816" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__10 
       (.I0(lowCL0[38]),
        .I1(lowCL0[36]),
        .I2(lowCL0[37]),
        .O(\lowCL0_reg[38]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1820" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__11 
       (.I0(lowCL0[20]),
        .I1(lowCL0[18]),
        .I2(lowCL0[19]),
        .O(\lowCL0_reg[20]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1824" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__12 
       (.I0(lowCL0[14]),
        .I1(lowCL0[12]),
        .I2(lowCL0[13]),
        .O(\lowCL0_reg[14]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1828" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__13 
       (.I0(lowCL0[8]),
        .I1(lowCL0[6]),
        .I2(lowCL0[7]),
        .O(\lowCL0_reg[8]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1832" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__14 
       (.I0(lowCL0[2]),
        .I1(lowCL0[0]),
        .I2(lowCL0[1]),
        .O(\lowCL0_reg[2]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1792" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__2 
       (.I0(uppCL0[26]),
        .I1(uppCL0[24]),
        .I2(uppCL0[25]),
        .O(\uppCL0_reg[26]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1772" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [1]),
        .I1(uppCL0[6]),
        .I2(\uppCL0_reg[45]_0 [0]),
        .O(\uppCL0_reg[8]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1776" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [4]),
        .I1(uppCL0[42]),
        .I2(\uppCL0_reg[45]_0 [3]),
        .O(\uppCL0_reg[44]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1796" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__5 
       (.I0(lowCL0[44]),
        .I1(lowCL0[42]),
        .I2(lowCL0[43]),
        .O(\lowCL0_reg[44]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1800" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__6 
       (.I0(uppCL0[2]),
        .I1(uppCL0[0]),
        .I2(uppCL0[1]),
        .O(\uppCL0_reg[2]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1804" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__7 
       (.I0(uppCL0[32]),
        .I1(uppCL0[30]),
        .I2(uppCL0[31]),
        .O(\uppCL0_reg[32]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1808" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__8 
       (.I0(lowCL0[32]),
        .I1(lowCL0[30]),
        .I2(lowCL0[31]),
        .O(\lowCL0_reg[32]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1812" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[1][18]_i_1__9 
       (.I0(lowCL0[26]),
        .I1(lowCL0[24]),
        .I2(lowCL0[25]),
        .O(\lowCL0_reg[26]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2028" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1 
       (.I0(uppCL0[38]),
        .I1(uppCL0[37]),
        .O(\uppCL0_reg[38]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2032" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__0 
       (.I0(uppCL0[20]),
        .I1(uppCL0[19]),
        .O(\uppCL0_reg[20]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2036" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__1 
       (.I0(uppCL0[14]),
        .I1(uppCL0[13]),
        .O(\uppCL0_reg[14]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2072" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__10 
       (.I0(lowCL0[38]),
        .I1(lowCL0[37]),
        .O(\lowCL0_reg[38]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2076" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__11 
       (.I0(lowCL0[20]),
        .I1(lowCL0[19]),
        .O(\lowCL0_reg[20]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2080" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__12 
       (.I0(lowCL0[14]),
        .I1(lowCL0[13]),
        .O(\lowCL0_reg[14]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2084" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__13 
       (.I0(lowCL0[8]),
        .I1(lowCL0[7]),
        .O(\lowCL0_reg[8]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2088" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__14 
       (.I0(lowCL0[2]),
        .I1(lowCL0[1]),
        .O(\lowCL0_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2040" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__2 
       (.I0(uppCL0[26]),
        .I1(uppCL0[25]),
        .O(\uppCL0_reg[26]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1980" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [1]),
        .I1(\uppCL0_reg[45]_0 [0]),
        .O(\uppCL0_reg[8]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1984" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [4]),
        .I1(\uppCL0_reg[45]_0 [3]),
        .O(\uppCL0_reg[44]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2052" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__5 
       (.I0(lowCL0[44]),
        .I1(lowCL0[43]),
        .O(\lowCL0_reg[44]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2056" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__6 
       (.I0(uppCL0[2]),
        .I1(uppCL0[1]),
        .O(\uppCL0_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2060" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__7 
       (.I0(uppCL0[32]),
        .I1(uppCL0[31]),
        .O(\uppCL0_reg[32]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2064" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__8 
       (.I0(lowCL0[32]),
        .I1(lowCL0[31]),
        .O(\lowCL0_reg[32]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2068" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[1][1]_i_1__9 
       (.I0(lowCL0[26]),
        .I1(lowCL0[25]),
        .O(\lowCL0_reg[26]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1597" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1 
       (.I0(uppCL0[37]),
        .I1(uppCL0[38]),
        .I2(uppCL0[39]),
        .I3(uppCL0[36]),
        .O(rs2mask0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1605" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__0 
       (.I0(uppCL0[19]),
        .I1(uppCL0[20]),
        .I2(uppCL0[21]),
        .I3(uppCL0[18]),
        .O(rs2mask0_2[0]));
  (* SOFT_HLUTNM = "soft_lutpair1613" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__1 
       (.I0(uppCL0[13]),
        .I1(uppCL0[14]),
        .I2(uppCL0[15]),
        .I3(uppCL0[12]),
        .O(rs2mask0_4[0]));
  (* SOFT_HLUTNM = "soft_lutpair1669" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__10 
       (.I0(lowCL0[37]),
        .I1(lowCL0[38]),
        .I2(lowCL0[39]),
        .I3(lowCL0[36]),
        .O(rs2mask0_18[0]));
  (* SOFT_HLUTNM = "soft_lutpair1677" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__11 
       (.I0(lowCL0[19]),
        .I1(lowCL0[20]),
        .I2(lowCL0[21]),
        .I3(lowCL0[18]),
        .O(rs2mask0_20[0]));
  (* SOFT_HLUTNM = "soft_lutpair1685" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__12 
       (.I0(lowCL0[13]),
        .I1(lowCL0[14]),
        .I2(lowCL0[15]),
        .I3(lowCL0[12]),
        .O(rs2mask0_22[0]));
  (* SOFT_HLUTNM = "soft_lutpair1693" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__13 
       (.I0(lowCL0[7]),
        .I1(lowCL0[8]),
        .I2(lowCL0[9]),
        .I3(lowCL0[6]),
        .O(rs2mask0_24[0]));
  (* SOFT_HLUTNM = "soft_lutpair1701" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__14 
       (.I0(lowCL0[1]),
        .I1(lowCL0[2]),
        .I2(lowCL0[3]),
        .I3(lowCL0[0]),
        .O(rs2mask0_26[0]));
  (* SOFT_HLUTNM = "soft_lutpair1621" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__2 
       (.I0(uppCL0[25]),
        .I1(uppCL0[26]),
        .I2(uppCL0[27]),
        .I3(uppCL0[24]),
        .O(rs2mask0_6[0]));
  (* SOFT_HLUTNM = "soft_lutpair1581" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [0]),
        .I1(\uppCL0_reg[45]_0 [1]),
        .I2(\uppCL0_reg[45]_0 [2]),
        .I3(uppCL0[6]),
        .O(rs2mask0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1589" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [3]),
        .I1(\uppCL0_reg[45]_0 [4]),
        .I2(\uppCL0_reg[45]_0 [5]),
        .I3(uppCL0[42]),
        .O(rs2mask0__0_0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1629" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__5 
       (.I0(lowCL0[43]),
        .I1(lowCL0[44]),
        .I2(lowCL0[45]),
        .I3(lowCL0[42]),
        .O(rs2mask0_8[0]));
  (* SOFT_HLUTNM = "soft_lutpair1637" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__6 
       (.I0(uppCL0[1]),
        .I1(uppCL0[2]),
        .I2(uppCL0[3]),
        .I3(uppCL0[0]),
        .O(rs2mask0_10[0]));
  (* SOFT_HLUTNM = "soft_lutpair1645" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__7 
       (.I0(uppCL0[31]),
        .I1(uppCL0[32]),
        .I2(uppCL0[33]),
        .I3(uppCL0[30]),
        .O(rs2mask0_12[0]));
  (* SOFT_HLUTNM = "soft_lutpair1653" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__8 
       (.I0(lowCL0[31]),
        .I1(lowCL0[32]),
        .I2(lowCL0[33]),
        .I3(lowCL0[30]),
        .O(rs2mask0_14[0]));
  (* SOFT_HLUTNM = "soft_lutpair1661" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[1][2]_i_1__9 
       (.I0(lowCL0[25]),
        .I1(lowCL0[26]),
        .I2(lowCL0[27]),
        .I3(lowCL0[24]),
        .O(rs2mask0_16[0]));
  (* SOFT_HLUTNM = "soft_lutpair2100" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1 
       (.I0(uppCL0[38]),
        .I1(uppCL0[39]),
        .O(rs2mask0[1]));
  (* SOFT_HLUTNM = "soft_lutpair2108" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__0 
       (.I0(uppCL0[20]),
        .I1(uppCL0[21]),
        .O(rs2mask0_2[1]));
  (* SOFT_HLUTNM = "soft_lutpair2116" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__1 
       (.I0(uppCL0[14]),
        .I1(uppCL0[15]),
        .O(rs2mask0_4[1]));
  (* SOFT_HLUTNM = "soft_lutpair2172" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__10 
       (.I0(lowCL0[38]),
        .I1(lowCL0[39]),
        .O(rs2mask0_18[1]));
  (* SOFT_HLUTNM = "soft_lutpair2180" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__11 
       (.I0(lowCL0[20]),
        .I1(lowCL0[21]),
        .O(rs2mask0_20[1]));
  (* SOFT_HLUTNM = "soft_lutpair2188" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__12 
       (.I0(lowCL0[14]),
        .I1(lowCL0[15]),
        .O(rs2mask0_22[1]));
  (* SOFT_HLUTNM = "soft_lutpair2196" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__13 
       (.I0(lowCL0[8]),
        .I1(lowCL0[9]),
        .O(rs2mask0_24[1]));
  (* SOFT_HLUTNM = "soft_lutpair2204" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__14 
       (.I0(lowCL0[2]),
        .I1(lowCL0[3]),
        .O(rs2mask0_26[1]));
  (* SOFT_HLUTNM = "soft_lutpair2124" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__2 
       (.I0(uppCL0[26]),
        .I1(uppCL0[27]),
        .O(rs2mask0_6[1]));
  (* SOFT_HLUTNM = "soft_lutpair2092" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [1]),
        .I1(\uppCL0_reg[45]_0 [2]),
        .O(rs2mask0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair2096" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [4]),
        .I1(\uppCL0_reg[45]_0 [5]),
        .O(rs2mask0__0_0[1]));
  (* SOFT_HLUTNM = "soft_lutpair2132" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__5 
       (.I0(lowCL0[44]),
        .I1(lowCL0[45]),
        .O(rs2mask0_8[1]));
  (* SOFT_HLUTNM = "soft_lutpair2140" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__6 
       (.I0(uppCL0[2]),
        .I1(uppCL0[3]),
        .O(rs2mask0_10[1]));
  (* SOFT_HLUTNM = "soft_lutpair2148" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__7 
       (.I0(uppCL0[32]),
        .I1(uppCL0[33]),
        .O(rs2mask0_12[1]));
  (* SOFT_HLUTNM = "soft_lutpair2156" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__8 
       (.I0(lowCL0[32]),
        .I1(lowCL0[33]),
        .O(rs2mask0_14[1]));
  (* SOFT_HLUTNM = "soft_lutpair2164" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[1][3]_i_1__9 
       (.I0(lowCL0[26]),
        .I1(lowCL0[27]),
        .O(rs2mask0_16[1]));
  (* SOFT_HLUTNM = "soft_lutpair1964" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1 
       (.I0(uppCL0[36]),
        .I1(uppCL0[38]),
        .I2(uppCL0[37]),
        .O(\uppCL0_reg[36]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1968" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__0 
       (.I0(uppCL0[18]),
        .I1(uppCL0[20]),
        .I2(uppCL0[19]),
        .O(\uppCL0_reg[18]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1972" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__1 
       (.I0(uppCL0[12]),
        .I1(uppCL0[14]),
        .I2(uppCL0[13]),
        .O(\uppCL0_reg[12]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2008" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__10 
       (.I0(lowCL0[36]),
        .I1(lowCL0[38]),
        .I2(lowCL0[37]),
        .O(\lowCL0_reg[36]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2012" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__11 
       (.I0(lowCL0[18]),
        .I1(lowCL0[20]),
        .I2(lowCL0[19]),
        .O(\lowCL0_reg[18]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2016" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__12 
       (.I0(lowCL0[12]),
        .I1(lowCL0[14]),
        .I2(lowCL0[13]),
        .O(\lowCL0_reg[12]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2020" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__13 
       (.I0(lowCL0[6]),
        .I1(lowCL0[8]),
        .I2(lowCL0[7]),
        .O(\lowCL0_reg[6]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2024" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__14 
       (.I0(lowCL0[0]),
        .I1(lowCL0[2]),
        .I2(lowCL0[1]),
        .O(\lowCL0_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1976" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__2 
       (.I0(uppCL0[24]),
        .I1(uppCL0[26]),
        .I2(uppCL0[25]),
        .O(\uppCL0_reg[24]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1980" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__3 
       (.I0(uppCL0[6]),
        .I1(\uppCL0_reg[45]_0 [1]),
        .I2(\uppCL0_reg[45]_0 [0]),
        .O(\uppCL0_reg[6]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1984" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__4 
       (.I0(uppCL0[42]),
        .I1(\uppCL0_reg[45]_0 [4]),
        .I2(\uppCL0_reg[45]_0 [3]),
        .O(\uppCL0_reg[42]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1988" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__5 
       (.I0(lowCL0[42]),
        .I1(lowCL0[44]),
        .I2(lowCL0[43]),
        .O(\lowCL0_reg[42]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1992" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__6 
       (.I0(uppCL0[0]),
        .I1(uppCL0[2]),
        .I2(uppCL0[1]),
        .O(\uppCL0_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1996" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__7 
       (.I0(uppCL0[30]),
        .I1(uppCL0[32]),
        .I2(uppCL0[31]),
        .O(\uppCL0_reg[30]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2000" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__8 
       (.I0(lowCL0[30]),
        .I1(lowCL0[32]),
        .I2(lowCL0[31]),
        .O(\lowCL0_reg[30]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2004" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[1][4]_i_1__9 
       (.I0(lowCL0[24]),
        .I1(lowCL0[26]),
        .I2(lowCL0[25]),
        .O(\lowCL0_reg[24]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1708" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1 
       (.I0(uppCL0[37]),
        .I1(uppCL0[38]),
        .I2(uppCL0[39]),
        .O(\blk1.(null)[0].diff [1]));
  (* SOFT_HLUTNM = "soft_lutpair1712" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__0 
       (.I0(uppCL0[19]),
        .I1(uppCL0[20]),
        .I2(uppCL0[21]),
        .O(\blk1.(null)[0].diff_1 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1716" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__1 
       (.I0(uppCL0[13]),
        .I1(uppCL0[14]),
        .I2(uppCL0[15]),
        .O(\blk1.(null)[0].diff_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1752" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__10 
       (.I0(lowCL0[13]),
        .I1(lowCL0[14]),
        .I2(lowCL0[15]),
        .O(\blk1.(null)[0].diff_21 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1756" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__11 
       (.I0(lowCL0[7]),
        .I1(lowCL0[8]),
        .I2(lowCL0[9]),
        .O(\blk1.(null)[0].diff_23 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1760" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__12 
       (.I0(lowCL0[1]),
        .I1(lowCL0[2]),
        .I2(lowCL0[3]),
        .O(\blk1.(null)[0].diff_25 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1720" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__2 
       (.I0(uppCL0[25]),
        .I1(uppCL0[26]),
        .I2(uppCL0[27]),
        .O(\blk1.(null)[0].diff_5 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1724" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__3 
       (.I0(lowCL0[43]),
        .I1(lowCL0[44]),
        .I2(lowCL0[45]),
        .O(\blk1.(null)[0].diff_7 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1728" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__4 
       (.I0(uppCL0[1]),
        .I1(uppCL0[2]),
        .I2(uppCL0[3]),
        .O(\blk1.(null)[0].diff_9 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1732" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__5 
       (.I0(uppCL0[31]),
        .I1(uppCL0[32]),
        .I2(uppCL0[33]),
        .O(\blk1.(null)[0].diff_11 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1736" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__6 
       (.I0(lowCL0[31]),
        .I1(lowCL0[32]),
        .I2(lowCL0[33]),
        .O(\blk1.(null)[0].diff_13 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1740" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__7 
       (.I0(lowCL0[25]),
        .I1(lowCL0[26]),
        .I2(lowCL0[27]),
        .O(\blk1.(null)[0].diff_15 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1744" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__8 
       (.I0(lowCL0[37]),
        .I1(lowCL0[38]),
        .I2(lowCL0[39]),
        .O(\blk1.(null)[0].diff_17 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1748" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[1][5]_i_1__9 
       (.I0(lowCL0[19]),
        .I1(lowCL0[20]),
        .I2(lowCL0[21]),
        .O(\blk1.(null)[0].diff_19 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1845" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1 
       (.I0(uppCL0[37]),
        .I1(uppCL0[38]),
        .I2(uppCL0[36]),
        .O(\uppCL0_reg[37]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1853" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__0 
       (.I0(uppCL0[19]),
        .I1(uppCL0[20]),
        .I2(uppCL0[18]),
        .O(\uppCL0_reg[19]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1861" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__1 
       (.I0(uppCL0[13]),
        .I1(uppCL0[14]),
        .I2(uppCL0[12]),
        .O(\uppCL0_reg[13]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1917" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__10 
       (.I0(lowCL0[37]),
        .I1(lowCL0[38]),
        .I2(lowCL0[36]),
        .O(\lowCL0_reg[37]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1925" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__11 
       (.I0(lowCL0[19]),
        .I1(lowCL0[20]),
        .I2(lowCL0[18]),
        .O(\lowCL0_reg[19]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1933" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__12 
       (.I0(lowCL0[13]),
        .I1(lowCL0[14]),
        .I2(lowCL0[12]),
        .O(\lowCL0_reg[13]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1941" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__13 
       (.I0(lowCL0[7]),
        .I1(lowCL0[8]),
        .I2(lowCL0[6]),
        .O(\lowCL0_reg[7]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1949" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__14 
       (.I0(lowCL0[1]),
        .I1(lowCL0[2]),
        .I2(lowCL0[0]),
        .O(\lowCL0_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1869" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__2 
       (.I0(uppCL0[25]),
        .I1(uppCL0[26]),
        .I2(uppCL0[24]),
        .O(\uppCL0_reg[25]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1836" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__3 
       (.I0(\uppCL0_reg[45]_0 [0]),
        .I1(\uppCL0_reg[45]_0 [1]),
        .I2(uppCL0[6]),
        .O(\uppCL0_reg[7]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1840" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__4 
       (.I0(\uppCL0_reg[45]_0 [3]),
        .I1(\uppCL0_reg[45]_0 [4]),
        .I2(uppCL0[42]),
        .O(\uppCL0_reg[43]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1877" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__5 
       (.I0(lowCL0[43]),
        .I1(lowCL0[44]),
        .I2(lowCL0[42]),
        .O(\lowCL0_reg[43]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1885" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__6 
       (.I0(uppCL0[1]),
        .I1(uppCL0[2]),
        .I2(uppCL0[0]),
        .O(\uppCL0_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1893" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__7 
       (.I0(uppCL0[31]),
        .I1(uppCL0[32]),
        .I2(uppCL0[30]),
        .O(\uppCL0_reg[31]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1901" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__8 
       (.I0(lowCL0[31]),
        .I1(lowCL0[32]),
        .I2(lowCL0[30]),
        .O(\lowCL0_reg[31]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1909" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[1][8]_i_1__9 
       (.I0(lowCL0[25]),
        .I1(lowCL0[26]),
        .I2(lowCL0[24]),
        .O(\lowCL0_reg[25]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair2101" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1 
       (.I0(uppCL0[37]),
        .I1(uppCL0[38]),
        .O(\blk1.(null)[0].diff [0]));
  (* SOFT_HLUTNM = "soft_lutpair2109" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__0 
       (.I0(uppCL0[19]),
        .I1(uppCL0[20]),
        .O(\blk1.(null)[0].diff_1 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2117" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__1 
       (.I0(uppCL0[13]),
        .I1(uppCL0[14]),
        .O(\blk1.(null)[0].diff_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2189" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__10 
       (.I0(lowCL0[13]),
        .I1(lowCL0[14]),
        .O(\blk1.(null)[0].diff_21 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2197" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__11 
       (.I0(lowCL0[7]),
        .I1(lowCL0[8]),
        .O(\blk1.(null)[0].diff_23 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2205" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__12 
       (.I0(lowCL0[1]),
        .I1(lowCL0[2]),
        .O(\blk1.(null)[0].diff_25 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2125" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__2 
       (.I0(uppCL0[25]),
        .I1(uppCL0[26]),
        .O(\blk1.(null)[0].diff_5 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2133" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__3 
       (.I0(lowCL0[43]),
        .I1(lowCL0[44]),
        .O(\blk1.(null)[0].diff_7 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2141" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__4 
       (.I0(uppCL0[1]),
        .I1(uppCL0[2]),
        .O(\blk1.(null)[0].diff_9 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2149" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__5 
       (.I0(uppCL0[31]),
        .I1(uppCL0[32]),
        .O(\blk1.(null)[0].diff_11 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2157" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__6 
       (.I0(lowCL0[31]),
        .I1(lowCL0[32]),
        .O(\blk1.(null)[0].diff_13 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2165" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__7 
       (.I0(lowCL0[25]),
        .I1(lowCL0[26]),
        .O(\blk1.(null)[0].diff_15 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2173" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__8 
       (.I0(lowCL0[37]),
        .I1(lowCL0[38]),
        .O(\blk1.(null)[0].diff_17 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2181" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[1][9]_i_1__9 
       (.I0(lowCL0[19]),
        .I1(lowCL0[20]),
        .O(\blk1.(null)[0].diff_19 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1709" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1 
       (.I0(uppCL1[39]),
        .I1(uppCL1[38]),
        .I2(uppCL1[37]),
        .O(\uppCL1_reg[39]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1713" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__0 
       (.I0(uppCL1[21]),
        .I1(uppCL1[20]),
        .I2(uppCL1[19]),
        .O(\uppCL1_reg[21]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1717" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__1 
       (.I0(uppCL1[15]),
        .I1(uppCL1[14]),
        .I2(uppCL1[13]),
        .O(\uppCL1_reg[15]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1745" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__10 
       (.I0(lowCL1[39]),
        .I1(lowCL1[38]),
        .I2(lowCL1[37]),
        .O(\lowCL1_reg[39]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1749" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__11 
       (.I0(lowCL1[21]),
        .I1(lowCL1[20]),
        .I2(lowCL1[19]),
        .O(\lowCL1_reg[21]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1753" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__12 
       (.I0(lowCL1[15]),
        .I1(lowCL1[14]),
        .I2(lowCL1[13]),
        .O(\lowCL1_reg[15]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1757" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__13 
       (.I0(lowCL1[9]),
        .I1(lowCL1[8]),
        .I2(lowCL1[7]),
        .O(\lowCL1_reg[9]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1761" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__14 
       (.I0(lowCL1[3]),
        .I1(lowCL1[2]),
        .I2(lowCL1[1]),
        .O(\lowCL1_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1721" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__2 
       (.I0(uppCL1[27]),
        .I1(uppCL1[26]),
        .I2(uppCL1[25]),
        .O(\uppCL1_reg[27]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1765" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [2]),
        .I1(\uppCL1_reg[45]_0 [1]),
        .I2(\uppCL1_reg[45]_0 [0]),
        .O(\uppCL1_reg[9]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1769" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [5]),
        .I1(\uppCL1_reg[45]_0 [4]),
        .I2(\uppCL1_reg[45]_0 [3]),
        .O(\uppCL1_reg[45]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1725" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__5 
       (.I0(lowCL1[45]),
        .I1(lowCL1[44]),
        .I2(lowCL1[43]),
        .O(\lowCL1_reg[45]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1729" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__6 
       (.I0(uppCL1[3]),
        .I1(uppCL1[2]),
        .I2(uppCL1[1]),
        .O(\uppCL1_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1733" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__7 
       (.I0(uppCL1[33]),
        .I1(uppCL1[32]),
        .I2(uppCL1[31]),
        .O(\uppCL1_reg[33]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1737" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__8 
       (.I0(lowCL1[33]),
        .I1(lowCL1[32]),
        .I2(lowCL1[31]),
        .O(\lowCL1_reg[33]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1741" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[2][11]_i_1__9 
       (.I0(lowCL1[27]),
        .I1(lowCL1[26]),
        .I2(lowCL1[25]),
        .O(\lowCL1_reg[27]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2029" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2 
       (.I0(uppCL1[38]),
        .I1(uppCL1[37]),
        .O(\uppCL1_reg[38]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2033" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__0 
       (.I0(uppCL1[20]),
        .I1(uppCL1[19]),
        .O(\uppCL1_reg[20]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2037" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__1 
       (.I0(uppCL1[14]),
        .I1(uppCL1[13]),
        .O(\uppCL1_reg[14]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2073" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__10 
       (.I0(lowCL1[38]),
        .I1(lowCL1[37]),
        .O(\lowCL1_reg[38]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2077" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__11 
       (.I0(lowCL1[20]),
        .I1(lowCL1[19]),
        .O(\lowCL1_reg[20]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2081" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__12 
       (.I0(lowCL1[14]),
        .I1(lowCL1[13]),
        .O(\lowCL1_reg[14]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2085" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__13 
       (.I0(lowCL1[8]),
        .I1(lowCL1[7]),
        .O(\lowCL1_reg[8]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2089" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__14 
       (.I0(lowCL1[2]),
        .I1(lowCL1[1]),
        .O(\lowCL1_reg[2]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2041" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__2 
       (.I0(uppCL1[26]),
        .I1(uppCL1[25]),
        .O(\uppCL1_reg[26]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2045" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__3 
       (.I0(\uppCL1_reg[45]_0 [1]),
        .I1(\uppCL1_reg[45]_0 [0]),
        .O(\uppCL1_reg[8]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2049" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__4 
       (.I0(\uppCL1_reg[45]_0 [4]),
        .I1(\uppCL1_reg[45]_0 [3]),
        .O(\uppCL1_reg[44]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2053" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__5 
       (.I0(lowCL1[44]),
        .I1(lowCL1[43]),
        .O(\lowCL1_reg[44]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2057" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__6 
       (.I0(uppCL1[2]),
        .I1(uppCL1[1]),
        .O(\uppCL1_reg[2]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2061" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__7 
       (.I0(uppCL1[32]),
        .I1(uppCL1[31]),
        .O(\uppCL1_reg[32]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2065" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__8 
       (.I0(lowCL1[32]),
        .I1(lowCL1[31]),
        .O(\lowCL1_reg[32]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2069" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[2][11]_i_2__9 
       (.I0(lowCL1[26]),
        .I1(lowCL1[25]),
        .O(\lowCL1_reg[26]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1598" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1 
       (.I0(uppCL1[37]),
        .I1(uppCL1[38]),
        .I2(uppCL1[39]),
        .I3(uppCL1[36]),
        .O(\uppCL1_reg[38]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1606" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__0 
       (.I0(uppCL1[19]),
        .I1(uppCL1[20]),
        .I2(uppCL1[21]),
        .I3(uppCL1[18]),
        .O(\uppCL1_reg[20]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1614" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__1 
       (.I0(uppCL1[13]),
        .I1(uppCL1[14]),
        .I2(uppCL1[15]),
        .I3(uppCL1[12]),
        .O(\uppCL1_reg[14]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1686" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__10 
       (.I0(lowCL1[13]),
        .I1(lowCL1[14]),
        .I2(lowCL1[15]),
        .I3(lowCL1[12]),
        .O(\lowCL1_reg[14]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1694" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__11 
       (.I0(lowCL1[7]),
        .I1(lowCL1[8]),
        .I2(lowCL1[9]),
        .I3(lowCL1[6]),
        .O(\lowCL1_reg[8]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1702" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__12 
       (.I0(lowCL1[1]),
        .I1(lowCL1[2]),
        .I2(lowCL1[3]),
        .I3(lowCL1[0]),
        .O(\lowCL1_reg[2]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1622" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__2 
       (.I0(uppCL1[25]),
        .I1(uppCL1[26]),
        .I2(uppCL1[27]),
        .I3(uppCL1[24]),
        .O(\uppCL1_reg[26]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1630" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__3 
       (.I0(lowCL1[43]),
        .I1(lowCL1[44]),
        .I2(lowCL1[45]),
        .I3(lowCL1[42]),
        .O(\lowCL1_reg[44]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1638" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__4 
       (.I0(uppCL1[1]),
        .I1(uppCL1[2]),
        .I2(uppCL1[3]),
        .I3(uppCL1[0]),
        .O(\uppCL1_reg[2]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1646" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__5 
       (.I0(uppCL1[31]),
        .I1(uppCL1[32]),
        .I2(uppCL1[33]),
        .I3(uppCL1[30]),
        .O(\uppCL1_reg[32]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1654" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__6 
       (.I0(lowCL1[31]),
        .I1(lowCL1[32]),
        .I2(lowCL1[33]),
        .I3(lowCL1[30]),
        .O(\lowCL1_reg[32]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1662" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__7 
       (.I0(lowCL1[25]),
        .I1(lowCL1[26]),
        .I2(lowCL1[27]),
        .I3(lowCL1[24]),
        .O(\lowCL1_reg[26]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1670" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__8 
       (.I0(lowCL1[37]),
        .I1(lowCL1[38]),
        .I2(lowCL1[39]),
        .I3(lowCL1[36]),
        .O(\lowCL1_reg[38]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1678" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[2][2]_i_1__9 
       (.I0(lowCL1[19]),
        .I1(lowCL1[20]),
        .I2(lowCL1[21]),
        .I3(lowCL1[18]),
        .O(\lowCL1_reg[20]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1846" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1 
       (.I0(uppCL1[37]),
        .I1(uppCL1[38]),
        .I2(uppCL1[39]),
        .O(\uppCL1_reg[38]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1854" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__0 
       (.I0(uppCL1[19]),
        .I1(uppCL1[20]),
        .I2(uppCL1[21]),
        .O(\uppCL1_reg[20]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1862" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__1 
       (.I0(uppCL1[13]),
        .I1(uppCL1[14]),
        .I2(uppCL1[15]),
        .O(\uppCL1_reg[14]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1934" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__10 
       (.I0(lowCL1[13]),
        .I1(lowCL1[14]),
        .I2(lowCL1[15]),
        .O(\lowCL1_reg[14]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1942" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__11 
       (.I0(lowCL1[7]),
        .I1(lowCL1[8]),
        .I2(lowCL1[9]),
        .O(\lowCL1_reg[8]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1950" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__12 
       (.I0(lowCL1[1]),
        .I1(lowCL1[2]),
        .I2(lowCL1[3]),
        .O(\lowCL1_reg[2]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1870" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__2 
       (.I0(uppCL1[25]),
        .I1(uppCL1[26]),
        .I2(uppCL1[27]),
        .O(\uppCL1_reg[26]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1878" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__3 
       (.I0(lowCL1[43]),
        .I1(lowCL1[44]),
        .I2(lowCL1[45]),
        .O(\lowCL1_reg[44]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1886" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__4 
       (.I0(uppCL1[1]),
        .I1(uppCL1[2]),
        .I2(uppCL1[3]),
        .O(\uppCL1_reg[2]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1894" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__5 
       (.I0(uppCL1[31]),
        .I1(uppCL1[32]),
        .I2(uppCL1[33]),
        .O(\uppCL1_reg[32]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1902" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__6 
       (.I0(lowCL1[31]),
        .I1(lowCL1[32]),
        .I2(lowCL1[33]),
        .O(\lowCL1_reg[32]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1910" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__7 
       (.I0(lowCL1[25]),
        .I1(lowCL1[26]),
        .I2(lowCL1[27]),
        .O(\lowCL1_reg[26]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1918" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__8 
       (.I0(lowCL1[37]),
        .I1(lowCL1[38]),
        .I2(lowCL1[39]),
        .O(\lowCL1_reg[38]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1926" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[2][3]_i_1__9 
       (.I0(lowCL1[19]),
        .I1(lowCL1[20]),
        .I2(lowCL1[21]),
        .O(\lowCL1_reg[20]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2102" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1 
       (.I0(uppCL1[38]),
        .I1(uppCL1[39]),
        .O(\uppCL1_reg[38]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2110" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__0 
       (.I0(uppCL1[20]),
        .I1(uppCL1[21]),
        .O(\uppCL1_reg[20]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2118" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__1 
       (.I0(uppCL1[14]),
        .I1(uppCL1[15]),
        .O(\uppCL1_reg[14]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2190" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__10 
       (.I0(lowCL1[14]),
        .I1(lowCL1[15]),
        .O(\lowCL1_reg[14]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2198" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__11 
       (.I0(lowCL1[8]),
        .I1(lowCL1[9]),
        .O(\lowCL1_reg[8]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2206" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__12 
       (.I0(lowCL1[2]),
        .I1(lowCL1[3]),
        .O(\lowCL1_reg[2]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2126" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__2 
       (.I0(uppCL1[26]),
        .I1(uppCL1[27]),
        .O(\uppCL1_reg[26]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2134" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__3 
       (.I0(lowCL1[44]),
        .I1(lowCL1[45]),
        .O(\lowCL1_reg[44]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2142" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__4 
       (.I0(uppCL1[2]),
        .I1(uppCL1[3]),
        .O(\uppCL1_reg[2]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2150" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__5 
       (.I0(uppCL1[32]),
        .I1(uppCL1[33]),
        .O(\uppCL1_reg[32]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2158" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__6 
       (.I0(lowCL1[32]),
        .I1(lowCL1[33]),
        .O(\lowCL1_reg[32]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2166" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__7 
       (.I0(lowCL1[26]),
        .I1(lowCL1[27]),
        .O(\lowCL1_reg[26]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2174" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__8 
       (.I0(lowCL1[38]),
        .I1(lowCL1[39]),
        .O(\lowCL1_reg[38]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2182" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[2][9]_i_1__9 
       (.I0(lowCL1[20]),
        .I1(lowCL1[21]),
        .O(\lowCL1_reg[20]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1599" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1 
       (.I0(uppCL1[37]),
        .I1(uppCL1[38]),
        .I2(uppCL1[39]),
        .I3(uppCL1[36]),
        .O(\uppCL1_reg[37]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1607" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__0 
       (.I0(uppCL1[19]),
        .I1(uppCL1[20]),
        .I2(uppCL1[21]),
        .I3(uppCL1[18]),
        .O(\uppCL1_reg[19]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1615" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__1 
       (.I0(uppCL1[13]),
        .I1(uppCL1[14]),
        .I2(uppCL1[15]),
        .I3(uppCL1[12]),
        .O(\uppCL1_reg[13]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1671" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__10 
       (.I0(lowCL1[37]),
        .I1(lowCL1[38]),
        .I2(lowCL1[39]),
        .I3(lowCL1[36]),
        .O(\lowCL1_reg[37]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1679" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__11 
       (.I0(lowCL1[19]),
        .I1(lowCL1[20]),
        .I2(lowCL1[21]),
        .I3(lowCL1[18]),
        .O(\lowCL1_reg[19]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1687" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__12 
       (.I0(lowCL1[13]),
        .I1(lowCL1[14]),
        .I2(lowCL1[15]),
        .I3(lowCL1[12]),
        .O(\lowCL1_reg[13]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1695" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__13 
       (.I0(lowCL1[7]),
        .I1(lowCL1[8]),
        .I2(lowCL1[9]),
        .I3(lowCL1[6]),
        .O(\lowCL1_reg[7]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1703" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__14 
       (.I0(lowCL1[1]),
        .I1(lowCL1[2]),
        .I2(lowCL1[3]),
        .I3(lowCL1[0]),
        .O(\lowCL1_reg[1]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1623" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__2 
       (.I0(uppCL1[25]),
        .I1(uppCL1[26]),
        .I2(uppCL1[27]),
        .I3(uppCL1[24]),
        .O(\uppCL1_reg[25]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1582" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [0]),
        .I1(\uppCL1_reg[45]_0 [1]),
        .I2(\uppCL1_reg[45]_0 [2]),
        .I3(uppCL1[6]),
        .O(\uppCL1_reg[7]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1590" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [3]),
        .I1(\uppCL1_reg[45]_0 [4]),
        .I2(\uppCL1_reg[45]_0 [5]),
        .I3(uppCL1[42]),
        .O(\uppCL1_reg[43]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1631" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__5 
       (.I0(lowCL1[43]),
        .I1(lowCL1[44]),
        .I2(lowCL1[45]),
        .I3(lowCL1[42]),
        .O(\lowCL1_reg[43]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1639" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__6 
       (.I0(uppCL1[1]),
        .I1(uppCL1[2]),
        .I2(uppCL1[3]),
        .I3(uppCL1[0]),
        .O(\uppCL1_reg[1]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1647" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__7 
       (.I0(uppCL1[31]),
        .I1(uppCL1[32]),
        .I2(uppCL1[33]),
        .I3(uppCL1[30]),
        .O(\uppCL1_reg[31]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1655" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__8 
       (.I0(lowCL1[31]),
        .I1(lowCL1[32]),
        .I2(lowCL1[33]),
        .I3(lowCL1[30]),
        .O(\lowCL1_reg[31]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1663" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[3][10]_i_1__9 
       (.I0(lowCL1[25]),
        .I1(lowCL1[26]),
        .I2(lowCL1[27]),
        .I3(lowCL1[24]),
        .O(\lowCL1_reg[25]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1846" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1 
       (.I0(uppCL1[37]),
        .I1(uppCL1[38]),
        .I2(uppCL1[39]),
        .O(\uppCL1_reg[37]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1854" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__0 
       (.I0(uppCL1[19]),
        .I1(uppCL1[20]),
        .I2(uppCL1[21]),
        .O(\uppCL1_reg[19]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1862" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__1 
       (.I0(uppCL1[13]),
        .I1(uppCL1[14]),
        .I2(uppCL1[15]),
        .O(\uppCL1_reg[13]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1934" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__10 
       (.I0(lowCL1[13]),
        .I1(lowCL1[14]),
        .I2(lowCL1[15]),
        .O(\lowCL1_reg[13]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1942" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__11 
       (.I0(lowCL1[7]),
        .I1(lowCL1[8]),
        .I2(lowCL1[9]),
        .O(\lowCL1_reg[7]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1950" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__12 
       (.I0(lowCL1[1]),
        .I1(lowCL1[2]),
        .I2(lowCL1[3]),
        .O(\lowCL1_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1870" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__2 
       (.I0(uppCL1[25]),
        .I1(uppCL1[26]),
        .I2(uppCL1[27]),
        .O(\uppCL1_reg[25]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1878" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__3 
       (.I0(lowCL1[43]),
        .I1(lowCL1[44]),
        .I2(lowCL1[45]),
        .O(\lowCL1_reg[43]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1886" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__4 
       (.I0(uppCL1[1]),
        .I1(uppCL1[2]),
        .I2(uppCL1[3]),
        .O(\uppCL1_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1894" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__5 
       (.I0(uppCL1[31]),
        .I1(uppCL1[32]),
        .I2(uppCL1[33]),
        .O(\uppCL1_reg[31]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1902" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__6 
       (.I0(lowCL1[31]),
        .I1(lowCL1[32]),
        .I2(lowCL1[33]),
        .O(\lowCL1_reg[31]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1910" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__7 
       (.I0(lowCL1[25]),
        .I1(lowCL1[26]),
        .I2(lowCL1[27]),
        .O(\lowCL1_reg[25]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1918" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__8 
       (.I0(lowCL1[37]),
        .I1(lowCL1[38]),
        .I2(lowCL1[39]),
        .O(\lowCL1_reg[37]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1926" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[3][11]_i_1__9 
       (.I0(lowCL1[19]),
        .I1(lowCL1[20]),
        .I2(lowCL1[21]),
        .O(\lowCL1_reg[19]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1598" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1 
       (.I0(uppCL1[37]),
        .I1(uppCL1[38]),
        .I2(uppCL1[39]),
        .I3(uppCL1[36]),
        .O(\uppCL1_reg[37]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1606" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__0 
       (.I0(uppCL1[19]),
        .I1(uppCL1[20]),
        .I2(uppCL1[21]),
        .I3(uppCL1[18]),
        .O(\uppCL1_reg[19]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1614" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__1 
       (.I0(uppCL1[13]),
        .I1(uppCL1[14]),
        .I2(uppCL1[15]),
        .I3(uppCL1[12]),
        .O(\uppCL1_reg[13]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1670" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__10 
       (.I0(lowCL1[37]),
        .I1(lowCL1[38]),
        .I2(lowCL1[39]),
        .I3(lowCL1[36]),
        .O(\lowCL1_reg[37]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1678" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__11 
       (.I0(lowCL1[19]),
        .I1(lowCL1[20]),
        .I2(lowCL1[21]),
        .I3(lowCL1[18]),
        .O(\lowCL1_reg[19]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1686" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__12 
       (.I0(lowCL1[13]),
        .I1(lowCL1[14]),
        .I2(lowCL1[15]),
        .I3(lowCL1[12]),
        .O(\lowCL1_reg[13]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1694" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__13 
       (.I0(lowCL1[7]),
        .I1(lowCL1[8]),
        .I2(lowCL1[9]),
        .I3(lowCL1[6]),
        .O(\lowCL1_reg[7]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1702" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__14 
       (.I0(lowCL1[1]),
        .I1(lowCL1[2]),
        .I2(lowCL1[3]),
        .I3(lowCL1[0]),
        .O(\lowCL1_reg[1]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1622" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__2 
       (.I0(uppCL1[25]),
        .I1(uppCL1[26]),
        .I2(uppCL1[27]),
        .I3(uppCL1[24]),
        .O(\uppCL1_reg[25]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1582" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [0]),
        .I1(\uppCL1_reg[45]_0 [1]),
        .I2(\uppCL1_reg[45]_0 [2]),
        .I3(uppCL1[6]),
        .O(\uppCL1_reg[7]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1590" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [3]),
        .I1(\uppCL1_reg[45]_0 [4]),
        .I2(\uppCL1_reg[45]_0 [5]),
        .I3(uppCL1[42]),
        .O(\uppCL1_reg[43]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1630" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__5 
       (.I0(lowCL1[43]),
        .I1(lowCL1[44]),
        .I2(lowCL1[45]),
        .I3(lowCL1[42]),
        .O(\lowCL1_reg[43]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1638" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__6 
       (.I0(uppCL1[1]),
        .I1(uppCL1[2]),
        .I2(uppCL1[3]),
        .I3(uppCL1[0]),
        .O(\uppCL1_reg[1]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1646" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__7 
       (.I0(uppCL1[31]),
        .I1(uppCL1[32]),
        .I2(uppCL1[33]),
        .I3(uppCL1[30]),
        .O(\uppCL1_reg[31]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1654" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__8 
       (.I0(lowCL1[31]),
        .I1(lowCL1[32]),
        .I2(lowCL1[33]),
        .I3(lowCL1[30]),
        .O(\lowCL1_reg[31]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1662" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[3][12]_i_1__9 
       (.I0(lowCL1[25]),
        .I1(lowCL1[26]),
        .I2(lowCL1[27]),
        .I3(lowCL1[24]),
        .O(\lowCL1_reg[25]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1965" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1 
       (.I0(uppCL1[38]),
        .I1(uppCL1[37]),
        .O(\uppCL1_reg[38]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1969" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__0 
       (.I0(uppCL1[20]),
        .I1(uppCL1[19]),
        .O(\uppCL1_reg[20]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1973" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__1 
       (.I0(uppCL1[14]),
        .I1(uppCL1[13]),
        .O(\uppCL1_reg[14]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2009" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__10 
       (.I0(lowCL1[38]),
        .I1(lowCL1[37]),
        .O(\lowCL1_reg[38]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2013" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__11 
       (.I0(lowCL1[20]),
        .I1(lowCL1[19]),
        .O(\lowCL1_reg[20]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2017" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__12 
       (.I0(lowCL1[14]),
        .I1(lowCL1[13]),
        .O(\lowCL1_reg[14]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2021" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__13 
       (.I0(lowCL1[8]),
        .I1(lowCL1[7]),
        .O(\lowCL1_reg[8]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2025" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__14 
       (.I0(lowCL1[2]),
        .I1(lowCL1[1]),
        .O(\lowCL1_reg[2]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1977" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__2 
       (.I0(uppCL1[26]),
        .I1(uppCL1[25]),
        .O(\uppCL1_reg[26]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1957" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [1]),
        .I1(\uppCL1_reg[45]_0 [0]),
        .O(\uppCL1_reg[8]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1961" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [4]),
        .I1(\uppCL1_reg[45]_0 [3]),
        .O(\uppCL1_reg[44]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1989" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__5 
       (.I0(lowCL1[44]),
        .I1(lowCL1[43]),
        .O(\lowCL1_reg[44]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1993" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__6 
       (.I0(uppCL1[2]),
        .I1(uppCL1[1]),
        .O(\uppCL1_reg[2]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1997" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__7 
       (.I0(uppCL1[32]),
        .I1(uppCL1[31]),
        .O(\uppCL1_reg[32]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2001" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__8 
       (.I0(lowCL1[32]),
        .I1(lowCL1[31]),
        .O(\lowCL1_reg[32]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2005" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[3][13]_i_1__9 
       (.I0(lowCL1[26]),
        .I1(lowCL1[25]),
        .O(\lowCL1_reg[26]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1781" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1 
       (.I0(uppCL1[37]),
        .I1(uppCL1[38]),
        .I2(uppCL1[36]),
        .O(\uppCL1_reg[37]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1785" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__0 
       (.I0(uppCL1[19]),
        .I1(uppCL1[20]),
        .I2(uppCL1[18]),
        .O(\uppCL1_reg[19]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1789" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__1 
       (.I0(uppCL1[13]),
        .I1(uppCL1[14]),
        .I2(uppCL1[12]),
        .O(\uppCL1_reg[13]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1817" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__10 
       (.I0(lowCL1[37]),
        .I1(lowCL1[38]),
        .I2(lowCL1[36]),
        .O(\lowCL1_reg[37]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1821" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__11 
       (.I0(lowCL1[19]),
        .I1(lowCL1[20]),
        .I2(lowCL1[18]),
        .O(\lowCL1_reg[19]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1825" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__12 
       (.I0(lowCL1[13]),
        .I1(lowCL1[14]),
        .I2(lowCL1[12]),
        .O(\lowCL1_reg[13]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1829" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__13 
       (.I0(lowCL1[7]),
        .I1(lowCL1[8]),
        .I2(lowCL1[6]),
        .O(\lowCL1_reg[7]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1833" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__14 
       (.I0(lowCL1[1]),
        .I1(lowCL1[2]),
        .I2(lowCL1[0]),
        .O(\lowCL1_reg[1]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1793" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__2 
       (.I0(uppCL1[25]),
        .I1(uppCL1[26]),
        .I2(uppCL1[24]),
        .O(\uppCL1_reg[25]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1773" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [0]),
        .I1(\uppCL1_reg[45]_0 [1]),
        .I2(uppCL1[6]),
        .O(\uppCL1_reg[7]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1777" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [3]),
        .I1(\uppCL1_reg[45]_0 [4]),
        .I2(uppCL1[42]),
        .O(\uppCL1_reg[43]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1797" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__5 
       (.I0(lowCL1[43]),
        .I1(lowCL1[44]),
        .I2(lowCL1[42]),
        .O(\lowCL1_reg[43]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1801" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__6 
       (.I0(uppCL1[1]),
        .I1(uppCL1[2]),
        .I2(uppCL1[0]),
        .O(\uppCL1_reg[1]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1805" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__7 
       (.I0(uppCL1[31]),
        .I1(uppCL1[32]),
        .I2(uppCL1[30]),
        .O(\uppCL1_reg[31]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1809" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__8 
       (.I0(lowCL1[31]),
        .I1(lowCL1[32]),
        .I2(lowCL1[30]),
        .O(\lowCL1_reg[31]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1813" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[3][14]_i_1__9 
       (.I0(lowCL1[25]),
        .I1(lowCL1[26]),
        .I2(lowCL1[24]),
        .O(\lowCL1_reg[25]_4 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1 
       (.I0(uppCL1[38]),
        .O(\uppCL1_reg[38]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__0 
       (.I0(uppCL1[26]),
        .O(\uppCL1_reg[26]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__1 
       (.I0(uppCL1[20]),
        .O(\uppCL1_reg[20]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__10 
       (.I0(lowCL1[26]),
        .O(\lowCL1_reg[26]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__11 
       (.I0(lowCL1[20]),
        .O(\lowCL1_reg[20]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__12 
       (.I0(lowCL1[14]),
        .O(\lowCL1_reg[14]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__13 
       (.I0(lowCL1[8]),
        .O(\lowCL1_reg[8]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__14 
       (.I0(lowCL1[2]),
        .O(\lowCL1_reg[2]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__2 
       (.I0(uppCL1[14]),
        .O(\uppCL1_reg[14]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair2217" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [4]),
        .O(\uppCL1_reg[44]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair2213" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [1]),
        .O(\uppCL1_reg[8]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__5 
       (.I0(lowCL1[44]),
        .O(\lowCL1_reg[44]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__6 
       (.I0(uppCL1[32]),
        .O(\uppCL1_reg[32]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__7 
       (.I0(uppCL1[2]),
        .O(\uppCL1_reg[2]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__8 
       (.I0(lowCL1[38]),
        .O(\lowCL1_reg[38]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[3][15]_i_1__9 
       (.I0(lowCL1[32]),
        .O(\lowCL1_reg[32]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1847" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1 
       (.I0(uppCL1[37]),
        .I1(uppCL1[38]),
        .I2(uppCL1[36]),
        .O(\uppCL1_reg[37]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1855" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__0 
       (.I0(uppCL1[19]),
        .I1(uppCL1[20]),
        .I2(uppCL1[18]),
        .O(\uppCL1_reg[19]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1863" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__1 
       (.I0(uppCL1[13]),
        .I1(uppCL1[14]),
        .I2(uppCL1[12]),
        .O(\uppCL1_reg[13]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1919" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__10 
       (.I0(lowCL1[37]),
        .I1(lowCL1[38]),
        .I2(lowCL1[36]),
        .O(\lowCL1_reg[37]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1927" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__11 
       (.I0(lowCL1[19]),
        .I1(lowCL1[20]),
        .I2(lowCL1[18]),
        .O(\lowCL1_reg[19]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1935" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__12 
       (.I0(lowCL1[13]),
        .I1(lowCL1[14]),
        .I2(lowCL1[12]),
        .O(\lowCL1_reg[13]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1943" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__13 
       (.I0(lowCL1[7]),
        .I1(lowCL1[8]),
        .I2(lowCL1[6]),
        .O(\lowCL1_reg[7]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1951" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__14 
       (.I0(lowCL1[1]),
        .I1(lowCL1[2]),
        .I2(lowCL1[0]),
        .O(\lowCL1_reg[1]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1871" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__2 
       (.I0(uppCL1[25]),
        .I1(uppCL1[26]),
        .I2(uppCL1[24]),
        .O(\uppCL1_reg[25]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1837" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [0]),
        .I1(\uppCL1_reg[45]_0 [1]),
        .I2(uppCL1[6]),
        .O(\uppCL1_reg[7]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1841" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [3]),
        .I1(\uppCL1_reg[45]_0 [4]),
        .I2(uppCL1[42]),
        .O(\uppCL1_reg[43]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1879" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__5 
       (.I0(lowCL1[43]),
        .I1(lowCL1[44]),
        .I2(lowCL1[42]),
        .O(\lowCL1_reg[43]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1887" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__6 
       (.I0(uppCL1[1]),
        .I1(uppCL1[2]),
        .I2(uppCL1[0]),
        .O(\uppCL1_reg[1]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1895" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__7 
       (.I0(uppCL1[31]),
        .I1(uppCL1[32]),
        .I2(uppCL1[30]),
        .O(\uppCL1_reg[31]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1903" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__8 
       (.I0(lowCL1[31]),
        .I1(lowCL1[32]),
        .I2(lowCL1[30]),
        .O(\lowCL1_reg[31]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1911" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[3][16]_i_1__9 
       (.I0(lowCL1[25]),
        .I1(lowCL1[26]),
        .I2(lowCL1[24]),
        .O(\lowCL1_reg[25]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair2103" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1 
       (.I0(uppCL1[38]),
        .I1(uppCL1[37]),
        .O(\uppCL1_reg[38]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2111" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__0 
       (.I0(uppCL1[20]),
        .I1(uppCL1[19]),
        .O(\uppCL1_reg[20]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2119" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__1 
       (.I0(uppCL1[14]),
        .I1(uppCL1[13]),
        .O(\uppCL1_reg[14]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2175" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__10 
       (.I0(lowCL1[38]),
        .I1(lowCL1[37]),
        .O(\lowCL1_reg[38]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2183" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__11 
       (.I0(lowCL1[20]),
        .I1(lowCL1[19]),
        .O(\lowCL1_reg[20]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2191" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__12 
       (.I0(lowCL1[14]),
        .I1(lowCL1[13]),
        .O(\lowCL1_reg[14]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2199" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__13 
       (.I0(lowCL1[8]),
        .I1(lowCL1[7]),
        .O(\lowCL1_reg[8]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2207" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__14 
       (.I0(lowCL1[2]),
        .I1(lowCL1[1]),
        .O(\lowCL1_reg[2]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2127" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__2 
       (.I0(uppCL1[26]),
        .I1(uppCL1[25]),
        .O(\uppCL1_reg[26]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2045" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [1]),
        .I1(\uppCL1_reg[45]_0 [0]),
        .O(\uppCL1_reg[8]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2049" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [4]),
        .I1(\uppCL1_reg[45]_0 [3]),
        .O(\uppCL1_reg[44]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2135" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__5 
       (.I0(lowCL1[44]),
        .I1(lowCL1[43]),
        .O(\lowCL1_reg[44]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2143" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__6 
       (.I0(uppCL1[2]),
        .I1(uppCL1[1]),
        .O(\uppCL1_reg[2]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2151" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__7 
       (.I0(uppCL1[32]),
        .I1(uppCL1[31]),
        .O(\uppCL1_reg[32]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2159" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__8 
       (.I0(lowCL1[32]),
        .I1(lowCL1[31]),
        .O(\lowCL1_reg[32]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2167" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[3][17]_i_1__9 
       (.I0(lowCL1[26]),
        .I1(lowCL1[25]),
        .O(\lowCL1_reg[26]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1781" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1 
       (.I0(uppCL1[38]),
        .I1(uppCL1[36]),
        .I2(uppCL1[37]),
        .O(\uppCL1_reg[38]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1785" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__0 
       (.I0(uppCL1[20]),
        .I1(uppCL1[18]),
        .I2(uppCL1[19]),
        .O(\uppCL1_reg[20]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1789" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__1 
       (.I0(uppCL1[14]),
        .I1(uppCL1[12]),
        .I2(uppCL1[13]),
        .O(\uppCL1_reg[14]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1817" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__10 
       (.I0(lowCL1[38]),
        .I1(lowCL1[36]),
        .I2(lowCL1[37]),
        .O(\lowCL1_reg[38]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1821" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__11 
       (.I0(lowCL1[20]),
        .I1(lowCL1[18]),
        .I2(lowCL1[19]),
        .O(\lowCL1_reg[20]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1825" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__12 
       (.I0(lowCL1[14]),
        .I1(lowCL1[12]),
        .I2(lowCL1[13]),
        .O(\lowCL1_reg[14]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1829" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__13 
       (.I0(lowCL1[8]),
        .I1(lowCL1[6]),
        .I2(lowCL1[7]),
        .O(\lowCL1_reg[8]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1833" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__14 
       (.I0(lowCL1[2]),
        .I1(lowCL1[0]),
        .I2(lowCL1[1]),
        .O(\lowCL1_reg[2]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1793" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__2 
       (.I0(uppCL1[26]),
        .I1(uppCL1[24]),
        .I2(uppCL1[25]),
        .O(\uppCL1_reg[26]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1773" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [1]),
        .I1(uppCL1[6]),
        .I2(\uppCL1_reg[45]_0 [0]),
        .O(\uppCL1_reg[8]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1777" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [4]),
        .I1(uppCL1[42]),
        .I2(\uppCL1_reg[45]_0 [3]),
        .O(\uppCL1_reg[44]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1797" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__5 
       (.I0(lowCL1[44]),
        .I1(lowCL1[42]),
        .I2(lowCL1[43]),
        .O(\lowCL1_reg[44]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1801" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__6 
       (.I0(uppCL1[2]),
        .I1(uppCL1[0]),
        .I2(uppCL1[1]),
        .O(\uppCL1_reg[2]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1805" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__7 
       (.I0(uppCL1[32]),
        .I1(uppCL1[30]),
        .I2(uppCL1[31]),
        .O(\uppCL1_reg[32]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1809" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__8 
       (.I0(lowCL1[32]),
        .I1(lowCL1[30]),
        .I2(lowCL1[31]),
        .O(\lowCL1_reg[32]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1813" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[3][18]_i_1__9 
       (.I0(lowCL1[26]),
        .I1(lowCL1[24]),
        .I2(lowCL1[25]),
        .O(\lowCL1_reg[26]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2029" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1 
       (.I0(uppCL1[38]),
        .I1(uppCL1[37]),
        .O(\uppCL1_reg[38]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2033" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__0 
       (.I0(uppCL1[20]),
        .I1(uppCL1[19]),
        .O(\uppCL1_reg[20]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2037" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__1 
       (.I0(uppCL1[14]),
        .I1(uppCL1[13]),
        .O(\uppCL1_reg[14]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2073" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__10 
       (.I0(lowCL1[38]),
        .I1(lowCL1[37]),
        .O(\lowCL1_reg[38]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2077" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__11 
       (.I0(lowCL1[20]),
        .I1(lowCL1[19]),
        .O(\lowCL1_reg[20]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2081" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__12 
       (.I0(lowCL1[14]),
        .I1(lowCL1[13]),
        .O(\lowCL1_reg[14]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2085" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__13 
       (.I0(lowCL1[8]),
        .I1(lowCL1[7]),
        .O(\lowCL1_reg[8]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2089" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__14 
       (.I0(lowCL1[2]),
        .I1(lowCL1[1]),
        .O(\lowCL1_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2041" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__2 
       (.I0(uppCL1[26]),
        .I1(uppCL1[25]),
        .O(\uppCL1_reg[26]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1981" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [1]),
        .I1(\uppCL1_reg[45]_0 [0]),
        .O(\uppCL1_reg[8]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1985" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [4]),
        .I1(\uppCL1_reg[45]_0 [3]),
        .O(\uppCL1_reg[44]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2053" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__5 
       (.I0(lowCL1[44]),
        .I1(lowCL1[43]),
        .O(\lowCL1_reg[44]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2057" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__6 
       (.I0(uppCL1[2]),
        .I1(uppCL1[1]),
        .O(\uppCL1_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2061" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__7 
       (.I0(uppCL1[32]),
        .I1(uppCL1[31]),
        .O(\uppCL1_reg[32]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2065" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__8 
       (.I0(lowCL1[32]),
        .I1(lowCL1[31]),
        .O(\lowCL1_reg[32]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2069" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[3][1]_i_1__9 
       (.I0(lowCL1[26]),
        .I1(lowCL1[25]),
        .O(\lowCL1_reg[26]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1599" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1 
       (.I0(uppCL1[37]),
        .I1(uppCL1[38]),
        .I2(uppCL1[39]),
        .I3(uppCL1[36]),
        .O(\uppCL1_reg[37]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1607" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__0 
       (.I0(uppCL1[19]),
        .I1(uppCL1[20]),
        .I2(uppCL1[21]),
        .I3(uppCL1[18]),
        .O(\uppCL1_reg[19]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1615" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__1 
       (.I0(uppCL1[13]),
        .I1(uppCL1[14]),
        .I2(uppCL1[15]),
        .I3(uppCL1[12]),
        .O(\uppCL1_reg[13]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1671" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__10 
       (.I0(lowCL1[37]),
        .I1(lowCL1[38]),
        .I2(lowCL1[39]),
        .I3(lowCL1[36]),
        .O(\lowCL1_reg[37]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1679" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__11 
       (.I0(lowCL1[19]),
        .I1(lowCL1[20]),
        .I2(lowCL1[21]),
        .I3(lowCL1[18]),
        .O(\lowCL1_reg[19]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1687" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__12 
       (.I0(lowCL1[13]),
        .I1(lowCL1[14]),
        .I2(lowCL1[15]),
        .I3(lowCL1[12]),
        .O(\lowCL1_reg[13]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1695" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__13 
       (.I0(lowCL1[7]),
        .I1(lowCL1[8]),
        .I2(lowCL1[9]),
        .I3(lowCL1[6]),
        .O(\lowCL1_reg[7]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1703" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__14 
       (.I0(lowCL1[1]),
        .I1(lowCL1[2]),
        .I2(lowCL1[3]),
        .I3(lowCL1[0]),
        .O(\lowCL1_reg[1]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1623" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__2 
       (.I0(uppCL1[25]),
        .I1(uppCL1[26]),
        .I2(uppCL1[27]),
        .I3(uppCL1[24]),
        .O(\uppCL1_reg[25]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1583" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [0]),
        .I1(\uppCL1_reg[45]_0 [1]),
        .I2(\uppCL1_reg[45]_0 [2]),
        .I3(uppCL1[6]),
        .O(\uppCL1_reg[7]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1591" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [3]),
        .I1(\uppCL1_reg[45]_0 [4]),
        .I2(\uppCL1_reg[45]_0 [5]),
        .I3(uppCL1[42]),
        .O(\uppCL1_reg[43]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1631" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__5 
       (.I0(lowCL1[43]),
        .I1(lowCL1[44]),
        .I2(lowCL1[45]),
        .I3(lowCL1[42]),
        .O(\lowCL1_reg[43]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1639" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__6 
       (.I0(uppCL1[1]),
        .I1(uppCL1[2]),
        .I2(uppCL1[3]),
        .I3(uppCL1[0]),
        .O(\uppCL1_reg[1]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1647" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__7 
       (.I0(uppCL1[31]),
        .I1(uppCL1[32]),
        .I2(uppCL1[33]),
        .I3(uppCL1[30]),
        .O(\uppCL1_reg[31]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1655" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__8 
       (.I0(lowCL1[31]),
        .I1(lowCL1[32]),
        .I2(lowCL1[33]),
        .I3(lowCL1[30]),
        .O(\lowCL1_reg[31]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1663" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[3][2]_i_1__9 
       (.I0(lowCL1[25]),
        .I1(lowCL1[26]),
        .I2(lowCL1[27]),
        .I3(lowCL1[24]),
        .O(\lowCL1_reg[25]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair2102" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1 
       (.I0(uppCL1[38]),
        .I1(uppCL1[39]),
        .O(\uppCL1_reg[38]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2110" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__0 
       (.I0(uppCL1[20]),
        .I1(uppCL1[21]),
        .O(\uppCL1_reg[20]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2118" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__1 
       (.I0(uppCL1[14]),
        .I1(uppCL1[15]),
        .O(\uppCL1_reg[14]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2174" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__10 
       (.I0(lowCL1[38]),
        .I1(lowCL1[39]),
        .O(\lowCL1_reg[38]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2182" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__11 
       (.I0(lowCL1[20]),
        .I1(lowCL1[21]),
        .O(\lowCL1_reg[20]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2190" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__12 
       (.I0(lowCL1[14]),
        .I1(lowCL1[15]),
        .O(\lowCL1_reg[14]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2198" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__13 
       (.I0(lowCL1[8]),
        .I1(lowCL1[9]),
        .O(\lowCL1_reg[8]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2206" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__14 
       (.I0(lowCL1[2]),
        .I1(lowCL1[3]),
        .O(\lowCL1_reg[2]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2126" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__2 
       (.I0(uppCL1[26]),
        .I1(uppCL1[27]),
        .O(\uppCL1_reg[26]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2093" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [1]),
        .I1(\uppCL1_reg[45]_0 [2]),
        .O(\uppCL1_reg[8]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2097" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [4]),
        .I1(\uppCL1_reg[45]_0 [5]),
        .O(\uppCL1_reg[44]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2134" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__5 
       (.I0(lowCL1[44]),
        .I1(lowCL1[45]),
        .O(\lowCL1_reg[44]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2142" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__6 
       (.I0(uppCL1[2]),
        .I1(uppCL1[3]),
        .O(\uppCL1_reg[2]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2150" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__7 
       (.I0(uppCL1[32]),
        .I1(uppCL1[33]),
        .O(\uppCL1_reg[32]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2158" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__8 
       (.I0(lowCL1[32]),
        .I1(lowCL1[33]),
        .O(\lowCL1_reg[32]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2166" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[3][3]_i_1__9 
       (.I0(lowCL1[26]),
        .I1(lowCL1[27]),
        .O(\lowCL1_reg[26]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1965" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1 
       (.I0(uppCL1[36]),
        .I1(uppCL1[38]),
        .I2(uppCL1[37]),
        .O(\uppCL1_reg[36]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1969" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__0 
       (.I0(uppCL1[18]),
        .I1(uppCL1[20]),
        .I2(uppCL1[19]),
        .O(\uppCL1_reg[18]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1973" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__1 
       (.I0(uppCL1[12]),
        .I1(uppCL1[14]),
        .I2(uppCL1[13]),
        .O(\uppCL1_reg[12]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2009" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__10 
       (.I0(lowCL1[36]),
        .I1(lowCL1[38]),
        .I2(lowCL1[37]),
        .O(\lowCL1_reg[36]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2013" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__11 
       (.I0(lowCL1[18]),
        .I1(lowCL1[20]),
        .I2(lowCL1[19]),
        .O(\lowCL1_reg[18]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2017" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__12 
       (.I0(lowCL1[12]),
        .I1(lowCL1[14]),
        .I2(lowCL1[13]),
        .O(\lowCL1_reg[12]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2021" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__13 
       (.I0(lowCL1[6]),
        .I1(lowCL1[8]),
        .I2(lowCL1[7]),
        .O(\lowCL1_reg[6]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2025" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__14 
       (.I0(lowCL1[0]),
        .I1(lowCL1[2]),
        .I2(lowCL1[1]),
        .O(\lowCL1_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1977" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__2 
       (.I0(uppCL1[24]),
        .I1(uppCL1[26]),
        .I2(uppCL1[25]),
        .O(\uppCL1_reg[24]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1981" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__3 
       (.I0(uppCL1[6]),
        .I1(\uppCL1_reg[45]_0 [1]),
        .I2(\uppCL1_reg[45]_0 [0]),
        .O(\uppCL1_reg[6]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1985" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__4 
       (.I0(uppCL1[42]),
        .I1(\uppCL1_reg[45]_0 [4]),
        .I2(\uppCL1_reg[45]_0 [3]),
        .O(\uppCL1_reg[42]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1989" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__5 
       (.I0(lowCL1[42]),
        .I1(lowCL1[44]),
        .I2(lowCL1[43]),
        .O(\lowCL1_reg[42]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1993" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__6 
       (.I0(uppCL1[0]),
        .I1(uppCL1[2]),
        .I2(uppCL1[1]),
        .O(\uppCL1_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1997" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__7 
       (.I0(uppCL1[30]),
        .I1(uppCL1[32]),
        .I2(uppCL1[31]),
        .O(\uppCL1_reg[30]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2001" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__8 
       (.I0(lowCL1[30]),
        .I1(lowCL1[32]),
        .I2(lowCL1[31]),
        .O(\lowCL1_reg[30]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2005" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[3][4]_i_1__9 
       (.I0(lowCL1[24]),
        .I1(lowCL1[26]),
        .I2(lowCL1[25]),
        .O(\lowCL1_reg[24]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1709" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1 
       (.I0(uppCL1[37]),
        .I1(uppCL1[38]),
        .I2(uppCL1[39]),
        .O(\uppCL1_reg[37]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1713" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__0 
       (.I0(uppCL1[19]),
        .I1(uppCL1[20]),
        .I2(uppCL1[21]),
        .O(\uppCL1_reg[19]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1717" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__1 
       (.I0(uppCL1[13]),
        .I1(uppCL1[14]),
        .I2(uppCL1[15]),
        .O(\uppCL1_reg[13]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1753" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__10 
       (.I0(lowCL1[13]),
        .I1(lowCL1[14]),
        .I2(lowCL1[15]),
        .O(\lowCL1_reg[13]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1757" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__11 
       (.I0(lowCL1[7]),
        .I1(lowCL1[8]),
        .I2(lowCL1[9]),
        .O(\lowCL1_reg[7]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1761" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__12 
       (.I0(lowCL1[1]),
        .I1(lowCL1[2]),
        .I2(lowCL1[3]),
        .O(\lowCL1_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1721" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__2 
       (.I0(uppCL1[25]),
        .I1(uppCL1[26]),
        .I2(uppCL1[27]),
        .O(\uppCL1_reg[25]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1725" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__3 
       (.I0(lowCL1[43]),
        .I1(lowCL1[44]),
        .I2(lowCL1[45]),
        .O(\lowCL1_reg[43]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1729" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__4 
       (.I0(uppCL1[1]),
        .I1(uppCL1[2]),
        .I2(uppCL1[3]),
        .O(\uppCL1_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1733" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__5 
       (.I0(uppCL1[31]),
        .I1(uppCL1[32]),
        .I2(uppCL1[33]),
        .O(\uppCL1_reg[31]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1737" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__6 
       (.I0(lowCL1[31]),
        .I1(lowCL1[32]),
        .I2(lowCL1[33]),
        .O(\lowCL1_reg[31]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1741" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__7 
       (.I0(lowCL1[25]),
        .I1(lowCL1[26]),
        .I2(lowCL1[27]),
        .O(\lowCL1_reg[25]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1745" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__8 
       (.I0(lowCL1[37]),
        .I1(lowCL1[38]),
        .I2(lowCL1[39]),
        .O(\lowCL1_reg[37]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1749" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[3][5]_i_1__9 
       (.I0(lowCL1[19]),
        .I1(lowCL1[20]),
        .I2(lowCL1[21]),
        .O(\lowCL1_reg[19]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1847" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1 
       (.I0(uppCL1[37]),
        .I1(uppCL1[38]),
        .I2(uppCL1[36]),
        .O(\uppCL1_reg[37]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1855" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__0 
       (.I0(uppCL1[19]),
        .I1(uppCL1[20]),
        .I2(uppCL1[18]),
        .O(\uppCL1_reg[19]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1863" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__1 
       (.I0(uppCL1[13]),
        .I1(uppCL1[14]),
        .I2(uppCL1[12]),
        .O(\uppCL1_reg[13]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1919" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__10 
       (.I0(lowCL1[37]),
        .I1(lowCL1[38]),
        .I2(lowCL1[36]),
        .O(\lowCL1_reg[37]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1927" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__11 
       (.I0(lowCL1[19]),
        .I1(lowCL1[20]),
        .I2(lowCL1[18]),
        .O(\lowCL1_reg[19]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1935" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__12 
       (.I0(lowCL1[13]),
        .I1(lowCL1[14]),
        .I2(lowCL1[12]),
        .O(\lowCL1_reg[13]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1943" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__13 
       (.I0(lowCL1[7]),
        .I1(lowCL1[8]),
        .I2(lowCL1[6]),
        .O(\lowCL1_reg[7]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1951" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__14 
       (.I0(lowCL1[1]),
        .I1(lowCL1[2]),
        .I2(lowCL1[0]),
        .O(\lowCL1_reg[1]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1871" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__2 
       (.I0(uppCL1[25]),
        .I1(uppCL1[26]),
        .I2(uppCL1[24]),
        .O(\uppCL1_reg[25]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1837" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__3 
       (.I0(\uppCL1_reg[45]_0 [0]),
        .I1(\uppCL1_reg[45]_0 [1]),
        .I2(uppCL1[6]),
        .O(\uppCL1_reg[7]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1841" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__4 
       (.I0(\uppCL1_reg[45]_0 [3]),
        .I1(\uppCL1_reg[45]_0 [4]),
        .I2(uppCL1[42]),
        .O(\uppCL1_reg[43]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1879" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__5 
       (.I0(lowCL1[43]),
        .I1(lowCL1[44]),
        .I2(lowCL1[42]),
        .O(\lowCL1_reg[43]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1887" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__6 
       (.I0(uppCL1[1]),
        .I1(uppCL1[2]),
        .I2(uppCL1[0]),
        .O(\uppCL1_reg[1]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1895" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__7 
       (.I0(uppCL1[31]),
        .I1(uppCL1[32]),
        .I2(uppCL1[30]),
        .O(\uppCL1_reg[31]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1903" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__8 
       (.I0(lowCL1[31]),
        .I1(lowCL1[32]),
        .I2(lowCL1[30]),
        .O(\lowCL1_reg[31]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1911" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[3][8]_i_1__9 
       (.I0(lowCL1[25]),
        .I1(lowCL1[26]),
        .I2(lowCL1[24]),
        .O(\lowCL1_reg[25]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2103" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1 
       (.I0(uppCL1[37]),
        .I1(uppCL1[38]),
        .O(\uppCL1_reg[37]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2111" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__0 
       (.I0(uppCL1[19]),
        .I1(uppCL1[20]),
        .O(\uppCL1_reg[19]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2119" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__1 
       (.I0(uppCL1[13]),
        .I1(uppCL1[14]),
        .O(\uppCL1_reg[13]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2191" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__10 
       (.I0(lowCL1[13]),
        .I1(lowCL1[14]),
        .O(\lowCL1_reg[13]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2199" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__11 
       (.I0(lowCL1[7]),
        .I1(lowCL1[8]),
        .O(\lowCL1_reg[7]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2207" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__12 
       (.I0(lowCL1[1]),
        .I1(lowCL1[2]),
        .O(\lowCL1_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2127" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__2 
       (.I0(uppCL1[25]),
        .I1(uppCL1[26]),
        .O(\uppCL1_reg[25]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2135" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__3 
       (.I0(lowCL1[43]),
        .I1(lowCL1[44]),
        .O(\lowCL1_reg[43]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2143" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__4 
       (.I0(uppCL1[1]),
        .I1(uppCL1[2]),
        .O(\uppCL1_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2151" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__5 
       (.I0(uppCL1[31]),
        .I1(uppCL1[32]),
        .O(\uppCL1_reg[31]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2159" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__6 
       (.I0(lowCL1[31]),
        .I1(lowCL1[32]),
        .O(\lowCL1_reg[31]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2167" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__7 
       (.I0(lowCL1[25]),
        .I1(lowCL1[26]),
        .O(\lowCL1_reg[25]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2175" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__8 
       (.I0(lowCL1[37]),
        .I1(lowCL1[38]),
        .O(\lowCL1_reg[37]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2183" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[3][9]_i_1__9 
       (.I0(lowCL1[19]),
        .I1(lowCL1[20]),
        .O(\lowCL1_reg[19]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1710" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1 
       (.I0(uppCL2[39]),
        .I1(uppCL2[38]),
        .I2(uppCL2[37]),
        .O(\uppCL2_reg[39]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1714" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__0 
       (.I0(uppCL2[21]),
        .I1(uppCL2[20]),
        .I2(uppCL2[19]),
        .O(\uppCL2_reg[21]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1718" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__1 
       (.I0(uppCL2[15]),
        .I1(uppCL2[14]),
        .I2(uppCL2[13]),
        .O(\uppCL2_reg[15]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1746" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__10 
       (.I0(lowCL2[39]),
        .I1(lowCL2[38]),
        .I2(lowCL2[37]),
        .O(\lowCL2_reg[39]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1750" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__11 
       (.I0(lowCL2[21]),
        .I1(lowCL2[20]),
        .I2(lowCL2[19]),
        .O(\lowCL2_reg[21]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1754" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__12 
       (.I0(lowCL2[15]),
        .I1(lowCL2[14]),
        .I2(lowCL2[13]),
        .O(\lowCL2_reg[15]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1758" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__13 
       (.I0(lowCL2[9]),
        .I1(lowCL2[8]),
        .I2(lowCL2[7]),
        .O(\lowCL2_reg[9]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1762" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__14 
       (.I0(lowCL2[3]),
        .I1(lowCL2[2]),
        .I2(lowCL2[1]),
        .O(\lowCL2_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1722" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__2 
       (.I0(uppCL2[27]),
        .I1(uppCL2[26]),
        .I2(uppCL2[25]),
        .O(\uppCL2_reg[27]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1766" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [2]),
        .I1(\uppCL2_reg[45]_0 [1]),
        .I2(\uppCL2_reg[45]_0 [0]),
        .O(\uppCL2_reg[9]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1770" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [5]),
        .I1(\uppCL2_reg[45]_0 [4]),
        .I2(\uppCL2_reg[45]_0 [3]),
        .O(\uppCL2_reg[45]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1726" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__5 
       (.I0(lowCL2[45]),
        .I1(lowCL2[44]),
        .I2(lowCL2[43]),
        .O(\lowCL2_reg[45]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1730" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__6 
       (.I0(uppCL2[3]),
        .I1(uppCL2[2]),
        .I2(uppCL2[1]),
        .O(\uppCL2_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1734" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__7 
       (.I0(uppCL2[33]),
        .I1(uppCL2[32]),
        .I2(uppCL2[31]),
        .O(\uppCL2_reg[33]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1738" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__8 
       (.I0(lowCL2[33]),
        .I1(lowCL2[32]),
        .I2(lowCL2[31]),
        .O(\lowCL2_reg[33]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1742" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[4][11]_i_1__9 
       (.I0(lowCL2[27]),
        .I1(lowCL2[26]),
        .I2(lowCL2[25]),
        .O(\lowCL2_reg[27]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2030" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2 
       (.I0(uppCL2[38]),
        .I1(uppCL2[37]),
        .O(\uppCL2_reg[38]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2034" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__0 
       (.I0(uppCL2[20]),
        .I1(uppCL2[19]),
        .O(\uppCL2_reg[20]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2038" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__1 
       (.I0(uppCL2[14]),
        .I1(uppCL2[13]),
        .O(\uppCL2_reg[14]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2074" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__10 
       (.I0(lowCL2[38]),
        .I1(lowCL2[37]),
        .O(\lowCL2_reg[38]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2078" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__11 
       (.I0(lowCL2[20]),
        .I1(lowCL2[19]),
        .O(\lowCL2_reg[20]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2082" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__12 
       (.I0(lowCL2[14]),
        .I1(lowCL2[13]),
        .O(\lowCL2_reg[14]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2086" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__13 
       (.I0(lowCL2[8]),
        .I1(lowCL2[7]),
        .O(\lowCL2_reg[8]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2090" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__14 
       (.I0(lowCL2[2]),
        .I1(lowCL2[1]),
        .O(\lowCL2_reg[2]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2042" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__2 
       (.I0(uppCL2[26]),
        .I1(uppCL2[25]),
        .O(\uppCL2_reg[26]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2046" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__3 
       (.I0(\uppCL2_reg[45]_0 [1]),
        .I1(\uppCL2_reg[45]_0 [0]),
        .O(\uppCL2_reg[8]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2050" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__4 
       (.I0(\uppCL2_reg[45]_0 [4]),
        .I1(\uppCL2_reg[45]_0 [3]),
        .O(\uppCL2_reg[44]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2054" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__5 
       (.I0(lowCL2[44]),
        .I1(lowCL2[43]),
        .O(\lowCL2_reg[44]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2058" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__6 
       (.I0(uppCL2[2]),
        .I1(uppCL2[1]),
        .O(\uppCL2_reg[2]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2062" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__7 
       (.I0(uppCL2[32]),
        .I1(uppCL2[31]),
        .O(\uppCL2_reg[32]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2066" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__8 
       (.I0(lowCL2[32]),
        .I1(lowCL2[31]),
        .O(\lowCL2_reg[32]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2070" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[4][11]_i_2__9 
       (.I0(lowCL2[26]),
        .I1(lowCL2[25]),
        .O(\lowCL2_reg[26]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1600" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1 
       (.I0(uppCL2[37]),
        .I1(uppCL2[38]),
        .I2(uppCL2[39]),
        .I3(uppCL2[36]),
        .O(\uppCL2_reg[38]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1608" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__0 
       (.I0(uppCL2[19]),
        .I1(uppCL2[20]),
        .I2(uppCL2[21]),
        .I3(uppCL2[18]),
        .O(\uppCL2_reg[20]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1616" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__1 
       (.I0(uppCL2[13]),
        .I1(uppCL2[14]),
        .I2(uppCL2[15]),
        .I3(uppCL2[12]),
        .O(\uppCL2_reg[14]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1688" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__10 
       (.I0(lowCL2[13]),
        .I1(lowCL2[14]),
        .I2(lowCL2[15]),
        .I3(lowCL2[12]),
        .O(\lowCL2_reg[14]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1696" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__11 
       (.I0(lowCL2[7]),
        .I1(lowCL2[8]),
        .I2(lowCL2[9]),
        .I3(lowCL2[6]),
        .O(\lowCL2_reg[8]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1704" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__12 
       (.I0(lowCL2[1]),
        .I1(lowCL2[2]),
        .I2(lowCL2[3]),
        .I3(lowCL2[0]),
        .O(\lowCL2_reg[2]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1624" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__2 
       (.I0(uppCL2[25]),
        .I1(uppCL2[26]),
        .I2(uppCL2[27]),
        .I3(uppCL2[24]),
        .O(\uppCL2_reg[26]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1632" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__3 
       (.I0(lowCL2[43]),
        .I1(lowCL2[44]),
        .I2(lowCL2[45]),
        .I3(lowCL2[42]),
        .O(\lowCL2_reg[44]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1640" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__4 
       (.I0(uppCL2[1]),
        .I1(uppCL2[2]),
        .I2(uppCL2[3]),
        .I3(uppCL2[0]),
        .O(\uppCL2_reg[2]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1648" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__5 
       (.I0(uppCL2[31]),
        .I1(uppCL2[32]),
        .I2(uppCL2[33]),
        .I3(uppCL2[30]),
        .O(\uppCL2_reg[32]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1656" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__6 
       (.I0(lowCL2[31]),
        .I1(lowCL2[32]),
        .I2(lowCL2[33]),
        .I3(lowCL2[30]),
        .O(\lowCL2_reg[32]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1664" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__7 
       (.I0(lowCL2[25]),
        .I1(lowCL2[26]),
        .I2(lowCL2[27]),
        .I3(lowCL2[24]),
        .O(\lowCL2_reg[26]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1672" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__8 
       (.I0(lowCL2[37]),
        .I1(lowCL2[38]),
        .I2(lowCL2[39]),
        .I3(lowCL2[36]),
        .O(\lowCL2_reg[38]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1680" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[4][2]_i_1__9 
       (.I0(lowCL2[19]),
        .I1(lowCL2[20]),
        .I2(lowCL2[21]),
        .I3(lowCL2[18]),
        .O(\lowCL2_reg[20]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1848" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1 
       (.I0(uppCL2[37]),
        .I1(uppCL2[38]),
        .I2(uppCL2[39]),
        .O(\uppCL2_reg[38]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1856" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__0 
       (.I0(uppCL2[19]),
        .I1(uppCL2[20]),
        .I2(uppCL2[21]),
        .O(\uppCL2_reg[20]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1864" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__1 
       (.I0(uppCL2[13]),
        .I1(uppCL2[14]),
        .I2(uppCL2[15]),
        .O(\uppCL2_reg[14]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1936" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__10 
       (.I0(lowCL2[13]),
        .I1(lowCL2[14]),
        .I2(lowCL2[15]),
        .O(\lowCL2_reg[14]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1944" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__11 
       (.I0(lowCL2[7]),
        .I1(lowCL2[8]),
        .I2(lowCL2[9]),
        .O(\lowCL2_reg[8]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1952" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__12 
       (.I0(lowCL2[1]),
        .I1(lowCL2[2]),
        .I2(lowCL2[3]),
        .O(\lowCL2_reg[2]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1872" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__2 
       (.I0(uppCL2[25]),
        .I1(uppCL2[26]),
        .I2(uppCL2[27]),
        .O(\uppCL2_reg[26]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1880" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__3 
       (.I0(lowCL2[43]),
        .I1(lowCL2[44]),
        .I2(lowCL2[45]),
        .O(\lowCL2_reg[44]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1888" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__4 
       (.I0(uppCL2[1]),
        .I1(uppCL2[2]),
        .I2(uppCL2[3]),
        .O(\uppCL2_reg[2]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1896" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__5 
       (.I0(uppCL2[31]),
        .I1(uppCL2[32]),
        .I2(uppCL2[33]),
        .O(\uppCL2_reg[32]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1904" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__6 
       (.I0(lowCL2[31]),
        .I1(lowCL2[32]),
        .I2(lowCL2[33]),
        .O(\lowCL2_reg[32]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1912" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__7 
       (.I0(lowCL2[25]),
        .I1(lowCL2[26]),
        .I2(lowCL2[27]),
        .O(\lowCL2_reg[26]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1920" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__8 
       (.I0(lowCL2[37]),
        .I1(lowCL2[38]),
        .I2(lowCL2[39]),
        .O(\lowCL2_reg[38]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1928" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[4][3]_i_1__9 
       (.I0(lowCL2[19]),
        .I1(lowCL2[20]),
        .I2(lowCL2[21]),
        .O(\lowCL2_reg[20]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2104" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1 
       (.I0(uppCL2[38]),
        .I1(uppCL2[39]),
        .O(\uppCL2_reg[38]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2112" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__0 
       (.I0(uppCL2[20]),
        .I1(uppCL2[21]),
        .O(\uppCL2_reg[20]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2120" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__1 
       (.I0(uppCL2[14]),
        .I1(uppCL2[15]),
        .O(\uppCL2_reg[14]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2192" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__10 
       (.I0(lowCL2[14]),
        .I1(lowCL2[15]),
        .O(\lowCL2_reg[14]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2200" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__11 
       (.I0(lowCL2[8]),
        .I1(lowCL2[9]),
        .O(\lowCL2_reg[8]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2208" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__12 
       (.I0(lowCL2[2]),
        .I1(lowCL2[3]),
        .O(\lowCL2_reg[2]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2128" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__2 
       (.I0(uppCL2[26]),
        .I1(uppCL2[27]),
        .O(\uppCL2_reg[26]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2136" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__3 
       (.I0(lowCL2[44]),
        .I1(lowCL2[45]),
        .O(\lowCL2_reg[44]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2144" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__4 
       (.I0(uppCL2[2]),
        .I1(uppCL2[3]),
        .O(\uppCL2_reg[2]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2152" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__5 
       (.I0(uppCL2[32]),
        .I1(uppCL2[33]),
        .O(\uppCL2_reg[32]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2160" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__6 
       (.I0(lowCL2[32]),
        .I1(lowCL2[33]),
        .O(\lowCL2_reg[32]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2168" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__7 
       (.I0(lowCL2[26]),
        .I1(lowCL2[27]),
        .O(\lowCL2_reg[26]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2176" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__8 
       (.I0(lowCL2[38]),
        .I1(lowCL2[39]),
        .O(\lowCL2_reg[38]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2184" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[4][9]_i_1__9 
       (.I0(lowCL2[20]),
        .I1(lowCL2[21]),
        .O(\lowCL2_reg[20]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1601" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1 
       (.I0(uppCL2[37]),
        .I1(uppCL2[38]),
        .I2(uppCL2[39]),
        .I3(uppCL2[36]),
        .O(\uppCL2_reg[37]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1609" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__0 
       (.I0(uppCL2[19]),
        .I1(uppCL2[20]),
        .I2(uppCL2[21]),
        .I3(uppCL2[18]),
        .O(\uppCL2_reg[19]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1617" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__1 
       (.I0(uppCL2[13]),
        .I1(uppCL2[14]),
        .I2(uppCL2[15]),
        .I3(uppCL2[12]),
        .O(\uppCL2_reg[13]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1673" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__10 
       (.I0(lowCL2[37]),
        .I1(lowCL2[38]),
        .I2(lowCL2[39]),
        .I3(lowCL2[36]),
        .O(\lowCL2_reg[37]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1681" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__11 
       (.I0(lowCL2[19]),
        .I1(lowCL2[20]),
        .I2(lowCL2[21]),
        .I3(lowCL2[18]),
        .O(\lowCL2_reg[19]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1689" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__12 
       (.I0(lowCL2[13]),
        .I1(lowCL2[14]),
        .I2(lowCL2[15]),
        .I3(lowCL2[12]),
        .O(\lowCL2_reg[13]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1697" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__13 
       (.I0(lowCL2[7]),
        .I1(lowCL2[8]),
        .I2(lowCL2[9]),
        .I3(lowCL2[6]),
        .O(\lowCL2_reg[7]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1705" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__14 
       (.I0(lowCL2[1]),
        .I1(lowCL2[2]),
        .I2(lowCL2[3]),
        .I3(lowCL2[0]),
        .O(\lowCL2_reg[1]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1625" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__2 
       (.I0(uppCL2[25]),
        .I1(uppCL2[26]),
        .I2(uppCL2[27]),
        .I3(uppCL2[24]),
        .O(\uppCL2_reg[25]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1584" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [0]),
        .I1(\uppCL2_reg[45]_0 [1]),
        .I2(\uppCL2_reg[45]_0 [2]),
        .I3(uppCL2[6]),
        .O(\uppCL2_reg[7]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1592" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [3]),
        .I1(\uppCL2_reg[45]_0 [4]),
        .I2(\uppCL2_reg[45]_0 [5]),
        .I3(uppCL2[42]),
        .O(\uppCL2_reg[43]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1633" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__5 
       (.I0(lowCL2[43]),
        .I1(lowCL2[44]),
        .I2(lowCL2[45]),
        .I3(lowCL2[42]),
        .O(\lowCL2_reg[43]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1641" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__6 
       (.I0(uppCL2[1]),
        .I1(uppCL2[2]),
        .I2(uppCL2[3]),
        .I3(uppCL2[0]),
        .O(\uppCL2_reg[1]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1649" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__7 
       (.I0(uppCL2[31]),
        .I1(uppCL2[32]),
        .I2(uppCL2[33]),
        .I3(uppCL2[30]),
        .O(\uppCL2_reg[31]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1657" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__8 
       (.I0(lowCL2[31]),
        .I1(lowCL2[32]),
        .I2(lowCL2[33]),
        .I3(lowCL2[30]),
        .O(\lowCL2_reg[31]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1665" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[5][10]_i_1__9 
       (.I0(lowCL2[25]),
        .I1(lowCL2[26]),
        .I2(lowCL2[27]),
        .I3(lowCL2[24]),
        .O(\lowCL2_reg[25]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1848" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1 
       (.I0(uppCL2[37]),
        .I1(uppCL2[38]),
        .I2(uppCL2[39]),
        .O(\uppCL2_reg[37]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1856" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__0 
       (.I0(uppCL2[19]),
        .I1(uppCL2[20]),
        .I2(uppCL2[21]),
        .O(\uppCL2_reg[19]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1864" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__1 
       (.I0(uppCL2[13]),
        .I1(uppCL2[14]),
        .I2(uppCL2[15]),
        .O(\uppCL2_reg[13]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1936" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__10 
       (.I0(lowCL2[13]),
        .I1(lowCL2[14]),
        .I2(lowCL2[15]),
        .O(\lowCL2_reg[13]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1944" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__11 
       (.I0(lowCL2[7]),
        .I1(lowCL2[8]),
        .I2(lowCL2[9]),
        .O(\lowCL2_reg[7]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1952" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__12 
       (.I0(lowCL2[1]),
        .I1(lowCL2[2]),
        .I2(lowCL2[3]),
        .O(\lowCL2_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1872" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__2 
       (.I0(uppCL2[25]),
        .I1(uppCL2[26]),
        .I2(uppCL2[27]),
        .O(\uppCL2_reg[25]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1880" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__3 
       (.I0(lowCL2[43]),
        .I1(lowCL2[44]),
        .I2(lowCL2[45]),
        .O(\lowCL2_reg[43]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1888" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__4 
       (.I0(uppCL2[1]),
        .I1(uppCL2[2]),
        .I2(uppCL2[3]),
        .O(\uppCL2_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1896" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__5 
       (.I0(uppCL2[31]),
        .I1(uppCL2[32]),
        .I2(uppCL2[33]),
        .O(\uppCL2_reg[31]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1904" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__6 
       (.I0(lowCL2[31]),
        .I1(lowCL2[32]),
        .I2(lowCL2[33]),
        .O(\lowCL2_reg[31]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1912" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__7 
       (.I0(lowCL2[25]),
        .I1(lowCL2[26]),
        .I2(lowCL2[27]),
        .O(\lowCL2_reg[25]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1920" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__8 
       (.I0(lowCL2[37]),
        .I1(lowCL2[38]),
        .I2(lowCL2[39]),
        .O(\lowCL2_reg[37]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1928" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[5][11]_i_1__9 
       (.I0(lowCL2[19]),
        .I1(lowCL2[20]),
        .I2(lowCL2[21]),
        .O(\lowCL2_reg[19]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1600" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1 
       (.I0(uppCL2[37]),
        .I1(uppCL2[38]),
        .I2(uppCL2[39]),
        .I3(uppCL2[36]),
        .O(\uppCL2_reg[37]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1608" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__0 
       (.I0(uppCL2[19]),
        .I1(uppCL2[20]),
        .I2(uppCL2[21]),
        .I3(uppCL2[18]),
        .O(\uppCL2_reg[19]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1616" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__1 
       (.I0(uppCL2[13]),
        .I1(uppCL2[14]),
        .I2(uppCL2[15]),
        .I3(uppCL2[12]),
        .O(\uppCL2_reg[13]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1672" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__10 
       (.I0(lowCL2[37]),
        .I1(lowCL2[38]),
        .I2(lowCL2[39]),
        .I3(lowCL2[36]),
        .O(\lowCL2_reg[37]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1680" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__11 
       (.I0(lowCL2[19]),
        .I1(lowCL2[20]),
        .I2(lowCL2[21]),
        .I3(lowCL2[18]),
        .O(\lowCL2_reg[19]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1688" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__12 
       (.I0(lowCL2[13]),
        .I1(lowCL2[14]),
        .I2(lowCL2[15]),
        .I3(lowCL2[12]),
        .O(\lowCL2_reg[13]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1696" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__13 
       (.I0(lowCL2[7]),
        .I1(lowCL2[8]),
        .I2(lowCL2[9]),
        .I3(lowCL2[6]),
        .O(\lowCL2_reg[7]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1704" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__14 
       (.I0(lowCL2[1]),
        .I1(lowCL2[2]),
        .I2(lowCL2[3]),
        .I3(lowCL2[0]),
        .O(\lowCL2_reg[1]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1624" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__2 
       (.I0(uppCL2[25]),
        .I1(uppCL2[26]),
        .I2(uppCL2[27]),
        .I3(uppCL2[24]),
        .O(\uppCL2_reg[25]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1584" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [0]),
        .I1(\uppCL2_reg[45]_0 [1]),
        .I2(\uppCL2_reg[45]_0 [2]),
        .I3(uppCL2[6]),
        .O(\uppCL2_reg[7]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1592" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [3]),
        .I1(\uppCL2_reg[45]_0 [4]),
        .I2(\uppCL2_reg[45]_0 [5]),
        .I3(uppCL2[42]),
        .O(\uppCL2_reg[43]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1632" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__5 
       (.I0(lowCL2[43]),
        .I1(lowCL2[44]),
        .I2(lowCL2[45]),
        .I3(lowCL2[42]),
        .O(\lowCL2_reg[43]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1640" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__6 
       (.I0(uppCL2[1]),
        .I1(uppCL2[2]),
        .I2(uppCL2[3]),
        .I3(uppCL2[0]),
        .O(\uppCL2_reg[1]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1648" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__7 
       (.I0(uppCL2[31]),
        .I1(uppCL2[32]),
        .I2(uppCL2[33]),
        .I3(uppCL2[30]),
        .O(\uppCL2_reg[31]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1656" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__8 
       (.I0(lowCL2[31]),
        .I1(lowCL2[32]),
        .I2(lowCL2[33]),
        .I3(lowCL2[30]),
        .O(\lowCL2_reg[31]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1664" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[5][12]_i_1__9 
       (.I0(lowCL2[25]),
        .I1(lowCL2[26]),
        .I2(lowCL2[27]),
        .I3(lowCL2[24]),
        .O(\lowCL2_reg[25]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1966" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1 
       (.I0(uppCL2[38]),
        .I1(uppCL2[37]),
        .O(\uppCL2_reg[38]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1970" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__0 
       (.I0(uppCL2[20]),
        .I1(uppCL2[19]),
        .O(\uppCL2_reg[20]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1974" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__1 
       (.I0(uppCL2[14]),
        .I1(uppCL2[13]),
        .O(\uppCL2_reg[14]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2010" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__10 
       (.I0(lowCL2[38]),
        .I1(lowCL2[37]),
        .O(\lowCL2_reg[38]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2014" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__11 
       (.I0(lowCL2[20]),
        .I1(lowCL2[19]),
        .O(\lowCL2_reg[20]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2018" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__12 
       (.I0(lowCL2[14]),
        .I1(lowCL2[13]),
        .O(\lowCL2_reg[14]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2022" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__13 
       (.I0(lowCL2[8]),
        .I1(lowCL2[7]),
        .O(\lowCL2_reg[8]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2026" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__14 
       (.I0(lowCL2[2]),
        .I1(lowCL2[1]),
        .O(\lowCL2_reg[2]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1978" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__2 
       (.I0(uppCL2[26]),
        .I1(uppCL2[25]),
        .O(\uppCL2_reg[26]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1958" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [1]),
        .I1(\uppCL2_reg[45]_0 [0]),
        .O(\uppCL2_reg[8]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1962" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [4]),
        .I1(\uppCL2_reg[45]_0 [3]),
        .O(\uppCL2_reg[44]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1990" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__5 
       (.I0(lowCL2[44]),
        .I1(lowCL2[43]),
        .O(\lowCL2_reg[44]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1994" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__6 
       (.I0(uppCL2[2]),
        .I1(uppCL2[1]),
        .O(\uppCL2_reg[2]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1998" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__7 
       (.I0(uppCL2[32]),
        .I1(uppCL2[31]),
        .O(\uppCL2_reg[32]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2002" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__8 
       (.I0(lowCL2[32]),
        .I1(lowCL2[31]),
        .O(\lowCL2_reg[32]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2006" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[5][13]_i_1__9 
       (.I0(lowCL2[26]),
        .I1(lowCL2[25]),
        .O(\lowCL2_reg[26]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1782" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1 
       (.I0(uppCL2[37]),
        .I1(uppCL2[38]),
        .I2(uppCL2[36]),
        .O(\uppCL2_reg[37]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1786" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__0 
       (.I0(uppCL2[19]),
        .I1(uppCL2[20]),
        .I2(uppCL2[18]),
        .O(\uppCL2_reg[19]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1790" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__1 
       (.I0(uppCL2[13]),
        .I1(uppCL2[14]),
        .I2(uppCL2[12]),
        .O(\uppCL2_reg[13]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1818" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__10 
       (.I0(lowCL2[37]),
        .I1(lowCL2[38]),
        .I2(lowCL2[36]),
        .O(\lowCL2_reg[37]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1822" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__11 
       (.I0(lowCL2[19]),
        .I1(lowCL2[20]),
        .I2(lowCL2[18]),
        .O(\lowCL2_reg[19]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1826" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__12 
       (.I0(lowCL2[13]),
        .I1(lowCL2[14]),
        .I2(lowCL2[12]),
        .O(\lowCL2_reg[13]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1830" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__13 
       (.I0(lowCL2[7]),
        .I1(lowCL2[8]),
        .I2(lowCL2[6]),
        .O(\lowCL2_reg[7]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1834" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__14 
       (.I0(lowCL2[1]),
        .I1(lowCL2[2]),
        .I2(lowCL2[0]),
        .O(\lowCL2_reg[1]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1794" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__2 
       (.I0(uppCL2[25]),
        .I1(uppCL2[26]),
        .I2(uppCL2[24]),
        .O(\uppCL2_reg[25]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1774" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [0]),
        .I1(\uppCL2_reg[45]_0 [1]),
        .I2(uppCL2[6]),
        .O(\uppCL2_reg[7]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1778" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [3]),
        .I1(\uppCL2_reg[45]_0 [4]),
        .I2(uppCL2[42]),
        .O(\uppCL2_reg[43]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1798" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__5 
       (.I0(lowCL2[43]),
        .I1(lowCL2[44]),
        .I2(lowCL2[42]),
        .O(\lowCL2_reg[43]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1802" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__6 
       (.I0(uppCL2[1]),
        .I1(uppCL2[2]),
        .I2(uppCL2[0]),
        .O(\uppCL2_reg[1]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1806" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__7 
       (.I0(uppCL2[31]),
        .I1(uppCL2[32]),
        .I2(uppCL2[30]),
        .O(\uppCL2_reg[31]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1810" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__8 
       (.I0(lowCL2[31]),
        .I1(lowCL2[32]),
        .I2(lowCL2[30]),
        .O(\lowCL2_reg[31]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1814" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[5][14]_i_1__9 
       (.I0(lowCL2[25]),
        .I1(lowCL2[26]),
        .I2(lowCL2[24]),
        .O(\lowCL2_reg[25]_4 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1 
       (.I0(uppCL2[38]),
        .O(\uppCL2_reg[38]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__0 
       (.I0(uppCL2[26]),
        .O(\uppCL2_reg[26]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__1 
       (.I0(uppCL2[20]),
        .O(\uppCL2_reg[20]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__10 
       (.I0(lowCL2[26]),
        .O(\lowCL2_reg[26]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__11 
       (.I0(lowCL2[20]),
        .O(\lowCL2_reg[20]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__12 
       (.I0(lowCL2[14]),
        .O(\lowCL2_reg[14]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__13 
       (.I0(lowCL2[8]),
        .O(\lowCL2_reg[8]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__14 
       (.I0(lowCL2[2]),
        .O(\lowCL2_reg[2]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__2 
       (.I0(uppCL2[14]),
        .O(\uppCL2_reg[14]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair2218" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [4]),
        .O(\uppCL2_reg[44]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair2214" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [1]),
        .O(\uppCL2_reg[8]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__5 
       (.I0(lowCL2[44]),
        .O(\lowCL2_reg[44]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__6 
       (.I0(uppCL2[32]),
        .O(\uppCL2_reg[32]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__7 
       (.I0(uppCL2[2]),
        .O(\uppCL2_reg[2]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__8 
       (.I0(lowCL2[38]),
        .O(\lowCL2_reg[38]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[5][15]_i_1__9 
       (.I0(lowCL2[32]),
        .O(\lowCL2_reg[32]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1849" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1 
       (.I0(uppCL2[37]),
        .I1(uppCL2[38]),
        .I2(uppCL2[36]),
        .O(\uppCL2_reg[37]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1857" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__0 
       (.I0(uppCL2[19]),
        .I1(uppCL2[20]),
        .I2(uppCL2[18]),
        .O(\uppCL2_reg[19]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1865" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__1 
       (.I0(uppCL2[13]),
        .I1(uppCL2[14]),
        .I2(uppCL2[12]),
        .O(\uppCL2_reg[13]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1921" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__10 
       (.I0(lowCL2[37]),
        .I1(lowCL2[38]),
        .I2(lowCL2[36]),
        .O(\lowCL2_reg[37]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1929" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__11 
       (.I0(lowCL2[19]),
        .I1(lowCL2[20]),
        .I2(lowCL2[18]),
        .O(\lowCL2_reg[19]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1937" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__12 
       (.I0(lowCL2[13]),
        .I1(lowCL2[14]),
        .I2(lowCL2[12]),
        .O(\lowCL2_reg[13]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1945" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__13 
       (.I0(lowCL2[7]),
        .I1(lowCL2[8]),
        .I2(lowCL2[6]),
        .O(\lowCL2_reg[7]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1953" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__14 
       (.I0(lowCL2[1]),
        .I1(lowCL2[2]),
        .I2(lowCL2[0]),
        .O(\lowCL2_reg[1]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1873" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__2 
       (.I0(uppCL2[25]),
        .I1(uppCL2[26]),
        .I2(uppCL2[24]),
        .O(\uppCL2_reg[25]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1838" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [0]),
        .I1(\uppCL2_reg[45]_0 [1]),
        .I2(uppCL2[6]),
        .O(\uppCL2_reg[7]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1842" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [3]),
        .I1(\uppCL2_reg[45]_0 [4]),
        .I2(uppCL2[42]),
        .O(\uppCL2_reg[43]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1881" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__5 
       (.I0(lowCL2[43]),
        .I1(lowCL2[44]),
        .I2(lowCL2[42]),
        .O(\lowCL2_reg[43]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1889" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__6 
       (.I0(uppCL2[1]),
        .I1(uppCL2[2]),
        .I2(uppCL2[0]),
        .O(\uppCL2_reg[1]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1897" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__7 
       (.I0(uppCL2[31]),
        .I1(uppCL2[32]),
        .I2(uppCL2[30]),
        .O(\uppCL2_reg[31]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1905" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__8 
       (.I0(lowCL2[31]),
        .I1(lowCL2[32]),
        .I2(lowCL2[30]),
        .O(\lowCL2_reg[31]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1913" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[5][16]_i_1__9 
       (.I0(lowCL2[25]),
        .I1(lowCL2[26]),
        .I2(lowCL2[24]),
        .O(\lowCL2_reg[25]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair2105" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1 
       (.I0(uppCL2[38]),
        .I1(uppCL2[37]),
        .O(\uppCL2_reg[38]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2113" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__0 
       (.I0(uppCL2[20]),
        .I1(uppCL2[19]),
        .O(\uppCL2_reg[20]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2121" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__1 
       (.I0(uppCL2[14]),
        .I1(uppCL2[13]),
        .O(\uppCL2_reg[14]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2177" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__10 
       (.I0(lowCL2[38]),
        .I1(lowCL2[37]),
        .O(\lowCL2_reg[38]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2185" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__11 
       (.I0(lowCL2[20]),
        .I1(lowCL2[19]),
        .O(\lowCL2_reg[20]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2193" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__12 
       (.I0(lowCL2[14]),
        .I1(lowCL2[13]),
        .O(\lowCL2_reg[14]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2201" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__13 
       (.I0(lowCL2[8]),
        .I1(lowCL2[7]),
        .O(\lowCL2_reg[8]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2209" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__14 
       (.I0(lowCL2[2]),
        .I1(lowCL2[1]),
        .O(\lowCL2_reg[2]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2129" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__2 
       (.I0(uppCL2[26]),
        .I1(uppCL2[25]),
        .O(\uppCL2_reg[26]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2046" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [1]),
        .I1(\uppCL2_reg[45]_0 [0]),
        .O(\uppCL2_reg[8]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2050" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [4]),
        .I1(\uppCL2_reg[45]_0 [3]),
        .O(\uppCL2_reg[44]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2137" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__5 
       (.I0(lowCL2[44]),
        .I1(lowCL2[43]),
        .O(\lowCL2_reg[44]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2145" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__6 
       (.I0(uppCL2[2]),
        .I1(uppCL2[1]),
        .O(\uppCL2_reg[2]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2153" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__7 
       (.I0(uppCL2[32]),
        .I1(uppCL2[31]),
        .O(\uppCL2_reg[32]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2161" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__8 
       (.I0(lowCL2[32]),
        .I1(lowCL2[31]),
        .O(\lowCL2_reg[32]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2169" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[5][17]_i_1__9 
       (.I0(lowCL2[26]),
        .I1(lowCL2[25]),
        .O(\lowCL2_reg[26]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1782" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1 
       (.I0(uppCL2[38]),
        .I1(uppCL2[36]),
        .I2(uppCL2[37]),
        .O(\uppCL2_reg[38]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1786" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__0 
       (.I0(uppCL2[20]),
        .I1(uppCL2[18]),
        .I2(uppCL2[19]),
        .O(\uppCL2_reg[20]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1790" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__1 
       (.I0(uppCL2[14]),
        .I1(uppCL2[12]),
        .I2(uppCL2[13]),
        .O(\uppCL2_reg[14]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1818" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__10 
       (.I0(lowCL2[38]),
        .I1(lowCL2[36]),
        .I2(lowCL2[37]),
        .O(\lowCL2_reg[38]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1822" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__11 
       (.I0(lowCL2[20]),
        .I1(lowCL2[18]),
        .I2(lowCL2[19]),
        .O(\lowCL2_reg[20]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1826" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__12 
       (.I0(lowCL2[14]),
        .I1(lowCL2[12]),
        .I2(lowCL2[13]),
        .O(\lowCL2_reg[14]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1830" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__13 
       (.I0(lowCL2[8]),
        .I1(lowCL2[6]),
        .I2(lowCL2[7]),
        .O(\lowCL2_reg[8]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1834" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__14 
       (.I0(lowCL2[2]),
        .I1(lowCL2[0]),
        .I2(lowCL2[1]),
        .O(\lowCL2_reg[2]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1794" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__2 
       (.I0(uppCL2[26]),
        .I1(uppCL2[24]),
        .I2(uppCL2[25]),
        .O(\uppCL2_reg[26]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1774" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [1]),
        .I1(uppCL2[6]),
        .I2(\uppCL2_reg[45]_0 [0]),
        .O(\uppCL2_reg[8]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1778" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [4]),
        .I1(uppCL2[42]),
        .I2(\uppCL2_reg[45]_0 [3]),
        .O(\uppCL2_reg[44]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1798" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__5 
       (.I0(lowCL2[44]),
        .I1(lowCL2[42]),
        .I2(lowCL2[43]),
        .O(\lowCL2_reg[44]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1802" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__6 
       (.I0(uppCL2[2]),
        .I1(uppCL2[0]),
        .I2(uppCL2[1]),
        .O(\uppCL2_reg[2]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1806" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__7 
       (.I0(uppCL2[32]),
        .I1(uppCL2[30]),
        .I2(uppCL2[31]),
        .O(\uppCL2_reg[32]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1810" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__8 
       (.I0(lowCL2[32]),
        .I1(lowCL2[30]),
        .I2(lowCL2[31]),
        .O(\lowCL2_reg[32]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1814" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[5][18]_i_1__9 
       (.I0(lowCL2[26]),
        .I1(lowCL2[24]),
        .I2(lowCL2[25]),
        .O(\lowCL2_reg[26]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2030" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1 
       (.I0(uppCL2[38]),
        .I1(uppCL2[37]),
        .O(\uppCL2_reg[38]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2034" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__0 
       (.I0(uppCL2[20]),
        .I1(uppCL2[19]),
        .O(\uppCL2_reg[20]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2038" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__1 
       (.I0(uppCL2[14]),
        .I1(uppCL2[13]),
        .O(\uppCL2_reg[14]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2074" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__10 
       (.I0(lowCL2[38]),
        .I1(lowCL2[37]),
        .O(\lowCL2_reg[38]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2078" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__11 
       (.I0(lowCL2[20]),
        .I1(lowCL2[19]),
        .O(\lowCL2_reg[20]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2082" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__12 
       (.I0(lowCL2[14]),
        .I1(lowCL2[13]),
        .O(\lowCL2_reg[14]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2086" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__13 
       (.I0(lowCL2[8]),
        .I1(lowCL2[7]),
        .O(\lowCL2_reg[8]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2090" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__14 
       (.I0(lowCL2[2]),
        .I1(lowCL2[1]),
        .O(\lowCL2_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2042" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__2 
       (.I0(uppCL2[26]),
        .I1(uppCL2[25]),
        .O(\uppCL2_reg[26]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1982" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [1]),
        .I1(\uppCL2_reg[45]_0 [0]),
        .O(\uppCL2_reg[8]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1986" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [4]),
        .I1(\uppCL2_reg[45]_0 [3]),
        .O(\uppCL2_reg[44]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2054" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__5 
       (.I0(lowCL2[44]),
        .I1(lowCL2[43]),
        .O(\lowCL2_reg[44]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2058" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__6 
       (.I0(uppCL2[2]),
        .I1(uppCL2[1]),
        .O(\uppCL2_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2062" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__7 
       (.I0(uppCL2[32]),
        .I1(uppCL2[31]),
        .O(\uppCL2_reg[32]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2066" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__8 
       (.I0(lowCL2[32]),
        .I1(lowCL2[31]),
        .O(\lowCL2_reg[32]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2070" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[5][1]_i_1__9 
       (.I0(lowCL2[26]),
        .I1(lowCL2[25]),
        .O(\lowCL2_reg[26]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1601" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1 
       (.I0(uppCL2[37]),
        .I1(uppCL2[38]),
        .I2(uppCL2[39]),
        .I3(uppCL2[36]),
        .O(\uppCL2_reg[37]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1609" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__0 
       (.I0(uppCL2[19]),
        .I1(uppCL2[20]),
        .I2(uppCL2[21]),
        .I3(uppCL2[18]),
        .O(\uppCL2_reg[19]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1617" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__1 
       (.I0(uppCL2[13]),
        .I1(uppCL2[14]),
        .I2(uppCL2[15]),
        .I3(uppCL2[12]),
        .O(\uppCL2_reg[13]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1673" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__10 
       (.I0(lowCL2[37]),
        .I1(lowCL2[38]),
        .I2(lowCL2[39]),
        .I3(lowCL2[36]),
        .O(\lowCL2_reg[37]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1681" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__11 
       (.I0(lowCL2[19]),
        .I1(lowCL2[20]),
        .I2(lowCL2[21]),
        .I3(lowCL2[18]),
        .O(\lowCL2_reg[19]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1689" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__12 
       (.I0(lowCL2[13]),
        .I1(lowCL2[14]),
        .I2(lowCL2[15]),
        .I3(lowCL2[12]),
        .O(\lowCL2_reg[13]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1697" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__13 
       (.I0(lowCL2[7]),
        .I1(lowCL2[8]),
        .I2(lowCL2[9]),
        .I3(lowCL2[6]),
        .O(\lowCL2_reg[7]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1705" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__14 
       (.I0(lowCL2[1]),
        .I1(lowCL2[2]),
        .I2(lowCL2[3]),
        .I3(lowCL2[0]),
        .O(\lowCL2_reg[1]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1625" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__2 
       (.I0(uppCL2[25]),
        .I1(uppCL2[26]),
        .I2(uppCL2[27]),
        .I3(uppCL2[24]),
        .O(\uppCL2_reg[25]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1585" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [0]),
        .I1(\uppCL2_reg[45]_0 [1]),
        .I2(\uppCL2_reg[45]_0 [2]),
        .I3(uppCL2[6]),
        .O(\uppCL2_reg[7]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1593" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [3]),
        .I1(\uppCL2_reg[45]_0 [4]),
        .I2(\uppCL2_reg[45]_0 [5]),
        .I3(uppCL2[42]),
        .O(\uppCL2_reg[43]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1633" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__5 
       (.I0(lowCL2[43]),
        .I1(lowCL2[44]),
        .I2(lowCL2[45]),
        .I3(lowCL2[42]),
        .O(\lowCL2_reg[43]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1641" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__6 
       (.I0(uppCL2[1]),
        .I1(uppCL2[2]),
        .I2(uppCL2[3]),
        .I3(uppCL2[0]),
        .O(\uppCL2_reg[1]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1649" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__7 
       (.I0(uppCL2[31]),
        .I1(uppCL2[32]),
        .I2(uppCL2[33]),
        .I3(uppCL2[30]),
        .O(\uppCL2_reg[31]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1657" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__8 
       (.I0(lowCL2[31]),
        .I1(lowCL2[32]),
        .I2(lowCL2[33]),
        .I3(lowCL2[30]),
        .O(\lowCL2_reg[31]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1665" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[5][2]_i_1__9 
       (.I0(lowCL2[25]),
        .I1(lowCL2[26]),
        .I2(lowCL2[27]),
        .I3(lowCL2[24]),
        .O(\lowCL2_reg[25]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair2104" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1 
       (.I0(uppCL2[38]),
        .I1(uppCL2[39]),
        .O(\uppCL2_reg[38]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2112" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__0 
       (.I0(uppCL2[20]),
        .I1(uppCL2[21]),
        .O(\uppCL2_reg[20]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2120" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__1 
       (.I0(uppCL2[14]),
        .I1(uppCL2[15]),
        .O(\uppCL2_reg[14]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2176" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__10 
       (.I0(lowCL2[38]),
        .I1(lowCL2[39]),
        .O(\lowCL2_reg[38]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2184" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__11 
       (.I0(lowCL2[20]),
        .I1(lowCL2[21]),
        .O(\lowCL2_reg[20]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2192" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__12 
       (.I0(lowCL2[14]),
        .I1(lowCL2[15]),
        .O(\lowCL2_reg[14]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2200" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__13 
       (.I0(lowCL2[8]),
        .I1(lowCL2[9]),
        .O(\lowCL2_reg[8]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2208" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__14 
       (.I0(lowCL2[2]),
        .I1(lowCL2[3]),
        .O(\lowCL2_reg[2]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2128" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__2 
       (.I0(uppCL2[26]),
        .I1(uppCL2[27]),
        .O(\uppCL2_reg[26]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2094" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [1]),
        .I1(\uppCL2_reg[45]_0 [2]),
        .O(\uppCL2_reg[8]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2098" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [4]),
        .I1(\uppCL2_reg[45]_0 [5]),
        .O(\uppCL2_reg[44]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2136" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__5 
       (.I0(lowCL2[44]),
        .I1(lowCL2[45]),
        .O(\lowCL2_reg[44]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2144" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__6 
       (.I0(uppCL2[2]),
        .I1(uppCL2[3]),
        .O(\uppCL2_reg[2]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2152" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__7 
       (.I0(uppCL2[32]),
        .I1(uppCL2[33]),
        .O(\uppCL2_reg[32]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2160" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__8 
       (.I0(lowCL2[32]),
        .I1(lowCL2[33]),
        .O(\lowCL2_reg[32]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2168" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[5][3]_i_1__9 
       (.I0(lowCL2[26]),
        .I1(lowCL2[27]),
        .O(\lowCL2_reg[26]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1966" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1 
       (.I0(uppCL2[36]),
        .I1(uppCL2[38]),
        .I2(uppCL2[37]),
        .O(\uppCL2_reg[36]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1970" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__0 
       (.I0(uppCL2[18]),
        .I1(uppCL2[20]),
        .I2(uppCL2[19]),
        .O(\uppCL2_reg[18]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1974" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__1 
       (.I0(uppCL2[12]),
        .I1(uppCL2[14]),
        .I2(uppCL2[13]),
        .O(\uppCL2_reg[12]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2010" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__10 
       (.I0(lowCL2[36]),
        .I1(lowCL2[38]),
        .I2(lowCL2[37]),
        .O(\lowCL2_reg[36]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2014" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__11 
       (.I0(lowCL2[18]),
        .I1(lowCL2[20]),
        .I2(lowCL2[19]),
        .O(\lowCL2_reg[18]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2018" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__12 
       (.I0(lowCL2[12]),
        .I1(lowCL2[14]),
        .I2(lowCL2[13]),
        .O(\lowCL2_reg[12]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2022" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__13 
       (.I0(lowCL2[6]),
        .I1(lowCL2[8]),
        .I2(lowCL2[7]),
        .O(\lowCL2_reg[6]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2026" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__14 
       (.I0(lowCL2[0]),
        .I1(lowCL2[2]),
        .I2(lowCL2[1]),
        .O(\lowCL2_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1978" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__2 
       (.I0(uppCL2[24]),
        .I1(uppCL2[26]),
        .I2(uppCL2[25]),
        .O(\uppCL2_reg[24]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1982" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__3 
       (.I0(uppCL2[6]),
        .I1(\uppCL2_reg[45]_0 [1]),
        .I2(\uppCL2_reg[45]_0 [0]),
        .O(\uppCL2_reg[6]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1986" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__4 
       (.I0(uppCL2[42]),
        .I1(\uppCL2_reg[45]_0 [4]),
        .I2(\uppCL2_reg[45]_0 [3]),
        .O(\uppCL2_reg[42]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1990" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__5 
       (.I0(lowCL2[42]),
        .I1(lowCL2[44]),
        .I2(lowCL2[43]),
        .O(\lowCL2_reg[42]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1994" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__6 
       (.I0(uppCL2[0]),
        .I1(uppCL2[2]),
        .I2(uppCL2[1]),
        .O(\uppCL2_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1998" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__7 
       (.I0(uppCL2[30]),
        .I1(uppCL2[32]),
        .I2(uppCL2[31]),
        .O(\uppCL2_reg[30]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2002" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__8 
       (.I0(lowCL2[30]),
        .I1(lowCL2[32]),
        .I2(lowCL2[31]),
        .O(\lowCL2_reg[30]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2006" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[5][4]_i_1__9 
       (.I0(lowCL2[24]),
        .I1(lowCL2[26]),
        .I2(lowCL2[25]),
        .O(\lowCL2_reg[24]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1710" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1 
       (.I0(uppCL2[37]),
        .I1(uppCL2[38]),
        .I2(uppCL2[39]),
        .O(\uppCL2_reg[37]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1714" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__0 
       (.I0(uppCL2[19]),
        .I1(uppCL2[20]),
        .I2(uppCL2[21]),
        .O(\uppCL2_reg[19]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1718" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__1 
       (.I0(uppCL2[13]),
        .I1(uppCL2[14]),
        .I2(uppCL2[15]),
        .O(\uppCL2_reg[13]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1754" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__10 
       (.I0(lowCL2[13]),
        .I1(lowCL2[14]),
        .I2(lowCL2[15]),
        .O(\lowCL2_reg[13]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1758" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__11 
       (.I0(lowCL2[7]),
        .I1(lowCL2[8]),
        .I2(lowCL2[9]),
        .O(\lowCL2_reg[7]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1762" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__12 
       (.I0(lowCL2[1]),
        .I1(lowCL2[2]),
        .I2(lowCL2[3]),
        .O(\lowCL2_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1722" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__2 
       (.I0(uppCL2[25]),
        .I1(uppCL2[26]),
        .I2(uppCL2[27]),
        .O(\uppCL2_reg[25]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1726" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__3 
       (.I0(lowCL2[43]),
        .I1(lowCL2[44]),
        .I2(lowCL2[45]),
        .O(\lowCL2_reg[43]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1730" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__4 
       (.I0(uppCL2[1]),
        .I1(uppCL2[2]),
        .I2(uppCL2[3]),
        .O(\uppCL2_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1734" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__5 
       (.I0(uppCL2[31]),
        .I1(uppCL2[32]),
        .I2(uppCL2[33]),
        .O(\uppCL2_reg[31]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1738" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__6 
       (.I0(lowCL2[31]),
        .I1(lowCL2[32]),
        .I2(lowCL2[33]),
        .O(\lowCL2_reg[31]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1742" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__7 
       (.I0(lowCL2[25]),
        .I1(lowCL2[26]),
        .I2(lowCL2[27]),
        .O(\lowCL2_reg[25]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1746" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__8 
       (.I0(lowCL2[37]),
        .I1(lowCL2[38]),
        .I2(lowCL2[39]),
        .O(\lowCL2_reg[37]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1750" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[5][5]_i_1__9 
       (.I0(lowCL2[19]),
        .I1(lowCL2[20]),
        .I2(lowCL2[21]),
        .O(\lowCL2_reg[19]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1849" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1 
       (.I0(uppCL2[37]),
        .I1(uppCL2[38]),
        .I2(uppCL2[36]),
        .O(\uppCL2_reg[37]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1857" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__0 
       (.I0(uppCL2[19]),
        .I1(uppCL2[20]),
        .I2(uppCL2[18]),
        .O(\uppCL2_reg[19]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1865" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__1 
       (.I0(uppCL2[13]),
        .I1(uppCL2[14]),
        .I2(uppCL2[12]),
        .O(\uppCL2_reg[13]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1921" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__10 
       (.I0(lowCL2[37]),
        .I1(lowCL2[38]),
        .I2(lowCL2[36]),
        .O(\lowCL2_reg[37]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1929" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__11 
       (.I0(lowCL2[19]),
        .I1(lowCL2[20]),
        .I2(lowCL2[18]),
        .O(\lowCL2_reg[19]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1937" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__12 
       (.I0(lowCL2[13]),
        .I1(lowCL2[14]),
        .I2(lowCL2[12]),
        .O(\lowCL2_reg[13]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1945" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__13 
       (.I0(lowCL2[7]),
        .I1(lowCL2[8]),
        .I2(lowCL2[6]),
        .O(\lowCL2_reg[7]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1953" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__14 
       (.I0(lowCL2[1]),
        .I1(lowCL2[2]),
        .I2(lowCL2[0]),
        .O(\lowCL2_reg[1]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1873" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__2 
       (.I0(uppCL2[25]),
        .I1(uppCL2[26]),
        .I2(uppCL2[24]),
        .O(\uppCL2_reg[25]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1838" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__3 
       (.I0(\uppCL2_reg[45]_0 [0]),
        .I1(\uppCL2_reg[45]_0 [1]),
        .I2(uppCL2[6]),
        .O(\uppCL2_reg[7]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1842" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__4 
       (.I0(\uppCL2_reg[45]_0 [3]),
        .I1(\uppCL2_reg[45]_0 [4]),
        .I2(uppCL2[42]),
        .O(\uppCL2_reg[43]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1881" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__5 
       (.I0(lowCL2[43]),
        .I1(lowCL2[44]),
        .I2(lowCL2[42]),
        .O(\lowCL2_reg[43]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1889" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__6 
       (.I0(uppCL2[1]),
        .I1(uppCL2[2]),
        .I2(uppCL2[0]),
        .O(\uppCL2_reg[1]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1897" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__7 
       (.I0(uppCL2[31]),
        .I1(uppCL2[32]),
        .I2(uppCL2[30]),
        .O(\uppCL2_reg[31]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1905" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__8 
       (.I0(lowCL2[31]),
        .I1(lowCL2[32]),
        .I2(lowCL2[30]),
        .O(\lowCL2_reg[31]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1913" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[5][8]_i_1__9 
       (.I0(lowCL2[25]),
        .I1(lowCL2[26]),
        .I2(lowCL2[24]),
        .O(\lowCL2_reg[25]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2105" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1 
       (.I0(uppCL2[37]),
        .I1(uppCL2[38]),
        .O(\uppCL2_reg[37]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2113" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__0 
       (.I0(uppCL2[19]),
        .I1(uppCL2[20]),
        .O(\uppCL2_reg[19]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2121" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__1 
       (.I0(uppCL2[13]),
        .I1(uppCL2[14]),
        .O(\uppCL2_reg[13]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2193" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__10 
       (.I0(lowCL2[13]),
        .I1(lowCL2[14]),
        .O(\lowCL2_reg[13]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2201" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__11 
       (.I0(lowCL2[7]),
        .I1(lowCL2[8]),
        .O(\lowCL2_reg[7]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2209" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__12 
       (.I0(lowCL2[1]),
        .I1(lowCL2[2]),
        .O(\lowCL2_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2129" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__2 
       (.I0(uppCL2[25]),
        .I1(uppCL2[26]),
        .O(\uppCL2_reg[25]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2137" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__3 
       (.I0(lowCL2[43]),
        .I1(lowCL2[44]),
        .O(\lowCL2_reg[43]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2145" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__4 
       (.I0(uppCL2[1]),
        .I1(uppCL2[2]),
        .O(\uppCL2_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2153" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__5 
       (.I0(uppCL2[31]),
        .I1(uppCL2[32]),
        .O(\uppCL2_reg[31]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2161" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__6 
       (.I0(lowCL2[31]),
        .I1(lowCL2[32]),
        .O(\lowCL2_reg[31]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2169" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__7 
       (.I0(lowCL2[25]),
        .I1(lowCL2[26]),
        .O(\lowCL2_reg[25]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2177" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__8 
       (.I0(lowCL2[37]),
        .I1(lowCL2[38]),
        .O(\lowCL2_reg[37]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2185" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[5][9]_i_1__9 
       (.I0(lowCL2[19]),
        .I1(lowCL2[20]),
        .O(\lowCL2_reg[19]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1711" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1 
       (.I0(uppCL3[39]),
        .I1(uppCL3[38]),
        .I2(uppCL3[37]),
        .O(\uppCL3_reg[39]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1715" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__0 
       (.I0(uppCL3[21]),
        .I1(uppCL3[20]),
        .I2(uppCL3[19]),
        .O(\uppCL3_reg[21]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1719" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__1 
       (.I0(uppCL3[15]),
        .I1(uppCL3[14]),
        .I2(uppCL3[13]),
        .O(\uppCL3_reg[15]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1747" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__10 
       (.I0(lowCL3[39]),
        .I1(lowCL3[38]),
        .I2(lowCL3[37]),
        .O(\lowCL3_reg[39]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1751" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__11 
       (.I0(lowCL3[21]),
        .I1(lowCL3[20]),
        .I2(lowCL3[19]),
        .O(\lowCL3_reg[21]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1755" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__12 
       (.I0(lowCL3[15]),
        .I1(lowCL3[14]),
        .I2(lowCL3[13]),
        .O(\lowCL3_reg[15]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1759" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__13 
       (.I0(lowCL3[9]),
        .I1(lowCL3[8]),
        .I2(lowCL3[7]),
        .O(\lowCL3_reg[9]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1763" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__14 
       (.I0(lowCL3[3]),
        .I1(lowCL3[2]),
        .I2(lowCL3[1]),
        .O(\lowCL3_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1723" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__2 
       (.I0(uppCL3[27]),
        .I1(uppCL3[26]),
        .I2(uppCL3[25]),
        .O(\uppCL3_reg[27]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1767" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [2]),
        .I1(\uppCL3_reg[45]_0 [1]),
        .I2(\uppCL3_reg[45]_0 [0]),
        .O(\uppCL3_reg[9]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1771" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [5]),
        .I1(\uppCL3_reg[45]_0 [4]),
        .I2(\uppCL3_reg[45]_0 [3]),
        .O(\uppCL3_reg[45]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1727" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__5 
       (.I0(lowCL3[45]),
        .I1(lowCL3[44]),
        .I2(lowCL3[43]),
        .O(\lowCL3_reg[45]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1731" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__6 
       (.I0(uppCL3[3]),
        .I1(uppCL3[2]),
        .I2(uppCL3[1]),
        .O(\uppCL3_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1735" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__7 
       (.I0(uppCL3[33]),
        .I1(uppCL3[32]),
        .I2(uppCL3[31]),
        .O(\uppCL3_reg[33]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1739" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__8 
       (.I0(lowCL3[33]),
        .I1(lowCL3[32]),
        .I2(lowCL3[31]),
        .O(\lowCL3_reg[33]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1743" *) 
  LUT3 #(
    .INIT(8'h95)) 
    \rsMask[6][11]_i_1__9 
       (.I0(lowCL3[27]),
        .I1(lowCL3[26]),
        .I2(lowCL3[25]),
        .O(\lowCL3_reg[27]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2031" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2 
       (.I0(uppCL3[38]),
        .I1(uppCL3[37]),
        .O(\uppCL3_reg[38]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2035" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__0 
       (.I0(uppCL3[20]),
        .I1(uppCL3[19]),
        .O(\uppCL3_reg[20]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2039" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__1 
       (.I0(uppCL3[14]),
        .I1(uppCL3[13]),
        .O(\uppCL3_reg[14]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2075" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__10 
       (.I0(lowCL3[38]),
        .I1(lowCL3[37]),
        .O(\lowCL3_reg[38]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2079" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__11 
       (.I0(lowCL3[20]),
        .I1(lowCL3[19]),
        .O(\lowCL3_reg[20]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2083" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__12 
       (.I0(lowCL3[14]),
        .I1(lowCL3[13]),
        .O(\lowCL3_reg[14]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2087" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__13 
       (.I0(lowCL3[8]),
        .I1(lowCL3[7]),
        .O(\lowCL3_reg[8]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2091" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__14 
       (.I0(lowCL3[2]),
        .I1(lowCL3[1]),
        .O(\lowCL3_reg[2]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2043" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__2 
       (.I0(uppCL3[26]),
        .I1(uppCL3[25]),
        .O(\uppCL3_reg[26]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2047" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__3 
       (.I0(\uppCL3_reg[45]_0 [1]),
        .I1(\uppCL3_reg[45]_0 [0]),
        .O(\uppCL3_reg[8]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2051" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__4 
       (.I0(\uppCL3_reg[45]_0 [4]),
        .I1(\uppCL3_reg[45]_0 [3]),
        .O(\uppCL3_reg[44]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2055" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__5 
       (.I0(lowCL3[44]),
        .I1(lowCL3[43]),
        .O(\lowCL3_reg[44]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2059" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__6 
       (.I0(uppCL3[2]),
        .I1(uppCL3[1]),
        .O(\uppCL3_reg[2]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2063" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__7 
       (.I0(uppCL3[32]),
        .I1(uppCL3[31]),
        .O(\uppCL3_reg[32]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2067" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__8 
       (.I0(lowCL3[32]),
        .I1(lowCL3[31]),
        .O(\lowCL3_reg[32]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2071" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \rsMask[6][11]_i_2__9 
       (.I0(lowCL3[26]),
        .I1(lowCL3[25]),
        .O(\lowCL3_reg[26]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1602" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1 
       (.I0(uppCL3[37]),
        .I1(uppCL3[38]),
        .I2(uppCL3[39]),
        .I3(uppCL3[36]),
        .O(\uppCL3_reg[38]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1610" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__0 
       (.I0(uppCL3[19]),
        .I1(uppCL3[20]),
        .I2(uppCL3[21]),
        .I3(uppCL3[18]),
        .O(\uppCL3_reg[20]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1618" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__1 
       (.I0(uppCL3[13]),
        .I1(uppCL3[14]),
        .I2(uppCL3[15]),
        .I3(uppCL3[12]),
        .O(\uppCL3_reg[14]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1690" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__10 
       (.I0(lowCL3[13]),
        .I1(lowCL3[14]),
        .I2(lowCL3[15]),
        .I3(lowCL3[12]),
        .O(\lowCL3_reg[14]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1698" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__11 
       (.I0(lowCL3[7]),
        .I1(lowCL3[8]),
        .I2(lowCL3[9]),
        .I3(lowCL3[6]),
        .O(\lowCL3_reg[8]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1706" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__12 
       (.I0(lowCL3[1]),
        .I1(lowCL3[2]),
        .I2(lowCL3[3]),
        .I3(lowCL3[0]),
        .O(\lowCL3_reg[2]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1626" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__2 
       (.I0(uppCL3[25]),
        .I1(uppCL3[26]),
        .I2(uppCL3[27]),
        .I3(uppCL3[24]),
        .O(\uppCL3_reg[26]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1634" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__3 
       (.I0(lowCL3[43]),
        .I1(lowCL3[44]),
        .I2(lowCL3[45]),
        .I3(lowCL3[42]),
        .O(\lowCL3_reg[44]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1642" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__4 
       (.I0(uppCL3[1]),
        .I1(uppCL3[2]),
        .I2(uppCL3[3]),
        .I3(uppCL3[0]),
        .O(\uppCL3_reg[2]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1650" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__5 
       (.I0(uppCL3[31]),
        .I1(uppCL3[32]),
        .I2(uppCL3[33]),
        .I3(uppCL3[30]),
        .O(\uppCL3_reg[32]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1658" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__6 
       (.I0(lowCL3[31]),
        .I1(lowCL3[32]),
        .I2(lowCL3[33]),
        .I3(lowCL3[30]),
        .O(\lowCL3_reg[32]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1666" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__7 
       (.I0(lowCL3[25]),
        .I1(lowCL3[26]),
        .I2(lowCL3[27]),
        .I3(lowCL3[24]),
        .O(\lowCL3_reg[26]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1674" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__8 
       (.I0(lowCL3[37]),
        .I1(lowCL3[38]),
        .I2(lowCL3[39]),
        .I3(lowCL3[36]),
        .O(\lowCL3_reg[38]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1682" *) 
  LUT4 #(
    .INIT(16'hC0C1)) 
    \rsMask[6][2]_i_1__9 
       (.I0(lowCL3[19]),
        .I1(lowCL3[20]),
        .I2(lowCL3[21]),
        .I3(lowCL3[18]),
        .O(\lowCL3_reg[20]_3 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1850" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1 
       (.I0(uppCL3[37]),
        .I1(uppCL3[38]),
        .I2(uppCL3[39]),
        .O(\uppCL3_reg[38]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1858" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__0 
       (.I0(uppCL3[19]),
        .I1(uppCL3[20]),
        .I2(uppCL3[21]),
        .O(\uppCL3_reg[20]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1866" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__1 
       (.I0(uppCL3[13]),
        .I1(uppCL3[14]),
        .I2(uppCL3[15]),
        .O(\uppCL3_reg[14]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1938" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__10 
       (.I0(lowCL3[13]),
        .I1(lowCL3[14]),
        .I2(lowCL3[15]),
        .O(\lowCL3_reg[14]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1946" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__11 
       (.I0(lowCL3[7]),
        .I1(lowCL3[8]),
        .I2(lowCL3[9]),
        .O(\lowCL3_reg[8]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1954" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__12 
       (.I0(lowCL3[1]),
        .I1(lowCL3[2]),
        .I2(lowCL3[3]),
        .O(\lowCL3_reg[2]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1874" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__2 
       (.I0(uppCL3[25]),
        .I1(uppCL3[26]),
        .I2(uppCL3[27]),
        .O(\uppCL3_reg[26]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1882" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__3 
       (.I0(lowCL3[43]),
        .I1(lowCL3[44]),
        .I2(lowCL3[45]),
        .O(\lowCL3_reg[44]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1890" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__4 
       (.I0(uppCL3[1]),
        .I1(uppCL3[2]),
        .I2(uppCL3[3]),
        .O(\uppCL3_reg[2]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1898" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__5 
       (.I0(uppCL3[31]),
        .I1(uppCL3[32]),
        .I2(uppCL3[33]),
        .O(\uppCL3_reg[32]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1906" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__6 
       (.I0(lowCL3[31]),
        .I1(lowCL3[32]),
        .I2(lowCL3[33]),
        .O(\lowCL3_reg[32]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1914" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__7 
       (.I0(lowCL3[25]),
        .I1(lowCL3[26]),
        .I2(lowCL3[27]),
        .O(\lowCL3_reg[26]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1922" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__8 
       (.I0(lowCL3[37]),
        .I1(lowCL3[38]),
        .I2(lowCL3[39]),
        .O(\lowCL3_reg[38]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1930" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[6][3]_i_1__9 
       (.I0(lowCL3[19]),
        .I1(lowCL3[20]),
        .I2(lowCL3[21]),
        .O(\lowCL3_reg[20]_3 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2106" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1 
       (.I0(uppCL3[38]),
        .I1(uppCL3[39]),
        .O(\uppCL3_reg[38]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2114" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__0 
       (.I0(uppCL3[20]),
        .I1(uppCL3[21]),
        .O(\uppCL3_reg[20]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2122" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__1 
       (.I0(uppCL3[14]),
        .I1(uppCL3[15]),
        .O(\uppCL3_reg[14]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2194" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__10 
       (.I0(lowCL3[14]),
        .I1(lowCL3[15]),
        .O(\lowCL3_reg[14]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2202" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__11 
       (.I0(lowCL3[8]),
        .I1(lowCL3[9]),
        .O(\lowCL3_reg[8]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2210" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__12 
       (.I0(lowCL3[2]),
        .I1(lowCL3[3]),
        .O(\lowCL3_reg[2]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2130" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__2 
       (.I0(uppCL3[26]),
        .I1(uppCL3[27]),
        .O(\uppCL3_reg[26]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2138" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__3 
       (.I0(lowCL3[44]),
        .I1(lowCL3[45]),
        .O(\lowCL3_reg[44]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2146" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__4 
       (.I0(uppCL3[2]),
        .I1(uppCL3[3]),
        .O(\uppCL3_reg[2]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2154" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__5 
       (.I0(uppCL3[32]),
        .I1(uppCL3[33]),
        .O(\uppCL3_reg[32]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2162" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__6 
       (.I0(lowCL3[32]),
        .I1(lowCL3[33]),
        .O(\lowCL3_reg[32]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2170" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__7 
       (.I0(lowCL3[26]),
        .I1(lowCL3[27]),
        .O(\lowCL3_reg[26]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2178" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__8 
       (.I0(lowCL3[38]),
        .I1(lowCL3[39]),
        .O(\lowCL3_reg[38]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2186" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[6][9]_i_1__9 
       (.I0(lowCL3[20]),
        .I1(lowCL3[21]),
        .O(\lowCL3_reg[20]_3 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1603" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1 
       (.I0(uppCL3[37]),
        .I1(uppCL3[38]),
        .I2(uppCL3[39]),
        .I3(uppCL3[36]),
        .O(\uppCL3_reg[37]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1611" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__0 
       (.I0(uppCL3[19]),
        .I1(uppCL3[20]),
        .I2(uppCL3[21]),
        .I3(uppCL3[18]),
        .O(\uppCL3_reg[19]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1619" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__1 
       (.I0(uppCL3[13]),
        .I1(uppCL3[14]),
        .I2(uppCL3[15]),
        .I3(uppCL3[12]),
        .O(\uppCL3_reg[13]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1675" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__10 
       (.I0(lowCL3[37]),
        .I1(lowCL3[38]),
        .I2(lowCL3[39]),
        .I3(lowCL3[36]),
        .O(\lowCL3_reg[37]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1683" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__11 
       (.I0(lowCL3[19]),
        .I1(lowCL3[20]),
        .I2(lowCL3[21]),
        .I3(lowCL3[18]),
        .O(\lowCL3_reg[19]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1691" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__12 
       (.I0(lowCL3[13]),
        .I1(lowCL3[14]),
        .I2(lowCL3[15]),
        .I3(lowCL3[12]),
        .O(\lowCL3_reg[13]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1699" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__13 
       (.I0(lowCL3[7]),
        .I1(lowCL3[8]),
        .I2(lowCL3[9]),
        .I3(lowCL3[6]),
        .O(\lowCL3_reg[7]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1707" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__14 
       (.I0(lowCL3[1]),
        .I1(lowCL3[2]),
        .I2(lowCL3[3]),
        .I3(lowCL3[0]),
        .O(\lowCL3_reg[1]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1627" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__2 
       (.I0(uppCL3[25]),
        .I1(uppCL3[26]),
        .I2(uppCL3[27]),
        .I3(uppCL3[24]),
        .O(\uppCL3_reg[25]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1586" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [0]),
        .I1(\uppCL3_reg[45]_0 [1]),
        .I2(\uppCL3_reg[45]_0 [2]),
        .I3(uppCL3[6]),
        .O(\uppCL3_reg[7]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1594" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [3]),
        .I1(\uppCL3_reg[45]_0 [4]),
        .I2(\uppCL3_reg[45]_0 [5]),
        .I3(uppCL3[42]),
        .O(\uppCL3_reg[43]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1635" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__5 
       (.I0(lowCL3[43]),
        .I1(lowCL3[44]),
        .I2(lowCL3[45]),
        .I3(lowCL3[42]),
        .O(\lowCL3_reg[43]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1643" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__6 
       (.I0(uppCL3[1]),
        .I1(uppCL3[2]),
        .I2(uppCL3[3]),
        .I3(uppCL3[0]),
        .O(\uppCL3_reg[1]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1651" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__7 
       (.I0(uppCL3[31]),
        .I1(uppCL3[32]),
        .I2(uppCL3[33]),
        .I3(uppCL3[30]),
        .O(\uppCL3_reg[31]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1659" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__8 
       (.I0(lowCL3[31]),
        .I1(lowCL3[32]),
        .I2(lowCL3[33]),
        .I3(lowCL3[30]),
        .O(\lowCL3_reg[31]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1667" *) 
  LUT4 #(
    .INIT(16'h060C)) 
    \rsMask[7][10]_i_1__9 
       (.I0(lowCL3[25]),
        .I1(lowCL3[26]),
        .I2(lowCL3[27]),
        .I3(lowCL3[24]),
        .O(\lowCL3_reg[25]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1850" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1 
       (.I0(uppCL3[37]),
        .I1(uppCL3[38]),
        .I2(uppCL3[39]),
        .O(\uppCL3_reg[37]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1858" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__0 
       (.I0(uppCL3[19]),
        .I1(uppCL3[20]),
        .I2(uppCL3[21]),
        .O(\uppCL3_reg[19]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1866" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__1 
       (.I0(uppCL3[13]),
        .I1(uppCL3[14]),
        .I2(uppCL3[15]),
        .O(\uppCL3_reg[13]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1938" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__10 
       (.I0(lowCL3[13]),
        .I1(lowCL3[14]),
        .I2(lowCL3[15]),
        .O(\lowCL3_reg[13]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1946" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__11 
       (.I0(lowCL3[7]),
        .I1(lowCL3[8]),
        .I2(lowCL3[9]),
        .O(\lowCL3_reg[7]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1954" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__12 
       (.I0(lowCL3[1]),
        .I1(lowCL3[2]),
        .I2(lowCL3[3]),
        .O(\lowCL3_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1874" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__2 
       (.I0(uppCL3[25]),
        .I1(uppCL3[26]),
        .I2(uppCL3[27]),
        .O(\uppCL3_reg[25]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1882" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__3 
       (.I0(lowCL3[43]),
        .I1(lowCL3[44]),
        .I2(lowCL3[45]),
        .O(\lowCL3_reg[43]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1890" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__4 
       (.I0(uppCL3[1]),
        .I1(uppCL3[2]),
        .I2(uppCL3[3]),
        .O(\uppCL3_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1898" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__5 
       (.I0(uppCL3[31]),
        .I1(uppCL3[32]),
        .I2(uppCL3[33]),
        .O(\uppCL3_reg[31]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1906" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__6 
       (.I0(lowCL3[31]),
        .I1(lowCL3[32]),
        .I2(lowCL3[33]),
        .O(\lowCL3_reg[31]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1914" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__7 
       (.I0(lowCL3[25]),
        .I1(lowCL3[26]),
        .I2(lowCL3[27]),
        .O(\lowCL3_reg[25]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1922" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__8 
       (.I0(lowCL3[37]),
        .I1(lowCL3[38]),
        .I2(lowCL3[39]),
        .O(\lowCL3_reg[37]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1930" *) 
  LUT3 #(
    .INIT(8'h4C)) 
    \rsMask[7][11]_i_1__9 
       (.I0(lowCL3[19]),
        .I1(lowCL3[20]),
        .I2(lowCL3[21]),
        .O(\lowCL3_reg[19]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1602" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1 
       (.I0(uppCL3[37]),
        .I1(uppCL3[38]),
        .I2(uppCL3[39]),
        .I3(uppCL3[36]),
        .O(\uppCL3_reg[37]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1610" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__0 
       (.I0(uppCL3[19]),
        .I1(uppCL3[20]),
        .I2(uppCL3[21]),
        .I3(uppCL3[18]),
        .O(\uppCL3_reg[19]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1618" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__1 
       (.I0(uppCL3[13]),
        .I1(uppCL3[14]),
        .I2(uppCL3[15]),
        .I3(uppCL3[12]),
        .O(\uppCL3_reg[13]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1674" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__10 
       (.I0(lowCL3[37]),
        .I1(lowCL3[38]),
        .I2(lowCL3[39]),
        .I3(lowCL3[36]),
        .O(\lowCL3_reg[37]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1682" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__11 
       (.I0(lowCL3[19]),
        .I1(lowCL3[20]),
        .I2(lowCL3[21]),
        .I3(lowCL3[18]),
        .O(\lowCL3_reg[19]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1690" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__12 
       (.I0(lowCL3[13]),
        .I1(lowCL3[14]),
        .I2(lowCL3[15]),
        .I3(lowCL3[12]),
        .O(\lowCL3_reg[13]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1698" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__13 
       (.I0(lowCL3[7]),
        .I1(lowCL3[8]),
        .I2(lowCL3[9]),
        .I3(lowCL3[6]),
        .O(\lowCL3_reg[7]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1706" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__14 
       (.I0(lowCL3[1]),
        .I1(lowCL3[2]),
        .I2(lowCL3[3]),
        .I3(lowCL3[0]),
        .O(\lowCL3_reg[1]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1626" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__2 
       (.I0(uppCL3[25]),
        .I1(uppCL3[26]),
        .I2(uppCL3[27]),
        .I3(uppCL3[24]),
        .O(\uppCL3_reg[25]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1586" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [0]),
        .I1(\uppCL3_reg[45]_0 [1]),
        .I2(\uppCL3_reg[45]_0 [2]),
        .I3(uppCL3[6]),
        .O(\uppCL3_reg[7]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1594" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [3]),
        .I1(\uppCL3_reg[45]_0 [4]),
        .I2(\uppCL3_reg[45]_0 [5]),
        .I3(uppCL3[42]),
        .O(\uppCL3_reg[43]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1634" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__5 
       (.I0(lowCL3[43]),
        .I1(lowCL3[44]),
        .I2(lowCL3[45]),
        .I3(lowCL3[42]),
        .O(\lowCL3_reg[43]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1642" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__6 
       (.I0(uppCL3[1]),
        .I1(uppCL3[2]),
        .I2(uppCL3[3]),
        .I3(uppCL3[0]),
        .O(\uppCL3_reg[1]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1650" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__7 
       (.I0(uppCL3[31]),
        .I1(uppCL3[32]),
        .I2(uppCL3[33]),
        .I3(uppCL3[30]),
        .O(\uppCL3_reg[31]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1658" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__8 
       (.I0(lowCL3[31]),
        .I1(lowCL3[32]),
        .I2(lowCL3[33]),
        .I3(lowCL3[30]),
        .O(\lowCL3_reg[31]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1666" *) 
  LUT4 #(
    .INIT(16'h0C18)) 
    \rsMask[7][12]_i_1__9 
       (.I0(lowCL3[25]),
        .I1(lowCL3[26]),
        .I2(lowCL3[27]),
        .I3(lowCL3[24]),
        .O(\lowCL3_reg[25]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1967" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1 
       (.I0(uppCL3[38]),
        .I1(uppCL3[37]),
        .O(\uppCL3_reg[38]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1971" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__0 
       (.I0(uppCL3[20]),
        .I1(uppCL3[19]),
        .O(\uppCL3_reg[20]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1975" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__1 
       (.I0(uppCL3[14]),
        .I1(uppCL3[13]),
        .O(\uppCL3_reg[14]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2011" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__10 
       (.I0(lowCL3[38]),
        .I1(lowCL3[37]),
        .O(\lowCL3_reg[38]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2015" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__11 
       (.I0(lowCL3[20]),
        .I1(lowCL3[19]),
        .O(\lowCL3_reg[20]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2019" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__12 
       (.I0(lowCL3[14]),
        .I1(lowCL3[13]),
        .O(\lowCL3_reg[14]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2023" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__13 
       (.I0(lowCL3[8]),
        .I1(lowCL3[7]),
        .O(\lowCL3_reg[8]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2027" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__14 
       (.I0(lowCL3[2]),
        .I1(lowCL3[1]),
        .O(\lowCL3_reg[2]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1979" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__2 
       (.I0(uppCL3[26]),
        .I1(uppCL3[25]),
        .O(\uppCL3_reg[26]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1959" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [1]),
        .I1(\uppCL3_reg[45]_0 [0]),
        .O(\uppCL3_reg[8]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1963" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [4]),
        .I1(\uppCL3_reg[45]_0 [3]),
        .O(\uppCL3_reg[44]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1991" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__5 
       (.I0(lowCL3[44]),
        .I1(lowCL3[43]),
        .O(\lowCL3_reg[44]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1995" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__6 
       (.I0(uppCL3[2]),
        .I1(uppCL3[1]),
        .O(\uppCL3_reg[2]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1999" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__7 
       (.I0(uppCL3[32]),
        .I1(uppCL3[31]),
        .O(\uppCL3_reg[32]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2003" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__8 
       (.I0(lowCL3[32]),
        .I1(lowCL3[31]),
        .O(\lowCL3_reg[32]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2007" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rsMask[7][13]_i_1__9 
       (.I0(lowCL3[26]),
        .I1(lowCL3[25]),
        .O(\lowCL3_reg[26]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1783" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1 
       (.I0(uppCL3[37]),
        .I1(uppCL3[38]),
        .I2(uppCL3[36]),
        .O(\uppCL3_reg[37]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1787" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__0 
       (.I0(uppCL3[19]),
        .I1(uppCL3[20]),
        .I2(uppCL3[18]),
        .O(\uppCL3_reg[19]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1791" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__1 
       (.I0(uppCL3[13]),
        .I1(uppCL3[14]),
        .I2(uppCL3[12]),
        .O(\uppCL3_reg[13]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1819" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__10 
       (.I0(lowCL3[37]),
        .I1(lowCL3[38]),
        .I2(lowCL3[36]),
        .O(\lowCL3_reg[37]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1823" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__11 
       (.I0(lowCL3[19]),
        .I1(lowCL3[20]),
        .I2(lowCL3[18]),
        .O(\lowCL3_reg[19]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1827" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__12 
       (.I0(lowCL3[13]),
        .I1(lowCL3[14]),
        .I2(lowCL3[12]),
        .O(\lowCL3_reg[13]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1831" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__13 
       (.I0(lowCL3[7]),
        .I1(lowCL3[8]),
        .I2(lowCL3[6]),
        .O(\lowCL3_reg[7]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1835" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__14 
       (.I0(lowCL3[1]),
        .I1(lowCL3[2]),
        .I2(lowCL3[0]),
        .O(\lowCL3_reg[1]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1795" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__2 
       (.I0(uppCL3[25]),
        .I1(uppCL3[26]),
        .I2(uppCL3[24]),
        .O(\uppCL3_reg[25]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1775" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [0]),
        .I1(\uppCL3_reg[45]_0 [1]),
        .I2(uppCL3[6]),
        .O(\uppCL3_reg[7]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1779" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [3]),
        .I1(\uppCL3_reg[45]_0 [4]),
        .I2(uppCL3[42]),
        .O(\uppCL3_reg[43]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1799" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__5 
       (.I0(lowCL3[43]),
        .I1(lowCL3[44]),
        .I2(lowCL3[42]),
        .O(\lowCL3_reg[43]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1803" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__6 
       (.I0(uppCL3[1]),
        .I1(uppCL3[2]),
        .I2(uppCL3[0]),
        .O(\uppCL3_reg[1]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1807" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__7 
       (.I0(uppCL3[31]),
        .I1(uppCL3[32]),
        .I2(uppCL3[30]),
        .O(\uppCL3_reg[31]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1811" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__8 
       (.I0(lowCL3[31]),
        .I1(lowCL3[32]),
        .I2(lowCL3[30]),
        .O(\lowCL3_reg[31]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1815" *) 
  LUT3 #(
    .INIT(8'h93)) 
    \rsMask[7][14]_i_1__9 
       (.I0(lowCL3[25]),
        .I1(lowCL3[26]),
        .I2(lowCL3[24]),
        .O(\lowCL3_reg[25]_4 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1 
       (.I0(uppCL3[38]),
        .O(\uppCL3_reg[38]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__0 
       (.I0(uppCL3[26]),
        .O(\uppCL3_reg[26]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__1 
       (.I0(uppCL3[20]),
        .O(\uppCL3_reg[20]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__10 
       (.I0(lowCL3[26]),
        .O(\lowCL3_reg[26]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__11 
       (.I0(lowCL3[20]),
        .O(\lowCL3_reg[20]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__12 
       (.I0(lowCL3[14]),
        .O(\lowCL3_reg[14]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__13 
       (.I0(lowCL3[8]),
        .O(\lowCL3_reg[8]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__14 
       (.I0(lowCL3[2]),
        .O(\lowCL3_reg[2]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__2 
       (.I0(uppCL3[14]),
        .O(\uppCL3_reg[14]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair2219" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [4]),
        .O(\uppCL3_reg[44]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair2215" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [1]),
        .O(\uppCL3_reg[8]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__5 
       (.I0(lowCL3[44]),
        .O(\lowCL3_reg[44]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__6 
       (.I0(uppCL3[32]),
        .O(\uppCL3_reg[32]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__7 
       (.I0(uppCL3[2]),
        .O(\uppCL3_reg[2]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__8 
       (.I0(lowCL3[38]),
        .O(\lowCL3_reg[38]_2 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rsMask[7][15]_i_1__9 
       (.I0(lowCL3[32]),
        .O(\lowCL3_reg[32]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1851" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1 
       (.I0(uppCL3[37]),
        .I1(uppCL3[38]),
        .I2(uppCL3[36]),
        .O(\uppCL3_reg[37]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1859" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__0 
       (.I0(uppCL3[19]),
        .I1(uppCL3[20]),
        .I2(uppCL3[18]),
        .O(\uppCL3_reg[19]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1867" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__1 
       (.I0(uppCL3[13]),
        .I1(uppCL3[14]),
        .I2(uppCL3[12]),
        .O(\uppCL3_reg[13]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1923" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__10 
       (.I0(lowCL3[37]),
        .I1(lowCL3[38]),
        .I2(lowCL3[36]),
        .O(\lowCL3_reg[37]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1931" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__11 
       (.I0(lowCL3[19]),
        .I1(lowCL3[20]),
        .I2(lowCL3[18]),
        .O(\lowCL3_reg[19]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1939" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__12 
       (.I0(lowCL3[13]),
        .I1(lowCL3[14]),
        .I2(lowCL3[12]),
        .O(\lowCL3_reg[13]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1947" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__13 
       (.I0(lowCL3[7]),
        .I1(lowCL3[8]),
        .I2(lowCL3[6]),
        .O(\lowCL3_reg[7]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1955" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__14 
       (.I0(lowCL3[1]),
        .I1(lowCL3[2]),
        .I2(lowCL3[0]),
        .O(\lowCL3_reg[1]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1875" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__2 
       (.I0(uppCL3[25]),
        .I1(uppCL3[26]),
        .I2(uppCL3[24]),
        .O(\uppCL3_reg[25]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1839" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [0]),
        .I1(\uppCL3_reg[45]_0 [1]),
        .I2(uppCL3[6]),
        .O(\uppCL3_reg[7]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1843" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [3]),
        .I1(\uppCL3_reg[45]_0 [4]),
        .I2(uppCL3[42]),
        .O(\uppCL3_reg[43]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1883" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__5 
       (.I0(lowCL3[43]),
        .I1(lowCL3[44]),
        .I2(lowCL3[42]),
        .O(\lowCL3_reg[43]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1891" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__6 
       (.I0(uppCL3[1]),
        .I1(uppCL3[2]),
        .I2(uppCL3[0]),
        .O(\uppCL3_reg[1]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1899" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__7 
       (.I0(uppCL3[31]),
        .I1(uppCL3[32]),
        .I2(uppCL3[30]),
        .O(\uppCL3_reg[31]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1907" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__8 
       (.I0(lowCL3[31]),
        .I1(lowCL3[32]),
        .I2(lowCL3[30]),
        .O(\lowCL3_reg[31]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1915" *) 
  LUT3 #(
    .INIT(8'h32)) 
    \rsMask[7][16]_i_1__9 
       (.I0(lowCL3[25]),
        .I1(lowCL3[26]),
        .I2(lowCL3[24]),
        .O(\lowCL3_reg[25]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair2107" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1 
       (.I0(uppCL3[38]),
        .I1(uppCL3[37]),
        .O(\uppCL3_reg[38]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2115" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__0 
       (.I0(uppCL3[20]),
        .I1(uppCL3[19]),
        .O(\uppCL3_reg[20]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2123" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__1 
       (.I0(uppCL3[14]),
        .I1(uppCL3[13]),
        .O(\uppCL3_reg[14]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2179" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__10 
       (.I0(lowCL3[38]),
        .I1(lowCL3[37]),
        .O(\lowCL3_reg[38]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2187" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__11 
       (.I0(lowCL3[20]),
        .I1(lowCL3[19]),
        .O(\lowCL3_reg[20]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2195" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__12 
       (.I0(lowCL3[14]),
        .I1(lowCL3[13]),
        .O(\lowCL3_reg[14]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2203" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__13 
       (.I0(lowCL3[8]),
        .I1(lowCL3[7]),
        .O(\lowCL3_reg[8]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2211" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__14 
       (.I0(lowCL3[2]),
        .I1(lowCL3[1]),
        .O(\lowCL3_reg[2]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2131" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__2 
       (.I0(uppCL3[26]),
        .I1(uppCL3[25]),
        .O(\uppCL3_reg[26]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2047" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [1]),
        .I1(\uppCL3_reg[45]_0 [0]),
        .O(\uppCL3_reg[8]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2051" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [4]),
        .I1(\uppCL3_reg[45]_0 [3]),
        .O(\uppCL3_reg[44]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2139" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__5 
       (.I0(lowCL3[44]),
        .I1(lowCL3[43]),
        .O(\lowCL3_reg[44]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2147" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__6 
       (.I0(uppCL3[2]),
        .I1(uppCL3[1]),
        .O(\uppCL3_reg[2]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2155" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__7 
       (.I0(uppCL3[32]),
        .I1(uppCL3[31]),
        .O(\uppCL3_reg[32]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2163" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__8 
       (.I0(lowCL3[32]),
        .I1(lowCL3[31]),
        .O(\lowCL3_reg[32]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2171" *) 
  LUT2 #(
    .INIT(4'h4)) 
    \rsMask[7][17]_i_1__9 
       (.I0(lowCL3[26]),
        .I1(lowCL3[25]),
        .O(\lowCL3_reg[26]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1783" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1 
       (.I0(uppCL3[38]),
        .I1(uppCL3[36]),
        .I2(uppCL3[37]),
        .O(\uppCL3_reg[38]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1787" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__0 
       (.I0(uppCL3[20]),
        .I1(uppCL3[18]),
        .I2(uppCL3[19]),
        .O(\uppCL3_reg[20]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1791" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__1 
       (.I0(uppCL3[14]),
        .I1(uppCL3[12]),
        .I2(uppCL3[13]),
        .O(\uppCL3_reg[14]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1819" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__10 
       (.I0(lowCL3[38]),
        .I1(lowCL3[36]),
        .I2(lowCL3[37]),
        .O(\lowCL3_reg[38]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1823" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__11 
       (.I0(lowCL3[20]),
        .I1(lowCL3[18]),
        .I2(lowCL3[19]),
        .O(\lowCL3_reg[20]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1827" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__12 
       (.I0(lowCL3[14]),
        .I1(lowCL3[12]),
        .I2(lowCL3[13]),
        .O(\lowCL3_reg[14]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1831" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__13 
       (.I0(lowCL3[8]),
        .I1(lowCL3[6]),
        .I2(lowCL3[7]),
        .O(\lowCL3_reg[8]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1835" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__14 
       (.I0(lowCL3[2]),
        .I1(lowCL3[0]),
        .I2(lowCL3[1]),
        .O(\lowCL3_reg[2]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1795" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__2 
       (.I0(uppCL3[26]),
        .I1(uppCL3[24]),
        .I2(uppCL3[25]),
        .O(\uppCL3_reg[26]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1775" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [1]),
        .I1(uppCL3[6]),
        .I2(\uppCL3_reg[45]_0 [0]),
        .O(\uppCL3_reg[8]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1779" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [4]),
        .I1(uppCL3[42]),
        .I2(\uppCL3_reg[45]_0 [3]),
        .O(\uppCL3_reg[44]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1799" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__5 
       (.I0(lowCL3[44]),
        .I1(lowCL3[42]),
        .I2(lowCL3[43]),
        .O(\lowCL3_reg[44]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1803" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__6 
       (.I0(uppCL3[2]),
        .I1(uppCL3[0]),
        .I2(uppCL3[1]),
        .O(\uppCL3_reg[2]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1807" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__7 
       (.I0(uppCL3[32]),
        .I1(uppCL3[30]),
        .I2(uppCL3[31]),
        .O(\uppCL3_reg[32]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1811" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__8 
       (.I0(lowCL3[32]),
        .I1(lowCL3[30]),
        .I2(lowCL3[31]),
        .O(\lowCL3_reg[32]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1815" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \rsMask[7][18]_i_1__9 
       (.I0(lowCL3[26]),
        .I1(lowCL3[24]),
        .I2(lowCL3[25]),
        .O(\lowCL3_reg[26]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2031" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1 
       (.I0(uppCL3[38]),
        .I1(uppCL3[37]),
        .O(\uppCL3_reg[38]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2035" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__0 
       (.I0(uppCL3[20]),
        .I1(uppCL3[19]),
        .O(\uppCL3_reg[20]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2039" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__1 
       (.I0(uppCL3[14]),
        .I1(uppCL3[13]),
        .O(\uppCL3_reg[14]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2075" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__10 
       (.I0(lowCL3[38]),
        .I1(lowCL3[37]),
        .O(\lowCL3_reg[38]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2079" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__11 
       (.I0(lowCL3[20]),
        .I1(lowCL3[19]),
        .O(\lowCL3_reg[20]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2083" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__12 
       (.I0(lowCL3[14]),
        .I1(lowCL3[13]),
        .O(\lowCL3_reg[14]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2087" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__13 
       (.I0(lowCL3[8]),
        .I1(lowCL3[7]),
        .O(\lowCL3_reg[8]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2091" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__14 
       (.I0(lowCL3[2]),
        .I1(lowCL3[1]),
        .O(\lowCL3_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2043" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__2 
       (.I0(uppCL3[26]),
        .I1(uppCL3[25]),
        .O(\uppCL3_reg[26]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1983" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [1]),
        .I1(\uppCL3_reg[45]_0 [0]),
        .O(\uppCL3_reg[8]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1987" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [4]),
        .I1(\uppCL3_reg[45]_0 [3]),
        .O(\uppCL3_reg[44]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2055" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__5 
       (.I0(lowCL3[44]),
        .I1(lowCL3[43]),
        .O(\lowCL3_reg[44]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2059" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__6 
       (.I0(uppCL3[2]),
        .I1(uppCL3[1]),
        .O(\uppCL3_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2063" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__7 
       (.I0(uppCL3[32]),
        .I1(uppCL3[31]),
        .O(\uppCL3_reg[32]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2067" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__8 
       (.I0(lowCL3[32]),
        .I1(lowCL3[31]),
        .O(\lowCL3_reg[32]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2071" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rsMask[7][1]_i_1__9 
       (.I0(lowCL3[26]),
        .I1(lowCL3[25]),
        .O(\lowCL3_reg[26]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1603" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1 
       (.I0(uppCL3[37]),
        .I1(uppCL3[38]),
        .I2(uppCL3[39]),
        .I3(uppCL3[36]),
        .O(\uppCL3_reg[37]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1611" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__0 
       (.I0(uppCL3[19]),
        .I1(uppCL3[20]),
        .I2(uppCL3[21]),
        .I3(uppCL3[18]),
        .O(\uppCL3_reg[19]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1619" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__1 
       (.I0(uppCL3[13]),
        .I1(uppCL3[14]),
        .I2(uppCL3[15]),
        .I3(uppCL3[12]),
        .O(\uppCL3_reg[13]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1675" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__10 
       (.I0(lowCL3[37]),
        .I1(lowCL3[38]),
        .I2(lowCL3[39]),
        .I3(lowCL3[36]),
        .O(\lowCL3_reg[37]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1683" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__11 
       (.I0(lowCL3[19]),
        .I1(lowCL3[20]),
        .I2(lowCL3[21]),
        .I3(lowCL3[18]),
        .O(\lowCL3_reg[19]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1691" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__12 
       (.I0(lowCL3[13]),
        .I1(lowCL3[14]),
        .I2(lowCL3[15]),
        .I3(lowCL3[12]),
        .O(\lowCL3_reg[13]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1699" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__13 
       (.I0(lowCL3[7]),
        .I1(lowCL3[8]),
        .I2(lowCL3[9]),
        .I3(lowCL3[6]),
        .O(\lowCL3_reg[7]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1707" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__14 
       (.I0(lowCL3[1]),
        .I1(lowCL3[2]),
        .I2(lowCL3[3]),
        .I3(lowCL3[0]),
        .O(\lowCL3_reg[1]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1627" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__2 
       (.I0(uppCL3[25]),
        .I1(uppCL3[26]),
        .I2(uppCL3[27]),
        .I3(uppCL3[24]),
        .O(\uppCL3_reg[25]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1587" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [0]),
        .I1(\uppCL3_reg[45]_0 [1]),
        .I2(\uppCL3_reg[45]_0 [2]),
        .I3(uppCL3[6]),
        .O(\uppCL3_reg[7]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1595" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [3]),
        .I1(\uppCL3_reg[45]_0 [4]),
        .I2(\uppCL3_reg[45]_0 [5]),
        .I3(uppCL3[42]),
        .O(\uppCL3_reg[43]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1635" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__5 
       (.I0(lowCL3[43]),
        .I1(lowCL3[44]),
        .I2(lowCL3[45]),
        .I3(lowCL3[42]),
        .O(\lowCL3_reg[43]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1643" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__6 
       (.I0(uppCL3[1]),
        .I1(uppCL3[2]),
        .I2(uppCL3[3]),
        .I3(uppCL3[0]),
        .O(\uppCL3_reg[1]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1651" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__7 
       (.I0(uppCL3[31]),
        .I1(uppCL3[32]),
        .I2(uppCL3[33]),
        .I3(uppCL3[30]),
        .O(\uppCL3_reg[31]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1659" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__8 
       (.I0(lowCL3[31]),
        .I1(lowCL3[32]),
        .I2(lowCL3[33]),
        .I3(lowCL3[30]),
        .O(\lowCL3_reg[31]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1667" *) 
  LUT4 #(
    .INIT(16'h40C0)) 
    \rsMask[7][2]_i_1__9 
       (.I0(lowCL3[25]),
        .I1(lowCL3[26]),
        .I2(lowCL3[27]),
        .I3(lowCL3[24]),
        .O(\lowCL3_reg[25]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair2106" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1 
       (.I0(uppCL3[38]),
        .I1(uppCL3[39]),
        .O(\uppCL3_reg[38]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2114" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__0 
       (.I0(uppCL3[20]),
        .I1(uppCL3[21]),
        .O(\uppCL3_reg[20]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2122" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__1 
       (.I0(uppCL3[14]),
        .I1(uppCL3[15]),
        .O(\uppCL3_reg[14]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2178" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__10 
       (.I0(lowCL3[38]),
        .I1(lowCL3[39]),
        .O(\lowCL3_reg[38]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2186" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__11 
       (.I0(lowCL3[20]),
        .I1(lowCL3[21]),
        .O(\lowCL3_reg[20]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2194" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__12 
       (.I0(lowCL3[14]),
        .I1(lowCL3[15]),
        .O(\lowCL3_reg[14]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2202" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__13 
       (.I0(lowCL3[8]),
        .I1(lowCL3[9]),
        .O(\lowCL3_reg[8]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2210" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__14 
       (.I0(lowCL3[2]),
        .I1(lowCL3[3]),
        .O(\lowCL3_reg[2]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2130" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__2 
       (.I0(uppCL3[26]),
        .I1(uppCL3[27]),
        .O(\uppCL3_reg[26]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2095" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [1]),
        .I1(\uppCL3_reg[45]_0 [2]),
        .O(\uppCL3_reg[8]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2099" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [4]),
        .I1(\uppCL3_reg[45]_0 [5]),
        .O(\uppCL3_reg[44]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2138" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__5 
       (.I0(lowCL3[44]),
        .I1(lowCL3[45]),
        .O(\lowCL3_reg[44]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2146" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__6 
       (.I0(uppCL3[2]),
        .I1(uppCL3[3]),
        .O(\uppCL3_reg[2]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2154" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__7 
       (.I0(uppCL3[32]),
        .I1(uppCL3[33]),
        .O(\uppCL3_reg[32]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2162" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__8 
       (.I0(lowCL3[32]),
        .I1(lowCL3[33]),
        .O(\lowCL3_reg[32]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2170" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \rsMask[7][3]_i_1__9 
       (.I0(lowCL3[26]),
        .I1(lowCL3[27]),
        .O(\lowCL3_reg[26]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1967" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1 
       (.I0(uppCL3[36]),
        .I1(uppCL3[38]),
        .I2(uppCL3[37]),
        .O(\uppCL3_reg[36]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1971" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__0 
       (.I0(uppCL3[18]),
        .I1(uppCL3[20]),
        .I2(uppCL3[19]),
        .O(\uppCL3_reg[18]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1975" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__1 
       (.I0(uppCL3[12]),
        .I1(uppCL3[14]),
        .I2(uppCL3[13]),
        .O(\uppCL3_reg[12]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2011" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__10 
       (.I0(lowCL3[36]),
        .I1(lowCL3[38]),
        .I2(lowCL3[37]),
        .O(\lowCL3_reg[36]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2015" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__11 
       (.I0(lowCL3[18]),
        .I1(lowCL3[20]),
        .I2(lowCL3[19]),
        .O(\lowCL3_reg[18]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2019" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__12 
       (.I0(lowCL3[12]),
        .I1(lowCL3[14]),
        .I2(lowCL3[13]),
        .O(\lowCL3_reg[12]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2023" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__13 
       (.I0(lowCL3[6]),
        .I1(lowCL3[8]),
        .I2(lowCL3[7]),
        .O(\lowCL3_reg[6]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2027" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__14 
       (.I0(lowCL3[0]),
        .I1(lowCL3[2]),
        .I2(lowCL3[1]),
        .O(\lowCL3_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1979" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__2 
       (.I0(uppCL3[24]),
        .I1(uppCL3[26]),
        .I2(uppCL3[25]),
        .O(\uppCL3_reg[24]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1983" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__3 
       (.I0(uppCL3[6]),
        .I1(\uppCL3_reg[45]_0 [1]),
        .I2(\uppCL3_reg[45]_0 [0]),
        .O(\uppCL3_reg[6]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1987" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__4 
       (.I0(uppCL3[42]),
        .I1(\uppCL3_reg[45]_0 [4]),
        .I2(\uppCL3_reg[45]_0 [3]),
        .O(\uppCL3_reg[42]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1991" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__5 
       (.I0(lowCL3[42]),
        .I1(lowCL3[44]),
        .I2(lowCL3[43]),
        .O(\lowCL3_reg[42]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1995" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__6 
       (.I0(uppCL3[0]),
        .I1(uppCL3[2]),
        .I2(uppCL3[1]),
        .O(\uppCL3_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1999" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__7 
       (.I0(uppCL3[30]),
        .I1(uppCL3[32]),
        .I2(uppCL3[31]),
        .O(\uppCL3_reg[30]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2003" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__8 
       (.I0(lowCL3[30]),
        .I1(lowCL3[32]),
        .I2(lowCL3[31]),
        .O(\lowCL3_reg[30]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2007" *) 
  LUT3 #(
    .INIT(8'hC1)) 
    \rsMask[7][4]_i_1__9 
       (.I0(lowCL3[24]),
        .I1(lowCL3[26]),
        .I2(lowCL3[25]),
        .O(\lowCL3_reg[24]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1711" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1 
       (.I0(uppCL3[37]),
        .I1(uppCL3[38]),
        .I2(uppCL3[39]),
        .O(\uppCL3_reg[37]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1715" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__0 
       (.I0(uppCL3[19]),
        .I1(uppCL3[20]),
        .I2(uppCL3[21]),
        .O(\uppCL3_reg[19]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1719" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__1 
       (.I0(uppCL3[13]),
        .I1(uppCL3[14]),
        .I2(uppCL3[15]),
        .O(\uppCL3_reg[13]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1755" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__10 
       (.I0(lowCL3[13]),
        .I1(lowCL3[14]),
        .I2(lowCL3[15]),
        .O(\lowCL3_reg[13]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1759" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__11 
       (.I0(lowCL3[7]),
        .I1(lowCL3[8]),
        .I2(lowCL3[9]),
        .O(\lowCL3_reg[7]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1763" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__12 
       (.I0(lowCL3[1]),
        .I1(lowCL3[2]),
        .I2(lowCL3[3]),
        .O(\lowCL3_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1723" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__2 
       (.I0(uppCL3[25]),
        .I1(uppCL3[26]),
        .I2(uppCL3[27]),
        .O(\uppCL3_reg[25]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1727" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__3 
       (.I0(lowCL3[43]),
        .I1(lowCL3[44]),
        .I2(lowCL3[45]),
        .O(\lowCL3_reg[43]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1731" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__4 
       (.I0(uppCL3[1]),
        .I1(uppCL3[2]),
        .I2(uppCL3[3]),
        .O(\uppCL3_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1735" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__5 
       (.I0(uppCL3[31]),
        .I1(uppCL3[32]),
        .I2(uppCL3[33]),
        .O(\uppCL3_reg[31]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1739" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__6 
       (.I0(lowCL3[31]),
        .I1(lowCL3[32]),
        .I2(lowCL3[33]),
        .O(\lowCL3_reg[31]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1743" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__7 
       (.I0(lowCL3[25]),
        .I1(lowCL3[26]),
        .I2(lowCL3[27]),
        .O(\lowCL3_reg[25]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1747" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__8 
       (.I0(lowCL3[37]),
        .I1(lowCL3[38]),
        .I2(lowCL3[39]),
        .O(\lowCL3_reg[37]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1751" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rsMask[7][5]_i_1__9 
       (.I0(lowCL3[19]),
        .I1(lowCL3[20]),
        .I2(lowCL3[21]),
        .O(\lowCL3_reg[19]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1851" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1 
       (.I0(uppCL3[37]),
        .I1(uppCL3[38]),
        .I2(uppCL3[36]),
        .O(\uppCL3_reg[37]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1859" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__0 
       (.I0(uppCL3[19]),
        .I1(uppCL3[20]),
        .I2(uppCL3[18]),
        .O(\uppCL3_reg[19]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1867" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__1 
       (.I0(uppCL3[13]),
        .I1(uppCL3[14]),
        .I2(uppCL3[12]),
        .O(\uppCL3_reg[13]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1923" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__10 
       (.I0(lowCL3[37]),
        .I1(lowCL3[38]),
        .I2(lowCL3[36]),
        .O(\lowCL3_reg[37]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1931" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__11 
       (.I0(lowCL3[19]),
        .I1(lowCL3[20]),
        .I2(lowCL3[18]),
        .O(\lowCL3_reg[19]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1939" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__12 
       (.I0(lowCL3[13]),
        .I1(lowCL3[14]),
        .I2(lowCL3[12]),
        .O(\lowCL3_reg[13]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1947" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__13 
       (.I0(lowCL3[7]),
        .I1(lowCL3[8]),
        .I2(lowCL3[6]),
        .O(\lowCL3_reg[7]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1955" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__14 
       (.I0(lowCL3[1]),
        .I1(lowCL3[2]),
        .I2(lowCL3[0]),
        .O(\lowCL3_reg[1]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1875" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__2 
       (.I0(uppCL3[25]),
        .I1(uppCL3[26]),
        .I2(uppCL3[24]),
        .O(\uppCL3_reg[25]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1839" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__3 
       (.I0(\uppCL3_reg[45]_0 [0]),
        .I1(\uppCL3_reg[45]_0 [1]),
        .I2(uppCL3[6]),
        .O(\uppCL3_reg[7]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1843" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__4 
       (.I0(\uppCL3_reg[45]_0 [3]),
        .I1(\uppCL3_reg[45]_0 [4]),
        .I2(uppCL3[42]),
        .O(\uppCL3_reg[43]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1883" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__5 
       (.I0(lowCL3[43]),
        .I1(lowCL3[44]),
        .I2(lowCL3[42]),
        .O(\lowCL3_reg[43]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1891" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__6 
       (.I0(uppCL3[1]),
        .I1(uppCL3[2]),
        .I2(uppCL3[0]),
        .O(\uppCL3_reg[1]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1899" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__7 
       (.I0(uppCL3[31]),
        .I1(uppCL3[32]),
        .I2(uppCL3[30]),
        .O(\uppCL3_reg[31]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1907" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__8 
       (.I0(lowCL3[31]),
        .I1(lowCL3[32]),
        .I2(lowCL3[30]),
        .O(\lowCL3_reg[31]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1915" *) 
  LUT3 #(
    .INIT(8'h36)) 
    \rsMask[7][8]_i_1__9 
       (.I0(lowCL3[25]),
        .I1(lowCL3[26]),
        .I2(lowCL3[24]),
        .O(\lowCL3_reg[25]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair2107" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1 
       (.I0(uppCL3[37]),
        .I1(uppCL3[38]),
        .O(\uppCL3_reg[37]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2115" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__0 
       (.I0(uppCL3[19]),
        .I1(uppCL3[20]),
        .O(\uppCL3_reg[19]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2123" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__1 
       (.I0(uppCL3[13]),
        .I1(uppCL3[14]),
        .O(\uppCL3_reg[13]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2195" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__10 
       (.I0(lowCL3[13]),
        .I1(lowCL3[14]),
        .O(\lowCL3_reg[13]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2203" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__11 
       (.I0(lowCL3[7]),
        .I1(lowCL3[8]),
        .O(\lowCL3_reg[7]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2211" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__12 
       (.I0(lowCL3[1]),
        .I1(lowCL3[2]),
        .O(\lowCL3_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2131" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__2 
       (.I0(uppCL3[25]),
        .I1(uppCL3[26]),
        .O(\uppCL3_reg[25]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2139" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__3 
       (.I0(lowCL3[43]),
        .I1(lowCL3[44]),
        .O(\lowCL3_reg[43]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2147" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__4 
       (.I0(uppCL3[1]),
        .I1(uppCL3[2]),
        .O(\uppCL3_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2155" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__5 
       (.I0(uppCL3[31]),
        .I1(uppCL3[32]),
        .O(\uppCL3_reg[31]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2163" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__6 
       (.I0(lowCL3[31]),
        .I1(lowCL3[32]),
        .O(\lowCL3_reg[31]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2171" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__7 
       (.I0(lowCL3[25]),
        .I1(lowCL3[26]),
        .O(\lowCL3_reg[25]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2179" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__8 
       (.I0(lowCL3[37]),
        .I1(lowCL3[38]),
        .O(\lowCL3_reg[37]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2187" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rsMask[7][9]_i_1__9 
       (.I0(lowCL3[19]),
        .I1(lowCL3[20]),
        .O(\lowCL3_reg[19]_0 ));
  (* KEEP = "yes" *) 
  FDRE rst_r1_reg
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(SR),
        .Q(rst_r1),
        .R(1'b0));
  FDRE t1_reg
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(bramB_en),
        .Q(t1),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    t2_reg
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(t1),
        .Q(t2),
        .R(1'b0));
  ddr4_0_ddr4_v2_2_17_cal_addr_decode u_ddr_cal_addr_decode
       (.D(D),
        .DMOut(DMOut),
        .DQOut(DQOut),
        .E(E),
        .O(O),
        .Q({\calSt_reg_n_0_[3] ,\calSt_reg_n_0_[2] ,\calSt_reg_n_0_[1] ,\calSt_reg_n_0_[0] }),
        .S(S),
        .SR(SR),
        .\SYNC[0].sync_reg_reg[1] (\SYNC[0].sync_reg_reg[1] ),
        .\SYNC[0].sync_reg_reg[1]_0 (\SYNC[0].sync_reg_reg[1]_0 ),
        .\SYNC[18].sync_reg_reg[1] (\SYNC[18].sync_reg_reg[1] ),
        .\SYNC[20].sync_reg_reg[1] (\SYNC[20].sync_reg_reg[1] ),
        .\SYNC[3].sync_reg_reg[1] (\SYNC[3].sync_reg_reg[1] ),
        .\SYNC[3].sync_reg_reg[1]_0 (\SYNC[3].sync_reg_reg[1]_0 ),
        .\SYNC[3].sync_reg_reg[1]_1 (\SYNC[3].sync_reg_reg[1]_1 ),
        .\SYNC[3].sync_reg_reg[1]_10 (\SYNC[3].sync_reg_reg[1]_10 ),
        .\SYNC[3].sync_reg_reg[1]_11 (\SYNC[3].sync_reg_reg[1]_11 ),
        .\SYNC[3].sync_reg_reg[1]_12 (\SYNC[3].sync_reg_reg[1]_12 ),
        .\SYNC[3].sync_reg_reg[1]_13 (\SYNC[3].sync_reg_reg[1]_13 ),
        .\SYNC[3].sync_reg_reg[1]_14 (\SYNC[3].sync_reg_reg[1]_14 ),
        .\SYNC[3].sync_reg_reg[1]_15 (\SYNC[3].sync_reg_reg[1]_15 ),
        .\SYNC[3].sync_reg_reg[1]_16 (\SYNC[3].sync_reg_reg[1]_16 ),
        .\SYNC[3].sync_reg_reg[1]_17 (\SYNC[3].sync_reg_reg[1]_17 ),
        .\SYNC[3].sync_reg_reg[1]_18 (\SYNC[3].sync_reg_reg[1]_18 ),
        .\SYNC[3].sync_reg_reg[1]_19 (\SYNC[3].sync_reg_reg[1]_19 ),
        .\SYNC[3].sync_reg_reg[1]_2 (\SYNC[3].sync_reg_reg[1]_2 ),
        .\SYNC[3].sync_reg_reg[1]_20 (\SYNC[3].sync_reg_reg[1]_20 ),
        .\SYNC[3].sync_reg_reg[1]_21 (\SYNC[3].sync_reg_reg[1]_21 ),
        .\SYNC[3].sync_reg_reg[1]_22 (\SYNC[3].sync_reg_reg[1]_22 ),
        .\SYNC[3].sync_reg_reg[1]_23 (\SYNC[3].sync_reg_reg[1]_23 ),
        .\SYNC[3].sync_reg_reg[1]_24 (\SYNC[3].sync_reg_reg[1]_24 ),
        .\SYNC[3].sync_reg_reg[1]_25 (\SYNC[3].sync_reg_reg[1]_25 ),
        .\SYNC[3].sync_reg_reg[1]_26 (\SYNC[3].sync_reg_reg[1]_26 ),
        .\SYNC[3].sync_reg_reg[1]_27 (\SYNC[3].sync_reg_reg[1]_27 ),
        .\SYNC[3].sync_reg_reg[1]_28 (\SYNC[3].sync_reg_reg[1]_28 ),
        .\SYNC[3].sync_reg_reg[1]_29 (\SYNC[3].sync_reg_reg[1]_29 ),
        .\SYNC[3].sync_reg_reg[1]_3 (\SYNC[3].sync_reg_reg[1]_3 ),
        .\SYNC[3].sync_reg_reg[1]_30 (\SYNC[3].sync_reg_reg[1]_30 ),
        .\SYNC[3].sync_reg_reg[1]_31 (\SYNC[3].sync_reg_reg[1]_31 ),
        .\SYNC[3].sync_reg_reg[1]_32 (\SYNC[3].sync_reg_reg[1]_32 ),
        .\SYNC[3].sync_reg_reg[1]_33 (\SYNC[3].sync_reg_reg[1]_33 ),
        .\SYNC[3].sync_reg_reg[1]_34 (\SYNC[3].sync_reg_reg[1]_34 ),
        .\SYNC[3].sync_reg_reg[1]_35 (\SYNC[3].sync_reg_reg[1]_35 ),
        .\SYNC[3].sync_reg_reg[1]_36 (\SYNC[3].sync_reg_reg[1]_36 ),
        .\SYNC[3].sync_reg_reg[1]_37 (\SYNC[3].sync_reg_reg[1]_37 ),
        .\SYNC[3].sync_reg_reg[1]_38 (\SYNC[3].sync_reg_reg[1]_38 ),
        .\SYNC[3].sync_reg_reg[1]_39 (\SYNC[3].sync_reg_reg[1]_39 ),
        .\SYNC[3].sync_reg_reg[1]_4 (\SYNC[3].sync_reg_reg[1]_4 ),
        .\SYNC[3].sync_reg_reg[1]_40 (\SYNC[3].sync_reg_reg[1]_40 ),
        .\SYNC[3].sync_reg_reg[1]_41 (\SYNC[3].sync_reg_reg[1]_41 ),
        .\SYNC[3].sync_reg_reg[1]_42 (\SYNC[3].sync_reg_reg[1]_42 ),
        .\SYNC[3].sync_reg_reg[1]_43 (\SYNC[3].sync_reg_reg[1]_43 ),
        .\SYNC[3].sync_reg_reg[1]_44 (\SYNC[3].sync_reg_reg[1]_44 ),
        .\SYNC[3].sync_reg_reg[1]_45 (\SYNC[3].sync_reg_reg[1]_45 ),
        .\SYNC[3].sync_reg_reg[1]_5 (\SYNC[3].sync_reg_reg[1]_5 ),
        .\SYNC[3].sync_reg_reg[1]_6 (\SYNC[3].sync_reg_reg[1]_6 ),
        .\SYNC[3].sync_reg_reg[1]_7 (\SYNC[3].sync_reg_reg[1]_7 ),
        .\SYNC[3].sync_reg_reg[1]_8 (\SYNC[3].sync_reg_reg[1]_8 ),
        .\SYNC[3].sync_reg_reg[1]_9 (\SYNC[3].sync_reg_reg[1]_9 ),
        .\SYNC[4].sync_reg_reg[1] (\SYNC[4].sync_reg_reg[1] ),
        .\SYNC[4].sync_reg_reg[1]_0 (\SYNC[4].sync_reg_reg[1]_0 ),
        .\SYNC[5].sync_reg_reg[1] (\SYNC[5].sync_reg_reg[1] ),
        .\SYNC[5].sync_reg_reg[1]_0 (\SYNC[5].sync_reg_reg[1]_0 ),
        .\SYNC[5].sync_reg_reg[1]_1 (\SYNC[5].sync_reg_reg[1]_1 ),
        .\SYNC[5].sync_reg_reg[1]_10 (\SYNC[5].sync_reg_reg[1]_10 ),
        .\SYNC[5].sync_reg_reg[1]_11 (\SYNC[5].sync_reg_reg[1]_11 ),
        .\SYNC[5].sync_reg_reg[1]_12 (\SYNC[5].sync_reg_reg[1]_12 ),
        .\SYNC[5].sync_reg_reg[1]_13 (\SYNC[5].sync_reg_reg[1]_13 ),
        .\SYNC[5].sync_reg_reg[1]_14 (\SYNC[5].sync_reg_reg[1]_14 ),
        .\SYNC[5].sync_reg_reg[1]_15 (\SYNC[5].sync_reg_reg[1]_15 ),
        .\SYNC[5].sync_reg_reg[1]_16 (\SYNC[5].sync_reg_reg[1]_16 ),
        .\SYNC[5].sync_reg_reg[1]_17 (\SYNC[5].sync_reg_reg[1]_17 ),
        .\SYNC[5].sync_reg_reg[1]_2 (\SYNC[5].sync_reg_reg[1]_2 ),
        .\SYNC[5].sync_reg_reg[1]_3 (\SYNC[5].sync_reg_reg[1]_3 ),
        .\SYNC[5].sync_reg_reg[1]_4 (\SYNC[5].sync_reg_reg[1]_4 ),
        .\SYNC[5].sync_reg_reg[1]_5 (\SYNC[5].sync_reg_reg[1]_5 ),
        .\SYNC[5].sync_reg_reg[1]_6 (\SYNC[5].sync_reg_reg[1]_6 ),
        .\SYNC[5].sync_reg_reg[1]_7 (\SYNC[5].sync_reg_reg[1]_7 ),
        .\SYNC[5].sync_reg_reg[1]_8 (\SYNC[5].sync_reg_reg[1]_8 ),
        .\SYNC[5].sync_reg_reg[1]_9 (\SYNC[5].sync_reg_reg[1]_9 ),
        .a_b_cmd_sel_start0(a_b_cmd_sel_start0),
        .a_b_cmd_sel_start_reg_0(a_b_cmd_sel_start_reg),
        .a_b_cmd_sel_start_reg_1(a_b_cmd_sel_start_reg_0),
        .\addr_dec_to_mb_data[0]_i_3 (\addr_dec_to_mb_data[0]_i_3 ),
        .\addr_dec_to_mb_data[31]_i_3 (\addr_dec_to_mb_data[31]_i_3 ),
        .\addr_dec_to_mb_data[4]_i_11 (\addr_dec_to_mb_data[4]_i_11 ),
        .\addr_dec_to_mb_data[6]_i_7 (\addr_dec_to_mb_data[6]_i_7 ),
        .\addr_dec_to_mb_data[6]_i_7_0 (\addr_dec_to_mb_data[6]_i_7_0 ),
        .\addr_dec_to_mb_data[7]_i_7_0 (\addr_dec_to_mb_data[7]_i_7 ),
        .\addr_dec_to_mb_data_reg[12]_0 (\addr_dec_to_mb_data_reg[12] ),
        .\addr_dec_to_mb_data_reg[14]_0 (\addr_dec_to_mb_data_reg[14] ),
        .\addr_dec_to_mb_data_reg[15]_0 (\addr_dec_to_mb_data_reg[15] ),
        .\addr_dec_to_mb_data_reg[19]_0 (\addr_dec_to_mb_data_reg[19] ),
        .\addr_dec_to_mb_data_reg[20]_0 (\addr_dec_to_mb_data_reg[20] ),
        .\addr_dec_to_mb_data_reg[21]_0 (\addr_dec_to_mb_data_reg[21] ),
        .\addr_dec_to_mb_data_reg[22]_0 (\addr_dec_to_mb_data_reg[22] ),
        .\addr_dec_to_mb_data_reg[23]_0 (\addr_dec_to_mb_data_reg[23] ),
        .\addr_dec_to_mb_data_reg[24]_0 (\addr_dec_to_mb_data_reg[24] ),
        .\addr_dec_to_mb_data_reg[25]_0 (\addr_dec_to_mb_data_reg[25] ),
        .\addr_dec_to_mb_data_reg[26]_0 (\addr_dec_to_mb_data_reg[26] ),
        .\addr_dec_to_mb_data_reg[27]_0 (\addr_dec_to_mb_data_reg[27] ),
        .\addr_dec_to_mb_data_reg[28]_0 (\addr_dec_to_mb_data_reg[28] ),
        .\addr_dec_to_mb_data_reg[29]_0 (\addr_dec_to_mb_data_reg[29] ),
        .\addr_dec_to_mb_data_reg[29]_1 (\addr_dec_to_mb_data_reg[29]_0 ),
        .\addr_dec_to_mb_data_reg[29]_2 (\addr_dec_to_mb_data_reg[29]_1 ),
        .\addr_dec_to_mb_data_reg[29]_3 (\addr_dec_to_mb_data_reg[29]_2 ),
        .\addr_dec_to_mb_data_reg[29]_4 (\addr_dec_to_mb_data_reg[29]_3 ),
        .\addr_dec_to_mb_data_reg[29]_5 (\addr_dec_to_mb_data_reg[29]_4 ),
        .\addr_dec_to_mb_data_reg[30]_0 (\addr_dec_to_mb_data_reg[30] ),
        .\addr_dec_to_mb_data_reg[30]_1 (\addr_dec_to_mb_data_reg[30]_0 ),
        .\addr_dec_to_mb_data_reg[31]_0 (\addr_dec_to_mb_data_reg[31] ),
        .\bisc_bit_reg[0]_0 (\bisc_bit_reg[0] ),
        .bisc_byte(bisc_byte),
        .calDone_reg_0(calDone_reg_0),
        .calDone_reg_1(mcalRdCAS),
        .calDone_reg_10(calDone_reg_9),
        .calDone_reg_11(calDone_reg_10),
        .calDone_reg_12(calDone_reg_11),
        .calDone_reg_13(calDone_reg_12),
        .calDone_reg_14(calDone_reg_14),
        .calDone_reg_2(mcalCasSlot),
        .calDone_reg_3(calDone_reg_2),
        .calDone_reg_4(calDone_reg_3),
        .calDone_reg_5(calDone_reg_4),
        .calDone_reg_6(calDone_reg_5),
        .calDone_reg_7(calDone_reg_6),
        .calDone_reg_8(calDone_reg_7),
        .calDone_reg_9(calDone_reg_8),
        .\calSt_reg[0] (u_ddr_cal_addr_decode_n_51),
        .\calSt_reg[2] (u_ddr_cal_addr_decode_n_50),
        .\cal_ACT_n_A_reg[7]_0 (\cal_ACT_n_A_reg[7] ),
        .\cal_ACT_n_pre_reg[7]_0 (\cal_ACT_n_pre_reg[7] ),
        .\cal_ADR_A_reg[0]_0 (\cal_ADR_A_reg[0] ),
        .\cal_ADR_A_reg[0]_1 (\cal_ADR_A_reg[0]_0 ),
        .\cal_ADR_A_reg[1]_0 (\cal_ADR_A_reg[1] ),
        .\cal_ADR_A_reg[20]_0 (\cal_ADR_A_reg[20] ),
        .\cal_ADR_A_reg[21]_0 (\cal_ADR_A_reg[21] ),
        .\cal_ADR_A_reg[22]_0 (\cal_ADR_A_reg[22] ),
        .\cal_ADR_A_reg[26]_0 (\cal_ADR_A_reg[26] ),
        .\cal_ADR_A_reg[27]_0 (\cal_ADR_A_reg[27] ),
        .\cal_ADR_A_reg[29]_0 (\cal_ADR_A_reg[29] ),
        .\cal_ADR_A_reg[2]_0 (\cal_ADR_A_reg[2] ),
        .\cal_ADR_A_reg[30]_0 (\cal_ADR_A_reg[30] ),
        .\cal_ADR_A_reg[31]_0 (\cal_ADR_A_reg[31] ),
        .\cal_ADR_A_reg[3]_0 (\cal_ADR_A_reg[3] ),
        .\cal_ADR_A_reg[4]_0 (\cal_ADR_A_reg[4] ),
        .\cal_ADR_A_reg[4]_1 (\cal_ADR_A_reg[4]_0 ),
        .\cal_ADR_B_reg[10]_0 (\cal_ADR_B_reg[10] ),
        .\cal_ADR_B_reg[11]_0 (\cal_ADR_B_reg[11] ),
        .\cal_ADR_B_reg[12]_0 (\cal_ADR_B_reg[12] ),
        .\cal_ADR_B_reg[13]_0 (\cal_ADR_B_reg[13] ),
        .\cal_ADR_B_reg[15]_0 (\cal_ADR_B_reg[15] ),
        .\cal_ADR_B_reg[17]_0 (\cal_ADR_B_reg[17] ),
        .\cal_ADR_B_reg[18]_0 (\cal_ADR_B_reg[18] ),
        .\cal_ADR_B_reg[19]_0 (\cal_ADR_B_reg[19] ),
        .\cal_ADR_B_reg[24]_0 (\cal_ADR_B_reg[24] ),
        .\cal_ADR_B_reg[25]_0 (\cal_ADR_B_reg[25] ),
        .\cal_ADR_B_reg[30]_0 (\cal_ADR_B_reg[30] ),
        .\cal_ADR_B_reg[31]_0 (\cal_ADR_B_reg[31] ),
        .\cal_ADR_B_reg[31]_1 (\cal_ADR_B_reg[31]_0 ),
        .\cal_CAS_A_reg[0]_0 (\cal_CAS_A_reg[0] ),
        .\cal_CS_A_reg[0]_0 (\cal_CS_A_reg[0] ),
        .\cal_CS_A_reg[4]_0 (\cal_CS_A_reg[4] ),
        .\cal_CS_A_reg[5]_0 (\cal_CS_A_reg[5] ),
        .\cal_CS_A_reg[6]_0 (\cal_CS_A_reg[6] ),
        .\cal_CS_A_reg[7]_0 (\cal_CS_A_reg[7] ),
        .\cal_CS_A_reg[7]_1 (\cal_CS_A_reg[7]_0 ),
        .\cal_CS_B_reg[5]_0 (\cal_CS_B_reg[5] ),
        .\cal_CS_B_reg[7]_0 (\cal_CS_B_reg[7] ),
        .cal_CS_n(cal_CS_n),
        .\cal_DMOut_n_A_reg[31]_0 (\cal_DMOut_n_A_reg[31] ),
        .\cal_DQOut_A_reg[31]_0 (\cal_DQOut_A_reg[31] ),
        .\cal_DQOut_A_reg[63]_0 (\cal_DQOut_A_reg[63] ),
        .\cal_DQOut_post_reg[31]_0 (\cal_DQOut_post_reg[31] ),
        .\cal_DQOut_post_reg[63]_0 (\cal_DQOut_post_reg[63] ),
        .\cal_DQOut_pre_reg[31]_0 (\cal_DQOut_pre_reg[31] ),
        .\cal_DQOut_pre_reg[63]_0 (\cal_DQOut_pre_reg[63] ),
        .\cal_DQPat_A_reg[31]_0 (\cal_DQPat_A_reg[31] ),
        .\cal_DQPat_A_reg[63]_0 (\cal_DQPat_A_reg[63] ),
        .\cal_DQPat_B_reg[31]_0 (\cal_DQPat_B_reg[31] ),
        .\cal_DQPat_B_reg[63]_0 (\cal_DQPat_B_reg[63] ),
        .\cal_RAS_B_reg[0]_0 (\cal_RAS_B_reg[0] ),
        .\cal_RAS_pre_reg[1]_0 (\cal_RAS_pre_reg[1] ),
        .\cal_RAS_pre_reg[2]_0 (\cal_RAS_pre_reg[2] ),
        .\cal_RST_CKE_ODT_PAR_reg[16]_0 (\cal_RST_CKE_ODT_PAR_reg[16] ),
        .\cal_RST_CKE_ODT_PAR_reg[16]_1 (\cal_RST_CKE_ODT_PAR_reg[16]_0 ),
        .\cal_RST_CKE_ODT_PAR_reg[30]_0 (\cal_RST_CKE_ODT_PAR_reg[30] ),
        .\cal_RST_CKE_ODT_PAR_reg[31]_0 (\cal_RST_CKE_ODT_PAR_reg[31] ),
        .\cal_RST_CKE_ODT_PAR_reg[7]_0 (\cal_RST_CKE_ODT_PAR_reg[7] ),
        .\cal_RST_CKE_ODT_PAR_reg[9]_0 (\cal_RST_CKE_ODT_PAR_reg[9] ),
        .cal_clear_fifo_rden(cal_clear_fifo_rden),
        .\cal_cmp_en_reg[7]_0 (\cal_cmp_en_reg[7] ),
        .\cal_cs_pos_reg[1]_0 (\cal_cs_pos_reg[1] ),
        .cal_oe_dis_low(cal_oe_dis_low),
        .\cal_oe_dis_low_reg[7]_0 (\cal_oe_dis_low_reg[7] ),
        .cal_oe_dis_upp(cal_oe_dis_upp),
        .\cal_oe_dis_upp_reg[7]_0 (\cal_oe_dis_upp_reg[7] ),
        .\cal_seq_a_a_dly_reg[7]_0 (\cal_seq_a_a_dly_reg[7] ),
        .\cal_seq_a_b_dly_reg[7]_0 (\cal_seq_a_b_dly_reg[7] ),
        .\cal_seq_b_a_dly_reg[7]_0 (\cal_seq_b_a_dly_reg[7] ),
        .cal_seq_cnt_gt_0_reg_0(cal_seq_cnt_gt_0_reg),
        .\cal_seq_cnt_reg[13]_0 (\cal_seq_cnt_reg[13] ),
        .\cal_seq_cnt_reg[31]_0 (\cal_seq_cnt_reg[31] ),
        .\cal_seq_rd_cnt_reg[7]_0 (\cal_seq_rd_cnt_reg[7] ),
        .\cal_seq_reg[2]_0 (\cal_seq_reg[2] ),
        .cal_timer_reg(cal_timer_reg),
        .\cal_timer_reg[0]_0 (cal_timer_reg_0_sn_1),
        .\cal_timer_reg[15]_0 (\cal_timer_reg[15] ),
        .\cal_timer_reg[21]_0 (cal_timer_reg_21_sn_1),
        .\cal_timer_reg[23]_0 (\cal_timer_reg[23] ),
        .\cal_timer_reg[24]_0 (cal_timer_reg_24_sn_1),
        .\cal_timer_reg[25]_0 (cal_timer_reg_25_sn_1),
        .\cal_timer_reg[28]_0 (cal_timer_reg_28_sn_1),
        .\cal_timer_reg[29]_0 (cal_timer_reg_29_sn_1),
        .\cal_timer_reg[31]_0 (\cal_timer_reg[31] ),
        .\clb2phy_wrcs0_low_reg[31]_0 (\clb2phy_wrcs0_low_reg[31] ),
        .clear_gt_data_ready_flag(clear_gt_data_ready_flag),
        .clear_gt_data_ready_flag_reg_0(clear_gt_data_ready_flag_reg),
        .\cmp_byte_reg[2]_0 (\cmp_byte_reg[2] ),
        .cnt_clr_access(cnt_clr_access),
        .cnt_clr_reg_0(cnt_clr_reg),
        .cnt_clr_reg_1(cnt_clr_reg_0),
        .\cplx_CAS_reg[6] (\cplx_CAS_reg[6] ),
        .\cplx_RAS_reg[6] (\cplx_RAS_reg[6] ),
        .\cplx_RAS_reg[6]_0 (\cplx_RAS_reg[6]_0 ),
        .cplx_cal_reg(cplx_cal_reg),
        .\cplx_config_reg[0]_0 (\cplx_config_reg[0] ),
        .\cplx_config_reg[16]_0 (\cplx_config_reg[16] ),
        .\cplx_config_reg[16]_1 (\cplx_config_reg[16]_0 ),
        .\cplx_config_reg[1]_0 (\cplx_config_reg[1] ),
        .\cplx_error_accum_reg[14] (\cplx_error_accum_reg[14] ),
        .\cplx_error_accum_reg[15] (\cplx_error_accum_reg[15] ),
        .\cplx_error_accum_reg[19] (\cplx_error_accum_reg[19] ),
        .\cplx_error_accum_reg[44] (\cplx_error_accum_reg[44] ),
        .\cplx_error_accum_reg[63] (\cplx_error_accum_reg[63] ),
        .cplx_status(cplx_status),
        .\dReg_reg[10] (\dReg_reg[10] ),
        .\dReg_reg[11] (\dReg_reg[11] ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_0 ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_1 ),
        .\dReg_reg[15] (\dReg_reg[15] ),
        .\dReg_reg[8] (\dReg_reg[8] ),
        .\dReg_reg[8]_0 (\dReg_reg[8]_0 ),
        .\dReg_reg[9] (\dReg_reg[9] ),
        .\dReg_reg[9]_0 (\dReg_reg[9]_0 ),
        .\dReg_reg[9]_1 (\dReg_reg[9]_1 ),
        .\delay_cntr_reg[2]_0 (\delay_cntr_reg[2] ),
        .douta(douta[8]),
        .\dqin_valid_shift_reg[0]_0 (\dqin_valid_shift_reg[0] ),
        .en_vtc(en_vtc),
        .\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 (\genblk10[3].cal_DMOut_n_A_r_reg[24] ),
        .\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 (\genblk10[6].cal_DMOut_n_A_r_reg[48] ),
        .\genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8]_0 (\genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8] ),
        .\genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9]_0 (\genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9] ),
        .gt_data_ready_flag(gt_data_ready_flag),
        .gt_data_ready_flag_nxt(gt_data_ready_flag_nxt),
        .gt_data_ready_flag_reg_0(gt_data_ready_flag_reg),
        .in0(in0),
        .\init_cal_BA_reg[15] (\init_cal_BA_reg[15]_0 ),
        .\init_cal_BA_reg[7] (\init_cal_BA_reg[7]_0 ),
        .init_cal_BG(init_cal_BG),
        .\init_cal_BG_reg[7] (\init_cal_BG_reg[7]_0 ),
        .init_cal_CKE(init_cal_CKE),
        .init_cal_CS_n(init_cal_CS_n),
        .init_cal_RESET_n(init_cal_RESET_n),
        .\init_cal_RESET_n_reg[7] (\init_cal_RESET_n[7]_i_2_n_0 ),
        .io_addr_strobe_r1_reg_0(io_addr_strobe_r1_reg),
        .io_address({io_address[20:16],io_address[12:11],io_address[9:8],io_address[6:0]}),
        .\io_read_data_reg[31]_0 (\io_read_data_reg[31] ),
        .io_ready_lvl_reg_0(io_ready_lvl_reg),
        .io_ready_reg_0(io_ready_reg),
        .io_ready_reg_1(io_ready_reg_0),
        .io_ready_reg_2(io_ready_reg_1),
        .io_write_data(io_write_data),
        .\lowCL0_reg[45]_0 ({ub_lowCL0[45:42],ub_lowCL0[39:36],ub_lowCL0[33:30],ub_lowCL0[27:24],ub_lowCL0[21:18],ub_lowCL0[15:12],ub_lowCL0[9:6],ub_lowCL0[3:0]}),
        .\lowCL1_reg[45]_0 ({ub_lowCL1[45:42],ub_lowCL1[39:36],ub_lowCL1[33:30],ub_lowCL1[27:24],ub_lowCL1[21:18],ub_lowCL1[15:12],ub_lowCL1[9:6],ub_lowCL1[3:0]}),
        .\lowCL2_reg[45]_0 ({ub_lowCL2[45:42],ub_lowCL2[39:36],ub_lowCL2[33:30],ub_lowCL2[27:24],ub_lowCL2[21:18],ub_lowCL2[15:12],ub_lowCL2[9:6],ub_lowCL2[3:0]}),
        .\lowCL3_reg[45]_0 ({ub_lowCL3[45:42],ub_lowCL3[39:36],ub_lowCL3[33:30],ub_lowCL3[27:24],ub_lowCL3[21:18],ub_lowCL3[15:12],ub_lowCL3[9:6],ub_lowCL3[3:0]}),
        .lrdimm_cal_mode_reg_0(lrdimm_cal_mode_reg),
        .lrdimm_cal_mode_reg_1(lrdimm_cal_mode_reg_0),
        .lrdimm_cal_mode_reg_2(lrdimm_cal_mode_reg_1),
        .lrdimm_cmp_clr(lrdimm_cmp_clr),
        .lrdimm_cmp_en_reg_0(lrdimm_cmp_en_reg),
        .lrdimm_cmp_en_reg_1(lrdimm_cmp_en_reg_0),
        .\max_rd_lat_reg[5]_0 (ub_max_rd_lat),
        .\max_rd_lat_reg[5]_1 (\max_rd_lat_reg[5]_0 ),
        .mcCasSlot2(mcCasSlot2),
        .mcRdCAS(mcRdCAS),
        .mcWrCAS(mcWrCAS),
        .mc_ADR(mc_ADR),
        .mc_BA(mc_BA),
        .mc_BG(mc_BG),
        .mc_CKE(mc_CKE),
        .mc_CKE7(mc_CKE7),
        .mc_CS_n(mc_CS_n),
        .mc_CS_n7(mc_CS_n7),
        .mc_ODT(mc_ODT),
        .mc_ODT7(mc_ODT7),
        .mcalRank(mcalRank),
        .\mcal_ADR_dly_reg[0][128] (\mcal_ADR_dly_reg[0][128] ),
        .\mcal_ADR_dly_reg[0][134] ({\init_cal_ADR_reg_n_0_[135] ,\init_cal_ADR_reg_n_0_[132] ,\init_cal_ADR_reg_n_0_[116] ,\init_cal_ADR_reg_n_0_[103] ,\init_cal_ADR_reg_n_0_[95] ,\init_cal_ADR_reg_n_0_[79] ,\init_cal_ADR_reg_n_0_[71] ,\init_cal_ADR_reg_n_0_[63] ,\init_cal_ADR_reg_n_0_[55] ,\init_cal_ADR_reg_n_0_[47] ,\init_cal_ADR_reg_n_0_[39] ,\init_cal_ADR_reg_n_0_[31] ,\init_cal_ADR_reg_n_0_[23] ,\init_cal_ADR_reg_n_0_[15] ,\init_cal_ADR_reg_n_0_[7] }),
        .\mcal_ADR_dly_reg[0][135] (\mcal_ADR_dly_reg[0][135] ),
        .\mcal_ADR_dly_reg[0][87] (\init_cal_ADR_reg_n_0_[87] ),
        .\mcal_BA_dly_reg[0][15] ({init_cal_BA[15],init_cal_BA[7]}),
        .\mcal_BA_dly_reg[0][8] (Q),
        .\mcal_DMIn_bit_r1_reg[7]_0 (\mcal_DMIn_bit_r1_reg[7] ),
        .\mcal_DMIn_n_r_reg[63]_0 (\mcal_DMIn_n_r_reg[63] ),
        .\mcal_DQIn_byte_r1_reg[31]_0 (\mcal_DQIn_byte_r1_reg[31] ),
        .\mcal_DQIn_byte_r1_reg[48]_0 (\mcal_DQIn_byte_r1_reg[48] ),
        .\mcal_DQIn_r_reg[511]_0 (\mcal_DQIn_r_reg[511] ),
        .\mcal_ODT_dly_reg[0][4] (calDone_reg_1),
        .\mcal_PAR_dly_reg[0][0] (\mcal_PAR_dly[0][0]_i_2_n_0 ),
        .\mcal_PAR_dly_reg[0][1] (\mcal_PAR_dly_reg[0][1] ),
        .\mcal_PAR_dly_reg[0][3] (\mcal_PAR_dly_reg[0][3] ),
        .\mcal_PAR_dly_reg[0][5] (\mcal_PAR_dly_reg[0][5] ),
        .\mcal_PAR_dly_reg[0][7] (\mcal_PAR_dly_reg[0][7] ),
        .mcal_rd_vref_value(mcal_rd_vref_value),
        .mem_reg_bram_0(mem_reg_bram_0),
        .\odt_shift_reg[0][17] (\SYNC[0].sync_reg_reg[1]_1 ),
        .out(rst_r1_reg_0),
        .p_1_in(p_1_in),
        .p_52_in(p_52_in),
        .pllGate(pllGate),
        .rdCAS_reg_0(calRdCAS),
        .rdCAS_reg_1(rdCAS_reg),
        .rdDataEn_pi(rdDataEn_pi),
        .\rdEn_reg[28] (\rdEn_reg[28] ),
        .\rdEn_reg[28]_0 (\rdEn_reg[28]_0 ),
        .\rdEn_reg[28]_1 (\rdEn_reg[28]_1 ),
        .\rdEn_reg[28]_10 (\rdEn_reg[28]_10 ),
        .\rdEn_reg[28]_11 (\rdEn_reg[28]_11 ),
        .\rdEn_reg[28]_12 (\rdEn_reg[28]_12 ),
        .\rdEn_reg[28]_2 (\rdEn_reg[28]_2 ),
        .\rdEn_reg[28]_3 (\rdEn_reg[28]_3 ),
        .\rdEn_reg[28]_4 (\rdEn_reg[28]_4 ),
        .\rdEn_reg[28]_5 (\rdEn_reg[28]_5 ),
        .\rdEn_reg[28]_6 (\rdEn_reg[28]_6 ),
        .\rdEn_reg[28]_7 (\rdEn_reg[28]_7 ),
        .\rdEn_reg[28]_8 (\rdEn_reg[28]_8 ),
        .\rdEn_reg[28]_9 (\rdEn_reg[28]_9 ),
        .\rdEn_reg[29] (\rdEn_reg[29] ),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_0 ),
        .\rdEn_reg[29]_1 (\rdEn_reg[29]_1 ),
        .\rdEn_reg[29]_10 (\rdEn_reg[29]_10 ),
        .\rdEn_reg[29]_11 (\rdEn_reg[29]_11 ),
        .\rdEn_reg[29]_12 (\rdEn_reg[29]_12 ),
        .\rdEn_reg[29]_13 (\rdEn_reg[29]_13 ),
        .\rdEn_reg[29]_2 (\rdEn_reg[29]_2 ),
        .\rdEn_reg[29]_3 (\rdEn_reg[29]_3 ),
        .\rdEn_reg[29]_4 (\rdEn_reg[29]_4 ),
        .\rdEn_reg[29]_5 (\rdEn_reg[29]_5 ),
        .\rdEn_reg[29]_6 (\rdEn_reg[29]_6 ),
        .\rdEn_reg[29]_7 (\rdEn_reg[29]_7 ),
        .\rdEn_reg[29]_8 (\rdEn_reg[29]_8 ),
        .\rdEn_reg[29]_9 (\rdEn_reg[29]_9 ),
        .rd_vref_value0_out(rd_vref_value0_out),
        .\rd_vref_value_reg[42]_0 (\rd_vref_value_reg[42] ),
        .\rd_vref_value_reg[43]_0 (\rd_vref_value_reg[43] ),
        .\rd_vref_value_reg[44]_0 (\rd_vref_value_reg[44] ),
        .\rd_vref_value_reg[45]_0 (\rd_vref_value_reg[45] ),
        .\rd_vref_value_reg[46]_0 (\rd_vref_value_reg[46] ),
        .\rd_vref_value_reg[48]_0 (\rd_vref_value_reg[48] ),
        .\rsMask_reg[1]_71 (\rsMask_reg[1]_71 ),
        .\rsMask_reg[1]_79 (\rsMask_reg[1]_79 ),
        .\rsMask_reg[3]_73 (\rsMask_reg[3]_73 ),
        .\rsMask_reg[3]_81 (\rsMask_reg[3]_81 ),
        .\rsMask_reg[5]_75 (\rsMask_reg[5]_75 ),
        .\rsMask_reg[5]_83 (\rsMask_reg[5]_83 ),
        .\rsMask_reg[7][18] (\rsMask_reg[7][18] ),
        .\rsMask_reg[7]_77 (\rsMask_reg[7]_77 ),
        .\rsMask_reg[7]_85 (\rsMask_reg[7]_85 ),
        .rst_r1_reg_0(rst_r1_reg_1),
        .rst_r1_reg_1(rst_r1_reg_2),
        .rst_r1_reg_10(rst_r1_reg_11),
        .rst_r1_reg_11(rst_r1_reg_12),
        .rst_r1_reg_12(rst_r1_reg_13),
        .rst_r1_reg_13(rst_r1_reg_14),
        .rst_r1_reg_14(rst_r1_reg_15),
        .rst_r1_reg_2(rst_r1_reg_3),
        .rst_r1_reg_3(rst_r1_reg_4),
        .rst_r1_reg_4(rst_r1_reg_5),
        .rst_r1_reg_5(rst_r1_reg_6),
        .rst_r1_reg_6(rst_r1_reg_7),
        .rst_r1_reg_7(rst_r1_reg_8),
        .rst_r1_reg_8(rst_r1_reg_9),
        .rst_r1_reg_9(rst_r1_reg_10),
        .stop_gate_tracking_ack_reg_0(stop_gate_tracking_ack_reg),
        .stop_gate_tracking_ack_reg_1(stop_gate_tracking_ack_reg_0),
        .\traffic_instr_nxt_instr_r1_reg[5]_0 (\traffic_instr_nxt_instr_r1_reg[5] ),
        .ub_initDone_reg_0(ub_initDone_reg),
        .ub_initDone_reg_1(u_ddr_cal_addr_decode_n_52),
        .ub_ready_reg_0(ub_ready_reg),
        .ub_ready_reg_1(ub_ready_reg_0),
        .\uppCL0_reg[45]_0 ({ub_uppCL0[45:42],ub_uppCL0[39:36],ub_uppCL0[33:30],ub_uppCL0[27:24],ub_uppCL0[21:18],ub_uppCL0[15:12],ub_uppCL0[9:6],ub_uppCL0[3:0]}),
        .\uppCL0_reg[47]_0 (\uppCL0_reg[47] ),
        .\uppCL1_reg[45]_0 ({ub_uppCL1[45:42],ub_uppCL1[39:36],ub_uppCL1[33:30],ub_uppCL1[27:24],ub_uppCL1[21:18],ub_uppCL1[15:12],ub_uppCL1[9:6],ub_uppCL1[3:0]}),
        .\uppCL1_reg[47]_0 (\uppCL1_reg[47] ),
        .\uppCL2_reg[45]_0 ({ub_uppCL2[45:42],ub_uppCL2[39:36],ub_uppCL2[33:30],ub_uppCL2[27:24],ub_uppCL2[21:18],ub_uppCL2[15:12],ub_uppCL2[9:6],ub_uppCL2[3:0]}),
        .\uppCL2_reg[47]_0 (\uppCL2_reg[47] ),
        .\uppCL3_reg[42]_0 (\uppCL3_reg[42]_1 ),
        .\uppCL3_reg[45]_0 ({ub_uppCL3[45:42],ub_uppCL3[39:36],ub_uppCL3[33:30],ub_uppCL3[27:24],ub_uppCL3[21:18],ub_uppCL3[15:12],ub_uppCL3[9:6],ub_uppCL3[3:0]}),
        .\uppCL3_reg[47]_0 (\uppCL3_reg[47] ),
        .wea(ub_xsdb_wr_en),
        .winAct(winAct),
        .winAct_reg(winAct_reg),
        .wosp(wosp),
        .\wosp_reg[1] (\wosp_reg[1] ),
        .\wosp_reg[1]_0 (\wosp_reg[1]_0 ),
        .\wosp_reg[1]_1 (\wosp_reg[1]_1 ),
        .\wosp_reg[1]_10 (\wosp_reg[1]_10 ),
        .\wosp_reg[1]_100 (\wosp_reg[1]_100 ),
        .\wosp_reg[1]_101 (\wosp_reg[1]_101 ),
        .\wosp_reg[1]_102 (\wosp_reg[1]_102 ),
        .\wosp_reg[1]_103 (\wosp_reg[1]_103 ),
        .\wosp_reg[1]_104 (\wosp_reg[1]_104 ),
        .\wosp_reg[1]_105 (\wosp_reg[1]_105 ),
        .\wosp_reg[1]_106 (\wosp_reg[1]_106 ),
        .\wosp_reg[1]_107 (\wosp_reg[1]_107 ),
        .\wosp_reg[1]_108 (\wosp_reg[1]_108 ),
        .\wosp_reg[1]_109 (\wosp_reg[1]_109 ),
        .\wosp_reg[1]_11 (\wosp_reg[1]_11 ),
        .\wosp_reg[1]_110 (\wosp_reg[1]_110 ),
        .\wosp_reg[1]_111 (\wosp_reg[1]_111 ),
        .\wosp_reg[1]_112 (\wosp_reg[1]_112 ),
        .\wosp_reg[1]_113 (\wosp_reg[1]_113 ),
        .\wosp_reg[1]_114 (\wosp_reg[1]_114 ),
        .\wosp_reg[1]_115 (\wosp_reg[1]_115 ),
        .\wosp_reg[1]_116 (\wosp_reg[1]_116 ),
        .\wosp_reg[1]_117 (\wosp_reg[1]_117 ),
        .\wosp_reg[1]_118 (\wosp_reg[1]_118 ),
        .\wosp_reg[1]_119 (\wosp_reg[1]_119 ),
        .\wosp_reg[1]_12 (\wosp_reg[1]_12 ),
        .\wosp_reg[1]_120 (\wosp_reg[1]_120 ),
        .\wosp_reg[1]_121 (\wosp_reg[1]_121 ),
        .\wosp_reg[1]_122 (\wosp_reg[1]_122 ),
        .\wosp_reg[1]_123 (\wosp_reg[1]_123 ),
        .\wosp_reg[1]_124 (\wosp_reg[1]_124 ),
        .\wosp_reg[1]_125 (\wosp_reg[1]_125 ),
        .\wosp_reg[1]_126 (\wosp_reg[1]_126 ),
        .\wosp_reg[1]_127 (\wosp_reg[1]_127 ),
        .\wosp_reg[1]_128 (\wosp_reg[1]_128 ),
        .\wosp_reg[1]_129 (\wosp_reg[1]_129 ),
        .\wosp_reg[1]_13 (\wosp_reg[1]_13 ),
        .\wosp_reg[1]_130 (\wosp_reg[1]_130 ),
        .\wosp_reg[1]_131 (\wosp_reg[1]_131 ),
        .\wosp_reg[1]_132 (\wosp_reg[1]_132 ),
        .\wosp_reg[1]_133 (\wosp_reg[1]_133 ),
        .\wosp_reg[1]_134 (\wosp_reg[1]_134 ),
        .\wosp_reg[1]_135 (\wosp_reg[1]_135 ),
        .\wosp_reg[1]_136 (\wosp_reg[1]_136 ),
        .\wosp_reg[1]_137 (\wosp_reg[1]_137 ),
        .\wosp_reg[1]_138 (\wosp_reg[1]_138 ),
        .\wosp_reg[1]_139 (\wosp_reg[1]_139 ),
        .\wosp_reg[1]_14 (\wosp_reg[1]_14 ),
        .\wosp_reg[1]_140 (\wosp_reg[1]_140 ),
        .\wosp_reg[1]_141 (\wosp_reg[1]_141 ),
        .\wosp_reg[1]_142 (\wosp_reg[1]_142 ),
        .\wosp_reg[1]_15 (\wosp_reg[1]_15 ),
        .\wosp_reg[1]_16 (\wosp_reg[1]_16 ),
        .\wosp_reg[1]_17 (\wosp_reg[1]_17 ),
        .\wosp_reg[1]_18 (\wosp_reg[1]_18 ),
        .\wosp_reg[1]_19 (\wosp_reg[1]_19 ),
        .\wosp_reg[1]_2 (\wosp_reg[1]_2 ),
        .\wosp_reg[1]_20 (\wosp_reg[1]_20 ),
        .\wosp_reg[1]_21 (\wosp_reg[1]_21 ),
        .\wosp_reg[1]_22 (\wosp_reg[1]_22 ),
        .\wosp_reg[1]_23 (\wosp_reg[1]_23 ),
        .\wosp_reg[1]_24 (\wosp_reg[1]_24 ),
        .\wosp_reg[1]_25 (\wosp_reg[1]_25 ),
        .\wosp_reg[1]_26 (\wosp_reg[1]_26 ),
        .\wosp_reg[1]_27 (\wosp_reg[1]_27 ),
        .\wosp_reg[1]_28 (\wosp_reg[1]_28 ),
        .\wosp_reg[1]_29 (\wosp_reg[1]_29 ),
        .\wosp_reg[1]_3 (\wosp_reg[1]_3 ),
        .\wosp_reg[1]_30 (\wosp_reg[1]_30 ),
        .\wosp_reg[1]_31 (\wosp_reg[1]_31 ),
        .\wosp_reg[1]_32 (\wosp_reg[1]_32 ),
        .\wosp_reg[1]_33 (\wosp_reg[1]_33 ),
        .\wosp_reg[1]_34 (\wosp_reg[1]_34 ),
        .\wosp_reg[1]_35 (\wosp_reg[1]_35 ),
        .\wosp_reg[1]_36 (\wosp_reg[1]_36 ),
        .\wosp_reg[1]_37 (\wosp_reg[1]_37 ),
        .\wosp_reg[1]_38 (\wosp_reg[1]_38 ),
        .\wosp_reg[1]_39 (\wosp_reg[1]_39 ),
        .\wosp_reg[1]_4 (\wosp_reg[1]_4 ),
        .\wosp_reg[1]_40 (\wosp_reg[1]_40 ),
        .\wosp_reg[1]_41 (\wosp_reg[1]_41 ),
        .\wosp_reg[1]_42 (\wosp_reg[1]_42 ),
        .\wosp_reg[1]_43 (\wosp_reg[1]_43 ),
        .\wosp_reg[1]_44 (\wosp_reg[1]_44 ),
        .\wosp_reg[1]_45 (\wosp_reg[1]_45 ),
        .\wosp_reg[1]_46 (\wosp_reg[1]_46 ),
        .\wosp_reg[1]_47 (\wosp_reg[1]_47 ),
        .\wosp_reg[1]_48 (\wosp_reg[1]_48 ),
        .\wosp_reg[1]_49 (\wosp_reg[1]_49 ),
        .\wosp_reg[1]_5 (\wosp_reg[1]_5 ),
        .\wosp_reg[1]_50 (\wosp_reg[1]_50 ),
        .\wosp_reg[1]_51 (\wosp_reg[1]_51 ),
        .\wosp_reg[1]_52 (\wosp_reg[1]_52 ),
        .\wosp_reg[1]_53 (\wosp_reg[1]_53 ),
        .\wosp_reg[1]_54 (\wosp_reg[1]_54 ),
        .\wosp_reg[1]_55 (\wosp_reg[1]_55 ),
        .\wosp_reg[1]_56 (\wosp_reg[1]_56 ),
        .\wosp_reg[1]_57 (\wosp_reg[1]_57 ),
        .\wosp_reg[1]_58 (\wosp_reg[1]_58 ),
        .\wosp_reg[1]_59 (\wosp_reg[1]_59 ),
        .\wosp_reg[1]_6 (\wosp_reg[1]_6 ),
        .\wosp_reg[1]_60 (\wosp_reg[1]_60 ),
        .\wosp_reg[1]_61 (\wosp_reg[1]_61 ),
        .\wosp_reg[1]_62 (\wosp_reg[1]_62 ),
        .\wosp_reg[1]_63 (\wosp_reg[1]_63 ),
        .\wosp_reg[1]_64 (\wosp_reg[1]_64 ),
        .\wosp_reg[1]_65 (\wosp_reg[1]_65 ),
        .\wosp_reg[1]_66 (\wosp_reg[1]_66 ),
        .\wosp_reg[1]_67 (\wosp_reg[1]_67 ),
        .\wosp_reg[1]_68 (\wosp_reg[1]_68 ),
        .\wosp_reg[1]_69 (\wosp_reg[1]_69 ),
        .\wosp_reg[1]_7 (\wosp_reg[1]_7 ),
        .\wosp_reg[1]_70 (\wosp_reg[1]_70 ),
        .\wosp_reg[1]_71 (\wosp_reg[1]_71 ),
        .\wosp_reg[1]_72 (\wosp_reg[1]_72 ),
        .\wosp_reg[1]_73 (\wosp_reg[1]_73 ),
        .\wosp_reg[1]_74 (\wosp_reg[1]_74 ),
        .\wosp_reg[1]_75 (\wosp_reg[1]_75 ),
        .\wosp_reg[1]_76 (\wosp_reg[1]_76 ),
        .\wosp_reg[1]_77 (\wosp_reg[1]_77 ),
        .\wosp_reg[1]_78 (\wosp_reg[1]_78 ),
        .\wosp_reg[1]_79 (\wosp_reg[1]_79 ),
        .\wosp_reg[1]_8 (\wosp_reg[1]_8 ),
        .\wosp_reg[1]_80 (\wosp_reg[1]_80 ),
        .\wosp_reg[1]_81 (\wosp_reg[1]_81 ),
        .\wosp_reg[1]_82 (\wosp_reg[1]_82 ),
        .\wosp_reg[1]_83 (\wosp_reg[1]_83 ),
        .\wosp_reg[1]_84 (\wosp_reg[1]_84 ),
        .\wosp_reg[1]_85 (\wosp_reg[1]_85 ),
        .\wosp_reg[1]_86 (\wosp_reg[1]_86 ),
        .\wosp_reg[1]_87 (\wosp_reg[1]_87 ),
        .\wosp_reg[1]_88 (\wosp_reg[1]_88 ),
        .\wosp_reg[1]_89 (\wosp_reg[1]_89 ),
        .\wosp_reg[1]_9 (\wosp_reg[1]_9 ),
        .\wosp_reg[1]_90 (\wosp_reg[1]_90 ),
        .\wosp_reg[1]_91 (\wosp_reg[1]_91 ),
        .\wosp_reg[1]_92 (\wosp_reg[1]_92 ),
        .\wosp_reg[1]_93 (\wosp_reg[1]_93 ),
        .\wosp_reg[1]_94 (\wosp_reg[1]_94 ),
        .\wosp_reg[1]_95 (\wosp_reg[1]_95 ),
        .\wosp_reg[1]_96 (\wosp_reg[1]_96 ),
        .\wosp_reg[1]_97 (\wosp_reg[1]_97 ),
        .\wosp_reg[1]_98 (\wosp_reg[1]_98 ),
        .\wosp_reg[1]_99 (\wosp_reg[1]_99 ),
        .\wosp_reg[2] (\wosp_reg[2] ),
        .\wosp_reg[2]_0 (\wosp_reg[2]_0 ),
        .\wosp_reg[2]_rep (\wosp_reg[2]_rep ),
        .\wosp_reg[2]_rep_0 (\wosp_reg[2]_rep_0 ),
        .\wosp_reg[2]_rep_1 (\wosp_reg[2]_rep_1 ),
        .\wosp_reg[2]_rep_2 (\wosp_reg[2]_rep_2 ),
        .\wosp_reg[2]_rep_3 (\wosp_reg[2]_rep_3 ),
        .\wosp_reg[2]_rep_4 (\wosp_reg[2]_rep_4 ),
        .\wosp_reg[2]_rep__0 (\wosp_reg[2]_rep__0 ),
        .\wosp_reg[2]_rep__0_0 (\wosp_reg[2]_rep__0_0 ),
        .\wosp_reg[2]_rep__0_1 (\wosp_reg[2]_rep__0_1 ),
        .\wosp_reg[2]_rep__0_2 (\wosp_reg[2]_rep__0_2 ),
        .\wosp_reg[2]_rep__0_3 (\wosp_reg[2]_rep__0_3 ),
        .\wosp_reg[2]_rep__0_4 (\wosp_reg[2]_rep__0_4 ),
        .\wosp_reg[2]_rep__1 (\wosp_reg[2]_rep__1 ),
        .\wosp_reg[2]_rep__1_0 (\wosp_reg[2]_rep__1_0 ),
        .\wosp_reg[2]_rep__1_1 (\wosp_reg[2]_rep__1_1 ),
        .\wosp_reg[2]_rep__1_10 (\wosp_reg[2]_rep__1_10 ),
        .\wosp_reg[2]_rep__1_11 (\wosp_reg[2]_rep__1_11 ),
        .\wosp_reg[2]_rep__1_12 (\wosp_reg[2]_rep__1_12 ),
        .\wosp_reg[2]_rep__1_13 (\wosp_reg[2]_rep__1_13 ),
        .\wosp_reg[2]_rep__1_2 (\wosp_reg[2]_rep__1_2 ),
        .\wosp_reg[2]_rep__1_3 (\wosp_reg[2]_rep__1_3 ),
        .\wosp_reg[2]_rep__1_4 (\wosp_reg[2]_rep__1_4 ),
        .\wosp_reg[2]_rep__1_5 (\wosp_reg[2]_rep__1_5 ),
        .\wosp_reg[2]_rep__1_6 (\wosp_reg[2]_rep__1_6 ),
        .\wosp_reg[2]_rep__1_7 (\wosp_reg[2]_rep__1_7 ),
        .\wosp_reg[2]_rep__1_8 (\wosp_reg[2]_rep__1_8 ),
        .\wosp_reg[2]_rep__1_9 (\wosp_reg[2]_rep__1_9 ),
        .\wosp_reg[2]_rep__2 (\wosp_reg[2]_rep__2 ),
        .\wosp_reg[2]_rep__2_0 (\wosp_reg[2]_rep__2_0 ),
        .\wosp_reg[2]_rep__2_1 (\wosp_reg[2]_rep__2_1 ),
        .\wosp_reg[2]_rep__2_10 (\wosp_reg[2]_rep__2_10 ),
        .\wosp_reg[2]_rep__2_11 (\wosp_reg[2]_rep__2_11 ),
        .\wosp_reg[2]_rep__2_12 (\wosp_reg[2]_rep__2_12 ),
        .\wosp_reg[2]_rep__2_13 (\wosp_reg[2]_rep__2_13 ),
        .\wosp_reg[2]_rep__2_14 (\wosp_reg[2]_rep__2_14 ),
        .\wosp_reg[2]_rep__2_15 (\wosp_reg[2]_rep__2_15 ),
        .\wosp_reg[2]_rep__2_16 (\wosp_reg[2]_rep__2_16 ),
        .\wosp_reg[2]_rep__2_17 (\wosp_reg[2]_rep__2_17 ),
        .\wosp_reg[2]_rep__2_18 (\wosp_reg[2]_rep__2_18 ),
        .\wosp_reg[2]_rep__2_19 (\wosp_reg[2]_rep__2_19 ),
        .\wosp_reg[2]_rep__2_2 (\wosp_reg[2]_rep__2_2 ),
        .\wosp_reg[2]_rep__2_20 (\wosp_reg[2]_rep__2_20 ),
        .\wosp_reg[2]_rep__2_21 (\wosp_reg[2]_rep__2_21 ),
        .\wosp_reg[2]_rep__2_22 (\wosp_reg[2]_rep__2_22 ),
        .\wosp_reg[2]_rep__2_23 (\wosp_reg[2]_rep__2_23 ),
        .\wosp_reg[2]_rep__2_24 (\wosp_reg[2]_rep__2_24 ),
        .\wosp_reg[2]_rep__2_25 (\wosp_reg[2]_rep__2_25 ),
        .\wosp_reg[2]_rep__2_26 (\wosp_reg[2]_rep__2_26 ),
        .\wosp_reg[2]_rep__2_27 (\wosp_reg[2]_rep__2_27 ),
        .\wosp_reg[2]_rep__2_28 (\wosp_reg[2]_rep__2_28 ),
        .\wosp_reg[2]_rep__2_29 (\wosp_reg[2]_rep__2_29 ),
        .\wosp_reg[2]_rep__2_3 (\wosp_reg[2]_rep__2_3 ),
        .\wosp_reg[2]_rep__2_30 (\wosp_reg[2]_rep__2_30 ),
        .\wosp_reg[2]_rep__2_31 (\wosp_reg[2]_rep__2_31 ),
        .\wosp_reg[2]_rep__2_32 (\wosp_reg[2]_rep__2_32 ),
        .\wosp_reg[2]_rep__2_33 (\wosp_reg[2]_rep__2_33 ),
        .\wosp_reg[2]_rep__2_34 (\wosp_reg[2]_rep__2_34 ),
        .\wosp_reg[2]_rep__2_4 (\wosp_reg[2]_rep__2_4 ),
        .\wosp_reg[2]_rep__2_5 (\wosp_reg[2]_rep__2_5 ),
        .\wosp_reg[2]_rep__2_6 (\wosp_reg[2]_rep__2_6 ),
        .\wosp_reg[2]_rep__2_7 (\wosp_reg[2]_rep__2_7 ),
        .\wosp_reg[2]_rep__2_8 (\wosp_reg[2]_rep__2_8 ),
        .\wosp_reg[2]_rep__2_9 (\wosp_reg[2]_rep__2_9 ),
        .\wosp_reg[2]_rep__3 (\wosp_reg[2]_rep__3 ),
        .\wosp_reg[2]_rep__3_0 (\wosp_reg[2]_rep__3_0 ),
        .\wosp_reg[2]_rep__3_1 (\wosp_reg[2]_rep__3_1 ),
        .\wosp_reg[2]_rep__3_10 (\wosp_reg[2]_rep__3_10 ),
        .\wosp_reg[2]_rep__3_11 (\wosp_reg[2]_rep__3_11 ),
        .\wosp_reg[2]_rep__3_12 (\wosp_reg[2]_rep__3_12 ),
        .\wosp_reg[2]_rep__3_13 (\wosp_reg[2]_rep__3_13 ),
        .\wosp_reg[2]_rep__3_14 (\wosp_reg[2]_rep__3_14 ),
        .\wosp_reg[2]_rep__3_15 (\wosp_reg[2]_rep__3_15 ),
        .\wosp_reg[2]_rep__3_16 (\wosp_reg[2]_rep__3_16 ),
        .\wosp_reg[2]_rep__3_17 (\wosp_reg[2]_rep__3_17 ),
        .\wosp_reg[2]_rep__3_18 (\wosp_reg[2]_rep__3_18 ),
        .\wosp_reg[2]_rep__3_19 (\wosp_reg[2]_rep__3_19 ),
        .\wosp_reg[2]_rep__3_2 (\wosp_reg[2]_rep__3_2 ),
        .\wosp_reg[2]_rep__3_20 (\wosp_reg[2]_rep__3_20 ),
        .\wosp_reg[2]_rep__3_21 (\wosp_reg[2]_rep__3_21 ),
        .\wosp_reg[2]_rep__3_22 (\wosp_reg[2]_rep__3_22 ),
        .\wosp_reg[2]_rep__3_23 (\wosp_reg[2]_rep__3_23 ),
        .\wosp_reg[2]_rep__3_24 (\wosp_reg[2]_rep__3_24 ),
        .\wosp_reg[2]_rep__3_25 (\wosp_reg[2]_rep__3_25 ),
        .\wosp_reg[2]_rep__3_26 (\wosp_reg[2]_rep__3_26 ),
        .\wosp_reg[2]_rep__3_27 (\wosp_reg[2]_rep__3_27 ),
        .\wosp_reg[2]_rep__3_28 (\wosp_reg[2]_rep__3_28 ),
        .\wosp_reg[2]_rep__3_29 (\wosp_reg[2]_rep__3_29 ),
        .\wosp_reg[2]_rep__3_3 (\wosp_reg[2]_rep__3_3 ),
        .\wosp_reg[2]_rep__3_30 (\wosp_reg[2]_rep__3_30 ),
        .\wosp_reg[2]_rep__3_31 (\wosp_reg[2]_rep__3_31 ),
        .\wosp_reg[2]_rep__3_32 (\wosp_reg[2]_rep__3_32 ),
        .\wosp_reg[2]_rep__3_33 (\wosp_reg[2]_rep__3_33 ),
        .\wosp_reg[2]_rep__3_4 (\wosp_reg[2]_rep__3_4 ),
        .\wosp_reg[2]_rep__3_5 (\wosp_reg[2]_rep__3_5 ),
        .\wosp_reg[2]_rep__3_6 (\wosp_reg[2]_rep__3_6 ),
        .\wosp_reg[2]_rep__3_7 (\wosp_reg[2]_rep__3_7 ),
        .\wosp_reg[2]_rep__3_8 (\wosp_reg[2]_rep__3_8 ),
        .\wosp_reg[2]_rep__3_9 (\wosp_reg[2]_rep__3_9 ),
        .\wosp_reg[2]_rep__4 (\wosp_reg[2]_rep__4 ),
        .\wosp_reg[2]_rep__4_0 (\wosp_reg[2]_rep__4_0 ),
        .\wosp_reg[2]_rep__4_1 (\wosp_reg[2]_rep__4_1 ),
        .\wosp_reg[2]_rep__4_10 (\wosp_reg[2]_rep__4_10 ),
        .\wosp_reg[2]_rep__4_11 (\wosp_reg[2]_rep__4_11 ),
        .\wosp_reg[2]_rep__4_12 (\wosp_reg[2]_rep__4_12 ),
        .\wosp_reg[2]_rep__4_13 (\wosp_reg[2]_rep__4_13 ),
        .\wosp_reg[2]_rep__4_14 (\wosp_reg[2]_rep__4_14 ),
        .\wosp_reg[2]_rep__4_15 (\wosp_reg[2]_rep__4_15 ),
        .\wosp_reg[2]_rep__4_16 (\wosp_reg[2]_rep__4_16 ),
        .\wosp_reg[2]_rep__4_17 (\wosp_reg[2]_rep__4_17 ),
        .\wosp_reg[2]_rep__4_18 (\wosp_reg[2]_rep__4_18 ),
        .\wosp_reg[2]_rep__4_19 (\wosp_reg[2]_rep__4_19 ),
        .\wosp_reg[2]_rep__4_2 (\wosp_reg[2]_rep__4_2 ),
        .\wosp_reg[2]_rep__4_20 (\wosp_reg[2]_rep__4_20 ),
        .\wosp_reg[2]_rep__4_21 (\wosp_reg[2]_rep__4_21 ),
        .\wosp_reg[2]_rep__4_22 (\wosp_reg[2]_rep__4_22 ),
        .\wosp_reg[2]_rep__4_23 (\wosp_reg[2]_rep__4_23 ),
        .\wosp_reg[2]_rep__4_24 (\wosp_reg[2]_rep__4_24 ),
        .\wosp_reg[2]_rep__4_25 (\wosp_reg[2]_rep__4_25 ),
        .\wosp_reg[2]_rep__4_26 (\wosp_reg[2]_rep__4_26 ),
        .\wosp_reg[2]_rep__4_27 (\wosp_reg[2]_rep__4_27 ),
        .\wosp_reg[2]_rep__4_28 (\wosp_reg[2]_rep__4_28 ),
        .\wosp_reg[2]_rep__4_29 (\wosp_reg[2]_rep__4_29 ),
        .\wosp_reg[2]_rep__4_3 (\wosp_reg[2]_rep__4_3 ),
        .\wosp_reg[2]_rep__4_30 (\wosp_reg[2]_rep__4_30 ),
        .\wosp_reg[2]_rep__4_31 (\wosp_reg[2]_rep__4_31 ),
        .\wosp_reg[2]_rep__4_32 (\wosp_reg[2]_rep__4_32 ),
        .\wosp_reg[2]_rep__4_33 (\wosp_reg[2]_rep__4_33 ),
        .\wosp_reg[2]_rep__4_4 (\wosp_reg[2]_rep__4_4 ),
        .\wosp_reg[2]_rep__4_5 (\wosp_reg[2]_rep__4_5 ),
        .\wosp_reg[2]_rep__4_6 (\wosp_reg[2]_rep__4_6 ),
        .\wosp_reg[2]_rep__4_7 (\wosp_reg[2]_rep__4_7 ),
        .\wosp_reg[2]_rep__4_8 (\wosp_reg[2]_rep__4_8 ),
        .\wosp_reg[2]_rep__4_9 (\wosp_reg[2]_rep__4_9 ),
        .\wosp_reg[2]_rep__5 (\wosp_reg[2]_rep__5 ),
        .\wosp_reg[2]_rep__5_0 (\wosp_reg[2]_rep__5_0 ),
        .\wosp_reg[2]_rep__5_1 (\wosp_reg[2]_rep__5_1 ),
        .\wosp_reg[2]_rep__5_10 (\wosp_reg[2]_rep__5_10 ),
        .\wosp_reg[2]_rep__5_11 (\wosp_reg[2]_rep__5_11 ),
        .\wosp_reg[2]_rep__5_12 (\wosp_reg[2]_rep__5_12 ),
        .\wosp_reg[2]_rep__5_13 (\wosp_reg[2]_rep__5_13 ),
        .\wosp_reg[2]_rep__5_14 (\wosp_reg[2]_rep__5_14 ),
        .\wosp_reg[2]_rep__5_15 (\wosp_reg[2]_rep__5_15 ),
        .\wosp_reg[2]_rep__5_16 (\wosp_reg[2]_rep__5_16 ),
        .\wosp_reg[2]_rep__5_17 (\wosp_reg[2]_rep__5_17 ),
        .\wosp_reg[2]_rep__5_18 (\wosp_reg[2]_rep__5_18 ),
        .\wosp_reg[2]_rep__5_19 (\wosp_reg[2]_rep__5_19 ),
        .\wosp_reg[2]_rep__5_2 (\wosp_reg[2]_rep__5_2 ),
        .\wosp_reg[2]_rep__5_20 (\wosp_reg[2]_rep__5_20 ),
        .\wosp_reg[2]_rep__5_21 (\wosp_reg[2]_rep__5_21 ),
        .\wosp_reg[2]_rep__5_22 (\wosp_reg[2]_rep__5_22 ),
        .\wosp_reg[2]_rep__5_23 (\wosp_reg[2]_rep__5_23 ),
        .\wosp_reg[2]_rep__5_24 (\wosp_reg[2]_rep__5_24 ),
        .\wosp_reg[2]_rep__5_25 (\wosp_reg[2]_rep__5_25 ),
        .\wosp_reg[2]_rep__5_26 (\wosp_reg[2]_rep__5_26 ),
        .\wosp_reg[2]_rep__5_27 (\wosp_reg[2]_rep__5_27 ),
        .\wosp_reg[2]_rep__5_28 (\wosp_reg[2]_rep__5_28 ),
        .\wosp_reg[2]_rep__5_29 (\wosp_reg[2]_rep__5_29 ),
        .\wosp_reg[2]_rep__5_3 (\wosp_reg[2]_rep__5_3 ),
        .\wosp_reg[2]_rep__5_30 (\wosp_reg[2]_rep__5_30 ),
        .\wosp_reg[2]_rep__5_31 (\wosp_reg[2]_rep__5_31 ),
        .\wosp_reg[2]_rep__5_32 (\wosp_reg[2]_rep__5_32 ),
        .\wosp_reg[2]_rep__5_33 (\wosp_reg[2]_rep__5_33 ),
        .\wosp_reg[2]_rep__5_4 (\wosp_reg[2]_rep__5_4 ),
        .\wosp_reg[2]_rep__5_5 (\wosp_reg[2]_rep__5_5 ),
        .\wosp_reg[2]_rep__5_6 (\wosp_reg[2]_rep__5_6 ),
        .\wosp_reg[2]_rep__5_7 (\wosp_reg[2]_rep__5_7 ),
        .\wosp_reg[2]_rep__5_8 (\wosp_reg[2]_rep__5_8 ),
        .\wosp_reg[2]_rep__5_9 (\wosp_reg[2]_rep__5_9 ),
        .\wosp_reg[2]_rep__6 (\wosp_reg[2]_rep__6 ),
        .\wosp_reg[2]_rep__6_0 (\wosp_reg[2]_rep__6_0 ),
        .\wosp_reg[2]_rep__6_1 (\wosp_reg[2]_rep__6_1 ),
        .\wosp_reg[2]_rep__6_10 (\wosp_reg[2]_rep__6_10 ),
        .\wosp_reg[2]_rep__6_11 (\wosp_reg[2]_rep__6_11 ),
        .\wosp_reg[2]_rep__6_12 (\wosp_reg[2]_rep__6_12 ),
        .\wosp_reg[2]_rep__6_13 (\wosp_reg[2]_rep__6_13 ),
        .\wosp_reg[2]_rep__6_14 (\wosp_reg[2]_rep__6_14 ),
        .\wosp_reg[2]_rep__6_15 (\wosp_reg[2]_rep__6_15 ),
        .\wosp_reg[2]_rep__6_16 (\wosp_reg[2]_rep__6_16 ),
        .\wosp_reg[2]_rep__6_17 (\wosp_reg[2]_rep__6_17 ),
        .\wosp_reg[2]_rep__6_18 (\wosp_reg[2]_rep__6_18 ),
        .\wosp_reg[2]_rep__6_19 (\wosp_reg[2]_rep__6_19 ),
        .\wosp_reg[2]_rep__6_2 (\wosp_reg[2]_rep__6_2 ),
        .\wosp_reg[2]_rep__6_20 (\wosp_reg[2]_rep__6_20 ),
        .\wosp_reg[2]_rep__6_21 (\wosp_reg[2]_rep__6_21 ),
        .\wosp_reg[2]_rep__6_22 (\wosp_reg[2]_rep__6_22 ),
        .\wosp_reg[2]_rep__6_23 (\wosp_reg[2]_rep__6_23 ),
        .\wosp_reg[2]_rep__6_24 (\wosp_reg[2]_rep__6_24 ),
        .\wosp_reg[2]_rep__6_25 (\wosp_reg[2]_rep__6_25 ),
        .\wosp_reg[2]_rep__6_26 (\wosp_reg[2]_rep__6_26 ),
        .\wosp_reg[2]_rep__6_27 (\wosp_reg[2]_rep__6_27 ),
        .\wosp_reg[2]_rep__6_28 (\wosp_reg[2]_rep__6_28 ),
        .\wosp_reg[2]_rep__6_29 (\wosp_reg[2]_rep__6_29 ),
        .\wosp_reg[2]_rep__6_3 (\wosp_reg[2]_rep__6_3 ),
        .\wosp_reg[2]_rep__6_30 (\wosp_reg[2]_rep__6_30 ),
        .\wosp_reg[2]_rep__6_31 (\wosp_reg[2]_rep__6_31 ),
        .\wosp_reg[2]_rep__6_32 (\wosp_reg[2]_rep__6_32 ),
        .\wosp_reg[2]_rep__6_33 (\wosp_reg[2]_rep__6_33 ),
        .\wosp_reg[2]_rep__6_34 (\wosp_reg[2]_rep__6_34 ),
        .\wosp_reg[2]_rep__6_35 (\wosp_reg[2]_rep__6_35 ),
        .\wosp_reg[2]_rep__6_36 (\wosp_reg[2]_rep__6_36 ),
        .\wosp_reg[2]_rep__6_37 (\wosp_reg[2]_rep__6_37 ),
        .\wosp_reg[2]_rep__6_38 (\wosp_reg[2]_rep__6_38 ),
        .\wosp_reg[2]_rep__6_39 (\wosp_reg[2]_rep__6_39 ),
        .\wosp_reg[2]_rep__6_4 (\wosp_reg[2]_rep__6_4 ),
        .\wosp_reg[2]_rep__6_40 (\wosp_reg[2]_rep__6_40 ),
        .\wosp_reg[2]_rep__6_41 (\wosp_reg[2]_rep__6_41 ),
        .\wosp_reg[2]_rep__6_42 (\wosp_reg[2]_rep__6_42 ),
        .\wosp_reg[2]_rep__6_5 (\wosp_reg[2]_rep__6_5 ),
        .\wosp_reg[2]_rep__6_6 (\wosp_reg[2]_rep__6_6 ),
        .\wosp_reg[2]_rep__6_7 (\wosp_reg[2]_rep__6_7 ),
        .\wosp_reg[2]_rep__6_8 (\wosp_reg[2]_rep__6_8 ),
        .\wosp_reg[2]_rep__6_9 (\wosp_reg[2]_rep__6_9 ),
        .\wosp_reg[2]_rep__7 (\wosp_reg[2]_rep__7 ),
        .\wosp_reg[2]_rep__7_0 (\wosp_reg[2]_rep__7_0 ),
        .wrCAS_reg_0(wrCAS_reg),
        .wrDataEn_pi(wrDataEn_pi),
        .wrDataVal(wrDataVal),
        .\wrQ_nxt[1]_13 (\wrQ_nxt[1]_13 ),
        .\wrQ_reg[1][0] (\wrQ_reg[1][0] ),
        .wren_reg_0(wren_reg),
        .\xsdb_wr_data_reg[8]_0 (ub_xsdb_wr_data),
        .xsdb_wr_en_reg_0(xsdb_wr_en_reg));
  ddr4_0_ddr4_v2_2_17_cal_config_rom u_ddr_config_rom
       (.\addr_dec_to_mb_data[5]_i_9 (io_ready_reg_1),
        .\dout_o_reg[11]_0 (\dout_o_reg[11] ),
        .\dout_o_reg[11]_1 (\dout_o_reg[11]_0 ),
        .\dout_o_reg[11]_2 (\SYNC[0].sync_reg_reg[1]_1 ),
        .\dout_o_reg[5]_0 (\dout_o_reg[5] ));
  ddr4_0_ddr4_v2_2_17_cal_xsdb_arbiter u_xsdb_arbiter
       (.CLK(s_dclk),
        .D({DDR_XSDB_BRAM_n_9,DDR_XSDB_BRAM_n_10,DDR_XSDB_BRAM_n_11,DDR_XSDB_BRAM_n_12,DDR_XSDB_BRAM_n_13,DDR_XSDB_BRAM_n_14,DDR_XSDB_BRAM_n_15,DDR_XSDB_BRAM_n_16,DDR_XSDB_BRAM_n_17}),
        .E(bramB_rdy),
        .Q(bramB_addr),
        .SS(rst_r1),
        .\SYNC[0].sync_reg_reg[1] (\SYNC[0].sync_reg_reg[1]_1 ),
        .bramB_en(bramB_en),
        .\bram_di_reg[8]_0 (bramB_di),
        .enb(bramB_en_stch),
        .s_den_o(s_den),
        .s_do_i(s_do),
        .s_drdy_i(s_drdy),
        .s_dwe_o(s_dwe),
        .\slave_addr_r_reg[15]_0 (s_daddr),
        .\slave_di_r_reg[8]_0 (s_di[8:0]),
        .t1(t1),
        .web(bramB_we));
  FDSE \uppCL0_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[0]),
        .Q(uppCL0[0]),
        .S(rst_r1));
  FDSE \uppCL0_reg[12] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[12]),
        .Q(uppCL0[12]),
        .S(rst_r1));
  FDRE \uppCL0_reg[13] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[13]),
        .Q(uppCL0[13]),
        .R(rst_r1));
  FDRE \uppCL0_reg[14] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[14]),
        .Q(uppCL0[14]),
        .R(rst_r1));
  FDRE \uppCL0_reg[15] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[15]),
        .Q(uppCL0[15]),
        .R(rst_r1));
  FDSE \uppCL0_reg[18] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[18]),
        .Q(uppCL0[18]),
        .S(rst_r1));
  FDRE \uppCL0_reg[19] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[19]),
        .Q(uppCL0[19]),
        .R(rst_r1));
  FDRE \uppCL0_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[1]),
        .Q(uppCL0[1]),
        .R(rst_r1));
  FDRE \uppCL0_reg[20] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[20]),
        .Q(uppCL0[20]),
        .R(rst_r1));
  FDRE \uppCL0_reg[21] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[21]),
        .Q(uppCL0[21]),
        .R(rst_r1));
  FDSE \uppCL0_reg[24] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[24]),
        .Q(uppCL0[24]),
        .S(rst_r1));
  FDRE \uppCL0_reg[25] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[25]),
        .Q(uppCL0[25]),
        .R(rst_r1));
  FDRE \uppCL0_reg[26] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[26]),
        .Q(uppCL0[26]),
        .R(rst_r1));
  FDRE \uppCL0_reg[27] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[27]),
        .Q(uppCL0[27]),
        .R(rst_r1));
  FDRE \uppCL0_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[2]),
        .Q(uppCL0[2]),
        .R(rst_r1));
  FDSE \uppCL0_reg[30] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[30]),
        .Q(uppCL0[30]),
        .S(rst_r1));
  FDRE \uppCL0_reg[31] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[31]),
        .Q(uppCL0[31]),
        .R(rst_r1));
  FDRE \uppCL0_reg[32] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[32]),
        .Q(uppCL0[32]),
        .R(rst_r1));
  FDRE \uppCL0_reg[33] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[33]),
        .Q(uppCL0[33]),
        .R(rst_r1));
  FDSE \uppCL0_reg[36] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[36]),
        .Q(uppCL0[36]),
        .S(rst_r1));
  FDRE \uppCL0_reg[37] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[37]),
        .Q(uppCL0[37]),
        .R(rst_r1));
  FDRE \uppCL0_reg[38] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[38]),
        .Q(uppCL0[38]),
        .R(rst_r1));
  FDRE \uppCL0_reg[39] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[39]),
        .Q(uppCL0[39]),
        .R(rst_r1));
  FDRE \uppCL0_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[3]),
        .Q(uppCL0[3]),
        .R(rst_r1));
  FDSE \uppCL0_reg[42] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[42]),
        .Q(uppCL0[42]),
        .S(rst_r1));
  FDRE \uppCL0_reg[43] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[43]),
        .Q(\uppCL0_reg[45]_0 [3]),
        .R(rst_r1));
  FDRE \uppCL0_reg[44] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[44]),
        .Q(\uppCL0_reg[45]_0 [4]),
        .R(rst_r1));
  FDRE \uppCL0_reg[45] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[45]),
        .Q(\uppCL0_reg[45]_0 [5]),
        .R(rst_r1));
  FDSE \uppCL0_reg[6] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[6]),
        .Q(uppCL0[6]),
        .S(rst_r1));
  FDRE \uppCL0_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[7]),
        .Q(\uppCL0_reg[45]_0 [0]),
        .R(rst_r1));
  FDRE \uppCL0_reg[8] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[8]),
        .Q(\uppCL0_reg[45]_0 [1]),
        .R(rst_r1));
  FDRE \uppCL0_reg[9] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL0[9]),
        .Q(\uppCL0_reg[45]_0 [2]),
        .R(rst_r1));
  FDSE \uppCL1_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[0]),
        .Q(uppCL1[0]),
        .S(rst_r1));
  FDSE \uppCL1_reg[12] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[12]),
        .Q(uppCL1[12]),
        .S(rst_r1));
  FDRE \uppCL1_reg[13] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[13]),
        .Q(uppCL1[13]),
        .R(rst_r1));
  FDRE \uppCL1_reg[14] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[14]),
        .Q(uppCL1[14]),
        .R(rst_r1));
  FDRE \uppCL1_reg[15] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[15]),
        .Q(uppCL1[15]),
        .R(rst_r1));
  FDSE \uppCL1_reg[18] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[18]),
        .Q(uppCL1[18]),
        .S(rst_r1));
  FDRE \uppCL1_reg[19] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[19]),
        .Q(uppCL1[19]),
        .R(rst_r1));
  FDRE \uppCL1_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[1]),
        .Q(uppCL1[1]),
        .R(rst_r1));
  FDRE \uppCL1_reg[20] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[20]),
        .Q(uppCL1[20]),
        .R(rst_r1));
  FDRE \uppCL1_reg[21] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[21]),
        .Q(uppCL1[21]),
        .R(rst_r1));
  FDSE \uppCL1_reg[24] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[24]),
        .Q(uppCL1[24]),
        .S(rst_r1));
  FDRE \uppCL1_reg[25] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[25]),
        .Q(uppCL1[25]),
        .R(rst_r1));
  FDRE \uppCL1_reg[26] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[26]),
        .Q(uppCL1[26]),
        .R(rst_r1));
  FDRE \uppCL1_reg[27] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[27]),
        .Q(uppCL1[27]),
        .R(rst_r1));
  FDRE \uppCL1_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[2]),
        .Q(uppCL1[2]),
        .R(rst_r1));
  FDSE \uppCL1_reg[30] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[30]),
        .Q(uppCL1[30]),
        .S(rst_r1));
  FDRE \uppCL1_reg[31] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[31]),
        .Q(uppCL1[31]),
        .R(rst_r1));
  FDRE \uppCL1_reg[32] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[32]),
        .Q(uppCL1[32]),
        .R(rst_r1));
  FDRE \uppCL1_reg[33] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[33]),
        .Q(uppCL1[33]),
        .R(rst_r1));
  FDSE \uppCL1_reg[36] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[36]),
        .Q(uppCL1[36]),
        .S(rst_r1));
  FDRE \uppCL1_reg[37] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[37]),
        .Q(uppCL1[37]),
        .R(rst_r1));
  FDRE \uppCL1_reg[38] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[38]),
        .Q(uppCL1[38]),
        .R(rst_r1));
  FDRE \uppCL1_reg[39] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[39]),
        .Q(uppCL1[39]),
        .R(rst_r1));
  FDRE \uppCL1_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[3]),
        .Q(uppCL1[3]),
        .R(rst_r1));
  FDSE \uppCL1_reg[42] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[42]),
        .Q(uppCL1[42]),
        .S(rst_r1));
  FDRE \uppCL1_reg[43] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[43]),
        .Q(\uppCL1_reg[45]_0 [3]),
        .R(rst_r1));
  FDRE \uppCL1_reg[44] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[44]),
        .Q(\uppCL1_reg[45]_0 [4]),
        .R(rst_r1));
  FDRE \uppCL1_reg[45] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[45]),
        .Q(\uppCL1_reg[45]_0 [5]),
        .R(rst_r1));
  FDSE \uppCL1_reg[6] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[6]),
        .Q(uppCL1[6]),
        .S(rst_r1));
  FDRE \uppCL1_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[7]),
        .Q(\uppCL1_reg[45]_0 [0]),
        .R(rst_r1));
  FDRE \uppCL1_reg[8] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[8]),
        .Q(\uppCL1_reg[45]_0 [1]),
        .R(rst_r1));
  FDRE \uppCL1_reg[9] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL1[9]),
        .Q(\uppCL1_reg[45]_0 [2]),
        .R(rst_r1));
  FDSE \uppCL2_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[0]),
        .Q(uppCL2[0]),
        .S(rst_r1));
  FDSE \uppCL2_reg[12] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[12]),
        .Q(uppCL2[12]),
        .S(rst_r1));
  FDRE \uppCL2_reg[13] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[13]),
        .Q(uppCL2[13]),
        .R(rst_r1));
  FDRE \uppCL2_reg[14] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[14]),
        .Q(uppCL2[14]),
        .R(rst_r1));
  FDRE \uppCL2_reg[15] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[15]),
        .Q(uppCL2[15]),
        .R(rst_r1));
  FDSE \uppCL2_reg[18] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[18]),
        .Q(uppCL2[18]),
        .S(rst_r1));
  FDRE \uppCL2_reg[19] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[19]),
        .Q(uppCL2[19]),
        .R(rst_r1));
  FDRE \uppCL2_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[1]),
        .Q(uppCL2[1]),
        .R(rst_r1));
  FDRE \uppCL2_reg[20] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[20]),
        .Q(uppCL2[20]),
        .R(rst_r1));
  FDRE \uppCL2_reg[21] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[21]),
        .Q(uppCL2[21]),
        .R(rst_r1));
  FDSE \uppCL2_reg[24] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[24]),
        .Q(uppCL2[24]),
        .S(rst_r1));
  FDRE \uppCL2_reg[25] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[25]),
        .Q(uppCL2[25]),
        .R(rst_r1));
  FDRE \uppCL2_reg[26] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[26]),
        .Q(uppCL2[26]),
        .R(rst_r1));
  FDRE \uppCL2_reg[27] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[27]),
        .Q(uppCL2[27]),
        .R(rst_r1));
  FDRE \uppCL2_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[2]),
        .Q(uppCL2[2]),
        .R(rst_r1));
  FDSE \uppCL2_reg[30] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[30]),
        .Q(uppCL2[30]),
        .S(rst_r1));
  FDRE \uppCL2_reg[31] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[31]),
        .Q(uppCL2[31]),
        .R(rst_r1));
  FDRE \uppCL2_reg[32] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[32]),
        .Q(uppCL2[32]),
        .R(rst_r1));
  FDRE \uppCL2_reg[33] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[33]),
        .Q(uppCL2[33]),
        .R(rst_r1));
  FDSE \uppCL2_reg[36] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[36]),
        .Q(uppCL2[36]),
        .S(rst_r1));
  FDRE \uppCL2_reg[37] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[37]),
        .Q(uppCL2[37]),
        .R(rst_r1));
  FDRE \uppCL2_reg[38] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[38]),
        .Q(uppCL2[38]),
        .R(rst_r1));
  FDRE \uppCL2_reg[39] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[39]),
        .Q(uppCL2[39]),
        .R(rst_r1));
  FDRE \uppCL2_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[3]),
        .Q(uppCL2[3]),
        .R(rst_r1));
  FDSE \uppCL2_reg[42] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[42]),
        .Q(uppCL2[42]),
        .S(rst_r1));
  FDRE \uppCL2_reg[43] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[43]),
        .Q(\uppCL2_reg[45]_0 [3]),
        .R(rst_r1));
  FDRE \uppCL2_reg[44] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[44]),
        .Q(\uppCL2_reg[45]_0 [4]),
        .R(rst_r1));
  FDRE \uppCL2_reg[45] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[45]),
        .Q(\uppCL2_reg[45]_0 [5]),
        .R(rst_r1));
  FDSE \uppCL2_reg[6] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[6]),
        .Q(uppCL2[6]),
        .S(rst_r1));
  FDRE \uppCL2_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[7]),
        .Q(\uppCL2_reg[45]_0 [0]),
        .R(rst_r1));
  FDRE \uppCL2_reg[8] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[8]),
        .Q(\uppCL2_reg[45]_0 [1]),
        .R(rst_r1));
  FDRE \uppCL2_reg[9] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL2[9]),
        .Q(\uppCL2_reg[45]_0 [2]),
        .R(rst_r1));
  FDSE \uppCL3_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[0]),
        .Q(uppCL3[0]),
        .S(rst_r1));
  FDSE \uppCL3_reg[12] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[12]),
        .Q(uppCL3[12]),
        .S(rst_r1));
  FDRE \uppCL3_reg[13] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[13]),
        .Q(uppCL3[13]),
        .R(rst_r1));
  FDRE \uppCL3_reg[14] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[14]),
        .Q(uppCL3[14]),
        .R(rst_r1));
  FDRE \uppCL3_reg[15] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[15]),
        .Q(uppCL3[15]),
        .R(rst_r1));
  FDSE \uppCL3_reg[18] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[18]),
        .Q(uppCL3[18]),
        .S(rst_r1));
  FDRE \uppCL3_reg[19] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[19]),
        .Q(uppCL3[19]),
        .R(rst_r1));
  FDRE \uppCL3_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[1]),
        .Q(uppCL3[1]),
        .R(rst_r1));
  FDRE \uppCL3_reg[20] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[20]),
        .Q(uppCL3[20]),
        .R(rst_r1));
  FDRE \uppCL3_reg[21] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[21]),
        .Q(uppCL3[21]),
        .R(rst_r1));
  FDSE \uppCL3_reg[24] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[24]),
        .Q(uppCL3[24]),
        .S(rst_r1));
  FDRE \uppCL3_reg[25] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[25]),
        .Q(uppCL3[25]),
        .R(rst_r1));
  FDRE \uppCL3_reg[26] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[26]),
        .Q(uppCL3[26]),
        .R(rst_r1));
  FDRE \uppCL3_reg[27] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[27]),
        .Q(uppCL3[27]),
        .R(rst_r1));
  FDRE \uppCL3_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[2]),
        .Q(uppCL3[2]),
        .R(rst_r1));
  FDSE \uppCL3_reg[30] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[30]),
        .Q(uppCL3[30]),
        .S(rst_r1));
  FDRE \uppCL3_reg[31] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[31]),
        .Q(uppCL3[31]),
        .R(rst_r1));
  FDRE \uppCL3_reg[32] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[32]),
        .Q(uppCL3[32]),
        .R(rst_r1));
  FDRE \uppCL3_reg[33] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[33]),
        .Q(uppCL3[33]),
        .R(rst_r1));
  FDSE \uppCL3_reg[36] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[36]),
        .Q(uppCL3[36]),
        .S(rst_r1));
  FDRE \uppCL3_reg[37] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[37]),
        .Q(uppCL3[37]),
        .R(rst_r1));
  FDRE \uppCL3_reg[38] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[38]),
        .Q(uppCL3[38]),
        .R(rst_r1));
  FDRE \uppCL3_reg[39] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[39]),
        .Q(uppCL3[39]),
        .R(rst_r1));
  FDRE \uppCL3_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[3]),
        .Q(uppCL3[3]),
        .R(rst_r1));
  FDSE \uppCL3_reg[42] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[42]),
        .Q(uppCL3[42]),
        .S(rst_r1));
  FDRE \uppCL3_reg[43] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[43]),
        .Q(\uppCL3_reg[45]_0 [3]),
        .R(rst_r1));
  FDRE \uppCL3_reg[44] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[44]),
        .Q(\uppCL3_reg[45]_0 [4]),
        .R(rst_r1));
  FDRE \uppCL3_reg[45] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[45]),
        .Q(\uppCL3_reg[45]_0 [5]),
        .R(rst_r1));
  FDSE \uppCL3_reg[6] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[6]),
        .Q(uppCL3[6]),
        .S(rst_r1));
  FDRE \uppCL3_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[7]),
        .Q(\uppCL3_reg[45]_0 [0]),
        .R(rst_r1));
  FDRE \uppCL3_reg[8] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[8]),
        .Q(\uppCL3_reg[45]_0 [1]),
        .R(rst_r1));
  FDRE \uppCL3_reg[9] 
       (.C(\SYNC[0].sync_reg_reg[1]_1 ),
        .CE(1'b1),
        .D(ub_uppCL3[9]),
        .Q(\uppCL3_reg[45]_0 [2]),
        .R(rst_r1));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_addr_decode" *) 
module ddr4_0_ddr4_v2_2_17_cal_addr_decode
   (cnt_clr_reg_0,
    out,
    calDone_reg_0,
    lrdimm_cmp_en_reg_0,
    clear_gt_data_ready_flag_reg_0,
    gt_data_ready_flag,
    io_ready_lvl_reg_0,
    D,
    ub_initDone_reg_0,
    en_vtc,
    rdCAS_reg_0,
    cal_clear_fifo_rden,
    wrCAS_reg_0,
    cal_timer_reg,
    stop_gate_tracking_ack_reg_0,
    a_b_cmd_sel_start_reg_0,
    wea,
    cal_oe_dis_low,
    cal_oe_dis_upp,
    \calSt_reg[2] ,
    \calSt_reg[0] ,
    ub_initDone_reg_1,
    rdCAS_reg_1,
    \cplx_CAS_reg[6] ,
    \cal_RAS_pre_reg[1]_0 ,
    \cal_RAS_pre_reg[2]_0 ,
    \cplx_RAS_reg[6] ,
    \cplx_RAS_reg[6]_0 ,
    \cal_ACT_n_pre_reg[7]_0 ,
    cal_CS_n,
    \init_cal_BA_reg[15] ,
    \cal_RST_CKE_ODT_PAR_reg[16]_0 ,
    ub_ready_reg_0,
    winAct_reg,
    cplx_cal_reg,
    calDone_reg_1,
    calDone_reg_2,
    mcalRank,
    calDone_reg_3,
    \init_cal_BA_reg[7] ,
    calDone_reg_4,
    \init_cal_BG_reg[7] ,
    calDone_reg_5,
    DQOut,
    DMOut,
    calDone_reg_6,
    calDone_reg_7,
    calDone_reg_8,
    calDone_reg_9,
    calDone_reg_10,
    calDone_reg_11,
    calDone_reg_12,
    calDone_reg_13,
    \wrQ_nxt[1]_13 ,
    \SYNC[0].sync_reg_reg[1] ,
    \cal_seq_rd_cnt_reg[7]_0 ,
    \cal_seq_cnt_reg[31]_0 ,
    \cal_CS_A_reg[6]_0 ,
    \cal_CS_A_reg[7]_0 ,
    \SYNC[20].sync_reg_reg[1] ,
    \cal_CS_A_reg[0]_0 ,
    \cplx_error_accum_reg[14] ,
    \cplx_error_accum_reg[15] ,
    \cplx_error_accum_reg[44] ,
    \cal_ADR_B_reg[12]_0 ,
    \cplx_error_accum_reg[19] ,
    \cal_ADR_A_reg[0]_0 ,
    \cal_timer_reg[29]_0 ,
    \cal_timer_reg[28]_0 ,
    \cal_timer_reg[25]_0 ,
    \cal_timer_reg[24]_0 ,
    \cal_timer_reg[21]_0 ,
    \cal_CS_B_reg[5]_0 ,
    \cal_CS_A_reg[5]_0 ,
    \cal_ADR_B_reg[30]_0 ,
    \cal_ADR_A_reg[30]_0 ,
    \SYNC[5].sync_reg_reg[1] ,
    \SYNC[5].sync_reg_reg[1]_0 ,
    \mcal_DQIn_byte_r1_reg[31]_0 ,
    \cal_ADR_A_reg[29]_0 ,
    \cal_ADR_A_reg[27]_0 ,
    \cal_ADR_A_reg[26]_0 ,
    \cal_ADR_B_reg[25]_0 ,
    \cal_ADR_B_reg[24]_0 ,
    \cal_ADR_A_reg[21]_0 ,
    \cal_ADR_A_reg[20]_0 ,
    \cal_ADR_B_reg[19]_0 ,
    \cal_ADR_B_reg[18]_0 ,
    \cal_ADR_B_reg[17]_0 ,
    \cal_RST_CKE_ODT_PAR_reg[16]_1 ,
    \cal_ADR_B_reg[15]_0 ,
    \cal_ADR_B_reg[13]_0 ,
    \cal_ADR_B_reg[11]_0 ,
    \cal_ADR_B_reg[10]_0 ,
    \cal_RST_CKE_ODT_PAR_reg[9]_0 ,
    \cal_ADR_A_reg[1]_0 ,
    \cal_RST_CKE_ODT_PAR_reg[30]_0 ,
    \cal_ADR_A_reg[4]_0 ,
    \cal_seq_cnt_reg[13]_0 ,
    mem_reg_bram_0,
    \cal_ADR_B_reg[31]_0 ,
    \SYNC[3].sync_reg_reg[1] ,
    \lowCL0_reg[45]_0 ,
    \SYNC[3].sync_reg_reg[1]_0 ,
    \SYNC[3].sync_reg_reg[1]_1 ,
    \SYNC[3].sync_reg_reg[1]_2 ,
    \SYNC[0].sync_reg_reg[1]_0 ,
    \SYNC[3].sync_reg_reg[1]_3 ,
    \SYNC[3].sync_reg_reg[1]_4 ,
    \lowCL1_reg[45]_0 ,
    \SYNC[3].sync_reg_reg[1]_5 ,
    \SYNC[3].sync_reg_reg[1]_6 ,
    \SYNC[3].sync_reg_reg[1]_7 ,
    \SYNC[3].sync_reg_reg[1]_8 ,
    \SYNC[3].sync_reg_reg[1]_9 ,
    \SYNC[3].sync_reg_reg[1]_10 ,
    \SYNC[3].sync_reg_reg[1]_11 ,
    \lowCL2_reg[45]_0 ,
    \SYNC[3].sync_reg_reg[1]_12 ,
    \SYNC[3].sync_reg_reg[1]_13 ,
    \SYNC[3].sync_reg_reg[1]_14 ,
    \SYNC[3].sync_reg_reg[1]_15 ,
    \SYNC[3].sync_reg_reg[1]_16 ,
    \lowCL3_reg[45]_0 ,
    \SYNC[3].sync_reg_reg[1]_17 ,
    \SYNC[3].sync_reg_reg[1]_18 ,
    \SYNC[3].sync_reg_reg[1]_19 ,
    \SYNC[3].sync_reg_reg[1]_20 ,
    \SYNC[3].sync_reg_reg[1]_21 ,
    \SYNC[3].sync_reg_reg[1]_22 ,
    \SYNC[3].sync_reg_reg[1]_23 ,
    \uppCL0_reg[45]_0 ,
    \SYNC[3].sync_reg_reg[1]_24 ,
    \SYNC[3].sync_reg_reg[1]_25 ,
    \SYNC[3].sync_reg_reg[1]_26 ,
    \SYNC[3].sync_reg_reg[1]_27 ,
    \SYNC[3].sync_reg_reg[1]_28 ,
    \uppCL1_reg[45]_0 ,
    \SYNC[3].sync_reg_reg[1]_29 ,
    \SYNC[3].sync_reg_reg[1]_30 ,
    \SYNC[3].sync_reg_reg[1]_31 ,
    \SYNC[3].sync_reg_reg[1]_32 ,
    \SYNC[3].sync_reg_reg[1]_33 ,
    \SYNC[3].sync_reg_reg[1]_34 ,
    \uppCL2_reg[45]_0 ,
    \SYNC[3].sync_reg_reg[1]_35 ,
    \SYNC[3].sync_reg_reg[1]_36 ,
    \SYNC[3].sync_reg_reg[1]_37 ,
    \SYNC[3].sync_reg_reg[1]_38 ,
    \SYNC[3].sync_reg_reg[1]_39 ,
    \SYNC[3].sync_reg_reg[1]_40 ,
    \uppCL3_reg[45]_0 ,
    \SYNC[3].sync_reg_reg[1]_41 ,
    \SYNC[3].sync_reg_reg[1]_42 ,
    \SYNC[3].sync_reg_reg[1]_43 ,
    \SYNC[3].sync_reg_reg[1]_44 ,
    \SYNC[3].sync_reg_reg[1]_45 ,
    \SYNC[5].sync_reg_reg[1]_1 ,
    \SYNC[5].sync_reg_reg[1]_2 ,
    \SYNC[5].sync_reg_reg[1]_3 ,
    \SYNC[5].sync_reg_reg[1]_4 ,
    \cal_ADR_A_reg[22]_0 ,
    \SYNC[5].sync_reg_reg[1]_5 ,
    \SYNC[5].sync_reg_reg[1]_6 ,
    \SYNC[5].sync_reg_reg[1]_7 ,
    \SYNC[5].sync_reg_reg[1]_8 ,
    \SYNC[5].sync_reg_reg[1]_9 ,
    \SYNC[5].sync_reg_reg[1]_10 ,
    \SYNC[5].sync_reg_reg[1]_11 ,
    \SYNC[5].sync_reg_reg[1]_12 ,
    \SYNC[5].sync_reg_reg[1]_13 ,
    \genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9]_0 ,
    \genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8]_0 ,
    \SYNC[4].sync_reg_reg[1] ,
    \SYNC[5].sync_reg_reg[1]_14 ,
    \cal_ADR_A_reg[4]_1 ,
    \cal_CS_A_reg[4]_0 ,
    \SYNC[4].sync_reg_reg[1]_0 ,
    \rd_vref_value_reg[46]_0 ,
    \mcal_DMIn_bit_r1_reg[7]_0 ,
    \cal_ADR_A_reg[3]_0 ,
    \SYNC[5].sync_reg_reg[1]_15 ,
    \cal_ADR_A_reg[2]_0 ,
    \SYNC[18].sync_reg_reg[1] ,
    \SYNC[5].sync_reg_reg[1]_16 ,
    gt_data_ready_flag_reg_0,
    cplx_status,
    \cal_ADR_A_reg[0]_1 ,
    rst_r1_reg_0,
    S,
    \delay_cntr_reg[2]_0 ,
    lrdimm_cal_mode_reg_0,
    lrdimm_cal_mode_reg_1,
    \SYNC[5].sync_reg_reg[1]_17 ,
    \rd_vref_value_reg[42]_0 ,
    mcal_rd_vref_value,
    \rd_vref_value_reg[43]_0 ,
    \rd_vref_value_reg[44]_0 ,
    \rd_vref_value_reg[45]_0 ,
    \rd_vref_value_reg[48]_0 ,
    in0,
    \rsMask_reg[7][18] ,
    rst_r1_reg_1,
    \wosp_reg[1] ,
    \wosp_reg[2]_rep ,
    \wosp_reg[2]_rep_0 ,
    \wosp_reg[1]_0 ,
    \wosp_reg[2]_rep__2 ,
    \wosp_reg[2]_rep__1 ,
    \wosp_reg[2]_rep__1_0 ,
    \wosp_reg[2]_rep__1_1 ,
    \wosp_reg[2]_rep__1_2 ,
    \wosp_reg[2]_rep__1_3 ,
    \wosp_reg[2]_rep__1_4 ,
    \wosp_reg[2]_rep__1_5 ,
    \wosp_reg[2]_rep__1_6 ,
    \wosp_reg[2]_rep__1_7 ,
    \wosp_reg[2]_rep__1_8 ,
    \wosp_reg[2]_rep__1_9 ,
    \wosp_reg[2]_rep__1_10 ,
    \wosp_reg[2]_rep__2_0 ,
    \wosp_reg[2]_rep__1_11 ,
    \wosp_reg[2]_rep__2_1 ,
    \wosp_reg[2]_rep__2_2 ,
    \wosp_reg[2]_rep__2_3 ,
    \wosp_reg[2]_rep__2_4 ,
    \wosp_reg[2]_rep__2_5 ,
    \wosp_reg[2]_rep__2_6 ,
    \wosp_reg[2]_rep__2_7 ,
    \wosp_reg[2]_rep__2_8 ,
    \wosp_reg[2]_rep__2_9 ,
    \wosp_reg[2]_rep__2_10 ,
    \wosp_reg[1]_1 ,
    \wosp_reg[1]_2 ,
    \wosp_reg[1]_3 ,
    \wosp_reg[1]_4 ,
    \wosp_reg[1]_5 ,
    \wosp_reg[1]_6 ,
    \wosp_reg[1]_7 ,
    \wosp_reg[1]_8 ,
    \wosp_reg[1]_9 ,
    \wosp_reg[1]_10 ,
    \wosp_reg[1]_11 ,
    \wosp_reg[1]_12 ,
    \wosp_reg[1]_13 ,
    \wosp_reg[1]_14 ,
    \wosp_reg[1]_15 ,
    \wosp_reg[1]_16 ,
    \wosp_reg[1]_17 ,
    \wosp_reg[2]_rep_1 ,
    \wosp_reg[2]_rep_2 ,
    \wosp_reg[1]_18 ,
    \wosp_reg[2]_rep__3 ,
    \wosp_reg[2]_rep__2_11 ,
    \wosp_reg[2]_rep__2_12 ,
    \wosp_reg[2]_rep__2_13 ,
    \wosp_reg[2]_rep__2_14 ,
    \wosp_reg[2]_rep__2_15 ,
    \wosp_reg[2]_rep__2_16 ,
    \wosp_reg[2]_rep__2_17 ,
    \wosp_reg[2]_rep__2_18 ,
    \wosp_reg[2]_rep__2_19 ,
    \wosp_reg[2]_rep__2_20 ,
    \wosp_reg[2]_rep__2_21 ,
    \wosp_reg[2]_rep__2_22 ,
    \wosp_reg[2]_rep__2_23 ,
    \wosp_reg[2]_rep__2_24 ,
    \wosp_reg[2]_rep__2_25 ,
    \wosp_reg[2]_rep__2_26 ,
    \wosp_reg[2]_rep__2_27 ,
    \wosp_reg[2]_rep__2_28 ,
    \wosp_reg[2]_rep__2_29 ,
    \wosp_reg[2]_rep__2_30 ,
    \wosp_reg[2]_rep__2_31 ,
    \wosp_reg[2]_rep__2_32 ,
    \wosp_reg[2]_rep__2_33 ,
    \wosp_reg[2]_rep__2_34 ,
    \wosp_reg[1]_19 ,
    \wosp_reg[1]_20 ,
    \wosp_reg[1]_21 ,
    \wosp_reg[1]_22 ,
    \wosp_reg[1]_23 ,
    \wosp_reg[1]_24 ,
    \wosp_reg[1]_25 ,
    \wosp_reg[1]_26 ,
    \wosp_reg[1]_27 ,
    \wosp_reg[1]_28 ,
    \wosp_reg[1]_29 ,
    \wosp_reg[1]_30 ,
    \wosp_reg[1]_31 ,
    \wosp_reg[1]_32 ,
    \wosp_reg[1]_33 ,
    \wosp_reg[1]_34 ,
    \wosp_reg[1]_35 ,
    \wosp_reg[2]_rep_3 ,
    \wosp_reg[2]_rep_4 ,
    \wosp_reg[1]_36 ,
    \wosp_reg[2]_rep__3_0 ,
    \wosp_reg[2]_rep__3_1 ,
    \wosp_reg[2]_rep__3_2 ,
    \wosp_reg[2]_rep__3_3 ,
    \wosp_reg[2]_rep__3_4 ,
    \wosp_reg[2]_rep__3_5 ,
    \wosp_reg[2]_rep__3_6 ,
    \wosp_reg[2]_rep__3_7 ,
    \wosp_reg[2]_rep__3_8 ,
    \wosp_reg[2]_rep__3_9 ,
    \wosp_reg[2]_rep__3_10 ,
    \wosp_reg[2]_rep__3_11 ,
    \wosp_reg[2]_rep__3_12 ,
    \wosp_reg[2]_rep__3_13 ,
    \wosp_reg[2]_rep__3_14 ,
    \wosp_reg[2]_rep__3_15 ,
    \wosp_reg[2]_rep__3_16 ,
    \wosp_reg[2]_rep__3_17 ,
    \wosp_reg[2]_rep__3_18 ,
    \wosp_reg[2]_rep__3_19 ,
    \wosp_reg[2]_rep__3_20 ,
    \wosp_reg[2]_rep__3_21 ,
    \wosp_reg[2]_rep__3_22 ,
    \wosp_reg[2]_rep__3_23 ,
    \wosp_reg[2]_rep__3_24 ,
    \wosp_reg[1]_37 ,
    \wosp_reg[1]_38 ,
    \wosp_reg[1]_39 ,
    \wosp_reg[1]_40 ,
    \wosp_reg[1]_41 ,
    \wosp_reg[1]_42 ,
    \wosp_reg[1]_43 ,
    \wosp_reg[1]_44 ,
    \wosp_reg[1]_45 ,
    \wosp_reg[1]_46 ,
    \wosp_reg[1]_47 ,
    \wosp_reg[1]_48 ,
    \wosp_reg[1]_49 ,
    \wosp_reg[1]_50 ,
    \wosp_reg[1]_51 ,
    \wosp_reg[1]_52 ,
    \wosp_reg[1]_53 ,
    \wosp_reg[2]_rep__0 ,
    \wosp_reg[2]_rep__0_0 ,
    \wosp_reg[1]_54 ,
    \wosp_reg[2]_rep__4 ,
    \wosp_reg[2]_rep__3_25 ,
    \wosp_reg[2]_rep__3_26 ,
    \wosp_reg[2]_rep__3_27 ,
    \wosp_reg[2]_rep__3_28 ,
    \wosp_reg[2]_rep__3_29 ,
    \wosp_reg[2]_rep__3_30 ,
    \wosp_reg[2]_rep__3_31 ,
    \wosp_reg[2]_rep__3_32 ,
    \wosp_reg[2]_rep__3_33 ,
    \wosp_reg[2]_rep__4_0 ,
    \wosp_reg[2]_rep__4_1 ,
    \wosp_reg[2]_rep__4_2 ,
    \wosp_reg[2]_rep__4_3 ,
    \wosp_reg[2]_rep__4_4 ,
    \wosp_reg[2]_rep__4_5 ,
    \wosp_reg[2]_rep__4_6 ,
    \wosp_reg[2]_rep__4_7 ,
    \wosp_reg[2]_rep__4_8 ,
    \wosp_reg[2]_rep__4_9 ,
    \wosp_reg[2]_rep__4_10 ,
    \wosp_reg[2]_rep__4_11 ,
    \wosp_reg[2]_rep__4_12 ,
    \wosp_reg[2]_rep__4_13 ,
    \wosp_reg[2]_rep__4_14 ,
    \wosp_reg[1]_55 ,
    \wosp_reg[1]_56 ,
    \wosp_reg[1]_57 ,
    \wosp_reg[1]_58 ,
    \wosp_reg[1]_59 ,
    \wosp_reg[1]_60 ,
    \wosp_reg[1]_61 ,
    \wosp_reg[1]_62 ,
    \wosp_reg[1]_63 ,
    \wosp_reg[1]_64 ,
    \wosp_reg[1]_65 ,
    \wosp_reg[1]_66 ,
    \wosp_reg[1]_67 ,
    \wosp_reg[1]_68 ,
    \wosp_reg[1]_69 ,
    \wosp_reg[1]_70 ,
    \wosp_reg[1]_71 ,
    \wosp_reg[2]_rep__0_1 ,
    \wosp_reg[2]_rep__0_2 ,
    \wosp_reg[1]_72 ,
    \wosp_reg[2]_rep__5 ,
    \wosp_reg[2]_rep__4_15 ,
    \wosp_reg[2]_rep__4_16 ,
    \wosp_reg[2]_rep__4_17 ,
    \wosp_reg[2]_rep__4_18 ,
    \wosp_reg[2]_rep__4_19 ,
    \wosp_reg[2]_rep__4_20 ,
    \wosp_reg[2]_rep__4_21 ,
    \wosp_reg[2]_rep__4_22 ,
    \wosp_reg[2]_rep__4_23 ,
    \wosp_reg[2]_rep__4_24 ,
    \wosp_reg[2]_rep__4_25 ,
    \wosp_reg[2]_rep__4_26 ,
    \wosp_reg[2]_rep__4_27 ,
    \wosp_reg[2]_rep__4_28 ,
    \wosp_reg[2]_rep__4_29 ,
    \wosp_reg[2]_rep__4_30 ,
    \wosp_reg[2]_rep__4_31 ,
    \wosp_reg[2]_rep__4_32 ,
    \wosp_reg[2]_rep__5_0 ,
    \wosp_reg[2]_rep__4_33 ,
    \wosp_reg[2]_rep__5_1 ,
    \wosp_reg[2]_rep__5_2 ,
    \wosp_reg[2]_rep__5_3 ,
    \wosp_reg[2]_rep__5_4 ,
    \wosp_reg[1]_73 ,
    \wosp_reg[1]_74 ,
    \wosp_reg[1]_75 ,
    \wosp_reg[1]_76 ,
    \wosp_reg[1]_77 ,
    \wosp_reg[1]_78 ,
    \wosp_reg[1]_79 ,
    \wosp_reg[1]_80 ,
    \wosp_reg[1]_81 ,
    \wosp_reg[1]_82 ,
    \wosp_reg[1]_83 ,
    \wosp_reg[1]_84 ,
    \wosp_reg[1]_85 ,
    \wosp_reg[1]_86 ,
    \wosp_reg[1]_87 ,
    \wosp_reg[1]_88 ,
    \wosp_reg[1]_89 ,
    \wosp_reg[2]_rep__0_3 ,
    \wosp_reg[2]_rep__0_4 ,
    \wosp_reg[1]_90 ,
    \wosp_reg[2]_rep__5_5 ,
    \wosp_reg[2]_rep__5_6 ,
    \wosp_reg[2]_rep__5_7 ,
    \wosp_reg[2]_rep__5_8 ,
    \wosp_reg[2]_rep__5_9 ,
    \wosp_reg[2]_rep__5_10 ,
    \wosp_reg[2]_rep__5_11 ,
    \wosp_reg[2]_rep__5_12 ,
    \wosp_reg[2]_rep__5_13 ,
    \wosp_reg[2]_rep__5_14 ,
    \wosp_reg[2]_rep__5_15 ,
    \wosp_reg[2]_rep__5_16 ,
    \wosp_reg[2]_rep__5_17 ,
    \wosp_reg[2]_rep__5_18 ,
    \wosp_reg[2]_rep__5_19 ,
    \wosp_reg[2]_rep__5_20 ,
    \wosp_reg[2]_rep__5_21 ,
    \wosp_reg[2]_rep__5_22 ,
    \wosp_reg[2]_rep__5_23 ,
    \wosp_reg[2]_rep__5_24 ,
    \wosp_reg[2]_rep__5_25 ,
    \wosp_reg[2]_rep__5_26 ,
    \wosp_reg[2]_rep__5_27 ,
    \wosp_reg[2]_rep__5_28 ,
    \wosp_reg[2]_rep__5_29 ,
    \wosp_reg[1]_91 ,
    \wosp_reg[1]_92 ,
    \wosp_reg[1]_93 ,
    \wosp_reg[1]_94 ,
    \wosp_reg[1]_95 ,
    \wosp_reg[1]_96 ,
    \wosp_reg[1]_97 ,
    \wosp_reg[1]_98 ,
    \wosp_reg[1]_99 ,
    \wosp_reg[1]_100 ,
    \wosp_reg[1]_101 ,
    \wosp_reg[1]_102 ,
    \wosp_reg[1]_103 ,
    \wosp_reg[1]_104 ,
    \wosp_reg[1]_105 ,
    \wosp_reg[1]_106 ,
    \wosp_reg[1]_107 ,
    \wosp_reg[2]_rep__1_12 ,
    \wosp_reg[2]_rep__1_13 ,
    \wosp_reg[1]_108 ,
    \wosp_reg[2]_rep__6 ,
    \wosp_reg[2]_rep__5_30 ,
    \wosp_reg[2]_rep__5_31 ,
    \wosp_reg[2]_rep__5_32 ,
    \wosp_reg[2]_rep__6_0 ,
    \wosp_reg[2]_rep__5_33 ,
    \wosp_reg[2]_rep__6_1 ,
    \wosp_reg[2]_rep__6_2 ,
    \wosp_reg[2]_rep__6_3 ,
    \wosp_reg[2]_rep__6_4 ,
    \wosp_reg[2]_rep__6_5 ,
    \wosp_reg[2]_rep__6_6 ,
    \wosp_reg[2]_rep__6_7 ,
    \wosp_reg[2]_rep__6_8 ,
    \wosp_reg[2]_rep__6_9 ,
    \wosp_reg[2]_rep__6_10 ,
    \wosp_reg[2]_rep__6_11 ,
    \wosp_reg[2]_rep__6_12 ,
    \wosp_reg[2]_rep__6_13 ,
    \wosp_reg[2]_rep__6_14 ,
    \wosp_reg[2]_rep__6_15 ,
    \wosp_reg[2]_rep__6_16 ,
    \wosp_reg[2]_rep__6_17 ,
    \wosp_reg[2]_rep__6_18 ,
    \wosp_reg[2]_rep__6_19 ,
    \wosp_reg[1]_109 ,
    \wosp_reg[1]_110 ,
    \wosp_reg[1]_111 ,
    \wosp_reg[1]_112 ,
    \wosp_reg[1]_113 ,
    \wosp_reg[1]_114 ,
    \wosp_reg[1]_115 ,
    \wosp_reg[1]_116 ,
    \wosp_reg[1]_117 ,
    \wosp_reg[1]_118 ,
    \wosp_reg[1]_119 ,
    \wosp_reg[1]_120 ,
    \wosp_reg[1]_121 ,
    \wosp_reg[1]_122 ,
    \wosp_reg[1]_123 ,
    \wosp_reg[1]_124 ,
    \wosp_reg[1]_125 ,
    \wosp_reg[2] ,
    \wosp_reg[2]_0 ,
    \wosp_reg[1]_126 ,
    \wosp_reg[2]_rep__6_20 ,
    \wosp_reg[2]_rep__7 ,
    \wosp_reg[2]_rep__7_0 ,
    \wosp_reg[2]_rep__6_21 ,
    \wosp_reg[2]_rep__6_22 ,
    \wosp_reg[2]_rep__6_23 ,
    \wosp_reg[2]_rep__6_24 ,
    \wosp_reg[2]_rep__6_25 ,
    \wosp_reg[2]_rep__6_26 ,
    \wosp_reg[2]_rep__6_27 ,
    \wosp_reg[2]_rep__6_28 ,
    \wosp_reg[2]_rep__6_29 ,
    \wosp_reg[2]_rep__6_30 ,
    \wosp_reg[2]_rep__6_31 ,
    \wosp_reg[2]_rep__6_32 ,
    \wosp_reg[2]_rep__6_33 ,
    \wosp_reg[2]_rep__6_34 ,
    \wosp_reg[2]_rep__6_35 ,
    \wosp_reg[2]_rep__6_36 ,
    \wosp_reg[2]_rep__6_37 ,
    \wosp_reg[2]_rep__6_38 ,
    \wosp_reg[2]_rep__6_39 ,
    \wosp_reg[2]_rep__6_40 ,
    \wosp_reg[2]_rep__6_41 ,
    \wosp_reg[2]_rep__6_42 ,
    \wosp_reg[1]_127 ,
    \wosp_reg[1]_128 ,
    \wosp_reg[1]_129 ,
    \wosp_reg[1]_130 ,
    \wosp_reg[1]_131 ,
    \wosp_reg[1]_132 ,
    \wosp_reg[1]_133 ,
    \wosp_reg[1]_134 ,
    \wosp_reg[1]_135 ,
    \wosp_reg[1]_136 ,
    \wosp_reg[1]_137 ,
    \wosp_reg[1]_138 ,
    \wosp_reg[1]_139 ,
    \wosp_reg[1]_140 ,
    \wosp_reg[1]_141 ,
    \wosp_reg[1]_142 ,
    rst_r1_reg_2,
    rst_r1_reg_3,
    rst_r1_reg_4,
    rst_r1_reg_5,
    rst_r1_reg_6,
    rst_r1_reg_7,
    rst_r1_reg_8,
    rst_r1_reg_9,
    rst_r1_reg_10,
    rst_r1_reg_11,
    rst_r1_reg_12,
    rst_r1_reg_13,
    rst_r1_reg_14,
    \mcal_DQIn_byte_r1_reg[48]_0 ,
    \io_read_data_reg[31]_0 ,
    bisc_byte,
    \xsdb_wr_data_reg[8]_0 ,
    \max_rd_lat_reg[5]_0 ,
    \cal_RST_CKE_ODT_PAR_reg[7]_0 ,
    \cplx_error_accum_reg[63] ,
    \odt_shift_reg[0][17] ,
    SR,
    io_addr_strobe_r1_reg_0,
    calDone_reg_14,
    io_write_data,
    lrdimm_cmp_clr,
    lrdimm_cal_mode_reg_2,
    p_52_in,
    clear_gt_data_ready_flag,
    gt_data_ready_flag_nxt,
    ub_ready_reg_1,
    E,
    wren_reg_0,
    \clb2phy_wrcs0_low_reg[31]_0 ,
    O,
    \cal_timer_reg[15]_0 ,
    \cal_timer_reg[23]_0 ,
    \cal_timer_reg[31]_0 ,
    stop_gate_tracking_ack_reg_1,
    cnt_clr_reg_1,
    a_b_cmd_sel_start_reg_1,
    lrdimm_cmp_en_reg_1,
    cal_seq_cnt_gt_0_reg_0,
    xsdb_wr_en_reg_0,
    \cal_oe_dis_low_reg[7]_0 ,
    \cal_oe_dis_upp_reg[7]_0 ,
    Q,
    pllGate,
    \init_cal_RESET_n_reg[7] ,
    init_cal_RESET_n,
    \mcal_ADR_dly_reg[0][134] ,
    \mcal_ADR_dly_reg[0][87] ,
    \mcal_BA_dly_reg[0][15] ,
    \mcal_BA_dly_reg[0][8] ,
    \mcal_ODT_dly_reg[0][4] ,
    mc_BA,
    init_cal_CKE,
    mc_CKE7,
    mc_CKE,
    mc_ODT,
    mc_ODT7,
    winAct,
    mc_CS_n,
    init_cal_CS_n,
    mc_CS_n7,
    mcRdCAS,
    mcCasSlot2,
    \mcal_ADR_dly_reg[0][135] ,
    mc_ADR,
    \mcal_ADR_dly_reg[0][128] ,
    mc_BG,
    p_1_in,
    \mcal_PAR_dly_reg[0][5] ,
    \mcal_PAR_dly_reg[0][3] ,
    \mcal_PAR_dly_reg[0][1] ,
    \mcal_PAR_dly_reg[0][0] ,
    \mcal_PAR_dly_reg[0][7] ,
    \dReg_reg[15] ,
    mcWrCAS,
    \wrQ_reg[1][0] ,
    \rsMask_reg[1]_71 ,
    \rsMask_reg[3]_73 ,
    \rsMask_reg[1]_79 ,
    \rsMask_reg[3]_81 ,
    \cplx_config_reg[16]_0 ,
    io_address,
    \cplx_config_reg[16]_1 ,
    cnt_clr_access,
    a_b_cmd_sel_start0,
    \cal_timer_reg[0]_0 ,
    \addr_dec_to_mb_data[7]_i_7_0 ,
    io_ready_reg_0,
    \addr_dec_to_mb_data_reg[15]_0 ,
    \addr_dec_to_mb_data_reg[19]_0 ,
    \addr_dec_to_mb_data_reg[12]_0 ,
    \addr_dec_to_mb_data[0]_i_3 ,
    io_ready_reg_1,
    io_ready_reg_2,
    \addr_dec_to_mb_data_reg[29]_0 ,
    \addr_dec_to_mb_data_reg[29]_1 ,
    \addr_dec_to_mb_data_reg[14]_0 ,
    \addr_dec_to_mb_data_reg[29]_2 ,
    \addr_dec_to_mb_data_reg[29]_3 ,
    \addr_dec_to_mb_data_reg[29]_4 ,
    \addr_dec_to_mb_data[4]_i_11 ,
    douta,
    \addr_dec_to_mb_data[31]_i_3 ,
    wrDataEn_pi,
    rdDataEn_pi,
    \addr_dec_to_mb_data[6]_i_7 ,
    \addr_dec_to_mb_data[6]_i_7_0 ,
    \rsMask_reg[7]_77 ,
    \rsMask_reg[5]_75 ,
    \rsMask_reg[7]_85 ,
    \rsMask_reg[5]_83 ,
    \rdEn_reg[29] ,
    \rdEn_reg[29]_0 ,
    \rdEn_reg[28] ,
    wosp,
    \dReg_reg[9] ,
    wrDataVal,
    \dReg_reg[9]_0 ,
    \dReg_reg[11] ,
    \dReg_reg[10] ,
    \dReg_reg[9]_1 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[8] ,
    \dReg_reg[8]_0 ,
    \rdEn_reg[29]_1 ,
    \rdEn_reg[28]_0 ,
    \rdEn_reg[29]_2 ,
    \rdEn_reg[28]_1 ,
    \rdEn_reg[29]_3 ,
    \rdEn_reg[28]_2 ,
    \rdEn_reg[29]_4 ,
    \rdEn_reg[28]_3 ,
    \rdEn_reg[29]_5 ,
    \rdEn_reg[28]_4 ,
    \rdEn_reg[29]_6 ,
    \rdEn_reg[28]_5 ,
    \rdEn_reg[29]_7 ,
    \rdEn_reg[28]_6 ,
    \rdEn_reg[29]_8 ,
    \rdEn_reg[28]_7 ,
    \rdEn_reg[29]_9 ,
    \rdEn_reg[28]_8 ,
    \rdEn_reg[29]_10 ,
    \rdEn_reg[28]_9 ,
    \rdEn_reg[29]_11 ,
    \rdEn_reg[28]_10 ,
    \rdEn_reg[29]_12 ,
    \rdEn_reg[28]_11 ,
    \rdEn_reg[29]_13 ,
    \rdEn_reg[28]_12 ,
    \cal_seq_reg[2]_0 ,
    \dqin_valid_shift_reg[0]_0 ,
    \mcal_DQIn_r_reg[511]_0 ,
    \cal_cmp_en_reg[7]_0 ,
    \cal_DQPat_A_reg[63]_0 ,
    \cal_DQPat_A_reg[31]_0 ,
    \cal_DQPat_B_reg[63]_0 ,
    \cal_DQPat_B_reg[31]_0 ,
    \cmp_byte_reg[2]_0 ,
    \cal_cs_pos_reg[1]_0 ,
    \cplx_config_reg[0]_0 ,
    \cplx_config_reg[1]_0 ,
    \cal_seq_a_b_dly_reg[7]_0 ,
    \cal_seq_a_a_dly_reg[7]_0 ,
    \cal_seq_b_a_dly_reg[7]_0 ,
    \cal_RST_CKE_ODT_PAR_reg[31]_0 ,
    \traffic_instr_nxt_instr_r1_reg[5]_0 ,
    \uppCL3_reg[42]_0 ,
    \uppCL0_reg[47]_0 ,
    \uppCL1_reg[47]_0 ,
    \uppCL2_reg[47]_0 ,
    \uppCL3_reg[47]_0 ,
    \cal_CS_A_reg[7]_1 ,
    \cal_CS_B_reg[7]_0 ,
    \mcal_DMIn_n_r_reg[63]_0 ,
    \cal_ADR_A_reg[31]_0 ,
    \cal_ADR_B_reg[31]_1 ,
    \addr_dec_to_mb_data_reg[31]_0 ,
    \addr_dec_to_mb_data_reg[30]_0 ,
    \addr_dec_to_mb_data_reg[30]_1 ,
    \addr_dec_to_mb_data_reg[29]_5 ,
    \addr_dec_to_mb_data_reg[28]_0 ,
    \addr_dec_to_mb_data_reg[27]_0 ,
    \addr_dec_to_mb_data_reg[26]_0 ,
    \addr_dec_to_mb_data_reg[25]_0 ,
    \addr_dec_to_mb_data_reg[24]_0 ,
    \addr_dec_to_mb_data_reg[23]_0 ,
    \addr_dec_to_mb_data_reg[22]_0 ,
    \addr_dec_to_mb_data_reg[21]_0 ,
    \addr_dec_to_mb_data_reg[20]_0 ,
    \bisc_bit_reg[0]_0 ,
    \cal_DQOut_A_reg[63]_0 ,
    \cal_DQOut_A_reg[31]_0 ,
    \cal_DQOut_pre_reg[63]_0 ,
    \cal_DQOut_pre_reg[31]_0 ,
    \cal_DQOut_post_reg[63]_0 ,
    \cal_DQOut_post_reg[31]_0 ,
    \cal_DMOut_n_A_reg[31]_0 ,
    \genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ,
    \genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ,
    \cal_CAS_A_reg[0]_0 ,
    \cal_RAS_B_reg[0]_0 ,
    \cal_ACT_n_A_reg[7]_0 ,
    \max_rd_lat_reg[5]_1 ,
    rd_vref_value0_out,
    init_cal_BG);
  output cnt_clr_reg_0;
  output out;
  output calDone_reg_0;
  output lrdimm_cmp_en_reg_0;
  output clear_gt_data_ready_flag_reg_0;
  output gt_data_ready_flag;
  output [0:0]io_ready_lvl_reg_0;
  output [0:0]D;
  output ub_initDone_reg_0;
  output en_vtc;
  output rdCAS_reg_0;
  output cal_clear_fifo_rden;
  output wrCAS_reg_0;
  output [31:0]cal_timer_reg;
  output stop_gate_tracking_ack_reg_0;
  output a_b_cmd_sel_start_reg_0;
  output wea;
  output [0:0]cal_oe_dis_low;
  output [0:0]cal_oe_dis_upp;
  output [0:0]\calSt_reg[2] ;
  output [0:0]\calSt_reg[0] ;
  output ub_initDone_reg_1;
  output rdCAS_reg_1;
  output [7:0]\cplx_CAS_reg[6] ;
  output \cal_RAS_pre_reg[1]_0 ;
  output \cal_RAS_pre_reg[2]_0 ;
  output \cplx_RAS_reg[6] ;
  output \cplx_RAS_reg[6]_0 ;
  output [5:0]\cal_ACT_n_pre_reg[7]_0 ;
  output [3:0]cal_CS_n;
  output [8:0]\init_cal_BA_reg[15] ;
  output [2:0]\cal_RST_CKE_ODT_PAR_reg[16]_0 ;
  output [2:0]ub_ready_reg_0;
  output [1:0]winAct_reg;
  output [3:0]cplx_cal_reg;
  output calDone_reg_1;
  output calDone_reg_2;
  output [1:0]mcalRank;
  output [76:0]calDone_reg_3;
  output \init_cal_BA_reg[7] ;
  output [3:0]calDone_reg_4;
  output \init_cal_BG_reg[7] ;
  output [7:0]calDone_reg_5;
  output [511:0]DQOut;
  output [63:0]DMOut;
  output calDone_reg_6;
  output calDone_reg_7;
  output calDone_reg_8;
  output calDone_reg_9;
  output calDone_reg_10;
  output calDone_reg_11;
  output calDone_reg_12;
  output calDone_reg_13;
  output [0:0]\wrQ_nxt[1]_13 ;
  output \SYNC[0].sync_reg_reg[1] ;
  output [7:0]\cal_seq_rd_cnt_reg[7]_0 ;
  output [31:0]\cal_seq_cnt_reg[31]_0 ;
  output \cal_CS_A_reg[6]_0 ;
  output \cal_CS_A_reg[7]_0 ;
  output \SYNC[20].sync_reg_reg[1] ;
  output \cal_CS_A_reg[0]_0 ;
  output \cplx_error_accum_reg[14] ;
  output \cplx_error_accum_reg[15] ;
  output \cplx_error_accum_reg[44] ;
  output \cal_ADR_B_reg[12]_0 ;
  output \cplx_error_accum_reg[19] ;
  output \cal_ADR_A_reg[0]_0 ;
  output \cal_timer_reg[29]_0 ;
  output \cal_timer_reg[28]_0 ;
  output \cal_timer_reg[25]_0 ;
  output \cal_timer_reg[24]_0 ;
  output \cal_timer_reg[21]_0 ;
  output [4:0]\cal_CS_B_reg[5]_0 ;
  output [4:0]\cal_CS_A_reg[5]_0 ;
  output [12:0]\cal_ADR_B_reg[30]_0 ;
  output [11:0]\cal_ADR_A_reg[30]_0 ;
  output \SYNC[5].sync_reg_reg[1] ;
  output \SYNC[5].sync_reg_reg[1]_0 ;
  output \mcal_DQIn_byte_r1_reg[31]_0 ;
  output \cal_ADR_A_reg[29]_0 ;
  output \cal_ADR_A_reg[27]_0 ;
  output \cal_ADR_A_reg[26]_0 ;
  output \cal_ADR_B_reg[25]_0 ;
  output \cal_ADR_B_reg[24]_0 ;
  output \cal_ADR_A_reg[21]_0 ;
  output \cal_ADR_A_reg[20]_0 ;
  output \cal_ADR_B_reg[19]_0 ;
  output \cal_ADR_B_reg[18]_0 ;
  output \cal_ADR_B_reg[17]_0 ;
  output \cal_RST_CKE_ODT_PAR_reg[16]_1 ;
  output \cal_ADR_B_reg[15]_0 ;
  output \cal_ADR_B_reg[13]_0 ;
  output \cal_ADR_B_reg[11]_0 ;
  output \cal_ADR_B_reg[10]_0 ;
  output \cal_RST_CKE_ODT_PAR_reg[9]_0 ;
  output \cal_ADR_A_reg[1]_0 ;
  output [10:0]\cal_RST_CKE_ODT_PAR_reg[30]_0 ;
  output \cal_ADR_A_reg[4]_0 ;
  output \cal_seq_cnt_reg[13]_0 ;
  output mem_reg_bram_0;
  output \cal_ADR_B_reg[31]_0 ;
  output \SYNC[3].sync_reg_reg[1] ;
  output [31:0]\lowCL0_reg[45]_0 ;
  output \SYNC[3].sync_reg_reg[1]_0 ;
  output \SYNC[3].sync_reg_reg[1]_1 ;
  output \SYNC[3].sync_reg_reg[1]_2 ;
  output \SYNC[0].sync_reg_reg[1]_0 ;
  output \SYNC[3].sync_reg_reg[1]_3 ;
  output \SYNC[3].sync_reg_reg[1]_4 ;
  output [31:0]\lowCL1_reg[45]_0 ;
  output \SYNC[3].sync_reg_reg[1]_5 ;
  output \SYNC[3].sync_reg_reg[1]_6 ;
  output \SYNC[3].sync_reg_reg[1]_7 ;
  output \SYNC[3].sync_reg_reg[1]_8 ;
  output \SYNC[3].sync_reg_reg[1]_9 ;
  output \SYNC[3].sync_reg_reg[1]_10 ;
  output \SYNC[3].sync_reg_reg[1]_11 ;
  output [31:0]\lowCL2_reg[45]_0 ;
  output \SYNC[3].sync_reg_reg[1]_12 ;
  output \SYNC[3].sync_reg_reg[1]_13 ;
  output \SYNC[3].sync_reg_reg[1]_14 ;
  output \SYNC[3].sync_reg_reg[1]_15 ;
  output \SYNC[3].sync_reg_reg[1]_16 ;
  output [31:0]\lowCL3_reg[45]_0 ;
  output \SYNC[3].sync_reg_reg[1]_17 ;
  output \SYNC[3].sync_reg_reg[1]_18 ;
  output \SYNC[3].sync_reg_reg[1]_19 ;
  output \SYNC[3].sync_reg_reg[1]_20 ;
  output \SYNC[3].sync_reg_reg[1]_21 ;
  output \SYNC[3].sync_reg_reg[1]_22 ;
  output \SYNC[3].sync_reg_reg[1]_23 ;
  output [31:0]\uppCL0_reg[45]_0 ;
  output \SYNC[3].sync_reg_reg[1]_24 ;
  output \SYNC[3].sync_reg_reg[1]_25 ;
  output \SYNC[3].sync_reg_reg[1]_26 ;
  output \SYNC[3].sync_reg_reg[1]_27 ;
  output \SYNC[3].sync_reg_reg[1]_28 ;
  output [31:0]\uppCL1_reg[45]_0 ;
  output \SYNC[3].sync_reg_reg[1]_29 ;
  output \SYNC[3].sync_reg_reg[1]_30 ;
  output \SYNC[3].sync_reg_reg[1]_31 ;
  output \SYNC[3].sync_reg_reg[1]_32 ;
  output \SYNC[3].sync_reg_reg[1]_33 ;
  output \SYNC[3].sync_reg_reg[1]_34 ;
  output [31:0]\uppCL2_reg[45]_0 ;
  output \SYNC[3].sync_reg_reg[1]_35 ;
  output \SYNC[3].sync_reg_reg[1]_36 ;
  output \SYNC[3].sync_reg_reg[1]_37 ;
  output \SYNC[3].sync_reg_reg[1]_38 ;
  output \SYNC[3].sync_reg_reg[1]_39 ;
  output \SYNC[3].sync_reg_reg[1]_40 ;
  output [31:0]\uppCL3_reg[45]_0 ;
  output \SYNC[3].sync_reg_reg[1]_41 ;
  output \SYNC[3].sync_reg_reg[1]_42 ;
  output \SYNC[3].sync_reg_reg[1]_43 ;
  output \SYNC[3].sync_reg_reg[1]_44 ;
  output \SYNC[3].sync_reg_reg[1]_45 ;
  output \SYNC[5].sync_reg_reg[1]_1 ;
  output \SYNC[5].sync_reg_reg[1]_2 ;
  output \SYNC[5].sync_reg_reg[1]_3 ;
  output \SYNC[5].sync_reg_reg[1]_4 ;
  output \cal_ADR_A_reg[22]_0 ;
  output \SYNC[5].sync_reg_reg[1]_5 ;
  output \SYNC[5].sync_reg_reg[1]_6 ;
  output \SYNC[5].sync_reg_reg[1]_7 ;
  output \SYNC[5].sync_reg_reg[1]_8 ;
  output \SYNC[5].sync_reg_reg[1]_9 ;
  output \SYNC[5].sync_reg_reg[1]_10 ;
  output \SYNC[5].sync_reg_reg[1]_11 ;
  output \SYNC[5].sync_reg_reg[1]_12 ;
  output \SYNC[5].sync_reg_reg[1]_13 ;
  output \genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9]_0 ;
  output \genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8]_0 ;
  output \SYNC[4].sync_reg_reg[1] ;
  output \SYNC[5].sync_reg_reg[1]_14 ;
  output \cal_ADR_A_reg[4]_1 ;
  output \cal_CS_A_reg[4]_0 ;
  output \SYNC[4].sync_reg_reg[1]_0 ;
  output \rd_vref_value_reg[46]_0 ;
  output [6:0]\mcal_DMIn_bit_r1_reg[7]_0 ;
  output \cal_ADR_A_reg[3]_0 ;
  output \SYNC[5].sync_reg_reg[1]_15 ;
  output \cal_ADR_A_reg[2]_0 ;
  output \SYNC[18].sync_reg_reg[1] ;
  output \SYNC[5].sync_reg_reg[1]_16 ;
  output gt_data_ready_flag_reg_0;
  output [0:0]cplx_status;
  output \cal_ADR_A_reg[0]_1 ;
  output rst_r1_reg_0;
  output [0:0]S;
  output [1:0]\delay_cntr_reg[2]_0 ;
  output lrdimm_cal_mode_reg_0;
  output lrdimm_cal_mode_reg_1;
  output \SYNC[5].sync_reg_reg[1]_17 ;
  output \rd_vref_value_reg[42]_0 ;
  output [55:0]mcal_rd_vref_value;
  output \rd_vref_value_reg[43]_0 ;
  output \rd_vref_value_reg[44]_0 ;
  output \rd_vref_value_reg[45]_0 ;
  output \rd_vref_value_reg[48]_0 ;
  output [1:0]in0;
  output [1:0]\rsMask_reg[7][18] ;
  output [1:0]rst_r1_reg_1;
  output \wosp_reg[1] ;
  output [1:0]\wosp_reg[2]_rep ;
  output \wosp_reg[2]_rep_0 ;
  output \wosp_reg[1]_0 ;
  output \wosp_reg[2]_rep__2 ;
  output [1:0]\wosp_reg[2]_rep__1 ;
  output \wosp_reg[2]_rep__1_0 ;
  output \wosp_reg[2]_rep__1_1 ;
  output [1:0]\wosp_reg[2]_rep__1_2 ;
  output \wosp_reg[2]_rep__1_3 ;
  output \wosp_reg[2]_rep__1_4 ;
  output [1:0]\wosp_reg[2]_rep__1_5 ;
  output \wosp_reg[2]_rep__1_6 ;
  output \wosp_reg[2]_rep__1_7 ;
  output [1:0]\wosp_reg[2]_rep__1_8 ;
  output \wosp_reg[2]_rep__1_9 ;
  output \wosp_reg[2]_rep__1_10 ;
  output [1:0]\wosp_reg[2]_rep__2_0 ;
  output \wosp_reg[2]_rep__1_11 ;
  output \wosp_reg[2]_rep__2_1 ;
  output [1:0]\wosp_reg[2]_rep__2_2 ;
  output \wosp_reg[2]_rep__2_3 ;
  output \wosp_reg[2]_rep__2_4 ;
  output [1:0]\wosp_reg[2]_rep__2_5 ;
  output \wosp_reg[2]_rep__2_6 ;
  output \wosp_reg[2]_rep__2_7 ;
  output [1:0]\wosp_reg[2]_rep__2_8 ;
  output \wosp_reg[2]_rep__2_9 ;
  output \wosp_reg[2]_rep__2_10 ;
  output \wosp_reg[1]_1 ;
  output \wosp_reg[1]_2 ;
  output \wosp_reg[1]_3 ;
  output \wosp_reg[1]_4 ;
  output \wosp_reg[1]_5 ;
  output \wosp_reg[1]_6 ;
  output \wosp_reg[1]_7 ;
  output \wosp_reg[1]_8 ;
  output \wosp_reg[1]_9 ;
  output \wosp_reg[1]_10 ;
  output \wosp_reg[1]_11 ;
  output \wosp_reg[1]_12 ;
  output \wosp_reg[1]_13 ;
  output \wosp_reg[1]_14 ;
  output \wosp_reg[1]_15 ;
  output \wosp_reg[1]_16 ;
  output \wosp_reg[1]_17 ;
  output [1:0]\wosp_reg[2]_rep_1 ;
  output \wosp_reg[2]_rep_2 ;
  output \wosp_reg[1]_18 ;
  output \wosp_reg[2]_rep__3 ;
  output [1:0]\wosp_reg[2]_rep__2_11 ;
  output \wosp_reg[2]_rep__2_12 ;
  output \wosp_reg[2]_rep__2_13 ;
  output [1:0]\wosp_reg[2]_rep__2_14 ;
  output \wosp_reg[2]_rep__2_15 ;
  output \wosp_reg[2]_rep__2_16 ;
  output [1:0]\wosp_reg[2]_rep__2_17 ;
  output \wosp_reg[2]_rep__2_18 ;
  output \wosp_reg[2]_rep__2_19 ;
  output [1:0]\wosp_reg[2]_rep__2_20 ;
  output \wosp_reg[2]_rep__2_21 ;
  output \wosp_reg[2]_rep__2_22 ;
  output [1:0]\wosp_reg[2]_rep__2_23 ;
  output \wosp_reg[2]_rep__2_24 ;
  output \wosp_reg[2]_rep__2_25 ;
  output [1:0]\wosp_reg[2]_rep__2_26 ;
  output \wosp_reg[2]_rep__2_27 ;
  output \wosp_reg[2]_rep__2_28 ;
  output [1:0]\wosp_reg[2]_rep__2_29 ;
  output \wosp_reg[2]_rep__2_30 ;
  output \wosp_reg[2]_rep__2_31 ;
  output [1:0]\wosp_reg[2]_rep__2_32 ;
  output \wosp_reg[2]_rep__2_33 ;
  output \wosp_reg[2]_rep__2_34 ;
  output \wosp_reg[1]_19 ;
  output \wosp_reg[1]_20 ;
  output \wosp_reg[1]_21 ;
  output \wosp_reg[1]_22 ;
  output \wosp_reg[1]_23 ;
  output \wosp_reg[1]_24 ;
  output \wosp_reg[1]_25 ;
  output \wosp_reg[1]_26 ;
  output \wosp_reg[1]_27 ;
  output \wosp_reg[1]_28 ;
  output \wosp_reg[1]_29 ;
  output \wosp_reg[1]_30 ;
  output \wosp_reg[1]_31 ;
  output \wosp_reg[1]_32 ;
  output \wosp_reg[1]_33 ;
  output \wosp_reg[1]_34 ;
  output \wosp_reg[1]_35 ;
  output [1:0]\wosp_reg[2]_rep_3 ;
  output \wosp_reg[2]_rep_4 ;
  output \wosp_reg[1]_36 ;
  output \wosp_reg[2]_rep__3_0 ;
  output [1:0]\wosp_reg[2]_rep__3_1 ;
  output \wosp_reg[2]_rep__3_2 ;
  output \wosp_reg[2]_rep__3_3 ;
  output [1:0]\wosp_reg[2]_rep__3_4 ;
  output \wosp_reg[2]_rep__3_5 ;
  output \wosp_reg[2]_rep__3_6 ;
  output [1:0]\wosp_reg[2]_rep__3_7 ;
  output \wosp_reg[2]_rep__3_8 ;
  output \wosp_reg[2]_rep__3_9 ;
  output [1:0]\wosp_reg[2]_rep__3_10 ;
  output \wosp_reg[2]_rep__3_11 ;
  output \wosp_reg[2]_rep__3_12 ;
  output [1:0]\wosp_reg[2]_rep__3_13 ;
  output \wosp_reg[2]_rep__3_14 ;
  output \wosp_reg[2]_rep__3_15 ;
  output [1:0]\wosp_reg[2]_rep__3_16 ;
  output \wosp_reg[2]_rep__3_17 ;
  output \wosp_reg[2]_rep__3_18 ;
  output [1:0]\wosp_reg[2]_rep__3_19 ;
  output \wosp_reg[2]_rep__3_20 ;
  output \wosp_reg[2]_rep__3_21 ;
  output [1:0]\wosp_reg[2]_rep__3_22 ;
  output \wosp_reg[2]_rep__3_23 ;
  output \wosp_reg[2]_rep__3_24 ;
  output \wosp_reg[1]_37 ;
  output \wosp_reg[1]_38 ;
  output \wosp_reg[1]_39 ;
  output \wosp_reg[1]_40 ;
  output \wosp_reg[1]_41 ;
  output \wosp_reg[1]_42 ;
  output \wosp_reg[1]_43 ;
  output \wosp_reg[1]_44 ;
  output \wosp_reg[1]_45 ;
  output \wosp_reg[1]_46 ;
  output \wosp_reg[1]_47 ;
  output \wosp_reg[1]_48 ;
  output \wosp_reg[1]_49 ;
  output \wosp_reg[1]_50 ;
  output \wosp_reg[1]_51 ;
  output \wosp_reg[1]_52 ;
  output \wosp_reg[1]_53 ;
  output [1:0]\wosp_reg[2]_rep__0 ;
  output \wosp_reg[2]_rep__0_0 ;
  output \wosp_reg[1]_54 ;
  output \wosp_reg[2]_rep__4 ;
  output [1:0]\wosp_reg[2]_rep__3_25 ;
  output \wosp_reg[2]_rep__3_26 ;
  output \wosp_reg[2]_rep__3_27 ;
  output [1:0]\wosp_reg[2]_rep__3_28 ;
  output \wosp_reg[2]_rep__3_29 ;
  output \wosp_reg[2]_rep__3_30 ;
  output [1:0]\wosp_reg[2]_rep__3_31 ;
  output \wosp_reg[2]_rep__3_32 ;
  output \wosp_reg[2]_rep__3_33 ;
  output [1:0]\wosp_reg[2]_rep__4_0 ;
  output \wosp_reg[2]_rep__4_1 ;
  output \wosp_reg[2]_rep__4_2 ;
  output [1:0]\wosp_reg[2]_rep__4_3 ;
  output \wosp_reg[2]_rep__4_4 ;
  output \wosp_reg[2]_rep__4_5 ;
  output [1:0]\wosp_reg[2]_rep__4_6 ;
  output \wosp_reg[2]_rep__4_7 ;
  output \wosp_reg[2]_rep__4_8 ;
  output [1:0]\wosp_reg[2]_rep__4_9 ;
  output \wosp_reg[2]_rep__4_10 ;
  output \wosp_reg[2]_rep__4_11 ;
  output [1:0]\wosp_reg[2]_rep__4_12 ;
  output \wosp_reg[2]_rep__4_13 ;
  output \wosp_reg[2]_rep__4_14 ;
  output \wosp_reg[1]_55 ;
  output \wosp_reg[1]_56 ;
  output \wosp_reg[1]_57 ;
  output \wosp_reg[1]_58 ;
  output \wosp_reg[1]_59 ;
  output \wosp_reg[1]_60 ;
  output \wosp_reg[1]_61 ;
  output \wosp_reg[1]_62 ;
  output \wosp_reg[1]_63 ;
  output \wosp_reg[1]_64 ;
  output \wosp_reg[1]_65 ;
  output \wosp_reg[1]_66 ;
  output \wosp_reg[1]_67 ;
  output \wosp_reg[1]_68 ;
  output \wosp_reg[1]_69 ;
  output \wosp_reg[1]_70 ;
  output \wosp_reg[1]_71 ;
  output [1:0]\wosp_reg[2]_rep__0_1 ;
  output \wosp_reg[2]_rep__0_2 ;
  output \wosp_reg[1]_72 ;
  output \wosp_reg[2]_rep__5 ;
  output [1:0]\wosp_reg[2]_rep__4_15 ;
  output \wosp_reg[2]_rep__4_16 ;
  output \wosp_reg[2]_rep__4_17 ;
  output [1:0]\wosp_reg[2]_rep__4_18 ;
  output \wosp_reg[2]_rep__4_19 ;
  output \wosp_reg[2]_rep__4_20 ;
  output [1:0]\wosp_reg[2]_rep__4_21 ;
  output \wosp_reg[2]_rep__4_22 ;
  output \wosp_reg[2]_rep__4_23 ;
  output [1:0]\wosp_reg[2]_rep__4_24 ;
  output \wosp_reg[2]_rep__4_25 ;
  output \wosp_reg[2]_rep__4_26 ;
  output [1:0]\wosp_reg[2]_rep__4_27 ;
  output \wosp_reg[2]_rep__4_28 ;
  output \wosp_reg[2]_rep__4_29 ;
  output [1:0]\wosp_reg[2]_rep__4_30 ;
  output \wosp_reg[2]_rep__4_31 ;
  output \wosp_reg[2]_rep__4_32 ;
  output [1:0]\wosp_reg[2]_rep__5_0 ;
  output \wosp_reg[2]_rep__4_33 ;
  output \wosp_reg[2]_rep__5_1 ;
  output [1:0]\wosp_reg[2]_rep__5_2 ;
  output \wosp_reg[2]_rep__5_3 ;
  output \wosp_reg[2]_rep__5_4 ;
  output \wosp_reg[1]_73 ;
  output \wosp_reg[1]_74 ;
  output \wosp_reg[1]_75 ;
  output \wosp_reg[1]_76 ;
  output \wosp_reg[1]_77 ;
  output \wosp_reg[1]_78 ;
  output \wosp_reg[1]_79 ;
  output \wosp_reg[1]_80 ;
  output \wosp_reg[1]_81 ;
  output \wosp_reg[1]_82 ;
  output \wosp_reg[1]_83 ;
  output \wosp_reg[1]_84 ;
  output \wosp_reg[1]_85 ;
  output \wosp_reg[1]_86 ;
  output \wosp_reg[1]_87 ;
  output \wosp_reg[1]_88 ;
  output \wosp_reg[1]_89 ;
  output [1:0]\wosp_reg[2]_rep__0_3 ;
  output \wosp_reg[2]_rep__0_4 ;
  output \wosp_reg[1]_90 ;
  output \wosp_reg[2]_rep__5_5 ;
  output [1:0]\wosp_reg[2]_rep__5_6 ;
  output \wosp_reg[2]_rep__5_7 ;
  output \wosp_reg[2]_rep__5_8 ;
  output [1:0]\wosp_reg[2]_rep__5_9 ;
  output \wosp_reg[2]_rep__5_10 ;
  output \wosp_reg[2]_rep__5_11 ;
  output [1:0]\wosp_reg[2]_rep__5_12 ;
  output \wosp_reg[2]_rep__5_13 ;
  output \wosp_reg[2]_rep__5_14 ;
  output [1:0]\wosp_reg[2]_rep__5_15 ;
  output \wosp_reg[2]_rep__5_16 ;
  output \wosp_reg[2]_rep__5_17 ;
  output [1:0]\wosp_reg[2]_rep__5_18 ;
  output \wosp_reg[2]_rep__5_19 ;
  output \wosp_reg[2]_rep__5_20 ;
  output [1:0]\wosp_reg[2]_rep__5_21 ;
  output \wosp_reg[2]_rep__5_22 ;
  output \wosp_reg[2]_rep__5_23 ;
  output [1:0]\wosp_reg[2]_rep__5_24 ;
  output \wosp_reg[2]_rep__5_25 ;
  output \wosp_reg[2]_rep__5_26 ;
  output [1:0]\wosp_reg[2]_rep__5_27 ;
  output \wosp_reg[2]_rep__5_28 ;
  output \wosp_reg[2]_rep__5_29 ;
  output \wosp_reg[1]_91 ;
  output \wosp_reg[1]_92 ;
  output \wosp_reg[1]_93 ;
  output \wosp_reg[1]_94 ;
  output \wosp_reg[1]_95 ;
  output \wosp_reg[1]_96 ;
  output \wosp_reg[1]_97 ;
  output \wosp_reg[1]_98 ;
  output \wosp_reg[1]_99 ;
  output \wosp_reg[1]_100 ;
  output \wosp_reg[1]_101 ;
  output \wosp_reg[1]_102 ;
  output \wosp_reg[1]_103 ;
  output \wosp_reg[1]_104 ;
  output \wosp_reg[1]_105 ;
  output \wosp_reg[1]_106 ;
  output \wosp_reg[1]_107 ;
  output [1:0]\wosp_reg[2]_rep__1_12 ;
  output \wosp_reg[2]_rep__1_13 ;
  output \wosp_reg[1]_108 ;
  output \wosp_reg[2]_rep__6 ;
  output [1:0]\wosp_reg[2]_rep__5_30 ;
  output \wosp_reg[2]_rep__5_31 ;
  output \wosp_reg[2]_rep__5_32 ;
  output [1:0]\wosp_reg[2]_rep__6_0 ;
  output \wosp_reg[2]_rep__5_33 ;
  output \wosp_reg[2]_rep__6_1 ;
  output [1:0]\wosp_reg[2]_rep__6_2 ;
  output \wosp_reg[2]_rep__6_3 ;
  output \wosp_reg[2]_rep__6_4 ;
  output [1:0]\wosp_reg[2]_rep__6_5 ;
  output \wosp_reg[2]_rep__6_6 ;
  output \wosp_reg[2]_rep__6_7 ;
  output [1:0]\wosp_reg[2]_rep__6_8 ;
  output \wosp_reg[2]_rep__6_9 ;
  output \wosp_reg[2]_rep__6_10 ;
  output [1:0]\wosp_reg[2]_rep__6_11 ;
  output \wosp_reg[2]_rep__6_12 ;
  output \wosp_reg[2]_rep__6_13 ;
  output [1:0]\wosp_reg[2]_rep__6_14 ;
  output \wosp_reg[2]_rep__6_15 ;
  output \wosp_reg[2]_rep__6_16 ;
  output [1:0]\wosp_reg[2]_rep__6_17 ;
  output \wosp_reg[2]_rep__6_18 ;
  output \wosp_reg[2]_rep__6_19 ;
  output \wosp_reg[1]_109 ;
  output \wosp_reg[1]_110 ;
  output \wosp_reg[1]_111 ;
  output \wosp_reg[1]_112 ;
  output \wosp_reg[1]_113 ;
  output \wosp_reg[1]_114 ;
  output \wosp_reg[1]_115 ;
  output \wosp_reg[1]_116 ;
  output \wosp_reg[1]_117 ;
  output \wosp_reg[1]_118 ;
  output \wosp_reg[1]_119 ;
  output \wosp_reg[1]_120 ;
  output \wosp_reg[1]_121 ;
  output \wosp_reg[1]_122 ;
  output \wosp_reg[1]_123 ;
  output \wosp_reg[1]_124 ;
  output \wosp_reg[1]_125 ;
  output [1:0]\wosp_reg[2] ;
  output \wosp_reg[2]_0 ;
  output \wosp_reg[1]_126 ;
  output \wosp_reg[2]_rep__6_20 ;
  output [1:0]\wosp_reg[2]_rep__7 ;
  output \wosp_reg[2]_rep__7_0 ;
  output \wosp_reg[2]_rep__6_21 ;
  output [1:0]\wosp_reg[2]_rep__6_22 ;
  output \wosp_reg[2]_rep__6_23 ;
  output \wosp_reg[2]_rep__6_24 ;
  output [1:0]\wosp_reg[2]_rep__6_25 ;
  output \wosp_reg[2]_rep__6_26 ;
  output \wosp_reg[2]_rep__6_27 ;
  output [1:0]\wosp_reg[2]_rep__6_28 ;
  output \wosp_reg[2]_rep__6_29 ;
  output \wosp_reg[2]_rep__6_30 ;
  output [1:0]\wosp_reg[2]_rep__6_31 ;
  output \wosp_reg[2]_rep__6_32 ;
  output \wosp_reg[2]_rep__6_33 ;
  output [1:0]\wosp_reg[2]_rep__6_34 ;
  output \wosp_reg[2]_rep__6_35 ;
  output \wosp_reg[2]_rep__6_36 ;
  output [1:0]\wosp_reg[2]_rep__6_37 ;
  output \wosp_reg[2]_rep__6_38 ;
  output \wosp_reg[2]_rep__6_39 ;
  output [1:0]\wosp_reg[2]_rep__6_40 ;
  output \wosp_reg[2]_rep__6_41 ;
  output \wosp_reg[2]_rep__6_42 ;
  output \wosp_reg[1]_127 ;
  output \wosp_reg[1]_128 ;
  output \wosp_reg[1]_129 ;
  output \wosp_reg[1]_130 ;
  output \wosp_reg[1]_131 ;
  output \wosp_reg[1]_132 ;
  output \wosp_reg[1]_133 ;
  output \wosp_reg[1]_134 ;
  output \wosp_reg[1]_135 ;
  output \wosp_reg[1]_136 ;
  output \wosp_reg[1]_137 ;
  output \wosp_reg[1]_138 ;
  output \wosp_reg[1]_139 ;
  output \wosp_reg[1]_140 ;
  output \wosp_reg[1]_141 ;
  output \wosp_reg[1]_142 ;
  output [1:0]rst_r1_reg_2;
  output [1:0]rst_r1_reg_3;
  output [1:0]rst_r1_reg_4;
  output [1:0]rst_r1_reg_5;
  output [1:0]rst_r1_reg_6;
  output [1:0]rst_r1_reg_7;
  output [1:0]rst_r1_reg_8;
  output [1:0]rst_r1_reg_9;
  output [1:0]rst_r1_reg_10;
  output [1:0]rst_r1_reg_11;
  output [1:0]rst_r1_reg_12;
  output [1:0]rst_r1_reg_13;
  output [1:0]rst_r1_reg_14;
  output [9:0]\mcal_DQIn_byte_r1_reg[48]_0 ;
  output [31:0]\io_read_data_reg[31]_0 ;
  output [8:0]bisc_byte;
  output [8:0]\xsdb_wr_data_reg[8]_0 ;
  output [5:0]\max_rd_lat_reg[5]_0 ;
  output [7:0]\cal_RST_CKE_ODT_PAR_reg[7]_0 ;
  output [53:0]\cplx_error_accum_reg[63] ;
  input \odt_shift_reg[0][17] ;
  input [0:0]SR;
  input io_addr_strobe_r1_reg_0;
  input calDone_reg_14;
  input [31:0]io_write_data;
  input lrdimm_cmp_clr;
  input lrdimm_cal_mode_reg_2;
  input p_52_in;
  input clear_gt_data_ready_flag;
  input gt_data_ready_flag_nxt;
  input ub_ready_reg_1;
  input [0:0]E;
  input wren_reg_0;
  input \clb2phy_wrcs0_low_reg[31]_0 ;
  input [7:0]O;
  input [7:0]\cal_timer_reg[15]_0 ;
  input [7:0]\cal_timer_reg[23]_0 ;
  input [7:0]\cal_timer_reg[31]_0 ;
  input stop_gate_tracking_ack_reg_1;
  input cnt_clr_reg_1;
  input a_b_cmd_sel_start_reg_1;
  input lrdimm_cmp_en_reg_1;
  input cal_seq_cnt_gt_0_reg_0;
  input [0:0]xsdb_wr_en_reg_0;
  input \cal_oe_dis_low_reg[7]_0 ;
  input \cal_oe_dis_upp_reg[7]_0 ;
  input [3:0]Q;
  input pllGate;
  input \init_cal_RESET_n_reg[7] ;
  input [0:0]init_cal_RESET_n;
  input [14:0]\mcal_ADR_dly_reg[0][134] ;
  input \mcal_ADR_dly_reg[0][87] ;
  input [1:0]\mcal_BA_dly_reg[0][15] ;
  input [1:0]\mcal_BA_dly_reg[0][8] ;
  input \mcal_ODT_dly_reg[0][4] ;
  input [6:0]mc_BA;
  input [0:0]init_cal_CKE;
  input mc_CKE7;
  input [1:0]mc_CKE;
  input [0:0]mc_ODT;
  input mc_ODT7;
  input winAct;
  input [0:0]mc_CS_n;
  input [0:0]init_cal_CS_n;
  input mc_CS_n7;
  input mcRdCAS;
  input mcCasSlot2;
  input [4:0]\mcal_ADR_dly_reg[0][135] ;
  input [35:0]mc_ADR;
  input [4:0]\mcal_ADR_dly_reg[0][128] ;
  input [2:0]mc_BG;
  input [0:0]p_1_in;
  input \mcal_PAR_dly_reg[0][5] ;
  input \mcal_PAR_dly_reg[0][3] ;
  input \mcal_PAR_dly_reg[0][1] ;
  input \mcal_PAR_dly_reg[0][0] ;
  input \mcal_PAR_dly_reg[0][7] ;
  input [575:0]\dReg_reg[15] ;
  input mcWrCAS;
  input \wrQ_reg[1][0] ;
  input [1:0]\rsMask_reg[1]_71 ;
  input [1:0]\rsMask_reg[3]_73 ;
  input [1:0]\rsMask_reg[1]_79 ;
  input [1:0]\rsMask_reg[3]_81 ;
  input [0:0]\cplx_config_reg[16]_0 ;
  input [15:0]io_address;
  input \cplx_config_reg[16]_1 ;
  input cnt_clr_access;
  input a_b_cmd_sel_start0;
  input \cal_timer_reg[0]_0 ;
  input \addr_dec_to_mb_data[7]_i_7_0 ;
  input io_ready_reg_0;
  input \addr_dec_to_mb_data_reg[15]_0 ;
  input \addr_dec_to_mb_data_reg[19]_0 ;
  input \addr_dec_to_mb_data_reg[12]_0 ;
  input \addr_dec_to_mb_data[0]_i_3 ;
  input io_ready_reg_1;
  input io_ready_reg_2;
  input \addr_dec_to_mb_data_reg[29]_0 ;
  input \addr_dec_to_mb_data_reg[29]_1 ;
  input \addr_dec_to_mb_data_reg[14]_0 ;
  input \addr_dec_to_mb_data_reg[29]_2 ;
  input \addr_dec_to_mb_data_reg[29]_3 ;
  input \addr_dec_to_mb_data_reg[29]_4 ;
  input \addr_dec_to_mb_data[4]_i_11 ;
  input [0:0]douta;
  input \addr_dec_to_mb_data[31]_i_3 ;
  input wrDataEn_pi;
  input rdDataEn_pi;
  input \addr_dec_to_mb_data[6]_i_7 ;
  input \addr_dec_to_mb_data[6]_i_7_0 ;
  input [1:0]\rsMask_reg[7]_77 ;
  input [1:0]\rsMask_reg[5]_75 ;
  input [1:0]\rsMask_reg[7]_85 ;
  input [1:0]\rsMask_reg[5]_83 ;
  input \rdEn_reg[29] ;
  input \rdEn_reg[29]_0 ;
  input \rdEn_reg[28] ;
  input [2:1]wosp;
  input \dReg_reg[9] ;
  input wrDataVal;
  input \dReg_reg[9]_0 ;
  input \dReg_reg[11] ;
  input \dReg_reg[10] ;
  input \dReg_reg[9]_1 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[8] ;
  input \dReg_reg[8]_0 ;
  input \rdEn_reg[29]_1 ;
  input \rdEn_reg[28]_0 ;
  input \rdEn_reg[29]_2 ;
  input \rdEn_reg[28]_1 ;
  input \rdEn_reg[29]_3 ;
  input \rdEn_reg[28]_2 ;
  input \rdEn_reg[29]_4 ;
  input \rdEn_reg[28]_3 ;
  input \rdEn_reg[29]_5 ;
  input \rdEn_reg[28]_4 ;
  input \rdEn_reg[29]_6 ;
  input \rdEn_reg[28]_5 ;
  input \rdEn_reg[29]_7 ;
  input \rdEn_reg[28]_6 ;
  input \rdEn_reg[29]_8 ;
  input \rdEn_reg[28]_7 ;
  input \rdEn_reg[29]_9 ;
  input \rdEn_reg[28]_8 ;
  input \rdEn_reg[29]_10 ;
  input \rdEn_reg[28]_9 ;
  input \rdEn_reg[29]_11 ;
  input \rdEn_reg[28]_10 ;
  input \rdEn_reg[29]_12 ;
  input \rdEn_reg[28]_11 ;
  input \rdEn_reg[29]_13 ;
  input \rdEn_reg[28]_12 ;
  input [0:0]\cal_seq_reg[2]_0 ;
  input [0:0]\dqin_valid_shift_reg[0]_0 ;
  input [511:0]\mcal_DQIn_r_reg[511]_0 ;
  input [0:0]\cal_cmp_en_reg[7]_0 ;
  input \cal_DQPat_A_reg[63]_0 ;
  input \cal_DQPat_A_reg[31]_0 ;
  input \cal_DQPat_B_reg[63]_0 ;
  input \cal_DQPat_B_reg[31]_0 ;
  input [0:0]\cmp_byte_reg[2]_0 ;
  input [0:0]\cal_cs_pos_reg[1]_0 ;
  input [0:0]\cplx_config_reg[0]_0 ;
  input \cplx_config_reg[1]_0 ;
  input [0:0]\cal_seq_a_b_dly_reg[7]_0 ;
  input [0:0]\cal_seq_a_a_dly_reg[7]_0 ;
  input [0:0]\cal_seq_b_a_dly_reg[7]_0 ;
  input [0:0]\cal_RST_CKE_ODT_PAR_reg[31]_0 ;
  input [0:0]\traffic_instr_nxt_instr_r1_reg[5]_0 ;
  input [7:0]\uppCL3_reg[42]_0 ;
  input [9:0]\uppCL0_reg[47]_0 ;
  input [9:0]\uppCL1_reg[47]_0 ;
  input [9:0]\uppCL2_reg[47]_0 ;
  input [9:0]\uppCL3_reg[47]_0 ;
  input [0:0]\cal_CS_A_reg[7]_1 ;
  input [0:0]\cal_CS_B_reg[7]_0 ;
  input [63:0]\mcal_DMIn_n_r_reg[63]_0 ;
  input [0:0]\cal_ADR_A_reg[31]_0 ;
  input [0:0]\cal_ADR_B_reg[31]_1 ;
  input [20:0]\addr_dec_to_mb_data_reg[31]_0 ;
  input \addr_dec_to_mb_data_reg[30]_0 ;
  input \addr_dec_to_mb_data_reg[30]_1 ;
  input \addr_dec_to_mb_data_reg[29]_5 ;
  input \addr_dec_to_mb_data_reg[28]_0 ;
  input \addr_dec_to_mb_data_reg[27]_0 ;
  input \addr_dec_to_mb_data_reg[26]_0 ;
  input \addr_dec_to_mb_data_reg[25]_0 ;
  input \addr_dec_to_mb_data_reg[24]_0 ;
  input \addr_dec_to_mb_data_reg[23]_0 ;
  input \addr_dec_to_mb_data_reg[22]_0 ;
  input \addr_dec_to_mb_data_reg[21]_0 ;
  input \addr_dec_to_mb_data_reg[20]_0 ;
  input [0:0]\bisc_bit_reg[0]_0 ;
  input \cal_DQOut_A_reg[63]_0 ;
  input \cal_DQOut_A_reg[31]_0 ;
  input \cal_DQOut_pre_reg[63]_0 ;
  input \cal_DQOut_pre_reg[31]_0 ;
  input \cal_DQOut_post_reg[63]_0 ;
  input \cal_DQOut_post_reg[31]_0 ;
  input [0:0]\cal_DMOut_n_A_reg[31]_0 ;
  input [0:0]\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ;
  input [0:0]\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ;
  input [0:0]\cal_CAS_A_reg[0]_0 ;
  input [0:0]\cal_RAS_B_reg[0]_0 ;
  input [0:0]\cal_ACT_n_A_reg[7]_0 ;
  input [0:0]\max_rd_lat_reg[5]_1 ;
  input [7:0]rd_vref_value0_out;
  input [0:0]init_cal_BG;

  wire [0:0]D;
  wire [63:0]DMOut;
  wire [511:0]DQOut;
  wire [0:0]E;
  wire [7:0]O;
  wire [3:0]Q;
  wire [0:0]S;
  wire [0:0]SR;
  wire \SYNC[0].sync_reg_reg[1] ;
  wire \SYNC[0].sync_reg_reg[1]_0 ;
  wire \SYNC[18].sync_reg_reg[1] ;
  wire \SYNC[20].sync_reg_reg[1] ;
  wire \SYNC[3].sync_reg_reg[1] ;
  wire \SYNC[3].sync_reg_reg[1]_0 ;
  wire \SYNC[3].sync_reg_reg[1]_1 ;
  wire \SYNC[3].sync_reg_reg[1]_10 ;
  wire \SYNC[3].sync_reg_reg[1]_11 ;
  wire \SYNC[3].sync_reg_reg[1]_12 ;
  wire \SYNC[3].sync_reg_reg[1]_13 ;
  wire \SYNC[3].sync_reg_reg[1]_14 ;
  wire \SYNC[3].sync_reg_reg[1]_15 ;
  wire \SYNC[3].sync_reg_reg[1]_16 ;
  wire \SYNC[3].sync_reg_reg[1]_17 ;
  wire \SYNC[3].sync_reg_reg[1]_18 ;
  wire \SYNC[3].sync_reg_reg[1]_19 ;
  wire \SYNC[3].sync_reg_reg[1]_2 ;
  wire \SYNC[3].sync_reg_reg[1]_20 ;
  wire \SYNC[3].sync_reg_reg[1]_21 ;
  wire \SYNC[3].sync_reg_reg[1]_22 ;
  wire \SYNC[3].sync_reg_reg[1]_23 ;
  wire \SYNC[3].sync_reg_reg[1]_24 ;
  wire \SYNC[3].sync_reg_reg[1]_25 ;
  wire \SYNC[3].sync_reg_reg[1]_26 ;
  wire \SYNC[3].sync_reg_reg[1]_27 ;
  wire \SYNC[3].sync_reg_reg[1]_28 ;
  wire \SYNC[3].sync_reg_reg[1]_29 ;
  wire \SYNC[3].sync_reg_reg[1]_3 ;
  wire \SYNC[3].sync_reg_reg[1]_30 ;
  wire \SYNC[3].sync_reg_reg[1]_31 ;
  wire \SYNC[3].sync_reg_reg[1]_32 ;
  wire \SYNC[3].sync_reg_reg[1]_33 ;
  wire \SYNC[3].sync_reg_reg[1]_34 ;
  wire \SYNC[3].sync_reg_reg[1]_35 ;
  wire \SYNC[3].sync_reg_reg[1]_36 ;
  wire \SYNC[3].sync_reg_reg[1]_37 ;
  wire \SYNC[3].sync_reg_reg[1]_38 ;
  wire \SYNC[3].sync_reg_reg[1]_39 ;
  wire \SYNC[3].sync_reg_reg[1]_4 ;
  wire \SYNC[3].sync_reg_reg[1]_40 ;
  wire \SYNC[3].sync_reg_reg[1]_41 ;
  wire \SYNC[3].sync_reg_reg[1]_42 ;
  wire \SYNC[3].sync_reg_reg[1]_43 ;
  wire \SYNC[3].sync_reg_reg[1]_44 ;
  wire \SYNC[3].sync_reg_reg[1]_45 ;
  wire \SYNC[3].sync_reg_reg[1]_5 ;
  wire \SYNC[3].sync_reg_reg[1]_6 ;
  wire \SYNC[3].sync_reg_reg[1]_7 ;
  wire \SYNC[3].sync_reg_reg[1]_8 ;
  wire \SYNC[3].sync_reg_reg[1]_9 ;
  wire \SYNC[4].sync_reg_reg[1] ;
  wire \SYNC[4].sync_reg_reg[1]_0 ;
  wire \SYNC[5].sync_reg_reg[1] ;
  wire \SYNC[5].sync_reg_reg[1]_0 ;
  wire \SYNC[5].sync_reg_reg[1]_1 ;
  wire \SYNC[5].sync_reg_reg[1]_10 ;
  wire \SYNC[5].sync_reg_reg[1]_11 ;
  wire \SYNC[5].sync_reg_reg[1]_12 ;
  wire \SYNC[5].sync_reg_reg[1]_13 ;
  wire \SYNC[5].sync_reg_reg[1]_14 ;
  wire \SYNC[5].sync_reg_reg[1]_15 ;
  wire \SYNC[5].sync_reg_reg[1]_16 ;
  wire \SYNC[5].sync_reg_reg[1]_17 ;
  wire \SYNC[5].sync_reg_reg[1]_2 ;
  wire \SYNC[5].sync_reg_reg[1]_3 ;
  wire \SYNC[5].sync_reg_reg[1]_4 ;
  wire \SYNC[5].sync_reg_reg[1]_5 ;
  wire \SYNC[5].sync_reg_reg[1]_6 ;
  wire \SYNC[5].sync_reg_reg[1]_7 ;
  wire \SYNC[5].sync_reg_reg[1]_8 ;
  wire \SYNC[5].sync_reg_reg[1]_9 ;
  wire a_b_cmd_sel;
  wire a_b_cmd_sel0;
  wire a_b_cmd_sel_start0;
  wire a_b_cmd_sel_start_reg_0;
  wire a_b_cmd_sel_start_reg_1;
  wire a_b_rd_sel_r;
  wire a_b_rd_sel_r_i_1_n_0;
  wire \addr_dec_to_mb_data[0]_i_26_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_3 ;
  wire \addr_dec_to_mb_data[0]_i_40_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_41_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_42_n_0 ;
  wire \addr_dec_to_mb_data[10]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[10]_i_14_n_0 ;
  wire \addr_dec_to_mb_data[11]_i_14_n_0 ;
  wire \addr_dec_to_mb_data[11]_i_15_n_0 ;
  wire \addr_dec_to_mb_data[12]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[12]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[13]_i_14_n_0 ;
  wire \addr_dec_to_mb_data[13]_i_15_n_0 ;
  wire \addr_dec_to_mb_data[14]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[14]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[15]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[15]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[17]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[18]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[19]_i_17_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_20_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_25_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_26_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_27_n_0 ;
  wire \addr_dec_to_mb_data[20]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[21]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[21]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[22]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[23]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[24]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[24]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[25]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[25]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[26]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[27]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[28]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[28]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[29]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[29]_i_14_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_38_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_39_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_40_n_0 ;
  wire \addr_dec_to_mb_data[30]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[31]_i_3 ;
  wire \addr_dec_to_mb_data[31]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_15_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_16_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_17_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_34_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_35_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_11 ;
  wire \addr_dec_to_mb_data[4]_i_36_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_37_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_44_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_45_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_33_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_34_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_35_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_36_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_19_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_22_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_23_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_7 ;
  wire \addr_dec_to_mb_data[6]_i_7_0 ;
  wire \addr_dec_to_mb_data[7]_i_16_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_22_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_25_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_7_0 ;
  wire \addr_dec_to_mb_data[8]_i_20_n_0 ;
  wire \addr_dec_to_mb_data[9]_i_15_n_0 ;
  wire \addr_dec_to_mb_data_reg[12]_0 ;
  wire \addr_dec_to_mb_data_reg[14]_0 ;
  wire \addr_dec_to_mb_data_reg[15]_0 ;
  wire \addr_dec_to_mb_data_reg[19]_0 ;
  wire \addr_dec_to_mb_data_reg[20]_0 ;
  wire \addr_dec_to_mb_data_reg[21]_0 ;
  wire \addr_dec_to_mb_data_reg[22]_0 ;
  wire \addr_dec_to_mb_data_reg[23]_0 ;
  wire \addr_dec_to_mb_data_reg[24]_0 ;
  wire \addr_dec_to_mb_data_reg[25]_0 ;
  wire \addr_dec_to_mb_data_reg[26]_0 ;
  wire \addr_dec_to_mb_data_reg[27]_0 ;
  wire \addr_dec_to_mb_data_reg[28]_0 ;
  wire \addr_dec_to_mb_data_reg[29]_0 ;
  wire \addr_dec_to_mb_data_reg[29]_1 ;
  wire \addr_dec_to_mb_data_reg[29]_2 ;
  wire \addr_dec_to_mb_data_reg[29]_3 ;
  wire \addr_dec_to_mb_data_reg[29]_4 ;
  wire \addr_dec_to_mb_data_reg[29]_5 ;
  wire \addr_dec_to_mb_data_reg[30]_0 ;
  wire \addr_dec_to_mb_data_reg[30]_1 ;
  wire [20:0]\addr_dec_to_mb_data_reg[31]_0 ;
  wire \addr_dec_to_mb_data_reg_n_0_[0] ;
  wire \addr_dec_to_mb_data_reg_n_0_[10] ;
  wire \addr_dec_to_mb_data_reg_n_0_[11] ;
  wire \addr_dec_to_mb_data_reg_n_0_[12] ;
  wire \addr_dec_to_mb_data_reg_n_0_[13] ;
  wire \addr_dec_to_mb_data_reg_n_0_[14] ;
  wire \addr_dec_to_mb_data_reg_n_0_[15] ;
  wire \addr_dec_to_mb_data_reg_n_0_[16] ;
  wire \addr_dec_to_mb_data_reg_n_0_[17] ;
  wire \addr_dec_to_mb_data_reg_n_0_[18] ;
  wire \addr_dec_to_mb_data_reg_n_0_[19] ;
  wire \addr_dec_to_mb_data_reg_n_0_[1] ;
  wire \addr_dec_to_mb_data_reg_n_0_[20] ;
  wire \addr_dec_to_mb_data_reg_n_0_[21] ;
  wire \addr_dec_to_mb_data_reg_n_0_[22] ;
  wire \addr_dec_to_mb_data_reg_n_0_[23] ;
  wire \addr_dec_to_mb_data_reg_n_0_[24] ;
  wire \addr_dec_to_mb_data_reg_n_0_[25] ;
  wire \addr_dec_to_mb_data_reg_n_0_[26] ;
  wire \addr_dec_to_mb_data_reg_n_0_[27] ;
  wire \addr_dec_to_mb_data_reg_n_0_[28] ;
  wire \addr_dec_to_mb_data_reg_n_0_[29] ;
  wire \addr_dec_to_mb_data_reg_n_0_[2] ;
  wire \addr_dec_to_mb_data_reg_n_0_[30] ;
  wire \addr_dec_to_mb_data_reg_n_0_[31] ;
  wire \addr_dec_to_mb_data_reg_n_0_[3] ;
  wire \addr_dec_to_mb_data_reg_n_0_[4] ;
  wire \addr_dec_to_mb_data_reg_n_0_[5] ;
  wire \addr_dec_to_mb_data_reg_n_0_[6] ;
  wire \addr_dec_to_mb_data_reg_n_0_[7] ;
  wire \addr_dec_to_mb_data_reg_n_0_[8] ;
  wire \addr_dec_to_mb_data_reg_n_0_[9] ;
  wire [0:0]\bisc_bit_reg[0]_0 ;
  wire [8:0]bisc_byte;
  wire [1:1]calCasSlot;
  wire calDone_reg_0;
  wire calDone_reg_1;
  wire calDone_reg_10;
  wire calDone_reg_11;
  wire calDone_reg_12;
  wire calDone_reg_13;
  wire calDone_reg_14;
  wire calDone_reg_2;
  wire [76:0]calDone_reg_3;
  wire [3:0]calDone_reg_4;
  wire [7:0]calDone_reg_5;
  wire calDone_reg_6;
  wire calDone_reg_7;
  wire calDone_reg_8;
  wire calDone_reg_9;
  wire [0:0]\calSt_reg[0] ;
  wire [0:0]\calSt_reg[2] ;
  wire [0:0]\cal_ACT_n_A_reg[7]_0 ;
  wire \cal_ACT_n_A_reg_n_0_[0] ;
  wire \cal_ACT_n_A_reg_n_0_[1] ;
  wire \cal_ACT_n_A_reg_n_0_[2] ;
  wire \cal_ACT_n_A_reg_n_0_[3] ;
  wire \cal_ACT_n_A_reg_n_0_[4] ;
  wire \cal_ACT_n_A_reg_n_0_[5] ;
  wire \cal_ACT_n_A_reg_n_0_[6] ;
  wire \cal_ACT_n_A_reg_n_0_[7] ;
  wire \cal_ACT_n_B_reg_n_0_[0] ;
  wire \cal_ACT_n_B_reg_n_0_[1] ;
  wire \cal_ACT_n_B_reg_n_0_[2] ;
  wire \cal_ACT_n_B_reg_n_0_[3] ;
  wire \cal_ACT_n_B_reg_n_0_[4] ;
  wire \cal_ACT_n_B_reg_n_0_[5] ;
  wire \cal_ACT_n_B_reg_n_0_[6] ;
  wire \cal_ACT_n_B_reg_n_0_[7] ;
  wire [7:0]cal_ACT_n_pre;
  wire [7:0]cal_ACT_n_pre_nxt;
  wire [5:0]\cal_ACT_n_pre_reg[7]_0 ;
  wire \cal_ADR_A_reg[0]_0 ;
  wire \cal_ADR_A_reg[0]_1 ;
  wire \cal_ADR_A_reg[1]_0 ;
  wire \cal_ADR_A_reg[20]_0 ;
  wire \cal_ADR_A_reg[21]_0 ;
  wire \cal_ADR_A_reg[22]_0 ;
  wire \cal_ADR_A_reg[26]_0 ;
  wire \cal_ADR_A_reg[27]_0 ;
  wire \cal_ADR_A_reg[29]_0 ;
  wire \cal_ADR_A_reg[2]_0 ;
  wire [11:0]\cal_ADR_A_reg[30]_0 ;
  wire [0:0]\cal_ADR_A_reg[31]_0 ;
  wire \cal_ADR_A_reg[3]_0 ;
  wire \cal_ADR_A_reg[4]_0 ;
  wire \cal_ADR_A_reg[4]_1 ;
  wire \cal_ADR_A_reg_n_0_[0] ;
  wire \cal_ADR_A_reg_n_0_[10] ;
  wire \cal_ADR_A_reg_n_0_[11] ;
  wire \cal_ADR_A_reg_n_0_[12] ;
  wire \cal_ADR_A_reg_n_0_[13] ;
  wire \cal_ADR_A_reg_n_0_[15] ;
  wire \cal_ADR_A_reg_n_0_[16] ;
  wire \cal_ADR_A_reg_n_0_[17] ;
  wire \cal_ADR_A_reg_n_0_[18] ;
  wire \cal_ADR_A_reg_n_0_[19] ;
  wire \cal_ADR_A_reg_n_0_[20] ;
  wire \cal_ADR_A_reg_n_0_[21] ;
  wire \cal_ADR_A_reg_n_0_[22] ;
  wire \cal_ADR_A_reg_n_0_[24] ;
  wire \cal_ADR_A_reg_n_0_[25] ;
  wire \cal_ADR_A_reg_n_0_[26] ;
  wire \cal_ADR_A_reg_n_0_[27] ;
  wire \cal_ADR_A_reg_n_0_[29] ;
  wire \cal_ADR_A_reg_n_0_[31] ;
  wire \cal_ADR_A_reg_n_0_[9] ;
  wire \cal_ADR_B_reg[10]_0 ;
  wire \cal_ADR_B_reg[11]_0 ;
  wire \cal_ADR_B_reg[12]_0 ;
  wire \cal_ADR_B_reg[13]_0 ;
  wire \cal_ADR_B_reg[15]_0 ;
  wire \cal_ADR_B_reg[17]_0 ;
  wire \cal_ADR_B_reg[18]_0 ;
  wire \cal_ADR_B_reg[19]_0 ;
  wire \cal_ADR_B_reg[24]_0 ;
  wire \cal_ADR_B_reg[25]_0 ;
  wire [12:0]\cal_ADR_B_reg[30]_0 ;
  wire \cal_ADR_B_reg[31]_0 ;
  wire [0:0]\cal_ADR_B_reg[31]_1 ;
  wire \cal_ADR_B_reg_n_0_[0] ;
  wire \cal_ADR_B_reg_n_0_[10] ;
  wire \cal_ADR_B_reg_n_0_[11] ;
  wire \cal_ADR_B_reg_n_0_[12] ;
  wire \cal_ADR_B_reg_n_0_[13] ;
  wire \cal_ADR_B_reg_n_0_[15] ;
  wire \cal_ADR_B_reg_n_0_[16] ;
  wire \cal_ADR_B_reg_n_0_[17] ;
  wire \cal_ADR_B_reg_n_0_[18] ;
  wire \cal_ADR_B_reg_n_0_[19] ;
  wire \cal_ADR_B_reg_n_0_[20] ;
  wire \cal_ADR_B_reg_n_0_[21] ;
  wire \cal_ADR_B_reg_n_0_[24] ;
  wire \cal_ADR_B_reg_n_0_[25] ;
  wire \cal_ADR_B_reg_n_0_[26] ;
  wire \cal_ADR_B_reg_n_0_[27] ;
  wire \cal_ADR_B_reg_n_0_[29] ;
  wire \cal_ADR_B_reg_n_0_[31] ;
  wire \cal_ADR_B_reg_n_0_[9] ;
  wire [7:0]cal_CAS_A;
  wire [0:0]\cal_CAS_A_reg[0]_0 ;
  wire [7:0]cal_CAS_B;
  wire [7:0]cal_CAS_pre;
  wire [7:0]cal_CAS_pre_nxt;
  wire \cal_CS_A_reg[0]_0 ;
  wire \cal_CS_A_reg[4]_0 ;
  wire [4:0]\cal_CS_A_reg[5]_0 ;
  wire \cal_CS_A_reg[6]_0 ;
  wire \cal_CS_A_reg[7]_0 ;
  wire [0:0]\cal_CS_A_reg[7]_1 ;
  wire \cal_CS_A_reg_n_0_[0] ;
  wire \cal_CS_A_reg_n_0_[6] ;
  wire \cal_CS_A_reg_n_0_[7] ;
  wire [4:0]\cal_CS_B_reg[5]_0 ;
  wire [0:0]\cal_CS_B_reg[7]_0 ;
  wire \cal_CS_B_reg_n_0_[0] ;
  wire \cal_CS_B_reg_n_0_[6] ;
  wire \cal_CS_B_reg_n_0_[7] ;
  wire [3:0]cal_CS_n;
  wire cal_CS_n_pre;
  wire \cal_CS_n_pre[0]_i_1_n_0 ;
  wire \cal_CS_n_pre[1]_i_1_n_0 ;
  wire \cal_CS_n_pre[2]_i_1_n_0 ;
  wire \cal_CS_n_pre[3]_i_1_n_0 ;
  wire \cal_CS_n_pre[4]_i_1_n_0 ;
  wire \cal_CS_n_pre[5]_i_1_n_0 ;
  wire \cal_CS_n_pre[6]_i_1_n_0 ;
  wire \cal_CS_n_pre[7]_i_2_n_0 ;
  wire \cal_CS_n_pre[7]_i_3_n_0 ;
  wire \cal_CS_n_pre[7]_i_4_n_0 ;
  wire \cal_CS_n_pre_reg_n_0_[0] ;
  wire \cal_CS_n_pre_reg_n_0_[1] ;
  wire \cal_CS_n_pre_reg_n_0_[2] ;
  wire \cal_CS_n_pre_reg_n_0_[3] ;
  wire \cal_CS_n_pre_reg_n_0_[4] ;
  wire \cal_CS_n_pre_reg_n_0_[5] ;
  wire \cal_CS_n_pre_reg_n_0_[6] ;
  wire \cal_CS_n_pre_reg_n_0_[7] ;
  wire [63:0]cal_DMOut_n;
  wire [0:0]\cal_DMOut_n_A_reg[31]_0 ;
  wire \cal_DMOut_n_A_reg_n_0_[0] ;
  wire \cal_DMOut_n_A_reg_n_0_[10] ;
  wire \cal_DMOut_n_A_reg_n_0_[11] ;
  wire \cal_DMOut_n_A_reg_n_0_[12] ;
  wire \cal_DMOut_n_A_reg_n_0_[13] ;
  wire \cal_DMOut_n_A_reg_n_0_[14] ;
  wire \cal_DMOut_n_A_reg_n_0_[15] ;
  wire \cal_DMOut_n_A_reg_n_0_[16] ;
  wire \cal_DMOut_n_A_reg_n_0_[17] ;
  wire \cal_DMOut_n_A_reg_n_0_[18] ;
  wire \cal_DMOut_n_A_reg_n_0_[19] ;
  wire \cal_DMOut_n_A_reg_n_0_[1] ;
  wire \cal_DMOut_n_A_reg_n_0_[20] ;
  wire \cal_DMOut_n_A_reg_n_0_[21] ;
  wire \cal_DMOut_n_A_reg_n_0_[22] ;
  wire \cal_DMOut_n_A_reg_n_0_[23] ;
  wire \cal_DMOut_n_A_reg_n_0_[24] ;
  wire \cal_DMOut_n_A_reg_n_0_[25] ;
  wire \cal_DMOut_n_A_reg_n_0_[26] ;
  wire \cal_DMOut_n_A_reg_n_0_[27] ;
  wire \cal_DMOut_n_A_reg_n_0_[28] ;
  wire \cal_DMOut_n_A_reg_n_0_[29] ;
  wire \cal_DMOut_n_A_reg_n_0_[2] ;
  wire \cal_DMOut_n_A_reg_n_0_[30] ;
  wire \cal_DMOut_n_A_reg_n_0_[31] ;
  wire \cal_DMOut_n_A_reg_n_0_[3] ;
  wire \cal_DMOut_n_A_reg_n_0_[4] ;
  wire \cal_DMOut_n_A_reg_n_0_[5] ;
  wire \cal_DMOut_n_A_reg_n_0_[6] ;
  wire \cal_DMOut_n_A_reg_n_0_[7] ;
  wire \cal_DMOut_n_A_reg_n_0_[8] ;
  wire \cal_DMOut_n_A_reg_n_0_[9] ;
  wire [63:0]cal_DMOut_n_nxt;
  wire [511:0]cal_DQOut;
  wire \cal_DQOut_A_reg[31]_0 ;
  wire \cal_DQOut_A_reg[63]_0 ;
  wire \cal_DQOut_A_reg_n_0_[0] ;
  wire \cal_DQOut_A_reg_n_0_[10] ;
  wire \cal_DQOut_A_reg_n_0_[11] ;
  wire \cal_DQOut_A_reg_n_0_[12] ;
  wire \cal_DQOut_A_reg_n_0_[13] ;
  wire \cal_DQOut_A_reg_n_0_[14] ;
  wire \cal_DQOut_A_reg_n_0_[15] ;
  wire \cal_DQOut_A_reg_n_0_[16] ;
  wire \cal_DQOut_A_reg_n_0_[17] ;
  wire \cal_DQOut_A_reg_n_0_[18] ;
  wire \cal_DQOut_A_reg_n_0_[19] ;
  wire \cal_DQOut_A_reg_n_0_[1] ;
  wire \cal_DQOut_A_reg_n_0_[20] ;
  wire \cal_DQOut_A_reg_n_0_[21] ;
  wire \cal_DQOut_A_reg_n_0_[22] ;
  wire \cal_DQOut_A_reg_n_0_[23] ;
  wire \cal_DQOut_A_reg_n_0_[24] ;
  wire \cal_DQOut_A_reg_n_0_[25] ;
  wire \cal_DQOut_A_reg_n_0_[26] ;
  wire \cal_DQOut_A_reg_n_0_[27] ;
  wire \cal_DQOut_A_reg_n_0_[28] ;
  wire \cal_DQOut_A_reg_n_0_[29] ;
  wire \cal_DQOut_A_reg_n_0_[2] ;
  wire \cal_DQOut_A_reg_n_0_[30] ;
  wire \cal_DQOut_A_reg_n_0_[31] ;
  wire \cal_DQOut_A_reg_n_0_[32] ;
  wire \cal_DQOut_A_reg_n_0_[33] ;
  wire \cal_DQOut_A_reg_n_0_[34] ;
  wire \cal_DQOut_A_reg_n_0_[35] ;
  wire \cal_DQOut_A_reg_n_0_[36] ;
  wire \cal_DQOut_A_reg_n_0_[37] ;
  wire \cal_DQOut_A_reg_n_0_[38] ;
  wire \cal_DQOut_A_reg_n_0_[39] ;
  wire \cal_DQOut_A_reg_n_0_[3] ;
  wire \cal_DQOut_A_reg_n_0_[40] ;
  wire \cal_DQOut_A_reg_n_0_[41] ;
  wire \cal_DQOut_A_reg_n_0_[42] ;
  wire \cal_DQOut_A_reg_n_0_[43] ;
  wire \cal_DQOut_A_reg_n_0_[44] ;
  wire \cal_DQOut_A_reg_n_0_[45] ;
  wire \cal_DQOut_A_reg_n_0_[46] ;
  wire \cal_DQOut_A_reg_n_0_[47] ;
  wire \cal_DQOut_A_reg_n_0_[48] ;
  wire \cal_DQOut_A_reg_n_0_[49] ;
  wire \cal_DQOut_A_reg_n_0_[4] ;
  wire \cal_DQOut_A_reg_n_0_[50] ;
  wire \cal_DQOut_A_reg_n_0_[51] ;
  wire \cal_DQOut_A_reg_n_0_[52] ;
  wire \cal_DQOut_A_reg_n_0_[53] ;
  wire \cal_DQOut_A_reg_n_0_[54] ;
  wire \cal_DQOut_A_reg_n_0_[55] ;
  wire \cal_DQOut_A_reg_n_0_[56] ;
  wire \cal_DQOut_A_reg_n_0_[57] ;
  wire \cal_DQOut_A_reg_n_0_[58] ;
  wire \cal_DQOut_A_reg_n_0_[59] ;
  wire \cal_DQOut_A_reg_n_0_[5] ;
  wire \cal_DQOut_A_reg_n_0_[60] ;
  wire \cal_DQOut_A_reg_n_0_[61] ;
  wire \cal_DQOut_A_reg_n_0_[62] ;
  wire \cal_DQOut_A_reg_n_0_[63] ;
  wire \cal_DQOut_A_reg_n_0_[6] ;
  wire \cal_DQOut_A_reg_n_0_[7] ;
  wire \cal_DQOut_A_reg_n_0_[8] ;
  wire \cal_DQOut_A_reg_n_0_[9] ;
  wire [511:0]cal_DQOut_nxt;
  wire \cal_DQOut_post_reg[31]_0 ;
  wire \cal_DQOut_post_reg[63]_0 ;
  wire \cal_DQOut_post_reg_n_0_[0] ;
  wire \cal_DQOut_post_reg_n_0_[10] ;
  wire \cal_DQOut_post_reg_n_0_[11] ;
  wire \cal_DQOut_post_reg_n_0_[12] ;
  wire \cal_DQOut_post_reg_n_0_[13] ;
  wire \cal_DQOut_post_reg_n_0_[14] ;
  wire \cal_DQOut_post_reg_n_0_[15] ;
  wire \cal_DQOut_post_reg_n_0_[16] ;
  wire \cal_DQOut_post_reg_n_0_[17] ;
  wire \cal_DQOut_post_reg_n_0_[18] ;
  wire \cal_DQOut_post_reg_n_0_[19] ;
  wire \cal_DQOut_post_reg_n_0_[1] ;
  wire \cal_DQOut_post_reg_n_0_[20] ;
  wire \cal_DQOut_post_reg_n_0_[21] ;
  wire \cal_DQOut_post_reg_n_0_[22] ;
  wire \cal_DQOut_post_reg_n_0_[23] ;
  wire \cal_DQOut_post_reg_n_0_[24] ;
  wire \cal_DQOut_post_reg_n_0_[25] ;
  wire \cal_DQOut_post_reg_n_0_[26] ;
  wire \cal_DQOut_post_reg_n_0_[27] ;
  wire \cal_DQOut_post_reg_n_0_[28] ;
  wire \cal_DQOut_post_reg_n_0_[29] ;
  wire \cal_DQOut_post_reg_n_0_[2] ;
  wire \cal_DQOut_post_reg_n_0_[30] ;
  wire \cal_DQOut_post_reg_n_0_[31] ;
  wire \cal_DQOut_post_reg_n_0_[32] ;
  wire \cal_DQOut_post_reg_n_0_[33] ;
  wire \cal_DQOut_post_reg_n_0_[34] ;
  wire \cal_DQOut_post_reg_n_0_[35] ;
  wire \cal_DQOut_post_reg_n_0_[36] ;
  wire \cal_DQOut_post_reg_n_0_[37] ;
  wire \cal_DQOut_post_reg_n_0_[38] ;
  wire \cal_DQOut_post_reg_n_0_[39] ;
  wire \cal_DQOut_post_reg_n_0_[3] ;
  wire \cal_DQOut_post_reg_n_0_[40] ;
  wire \cal_DQOut_post_reg_n_0_[41] ;
  wire \cal_DQOut_post_reg_n_0_[42] ;
  wire \cal_DQOut_post_reg_n_0_[43] ;
  wire \cal_DQOut_post_reg_n_0_[44] ;
  wire \cal_DQOut_post_reg_n_0_[45] ;
  wire \cal_DQOut_post_reg_n_0_[46] ;
  wire \cal_DQOut_post_reg_n_0_[47] ;
  wire \cal_DQOut_post_reg_n_0_[48] ;
  wire \cal_DQOut_post_reg_n_0_[49] ;
  wire \cal_DQOut_post_reg_n_0_[4] ;
  wire \cal_DQOut_post_reg_n_0_[50] ;
  wire \cal_DQOut_post_reg_n_0_[51] ;
  wire \cal_DQOut_post_reg_n_0_[52] ;
  wire \cal_DQOut_post_reg_n_0_[53] ;
  wire \cal_DQOut_post_reg_n_0_[54] ;
  wire \cal_DQOut_post_reg_n_0_[55] ;
  wire \cal_DQOut_post_reg_n_0_[56] ;
  wire \cal_DQOut_post_reg_n_0_[57] ;
  wire \cal_DQOut_post_reg_n_0_[58] ;
  wire \cal_DQOut_post_reg_n_0_[59] ;
  wire \cal_DQOut_post_reg_n_0_[5] ;
  wire \cal_DQOut_post_reg_n_0_[60] ;
  wire \cal_DQOut_post_reg_n_0_[61] ;
  wire \cal_DQOut_post_reg_n_0_[62] ;
  wire \cal_DQOut_post_reg_n_0_[63] ;
  wire \cal_DQOut_post_reg_n_0_[6] ;
  wire \cal_DQOut_post_reg_n_0_[7] ;
  wire \cal_DQOut_post_reg_n_0_[8] ;
  wire \cal_DQOut_post_reg_n_0_[9] ;
  wire \cal_DQOut_pre_reg[31]_0 ;
  wire \cal_DQOut_pre_reg[63]_0 ;
  wire \cal_DQOut_pre_reg_n_0_[0] ;
  wire \cal_DQOut_pre_reg_n_0_[10] ;
  wire \cal_DQOut_pre_reg_n_0_[11] ;
  wire \cal_DQOut_pre_reg_n_0_[12] ;
  wire \cal_DQOut_pre_reg_n_0_[13] ;
  wire \cal_DQOut_pre_reg_n_0_[14] ;
  wire \cal_DQOut_pre_reg_n_0_[15] ;
  wire \cal_DQOut_pre_reg_n_0_[16] ;
  wire \cal_DQOut_pre_reg_n_0_[17] ;
  wire \cal_DQOut_pre_reg_n_0_[18] ;
  wire \cal_DQOut_pre_reg_n_0_[19] ;
  wire \cal_DQOut_pre_reg_n_0_[1] ;
  wire \cal_DQOut_pre_reg_n_0_[20] ;
  wire \cal_DQOut_pre_reg_n_0_[21] ;
  wire \cal_DQOut_pre_reg_n_0_[22] ;
  wire \cal_DQOut_pre_reg_n_0_[23] ;
  wire \cal_DQOut_pre_reg_n_0_[24] ;
  wire \cal_DQOut_pre_reg_n_0_[25] ;
  wire \cal_DQOut_pre_reg_n_0_[26] ;
  wire \cal_DQOut_pre_reg_n_0_[27] ;
  wire \cal_DQOut_pre_reg_n_0_[28] ;
  wire \cal_DQOut_pre_reg_n_0_[29] ;
  wire \cal_DQOut_pre_reg_n_0_[2] ;
  wire \cal_DQOut_pre_reg_n_0_[30] ;
  wire \cal_DQOut_pre_reg_n_0_[31] ;
  wire \cal_DQOut_pre_reg_n_0_[32] ;
  wire \cal_DQOut_pre_reg_n_0_[33] ;
  wire \cal_DQOut_pre_reg_n_0_[34] ;
  wire \cal_DQOut_pre_reg_n_0_[35] ;
  wire \cal_DQOut_pre_reg_n_0_[36] ;
  wire \cal_DQOut_pre_reg_n_0_[37] ;
  wire \cal_DQOut_pre_reg_n_0_[38] ;
  wire \cal_DQOut_pre_reg_n_0_[39] ;
  wire \cal_DQOut_pre_reg_n_0_[3] ;
  wire \cal_DQOut_pre_reg_n_0_[40] ;
  wire \cal_DQOut_pre_reg_n_0_[41] ;
  wire \cal_DQOut_pre_reg_n_0_[42] ;
  wire \cal_DQOut_pre_reg_n_0_[43] ;
  wire \cal_DQOut_pre_reg_n_0_[44] ;
  wire \cal_DQOut_pre_reg_n_0_[45] ;
  wire \cal_DQOut_pre_reg_n_0_[46] ;
  wire \cal_DQOut_pre_reg_n_0_[47] ;
  wire \cal_DQOut_pre_reg_n_0_[48] ;
  wire \cal_DQOut_pre_reg_n_0_[49] ;
  wire \cal_DQOut_pre_reg_n_0_[4] ;
  wire \cal_DQOut_pre_reg_n_0_[50] ;
  wire \cal_DQOut_pre_reg_n_0_[51] ;
  wire \cal_DQOut_pre_reg_n_0_[52] ;
  wire \cal_DQOut_pre_reg_n_0_[53] ;
  wire \cal_DQOut_pre_reg_n_0_[54] ;
  wire \cal_DQOut_pre_reg_n_0_[55] ;
  wire \cal_DQOut_pre_reg_n_0_[56] ;
  wire \cal_DQOut_pre_reg_n_0_[57] ;
  wire \cal_DQOut_pre_reg_n_0_[58] ;
  wire \cal_DQOut_pre_reg_n_0_[59] ;
  wire \cal_DQOut_pre_reg_n_0_[5] ;
  wire \cal_DQOut_pre_reg_n_0_[60] ;
  wire \cal_DQOut_pre_reg_n_0_[61] ;
  wire \cal_DQOut_pre_reg_n_0_[62] ;
  wire \cal_DQOut_pre_reg_n_0_[63] ;
  wire \cal_DQOut_pre_reg_n_0_[6] ;
  wire \cal_DQOut_pre_reg_n_0_[7] ;
  wire \cal_DQOut_pre_reg_n_0_[8] ;
  wire \cal_DQOut_pre_reg_n_0_[9] ;
  wire \cal_DQPat_A_reg[31]_0 ;
  wire \cal_DQPat_A_reg[63]_0 ;
  wire \cal_DQPat_A_reg_n_0_[0] ;
  wire \cal_DQPat_A_reg_n_0_[10] ;
  wire \cal_DQPat_A_reg_n_0_[11] ;
  wire \cal_DQPat_A_reg_n_0_[12] ;
  wire \cal_DQPat_A_reg_n_0_[13] ;
  wire \cal_DQPat_A_reg_n_0_[14] ;
  wire \cal_DQPat_A_reg_n_0_[15] ;
  wire \cal_DQPat_A_reg_n_0_[16] ;
  wire \cal_DQPat_A_reg_n_0_[17] ;
  wire \cal_DQPat_A_reg_n_0_[18] ;
  wire \cal_DQPat_A_reg_n_0_[19] ;
  wire \cal_DQPat_A_reg_n_0_[1] ;
  wire \cal_DQPat_A_reg_n_0_[20] ;
  wire \cal_DQPat_A_reg_n_0_[21] ;
  wire \cal_DQPat_A_reg_n_0_[22] ;
  wire \cal_DQPat_A_reg_n_0_[23] ;
  wire \cal_DQPat_A_reg_n_0_[24] ;
  wire \cal_DQPat_A_reg_n_0_[25] ;
  wire \cal_DQPat_A_reg_n_0_[26] ;
  wire \cal_DQPat_A_reg_n_0_[27] ;
  wire \cal_DQPat_A_reg_n_0_[28] ;
  wire \cal_DQPat_A_reg_n_0_[29] ;
  wire \cal_DQPat_A_reg_n_0_[2] ;
  wire \cal_DQPat_A_reg_n_0_[30] ;
  wire \cal_DQPat_A_reg_n_0_[31] ;
  wire \cal_DQPat_A_reg_n_0_[32] ;
  wire \cal_DQPat_A_reg_n_0_[33] ;
  wire \cal_DQPat_A_reg_n_0_[34] ;
  wire \cal_DQPat_A_reg_n_0_[35] ;
  wire \cal_DQPat_A_reg_n_0_[36] ;
  wire \cal_DQPat_A_reg_n_0_[37] ;
  wire \cal_DQPat_A_reg_n_0_[38] ;
  wire \cal_DQPat_A_reg_n_0_[39] ;
  wire \cal_DQPat_A_reg_n_0_[3] ;
  wire \cal_DQPat_A_reg_n_0_[40] ;
  wire \cal_DQPat_A_reg_n_0_[41] ;
  wire \cal_DQPat_A_reg_n_0_[42] ;
  wire \cal_DQPat_A_reg_n_0_[43] ;
  wire \cal_DQPat_A_reg_n_0_[44] ;
  wire \cal_DQPat_A_reg_n_0_[45] ;
  wire \cal_DQPat_A_reg_n_0_[46] ;
  wire \cal_DQPat_A_reg_n_0_[47] ;
  wire \cal_DQPat_A_reg_n_0_[48] ;
  wire \cal_DQPat_A_reg_n_0_[49] ;
  wire \cal_DQPat_A_reg_n_0_[4] ;
  wire \cal_DQPat_A_reg_n_0_[50] ;
  wire \cal_DQPat_A_reg_n_0_[51] ;
  wire \cal_DQPat_A_reg_n_0_[52] ;
  wire \cal_DQPat_A_reg_n_0_[53] ;
  wire \cal_DQPat_A_reg_n_0_[54] ;
  wire \cal_DQPat_A_reg_n_0_[55] ;
  wire \cal_DQPat_A_reg_n_0_[56] ;
  wire \cal_DQPat_A_reg_n_0_[57] ;
  wire \cal_DQPat_A_reg_n_0_[58] ;
  wire \cal_DQPat_A_reg_n_0_[59] ;
  wire \cal_DQPat_A_reg_n_0_[5] ;
  wire \cal_DQPat_A_reg_n_0_[60] ;
  wire \cal_DQPat_A_reg_n_0_[61] ;
  wire \cal_DQPat_A_reg_n_0_[62] ;
  wire \cal_DQPat_A_reg_n_0_[63] ;
  wire \cal_DQPat_A_reg_n_0_[6] ;
  wire \cal_DQPat_A_reg_n_0_[7] ;
  wire \cal_DQPat_A_reg_n_0_[8] ;
  wire \cal_DQPat_A_reg_n_0_[9] ;
  wire \cal_DQPat_B_reg[31]_0 ;
  wire \cal_DQPat_B_reg[63]_0 ;
  wire \cal_DQPat_B_reg_n_0_[0] ;
  wire \cal_DQPat_B_reg_n_0_[10] ;
  wire \cal_DQPat_B_reg_n_0_[11] ;
  wire \cal_DQPat_B_reg_n_0_[12] ;
  wire \cal_DQPat_B_reg_n_0_[13] ;
  wire \cal_DQPat_B_reg_n_0_[14] ;
  wire \cal_DQPat_B_reg_n_0_[15] ;
  wire \cal_DQPat_B_reg_n_0_[16] ;
  wire \cal_DQPat_B_reg_n_0_[17] ;
  wire \cal_DQPat_B_reg_n_0_[18] ;
  wire \cal_DQPat_B_reg_n_0_[19] ;
  wire \cal_DQPat_B_reg_n_0_[1] ;
  wire \cal_DQPat_B_reg_n_0_[20] ;
  wire \cal_DQPat_B_reg_n_0_[21] ;
  wire \cal_DQPat_B_reg_n_0_[22] ;
  wire \cal_DQPat_B_reg_n_0_[23] ;
  wire \cal_DQPat_B_reg_n_0_[24] ;
  wire \cal_DQPat_B_reg_n_0_[25] ;
  wire \cal_DQPat_B_reg_n_0_[26] ;
  wire \cal_DQPat_B_reg_n_0_[27] ;
  wire \cal_DQPat_B_reg_n_0_[28] ;
  wire \cal_DQPat_B_reg_n_0_[29] ;
  wire \cal_DQPat_B_reg_n_0_[2] ;
  wire \cal_DQPat_B_reg_n_0_[30] ;
  wire \cal_DQPat_B_reg_n_0_[31] ;
  wire \cal_DQPat_B_reg_n_0_[32] ;
  wire \cal_DQPat_B_reg_n_0_[33] ;
  wire \cal_DQPat_B_reg_n_0_[34] ;
  wire \cal_DQPat_B_reg_n_0_[35] ;
  wire \cal_DQPat_B_reg_n_0_[36] ;
  wire \cal_DQPat_B_reg_n_0_[37] ;
  wire \cal_DQPat_B_reg_n_0_[38] ;
  wire \cal_DQPat_B_reg_n_0_[39] ;
  wire \cal_DQPat_B_reg_n_0_[3] ;
  wire \cal_DQPat_B_reg_n_0_[40] ;
  wire \cal_DQPat_B_reg_n_0_[41] ;
  wire \cal_DQPat_B_reg_n_0_[42] ;
  wire \cal_DQPat_B_reg_n_0_[43] ;
  wire \cal_DQPat_B_reg_n_0_[44] ;
  wire \cal_DQPat_B_reg_n_0_[45] ;
  wire \cal_DQPat_B_reg_n_0_[46] ;
  wire \cal_DQPat_B_reg_n_0_[47] ;
  wire \cal_DQPat_B_reg_n_0_[48] ;
  wire \cal_DQPat_B_reg_n_0_[49] ;
  wire \cal_DQPat_B_reg_n_0_[4] ;
  wire \cal_DQPat_B_reg_n_0_[50] ;
  wire \cal_DQPat_B_reg_n_0_[51] ;
  wire \cal_DQPat_B_reg_n_0_[52] ;
  wire \cal_DQPat_B_reg_n_0_[53] ;
  wire \cal_DQPat_B_reg_n_0_[54] ;
  wire \cal_DQPat_B_reg_n_0_[55] ;
  wire \cal_DQPat_B_reg_n_0_[56] ;
  wire \cal_DQPat_B_reg_n_0_[57] ;
  wire \cal_DQPat_B_reg_n_0_[58] ;
  wire \cal_DQPat_B_reg_n_0_[59] ;
  wire \cal_DQPat_B_reg_n_0_[5] ;
  wire \cal_DQPat_B_reg_n_0_[60] ;
  wire \cal_DQPat_B_reg_n_0_[61] ;
  wire \cal_DQPat_B_reg_n_0_[62] ;
  wire \cal_DQPat_B_reg_n_0_[63] ;
  wire \cal_DQPat_B_reg_n_0_[6] ;
  wire \cal_DQPat_B_reg_n_0_[7] ;
  wire \cal_DQPat_B_reg_n_0_[8] ;
  wire \cal_DQPat_B_reg_n_0_[9] ;
  wire \cal_DQ[0]_i_1_n_0 ;
  wire \cal_DQ[100]_i_1_n_0 ;
  wire \cal_DQ[101]_i_1_n_0 ;
  wire \cal_DQ[102]_i_1_n_0 ;
  wire \cal_DQ[103]_i_1_n_0 ;
  wire \cal_DQ[104]_i_1_n_0 ;
  wire \cal_DQ[105]_i_1_n_0 ;
  wire \cal_DQ[106]_i_1_n_0 ;
  wire \cal_DQ[107]_i_1_n_0 ;
  wire \cal_DQ[108]_i_1_n_0 ;
  wire \cal_DQ[109]_i_1_n_0 ;
  wire \cal_DQ[10]_i_1_n_0 ;
  wire \cal_DQ[110]_i_1_n_0 ;
  wire \cal_DQ[111]_i_1_n_0 ;
  wire \cal_DQ[112]_i_1_n_0 ;
  wire \cal_DQ[113]_i_1_n_0 ;
  wire \cal_DQ[114]_i_1_n_0 ;
  wire \cal_DQ[115]_i_1_n_0 ;
  wire \cal_DQ[116]_i_1_n_0 ;
  wire \cal_DQ[117]_i_1_n_0 ;
  wire \cal_DQ[118]_i_1_n_0 ;
  wire \cal_DQ[119]_i_1_n_0 ;
  wire \cal_DQ[11]_i_1_n_0 ;
  wire \cal_DQ[120]_i_1_n_0 ;
  wire \cal_DQ[121]_i_1_n_0 ;
  wire \cal_DQ[122]_i_1_n_0 ;
  wire \cal_DQ[123]_i_1_n_0 ;
  wire \cal_DQ[124]_i_1_n_0 ;
  wire \cal_DQ[125]_i_1_n_0 ;
  wire \cal_DQ[126]_i_1_n_0 ;
  wire \cal_DQ[127]_i_1_n_0 ;
  wire \cal_DQ[127]_i_2_n_0 ;
  wire \cal_DQ[128]_i_1_n_0 ;
  wire \cal_DQ[129]_i_1_n_0 ;
  wire \cal_DQ[12]_i_1_n_0 ;
  wire \cal_DQ[130]_i_1_n_0 ;
  wire \cal_DQ[131]_i_1_n_0 ;
  wire \cal_DQ[132]_i_1_n_0 ;
  wire \cal_DQ[133]_i_1_n_0 ;
  wire \cal_DQ[134]_i_1_n_0 ;
  wire \cal_DQ[135]_i_1_n_0 ;
  wire \cal_DQ[136]_i_1_n_0 ;
  wire \cal_DQ[137]_i_1_n_0 ;
  wire \cal_DQ[138]_i_1_n_0 ;
  wire \cal_DQ[139]_i_1_n_0 ;
  wire \cal_DQ[13]_i_1_n_0 ;
  wire \cal_DQ[140]_i_1_n_0 ;
  wire \cal_DQ[141]_i_1_n_0 ;
  wire \cal_DQ[142]_i_1_n_0 ;
  wire \cal_DQ[143]_i_1_n_0 ;
  wire \cal_DQ[144]_i_1_n_0 ;
  wire \cal_DQ[145]_i_1_n_0 ;
  wire \cal_DQ[146]_i_1_n_0 ;
  wire \cal_DQ[147]_i_1_n_0 ;
  wire \cal_DQ[148]_i_1_n_0 ;
  wire \cal_DQ[149]_i_1_n_0 ;
  wire \cal_DQ[14]_i_1_n_0 ;
  wire \cal_DQ[150]_i_1_n_0 ;
  wire \cal_DQ[151]_i_1_n_0 ;
  wire \cal_DQ[152]_i_1_n_0 ;
  wire \cal_DQ[153]_i_1_n_0 ;
  wire \cal_DQ[154]_i_1_n_0 ;
  wire \cal_DQ[155]_i_1_n_0 ;
  wire \cal_DQ[156]_i_1_n_0 ;
  wire \cal_DQ[157]_i_1_n_0 ;
  wire \cal_DQ[158]_i_1_n_0 ;
  wire \cal_DQ[159]_i_1_n_0 ;
  wire \cal_DQ[15]_i_1_n_0 ;
  wire \cal_DQ[160]_i_1_n_0 ;
  wire \cal_DQ[161]_i_1_n_0 ;
  wire \cal_DQ[162]_i_1_n_0 ;
  wire \cal_DQ[163]_i_1_n_0 ;
  wire \cal_DQ[164]_i_1_n_0 ;
  wire \cal_DQ[165]_i_1_n_0 ;
  wire \cal_DQ[166]_i_1_n_0 ;
  wire \cal_DQ[167]_i_1_n_0 ;
  wire \cal_DQ[168]_i_1_n_0 ;
  wire \cal_DQ[169]_i_1_n_0 ;
  wire \cal_DQ[16]_i_1_n_0 ;
  wire \cal_DQ[170]_i_1_n_0 ;
  wire \cal_DQ[171]_i_1_n_0 ;
  wire \cal_DQ[172]_i_1_n_0 ;
  wire \cal_DQ[173]_i_1_n_0 ;
  wire \cal_DQ[174]_i_1_n_0 ;
  wire \cal_DQ[175]_i_1_n_0 ;
  wire \cal_DQ[176]_i_1_n_0 ;
  wire \cal_DQ[177]_i_1_n_0 ;
  wire \cal_DQ[178]_i_1_n_0 ;
  wire \cal_DQ[179]_i_1_n_0 ;
  wire \cal_DQ[17]_i_1_n_0 ;
  wire \cal_DQ[180]_i_1_n_0 ;
  wire \cal_DQ[181]_i_1_n_0 ;
  wire \cal_DQ[182]_i_1_n_0 ;
  wire \cal_DQ[183]_i_1_n_0 ;
  wire \cal_DQ[184]_i_1_n_0 ;
  wire \cal_DQ[185]_i_1_n_0 ;
  wire \cal_DQ[186]_i_1_n_0 ;
  wire \cal_DQ[187]_i_1_n_0 ;
  wire \cal_DQ[188]_i_1_n_0 ;
  wire \cal_DQ[189]_i_1_n_0 ;
  wire \cal_DQ[18]_i_1_n_0 ;
  wire \cal_DQ[190]_i_1_n_0 ;
  wire \cal_DQ[191]_i_1_n_0 ;
  wire \cal_DQ[191]_i_2_n_0 ;
  wire \cal_DQ[191]_i_3_n_0 ;
  wire \cal_DQ[192]_i_1_n_0 ;
  wire \cal_DQ[193]_i_1_n_0 ;
  wire \cal_DQ[194]_i_1_n_0 ;
  wire \cal_DQ[195]_i_1_n_0 ;
  wire \cal_DQ[196]_i_1_n_0 ;
  wire \cal_DQ[197]_i_1_n_0 ;
  wire \cal_DQ[198]_i_1_n_0 ;
  wire \cal_DQ[199]_i_1_n_0 ;
  wire \cal_DQ[19]_i_1_n_0 ;
  wire \cal_DQ[1]_i_1_n_0 ;
  wire \cal_DQ[200]_i_1_n_0 ;
  wire \cal_DQ[201]_i_1_n_0 ;
  wire \cal_DQ[202]_i_1_n_0 ;
  wire \cal_DQ[203]_i_1_n_0 ;
  wire \cal_DQ[204]_i_1_n_0 ;
  wire \cal_DQ[205]_i_1_n_0 ;
  wire \cal_DQ[206]_i_1_n_0 ;
  wire \cal_DQ[207]_i_1_n_0 ;
  wire \cal_DQ[208]_i_1_n_0 ;
  wire \cal_DQ[209]_i_1_n_0 ;
  wire \cal_DQ[20]_i_1_n_0 ;
  wire \cal_DQ[210]_i_1_n_0 ;
  wire \cal_DQ[211]_i_1_n_0 ;
  wire \cal_DQ[212]_i_1_n_0 ;
  wire \cal_DQ[213]_i_1_n_0 ;
  wire \cal_DQ[214]_i_1_n_0 ;
  wire \cal_DQ[215]_i_1_n_0 ;
  wire \cal_DQ[216]_i_1_n_0 ;
  wire \cal_DQ[217]_i_1_n_0 ;
  wire \cal_DQ[218]_i_1_n_0 ;
  wire \cal_DQ[219]_i_1_n_0 ;
  wire \cal_DQ[21]_i_1_n_0 ;
  wire \cal_DQ[220]_i_1_n_0 ;
  wire \cal_DQ[221]_i_1_n_0 ;
  wire \cal_DQ[222]_i_1_n_0 ;
  wire \cal_DQ[223]_i_1_n_0 ;
  wire \cal_DQ[224]_i_1_n_0 ;
  wire \cal_DQ[225]_i_1_n_0 ;
  wire \cal_DQ[226]_i_1_n_0 ;
  wire \cal_DQ[227]_i_1_n_0 ;
  wire \cal_DQ[228]_i_1_n_0 ;
  wire \cal_DQ[229]_i_1_n_0 ;
  wire \cal_DQ[22]_i_1_n_0 ;
  wire \cal_DQ[230]_i_1_n_0 ;
  wire \cal_DQ[231]_i_1_n_0 ;
  wire \cal_DQ[232]_i_1_n_0 ;
  wire \cal_DQ[233]_i_1_n_0 ;
  wire \cal_DQ[234]_i_1_n_0 ;
  wire \cal_DQ[235]_i_1_n_0 ;
  wire \cal_DQ[236]_i_1_n_0 ;
  wire \cal_DQ[237]_i_1_n_0 ;
  wire \cal_DQ[238]_i_1_n_0 ;
  wire \cal_DQ[239]_i_1_n_0 ;
  wire \cal_DQ[23]_i_1_n_0 ;
  wire \cal_DQ[240]_i_1_n_0 ;
  wire \cal_DQ[241]_i_1_n_0 ;
  wire \cal_DQ[242]_i_1_n_0 ;
  wire \cal_DQ[243]_i_1_n_0 ;
  wire \cal_DQ[244]_i_1_n_0 ;
  wire \cal_DQ[245]_i_1_n_0 ;
  wire \cal_DQ[246]_i_1_n_0 ;
  wire \cal_DQ[247]_i_1_n_0 ;
  wire \cal_DQ[248]_i_1_n_0 ;
  wire \cal_DQ[249]_i_1_n_0 ;
  wire \cal_DQ[24]_i_1_n_0 ;
  wire \cal_DQ[250]_i_1_n_0 ;
  wire \cal_DQ[251]_i_1_n_0 ;
  wire \cal_DQ[252]_i_1_n_0 ;
  wire \cal_DQ[253]_i_1_n_0 ;
  wire \cal_DQ[254]_i_1_n_0 ;
  wire \cal_DQ[255]_i_1_n_0 ;
  wire \cal_DQ[255]_i_2_n_0 ;
  wire \cal_DQ[255]_i_3_n_0 ;
  wire \cal_DQ[256]_i_1_n_0 ;
  wire \cal_DQ[257]_i_1_n_0 ;
  wire \cal_DQ[258]_i_1_n_0 ;
  wire \cal_DQ[259]_i_1_n_0 ;
  wire \cal_DQ[25]_i_1_n_0 ;
  wire \cal_DQ[260]_i_1_n_0 ;
  wire \cal_DQ[261]_i_1_n_0 ;
  wire \cal_DQ[262]_i_1_n_0 ;
  wire \cal_DQ[263]_i_1_n_0 ;
  wire \cal_DQ[264]_i_1_n_0 ;
  wire \cal_DQ[265]_i_1_n_0 ;
  wire \cal_DQ[266]_i_1_n_0 ;
  wire \cal_DQ[267]_i_1_n_0 ;
  wire \cal_DQ[268]_i_1_n_0 ;
  wire \cal_DQ[269]_i_1_n_0 ;
  wire \cal_DQ[26]_i_1_n_0 ;
  wire \cal_DQ[270]_i_1_n_0 ;
  wire \cal_DQ[271]_i_1_n_0 ;
  wire \cal_DQ[272]_i_1_n_0 ;
  wire \cal_DQ[273]_i_1_n_0 ;
  wire \cal_DQ[274]_i_1_n_0 ;
  wire \cal_DQ[275]_i_1_n_0 ;
  wire \cal_DQ[276]_i_1_n_0 ;
  wire \cal_DQ[277]_i_1_n_0 ;
  wire \cal_DQ[278]_i_1_n_0 ;
  wire \cal_DQ[279]_i_1_n_0 ;
  wire \cal_DQ[27]_i_1_n_0 ;
  wire \cal_DQ[280]_i_1_n_0 ;
  wire \cal_DQ[281]_i_1_n_0 ;
  wire \cal_DQ[282]_i_1_n_0 ;
  wire \cal_DQ[283]_i_1_n_0 ;
  wire \cal_DQ[284]_i_1_n_0 ;
  wire \cal_DQ[285]_i_1_n_0 ;
  wire \cal_DQ[286]_i_1_n_0 ;
  wire \cal_DQ[287]_i_1_n_0 ;
  wire \cal_DQ[288]_i_1_n_0 ;
  wire \cal_DQ[289]_i_1_n_0 ;
  wire \cal_DQ[28]_i_1_n_0 ;
  wire \cal_DQ[290]_i_1_n_0 ;
  wire \cal_DQ[291]_i_1_n_0 ;
  wire \cal_DQ[292]_i_1_n_0 ;
  wire \cal_DQ[293]_i_1_n_0 ;
  wire \cal_DQ[294]_i_1_n_0 ;
  wire \cal_DQ[295]_i_1_n_0 ;
  wire \cal_DQ[296]_i_1_n_0 ;
  wire \cal_DQ[297]_i_1_n_0 ;
  wire \cal_DQ[298]_i_1_n_0 ;
  wire \cal_DQ[299]_i_1_n_0 ;
  wire \cal_DQ[29]_i_1_n_0 ;
  wire \cal_DQ[2]_i_1_n_0 ;
  wire \cal_DQ[300]_i_1_n_0 ;
  wire \cal_DQ[301]_i_1_n_0 ;
  wire \cal_DQ[302]_i_1_n_0 ;
  wire \cal_DQ[303]_i_1_n_0 ;
  wire \cal_DQ[304]_i_1_n_0 ;
  wire \cal_DQ[305]_i_1_n_0 ;
  wire \cal_DQ[306]_i_1_n_0 ;
  wire \cal_DQ[307]_i_1_n_0 ;
  wire \cal_DQ[308]_i_1_n_0 ;
  wire \cal_DQ[309]_i_1_n_0 ;
  wire \cal_DQ[30]_i_1_n_0 ;
  wire \cal_DQ[310]_i_1_n_0 ;
  wire \cal_DQ[311]_i_1_n_0 ;
  wire \cal_DQ[312]_i_1_n_0 ;
  wire \cal_DQ[313]_i_1_n_0 ;
  wire \cal_DQ[314]_i_1_n_0 ;
  wire \cal_DQ[315]_i_1_n_0 ;
  wire \cal_DQ[316]_i_1_n_0 ;
  wire \cal_DQ[317]_i_1_n_0 ;
  wire \cal_DQ[318]_i_1_n_0 ;
  wire \cal_DQ[319]_i_1_n_0 ;
  wire \cal_DQ[319]_i_2_n_0 ;
  wire \cal_DQ[319]_i_3_n_0 ;
  wire \cal_DQ[31]_i_1_n_0 ;
  wire \cal_DQ[320]_i_1_n_0 ;
  wire \cal_DQ[321]_i_1_n_0 ;
  wire \cal_DQ[322]_i_1_n_0 ;
  wire \cal_DQ[323]_i_1_n_0 ;
  wire \cal_DQ[324]_i_1_n_0 ;
  wire \cal_DQ[325]_i_1_n_0 ;
  wire \cal_DQ[326]_i_1_n_0 ;
  wire \cal_DQ[327]_i_1_n_0 ;
  wire \cal_DQ[328]_i_1_n_0 ;
  wire \cal_DQ[329]_i_1_n_0 ;
  wire \cal_DQ[32]_i_1_n_0 ;
  wire \cal_DQ[330]_i_1_n_0 ;
  wire \cal_DQ[331]_i_1_n_0 ;
  wire \cal_DQ[332]_i_1_n_0 ;
  wire \cal_DQ[333]_i_1_n_0 ;
  wire \cal_DQ[334]_i_1_n_0 ;
  wire \cal_DQ[335]_i_1_n_0 ;
  wire \cal_DQ[336]_i_1_n_0 ;
  wire \cal_DQ[337]_i_1_n_0 ;
  wire \cal_DQ[338]_i_1_n_0 ;
  wire \cal_DQ[339]_i_1_n_0 ;
  wire \cal_DQ[33]_i_1_n_0 ;
  wire \cal_DQ[340]_i_1_n_0 ;
  wire \cal_DQ[341]_i_1_n_0 ;
  wire \cal_DQ[342]_i_1_n_0 ;
  wire \cal_DQ[343]_i_1_n_0 ;
  wire \cal_DQ[344]_i_1_n_0 ;
  wire \cal_DQ[345]_i_1_n_0 ;
  wire \cal_DQ[346]_i_1_n_0 ;
  wire \cal_DQ[347]_i_1_n_0 ;
  wire \cal_DQ[348]_i_1_n_0 ;
  wire \cal_DQ[349]_i_1_n_0 ;
  wire \cal_DQ[34]_i_1_n_0 ;
  wire \cal_DQ[350]_i_1_n_0 ;
  wire \cal_DQ[351]_i_1_n_0 ;
  wire \cal_DQ[352]_i_1_n_0 ;
  wire \cal_DQ[353]_i_1_n_0 ;
  wire \cal_DQ[354]_i_1_n_0 ;
  wire \cal_DQ[355]_i_1_n_0 ;
  wire \cal_DQ[356]_i_1_n_0 ;
  wire \cal_DQ[357]_i_1_n_0 ;
  wire \cal_DQ[358]_i_1_n_0 ;
  wire \cal_DQ[359]_i_1_n_0 ;
  wire \cal_DQ[35]_i_1_n_0 ;
  wire \cal_DQ[360]_i_1_n_0 ;
  wire \cal_DQ[361]_i_1_n_0 ;
  wire \cal_DQ[362]_i_1_n_0 ;
  wire \cal_DQ[363]_i_1_n_0 ;
  wire \cal_DQ[364]_i_1_n_0 ;
  wire \cal_DQ[365]_i_1_n_0 ;
  wire \cal_DQ[366]_i_1_n_0 ;
  wire \cal_DQ[367]_i_1_n_0 ;
  wire \cal_DQ[368]_i_1_n_0 ;
  wire \cal_DQ[369]_i_1_n_0 ;
  wire \cal_DQ[36]_i_1_n_0 ;
  wire \cal_DQ[370]_i_1_n_0 ;
  wire \cal_DQ[371]_i_1_n_0 ;
  wire \cal_DQ[372]_i_1_n_0 ;
  wire \cal_DQ[373]_i_1_n_0 ;
  wire \cal_DQ[374]_i_1_n_0 ;
  wire \cal_DQ[375]_i_1_n_0 ;
  wire \cal_DQ[376]_i_1_n_0 ;
  wire \cal_DQ[377]_i_1_n_0 ;
  wire \cal_DQ[378]_i_1_n_0 ;
  wire \cal_DQ[379]_i_1_n_0 ;
  wire \cal_DQ[37]_i_1_n_0 ;
  wire \cal_DQ[380]_i_1_n_0 ;
  wire \cal_DQ[381]_i_1_n_0 ;
  wire \cal_DQ[382]_i_1_n_0 ;
  wire \cal_DQ[383]_i_1_n_0 ;
  wire \cal_DQ[383]_i_2_n_0 ;
  wire \cal_DQ[384]_i_1_n_0 ;
  wire \cal_DQ[385]_i_1_n_0 ;
  wire \cal_DQ[386]_i_1_n_0 ;
  wire \cal_DQ[387]_i_1_n_0 ;
  wire \cal_DQ[388]_i_1_n_0 ;
  wire \cal_DQ[389]_i_1_n_0 ;
  wire \cal_DQ[38]_i_1_n_0 ;
  wire \cal_DQ[390]_i_1_n_0 ;
  wire \cal_DQ[391]_i_1_n_0 ;
  wire \cal_DQ[392]_i_1_n_0 ;
  wire \cal_DQ[393]_i_1_n_0 ;
  wire \cal_DQ[394]_i_1_n_0 ;
  wire \cal_DQ[395]_i_1_n_0 ;
  wire \cal_DQ[396]_i_1_n_0 ;
  wire \cal_DQ[397]_i_1_n_0 ;
  wire \cal_DQ[398]_i_1_n_0 ;
  wire \cal_DQ[399]_i_1_n_0 ;
  wire \cal_DQ[39]_i_1_n_0 ;
  wire \cal_DQ[3]_i_1_n_0 ;
  wire \cal_DQ[400]_i_1_n_0 ;
  wire \cal_DQ[401]_i_1_n_0 ;
  wire \cal_DQ[402]_i_1_n_0 ;
  wire \cal_DQ[403]_i_1_n_0 ;
  wire \cal_DQ[404]_i_1_n_0 ;
  wire \cal_DQ[405]_i_1_n_0 ;
  wire \cal_DQ[406]_i_1_n_0 ;
  wire \cal_DQ[407]_i_1_n_0 ;
  wire \cal_DQ[408]_i_1_n_0 ;
  wire \cal_DQ[409]_i_1_n_0 ;
  wire \cal_DQ[40]_i_1_n_0 ;
  wire \cal_DQ[410]_i_1_n_0 ;
  wire \cal_DQ[411]_i_1_n_0 ;
  wire \cal_DQ[412]_i_1_n_0 ;
  wire \cal_DQ[413]_i_1_n_0 ;
  wire \cal_DQ[414]_i_1_n_0 ;
  wire \cal_DQ[415]_i_1_n_0 ;
  wire \cal_DQ[416]_i_1_n_0 ;
  wire \cal_DQ[417]_i_1_n_0 ;
  wire \cal_DQ[418]_i_1_n_0 ;
  wire \cal_DQ[419]_i_1_n_0 ;
  wire \cal_DQ[41]_i_1_n_0 ;
  wire \cal_DQ[420]_i_1_n_0 ;
  wire \cal_DQ[421]_i_1_n_0 ;
  wire \cal_DQ[422]_i_1_n_0 ;
  wire \cal_DQ[423]_i_1_n_0 ;
  wire \cal_DQ[424]_i_1_n_0 ;
  wire \cal_DQ[425]_i_1_n_0 ;
  wire \cal_DQ[426]_i_1_n_0 ;
  wire \cal_DQ[427]_i_1_n_0 ;
  wire \cal_DQ[428]_i_1_n_0 ;
  wire \cal_DQ[429]_i_1_n_0 ;
  wire \cal_DQ[42]_i_1_n_0 ;
  wire \cal_DQ[430]_i_1_n_0 ;
  wire \cal_DQ[431]_i_1_n_0 ;
  wire \cal_DQ[432]_i_1_n_0 ;
  wire \cal_DQ[433]_i_1_n_0 ;
  wire \cal_DQ[434]_i_1_n_0 ;
  wire \cal_DQ[435]_i_1_n_0 ;
  wire \cal_DQ[436]_i_1_n_0 ;
  wire \cal_DQ[437]_i_1_n_0 ;
  wire \cal_DQ[438]_i_1_n_0 ;
  wire \cal_DQ[439]_i_1_n_0 ;
  wire \cal_DQ[43]_i_1_n_0 ;
  wire \cal_DQ[440]_i_1_n_0 ;
  wire \cal_DQ[441]_i_1_n_0 ;
  wire \cal_DQ[442]_i_1_n_0 ;
  wire \cal_DQ[443]_i_1_n_0 ;
  wire \cal_DQ[444]_i_1_n_0 ;
  wire \cal_DQ[445]_i_1_n_0 ;
  wire \cal_DQ[446]_i_1_n_0 ;
  wire \cal_DQ[447]_i_1_n_0 ;
  wire \cal_DQ[447]_i_2_n_0 ;
  wire \cal_DQ[447]_i_3_n_0 ;
  wire \cal_DQ[448]_i_1_n_0 ;
  wire \cal_DQ[448]_i_2_n_0 ;
  wire \cal_DQ[448]_i_3_n_0 ;
  wire \cal_DQ[449]_i_1_n_0 ;
  wire \cal_DQ[449]_i_2_n_0 ;
  wire \cal_DQ[449]_i_3_n_0 ;
  wire \cal_DQ[44]_i_1_n_0 ;
  wire \cal_DQ[450]_i_1_n_0 ;
  wire \cal_DQ[450]_i_2_n_0 ;
  wire \cal_DQ[450]_i_3_n_0 ;
  wire \cal_DQ[451]_i_1_n_0 ;
  wire \cal_DQ[451]_i_2_n_0 ;
  wire \cal_DQ[451]_i_3_n_0 ;
  wire \cal_DQ[452]_i_1_n_0 ;
  wire \cal_DQ[452]_i_2_n_0 ;
  wire \cal_DQ[452]_i_3_n_0 ;
  wire \cal_DQ[453]_i_1_n_0 ;
  wire \cal_DQ[453]_i_2_n_0 ;
  wire \cal_DQ[453]_i_3_n_0 ;
  wire \cal_DQ[454]_i_1_n_0 ;
  wire \cal_DQ[454]_i_2_n_0 ;
  wire \cal_DQ[454]_i_3_n_0 ;
  wire \cal_DQ[455]_i_1_n_0 ;
  wire \cal_DQ[455]_i_2_n_0 ;
  wire \cal_DQ[455]_i_3_n_0 ;
  wire \cal_DQ[456]_i_1_n_0 ;
  wire \cal_DQ[456]_i_2_n_0 ;
  wire \cal_DQ[456]_i_3_n_0 ;
  wire \cal_DQ[457]_i_1_n_0 ;
  wire \cal_DQ[457]_i_2_n_0 ;
  wire \cal_DQ[457]_i_3_n_0 ;
  wire \cal_DQ[458]_i_1_n_0 ;
  wire \cal_DQ[458]_i_2_n_0 ;
  wire \cal_DQ[458]_i_3_n_0 ;
  wire \cal_DQ[459]_i_1_n_0 ;
  wire \cal_DQ[459]_i_2_n_0 ;
  wire \cal_DQ[459]_i_3_n_0 ;
  wire \cal_DQ[45]_i_1_n_0 ;
  wire \cal_DQ[460]_i_1_n_0 ;
  wire \cal_DQ[460]_i_2_n_0 ;
  wire \cal_DQ[460]_i_3_n_0 ;
  wire \cal_DQ[461]_i_1_n_0 ;
  wire \cal_DQ[461]_i_2_n_0 ;
  wire \cal_DQ[461]_i_3_n_0 ;
  wire \cal_DQ[462]_i_1_n_0 ;
  wire \cal_DQ[462]_i_2_n_0 ;
  wire \cal_DQ[462]_i_3_n_0 ;
  wire \cal_DQ[463]_i_1_n_0 ;
  wire \cal_DQ[463]_i_2_n_0 ;
  wire \cal_DQ[463]_i_3_n_0 ;
  wire \cal_DQ[464]_i_1_n_0 ;
  wire \cal_DQ[464]_i_2_n_0 ;
  wire \cal_DQ[464]_i_3_n_0 ;
  wire \cal_DQ[465]_i_1_n_0 ;
  wire \cal_DQ[465]_i_2_n_0 ;
  wire \cal_DQ[465]_i_3_n_0 ;
  wire \cal_DQ[466]_i_1_n_0 ;
  wire \cal_DQ[466]_i_2_n_0 ;
  wire \cal_DQ[466]_i_3_n_0 ;
  wire \cal_DQ[467]_i_1_n_0 ;
  wire \cal_DQ[467]_i_2_n_0 ;
  wire \cal_DQ[467]_i_3_n_0 ;
  wire \cal_DQ[468]_i_1_n_0 ;
  wire \cal_DQ[468]_i_2_n_0 ;
  wire \cal_DQ[468]_i_3_n_0 ;
  wire \cal_DQ[469]_i_1_n_0 ;
  wire \cal_DQ[469]_i_2_n_0 ;
  wire \cal_DQ[469]_i_3_n_0 ;
  wire \cal_DQ[46]_i_1_n_0 ;
  wire \cal_DQ[470]_i_1_n_0 ;
  wire \cal_DQ[470]_i_2_n_0 ;
  wire \cal_DQ[470]_i_3_n_0 ;
  wire \cal_DQ[471]_i_1_n_0 ;
  wire \cal_DQ[471]_i_2_n_0 ;
  wire \cal_DQ[471]_i_3_n_0 ;
  wire \cal_DQ[472]_i_1_n_0 ;
  wire \cal_DQ[472]_i_2_n_0 ;
  wire \cal_DQ[472]_i_3_n_0 ;
  wire \cal_DQ[473]_i_1_n_0 ;
  wire \cal_DQ[473]_i_2_n_0 ;
  wire \cal_DQ[473]_i_3_n_0 ;
  wire \cal_DQ[474]_i_1_n_0 ;
  wire \cal_DQ[474]_i_2_n_0 ;
  wire \cal_DQ[474]_i_3_n_0 ;
  wire \cal_DQ[475]_i_1_n_0 ;
  wire \cal_DQ[475]_i_2_n_0 ;
  wire \cal_DQ[475]_i_3_n_0 ;
  wire \cal_DQ[476]_i_1_n_0 ;
  wire \cal_DQ[476]_i_2_n_0 ;
  wire \cal_DQ[476]_i_3_n_0 ;
  wire \cal_DQ[477]_i_1_n_0 ;
  wire \cal_DQ[477]_i_2_n_0 ;
  wire \cal_DQ[477]_i_3_n_0 ;
  wire \cal_DQ[478]_i_1_n_0 ;
  wire \cal_DQ[478]_i_2_n_0 ;
  wire \cal_DQ[478]_i_3_n_0 ;
  wire \cal_DQ[479]_i_1_n_0 ;
  wire \cal_DQ[479]_i_2_n_0 ;
  wire \cal_DQ[479]_i_3_n_0 ;
  wire \cal_DQ[47]_i_1_n_0 ;
  wire \cal_DQ[480]_i_1_n_0 ;
  wire \cal_DQ[480]_i_2_n_0 ;
  wire \cal_DQ[480]_i_3_n_0 ;
  wire \cal_DQ[481]_i_1_n_0 ;
  wire \cal_DQ[481]_i_2_n_0 ;
  wire \cal_DQ[481]_i_3_n_0 ;
  wire \cal_DQ[482]_i_1_n_0 ;
  wire \cal_DQ[482]_i_2_n_0 ;
  wire \cal_DQ[482]_i_3_n_0 ;
  wire \cal_DQ[483]_i_1_n_0 ;
  wire \cal_DQ[483]_i_2_n_0 ;
  wire \cal_DQ[483]_i_3_n_0 ;
  wire \cal_DQ[484]_i_1_n_0 ;
  wire \cal_DQ[484]_i_2_n_0 ;
  wire \cal_DQ[484]_i_3_n_0 ;
  wire \cal_DQ[485]_i_1_n_0 ;
  wire \cal_DQ[485]_i_2_n_0 ;
  wire \cal_DQ[485]_i_3_n_0 ;
  wire \cal_DQ[486]_i_1_n_0 ;
  wire \cal_DQ[486]_i_2_n_0 ;
  wire \cal_DQ[486]_i_3_n_0 ;
  wire \cal_DQ[487]_i_1_n_0 ;
  wire \cal_DQ[487]_i_2_n_0 ;
  wire \cal_DQ[487]_i_3_n_0 ;
  wire \cal_DQ[488]_i_1_n_0 ;
  wire \cal_DQ[488]_i_2_n_0 ;
  wire \cal_DQ[488]_i_3_n_0 ;
  wire \cal_DQ[489]_i_1_n_0 ;
  wire \cal_DQ[489]_i_2_n_0 ;
  wire \cal_DQ[489]_i_3_n_0 ;
  wire \cal_DQ[48]_i_1_n_0 ;
  wire \cal_DQ[490]_i_1_n_0 ;
  wire \cal_DQ[490]_i_2_n_0 ;
  wire \cal_DQ[490]_i_3_n_0 ;
  wire \cal_DQ[491]_i_1_n_0 ;
  wire \cal_DQ[491]_i_2_n_0 ;
  wire \cal_DQ[491]_i_3_n_0 ;
  wire \cal_DQ[492]_i_1_n_0 ;
  wire \cal_DQ[492]_i_2_n_0 ;
  wire \cal_DQ[492]_i_3_n_0 ;
  wire \cal_DQ[493]_i_1_n_0 ;
  wire \cal_DQ[493]_i_2_n_0 ;
  wire \cal_DQ[493]_i_3_n_0 ;
  wire \cal_DQ[494]_i_1_n_0 ;
  wire \cal_DQ[494]_i_2_n_0 ;
  wire \cal_DQ[494]_i_3_n_0 ;
  wire \cal_DQ[495]_i_1_n_0 ;
  wire \cal_DQ[495]_i_2_n_0 ;
  wire \cal_DQ[495]_i_3_n_0 ;
  wire \cal_DQ[496]_i_1_n_0 ;
  wire \cal_DQ[496]_i_2_n_0 ;
  wire \cal_DQ[496]_i_3_n_0 ;
  wire \cal_DQ[497]_i_1_n_0 ;
  wire \cal_DQ[497]_i_2_n_0 ;
  wire \cal_DQ[497]_i_3_n_0 ;
  wire \cal_DQ[498]_i_1_n_0 ;
  wire \cal_DQ[498]_i_2_n_0 ;
  wire \cal_DQ[498]_i_3_n_0 ;
  wire \cal_DQ[499]_i_1_n_0 ;
  wire \cal_DQ[499]_i_2_n_0 ;
  wire \cal_DQ[499]_i_3_n_0 ;
  wire \cal_DQ[49]_i_1_n_0 ;
  wire \cal_DQ[4]_i_1_n_0 ;
  wire \cal_DQ[500]_i_1_n_0 ;
  wire \cal_DQ[500]_i_2_n_0 ;
  wire \cal_DQ[500]_i_3_n_0 ;
  wire \cal_DQ[501]_i_1_n_0 ;
  wire \cal_DQ[501]_i_2_n_0 ;
  wire \cal_DQ[501]_i_3_n_0 ;
  wire \cal_DQ[502]_i_1_n_0 ;
  wire \cal_DQ[502]_i_2_n_0 ;
  wire \cal_DQ[502]_i_3_n_0 ;
  wire \cal_DQ[503]_i_1_n_0 ;
  wire \cal_DQ[503]_i_2_n_0 ;
  wire \cal_DQ[503]_i_3_n_0 ;
  wire \cal_DQ[504]_i_1_n_0 ;
  wire \cal_DQ[504]_i_2_n_0 ;
  wire \cal_DQ[504]_i_3_n_0 ;
  wire \cal_DQ[505]_i_1_n_0 ;
  wire \cal_DQ[505]_i_2_n_0 ;
  wire \cal_DQ[505]_i_3_n_0 ;
  wire \cal_DQ[506]_i_1_n_0 ;
  wire \cal_DQ[506]_i_2_n_0 ;
  wire \cal_DQ[506]_i_3_n_0 ;
  wire \cal_DQ[507]_i_1_n_0 ;
  wire \cal_DQ[507]_i_2_n_0 ;
  wire \cal_DQ[507]_i_3_n_0 ;
  wire \cal_DQ[508]_i_1_n_0 ;
  wire \cal_DQ[508]_i_2_n_0 ;
  wire \cal_DQ[508]_i_3_n_0 ;
  wire \cal_DQ[509]_i_1_n_0 ;
  wire \cal_DQ[509]_i_2_n_0 ;
  wire \cal_DQ[509]_i_3_n_0 ;
  wire \cal_DQ[50]_i_1_n_0 ;
  wire \cal_DQ[510]_i_1_n_0 ;
  wire \cal_DQ[510]_i_2_n_0 ;
  wire \cal_DQ[510]_i_3_n_0 ;
  wire \cal_DQ[511]_i_1_n_0 ;
  wire \cal_DQ[511]_i_2_n_0 ;
  wire \cal_DQ[511]_i_3_n_0 ;
  wire \cal_DQ[511]_i_4_n_0 ;
  wire \cal_DQ[511]_i_5_n_0 ;
  wire \cal_DQ[511]_i_6_n_0 ;
  wire \cal_DQ[51]_i_1_n_0 ;
  wire \cal_DQ[52]_i_1_n_0 ;
  wire \cal_DQ[53]_i_1_n_0 ;
  wire \cal_DQ[54]_i_1_n_0 ;
  wire \cal_DQ[55]_i_1_n_0 ;
  wire \cal_DQ[56]_i_1_n_0 ;
  wire \cal_DQ[57]_i_1_n_0 ;
  wire \cal_DQ[58]_i_1_n_0 ;
  wire \cal_DQ[59]_i_1_n_0 ;
  wire \cal_DQ[5]_i_1_n_0 ;
  wire \cal_DQ[60]_i_1_n_0 ;
  wire \cal_DQ[61]_i_1_n_0 ;
  wire \cal_DQ[62]_i_1_n_0 ;
  wire \cal_DQ[63]_i_1_n_0 ;
  wire \cal_DQ[63]_i_2_n_0 ;
  wire \cal_DQ[64]_i_1_n_0 ;
  wire \cal_DQ[65]_i_1_n_0 ;
  wire \cal_DQ[66]_i_1_n_0 ;
  wire \cal_DQ[67]_i_1_n_0 ;
  wire \cal_DQ[68]_i_1_n_0 ;
  wire \cal_DQ[69]_i_1_n_0 ;
  wire \cal_DQ[6]_i_1_n_0 ;
  wire \cal_DQ[70]_i_1_n_0 ;
  wire \cal_DQ[71]_i_1_n_0 ;
  wire \cal_DQ[72]_i_1_n_0 ;
  wire \cal_DQ[73]_i_1_n_0 ;
  wire \cal_DQ[74]_i_1_n_0 ;
  wire \cal_DQ[75]_i_1_n_0 ;
  wire \cal_DQ[76]_i_1_n_0 ;
  wire \cal_DQ[77]_i_1_n_0 ;
  wire \cal_DQ[78]_i_1_n_0 ;
  wire \cal_DQ[79]_i_1_n_0 ;
  wire \cal_DQ[7]_i_1_n_0 ;
  wire \cal_DQ[80]_i_1_n_0 ;
  wire \cal_DQ[81]_i_1_n_0 ;
  wire \cal_DQ[82]_i_1_n_0 ;
  wire \cal_DQ[83]_i_1_n_0 ;
  wire \cal_DQ[84]_i_1_n_0 ;
  wire \cal_DQ[85]_i_1_n_0 ;
  wire \cal_DQ[86]_i_1_n_0 ;
  wire \cal_DQ[87]_i_1_n_0 ;
  wire \cal_DQ[88]_i_1_n_0 ;
  wire \cal_DQ[89]_i_1_n_0 ;
  wire \cal_DQ[8]_i_1_n_0 ;
  wire \cal_DQ[90]_i_1_n_0 ;
  wire \cal_DQ[91]_i_1_n_0 ;
  wire \cal_DQ[92]_i_1_n_0 ;
  wire \cal_DQ[93]_i_1_n_0 ;
  wire \cal_DQ[94]_i_1_n_0 ;
  wire \cal_DQ[95]_i_1_n_0 ;
  wire \cal_DQ[96]_i_1_n_0 ;
  wire \cal_DQ[97]_i_1_n_0 ;
  wire \cal_DQ[98]_i_1_n_0 ;
  wire \cal_DQ[99]_i_1_n_0 ;
  wire \cal_DQ[9]_i_1_n_0 ;
  wire \cal_DQ_reg_n_0_[0] ;
  wire \cal_DQ_reg_n_0_[100] ;
  wire \cal_DQ_reg_n_0_[101] ;
  wire \cal_DQ_reg_n_0_[102] ;
  wire \cal_DQ_reg_n_0_[103] ;
  wire \cal_DQ_reg_n_0_[104] ;
  wire \cal_DQ_reg_n_0_[105] ;
  wire \cal_DQ_reg_n_0_[106] ;
  wire \cal_DQ_reg_n_0_[107] ;
  wire \cal_DQ_reg_n_0_[108] ;
  wire \cal_DQ_reg_n_0_[109] ;
  wire \cal_DQ_reg_n_0_[10] ;
  wire \cal_DQ_reg_n_0_[110] ;
  wire \cal_DQ_reg_n_0_[111] ;
  wire \cal_DQ_reg_n_0_[112] ;
  wire \cal_DQ_reg_n_0_[113] ;
  wire \cal_DQ_reg_n_0_[114] ;
  wire \cal_DQ_reg_n_0_[115] ;
  wire \cal_DQ_reg_n_0_[116] ;
  wire \cal_DQ_reg_n_0_[117] ;
  wire \cal_DQ_reg_n_0_[118] ;
  wire \cal_DQ_reg_n_0_[119] ;
  wire \cal_DQ_reg_n_0_[11] ;
  wire \cal_DQ_reg_n_0_[120] ;
  wire \cal_DQ_reg_n_0_[121] ;
  wire \cal_DQ_reg_n_0_[122] ;
  wire \cal_DQ_reg_n_0_[123] ;
  wire \cal_DQ_reg_n_0_[124] ;
  wire \cal_DQ_reg_n_0_[125] ;
  wire \cal_DQ_reg_n_0_[126] ;
  wire \cal_DQ_reg_n_0_[127] ;
  wire \cal_DQ_reg_n_0_[128] ;
  wire \cal_DQ_reg_n_0_[129] ;
  wire \cal_DQ_reg_n_0_[12] ;
  wire \cal_DQ_reg_n_0_[130] ;
  wire \cal_DQ_reg_n_0_[131] ;
  wire \cal_DQ_reg_n_0_[132] ;
  wire \cal_DQ_reg_n_0_[133] ;
  wire \cal_DQ_reg_n_0_[134] ;
  wire \cal_DQ_reg_n_0_[135] ;
  wire \cal_DQ_reg_n_0_[136] ;
  wire \cal_DQ_reg_n_0_[137] ;
  wire \cal_DQ_reg_n_0_[138] ;
  wire \cal_DQ_reg_n_0_[139] ;
  wire \cal_DQ_reg_n_0_[13] ;
  wire \cal_DQ_reg_n_0_[140] ;
  wire \cal_DQ_reg_n_0_[141] ;
  wire \cal_DQ_reg_n_0_[142] ;
  wire \cal_DQ_reg_n_0_[143] ;
  wire \cal_DQ_reg_n_0_[144] ;
  wire \cal_DQ_reg_n_0_[145] ;
  wire \cal_DQ_reg_n_0_[146] ;
  wire \cal_DQ_reg_n_0_[147] ;
  wire \cal_DQ_reg_n_0_[148] ;
  wire \cal_DQ_reg_n_0_[149] ;
  wire \cal_DQ_reg_n_0_[14] ;
  wire \cal_DQ_reg_n_0_[150] ;
  wire \cal_DQ_reg_n_0_[151] ;
  wire \cal_DQ_reg_n_0_[152] ;
  wire \cal_DQ_reg_n_0_[153] ;
  wire \cal_DQ_reg_n_0_[154] ;
  wire \cal_DQ_reg_n_0_[155] ;
  wire \cal_DQ_reg_n_0_[156] ;
  wire \cal_DQ_reg_n_0_[157] ;
  wire \cal_DQ_reg_n_0_[158] ;
  wire \cal_DQ_reg_n_0_[159] ;
  wire \cal_DQ_reg_n_0_[15] ;
  wire \cal_DQ_reg_n_0_[160] ;
  wire \cal_DQ_reg_n_0_[161] ;
  wire \cal_DQ_reg_n_0_[162] ;
  wire \cal_DQ_reg_n_0_[163] ;
  wire \cal_DQ_reg_n_0_[164] ;
  wire \cal_DQ_reg_n_0_[165] ;
  wire \cal_DQ_reg_n_0_[166] ;
  wire \cal_DQ_reg_n_0_[167] ;
  wire \cal_DQ_reg_n_0_[168] ;
  wire \cal_DQ_reg_n_0_[169] ;
  wire \cal_DQ_reg_n_0_[16] ;
  wire \cal_DQ_reg_n_0_[170] ;
  wire \cal_DQ_reg_n_0_[171] ;
  wire \cal_DQ_reg_n_0_[172] ;
  wire \cal_DQ_reg_n_0_[173] ;
  wire \cal_DQ_reg_n_0_[174] ;
  wire \cal_DQ_reg_n_0_[175] ;
  wire \cal_DQ_reg_n_0_[176] ;
  wire \cal_DQ_reg_n_0_[177] ;
  wire \cal_DQ_reg_n_0_[178] ;
  wire \cal_DQ_reg_n_0_[179] ;
  wire \cal_DQ_reg_n_0_[17] ;
  wire \cal_DQ_reg_n_0_[180] ;
  wire \cal_DQ_reg_n_0_[181] ;
  wire \cal_DQ_reg_n_0_[182] ;
  wire \cal_DQ_reg_n_0_[183] ;
  wire \cal_DQ_reg_n_0_[184] ;
  wire \cal_DQ_reg_n_0_[185] ;
  wire \cal_DQ_reg_n_0_[186] ;
  wire \cal_DQ_reg_n_0_[187] ;
  wire \cal_DQ_reg_n_0_[188] ;
  wire \cal_DQ_reg_n_0_[189] ;
  wire \cal_DQ_reg_n_0_[18] ;
  wire \cal_DQ_reg_n_0_[190] ;
  wire \cal_DQ_reg_n_0_[191] ;
  wire \cal_DQ_reg_n_0_[192] ;
  wire \cal_DQ_reg_n_0_[193] ;
  wire \cal_DQ_reg_n_0_[194] ;
  wire \cal_DQ_reg_n_0_[195] ;
  wire \cal_DQ_reg_n_0_[196] ;
  wire \cal_DQ_reg_n_0_[197] ;
  wire \cal_DQ_reg_n_0_[198] ;
  wire \cal_DQ_reg_n_0_[199] ;
  wire \cal_DQ_reg_n_0_[19] ;
  wire \cal_DQ_reg_n_0_[1] ;
  wire \cal_DQ_reg_n_0_[200] ;
  wire \cal_DQ_reg_n_0_[201] ;
  wire \cal_DQ_reg_n_0_[202] ;
  wire \cal_DQ_reg_n_0_[203] ;
  wire \cal_DQ_reg_n_0_[204] ;
  wire \cal_DQ_reg_n_0_[205] ;
  wire \cal_DQ_reg_n_0_[206] ;
  wire \cal_DQ_reg_n_0_[207] ;
  wire \cal_DQ_reg_n_0_[208] ;
  wire \cal_DQ_reg_n_0_[209] ;
  wire \cal_DQ_reg_n_0_[20] ;
  wire \cal_DQ_reg_n_0_[210] ;
  wire \cal_DQ_reg_n_0_[211] ;
  wire \cal_DQ_reg_n_0_[212] ;
  wire \cal_DQ_reg_n_0_[213] ;
  wire \cal_DQ_reg_n_0_[214] ;
  wire \cal_DQ_reg_n_0_[215] ;
  wire \cal_DQ_reg_n_0_[216] ;
  wire \cal_DQ_reg_n_0_[217] ;
  wire \cal_DQ_reg_n_0_[218] ;
  wire \cal_DQ_reg_n_0_[219] ;
  wire \cal_DQ_reg_n_0_[21] ;
  wire \cal_DQ_reg_n_0_[220] ;
  wire \cal_DQ_reg_n_0_[221] ;
  wire \cal_DQ_reg_n_0_[222] ;
  wire \cal_DQ_reg_n_0_[223] ;
  wire \cal_DQ_reg_n_0_[224] ;
  wire \cal_DQ_reg_n_0_[225] ;
  wire \cal_DQ_reg_n_0_[226] ;
  wire \cal_DQ_reg_n_0_[227] ;
  wire \cal_DQ_reg_n_0_[228] ;
  wire \cal_DQ_reg_n_0_[229] ;
  wire \cal_DQ_reg_n_0_[22] ;
  wire \cal_DQ_reg_n_0_[230] ;
  wire \cal_DQ_reg_n_0_[231] ;
  wire \cal_DQ_reg_n_0_[232] ;
  wire \cal_DQ_reg_n_0_[233] ;
  wire \cal_DQ_reg_n_0_[234] ;
  wire \cal_DQ_reg_n_0_[235] ;
  wire \cal_DQ_reg_n_0_[236] ;
  wire \cal_DQ_reg_n_0_[237] ;
  wire \cal_DQ_reg_n_0_[238] ;
  wire \cal_DQ_reg_n_0_[239] ;
  wire \cal_DQ_reg_n_0_[23] ;
  wire \cal_DQ_reg_n_0_[240] ;
  wire \cal_DQ_reg_n_0_[241] ;
  wire \cal_DQ_reg_n_0_[242] ;
  wire \cal_DQ_reg_n_0_[243] ;
  wire \cal_DQ_reg_n_0_[244] ;
  wire \cal_DQ_reg_n_0_[245] ;
  wire \cal_DQ_reg_n_0_[246] ;
  wire \cal_DQ_reg_n_0_[247] ;
  wire \cal_DQ_reg_n_0_[248] ;
  wire \cal_DQ_reg_n_0_[249] ;
  wire \cal_DQ_reg_n_0_[24] ;
  wire \cal_DQ_reg_n_0_[250] ;
  wire \cal_DQ_reg_n_0_[251] ;
  wire \cal_DQ_reg_n_0_[252] ;
  wire \cal_DQ_reg_n_0_[253] ;
  wire \cal_DQ_reg_n_0_[254] ;
  wire \cal_DQ_reg_n_0_[255] ;
  wire \cal_DQ_reg_n_0_[256] ;
  wire \cal_DQ_reg_n_0_[257] ;
  wire \cal_DQ_reg_n_0_[258] ;
  wire \cal_DQ_reg_n_0_[259] ;
  wire \cal_DQ_reg_n_0_[25] ;
  wire \cal_DQ_reg_n_0_[260] ;
  wire \cal_DQ_reg_n_0_[261] ;
  wire \cal_DQ_reg_n_0_[262] ;
  wire \cal_DQ_reg_n_0_[263] ;
  wire \cal_DQ_reg_n_0_[264] ;
  wire \cal_DQ_reg_n_0_[265] ;
  wire \cal_DQ_reg_n_0_[266] ;
  wire \cal_DQ_reg_n_0_[267] ;
  wire \cal_DQ_reg_n_0_[268] ;
  wire \cal_DQ_reg_n_0_[269] ;
  wire \cal_DQ_reg_n_0_[26] ;
  wire \cal_DQ_reg_n_0_[270] ;
  wire \cal_DQ_reg_n_0_[271] ;
  wire \cal_DQ_reg_n_0_[272] ;
  wire \cal_DQ_reg_n_0_[273] ;
  wire \cal_DQ_reg_n_0_[274] ;
  wire \cal_DQ_reg_n_0_[275] ;
  wire \cal_DQ_reg_n_0_[276] ;
  wire \cal_DQ_reg_n_0_[277] ;
  wire \cal_DQ_reg_n_0_[278] ;
  wire \cal_DQ_reg_n_0_[279] ;
  wire \cal_DQ_reg_n_0_[27] ;
  wire \cal_DQ_reg_n_0_[280] ;
  wire \cal_DQ_reg_n_0_[281] ;
  wire \cal_DQ_reg_n_0_[282] ;
  wire \cal_DQ_reg_n_0_[283] ;
  wire \cal_DQ_reg_n_0_[284] ;
  wire \cal_DQ_reg_n_0_[285] ;
  wire \cal_DQ_reg_n_0_[286] ;
  wire \cal_DQ_reg_n_0_[287] ;
  wire \cal_DQ_reg_n_0_[288] ;
  wire \cal_DQ_reg_n_0_[289] ;
  wire \cal_DQ_reg_n_0_[28] ;
  wire \cal_DQ_reg_n_0_[290] ;
  wire \cal_DQ_reg_n_0_[291] ;
  wire \cal_DQ_reg_n_0_[292] ;
  wire \cal_DQ_reg_n_0_[293] ;
  wire \cal_DQ_reg_n_0_[294] ;
  wire \cal_DQ_reg_n_0_[295] ;
  wire \cal_DQ_reg_n_0_[296] ;
  wire \cal_DQ_reg_n_0_[297] ;
  wire \cal_DQ_reg_n_0_[298] ;
  wire \cal_DQ_reg_n_0_[299] ;
  wire \cal_DQ_reg_n_0_[29] ;
  wire \cal_DQ_reg_n_0_[2] ;
  wire \cal_DQ_reg_n_0_[300] ;
  wire \cal_DQ_reg_n_0_[301] ;
  wire \cal_DQ_reg_n_0_[302] ;
  wire \cal_DQ_reg_n_0_[303] ;
  wire \cal_DQ_reg_n_0_[304] ;
  wire \cal_DQ_reg_n_0_[305] ;
  wire \cal_DQ_reg_n_0_[306] ;
  wire \cal_DQ_reg_n_0_[307] ;
  wire \cal_DQ_reg_n_0_[308] ;
  wire \cal_DQ_reg_n_0_[309] ;
  wire \cal_DQ_reg_n_0_[30] ;
  wire \cal_DQ_reg_n_0_[310] ;
  wire \cal_DQ_reg_n_0_[311] ;
  wire \cal_DQ_reg_n_0_[312] ;
  wire \cal_DQ_reg_n_0_[313] ;
  wire \cal_DQ_reg_n_0_[314] ;
  wire \cal_DQ_reg_n_0_[315] ;
  wire \cal_DQ_reg_n_0_[316] ;
  wire \cal_DQ_reg_n_0_[317] ;
  wire \cal_DQ_reg_n_0_[318] ;
  wire \cal_DQ_reg_n_0_[319] ;
  wire \cal_DQ_reg_n_0_[31] ;
  wire \cal_DQ_reg_n_0_[320] ;
  wire \cal_DQ_reg_n_0_[321] ;
  wire \cal_DQ_reg_n_0_[322] ;
  wire \cal_DQ_reg_n_0_[323] ;
  wire \cal_DQ_reg_n_0_[324] ;
  wire \cal_DQ_reg_n_0_[325] ;
  wire \cal_DQ_reg_n_0_[326] ;
  wire \cal_DQ_reg_n_0_[327] ;
  wire \cal_DQ_reg_n_0_[328] ;
  wire \cal_DQ_reg_n_0_[329] ;
  wire \cal_DQ_reg_n_0_[32] ;
  wire \cal_DQ_reg_n_0_[330] ;
  wire \cal_DQ_reg_n_0_[331] ;
  wire \cal_DQ_reg_n_0_[332] ;
  wire \cal_DQ_reg_n_0_[333] ;
  wire \cal_DQ_reg_n_0_[334] ;
  wire \cal_DQ_reg_n_0_[335] ;
  wire \cal_DQ_reg_n_0_[336] ;
  wire \cal_DQ_reg_n_0_[337] ;
  wire \cal_DQ_reg_n_0_[338] ;
  wire \cal_DQ_reg_n_0_[339] ;
  wire \cal_DQ_reg_n_0_[33] ;
  wire \cal_DQ_reg_n_0_[340] ;
  wire \cal_DQ_reg_n_0_[341] ;
  wire \cal_DQ_reg_n_0_[342] ;
  wire \cal_DQ_reg_n_0_[343] ;
  wire \cal_DQ_reg_n_0_[344] ;
  wire \cal_DQ_reg_n_0_[345] ;
  wire \cal_DQ_reg_n_0_[346] ;
  wire \cal_DQ_reg_n_0_[347] ;
  wire \cal_DQ_reg_n_0_[348] ;
  wire \cal_DQ_reg_n_0_[349] ;
  wire \cal_DQ_reg_n_0_[34] ;
  wire \cal_DQ_reg_n_0_[350] ;
  wire \cal_DQ_reg_n_0_[351] ;
  wire \cal_DQ_reg_n_0_[352] ;
  wire \cal_DQ_reg_n_0_[353] ;
  wire \cal_DQ_reg_n_0_[354] ;
  wire \cal_DQ_reg_n_0_[355] ;
  wire \cal_DQ_reg_n_0_[356] ;
  wire \cal_DQ_reg_n_0_[357] ;
  wire \cal_DQ_reg_n_0_[358] ;
  wire \cal_DQ_reg_n_0_[359] ;
  wire \cal_DQ_reg_n_0_[35] ;
  wire \cal_DQ_reg_n_0_[360] ;
  wire \cal_DQ_reg_n_0_[361] ;
  wire \cal_DQ_reg_n_0_[362] ;
  wire \cal_DQ_reg_n_0_[363] ;
  wire \cal_DQ_reg_n_0_[364] ;
  wire \cal_DQ_reg_n_0_[365] ;
  wire \cal_DQ_reg_n_0_[366] ;
  wire \cal_DQ_reg_n_0_[367] ;
  wire \cal_DQ_reg_n_0_[368] ;
  wire \cal_DQ_reg_n_0_[369] ;
  wire \cal_DQ_reg_n_0_[36] ;
  wire \cal_DQ_reg_n_0_[370] ;
  wire \cal_DQ_reg_n_0_[371] ;
  wire \cal_DQ_reg_n_0_[372] ;
  wire \cal_DQ_reg_n_0_[373] ;
  wire \cal_DQ_reg_n_0_[374] ;
  wire \cal_DQ_reg_n_0_[375] ;
  wire \cal_DQ_reg_n_0_[376] ;
  wire \cal_DQ_reg_n_0_[377] ;
  wire \cal_DQ_reg_n_0_[378] ;
  wire \cal_DQ_reg_n_0_[379] ;
  wire \cal_DQ_reg_n_0_[37] ;
  wire \cal_DQ_reg_n_0_[380] ;
  wire \cal_DQ_reg_n_0_[381] ;
  wire \cal_DQ_reg_n_0_[382] ;
  wire \cal_DQ_reg_n_0_[383] ;
  wire \cal_DQ_reg_n_0_[384] ;
  wire \cal_DQ_reg_n_0_[385] ;
  wire \cal_DQ_reg_n_0_[386] ;
  wire \cal_DQ_reg_n_0_[387] ;
  wire \cal_DQ_reg_n_0_[388] ;
  wire \cal_DQ_reg_n_0_[389] ;
  wire \cal_DQ_reg_n_0_[38] ;
  wire \cal_DQ_reg_n_0_[390] ;
  wire \cal_DQ_reg_n_0_[391] ;
  wire \cal_DQ_reg_n_0_[392] ;
  wire \cal_DQ_reg_n_0_[393] ;
  wire \cal_DQ_reg_n_0_[394] ;
  wire \cal_DQ_reg_n_0_[395] ;
  wire \cal_DQ_reg_n_0_[396] ;
  wire \cal_DQ_reg_n_0_[397] ;
  wire \cal_DQ_reg_n_0_[398] ;
  wire \cal_DQ_reg_n_0_[399] ;
  wire \cal_DQ_reg_n_0_[39] ;
  wire \cal_DQ_reg_n_0_[3] ;
  wire \cal_DQ_reg_n_0_[400] ;
  wire \cal_DQ_reg_n_0_[401] ;
  wire \cal_DQ_reg_n_0_[402] ;
  wire \cal_DQ_reg_n_0_[403] ;
  wire \cal_DQ_reg_n_0_[404] ;
  wire \cal_DQ_reg_n_0_[405] ;
  wire \cal_DQ_reg_n_0_[406] ;
  wire \cal_DQ_reg_n_0_[407] ;
  wire \cal_DQ_reg_n_0_[408] ;
  wire \cal_DQ_reg_n_0_[409] ;
  wire \cal_DQ_reg_n_0_[40] ;
  wire \cal_DQ_reg_n_0_[410] ;
  wire \cal_DQ_reg_n_0_[411] ;
  wire \cal_DQ_reg_n_0_[412] ;
  wire \cal_DQ_reg_n_0_[413] ;
  wire \cal_DQ_reg_n_0_[414] ;
  wire \cal_DQ_reg_n_0_[415] ;
  wire \cal_DQ_reg_n_0_[416] ;
  wire \cal_DQ_reg_n_0_[417] ;
  wire \cal_DQ_reg_n_0_[418] ;
  wire \cal_DQ_reg_n_0_[419] ;
  wire \cal_DQ_reg_n_0_[41] ;
  wire \cal_DQ_reg_n_0_[420] ;
  wire \cal_DQ_reg_n_0_[421] ;
  wire \cal_DQ_reg_n_0_[422] ;
  wire \cal_DQ_reg_n_0_[423] ;
  wire \cal_DQ_reg_n_0_[424] ;
  wire \cal_DQ_reg_n_0_[425] ;
  wire \cal_DQ_reg_n_0_[426] ;
  wire \cal_DQ_reg_n_0_[427] ;
  wire \cal_DQ_reg_n_0_[428] ;
  wire \cal_DQ_reg_n_0_[429] ;
  wire \cal_DQ_reg_n_0_[42] ;
  wire \cal_DQ_reg_n_0_[430] ;
  wire \cal_DQ_reg_n_0_[431] ;
  wire \cal_DQ_reg_n_0_[432] ;
  wire \cal_DQ_reg_n_0_[433] ;
  wire \cal_DQ_reg_n_0_[434] ;
  wire \cal_DQ_reg_n_0_[435] ;
  wire \cal_DQ_reg_n_0_[436] ;
  wire \cal_DQ_reg_n_0_[437] ;
  wire \cal_DQ_reg_n_0_[438] ;
  wire \cal_DQ_reg_n_0_[439] ;
  wire \cal_DQ_reg_n_0_[43] ;
  wire \cal_DQ_reg_n_0_[440] ;
  wire \cal_DQ_reg_n_0_[441] ;
  wire \cal_DQ_reg_n_0_[442] ;
  wire \cal_DQ_reg_n_0_[443] ;
  wire \cal_DQ_reg_n_0_[444] ;
  wire \cal_DQ_reg_n_0_[445] ;
  wire \cal_DQ_reg_n_0_[446] ;
  wire \cal_DQ_reg_n_0_[447] ;
  wire \cal_DQ_reg_n_0_[448] ;
  wire \cal_DQ_reg_n_0_[449] ;
  wire \cal_DQ_reg_n_0_[44] ;
  wire \cal_DQ_reg_n_0_[450] ;
  wire \cal_DQ_reg_n_0_[451] ;
  wire \cal_DQ_reg_n_0_[452] ;
  wire \cal_DQ_reg_n_0_[453] ;
  wire \cal_DQ_reg_n_0_[454] ;
  wire \cal_DQ_reg_n_0_[455] ;
  wire \cal_DQ_reg_n_0_[456] ;
  wire \cal_DQ_reg_n_0_[457] ;
  wire \cal_DQ_reg_n_0_[458] ;
  wire \cal_DQ_reg_n_0_[459] ;
  wire \cal_DQ_reg_n_0_[45] ;
  wire \cal_DQ_reg_n_0_[460] ;
  wire \cal_DQ_reg_n_0_[461] ;
  wire \cal_DQ_reg_n_0_[462] ;
  wire \cal_DQ_reg_n_0_[463] ;
  wire \cal_DQ_reg_n_0_[464] ;
  wire \cal_DQ_reg_n_0_[465] ;
  wire \cal_DQ_reg_n_0_[466] ;
  wire \cal_DQ_reg_n_0_[467] ;
  wire \cal_DQ_reg_n_0_[468] ;
  wire \cal_DQ_reg_n_0_[469] ;
  wire \cal_DQ_reg_n_0_[46] ;
  wire \cal_DQ_reg_n_0_[470] ;
  wire \cal_DQ_reg_n_0_[471] ;
  wire \cal_DQ_reg_n_0_[472] ;
  wire \cal_DQ_reg_n_0_[473] ;
  wire \cal_DQ_reg_n_0_[474] ;
  wire \cal_DQ_reg_n_0_[475] ;
  wire \cal_DQ_reg_n_0_[476] ;
  wire \cal_DQ_reg_n_0_[477] ;
  wire \cal_DQ_reg_n_0_[478] ;
  wire \cal_DQ_reg_n_0_[479] ;
  wire \cal_DQ_reg_n_0_[47] ;
  wire \cal_DQ_reg_n_0_[480] ;
  wire \cal_DQ_reg_n_0_[481] ;
  wire \cal_DQ_reg_n_0_[482] ;
  wire \cal_DQ_reg_n_0_[483] ;
  wire \cal_DQ_reg_n_0_[484] ;
  wire \cal_DQ_reg_n_0_[485] ;
  wire \cal_DQ_reg_n_0_[486] ;
  wire \cal_DQ_reg_n_0_[487] ;
  wire \cal_DQ_reg_n_0_[488] ;
  wire \cal_DQ_reg_n_0_[489] ;
  wire \cal_DQ_reg_n_0_[48] ;
  wire \cal_DQ_reg_n_0_[490] ;
  wire \cal_DQ_reg_n_0_[491] ;
  wire \cal_DQ_reg_n_0_[492] ;
  wire \cal_DQ_reg_n_0_[493] ;
  wire \cal_DQ_reg_n_0_[494] ;
  wire \cal_DQ_reg_n_0_[495] ;
  wire \cal_DQ_reg_n_0_[496] ;
  wire \cal_DQ_reg_n_0_[497] ;
  wire \cal_DQ_reg_n_0_[498] ;
  wire \cal_DQ_reg_n_0_[499] ;
  wire \cal_DQ_reg_n_0_[49] ;
  wire \cal_DQ_reg_n_0_[4] ;
  wire \cal_DQ_reg_n_0_[500] ;
  wire \cal_DQ_reg_n_0_[501] ;
  wire \cal_DQ_reg_n_0_[502] ;
  wire \cal_DQ_reg_n_0_[503] ;
  wire \cal_DQ_reg_n_0_[504] ;
  wire \cal_DQ_reg_n_0_[505] ;
  wire \cal_DQ_reg_n_0_[506] ;
  wire \cal_DQ_reg_n_0_[507] ;
  wire \cal_DQ_reg_n_0_[508] ;
  wire \cal_DQ_reg_n_0_[509] ;
  wire \cal_DQ_reg_n_0_[50] ;
  wire \cal_DQ_reg_n_0_[510] ;
  wire \cal_DQ_reg_n_0_[511] ;
  wire \cal_DQ_reg_n_0_[51] ;
  wire \cal_DQ_reg_n_0_[52] ;
  wire \cal_DQ_reg_n_0_[53] ;
  wire \cal_DQ_reg_n_0_[54] ;
  wire \cal_DQ_reg_n_0_[55] ;
  wire \cal_DQ_reg_n_0_[56] ;
  wire \cal_DQ_reg_n_0_[57] ;
  wire \cal_DQ_reg_n_0_[58] ;
  wire \cal_DQ_reg_n_0_[59] ;
  wire \cal_DQ_reg_n_0_[5] ;
  wire \cal_DQ_reg_n_0_[60] ;
  wire \cal_DQ_reg_n_0_[61] ;
  wire \cal_DQ_reg_n_0_[62] ;
  wire \cal_DQ_reg_n_0_[63] ;
  wire \cal_DQ_reg_n_0_[64] ;
  wire \cal_DQ_reg_n_0_[65] ;
  wire \cal_DQ_reg_n_0_[66] ;
  wire \cal_DQ_reg_n_0_[67] ;
  wire \cal_DQ_reg_n_0_[68] ;
  wire \cal_DQ_reg_n_0_[69] ;
  wire \cal_DQ_reg_n_0_[6] ;
  wire \cal_DQ_reg_n_0_[70] ;
  wire \cal_DQ_reg_n_0_[71] ;
  wire \cal_DQ_reg_n_0_[72] ;
  wire \cal_DQ_reg_n_0_[73] ;
  wire \cal_DQ_reg_n_0_[74] ;
  wire \cal_DQ_reg_n_0_[75] ;
  wire \cal_DQ_reg_n_0_[76] ;
  wire \cal_DQ_reg_n_0_[77] ;
  wire \cal_DQ_reg_n_0_[78] ;
  wire \cal_DQ_reg_n_0_[79] ;
  wire \cal_DQ_reg_n_0_[7] ;
  wire \cal_DQ_reg_n_0_[80] ;
  wire \cal_DQ_reg_n_0_[81] ;
  wire \cal_DQ_reg_n_0_[82] ;
  wire \cal_DQ_reg_n_0_[83] ;
  wire \cal_DQ_reg_n_0_[84] ;
  wire \cal_DQ_reg_n_0_[85] ;
  wire \cal_DQ_reg_n_0_[86] ;
  wire \cal_DQ_reg_n_0_[87] ;
  wire \cal_DQ_reg_n_0_[88] ;
  wire \cal_DQ_reg_n_0_[89] ;
  wire \cal_DQ_reg_n_0_[8] ;
  wire \cal_DQ_reg_n_0_[90] ;
  wire \cal_DQ_reg_n_0_[91] ;
  wire \cal_DQ_reg_n_0_[92] ;
  wire \cal_DQ_reg_n_0_[93] ;
  wire \cal_DQ_reg_n_0_[94] ;
  wire \cal_DQ_reg_n_0_[95] ;
  wire \cal_DQ_reg_n_0_[96] ;
  wire \cal_DQ_reg_n_0_[97] ;
  wire \cal_DQ_reg_n_0_[98] ;
  wire \cal_DQ_reg_n_0_[99] ;
  wire \cal_DQ_reg_n_0_[9] ;
  wire \cal_RAS_A_reg_n_0_[0] ;
  wire \cal_RAS_A_reg_n_0_[1] ;
  wire \cal_RAS_A_reg_n_0_[2] ;
  wire \cal_RAS_A_reg_n_0_[3] ;
  wire \cal_RAS_A_reg_n_0_[4] ;
  wire \cal_RAS_A_reg_n_0_[5] ;
  wire \cal_RAS_A_reg_n_0_[6] ;
  wire \cal_RAS_A_reg_n_0_[7] ;
  wire [7:0]cal_RAS_B;
  wire [0:0]\cal_RAS_B_reg[0]_0 ;
  wire [7:0]cal_RAS_pre;
  wire [7:0]cal_RAS_pre_nxt;
  wire \cal_RAS_pre_reg[1]_0 ;
  wire \cal_RAS_pre_reg[2]_0 ;
  wire [2:0]\cal_RST_CKE_ODT_PAR_reg[16]_0 ;
  wire \cal_RST_CKE_ODT_PAR_reg[16]_1 ;
  wire [10:0]\cal_RST_CKE_ODT_PAR_reg[30]_0 ;
  wire [0:0]\cal_RST_CKE_ODT_PAR_reg[31]_0 ;
  wire [7:0]\cal_RST_CKE_ODT_PAR_reg[7]_0 ;
  wire \cal_RST_CKE_ODT_PAR_reg[9]_0 ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[10] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[11] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[12] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[13] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[15] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[17] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[18] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[19] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[20] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[21] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[22] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[24] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[25] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[26] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[27] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[29] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[31] ;
  wire \cal_RST_CKE_ODT_PAR_reg_n_0_[9] ;
  wire [7:0]cal_WE_A;
  wire [7:0]cal_WE_B;
  wire [7:0]cal_WE_pre;
  wire [7:0]cal_WE_pre_nxt;
  wire cal_clear_fifo_rden;
  wire [0:0]\cal_cmp_en_reg[7]_0 ;
  wire \cal_cmp_en_reg_n_0_[0] ;
  wire \cal_cmp_en_reg_n_0_[1] ;
  wire \cal_cmp_en_reg_n_0_[2] ;
  wire \cal_cmp_en_reg_n_0_[3] ;
  wire \cal_cmp_en_reg_n_0_[4] ;
  wire \cal_cmp_en_reg_n_0_[5] ;
  wire \cal_cmp_en_reg_n_0_[6] ;
  wire \cal_cmp_en_reg_n_0_[7] ;
  wire [0:0]\cal_cs_pos_reg[1]_0 ;
  wire \cal_cs_pos_reg_n_0_[0] ;
  wire \cal_cs_pos_reg_n_0_[1] ;
  wire [0:0]cal_oe_dis_low;
  wire \cal_oe_dis_low_reg[7]_0 ;
  wire [0:0]cal_oe_dis_upp;
  wire \cal_oe_dis_upp_reg[7]_0 ;
  wire [0:0]\cal_seq_a_a_dly_reg[7]_0 ;
  wire \cal_seq_a_a_dly_reg_n_0_[0] ;
  wire \cal_seq_a_a_dly_reg_n_0_[1] ;
  wire \cal_seq_a_a_dly_reg_n_0_[2] ;
  wire \cal_seq_a_a_dly_reg_n_0_[3] ;
  wire \cal_seq_a_a_dly_reg_n_0_[4] ;
  wire \cal_seq_a_a_dly_reg_n_0_[5] ;
  wire \cal_seq_a_a_dly_reg_n_0_[6] ;
  wire \cal_seq_a_a_dly_reg_n_0_[7] ;
  wire [0:0]\cal_seq_a_b_dly_reg[7]_0 ;
  wire \cal_seq_a_b_dly_reg_n_0_[0] ;
  wire \cal_seq_a_b_dly_reg_n_0_[1] ;
  wire \cal_seq_a_b_dly_reg_n_0_[2] ;
  wire \cal_seq_a_b_dly_reg_n_0_[3] ;
  wire \cal_seq_a_b_dly_reg_n_0_[4] ;
  wire \cal_seq_a_b_dly_reg_n_0_[5] ;
  wire \cal_seq_a_b_dly_reg_n_0_[6] ;
  wire \cal_seq_a_b_dly_reg_n_0_[7] ;
  wire [0:0]\cal_seq_b_a_dly_reg[7]_0 ;
  wire \cal_seq_b_a_dly_reg_n_0_[0] ;
  wire \cal_seq_b_a_dly_reg_n_0_[1] ;
  wire \cal_seq_b_a_dly_reg_n_0_[2] ;
  wire \cal_seq_b_a_dly_reg_n_0_[3] ;
  wire \cal_seq_b_a_dly_reg_n_0_[4] ;
  wire \cal_seq_b_a_dly_reg_n_0_[5] ;
  wire \cal_seq_b_a_dly_reg_n_0_[6] ;
  wire \cal_seq_b_a_dly_reg_n_0_[7] ;
  wire cal_seq_cnt0;
  wire [31:1]cal_seq_cnt0__0;
  wire \cal_seq_cnt[0]_i_1_n_0 ;
  wire \cal_seq_cnt[10]_i_1_n_0 ;
  wire \cal_seq_cnt[11]_i_1_n_0 ;
  wire \cal_seq_cnt[12]_i_1_n_0 ;
  wire \cal_seq_cnt[13]_i_1_n_0 ;
  wire \cal_seq_cnt[14]_i_1_n_0 ;
  wire \cal_seq_cnt[15]_i_1_n_0 ;
  wire \cal_seq_cnt[16]_i_10_n_0 ;
  wire \cal_seq_cnt[16]_i_1_n_0 ;
  wire \cal_seq_cnt[16]_i_3_n_0 ;
  wire \cal_seq_cnt[16]_i_4_n_0 ;
  wire \cal_seq_cnt[16]_i_5_n_0 ;
  wire \cal_seq_cnt[16]_i_6_n_0 ;
  wire \cal_seq_cnt[16]_i_7_n_0 ;
  wire \cal_seq_cnt[16]_i_8_n_0 ;
  wire \cal_seq_cnt[16]_i_9_n_0 ;
  wire \cal_seq_cnt[17]_i_1_n_0 ;
  wire \cal_seq_cnt[18]_i_1_n_0 ;
  wire \cal_seq_cnt[19]_i_1_n_0 ;
  wire \cal_seq_cnt[1]_i_1_n_0 ;
  wire \cal_seq_cnt[20]_i_1_n_0 ;
  wire \cal_seq_cnt[21]_i_1_n_0 ;
  wire \cal_seq_cnt[22]_i_1_n_0 ;
  wire \cal_seq_cnt[23]_i_1_n_0 ;
  wire \cal_seq_cnt[24]_i_10_n_0 ;
  wire \cal_seq_cnt[24]_i_1_n_0 ;
  wire \cal_seq_cnt[24]_i_3_n_0 ;
  wire \cal_seq_cnt[24]_i_4_n_0 ;
  wire \cal_seq_cnt[24]_i_5_n_0 ;
  wire \cal_seq_cnt[24]_i_6_n_0 ;
  wire \cal_seq_cnt[24]_i_7_n_0 ;
  wire \cal_seq_cnt[24]_i_8_n_0 ;
  wire \cal_seq_cnt[24]_i_9_n_0 ;
  wire \cal_seq_cnt[25]_i_1_n_0 ;
  wire \cal_seq_cnt[26]_i_1_n_0 ;
  wire \cal_seq_cnt[27]_i_1_n_0 ;
  wire \cal_seq_cnt[28]_i_1_n_0 ;
  wire \cal_seq_cnt[29]_i_1_n_0 ;
  wire \cal_seq_cnt[2]_i_1_n_0 ;
  wire \cal_seq_cnt[30]_i_1_n_0 ;
  wire \cal_seq_cnt[31]_i_10_n_0 ;
  wire \cal_seq_cnt[31]_i_1_n_0 ;
  wire \cal_seq_cnt[31]_i_2_n_0 ;
  wire \cal_seq_cnt[31]_i_4_n_0 ;
  wire \cal_seq_cnt[31]_i_5_n_0 ;
  wire \cal_seq_cnt[31]_i_6_n_0 ;
  wire \cal_seq_cnt[31]_i_7_n_0 ;
  wire \cal_seq_cnt[31]_i_8_n_0 ;
  wire \cal_seq_cnt[31]_i_9_n_0 ;
  wire \cal_seq_cnt[3]_i_1_n_0 ;
  wire \cal_seq_cnt[4]_i_1_n_0 ;
  wire \cal_seq_cnt[5]_i_1_n_0 ;
  wire \cal_seq_cnt[6]_i_1_n_0 ;
  wire \cal_seq_cnt[7]_i_1_n_0 ;
  wire \cal_seq_cnt[8]_i_10_n_0 ;
  wire \cal_seq_cnt[8]_i_1_n_0 ;
  wire \cal_seq_cnt[8]_i_3_n_0 ;
  wire \cal_seq_cnt[8]_i_4_n_0 ;
  wire \cal_seq_cnt[8]_i_5_n_0 ;
  wire \cal_seq_cnt[8]_i_6_n_0 ;
  wire \cal_seq_cnt[8]_i_7_n_0 ;
  wire \cal_seq_cnt[8]_i_8_n_0 ;
  wire \cal_seq_cnt[8]_i_9_n_0 ;
  wire \cal_seq_cnt[9]_i_1_n_0 ;
  wire cal_seq_cnt_gt_0;
  wire cal_seq_cnt_gt_0_i_10_n_0;
  wire cal_seq_cnt_gt_0_i_11_n_0;
  wire cal_seq_cnt_gt_0_i_14_n_0;
  wire cal_seq_cnt_gt_0_i_15_n_0;
  wire cal_seq_cnt_gt_0_i_16_n_0;
  wire cal_seq_cnt_gt_0_i_17_n_0;
  wire cal_seq_cnt_gt_0_i_9_n_0;
  wire cal_seq_cnt_gt_0_reg_0;
  wire \cal_seq_cnt_reg[13]_0 ;
  wire \cal_seq_cnt_reg[16]_i_2_n_0 ;
  wire \cal_seq_cnt_reg[16]_i_2_n_1 ;
  wire \cal_seq_cnt_reg[16]_i_2_n_2 ;
  wire \cal_seq_cnt_reg[16]_i_2_n_3 ;
  wire \cal_seq_cnt_reg[16]_i_2_n_4 ;
  wire \cal_seq_cnt_reg[16]_i_2_n_5 ;
  wire \cal_seq_cnt_reg[16]_i_2_n_6 ;
  wire \cal_seq_cnt_reg[16]_i_2_n_7 ;
  wire \cal_seq_cnt_reg[24]_i_2_n_0 ;
  wire \cal_seq_cnt_reg[24]_i_2_n_1 ;
  wire \cal_seq_cnt_reg[24]_i_2_n_2 ;
  wire \cal_seq_cnt_reg[24]_i_2_n_3 ;
  wire \cal_seq_cnt_reg[24]_i_2_n_4 ;
  wire \cal_seq_cnt_reg[24]_i_2_n_5 ;
  wire \cal_seq_cnt_reg[24]_i_2_n_6 ;
  wire \cal_seq_cnt_reg[24]_i_2_n_7 ;
  wire [31:0]\cal_seq_cnt_reg[31]_0 ;
  wire \cal_seq_cnt_reg[31]_i_3_n_2 ;
  wire \cal_seq_cnt_reg[31]_i_3_n_3 ;
  wire \cal_seq_cnt_reg[31]_i_3_n_4 ;
  wire \cal_seq_cnt_reg[31]_i_3_n_5 ;
  wire \cal_seq_cnt_reg[31]_i_3_n_6 ;
  wire \cal_seq_cnt_reg[31]_i_3_n_7 ;
  wire \cal_seq_cnt_reg[8]_i_2_n_0 ;
  wire \cal_seq_cnt_reg[8]_i_2_n_1 ;
  wire \cal_seq_cnt_reg[8]_i_2_n_2 ;
  wire \cal_seq_cnt_reg[8]_i_2_n_3 ;
  wire \cal_seq_cnt_reg[8]_i_2_n_4 ;
  wire \cal_seq_cnt_reg[8]_i_2_n_5 ;
  wire \cal_seq_cnt_reg[8]_i_2_n_6 ;
  wire \cal_seq_cnt_reg[8]_i_2_n_7 ;
  wire \cal_seq_rd_cnt[0]_i_1_n_0 ;
  wire \cal_seq_rd_cnt[1]_i_1_n_0 ;
  wire \cal_seq_rd_cnt[2]_i_1_n_0 ;
  wire \cal_seq_rd_cnt[3]_i_1_n_0 ;
  wire \cal_seq_rd_cnt[3]_i_2_n_0 ;
  wire \cal_seq_rd_cnt[4]_i_1_n_0 ;
  wire \cal_seq_rd_cnt[4]_i_2_n_0 ;
  wire \cal_seq_rd_cnt[5]_i_1_n_0 ;
  wire \cal_seq_rd_cnt[5]_i_2_n_0 ;
  wire \cal_seq_rd_cnt[6]_i_1_n_0 ;
  wire \cal_seq_rd_cnt[7]_i_1_n_0 ;
  wire \cal_seq_rd_cnt[7]_i_2_n_0 ;
  wire \cal_seq_rd_cnt[7]_i_3_n_0 ;
  wire \cal_seq_rd_cnt[7]_i_4_n_0 ;
  wire [7:0]\cal_seq_rd_cnt_reg[7]_0 ;
  wire [0:0]\cal_seq_reg[2]_0 ;
  wire \cal_seq_reg_n_0_[0] ;
  wire \cal_seq_reg_n_0_[2] ;
  wire cal_timer0;
  wire \cal_timer[0]_i_16_n_0 ;
  wire \cal_timer[0]_i_17_n_0 ;
  wire \cal_timer[0]_i_18_n_0 ;
  wire \cal_timer[0]_i_19_n_0 ;
  wire \cal_timer[0]_i_20_n_0 ;
  wire \cal_timer[0]_i_4_n_0 ;
  wire \cal_timer[0]_i_5_n_0 ;
  wire \cal_timer[0]_i_6_n_0 ;
  wire [31:0]cal_timer_reg;
  wire \cal_timer_reg[0]_0 ;
  wire [7:0]\cal_timer_reg[15]_0 ;
  wire \cal_timer_reg[21]_0 ;
  wire [7:0]\cal_timer_reg[23]_0 ;
  wire \cal_timer_reg[24]_0 ;
  wire \cal_timer_reg[25]_0 ;
  wire \cal_timer_reg[28]_0 ;
  wire \cal_timer_reg[29]_0 ;
  wire [7:0]\cal_timer_reg[31]_0 ;
  wire \casSlot_reg_n_0_[0] ;
  wire clb2phy_fifo_rden_nxt0;
  wire \clb2phy_wrcs0_low_reg[31]_0 ;
  wire \clb2phy_wrcs0_low_reg_n_0_[31] ;
  wire \clb2phy_wrcs1_low_reg_n_0_[31] ;
  wire clear_fifo_rden_nxt;
  wire clear_gt_data_ready_flag;
  wire clear_gt_data_ready_flag_reg_0;
  wire \cmd_gen_dly[7]_i_10_n_0 ;
  wire \cmd_gen_dly[7]_i_11_n_0 ;
  wire \cmd_gen_dly[7]_i_12_n_0 ;
  wire \cmd_gen_dly[7]_i_13_n_0 ;
  wire \cmd_gen_dly[7]_i_14_n_0 ;
  wire \cmd_gen_dly[7]_i_1_n_0 ;
  wire \cmd_gen_dly[7]_i_4_n_0 ;
  wire \cmd_gen_dly[7]_i_5_n_0 ;
  wire \cmd_gen_dly[7]_i_6_n_0 ;
  wire \cmd_gen_dly[7]_i_7_n_0 ;
  wire \cmd_gen_dly[7]_i_8_n_0 ;
  wire \cmd_gen_dly[7]_i_9_n_0 ;
  wire [7:0]cmd_gen_dly_reg;
  wire \cmd_gen_dly_reg[7]_i_3_n_0 ;
  wire cmd_go_i_1_n_0;
  wire cmd_go_ind;
  wire cmd_go_reg_n_0;
  wire \cmp_byte_reg[0]_rep_n_0 ;
  wire \cmp_byte_reg[1]_rep_n_0 ;
  wire [0:0]\cmp_byte_reg[2]_0 ;
  wire \cmp_byte_reg_n_0_[0] ;
  wire \cmp_byte_reg_n_0_[1] ;
  wire \cmp_byte_reg_n_0_[2] ;
  wire cnt_clr_access;
  wire cnt_clr_reg_0;
  wire cnt_clr_reg_1;
  wire config_rd_val;
  wire config_rd_val0;
  wire [7:0]\cplx_CAS_reg[6] ;
  wire \cplx_RAS_reg[6] ;
  wire \cplx_RAS_reg[6]_0 ;
  wire cplx_cal;
  wire [3:0]cplx_cal_reg;
  wire [16:16]cplx_config0_out;
  wire [0:0]\cplx_config_reg[0]_0 ;
  wire [0:0]\cplx_config_reg[16]_0 ;
  wire \cplx_config_reg[16]_1 ;
  wire \cplx_config_reg[1]_0 ;
  wire \cplx_config_reg_n_0_[0] ;
  wire \cplx_config_reg_n_0_[10] ;
  wire \cplx_config_reg_n_0_[11] ;
  wire \cplx_config_reg_n_0_[12] ;
  wire \cplx_config_reg_n_0_[13] ;
  wire \cplx_config_reg_n_0_[14] ;
  wire \cplx_config_reg_n_0_[15] ;
  wire \cplx_config_reg_n_0_[16] ;
  wire \cplx_config_reg_n_0_[1] ;
  wire \cplx_config_reg_n_0_[2] ;
  wire \cplx_config_reg_n_0_[3] ;
  wire \cplx_config_reg_n_0_[4] ;
  wire \cplx_config_reg_n_0_[5] ;
  wire \cplx_config_reg_n_0_[6] ;
  wire \cplx_config_reg_n_0_[7] ;
  wire \cplx_config_reg_n_0_[8] ;
  wire \cplx_config_reg_n_0_[9] ;
  wire \cplx_error_accum_reg[14] ;
  wire \cplx_error_accum_reg[15] ;
  wire \cplx_error_accum_reg[19] ;
  wire \cplx_error_accum_reg[44] ;
  wire [53:0]\cplx_error_accum_reg[63] ;
  wire [0:0]cplx_status;
  wire \dReg_reg[10] ;
  wire \dReg_reg[11] ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [575:0]\dReg_reg[15] ;
  wire \dReg_reg[8] ;
  wire \dReg_reg[8]_0 ;
  wire \dReg_reg[9] ;
  wire \dReg_reg[9]_0 ;
  wire \dReg_reg[9]_1 ;
  wire [63:0]data1;
  wire [63:0]data2;
  wire [63:0]data3;
  wire [63:0]data4;
  wire [63:0]data5;
  wire [63:0]data6;
  wire [63:0]data7;
  wire \delay_cntr[0]_i_1_n_0 ;
  wire \delay_cntr[2]_i_1_n_0 ;
  wire \delay_cntr[2]_i_3_n_0 ;
  wire \delay_cntr[2]_i_4_n_0 ;
  wire delay_cntr_rd_valid0;
  wire [1:0]\delay_cntr_reg[2]_0 ;
  wire devices_dsel;
  wire [0:0]douta;
  wire [2:1]dqin_valid_shift_nxt;
  wire [0:0]\dqin_valid_shift_reg[0]_0 ;
  wire \dqin_valid_shift_reg_n_0_[0] ;
  wire \dqin_valid_shift_reg_n_0_[2] ;
  wire \dram_device_sel_reg_n_0_[0] ;
  wire \dram_device_sel_reg_n_0_[1] ;
  wire \dram_device_sel_reg_n_0_[2] ;
  wire \dram_device_sel_reg_n_0_[3] ;
  wire \dram_device_sel_reg_n_0_[4] ;
  wire \dram_device_sel_reg_n_0_[5] ;
  wire \dram_device_sel_reg_n_0_[6] ;
  wire \dram_device_sel_reg_n_0_[7] ;
  wire en_vtc;
  wire [2:0]extended_write;
  wire extended_write_mode;
  wire [7:0]\genblk10[0].cal_DMOut_n_A_r_reg ;
  wire [7:0]\genblk10[1].cal_DMOut_n_A_r_reg ;
  wire [7:0]\genblk10[2].cal_DMOut_n_A_r_reg ;
  wire [7:0]\genblk10[3].cal_DMOut_n_A_r_reg ;
  wire [0:0]\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ;
  wire [7:0]\genblk10[4].cal_DMOut_n_A_r_reg ;
  wire [7:0]\genblk10[5].cal_DMOut_n_A_r_reg ;
  wire [7:0]\genblk10[6].cal_DMOut_n_A_r_reg ;
  wire [0:0]\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ;
  wire [7:0]\genblk10[7].cal_DMOut_n_A_r_reg ;
  wire \genblk6[0].mcal_DQ0In_lrdimm_and_r[0]_i_2_n_0 ;
  wire \genblk6[0].mcal_DQ0In_lrdimm_or_r[0]_i_3_n_0 ;
  wire \genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ;
  wire \genblk6[0].mcal_DQ0In_lrdimm_or_r_reg_n_0_[0] ;
  wire \genblk6[10].mcal_DQ0In_lrdimm_and_r[10]_i_2_n_0 ;
  wire \genblk6[10].mcal_DQ0In_lrdimm_or_r[10]_i_2_n_0 ;
  wire \genblk6[10].mcal_DQ0In_lrdimm_or_r_reg_n_0_[10] ;
  wire \genblk6[11].mcal_DQ0In_lrdimm_and_r[11]_i_2_n_0 ;
  wire \genblk6[11].mcal_DQ0In_lrdimm_or_r[11]_i_2_n_0 ;
  wire \genblk6[11].mcal_DQ0In_lrdimm_or_r_reg_n_0_[11] ;
  wire \genblk6[12].mcal_DQ0In_lrdimm_and_r[12]_i_2_n_0 ;
  wire \genblk6[12].mcal_DQ0In_lrdimm_or_r[12]_i_2_n_0 ;
  wire \genblk6[12].mcal_DQ0In_lrdimm_or_r_reg_n_0_[12] ;
  wire \genblk6[13].mcal_DQ0In_lrdimm_and_r[13]_i_2_n_0 ;
  wire \genblk6[13].mcal_DQ0In_lrdimm_or_r[13]_i_2_n_0 ;
  wire \genblk6[13].mcal_DQ0In_lrdimm_or_r_reg_n_0_[13] ;
  wire \genblk6[14].mcal_DQ0In_lrdimm_and_r[14]_i_2_n_0 ;
  wire \genblk6[14].mcal_DQ0In_lrdimm_or_r[14]_i_2_n_0 ;
  wire \genblk6[14].mcal_DQ0In_lrdimm_or_r_reg_n_0_[14] ;
  wire \genblk6[15].mcal_DQ0In_lrdimm_and_r[15]_i_2_n_0 ;
  wire \genblk6[15].mcal_DQ0In_lrdimm_or_r[15]_i_2_n_0 ;
  wire \genblk6[15].mcal_DQ0In_lrdimm_or_r_reg_n_0_[15] ;
  wire \genblk6[1].mcal_DQ0In_lrdimm_and_r[1]_i_2_n_0 ;
  wire \genblk6[1].mcal_DQ0In_lrdimm_or_r[1]_i_2_n_0 ;
  wire \genblk6[1].mcal_DQ0In_lrdimm_or_r_reg_n_0_[1] ;
  wire \genblk6[2].mcal_DQ0In_lrdimm_and_r[2]_i_2_n_0 ;
  wire \genblk6[2].mcal_DQ0In_lrdimm_or_r[2]_i_2_n_0 ;
  wire \genblk6[2].mcal_DQ0In_lrdimm_or_r_reg_n_0_[2] ;
  wire \genblk6[3].mcal_DQ0In_lrdimm_and_r[3]_i_2_n_0 ;
  wire \genblk6[3].mcal_DQ0In_lrdimm_or_r[3]_i_2_n_0 ;
  wire \genblk6[3].mcal_DQ0In_lrdimm_or_r_reg_n_0_[3] ;
  wire \genblk6[4].mcal_DQ0In_lrdimm_and_r[4]_i_2_n_0 ;
  wire \genblk6[4].mcal_DQ0In_lrdimm_or_r[4]_i_2_n_0 ;
  wire \genblk6[4].mcal_DQ0In_lrdimm_or_r_reg_n_0_[4] ;
  wire \genblk6[5].mcal_DQ0In_lrdimm_and_r[5]_i_2_n_0 ;
  wire \genblk6[5].mcal_DQ0In_lrdimm_or_r[5]_i_2_n_0 ;
  wire \genblk6[5].mcal_DQ0In_lrdimm_or_r_reg_n_0_[5] ;
  wire \genblk6[6].mcal_DQ0In_lrdimm_and_r[6]_i_2_n_0 ;
  wire \genblk6[6].mcal_DQ0In_lrdimm_or_r[6]_i_2_n_0 ;
  wire \genblk6[6].mcal_DQ0In_lrdimm_or_r_reg_n_0_[6] ;
  wire \genblk6[7].mcal_DQ0In_lrdimm_and_r[7]_i_2_n_0 ;
  wire \genblk6[7].mcal_DQ0In_lrdimm_or_r[7]_i_2_n_0 ;
  wire \genblk6[7].mcal_DQ0In_lrdimm_or_r_reg_n_0_[7] ;
  wire \genblk6[8].mcal_DQ0In_lrdimm_and_r[8]_i_2_n_0 ;
  wire \genblk6[8].mcal_DQ0In_lrdimm_or_r[8]_i_2_n_0 ;
  wire \genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8]_0 ;
  wire \genblk6[8].mcal_DQ0In_lrdimm_or_r_reg_n_0_[8] ;
  wire \genblk6[9].mcal_DQ0In_lrdimm_and_r[9]_i_2_n_0 ;
  wire \genblk6[9].mcal_DQ0In_lrdimm_or_r[9]_i_2_n_0 ;
  wire \genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9]_0 ;
  wire \genblk6[9].mcal_DQ0In_lrdimm_or_r_reg_n_0_[9] ;
  wire gt_data_ready_flag;
  wire gt_data_ready_flag_nxt;
  wire gt_data_ready_flag_reg_0;
  wire [1:0]in0;
  wire [8:0]\init_cal_BA_reg[15] ;
  wire \init_cal_BA_reg[7] ;
  wire [0:0]init_cal_BG;
  wire \init_cal_BG_reg[7] ;
  wire [0:0]init_cal_CKE;
  wire [0:0]init_cal_CS_n;
  wire [0:0]init_cal_RESET_n;
  wire \init_cal_RESET_n_reg[7] ;
  wire io_addr_strobe_r1;
  wire io_addr_strobe_r1_reg_0;
  wire io_addr_strobe_r2;
  wire [15:0]io_address;
  wire [31:0]\io_read_data_reg[31]_0 ;
  wire io_ready;
  wire io_ready_i_1_n_0;
  wire io_ready_lvl_i_1_n_0;
  wire [0:0]io_ready_lvl_reg_0;
  wire io_ready_reg_0;
  wire io_ready_reg_1;
  wire io_ready_reg_2;
  wire [31:0]io_write_data;
  wire [47:32]lowCL00;
  wire \lowCL0[42]_i_3_n_0 ;
  wire \lowCL0[42]_i_4_n_0 ;
  wire \lowCL0[43]_i_3_n_0 ;
  wire \lowCL0[43]_i_4_n_0 ;
  wire \lowCL0[44]_i_3_n_0 ;
  wire \lowCL0[44]_i_4_n_0 ;
  wire \lowCL0[45]_i_3_n_0 ;
  wire \lowCL0[45]_i_4_n_0 ;
  wire \lowCL0[46]_i_3_n_0 ;
  wire \lowCL0[46]_i_4_n_0 ;
  wire \lowCL0[47]_i_6_n_0 ;
  wire \lowCL0[47]_i_7_n_0 ;
  wire \lowCL0_reg[42]_i_2_n_0 ;
  wire [31:0]\lowCL0_reg[45]_0 ;
  wire \lowCL0_reg_n_0_[10] ;
  wire \lowCL0_reg_n_0_[11] ;
  wire \lowCL0_reg_n_0_[16] ;
  wire \lowCL0_reg_n_0_[17] ;
  wire \lowCL0_reg_n_0_[22] ;
  wire \lowCL0_reg_n_0_[23] ;
  wire \lowCL0_reg_n_0_[28] ;
  wire \lowCL0_reg_n_0_[29] ;
  wire \lowCL0_reg_n_0_[34] ;
  wire \lowCL0_reg_n_0_[35] ;
  wire \lowCL0_reg_n_0_[40] ;
  wire \lowCL0_reg_n_0_[41] ;
  wire \lowCL0_reg_n_0_[46] ;
  wire \lowCL0_reg_n_0_[47] ;
  wire \lowCL0_reg_n_0_[4] ;
  wire \lowCL0_reg_n_0_[5] ;
  wire [47:32]lowCL10;
  wire \lowCL1[42]_i_3_n_0 ;
  wire \lowCL1[42]_i_4_n_0 ;
  wire \lowCL1[43]_i_3_n_0 ;
  wire \lowCL1[43]_i_4_n_0 ;
  wire \lowCL1[44]_i_3_n_0 ;
  wire \lowCL1[44]_i_4_n_0 ;
  wire \lowCL1[45]_i_3_n_0 ;
  wire \lowCL1[45]_i_4_n_0 ;
  wire \lowCL1[46]_i_3_n_0 ;
  wire \lowCL1[46]_i_4_n_0 ;
  wire \lowCL1[47]_i_3_n_0 ;
  wire \lowCL1[47]_i_4_n_0 ;
  wire [31:0]\lowCL1_reg[45]_0 ;
  wire \lowCL1_reg_n_0_[10] ;
  wire \lowCL1_reg_n_0_[11] ;
  wire \lowCL1_reg_n_0_[16] ;
  wire \lowCL1_reg_n_0_[17] ;
  wire \lowCL1_reg_n_0_[22] ;
  wire \lowCL1_reg_n_0_[23] ;
  wire \lowCL1_reg_n_0_[28] ;
  wire \lowCL1_reg_n_0_[29] ;
  wire \lowCL1_reg_n_0_[34] ;
  wire \lowCL1_reg_n_0_[35] ;
  wire \lowCL1_reg_n_0_[40] ;
  wire \lowCL1_reg_n_0_[41] ;
  wire \lowCL1_reg_n_0_[46] ;
  wire \lowCL1_reg_n_0_[47] ;
  wire \lowCL1_reg_n_0_[4] ;
  wire \lowCL1_reg_n_0_[5] ;
  wire [47:32]lowCL20;
  wire \lowCL2[42]_i_3_n_0 ;
  wire \lowCL2[42]_i_4_n_0 ;
  wire \lowCL2[43]_i_3_n_0 ;
  wire \lowCL2[43]_i_4_n_0 ;
  wire \lowCL2[44]_i_3_n_0 ;
  wire \lowCL2[44]_i_4_n_0 ;
  wire \lowCL2[45]_i_3_n_0 ;
  wire \lowCL2[45]_i_4_n_0 ;
  wire \lowCL2[46]_i_3_n_0 ;
  wire \lowCL2[46]_i_4_n_0 ;
  wire \lowCL2[47]_i_3_n_0 ;
  wire \lowCL2[47]_i_4_n_0 ;
  wire [31:0]\lowCL2_reg[45]_0 ;
  wire \lowCL2_reg_n_0_[10] ;
  wire \lowCL2_reg_n_0_[11] ;
  wire \lowCL2_reg_n_0_[16] ;
  wire \lowCL2_reg_n_0_[17] ;
  wire \lowCL2_reg_n_0_[22] ;
  wire \lowCL2_reg_n_0_[23] ;
  wire \lowCL2_reg_n_0_[28] ;
  wire \lowCL2_reg_n_0_[29] ;
  wire \lowCL2_reg_n_0_[34] ;
  wire \lowCL2_reg_n_0_[35] ;
  wire \lowCL2_reg_n_0_[40] ;
  wire \lowCL2_reg_n_0_[41] ;
  wire \lowCL2_reg_n_0_[46] ;
  wire \lowCL2_reg_n_0_[47] ;
  wire \lowCL2_reg_n_0_[4] ;
  wire \lowCL2_reg_n_0_[5] ;
  wire [47:32]lowCL30;
  wire \lowCL3[42]_i_3_n_0 ;
  wire \lowCL3[42]_i_4_n_0 ;
  wire \lowCL3[43]_i_3_n_0 ;
  wire \lowCL3[43]_i_4_n_0 ;
  wire \lowCL3[44]_i_3_n_0 ;
  wire \lowCL3[44]_i_4_n_0 ;
  wire \lowCL3[45]_i_3_n_0 ;
  wire \lowCL3[45]_i_4_n_0 ;
  wire \lowCL3[46]_i_3_n_0 ;
  wire \lowCL3[46]_i_4_n_0 ;
  wire \lowCL3[47]_i_3_n_0 ;
  wire \lowCL3[47]_i_4_n_0 ;
  wire [31:0]\lowCL3_reg[45]_0 ;
  wire \lowCL3_reg_n_0_[10] ;
  wire \lowCL3_reg_n_0_[11] ;
  wire \lowCL3_reg_n_0_[16] ;
  wire \lowCL3_reg_n_0_[17] ;
  wire \lowCL3_reg_n_0_[22] ;
  wire \lowCL3_reg_n_0_[23] ;
  wire \lowCL3_reg_n_0_[28] ;
  wire \lowCL3_reg_n_0_[29] ;
  wire \lowCL3_reg_n_0_[34] ;
  wire \lowCL3_reg_n_0_[35] ;
  wire \lowCL3_reg_n_0_[40] ;
  wire \lowCL3_reg_n_0_[41] ;
  wire \lowCL3_reg_n_0_[46] ;
  wire \lowCL3_reg_n_0_[47] ;
  wire \lowCL3_reg_n_0_[4] ;
  wire \lowCL3_reg_n_0_[5] ;
  wire lrdimm_cal_mode;
  wire lrdimm_cal_mode_reg_0;
  wire lrdimm_cal_mode_reg_1;
  wire lrdimm_cal_mode_reg_2;
  wire lrdimm_cmp_clr;
  wire lrdimm_cmp_clr_reg_n_0;
  wire lrdimm_cmp_en_reg_0;
  wire lrdimm_cmp_en_reg_1;
  wire lrdimm_drive_dq_reg_n_0;
  wire [5:0]\max_rd_lat_reg[5]_0 ;
  wire [0:0]\max_rd_lat_reg[5]_1 ;
  wire mcCasSlot2;
  wire mcRdCAS;
  wire mcWrCAS;
  wire [35:0]mc_ADR;
  wire [6:0]mc_BA;
  wire [2:0]mc_BG;
  wire [1:0]mc_CKE;
  wire mc_CKE7;
  wire [0:0]mc_CS_n;
  wire mc_CS_n7;
  wire [0:0]mc_ODT;
  wire mc_ODT7;
  wire [1:0]mcalRank;
  wire [4:0]\mcal_ADR_dly_reg[0][128] ;
  wire [14:0]\mcal_ADR_dly_reg[0][134] ;
  wire [4:0]\mcal_ADR_dly_reg[0][135] ;
  wire \mcal_ADR_dly_reg[0][87] ;
  wire [1:0]\mcal_BA_dly_reg[0][15] ;
  wire [1:0]\mcal_BA_dly_reg[0][8] ;
  wire [5:5]mcal_DMIn_bit_r1;
  wire \mcal_DMIn_bit_r1[0]_i_2_n_0 ;
  wire \mcal_DMIn_bit_r1[0]_i_3_n_0 ;
  wire \mcal_DMIn_bit_r1[1]_i_2_n_0 ;
  wire \mcal_DMIn_bit_r1[1]_i_3_n_0 ;
  wire \mcal_DMIn_bit_r1[2]_i_2_n_0 ;
  wire \mcal_DMIn_bit_r1[2]_i_3_n_0 ;
  wire \mcal_DMIn_bit_r1[3]_i_2_n_0 ;
  wire \mcal_DMIn_bit_r1[3]_i_3_n_0 ;
  wire \mcal_DMIn_bit_r1[4]_i_2_n_0 ;
  wire \mcal_DMIn_bit_r1[4]_i_3_n_0 ;
  wire \mcal_DMIn_bit_r1[5]_i_2_n_0 ;
  wire \mcal_DMIn_bit_r1[5]_i_3_n_0 ;
  wire \mcal_DMIn_bit_r1[6]_i_2_n_0 ;
  wire \mcal_DMIn_bit_r1[6]_i_3_n_0 ;
  wire \mcal_DMIn_bit_r1[7]_i_2_n_0 ;
  wire \mcal_DMIn_bit_r1[7]_i_3_n_0 ;
  wire \mcal_DMIn_bit_r1_reg[0]_i_1_n_0 ;
  wire \mcal_DMIn_bit_r1_reg[1]_i_1_n_0 ;
  wire \mcal_DMIn_bit_r1_reg[2]_i_1_n_0 ;
  wire \mcal_DMIn_bit_r1_reg[3]_i_1_n_0 ;
  wire \mcal_DMIn_bit_r1_reg[4]_i_1_n_0 ;
  wire \mcal_DMIn_bit_r1_reg[5]_i_1_n_0 ;
  wire \mcal_DMIn_bit_r1_reg[6]_i_1_n_0 ;
  wire [6:0]\mcal_DMIn_bit_r1_reg[7]_0 ;
  wire \mcal_DMIn_bit_r1_reg[7]_i_1_n_0 ;
  wire [63:0]mcal_DMIn_n_r;
  wire [63:0]\mcal_DMIn_n_r_reg[63]_0 ;
  wire mcal_DQ0In_lrdimm_and_0;
  wire mcal_DQ0In_lrdimm_and_1;
  wire mcal_DQ0In_lrdimm_and_10;
  wire mcal_DQ0In_lrdimm_and_11;
  wire mcal_DQ0In_lrdimm_and_12;
  wire mcal_DQ0In_lrdimm_and_13;
  wire mcal_DQ0In_lrdimm_and_14;
  wire mcal_DQ0In_lrdimm_and_15;
  wire mcal_DQ0In_lrdimm_and_2;
  wire mcal_DQ0In_lrdimm_and_3;
  wire mcal_DQ0In_lrdimm_and_4;
  wire mcal_DQ0In_lrdimm_and_5;
  wire mcal_DQ0In_lrdimm_and_6;
  wire mcal_DQ0In_lrdimm_and_7;
  wire mcal_DQ0In_lrdimm_and_8;
  wire mcal_DQ0In_lrdimm_and_9;
  wire mcal_DQ0In_lrdimm_or_0;
  wire mcal_DQ0In_lrdimm_or_1;
  wire mcal_DQ0In_lrdimm_or_10;
  wire mcal_DQ0In_lrdimm_or_11;
  wire mcal_DQ0In_lrdimm_or_12;
  wire mcal_DQ0In_lrdimm_or_13;
  wire mcal_DQ0In_lrdimm_or_14;
  wire mcal_DQ0In_lrdimm_or_15;
  wire mcal_DQ0In_lrdimm_or_2;
  wire mcal_DQ0In_lrdimm_or_3;
  wire mcal_DQ0In_lrdimm_or_4;
  wire mcal_DQ0In_lrdimm_or_5;
  wire mcal_DQ0In_lrdimm_or_6;
  wire mcal_DQ0In_lrdimm_or_7;
  wire mcal_DQ0In_lrdimm_or_8;
  wire mcal_DQ0In_lrdimm_or_9;
  wire [63:0]mcal_DQIn_byte_r;
  wire mcal_DQIn_byte_r0;
  wire [63:0]mcal_DQIn_byte_r1;
  wire \mcal_DQIn_byte_r1[0]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[0]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[10]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[10]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[11]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[11]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[12]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[12]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[13]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[13]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[14]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[14]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[15]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[15]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[16]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[16]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[17]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[17]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[18]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[18]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[19]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[19]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[1]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[1]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[20]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[20]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[21]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[21]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[22]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[22]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[23]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[23]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[24]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[24]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[25]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[25]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[26]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[26]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[27]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[27]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[28]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[28]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[29]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[29]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[2]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[2]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[30]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[30]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[31]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[31]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[32]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[32]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[33]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[33]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[34]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[34]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[35]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[35]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[36]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[36]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[37]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[37]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[38]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[38]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[39]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[39]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[3]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[3]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[40]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[40]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[41]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[41]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[42]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[42]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[43]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[43]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[44]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[44]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[45]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[45]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[46]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[46]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[47]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[47]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[48]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[48]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[49]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[49]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[4]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[4]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[50]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[50]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[51]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[51]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[52]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[52]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[53]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[53]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[54]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[54]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[55]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[55]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[56]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[56]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[57]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[57]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[58]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[58]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[59]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[59]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[5]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[5]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[60]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[60]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[61]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[61]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[62]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[62]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[63]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[63]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[6]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[6]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[7]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[7]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[8]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[8]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1[9]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r1[9]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[0]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[10]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[11]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[12]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[13]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[14]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[15]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[16]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[17]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[18]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[19]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[1]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[20]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[21]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[22]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[23]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[24]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[25]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[26]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[27]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[28]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[29]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[2]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[30]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[31]_0 ;
  wire \mcal_DQIn_byte_r1_reg[31]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[32]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[33]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[34]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[35]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[36]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[37]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[38]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[39]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[3]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[40]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[41]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[42]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[43]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[44]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[45]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[46]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[47]_i_1_n_0 ;
  wire [9:0]\mcal_DQIn_byte_r1_reg[48]_0 ;
  wire \mcal_DQIn_byte_r1_reg[48]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[49]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[4]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[50]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[51]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[52]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[53]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[54]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[55]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[56]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[57]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[58]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[59]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[5]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[60]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[61]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[62]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[63]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[6]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[7]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[8]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r1_reg[9]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r[0]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[0]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[10]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[10]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[11]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[11]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[12]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[12]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[13]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[13]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[14]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[14]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[15]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[15]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[16]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[16]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[17]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[17]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[18]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[18]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[19]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[19]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[1]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[1]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[20]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[20]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[21]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[21]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[22]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[22]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[23]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[23]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[24]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[24]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[25]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[25]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[26]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[26]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[27]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[27]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[28]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[28]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[29]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[29]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[2]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[2]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[30]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[30]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[31]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[31]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[32]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[32]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[33]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[33]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[34]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[34]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[35]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[35]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[36]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[36]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[37]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[37]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[38]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[38]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[39]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[39]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[3]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[3]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[40]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[40]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[41]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[41]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[42]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[42]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[43]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[43]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[44]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[44]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[45]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[45]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[46]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[46]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[47]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[47]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[48]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[48]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[49]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[49]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[4]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[4]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[50]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[50]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[51]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[51]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[52]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[52]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[53]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[53]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[54]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[54]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[55]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[55]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[56]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[56]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[57]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[57]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[58]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[58]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[59]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[59]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[5]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[5]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[60]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[60]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[61]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[61]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[62]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[62]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[63]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[63]_i_4_n_0 ;
  wire \mcal_DQIn_byte_r[6]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[6]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[7]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[7]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[8]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[8]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r[9]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r[9]_i_3_n_0 ;
  wire \mcal_DQIn_byte_r_reg[0]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[10]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[11]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[12]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[13]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[14]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[15]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[16]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[17]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[18]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[19]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[1]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[20]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[21]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[22]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[23]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[24]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[25]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[26]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[27]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[28]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[29]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[2]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[30]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[31]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[32]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[33]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[34]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[35]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[36]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[37]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[38]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[39]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[3]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[40]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[41]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[42]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[43]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[44]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[45]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[46]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[47]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[48]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[49]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[4]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[50]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[51]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[52]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[53]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[54]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[55]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[56]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[57]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[58]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[59]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[5]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[60]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[61]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[62]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[63]_i_2_n_0 ;
  wire \mcal_DQIn_byte_r_reg[6]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[7]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[8]_i_1_n_0 ;
  wire \mcal_DQIn_byte_r_reg[9]_i_1_n_0 ;
  wire [511:0]\mcal_DQIn_r_reg[511]_0 ;
  wire \mcal_DQIn_r_reg_n_0_[0] ;
  wire \mcal_DQIn_r_reg_n_0_[100] ;
  wire \mcal_DQIn_r_reg_n_0_[101] ;
  wire \mcal_DQIn_r_reg_n_0_[102] ;
  wire \mcal_DQIn_r_reg_n_0_[103] ;
  wire \mcal_DQIn_r_reg_n_0_[104] ;
  wire \mcal_DQIn_r_reg_n_0_[105] ;
  wire \mcal_DQIn_r_reg_n_0_[106] ;
  wire \mcal_DQIn_r_reg_n_0_[107] ;
  wire \mcal_DQIn_r_reg_n_0_[108] ;
  wire \mcal_DQIn_r_reg_n_0_[109] ;
  wire \mcal_DQIn_r_reg_n_0_[10] ;
  wire \mcal_DQIn_r_reg_n_0_[110] ;
  wire \mcal_DQIn_r_reg_n_0_[111] ;
  wire \mcal_DQIn_r_reg_n_0_[112] ;
  wire \mcal_DQIn_r_reg_n_0_[113] ;
  wire \mcal_DQIn_r_reg_n_0_[114] ;
  wire \mcal_DQIn_r_reg_n_0_[115] ;
  wire \mcal_DQIn_r_reg_n_0_[116] ;
  wire \mcal_DQIn_r_reg_n_0_[117] ;
  wire \mcal_DQIn_r_reg_n_0_[118] ;
  wire \mcal_DQIn_r_reg_n_0_[119] ;
  wire \mcal_DQIn_r_reg_n_0_[11] ;
  wire \mcal_DQIn_r_reg_n_0_[120] ;
  wire \mcal_DQIn_r_reg_n_0_[121] ;
  wire \mcal_DQIn_r_reg_n_0_[122] ;
  wire \mcal_DQIn_r_reg_n_0_[123] ;
  wire \mcal_DQIn_r_reg_n_0_[124] ;
  wire \mcal_DQIn_r_reg_n_0_[125] ;
  wire \mcal_DQIn_r_reg_n_0_[126] ;
  wire \mcal_DQIn_r_reg_n_0_[127] ;
  wire \mcal_DQIn_r_reg_n_0_[128] ;
  wire \mcal_DQIn_r_reg_n_0_[129] ;
  wire \mcal_DQIn_r_reg_n_0_[12] ;
  wire \mcal_DQIn_r_reg_n_0_[130] ;
  wire \mcal_DQIn_r_reg_n_0_[131] ;
  wire \mcal_DQIn_r_reg_n_0_[132] ;
  wire \mcal_DQIn_r_reg_n_0_[133] ;
  wire \mcal_DQIn_r_reg_n_0_[134] ;
  wire \mcal_DQIn_r_reg_n_0_[135] ;
  wire \mcal_DQIn_r_reg_n_0_[136] ;
  wire \mcal_DQIn_r_reg_n_0_[137] ;
  wire \mcal_DQIn_r_reg_n_0_[138] ;
  wire \mcal_DQIn_r_reg_n_0_[139] ;
  wire \mcal_DQIn_r_reg_n_0_[13] ;
  wire \mcal_DQIn_r_reg_n_0_[140] ;
  wire \mcal_DQIn_r_reg_n_0_[141] ;
  wire \mcal_DQIn_r_reg_n_0_[142] ;
  wire \mcal_DQIn_r_reg_n_0_[143] ;
  wire \mcal_DQIn_r_reg_n_0_[144] ;
  wire \mcal_DQIn_r_reg_n_0_[145] ;
  wire \mcal_DQIn_r_reg_n_0_[146] ;
  wire \mcal_DQIn_r_reg_n_0_[147] ;
  wire \mcal_DQIn_r_reg_n_0_[148] ;
  wire \mcal_DQIn_r_reg_n_0_[149] ;
  wire \mcal_DQIn_r_reg_n_0_[14] ;
  wire \mcal_DQIn_r_reg_n_0_[150] ;
  wire \mcal_DQIn_r_reg_n_0_[151] ;
  wire \mcal_DQIn_r_reg_n_0_[152] ;
  wire \mcal_DQIn_r_reg_n_0_[153] ;
  wire \mcal_DQIn_r_reg_n_0_[154] ;
  wire \mcal_DQIn_r_reg_n_0_[155] ;
  wire \mcal_DQIn_r_reg_n_0_[156] ;
  wire \mcal_DQIn_r_reg_n_0_[157] ;
  wire \mcal_DQIn_r_reg_n_0_[158] ;
  wire \mcal_DQIn_r_reg_n_0_[159] ;
  wire \mcal_DQIn_r_reg_n_0_[15] ;
  wire \mcal_DQIn_r_reg_n_0_[160] ;
  wire \mcal_DQIn_r_reg_n_0_[161] ;
  wire \mcal_DQIn_r_reg_n_0_[162] ;
  wire \mcal_DQIn_r_reg_n_0_[163] ;
  wire \mcal_DQIn_r_reg_n_0_[164] ;
  wire \mcal_DQIn_r_reg_n_0_[165] ;
  wire \mcal_DQIn_r_reg_n_0_[166] ;
  wire \mcal_DQIn_r_reg_n_0_[167] ;
  wire \mcal_DQIn_r_reg_n_0_[168] ;
  wire \mcal_DQIn_r_reg_n_0_[169] ;
  wire \mcal_DQIn_r_reg_n_0_[16] ;
  wire \mcal_DQIn_r_reg_n_0_[170] ;
  wire \mcal_DQIn_r_reg_n_0_[171] ;
  wire \mcal_DQIn_r_reg_n_0_[172] ;
  wire \mcal_DQIn_r_reg_n_0_[173] ;
  wire \mcal_DQIn_r_reg_n_0_[174] ;
  wire \mcal_DQIn_r_reg_n_0_[175] ;
  wire \mcal_DQIn_r_reg_n_0_[176] ;
  wire \mcal_DQIn_r_reg_n_0_[177] ;
  wire \mcal_DQIn_r_reg_n_0_[178] ;
  wire \mcal_DQIn_r_reg_n_0_[179] ;
  wire \mcal_DQIn_r_reg_n_0_[17] ;
  wire \mcal_DQIn_r_reg_n_0_[180] ;
  wire \mcal_DQIn_r_reg_n_0_[181] ;
  wire \mcal_DQIn_r_reg_n_0_[182] ;
  wire \mcal_DQIn_r_reg_n_0_[183] ;
  wire \mcal_DQIn_r_reg_n_0_[184] ;
  wire \mcal_DQIn_r_reg_n_0_[185] ;
  wire \mcal_DQIn_r_reg_n_0_[186] ;
  wire \mcal_DQIn_r_reg_n_0_[187] ;
  wire \mcal_DQIn_r_reg_n_0_[188] ;
  wire \mcal_DQIn_r_reg_n_0_[189] ;
  wire \mcal_DQIn_r_reg_n_0_[18] ;
  wire \mcal_DQIn_r_reg_n_0_[190] ;
  wire \mcal_DQIn_r_reg_n_0_[191] ;
  wire \mcal_DQIn_r_reg_n_0_[192] ;
  wire \mcal_DQIn_r_reg_n_0_[193] ;
  wire \mcal_DQIn_r_reg_n_0_[194] ;
  wire \mcal_DQIn_r_reg_n_0_[195] ;
  wire \mcal_DQIn_r_reg_n_0_[196] ;
  wire \mcal_DQIn_r_reg_n_0_[197] ;
  wire \mcal_DQIn_r_reg_n_0_[198] ;
  wire \mcal_DQIn_r_reg_n_0_[199] ;
  wire \mcal_DQIn_r_reg_n_0_[19] ;
  wire \mcal_DQIn_r_reg_n_0_[1] ;
  wire \mcal_DQIn_r_reg_n_0_[200] ;
  wire \mcal_DQIn_r_reg_n_0_[201] ;
  wire \mcal_DQIn_r_reg_n_0_[202] ;
  wire \mcal_DQIn_r_reg_n_0_[203] ;
  wire \mcal_DQIn_r_reg_n_0_[204] ;
  wire \mcal_DQIn_r_reg_n_0_[205] ;
  wire \mcal_DQIn_r_reg_n_0_[206] ;
  wire \mcal_DQIn_r_reg_n_0_[207] ;
  wire \mcal_DQIn_r_reg_n_0_[208] ;
  wire \mcal_DQIn_r_reg_n_0_[209] ;
  wire \mcal_DQIn_r_reg_n_0_[20] ;
  wire \mcal_DQIn_r_reg_n_0_[210] ;
  wire \mcal_DQIn_r_reg_n_0_[211] ;
  wire \mcal_DQIn_r_reg_n_0_[212] ;
  wire \mcal_DQIn_r_reg_n_0_[213] ;
  wire \mcal_DQIn_r_reg_n_0_[214] ;
  wire \mcal_DQIn_r_reg_n_0_[215] ;
  wire \mcal_DQIn_r_reg_n_0_[216] ;
  wire \mcal_DQIn_r_reg_n_0_[217] ;
  wire \mcal_DQIn_r_reg_n_0_[218] ;
  wire \mcal_DQIn_r_reg_n_0_[219] ;
  wire \mcal_DQIn_r_reg_n_0_[21] ;
  wire \mcal_DQIn_r_reg_n_0_[220] ;
  wire \mcal_DQIn_r_reg_n_0_[221] ;
  wire \mcal_DQIn_r_reg_n_0_[222] ;
  wire \mcal_DQIn_r_reg_n_0_[223] ;
  wire \mcal_DQIn_r_reg_n_0_[224] ;
  wire \mcal_DQIn_r_reg_n_0_[225] ;
  wire \mcal_DQIn_r_reg_n_0_[226] ;
  wire \mcal_DQIn_r_reg_n_0_[227] ;
  wire \mcal_DQIn_r_reg_n_0_[228] ;
  wire \mcal_DQIn_r_reg_n_0_[229] ;
  wire \mcal_DQIn_r_reg_n_0_[22] ;
  wire \mcal_DQIn_r_reg_n_0_[230] ;
  wire \mcal_DQIn_r_reg_n_0_[231] ;
  wire \mcal_DQIn_r_reg_n_0_[232] ;
  wire \mcal_DQIn_r_reg_n_0_[233] ;
  wire \mcal_DQIn_r_reg_n_0_[234] ;
  wire \mcal_DQIn_r_reg_n_0_[235] ;
  wire \mcal_DQIn_r_reg_n_0_[236] ;
  wire \mcal_DQIn_r_reg_n_0_[237] ;
  wire \mcal_DQIn_r_reg_n_0_[238] ;
  wire \mcal_DQIn_r_reg_n_0_[239] ;
  wire \mcal_DQIn_r_reg_n_0_[23] ;
  wire \mcal_DQIn_r_reg_n_0_[240] ;
  wire \mcal_DQIn_r_reg_n_0_[241] ;
  wire \mcal_DQIn_r_reg_n_0_[242] ;
  wire \mcal_DQIn_r_reg_n_0_[243] ;
  wire \mcal_DQIn_r_reg_n_0_[244] ;
  wire \mcal_DQIn_r_reg_n_0_[245] ;
  wire \mcal_DQIn_r_reg_n_0_[246] ;
  wire \mcal_DQIn_r_reg_n_0_[247] ;
  wire \mcal_DQIn_r_reg_n_0_[248] ;
  wire \mcal_DQIn_r_reg_n_0_[249] ;
  wire \mcal_DQIn_r_reg_n_0_[24] ;
  wire \mcal_DQIn_r_reg_n_0_[250] ;
  wire \mcal_DQIn_r_reg_n_0_[251] ;
  wire \mcal_DQIn_r_reg_n_0_[252] ;
  wire \mcal_DQIn_r_reg_n_0_[253] ;
  wire \mcal_DQIn_r_reg_n_0_[254] ;
  wire \mcal_DQIn_r_reg_n_0_[255] ;
  wire \mcal_DQIn_r_reg_n_0_[256] ;
  wire \mcal_DQIn_r_reg_n_0_[257] ;
  wire \mcal_DQIn_r_reg_n_0_[258] ;
  wire \mcal_DQIn_r_reg_n_0_[259] ;
  wire \mcal_DQIn_r_reg_n_0_[25] ;
  wire \mcal_DQIn_r_reg_n_0_[260] ;
  wire \mcal_DQIn_r_reg_n_0_[261] ;
  wire \mcal_DQIn_r_reg_n_0_[262] ;
  wire \mcal_DQIn_r_reg_n_0_[263] ;
  wire \mcal_DQIn_r_reg_n_0_[264] ;
  wire \mcal_DQIn_r_reg_n_0_[265] ;
  wire \mcal_DQIn_r_reg_n_0_[266] ;
  wire \mcal_DQIn_r_reg_n_0_[267] ;
  wire \mcal_DQIn_r_reg_n_0_[268] ;
  wire \mcal_DQIn_r_reg_n_0_[269] ;
  wire \mcal_DQIn_r_reg_n_0_[26] ;
  wire \mcal_DQIn_r_reg_n_0_[270] ;
  wire \mcal_DQIn_r_reg_n_0_[271] ;
  wire \mcal_DQIn_r_reg_n_0_[272] ;
  wire \mcal_DQIn_r_reg_n_0_[273] ;
  wire \mcal_DQIn_r_reg_n_0_[274] ;
  wire \mcal_DQIn_r_reg_n_0_[275] ;
  wire \mcal_DQIn_r_reg_n_0_[276] ;
  wire \mcal_DQIn_r_reg_n_0_[277] ;
  wire \mcal_DQIn_r_reg_n_0_[278] ;
  wire \mcal_DQIn_r_reg_n_0_[279] ;
  wire \mcal_DQIn_r_reg_n_0_[27] ;
  wire \mcal_DQIn_r_reg_n_0_[280] ;
  wire \mcal_DQIn_r_reg_n_0_[281] ;
  wire \mcal_DQIn_r_reg_n_0_[282] ;
  wire \mcal_DQIn_r_reg_n_0_[283] ;
  wire \mcal_DQIn_r_reg_n_0_[284] ;
  wire \mcal_DQIn_r_reg_n_0_[285] ;
  wire \mcal_DQIn_r_reg_n_0_[286] ;
  wire \mcal_DQIn_r_reg_n_0_[287] ;
  wire \mcal_DQIn_r_reg_n_0_[288] ;
  wire \mcal_DQIn_r_reg_n_0_[289] ;
  wire \mcal_DQIn_r_reg_n_0_[28] ;
  wire \mcal_DQIn_r_reg_n_0_[290] ;
  wire \mcal_DQIn_r_reg_n_0_[291] ;
  wire \mcal_DQIn_r_reg_n_0_[292] ;
  wire \mcal_DQIn_r_reg_n_0_[293] ;
  wire \mcal_DQIn_r_reg_n_0_[294] ;
  wire \mcal_DQIn_r_reg_n_0_[295] ;
  wire \mcal_DQIn_r_reg_n_0_[296] ;
  wire \mcal_DQIn_r_reg_n_0_[297] ;
  wire \mcal_DQIn_r_reg_n_0_[298] ;
  wire \mcal_DQIn_r_reg_n_0_[299] ;
  wire \mcal_DQIn_r_reg_n_0_[29] ;
  wire \mcal_DQIn_r_reg_n_0_[2] ;
  wire \mcal_DQIn_r_reg_n_0_[300] ;
  wire \mcal_DQIn_r_reg_n_0_[301] ;
  wire \mcal_DQIn_r_reg_n_0_[302] ;
  wire \mcal_DQIn_r_reg_n_0_[303] ;
  wire \mcal_DQIn_r_reg_n_0_[304] ;
  wire \mcal_DQIn_r_reg_n_0_[305] ;
  wire \mcal_DQIn_r_reg_n_0_[306] ;
  wire \mcal_DQIn_r_reg_n_0_[307] ;
  wire \mcal_DQIn_r_reg_n_0_[308] ;
  wire \mcal_DQIn_r_reg_n_0_[309] ;
  wire \mcal_DQIn_r_reg_n_0_[30] ;
  wire \mcal_DQIn_r_reg_n_0_[310] ;
  wire \mcal_DQIn_r_reg_n_0_[311] ;
  wire \mcal_DQIn_r_reg_n_0_[312] ;
  wire \mcal_DQIn_r_reg_n_0_[313] ;
  wire \mcal_DQIn_r_reg_n_0_[314] ;
  wire \mcal_DQIn_r_reg_n_0_[315] ;
  wire \mcal_DQIn_r_reg_n_0_[316] ;
  wire \mcal_DQIn_r_reg_n_0_[317] ;
  wire \mcal_DQIn_r_reg_n_0_[318] ;
  wire \mcal_DQIn_r_reg_n_0_[319] ;
  wire \mcal_DQIn_r_reg_n_0_[31] ;
  wire \mcal_DQIn_r_reg_n_0_[320] ;
  wire \mcal_DQIn_r_reg_n_0_[321] ;
  wire \mcal_DQIn_r_reg_n_0_[322] ;
  wire \mcal_DQIn_r_reg_n_0_[323] ;
  wire \mcal_DQIn_r_reg_n_0_[324] ;
  wire \mcal_DQIn_r_reg_n_0_[325] ;
  wire \mcal_DQIn_r_reg_n_0_[326] ;
  wire \mcal_DQIn_r_reg_n_0_[327] ;
  wire \mcal_DQIn_r_reg_n_0_[328] ;
  wire \mcal_DQIn_r_reg_n_0_[329] ;
  wire \mcal_DQIn_r_reg_n_0_[330] ;
  wire \mcal_DQIn_r_reg_n_0_[331] ;
  wire \mcal_DQIn_r_reg_n_0_[332] ;
  wire \mcal_DQIn_r_reg_n_0_[333] ;
  wire \mcal_DQIn_r_reg_n_0_[334] ;
  wire \mcal_DQIn_r_reg_n_0_[335] ;
  wire \mcal_DQIn_r_reg_n_0_[336] ;
  wire \mcal_DQIn_r_reg_n_0_[337] ;
  wire \mcal_DQIn_r_reg_n_0_[338] ;
  wire \mcal_DQIn_r_reg_n_0_[339] ;
  wire \mcal_DQIn_r_reg_n_0_[340] ;
  wire \mcal_DQIn_r_reg_n_0_[341] ;
  wire \mcal_DQIn_r_reg_n_0_[342] ;
  wire \mcal_DQIn_r_reg_n_0_[343] ;
  wire \mcal_DQIn_r_reg_n_0_[344] ;
  wire \mcal_DQIn_r_reg_n_0_[345] ;
  wire \mcal_DQIn_r_reg_n_0_[346] ;
  wire \mcal_DQIn_r_reg_n_0_[347] ;
  wire \mcal_DQIn_r_reg_n_0_[348] ;
  wire \mcal_DQIn_r_reg_n_0_[349] ;
  wire \mcal_DQIn_r_reg_n_0_[350] ;
  wire \mcal_DQIn_r_reg_n_0_[351] ;
  wire \mcal_DQIn_r_reg_n_0_[352] ;
  wire \mcal_DQIn_r_reg_n_0_[353] ;
  wire \mcal_DQIn_r_reg_n_0_[354] ;
  wire \mcal_DQIn_r_reg_n_0_[355] ;
  wire \mcal_DQIn_r_reg_n_0_[356] ;
  wire \mcal_DQIn_r_reg_n_0_[357] ;
  wire \mcal_DQIn_r_reg_n_0_[358] ;
  wire \mcal_DQIn_r_reg_n_0_[359] ;
  wire \mcal_DQIn_r_reg_n_0_[360] ;
  wire \mcal_DQIn_r_reg_n_0_[361] ;
  wire \mcal_DQIn_r_reg_n_0_[362] ;
  wire \mcal_DQIn_r_reg_n_0_[363] ;
  wire \mcal_DQIn_r_reg_n_0_[364] ;
  wire \mcal_DQIn_r_reg_n_0_[365] ;
  wire \mcal_DQIn_r_reg_n_0_[366] ;
  wire \mcal_DQIn_r_reg_n_0_[367] ;
  wire \mcal_DQIn_r_reg_n_0_[368] ;
  wire \mcal_DQIn_r_reg_n_0_[369] ;
  wire \mcal_DQIn_r_reg_n_0_[370] ;
  wire \mcal_DQIn_r_reg_n_0_[371] ;
  wire \mcal_DQIn_r_reg_n_0_[372] ;
  wire \mcal_DQIn_r_reg_n_0_[373] ;
  wire \mcal_DQIn_r_reg_n_0_[374] ;
  wire \mcal_DQIn_r_reg_n_0_[375] ;
  wire \mcal_DQIn_r_reg_n_0_[376] ;
  wire \mcal_DQIn_r_reg_n_0_[377] ;
  wire \mcal_DQIn_r_reg_n_0_[378] ;
  wire \mcal_DQIn_r_reg_n_0_[379] ;
  wire \mcal_DQIn_r_reg_n_0_[380] ;
  wire \mcal_DQIn_r_reg_n_0_[381] ;
  wire \mcal_DQIn_r_reg_n_0_[382] ;
  wire \mcal_DQIn_r_reg_n_0_[383] ;
  wire \mcal_DQIn_r_reg_n_0_[384] ;
  wire \mcal_DQIn_r_reg_n_0_[385] ;
  wire \mcal_DQIn_r_reg_n_0_[386] ;
  wire \mcal_DQIn_r_reg_n_0_[387] ;
  wire \mcal_DQIn_r_reg_n_0_[388] ;
  wire \mcal_DQIn_r_reg_n_0_[389] ;
  wire \mcal_DQIn_r_reg_n_0_[390] ;
  wire \mcal_DQIn_r_reg_n_0_[391] ;
  wire \mcal_DQIn_r_reg_n_0_[392] ;
  wire \mcal_DQIn_r_reg_n_0_[393] ;
  wire \mcal_DQIn_r_reg_n_0_[394] ;
  wire \mcal_DQIn_r_reg_n_0_[395] ;
  wire \mcal_DQIn_r_reg_n_0_[396] ;
  wire \mcal_DQIn_r_reg_n_0_[397] ;
  wire \mcal_DQIn_r_reg_n_0_[398] ;
  wire \mcal_DQIn_r_reg_n_0_[399] ;
  wire \mcal_DQIn_r_reg_n_0_[3] ;
  wire \mcal_DQIn_r_reg_n_0_[400] ;
  wire \mcal_DQIn_r_reg_n_0_[401] ;
  wire \mcal_DQIn_r_reg_n_0_[402] ;
  wire \mcal_DQIn_r_reg_n_0_[403] ;
  wire \mcal_DQIn_r_reg_n_0_[404] ;
  wire \mcal_DQIn_r_reg_n_0_[405] ;
  wire \mcal_DQIn_r_reg_n_0_[406] ;
  wire \mcal_DQIn_r_reg_n_0_[407] ;
  wire \mcal_DQIn_r_reg_n_0_[408] ;
  wire \mcal_DQIn_r_reg_n_0_[409] ;
  wire \mcal_DQIn_r_reg_n_0_[40] ;
  wire \mcal_DQIn_r_reg_n_0_[410] ;
  wire \mcal_DQIn_r_reg_n_0_[411] ;
  wire \mcal_DQIn_r_reg_n_0_[412] ;
  wire \mcal_DQIn_r_reg_n_0_[413] ;
  wire \mcal_DQIn_r_reg_n_0_[414] ;
  wire \mcal_DQIn_r_reg_n_0_[415] ;
  wire \mcal_DQIn_r_reg_n_0_[416] ;
  wire \mcal_DQIn_r_reg_n_0_[417] ;
  wire \mcal_DQIn_r_reg_n_0_[418] ;
  wire \mcal_DQIn_r_reg_n_0_[419] ;
  wire \mcal_DQIn_r_reg_n_0_[41] ;
  wire \mcal_DQIn_r_reg_n_0_[420] ;
  wire \mcal_DQIn_r_reg_n_0_[421] ;
  wire \mcal_DQIn_r_reg_n_0_[422] ;
  wire \mcal_DQIn_r_reg_n_0_[423] ;
  wire \mcal_DQIn_r_reg_n_0_[424] ;
  wire \mcal_DQIn_r_reg_n_0_[425] ;
  wire \mcal_DQIn_r_reg_n_0_[426] ;
  wire \mcal_DQIn_r_reg_n_0_[427] ;
  wire \mcal_DQIn_r_reg_n_0_[428] ;
  wire \mcal_DQIn_r_reg_n_0_[429] ;
  wire \mcal_DQIn_r_reg_n_0_[42] ;
  wire \mcal_DQIn_r_reg_n_0_[430] ;
  wire \mcal_DQIn_r_reg_n_0_[431] ;
  wire \mcal_DQIn_r_reg_n_0_[432] ;
  wire \mcal_DQIn_r_reg_n_0_[433] ;
  wire \mcal_DQIn_r_reg_n_0_[434] ;
  wire \mcal_DQIn_r_reg_n_0_[435] ;
  wire \mcal_DQIn_r_reg_n_0_[436] ;
  wire \mcal_DQIn_r_reg_n_0_[437] ;
  wire \mcal_DQIn_r_reg_n_0_[438] ;
  wire \mcal_DQIn_r_reg_n_0_[439] ;
  wire \mcal_DQIn_r_reg_n_0_[43] ;
  wire \mcal_DQIn_r_reg_n_0_[440] ;
  wire \mcal_DQIn_r_reg_n_0_[441] ;
  wire \mcal_DQIn_r_reg_n_0_[442] ;
  wire \mcal_DQIn_r_reg_n_0_[443] ;
  wire \mcal_DQIn_r_reg_n_0_[444] ;
  wire \mcal_DQIn_r_reg_n_0_[445] ;
  wire \mcal_DQIn_r_reg_n_0_[446] ;
  wire \mcal_DQIn_r_reg_n_0_[447] ;
  wire \mcal_DQIn_r_reg_n_0_[448] ;
  wire \mcal_DQIn_r_reg_n_0_[449] ;
  wire \mcal_DQIn_r_reg_n_0_[44] ;
  wire \mcal_DQIn_r_reg_n_0_[450] ;
  wire \mcal_DQIn_r_reg_n_0_[451] ;
  wire \mcal_DQIn_r_reg_n_0_[452] ;
  wire \mcal_DQIn_r_reg_n_0_[453] ;
  wire \mcal_DQIn_r_reg_n_0_[454] ;
  wire \mcal_DQIn_r_reg_n_0_[455] ;
  wire \mcal_DQIn_r_reg_n_0_[456] ;
  wire \mcal_DQIn_r_reg_n_0_[457] ;
  wire \mcal_DQIn_r_reg_n_0_[458] ;
  wire \mcal_DQIn_r_reg_n_0_[459] ;
  wire \mcal_DQIn_r_reg_n_0_[45] ;
  wire \mcal_DQIn_r_reg_n_0_[460] ;
  wire \mcal_DQIn_r_reg_n_0_[461] ;
  wire \mcal_DQIn_r_reg_n_0_[462] ;
  wire \mcal_DQIn_r_reg_n_0_[463] ;
  wire \mcal_DQIn_r_reg_n_0_[464] ;
  wire \mcal_DQIn_r_reg_n_0_[465] ;
  wire \mcal_DQIn_r_reg_n_0_[466] ;
  wire \mcal_DQIn_r_reg_n_0_[467] ;
  wire \mcal_DQIn_r_reg_n_0_[468] ;
  wire \mcal_DQIn_r_reg_n_0_[469] ;
  wire \mcal_DQIn_r_reg_n_0_[46] ;
  wire \mcal_DQIn_r_reg_n_0_[470] ;
  wire \mcal_DQIn_r_reg_n_0_[471] ;
  wire \mcal_DQIn_r_reg_n_0_[472] ;
  wire \mcal_DQIn_r_reg_n_0_[473] ;
  wire \mcal_DQIn_r_reg_n_0_[474] ;
  wire \mcal_DQIn_r_reg_n_0_[475] ;
  wire \mcal_DQIn_r_reg_n_0_[476] ;
  wire \mcal_DQIn_r_reg_n_0_[477] ;
  wire \mcal_DQIn_r_reg_n_0_[478] ;
  wire \mcal_DQIn_r_reg_n_0_[479] ;
  wire \mcal_DQIn_r_reg_n_0_[47] ;
  wire \mcal_DQIn_r_reg_n_0_[480] ;
  wire \mcal_DQIn_r_reg_n_0_[481] ;
  wire \mcal_DQIn_r_reg_n_0_[482] ;
  wire \mcal_DQIn_r_reg_n_0_[483] ;
  wire \mcal_DQIn_r_reg_n_0_[484] ;
  wire \mcal_DQIn_r_reg_n_0_[485] ;
  wire \mcal_DQIn_r_reg_n_0_[486] ;
  wire \mcal_DQIn_r_reg_n_0_[487] ;
  wire \mcal_DQIn_r_reg_n_0_[488] ;
  wire \mcal_DQIn_r_reg_n_0_[489] ;
  wire \mcal_DQIn_r_reg_n_0_[48] ;
  wire \mcal_DQIn_r_reg_n_0_[490] ;
  wire \mcal_DQIn_r_reg_n_0_[491] ;
  wire \mcal_DQIn_r_reg_n_0_[492] ;
  wire \mcal_DQIn_r_reg_n_0_[493] ;
  wire \mcal_DQIn_r_reg_n_0_[494] ;
  wire \mcal_DQIn_r_reg_n_0_[495] ;
  wire \mcal_DQIn_r_reg_n_0_[496] ;
  wire \mcal_DQIn_r_reg_n_0_[497] ;
  wire \mcal_DQIn_r_reg_n_0_[498] ;
  wire \mcal_DQIn_r_reg_n_0_[499] ;
  wire \mcal_DQIn_r_reg_n_0_[49] ;
  wire \mcal_DQIn_r_reg_n_0_[4] ;
  wire \mcal_DQIn_r_reg_n_0_[500] ;
  wire \mcal_DQIn_r_reg_n_0_[501] ;
  wire \mcal_DQIn_r_reg_n_0_[502] ;
  wire \mcal_DQIn_r_reg_n_0_[503] ;
  wire \mcal_DQIn_r_reg_n_0_[504] ;
  wire \mcal_DQIn_r_reg_n_0_[505] ;
  wire \mcal_DQIn_r_reg_n_0_[506] ;
  wire \mcal_DQIn_r_reg_n_0_[507] ;
  wire \mcal_DQIn_r_reg_n_0_[508] ;
  wire \mcal_DQIn_r_reg_n_0_[509] ;
  wire \mcal_DQIn_r_reg_n_0_[50] ;
  wire \mcal_DQIn_r_reg_n_0_[510] ;
  wire \mcal_DQIn_r_reg_n_0_[511] ;
  wire \mcal_DQIn_r_reg_n_0_[51] ;
  wire \mcal_DQIn_r_reg_n_0_[52] ;
  wire \mcal_DQIn_r_reg_n_0_[53] ;
  wire \mcal_DQIn_r_reg_n_0_[54] ;
  wire \mcal_DQIn_r_reg_n_0_[55] ;
  wire \mcal_DQIn_r_reg_n_0_[56] ;
  wire \mcal_DQIn_r_reg_n_0_[57] ;
  wire \mcal_DQIn_r_reg_n_0_[58] ;
  wire \mcal_DQIn_r_reg_n_0_[59] ;
  wire \mcal_DQIn_r_reg_n_0_[5] ;
  wire \mcal_DQIn_r_reg_n_0_[60] ;
  wire \mcal_DQIn_r_reg_n_0_[61] ;
  wire \mcal_DQIn_r_reg_n_0_[62] ;
  wire \mcal_DQIn_r_reg_n_0_[63] ;
  wire \mcal_DQIn_r_reg_n_0_[64] ;
  wire \mcal_DQIn_r_reg_n_0_[65] ;
  wire \mcal_DQIn_r_reg_n_0_[66] ;
  wire \mcal_DQIn_r_reg_n_0_[67] ;
  wire \mcal_DQIn_r_reg_n_0_[68] ;
  wire \mcal_DQIn_r_reg_n_0_[69] ;
  wire \mcal_DQIn_r_reg_n_0_[6] ;
  wire \mcal_DQIn_r_reg_n_0_[70] ;
  wire \mcal_DQIn_r_reg_n_0_[71] ;
  wire \mcal_DQIn_r_reg_n_0_[72] ;
  wire \mcal_DQIn_r_reg_n_0_[73] ;
  wire \mcal_DQIn_r_reg_n_0_[74] ;
  wire \mcal_DQIn_r_reg_n_0_[75] ;
  wire \mcal_DQIn_r_reg_n_0_[76] ;
  wire \mcal_DQIn_r_reg_n_0_[77] ;
  wire \mcal_DQIn_r_reg_n_0_[78] ;
  wire \mcal_DQIn_r_reg_n_0_[79] ;
  wire \mcal_DQIn_r_reg_n_0_[7] ;
  wire \mcal_DQIn_r_reg_n_0_[80] ;
  wire \mcal_DQIn_r_reg_n_0_[81] ;
  wire \mcal_DQIn_r_reg_n_0_[82] ;
  wire \mcal_DQIn_r_reg_n_0_[83] ;
  wire \mcal_DQIn_r_reg_n_0_[84] ;
  wire \mcal_DQIn_r_reg_n_0_[85] ;
  wire \mcal_DQIn_r_reg_n_0_[86] ;
  wire \mcal_DQIn_r_reg_n_0_[87] ;
  wire \mcal_DQIn_r_reg_n_0_[88] ;
  wire \mcal_DQIn_r_reg_n_0_[89] ;
  wire \mcal_DQIn_r_reg_n_0_[8] ;
  wire \mcal_DQIn_r_reg_n_0_[90] ;
  wire \mcal_DQIn_r_reg_n_0_[91] ;
  wire \mcal_DQIn_r_reg_n_0_[92] ;
  wire \mcal_DQIn_r_reg_n_0_[93] ;
  wire \mcal_DQIn_r_reg_n_0_[94] ;
  wire \mcal_DQIn_r_reg_n_0_[95] ;
  wire \mcal_DQIn_r_reg_n_0_[96] ;
  wire \mcal_DQIn_r_reg_n_0_[97] ;
  wire \mcal_DQIn_r_reg_n_0_[98] ;
  wire \mcal_DQIn_r_reg_n_0_[99] ;
  wire \mcal_DQIn_r_reg_n_0_[9] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[0] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[10] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[11] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[12] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[13] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[14] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[15] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[16] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[17] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[18] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[19] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[1] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[20] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[21] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[22] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[23] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[24] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[25] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[26] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[27] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[28] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[29] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[2] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[30] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[31] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[32] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[33] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[34] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[35] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[36] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[37] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[38] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[39] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[3] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[40] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[41] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[42] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[43] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[44] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[45] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[46] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[47] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[48] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[49] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[4] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[50] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[51] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[52] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[53] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[54] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[55] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[56] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[57] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[58] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[59] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[5] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[60] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[61] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[62] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[63] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[6] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[7] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[8] ;
  wire \mcal_DQIn_r_valid_reg_n_0_[9] ;
  wire \mcal_ODT_dly[0][4]_i_4_n_0 ;
  wire \mcal_ODT_dly_reg[0][4] ;
  wire \mcal_PAR_dly_reg[0][0] ;
  wire \mcal_PAR_dly_reg[0][1] ;
  wire \mcal_PAR_dly_reg[0][3] ;
  wire \mcal_PAR_dly_reg[0][5] ;
  wire \mcal_PAR_dly_reg[0][7] ;
  wire [63:0]mcal_dq_cmp;
  wire [63:0]mcal_dq_cmp0;
  wire \mcal_dq_cmp[63]_i_1_n_0 ;
  wire [47:32]mcal_dq_cmp_lrdimm;
  wire [55:0]mcal_rd_vref_value;
  wire mem_reg_bram_0;
  wire \odt_shift_reg[0][17] ;
  wire [7:0]p_0_in;
  wire p_0_in32_in;
  wire [7:0]p_0_in__0;
  wire [0:0]p_1_in;
  wire p_52_in;
  wire pllGate;
  wire rdCAS_i_3_n_0;
  wire rdCAS_reg_0;
  wire rdCAS_reg_1;
  wire rdDataEn_pi;
  wire rdEn_nxt_inferred_i_31__2_n_0;
  wire rdEn_nxt_inferred_i_33__2_n_0;
  wire rdEn_nxt_inferred_i_33__3_n_0;
  wire rdEn_nxt_inferred_i_34__3_n_0;
  wire rdEn_nxt_inferred_i_35__4_n_0;
  wire \rdEn_reg[28] ;
  wire \rdEn_reg[28]_0 ;
  wire \rdEn_reg[28]_1 ;
  wire \rdEn_reg[28]_10 ;
  wire \rdEn_reg[28]_11 ;
  wire \rdEn_reg[28]_12 ;
  wire \rdEn_reg[28]_2 ;
  wire \rdEn_reg[28]_3 ;
  wire \rdEn_reg[28]_4 ;
  wire \rdEn_reg[28]_5 ;
  wire \rdEn_reg[28]_6 ;
  wire \rdEn_reg[28]_7 ;
  wire \rdEn_reg[28]_8 ;
  wire \rdEn_reg[28]_9 ;
  wire \rdEn_reg[29] ;
  wire \rdEn_reg[29]_0 ;
  wire \rdEn_reg[29]_1 ;
  wire \rdEn_reg[29]_10 ;
  wire \rdEn_reg[29]_11 ;
  wire \rdEn_reg[29]_12 ;
  wire \rdEn_reg[29]_13 ;
  wire \rdEn_reg[29]_2 ;
  wire \rdEn_reg[29]_3 ;
  wire \rdEn_reg[29]_4 ;
  wire \rdEn_reg[29]_5 ;
  wire \rdEn_reg[29]_6 ;
  wire \rdEn_reg[29]_7 ;
  wire \rdEn_reg[29]_8 ;
  wire \rdEn_reg[29]_9 ;
  wire [7:0]rd_vref_value0_out;
  wire \rd_vref_value_reg[42]_0 ;
  wire \rd_vref_value_reg[43]_0 ;
  wire \rd_vref_value_reg[44]_0 ;
  wire \rd_vref_value_reg[45]_0 ;
  wire \rd_vref_value_reg[46]_0 ;
  wire \rd_vref_value_reg[48]_0 ;
  wire [1:0]\rsMask_reg[1]_71 ;
  wire [1:0]\rsMask_reg[1]_79 ;
  wire [1:0]\rsMask_reg[3]_73 ;
  wire [1:0]\rsMask_reg[3]_81 ;
  wire [1:0]\rsMask_reg[5]_75 ;
  wire [1:0]\rsMask_reg[5]_83 ;
  wire [1:0]\rsMask_reg[7][18] ;
  wire [1:0]\rsMask_reg[7]_77 ;
  wire [1:0]\rsMask_reg[7]_85 ;
  (* RTL_KEEP = "true" *) wire rst_r1;
  wire rst_r1_reg_0;
  wire [1:0]rst_r1_reg_1;
  wire [1:0]rst_r1_reg_10;
  wire [1:0]rst_r1_reg_11;
  wire [1:0]rst_r1_reg_12;
  wire [1:0]rst_r1_reg_13;
  wire [1:0]rst_r1_reg_14;
  wire [1:0]rst_r1_reg_2;
  wire [1:0]rst_r1_reg_3;
  wire [1:0]rst_r1_reg_4;
  wire [1:0]rst_r1_reg_5;
  wire [1:0]rst_r1_reg_6;
  wire [1:0]rst_r1_reg_7;
  wire [1:0]rst_r1_reg_8;
  wire [1:0]rst_r1_reg_9;
  wire seq_cnt_access;
  wire seq_cnt_access_i_1_n_0;
  wire seq_cnt_dec;
  wire seq_cnt_dec_i_1_n_0;
  wire stop_gate_tracking_ack_reg_0;
  wire stop_gate_tracking_ack_reg_1;
  wire traffic_clr_error_r1_reg_srl2_n_0;
  wire traffic_clr_error_r2;
  wire [0:0]\traffic_instr_nxt_instr_r1_reg[5]_0 ;
  wire \traffic_instr_nxt_instr_r1_reg_n_0_[0] ;
  wire \traffic_instr_nxt_instr_r1_reg_n_0_[1] ;
  wire \traffic_instr_nxt_instr_r1_reg_n_0_[2] ;
  wire \traffic_instr_nxt_instr_r1_reg_n_0_[3] ;
  wire \traffic_instr_nxt_instr_r1_reg_n_0_[4] ;
  wire \traffic_instr_nxt_instr_r1_reg_n_0_[5] ;
  wire u_ddr_cal_cplx_n_134;
  wire u_ddr_cal_cplx_n_136;
  wire [0:0]ub_cal_CKE;
  wire [7:0]ub_cal_ODT;
  wire [4:0]ub_cal_RESET_n;
  wire ub_initDone_reg_0;
  wire ub_initDone_reg_1;
  wire ub_ready;
  wire [2:0]ub_ready_reg_0;
  wire ub_ready_reg_1;
  wire \uppCL0[42]_i_3_n_0 ;
  wire \uppCL0[42]_i_4_n_0 ;
  wire \uppCL0[43]_i_3_n_0 ;
  wire \uppCL0[43]_i_4_n_0 ;
  wire \uppCL0[44]_i_3_n_0 ;
  wire \uppCL0[44]_i_4_n_0 ;
  wire \uppCL0[45]_i_3_n_0 ;
  wire \uppCL0[45]_i_4_n_0 ;
  wire \uppCL0[46]_i_3_n_0 ;
  wire \uppCL0[46]_i_4_n_0 ;
  wire \uppCL0[47]_i_3_n_0 ;
  wire \uppCL0[47]_i_4_n_0 ;
  wire [31:0]\uppCL0_reg[45]_0 ;
  wire [9:0]\uppCL0_reg[47]_0 ;
  wire \uppCL0_reg_n_0_[10] ;
  wire \uppCL0_reg_n_0_[11] ;
  wire \uppCL0_reg_n_0_[16] ;
  wire \uppCL0_reg_n_0_[17] ;
  wire \uppCL0_reg_n_0_[22] ;
  wire \uppCL0_reg_n_0_[23] ;
  wire \uppCL0_reg_n_0_[28] ;
  wire \uppCL0_reg_n_0_[29] ;
  wire \uppCL0_reg_n_0_[34] ;
  wire \uppCL0_reg_n_0_[35] ;
  wire \uppCL0_reg_n_0_[40] ;
  wire \uppCL0_reg_n_0_[41] ;
  wire \uppCL0_reg_n_0_[46] ;
  wire \uppCL0_reg_n_0_[47] ;
  wire \uppCL0_reg_n_0_[4] ;
  wire \uppCL0_reg_n_0_[5] ;
  wire \uppCL1[42]_i_3_n_0 ;
  wire \uppCL1[42]_i_4_n_0 ;
  wire \uppCL1[43]_i_3_n_0 ;
  wire \uppCL1[43]_i_4_n_0 ;
  wire \uppCL1[44]_i_3_n_0 ;
  wire \uppCL1[44]_i_4_n_0 ;
  wire \uppCL1[45]_i_3_n_0 ;
  wire \uppCL1[45]_i_4_n_0 ;
  wire \uppCL1[46]_i_3_n_0 ;
  wire \uppCL1[46]_i_4_n_0 ;
  wire \uppCL1[47]_i_3_n_0 ;
  wire \uppCL1[47]_i_4_n_0 ;
  wire [31:0]\uppCL1_reg[45]_0 ;
  wire [9:0]\uppCL1_reg[47]_0 ;
  wire \uppCL1_reg_n_0_[10] ;
  wire \uppCL1_reg_n_0_[11] ;
  wire \uppCL1_reg_n_0_[16] ;
  wire \uppCL1_reg_n_0_[17] ;
  wire \uppCL1_reg_n_0_[22] ;
  wire \uppCL1_reg_n_0_[23] ;
  wire \uppCL1_reg_n_0_[28] ;
  wire \uppCL1_reg_n_0_[29] ;
  wire \uppCL1_reg_n_0_[34] ;
  wire \uppCL1_reg_n_0_[35] ;
  wire \uppCL1_reg_n_0_[40] ;
  wire \uppCL1_reg_n_0_[41] ;
  wire \uppCL1_reg_n_0_[46] ;
  wire \uppCL1_reg_n_0_[47] ;
  wire \uppCL1_reg_n_0_[4] ;
  wire \uppCL1_reg_n_0_[5] ;
  wire \uppCL2[42]_i_3_n_0 ;
  wire \uppCL2[42]_i_4_n_0 ;
  wire \uppCL2[43]_i_3_n_0 ;
  wire \uppCL2[43]_i_4_n_0 ;
  wire \uppCL2[44]_i_3_n_0 ;
  wire \uppCL2[44]_i_4_n_0 ;
  wire \uppCL2[45]_i_3_n_0 ;
  wire \uppCL2[45]_i_4_n_0 ;
  wire \uppCL2[46]_i_3_n_0 ;
  wire \uppCL2[46]_i_4_n_0 ;
  wire \uppCL2[47]_i_3_n_0 ;
  wire \uppCL2[47]_i_4_n_0 ;
  wire [31:0]\uppCL2_reg[45]_0 ;
  wire [9:0]\uppCL2_reg[47]_0 ;
  wire \uppCL2_reg_n_0_[10] ;
  wire \uppCL2_reg_n_0_[11] ;
  wire \uppCL2_reg_n_0_[16] ;
  wire \uppCL2_reg_n_0_[17] ;
  wire \uppCL2_reg_n_0_[22] ;
  wire \uppCL2_reg_n_0_[23] ;
  wire \uppCL2_reg_n_0_[28] ;
  wire \uppCL2_reg_n_0_[29] ;
  wire \uppCL2_reg_n_0_[34] ;
  wire \uppCL2_reg_n_0_[35] ;
  wire \uppCL2_reg_n_0_[40] ;
  wire \uppCL2_reg_n_0_[41] ;
  wire \uppCL2_reg_n_0_[46] ;
  wire \uppCL2_reg_n_0_[47] ;
  wire \uppCL2_reg_n_0_[4] ;
  wire \uppCL2_reg_n_0_[5] ;
  wire \uppCL3[42]_i_3_n_0 ;
  wire \uppCL3[42]_i_4_n_0 ;
  wire \uppCL3[43]_i_3_n_0 ;
  wire \uppCL3[43]_i_4_n_0 ;
  wire \uppCL3[44]_i_3_n_0 ;
  wire \uppCL3[44]_i_4_n_0 ;
  wire \uppCL3[45]_i_3_n_0 ;
  wire \uppCL3[45]_i_4_n_0 ;
  wire \uppCL3[46]_i_3_n_0 ;
  wire \uppCL3[46]_i_4_n_0 ;
  wire \uppCL3[47]_i_3_n_0 ;
  wire \uppCL3[47]_i_4_n_0 ;
  wire [7:0]\uppCL3_reg[42]_0 ;
  wire [31:0]\uppCL3_reg[45]_0 ;
  wire [9:0]\uppCL3_reg[47]_0 ;
  wire \uppCL3_reg_n_0_[10] ;
  wire \uppCL3_reg_n_0_[11] ;
  wire \uppCL3_reg_n_0_[16] ;
  wire \uppCL3_reg_n_0_[17] ;
  wire \uppCL3_reg_n_0_[22] ;
  wire \uppCL3_reg_n_0_[23] ;
  wire \uppCL3_reg_n_0_[28] ;
  wire \uppCL3_reg_n_0_[29] ;
  wire \uppCL3_reg_n_0_[34] ;
  wire \uppCL3_reg_n_0_[35] ;
  wire \uppCL3_reg_n_0_[40] ;
  wire \uppCL3_reg_n_0_[41] ;
  wire \uppCL3_reg_n_0_[46] ;
  wire \uppCL3_reg_n_0_[47] ;
  wire \uppCL3_reg_n_0_[4] ;
  wire \uppCL3_reg_n_0_[5] ;
  wire wea;
  wire winAct;
  wire [1:0]winAct_reg;
  wire [2:1]wosp;
  wire \wosp_reg[1] ;
  wire \wosp_reg[1]_0 ;
  wire \wosp_reg[1]_1 ;
  wire \wosp_reg[1]_10 ;
  wire \wosp_reg[1]_100 ;
  wire \wosp_reg[1]_101 ;
  wire \wosp_reg[1]_102 ;
  wire \wosp_reg[1]_103 ;
  wire \wosp_reg[1]_104 ;
  wire \wosp_reg[1]_105 ;
  wire \wosp_reg[1]_106 ;
  wire \wosp_reg[1]_107 ;
  wire \wosp_reg[1]_108 ;
  wire \wosp_reg[1]_109 ;
  wire \wosp_reg[1]_11 ;
  wire \wosp_reg[1]_110 ;
  wire \wosp_reg[1]_111 ;
  wire \wosp_reg[1]_112 ;
  wire \wosp_reg[1]_113 ;
  wire \wosp_reg[1]_114 ;
  wire \wosp_reg[1]_115 ;
  wire \wosp_reg[1]_116 ;
  wire \wosp_reg[1]_117 ;
  wire \wosp_reg[1]_118 ;
  wire \wosp_reg[1]_119 ;
  wire \wosp_reg[1]_12 ;
  wire \wosp_reg[1]_120 ;
  wire \wosp_reg[1]_121 ;
  wire \wosp_reg[1]_122 ;
  wire \wosp_reg[1]_123 ;
  wire \wosp_reg[1]_124 ;
  wire \wosp_reg[1]_125 ;
  wire \wosp_reg[1]_126 ;
  wire \wosp_reg[1]_127 ;
  wire \wosp_reg[1]_128 ;
  wire \wosp_reg[1]_129 ;
  wire \wosp_reg[1]_13 ;
  wire \wosp_reg[1]_130 ;
  wire \wosp_reg[1]_131 ;
  wire \wosp_reg[1]_132 ;
  wire \wosp_reg[1]_133 ;
  wire \wosp_reg[1]_134 ;
  wire \wosp_reg[1]_135 ;
  wire \wosp_reg[1]_136 ;
  wire \wosp_reg[1]_137 ;
  wire \wosp_reg[1]_138 ;
  wire \wosp_reg[1]_139 ;
  wire \wosp_reg[1]_14 ;
  wire \wosp_reg[1]_140 ;
  wire \wosp_reg[1]_141 ;
  wire \wosp_reg[1]_142 ;
  wire \wosp_reg[1]_15 ;
  wire \wosp_reg[1]_16 ;
  wire \wosp_reg[1]_17 ;
  wire \wosp_reg[1]_18 ;
  wire \wosp_reg[1]_19 ;
  wire \wosp_reg[1]_2 ;
  wire \wosp_reg[1]_20 ;
  wire \wosp_reg[1]_21 ;
  wire \wosp_reg[1]_22 ;
  wire \wosp_reg[1]_23 ;
  wire \wosp_reg[1]_24 ;
  wire \wosp_reg[1]_25 ;
  wire \wosp_reg[1]_26 ;
  wire \wosp_reg[1]_27 ;
  wire \wosp_reg[1]_28 ;
  wire \wosp_reg[1]_29 ;
  wire \wosp_reg[1]_3 ;
  wire \wosp_reg[1]_30 ;
  wire \wosp_reg[1]_31 ;
  wire \wosp_reg[1]_32 ;
  wire \wosp_reg[1]_33 ;
  wire \wosp_reg[1]_34 ;
  wire \wosp_reg[1]_35 ;
  wire \wosp_reg[1]_36 ;
  wire \wosp_reg[1]_37 ;
  wire \wosp_reg[1]_38 ;
  wire \wosp_reg[1]_39 ;
  wire \wosp_reg[1]_4 ;
  wire \wosp_reg[1]_40 ;
  wire \wosp_reg[1]_41 ;
  wire \wosp_reg[1]_42 ;
  wire \wosp_reg[1]_43 ;
  wire \wosp_reg[1]_44 ;
  wire \wosp_reg[1]_45 ;
  wire \wosp_reg[1]_46 ;
  wire \wosp_reg[1]_47 ;
  wire \wosp_reg[1]_48 ;
  wire \wosp_reg[1]_49 ;
  wire \wosp_reg[1]_5 ;
  wire \wosp_reg[1]_50 ;
  wire \wosp_reg[1]_51 ;
  wire \wosp_reg[1]_52 ;
  wire \wosp_reg[1]_53 ;
  wire \wosp_reg[1]_54 ;
  wire \wosp_reg[1]_55 ;
  wire \wosp_reg[1]_56 ;
  wire \wosp_reg[1]_57 ;
  wire \wosp_reg[1]_58 ;
  wire \wosp_reg[1]_59 ;
  wire \wosp_reg[1]_6 ;
  wire \wosp_reg[1]_60 ;
  wire \wosp_reg[1]_61 ;
  wire \wosp_reg[1]_62 ;
  wire \wosp_reg[1]_63 ;
  wire \wosp_reg[1]_64 ;
  wire \wosp_reg[1]_65 ;
  wire \wosp_reg[1]_66 ;
  wire \wosp_reg[1]_67 ;
  wire \wosp_reg[1]_68 ;
  wire \wosp_reg[1]_69 ;
  wire \wosp_reg[1]_7 ;
  wire \wosp_reg[1]_70 ;
  wire \wosp_reg[1]_71 ;
  wire \wosp_reg[1]_72 ;
  wire \wosp_reg[1]_73 ;
  wire \wosp_reg[1]_74 ;
  wire \wosp_reg[1]_75 ;
  wire \wosp_reg[1]_76 ;
  wire \wosp_reg[1]_77 ;
  wire \wosp_reg[1]_78 ;
  wire \wosp_reg[1]_79 ;
  wire \wosp_reg[1]_8 ;
  wire \wosp_reg[1]_80 ;
  wire \wosp_reg[1]_81 ;
  wire \wosp_reg[1]_82 ;
  wire \wosp_reg[1]_83 ;
  wire \wosp_reg[1]_84 ;
  wire \wosp_reg[1]_85 ;
  wire \wosp_reg[1]_86 ;
  wire \wosp_reg[1]_87 ;
  wire \wosp_reg[1]_88 ;
  wire \wosp_reg[1]_89 ;
  wire \wosp_reg[1]_9 ;
  wire \wosp_reg[1]_90 ;
  wire \wosp_reg[1]_91 ;
  wire \wosp_reg[1]_92 ;
  wire \wosp_reg[1]_93 ;
  wire \wosp_reg[1]_94 ;
  wire \wosp_reg[1]_95 ;
  wire \wosp_reg[1]_96 ;
  wire \wosp_reg[1]_97 ;
  wire \wosp_reg[1]_98 ;
  wire \wosp_reg[1]_99 ;
  wire [1:0]\wosp_reg[2] ;
  wire \wosp_reg[2]_0 ;
  wire [1:0]\wosp_reg[2]_rep ;
  wire \wosp_reg[2]_rep_0 ;
  wire [1:0]\wosp_reg[2]_rep_1 ;
  wire \wosp_reg[2]_rep_2 ;
  wire [1:0]\wosp_reg[2]_rep_3 ;
  wire \wosp_reg[2]_rep_4 ;
  wire [1:0]\wosp_reg[2]_rep__0 ;
  wire \wosp_reg[2]_rep__0_0 ;
  wire [1:0]\wosp_reg[2]_rep__0_1 ;
  wire \wosp_reg[2]_rep__0_2 ;
  wire [1:0]\wosp_reg[2]_rep__0_3 ;
  wire \wosp_reg[2]_rep__0_4 ;
  wire [1:0]\wosp_reg[2]_rep__1 ;
  wire \wosp_reg[2]_rep__1_0 ;
  wire \wosp_reg[2]_rep__1_1 ;
  wire \wosp_reg[2]_rep__1_10 ;
  wire \wosp_reg[2]_rep__1_11 ;
  wire [1:0]\wosp_reg[2]_rep__1_12 ;
  wire \wosp_reg[2]_rep__1_13 ;
  wire [1:0]\wosp_reg[2]_rep__1_2 ;
  wire \wosp_reg[2]_rep__1_3 ;
  wire \wosp_reg[2]_rep__1_4 ;
  wire [1:0]\wosp_reg[2]_rep__1_5 ;
  wire \wosp_reg[2]_rep__1_6 ;
  wire \wosp_reg[2]_rep__1_7 ;
  wire [1:0]\wosp_reg[2]_rep__1_8 ;
  wire \wosp_reg[2]_rep__1_9 ;
  wire \wosp_reg[2]_rep__2 ;
  wire [1:0]\wosp_reg[2]_rep__2_0 ;
  wire \wosp_reg[2]_rep__2_1 ;
  wire \wosp_reg[2]_rep__2_10 ;
  wire [1:0]\wosp_reg[2]_rep__2_11 ;
  wire \wosp_reg[2]_rep__2_12 ;
  wire \wosp_reg[2]_rep__2_13 ;
  wire [1:0]\wosp_reg[2]_rep__2_14 ;
  wire \wosp_reg[2]_rep__2_15 ;
  wire \wosp_reg[2]_rep__2_16 ;
  wire [1:0]\wosp_reg[2]_rep__2_17 ;
  wire \wosp_reg[2]_rep__2_18 ;
  wire \wosp_reg[2]_rep__2_19 ;
  wire [1:0]\wosp_reg[2]_rep__2_2 ;
  wire [1:0]\wosp_reg[2]_rep__2_20 ;
  wire \wosp_reg[2]_rep__2_21 ;
  wire \wosp_reg[2]_rep__2_22 ;
  wire [1:0]\wosp_reg[2]_rep__2_23 ;
  wire \wosp_reg[2]_rep__2_24 ;
  wire \wosp_reg[2]_rep__2_25 ;
  wire [1:0]\wosp_reg[2]_rep__2_26 ;
  wire \wosp_reg[2]_rep__2_27 ;
  wire \wosp_reg[2]_rep__2_28 ;
  wire [1:0]\wosp_reg[2]_rep__2_29 ;
  wire \wosp_reg[2]_rep__2_3 ;
  wire \wosp_reg[2]_rep__2_30 ;
  wire \wosp_reg[2]_rep__2_31 ;
  wire [1:0]\wosp_reg[2]_rep__2_32 ;
  wire \wosp_reg[2]_rep__2_33 ;
  wire \wosp_reg[2]_rep__2_34 ;
  wire \wosp_reg[2]_rep__2_4 ;
  wire [1:0]\wosp_reg[2]_rep__2_5 ;
  wire \wosp_reg[2]_rep__2_6 ;
  wire \wosp_reg[2]_rep__2_7 ;
  wire [1:0]\wosp_reg[2]_rep__2_8 ;
  wire \wosp_reg[2]_rep__2_9 ;
  wire \wosp_reg[2]_rep__3 ;
  wire \wosp_reg[2]_rep__3_0 ;
  wire [1:0]\wosp_reg[2]_rep__3_1 ;
  wire [1:0]\wosp_reg[2]_rep__3_10 ;
  wire \wosp_reg[2]_rep__3_11 ;
  wire \wosp_reg[2]_rep__3_12 ;
  wire [1:0]\wosp_reg[2]_rep__3_13 ;
  wire \wosp_reg[2]_rep__3_14 ;
  wire \wosp_reg[2]_rep__3_15 ;
  wire [1:0]\wosp_reg[2]_rep__3_16 ;
  wire \wosp_reg[2]_rep__3_17 ;
  wire \wosp_reg[2]_rep__3_18 ;
  wire [1:0]\wosp_reg[2]_rep__3_19 ;
  wire \wosp_reg[2]_rep__3_2 ;
  wire \wosp_reg[2]_rep__3_20 ;
  wire \wosp_reg[2]_rep__3_21 ;
  wire [1:0]\wosp_reg[2]_rep__3_22 ;
  wire \wosp_reg[2]_rep__3_23 ;
  wire \wosp_reg[2]_rep__3_24 ;
  wire [1:0]\wosp_reg[2]_rep__3_25 ;
  wire \wosp_reg[2]_rep__3_26 ;
  wire \wosp_reg[2]_rep__3_27 ;
  wire [1:0]\wosp_reg[2]_rep__3_28 ;
  wire \wosp_reg[2]_rep__3_29 ;
  wire \wosp_reg[2]_rep__3_3 ;
  wire \wosp_reg[2]_rep__3_30 ;
  wire [1:0]\wosp_reg[2]_rep__3_31 ;
  wire \wosp_reg[2]_rep__3_32 ;
  wire \wosp_reg[2]_rep__3_33 ;
  wire [1:0]\wosp_reg[2]_rep__3_4 ;
  wire \wosp_reg[2]_rep__3_5 ;
  wire \wosp_reg[2]_rep__3_6 ;
  wire [1:0]\wosp_reg[2]_rep__3_7 ;
  wire \wosp_reg[2]_rep__3_8 ;
  wire \wosp_reg[2]_rep__3_9 ;
  wire \wosp_reg[2]_rep__4 ;
  wire [1:0]\wosp_reg[2]_rep__4_0 ;
  wire \wosp_reg[2]_rep__4_1 ;
  wire \wosp_reg[2]_rep__4_10 ;
  wire \wosp_reg[2]_rep__4_11 ;
  wire [1:0]\wosp_reg[2]_rep__4_12 ;
  wire \wosp_reg[2]_rep__4_13 ;
  wire \wosp_reg[2]_rep__4_14 ;
  wire [1:0]\wosp_reg[2]_rep__4_15 ;
  wire \wosp_reg[2]_rep__4_16 ;
  wire \wosp_reg[2]_rep__4_17 ;
  wire [1:0]\wosp_reg[2]_rep__4_18 ;
  wire \wosp_reg[2]_rep__4_19 ;
  wire \wosp_reg[2]_rep__4_2 ;
  wire \wosp_reg[2]_rep__4_20 ;
  wire [1:0]\wosp_reg[2]_rep__4_21 ;
  wire \wosp_reg[2]_rep__4_22 ;
  wire \wosp_reg[2]_rep__4_23 ;
  wire [1:0]\wosp_reg[2]_rep__4_24 ;
  wire \wosp_reg[2]_rep__4_25 ;
  wire \wosp_reg[2]_rep__4_26 ;
  wire [1:0]\wosp_reg[2]_rep__4_27 ;
  wire \wosp_reg[2]_rep__4_28 ;
  wire \wosp_reg[2]_rep__4_29 ;
  wire [1:0]\wosp_reg[2]_rep__4_3 ;
  wire [1:0]\wosp_reg[2]_rep__4_30 ;
  wire \wosp_reg[2]_rep__4_31 ;
  wire \wosp_reg[2]_rep__4_32 ;
  wire \wosp_reg[2]_rep__4_33 ;
  wire \wosp_reg[2]_rep__4_4 ;
  wire \wosp_reg[2]_rep__4_5 ;
  wire [1:0]\wosp_reg[2]_rep__4_6 ;
  wire \wosp_reg[2]_rep__4_7 ;
  wire \wosp_reg[2]_rep__4_8 ;
  wire [1:0]\wosp_reg[2]_rep__4_9 ;
  wire \wosp_reg[2]_rep__5 ;
  wire [1:0]\wosp_reg[2]_rep__5_0 ;
  wire \wosp_reg[2]_rep__5_1 ;
  wire \wosp_reg[2]_rep__5_10 ;
  wire \wosp_reg[2]_rep__5_11 ;
  wire [1:0]\wosp_reg[2]_rep__5_12 ;
  wire \wosp_reg[2]_rep__5_13 ;
  wire \wosp_reg[2]_rep__5_14 ;
  wire [1:0]\wosp_reg[2]_rep__5_15 ;
  wire \wosp_reg[2]_rep__5_16 ;
  wire \wosp_reg[2]_rep__5_17 ;
  wire [1:0]\wosp_reg[2]_rep__5_18 ;
  wire \wosp_reg[2]_rep__5_19 ;
  wire [1:0]\wosp_reg[2]_rep__5_2 ;
  wire \wosp_reg[2]_rep__5_20 ;
  wire [1:0]\wosp_reg[2]_rep__5_21 ;
  wire \wosp_reg[2]_rep__5_22 ;
  wire \wosp_reg[2]_rep__5_23 ;
  wire [1:0]\wosp_reg[2]_rep__5_24 ;
  wire \wosp_reg[2]_rep__5_25 ;
  wire \wosp_reg[2]_rep__5_26 ;
  wire [1:0]\wosp_reg[2]_rep__5_27 ;
  wire \wosp_reg[2]_rep__5_28 ;
  wire \wosp_reg[2]_rep__5_29 ;
  wire \wosp_reg[2]_rep__5_3 ;
  wire [1:0]\wosp_reg[2]_rep__5_30 ;
  wire \wosp_reg[2]_rep__5_31 ;
  wire \wosp_reg[2]_rep__5_32 ;
  wire \wosp_reg[2]_rep__5_33 ;
  wire \wosp_reg[2]_rep__5_4 ;
  wire \wosp_reg[2]_rep__5_5 ;
  wire [1:0]\wosp_reg[2]_rep__5_6 ;
  wire \wosp_reg[2]_rep__5_7 ;
  wire \wosp_reg[2]_rep__5_8 ;
  wire [1:0]\wosp_reg[2]_rep__5_9 ;
  wire \wosp_reg[2]_rep__6 ;
  wire [1:0]\wosp_reg[2]_rep__6_0 ;
  wire \wosp_reg[2]_rep__6_1 ;
  wire \wosp_reg[2]_rep__6_10 ;
  wire [1:0]\wosp_reg[2]_rep__6_11 ;
  wire \wosp_reg[2]_rep__6_12 ;
  wire \wosp_reg[2]_rep__6_13 ;
  wire [1:0]\wosp_reg[2]_rep__6_14 ;
  wire \wosp_reg[2]_rep__6_15 ;
  wire \wosp_reg[2]_rep__6_16 ;
  wire [1:0]\wosp_reg[2]_rep__6_17 ;
  wire \wosp_reg[2]_rep__6_18 ;
  wire \wosp_reg[2]_rep__6_19 ;
  wire [1:0]\wosp_reg[2]_rep__6_2 ;
  wire \wosp_reg[2]_rep__6_20 ;
  wire \wosp_reg[2]_rep__6_21 ;
  wire [1:0]\wosp_reg[2]_rep__6_22 ;
  wire \wosp_reg[2]_rep__6_23 ;
  wire \wosp_reg[2]_rep__6_24 ;
  wire [1:0]\wosp_reg[2]_rep__6_25 ;
  wire \wosp_reg[2]_rep__6_26 ;
  wire \wosp_reg[2]_rep__6_27 ;
  wire [1:0]\wosp_reg[2]_rep__6_28 ;
  wire \wosp_reg[2]_rep__6_29 ;
  wire \wosp_reg[2]_rep__6_3 ;
  wire \wosp_reg[2]_rep__6_30 ;
  wire [1:0]\wosp_reg[2]_rep__6_31 ;
  wire \wosp_reg[2]_rep__6_32 ;
  wire \wosp_reg[2]_rep__6_33 ;
  wire [1:0]\wosp_reg[2]_rep__6_34 ;
  wire \wosp_reg[2]_rep__6_35 ;
  wire \wosp_reg[2]_rep__6_36 ;
  wire [1:0]\wosp_reg[2]_rep__6_37 ;
  wire \wosp_reg[2]_rep__6_38 ;
  wire \wosp_reg[2]_rep__6_39 ;
  wire \wosp_reg[2]_rep__6_4 ;
  wire [1:0]\wosp_reg[2]_rep__6_40 ;
  wire \wosp_reg[2]_rep__6_41 ;
  wire \wosp_reg[2]_rep__6_42 ;
  wire [1:0]\wosp_reg[2]_rep__6_5 ;
  wire \wosp_reg[2]_rep__6_6 ;
  wire \wosp_reg[2]_rep__6_7 ;
  wire [1:0]\wosp_reg[2]_rep__6_8 ;
  wire \wosp_reg[2]_rep__6_9 ;
  wire [1:0]\wosp_reg[2]_rep__7 ;
  wire \wosp_reg[2]_rep__7_0 ;
  wire wrCAS_reg_0;
  wire wrDataEn_pi;
  wire wrDataVal;
  wire [0:0]\wrQ_nxt[1]_13 ;
  wire \wrQ_reg[1][0] ;
  wire wren;
  wire wren_reg_0;
  wire write_vref_mode_reg_n_0;
  wire wrlvl_mode;
  wire [8:0]\xsdb_wr_data_reg[8]_0 ;
  wire [0:0]xsdb_wr_en_reg_0;
  wire [7:6]\NLW_cal_seq_cnt_reg[31]_i_3_CO_UNCONNECTED ;
  wire [7:7]\NLW_cal_seq_cnt_reg[31]_i_3_O_UNCONNECTED ;

  assign out = rst_r1;
  LUT3 #(
    .INIT(8'h28)) 
    a_b_cmd_sel_i_1
       (.I0(\cal_seq_reg_n_0_[0] ),
        .I1(\cal_seq_cnt_reg[31]_0 [0]),
        .I2(a_b_cmd_sel_start_reg_0),
        .O(a_b_cmd_sel0));
  FDRE a_b_cmd_sel_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(a_b_cmd_sel0),
        .Q(a_b_cmd_sel),
        .R(rst_r1));
  FDRE a_b_cmd_sel_start_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(a_b_cmd_sel_start_reg_1),
        .Q(a_b_cmd_sel_start_reg_0),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h00000060)) 
    a_b_rd_sel_r_i_1
       (.I0(a_b_cmd_sel_start_reg_0),
        .I1(\cal_seq_rd_cnt_reg[7]_0 [0]),
        .I2(\cal_seq_reg_n_0_[0] ),
        .I3(cnt_clr_reg_0),
        .I4(rst_r1),
        .O(a_b_rd_sel_r_i_1_n_0));
  FDRE a_b_rd_sel_r_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(a_b_rd_sel_r_i_1_n_0),
        .Q(a_b_rd_sel_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h8B888BBB)) 
    \addr_dec_to_mb_data[0]_i_11 
       (.I0(\addr_dec_to_mb_data[0]_i_26_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[32]),
        .I3(io_address[0]),
        .I4(mcal_DQIn_byte_r1[0]),
        .O(\SYNC[5].sync_reg_reg[1]_16 ));
  LUT6 #(
    .INIT(64'hAFA0A0A0C0C0C0C0)) 
    \addr_dec_to_mb_data[0]_i_12 
       (.I0(\cal_ADR_A_reg_n_0_[0] ),
        .I1(\cal_ADR_B_reg_n_0_[0] ),
        .I2(\addr_dec_to_mb_data[0]_i_3 ),
        .I3(ub_cal_RESET_n[0]),
        .I4(io_address[6]),
        .I5(io_address[13]),
        .O(\cal_ADR_A_reg[0]_0 ));
  LUT4 #(
    .INIT(16'h4777)) 
    \addr_dec_to_mb_data[0]_i_25 
       (.I0(\cal_CS_A_reg_n_0_[0] ),
        .I1(io_address[13]),
        .I2(io_address[14]),
        .I3(\cal_CS_B_reg_n_0_[0] ),
        .O(\cal_CS_A_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h2EFF2E00)) 
    \addr_dec_to_mb_data[0]_i_26 
       (.I0(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg_n_0_[0] ),
        .I1(io_address[0]),
        .I2(mcal_dq_cmp_lrdimm[32]),
        .I3(lrdimm_cal_mode),
        .I4(\addr_dec_to_mb_data[0]_i_40_n_0 ),
        .O(\addr_dec_to_mb_data[0]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    \addr_dec_to_mb_data[0]_i_27 
       (.I0(\addr_dec_to_mb_data[6]_i_7 ),
        .I1(mcal_rd_vref_value[42]),
        .I2(\addr_dec_to_mb_data[6]_i_7_0 ),
        .I3(mcal_rd_vref_value[49]),
        .I4(\addr_dec_to_mb_data[0]_i_41_n_0 ),
        .I5(\addr_dec_to_mb_data[0]_i_42_n_0 ),
        .O(\rd_vref_value_reg[42]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \addr_dec_to_mb_data[0]_i_30 
       (.I0(\uppCL0[42]_i_4_n_0 ),
        .I1(\uppCL0[42]_i_3_n_0 ),
        .I2(io_address[0]),
        .I3(\lowCL0[42]_i_4_n_0 ),
        .I4(io_address[3]),
        .I5(\lowCL0[42]_i_3_n_0 ),
        .O(\SYNC[0].sync_reg_reg[1]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \addr_dec_to_mb_data[0]_i_33 
       (.I0(\cal_ADR_A_reg_n_0_[0] ),
        .I1(io_address[13]),
        .I2(\cal_ADR_B_reg_n_0_[0] ),
        .O(\cal_ADR_A_reg[0]_1 ));
  LUT5 #(
    .INIT(32'h707F7F7F)) 
    \addr_dec_to_mb_data[0]_i_40 
       (.I0(mcal_dq_cmp[32]),
        .I1(\cal_cmp_en_reg_n_0_[4] ),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp[0]),
        .I4(\cal_cmp_en_reg_n_0_[0] ),
        .O(\addr_dec_to_mb_data[0]_i_40_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000F0CCAA)) 
    \addr_dec_to_mb_data[0]_i_41 
       (.I0(mcal_rd_vref_value[0]),
        .I1(mcal_rd_vref_value[7]),
        .I2(mcal_rd_vref_value[14]),
        .I3(io_address[0]),
        .I4(io_address[1]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[0]_i_41_n_0 ));
  LUT6 #(
    .INIT(64'h00F000CCAA000000)) 
    \addr_dec_to_mb_data[0]_i_42 
       (.I0(mcal_rd_vref_value[21]),
        .I1(mcal_rd_vref_value[28]),
        .I2(mcal_rd_vref_value[35]),
        .I3(io_address[1]),
        .I4(io_address[0]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[0]_i_42_n_0 ));
  LUT5 #(
    .INIT(32'h8B888BBB)) 
    \addr_dec_to_mb_data[10]_i_11 
       (.I0(\addr_dec_to_mb_data[10]_i_13_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[42]),
        .I3(io_address[0]),
        .I4(mcal_DQIn_byte_r1[10]),
        .O(\SYNC[5].sync_reg_reg[1]_13 ));
  LUT5 #(
    .INIT(32'h2EFF2E00)) 
    \addr_dec_to_mb_data[10]_i_13 
       (.I0(\genblk6[10].mcal_DQ0In_lrdimm_or_r_reg_n_0_[10] ),
        .I1(io_address[0]),
        .I2(mcal_dq_cmp_lrdimm[42]),
        .I3(lrdimm_cal_mode),
        .I4(\addr_dec_to_mb_data[10]_i_14_n_0 ),
        .O(\addr_dec_to_mb_data[10]_i_13_n_0 ));
  LUT5 #(
    .INIT(32'h07F7F7F7)) 
    \addr_dec_to_mb_data[10]_i_14 
       (.I0(mcal_dq_cmp[10]),
        .I1(\cal_cmp_en_reg_n_0_[1] ),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp[42]),
        .I4(\cal_cmp_en_reg_n_0_[5] ),
        .O(\addr_dec_to_mb_data[10]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hDD0DDD0D0000DD0D)) 
    \addr_dec_to_mb_data[10]_i_8 
       (.I0(\cal_ADR_B_reg_n_0_[10] ),
        .I1(\addr_dec_to_mb_data_reg[29]_4 ),
        .I2(\cal_ADR_A_reg_n_0_[10] ),
        .I3(\addr_dec_to_mb_data_reg[29]_2 ),
        .I4(\cal_RST_CKE_ODT_PAR_reg_n_0_[10] ),
        .I5(\addr_dec_to_mb_data_reg[29]_3 ),
        .O(\cal_ADR_B_reg[10]_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \addr_dec_to_mb_data[11]_i_10 
       (.I0(\addr_dec_to_mb_data[11]_i_14_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[43]),
        .I3(io_address[0]),
        .I4(mcal_DQIn_byte_r1[11]),
        .O(\SYNC[5].sync_reg_reg[1]_12 ));
  LUT5 #(
    .INIT(32'hD1FFD100)) 
    \addr_dec_to_mb_data[11]_i_14 
       (.I0(\genblk6[11].mcal_DQ0In_lrdimm_or_r_reg_n_0_[11] ),
        .I1(io_address[0]),
        .I2(mcal_dq_cmp_lrdimm[43]),
        .I3(lrdimm_cal_mode),
        .I4(\addr_dec_to_mb_data[11]_i_15_n_0 ),
        .O(\addr_dec_to_mb_data[11]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'h8F808080)) 
    \addr_dec_to_mb_data[11]_i_15 
       (.I0(mcal_dq_cmp[43]),
        .I1(\cal_cmp_en_reg_n_0_[5] ),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp[11]),
        .I4(\cal_cmp_en_reg_n_0_[1] ),
        .O(\addr_dec_to_mb_data[11]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hDD0DDD0D0000DD0D)) 
    \addr_dec_to_mb_data[11]_i_8 
       (.I0(\cal_ADR_B_reg_n_0_[11] ),
        .I1(\addr_dec_to_mb_data_reg[29]_4 ),
        .I2(\cal_ADR_A_reg_n_0_[11] ),
        .I3(\addr_dec_to_mb_data_reg[29]_2 ),
        .I4(\cal_RST_CKE_ODT_PAR_reg_n_0_[11] ),
        .I5(\addr_dec_to_mb_data_reg[29]_3 ),
        .O(\cal_ADR_B_reg[11]_0 ));
  LUT5 #(
    .INIT(32'h2EFF2E00)) 
    \addr_dec_to_mb_data[12]_i_11 
       (.I0(\genblk6[12].mcal_DQ0In_lrdimm_or_r_reg_n_0_[12] ),
        .I1(io_address[0]),
        .I2(mcal_dq_cmp_lrdimm[44]),
        .I3(lrdimm_cal_mode),
        .I4(\addr_dec_to_mb_data[12]_i_12_n_0 ),
        .O(\addr_dec_to_mb_data[12]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'h07F7F7F7)) 
    \addr_dec_to_mb_data[12]_i_12 
       (.I0(mcal_dq_cmp[12]),
        .I1(\cal_cmp_en_reg_n_0_[1] ),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp[44]),
        .I4(\cal_cmp_en_reg_n_0_[5] ),
        .O(\addr_dec_to_mb_data[12]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hDD0DDD0D0000DD0D)) 
    \addr_dec_to_mb_data[12]_i_8 
       (.I0(\cal_ADR_B_reg_n_0_[12] ),
        .I1(\addr_dec_to_mb_data_reg[29]_4 ),
        .I2(\cal_ADR_A_reg_n_0_[12] ),
        .I3(\addr_dec_to_mb_data_reg[29]_2 ),
        .I4(\cal_RST_CKE_ODT_PAR_reg_n_0_[12] ),
        .I5(\addr_dec_to_mb_data_reg[29]_3 ),
        .O(\cal_ADR_B_reg[12]_0 ));
  LUT5 #(
    .INIT(32'h8B888BBB)) 
    \addr_dec_to_mb_data[12]_i_9 
       (.I0(\addr_dec_to_mb_data[12]_i_11_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[44]),
        .I3(io_address[0]),
        .I4(mcal_DQIn_byte_r1[12]),
        .O(\SYNC[5].sync_reg_reg[1]_11 ));
  LUT6 #(
    .INIT(64'hDD0DDD0D0000DD0D)) 
    \addr_dec_to_mb_data[13]_i_11 
       (.I0(\cal_ADR_B_reg_n_0_[13] ),
        .I1(\addr_dec_to_mb_data_reg[29]_4 ),
        .I2(\cal_ADR_A_reg_n_0_[13] ),
        .I3(\addr_dec_to_mb_data_reg[29]_2 ),
        .I4(\cal_RST_CKE_ODT_PAR_reg_n_0_[13] ),
        .I5(\addr_dec_to_mb_data_reg[29]_3 ),
        .O(\cal_ADR_B_reg[13]_0 ));
  LUT5 #(
    .INIT(32'h8B888BBB)) 
    \addr_dec_to_mb_data[13]_i_12 
       (.I0(\addr_dec_to_mb_data[13]_i_14_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[45]),
        .I3(io_address[0]),
        .I4(mcal_DQIn_byte_r1[13]),
        .O(\SYNC[5].sync_reg_reg[1]_10 ));
  LUT5 #(
    .INIT(32'h2EFF2E00)) 
    \addr_dec_to_mb_data[13]_i_14 
       (.I0(\genblk6[13].mcal_DQ0In_lrdimm_or_r_reg_n_0_[13] ),
        .I1(io_address[0]),
        .I2(mcal_dq_cmp_lrdimm[45]),
        .I3(lrdimm_cal_mode),
        .I4(\addr_dec_to_mb_data[13]_i_15_n_0 ),
        .O(\addr_dec_to_mb_data[13]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'h07F7F7F7)) 
    \addr_dec_to_mb_data[13]_i_15 
       (.I0(mcal_dq_cmp[13]),
        .I1(\cal_cmp_en_reg_n_0_[1] ),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp[45]),
        .I4(\cal_cmp_en_reg_n_0_[5] ),
        .O(\addr_dec_to_mb_data[13]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hAAABBBABFFFFFFFF)) 
    \addr_dec_to_mb_data[14]_i_2 
       (.I0(\addr_dec_to_mb_data[14]_i_6_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[14]),
        .I3(io_address[0]),
        .I4(mcal_DQIn_byte_r1[46]),
        .I5(\addr_dec_to_mb_data_reg[14]_0 ),
        .O(\SYNC[5].sync_reg_reg[1] ));
  LUT6 #(
    .INIT(64'h02A2A2A202A20202)) 
    \addr_dec_to_mb_data[14]_i_6 
       (.I0(io_address[5]),
        .I1(\addr_dec_to_mb_data[14]_i_9_n_0 ),
        .I2(lrdimm_cal_mode),
        .I3(mcal_dq_cmp_lrdimm[46]),
        .I4(io_address[0]),
        .I5(\genblk6[14].mcal_DQ0In_lrdimm_or_r_reg_n_0_[14] ),
        .O(\addr_dec_to_mb_data[14]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h8F808080)) 
    \addr_dec_to_mb_data[14]_i_9 
       (.I0(mcal_dq_cmp[46]),
        .I1(\cal_cmp_en_reg_n_0_[5] ),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp[14]),
        .I4(\cal_cmp_en_reg_n_0_[1] ),
        .O(\addr_dec_to_mb_data[14]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h8F808080)) 
    \addr_dec_to_mb_data[15]_i_12 
       (.I0(mcal_dq_cmp[47]),
        .I1(\cal_cmp_en_reg_n_0_[5] ),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp[15]),
        .I4(\cal_cmp_en_reg_n_0_[1] ),
        .O(\addr_dec_to_mb_data[15]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAAABBBABFFFFFFFF)) 
    \addr_dec_to_mb_data[15]_i_4 
       (.I0(\addr_dec_to_mb_data[15]_i_8_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[15]),
        .I3(io_address[0]),
        .I4(mcal_DQIn_byte_r1[47]),
        .I5(\addr_dec_to_mb_data_reg[14]_0 ),
        .O(\SYNC[5].sync_reg_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h02A2A2A202A20202)) 
    \addr_dec_to_mb_data[15]_i_8 
       (.I0(io_address[5]),
        .I1(\addr_dec_to_mb_data[15]_i_12_n_0 ),
        .I2(lrdimm_cal_mode),
        .I3(mcal_dq_cmp_lrdimm[47]),
        .I4(io_address[0]),
        .I5(\genblk6[15].mcal_DQ0In_lrdimm_or_r_reg_n_0_[15] ),
        .O(\addr_dec_to_mb_data[15]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hDD0DDD0D0000DD0D)) 
    \addr_dec_to_mb_data[15]_i_9 
       (.I0(\cal_ADR_B_reg_n_0_[15] ),
        .I1(\addr_dec_to_mb_data_reg[29]_4 ),
        .I2(\cal_ADR_A_reg_n_0_[15] ),
        .I3(\addr_dec_to_mb_data_reg[29]_2 ),
        .I4(\cal_RST_CKE_ODT_PAR_reg_n_0_[15] ),
        .I5(\addr_dec_to_mb_data_reg[29]_3 ),
        .O(\cal_ADR_B_reg[15]_0 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[16]_i_10 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[2] ),
        .I2(mcal_dq_cmp[16]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[6] ),
        .I5(mcal_dq_cmp[48]),
        .O(lrdimm_cal_mode_reg_0));
  LUT6 #(
    .INIT(64'hD0DD0000D0DDD0DD)) 
    \addr_dec_to_mb_data[16]_i_9 
       (.I0(ub_cal_CKE),
        .I1(\addr_dec_to_mb_data_reg[29]_3 ),
        .I2(\addr_dec_to_mb_data_reg[29]_2 ),
        .I3(\cal_ADR_A_reg_n_0_[16] ),
        .I4(\addr_dec_to_mb_data_reg[29]_4 ),
        .I5(\cal_ADR_B_reg_n_0_[16] ),
        .O(\cal_RST_CKE_ODT_PAR_reg[16]_1 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[17]_i_10 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[2] ),
        .I2(mcal_dq_cmp[17]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[6] ),
        .I5(mcal_dq_cmp[49]),
        .O(\addr_dec_to_mb_data[17]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hDD0DDD0D0000DD0D)) 
    \addr_dec_to_mb_data[17]_i_8 
       (.I0(\cal_ADR_B_reg_n_0_[17] ),
        .I1(\addr_dec_to_mb_data_reg[29]_4 ),
        .I2(\cal_ADR_A_reg_n_0_[17] ),
        .I3(\addr_dec_to_mb_data_reg[29]_2 ),
        .I4(\cal_RST_CKE_ODT_PAR_reg_n_0_[17] ),
        .I5(\addr_dec_to_mb_data_reg[29]_3 ),
        .O(\cal_ADR_B_reg[17]_0 ));
  LUT5 #(
    .INIT(32'h88BB8B8B)) 
    \addr_dec_to_mb_data[17]_i_9 
       (.I0(\addr_dec_to_mb_data[17]_i_10_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[17]),
        .I3(mcal_DQIn_byte_r1[49]),
        .I4(io_address[0]),
        .O(\SYNC[5].sync_reg_reg[1]_9 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[18]_i_10 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[2] ),
        .I2(mcal_dq_cmp[18]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[6] ),
        .I5(mcal_dq_cmp[50]),
        .O(\addr_dec_to_mb_data[18]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hDD0DDD0D0000DD0D)) 
    \addr_dec_to_mb_data[18]_i_8 
       (.I0(\cal_ADR_B_reg_n_0_[18] ),
        .I1(\addr_dec_to_mb_data_reg[29]_4 ),
        .I2(\cal_ADR_A_reg_n_0_[18] ),
        .I3(\addr_dec_to_mb_data_reg[29]_2 ),
        .I4(\cal_RST_CKE_ODT_PAR_reg_n_0_[18] ),
        .I5(\addr_dec_to_mb_data_reg[29]_3 ),
        .O(\cal_ADR_B_reg[18]_0 ));
  LUT5 #(
    .INIT(32'h88BB8B8B)) 
    \addr_dec_to_mb_data[18]_i_9 
       (.I0(\addr_dec_to_mb_data[18]_i_10_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[18]),
        .I3(mcal_DQIn_byte_r1[50]),
        .I4(io_address[0]),
        .O(\SYNC[5].sync_reg_reg[1]_8 ));
  LUT6 #(
    .INIT(64'hDD0DDD0D0000DD0D)) 
    \addr_dec_to_mb_data[19]_i_12 
       (.I0(\cal_ADR_B_reg_n_0_[19] ),
        .I1(\addr_dec_to_mb_data_reg[29]_4 ),
        .I2(\cal_ADR_A_reg_n_0_[19] ),
        .I3(\addr_dec_to_mb_data_reg[29]_2 ),
        .I4(\cal_RST_CKE_ODT_PAR_reg_n_0_[19] ),
        .I5(\addr_dec_to_mb_data_reg[29]_3 ),
        .O(\cal_ADR_B_reg[19]_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \addr_dec_to_mb_data[19]_i_15 
       (.I0(\addr_dec_to_mb_data[19]_i_17_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[51]),
        .I3(io_address[0]),
        .I4(mcal_DQIn_byte_r1[19]),
        .O(\SYNC[5].sync_reg_reg[1]_7 ));
  LUT6 #(
    .INIT(64'h00000000F8080808)) 
    \addr_dec_to_mb_data[19]_i_17 
       (.I0(\cal_cmp_en_reg_n_0_[2] ),
        .I1(mcal_dq_cmp[19]),
        .I2(io_address[0]),
        .I3(\cal_cmp_en_reg_n_0_[6] ),
        .I4(mcal_dq_cmp[51]),
        .I5(lrdimm_cal_mode),
        .O(\addr_dec_to_mb_data[19]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h8888888080808880)) 
    \addr_dec_to_mb_data[1]_i_11 
       (.I0(\addr_dec_to_mb_data[1]_i_20_n_0 ),
        .I1(io_address[11]),
        .I2(io_address[5]),
        .I3(mcal_DQIn_byte_r1[1]),
        .I4(io_address[0]),
        .I5(mcal_DQIn_byte_r1[33]),
        .O(\SYNC[18].sync_reg_reg[1] ));
  LUT6 #(
    .INIT(64'hFF470000FF47FF47)) 
    \addr_dec_to_mb_data[1]_i_19 
       (.I0(\cal_ADR_A_reg[30]_0 [0]),
        .I1(io_address[10]),
        .I2(\cal_RST_CKE_ODT_PAR_reg[30]_0 [0]),
        .I3(\addr_dec_to_mb_data[4]_i_11 ),
        .I4(\addr_dec_to_mb_data_reg[29]_4 ),
        .I5(\cal_ADR_B_reg[30]_0 [0]),
        .O(\cal_ADR_A_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hD555D5DDFFFFFFFF)) 
    \addr_dec_to_mb_data[1]_i_20 
       (.I0(io_address[5]),
        .I1(lrdimm_cal_mode),
        .I2(mcal_dq_cmp_lrdimm[33]),
        .I3(io_address[0]),
        .I4(\genblk6[1].mcal_DQ0In_lrdimm_or_r_reg_n_0_[1] ),
        .I5(\addr_dec_to_mb_data[1]_i_25_n_0 ),
        .O(\addr_dec_to_mb_data[1]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    \addr_dec_to_mb_data[1]_i_21 
       (.I0(\addr_dec_to_mb_data[6]_i_7 ),
        .I1(mcal_rd_vref_value[43]),
        .I2(\addr_dec_to_mb_data[6]_i_7_0 ),
        .I3(mcal_rd_vref_value[50]),
        .I4(\addr_dec_to_mb_data[1]_i_26_n_0 ),
        .I5(\addr_dec_to_mb_data[1]_i_27_n_0 ),
        .O(\rd_vref_value_reg[43]_0 ));
  LUT6 #(
    .INIT(64'hABBBEFFFEFFFEFFF)) 
    \addr_dec_to_mb_data[1]_i_25 
       (.I0(lrdimm_cal_mode),
        .I1(io_address[0]),
        .I2(\cal_cmp_en_reg_n_0_[0] ),
        .I3(mcal_dq_cmp[1]),
        .I4(\cal_cmp_en_reg_n_0_[4] ),
        .I5(mcal_dq_cmp[33]),
        .O(\addr_dec_to_mb_data[1]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000F0CCAA)) 
    \addr_dec_to_mb_data[1]_i_26 
       (.I0(mcal_rd_vref_value[1]),
        .I1(mcal_rd_vref_value[8]),
        .I2(mcal_rd_vref_value[15]),
        .I3(io_address[0]),
        .I4(io_address[1]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[1]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'h00F000CCAA000000)) 
    \addr_dec_to_mb_data[1]_i_27 
       (.I0(mcal_rd_vref_value[22]),
        .I1(mcal_rd_vref_value[29]),
        .I2(mcal_rd_vref_value[36]),
        .I3(io_address[1]),
        .I4(io_address[0]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[1]_i_27_n_0 ));
  LUT6 #(
    .INIT(64'hD0DD0000D0DDD0DD)) 
    \addr_dec_to_mb_data[20]_i_6 
       (.I0(\cal_ADR_A_reg_n_0_[20] ),
        .I1(\addr_dec_to_mb_data_reg[29]_2 ),
        .I2(\addr_dec_to_mb_data_reg[29]_3 ),
        .I3(\cal_RST_CKE_ODT_PAR_reg_n_0_[20] ),
        .I4(\addr_dec_to_mb_data_reg[29]_4 ),
        .I5(\cal_ADR_B_reg_n_0_[20] ),
        .O(\cal_ADR_A_reg[20]_0 ));
  LUT5 #(
    .INIT(32'h88BB8B8B)) 
    \addr_dec_to_mb_data[20]_i_7 
       (.I0(\addr_dec_to_mb_data[20]_i_9_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[20]),
        .I3(mcal_DQIn_byte_r1[52]),
        .I4(io_address[0]),
        .O(\SYNC[5].sync_reg_reg[1]_6 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[20]_i_9 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[2] ),
        .I2(mcal_dq_cmp[20]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[6] ),
        .I5(mcal_dq_cmp[52]),
        .O(\addr_dec_to_mb_data[20]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h22F222F2FFFF22F2)) 
    \addr_dec_to_mb_data[21]_i_3 
       (.I0(\cal_ADR_A_reg_n_0_[21] ),
        .I1(\addr_dec_to_mb_data_reg[29]_2 ),
        .I2(\cal_RST_CKE_ODT_PAR_reg_n_0_[21] ),
        .I3(\addr_dec_to_mb_data_reg[29]_3 ),
        .I4(\cal_ADR_B_reg_n_0_[21] ),
        .I5(\addr_dec_to_mb_data_reg[29]_4 ),
        .O(\cal_ADR_A_reg[21]_0 ));
  LUT4 #(
    .INIT(16'hD0DD)) 
    \addr_dec_to_mb_data[21]_i_4 
       (.I0(cal_timer_reg[21]),
        .I1(\addr_dec_to_mb_data_reg[29]_0 ),
        .I2(\addr_dec_to_mb_data[21]_i_6_n_0 ),
        .I3(\addr_dec_to_mb_data_reg[29]_1 ),
        .O(\cal_timer_reg[21]_0 ));
  LUT5 #(
    .INIT(32'h88BB8B8B)) 
    \addr_dec_to_mb_data[21]_i_6 
       (.I0(\addr_dec_to_mb_data[21]_i_8_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[21]),
        .I3(mcal_DQIn_byte_r1[53]),
        .I4(io_address[0]),
        .O(\addr_dec_to_mb_data[21]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[21]_i_8 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[2] ),
        .I2(mcal_dq_cmp[21]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[6] ),
        .I5(mcal_dq_cmp[53]),
        .O(\addr_dec_to_mb_data[21]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'h88BB8B8B)) 
    \addr_dec_to_mb_data[22]_i_2 
       (.I0(\addr_dec_to_mb_data[22]_i_4_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[22]),
        .I3(mcal_DQIn_byte_r1[54]),
        .I4(io_address[0]),
        .O(\SYNC[5].sync_reg_reg[1]_5 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[22]_i_4 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[2] ),
        .I2(mcal_dq_cmp[22]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[6] ),
        .I5(mcal_dq_cmp[54]),
        .O(\addr_dec_to_mb_data[22]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h553F)) 
    \addr_dec_to_mb_data[22]_i_8 
       (.I0(\cal_ADR_A_reg_n_0_[22] ),
        .I1(io_address[6]),
        .I2(\cal_RST_CKE_ODT_PAR_reg_n_0_[22] ),
        .I3(io_address[10]),
        .O(\cal_ADR_A_reg[22]_0 ));
  LUT5 #(
    .INIT(32'h88BB8B8B)) 
    \addr_dec_to_mb_data[23]_i_2 
       (.I0(\addr_dec_to_mb_data[23]_i_4_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[23]),
        .I3(mcal_DQIn_byte_r1[55]),
        .I4(io_address[0]),
        .O(\SYNC[5].sync_reg_reg[1]_4 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[23]_i_4 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[2] ),
        .I2(mcal_dq_cmp[23]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[6] ),
        .I5(mcal_dq_cmp[55]),
        .O(\addr_dec_to_mb_data[23]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hD0DD)) 
    \addr_dec_to_mb_data[24]_i_4 
       (.I0(cal_timer_reg[24]),
        .I1(\addr_dec_to_mb_data_reg[29]_0 ),
        .I2(\addr_dec_to_mb_data[24]_i_7_n_0 ),
        .I3(\addr_dec_to_mb_data_reg[29]_1 ),
        .O(\cal_timer_reg[24]_0 ));
  LUT6 #(
    .INIT(64'hDD0DDD0D0000DD0D)) 
    \addr_dec_to_mb_data[24]_i_6 
       (.I0(\cal_ADR_B_reg_n_0_[24] ),
        .I1(\addr_dec_to_mb_data_reg[29]_4 ),
        .I2(\cal_ADR_A_reg_n_0_[24] ),
        .I3(\addr_dec_to_mb_data_reg[29]_2 ),
        .I4(\cal_RST_CKE_ODT_PAR_reg_n_0_[24] ),
        .I5(\addr_dec_to_mb_data_reg[29]_3 ),
        .O(\cal_ADR_B_reg[24]_0 ));
  LUT5 #(
    .INIT(32'h88BB8B8B)) 
    \addr_dec_to_mb_data[24]_i_7 
       (.I0(\addr_dec_to_mb_data[24]_i_9_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[24]),
        .I3(mcal_DQIn_byte_r1[56]),
        .I4(io_address[0]),
        .O(\addr_dec_to_mb_data[24]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[24]_i_9 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[3] ),
        .I2(mcal_dq_cmp[24]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[7] ),
        .I5(mcal_dq_cmp[56]),
        .O(\addr_dec_to_mb_data[24]_i_9_n_0 ));
  LUT4 #(
    .INIT(16'hD0DD)) 
    \addr_dec_to_mb_data[25]_i_4 
       (.I0(cal_timer_reg[25]),
        .I1(\addr_dec_to_mb_data_reg[29]_0 ),
        .I2(\addr_dec_to_mb_data[25]_i_7_n_0 ),
        .I3(\addr_dec_to_mb_data_reg[29]_1 ),
        .O(\cal_timer_reg[25]_0 ));
  LUT6 #(
    .INIT(64'hDD0DDD0D0000DD0D)) 
    \addr_dec_to_mb_data[25]_i_6 
       (.I0(\cal_ADR_B_reg_n_0_[25] ),
        .I1(\addr_dec_to_mb_data_reg[29]_4 ),
        .I2(\cal_ADR_A_reg_n_0_[25] ),
        .I3(\addr_dec_to_mb_data_reg[29]_2 ),
        .I4(\cal_RST_CKE_ODT_PAR_reg_n_0_[25] ),
        .I5(\addr_dec_to_mb_data_reg[29]_3 ),
        .O(\cal_ADR_B_reg[25]_0 ));
  LUT5 #(
    .INIT(32'h88BB8B8B)) 
    \addr_dec_to_mb_data[25]_i_7 
       (.I0(\addr_dec_to_mb_data[25]_i_9_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[25]),
        .I3(mcal_DQIn_byte_r1[57]),
        .I4(io_address[0]),
        .O(\addr_dec_to_mb_data[25]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[25]_i_9 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[3] ),
        .I2(mcal_dq_cmp[25]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[7] ),
        .I5(mcal_dq_cmp[57]),
        .O(\addr_dec_to_mb_data[25]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hD0DD0000D0DDD0DD)) 
    \addr_dec_to_mb_data[26]_i_6 
       (.I0(\cal_ADR_A_reg_n_0_[26] ),
        .I1(\addr_dec_to_mb_data_reg[29]_2 ),
        .I2(\addr_dec_to_mb_data_reg[29]_3 ),
        .I3(\cal_RST_CKE_ODT_PAR_reg_n_0_[26] ),
        .I4(\addr_dec_to_mb_data_reg[29]_4 ),
        .I5(\cal_ADR_B_reg_n_0_[26] ),
        .O(\cal_ADR_A_reg[26]_0 ));
  LUT5 #(
    .INIT(32'h88BB8B8B)) 
    \addr_dec_to_mb_data[26]_i_7 
       (.I0(\addr_dec_to_mb_data[26]_i_9_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[26]),
        .I3(mcal_DQIn_byte_r1[58]),
        .I4(io_address[0]),
        .O(\SYNC[5].sync_reg_reg[1]_3 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[26]_i_9 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[3] ),
        .I2(mcal_dq_cmp[26]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[7] ),
        .I5(mcal_dq_cmp[58]),
        .O(\addr_dec_to_mb_data[26]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[27]_i_10 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[3] ),
        .I2(mcal_dq_cmp[27]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[7] ),
        .I5(mcal_dq_cmp[59]),
        .O(\addr_dec_to_mb_data[27]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hD0DD0000D0DDD0DD)) 
    \addr_dec_to_mb_data[27]_i_7 
       (.I0(\cal_ADR_A_reg_n_0_[27] ),
        .I1(\addr_dec_to_mb_data_reg[29]_2 ),
        .I2(\addr_dec_to_mb_data_reg[29]_3 ),
        .I3(\cal_RST_CKE_ODT_PAR_reg_n_0_[27] ),
        .I4(\addr_dec_to_mb_data_reg[29]_4 ),
        .I5(\cal_ADR_B_reg_n_0_[27] ),
        .O(\cal_ADR_A_reg[27]_0 ));
  LUT5 #(
    .INIT(32'h88BB8B8B)) 
    \addr_dec_to_mb_data[27]_i_8 
       (.I0(\addr_dec_to_mb_data[27]_i_10_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[27]),
        .I3(mcal_DQIn_byte_r1[59]),
        .I4(io_address[0]),
        .O(\SYNC[5].sync_reg_reg[1]_2 ));
  LUT4 #(
    .INIT(16'hD0DD)) 
    \addr_dec_to_mb_data[28]_i_4 
       (.I0(cal_timer_reg[28]),
        .I1(\addr_dec_to_mb_data_reg[29]_0 ),
        .I2(\addr_dec_to_mb_data[28]_i_6_n_0 ),
        .I3(\addr_dec_to_mb_data_reg[29]_1 ),
        .O(\cal_timer_reg[28]_0 ));
  LUT5 #(
    .INIT(32'h88BB8B8B)) 
    \addr_dec_to_mb_data[28]_i_6 
       (.I0(\addr_dec_to_mb_data[28]_i_8_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[28]),
        .I3(mcal_DQIn_byte_r1[60]),
        .I4(io_address[0]),
        .O(\addr_dec_to_mb_data[28]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[28]_i_8 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[3] ),
        .I2(mcal_dq_cmp[28]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[7] ),
        .I5(mcal_dq_cmp[60]),
        .O(\addr_dec_to_mb_data[28]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'h88BB8B8B)) 
    \addr_dec_to_mb_data[29]_i_12 
       (.I0(\addr_dec_to_mb_data[29]_i_14_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[29]),
        .I3(mcal_DQIn_byte_r1[61]),
        .I4(io_address[0]),
        .O(\addr_dec_to_mb_data[29]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[29]_i_14 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[3] ),
        .I2(mcal_dq_cmp[29]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[7] ),
        .I5(mcal_dq_cmp[61]),
        .O(\addr_dec_to_mb_data[29]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hD0DD0000D0DDD0DD)) 
    \addr_dec_to_mb_data[29]_i_4 
       (.I0(\cal_ADR_A_reg_n_0_[29] ),
        .I1(\addr_dec_to_mb_data_reg[29]_2 ),
        .I2(\addr_dec_to_mb_data_reg[29]_3 ),
        .I3(\cal_RST_CKE_ODT_PAR_reg_n_0_[29] ),
        .I4(\addr_dec_to_mb_data_reg[29]_4 ),
        .I5(\cal_ADR_B_reg_n_0_[29] ),
        .O(\cal_ADR_A_reg[29]_0 ));
  LUT4 #(
    .INIT(16'hD0DD)) 
    \addr_dec_to_mb_data[29]_i_6 
       (.I0(cal_timer_reg[29]),
        .I1(\addr_dec_to_mb_data_reg[29]_0 ),
        .I2(\addr_dec_to_mb_data[29]_i_12_n_0 ),
        .I3(\addr_dec_to_mb_data_reg[29]_1 ),
        .O(\cal_timer_reg[29]_0 ));
  LUT6 #(
    .INIT(64'h0888088888880088)) 
    \addr_dec_to_mb_data[2]_i_30 
       (.I0(\addr_dec_to_mb_data[2]_i_38_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_dq_cmp_lrdimm[34]),
        .I3(lrdimm_cal_mode),
        .I4(\genblk6[2].mcal_DQ0In_lrdimm_or_r_reg_n_0_[2] ),
        .I5(io_address[0]),
        .O(\SYNC[5].sync_reg_reg[1]_15 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    \addr_dec_to_mb_data[2]_i_31 
       (.I0(\addr_dec_to_mb_data[6]_i_7 ),
        .I1(mcal_rd_vref_value[44]),
        .I2(\addr_dec_to_mb_data[6]_i_7_0 ),
        .I3(mcal_rd_vref_value[51]),
        .I4(\addr_dec_to_mb_data[2]_i_39_n_0 ),
        .I5(\addr_dec_to_mb_data[2]_i_40_n_0 ),
        .O(\rd_vref_value_reg[44]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \addr_dec_to_mb_data[2]_i_37 
       (.I0(\cal_ADR_A_reg[30]_0 [1]),
        .I1(io_address[10]),
        .I2(\cal_RST_CKE_ODT_PAR_reg[30]_0 [1]),
        .O(\cal_ADR_A_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hABBBEFFFEFFFEFFF)) 
    \addr_dec_to_mb_data[2]_i_38 
       (.I0(lrdimm_cal_mode),
        .I1(io_address[0]),
        .I2(\cal_cmp_en_reg_n_0_[0] ),
        .I3(mcal_dq_cmp[2]),
        .I4(\cal_cmp_en_reg_n_0_[4] ),
        .I5(mcal_dq_cmp[34]),
        .O(\addr_dec_to_mb_data[2]_i_38_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000F0CCAA)) 
    \addr_dec_to_mb_data[2]_i_39 
       (.I0(mcal_rd_vref_value[2]),
        .I1(mcal_rd_vref_value[9]),
        .I2(mcal_rd_vref_value[16]),
        .I3(io_address[0]),
        .I4(io_address[1]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[2]_i_39_n_0 ));
  LUT6 #(
    .INIT(64'h00F000CCAA000000)) 
    \addr_dec_to_mb_data[2]_i_40 
       (.I0(mcal_rd_vref_value[23]),
        .I1(mcal_rd_vref_value[30]),
        .I2(mcal_rd_vref_value[37]),
        .I3(io_address[1]),
        .I4(io_address[0]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[2]_i_40_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \addr_dec_to_mb_data[30]_i_5 
       (.I0(\addr_dec_to_mb_data[30]_i_7_n_0 ),
        .I1(io_address[5]),
        .I2(mcal_DQIn_byte_r1[62]),
        .I3(io_address[0]),
        .I4(mcal_DQIn_byte_r1[30]),
        .O(\SYNC[5].sync_reg_reg[1]_1 ));
  LUT6 #(
    .INIT(64'h00000000F8080808)) 
    \addr_dec_to_mb_data[30]_i_7 
       (.I0(\cal_cmp_en_reg_n_0_[3] ),
        .I1(mcal_dq_cmp[30]),
        .I2(io_address[0]),
        .I3(\cal_cmp_en_reg_n_0_[7] ),
        .I4(mcal_dq_cmp[62]),
        .I5(lrdimm_cal_mode),
        .O(\addr_dec_to_mb_data[30]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hB833B800)) 
    \addr_dec_to_mb_data[31]_i_11 
       (.I0(\cal_ADR_B_reg_n_0_[31] ),
        .I1(\addr_dec_to_mb_data[31]_i_3 ),
        .I2(\cal_ADR_A_reg_n_0_[31] ),
        .I3(io_address[10]),
        .I4(\cal_RST_CKE_ODT_PAR_reg_n_0_[31] ),
        .O(\cal_ADR_B_reg[31]_0 ));
  LUT6 #(
    .INIT(64'hFFE200E200000000)) 
    \addr_dec_to_mb_data[31]_i_2 
       (.I0(mcal_DQIn_byte_r1[31]),
        .I1(io_address[0]),
        .I2(mcal_DQIn_byte_r1[63]),
        .I3(io_address[5]),
        .I4(\addr_dec_to_mb_data[31]_i_7_n_0 ),
        .I5(\addr_dec_to_mb_data_reg[14]_0 ),
        .O(\mcal_DQIn_byte_r1_reg[31]_0 ));
  LUT6 #(
    .INIT(64'h00000000F8080808)) 
    \addr_dec_to_mb_data[31]_i_7 
       (.I0(\cal_cmp_en_reg_n_0_[3] ),
        .I1(mcal_dq_cmp[31]),
        .I2(io_address[0]),
        .I3(\cal_cmp_en_reg_n_0_[7] ),
        .I4(mcal_dq_cmp[63]),
        .I5(lrdimm_cal_mode),
        .O(\addr_dec_to_mb_data[31]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    \addr_dec_to_mb_data[3]_i_14 
       (.I0(\addr_dec_to_mb_data[6]_i_7 ),
        .I1(mcal_rd_vref_value[45]),
        .I2(\addr_dec_to_mb_data[6]_i_7_0 ),
        .I3(mcal_rd_vref_value[52]),
        .I4(\addr_dec_to_mb_data[3]_i_34_n_0 ),
        .I5(\addr_dec_to_mb_data[3]_i_35_n_0 ),
        .O(\rd_vref_value_reg[45]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1162" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \addr_dec_to_mb_data[3]_i_15 
       (.I0(mcal_DQIn_byte_r1[35]),
        .I1(io_address[0]),
        .I2(mcal_DQIn_byte_r1[3]),
        .O(\addr_dec_to_mb_data[3]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'h8F808080)) 
    \addr_dec_to_mb_data[3]_i_16 
       (.I0(mcal_dq_cmp[35]),
        .I1(\cal_cmp_en_reg_n_0_[4] ),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp[3]),
        .I4(\cal_cmp_en_reg_n_0_[0] ),
        .O(\addr_dec_to_mb_data[3]_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1162" *) 
  LUT3 #(
    .INIT(8'hD1)) 
    \addr_dec_to_mb_data[3]_i_17 
       (.I0(\genblk6[3].mcal_DQ0In_lrdimm_or_r_reg_n_0_[3] ),
        .I1(io_address[0]),
        .I2(mcal_dq_cmp_lrdimm[35]),
        .O(\addr_dec_to_mb_data[3]_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1163" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \addr_dec_to_mb_data[3]_i_26 
       (.I0(\cal_ADR_A_reg[30]_0 [2]),
        .I1(io_address[10]),
        .I2(\cal_RST_CKE_ODT_PAR_reg[30]_0 [2]),
        .O(\cal_ADR_A_reg[3]_0 ));
  LUT6 #(
    .INIT(64'h0000000000F0CCAA)) 
    \addr_dec_to_mb_data[3]_i_34 
       (.I0(mcal_rd_vref_value[3]),
        .I1(mcal_rd_vref_value[10]),
        .I2(mcal_rd_vref_value[17]),
        .I3(io_address[0]),
        .I4(io_address[1]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[3]_i_34_n_0 ));
  LUT6 #(
    .INIT(64'h00F000CCAA000000)) 
    \addr_dec_to_mb_data[3]_i_35 
       (.I0(mcal_rd_vref_value[24]),
        .I1(mcal_rd_vref_value[31]),
        .I2(mcal_rd_vref_value[38]),
        .I3(io_address[1]),
        .I4(io_address[0]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[3]_i_35_n_0 ));
  LUT6 #(
    .INIT(64'hEEE222E200000000)) 
    \addr_dec_to_mb_data[3]_i_5 
       (.I0(\addr_dec_to_mb_data[3]_i_15_n_0 ),
        .I1(io_address[5]),
        .I2(\addr_dec_to_mb_data[3]_i_16_n_0 ),
        .I3(lrdimm_cal_mode),
        .I4(\addr_dec_to_mb_data[3]_i_17_n_0 ),
        .I5(io_address[11]),
        .O(\SYNC[5].sync_reg_reg[1]_17 ));
  (* SOFT_HLUTNM = "soft_lutpair887" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \addr_dec_to_mb_data[4]_i_17 
       (.I0(\cal_CS_A_reg[5]_0 [3]),
        .I1(io_address[13]),
        .I2(io_address[14]),
        .I3(\cal_CS_B_reg[5]_0 [3]),
        .O(\cal_CS_A_reg[4]_0 ));
  LUT6 #(
    .INIT(64'h202F2020202F2F2F)) 
    \addr_dec_to_mb_data[4]_i_19 
       (.I0(\addr_dec_to_mb_data[4]_i_36_n_0 ),
        .I1(\addr_dec_to_mb_data[4]_i_37_n_0 ),
        .I2(io_address[5]),
        .I3(mcal_DQIn_byte_r1[36]),
        .I4(io_address[0]),
        .I5(mcal_DQIn_byte_r1[4]),
        .O(\SYNC[5].sync_reg_reg[1]_14 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \addr_dec_to_mb_data[4]_i_27 
       (.I0(\cal_ADR_A_reg[30]_0 [3]),
        .I1(io_address[10]),
        .I2(ub_cal_RESET_n[4]),
        .O(\cal_ADR_A_reg[4]_1 ));
  LUT6 #(
    .INIT(64'hFF470000FF47FF47)) 
    \addr_dec_to_mb_data[4]_i_32 
       (.I0(\cal_ADR_A_reg[30]_0 [3]),
        .I1(io_address[10]),
        .I2(ub_cal_RESET_n[4]),
        .I3(\addr_dec_to_mb_data[4]_i_11 ),
        .I4(\addr_dec_to_mb_data_reg[29]_4 ),
        .I5(\cal_ADR_B_reg[30]_0 [3]),
        .O(\cal_ADR_A_reg[4]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \addr_dec_to_mb_data[4]_i_33 
       (.I0(\rd_vref_value_reg[46]_0 ),
        .I1(io_address[4]),
        .I2(\mcal_DMIn_bit_r1_reg[7]_0 [4]),
        .O(\SYNC[4].sync_reg_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAABFFFBFFFBFFFBF)) 
    \addr_dec_to_mb_data[4]_i_36 
       (.I0(lrdimm_cal_mode),
        .I1(\cal_cmp_en_reg_n_0_[0] ),
        .I2(mcal_dq_cmp[4]),
        .I3(io_address[0]),
        .I4(\cal_cmp_en_reg_n_0_[4] ),
        .I5(mcal_dq_cmp[36]),
        .O(\addr_dec_to_mb_data[4]_i_36_n_0 ));
  LUT4 #(
    .INIT(16'h808A)) 
    \addr_dec_to_mb_data[4]_i_37 
       (.I0(lrdimm_cal_mode),
        .I1(mcal_dq_cmp_lrdimm[36]),
        .I2(io_address[0]),
        .I3(\genblk6[4].mcal_DQ0In_lrdimm_or_r_reg_n_0_[4] ),
        .O(\addr_dec_to_mb_data[4]_i_37_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    \addr_dec_to_mb_data[4]_i_41 
       (.I0(\addr_dec_to_mb_data[6]_i_7 ),
        .I1(mcal_rd_vref_value[46]),
        .I2(\addr_dec_to_mb_data[6]_i_7_0 ),
        .I3(mcal_rd_vref_value[53]),
        .I4(\addr_dec_to_mb_data[4]_i_44_n_0 ),
        .I5(\addr_dec_to_mb_data[4]_i_45_n_0 ),
        .O(\rd_vref_value_reg[46]_0 ));
  LUT6 #(
    .INIT(64'h0000000000F0CCAA)) 
    \addr_dec_to_mb_data[4]_i_44 
       (.I0(mcal_rd_vref_value[4]),
        .I1(mcal_rd_vref_value[11]),
        .I2(mcal_rd_vref_value[18]),
        .I3(io_address[0]),
        .I4(io_address[1]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[4]_i_44_n_0 ));
  LUT6 #(
    .INIT(64'h00F000CCAA000000)) 
    \addr_dec_to_mb_data[4]_i_45 
       (.I0(mcal_rd_vref_value[25]),
        .I1(mcal_rd_vref_value[32]),
        .I2(mcal_rd_vref_value[39]),
        .I3(io_address[1]),
        .I4(io_address[0]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[4]_i_45_n_0 ));
  LUT6 #(
    .INIT(64'h2EEE22E2FFFFFFFF)) 
    \addr_dec_to_mb_data[5]_i_17 
       (.I0(\addr_dec_to_mb_data[5]_i_33_n_0 ),
        .I1(lrdimm_cal_mode),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp_lrdimm[37]),
        .I4(\genblk6[5].mcal_DQ0In_lrdimm_or_r_reg_n_0_[5] ),
        .I5(io_address[5]),
        .O(lrdimm_cal_mode_reg_1));
  LUT4 #(
    .INIT(16'h88B8)) 
    \addr_dec_to_mb_data[5]_i_19 
       (.I0(\addr_dec_to_mb_data[5]_i_34_n_0 ),
        .I1(io_address[4]),
        .I2(mcal_DMIn_bit_r1),
        .I3(io_address[5]),
        .O(\SYNC[4].sync_reg_reg[1] ));
  LUT5 #(
    .INIT(32'h77770FFF)) 
    \addr_dec_to_mb_data[5]_i_33 
       (.I0(mcal_dq_cmp[37]),
        .I1(\cal_cmp_en_reg_n_0_[4] ),
        .I2(mcal_dq_cmp[5]),
        .I3(\cal_cmp_en_reg_n_0_[0] ),
        .I4(io_address[0]),
        .O(\addr_dec_to_mb_data[5]_i_33_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    \addr_dec_to_mb_data[5]_i_34 
       (.I0(\addr_dec_to_mb_data[6]_i_7 ),
        .I1(mcal_rd_vref_value[47]),
        .I2(\addr_dec_to_mb_data[6]_i_7_0 ),
        .I3(mcal_rd_vref_value[54]),
        .I4(\addr_dec_to_mb_data[5]_i_35_n_0 ),
        .I5(\addr_dec_to_mb_data[5]_i_36_n_0 ),
        .O(\addr_dec_to_mb_data[5]_i_34_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000F0CCAA)) 
    \addr_dec_to_mb_data[5]_i_35 
       (.I0(mcal_rd_vref_value[5]),
        .I1(mcal_rd_vref_value[12]),
        .I2(mcal_rd_vref_value[19]),
        .I3(io_address[0]),
        .I4(io_address[1]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[5]_i_35_n_0 ));
  LUT6 #(
    .INIT(64'h00F000CCAA000000)) 
    \addr_dec_to_mb_data[5]_i_36 
       (.I0(mcal_rd_vref_value[26]),
        .I1(mcal_rd_vref_value[33]),
        .I2(mcal_rd_vref_value[40]),
        .I3(io_address[1]),
        .I4(io_address[0]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[5]_i_36_n_0 ));
  LUT6 #(
    .INIT(64'h2EEE22E2FFFFFFFF)) 
    \addr_dec_to_mb_data[6]_i_13 
       (.I0(\addr_dec_to_mb_data[6]_i_19_n_0 ),
        .I1(lrdimm_cal_mode),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp_lrdimm[38]),
        .I4(\genblk6[6].mcal_DQ0In_lrdimm_or_r_reg_n_0_[6] ),
        .I5(io_address[5]),
        .O(\addr_dec_to_mb_data[6]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    \addr_dec_to_mb_data[6]_i_14 
       (.I0(\addr_dec_to_mb_data[6]_i_7 ),
        .I1(mcal_rd_vref_value[48]),
        .I2(\addr_dec_to_mb_data[6]_i_7_0 ),
        .I3(mcal_rd_vref_value[55]),
        .I4(\addr_dec_to_mb_data[6]_i_22_n_0 ),
        .I5(\addr_dec_to_mb_data[6]_i_23_n_0 ),
        .O(\rd_vref_value_reg[48]_0 ));
  LUT5 #(
    .INIT(32'h77770FFF)) 
    \addr_dec_to_mb_data[6]_i_19 
       (.I0(mcal_dq_cmp[38]),
        .I1(\cal_cmp_en_reg_n_0_[4] ),
        .I2(mcal_dq_cmp[6]),
        .I3(\cal_cmp_en_reg_n_0_[0] ),
        .I4(io_address[0]),
        .O(\addr_dec_to_mb_data[6]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000F0CCAA)) 
    \addr_dec_to_mb_data[6]_i_22 
       (.I0(mcal_rd_vref_value[6]),
        .I1(mcal_rd_vref_value[13]),
        .I2(mcal_rd_vref_value[20]),
        .I3(io_address[0]),
        .I4(io_address[1]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[6]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'h00F000CCAA000000)) 
    \addr_dec_to_mb_data[6]_i_23 
       (.I0(mcal_rd_vref_value[27]),
        .I1(mcal_rd_vref_value[34]),
        .I2(mcal_rd_vref_value[41]),
        .I3(io_address[1]),
        .I4(io_address[0]),
        .I5(io_address[2]),
        .O(\addr_dec_to_mb_data[6]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF47440000)) 
    \addr_dec_to_mb_data[6]_i_3 
       (.I0(\cal_CS_A_reg_n_0_[6] ),
        .I1(io_address[13]),
        .I2(\cal_CS_B_reg_n_0_[6] ),
        .I3(io_address[14]),
        .I4(io_address[8]),
        .I5(\addr_dec_to_mb_data[6]_i_6_n_0 ),
        .O(\cal_CS_A_reg[6]_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAA02A2)) 
    \addr_dec_to_mb_data[6]_i_6 
       (.I0(\addr_dec_to_mb_data[6]_i_13_n_0 ),
        .I1(mcal_DQIn_byte_r1[6]),
        .I2(io_address[0]),
        .I3(mcal_DQIn_byte_r1[38]),
        .I4(io_address[5]),
        .I5(\addr_dec_to_mb_data[7]_i_7_0 ),
        .O(\addr_dec_to_mb_data[6]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAA02A2)) 
    \addr_dec_to_mb_data[7]_i_16 
       (.I0(\addr_dec_to_mb_data[7]_i_22_n_0 ),
        .I1(mcal_DQIn_byte_r1[7]),
        .I2(io_address[0]),
        .I3(mcal_DQIn_byte_r1[39]),
        .I4(io_address[5]),
        .I5(\addr_dec_to_mb_data[7]_i_7_0 ),
        .O(\addr_dec_to_mb_data[7]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h2EEE22E2FFFFFFFF)) 
    \addr_dec_to_mb_data[7]_i_22 
       (.I0(\addr_dec_to_mb_data[7]_i_25_n_0 ),
        .I1(lrdimm_cal_mode),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp_lrdimm[39]),
        .I4(\genblk6[7].mcal_DQ0In_lrdimm_or_r_reg_n_0_[7] ),
        .I5(io_address[5]),
        .O(\addr_dec_to_mb_data[7]_i_22_n_0 ));
  LUT5 #(
    .INIT(32'h77770FFF)) 
    \addr_dec_to_mb_data[7]_i_25 
       (.I0(mcal_dq_cmp[39]),
        .I1(\cal_cmp_en_reg_n_0_[4] ),
        .I2(mcal_dq_cmp[7]),
        .I3(\cal_cmp_en_reg_n_0_[0] ),
        .I4(io_address[0]),
        .O(\addr_dec_to_mb_data[7]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF47440000)) 
    \addr_dec_to_mb_data[7]_i_7 
       (.I0(\cal_CS_A_reg_n_0_[7] ),
        .I1(io_address[13]),
        .I2(\cal_CS_B_reg_n_0_[7] ),
        .I3(io_address[14]),
        .I4(io_address[8]),
        .I5(\addr_dec_to_mb_data[7]_i_16_n_0 ),
        .O(\cal_CS_A_reg[7]_0 ));
  LUT5 #(
    .INIT(32'h2EFF2E00)) 
    \addr_dec_to_mb_data[8]_i_14 
       (.I0(\genblk6[8].mcal_DQ0In_lrdimm_or_r_reg_n_0_[8] ),
        .I1(io_address[0]),
        .I2(mcal_dq_cmp_lrdimm[40]),
        .I3(lrdimm_cal_mode),
        .I4(\addr_dec_to_mb_data[8]_i_20_n_0 ),
        .O(\genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8]_0 ));
  LUT5 #(
    .INIT(32'h07F7F7F7)) 
    \addr_dec_to_mb_data[8]_i_20 
       (.I0(mcal_dq_cmp[8]),
        .I1(\cal_cmp_en_reg_n_0_[1] ),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp[40]),
        .I4(\cal_cmp_en_reg_n_0_[5] ),
        .O(\addr_dec_to_mb_data[8]_i_20_n_0 ));
  LUT4 #(
    .INIT(16'h15D5)) 
    \addr_dec_to_mb_data[8]_i_22 
       (.I0(douta),
        .I1(io_address[14]),
        .I2(io_address[10]),
        .I3(\cal_ADR_B_reg[30]_0 [7]),
        .O(mem_reg_bram_0));
  LUT5 #(
    .INIT(32'hD1FFD100)) 
    \addr_dec_to_mb_data[9]_i_10 
       (.I0(\genblk6[9].mcal_DQ0In_lrdimm_or_r_reg_n_0_[9] ),
        .I1(io_address[0]),
        .I2(mcal_dq_cmp_lrdimm[41]),
        .I3(lrdimm_cal_mode),
        .I4(\addr_dec_to_mb_data[9]_i_15_n_0 ),
        .O(\genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9]_0 ));
  LUT6 #(
    .INIT(64'hD0DD0000D0DDD0DD)) 
    \addr_dec_to_mb_data[9]_i_13 
       (.I0(\cal_RST_CKE_ODT_PAR_reg_n_0_[9] ),
        .I1(\addr_dec_to_mb_data_reg[29]_3 ),
        .I2(\addr_dec_to_mb_data_reg[29]_2 ),
        .I3(\cal_ADR_A_reg_n_0_[9] ),
        .I4(\addr_dec_to_mb_data_reg[29]_4 ),
        .I5(\cal_ADR_B_reg_n_0_[9] ),
        .O(\cal_RST_CKE_ODT_PAR_reg[9]_0 ));
  LUT5 #(
    .INIT(32'h8F808080)) 
    \addr_dec_to_mb_data[9]_i_15 
       (.I0(mcal_dq_cmp[41]),
        .I1(\cal_cmp_en_reg_n_0_[5] ),
        .I2(io_address[0]),
        .I3(mcal_dq_cmp[9]),
        .I4(\cal_cmp_en_reg_n_0_[1] ),
        .O(\addr_dec_to_mb_data[9]_i_15_n_0 ));
  FDRE \addr_dec_to_mb_data_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [0]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [10]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [11]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [12]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [13]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [14]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [15]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [16]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [17]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [18]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [19]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [1]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[20]_0 ),
        .Q(\addr_dec_to_mb_data_reg_n_0_[20] ),
        .R(\addr_dec_to_mb_data_reg[30]_0 ));
  FDRE \addr_dec_to_mb_data_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[21]_0 ),
        .Q(\addr_dec_to_mb_data_reg_n_0_[21] ),
        .R(\addr_dec_to_mb_data_reg[30]_0 ));
  FDRE \addr_dec_to_mb_data_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[22]_0 ),
        .Q(\addr_dec_to_mb_data_reg_n_0_[22] ),
        .R(\addr_dec_to_mb_data_reg[30]_0 ));
  FDRE \addr_dec_to_mb_data_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[23]_0 ),
        .Q(\addr_dec_to_mb_data_reg_n_0_[23] ),
        .R(\addr_dec_to_mb_data_reg[30]_0 ));
  FDRE \addr_dec_to_mb_data_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[24]_0 ),
        .Q(\addr_dec_to_mb_data_reg_n_0_[24] ),
        .R(\addr_dec_to_mb_data_reg[30]_0 ));
  FDRE \addr_dec_to_mb_data_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[25]_0 ),
        .Q(\addr_dec_to_mb_data_reg_n_0_[25] ),
        .R(\addr_dec_to_mb_data_reg[30]_0 ));
  FDRE \addr_dec_to_mb_data_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[26]_0 ),
        .Q(\addr_dec_to_mb_data_reg_n_0_[26] ),
        .R(\addr_dec_to_mb_data_reg[30]_0 ));
  FDRE \addr_dec_to_mb_data_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[27]_0 ),
        .Q(\addr_dec_to_mb_data_reg_n_0_[27] ),
        .R(\addr_dec_to_mb_data_reg[30]_0 ));
  FDRE \addr_dec_to_mb_data_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[28]_0 ),
        .Q(\addr_dec_to_mb_data_reg_n_0_[28] ),
        .R(\addr_dec_to_mb_data_reg[30]_0 ));
  FDRE \addr_dec_to_mb_data_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[29]_5 ),
        .Q(\addr_dec_to_mb_data_reg_n_0_[29] ),
        .R(\addr_dec_to_mb_data_reg[30]_0 ));
  FDRE \addr_dec_to_mb_data_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [2]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[30]_1 ),
        .Q(\addr_dec_to_mb_data_reg_n_0_[30] ),
        .R(\addr_dec_to_mb_data_reg[30]_0 ));
  FDRE \addr_dec_to_mb_data_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [20]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [3]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [4]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [5]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [6]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [7]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [8]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \addr_dec_to_mb_data_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\addr_dec_to_mb_data_reg[31]_0 [9]),
        .Q(\addr_dec_to_mb_data_reg_n_0_[9] ),
        .R(1'b0));
  FDRE \bisc_bit_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\bisc_bit_reg[0]_0 ),
        .D(io_write_data[0]),
        .Q(bisc_byte[0]),
        .R(rst_r1));
  FDRE \bisc_bit_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\bisc_bit_reg[0]_0 ),
        .D(io_write_data[1]),
        .Q(bisc_byte[1]),
        .R(rst_r1));
  FDRE \bisc_bit_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\bisc_bit_reg[0]_0 ),
        .D(io_write_data[2]),
        .Q(bisc_byte[2]),
        .R(rst_r1));
  FDRE \bisc_bit_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\bisc_bit_reg[0]_0 ),
        .D(io_write_data[3]),
        .Q(bisc_byte[3]),
        .R(rst_r1));
  FDRE \bisc_nibble_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\bisc_bit_reg[0]_0 ),
        .D(io_write_data[4]),
        .Q(bisc_byte[4]),
        .R(rst_r1));
  FDRE \bisc_nibble_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\bisc_bit_reg[0]_0 ),
        .D(io_write_data[5]),
        .Q(bisc_byte[5]),
        .R(rst_r1));
  FDRE \bisc_nibble_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\bisc_bit_reg[0]_0 ),
        .D(io_write_data[6]),
        .Q(bisc_byte[6]),
        .R(rst_r1));
  FDRE \bisc_nibble_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\bisc_bit_reg[0]_0 ),
        .D(io_write_data[7]),
        .Q(bisc_byte[7]),
        .R(rst_r1));
  FDRE \bisc_nibble_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\bisc_bit_reg[0]_0 ),
        .D(io_write_data[8]),
        .Q(bisc_byte[8]),
        .R(rst_r1));
  FDRE calDone_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(calDone_reg_14),
        .D(io_write_data[1]),
        .Q(calDone_reg_0),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_A_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ACT_n_A_reg[7]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_ACT_n_A_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_A_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ACT_n_A_reg[7]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_ACT_n_A_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_A_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ACT_n_A_reg[7]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_ACT_n_A_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_A_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ACT_n_A_reg[7]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_ACT_n_A_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_A_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ACT_n_A_reg[7]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_ACT_n_A_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_A_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ACT_n_A_reg[7]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_ACT_n_A_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_A_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ACT_n_A_reg[7]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_ACT_n_A_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_A_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ACT_n_A_reg[7]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_ACT_n_A_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_B_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_ACT_n_B_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_B_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_ACT_n_B_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_B_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_ACT_n_B_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_B_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_ACT_n_B_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_B_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_ACT_n_B_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_B_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_ACT_n_B_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_B_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_ACT_n_B_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_ACT_n_B_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_ACT_n_B_reg_n_0_[7] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1555" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_ACT_n_pre[0]_i_1 
       (.I0(\cal_ACT_n_B_reg_n_0_[0] ),
        .I1(a_b_cmd_sel),
        .I2(\cal_ACT_n_A_reg_n_0_[0] ),
        .O(cal_ACT_n_pre_nxt[0]));
  (* SOFT_HLUTNM = "soft_lutpair1555" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_ACT_n_pre[1]_i_1 
       (.I0(\cal_ACT_n_B_reg_n_0_[1] ),
        .I1(a_b_cmd_sel),
        .I2(\cal_ACT_n_A_reg_n_0_[1] ),
        .O(cal_ACT_n_pre_nxt[1]));
  (* SOFT_HLUTNM = "soft_lutpair1554" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_ACT_n_pre[2]_i_1 
       (.I0(\cal_ACT_n_B_reg_n_0_[2] ),
        .I1(a_b_cmd_sel),
        .I2(\cal_ACT_n_A_reg_n_0_[2] ),
        .O(cal_ACT_n_pre_nxt[2]));
  (* SOFT_HLUTNM = "soft_lutpair1554" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_ACT_n_pre[3]_i_1 
       (.I0(\cal_ACT_n_B_reg_n_0_[3] ),
        .I1(a_b_cmd_sel),
        .I2(\cal_ACT_n_A_reg_n_0_[3] ),
        .O(cal_ACT_n_pre_nxt[3]));
  (* SOFT_HLUTNM = "soft_lutpair1553" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_ACT_n_pre[4]_i_1 
       (.I0(\cal_ACT_n_B_reg_n_0_[4] ),
        .I1(a_b_cmd_sel),
        .I2(\cal_ACT_n_A_reg_n_0_[4] ),
        .O(cal_ACT_n_pre_nxt[4]));
  (* SOFT_HLUTNM = "soft_lutpair1553" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_ACT_n_pre[5]_i_1 
       (.I0(\cal_ACT_n_B_reg_n_0_[5] ),
        .I1(a_b_cmd_sel),
        .I2(\cal_ACT_n_A_reg_n_0_[5] ),
        .O(cal_ACT_n_pre_nxt[5]));
  (* SOFT_HLUTNM = "soft_lutpair1552" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_ACT_n_pre[6]_i_1 
       (.I0(\cal_ACT_n_B_reg_n_0_[6] ),
        .I1(a_b_cmd_sel),
        .I2(\cal_ACT_n_A_reg_n_0_[6] ),
        .O(cal_ACT_n_pre_nxt[6]));
  (* SOFT_HLUTNM = "soft_lutpair1552" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_ACT_n_pre[7]_i_1 
       (.I0(\cal_ACT_n_B_reg_n_0_[7] ),
        .I1(a_b_cmd_sel),
        .I2(\cal_ACT_n_A_reg_n_0_[7] ),
        .O(cal_ACT_n_pre_nxt[7]));
  FDSE #(
    .INIT(1'b1)) 
    \cal_ACT_n_pre_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_ACT_n_pre_nxt[0]),
        .Q(cal_ACT_n_pre[0]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_ACT_n_pre_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_ACT_n_pre_nxt[1]),
        .Q(cal_ACT_n_pre[1]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_ACT_n_pre_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_ACT_n_pre_nxt[2]),
        .Q(cal_ACT_n_pre[2]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_ACT_n_pre_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_ACT_n_pre_nxt[3]),
        .Q(cal_ACT_n_pre[3]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_ACT_n_pre_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_ACT_n_pre_nxt[4]),
        .Q(cal_ACT_n_pre[4]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_ACT_n_pre_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_ACT_n_pre_nxt[5]),
        .Q(cal_ACT_n_pre[5]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_ACT_n_pre_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_ACT_n_pre_nxt[6]),
        .Q(cal_ACT_n_pre[6]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_ACT_n_pre_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_ACT_n_pre_nxt[7]),
        .Q(cal_ACT_n_pre[7]),
        .S(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_ADR_A_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_ADR_A_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_ADR_A_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_ADR_A_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_ADR_A_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_ADR_A_reg[30]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_ADR_A_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_ADR_A_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_ADR_A_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_ADR_A_reg_n_0_[18] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_ADR_A_reg_n_0_[19] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_ADR_A_reg[30]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_ADR_A_reg_n_0_[20] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_ADR_A_reg_n_0_[21] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_ADR_A_reg_n_0_[22] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_ADR_A_reg[30]_0 [9]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_ADR_A_reg_n_0_[24] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_ADR_A_reg_n_0_[25] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_ADR_A_reg_n_0_[26] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_ADR_A_reg_n_0_[27] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_ADR_A_reg[30]_0 [10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_ADR_A_reg_n_0_[29] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_ADR_A_reg[30]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_ADR_A_reg[30]_0 [11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_ADR_A_reg_n_0_[31] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_ADR_A_reg[30]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_ADR_A_reg[30]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_ADR_A_reg[30]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_ADR_A_reg[30]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_ADR_A_reg[30]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_ADR_A_reg[30]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_A_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_A_reg[31]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_ADR_A_reg_n_0_[9] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[0]),
        .Q(\cal_ADR_B_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[10]),
        .Q(\cal_ADR_B_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[11]),
        .Q(\cal_ADR_B_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[12]),
        .Q(\cal_ADR_B_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[13]),
        .Q(\cal_ADR_B_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[14]),
        .Q(\cal_ADR_B_reg[30]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[15]),
        .Q(\cal_ADR_B_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[16]),
        .Q(\cal_ADR_B_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[17]),
        .Q(\cal_ADR_B_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[18]),
        .Q(\cal_ADR_B_reg_n_0_[18] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[19]),
        .Q(\cal_ADR_B_reg_n_0_[19] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[1]),
        .Q(\cal_ADR_B_reg[30]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[20]),
        .Q(\cal_ADR_B_reg_n_0_[20] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[21]),
        .Q(\cal_ADR_B_reg_n_0_[21] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[22]),
        .Q(\cal_ADR_B_reg[30]_0 [9]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[23]),
        .Q(\cal_ADR_B_reg[30]_0 [10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[24]),
        .Q(\cal_ADR_B_reg_n_0_[24] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[25]),
        .Q(\cal_ADR_B_reg_n_0_[25] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[26]),
        .Q(\cal_ADR_B_reg_n_0_[26] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[27]),
        .Q(\cal_ADR_B_reg_n_0_[27] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[28]),
        .Q(\cal_ADR_B_reg[30]_0 [11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[29]),
        .Q(\cal_ADR_B_reg_n_0_[29] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[2]),
        .Q(\cal_ADR_B_reg[30]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[30]),
        .Q(\cal_ADR_B_reg[30]_0 [12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[31]),
        .Q(\cal_ADR_B_reg_n_0_[31] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[3]),
        .Q(\cal_ADR_B_reg[30]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[4]),
        .Q(\cal_ADR_B_reg[30]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[5]),
        .Q(\cal_ADR_B_reg[30]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[6]),
        .Q(\cal_ADR_B_reg[30]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[7]),
        .Q(\cal_ADR_B_reg[30]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[8]),
        .Q(\cal_ADR_B_reg[30]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_ADR_B_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_ADR_B_reg[31]_1 ),
        .D(io_write_data[9]),
        .Q(\cal_ADR_B_reg_n_0_[9] ),
        .R(1'b0));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_A_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[24]),
        .Q(cal_CAS_A[0]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_A_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[25]),
        .Q(cal_CAS_A[1]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_A_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[26]),
        .Q(cal_CAS_A[2]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_A_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[27]),
        .Q(cal_CAS_A[3]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_A_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[28]),
        .Q(cal_CAS_A[4]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_A_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[29]),
        .Q(cal_CAS_A[5]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_A_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[30]),
        .Q(cal_CAS_A[6]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_A_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[31]),
        .Q(cal_CAS_A[7]),
        .S(rst_r1));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CAS_B_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[24]),
        .Q(cal_CAS_B[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CAS_B_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[25]),
        .Q(cal_CAS_B[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CAS_B_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[26]),
        .Q(cal_CAS_B[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CAS_B_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[27]),
        .Q(cal_CAS_B[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CAS_B_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[28]),
        .Q(cal_CAS_B[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CAS_B_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[29]),
        .Q(cal_CAS_B[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CAS_B_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[30]),
        .Q(cal_CAS_B[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CAS_B_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[31]),
        .Q(cal_CAS_B[7]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1547" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CAS_pre[0]_i_1 
       (.I0(cal_CAS_B[0]),
        .I1(a_b_cmd_sel),
        .I2(cal_CAS_A[0]),
        .O(cal_CAS_pre_nxt[0]));
  (* SOFT_HLUTNM = "soft_lutpair1547" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CAS_pre[1]_i_1 
       (.I0(cal_CAS_B[1]),
        .I1(a_b_cmd_sel),
        .I2(cal_CAS_A[1]),
        .O(cal_CAS_pre_nxt[1]));
  (* SOFT_HLUTNM = "soft_lutpair1546" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CAS_pre[2]_i_1 
       (.I0(cal_CAS_B[2]),
        .I1(a_b_cmd_sel),
        .I2(cal_CAS_A[2]),
        .O(cal_CAS_pre_nxt[2]));
  (* SOFT_HLUTNM = "soft_lutpair1546" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CAS_pre[3]_i_1 
       (.I0(cal_CAS_B[3]),
        .I1(a_b_cmd_sel),
        .I2(cal_CAS_A[3]),
        .O(cal_CAS_pre_nxt[3]));
  (* SOFT_HLUTNM = "soft_lutpair1545" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CAS_pre[4]_i_1 
       (.I0(cal_CAS_B[4]),
        .I1(a_b_cmd_sel),
        .I2(cal_CAS_A[4]),
        .O(cal_CAS_pre_nxt[4]));
  (* SOFT_HLUTNM = "soft_lutpair1545" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CAS_pre[5]_i_1 
       (.I0(cal_CAS_B[5]),
        .I1(a_b_cmd_sel),
        .I2(cal_CAS_A[5]),
        .O(cal_CAS_pre_nxt[5]));
  (* SOFT_HLUTNM = "soft_lutpair1544" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CAS_pre[6]_i_1 
       (.I0(cal_CAS_B[6]),
        .I1(a_b_cmd_sel),
        .I2(cal_CAS_A[6]),
        .O(cal_CAS_pre_nxt[6]));
  (* SOFT_HLUTNM = "soft_lutpair1544" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CAS_pre[7]_i_1 
       (.I0(cal_CAS_B[7]),
        .I1(a_b_cmd_sel),
        .I2(cal_CAS_A[7]),
        .O(cal_CAS_pre_nxt[7]));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_pre_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_CAS_pre_nxt[0]),
        .Q(cal_CAS_pre[0]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_pre_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_CAS_pre_nxt[1]),
        .Q(cal_CAS_pre[1]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_pre_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_CAS_pre_nxt[2]),
        .Q(cal_CAS_pre[2]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_pre_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_CAS_pre_nxt[3]),
        .Q(cal_CAS_pre[3]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_pre_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_CAS_pre_nxt[4]),
        .Q(cal_CAS_pre[4]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_pre_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_CAS_pre_nxt[5]),
        .Q(cal_CAS_pre[5]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_pre_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_CAS_pre_nxt[6]),
        .Q(cal_CAS_pre[6]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CAS_pre_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_CAS_pre_nxt[7]),
        .Q(cal_CAS_pre[7]),
        .S(rst_r1));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_A_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_A_reg[7]_1 ),
        .D(io_write_data[0]),
        .Q(\cal_CS_A_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_A_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_A_reg[7]_1 ),
        .D(io_write_data[1]),
        .Q(\cal_CS_A_reg[5]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_A_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_A_reg[7]_1 ),
        .D(io_write_data[2]),
        .Q(\cal_CS_A_reg[5]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_A_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_A_reg[7]_1 ),
        .D(io_write_data[3]),
        .Q(\cal_CS_A_reg[5]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_A_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_A_reg[7]_1 ),
        .D(io_write_data[4]),
        .Q(\cal_CS_A_reg[5]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_A_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_A_reg[7]_1 ),
        .D(io_write_data[5]),
        .Q(\cal_CS_A_reg[5]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_A_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_A_reg[7]_1 ),
        .D(io_write_data[6]),
        .Q(\cal_CS_A_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_A_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_A_reg[7]_1 ),
        .D(io_write_data[7]),
        .Q(\cal_CS_A_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_B_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_B_reg[7]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_CS_B_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_B_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_B_reg[7]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_CS_B_reg[5]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_B_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_B_reg[7]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_CS_B_reg[5]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_B_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_B_reg[7]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_CS_B_reg[5]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_B_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_B_reg[7]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_CS_B_reg[5]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_B_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_B_reg[7]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_CS_B_reg[5]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_B_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_B_reg[7]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_CS_B_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_CS_B_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CS_B_reg[7]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_CS_B_reg_n_0_[7] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1534" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CS_n_pre[0]_i_1 
       (.I0(\cal_CS_B_reg_n_0_[0] ),
        .I1(\cal_CS_n_pre[7]_i_4_n_0 ),
        .I2(\cal_CS_A_reg_n_0_[0] ),
        .O(\cal_CS_n_pre[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1534" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CS_n_pre[1]_i_1 
       (.I0(\cal_CS_B_reg[5]_0 [0]),
        .I1(\cal_CS_n_pre[7]_i_4_n_0 ),
        .I2(\cal_CS_A_reg[5]_0 [0]),
        .O(\cal_CS_n_pre[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1535" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CS_n_pre[2]_i_1 
       (.I0(\cal_CS_B_reg[5]_0 [1]),
        .I1(\cal_CS_n_pre[7]_i_4_n_0 ),
        .I2(\cal_CS_A_reg[5]_0 [1]),
        .O(\cal_CS_n_pre[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1535" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CS_n_pre[3]_i_1 
       (.I0(\cal_CS_B_reg[5]_0 [2]),
        .I1(\cal_CS_n_pre[7]_i_4_n_0 ),
        .I2(\cal_CS_A_reg[5]_0 [2]),
        .O(\cal_CS_n_pre[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair887" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CS_n_pre[4]_i_1 
       (.I0(\cal_CS_B_reg[5]_0 [3]),
        .I1(\cal_CS_n_pre[7]_i_4_n_0 ),
        .I2(\cal_CS_A_reg[5]_0 [3]),
        .O(\cal_CS_n_pre[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1536" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CS_n_pre[5]_i_1 
       (.I0(\cal_CS_B_reg[5]_0 [4]),
        .I1(\cal_CS_n_pre[7]_i_4_n_0 ),
        .I2(\cal_CS_A_reg[5]_0 [4]),
        .O(\cal_CS_n_pre[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1536" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CS_n_pre[6]_i_1 
       (.I0(\cal_CS_B_reg_n_0_[6] ),
        .I1(\cal_CS_n_pre[7]_i_4_n_0 ),
        .I2(\cal_CS_A_reg_n_0_[6] ),
        .O(\cal_CS_n_pre[6]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_CS_n_pre[7]_i_2 
       (.I0(\cal_CS_B_reg_n_0_[7] ),
        .I1(\cal_CS_n_pre[7]_i_4_n_0 ),
        .I2(\cal_CS_A_reg_n_0_[7] ),
        .O(\cal_CS_n_pre[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair901" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    \cal_CS_n_pre[7]_i_3 
       (.I0(wrlvl_mode),
        .I1(cal_seq_cnt_gt_0),
        .I2(seq_cnt_dec),
        .I3(extended_write_mode),
        .O(\cal_CS_n_pre[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000060000000)) 
    \cal_CS_n_pre[7]_i_4 
       (.I0(a_b_cmd_sel_start_reg_0),
        .I1(\cal_seq_cnt_reg[31]_0 [0]),
        .I2(\cal_seq_reg_n_0_[0] ),
        .I3(cal_seq_cnt_gt_0),
        .I4(seq_cnt_dec),
        .I5(extended_write_mode),
        .O(\cal_CS_n_pre[7]_i_4_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CS_n_pre_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_CS_n_pre[0]_i_1_n_0 ),
        .Q(\cal_CS_n_pre_reg_n_0_[0] ),
        .S(cal_CS_n_pre));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CS_n_pre_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_CS_n_pre[1]_i_1_n_0 ),
        .Q(\cal_CS_n_pre_reg_n_0_[1] ),
        .S(cal_CS_n_pre));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CS_n_pre_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_CS_n_pre[2]_i_1_n_0 ),
        .Q(\cal_CS_n_pre_reg_n_0_[2] ),
        .S(cal_CS_n_pre));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CS_n_pre_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_CS_n_pre[3]_i_1_n_0 ),
        .Q(\cal_CS_n_pre_reg_n_0_[3] ),
        .S(cal_CS_n_pre));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CS_n_pre_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_CS_n_pre[4]_i_1_n_0 ),
        .Q(\cal_CS_n_pre_reg_n_0_[4] ),
        .S(cal_CS_n_pre));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CS_n_pre_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_CS_n_pre[5]_i_1_n_0 ),
        .Q(\cal_CS_n_pre_reg_n_0_[5] ),
        .S(cal_CS_n_pre));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CS_n_pre_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_CS_n_pre[6]_i_1_n_0 ),
        .Q(\cal_CS_n_pre_reg_n_0_[6] ),
        .S(cal_CS_n_pre));
  FDSE #(
    .INIT(1'b1)) 
    \cal_CS_n_pre_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_CS_n_pre[7]_i_2_n_0 ),
        .Q(\cal_CS_n_pre_reg_n_0_[7] ),
        .S(cal_CS_n_pre));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_DMOut_n_A_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_DMOut_n_A_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_DMOut_n_A_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_DMOut_n_A_reg_n_0_[12] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_DMOut_n_A_reg_n_0_[13] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_DMOut_n_A_reg_n_0_[14] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_DMOut_n_A_reg_n_0_[15] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_DMOut_n_A_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_DMOut_n_A_reg_n_0_[17] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_DMOut_n_A_reg_n_0_[18] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_DMOut_n_A_reg_n_0_[19] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_DMOut_n_A_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_DMOut_n_A_reg_n_0_[20] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_DMOut_n_A_reg_n_0_[21] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_DMOut_n_A_reg_n_0_[22] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_DMOut_n_A_reg_n_0_[23] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_DMOut_n_A_reg_n_0_[24] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_DMOut_n_A_reg_n_0_[25] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_DMOut_n_A_reg_n_0_[26] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_DMOut_n_A_reg_n_0_[27] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_DMOut_n_A_reg_n_0_[28] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_DMOut_n_A_reg_n_0_[29] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_DMOut_n_A_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_DMOut_n_A_reg_n_0_[30] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_DMOut_n_A_reg_n_0_[31] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_DMOut_n_A_reg_n_0_[3] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_DMOut_n_A_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_DMOut_n_A_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_DMOut_n_A_reg_n_0_[6] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_DMOut_n_A_reg_n_0_[7] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_DMOut_n_A_reg_n_0_[8] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_A_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DMOut_n_A_reg[31]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_DMOut_n_A_reg_n_0_[9] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[0]),
        .Q(cal_DMOut_n[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[10]),
        .Q(cal_DMOut_n[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[11]),
        .Q(cal_DMOut_n[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[12]),
        .Q(cal_DMOut_n[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[13]),
        .Q(cal_DMOut_n[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[14]),
        .Q(cal_DMOut_n[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[15]),
        .Q(cal_DMOut_n[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[16]),
        .Q(cal_DMOut_n[16]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[17]),
        .Q(cal_DMOut_n[17]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[18]),
        .Q(cal_DMOut_n[18]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[19]),
        .Q(cal_DMOut_n[19]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[1]),
        .Q(cal_DMOut_n[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[20]),
        .Q(cal_DMOut_n[20]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[21]),
        .Q(cal_DMOut_n[21]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[22]),
        .Q(cal_DMOut_n[22]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[23]),
        .Q(cal_DMOut_n[23]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[24]),
        .Q(cal_DMOut_n[24]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[25]),
        .Q(cal_DMOut_n[25]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[26]),
        .Q(cal_DMOut_n[26]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[27]),
        .Q(cal_DMOut_n[27]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[28]),
        .Q(cal_DMOut_n[28]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[29]),
        .Q(cal_DMOut_n[29]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[2]),
        .Q(cal_DMOut_n[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[30]),
        .Q(cal_DMOut_n[30]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[31]),
        .Q(cal_DMOut_n[31]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[32]),
        .Q(cal_DMOut_n[32]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[33]),
        .Q(cal_DMOut_n[33]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[34]),
        .Q(cal_DMOut_n[34]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[35]),
        .Q(cal_DMOut_n[35]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[36]),
        .Q(cal_DMOut_n[36]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[37]),
        .Q(cal_DMOut_n[37]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[38]),
        .Q(cal_DMOut_n[38]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[39]),
        .Q(cal_DMOut_n[39]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[3]),
        .Q(cal_DMOut_n[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[40]),
        .Q(cal_DMOut_n[40]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[41]),
        .Q(cal_DMOut_n[41]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[42]),
        .Q(cal_DMOut_n[42]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[43]),
        .Q(cal_DMOut_n[43]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[44]),
        .Q(cal_DMOut_n[44]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[45]),
        .Q(cal_DMOut_n[45]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[46]),
        .Q(cal_DMOut_n[46]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[47]),
        .Q(cal_DMOut_n[47]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[48]),
        .Q(cal_DMOut_n[48]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[49]),
        .Q(cal_DMOut_n[49]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[4]),
        .Q(cal_DMOut_n[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[50]),
        .Q(cal_DMOut_n[50]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[51]),
        .Q(cal_DMOut_n[51]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[52]),
        .Q(cal_DMOut_n[52]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[53]),
        .Q(cal_DMOut_n[53]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[54]),
        .Q(cal_DMOut_n[54]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[55]),
        .Q(cal_DMOut_n[55]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[56]),
        .Q(cal_DMOut_n[56]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[57]),
        .Q(cal_DMOut_n[57]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[58]),
        .Q(cal_DMOut_n[58]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[59]),
        .Q(cal_DMOut_n[59]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[5]),
        .Q(cal_DMOut_n[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[60]),
        .Q(cal_DMOut_n[60]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[61]),
        .Q(cal_DMOut_n[61]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[62]),
        .Q(cal_DMOut_n[62]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[63]),
        .Q(cal_DMOut_n[63]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[6]),
        .Q(cal_DMOut_n[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[7]),
        .Q(cal_DMOut_n[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[8]),
        .Q(cal_DMOut_n[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DMOut_n_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DMOut_n_nxt[9]),
        .Q(cal_DMOut_n[9]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_DQOut_A_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_DQOut_A_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_DQOut_A_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_DQOut_A_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_DQOut_A_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_DQOut_A_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_DQOut_A_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_DQOut_A_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_DQOut_A_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_DQOut_A_reg_n_0_[18] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_DQOut_A_reg_n_0_[19] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_DQOut_A_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_DQOut_A_reg_n_0_[20] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_DQOut_A_reg_n_0_[21] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_DQOut_A_reg_n_0_[22] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_DQOut_A_reg_n_0_[23] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_DQOut_A_reg_n_0_[24] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_DQOut_A_reg_n_0_[25] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_DQOut_A_reg_n_0_[26] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_DQOut_A_reg_n_0_[27] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_DQOut_A_reg_n_0_[28] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_DQOut_A_reg_n_0_[29] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_DQOut_A_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_DQOut_A_reg_n_0_[30] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_DQOut_A_reg_n_0_[31] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_DQOut_A_reg_n_0_[32] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_DQOut_A_reg_n_0_[33] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_DQOut_A_reg_n_0_[34] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_DQOut_A_reg_n_0_[35] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_DQOut_A_reg_n_0_[36] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_DQOut_A_reg_n_0_[37] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_DQOut_A_reg_n_0_[38] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_DQOut_A_reg_n_0_[39] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_DQOut_A_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_DQOut_A_reg_n_0_[40] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_DQOut_A_reg_n_0_[41] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_DQOut_A_reg_n_0_[42] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_DQOut_A_reg_n_0_[43] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_DQOut_A_reg_n_0_[44] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_DQOut_A_reg_n_0_[45] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_DQOut_A_reg_n_0_[46] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_DQOut_A_reg_n_0_[47] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_DQOut_A_reg_n_0_[48] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_DQOut_A_reg_n_0_[49] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_DQOut_A_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_DQOut_A_reg_n_0_[50] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_DQOut_A_reg_n_0_[51] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_DQOut_A_reg_n_0_[52] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_DQOut_A_reg_n_0_[53] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_DQOut_A_reg_n_0_[54] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_DQOut_A_reg_n_0_[55] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_DQOut_A_reg_n_0_[56] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_DQOut_A_reg_n_0_[57] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_DQOut_A_reg_n_0_[58] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_DQOut_A_reg_n_0_[59] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_DQOut_A_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_DQOut_A_reg_n_0_[60] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_DQOut_A_reg_n_0_[61] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_DQOut_A_reg_n_0_[62] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[63]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_DQOut_A_reg_n_0_[63] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_DQOut_A_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_DQOut_A_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_DQOut_A_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_A_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_A_reg[31]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_DQOut_A_reg_n_0_[9] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFFFF7)) 
    \cal_DQOut_post[31]_i_2 
       (.I0(\cplx_config_reg[16]_0 ),
        .I1(io_addr_strobe_r1_reg_0),
        .I2(rst_r1),
        .I3(io_address[12]),
        .I4(io_address[15]),
        .O(\SYNC[0].sync_reg_reg[1] ));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_DQOut_post_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_DQOut_post_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_DQOut_post_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_DQOut_post_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_DQOut_post_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_DQOut_post_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_DQOut_post_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_DQOut_post_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_DQOut_post_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_DQOut_post_reg_n_0_[18] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_DQOut_post_reg_n_0_[19] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_DQOut_post_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_DQOut_post_reg_n_0_[20] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_DQOut_post_reg_n_0_[21] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_DQOut_post_reg_n_0_[22] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_DQOut_post_reg_n_0_[23] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_DQOut_post_reg_n_0_[24] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_DQOut_post_reg_n_0_[25] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_DQOut_post_reg_n_0_[26] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_DQOut_post_reg_n_0_[27] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_DQOut_post_reg_n_0_[28] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_DQOut_post_reg_n_0_[29] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_DQOut_post_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_DQOut_post_reg_n_0_[30] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_DQOut_post_reg_n_0_[31] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_DQOut_post_reg_n_0_[32] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_DQOut_post_reg_n_0_[33] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_DQOut_post_reg_n_0_[34] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_DQOut_post_reg_n_0_[35] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_DQOut_post_reg_n_0_[36] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_DQOut_post_reg_n_0_[37] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_DQOut_post_reg_n_0_[38] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_DQOut_post_reg_n_0_[39] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_DQOut_post_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_DQOut_post_reg_n_0_[40] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_DQOut_post_reg_n_0_[41] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_DQOut_post_reg_n_0_[42] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_DQOut_post_reg_n_0_[43] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_DQOut_post_reg_n_0_[44] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_DQOut_post_reg_n_0_[45] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_DQOut_post_reg_n_0_[46] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_DQOut_post_reg_n_0_[47] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_DQOut_post_reg_n_0_[48] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_DQOut_post_reg_n_0_[49] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_DQOut_post_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_DQOut_post_reg_n_0_[50] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_DQOut_post_reg_n_0_[51] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_DQOut_post_reg_n_0_[52] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_DQOut_post_reg_n_0_[53] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_DQOut_post_reg_n_0_[54] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_DQOut_post_reg_n_0_[55] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_DQOut_post_reg_n_0_[56] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_DQOut_post_reg_n_0_[57] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_DQOut_post_reg_n_0_[58] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_DQOut_post_reg_n_0_[59] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_DQOut_post_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_DQOut_post_reg_n_0_[60] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_DQOut_post_reg_n_0_[61] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_DQOut_post_reg_n_0_[62] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[63]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_DQOut_post_reg_n_0_[63] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_DQOut_post_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_DQOut_post_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_DQOut_post_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_post_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_post_reg[31]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_DQOut_post_reg_n_0_[9] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_DQOut_pre_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_DQOut_pre_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_DQOut_pre_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_DQOut_pre_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_DQOut_pre_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_DQOut_pre_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_DQOut_pre_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_DQOut_pre_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_DQOut_pre_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_DQOut_pre_reg_n_0_[18] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_DQOut_pre_reg_n_0_[19] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_DQOut_pre_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_DQOut_pre_reg_n_0_[20] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_DQOut_pre_reg_n_0_[21] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_DQOut_pre_reg_n_0_[22] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_DQOut_pre_reg_n_0_[23] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_DQOut_pre_reg_n_0_[24] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_DQOut_pre_reg_n_0_[25] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_DQOut_pre_reg_n_0_[26] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_DQOut_pre_reg_n_0_[27] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_DQOut_pre_reg_n_0_[28] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_DQOut_pre_reg_n_0_[29] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_DQOut_pre_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_DQOut_pre_reg_n_0_[30] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_DQOut_pre_reg_n_0_[31] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_DQOut_pre_reg_n_0_[32] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_DQOut_pre_reg_n_0_[33] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_DQOut_pre_reg_n_0_[34] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_DQOut_pre_reg_n_0_[35] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_DQOut_pre_reg_n_0_[36] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_DQOut_pre_reg_n_0_[37] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_DQOut_pre_reg_n_0_[38] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_DQOut_pre_reg_n_0_[39] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_DQOut_pre_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_DQOut_pre_reg_n_0_[40] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_DQOut_pre_reg_n_0_[41] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_DQOut_pre_reg_n_0_[42] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_DQOut_pre_reg_n_0_[43] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_DQOut_pre_reg_n_0_[44] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_DQOut_pre_reg_n_0_[45] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_DQOut_pre_reg_n_0_[46] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_DQOut_pre_reg_n_0_[47] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_DQOut_pre_reg_n_0_[48] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_DQOut_pre_reg_n_0_[49] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_DQOut_pre_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_DQOut_pre_reg_n_0_[50] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_DQOut_pre_reg_n_0_[51] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_DQOut_pre_reg_n_0_[52] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_DQOut_pre_reg_n_0_[53] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_DQOut_pre_reg_n_0_[54] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_DQOut_pre_reg_n_0_[55] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_DQOut_pre_reg_n_0_[56] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_DQOut_pre_reg_n_0_[57] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_DQOut_pre_reg_n_0_[58] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_DQOut_pre_reg_n_0_[59] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_DQOut_pre_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_DQOut_pre_reg_n_0_[60] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_DQOut_pre_reg_n_0_[61] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_DQOut_pre_reg_n_0_[62] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[63]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_DQOut_pre_reg_n_0_[63] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_DQOut_pre_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_DQOut_pre_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_DQOut_pre_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQOut_pre_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQOut_pre_reg[31]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_DQOut_pre_reg_n_0_[9] ),
        .R(1'b0));
  FDRE \cal_DQOut_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[0]),
        .Q(cal_DQOut[0]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[100] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[100]),
        .Q(cal_DQOut[100]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[101] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[101]),
        .Q(cal_DQOut[101]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[102] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[102]),
        .Q(cal_DQOut[102]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[103] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[103]),
        .Q(cal_DQOut[103]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[104] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[104]),
        .Q(cal_DQOut[104]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[105] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[105]),
        .Q(cal_DQOut[105]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[106] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[106]),
        .Q(cal_DQOut[106]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[107] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[107]),
        .Q(cal_DQOut[107]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[108] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[108]),
        .Q(cal_DQOut[108]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[109] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[109]),
        .Q(cal_DQOut[109]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[10]),
        .Q(cal_DQOut[10]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[110] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[110]),
        .Q(cal_DQOut[110]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[111] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[111]),
        .Q(cal_DQOut[111]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[112] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[112]),
        .Q(cal_DQOut[112]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[113] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[113]),
        .Q(cal_DQOut[113]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[114] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[114]),
        .Q(cal_DQOut[114]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[115] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[115]),
        .Q(cal_DQOut[115]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[116] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[116]),
        .Q(cal_DQOut[116]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[117] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[117]),
        .Q(cal_DQOut[117]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[118] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[118]),
        .Q(cal_DQOut[118]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[119] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[119]),
        .Q(cal_DQOut[119]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[11]),
        .Q(cal_DQOut[11]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[120] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[120]),
        .Q(cal_DQOut[120]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[121] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[121]),
        .Q(cal_DQOut[121]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[122] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[122]),
        .Q(cal_DQOut[122]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[123] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[123]),
        .Q(cal_DQOut[123]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[124] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[124]),
        .Q(cal_DQOut[124]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[125] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[125]),
        .Q(cal_DQOut[125]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[126] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[126]),
        .Q(cal_DQOut[126]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[127] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[127]),
        .Q(cal_DQOut[127]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[128] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[128]),
        .Q(cal_DQOut[128]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[129] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[129]),
        .Q(cal_DQOut[129]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[12]),
        .Q(cal_DQOut[12]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[130] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[130]),
        .Q(cal_DQOut[130]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[131] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[131]),
        .Q(cal_DQOut[131]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[132] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[132]),
        .Q(cal_DQOut[132]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[133] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[133]),
        .Q(cal_DQOut[133]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[134] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[134]),
        .Q(cal_DQOut[134]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[135] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[135]),
        .Q(cal_DQOut[135]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[136] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[136]),
        .Q(cal_DQOut[136]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[137] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[137]),
        .Q(cal_DQOut[137]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[138] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[138]),
        .Q(cal_DQOut[138]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[139] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[139]),
        .Q(cal_DQOut[139]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[13]),
        .Q(cal_DQOut[13]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[140] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[140]),
        .Q(cal_DQOut[140]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[141] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[141]),
        .Q(cal_DQOut[141]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[142] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[142]),
        .Q(cal_DQOut[142]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[143] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[143]),
        .Q(cal_DQOut[143]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[144] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[144]),
        .Q(cal_DQOut[144]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[145] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[145]),
        .Q(cal_DQOut[145]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[146] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[146]),
        .Q(cal_DQOut[146]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[147] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[147]),
        .Q(cal_DQOut[147]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[148] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[148]),
        .Q(cal_DQOut[148]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[149] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[149]),
        .Q(cal_DQOut[149]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[14]),
        .Q(cal_DQOut[14]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[150] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[150]),
        .Q(cal_DQOut[150]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[151] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[151]),
        .Q(cal_DQOut[151]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[152] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[152]),
        .Q(cal_DQOut[152]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[153] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[153]),
        .Q(cal_DQOut[153]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[154] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[154]),
        .Q(cal_DQOut[154]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[155] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[155]),
        .Q(cal_DQOut[155]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[156] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[156]),
        .Q(cal_DQOut[156]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[157] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[157]),
        .Q(cal_DQOut[157]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[158] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[158]),
        .Q(cal_DQOut[158]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[159] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[159]),
        .Q(cal_DQOut[159]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[15]),
        .Q(cal_DQOut[15]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[160] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[160]),
        .Q(cal_DQOut[160]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[161] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[161]),
        .Q(cal_DQOut[161]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[162] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[162]),
        .Q(cal_DQOut[162]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[163] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[163]),
        .Q(cal_DQOut[163]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[164] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[164]),
        .Q(cal_DQOut[164]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[165] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[165]),
        .Q(cal_DQOut[165]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[166] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[166]),
        .Q(cal_DQOut[166]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[167] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[167]),
        .Q(cal_DQOut[167]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[168] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[168]),
        .Q(cal_DQOut[168]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[169] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[169]),
        .Q(cal_DQOut[169]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[16]),
        .Q(cal_DQOut[16]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[170] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[170]),
        .Q(cal_DQOut[170]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[171] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[171]),
        .Q(cal_DQOut[171]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[172] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[172]),
        .Q(cal_DQOut[172]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[173] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[173]),
        .Q(cal_DQOut[173]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[174] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[174]),
        .Q(cal_DQOut[174]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[175] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[175]),
        .Q(cal_DQOut[175]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[176] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[176]),
        .Q(cal_DQOut[176]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[177] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[177]),
        .Q(cal_DQOut[177]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[178] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[178]),
        .Q(cal_DQOut[178]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[179] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[179]),
        .Q(cal_DQOut[179]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[17]),
        .Q(cal_DQOut[17]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[180] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[180]),
        .Q(cal_DQOut[180]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[181] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[181]),
        .Q(cal_DQOut[181]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[182] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[182]),
        .Q(cal_DQOut[182]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[183] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[183]),
        .Q(cal_DQOut[183]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[184] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[184]),
        .Q(cal_DQOut[184]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[185] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[185]),
        .Q(cal_DQOut[185]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[186] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[186]),
        .Q(cal_DQOut[186]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[187] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[187]),
        .Q(cal_DQOut[187]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[188] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[188]),
        .Q(cal_DQOut[188]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[189] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[189]),
        .Q(cal_DQOut[189]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[18]),
        .Q(cal_DQOut[18]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[190] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[190]),
        .Q(cal_DQOut[190]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[191] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[191]),
        .Q(cal_DQOut[191]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[192] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[192]),
        .Q(cal_DQOut[192]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[193] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[193]),
        .Q(cal_DQOut[193]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[194] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[194]),
        .Q(cal_DQOut[194]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[195] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[195]),
        .Q(cal_DQOut[195]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[196] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[196]),
        .Q(cal_DQOut[196]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[197] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[197]),
        .Q(cal_DQOut[197]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[198] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[198]),
        .Q(cal_DQOut[198]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[199] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[199]),
        .Q(cal_DQOut[199]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[19]),
        .Q(cal_DQOut[19]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[1]),
        .Q(cal_DQOut[1]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[200] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[200]),
        .Q(cal_DQOut[200]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[201] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[201]),
        .Q(cal_DQOut[201]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[202] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[202]),
        .Q(cal_DQOut[202]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[203] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[203]),
        .Q(cal_DQOut[203]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[204] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[204]),
        .Q(cal_DQOut[204]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[205] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[205]),
        .Q(cal_DQOut[205]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[206] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[206]),
        .Q(cal_DQOut[206]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[207] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[207]),
        .Q(cal_DQOut[207]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[208] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[208]),
        .Q(cal_DQOut[208]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[209] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[209]),
        .Q(cal_DQOut[209]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[20]),
        .Q(cal_DQOut[20]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[210] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[210]),
        .Q(cal_DQOut[210]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[211] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[211]),
        .Q(cal_DQOut[211]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[212] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[212]),
        .Q(cal_DQOut[212]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[213] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[213]),
        .Q(cal_DQOut[213]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[214] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[214]),
        .Q(cal_DQOut[214]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[215] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[215]),
        .Q(cal_DQOut[215]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[216] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[216]),
        .Q(cal_DQOut[216]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[217] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[217]),
        .Q(cal_DQOut[217]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[218] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[218]),
        .Q(cal_DQOut[218]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[219] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[219]),
        .Q(cal_DQOut[219]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[21]),
        .Q(cal_DQOut[21]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[220] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[220]),
        .Q(cal_DQOut[220]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[221] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[221]),
        .Q(cal_DQOut[221]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[222] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[222]),
        .Q(cal_DQOut[222]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[223] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[223]),
        .Q(cal_DQOut[223]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[224] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[224]),
        .Q(cal_DQOut[224]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[225] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[225]),
        .Q(cal_DQOut[225]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[226] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[226]),
        .Q(cal_DQOut[226]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[227] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[227]),
        .Q(cal_DQOut[227]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[228] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[228]),
        .Q(cal_DQOut[228]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[229] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[229]),
        .Q(cal_DQOut[229]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[22]),
        .Q(cal_DQOut[22]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[230] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[230]),
        .Q(cal_DQOut[230]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[231] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[231]),
        .Q(cal_DQOut[231]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[232] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[232]),
        .Q(cal_DQOut[232]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[233] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[233]),
        .Q(cal_DQOut[233]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[234] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[234]),
        .Q(cal_DQOut[234]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[235] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[235]),
        .Q(cal_DQOut[235]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[236] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[236]),
        .Q(cal_DQOut[236]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[237] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[237]),
        .Q(cal_DQOut[237]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[238] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[238]),
        .Q(cal_DQOut[238]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[239] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[239]),
        .Q(cal_DQOut[239]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[23]),
        .Q(cal_DQOut[23]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[240] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[240]),
        .Q(cal_DQOut[240]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[241] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[241]),
        .Q(cal_DQOut[241]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[242] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[242]),
        .Q(cal_DQOut[242]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[243] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[243]),
        .Q(cal_DQOut[243]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[244] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[244]),
        .Q(cal_DQOut[244]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[245] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[245]),
        .Q(cal_DQOut[245]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[246] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[246]),
        .Q(cal_DQOut[246]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[247] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[247]),
        .Q(cal_DQOut[247]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[248] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[248]),
        .Q(cal_DQOut[248]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[249] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[249]),
        .Q(cal_DQOut[249]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[24]),
        .Q(cal_DQOut[24]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[250] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[250]),
        .Q(cal_DQOut[250]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[251] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[251]),
        .Q(cal_DQOut[251]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[252] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[252]),
        .Q(cal_DQOut[252]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[253] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[253]),
        .Q(cal_DQOut[253]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[254] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[254]),
        .Q(cal_DQOut[254]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[255] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[255]),
        .Q(cal_DQOut[255]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[256] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[256]),
        .Q(cal_DQOut[256]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[257] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[257]),
        .Q(cal_DQOut[257]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[258] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[258]),
        .Q(cal_DQOut[258]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[259] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[259]),
        .Q(cal_DQOut[259]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[25]),
        .Q(cal_DQOut[25]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[260] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[260]),
        .Q(cal_DQOut[260]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[261] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[261]),
        .Q(cal_DQOut[261]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[262] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[262]),
        .Q(cal_DQOut[262]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[263] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[263]),
        .Q(cal_DQOut[263]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[264] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[264]),
        .Q(cal_DQOut[264]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[265] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[265]),
        .Q(cal_DQOut[265]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[266] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[266]),
        .Q(cal_DQOut[266]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[267] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[267]),
        .Q(cal_DQOut[267]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[268] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[268]),
        .Q(cal_DQOut[268]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[269] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[269]),
        .Q(cal_DQOut[269]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[26]),
        .Q(cal_DQOut[26]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[270] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[270]),
        .Q(cal_DQOut[270]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[271] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[271]),
        .Q(cal_DQOut[271]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[272] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[272]),
        .Q(cal_DQOut[272]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[273] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[273]),
        .Q(cal_DQOut[273]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[274] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[274]),
        .Q(cal_DQOut[274]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[275] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[275]),
        .Q(cal_DQOut[275]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[276] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[276]),
        .Q(cal_DQOut[276]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[277] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[277]),
        .Q(cal_DQOut[277]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[278] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[278]),
        .Q(cal_DQOut[278]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[279] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[279]),
        .Q(cal_DQOut[279]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[27]),
        .Q(cal_DQOut[27]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[280] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[280]),
        .Q(cal_DQOut[280]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[281] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[281]),
        .Q(cal_DQOut[281]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[282] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[282]),
        .Q(cal_DQOut[282]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[283] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[283]),
        .Q(cal_DQOut[283]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[284] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[284]),
        .Q(cal_DQOut[284]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[285] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[285]),
        .Q(cal_DQOut[285]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[286] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[286]),
        .Q(cal_DQOut[286]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[287] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[287]),
        .Q(cal_DQOut[287]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[288] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[288]),
        .Q(cal_DQOut[288]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[289] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[289]),
        .Q(cal_DQOut[289]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[28]),
        .Q(cal_DQOut[28]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[290] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[290]),
        .Q(cal_DQOut[290]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[291] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[291]),
        .Q(cal_DQOut[291]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[292] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[292]),
        .Q(cal_DQOut[292]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[293] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[293]),
        .Q(cal_DQOut[293]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[294] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[294]),
        .Q(cal_DQOut[294]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[295] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[295]),
        .Q(cal_DQOut[295]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[296] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[296]),
        .Q(cal_DQOut[296]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[297] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[297]),
        .Q(cal_DQOut[297]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[298] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[298]),
        .Q(cal_DQOut[298]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[299] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[299]),
        .Q(cal_DQOut[299]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[29]),
        .Q(cal_DQOut[29]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[2]),
        .Q(cal_DQOut[2]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[300] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[300]),
        .Q(cal_DQOut[300]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[301] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[301]),
        .Q(cal_DQOut[301]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[302] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[302]),
        .Q(cal_DQOut[302]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[303] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[303]),
        .Q(cal_DQOut[303]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[304] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[304]),
        .Q(cal_DQOut[304]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[305] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[305]),
        .Q(cal_DQOut[305]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[306] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[306]),
        .Q(cal_DQOut[306]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[307] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[307]),
        .Q(cal_DQOut[307]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[308] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[308]),
        .Q(cal_DQOut[308]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[309] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[309]),
        .Q(cal_DQOut[309]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[30]),
        .Q(cal_DQOut[30]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[310] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[310]),
        .Q(cal_DQOut[310]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[311] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[311]),
        .Q(cal_DQOut[311]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[312] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[312]),
        .Q(cal_DQOut[312]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[313] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[313]),
        .Q(cal_DQOut[313]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[314] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[314]),
        .Q(cal_DQOut[314]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[315] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[315]),
        .Q(cal_DQOut[315]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[316] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[316]),
        .Q(cal_DQOut[316]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[317] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[317]),
        .Q(cal_DQOut[317]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[318] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[318]),
        .Q(cal_DQOut[318]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[319] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[319]),
        .Q(cal_DQOut[319]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[31]),
        .Q(cal_DQOut[31]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[320] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[320]),
        .Q(cal_DQOut[320]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[321] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[321]),
        .Q(cal_DQOut[321]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[322] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[322]),
        .Q(cal_DQOut[322]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[323] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[323]),
        .Q(cal_DQOut[323]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[324] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[324]),
        .Q(cal_DQOut[324]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[325] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[325]),
        .Q(cal_DQOut[325]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[326] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[326]),
        .Q(cal_DQOut[326]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[327] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[327]),
        .Q(cal_DQOut[327]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[328] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[328]),
        .Q(cal_DQOut[328]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[329] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[329]),
        .Q(cal_DQOut[329]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[32]),
        .Q(cal_DQOut[32]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[330] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[330]),
        .Q(cal_DQOut[330]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[331] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[331]),
        .Q(cal_DQOut[331]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[332] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[332]),
        .Q(cal_DQOut[332]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[333] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[333]),
        .Q(cal_DQOut[333]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[334] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[334]),
        .Q(cal_DQOut[334]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[335] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[335]),
        .Q(cal_DQOut[335]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[336] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[336]),
        .Q(cal_DQOut[336]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[337] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[337]),
        .Q(cal_DQOut[337]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[338] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[338]),
        .Q(cal_DQOut[338]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[339] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[339]),
        .Q(cal_DQOut[339]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[33]),
        .Q(cal_DQOut[33]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[340] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[340]),
        .Q(cal_DQOut[340]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[341] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[341]),
        .Q(cal_DQOut[341]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[342] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[342]),
        .Q(cal_DQOut[342]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[343] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[343]),
        .Q(cal_DQOut[343]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[344] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[344]),
        .Q(cal_DQOut[344]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[345] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[345]),
        .Q(cal_DQOut[345]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[346] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[346]),
        .Q(cal_DQOut[346]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[347] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[347]),
        .Q(cal_DQOut[347]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[348] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[348]),
        .Q(cal_DQOut[348]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[349] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[349]),
        .Q(cal_DQOut[349]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[34]),
        .Q(cal_DQOut[34]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[350] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[350]),
        .Q(cal_DQOut[350]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[351] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[351]),
        .Q(cal_DQOut[351]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[352] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[352]),
        .Q(cal_DQOut[352]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[353] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[353]),
        .Q(cal_DQOut[353]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[354] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[354]),
        .Q(cal_DQOut[354]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[355] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[355]),
        .Q(cal_DQOut[355]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[356] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[356]),
        .Q(cal_DQOut[356]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[357] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[357]),
        .Q(cal_DQOut[357]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[358] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[358]),
        .Q(cal_DQOut[358]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[359] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[359]),
        .Q(cal_DQOut[359]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[35]),
        .Q(cal_DQOut[35]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[360] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[360]),
        .Q(cal_DQOut[360]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[361] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[361]),
        .Q(cal_DQOut[361]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[362] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[362]),
        .Q(cal_DQOut[362]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[363] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[363]),
        .Q(cal_DQOut[363]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[364] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[364]),
        .Q(cal_DQOut[364]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[365] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[365]),
        .Q(cal_DQOut[365]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[366] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[366]),
        .Q(cal_DQOut[366]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[367] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[367]),
        .Q(cal_DQOut[367]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[368] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[368]),
        .Q(cal_DQOut[368]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[369] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[369]),
        .Q(cal_DQOut[369]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[36]),
        .Q(cal_DQOut[36]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[370] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[370]),
        .Q(cal_DQOut[370]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[371] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[371]),
        .Q(cal_DQOut[371]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[372] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[372]),
        .Q(cal_DQOut[372]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[373] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[373]),
        .Q(cal_DQOut[373]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[374] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[374]),
        .Q(cal_DQOut[374]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[375] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[375]),
        .Q(cal_DQOut[375]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[376] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[376]),
        .Q(cal_DQOut[376]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[377] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[377]),
        .Q(cal_DQOut[377]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[378] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[378]),
        .Q(cal_DQOut[378]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[379] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[379]),
        .Q(cal_DQOut[379]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[37]),
        .Q(cal_DQOut[37]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[380] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[380]),
        .Q(cal_DQOut[380]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[381] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[381]),
        .Q(cal_DQOut[381]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[382] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[382]),
        .Q(cal_DQOut[382]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[383] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[383]),
        .Q(cal_DQOut[383]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[384] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[384]),
        .Q(cal_DQOut[384]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[385] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[385]),
        .Q(cal_DQOut[385]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[386] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[386]),
        .Q(cal_DQOut[386]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[387] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[387]),
        .Q(cal_DQOut[387]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[388] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[388]),
        .Q(cal_DQOut[388]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[389] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[389]),
        .Q(cal_DQOut[389]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[38]),
        .Q(cal_DQOut[38]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[390] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[390]),
        .Q(cal_DQOut[390]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[391] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[391]),
        .Q(cal_DQOut[391]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[392] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[392]),
        .Q(cal_DQOut[392]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[393] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[393]),
        .Q(cal_DQOut[393]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[394] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[394]),
        .Q(cal_DQOut[394]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[395] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[395]),
        .Q(cal_DQOut[395]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[396] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[396]),
        .Q(cal_DQOut[396]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[397] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[397]),
        .Q(cal_DQOut[397]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[398] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[398]),
        .Q(cal_DQOut[398]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[399] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[399]),
        .Q(cal_DQOut[399]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[39]),
        .Q(cal_DQOut[39]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[3]),
        .Q(cal_DQOut[3]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[400] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[400]),
        .Q(cal_DQOut[400]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[401] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[401]),
        .Q(cal_DQOut[401]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[402] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[402]),
        .Q(cal_DQOut[402]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[403] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[403]),
        .Q(cal_DQOut[403]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[404] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[404]),
        .Q(cal_DQOut[404]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[405] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[405]),
        .Q(cal_DQOut[405]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[406] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[406]),
        .Q(cal_DQOut[406]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[407] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[407]),
        .Q(cal_DQOut[407]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[408] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[408]),
        .Q(cal_DQOut[408]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[409] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[409]),
        .Q(cal_DQOut[409]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[40]),
        .Q(cal_DQOut[40]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[410] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[410]),
        .Q(cal_DQOut[410]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[411] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[411]),
        .Q(cal_DQOut[411]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[412] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[412]),
        .Q(cal_DQOut[412]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[413] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[413]),
        .Q(cal_DQOut[413]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[414] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[414]),
        .Q(cal_DQOut[414]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[415] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[415]),
        .Q(cal_DQOut[415]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[416] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[416]),
        .Q(cal_DQOut[416]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[417] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[417]),
        .Q(cal_DQOut[417]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[418] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[418]),
        .Q(cal_DQOut[418]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[419] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[419]),
        .Q(cal_DQOut[419]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[41]),
        .Q(cal_DQOut[41]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[420] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[420]),
        .Q(cal_DQOut[420]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[421] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[421]),
        .Q(cal_DQOut[421]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[422] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[422]),
        .Q(cal_DQOut[422]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[423] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[423]),
        .Q(cal_DQOut[423]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[424] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[424]),
        .Q(cal_DQOut[424]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[425] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[425]),
        .Q(cal_DQOut[425]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[426] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[426]),
        .Q(cal_DQOut[426]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[427] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[427]),
        .Q(cal_DQOut[427]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[428] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[428]),
        .Q(cal_DQOut[428]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[429] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[429]),
        .Q(cal_DQOut[429]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[42]),
        .Q(cal_DQOut[42]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[430] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[430]),
        .Q(cal_DQOut[430]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[431] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[431]),
        .Q(cal_DQOut[431]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[432] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[432]),
        .Q(cal_DQOut[432]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[433] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[433]),
        .Q(cal_DQOut[433]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[434] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[434]),
        .Q(cal_DQOut[434]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[435] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[435]),
        .Q(cal_DQOut[435]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[436] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[436]),
        .Q(cal_DQOut[436]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[437] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[437]),
        .Q(cal_DQOut[437]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[438] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[438]),
        .Q(cal_DQOut[438]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[439] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[439]),
        .Q(cal_DQOut[439]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[43]),
        .Q(cal_DQOut[43]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[440] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[440]),
        .Q(cal_DQOut[440]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[441] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[441]),
        .Q(cal_DQOut[441]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[442] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[442]),
        .Q(cal_DQOut[442]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[443] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[443]),
        .Q(cal_DQOut[443]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[444] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[444]),
        .Q(cal_DQOut[444]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[445] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[445]),
        .Q(cal_DQOut[445]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[446] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[446]),
        .Q(cal_DQOut[446]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[447] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[447]),
        .Q(cal_DQOut[447]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[448] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[448]),
        .Q(cal_DQOut[448]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[449] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[449]),
        .Q(cal_DQOut[449]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[44]),
        .Q(cal_DQOut[44]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[450] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[450]),
        .Q(cal_DQOut[450]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[451] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[451]),
        .Q(cal_DQOut[451]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[452] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[452]),
        .Q(cal_DQOut[452]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[453] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[453]),
        .Q(cal_DQOut[453]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[454] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[454]),
        .Q(cal_DQOut[454]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[455] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[455]),
        .Q(cal_DQOut[455]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[456] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[456]),
        .Q(cal_DQOut[456]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[457] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[457]),
        .Q(cal_DQOut[457]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[458] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[458]),
        .Q(cal_DQOut[458]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[459] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[459]),
        .Q(cal_DQOut[459]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[45]),
        .Q(cal_DQOut[45]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[460] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[460]),
        .Q(cal_DQOut[460]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[461] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[461]),
        .Q(cal_DQOut[461]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[462] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[462]),
        .Q(cal_DQOut[462]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[463] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[463]),
        .Q(cal_DQOut[463]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[464] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[464]),
        .Q(cal_DQOut[464]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[465] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[465]),
        .Q(cal_DQOut[465]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[466] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[466]),
        .Q(cal_DQOut[466]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[467] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[467]),
        .Q(cal_DQOut[467]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[468] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[468]),
        .Q(cal_DQOut[468]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[469] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[469]),
        .Q(cal_DQOut[469]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[46]),
        .Q(cal_DQOut[46]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[470] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[470]),
        .Q(cal_DQOut[470]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[471] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[471]),
        .Q(cal_DQOut[471]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[472] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[472]),
        .Q(cal_DQOut[472]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[473] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[473]),
        .Q(cal_DQOut[473]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[474] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[474]),
        .Q(cal_DQOut[474]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[475] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[475]),
        .Q(cal_DQOut[475]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[476] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[476]),
        .Q(cal_DQOut[476]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[477] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[477]),
        .Q(cal_DQOut[477]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[478] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[478]),
        .Q(cal_DQOut[478]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[479] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[479]),
        .Q(cal_DQOut[479]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[47]),
        .Q(cal_DQOut[47]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[480] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[480]),
        .Q(cal_DQOut[480]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[481] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[481]),
        .Q(cal_DQOut[481]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[482] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[482]),
        .Q(cal_DQOut[482]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[483] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[483]),
        .Q(cal_DQOut[483]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[484] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[484]),
        .Q(cal_DQOut[484]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[485] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[485]),
        .Q(cal_DQOut[485]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[486] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[486]),
        .Q(cal_DQOut[486]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[487] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[487]),
        .Q(cal_DQOut[487]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[488] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[488]),
        .Q(cal_DQOut[488]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[489] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[489]),
        .Q(cal_DQOut[489]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[48]),
        .Q(cal_DQOut[48]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[490] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[490]),
        .Q(cal_DQOut[490]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[491] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[491]),
        .Q(cal_DQOut[491]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[492] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[492]),
        .Q(cal_DQOut[492]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[493] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[493]),
        .Q(cal_DQOut[493]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[494] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[494]),
        .Q(cal_DQOut[494]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[495] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[495]),
        .Q(cal_DQOut[495]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[496] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[496]),
        .Q(cal_DQOut[496]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[497] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[497]),
        .Q(cal_DQOut[497]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[498] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[498]),
        .Q(cal_DQOut[498]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[499] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[499]),
        .Q(cal_DQOut[499]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[49]),
        .Q(cal_DQOut[49]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[4]),
        .Q(cal_DQOut[4]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[500] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[500]),
        .Q(cal_DQOut[500]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[501] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[501]),
        .Q(cal_DQOut[501]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[502] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[502]),
        .Q(cal_DQOut[502]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[503] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[503]),
        .Q(cal_DQOut[503]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[504] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[504]),
        .Q(cal_DQOut[504]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[505] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[505]),
        .Q(cal_DQOut[505]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[506] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[506]),
        .Q(cal_DQOut[506]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[507] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[507]),
        .Q(cal_DQOut[507]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[508] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[508]),
        .Q(cal_DQOut[508]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[509] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[509]),
        .Q(cal_DQOut[509]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[50]),
        .Q(cal_DQOut[50]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[510] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[510]),
        .Q(cal_DQOut[510]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[511] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[511]),
        .Q(cal_DQOut[511]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[51]),
        .Q(cal_DQOut[51]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[52]),
        .Q(cal_DQOut[52]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[53]),
        .Q(cal_DQOut[53]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[54]),
        .Q(cal_DQOut[54]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[55]),
        .Q(cal_DQOut[55]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[56]),
        .Q(cal_DQOut[56]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[57]),
        .Q(cal_DQOut[57]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[58]),
        .Q(cal_DQOut[58]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[59]),
        .Q(cal_DQOut[59]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[5]),
        .Q(cal_DQOut[5]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[60]),
        .Q(cal_DQOut[60]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[61]),
        .Q(cal_DQOut[61]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[62]),
        .Q(cal_DQOut[62]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[63]),
        .Q(cal_DQOut[63]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[64] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[64]),
        .Q(cal_DQOut[64]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[65] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[65]),
        .Q(cal_DQOut[65]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[66] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[66]),
        .Q(cal_DQOut[66]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[67] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[67]),
        .Q(cal_DQOut[67]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[68] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[68]),
        .Q(cal_DQOut[68]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[69] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[69]),
        .Q(cal_DQOut[69]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[6]),
        .Q(cal_DQOut[6]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[70] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[70]),
        .Q(cal_DQOut[70]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[71] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[71]),
        .Q(cal_DQOut[71]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[72] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[72]),
        .Q(cal_DQOut[72]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[73] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[73]),
        .Q(cal_DQOut[73]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[74] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[74]),
        .Q(cal_DQOut[74]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[75] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[75]),
        .Q(cal_DQOut[75]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[76] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[76]),
        .Q(cal_DQOut[76]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[77] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[77]),
        .Q(cal_DQOut[77]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[78] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[78]),
        .Q(cal_DQOut[78]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[79] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[79]),
        .Q(cal_DQOut[79]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[7]),
        .Q(cal_DQOut[7]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[80] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[80]),
        .Q(cal_DQOut[80]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[81] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[81]),
        .Q(cal_DQOut[81]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[82] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[82]),
        .Q(cal_DQOut[82]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[83] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[83]),
        .Q(cal_DQOut[83]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[84] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[84]),
        .Q(cal_DQOut[84]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[85] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[85]),
        .Q(cal_DQOut[85]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[86] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[86]),
        .Q(cal_DQOut[86]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[87] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[87]),
        .Q(cal_DQOut[87]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[88] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[88]),
        .Q(cal_DQOut[88]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[89] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[89]),
        .Q(cal_DQOut[89]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[8]),
        .Q(cal_DQOut[8]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[90] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[90]),
        .Q(cal_DQOut[90]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[91] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[91]),
        .Q(cal_DQOut[91]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[92] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[92]),
        .Q(cal_DQOut[92]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[93] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[93]),
        .Q(cal_DQOut[93]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[94] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[94]),
        .Q(cal_DQOut[94]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[95] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[95]),
        .Q(cal_DQOut[95]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[96] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[96]),
        .Q(cal_DQOut[96]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[97] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[97]),
        .Q(cal_DQOut[97]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[98] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[98]),
        .Q(cal_DQOut[98]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[99] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[99]),
        .Q(cal_DQOut[99]),
        .R(1'b0));
  FDRE \cal_DQOut_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_DQOut_nxt[9]),
        .Q(cal_DQOut[9]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_DQPat_A_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_DQPat_A_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_DQPat_A_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_DQPat_A_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_DQPat_A_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_DQPat_A_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_DQPat_A_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_DQPat_A_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_DQPat_A_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_DQPat_A_reg_n_0_[18] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_DQPat_A_reg_n_0_[19] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_DQPat_A_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_DQPat_A_reg_n_0_[20] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_DQPat_A_reg_n_0_[21] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_DQPat_A_reg_n_0_[22] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_DQPat_A_reg_n_0_[23] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_DQPat_A_reg_n_0_[24] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_DQPat_A_reg_n_0_[25] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_DQPat_A_reg_n_0_[26] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_DQPat_A_reg_n_0_[27] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_DQPat_A_reg_n_0_[28] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_DQPat_A_reg_n_0_[29] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_DQPat_A_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_DQPat_A_reg_n_0_[30] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_DQPat_A_reg_n_0_[31] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_DQPat_A_reg_n_0_[32] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_DQPat_A_reg_n_0_[33] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_DQPat_A_reg_n_0_[34] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_DQPat_A_reg_n_0_[35] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_DQPat_A_reg_n_0_[36] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_DQPat_A_reg_n_0_[37] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_DQPat_A_reg_n_0_[38] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_DQPat_A_reg_n_0_[39] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_DQPat_A_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_DQPat_A_reg_n_0_[40] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_DQPat_A_reg_n_0_[41] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_DQPat_A_reg_n_0_[42] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_DQPat_A_reg_n_0_[43] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_DQPat_A_reg_n_0_[44] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_DQPat_A_reg_n_0_[45] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_DQPat_A_reg_n_0_[46] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_DQPat_A_reg_n_0_[47] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_DQPat_A_reg_n_0_[48] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_DQPat_A_reg_n_0_[49] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_DQPat_A_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_DQPat_A_reg_n_0_[50] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_DQPat_A_reg_n_0_[51] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_DQPat_A_reg_n_0_[52] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_DQPat_A_reg_n_0_[53] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_DQPat_A_reg_n_0_[54] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_DQPat_A_reg_n_0_[55] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_DQPat_A_reg_n_0_[56] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_DQPat_A_reg_n_0_[57] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_DQPat_A_reg_n_0_[58] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_DQPat_A_reg_n_0_[59] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_DQPat_A_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_DQPat_A_reg_n_0_[60] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_DQPat_A_reg_n_0_[61] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_DQPat_A_reg_n_0_[62] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[63]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_DQPat_A_reg_n_0_[63] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_DQPat_A_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_DQPat_A_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_DQPat_A_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_A_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_A_reg[31]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_DQPat_A_reg_n_0_[9] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_DQPat_B_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_DQPat_B_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_DQPat_B_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_DQPat_B_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_DQPat_B_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_DQPat_B_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_DQPat_B_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_DQPat_B_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_DQPat_B_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_DQPat_B_reg_n_0_[18] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_DQPat_B_reg_n_0_[19] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_DQPat_B_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_DQPat_B_reg_n_0_[20] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_DQPat_B_reg_n_0_[21] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_DQPat_B_reg_n_0_[22] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_DQPat_B_reg_n_0_[23] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_DQPat_B_reg_n_0_[24] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_DQPat_B_reg_n_0_[25] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_DQPat_B_reg_n_0_[26] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_DQPat_B_reg_n_0_[27] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_DQPat_B_reg_n_0_[28] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_DQPat_B_reg_n_0_[29] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_DQPat_B_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_DQPat_B_reg_n_0_[30] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_DQPat_B_reg_n_0_[31] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_DQPat_B_reg_n_0_[32] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_DQPat_B_reg_n_0_[33] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_DQPat_B_reg_n_0_[34] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_DQPat_B_reg_n_0_[35] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_DQPat_B_reg_n_0_[36] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_DQPat_B_reg_n_0_[37] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_DQPat_B_reg_n_0_[38] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_DQPat_B_reg_n_0_[39] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_DQPat_B_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_DQPat_B_reg_n_0_[40] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_DQPat_B_reg_n_0_[41] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_DQPat_B_reg_n_0_[42] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_DQPat_B_reg_n_0_[43] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_DQPat_B_reg_n_0_[44] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_DQPat_B_reg_n_0_[45] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_DQPat_B_reg_n_0_[46] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_DQPat_B_reg_n_0_[47] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_DQPat_B_reg_n_0_[48] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_DQPat_B_reg_n_0_[49] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_DQPat_B_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_DQPat_B_reg_n_0_[50] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_DQPat_B_reg_n_0_[51] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_DQPat_B_reg_n_0_[52] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_DQPat_B_reg_n_0_[53] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_DQPat_B_reg_n_0_[54] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_DQPat_B_reg_n_0_[55] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_DQPat_B_reg_n_0_[56] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_DQPat_B_reg_n_0_[57] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_DQPat_B_reg_n_0_[58] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_DQPat_B_reg_n_0_[59] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_DQPat_B_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_DQPat_B_reg_n_0_[60] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_DQPat_B_reg_n_0_[61] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_DQPat_B_reg_n_0_[62] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[63]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_DQPat_B_reg_n_0_[63] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_DQPat_B_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_DQPat_B_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_DQPat_B_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_DQPat_B_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_DQPat_B_reg[31]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_DQPat_B_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1031" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[0]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[448]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1081" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[100]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[484]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[100]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1081" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[101]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[485]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[101]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1082" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[102]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[486]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[102]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1082" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[103]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[487]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[103]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1083" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[104]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[488]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[104]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1083" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[105]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[489]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[105]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1084" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[106]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[490]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[106]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1084" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[107]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[491]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[107]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1085" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[108]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[492]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[108]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1085" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[109]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[493]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[109]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1036" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[10]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[458]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1086" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[110]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[494]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[110]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1086" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[111]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[495]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[111]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1087" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[112]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[496]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[112]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1087" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[113]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[497]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[113]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1088" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[114]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[498]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[114]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1088" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[115]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[499]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[115]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1089" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[116]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[500]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[116]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1089" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[117]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[501]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[117]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1090" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[118]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[502]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[118]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1090" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[119]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[503]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[119]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1036" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[11]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[459]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1091" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[120]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[504]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[120]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1091" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[121]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[505]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[121]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1092" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[122]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[506]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[122]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1092" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[123]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[507]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[123]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1093" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[124]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[508]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[124]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1093" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[125]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[509]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[125]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1094" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[126]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[510]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[126]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1094" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[127]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[127]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAA8AAAAAAAA)) 
    \cal_DQ[127]_i_2 
       (.I0(\cal_DQ[511]_i_5_n_0 ),
        .I1(\dram_device_sel_reg_n_0_[4] ),
        .I2(\dram_device_sel_reg_n_0_[5] ),
        .I3(\dram_device_sel_reg_n_0_[1] ),
        .I4(\dram_device_sel_reg_n_0_[7] ),
        .I5(\cal_DQ[255]_i_3_n_0 ),
        .O(\cal_DQ[127]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair967" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[128]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[448]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[128]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair967" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[129]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[449]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[129]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1037" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[12]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[460]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair968" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[130]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[450]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[130]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair968" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[131]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[451]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[131]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair969" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[132]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[452]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[132]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair969" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[133]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[453]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[133]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair970" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[134]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[454]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[134]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair970" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[135]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[455]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[135]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair971" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[136]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[456]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[136]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair971" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[137]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[457]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[137]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair972" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[138]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[458]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[138]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair972" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[139]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[459]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[139]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1037" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[13]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[461]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair973" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[140]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[460]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[140]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair973" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[141]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[461]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[141]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair974" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[142]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[462]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[142]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair974" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[143]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[463]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[143]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair975" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[144]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[464]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[144]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair975" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[145]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[465]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[145]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair976" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[146]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[466]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[146]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair976" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[147]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[467]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[147]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair977" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[148]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[468]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[148]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair977" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[149]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[469]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[149]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1038" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[14]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[462]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair978" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[150]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[470]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[150]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair978" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[151]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[471]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[151]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair979" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[152]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[472]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[152]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair979" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[153]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[473]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[153]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair980" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[154]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[474]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[154]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair980" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[155]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[475]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[155]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair981" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[156]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[476]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[156]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair981" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[157]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[477]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[157]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair982" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[158]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[478]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[158]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair982" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[159]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[479]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[159]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1038" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[15]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[463]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair983" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[160]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[480]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[160]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair983" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[161]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[481]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[161]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair984" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[162]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[482]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[162]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair984" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[163]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[483]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[163]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair985" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[164]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[484]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[164]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair985" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[165]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[485]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[165]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair986" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[166]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[486]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[166]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair986" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[167]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[487]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[167]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair987" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[168]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[488]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[168]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair987" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[169]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[489]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[169]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1039" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[16]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[464]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair988" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[170]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[490]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[170]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair988" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[171]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[491]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[171]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair989" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[172]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[492]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[172]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair989" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[173]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[493]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[173]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair990" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[174]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[494]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[174]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair990" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[175]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[495]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[175]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair991" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[176]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[496]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[176]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair991" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[177]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[497]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[177]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair992" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[178]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[498]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[178]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair992" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[179]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[499]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[179]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1039" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[17]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[465]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[17]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair993" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[180]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[500]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[180]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair993" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[181]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[501]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[181]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair994" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[182]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[502]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[182]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair994" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[183]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[503]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[183]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair995" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[184]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[504]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[184]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair995" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[185]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[505]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[185]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair996" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[186]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[506]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[186]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair996" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[187]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[507]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[187]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair997" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[188]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[508]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[188]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair997" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[189]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[509]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[189]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1040" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[18]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[466]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[18]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair998" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[190]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[510]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[190]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair998" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[191]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[2] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_2_n_0 ),
        .I3(\cal_DQ[191]_i_2_n_0 ),
        .O(\cal_DQ[191]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAA2AAAAAAAA)) 
    \cal_DQ[191]_i_2 
       (.I0(\cal_DQ[511]_i_5_n_0 ),
        .I1(\dram_device_sel_reg_n_0_[1] ),
        .I2(\dram_device_sel_reg_n_0_[5] ),
        .I3(\dram_device_sel_reg_n_0_[0] ),
        .I4(\dram_device_sel_reg_n_0_[7] ),
        .I5(\cal_DQ[191]_i_3_n_0 ),
        .O(\cal_DQ[191]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1160" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \cal_DQ[191]_i_3 
       (.I0(\dram_device_sel_reg_n_0_[4] ),
        .I1(\dram_device_sel_reg_n_0_[6] ),
        .I2(\dram_device_sel_reg_n_0_[3] ),
        .I3(\dram_device_sel_reg_n_0_[2] ),
        .O(\cal_DQ[191]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1095" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[192]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[448]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[192]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1095" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[193]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[449]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[193]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1096" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[194]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[450]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[194]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1096" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[195]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[451]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[195]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1097" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[196]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[452]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[196]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1097" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[197]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[453]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[197]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1098" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[198]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[454]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[198]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1098" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[199]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[455]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[199]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1040" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[19]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[467]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[19]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1031" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[1]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[449]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1099" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[200]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[456]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[200]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1099" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[201]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[457]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[201]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1100" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[202]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[458]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[202]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1100" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[203]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[459]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[203]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1101" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[204]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[460]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[204]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1101" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[205]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[461]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[205]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1102" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[206]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[462]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[206]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1102" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[207]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[463]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[207]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1103" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[208]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[464]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[208]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1103" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[209]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[465]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[209]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1041" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[20]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[468]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1104" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[210]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[466]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[210]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1104" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[211]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[467]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[211]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1105" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[212]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[468]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[212]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1105" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[213]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[469]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[213]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1106" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[214]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[470]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[214]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1106" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[215]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[471]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[215]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1107" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[216]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[472]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[216]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1107" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[217]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[473]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[217]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1108" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[218]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[474]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[218]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1108" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[219]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[475]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[219]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1041" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[21]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[469]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1109" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[220]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[476]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[220]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1109" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[221]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[477]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[221]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1110" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[222]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[478]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[222]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1110" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[223]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[479]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[223]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1111" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[224]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[480]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[224]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1111" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[225]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[481]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[225]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1112" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[226]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[482]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[226]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1112" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[227]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[483]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[227]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1113" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[228]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[484]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[228]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1113" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[229]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[485]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[229]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1042" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[22]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[470]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1114" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[230]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[486]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[230]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1114" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[231]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[487]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[231]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1115" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[232]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[488]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[232]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1115" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[233]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[489]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[233]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1116" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[234]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[490]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[234]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1116" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[235]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[491]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[235]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1117" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[236]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[492]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[236]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1117" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[237]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[493]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[237]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1118" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[238]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[494]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[238]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1118" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[239]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[495]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[239]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1042" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[23]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[471]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[23]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1119" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[240]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[496]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[240]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1119" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[241]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[497]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[241]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1120" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[242]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[498]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[242]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1120" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[243]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[499]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[243]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1121" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[244]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[500]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[244]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1121" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[245]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[501]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[245]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1122" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[246]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[502]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[246]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1122" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[247]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[503]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[247]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1123" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[248]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[504]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[248]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1123" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[249]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[505]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[249]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1043" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[24]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[472]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[24]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1124" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[250]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[506]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[250]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1124" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[251]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[507]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[251]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1125" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[252]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[508]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[252]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1125" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[253]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[509]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[253]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1126" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[254]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[510]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[254]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1126" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[255]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[3] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_2_n_0 ),
        .I3(\cal_DQ[255]_i_2_n_0 ),
        .O(\cal_DQ[255]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAA8AAAAAAAAAA)) 
    \cal_DQ[255]_i_2 
       (.I0(\cal_DQ[511]_i_5_n_0 ),
        .I1(\dram_device_sel_reg_n_0_[5] ),
        .I2(\dram_device_sel_reg_n_0_[7] ),
        .I3(\dram_device_sel_reg_n_0_[1] ),
        .I4(\dram_device_sel_reg_n_0_[4] ),
        .I5(\cal_DQ[255]_i_3_n_0 ),
        .O(\cal_DQ[255]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0004)) 
    \cal_DQ[255]_i_3 
       (.I0(\dram_device_sel_reg_n_0_[6] ),
        .I1(\dram_device_sel_reg_n_0_[0] ),
        .I2(\dram_device_sel_reg_n_0_[3] ),
        .I3(\dram_device_sel_reg_n_0_[2] ),
        .O(\cal_DQ[255]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair935" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[256]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[448]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[256]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair935" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[257]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[449]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[257]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair936" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[258]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[450]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[258]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair936" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[259]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[451]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[259]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1043" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[25]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[473]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[25]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair937" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[260]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[452]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[260]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair937" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[261]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[453]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[261]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair938" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[262]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[454]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[262]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair938" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[263]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[455]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[263]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair939" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[264]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[456]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[264]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair939" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[265]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[457]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[265]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair940" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[266]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[458]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[266]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair940" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[267]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[459]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[267]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair941" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[268]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[460]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[268]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair941" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[269]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[461]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[269]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1044" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[26]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[474]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[26]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair942" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[270]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[462]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[270]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair942" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[271]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[463]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[271]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair943" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[272]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[464]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[272]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair943" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[273]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[465]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[273]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair944" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[274]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[466]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[274]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair944" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[275]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[467]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[275]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair945" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[276]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[468]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[276]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair945" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[277]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[469]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[277]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair946" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[278]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[470]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[278]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair946" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[279]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[471]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[279]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1044" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[27]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[475]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[27]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair947" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[280]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[472]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[280]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair947" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[281]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[473]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[281]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair948" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[282]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[474]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[282]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair948" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[283]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[475]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[283]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair949" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[284]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[476]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[284]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair949" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[285]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[477]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[285]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair950" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[286]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[478]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[286]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair950" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[287]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[479]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[287]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair951" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[288]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[480]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[288]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair951" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[289]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[481]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[289]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1045" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[28]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[476]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair952" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[290]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[482]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[290]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair952" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[291]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[483]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[291]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair953" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[292]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[484]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[292]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair953" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[293]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[485]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[293]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair954" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[294]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[486]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[294]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair954" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[295]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[487]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[295]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair955" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[296]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[488]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[296]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair955" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[297]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[489]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[297]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair956" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[298]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[490]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[298]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair956" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[299]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[491]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[299]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1045" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[29]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[477]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1032" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[2]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[450]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair957" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[300]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[492]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[300]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair957" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[301]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[493]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[301]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair958" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[302]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[494]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[302]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair958" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[303]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[495]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[303]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair959" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[304]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[496]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[304]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair959" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[305]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[497]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[305]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair960" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[306]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[498]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[306]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair960" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[307]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[499]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[307]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair961" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[308]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[500]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[308]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair961" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[309]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[501]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[309]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1046" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[30]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[478]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[30]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair962" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[310]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[502]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[310]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair962" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[311]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[503]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[311]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair963" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[312]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[504]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[312]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair963" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[313]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[505]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[313]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair964" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[314]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[506]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[314]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair964" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[315]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[507]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[315]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair965" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[316]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[508]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[316]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair965" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[317]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[509]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[317]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair966" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[318]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[510]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[318]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair966" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[319]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[4] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_2_n_0 ),
        .I3(\cal_DQ[319]_i_2_n_0 ),
        .O(\cal_DQ[319]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA8)) 
    \cal_DQ[319]_i_2 
       (.I0(\cal_DQ[511]_i_5_n_0 ),
        .I1(\cal_DQ[319]_i_3_n_0 ),
        .I2(\dram_device_sel_reg_n_0_[3] ),
        .I3(\dram_device_sel_reg_n_0_[7] ),
        .I4(\dram_device_sel_reg_n_0_[0] ),
        .I5(\dram_device_sel_reg_n_0_[1] ),
        .O(\cal_DQ[319]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1159" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    \cal_DQ[319]_i_3 
       (.I0(\dram_device_sel_reg_n_0_[4] ),
        .I1(\dram_device_sel_reg_n_0_[5] ),
        .I2(\dram_device_sel_reg_n_0_[2] ),
        .I3(\dram_device_sel_reg_n_0_[6] ),
        .O(\cal_DQ[319]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1046" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[31]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[479]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair999" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[320]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[448]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[320]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair999" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[321]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[449]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[321]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1000" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[322]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[450]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[322]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1000" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[323]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[451]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[323]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1001" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[324]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[452]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[324]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1001" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[325]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[453]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[325]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1002" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[326]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[454]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[326]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1002" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[327]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[455]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[327]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1003" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[328]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[456]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[328]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1003" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[329]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[457]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[329]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1047" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[32]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[480]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[32]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1004" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[330]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[458]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[330]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1004" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[331]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[459]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[331]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1005" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[332]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[460]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[332]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1005" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[333]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[461]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[333]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1006" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[334]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[462]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[334]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1006" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[335]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[463]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[335]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1007" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[336]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[464]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[336]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1007" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[337]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[465]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[337]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1008" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[338]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[466]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[338]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1008" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[339]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[467]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[339]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1047" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[33]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[481]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[33]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1009" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[340]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[468]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[340]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1009" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[341]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[469]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[341]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1010" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[342]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[470]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[342]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1010" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[343]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[471]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[343]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1011" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[344]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[472]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[344]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1011" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[345]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[473]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[345]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1012" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[346]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[474]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[346]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1012" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[347]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[475]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[347]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1013" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[348]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[476]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[348]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1013" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[349]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[477]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[349]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1048" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[34]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[482]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[34]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1014" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[350]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[478]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[350]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1014" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[351]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[479]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[351]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1015" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[352]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[480]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[352]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1015" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[353]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[481]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[353]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1016" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[354]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[482]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[354]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1016" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[355]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[483]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[355]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1017" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[356]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[484]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[356]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1017" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[357]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[485]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[357]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1018" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[358]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[486]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[358]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1018" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[359]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[487]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[359]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1048" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[35]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[483]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[35]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1019" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[360]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[488]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[360]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1019" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[361]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[489]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[361]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1020" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[362]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[490]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[362]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1020" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[363]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[491]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[363]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1021" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[364]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[492]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[364]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1021" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[365]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[493]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[365]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1022" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[366]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[494]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[366]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1022" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[367]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[495]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[367]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1023" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[368]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[496]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[368]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1023" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[369]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[497]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[369]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1049" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[36]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[484]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[36]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1024" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[370]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[498]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[370]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1024" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[371]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[499]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[371]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1025" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[372]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[500]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[372]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1025" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[373]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[501]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[373]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1026" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[374]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[502]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[374]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1026" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[375]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[503]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[375]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1027" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[376]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[504]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[376]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1027" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[377]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[505]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[377]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1028" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[378]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[506]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[378]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1028" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[379]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[507]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[379]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1049" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[37]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[485]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[37]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1029" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[380]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[508]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[380]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1029" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[381]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[509]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[381]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1030" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[382]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[510]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[382]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1030" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[383]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[5] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_2_n_0 ),
        .I3(\cal_DQ[383]_i_2_n_0 ),
        .O(\cal_DQ[383]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAA8AAAAAAAA)) 
    \cal_DQ[383]_i_2 
       (.I0(\cal_DQ[511]_i_5_n_0 ),
        .I1(\dram_device_sel_reg_n_0_[1] ),
        .I2(\dram_device_sel_reg_n_0_[7] ),
        .I3(\dram_device_sel_reg_n_0_[3] ),
        .I4(\dram_device_sel_reg_n_0_[5] ),
        .I5(\cal_DQ[511]_i_6_n_0 ),
        .O(\cal_DQ[383]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1127" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[384]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[448]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[384]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1127" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[385]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[449]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[385]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1128" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[386]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[450]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[386]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1128" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[387]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[451]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[387]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1129" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[388]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[452]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[388]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1129" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[389]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[453]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[389]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1050" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[38]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[486]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[38]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1130" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[390]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[454]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[390]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1130" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[391]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[455]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[391]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1131" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[392]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[456]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[392]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1131" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[393]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[457]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[393]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1132" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[394]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[458]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[394]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1132" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[395]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[459]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[395]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1133" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[396]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[460]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[396]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1133" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[397]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[461]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[397]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1134" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[398]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[462]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[398]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1134" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[399]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[463]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[399]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1050" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[39]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[487]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[39]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1032" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[3]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[451]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1135" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[400]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[464]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[400]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1135" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[401]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[465]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[401]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1136" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[402]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[466]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[402]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1136" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[403]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[467]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[403]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1137" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[404]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[468]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[404]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1137" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[405]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[469]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[405]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1138" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[406]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[470]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[406]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1138" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[407]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[471]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[407]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1139" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[408]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[472]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[408]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1139" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[409]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[473]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[409]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1051" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[40]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[488]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[40]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1140" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[410]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[474]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[410]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1140" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[411]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[475]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[411]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1141" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[412]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[476]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[412]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1141" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[413]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[477]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[413]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1142" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[414]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[478]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[414]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1142" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[415]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[479]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[415]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1143" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[416]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[480]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[416]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1143" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[417]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[481]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[417]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1144" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[418]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[482]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[418]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1144" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[419]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[483]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[419]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1051" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[41]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[489]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[41]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1145" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[420]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[484]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[420]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1145" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[421]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[485]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[421]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1146" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[422]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[486]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[422]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1146" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[423]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[487]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[423]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1147" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[424]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[488]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[424]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1147" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[425]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[489]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[425]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1148" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[426]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[490]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[426]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1148" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[427]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[491]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[427]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1149" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[428]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[492]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[428]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1149" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[429]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[493]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[429]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1052" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[42]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[490]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[42]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1150" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[430]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[494]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[430]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1150" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[431]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[495]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[431]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1151" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[432]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[496]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[432]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1151" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[433]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[497]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[433]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1152" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[434]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[498]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[434]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1152" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[435]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[499]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[435]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1153" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[436]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[500]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[436]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1153" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[437]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[501]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[437]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1154" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[438]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[502]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[438]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1154" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[439]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[503]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[439]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1052" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[43]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[491]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[43]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1155" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[440]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[504]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[440]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1155" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[441]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[505]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[441]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1156" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[442]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[506]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[442]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1156" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[443]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[507]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[443]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1157" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[444]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[508]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[444]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1157" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[445]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[509]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[445]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1158" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[446]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[510]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[446]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1158" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[447]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[6] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_2_n_0 ),
        .I3(\cal_DQ[447]_i_2_n_0 ),
        .O(\cal_DQ[447]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA8)) 
    \cal_DQ[447]_i_2 
       (.I0(\cal_DQ[511]_i_5_n_0 ),
        .I1(\cal_DQ[447]_i_3_n_0 ),
        .I2(\dram_device_sel_reg_n_0_[3] ),
        .I3(\dram_device_sel_reg_n_0_[5] ),
        .I4(\dram_device_sel_reg_n_0_[0] ),
        .I5(\dram_device_sel_reg_n_0_[7] ),
        .O(\cal_DQ[447]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1159" *) 
  LUT4 #(
    .INIT(16'hFFDF)) 
    \cal_DQ[447]_i_3 
       (.I0(\dram_device_sel_reg_n_0_[2] ),
        .I1(\dram_device_sel_reg_n_0_[6] ),
        .I2(\dram_device_sel_reg_n_0_[1] ),
        .I3(\dram_device_sel_reg_n_0_[4] ),
        .O(\cal_DQ[447]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair903" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[448]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[448]_i_2_n_0 ),
        .O(\cal_DQ[448]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[448]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[448]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[0] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[448]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[448]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[0] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[0] ),
        .O(\cal_DQ[448]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair903" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[449]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[449]_i_2_n_0 ),
        .O(\cal_DQ[449]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[449]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[449]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[1] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[449]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[449]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[1] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[1] ),
        .O(\cal_DQ[449]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1053" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[44]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[492]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[44]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair904" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[450]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[450]_i_2_n_0 ),
        .O(\cal_DQ[450]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[450]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[450]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[2] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[450]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[450]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[2] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[2] ),
        .O(\cal_DQ[450]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair904" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[451]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[451]_i_2_n_0 ),
        .O(\cal_DQ[451]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[451]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[451]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[3] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[451]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[451]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[3] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[3] ),
        .O(\cal_DQ[451]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair905" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[452]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[452]_i_2_n_0 ),
        .O(\cal_DQ[452]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[452]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[452]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[4] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[452]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[452]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[4] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[4] ),
        .O(\cal_DQ[452]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair905" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[453]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[453]_i_2_n_0 ),
        .O(\cal_DQ[453]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[453]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[453]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[5] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[453]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[453]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[5] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[5] ),
        .O(\cal_DQ[453]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair906" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[454]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[454]_i_2_n_0 ),
        .O(\cal_DQ[454]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[454]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[454]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[6] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[454]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[454]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[6] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[6] ),
        .O(\cal_DQ[454]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair906" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[455]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[455]_i_2_n_0 ),
        .O(\cal_DQ[455]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[455]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[455]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[7] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[455]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[455]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[7] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[7] ),
        .O(\cal_DQ[455]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair907" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[456]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[456]_i_2_n_0 ),
        .O(\cal_DQ[456]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[456]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[456]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[8] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[456]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[456]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[8] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[8] ),
        .O(\cal_DQ[456]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair907" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[457]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[457]_i_2_n_0 ),
        .O(\cal_DQ[457]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[457]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[457]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[9] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[457]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[457]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[9] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[9] ),
        .O(\cal_DQ[457]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair908" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[458]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[458]_i_2_n_0 ),
        .O(\cal_DQ[458]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[458]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[458]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[10] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[458]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[458]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[10] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[10] ),
        .O(\cal_DQ[458]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair908" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[459]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[459]_i_2_n_0 ),
        .O(\cal_DQ[459]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[459]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[459]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[11] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[459]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[459]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[11] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[11] ),
        .O(\cal_DQ[459]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1053" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[45]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[493]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[45]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair909" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[460]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[460]_i_2_n_0 ),
        .O(\cal_DQ[460]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[460]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[460]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[12] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[460]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[460]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[12] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[12] ),
        .O(\cal_DQ[460]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair909" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[461]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[461]_i_2_n_0 ),
        .O(\cal_DQ[461]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[461]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[461]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[13] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[461]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[461]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[13] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[13] ),
        .O(\cal_DQ[461]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair910" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[462]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[462]_i_2_n_0 ),
        .O(\cal_DQ[462]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[462]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[462]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[14] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[462]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[462]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[14] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[14] ),
        .O(\cal_DQ[462]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair910" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[463]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[463]_i_2_n_0 ),
        .O(\cal_DQ[463]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[463]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[463]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[15] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[463]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[463]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[15] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[15] ),
        .O(\cal_DQ[463]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair911" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[464]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[464]_i_2_n_0 ),
        .O(\cal_DQ[464]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[464]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[464]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[16] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[464]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[464]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[16] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[16] ),
        .O(\cal_DQ[464]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair911" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[465]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[465]_i_2_n_0 ),
        .O(\cal_DQ[465]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[465]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[465]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[17] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[465]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[465]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[17] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[17] ),
        .O(\cal_DQ[465]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair912" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[466]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[466]_i_2_n_0 ),
        .O(\cal_DQ[466]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[466]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[466]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[18] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[466]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[466]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[18] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[18] ),
        .O(\cal_DQ[466]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair912" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[467]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[467]_i_2_n_0 ),
        .O(\cal_DQ[467]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[467]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[467]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[19] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[467]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[467]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[19] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[19] ),
        .O(\cal_DQ[467]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair913" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[468]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[468]_i_2_n_0 ),
        .O(\cal_DQ[468]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[468]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[468]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[20] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[468]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[468]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[20] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[20] ),
        .O(\cal_DQ[468]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair913" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[469]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[469]_i_2_n_0 ),
        .O(\cal_DQ[469]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[469]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[469]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[21] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[469]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[469]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[21] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[21] ),
        .O(\cal_DQ[469]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1054" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[46]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[494]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[46]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair914" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[470]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[470]_i_2_n_0 ),
        .O(\cal_DQ[470]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[470]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[470]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[22] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[470]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[470]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[22] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[22] ),
        .O(\cal_DQ[470]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair914" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[471]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[471]_i_2_n_0 ),
        .O(\cal_DQ[471]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[471]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[471]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[23] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[471]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[471]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[23] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[23] ),
        .O(\cal_DQ[471]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair915" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[472]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[472]_i_2_n_0 ),
        .O(\cal_DQ[472]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[472]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[472]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[24] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[472]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[472]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[24] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[24] ),
        .O(\cal_DQ[472]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair915" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[473]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[473]_i_2_n_0 ),
        .O(\cal_DQ[473]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[473]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[473]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[25] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[473]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[473]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[25] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[25] ),
        .O(\cal_DQ[473]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair916" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[474]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[474]_i_2_n_0 ),
        .O(\cal_DQ[474]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[474]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[474]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[26] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[474]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[474]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[26] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[26] ),
        .O(\cal_DQ[474]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair916" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[475]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[475]_i_2_n_0 ),
        .O(\cal_DQ[475]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[475]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[475]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[27] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[475]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[475]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[27] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[27] ),
        .O(\cal_DQ[475]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair917" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[476]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[476]_i_2_n_0 ),
        .O(\cal_DQ[476]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[476]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[476]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[28] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[476]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[476]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[28] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[28] ),
        .O(\cal_DQ[476]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair917" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[477]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[477]_i_2_n_0 ),
        .O(\cal_DQ[477]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[477]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[477]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[29] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[477]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[477]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[29] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[29] ),
        .O(\cal_DQ[477]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair918" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[478]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[478]_i_2_n_0 ),
        .O(\cal_DQ[478]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[478]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[478]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[30] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[478]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[478]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[30] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[30] ),
        .O(\cal_DQ[478]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair918" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[479]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[479]_i_2_n_0 ),
        .O(\cal_DQ[479]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[479]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[479]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[31] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[479]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[479]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[31] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[31] ),
        .O(\cal_DQ[479]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1054" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[47]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[495]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair919" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[480]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[480]_i_2_n_0 ),
        .O(\cal_DQ[480]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[480]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[480]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[32] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[480]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[480]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[32] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[32] ),
        .O(\cal_DQ[480]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair919" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[481]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[481]_i_2_n_0 ),
        .O(\cal_DQ[481]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[481]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[481]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[33] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[481]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[481]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[33] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[33] ),
        .O(\cal_DQ[481]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair920" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[482]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[482]_i_2_n_0 ),
        .O(\cal_DQ[482]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[482]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[482]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[34] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[482]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[482]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[34] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[34] ),
        .O(\cal_DQ[482]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair920" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[483]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[483]_i_2_n_0 ),
        .O(\cal_DQ[483]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[483]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[483]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[35] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[483]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[483]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[35] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[35] ),
        .O(\cal_DQ[483]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair921" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[484]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[484]_i_2_n_0 ),
        .O(\cal_DQ[484]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[484]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[484]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[36] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[484]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[484]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[36] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[36] ),
        .O(\cal_DQ[484]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair921" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[485]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[485]_i_2_n_0 ),
        .O(\cal_DQ[485]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[485]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[485]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[37] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[485]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[485]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[37] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[37] ),
        .O(\cal_DQ[485]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair922" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[486]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[486]_i_2_n_0 ),
        .O(\cal_DQ[486]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[486]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[486]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[38] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[486]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[486]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[38] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[38] ),
        .O(\cal_DQ[486]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair922" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[487]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[487]_i_2_n_0 ),
        .O(\cal_DQ[487]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[487]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[487]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[39] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[487]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[487]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[39] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[39] ),
        .O(\cal_DQ[487]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair923" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[488]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[488]_i_2_n_0 ),
        .O(\cal_DQ[488]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[488]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[488]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[40] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[488]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[488]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[40] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[40] ),
        .O(\cal_DQ[488]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair923" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[489]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[489]_i_2_n_0 ),
        .O(\cal_DQ[489]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[489]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[489]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[41] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[489]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[489]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[41] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[41] ),
        .O(\cal_DQ[489]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1055" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[48]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[496]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[48]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair924" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[490]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[490]_i_2_n_0 ),
        .O(\cal_DQ[490]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[490]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[490]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[42] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[490]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[490]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[42] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[42] ),
        .O(\cal_DQ[490]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair924" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[491]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[491]_i_2_n_0 ),
        .O(\cal_DQ[491]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[491]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[491]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[43] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[491]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[491]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[43] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[43] ),
        .O(\cal_DQ[491]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair925" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[492]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[492]_i_2_n_0 ),
        .O(\cal_DQ[492]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[492]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[492]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[44] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[492]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[492]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[44] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[44] ),
        .O(\cal_DQ[492]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair925" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[493]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[493]_i_2_n_0 ),
        .O(\cal_DQ[493]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[493]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[493]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[45] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[493]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[493]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[45] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[45] ),
        .O(\cal_DQ[493]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair926" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[494]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[494]_i_2_n_0 ),
        .O(\cal_DQ[494]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[494]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[494]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[46] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[494]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[494]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[46] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[46] ),
        .O(\cal_DQ[494]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair926" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[495]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[495]_i_2_n_0 ),
        .O(\cal_DQ[495]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[495]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[495]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[47] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[495]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[495]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[47] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[47] ),
        .O(\cal_DQ[495]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair927" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[496]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[496]_i_2_n_0 ),
        .O(\cal_DQ[496]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[496]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[496]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[48] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[496]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[496]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[48] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[48] ),
        .O(\cal_DQ[496]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair927" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[497]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[497]_i_2_n_0 ),
        .O(\cal_DQ[497]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[497]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[497]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[49] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[497]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[497]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[49] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[49] ),
        .O(\cal_DQ[497]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair928" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[498]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[498]_i_2_n_0 ),
        .O(\cal_DQ[498]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[498]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[498]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[50] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[498]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[498]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[50] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[50] ),
        .O(\cal_DQ[498]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair928" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[499]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[499]_i_2_n_0 ),
        .O(\cal_DQ[499]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[499]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[499]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[51] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[499]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[499]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[51] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[51] ),
        .O(\cal_DQ[499]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1055" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[49]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[497]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[49]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1033" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[4]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[452]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair929" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[500]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[500]_i_2_n_0 ),
        .O(\cal_DQ[500]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[500]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[500]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[52] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[500]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[500]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[52] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[52] ),
        .O(\cal_DQ[500]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair929" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[501]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[501]_i_2_n_0 ),
        .O(\cal_DQ[501]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[501]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[501]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[53] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[501]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[501]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[53] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[53] ),
        .O(\cal_DQ[501]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair930" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[502]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[502]_i_2_n_0 ),
        .O(\cal_DQ[502]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[502]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[502]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[54] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[502]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[502]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[54] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[54] ),
        .O(\cal_DQ[502]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair930" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[503]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[503]_i_2_n_0 ),
        .O(\cal_DQ[503]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[503]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[503]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[55] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[503]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[503]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[55] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[55] ),
        .O(\cal_DQ[503]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair931" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[504]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[504]_i_2_n_0 ),
        .O(\cal_DQ[504]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[504]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[504]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[56] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[504]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[504]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[56] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[56] ),
        .O(\cal_DQ[504]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair931" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[505]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[505]_i_2_n_0 ),
        .O(\cal_DQ[505]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[505]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[505]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[57] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[505]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[505]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[57] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[57] ),
        .O(\cal_DQ[505]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair932" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[506]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[506]_i_2_n_0 ),
        .O(\cal_DQ[506]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[506]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[506]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[58] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[506]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[506]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[58] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[58] ),
        .O(\cal_DQ[506]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair932" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[507]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[507]_i_2_n_0 ),
        .O(\cal_DQ[507]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[507]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[507]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[59] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[507]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[507]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[59] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[59] ),
        .O(\cal_DQ[507]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair933" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[508]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[508]_i_2_n_0 ),
        .O(\cal_DQ[508]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[508]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[508]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[60] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[508]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[508]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[60] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[60] ),
        .O(\cal_DQ[508]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair933" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[509]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[509]_i_2_n_0 ),
        .O(\cal_DQ[509]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[509]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[509]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[61] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[509]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[509]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[61] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[61] ),
        .O(\cal_DQ[509]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1056" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[50]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[498]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[50]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair934" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[510]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_3_n_0 ),
        .I3(\cal_DQ[510]_i_2_n_0 ),
        .O(\cal_DQ[510]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[510]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[510]_i_3_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[62] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[510]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[510]_i_3 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[62] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[62] ),
        .O(\cal_DQ[510]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair934" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[511]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[7] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_2_n_0 ),
        .I3(\cal_DQ[511]_i_3_n_0 ),
        .O(\cal_DQ[511]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF758A00)) 
    \cal_DQ[511]_i_2 
       (.I0(extended_write_mode),
        .I1(wren),
        .I2(wren_reg_0),
        .I3(\cal_DQ[511]_i_4_n_0 ),
        .I4(\cal_DQOut_A_reg_n_0_[63] ),
        .I5(write_vref_mode_reg_n_0),
        .O(\cal_DQ[511]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAA2AAAAAAAA)) 
    \cal_DQ[511]_i_3 
       (.I0(\cal_DQ[511]_i_5_n_0 ),
        .I1(\dram_device_sel_reg_n_0_[1] ),
        .I2(\dram_device_sel_reg_n_0_[5] ),
        .I3(\dram_device_sel_reg_n_0_[3] ),
        .I4(\dram_device_sel_reg_n_0_[7] ),
        .I5(\cal_DQ[511]_i_6_n_0 ),
        .O(\cal_DQ[511]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h8F80)) 
    \cal_DQ[511]_i_4 
       (.I0(wren),
        .I1(\cal_DQOut_post_reg_n_0_[63] ),
        .I2(wren_reg_0),
        .I3(\cal_DQOut_pre_reg_n_0_[63] ),
        .O(\cal_DQ[511]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cal_DQ[511]_i_5 
       (.I0(write_vref_mode_reg_n_0),
        .I1(devices_dsel),
        .O(\cal_DQ[511]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1160" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \cal_DQ[511]_i_6 
       (.I0(\dram_device_sel_reg_n_0_[4] ),
        .I1(\dram_device_sel_reg_n_0_[6] ),
        .I2(\dram_device_sel_reg_n_0_[2] ),
        .I3(\dram_device_sel_reg_n_0_[0] ),
        .O(\cal_DQ[511]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1056" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[51]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[499]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[51]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1057" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[52]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[500]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[52]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1057" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[53]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[501]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[53]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1058" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[54]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[502]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[54]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1058" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[55]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[503]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[55]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1059" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[56]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[504]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[56]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1059" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[57]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[505]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[57]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1060" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[58]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[506]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[58]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1060" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[59]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[507]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[59]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1033" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[5]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[453]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1061" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[60]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[508]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[60]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1061" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[61]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[509]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[61]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1062" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[62]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[510]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[62]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1062" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[63]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[511]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[63]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAA8AAAAAAAA)) 
    \cal_DQ[63]_i_2 
       (.I0(\cal_DQ[511]_i_5_n_0 ),
        .I1(\dram_device_sel_reg_n_0_[5] ),
        .I2(\dram_device_sel_reg_n_0_[7] ),
        .I3(\dram_device_sel_reg_n_0_[0] ),
        .I4(\dram_device_sel_reg_n_0_[1] ),
        .I5(\cal_DQ[191]_i_3_n_0 ),
        .O(\cal_DQ[63]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1063" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[64]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[448]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[64]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1063" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[65]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[449]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[65]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1064" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[66]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[450]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[66]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1064" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[67]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[451]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[67]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1065" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[68]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[452]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[68]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1065" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[69]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[453]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[69]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1034" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[6]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[454]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1066" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[70]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[454]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[70]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1066" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[71]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[455]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[71]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1067" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[72]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[456]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[72]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1067" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[73]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[457]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[73]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1068" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[74]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[458]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[74]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1068" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[75]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[459]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[75]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1069" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[76]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[460]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[76]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1069" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[77]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[461]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[77]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1070" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[78]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[462]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[78]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1070" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[79]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[463]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[79]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1034" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[7]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[455]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1071" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[80]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[464]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[80]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1071" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[81]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[465]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[81]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1072" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[82]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[466]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[82]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1072" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[83]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[467]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[83]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1073" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[84]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[468]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[84]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1073" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[85]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[469]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[85]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1074" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[86]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[470]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[86]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1074" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[87]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[471]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[87]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1075" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[88]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[472]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[88]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1075" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[89]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[473]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[89]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1035" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[8]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[456]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1076" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[90]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[474]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[90]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1076" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[91]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[475]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[91]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1077" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[92]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[476]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[92]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1077" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[93]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[477]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[93]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1078" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[94]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[478]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[94]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1078" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[95]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[479]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[95]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1079" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[96]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[480]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[96]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1079" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[97]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[481]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[97]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1080" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[98]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[482]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[98]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1080" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[99]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[1] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[483]_i_2_n_0 ),
        .I3(\cal_DQ[127]_i_2_n_0 ),
        .O(\cal_DQ[99]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1035" *) 
  LUT4 #(
    .INIT(16'h7774)) 
    \cal_DQ[9]_i_1 
       (.I0(\cal_DQOut_A_reg_n_0_[0] ),
        .I1(lrdimm_drive_dq_reg_n_0),
        .I2(\cal_DQ[457]_i_2_n_0 ),
        .I3(\cal_DQ[63]_i_2_n_0 ),
        .O(\cal_DQ[9]_i_1_n_0 ));
  FDRE \cal_DQ_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[0]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[100] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[100]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[100] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[101] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[101]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[101] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[102] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[102]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[102] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[103] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[103]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[103] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[104] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[104]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[104] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[105] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[105]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[105] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[106] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[106]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[106] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[107] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[107]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[107] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[108] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[108]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[108] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[109] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[109]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[109] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[10]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[110] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[110]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[110] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[111] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[111]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[111] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[112] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[112]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[112] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[113] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[113]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[113] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[114] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[114]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[114] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[115] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[115]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[115] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[116] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[116]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[116] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[117] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[117]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[117] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[118] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[118]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[118] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[119] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[119]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[119] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[11]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[120] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[120]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[120] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[121] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[121]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[121] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[122] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[122]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[122] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[123] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[123]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[123] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[124] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[124]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[124] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[125] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[125]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[125] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[126] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[126]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[126] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[127] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[127]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[127] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[128] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[128]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[128] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[129] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[129]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[129] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[12]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[130] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[130]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[130] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[131] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[131]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[131] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[132] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[132]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[132] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[133] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[133]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[133] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[134] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[134]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[134] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[135] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[135]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[135] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[136] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[136]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[136] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[137] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[137]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[137] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[138] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[138]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[138] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[139] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[139]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[139] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[13]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[140] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[140]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[140] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[141] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[141]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[141] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[142] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[142]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[142] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[143] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[143]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[143] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[144] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[144]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[144] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[145] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[145]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[145] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[146] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[146]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[146] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[147] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[147]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[147] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[148] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[148]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[148] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[149] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[149]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[149] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[14]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[150] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[150]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[150] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[151] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[151]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[151] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[152] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[152]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[152] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[153] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[153]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[153] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[154] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[154]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[154] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[155] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[155]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[155] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[156] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[156]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[156] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[157] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[157]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[157] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[158] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[158]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[158] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[159] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[159]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[159] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[15]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[160] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[160]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[160] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[161] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[161]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[161] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[162] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[162]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[162] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[163] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[163]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[163] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[164] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[164]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[164] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[165] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[165]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[165] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[166] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[166]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[166] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[167] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[167]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[167] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[168] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[168]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[168] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[169] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[169]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[169] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[16]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[170] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[170]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[170] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[171] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[171]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[171] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[172] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[172]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[172] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[173] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[173]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[173] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[174] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[174]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[174] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[175] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[175]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[175] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[176] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[176]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[176] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[177] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[177]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[177] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[178] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[178]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[178] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[179] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[179]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[179] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[17]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[180] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[180]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[180] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[181] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[181]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[181] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[182] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[182]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[182] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[183] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[183]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[183] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[184] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[184]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[184] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[185] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[185]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[185] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[186] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[186]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[186] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[187] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[187]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[187] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[188] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[188]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[188] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[189] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[189]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[189] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[18]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[190] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[190]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[190] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[191] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[191]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[191] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[192] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[192]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[192] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[193] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[193]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[193] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[194] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[194]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[194] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[195] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[195]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[195] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[196] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[196]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[196] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[197] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[197]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[197] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[198] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[198]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[198] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[199] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[199]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[199] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[19]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[1]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[200] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[200]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[200] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[201] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[201]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[201] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[202] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[202]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[202] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[203] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[203]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[203] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[204] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[204]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[204] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[205] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[205]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[205] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[206] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[206]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[206] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[207] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[207]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[207] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[208] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[208]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[208] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[209] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[209]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[209] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[20]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[20] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[210] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[210]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[210] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[211] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[211]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[211] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[212] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[212]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[212] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[213] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[213]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[213] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[214] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[214]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[214] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[215] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[215]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[215] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[216] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[216]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[216] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[217] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[217]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[217] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[218] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[218]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[218] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[219] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[219]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[219] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[21]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[21] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[220] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[220]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[220] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[221] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[221]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[221] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[222] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[222]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[222] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[223] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[223]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[223] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[224] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[224]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[224] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[225] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[225]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[225] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[226] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[226]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[226] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[227] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[227]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[227] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[228] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[228]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[228] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[229] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[229]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[229] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[22]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[22] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[230] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[230]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[230] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[231] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[231]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[231] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[232] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[232]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[232] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[233] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[233]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[233] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[234] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[234]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[234] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[235] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[235]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[235] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[236] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[236]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[236] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[237] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[237]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[237] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[238] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[238]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[238] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[239] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[239]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[239] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[23]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[23] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[240] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[240]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[240] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[241] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[241]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[241] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[242] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[242]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[242] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[243] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[243]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[243] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[244] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[244]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[244] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[245] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[245]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[245] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[246] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[246]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[246] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[247] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[247]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[247] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[248] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[248]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[248] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[249] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[249]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[249] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[24]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[250] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[250]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[250] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[251] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[251]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[251] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[252] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[252]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[252] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[253] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[253]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[253] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[254] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[254]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[254] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[255] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[255]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[255] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[256] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[256]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[256] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[257] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[257]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[257] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[258] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[258]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[258] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[259] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[259]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[259] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[25]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[260] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[260]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[260] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[261] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[261]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[261] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[262] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[262]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[262] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[263] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[263]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[263] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[264] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[264]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[264] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[265] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[265]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[265] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[266] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[266]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[266] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[267] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[267]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[267] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[268] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[268]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[268] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[269] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[269]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[269] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[26]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[270] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[270]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[270] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[271] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[271]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[271] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[272] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[272]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[272] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[273] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[273]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[273] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[274] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[274]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[274] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[275] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[275]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[275] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[276] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[276]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[276] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[277] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[277]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[277] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[278] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[278]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[278] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[279] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[279]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[279] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[27]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[27] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[280] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[280]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[280] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[281] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[281]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[281] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[282] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[282]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[282] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[283] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[283]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[283] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[284] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[284]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[284] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[285] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[285]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[285] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[286] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[286]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[286] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[287] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[287]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[287] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[288] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[288]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[288] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[289] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[289]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[289] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[28]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[28] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[290] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[290]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[290] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[291] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[291]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[291] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[292] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[292]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[292] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[293] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[293]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[293] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[294] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[294]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[294] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[295] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[295]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[295] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[296] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[296]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[296] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[297] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[297]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[297] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[298] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[298]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[298] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[299] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[299]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[299] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[29]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[29] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[2]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[300] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[300]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[300] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[301] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[301]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[301] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[302] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[302]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[302] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[303] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[303]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[303] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[304] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[304]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[304] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[305] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[305]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[305] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[306] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[306]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[306] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[307] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[307]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[307] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[308] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[308]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[308] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[309] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[309]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[309] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[30]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[30] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[310] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[310]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[310] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[311] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[311]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[311] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[312] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[312]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[312] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[313] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[313]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[313] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[314] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[314]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[314] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[315] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[315]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[315] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[316] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[316]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[316] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[317] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[317]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[317] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[318] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[318]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[318] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[319] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[319]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[319] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[31]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[320] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[320]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[320] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[321] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[321]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[321] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[322] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[322]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[322] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[323] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[323]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[323] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[324] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[324]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[324] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[325] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[325]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[325] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[326] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[326]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[326] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[327] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[327]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[327] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[328] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[328]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[328] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[329] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[329]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[329] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[32]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[32] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[330] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[330]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[330] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[331] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[331]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[331] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[332] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[332]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[332] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[333] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[333]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[333] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[334] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[334]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[334] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[335] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[335]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[335] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[336] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[336]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[336] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[337] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[337]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[337] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[338] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[338]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[338] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[339] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[339]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[339] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[33]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[33] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[340] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[340]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[340] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[341] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[341]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[341] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[342] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[342]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[342] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[343] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[343]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[343] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[344] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[344]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[344] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[345] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[345]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[345] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[346] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[346]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[346] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[347] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[347]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[347] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[348] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[348]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[348] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[349] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[349]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[349] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[34]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[34] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[350] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[350]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[350] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[351] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[351]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[351] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[352] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[352]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[352] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[353] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[353]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[353] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[354] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[354]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[354] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[355] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[355]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[355] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[356] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[356]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[356] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[357] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[357]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[357] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[358] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[358]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[358] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[359] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[359]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[359] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[35]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[35] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[360] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[360]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[360] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[361] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[361]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[361] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[362] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[362]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[362] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[363] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[363]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[363] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[364] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[364]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[364] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[365] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[365]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[365] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[366] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[366]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[366] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[367] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[367]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[367] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[368] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[368]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[368] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[369] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[369]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[369] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[36]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[36] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[370] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[370]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[370] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[371] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[371]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[371] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[372] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[372]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[372] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[373] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[373]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[373] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[374] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[374]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[374] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[375] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[375]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[375] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[376] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[376]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[376] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[377] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[377]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[377] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[378] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[378]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[378] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[379] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[379]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[379] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[37]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[37] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[380] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[380]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[380] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[381] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[381]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[381] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[382] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[382]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[382] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[383] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[383]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[383] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[384] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[384]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[384] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[385] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[385]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[385] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[386] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[386]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[386] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[387] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[387]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[387] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[388] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[388]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[388] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[389] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[389]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[389] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[38]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[38] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[390] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[390]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[390] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[391] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[391]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[391] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[392] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[392]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[392] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[393] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[393]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[393] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[394] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[394]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[394] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[395] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[395]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[395] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[396] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[396]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[396] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[397] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[397]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[397] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[398] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[398]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[398] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[399] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[399]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[399] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[39]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[39] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[3]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[400] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[400]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[400] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[401] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[401]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[401] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[402] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[402]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[402] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[403] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[403]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[403] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[404] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[404]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[404] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[405] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[405]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[405] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[406] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[406]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[406] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[407] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[407]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[407] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[408] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[408]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[408] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[409] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[409]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[409] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[40]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[40] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[410] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[410]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[410] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[411] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[411]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[411] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[412] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[412]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[412] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[413] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[413]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[413] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[414] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[414]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[414] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[415] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[415]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[415] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[416] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[416]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[416] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[417] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[417]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[417] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[418] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[418]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[418] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[419] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[419]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[419] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[41]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[41] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[420] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[420]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[420] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[421] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[421]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[421] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[422] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[422]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[422] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[423] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[423]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[423] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[424] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[424]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[424] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[425] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[425]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[425] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[426] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[426]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[426] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[427] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[427]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[427] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[428] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[428]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[428] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[429] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[429]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[429] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[42]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[42] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[430] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[430]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[430] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[431] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[431]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[431] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[432] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[432]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[432] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[433] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[433]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[433] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[434] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[434]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[434] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[435] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[435]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[435] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[436] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[436]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[436] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[437] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[437]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[437] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[438] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[438]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[438] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[439] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[439]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[439] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[43]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[43] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[440] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[440]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[440] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[441] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[441]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[441] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[442] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[442]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[442] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[443] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[443]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[443] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[444] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[444]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[444] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[445] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[445]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[445] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[446] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[446]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[446] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[447] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[447]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[447] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[448] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[448]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[448] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[449] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[449]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[449] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[44]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[44] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[450] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[450]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[450] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[451] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[451]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[451] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[452] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[452]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[452] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[453] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[453]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[453] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[454] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[454]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[454] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[455] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[455]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[455] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[456] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[456]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[456] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[457] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[457]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[457] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[458] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[458]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[458] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[459] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[459]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[459] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[45]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[45] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[460] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[460]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[460] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[461] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[461]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[461] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[462] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[462]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[462] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[463] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[463]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[463] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[464] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[464]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[464] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[465] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[465]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[465] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[466] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[466]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[466] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[467] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[467]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[467] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[468] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[468]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[468] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[469] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[469]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[469] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[46]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[46] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[470] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[470]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[470] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[471] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[471]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[471] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[472] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[472]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[472] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[473] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[473]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[473] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[474] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[474]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[474] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[475] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[475]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[475] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[476] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[476]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[476] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[477] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[477]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[477] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[478] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[478]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[478] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[479] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[479]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[479] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[47]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[47] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[480] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[480]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[480] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[481] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[481]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[481] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[482] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[482]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[482] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[483] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[483]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[483] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[484] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[484]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[484] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[485] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[485]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[485] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[486] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[486]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[486] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[487] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[487]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[487] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[488] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[488]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[488] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[489] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[489]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[489] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[48]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[48] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[490] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[490]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[490] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[491] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[491]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[491] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[492] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[492]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[492] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[493] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[493]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[493] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[494] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[494]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[494] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[495] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[495]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[495] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[496] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[496]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[496] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[497] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[497]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[497] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[498] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[498]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[498] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[499] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[499]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[499] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[49]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[49] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[4]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[500] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[500]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[500] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[501] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[501]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[501] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[502] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[502]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[502] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[503] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[503]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[503] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[504] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[504]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[504] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[505] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[505]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[505] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[506] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[506]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[506] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[507] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[507]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[507] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[508] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[508]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[508] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[509] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[509]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[509] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[50]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[50] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[510] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[510]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[510] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[511] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[511]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[511] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[51]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[51] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[52]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[52] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[53]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[53] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[54]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[54] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[55]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[55] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[56]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[56] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[57]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[57] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[58]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[58] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[59]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[59] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[5]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[60]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[60] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[61]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[61] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[62]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[62] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[63]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[63] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[64] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[64]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[64] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[65] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[65]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[65] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[66] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[66]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[66] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[67] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[67]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[67] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[68] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[68]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[68] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[69] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[69]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[69] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[6]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[70] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[70]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[70] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[71] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[71]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[71] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[72] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[72]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[72] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[73] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[73]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[73] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[74] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[74]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[74] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[75] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[75]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[75] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[76] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[76]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[76] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[77] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[77]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[77] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[78] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[78]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[78] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[79] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[79]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[79] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[7]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[80] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[80]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[80] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[81] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[81]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[81] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[82] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[82]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[82] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[83] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[83]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[83] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[84] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[84]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[84] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[85] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[85]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[85] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[86] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[86]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[86] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[87] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[87]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[87] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[88] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[88]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[88] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[89] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[89]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[89] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[8]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[90] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[90]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[90] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[91] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[91]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[91] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[92] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[92]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[92] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[93] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[93]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[93] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[94] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[94]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[94] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[95] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[95]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[95] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[96] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[96]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[96] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[97] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[97]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[97] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[98] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[98]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[98] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[99] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[99]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[99] ),
        .R(1'b0));
  FDRE \cal_DQ_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_DQ[9]_i_1_n_0 ),
        .Q(\cal_DQ_reg_n_0_[9] ),
        .R(1'b0));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_A_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[16]),
        .Q(\cal_RAS_A_reg_n_0_[0] ),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_A_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_RAS_A_reg_n_0_[1] ),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_A_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_RAS_A_reg_n_0_[2] ),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_A_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_RAS_A_reg_n_0_[3] ),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_A_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_RAS_A_reg_n_0_[4] ),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_A_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_RAS_A_reg_n_0_[5] ),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_A_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_RAS_A_reg_n_0_[6] ),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_A_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_RAS_A_reg_n_0_[7] ),
        .S(rst_r1));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RAS_B_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[16]),
        .Q(cal_RAS_B[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RAS_B_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[17]),
        .Q(cal_RAS_B[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RAS_B_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[18]),
        .Q(cal_RAS_B[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RAS_B_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[19]),
        .Q(cal_RAS_B[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RAS_B_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[20]),
        .Q(cal_RAS_B[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RAS_B_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[21]),
        .Q(cal_RAS_B[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RAS_B_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[22]),
        .Q(cal_RAS_B[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RAS_B_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[23]),
        .Q(cal_RAS_B[7]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1551" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_RAS_pre[0]_i_1 
       (.I0(cal_RAS_B[0]),
        .I1(a_b_cmd_sel),
        .I2(\cal_RAS_A_reg_n_0_[0] ),
        .O(cal_RAS_pre_nxt[0]));
  (* SOFT_HLUTNM = "soft_lutpair1551" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_RAS_pre[1]_i_1 
       (.I0(cal_RAS_B[1]),
        .I1(a_b_cmd_sel),
        .I2(\cal_RAS_A_reg_n_0_[1] ),
        .O(cal_RAS_pre_nxt[1]));
  (* SOFT_HLUTNM = "soft_lutpair1550" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_RAS_pre[2]_i_1 
       (.I0(cal_RAS_B[2]),
        .I1(a_b_cmd_sel),
        .I2(\cal_RAS_A_reg_n_0_[2] ),
        .O(cal_RAS_pre_nxt[2]));
  (* SOFT_HLUTNM = "soft_lutpair1550" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_RAS_pre[3]_i_1 
       (.I0(cal_RAS_B[3]),
        .I1(a_b_cmd_sel),
        .I2(\cal_RAS_A_reg_n_0_[3] ),
        .O(cal_RAS_pre_nxt[3]));
  (* SOFT_HLUTNM = "soft_lutpair1549" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_RAS_pre[4]_i_1 
       (.I0(cal_RAS_B[4]),
        .I1(a_b_cmd_sel),
        .I2(\cal_RAS_A_reg_n_0_[4] ),
        .O(cal_RAS_pre_nxt[4]));
  (* SOFT_HLUTNM = "soft_lutpair1549" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_RAS_pre[5]_i_1 
       (.I0(cal_RAS_B[5]),
        .I1(a_b_cmd_sel),
        .I2(\cal_RAS_A_reg_n_0_[5] ),
        .O(cal_RAS_pre_nxt[5]));
  (* SOFT_HLUTNM = "soft_lutpair1548" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_RAS_pre[6]_i_1 
       (.I0(cal_RAS_B[6]),
        .I1(a_b_cmd_sel),
        .I2(\cal_RAS_A_reg_n_0_[6] ),
        .O(cal_RAS_pre_nxt[6]));
  (* SOFT_HLUTNM = "soft_lutpair1548" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_RAS_pre[7]_i_1 
       (.I0(cal_RAS_B[7]),
        .I1(a_b_cmd_sel),
        .I2(\cal_RAS_A_reg_n_0_[7] ),
        .O(cal_RAS_pre_nxt[7]));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_pre_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_RAS_pre_nxt[0]),
        .Q(cal_RAS_pre[0]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_pre_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_RAS_pre_nxt[1]),
        .Q(cal_RAS_pre[1]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_pre_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_RAS_pre_nxt[2]),
        .Q(cal_RAS_pre[2]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_pre_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_RAS_pre_nxt[3]),
        .Q(cal_RAS_pre[3]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_pre_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_RAS_pre_nxt[4]),
        .Q(cal_RAS_pre[4]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_pre_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_RAS_pre_nxt[5]),
        .Q(cal_RAS_pre[5]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_pre_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_RAS_pre_nxt[6]),
        .Q(cal_RAS_pre[6]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_RAS_pre_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_RAS_pre_nxt[7]),
        .Q(cal_RAS_pre[7]),
        .S(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair1558" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \cal_RESET_n[0]_i_1 
       (.I0(ub_cal_RESET_n[0]),
        .I1(init_cal_RESET_n),
        .I2(ub_ready),
        .O(\cal_RST_CKE_ODT_PAR_reg[7]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1556" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \cal_RESET_n[1]_i_1 
       (.I0(\cal_RST_CKE_ODT_PAR_reg[30]_0 [0]),
        .I1(init_cal_RESET_n),
        .I2(ub_ready),
        .O(\cal_RST_CKE_ODT_PAR_reg[7]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1556" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \cal_RESET_n[2]_i_1 
       (.I0(\cal_RST_CKE_ODT_PAR_reg[30]_0 [1]),
        .I1(init_cal_RESET_n),
        .I2(ub_ready),
        .O(\cal_RST_CKE_ODT_PAR_reg[7]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1163" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \cal_RESET_n[3]_i_1 
       (.I0(\cal_RST_CKE_ODT_PAR_reg[30]_0 [2]),
        .I1(init_cal_RESET_n),
        .I2(ub_ready),
        .O(\cal_RST_CKE_ODT_PAR_reg[7]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair1557" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \cal_RESET_n[4]_i_1 
       (.I0(ub_cal_RESET_n[4]),
        .I1(init_cal_RESET_n),
        .I2(ub_ready),
        .O(\cal_RST_CKE_ODT_PAR_reg[7]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair1557" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \cal_RESET_n[5]_i_1 
       (.I0(\cal_RST_CKE_ODT_PAR_reg[30]_0 [3]),
        .I1(init_cal_RESET_n),
        .I2(ub_ready),
        .O(\cal_RST_CKE_ODT_PAR_reg[7]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair1558" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \cal_RESET_n[6]_i_1 
       (.I0(\cal_RST_CKE_ODT_PAR_reg[30]_0 [4]),
        .I1(init_cal_RESET_n),
        .I2(ub_ready),
        .O(\cal_RST_CKE_ODT_PAR_reg[7]_0 [6]));
  LUT3 #(
    .INIT(8'hAC)) 
    \cal_RESET_n[7]_i_1 
       (.I0(\cal_RST_CKE_ODT_PAR_reg[30]_0 [5]),
        .I1(init_cal_RESET_n),
        .I2(ub_ready),
        .O(\cal_RST_CKE_ODT_PAR_reg[7]_0 [7]));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[0]),
        .Q(ub_cal_RESET_n[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RST_CKE_ODT_PAR_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[10]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RST_CKE_ODT_PAR_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[11]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RST_CKE_ODT_PAR_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[12]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RST_CKE_ODT_PAR_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[13]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RST_CKE_ODT_PAR_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[14]),
        .Q(\cal_RST_CKE_ODT_PAR_reg[30]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RST_CKE_ODT_PAR_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[15]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[16]),
        .Q(ub_cal_CKE),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[17]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[18]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[18] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[19]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[19] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_RST_CKE_ODT_PAR_reg[30]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[20]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[20] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[21]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[21] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[22]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[22] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[23]),
        .Q(\cal_RST_CKE_ODT_PAR_reg[30]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[24]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[24] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[25]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[25] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[26]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[26] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[27]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[27] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[28]),
        .Q(\cal_RST_CKE_ODT_PAR_reg[30]_0 [9]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[29]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[29] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_RST_CKE_ODT_PAR_reg[30]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[30]),
        .Q(\cal_RST_CKE_ODT_PAR_reg[30]_0 [10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[31]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[31] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_RST_CKE_ODT_PAR_reg[30]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[4]),
        .Q(ub_cal_RESET_n[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_RST_CKE_ODT_PAR_reg[30]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_RST_CKE_ODT_PAR_reg[30]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_RST_CKE_ODT_PAR_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_RST_CKE_ODT_PAR_reg[30]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RST_CKE_ODT_PAR_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[8]),
        .Q(\cal_RST_CKE_ODT_PAR_reg[30]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RST_CKE_ODT_PAR_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RST_CKE_ODT_PAR_reg[31]_0 ),
        .D(io_write_data[9]),
        .Q(\cal_RST_CKE_ODT_PAR_reg_n_0_[9] ),
        .R(1'b0));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_A_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[8]),
        .Q(cal_WE_A[0]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_A_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[9]),
        .Q(cal_WE_A[1]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_A_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[10]),
        .Q(cal_WE_A[2]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_A_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[11]),
        .Q(cal_WE_A[3]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_A_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[12]),
        .Q(cal_WE_A[4]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_A_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[13]),
        .Q(cal_WE_A[5]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_A_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[14]),
        .Q(cal_WE_A[6]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_A_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_CAS_A_reg[0]_0 ),
        .D(io_write_data[15]),
        .Q(cal_WE_A[7]),
        .S(rst_r1));
  FDRE #(
    .INIT(1'b1)) 
    \cal_WE_B_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[8]),
        .Q(cal_WE_B[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_WE_B_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[9]),
        .Q(cal_WE_B[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_WE_B_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[10]),
        .Q(cal_WE_B[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_WE_B_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[11]),
        .Q(cal_WE_B[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_WE_B_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[12]),
        .Q(cal_WE_B[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_WE_B_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[13]),
        .Q(cal_WE_B[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_WE_B_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[14]),
        .Q(cal_WE_B[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_WE_B_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_RAS_B_reg[0]_0 ),
        .D(io_write_data[15]),
        .Q(cal_WE_B[7]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1543" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_WE_pre[0]_i_1 
       (.I0(cal_WE_B[0]),
        .I1(a_b_cmd_sel),
        .I2(cal_WE_A[0]),
        .O(cal_WE_pre_nxt[0]));
  (* SOFT_HLUTNM = "soft_lutpair1543" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_WE_pre[1]_i_1 
       (.I0(cal_WE_B[1]),
        .I1(a_b_cmd_sel),
        .I2(cal_WE_A[1]),
        .O(cal_WE_pre_nxt[1]));
  (* SOFT_HLUTNM = "soft_lutpair1542" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_WE_pre[2]_i_1 
       (.I0(cal_WE_B[2]),
        .I1(a_b_cmd_sel),
        .I2(cal_WE_A[2]),
        .O(cal_WE_pre_nxt[2]));
  (* SOFT_HLUTNM = "soft_lutpair1542" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_WE_pre[3]_i_1 
       (.I0(cal_WE_B[3]),
        .I1(a_b_cmd_sel),
        .I2(cal_WE_A[3]),
        .O(cal_WE_pre_nxt[3]));
  (* SOFT_HLUTNM = "soft_lutpair1541" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_WE_pre[4]_i_1 
       (.I0(cal_WE_B[4]),
        .I1(a_b_cmd_sel),
        .I2(cal_WE_A[4]),
        .O(cal_WE_pre_nxt[4]));
  (* SOFT_HLUTNM = "soft_lutpair1541" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_WE_pre[5]_i_1 
       (.I0(cal_WE_B[5]),
        .I1(a_b_cmd_sel),
        .I2(cal_WE_A[5]),
        .O(cal_WE_pre_nxt[5]));
  (* SOFT_HLUTNM = "soft_lutpair1540" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_WE_pre[6]_i_1 
       (.I0(cal_WE_B[6]),
        .I1(a_b_cmd_sel),
        .I2(cal_WE_A[6]),
        .O(cal_WE_pre_nxt[6]));
  (* SOFT_HLUTNM = "soft_lutpair1540" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_WE_pre[7]_i_1 
       (.I0(cal_WE_B[7]),
        .I1(a_b_cmd_sel),
        .I2(cal_WE_A[7]),
        .O(cal_WE_pre_nxt[7]));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_pre_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_WE_pre_nxt[0]),
        .Q(cal_WE_pre[0]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_pre_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_WE_pre_nxt[1]),
        .Q(cal_WE_pre[1]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_pre_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_WE_pre_nxt[2]),
        .Q(cal_WE_pre[2]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_pre_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_WE_pre_nxt[3]),
        .Q(cal_WE_pre[3]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_pre_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_WE_pre_nxt[4]),
        .Q(cal_WE_pre[4]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_pre_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_WE_pre_nxt[5]),
        .Q(cal_WE_pre[5]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_pre_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_WE_pre_nxt[6]),
        .Q(cal_WE_pre[6]),
        .S(rst_r1));
  FDSE #(
    .INIT(1'b1)) 
    \cal_WE_pre_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_WE_pre_nxt[7]),
        .Q(cal_WE_pre[7]),
        .S(rst_r1));
  FDSE \cal_cmp_en_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_cmp_en_reg[7]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_cmp_en_reg_n_0_[0] ),
        .S(rst_r1));
  FDSE \cal_cmp_en_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_cmp_en_reg[7]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_cmp_en_reg_n_0_[1] ),
        .S(rst_r1));
  FDSE \cal_cmp_en_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_cmp_en_reg[7]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_cmp_en_reg_n_0_[2] ),
        .S(rst_r1));
  FDSE \cal_cmp_en_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_cmp_en_reg[7]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_cmp_en_reg_n_0_[3] ),
        .S(rst_r1));
  FDSE \cal_cmp_en_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_cmp_en_reg[7]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_cmp_en_reg_n_0_[4] ),
        .S(rst_r1));
  FDSE \cal_cmp_en_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_cmp_en_reg[7]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_cmp_en_reg_n_0_[5] ),
        .S(rst_r1));
  FDSE \cal_cmp_en_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_cmp_en_reg[7]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_cmp_en_reg_n_0_[6] ),
        .S(rst_r1));
  FDSE \cal_cmp_en_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_cmp_en_reg[7]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_cmp_en_reg_n_0_[7] ),
        .S(rst_r1));
  LUT3 #(
    .INIT(8'hBF)) 
    \cal_cs_pos[1]_i_3 
       (.I0(rst_r1),
        .I1(io_addr_strobe_r1_reg_0),
        .I2(\cplx_config_reg[16]_0 ),
        .O(rst_r1_reg_0));
  FDRE \cal_cs_pos_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_cs_pos_reg[1]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_cs_pos_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \cal_cs_pos_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_cs_pos_reg[1]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_cs_pos_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cal_oe_dis_low_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_oe_dis_low_reg[7]_0 ),
        .Q(cal_oe_dis_low),
        .R(rst_r1));
  FDRE \cal_oe_dis_upp_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_oe_dis_upp_reg[7]_0 ),
        .Q(cal_oe_dis_upp),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b1)) 
    \cal_seq_a_a_dly_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_a_dly_reg[7]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_seq_a_a_dly_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_a_dly_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_a_dly_reg[7]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_seq_a_a_dly_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_a_dly_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_a_dly_reg[7]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_seq_a_a_dly_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_a_dly_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_a_dly_reg[7]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_seq_a_a_dly_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_a_dly_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_a_dly_reg[7]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_seq_a_a_dly_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_a_dly_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_a_dly_reg[7]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_seq_a_a_dly_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_a_dly_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_a_dly_reg[7]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_seq_a_a_dly_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_a_dly_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_a_dly_reg[7]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_seq_a_a_dly_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_seq_a_b_dly_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_b_dly_reg[7]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_seq_a_b_dly_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_b_dly_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_b_dly_reg[7]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_seq_a_b_dly_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_b_dly_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_b_dly_reg[7]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_seq_a_b_dly_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_b_dly_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_b_dly_reg[7]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_seq_a_b_dly_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_b_dly_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_b_dly_reg[7]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_seq_a_b_dly_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_b_dly_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_b_dly_reg[7]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_seq_a_b_dly_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_b_dly_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_b_dly_reg[7]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_seq_a_b_dly_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_a_b_dly_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_a_b_dly_reg[7]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_seq_a_b_dly_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    \cal_seq_b_a_dly_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_b_a_dly_reg[7]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_seq_b_a_dly_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_b_a_dly_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_b_a_dly_reg[7]_0 ),
        .D(io_write_data[1]),
        .Q(\cal_seq_b_a_dly_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_b_a_dly_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_b_a_dly_reg[7]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_seq_b_a_dly_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_b_a_dly_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_b_a_dly_reg[7]_0 ),
        .D(io_write_data[3]),
        .Q(\cal_seq_b_a_dly_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_b_a_dly_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_b_a_dly_reg[7]_0 ),
        .D(io_write_data[4]),
        .Q(\cal_seq_b_a_dly_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_b_a_dly_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_b_a_dly_reg[7]_0 ),
        .D(io_write_data[5]),
        .Q(\cal_seq_b_a_dly_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_b_a_dly_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_b_a_dly_reg[7]_0 ),
        .D(io_write_data[6]),
        .Q(\cal_seq_b_a_dly_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_b_a_dly_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_b_a_dly_reg[7]_0 ),
        .D(io_write_data[7]),
        .Q(\cal_seq_b_a_dly_reg_n_0_[7] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair902" *) 
  LUT4 #(
    .INIT(16'h888B)) 
    \cal_seq_cnt[0]_i_1 
       (.I0(io_write_data[0]),
        .I1(a_b_cmd_sel_start0),
        .I2(cnt_clr_reg_0),
        .I3(\cal_seq_cnt_reg[31]_0 [0]),
        .O(\cal_seq_cnt[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[10]_i_1 
       (.I0(io_write_data[10]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[10]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[10]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[11]_i_1 
       (.I0(io_write_data[11]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[11]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[11]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[12]_i_1 
       (.I0(io_write_data[12]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[12]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[12]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[13]_i_1 
       (.I0(io_write_data[13]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[13]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[13]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[14]_i_1 
       (.I0(io_write_data[14]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[14]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[14]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[15]_i_1 
       (.I0(io_write_data[15]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[15]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[15]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[16]_i_1 
       (.I0(io_write_data[16]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[16]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[16]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[16]_i_10 
       (.I0(\cal_seq_cnt_reg[31]_0 [9]),
        .O(\cal_seq_cnt[16]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[16]_i_3 
       (.I0(\cal_seq_cnt_reg[31]_0 [16]),
        .O(\cal_seq_cnt[16]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[16]_i_4 
       (.I0(\cal_seq_cnt_reg[31]_0 [15]),
        .O(\cal_seq_cnt[16]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[16]_i_5 
       (.I0(\cal_seq_cnt_reg[31]_0 [14]),
        .O(\cal_seq_cnt[16]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[16]_i_6 
       (.I0(\cal_seq_cnt_reg[31]_0 [13]),
        .O(\cal_seq_cnt[16]_i_6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[16]_i_7 
       (.I0(\cal_seq_cnt_reg[31]_0 [12]),
        .O(\cal_seq_cnt[16]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[16]_i_8 
       (.I0(\cal_seq_cnt_reg[31]_0 [11]),
        .O(\cal_seq_cnt[16]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[16]_i_9 
       (.I0(\cal_seq_cnt_reg[31]_0 [10]),
        .O(\cal_seq_cnt[16]_i_9_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[17]_i_1 
       (.I0(io_write_data[17]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[17]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[17]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[18]_i_1 
       (.I0(io_write_data[18]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[18]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[18]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[19]_i_1 
       (.I0(io_write_data[19]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[19]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[19]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[1]_i_1 
       (.I0(io_write_data[1]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[1]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[20]_i_1 
       (.I0(io_write_data[20]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[20]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[20]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[21]_i_1 
       (.I0(io_write_data[21]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[21]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[21]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[22]_i_1 
       (.I0(io_write_data[22]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[22]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[22]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[23]_i_1 
       (.I0(io_write_data[23]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[23]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[23]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[24]_i_1 
       (.I0(io_write_data[24]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[24]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[24]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[24]_i_10 
       (.I0(\cal_seq_cnt_reg[31]_0 [17]),
        .O(\cal_seq_cnt[24]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[24]_i_3 
       (.I0(\cal_seq_cnt_reg[31]_0 [24]),
        .O(\cal_seq_cnt[24]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[24]_i_4 
       (.I0(\cal_seq_cnt_reg[31]_0 [23]),
        .O(\cal_seq_cnt[24]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[24]_i_5 
       (.I0(\cal_seq_cnt_reg[31]_0 [22]),
        .O(\cal_seq_cnt[24]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[24]_i_6 
       (.I0(\cal_seq_cnt_reg[31]_0 [21]),
        .O(\cal_seq_cnt[24]_i_6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[24]_i_7 
       (.I0(\cal_seq_cnt_reg[31]_0 [20]),
        .O(\cal_seq_cnt[24]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[24]_i_8 
       (.I0(\cal_seq_cnt_reg[31]_0 [19]),
        .O(\cal_seq_cnt[24]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[24]_i_9 
       (.I0(\cal_seq_cnt_reg[31]_0 [18]),
        .O(\cal_seq_cnt[24]_i_9_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[25]_i_1 
       (.I0(io_write_data[25]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[25]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[25]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[26]_i_1 
       (.I0(io_write_data[26]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[26]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[26]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[27]_i_1 
       (.I0(io_write_data[27]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[27]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[27]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[28]_i_1 
       (.I0(io_write_data[28]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[28]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[28]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[29]_i_1 
       (.I0(io_write_data[29]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[29]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[29]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[2]_i_1 
       (.I0(io_write_data[2]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[2]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[30]_i_1 
       (.I0(io_write_data[30]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[30]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[30]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hBBBABABA)) 
    \cal_seq_cnt[31]_i_1 
       (.I0(a_b_cmd_sel_start0),
        .I1(cnt_clr_access),
        .I2(cnt_clr_reg_0),
        .I3(seq_cnt_dec),
        .I4(cal_seq_cnt_gt_0),
        .O(\cal_seq_cnt[31]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[31]_i_10 
       (.I0(\cal_seq_cnt_reg[31]_0 [25]),
        .O(\cal_seq_cnt[31]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[31]_i_2 
       (.I0(io_write_data[31]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[31]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[31]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[31]_i_4 
       (.I0(\cal_seq_cnt_reg[31]_0 [31]),
        .O(\cal_seq_cnt[31]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[31]_i_5 
       (.I0(\cal_seq_cnt_reg[31]_0 [30]),
        .O(\cal_seq_cnt[31]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[31]_i_6 
       (.I0(\cal_seq_cnt_reg[31]_0 [29]),
        .O(\cal_seq_cnt[31]_i_6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[31]_i_7 
       (.I0(\cal_seq_cnt_reg[31]_0 [28]),
        .O(\cal_seq_cnt[31]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[31]_i_8 
       (.I0(\cal_seq_cnt_reg[31]_0 [27]),
        .O(\cal_seq_cnt[31]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[31]_i_9 
       (.I0(\cal_seq_cnt_reg[31]_0 [26]),
        .O(\cal_seq_cnt[31]_i_9_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[3]_i_1 
       (.I0(io_write_data[3]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[3]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[4]_i_1 
       (.I0(io_write_data[4]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[4]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[5]_i_1 
       (.I0(io_write_data[5]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[5]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hA3A0)) 
    \cal_seq_cnt[6]_i_1 
       (.I0(io_write_data[6]),
        .I1(cnt_clr_reg_0),
        .I2(a_b_cmd_sel_start0),
        .I3(cal_seq_cnt0__0[6]),
        .O(\cal_seq_cnt[6]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hA3A0)) 
    \cal_seq_cnt[7]_i_1 
       (.I0(io_write_data[7]),
        .I1(cnt_clr_reg_0),
        .I2(a_b_cmd_sel_start0),
        .I3(cal_seq_cnt0__0[7]),
        .O(\cal_seq_cnt[7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[8]_i_1 
       (.I0(io_write_data[8]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[8]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[8]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[8]_i_10 
       (.I0(\cal_seq_cnt_reg[31]_0 [1]),
        .O(\cal_seq_cnt[8]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[8]_i_3 
       (.I0(\cal_seq_cnt_reg[31]_0 [8]),
        .O(\cal_seq_cnt[8]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[8]_i_4 
       (.I0(\cal_seq_cnt_reg[31]_0 [7]),
        .O(\cal_seq_cnt[8]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[8]_i_5 
       (.I0(\cal_seq_cnt_reg[31]_0 [6]),
        .O(\cal_seq_cnt[8]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[8]_i_6 
       (.I0(\cal_seq_cnt_reg[31]_0 [5]),
        .O(\cal_seq_cnt[8]_i_6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[8]_i_7 
       (.I0(\cal_seq_cnt_reg[31]_0 [4]),
        .O(\cal_seq_cnt[8]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[8]_i_8 
       (.I0(\cal_seq_cnt_reg[31]_0 [3]),
        .O(\cal_seq_cnt[8]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cal_seq_cnt[8]_i_9 
       (.I0(\cal_seq_cnt_reg[31]_0 [2]),
        .O(\cal_seq_cnt[8]_i_9_n_0 ));
  LUT4 #(
    .INIT(16'h88B8)) 
    \cal_seq_cnt[9]_i_1 
       (.I0(io_write_data[9]),
        .I1(a_b_cmd_sel_start0),
        .I2(cal_seq_cnt0__0[9]),
        .I3(cnt_clr_reg_0),
        .O(\cal_seq_cnt[9]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    cal_seq_cnt_gt_0_i_10
       (.I0(cal_seq_cnt_gt_0_i_15_n_0),
        .I1(\cal_seq_cnt_reg[31]_0 [31]),
        .I2(\cal_seq_cnt_reg[31]_0 [14]),
        .I3(\cal_seq_cnt_reg[31]_0 [3]),
        .I4(\cal_seq_cnt_reg[31]_0 [4]),
        .I5(cal_seq_cnt_gt_0_i_16_n_0),
        .O(cal_seq_cnt_gt_0_i_10_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF4)) 
    cal_seq_cnt_gt_0_i_11
       (.I0(seq_cnt_dec),
        .I1(\cal_seq_cnt_reg[31]_0 [0]),
        .I2(\cal_seq_cnt_reg[31]_0 [29]),
        .I3(\cal_seq_cnt_reg[31]_0 [20]),
        .I4(\cal_seq_cnt_reg[31]_0 [26]),
        .I5(\cal_seq_cnt_reg[31]_0 [9]),
        .O(cal_seq_cnt_gt_0_i_11_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    cal_seq_cnt_gt_0_i_14
       (.I0(\cal_seq_cnt_reg[31]_0 [24]),
        .I1(\cal_seq_cnt_reg[31]_0 [27]),
        .I2(\cal_seq_cnt_reg[31]_0 [16]),
        .I3(\cal_seq_cnt_reg[31]_0 [21]),
        .O(cal_seq_cnt_gt_0_i_14_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    cal_seq_cnt_gt_0_i_15
       (.I0(\cal_seq_cnt_reg[31]_0 [11]),
        .I1(\cal_seq_cnt_reg[31]_0 [15]),
        .I2(\cal_seq_cnt_reg[31]_0 [2]),
        .I3(\cal_seq_cnt_reg[31]_0 [17]),
        .O(cal_seq_cnt_gt_0_i_15_n_0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    cal_seq_cnt_gt_0_i_16
       (.I0(\cal_seq_cnt_reg[31]_0 [30]),
        .I1(\cal_seq_cnt_reg[31]_0 [6]),
        .I2(\cal_seq_cnt_reg[31]_0 [10]),
        .I3(\cal_seq_cnt_reg[31]_0 [8]),
        .I4(cal_seq_cnt_gt_0_i_17_n_0),
        .O(cal_seq_cnt_gt_0_i_16_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    cal_seq_cnt_gt_0_i_17
       (.I0(\cal_seq_cnt_reg[31]_0 [5]),
        .I1(\cal_seq_cnt_reg[31]_0 [25]),
        .I2(\cal_seq_cnt_reg[31]_0 [18]),
        .I3(\cal_seq_cnt_reg[31]_0 [23]),
        .O(cal_seq_cnt_gt_0_i_17_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    cal_seq_cnt_gt_0_i_4
       (.I0(cal_seq_cnt_gt_0_i_9_n_0),
        .I1(\cal_seq_cnt_reg[31]_0 [13]),
        .I2(\cal_seq_cnt_reg[31]_0 [12]),
        .I3(\cal_seq_cnt_reg[31]_0 [19]),
        .I4(cal_seq_cnt_gt_0_i_10_n_0),
        .I5(cal_seq_cnt_gt_0_i_11_n_0),
        .O(\cal_seq_cnt_reg[13]_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    cal_seq_cnt_gt_0_i_9
       (.I0(\cal_seq_cnt_reg[31]_0 [28]),
        .I1(\cal_seq_cnt_reg[31]_0 [1]),
        .I2(\cal_seq_cnt_reg[31]_0 [22]),
        .I3(\cal_seq_cnt_reg[31]_0 [7]),
        .I4(cal_seq_cnt_gt_0_i_14_n_0),
        .O(cal_seq_cnt_gt_0_i_9_n_0));
  FDRE cal_seq_cnt_gt_0_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_seq_cnt_gt_0_reg_0),
        .Q(cal_seq_cnt_gt_0),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[0]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[10]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[11]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[12]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[13]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[14]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[15]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[16]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [16]),
        .R(1'b0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 \cal_seq_cnt_reg[16]_i_2 
       (.CI(\cal_seq_cnt_reg[8]_i_2_n_0 ),
        .CI_TOP(1'b0),
        .CO({\cal_seq_cnt_reg[16]_i_2_n_0 ,\cal_seq_cnt_reg[16]_i_2_n_1 ,\cal_seq_cnt_reg[16]_i_2_n_2 ,\cal_seq_cnt_reg[16]_i_2_n_3 ,\cal_seq_cnt_reg[16]_i_2_n_4 ,\cal_seq_cnt_reg[16]_i_2_n_5 ,\cal_seq_cnt_reg[16]_i_2_n_6 ,\cal_seq_cnt_reg[16]_i_2_n_7 }),
        .DI(\cal_seq_cnt_reg[31]_0 [16:9]),
        .O(cal_seq_cnt0__0[16:9]),
        .S({\cal_seq_cnt[16]_i_3_n_0 ,\cal_seq_cnt[16]_i_4_n_0 ,\cal_seq_cnt[16]_i_5_n_0 ,\cal_seq_cnt[16]_i_6_n_0 ,\cal_seq_cnt[16]_i_7_n_0 ,\cal_seq_cnt[16]_i_8_n_0 ,\cal_seq_cnt[16]_i_9_n_0 ,\cal_seq_cnt[16]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[17]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [17]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[18]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [18]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[19]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [19]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[1]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[20]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [20]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[21]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [21]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[22]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [22]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[23]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [23]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[24]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [24]),
        .R(1'b0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 \cal_seq_cnt_reg[24]_i_2 
       (.CI(\cal_seq_cnt_reg[16]_i_2_n_0 ),
        .CI_TOP(1'b0),
        .CO({\cal_seq_cnt_reg[24]_i_2_n_0 ,\cal_seq_cnt_reg[24]_i_2_n_1 ,\cal_seq_cnt_reg[24]_i_2_n_2 ,\cal_seq_cnt_reg[24]_i_2_n_3 ,\cal_seq_cnt_reg[24]_i_2_n_4 ,\cal_seq_cnt_reg[24]_i_2_n_5 ,\cal_seq_cnt_reg[24]_i_2_n_6 ,\cal_seq_cnt_reg[24]_i_2_n_7 }),
        .DI(\cal_seq_cnt_reg[31]_0 [24:17]),
        .O(cal_seq_cnt0__0[24:17]),
        .S({\cal_seq_cnt[24]_i_3_n_0 ,\cal_seq_cnt[24]_i_4_n_0 ,\cal_seq_cnt[24]_i_5_n_0 ,\cal_seq_cnt[24]_i_6_n_0 ,\cal_seq_cnt[24]_i_7_n_0 ,\cal_seq_cnt[24]_i_8_n_0 ,\cal_seq_cnt[24]_i_9_n_0 ,\cal_seq_cnt[24]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[25]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [25]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[26]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [26]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[27]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [27]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[28]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [28]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[29]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [29]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[2]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[30]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [30]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[31]_i_2_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [31]),
        .R(1'b0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 \cal_seq_cnt_reg[31]_i_3 
       (.CI(\cal_seq_cnt_reg[24]_i_2_n_0 ),
        .CI_TOP(1'b0),
        .CO({\NLW_cal_seq_cnt_reg[31]_i_3_CO_UNCONNECTED [7:6],\cal_seq_cnt_reg[31]_i_3_n_2 ,\cal_seq_cnt_reg[31]_i_3_n_3 ,\cal_seq_cnt_reg[31]_i_3_n_4 ,\cal_seq_cnt_reg[31]_i_3_n_5 ,\cal_seq_cnt_reg[31]_i_3_n_6 ,\cal_seq_cnt_reg[31]_i_3_n_7 }),
        .DI({1'b0,1'b0,\cal_seq_cnt_reg[31]_0 [30:25]}),
        .O({\NLW_cal_seq_cnt_reg[31]_i_3_O_UNCONNECTED [7],cal_seq_cnt0__0[31:25]}),
        .S({1'b0,\cal_seq_cnt[31]_i_4_n_0 ,\cal_seq_cnt[31]_i_5_n_0 ,\cal_seq_cnt[31]_i_6_n_0 ,\cal_seq_cnt[31]_i_7_n_0 ,\cal_seq_cnt[31]_i_8_n_0 ,\cal_seq_cnt[31]_i_9_n_0 ,\cal_seq_cnt[31]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[3]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[4]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[5]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[6]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[7]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[8]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [8]),
        .R(1'b0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 \cal_seq_cnt_reg[8]_i_2 
       (.CI(\cal_seq_cnt_reg[31]_0 [0]),
        .CI_TOP(1'b0),
        .CO({\cal_seq_cnt_reg[8]_i_2_n_0 ,\cal_seq_cnt_reg[8]_i_2_n_1 ,\cal_seq_cnt_reg[8]_i_2_n_2 ,\cal_seq_cnt_reg[8]_i_2_n_3 ,\cal_seq_cnt_reg[8]_i_2_n_4 ,\cal_seq_cnt_reg[8]_i_2_n_5 ,\cal_seq_cnt_reg[8]_i_2_n_6 ,\cal_seq_cnt_reg[8]_i_2_n_7 }),
        .DI(\cal_seq_cnt_reg[31]_0 [8:1]),
        .O(cal_seq_cnt0__0[8:1]),
        .S({\cal_seq_cnt[8]_i_3_n_0 ,\cal_seq_cnt[8]_i_4_n_0 ,\cal_seq_cnt[8]_i_5_n_0 ,\cal_seq_cnt[8]_i_6_n_0 ,\cal_seq_cnt[8]_i_7_n_0 ,\cal_seq_cnt[8]_i_8_n_0 ,\cal_seq_cnt[8]_i_9_n_0 ,\cal_seq_cnt[8]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_cnt_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_cnt[31]_i_1_n_0 ),
        .D(\cal_seq_cnt[9]_i_1_n_0 ),
        .Q(\cal_seq_cnt_reg[31]_0 [9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair902" *) 
  LUT4 #(
    .INIT(16'h888B)) 
    \cal_seq_rd_cnt[0]_i_1 
       (.I0(io_write_data[0]),
        .I1(a_b_cmd_sel_start0),
        .I2(cnt_clr_reg_0),
        .I3(\cal_seq_rd_cnt_reg[7]_0 [0]),
        .O(\cal_seq_rd_cnt[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h8B88888B)) 
    \cal_seq_rd_cnt[1]_i_1 
       (.I0(io_write_data[1]),
        .I1(a_b_cmd_sel_start0),
        .I2(cnt_clr_reg_0),
        .I3(\cal_seq_rd_cnt_reg[7]_0 [1]),
        .I4(\cal_seq_rd_cnt_reg[7]_0 [0]),
        .O(\cal_seq_rd_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBB8888B)) 
    \cal_seq_rd_cnt[2]_i_1 
       (.I0(io_write_data[2]),
        .I1(a_b_cmd_sel_start0),
        .I2(\cal_seq_rd_cnt_reg[7]_0 [0]),
        .I3(\cal_seq_rd_cnt_reg[7]_0 [1]),
        .I4(\cal_seq_rd_cnt_reg[7]_0 [2]),
        .I5(cnt_clr_reg_0),
        .O(\cal_seq_rd_cnt[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h88888BB8)) 
    \cal_seq_rd_cnt[3]_i_1 
       (.I0(io_write_data[3]),
        .I1(a_b_cmd_sel_start0),
        .I2(\cal_seq_rd_cnt[3]_i_2_n_0 ),
        .I3(\cal_seq_rd_cnt_reg[7]_0 [3]),
        .I4(cnt_clr_reg_0),
        .O(\cal_seq_rd_cnt[3]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \cal_seq_rd_cnt[3]_i_2 
       (.I0(\cal_seq_rd_cnt_reg[7]_0 [1]),
        .I1(\cal_seq_rd_cnt_reg[7]_0 [0]),
        .I2(\cal_seq_rd_cnt_reg[7]_0 [2]),
        .O(\cal_seq_rd_cnt[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h88888BB8)) 
    \cal_seq_rd_cnt[4]_i_1 
       (.I0(io_write_data[4]),
        .I1(a_b_cmd_sel_start0),
        .I2(\cal_seq_rd_cnt[4]_i_2_n_0 ),
        .I3(\cal_seq_rd_cnt_reg[7]_0 [4]),
        .I4(cnt_clr_reg_0),
        .O(\cal_seq_rd_cnt[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair885" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \cal_seq_rd_cnt[4]_i_2 
       (.I0(\cal_seq_rd_cnt_reg[7]_0 [2]),
        .I1(\cal_seq_rd_cnt_reg[7]_0 [0]),
        .I2(\cal_seq_rd_cnt_reg[7]_0 [1]),
        .I3(\cal_seq_rd_cnt_reg[7]_0 [3]),
        .O(\cal_seq_rd_cnt[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFF060006)) 
    \cal_seq_rd_cnt[5]_i_1 
       (.I0(\cal_seq_rd_cnt_reg[7]_0 [5]),
        .I1(\cal_seq_rd_cnt[5]_i_2_n_0 ),
        .I2(cnt_clr_reg_0),
        .I3(a_b_cmd_sel_start0),
        .I4(io_write_data[5]),
        .O(\cal_seq_rd_cnt[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair885" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \cal_seq_rd_cnt[5]_i_2 
       (.I0(\cal_seq_rd_cnt_reg[7]_0 [3]),
        .I1(\cal_seq_rd_cnt_reg[7]_0 [1]),
        .I2(\cal_seq_rd_cnt_reg[7]_0 [0]),
        .I3(\cal_seq_rd_cnt_reg[7]_0 [2]),
        .I4(\cal_seq_rd_cnt_reg[7]_0 [4]),
        .O(\cal_seq_rd_cnt[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFF060006)) 
    \cal_seq_rd_cnt[6]_i_1 
       (.I0(\cal_seq_rd_cnt_reg[7]_0 [6]),
        .I1(\cal_seq_rd_cnt[7]_i_4_n_0 ),
        .I2(cnt_clr_reg_0),
        .I3(a_b_cmd_sel_start0),
        .I4(io_write_data[6]),
        .O(\cal_seq_rd_cnt[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000DDDDDD5D)) 
    \cal_seq_rd_cnt[7]_i_1 
       (.I0(\cal_seq_rd_cnt[7]_i_3_n_0 ),
        .I1(p_0_in32_in),
        .I2(\cal_seq_rd_cnt[7]_i_4_n_0 ),
        .I3(\cal_seq_rd_cnt_reg[7]_0 [6]),
        .I4(\cal_seq_rd_cnt_reg[7]_0 [7]),
        .I5(cnt_clr_access),
        .O(\cal_seq_rd_cnt[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF009A0000009A)) 
    \cal_seq_rd_cnt[7]_i_2 
       (.I0(\cal_seq_rd_cnt_reg[7]_0 [7]),
        .I1(\cal_seq_rd_cnt_reg[7]_0 [6]),
        .I2(\cal_seq_rd_cnt[7]_i_4_n_0 ),
        .I3(cnt_clr_reg_0),
        .I4(a_b_cmd_sel_start0),
        .I5(io_write_data[7]),
        .O(\cal_seq_rd_cnt[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \cal_seq_rd_cnt[7]_i_3 
       (.I0(cnt_clr_reg_0),
        .I1(a_b_cmd_sel_start0),
        .O(\cal_seq_rd_cnt[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \cal_seq_rd_cnt[7]_i_4 
       (.I0(\cal_seq_rd_cnt_reg[7]_0 [4]),
        .I1(\cal_seq_rd_cnt_reg[7]_0 [2]),
        .I2(\cal_seq_rd_cnt_reg[7]_0 [0]),
        .I3(\cal_seq_rd_cnt_reg[7]_0 [1]),
        .I4(\cal_seq_rd_cnt_reg[7]_0 [3]),
        .I5(\cal_seq_rd_cnt_reg[7]_0 [5]),
        .O(\cal_seq_rd_cnt[7]_i_4_n_0 ));
  FDRE \cal_seq_rd_cnt_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_rd_cnt[7]_i_1_n_0 ),
        .D(\cal_seq_rd_cnt[0]_i_1_n_0 ),
        .Q(\cal_seq_rd_cnt_reg[7]_0 [0]),
        .R(1'b0));
  FDRE \cal_seq_rd_cnt_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_rd_cnt[7]_i_1_n_0 ),
        .D(\cal_seq_rd_cnt[1]_i_1_n_0 ),
        .Q(\cal_seq_rd_cnt_reg[7]_0 [1]),
        .R(1'b0));
  FDRE \cal_seq_rd_cnt_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_rd_cnt[7]_i_1_n_0 ),
        .D(\cal_seq_rd_cnt[2]_i_1_n_0 ),
        .Q(\cal_seq_rd_cnt_reg[7]_0 [2]),
        .R(1'b0));
  FDRE \cal_seq_rd_cnt_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_rd_cnt[7]_i_1_n_0 ),
        .D(\cal_seq_rd_cnt[3]_i_1_n_0 ),
        .Q(\cal_seq_rd_cnt_reg[7]_0 [3]),
        .R(1'b0));
  FDRE \cal_seq_rd_cnt_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_rd_cnt[7]_i_1_n_0 ),
        .D(\cal_seq_rd_cnt[4]_i_1_n_0 ),
        .Q(\cal_seq_rd_cnt_reg[7]_0 [4]),
        .R(1'b0));
  FDRE \cal_seq_rd_cnt_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_rd_cnt[7]_i_1_n_0 ),
        .D(\cal_seq_rd_cnt[5]_i_1_n_0 ),
        .Q(\cal_seq_rd_cnt_reg[7]_0 [5]),
        .R(1'b0));
  FDRE \cal_seq_rd_cnt_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_rd_cnt[7]_i_1_n_0 ),
        .D(\cal_seq_rd_cnt[6]_i_1_n_0 ),
        .Q(\cal_seq_rd_cnt_reg[7]_0 [6]),
        .R(1'b0));
  FDRE \cal_seq_rd_cnt_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_rd_cnt[7]_i_1_n_0 ),
        .D(\cal_seq_rd_cnt[7]_i_2_n_0 ),
        .Q(\cal_seq_rd_cnt_reg[7]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_reg[2]_0 ),
        .D(io_write_data[0]),
        .Q(\cal_seq_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_reg[2]_0 ),
        .D(io_write_data[1]),
        .Q(wrlvl_mode),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_seq_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cal_seq_reg[2]_0 ),
        .D(io_write_data[2]),
        .Q(\cal_seq_reg_n_0_[2] ),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'hFFFFFFFD)) 
    \cal_timer[0]_i_1 
       (.I0(cal_timer_reg[5]),
        .I1(\cal_timer_reg[0]_0 ),
        .I2(\cal_timer[0]_i_4_n_0 ),
        .I3(\cal_timer[0]_i_5_n_0 ),
        .I4(\cal_timer[0]_i_6_n_0 ),
        .O(cal_timer0));
  LUT3 #(
    .INIT(8'hC5)) 
    \cal_timer[0]_i_15 
       (.I0(cal_timer_reg[0]),
        .I1(io_write_data[0]),
        .I2(\cal_timer_reg[0]_0 ),
        .O(S));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \cal_timer[0]_i_16 
       (.I0(cal_timer_reg[26]),
        .I1(cal_timer_reg[25]),
        .I2(cal_timer_reg[21]),
        .I3(cal_timer_reg[9]),
        .O(\cal_timer[0]_i_16_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \cal_timer[0]_i_17 
       (.I0(cal_timer_reg[16]),
        .I1(cal_timer_reg[2]),
        .I2(cal_timer_reg[15]),
        .I3(cal_timer_reg[14]),
        .O(\cal_timer[0]_i_17_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \cal_timer[0]_i_18 
       (.I0(cal_timer_reg[17]),
        .I1(cal_timer_reg[4]),
        .I2(cal_timer_reg[22]),
        .I3(cal_timer_reg[19]),
        .O(\cal_timer[0]_i_18_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \cal_timer[0]_i_19 
       (.I0(cal_timer_reg[30]),
        .I1(cal_timer_reg[29]),
        .I2(cal_timer_reg[24]),
        .I3(cal_timer_reg[0]),
        .O(\cal_timer[0]_i_19_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \cal_timer[0]_i_20 
       (.I0(cal_timer_reg[7]),
        .I1(cal_timer_reg[1]),
        .I2(cal_timer_reg[28]),
        .I3(cal_timer_reg[20]),
        .O(\cal_timer[0]_i_20_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \cal_timer[0]_i_4 
       (.I0(cal_timer_reg[8]),
        .I1(cal_timer_reg[27]),
        .I2(cal_timer_reg[10]),
        .I3(cal_timer_reg[18]),
        .I4(\cal_timer[0]_i_16_n_0 ),
        .O(\cal_timer[0]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \cal_timer[0]_i_5 
       (.I0(cal_timer_reg[12]),
        .I1(cal_timer_reg[23]),
        .I2(cal_timer_reg[11]),
        .I3(cal_timer_reg[13]),
        .I4(\cal_timer[0]_i_17_n_0 ),
        .O(\cal_timer[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFFFFFFFFFFFFF)) 
    \cal_timer[0]_i_6 
       (.I0(\cal_timer[0]_i_18_n_0 ),
        .I1(\cal_timer[0]_i_19_n_0 ),
        .I2(\cal_timer[0]_i_20_n_0 ),
        .I3(cal_timer_reg[3]),
        .I4(cal_timer_reg[31]),
        .I5(cal_timer_reg[6]),
        .O(\cal_timer[0]_i_6_n_0 ));
  FDRE \cal_timer_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(O[0]),
        .Q(cal_timer_reg[0]),
        .R(rst_r1));
  FDRE \cal_timer_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[15]_0 [2]),
        .Q(cal_timer_reg[10]),
        .R(rst_r1));
  FDRE \cal_timer_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[15]_0 [3]),
        .Q(cal_timer_reg[11]),
        .R(rst_r1));
  FDRE \cal_timer_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[15]_0 [4]),
        .Q(cal_timer_reg[12]),
        .R(rst_r1));
  FDRE \cal_timer_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[15]_0 [5]),
        .Q(cal_timer_reg[13]),
        .R(rst_r1));
  FDRE \cal_timer_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[15]_0 [6]),
        .Q(cal_timer_reg[14]),
        .R(rst_r1));
  FDRE \cal_timer_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[15]_0 [7]),
        .Q(cal_timer_reg[15]),
        .R(rst_r1));
  FDRE \cal_timer_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[23]_0 [0]),
        .Q(cal_timer_reg[16]),
        .R(rst_r1));
  FDRE \cal_timer_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[23]_0 [1]),
        .Q(cal_timer_reg[17]),
        .R(rst_r1));
  FDRE \cal_timer_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[23]_0 [2]),
        .Q(cal_timer_reg[18]),
        .R(rst_r1));
  FDRE \cal_timer_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[23]_0 [3]),
        .Q(cal_timer_reg[19]),
        .R(rst_r1));
  FDRE \cal_timer_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(O[1]),
        .Q(cal_timer_reg[1]),
        .R(rst_r1));
  FDRE \cal_timer_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[23]_0 [4]),
        .Q(cal_timer_reg[20]),
        .R(rst_r1));
  FDRE \cal_timer_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[23]_0 [5]),
        .Q(cal_timer_reg[21]),
        .R(rst_r1));
  FDRE \cal_timer_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[23]_0 [6]),
        .Q(cal_timer_reg[22]),
        .R(rst_r1));
  FDRE \cal_timer_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[23]_0 [7]),
        .Q(cal_timer_reg[23]),
        .R(rst_r1));
  FDRE \cal_timer_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[31]_0 [0]),
        .Q(cal_timer_reg[24]),
        .R(rst_r1));
  FDRE \cal_timer_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[31]_0 [1]),
        .Q(cal_timer_reg[25]),
        .R(rst_r1));
  FDRE \cal_timer_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[31]_0 [2]),
        .Q(cal_timer_reg[26]),
        .R(rst_r1));
  FDRE \cal_timer_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[31]_0 [3]),
        .Q(cal_timer_reg[27]),
        .R(rst_r1));
  FDRE \cal_timer_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[31]_0 [4]),
        .Q(cal_timer_reg[28]),
        .R(rst_r1));
  FDRE \cal_timer_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[31]_0 [5]),
        .Q(cal_timer_reg[29]),
        .R(rst_r1));
  FDRE \cal_timer_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(O[2]),
        .Q(cal_timer_reg[2]),
        .R(rst_r1));
  FDRE \cal_timer_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[31]_0 [6]),
        .Q(cal_timer_reg[30]),
        .R(rst_r1));
  FDRE \cal_timer_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[31]_0 [7]),
        .Q(cal_timer_reg[31]),
        .R(rst_r1));
  FDRE \cal_timer_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(O[3]),
        .Q(cal_timer_reg[3]),
        .R(rst_r1));
  FDRE \cal_timer_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(O[4]),
        .Q(cal_timer_reg[4]),
        .R(rst_r1));
  FDRE \cal_timer_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(O[5]),
        .Q(cal_timer_reg[5]),
        .R(rst_r1));
  FDRE \cal_timer_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(O[6]),
        .Q(cal_timer_reg[6]),
        .R(rst_r1));
  FDRE \cal_timer_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(O[7]),
        .Q(cal_timer_reg[7]),
        .R(rst_r1));
  FDRE \cal_timer_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[15]_0 [0]),
        .Q(cal_timer_reg[8]),
        .R(rst_r1));
  FDRE \cal_timer_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(cal_timer0),
        .D(\cal_timer_reg[15]_0 [1]),
        .Q(cal_timer_reg[9]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \casSlot_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_cs_pos_reg_n_0_[0] ),
        .Q(\casSlot_reg_n_0_[0] ),
        .R(cplx_cal));
  FDSE #(
    .INIT(1'b0)) 
    \casSlot_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_cs_pos_reg_n_0_[1] ),
        .Q(calCasSlot),
        .S(cplx_cal));
  (* SOFT_HLUTNM = "soft_lutpair1538" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \clb2phy_fifo_rden[103]_i_1 
       (.I0(lrdimm_cal_mode),
        .I1(wrlvl_mode),
        .I2(calDone_reg_0),
        .O(clb2phy_fifo_rden_nxt0));
  FDRE \clb2phy_fifo_rden_reg[103] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(clb2phy_fifo_rden_nxt0),
        .Q(D),
        .R(1'b0));
  FDRE \clb2phy_wrcs0_low_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\clb2phy_wrcs0_low_reg[31]_0 ),
        .D(io_write_data[0]),
        .Q(\clb2phy_wrcs0_low_reg_n_0_[31] ),
        .R(rst_r1));
  FDRE \clb2phy_wrcs1_low_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\clb2phy_wrcs0_low_reg[31]_0 ),
        .D(io_write_data[1]),
        .Q(\clb2phy_wrcs1_low_reg_n_0_[31] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair1538" *) 
  LUT2 #(
    .INIT(4'h2)) 
    clear_fifo_rden_i_1
       (.I0(cnt_clr_reg_0),
        .I1(calDone_reg_0),
        .O(clear_fifo_rden_nxt));
  FDRE clear_fifo_rden_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(clear_fifo_rden_nxt),
        .Q(cal_clear_fifo_rden),
        .R(1'b0));
  FDRE clear_gt_data_ready_flag_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(clear_gt_data_ready_flag),
        .Q(clear_gt_data_ready_flag_reg_0),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_gen_dly[0]_i_1 
       (.I0(cmd_gen_dly_reg[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1539" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cmd_gen_dly[1]_i_1 
       (.I0(cmd_gen_dly_reg[0]),
        .I1(cmd_gen_dly_reg[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1539" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cmd_gen_dly[2]_i_1 
       (.I0(cmd_gen_dly_reg[2]),
        .I1(cmd_gen_dly_reg[1]),
        .I2(cmd_gen_dly_reg[0]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair886" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cmd_gen_dly[3]_i_1 
       (.I0(cmd_gen_dly_reg[3]),
        .I1(cmd_gen_dly_reg[0]),
        .I2(cmd_gen_dly_reg[1]),
        .I3(cmd_gen_dly_reg[2]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair886" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cmd_gen_dly[4]_i_1 
       (.I0(cmd_gen_dly_reg[4]),
        .I1(cmd_gen_dly_reg[2]),
        .I2(cmd_gen_dly_reg[1]),
        .I3(cmd_gen_dly_reg[0]),
        .I4(cmd_gen_dly_reg[3]),
        .O(p_0_in__0[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cmd_gen_dly[5]_i_1 
       (.I0(cmd_gen_dly_reg[5]),
        .I1(cmd_gen_dly_reg[3]),
        .I2(cmd_gen_dly_reg[0]),
        .I3(cmd_gen_dly_reg[1]),
        .I4(cmd_gen_dly_reg[2]),
        .I5(cmd_gen_dly_reg[4]),
        .O(p_0_in__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair1537" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cmd_gen_dly[6]_i_1 
       (.I0(cmd_gen_dly_reg[6]),
        .I1(\cmd_gen_dly[7]_i_4_n_0 ),
        .O(p_0_in__0[6]));
  LUT4 #(
    .INIT(16'hFBFF)) 
    \cmd_gen_dly[7]_i_1 
       (.I0(\cmd_gen_dly_reg[7]_i_3_n_0 ),
        .I1(cal_seq_cnt_gt_0),
        .I2(rst_r1),
        .I3(cmd_go_reg_n_0),
        .O(\cmd_gen_dly[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4004000000004004)) 
    \cmd_gen_dly[7]_i_10 
       (.I0(\cmd_gen_dly[7]_i_13_n_0 ),
        .I1(\cmd_gen_dly[7]_i_14_n_0 ),
        .I2(cmd_gen_dly_reg[6]),
        .I3(\cal_seq_b_a_dly_reg_n_0_[6] ),
        .I4(cmd_gen_dly_reg[7]),
        .I5(\cal_seq_b_a_dly_reg_n_0_[7] ),
        .O(\cmd_gen_dly[7]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmd_gen_dly[7]_i_11 
       (.I0(\cal_seq_a_b_dly_reg_n_0_[0] ),
        .I1(cmd_gen_dly_reg[0]),
        .I2(cmd_gen_dly_reg[1]),
        .I3(\cal_seq_a_b_dly_reg_n_0_[1] ),
        .I4(cmd_gen_dly_reg[2]),
        .I5(\cal_seq_a_b_dly_reg_n_0_[2] ),
        .O(\cmd_gen_dly[7]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmd_gen_dly[7]_i_12 
       (.I0(\cal_seq_a_b_dly_reg_n_0_[3] ),
        .I1(cmd_gen_dly_reg[3]),
        .I2(cmd_gen_dly_reg[5]),
        .I3(\cal_seq_a_b_dly_reg_n_0_[5] ),
        .I4(cmd_gen_dly_reg[4]),
        .I5(\cal_seq_a_b_dly_reg_n_0_[4] ),
        .O(\cmd_gen_dly[7]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmd_gen_dly[7]_i_13 
       (.I0(\cal_seq_b_a_dly_reg_n_0_[0] ),
        .I1(cmd_gen_dly_reg[0]),
        .I2(cmd_gen_dly_reg[2]),
        .I3(\cal_seq_b_a_dly_reg_n_0_[2] ),
        .I4(cmd_gen_dly_reg[1]),
        .I5(\cal_seq_b_a_dly_reg_n_0_[1] ),
        .O(\cmd_gen_dly[7]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \cmd_gen_dly[7]_i_14 
       (.I0(\cal_seq_b_a_dly_reg_n_0_[3] ),
        .I1(cmd_gen_dly_reg[3]),
        .I2(cmd_gen_dly_reg[5]),
        .I3(\cal_seq_b_a_dly_reg_n_0_[5] ),
        .I4(cmd_gen_dly_reg[4]),
        .I5(\cal_seq_b_a_dly_reg_n_0_[4] ),
        .O(\cmd_gen_dly[7]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1537" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cmd_gen_dly[7]_i_2 
       (.I0(cmd_gen_dly_reg[7]),
        .I1(\cmd_gen_dly[7]_i_4_n_0 ),
        .I2(cmd_gen_dly_reg[6]),
        .O(p_0_in__0[7]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \cmd_gen_dly[7]_i_4 
       (.I0(cmd_gen_dly_reg[5]),
        .I1(cmd_gen_dly_reg[3]),
        .I2(cmd_gen_dly_reg[0]),
        .I3(cmd_gen_dly_reg[1]),
        .I4(cmd_gen_dly_reg[2]),
        .I5(cmd_gen_dly_reg[4]),
        .O(\cmd_gen_dly[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4004000000004004)) 
    \cmd_gen_dly[7]_i_5 
       (.I0(\cmd_gen_dly[7]_i_7_n_0 ),
        .I1(\cmd_gen_dly[7]_i_8_n_0 ),
        .I2(cmd_gen_dly_reg[6]),
        .I3(\cal_seq_a_a_dly_reg_n_0_[6] ),
        .I4(cmd_gen_dly_reg[7]),
        .I5(\cal_seq_a_a_dly_reg_n_0_[7] ),
        .O(\cmd_gen_dly[7]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hBEEB8228)) 
    \cmd_gen_dly[7]_i_6 
       (.I0(\cmd_gen_dly[7]_i_9_n_0 ),
        .I1(seq_cnt_dec),
        .I2(\cal_seq_cnt_reg[31]_0 [0]),
        .I3(a_b_cmd_sel_start_reg_0),
        .I4(\cmd_gen_dly[7]_i_10_n_0 ),
        .O(\cmd_gen_dly[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmd_gen_dly[7]_i_7 
       (.I0(\cal_seq_a_a_dly_reg_n_0_[0] ),
        .I1(cmd_gen_dly_reg[0]),
        .I2(cmd_gen_dly_reg[1]),
        .I3(\cal_seq_a_a_dly_reg_n_0_[1] ),
        .I4(cmd_gen_dly_reg[2]),
        .I5(\cal_seq_a_a_dly_reg_n_0_[2] ),
        .O(\cmd_gen_dly[7]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \cmd_gen_dly[7]_i_8 
       (.I0(\cal_seq_a_a_dly_reg_n_0_[3] ),
        .I1(cmd_gen_dly_reg[3]),
        .I2(cmd_gen_dly_reg[4]),
        .I3(\cal_seq_a_a_dly_reg_n_0_[4] ),
        .I4(cmd_gen_dly_reg[5]),
        .I5(\cal_seq_a_a_dly_reg_n_0_[5] ),
        .O(\cmd_gen_dly[7]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000009009)) 
    \cmd_gen_dly[7]_i_9 
       (.I0(cmd_gen_dly_reg[7]),
        .I1(\cal_seq_a_b_dly_reg_n_0_[7] ),
        .I2(cmd_gen_dly_reg[6]),
        .I3(\cal_seq_a_b_dly_reg_n_0_[6] ),
        .I4(\cmd_gen_dly[7]_i_11_n_0 ),
        .I5(\cmd_gen_dly[7]_i_12_n_0 ),
        .O(\cmd_gen_dly[7]_i_9_n_0 ));
  FDRE \cmd_gen_dly_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(cmd_gen_dly_reg[0]),
        .R(\cmd_gen_dly[7]_i_1_n_0 ));
  FDRE \cmd_gen_dly_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(cmd_gen_dly_reg[1]),
        .R(\cmd_gen_dly[7]_i_1_n_0 ));
  FDRE \cmd_gen_dly_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(cmd_gen_dly_reg[2]),
        .R(\cmd_gen_dly[7]_i_1_n_0 ));
  FDRE \cmd_gen_dly_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(cmd_gen_dly_reg[3]),
        .R(\cmd_gen_dly[7]_i_1_n_0 ));
  FDRE \cmd_gen_dly_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(p_0_in__0[4]),
        .Q(cmd_gen_dly_reg[4]),
        .R(\cmd_gen_dly[7]_i_1_n_0 ));
  FDRE \cmd_gen_dly_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(p_0_in__0[5]),
        .Q(cmd_gen_dly_reg[5]),
        .R(\cmd_gen_dly[7]_i_1_n_0 ));
  FDRE \cmd_gen_dly_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(p_0_in__0[6]),
        .Q(cmd_gen_dly_reg[6]),
        .R(\cmd_gen_dly[7]_i_1_n_0 ));
  FDRE \cmd_gen_dly_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(p_0_in__0[7]),
        .Q(cmd_gen_dly_reg[7]),
        .R(\cmd_gen_dly[7]_i_1_n_0 ));
  MUXF7 \cmd_gen_dly_reg[7]_i_3 
       (.I0(\cmd_gen_dly[7]_i_5_n_0 ),
        .I1(\cmd_gen_dly[7]_i_6_n_0 ),
        .O(\cmd_gen_dly_reg[7]_i_3_n_0 ),
        .S(\cal_seq_reg_n_0_[0] ));
  LUT5 #(
    .INIT(32'hAAAAEA00)) 
    cmd_go_i_1
       (.I0(cmd_go_reg_n_0),
        .I1(cmd_go_ind),
        .I2(seq_cnt_access),
        .I3(cal_seq_cnt_gt_0),
        .I4(rst_r1),
        .O(cmd_go_i_1_n_0));
  FDRE cmd_go_ind_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(p_52_in),
        .Q(cmd_go_ind),
        .R(1'b0));
  FDRE cmd_go_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cmd_go_i_1_n_0),
        .Q(cmd_go_reg_n_0),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmp_byte_reg[0]" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cmp_byte_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cmp_byte_reg[2]_0 ),
        .D(io_address[1]),
        .Q(\cmp_byte_reg_n_0_[0] ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmp_byte_reg[0]" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cmp_byte_reg[0]_rep 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cmp_byte_reg[2]_0 ),
        .D(io_address[1]),
        .Q(\cmp_byte_reg[0]_rep_n_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmp_byte_reg[1]" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cmp_byte_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cmp_byte_reg[2]_0 ),
        .D(io_address[2]),
        .Q(\cmp_byte_reg_n_0_[1] ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "cmp_byte_reg[1]" *) 
  FDRE #(
    .INIT(1'b0)) 
    \cmp_byte_reg[1]_rep 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cmp_byte_reg[2]_0 ),
        .D(io_address[2]),
        .Q(\cmp_byte_reg[1]_rep_n_0 ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cmp_byte_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cmp_byte_reg[2]_0 ),
        .D(io_address[3]),
        .Q(\cmp_byte_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    cnt_clr_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cnt_clr_reg_1),
        .Q(cnt_clr_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFF55FFFFFFFFEA55)) 
    \cntr[17]_i_1 
       (.I0(Q[2]),
        .I1(ub_initDone_reg_0),
        .I2(pllGate),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(Q[3]),
        .O(\calSt_reg[2] ));
  LUT2 #(
    .INIT(4'h2)) 
    config_rd_val_i_1
       (.I0(io_addr_strobe_r1_reg_0),
        .I1(\cplx_config_reg[16]_0 ),
        .O(config_rd_val0));
  FDRE config_rd_val_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(config_rd_val0),
        .Q(config_rd_val),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hCAAAAAAA)) 
    \cplx_config[16]_i_1 
       (.I0(\cplx_config_reg_n_0_[16] ),
        .I1(io_write_data[16]),
        .I2(io_addr_strobe_r1_reg_0),
        .I3(\cplx_config_reg[16]_0 ),
        .I4(\cplx_config_reg[16]_1 ),
        .O(cplx_config0_out));
  FDRE \cplx_config_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cplx_config_reg[0]_0 ),
        .Q(\cplx_config_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[10]),
        .Q(\cplx_config_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[11]),
        .Q(\cplx_config_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[12]),
        .Q(\cplx_config_reg_n_0_[12] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[13]),
        .Q(\cplx_config_reg_n_0_[13] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[14]),
        .Q(\cplx_config_reg_n_0_[14] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[15]),
        .Q(\cplx_config_reg_n_0_[15] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cplx_config0_out),
        .Q(\cplx_config_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[1]),
        .Q(\cplx_config_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[2]),
        .Q(\cplx_config_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[3]),
        .Q(\cplx_config_reg_n_0_[3] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[4]),
        .Q(\cplx_config_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[5]),
        .Q(\cplx_config_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[6]),
        .Q(\cplx_config_reg_n_0_[6] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[7]),
        .Q(\cplx_config_reg_n_0_[7] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[8]),
        .Q(\cplx_config_reg_n_0_[8] ),
        .R(rst_r1));
  FDRE \cplx_config_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\cplx_config_reg[1]_0 ),
        .D(io_write_data[9]),
        .Q(\cplx_config_reg_n_0_[9] ),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1 
       (.I0(DQOut[2]),
        .I1(DQOut[6]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9] ),
        .I4(DQOut[4]),
        .O(\wosp_reg[1]_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__0 
       (.I0(DQOut[10]),
        .I1(DQOut[14]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[12]),
        .O(\wosp_reg[1]_2 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__1 
       (.I0(DQOut[18]),
        .I1(DQOut[22]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[20]),
        .O(\wosp_reg[1]_4 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__10 
       (.I0(DQOut[82]),
        .I1(DQOut[86]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[84]),
        .O(\wosp_reg[1]_22 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__11 
       (.I0(DQOut[90]),
        .I1(DQOut[94]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[92]),
        .O(\wosp_reg[1]_24 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__12 
       (.I0(DQOut[98]),
        .I1(DQOut[102]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[100]),
        .O(\wosp_reg[1]_26 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__13 
       (.I0(DQOut[106]),
        .I1(DQOut[110]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[108]),
        .O(\wosp_reg[1]_28 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__14 
       (.I0(DQOut[114]),
        .I1(DQOut[118]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[116]),
        .O(\wosp_reg[1]_30 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__15 
       (.I0(DQOut[122]),
        .I1(DQOut[126]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[124]),
        .O(\wosp_reg[1]_32 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__16 
       (.I0(DMOut[10]),
        .I1(DMOut[14]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DMOut[12]),
        .O(\wosp_reg[1]_34 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__17 
       (.I0(DQOut[130]),
        .I1(DQOut[134]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9] ),
        .I4(DQOut[132]),
        .O(\wosp_reg[1]_36 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__18 
       (.I0(DQOut[138]),
        .I1(DQOut[142]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[140]),
        .O(\wosp_reg[1]_38 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__19 
       (.I0(DQOut[146]),
        .I1(DQOut[150]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[148]),
        .O(\wosp_reg[1]_40 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__2 
       (.I0(DQOut[26]),
        .I1(DQOut[30]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[28]),
        .O(\wosp_reg[1]_6 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__20 
       (.I0(DQOut[154]),
        .I1(DQOut[158]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[156]),
        .O(\wosp_reg[1]_42 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__21 
       (.I0(DQOut[162]),
        .I1(DQOut[166]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[164]),
        .O(\wosp_reg[1]_44 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__22 
       (.I0(DQOut[170]),
        .I1(DQOut[174]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[172]),
        .O(\wosp_reg[1]_46 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__23 
       (.I0(DQOut[178]),
        .I1(DQOut[182]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[180]),
        .O(\wosp_reg[1]_48 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__24 
       (.I0(DQOut[186]),
        .I1(DQOut[190]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[188]),
        .O(\wosp_reg[1]_50 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__25 
       (.I0(DMOut[18]),
        .I1(DMOut[22]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DMOut[20]),
        .O(\wosp_reg[1]_52 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__26 
       (.I0(DQOut[194]),
        .I1(DQOut[198]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_1 ),
        .I4(DQOut[196]),
        .O(\wosp_reg[1]_54 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__27 
       (.I0(DQOut[202]),
        .I1(DQOut[206]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[204]),
        .O(\wosp_reg[1]_56 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__28 
       (.I0(DQOut[210]),
        .I1(DQOut[214]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[212]),
        .O(\wosp_reg[1]_58 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__29 
       (.I0(DQOut[218]),
        .I1(DQOut[222]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[220]),
        .O(\wosp_reg[1]_60 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__3 
       (.I0(DQOut[34]),
        .I1(DQOut[38]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[36]),
        .O(\wosp_reg[1]_8 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__30 
       (.I0(DQOut[226]),
        .I1(DQOut[230]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[228]),
        .O(\wosp_reg[1]_62 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__31 
       (.I0(DQOut[234]),
        .I1(DQOut[238]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[236]),
        .O(\wosp_reg[1]_64 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__32 
       (.I0(DQOut[242]),
        .I1(DQOut[246]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[244]),
        .O(\wosp_reg[1]_66 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__33 
       (.I0(DQOut[250]),
        .I1(DQOut[254]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[252]),
        .O(\wosp_reg[1]_68 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__34 
       (.I0(DMOut[26]),
        .I1(DMOut[30]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DMOut[28]),
        .O(\wosp_reg[1]_70 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__35 
       (.I0(DQOut[258]),
        .I1(DQOut[262]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_1 ),
        .I4(DQOut[260]),
        .O(\wosp_reg[1]_72 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__36 
       (.I0(DQOut[266]),
        .I1(DQOut[270]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[268]),
        .O(\wosp_reg[1]_74 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__37 
       (.I0(DQOut[274]),
        .I1(DQOut[278]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[276]),
        .O(\wosp_reg[1]_76 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__38 
       (.I0(DQOut[282]),
        .I1(DQOut[286]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[284]),
        .O(\wosp_reg[1]_78 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__39 
       (.I0(DQOut[290]),
        .I1(DQOut[294]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[292]),
        .O(\wosp_reg[1]_80 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__4 
       (.I0(DQOut[42]),
        .I1(DQOut[46]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11] ),
        .I4(DQOut[44]),
        .O(\wosp_reg[1]_10 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__40 
       (.I0(DQOut[298]),
        .I1(DQOut[302]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[300]),
        .O(\wosp_reg[1]_82 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__41 
       (.I0(DQOut[306]),
        .I1(DQOut[310]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[308]),
        .O(\wosp_reg[1]_84 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__42 
       (.I0(DQOut[314]),
        .I1(DQOut[318]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[316]),
        .O(\wosp_reg[1]_86 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__43 
       (.I0(DMOut[34]),
        .I1(DMOut[38]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DMOut[36]),
        .O(\wosp_reg[1]_88 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__44 
       (.I0(DQOut[322]),
        .I1(DQOut[326]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_1 ),
        .I4(DQOut[324]),
        .O(\wosp_reg[1]_90 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__45 
       (.I0(DQOut[330]),
        .I1(DQOut[334]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[332]),
        .O(\wosp_reg[1]_92 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__46 
       (.I0(DQOut[338]),
        .I1(DQOut[342]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[340]),
        .O(\wosp_reg[1]_94 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__47 
       (.I0(DQOut[346]),
        .I1(DQOut[350]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[348]),
        .O(\wosp_reg[1]_96 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__48 
       (.I0(DQOut[354]),
        .I1(DQOut[358]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[356]),
        .O(\wosp_reg[1]_98 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__49 
       (.I0(DQOut[362]),
        .I1(DQOut[366]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[364]),
        .O(\wosp_reg[1]_100 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__5 
       (.I0(DQOut[50]),
        .I1(DQOut[54]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11] ),
        .I4(DQOut[52]),
        .O(\wosp_reg[1]_12 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__50 
       (.I0(DQOut[370]),
        .I1(DQOut[374]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[372]),
        .O(\wosp_reg[1]_102 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__51 
       (.I0(DQOut[378]),
        .I1(DQOut[382]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[380]),
        .O(\wosp_reg[1]_104 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__52 
       (.I0(DMOut[42]),
        .I1(DMOut[46]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DMOut[44]),
        .O(\wosp_reg[1]_106 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__53 
       (.I0(DQOut[386]),
        .I1(DQOut[390]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11] ),
        .I4(DQOut[388]),
        .O(\wosp_reg[1]_108 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__54 
       (.I0(DQOut[394]),
        .I1(DQOut[398]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[396]),
        .O(\wosp_reg[1]_110 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__55 
       (.I0(DQOut[402]),
        .I1(DQOut[406]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[404]),
        .O(\wosp_reg[1]_112 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__56 
       (.I0(DQOut[410]),
        .I1(DQOut[414]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[412]),
        .O(\wosp_reg[1]_114 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__57 
       (.I0(DQOut[418]),
        .I1(DQOut[422]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[420]),
        .O(\wosp_reg[1]_116 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__58 
       (.I0(DQOut[426]),
        .I1(DQOut[430]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[428]),
        .O(\wosp_reg[1]_118 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__59 
       (.I0(DQOut[434]),
        .I1(DQOut[438]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[436]),
        .O(\wosp_reg[1]_120 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__6 
       (.I0(DQOut[58]),
        .I1(DQOut[62]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11] ),
        .I4(DQOut[60]),
        .O(\wosp_reg[1]_14 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__60 
       (.I0(DQOut[442]),
        .I1(DQOut[446]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[444]),
        .O(\wosp_reg[1]_122 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__61 
       (.I0(DMOut[50]),
        .I1(DMOut[54]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DMOut[52]),
        .O(\wosp_reg[1]_124 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__62 
       (.I0(DQOut[450]),
        .I1(DQOut[454]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[452]),
        .O(\wosp_reg[1]_126 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__63 
       (.I0(DQOut[458]),
        .I1(DQOut[462]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[460]),
        .O(\wosp_reg[1]_128 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__64 
       (.I0(DQOut[466]),
        .I1(DQOut[470]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[468]),
        .O(\wosp_reg[1]_130 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__65 
       (.I0(DQOut[474]),
        .I1(DQOut[478]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[476]),
        .O(\wosp_reg[1]_132 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__66 
       (.I0(DQOut[482]),
        .I1(DQOut[486]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[484]),
        .O(\wosp_reg[1]_134 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__67 
       (.I0(DQOut[490]),
        .I1(DQOut[494]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[492]),
        .O(\wosp_reg[1]_136 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__68 
       (.I0(DQOut[498]),
        .I1(DQOut[502]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[500]),
        .O(\wosp_reg[1]_138 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__69 
       (.I0(DQOut[506]),
        .I1(DQOut[510]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[508]),
        .O(\wosp_reg[1]_140 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__7 
       (.I0(DMOut[2]),
        .I1(DMOut[6]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11] ),
        .I4(DMOut[4]),
        .O(\wosp_reg[1]_16 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__70 
       (.I0(DMOut[58]),
        .I1(DMOut[62]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DMOut[60]),
        .O(\wosp_reg[1]_142 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__8 
       (.I0(DQOut[66]),
        .I1(DQOut[70]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9] ),
        .I4(DQOut[68]),
        .O(\wosp_reg[1]_18 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[10]_i_1__9 
       (.I0(DQOut[74]),
        .I1(DQOut[78]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[76]),
        .O(\wosp_reg[1]_20 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__0 
       (.I0(DQOut[11]),
        .I1(DQOut[15]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[13]),
        .O(\wosp_reg[1]_1 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__1 
       (.I0(DQOut[19]),
        .I1(DQOut[23]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[21]),
        .O(\wosp_reg[1]_3 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__10 
       (.I0(DQOut[83]),
        .I1(DQOut[87]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[85]),
        .O(\wosp_reg[1]_21 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__11 
       (.I0(DQOut[91]),
        .I1(DQOut[95]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[93]),
        .O(\wosp_reg[1]_23 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__12 
       (.I0(DQOut[99]),
        .I1(DQOut[103]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[101]),
        .O(\wosp_reg[1]_25 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__13 
       (.I0(DQOut[107]),
        .I1(DQOut[111]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[109]),
        .O(\wosp_reg[1]_27 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__14 
       (.I0(DQOut[115]),
        .I1(DQOut[119]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[117]),
        .O(\wosp_reg[1]_29 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__15 
       (.I0(DQOut[123]),
        .I1(DQOut[127]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[125]),
        .O(\wosp_reg[1]_31 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__16 
       (.I0(DMOut[11]),
        .I1(DMOut[15]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DMOut[13]),
        .O(\wosp_reg[1]_33 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__17 
       (.I0(DQOut[131]),
        .I1(DQOut[135]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9] ),
        .I4(DQOut[133]),
        .O(\wosp_reg[1]_35 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__18 
       (.I0(DQOut[139]),
        .I1(DQOut[143]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[141]),
        .O(\wosp_reg[1]_37 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__19 
       (.I0(DQOut[147]),
        .I1(DQOut[151]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[149]),
        .O(\wosp_reg[1]_39 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__2 
       (.I0(DQOut[27]),
        .I1(DQOut[31]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[29]),
        .O(\wosp_reg[1]_5 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__20 
       (.I0(DQOut[155]),
        .I1(DQOut[159]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[157]),
        .O(\wosp_reg[1]_41 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__21 
       (.I0(DQOut[163]),
        .I1(DQOut[167]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[165]),
        .O(\wosp_reg[1]_43 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__22 
       (.I0(DQOut[171]),
        .I1(DQOut[175]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[173]),
        .O(\wosp_reg[1]_45 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__23 
       (.I0(DQOut[179]),
        .I1(DQOut[183]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[181]),
        .O(\wosp_reg[1]_47 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__24 
       (.I0(DQOut[187]),
        .I1(DQOut[191]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[189]),
        .O(\wosp_reg[1]_49 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__25 
       (.I0(DMOut[19]),
        .I1(DMOut[23]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DMOut[21]),
        .O(\wosp_reg[1]_51 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__26 
       (.I0(DQOut[195]),
        .I1(DQOut[199]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_1 ),
        .I4(DQOut[197]),
        .O(\wosp_reg[1]_53 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__27 
       (.I0(DQOut[203]),
        .I1(DQOut[207]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[205]),
        .O(\wosp_reg[1]_55 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__28 
       (.I0(DQOut[211]),
        .I1(DQOut[215]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[213]),
        .O(\wosp_reg[1]_57 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__29 
       (.I0(DQOut[219]),
        .I1(DQOut[223]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[221]),
        .O(\wosp_reg[1]_59 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__3 
       (.I0(DQOut[35]),
        .I1(DQOut[39]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_0 ),
        .I4(DQOut[37]),
        .O(\wosp_reg[1]_7 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__30 
       (.I0(DQOut[227]),
        .I1(DQOut[231]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[229]),
        .O(\wosp_reg[1]_61 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__31 
       (.I0(DQOut[235]),
        .I1(DQOut[239]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[237]),
        .O(\wosp_reg[1]_63 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__32 
       (.I0(DQOut[243]),
        .I1(DQOut[247]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[245]),
        .O(\wosp_reg[1]_65 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__33 
       (.I0(DQOut[251]),
        .I1(DQOut[255]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[253]),
        .O(\wosp_reg[1]_67 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__34 
       (.I0(DMOut[27]),
        .I1(DMOut[31]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DMOut[29]),
        .O(\wosp_reg[1]_69 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__35 
       (.I0(DQOut[259]),
        .I1(DQOut[263]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_1 ),
        .I4(DQOut[261]),
        .O(\wosp_reg[1]_71 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__36 
       (.I0(DQOut[267]),
        .I1(DQOut[271]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[269]),
        .O(\wosp_reg[1]_73 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__37 
       (.I0(DQOut[275]),
        .I1(DQOut[279]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[277]),
        .O(\wosp_reg[1]_75 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__38 
       (.I0(DQOut[283]),
        .I1(DQOut[287]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[285]),
        .O(\wosp_reg[1]_77 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__39 
       (.I0(DQOut[291]),
        .I1(DQOut[295]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[293]),
        .O(\wosp_reg[1]_79 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__4 
       (.I0(DQOut[43]),
        .I1(DQOut[47]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11] ),
        .I4(DQOut[45]),
        .O(\wosp_reg[1]_9 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__40 
       (.I0(DQOut[299]),
        .I1(DQOut[303]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[301]),
        .O(\wosp_reg[1]_81 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__41 
       (.I0(DQOut[307]),
        .I1(DQOut[311]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[309]),
        .O(\wosp_reg[1]_83 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__42 
       (.I0(DQOut[315]),
        .I1(DQOut[319]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DQOut[317]),
        .O(\wosp_reg[1]_85 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__43 
       (.I0(DMOut[35]),
        .I1(DMOut[39]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_0 ),
        .I4(DMOut[37]),
        .O(\wosp_reg[1]_87 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__44 
       (.I0(DQOut[323]),
        .I1(DQOut[327]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9]_1 ),
        .I4(DQOut[325]),
        .O(\wosp_reg[1]_89 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__45 
       (.I0(DQOut[331]),
        .I1(DQOut[335]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[333]),
        .O(\wosp_reg[1]_91 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__46 
       (.I0(DQOut[339]),
        .I1(DQOut[343]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[341]),
        .O(\wosp_reg[1]_93 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__47 
       (.I0(DQOut[347]),
        .I1(DQOut[351]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[349]),
        .O(\wosp_reg[1]_95 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__48 
       (.I0(DQOut[355]),
        .I1(DQOut[359]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[357]),
        .O(\wosp_reg[1]_97 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__49 
       (.I0(DQOut[363]),
        .I1(DQOut[367]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[365]),
        .O(\wosp_reg[1]_99 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__5 
       (.I0(DQOut[51]),
        .I1(DQOut[55]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11] ),
        .I4(DQOut[53]),
        .O(\wosp_reg[1]_11 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__50 
       (.I0(DQOut[371]),
        .I1(DQOut[375]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[373]),
        .O(\wosp_reg[1]_101 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__51 
       (.I0(DQOut[379]),
        .I1(DQOut[383]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DQOut[381]),
        .O(\wosp_reg[1]_103 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__52 
       (.I0(DMOut[43]),
        .I1(DMOut[47]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DMOut[45]),
        .O(\wosp_reg[1]_105 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__53 
       (.I0(DQOut[387]),
        .I1(DQOut[391]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11] ),
        .I4(DQOut[389]),
        .O(\wosp_reg[1]_107 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__54 
       (.I0(DQOut[395]),
        .I1(DQOut[399]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[397]),
        .O(\wosp_reg[1]_109 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__55 
       (.I0(DQOut[403]),
        .I1(DQOut[407]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[405]),
        .O(\wosp_reg[1]_111 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__56 
       (.I0(DQOut[411]),
        .I1(DQOut[415]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[413]),
        .O(\wosp_reg[1]_113 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__57 
       (.I0(DQOut[419]),
        .I1(DQOut[423]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[421]),
        .O(\wosp_reg[1]_115 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__58 
       (.I0(DQOut[427]),
        .I1(DQOut[431]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[429]),
        .O(\wosp_reg[1]_117 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__59 
       (.I0(DQOut[435]),
        .I1(DQOut[439]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[437]),
        .O(\wosp_reg[1]_119 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__6 
       (.I0(DQOut[59]),
        .I1(DQOut[63]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11] ),
        .I4(DQOut[61]),
        .O(\wosp_reg[1]_13 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__60 
       (.I0(DQOut[443]),
        .I1(DQOut[447]),
        .I2(wosp[1]),
        .I3(\dReg_reg[8] ),
        .I4(DQOut[445]),
        .O(\wosp_reg[1]_121 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__61 
       (.I0(DMOut[51]),
        .I1(DMOut[55]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11]_1 ),
        .I4(DMOut[53]),
        .O(\wosp_reg[1]_123 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__62 
       (.I0(DQOut[451]),
        .I1(DQOut[455]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[453]),
        .O(\wosp_reg[1]_125 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__63 
       (.I0(DQOut[459]),
        .I1(DQOut[463]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[461]),
        .O(\wosp_reg[1]_127 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__64 
       (.I0(DQOut[467]),
        .I1(DQOut[471]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[469]),
        .O(\wosp_reg[1]_129 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__65 
       (.I0(DQOut[475]),
        .I1(DQOut[479]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[477]),
        .O(\wosp_reg[1]_131 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__66 
       (.I0(DQOut[483]),
        .I1(DQOut[487]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[485]),
        .O(\wosp_reg[1]_133 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__67 
       (.I0(DQOut[491]),
        .I1(DQOut[495]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[493]),
        .O(\wosp_reg[1]_135 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__68 
       (.I0(DQOut[499]),
        .I1(DQOut[503]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[501]),
        .O(\wosp_reg[1]_137 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__69 
       (.I0(DQOut[507]),
        .I1(DQOut[511]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DQOut[509]),
        .O(\wosp_reg[1]_139 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__7 
       (.I0(DMOut[3]),
        .I1(DMOut[7]),
        .I2(wosp[1]),
        .I3(\dReg_reg[11] ),
        .I4(DMOut[5]),
        .O(\wosp_reg[1]_15 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__70 
       (.I0(DMOut[59]),
        .I1(DMOut[63]),
        .I2(wosp[1]),
        .I3(wosp[2]),
        .I4(DMOut[61]),
        .O(\wosp_reg[1]_141 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__8 
       (.I0(DQOut[67]),
        .I1(DQOut[71]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9] ),
        .I4(DQOut[69]),
        .O(\wosp_reg[1]_17 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_1__9 
       (.I0(DQOut[75]),
        .I1(DQOut[79]),
        .I2(wosp[1]),
        .I3(\dReg_reg[10] ),
        .I4(DQOut[77]),
        .O(\wosp_reg[1]_19 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \dReg[11]_i_2 
       (.I0(DQOut[3]),
        .I1(DQOut[7]),
        .I2(wosp[1]),
        .I3(\dReg_reg[9] ),
        .I4(DQOut[5]),
        .O(\wosp_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair1314" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2 
       (.I0(\dReg_reg[15] [487]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[508]),
        .O(DQOut[508]));
  (* SOFT_HLUTNM = "soft_lutpair1315" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__0 
       (.I0(\dReg_reg[15] [486]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[500]),
        .O(DQOut[500]));
  (* SOFT_HLUTNM = "soft_lutpair1316" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__1 
       (.I0(\dReg_reg[15] [485]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[492]),
        .O(DQOut[492]));
  (* SOFT_HLUTNM = "soft_lutpair1325" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__10 
       (.I0(\dReg_reg[15] [420]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[420]),
        .O(DQOut[420]));
  (* SOFT_HLUTNM = "soft_lutpair1326" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__11 
       (.I0(\dReg_reg[15] [419]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[412]),
        .O(DQOut[412]));
  (* SOFT_HLUTNM = "soft_lutpair1327" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__12 
       (.I0(\dReg_reg[15] [418]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[404]),
        .O(DQOut[404]));
  (* SOFT_HLUTNM = "soft_lutpair1328" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__13 
       (.I0(\dReg_reg[15] [417]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[396]),
        .O(DQOut[396]));
  (* SOFT_HLUTNM = "soft_lutpair1329" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__14 
       (.I0(\dReg_reg[15] [416]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[388]),
        .O(DQOut[388]));
  (* SOFT_HLUTNM = "soft_lutpair1330" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__15 
       (.I0(\dReg_reg[15] [359]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[380]),
        .O(DQOut[380]));
  (* SOFT_HLUTNM = "soft_lutpair1331" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__16 
       (.I0(\dReg_reg[15] [358]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[372]),
        .O(DQOut[372]));
  (* SOFT_HLUTNM = "soft_lutpair1332" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__17 
       (.I0(\dReg_reg[15] [357]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[364]),
        .O(DQOut[364]));
  (* SOFT_HLUTNM = "soft_lutpair1333" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__18 
       (.I0(\dReg_reg[15] [356]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[356]),
        .O(DQOut[356]));
  (* SOFT_HLUTNM = "soft_lutpair1334" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__19 
       (.I0(\dReg_reg[15] [355]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[348]),
        .O(DQOut[348]));
  (* SOFT_HLUTNM = "soft_lutpair1317" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__2 
       (.I0(\dReg_reg[15] [484]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[484]),
        .O(DQOut[484]));
  (* SOFT_HLUTNM = "soft_lutpair1335" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__20 
       (.I0(\dReg_reg[15] [354]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[340]),
        .O(DQOut[340]));
  (* SOFT_HLUTNM = "soft_lutpair1336" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__21 
       (.I0(\dReg_reg[15] [353]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[332]),
        .O(DQOut[332]));
  (* SOFT_HLUTNM = "soft_lutpair1337" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__22 
       (.I0(\dReg_reg[15] [352]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[324]),
        .O(DQOut[324]));
  (* SOFT_HLUTNM = "soft_lutpair1338" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__23 
       (.I0(\dReg_reg[15] [295]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[316]),
        .O(DQOut[316]));
  (* SOFT_HLUTNM = "soft_lutpair1339" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__24 
       (.I0(\dReg_reg[15] [294]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[308]),
        .O(DQOut[308]));
  (* SOFT_HLUTNM = "soft_lutpair1340" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__25 
       (.I0(\dReg_reg[15] [293]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[300]),
        .O(DQOut[300]));
  (* SOFT_HLUTNM = "soft_lutpair1341" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__26 
       (.I0(\dReg_reg[15] [292]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[292]),
        .O(DQOut[292]));
  (* SOFT_HLUTNM = "soft_lutpair1342" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__27 
       (.I0(\dReg_reg[15] [291]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[284]),
        .O(DQOut[284]));
  (* SOFT_HLUTNM = "soft_lutpair1343" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__28 
       (.I0(\dReg_reg[15] [290]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[276]),
        .O(DQOut[276]));
  (* SOFT_HLUTNM = "soft_lutpair1344" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__29 
       (.I0(\dReg_reg[15] [289]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[268]),
        .O(DQOut[268]));
  (* SOFT_HLUTNM = "soft_lutpair1318" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__3 
       (.I0(\dReg_reg[15] [483]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[476]),
        .O(DQOut[476]));
  (* SOFT_HLUTNM = "soft_lutpair1345" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__30 
       (.I0(\dReg_reg[15] [288]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[260]),
        .O(DQOut[260]));
  (* SOFT_HLUTNM = "soft_lutpair1346" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__31 
       (.I0(\dReg_reg[15] [231]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[252]),
        .O(DQOut[252]));
  (* SOFT_HLUTNM = "soft_lutpair1347" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__32 
       (.I0(\dReg_reg[15] [230]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[244]),
        .O(DQOut[244]));
  (* SOFT_HLUTNM = "soft_lutpair1348" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__33 
       (.I0(\dReg_reg[15] [229]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[236]),
        .O(DQOut[236]));
  (* SOFT_HLUTNM = "soft_lutpair1349" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__34 
       (.I0(\dReg_reg[15] [228]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[228]),
        .O(DQOut[228]));
  (* SOFT_HLUTNM = "soft_lutpair1350" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__35 
       (.I0(\dReg_reg[15] [227]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[220]),
        .O(DQOut[220]));
  (* SOFT_HLUTNM = "soft_lutpair1351" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__36 
       (.I0(\dReg_reg[15] [226]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[212]),
        .O(DQOut[212]));
  (* SOFT_HLUTNM = "soft_lutpair1352" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__37 
       (.I0(\dReg_reg[15] [225]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[204]),
        .O(DQOut[204]));
  (* SOFT_HLUTNM = "soft_lutpair1353" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__38 
       (.I0(\dReg_reg[15] [224]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[196]),
        .O(DQOut[196]));
  (* SOFT_HLUTNM = "soft_lutpair1354" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__39 
       (.I0(\dReg_reg[15] [167]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[188]),
        .O(DQOut[188]));
  (* SOFT_HLUTNM = "soft_lutpair1319" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__4 
       (.I0(\dReg_reg[15] [482]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[468]),
        .O(DQOut[468]));
  (* SOFT_HLUTNM = "soft_lutpair1355" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__40 
       (.I0(\dReg_reg[15] [166]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[180]),
        .O(DQOut[180]));
  (* SOFT_HLUTNM = "soft_lutpair1356" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__41 
       (.I0(\dReg_reg[15] [165]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[172]),
        .O(DQOut[172]));
  (* SOFT_HLUTNM = "soft_lutpair1357" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__42 
       (.I0(\dReg_reg[15] [164]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[164]),
        .O(DQOut[164]));
  (* SOFT_HLUTNM = "soft_lutpair1358" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__43 
       (.I0(\dReg_reg[15] [163]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[156]),
        .O(DQOut[156]));
  (* SOFT_HLUTNM = "soft_lutpair1359" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__44 
       (.I0(\dReg_reg[15] [162]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[148]),
        .O(DQOut[148]));
  (* SOFT_HLUTNM = "soft_lutpair1360" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__45 
       (.I0(\dReg_reg[15] [161]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[140]),
        .O(DQOut[140]));
  (* SOFT_HLUTNM = "soft_lutpair1361" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__46 
       (.I0(\dReg_reg[15] [160]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[132]),
        .O(DQOut[132]));
  (* SOFT_HLUTNM = "soft_lutpair1362" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__47 
       (.I0(\dReg_reg[15] [103]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[124]),
        .O(DQOut[124]));
  (* SOFT_HLUTNM = "soft_lutpair1363" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__48 
       (.I0(\dReg_reg[15] [102]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[116]),
        .O(DQOut[116]));
  (* SOFT_HLUTNM = "soft_lutpair1364" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__49 
       (.I0(\dReg_reg[15] [101]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[108]),
        .O(DQOut[108]));
  (* SOFT_HLUTNM = "soft_lutpair1320" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__5 
       (.I0(\dReg_reg[15] [481]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[460]),
        .O(DQOut[460]));
  (* SOFT_HLUTNM = "soft_lutpair1365" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__50 
       (.I0(\dReg_reg[15] [100]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[100]),
        .O(DQOut[100]));
  (* SOFT_HLUTNM = "soft_lutpair1366" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__51 
       (.I0(\dReg_reg[15] [99]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[92]),
        .O(DQOut[92]));
  (* SOFT_HLUTNM = "soft_lutpair1367" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__52 
       (.I0(\dReg_reg[15] [98]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[84]),
        .O(DQOut[84]));
  (* SOFT_HLUTNM = "soft_lutpair1368" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__53 
       (.I0(\dReg_reg[15] [97]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[76]),
        .O(DQOut[76]));
  (* SOFT_HLUTNM = "soft_lutpair1369" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__54 
       (.I0(\dReg_reg[15] [96]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[68]),
        .O(DQOut[68]));
  (* SOFT_HLUTNM = "soft_lutpair1370" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__55 
       (.I0(\dReg_reg[15] [39]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[60]),
        .O(DQOut[60]));
  (* SOFT_HLUTNM = "soft_lutpair1371" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__56 
       (.I0(\dReg_reg[15] [38]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[52]),
        .O(DQOut[52]));
  (* SOFT_HLUTNM = "soft_lutpair1372" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__57 
       (.I0(\dReg_reg[15] [37]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[44]),
        .O(DQOut[44]));
  (* SOFT_HLUTNM = "soft_lutpair1373" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__58 
       (.I0(\dReg_reg[15] [36]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[36]),
        .O(DQOut[36]));
  (* SOFT_HLUTNM = "soft_lutpair1374" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__59 
       (.I0(\dReg_reg[15] [35]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[28]),
        .O(DQOut[28]));
  (* SOFT_HLUTNM = "soft_lutpair1321" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__6 
       (.I0(\dReg_reg[15] [480]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[452]),
        .O(DQOut[452]));
  (* SOFT_HLUTNM = "soft_lutpair1375" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__60 
       (.I0(\dReg_reg[15] [34]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[20]),
        .O(DQOut[20]));
  (* SOFT_HLUTNM = "soft_lutpair1376" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__61 
       (.I0(\dReg_reg[15] [33]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[12]),
        .O(DQOut[12]));
  (* SOFT_HLUTNM = "soft_lutpair1377" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__62 
       (.I0(\dReg_reg[15] [32]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[4]),
        .O(DQOut[4]));
  (* SOFT_HLUTNM = "soft_lutpair1378" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[12]_i_2__63 
       (.I0(\dReg_reg[15] [572]),
        .I1(cal_DMOut_n[60]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[60]));
  (* SOFT_HLUTNM = "soft_lutpair1379" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[12]_i_2__64 
       (.I0(\dReg_reg[15] [564]),
        .I1(cal_DMOut_n[52]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[52]));
  (* SOFT_HLUTNM = "soft_lutpair1380" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[12]_i_2__65 
       (.I0(\dReg_reg[15] [556]),
        .I1(cal_DMOut_n[44]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[44]));
  (* SOFT_HLUTNM = "soft_lutpair1381" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[12]_i_2__66 
       (.I0(\dReg_reg[15] [548]),
        .I1(cal_DMOut_n[36]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[36]));
  (* SOFT_HLUTNM = "soft_lutpair1382" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[12]_i_2__67 
       (.I0(\dReg_reg[15] [540]),
        .I1(cal_DMOut_n[28]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[28]));
  (* SOFT_HLUTNM = "soft_lutpair1383" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[12]_i_2__68 
       (.I0(\dReg_reg[15] [532]),
        .I1(cal_DMOut_n[20]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[20]));
  (* SOFT_HLUTNM = "soft_lutpair1384" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[12]_i_2__69 
       (.I0(\dReg_reg[15] [524]),
        .I1(cal_DMOut_n[12]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[12]));
  (* SOFT_HLUTNM = "soft_lutpair1322" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__7 
       (.I0(\dReg_reg[15] [423]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[444]),
        .O(DQOut[444]));
  (* SOFT_HLUTNM = "soft_lutpair1385" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[12]_i_2__70 
       (.I0(\dReg_reg[15] [516]),
        .I1(cal_DMOut_n[4]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[4]));
  (* SOFT_HLUTNM = "soft_lutpair1323" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__8 
       (.I0(\dReg_reg[15] [422]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[436]),
        .O(DQOut[436]));
  (* SOFT_HLUTNM = "soft_lutpair1324" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[12]_i_2__9 
       (.I0(\dReg_reg[15] [421]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[428]),
        .O(DQOut[428]));
  (* SOFT_HLUTNM = "soft_lutpair1314" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2 
       (.I0(\dReg_reg[15] [495]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[509]),
        .O(DQOut[509]));
  (* SOFT_HLUTNM = "soft_lutpair1315" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__0 
       (.I0(\dReg_reg[15] [494]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[501]),
        .O(DQOut[501]));
  (* SOFT_HLUTNM = "soft_lutpair1316" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__1 
       (.I0(\dReg_reg[15] [493]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[493]),
        .O(DQOut[493]));
  (* SOFT_HLUTNM = "soft_lutpair1325" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__10 
       (.I0(\dReg_reg[15] [428]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[421]),
        .O(DQOut[421]));
  (* SOFT_HLUTNM = "soft_lutpair1326" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__11 
       (.I0(\dReg_reg[15] [427]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[413]),
        .O(DQOut[413]));
  (* SOFT_HLUTNM = "soft_lutpair1327" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__12 
       (.I0(\dReg_reg[15] [426]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[405]),
        .O(DQOut[405]));
  (* SOFT_HLUTNM = "soft_lutpair1328" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__13 
       (.I0(\dReg_reg[15] [425]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[397]),
        .O(DQOut[397]));
  (* SOFT_HLUTNM = "soft_lutpair1329" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__14 
       (.I0(\dReg_reg[15] [424]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[389]),
        .O(DQOut[389]));
  (* SOFT_HLUTNM = "soft_lutpair1330" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__15 
       (.I0(\dReg_reg[15] [367]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[381]),
        .O(DQOut[381]));
  (* SOFT_HLUTNM = "soft_lutpair1331" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__16 
       (.I0(\dReg_reg[15] [366]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[373]),
        .O(DQOut[373]));
  (* SOFT_HLUTNM = "soft_lutpair1332" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__17 
       (.I0(\dReg_reg[15] [365]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[365]),
        .O(DQOut[365]));
  (* SOFT_HLUTNM = "soft_lutpair1333" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__18 
       (.I0(\dReg_reg[15] [364]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[357]),
        .O(DQOut[357]));
  (* SOFT_HLUTNM = "soft_lutpair1334" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__19 
       (.I0(\dReg_reg[15] [363]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[349]),
        .O(DQOut[349]));
  (* SOFT_HLUTNM = "soft_lutpair1317" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__2 
       (.I0(\dReg_reg[15] [492]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[485]),
        .O(DQOut[485]));
  (* SOFT_HLUTNM = "soft_lutpair1335" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__20 
       (.I0(\dReg_reg[15] [362]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[341]),
        .O(DQOut[341]));
  (* SOFT_HLUTNM = "soft_lutpair1336" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__21 
       (.I0(\dReg_reg[15] [361]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[333]),
        .O(DQOut[333]));
  (* SOFT_HLUTNM = "soft_lutpair1337" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__22 
       (.I0(\dReg_reg[15] [360]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[325]),
        .O(DQOut[325]));
  (* SOFT_HLUTNM = "soft_lutpair1338" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__23 
       (.I0(\dReg_reg[15] [303]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[317]),
        .O(DQOut[317]));
  (* SOFT_HLUTNM = "soft_lutpair1339" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__24 
       (.I0(\dReg_reg[15] [302]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[309]),
        .O(DQOut[309]));
  (* SOFT_HLUTNM = "soft_lutpair1340" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__25 
       (.I0(\dReg_reg[15] [301]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[301]),
        .O(DQOut[301]));
  (* SOFT_HLUTNM = "soft_lutpair1341" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__26 
       (.I0(\dReg_reg[15] [300]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[293]),
        .O(DQOut[293]));
  (* SOFT_HLUTNM = "soft_lutpair1342" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__27 
       (.I0(\dReg_reg[15] [299]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[285]),
        .O(DQOut[285]));
  (* SOFT_HLUTNM = "soft_lutpair1343" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__28 
       (.I0(\dReg_reg[15] [298]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[277]),
        .O(DQOut[277]));
  (* SOFT_HLUTNM = "soft_lutpair1344" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__29 
       (.I0(\dReg_reg[15] [297]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[269]),
        .O(DQOut[269]));
  (* SOFT_HLUTNM = "soft_lutpair1318" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__3 
       (.I0(\dReg_reg[15] [491]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[477]),
        .O(DQOut[477]));
  (* SOFT_HLUTNM = "soft_lutpair1345" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__30 
       (.I0(\dReg_reg[15] [296]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[261]),
        .O(DQOut[261]));
  (* SOFT_HLUTNM = "soft_lutpair1346" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__31 
       (.I0(\dReg_reg[15] [239]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[253]),
        .O(DQOut[253]));
  (* SOFT_HLUTNM = "soft_lutpair1347" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__32 
       (.I0(\dReg_reg[15] [238]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[245]),
        .O(DQOut[245]));
  (* SOFT_HLUTNM = "soft_lutpair1348" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__33 
       (.I0(\dReg_reg[15] [237]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[237]),
        .O(DQOut[237]));
  (* SOFT_HLUTNM = "soft_lutpair1349" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__34 
       (.I0(\dReg_reg[15] [236]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[229]),
        .O(DQOut[229]));
  (* SOFT_HLUTNM = "soft_lutpair1350" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__35 
       (.I0(\dReg_reg[15] [235]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[221]),
        .O(DQOut[221]));
  (* SOFT_HLUTNM = "soft_lutpair1351" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__36 
       (.I0(\dReg_reg[15] [234]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[213]),
        .O(DQOut[213]));
  (* SOFT_HLUTNM = "soft_lutpair1352" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__37 
       (.I0(\dReg_reg[15] [233]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[205]),
        .O(DQOut[205]));
  (* SOFT_HLUTNM = "soft_lutpair1353" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__38 
       (.I0(\dReg_reg[15] [232]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[197]),
        .O(DQOut[197]));
  (* SOFT_HLUTNM = "soft_lutpair1354" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__39 
       (.I0(\dReg_reg[15] [175]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[189]),
        .O(DQOut[189]));
  (* SOFT_HLUTNM = "soft_lutpair1319" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__4 
       (.I0(\dReg_reg[15] [490]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[469]),
        .O(DQOut[469]));
  (* SOFT_HLUTNM = "soft_lutpair1355" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__40 
       (.I0(\dReg_reg[15] [174]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[181]),
        .O(DQOut[181]));
  (* SOFT_HLUTNM = "soft_lutpair1356" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__41 
       (.I0(\dReg_reg[15] [173]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[173]),
        .O(DQOut[173]));
  (* SOFT_HLUTNM = "soft_lutpair1357" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__42 
       (.I0(\dReg_reg[15] [172]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[165]),
        .O(DQOut[165]));
  (* SOFT_HLUTNM = "soft_lutpair1358" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__43 
       (.I0(\dReg_reg[15] [171]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[157]),
        .O(DQOut[157]));
  (* SOFT_HLUTNM = "soft_lutpair1359" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__44 
       (.I0(\dReg_reg[15] [170]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[149]),
        .O(DQOut[149]));
  (* SOFT_HLUTNM = "soft_lutpair1360" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__45 
       (.I0(\dReg_reg[15] [169]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[141]),
        .O(DQOut[141]));
  (* SOFT_HLUTNM = "soft_lutpair1361" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__46 
       (.I0(\dReg_reg[15] [168]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[133]),
        .O(DQOut[133]));
  (* SOFT_HLUTNM = "soft_lutpair1362" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__47 
       (.I0(\dReg_reg[15] [111]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[125]),
        .O(DQOut[125]));
  (* SOFT_HLUTNM = "soft_lutpair1363" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__48 
       (.I0(\dReg_reg[15] [110]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[117]),
        .O(DQOut[117]));
  (* SOFT_HLUTNM = "soft_lutpair1364" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__49 
       (.I0(\dReg_reg[15] [109]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[109]),
        .O(DQOut[109]));
  (* SOFT_HLUTNM = "soft_lutpair1320" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__5 
       (.I0(\dReg_reg[15] [489]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[461]),
        .O(DQOut[461]));
  (* SOFT_HLUTNM = "soft_lutpair1365" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__50 
       (.I0(\dReg_reg[15] [108]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[101]),
        .O(DQOut[101]));
  (* SOFT_HLUTNM = "soft_lutpair1366" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__51 
       (.I0(\dReg_reg[15] [107]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[93]),
        .O(DQOut[93]));
  (* SOFT_HLUTNM = "soft_lutpair1367" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__52 
       (.I0(\dReg_reg[15] [106]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[85]),
        .O(DQOut[85]));
  (* SOFT_HLUTNM = "soft_lutpair1368" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__53 
       (.I0(\dReg_reg[15] [105]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[77]),
        .O(DQOut[77]));
  (* SOFT_HLUTNM = "soft_lutpair1369" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__54 
       (.I0(\dReg_reg[15] [104]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[69]),
        .O(DQOut[69]));
  (* SOFT_HLUTNM = "soft_lutpair1370" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__55 
       (.I0(\dReg_reg[15] [47]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[61]),
        .O(DQOut[61]));
  (* SOFT_HLUTNM = "soft_lutpair1371" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__56 
       (.I0(\dReg_reg[15] [46]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[53]),
        .O(DQOut[53]));
  (* SOFT_HLUTNM = "soft_lutpair1372" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__57 
       (.I0(\dReg_reg[15] [45]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[45]),
        .O(DQOut[45]));
  (* SOFT_HLUTNM = "soft_lutpair1373" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__58 
       (.I0(\dReg_reg[15] [44]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[37]),
        .O(DQOut[37]));
  (* SOFT_HLUTNM = "soft_lutpair1374" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__59 
       (.I0(\dReg_reg[15] [43]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[29]),
        .O(DQOut[29]));
  (* SOFT_HLUTNM = "soft_lutpair1321" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__6 
       (.I0(\dReg_reg[15] [488]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[453]),
        .O(DQOut[453]));
  (* SOFT_HLUTNM = "soft_lutpair1375" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__60 
       (.I0(\dReg_reg[15] [42]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[21]),
        .O(DQOut[21]));
  (* SOFT_HLUTNM = "soft_lutpair1376" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__61 
       (.I0(\dReg_reg[15] [41]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[13]),
        .O(DQOut[13]));
  (* SOFT_HLUTNM = "soft_lutpair1377" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__62 
       (.I0(\dReg_reg[15] [40]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[5]),
        .O(DQOut[5]));
  (* SOFT_HLUTNM = "soft_lutpair1378" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[13]_i_2__63 
       (.I0(\dReg_reg[15] [573]),
        .I1(cal_DMOut_n[61]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[61]));
  (* SOFT_HLUTNM = "soft_lutpair1379" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[13]_i_2__64 
       (.I0(\dReg_reg[15] [565]),
        .I1(cal_DMOut_n[53]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[53]));
  (* SOFT_HLUTNM = "soft_lutpair1380" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[13]_i_2__65 
       (.I0(\dReg_reg[15] [557]),
        .I1(cal_DMOut_n[45]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[45]));
  (* SOFT_HLUTNM = "soft_lutpair1381" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[13]_i_2__66 
       (.I0(\dReg_reg[15] [549]),
        .I1(cal_DMOut_n[37]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[37]));
  (* SOFT_HLUTNM = "soft_lutpair1382" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[13]_i_2__67 
       (.I0(\dReg_reg[15] [541]),
        .I1(cal_DMOut_n[29]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[29]));
  (* SOFT_HLUTNM = "soft_lutpair1383" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[13]_i_2__68 
       (.I0(\dReg_reg[15] [533]),
        .I1(cal_DMOut_n[21]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[21]));
  (* SOFT_HLUTNM = "soft_lutpair1384" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[13]_i_2__69 
       (.I0(\dReg_reg[15] [525]),
        .I1(cal_DMOut_n[13]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[13]));
  (* SOFT_HLUTNM = "soft_lutpair1322" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__7 
       (.I0(\dReg_reg[15] [431]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[445]),
        .O(DQOut[445]));
  (* SOFT_HLUTNM = "soft_lutpair1385" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[13]_i_2__70 
       (.I0(\dReg_reg[15] [517]),
        .I1(cal_DMOut_n[5]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[5]));
  (* SOFT_HLUTNM = "soft_lutpair1323" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__8 
       (.I0(\dReg_reg[15] [430]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[437]),
        .O(DQOut[437]));
  (* SOFT_HLUTNM = "soft_lutpair1324" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[13]_i_2__9 
       (.I0(\dReg_reg[15] [429]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[429]),
        .O(DQOut[429]));
  (* SOFT_HLUTNM = "soft_lutpair1454" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__0 
       (.I0(\dReg_reg[15] [503]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[510]),
        .O(DQOut[510]));
  (* SOFT_HLUTNM = "soft_lutpair1514" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__1 
       (.I0(\dReg_reg[15] [502]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[502]),
        .O(DQOut[502]));
  (* SOFT_HLUTNM = "soft_lutpair1461" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__10 
       (.I0(\dReg_reg[15] [437]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[430]),
        .O(DQOut[430]));
  (* SOFT_HLUTNM = "soft_lutpair1517" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__11 
       (.I0(\dReg_reg[15] [436]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[422]),
        .O(DQOut[422]));
  (* SOFT_HLUTNM = "soft_lutpair1462" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__12 
       (.I0(\dReg_reg[15] [435]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[414]),
        .O(DQOut[414]));
  (* SOFT_HLUTNM = "soft_lutpair1463" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__13 
       (.I0(\dReg_reg[15] [434]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[406]),
        .O(DQOut[406]));
  (* SOFT_HLUTNM = "soft_lutpair1464" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__14 
       (.I0(\dReg_reg[15] [433]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[398]),
        .O(DQOut[398]));
  (* SOFT_HLUTNM = "soft_lutpair1517" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__15 
       (.I0(\dReg_reg[15] [432]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[390]),
        .O(DQOut[390]));
  (* SOFT_HLUTNM = "soft_lutpair1465" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__16 
       (.I0(\dReg_reg[15] [375]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[382]),
        .O(DQOut[382]));
  (* SOFT_HLUTNM = "soft_lutpair1518" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__17 
       (.I0(\dReg_reg[15] [374]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[374]),
        .O(DQOut[374]));
  (* SOFT_HLUTNM = "soft_lutpair1467" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__18 
       (.I0(\dReg_reg[15] [373]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[366]),
        .O(DQOut[366]));
  (* SOFT_HLUTNM = "soft_lutpair1519" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__19 
       (.I0(\dReg_reg[15] [372]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[358]),
        .O(DQOut[358]));
  (* SOFT_HLUTNM = "soft_lutpair1456" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__2 
       (.I0(\dReg_reg[15] [501]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[494]),
        .O(DQOut[494]));
  (* SOFT_HLUTNM = "soft_lutpair1468" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__20 
       (.I0(\dReg_reg[15] [371]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[350]),
        .O(DQOut[350]));
  (* SOFT_HLUTNM = "soft_lutpair1469" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__21 
       (.I0(\dReg_reg[15] [370]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[342]),
        .O(DQOut[342]));
  (* SOFT_HLUTNM = "soft_lutpair1470" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__22 
       (.I0(\dReg_reg[15] [369]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[334]),
        .O(DQOut[334]));
  (* SOFT_HLUTNM = "soft_lutpair1519" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__23 
       (.I0(\dReg_reg[15] [368]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[326]),
        .O(DQOut[326]));
  (* SOFT_HLUTNM = "soft_lutpair1471" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__24 
       (.I0(\dReg_reg[15] [311]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[318]),
        .O(DQOut[318]));
  (* SOFT_HLUTNM = "soft_lutpair1520" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__25 
       (.I0(\dReg_reg[15] [310]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[310]),
        .O(DQOut[310]));
  (* SOFT_HLUTNM = "soft_lutpair1472" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__26 
       (.I0(\dReg_reg[15] [309]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[302]),
        .O(DQOut[302]));
  (* SOFT_HLUTNM = "soft_lutpair1521" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__27 
       (.I0(\dReg_reg[15] [308]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[294]),
        .O(DQOut[294]));
  (* SOFT_HLUTNM = "soft_lutpair1473" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__28 
       (.I0(\dReg_reg[15] [307]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[286]),
        .O(DQOut[286]));
  (* SOFT_HLUTNM = "soft_lutpair1474" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__29 
       (.I0(\dReg_reg[15] [306]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[278]),
        .O(DQOut[278]));
  (* SOFT_HLUTNM = "soft_lutpair1515" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__3 
       (.I0(\dReg_reg[15] [500]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[486]),
        .O(DQOut[486]));
  (* SOFT_HLUTNM = "soft_lutpair1475" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__30 
       (.I0(\dReg_reg[15] [305]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[270]),
        .O(DQOut[270]));
  (* SOFT_HLUTNM = "soft_lutpair1521" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__31 
       (.I0(\dReg_reg[15] [304]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[262]),
        .O(DQOut[262]));
  (* SOFT_HLUTNM = "soft_lutpair1476" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__32 
       (.I0(\dReg_reg[15] [247]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[254]),
        .O(DQOut[254]));
  (* SOFT_HLUTNM = "soft_lutpair1522" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__33 
       (.I0(\dReg_reg[15] [246]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[246]),
        .O(DQOut[246]));
  (* SOFT_HLUTNM = "soft_lutpair1478" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__34 
       (.I0(\dReg_reg[15] [245]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[238]),
        .O(DQOut[238]));
  (* SOFT_HLUTNM = "soft_lutpair1523" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__35 
       (.I0(\dReg_reg[15] [244]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[230]),
        .O(DQOut[230]));
  (* SOFT_HLUTNM = "soft_lutpair1479" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__36 
       (.I0(\dReg_reg[15] [243]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[222]),
        .O(DQOut[222]));
  (* SOFT_HLUTNM = "soft_lutpair1480" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__37 
       (.I0(\dReg_reg[15] [242]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[214]),
        .O(DQOut[214]));
  (* SOFT_HLUTNM = "soft_lutpair1481" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__38 
       (.I0(\dReg_reg[15] [241]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[206]),
        .O(DQOut[206]));
  (* SOFT_HLUTNM = "soft_lutpair1523" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__39 
       (.I0(\dReg_reg[15] [240]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[198]),
        .O(DQOut[198]));
  (* SOFT_HLUTNM = "soft_lutpair1457" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__4 
       (.I0(\dReg_reg[15] [499]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[478]),
        .O(DQOut[478]));
  (* SOFT_HLUTNM = "soft_lutpair1482" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__40 
       (.I0(\dReg_reg[15] [183]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[190]),
        .O(DQOut[190]));
  (* SOFT_HLUTNM = "soft_lutpair1524" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__41 
       (.I0(\dReg_reg[15] [182]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[182]),
        .O(DQOut[182]));
  (* SOFT_HLUTNM = "soft_lutpair1483" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__42 
       (.I0(\dReg_reg[15] [181]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[174]),
        .O(DQOut[174]));
  (* SOFT_HLUTNM = "soft_lutpair1525" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__43 
       (.I0(\dReg_reg[15] [180]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[166]),
        .O(DQOut[166]));
  (* SOFT_HLUTNM = "soft_lutpair1484" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__44 
       (.I0(\dReg_reg[15] [179]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[158]),
        .O(DQOut[158]));
  (* SOFT_HLUTNM = "soft_lutpair1485" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__45 
       (.I0(\dReg_reg[15] [178]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[150]),
        .O(DQOut[150]));
  (* SOFT_HLUTNM = "soft_lutpair1486" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__46 
       (.I0(\dReg_reg[15] [177]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[142]),
        .O(DQOut[142]));
  (* SOFT_HLUTNM = "soft_lutpair1525" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__47 
       (.I0(\dReg_reg[15] [176]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[134]),
        .O(DQOut[134]));
  (* SOFT_HLUTNM = "soft_lutpair1487" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__48 
       (.I0(\dReg_reg[15] [119]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[126]),
        .O(DQOut[126]));
  (* SOFT_HLUTNM = "soft_lutpair1526" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__49 
       (.I0(\dReg_reg[15] [118]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[118]),
        .O(DQOut[118]));
  (* SOFT_HLUTNM = "soft_lutpair1458" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__5 
       (.I0(\dReg_reg[15] [498]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[470]),
        .O(DQOut[470]));
  (* SOFT_HLUTNM = "soft_lutpair1489" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__50 
       (.I0(\dReg_reg[15] [117]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[110]),
        .O(DQOut[110]));
  (* SOFT_HLUTNM = "soft_lutpair1527" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__51 
       (.I0(\dReg_reg[15] [116]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[102]),
        .O(DQOut[102]));
  (* SOFT_HLUTNM = "soft_lutpair1490" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__52 
       (.I0(\dReg_reg[15] [115]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[94]),
        .O(DQOut[94]));
  (* SOFT_HLUTNM = "soft_lutpair1491" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__53 
       (.I0(\dReg_reg[15] [114]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[86]),
        .O(DQOut[86]));
  (* SOFT_HLUTNM = "soft_lutpair1492" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__54 
       (.I0(\dReg_reg[15] [113]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[78]),
        .O(DQOut[78]));
  (* SOFT_HLUTNM = "soft_lutpair1527" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__55 
       (.I0(\dReg_reg[15] [112]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[70]),
        .O(DQOut[70]));
  (* SOFT_HLUTNM = "soft_lutpair1493" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__56 
       (.I0(\dReg_reg[15] [55]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[62]),
        .O(DQOut[62]));
  (* SOFT_HLUTNM = "soft_lutpair1528" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__57 
       (.I0(\dReg_reg[15] [54]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[54]),
        .O(DQOut[54]));
  (* SOFT_HLUTNM = "soft_lutpair1494" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__58 
       (.I0(\dReg_reg[15] [53]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[46]),
        .O(DQOut[46]));
  (* SOFT_HLUTNM = "soft_lutpair1529" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__59 
       (.I0(\dReg_reg[15] [52]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[38]),
        .O(DQOut[38]));
  (* SOFT_HLUTNM = "soft_lutpair1459" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__6 
       (.I0(\dReg_reg[15] [497]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[462]),
        .O(DQOut[462]));
  (* SOFT_HLUTNM = "soft_lutpair1495" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__60 
       (.I0(\dReg_reg[15] [51]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[30]),
        .O(DQOut[30]));
  (* SOFT_HLUTNM = "soft_lutpair1496" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__61 
       (.I0(\dReg_reg[15] [50]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[22]),
        .O(DQOut[22]));
  (* SOFT_HLUTNM = "soft_lutpair1497" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__62 
       (.I0(\dReg_reg[15] [49]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[14]),
        .O(DQOut[14]));
  (* SOFT_HLUTNM = "soft_lutpair1506" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[14]_i_1__63 
       (.I0(\dReg_reg[15] [574]),
        .I1(cal_DMOut_n[62]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[62]));
  (* SOFT_HLUTNM = "soft_lutpair1506" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[14]_i_1__64 
       (.I0(\dReg_reg[15] [566]),
        .I1(cal_DMOut_n[54]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[54]));
  (* SOFT_HLUTNM = "soft_lutpair1507" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[14]_i_1__65 
       (.I0(\dReg_reg[15] [558]),
        .I1(cal_DMOut_n[46]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[46]));
  (* SOFT_HLUTNM = "soft_lutpair1507" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[14]_i_1__66 
       (.I0(\dReg_reg[15] [550]),
        .I1(cal_DMOut_n[38]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[38]));
  (* SOFT_HLUTNM = "soft_lutpair1508" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[14]_i_1__67 
       (.I0(\dReg_reg[15] [542]),
        .I1(cal_DMOut_n[30]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[30]));
  (* SOFT_HLUTNM = "soft_lutpair1508" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[14]_i_1__68 
       (.I0(\dReg_reg[15] [534]),
        .I1(cal_DMOut_n[22]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[22]));
  (* SOFT_HLUTNM = "soft_lutpair1509" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[14]_i_1__69 
       (.I0(\dReg_reg[15] [526]),
        .I1(cal_DMOut_n[14]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[14]));
  (* SOFT_HLUTNM = "soft_lutpair1515" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__7 
       (.I0(\dReg_reg[15] [496]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[454]),
        .O(DQOut[454]));
  (* SOFT_HLUTNM = "soft_lutpair1509" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[14]_i_1__70 
       (.I0(\dReg_reg[15] [518]),
        .I1(cal_DMOut_n[6]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[6]));
  (* SOFT_HLUTNM = "soft_lutpair1460" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__8 
       (.I0(\dReg_reg[15] [439]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[446]),
        .O(DQOut[446]));
  (* SOFT_HLUTNM = "soft_lutpair1516" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_1__9 
       (.I0(\dReg_reg[15] [438]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[438]),
        .O(DQOut[438]));
  (* SOFT_HLUTNM = "soft_lutpair1529" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[14]_i_2 
       (.I0(\dReg_reg[15] [48]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[6]),
        .O(DQOut[6]));
  (* SOFT_HLUTNM = "soft_lutpair1514" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__10 
       (.I0(\dReg_reg[15] [508]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[487]),
        .O(DQOut[487]));
  (* SOFT_HLUTNM = "soft_lutpair1456" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__11 
       (.I0(\dReg_reg[15] [507]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[479]),
        .O(DQOut[479]));
  (* SOFT_HLUTNM = "soft_lutpair1457" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__12 
       (.I0(\dReg_reg[15] [506]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[471]),
        .O(DQOut[471]));
  (* SOFT_HLUTNM = "soft_lutpair1458" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__13 
       (.I0(\dReg_reg[15] [505]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[463]),
        .O(DQOut[463]));
  (* SOFT_HLUTNM = "soft_lutpair1459" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__14 
       (.I0(\dReg_reg[15] [447]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[447]),
        .O(DQOut[447]));
  (* SOFT_HLUTNM = "soft_lutpair1460" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__15 
       (.I0(\dReg_reg[15] [446]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[439]),
        .O(DQOut[439]));
  (* SOFT_HLUTNM = "soft_lutpair1461" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__16 
       (.I0(\dReg_reg[15] [445]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[431]),
        .O(DQOut[431]));
  (* SOFT_HLUTNM = "soft_lutpair1516" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__17 
       (.I0(\dReg_reg[15] [444]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[423]),
        .O(DQOut[423]));
  (* SOFT_HLUTNM = "soft_lutpair1462" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__18 
       (.I0(\dReg_reg[15] [443]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[415]),
        .O(DQOut[415]));
  (* SOFT_HLUTNM = "soft_lutpair1463" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__19 
       (.I0(\dReg_reg[15] [442]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[407]),
        .O(DQOut[407]));
  (* SOFT_HLUTNM = "soft_lutpair1464" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__20 
       (.I0(\dReg_reg[15] [441]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[399]),
        .O(DQOut[399]));
  (* SOFT_HLUTNM = "soft_lutpair1465" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__21 
       (.I0(\dReg_reg[15] [383]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[383]),
        .O(DQOut[383]));
  (* SOFT_HLUTNM = "soft_lutpair1466" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__22 
       (.I0(\dReg_reg[15] [382]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[375]),
        .O(DQOut[375]));
  (* SOFT_HLUTNM = "soft_lutpair1466" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__23 
       (.I0(\dReg_reg[15] [381]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[367]),
        .O(DQOut[367]));
  (* SOFT_HLUTNM = "soft_lutpair1518" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__24 
       (.I0(\dReg_reg[15] [380]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[359]),
        .O(DQOut[359]));
  (* SOFT_HLUTNM = "soft_lutpair1467" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__25 
       (.I0(\dReg_reg[15] [379]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[351]),
        .O(DQOut[351]));
  (* SOFT_HLUTNM = "soft_lutpair1468" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__26 
       (.I0(\dReg_reg[15] [378]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[343]),
        .O(DQOut[343]));
  (* SOFT_HLUTNM = "soft_lutpair1469" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__27 
       (.I0(\dReg_reg[15] [377]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[335]),
        .O(DQOut[335]));
  (* SOFT_HLUTNM = "soft_lutpair1470" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__28 
       (.I0(\dReg_reg[15] [319]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[319]),
        .O(DQOut[319]));
  (* SOFT_HLUTNM = "soft_lutpair1471" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__29 
       (.I0(\dReg_reg[15] [318]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[311]),
        .O(DQOut[311]));
  (* SOFT_HLUTNM = "soft_lutpair1472" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__30 
       (.I0(\dReg_reg[15] [317]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[303]),
        .O(DQOut[303]));
  (* SOFT_HLUTNM = "soft_lutpair1520" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__31 
       (.I0(\dReg_reg[15] [316]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[295]),
        .O(DQOut[295]));
  (* SOFT_HLUTNM = "soft_lutpair1473" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__32 
       (.I0(\dReg_reg[15] [315]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[287]),
        .O(DQOut[287]));
  (* SOFT_HLUTNM = "soft_lutpair1474" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__33 
       (.I0(\dReg_reg[15] [314]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[279]),
        .O(DQOut[279]));
  (* SOFT_HLUTNM = "soft_lutpair1475" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__34 
       (.I0(\dReg_reg[15] [313]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[271]),
        .O(DQOut[271]));
  (* SOFT_HLUTNM = "soft_lutpair1476" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__35 
       (.I0(\dReg_reg[15] [255]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[255]),
        .O(DQOut[255]));
  (* SOFT_HLUTNM = "soft_lutpair1477" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__36 
       (.I0(\dReg_reg[15] [254]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[247]),
        .O(DQOut[247]));
  (* SOFT_HLUTNM = "soft_lutpair1477" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__37 
       (.I0(\dReg_reg[15] [253]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[239]),
        .O(DQOut[239]));
  (* SOFT_HLUTNM = "soft_lutpair1522" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__38 
       (.I0(\dReg_reg[15] [252]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[231]),
        .O(DQOut[231]));
  (* SOFT_HLUTNM = "soft_lutpair1478" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__39 
       (.I0(\dReg_reg[15] [251]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[223]),
        .O(DQOut[223]));
  (* SOFT_HLUTNM = "soft_lutpair1479" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__40 
       (.I0(\dReg_reg[15] [250]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[215]),
        .O(DQOut[215]));
  (* SOFT_HLUTNM = "soft_lutpair1480" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__41 
       (.I0(\dReg_reg[15] [249]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[207]),
        .O(DQOut[207]));
  (* SOFT_HLUTNM = "soft_lutpair1481" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__42 
       (.I0(\dReg_reg[15] [191]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[191]),
        .O(DQOut[191]));
  (* SOFT_HLUTNM = "soft_lutpair1482" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__43 
       (.I0(\dReg_reg[15] [190]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[183]),
        .O(DQOut[183]));
  (* SOFT_HLUTNM = "soft_lutpair1483" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__44 
       (.I0(\dReg_reg[15] [189]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[175]),
        .O(DQOut[175]));
  (* SOFT_HLUTNM = "soft_lutpair1524" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__45 
       (.I0(\dReg_reg[15] [188]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[167]),
        .O(DQOut[167]));
  (* SOFT_HLUTNM = "soft_lutpair1484" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__46 
       (.I0(\dReg_reg[15] [187]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[159]),
        .O(DQOut[159]));
  (* SOFT_HLUTNM = "soft_lutpair1485" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__47 
       (.I0(\dReg_reg[15] [186]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[151]),
        .O(DQOut[151]));
  (* SOFT_HLUTNM = "soft_lutpair1486" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__48 
       (.I0(\dReg_reg[15] [185]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[143]),
        .O(DQOut[143]));
  (* SOFT_HLUTNM = "soft_lutpair1487" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__49 
       (.I0(\dReg_reg[15] [127]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[127]),
        .O(DQOut[127]));
  (* SOFT_HLUTNM = "soft_lutpair1488" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__50 
       (.I0(\dReg_reg[15] [126]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[119]),
        .O(DQOut[119]));
  (* SOFT_HLUTNM = "soft_lutpair1488" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__51 
       (.I0(\dReg_reg[15] [125]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[111]),
        .O(DQOut[111]));
  (* SOFT_HLUTNM = "soft_lutpair1526" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__52 
       (.I0(\dReg_reg[15] [124]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[103]),
        .O(DQOut[103]));
  (* SOFT_HLUTNM = "soft_lutpair1489" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__53 
       (.I0(\dReg_reg[15] [123]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[95]),
        .O(DQOut[95]));
  (* SOFT_HLUTNM = "soft_lutpair1490" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__54 
       (.I0(\dReg_reg[15] [122]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[87]),
        .O(DQOut[87]));
  (* SOFT_HLUTNM = "soft_lutpair1491" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__55 
       (.I0(\dReg_reg[15] [121]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[79]),
        .O(DQOut[79]));
  (* SOFT_HLUTNM = "soft_lutpair1492" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__56 
       (.I0(\dReg_reg[15] [63]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[63]),
        .O(DQOut[63]));
  (* SOFT_HLUTNM = "soft_lutpair1493" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__57 
       (.I0(\dReg_reg[15] [62]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[55]),
        .O(DQOut[55]));
  (* SOFT_HLUTNM = "soft_lutpair1494" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__58 
       (.I0(\dReg_reg[15] [61]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[47]),
        .O(DQOut[47]));
  (* SOFT_HLUTNM = "soft_lutpair1528" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__59 
       (.I0(\dReg_reg[15] [60]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[39]),
        .O(DQOut[39]));
  (* SOFT_HLUTNM = "soft_lutpair1495" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__60 
       (.I0(\dReg_reg[15] [59]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[31]),
        .O(DQOut[31]));
  (* SOFT_HLUTNM = "soft_lutpair1496" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__61 
       (.I0(\dReg_reg[15] [58]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[23]),
        .O(DQOut[23]));
  (* SOFT_HLUTNM = "soft_lutpair1497" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__62 
       (.I0(\dReg_reg[15] [57]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[15]),
        .O(DQOut[15]));
  (* SOFT_HLUTNM = "soft_lutpair1530" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[15]_i_1__63 
       (.I0(\dReg_reg[15] [575]),
        .I1(cal_DMOut_n[63]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[63]));
  (* SOFT_HLUTNM = "soft_lutpair1530" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[15]_i_1__64 
       (.I0(\dReg_reg[15] [567]),
        .I1(cal_DMOut_n[55]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[55]));
  (* SOFT_HLUTNM = "soft_lutpair1531" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[15]_i_1__65 
       (.I0(\dReg_reg[15] [559]),
        .I1(cal_DMOut_n[47]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[47]));
  (* SOFT_HLUTNM = "soft_lutpair1531" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[15]_i_1__66 
       (.I0(\dReg_reg[15] [551]),
        .I1(cal_DMOut_n[39]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[39]));
  (* SOFT_HLUTNM = "soft_lutpair1532" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[15]_i_1__67 
       (.I0(\dReg_reg[15] [543]),
        .I1(cal_DMOut_n[31]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[31]));
  (* SOFT_HLUTNM = "soft_lutpair1532" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[15]_i_1__68 
       (.I0(\dReg_reg[15] [535]),
        .I1(cal_DMOut_n[23]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[23]));
  (* SOFT_HLUTNM = "soft_lutpair1533" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[15]_i_1__69 
       (.I0(\dReg_reg[15] [527]),
        .I1(cal_DMOut_n[15]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[15]));
  (* SOFT_HLUTNM = "soft_lutpair1454" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__7 
       (.I0(\dReg_reg[15] [511]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[511]),
        .O(DQOut[511]));
  (* SOFT_HLUTNM = "soft_lutpair1533" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[15]_i_1__70 
       (.I0(\dReg_reg[15] [519]),
        .I1(cal_DMOut_n[7]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[7]));
  (* SOFT_HLUTNM = "soft_lutpair1455" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__8 
       (.I0(\dReg_reg[15] [510]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[503]),
        .O(DQOut[503]));
  (* SOFT_HLUTNM = "soft_lutpair1455" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_1__9 
       (.I0(\dReg_reg[15] [509]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[495]),
        .O(DQOut[495]));
  (* SOFT_HLUTNM = "soft_lutpair1510" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_2 
       (.I0(\dReg_reg[15] [504]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[455]),
        .O(DQOut[455]));
  (* SOFT_HLUTNM = "soft_lutpair1510" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_2__0 
       (.I0(\dReg_reg[15] [440]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[391]),
        .O(DQOut[391]));
  (* SOFT_HLUTNM = "soft_lutpair1511" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_2__1 
       (.I0(\dReg_reg[15] [376]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[327]),
        .O(DQOut[327]));
  (* SOFT_HLUTNM = "soft_lutpair1511" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_2__2 
       (.I0(\dReg_reg[15] [312]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[263]),
        .O(DQOut[263]));
  (* SOFT_HLUTNM = "soft_lutpair1512" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_2__3 
       (.I0(\dReg_reg[15] [248]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[199]),
        .O(DQOut[199]));
  (* SOFT_HLUTNM = "soft_lutpair1512" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_2__4 
       (.I0(\dReg_reg[15] [184]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[135]),
        .O(DQOut[135]));
  (* SOFT_HLUTNM = "soft_lutpair1513" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_2__5 
       (.I0(\dReg_reg[15] [120]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[71]),
        .O(DQOut[71]));
  (* SOFT_HLUTNM = "soft_lutpair1513" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[15]_i_2__6 
       (.I0(\dReg_reg[15] [56]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[7]),
        .O(DQOut[7]));
  (* SOFT_HLUTNM = "soft_lutpair1172" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2 
       (.I0(\dReg_reg[15] [455]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[504]),
        .O(DQOut[504]));
  (* SOFT_HLUTNM = "soft_lutpair1173" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__0 
       (.I0(\dReg_reg[15] [454]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[496]),
        .O(DQOut[496]));
  (* SOFT_HLUTNM = "soft_lutpair1174" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__1 
       (.I0(\dReg_reg[15] [453]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[488]),
        .O(DQOut[488]));
  (* SOFT_HLUTNM = "soft_lutpair1183" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__10 
       (.I0(\dReg_reg[15] [388]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[416]),
        .O(DQOut[416]));
  (* SOFT_HLUTNM = "soft_lutpair1184" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__11 
       (.I0(\dReg_reg[15] [387]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[408]),
        .O(DQOut[408]));
  (* SOFT_HLUTNM = "soft_lutpair1185" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__12 
       (.I0(\dReg_reg[15] [386]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[400]),
        .O(DQOut[400]));
  (* SOFT_HLUTNM = "soft_lutpair1186" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__13 
       (.I0(\dReg_reg[15] [385]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[392]),
        .O(DQOut[392]));
  (* SOFT_HLUTNM = "soft_lutpair1187" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__14 
       (.I0(\dReg_reg[15] [384]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[384]),
        .O(DQOut[384]));
  (* SOFT_HLUTNM = "soft_lutpair1188" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__15 
       (.I0(\dReg_reg[15] [327]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[376]),
        .O(DQOut[376]));
  (* SOFT_HLUTNM = "soft_lutpair1189" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__16 
       (.I0(\dReg_reg[15] [326]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[368]),
        .O(DQOut[368]));
  (* SOFT_HLUTNM = "soft_lutpair1190" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__17 
       (.I0(\dReg_reg[15] [325]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[360]),
        .O(DQOut[360]));
  (* SOFT_HLUTNM = "soft_lutpair1191" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__18 
       (.I0(\dReg_reg[15] [324]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[352]),
        .O(DQOut[352]));
  (* SOFT_HLUTNM = "soft_lutpair1192" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__19 
       (.I0(\dReg_reg[15] [323]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[344]),
        .O(DQOut[344]));
  (* SOFT_HLUTNM = "soft_lutpair1175" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__2 
       (.I0(\dReg_reg[15] [452]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[480]),
        .O(DQOut[480]));
  (* SOFT_HLUTNM = "soft_lutpair1193" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__20 
       (.I0(\dReg_reg[15] [322]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[336]),
        .O(DQOut[336]));
  (* SOFT_HLUTNM = "soft_lutpair1194" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__21 
       (.I0(\dReg_reg[15] [321]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[328]),
        .O(DQOut[328]));
  (* SOFT_HLUTNM = "soft_lutpair1195" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__22 
       (.I0(\dReg_reg[15] [320]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[320]),
        .O(DQOut[320]));
  (* SOFT_HLUTNM = "soft_lutpair1196" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__23 
       (.I0(\dReg_reg[15] [263]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[312]),
        .O(DQOut[312]));
  (* SOFT_HLUTNM = "soft_lutpair1197" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__24 
       (.I0(\dReg_reg[15] [262]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[304]),
        .O(DQOut[304]));
  (* SOFT_HLUTNM = "soft_lutpair1198" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__25 
       (.I0(\dReg_reg[15] [261]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[296]),
        .O(DQOut[296]));
  (* SOFT_HLUTNM = "soft_lutpair1199" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__26 
       (.I0(\dReg_reg[15] [260]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[288]),
        .O(DQOut[288]));
  (* SOFT_HLUTNM = "soft_lutpair1200" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__27 
       (.I0(\dReg_reg[15] [259]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[280]),
        .O(DQOut[280]));
  (* SOFT_HLUTNM = "soft_lutpair1201" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__28 
       (.I0(\dReg_reg[15] [258]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[272]),
        .O(DQOut[272]));
  (* SOFT_HLUTNM = "soft_lutpair1202" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__29 
       (.I0(\dReg_reg[15] [257]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[264]),
        .O(DQOut[264]));
  (* SOFT_HLUTNM = "soft_lutpair1176" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__3 
       (.I0(\dReg_reg[15] [451]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[472]),
        .O(DQOut[472]));
  (* SOFT_HLUTNM = "soft_lutpair1203" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__30 
       (.I0(\dReg_reg[15] [256]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[256]),
        .O(DQOut[256]));
  (* SOFT_HLUTNM = "soft_lutpair1204" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__31 
       (.I0(\dReg_reg[15] [199]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[248]),
        .O(DQOut[248]));
  (* SOFT_HLUTNM = "soft_lutpair1205" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__32 
       (.I0(\dReg_reg[15] [198]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[240]),
        .O(DQOut[240]));
  (* SOFT_HLUTNM = "soft_lutpair1206" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__33 
       (.I0(\dReg_reg[15] [197]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[232]),
        .O(DQOut[232]));
  (* SOFT_HLUTNM = "soft_lutpair1207" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__34 
       (.I0(\dReg_reg[15] [196]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[224]),
        .O(DQOut[224]));
  (* SOFT_HLUTNM = "soft_lutpair1208" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__35 
       (.I0(\dReg_reg[15] [195]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[216]),
        .O(DQOut[216]));
  (* SOFT_HLUTNM = "soft_lutpair1209" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__36 
       (.I0(\dReg_reg[15] [194]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[208]),
        .O(DQOut[208]));
  (* SOFT_HLUTNM = "soft_lutpair1210" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__37 
       (.I0(\dReg_reg[15] [193]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[200]),
        .O(DQOut[200]));
  (* SOFT_HLUTNM = "soft_lutpair1211" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__38 
       (.I0(\dReg_reg[15] [192]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[192]),
        .O(DQOut[192]));
  (* SOFT_HLUTNM = "soft_lutpair1212" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__39 
       (.I0(\dReg_reg[15] [135]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[184]),
        .O(DQOut[184]));
  (* SOFT_HLUTNM = "soft_lutpair1177" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__4 
       (.I0(\dReg_reg[15] [450]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[464]),
        .O(DQOut[464]));
  (* SOFT_HLUTNM = "soft_lutpair1213" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__40 
       (.I0(\dReg_reg[15] [134]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[176]),
        .O(DQOut[176]));
  (* SOFT_HLUTNM = "soft_lutpair1214" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__41 
       (.I0(\dReg_reg[15] [133]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[168]),
        .O(DQOut[168]));
  (* SOFT_HLUTNM = "soft_lutpair1215" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__42 
       (.I0(\dReg_reg[15] [132]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[160]),
        .O(DQOut[160]));
  (* SOFT_HLUTNM = "soft_lutpair1216" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__43 
       (.I0(\dReg_reg[15] [131]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[152]),
        .O(DQOut[152]));
  (* SOFT_HLUTNM = "soft_lutpair1217" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__44 
       (.I0(\dReg_reg[15] [130]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[144]),
        .O(DQOut[144]));
  (* SOFT_HLUTNM = "soft_lutpair1218" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__45 
       (.I0(\dReg_reg[15] [129]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[136]),
        .O(DQOut[136]));
  (* SOFT_HLUTNM = "soft_lutpair1219" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__46 
       (.I0(\dReg_reg[15] [128]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[128]),
        .O(DQOut[128]));
  (* SOFT_HLUTNM = "soft_lutpair1220" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__47 
       (.I0(\dReg_reg[15] [71]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[120]),
        .O(DQOut[120]));
  (* SOFT_HLUTNM = "soft_lutpair1221" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__48 
       (.I0(\dReg_reg[15] [70]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[112]),
        .O(DQOut[112]));
  (* SOFT_HLUTNM = "soft_lutpair1222" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__49 
       (.I0(\dReg_reg[15] [69]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[104]),
        .O(DQOut[104]));
  (* SOFT_HLUTNM = "soft_lutpair1178" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__5 
       (.I0(\dReg_reg[15] [449]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[456]),
        .O(DQOut[456]));
  (* SOFT_HLUTNM = "soft_lutpair1223" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__50 
       (.I0(\dReg_reg[15] [68]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[96]),
        .O(DQOut[96]));
  (* SOFT_HLUTNM = "soft_lutpair1224" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__51 
       (.I0(\dReg_reg[15] [67]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[88]),
        .O(DQOut[88]));
  (* SOFT_HLUTNM = "soft_lutpair1225" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__52 
       (.I0(\dReg_reg[15] [66]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[80]),
        .O(DQOut[80]));
  (* SOFT_HLUTNM = "soft_lutpair1226" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__53 
       (.I0(\dReg_reg[15] [65]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[72]),
        .O(DQOut[72]));
  (* SOFT_HLUTNM = "soft_lutpair1227" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__54 
       (.I0(\dReg_reg[15] [64]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[64]),
        .O(DQOut[64]));
  (* SOFT_HLUTNM = "soft_lutpair1228" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__55 
       (.I0(\dReg_reg[15] [7]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[56]),
        .O(DQOut[56]));
  (* SOFT_HLUTNM = "soft_lutpair1229" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__56 
       (.I0(\dReg_reg[15] [6]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[48]),
        .O(DQOut[48]));
  (* SOFT_HLUTNM = "soft_lutpair1230" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__57 
       (.I0(\dReg_reg[15] [5]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[40]),
        .O(DQOut[40]));
  (* SOFT_HLUTNM = "soft_lutpair1231" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__58 
       (.I0(\dReg_reg[15] [4]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[32]),
        .O(DQOut[32]));
  (* SOFT_HLUTNM = "soft_lutpair1232" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__59 
       (.I0(\dReg_reg[15] [3]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[24]),
        .O(DQOut[24]));
  (* SOFT_HLUTNM = "soft_lutpair1179" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__6 
       (.I0(\dReg_reg[15] [448]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[448]),
        .O(DQOut[448]));
  (* SOFT_HLUTNM = "soft_lutpair1233" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__60 
       (.I0(\dReg_reg[15] [2]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[16]),
        .O(DQOut[16]));
  (* SOFT_HLUTNM = "soft_lutpair1234" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__61 
       (.I0(\dReg_reg[15] [1]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[8]),
        .O(DQOut[8]));
  (* SOFT_HLUTNM = "soft_lutpair1235" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__62 
       (.I0(\dReg_reg[15] [0]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[0]),
        .O(DQOut[0]));
  (* SOFT_HLUTNM = "soft_lutpair1299" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[4]_i_2__63 
       (.I0(\dReg_reg[15] [568]),
        .I1(cal_DMOut_n[56]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[56]));
  (* SOFT_HLUTNM = "soft_lutpair1300" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[4]_i_2__64 
       (.I0(\dReg_reg[15] [560]),
        .I1(cal_DMOut_n[48]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[48]));
  (* SOFT_HLUTNM = "soft_lutpair1301" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[4]_i_2__65 
       (.I0(\dReg_reg[15] [552]),
        .I1(cal_DMOut_n[40]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[40]));
  (* SOFT_HLUTNM = "soft_lutpair1302" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[4]_i_2__66 
       (.I0(\dReg_reg[15] [544]),
        .I1(cal_DMOut_n[32]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[32]));
  (* SOFT_HLUTNM = "soft_lutpair1303" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[4]_i_2__67 
       (.I0(\dReg_reg[15] [536]),
        .I1(cal_DMOut_n[24]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[24]));
  (* SOFT_HLUTNM = "soft_lutpair1304" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[4]_i_2__68 
       (.I0(\dReg_reg[15] [528]),
        .I1(cal_DMOut_n[16]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[16]));
  (* SOFT_HLUTNM = "soft_lutpair1305" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[4]_i_2__69 
       (.I0(\dReg_reg[15] [520]),
        .I1(cal_DMOut_n[8]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[8]));
  (* SOFT_HLUTNM = "soft_lutpair1180" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__7 
       (.I0(\dReg_reg[15] [391]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[440]),
        .O(DQOut[440]));
  (* SOFT_HLUTNM = "soft_lutpair1306" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[4]_i_2__70 
       (.I0(\dReg_reg[15] [512]),
        .I1(cal_DMOut_n[0]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[0]));
  (* SOFT_HLUTNM = "soft_lutpair1181" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__8 
       (.I0(\dReg_reg[15] [390]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[432]),
        .O(DQOut[432]));
  (* SOFT_HLUTNM = "soft_lutpair1182" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[4]_i_2__9 
       (.I0(\dReg_reg[15] [389]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[424]),
        .O(DQOut[424]));
  (* SOFT_HLUTNM = "soft_lutpair1172" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2 
       (.I0(\dReg_reg[15] [463]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[505]),
        .O(DQOut[505]));
  (* SOFT_HLUTNM = "soft_lutpair1173" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__0 
       (.I0(\dReg_reg[15] [462]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[497]),
        .O(DQOut[497]));
  (* SOFT_HLUTNM = "soft_lutpair1174" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__1 
       (.I0(\dReg_reg[15] [461]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[489]),
        .O(DQOut[489]));
  (* SOFT_HLUTNM = "soft_lutpair1183" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__10 
       (.I0(\dReg_reg[15] [396]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[417]),
        .O(DQOut[417]));
  (* SOFT_HLUTNM = "soft_lutpair1184" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__11 
       (.I0(\dReg_reg[15] [395]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[409]),
        .O(DQOut[409]));
  (* SOFT_HLUTNM = "soft_lutpair1185" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__12 
       (.I0(\dReg_reg[15] [394]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[401]),
        .O(DQOut[401]));
  (* SOFT_HLUTNM = "soft_lutpair1186" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__13 
       (.I0(\dReg_reg[15] [393]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[393]),
        .O(DQOut[393]));
  (* SOFT_HLUTNM = "soft_lutpair1187" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__14 
       (.I0(\dReg_reg[15] [392]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[385]),
        .O(DQOut[385]));
  (* SOFT_HLUTNM = "soft_lutpair1188" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__15 
       (.I0(\dReg_reg[15] [335]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[377]),
        .O(DQOut[377]));
  (* SOFT_HLUTNM = "soft_lutpair1189" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__16 
       (.I0(\dReg_reg[15] [334]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[369]),
        .O(DQOut[369]));
  (* SOFT_HLUTNM = "soft_lutpair1190" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__17 
       (.I0(\dReg_reg[15] [333]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[361]),
        .O(DQOut[361]));
  (* SOFT_HLUTNM = "soft_lutpair1191" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__18 
       (.I0(\dReg_reg[15] [332]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[353]),
        .O(DQOut[353]));
  (* SOFT_HLUTNM = "soft_lutpair1192" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__19 
       (.I0(\dReg_reg[15] [331]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[345]),
        .O(DQOut[345]));
  (* SOFT_HLUTNM = "soft_lutpair1175" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__2 
       (.I0(\dReg_reg[15] [460]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[481]),
        .O(DQOut[481]));
  (* SOFT_HLUTNM = "soft_lutpair1193" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__20 
       (.I0(\dReg_reg[15] [330]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[337]),
        .O(DQOut[337]));
  (* SOFT_HLUTNM = "soft_lutpair1194" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__21 
       (.I0(\dReg_reg[15] [329]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[329]),
        .O(DQOut[329]));
  (* SOFT_HLUTNM = "soft_lutpair1195" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__22 
       (.I0(\dReg_reg[15] [328]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[321]),
        .O(DQOut[321]));
  (* SOFT_HLUTNM = "soft_lutpair1196" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__23 
       (.I0(\dReg_reg[15] [271]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[313]),
        .O(DQOut[313]));
  (* SOFT_HLUTNM = "soft_lutpair1197" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__24 
       (.I0(\dReg_reg[15] [270]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[305]),
        .O(DQOut[305]));
  (* SOFT_HLUTNM = "soft_lutpair1198" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__25 
       (.I0(\dReg_reg[15] [269]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[297]),
        .O(DQOut[297]));
  (* SOFT_HLUTNM = "soft_lutpair1199" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__26 
       (.I0(\dReg_reg[15] [268]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[289]),
        .O(DQOut[289]));
  (* SOFT_HLUTNM = "soft_lutpair1200" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__27 
       (.I0(\dReg_reg[15] [267]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[281]),
        .O(DQOut[281]));
  (* SOFT_HLUTNM = "soft_lutpair1201" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__28 
       (.I0(\dReg_reg[15] [266]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[273]),
        .O(DQOut[273]));
  (* SOFT_HLUTNM = "soft_lutpair1202" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__29 
       (.I0(\dReg_reg[15] [265]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[265]),
        .O(DQOut[265]));
  (* SOFT_HLUTNM = "soft_lutpair1176" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__3 
       (.I0(\dReg_reg[15] [459]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[473]),
        .O(DQOut[473]));
  (* SOFT_HLUTNM = "soft_lutpair1203" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__30 
       (.I0(\dReg_reg[15] [264]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[257]),
        .O(DQOut[257]));
  (* SOFT_HLUTNM = "soft_lutpair1204" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__31 
       (.I0(\dReg_reg[15] [207]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[249]),
        .O(DQOut[249]));
  (* SOFT_HLUTNM = "soft_lutpair1205" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__32 
       (.I0(\dReg_reg[15] [206]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[241]),
        .O(DQOut[241]));
  (* SOFT_HLUTNM = "soft_lutpair1206" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__33 
       (.I0(\dReg_reg[15] [205]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[233]),
        .O(DQOut[233]));
  (* SOFT_HLUTNM = "soft_lutpair1207" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__34 
       (.I0(\dReg_reg[15] [204]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[225]),
        .O(DQOut[225]));
  (* SOFT_HLUTNM = "soft_lutpair1208" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__35 
       (.I0(\dReg_reg[15] [203]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[217]),
        .O(DQOut[217]));
  (* SOFT_HLUTNM = "soft_lutpair1209" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__36 
       (.I0(\dReg_reg[15] [202]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[209]),
        .O(DQOut[209]));
  (* SOFT_HLUTNM = "soft_lutpair1210" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__37 
       (.I0(\dReg_reg[15] [201]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[201]),
        .O(DQOut[201]));
  (* SOFT_HLUTNM = "soft_lutpair1211" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__38 
       (.I0(\dReg_reg[15] [200]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[193]),
        .O(DQOut[193]));
  (* SOFT_HLUTNM = "soft_lutpair1212" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__39 
       (.I0(\dReg_reg[15] [143]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[185]),
        .O(DQOut[185]));
  (* SOFT_HLUTNM = "soft_lutpair1177" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__4 
       (.I0(\dReg_reg[15] [458]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[465]),
        .O(DQOut[465]));
  (* SOFT_HLUTNM = "soft_lutpair1213" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__40 
       (.I0(\dReg_reg[15] [142]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[177]),
        .O(DQOut[177]));
  (* SOFT_HLUTNM = "soft_lutpair1214" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__41 
       (.I0(\dReg_reg[15] [141]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[169]),
        .O(DQOut[169]));
  (* SOFT_HLUTNM = "soft_lutpair1215" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__42 
       (.I0(\dReg_reg[15] [140]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[161]),
        .O(DQOut[161]));
  (* SOFT_HLUTNM = "soft_lutpair1216" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__43 
       (.I0(\dReg_reg[15] [139]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[153]),
        .O(DQOut[153]));
  (* SOFT_HLUTNM = "soft_lutpair1217" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__44 
       (.I0(\dReg_reg[15] [138]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[145]),
        .O(DQOut[145]));
  (* SOFT_HLUTNM = "soft_lutpair1218" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__45 
       (.I0(\dReg_reg[15] [137]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[137]),
        .O(DQOut[137]));
  (* SOFT_HLUTNM = "soft_lutpair1219" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__46 
       (.I0(\dReg_reg[15] [136]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[129]),
        .O(DQOut[129]));
  (* SOFT_HLUTNM = "soft_lutpair1220" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__47 
       (.I0(\dReg_reg[15] [79]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[121]),
        .O(DQOut[121]));
  (* SOFT_HLUTNM = "soft_lutpair1221" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__48 
       (.I0(\dReg_reg[15] [78]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[113]),
        .O(DQOut[113]));
  (* SOFT_HLUTNM = "soft_lutpair1222" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__49 
       (.I0(\dReg_reg[15] [77]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[105]),
        .O(DQOut[105]));
  (* SOFT_HLUTNM = "soft_lutpair1178" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__5 
       (.I0(\dReg_reg[15] [457]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[457]),
        .O(DQOut[457]));
  (* SOFT_HLUTNM = "soft_lutpair1223" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__50 
       (.I0(\dReg_reg[15] [76]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[97]),
        .O(DQOut[97]));
  (* SOFT_HLUTNM = "soft_lutpair1224" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__51 
       (.I0(\dReg_reg[15] [75]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[89]),
        .O(DQOut[89]));
  (* SOFT_HLUTNM = "soft_lutpair1225" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__52 
       (.I0(\dReg_reg[15] [74]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[81]),
        .O(DQOut[81]));
  (* SOFT_HLUTNM = "soft_lutpair1226" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__53 
       (.I0(\dReg_reg[15] [73]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[73]),
        .O(DQOut[73]));
  (* SOFT_HLUTNM = "soft_lutpair1227" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__54 
       (.I0(\dReg_reg[15] [72]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[65]),
        .O(DQOut[65]));
  (* SOFT_HLUTNM = "soft_lutpair1228" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__55 
       (.I0(\dReg_reg[15] [15]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[57]),
        .O(DQOut[57]));
  (* SOFT_HLUTNM = "soft_lutpair1229" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__56 
       (.I0(\dReg_reg[15] [14]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[49]),
        .O(DQOut[49]));
  (* SOFT_HLUTNM = "soft_lutpair1230" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__57 
       (.I0(\dReg_reg[15] [13]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[41]),
        .O(DQOut[41]));
  (* SOFT_HLUTNM = "soft_lutpair1231" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__58 
       (.I0(\dReg_reg[15] [12]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[33]),
        .O(DQOut[33]));
  (* SOFT_HLUTNM = "soft_lutpair1232" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__59 
       (.I0(\dReg_reg[15] [11]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[25]),
        .O(DQOut[25]));
  (* SOFT_HLUTNM = "soft_lutpair1179" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__6 
       (.I0(\dReg_reg[15] [456]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[449]),
        .O(DQOut[449]));
  (* SOFT_HLUTNM = "soft_lutpair1233" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__60 
       (.I0(\dReg_reg[15] [10]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[17]),
        .O(DQOut[17]));
  (* SOFT_HLUTNM = "soft_lutpair1234" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__61 
       (.I0(\dReg_reg[15] [9]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[9]),
        .O(DQOut[9]));
  (* SOFT_HLUTNM = "soft_lutpair1235" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__62 
       (.I0(\dReg_reg[15] [8]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[1]),
        .O(DQOut[1]));
  (* SOFT_HLUTNM = "soft_lutpair1299" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[5]_i_2__63 
       (.I0(\dReg_reg[15] [569]),
        .I1(cal_DMOut_n[57]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[57]));
  (* SOFT_HLUTNM = "soft_lutpair1300" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[5]_i_2__64 
       (.I0(\dReg_reg[15] [561]),
        .I1(cal_DMOut_n[49]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[49]));
  (* SOFT_HLUTNM = "soft_lutpair1301" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[5]_i_2__65 
       (.I0(\dReg_reg[15] [553]),
        .I1(cal_DMOut_n[41]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[41]));
  (* SOFT_HLUTNM = "soft_lutpair1302" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[5]_i_2__66 
       (.I0(\dReg_reg[15] [545]),
        .I1(cal_DMOut_n[33]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[33]));
  (* SOFT_HLUTNM = "soft_lutpair1303" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[5]_i_2__67 
       (.I0(\dReg_reg[15] [537]),
        .I1(cal_DMOut_n[25]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[25]));
  (* SOFT_HLUTNM = "soft_lutpair1304" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[5]_i_2__68 
       (.I0(\dReg_reg[15] [529]),
        .I1(cal_DMOut_n[17]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[17]));
  (* SOFT_HLUTNM = "soft_lutpair1305" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[5]_i_2__69 
       (.I0(\dReg_reg[15] [521]),
        .I1(cal_DMOut_n[9]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[9]));
  (* SOFT_HLUTNM = "soft_lutpair1180" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__7 
       (.I0(\dReg_reg[15] [399]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[441]),
        .O(DQOut[441]));
  (* SOFT_HLUTNM = "soft_lutpair1306" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[5]_i_2__70 
       (.I0(\dReg_reg[15] [513]),
        .I1(cal_DMOut_n[1]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[1]));
  (* SOFT_HLUTNM = "soft_lutpair1181" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__8 
       (.I0(\dReg_reg[15] [398]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[433]),
        .O(DQOut[433]));
  (* SOFT_HLUTNM = "soft_lutpair1182" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[5]_i_2__9 
       (.I0(\dReg_reg[15] [397]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[425]),
        .O(DQOut[425]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1 
       (.I0(DQOut[2]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[6]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2 ),
        .O(\wosp_reg[2]_rep [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__0 
       (.I0(DMOut[2]),
        .I1(\dReg_reg[11] ),
        .I2(DMOut[6]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__1_0 ),
        .O(\wosp_reg[2]_rep__1 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__1 
       (.I0(DQOut[58]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[62]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__1_3 ),
        .O(\wosp_reg[2]_rep__1_2 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__10 
       (.I0(DQOut[122]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[126]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_15 ),
        .O(\wosp_reg[2]_rep__2_14 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__11 
       (.I0(DQOut[114]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[118]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_18 ),
        .O(\wosp_reg[2]_rep__2_17 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__12 
       (.I0(DQOut[106]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[110]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_21 ),
        .O(\wosp_reg[2]_rep__2_20 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__13 
       (.I0(DQOut[98]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[102]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_24 ),
        .O(\wosp_reg[2]_rep__2_23 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__14 
       (.I0(DQOut[90]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[94]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_27 ),
        .O(\wosp_reg[2]_rep__2_26 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__15 
       (.I0(DQOut[82]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[86]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_30 ),
        .O(\wosp_reg[2]_rep__2_29 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__16 
       (.I0(DQOut[74]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[78]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_33 ),
        .O(\wosp_reg[2]_rep__2_32 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__17 
       (.I0(DQOut[130]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[134]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_0 ),
        .O(\wosp_reg[2]_rep_3 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__18 
       (.I0(DMOut[18]),
        .I1(\dReg_reg[10] ),
        .I2(DMOut[22]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_2 ),
        .O(\wosp_reg[2]_rep__3_1 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__19 
       (.I0(DQOut[186]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[190]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_5 ),
        .O(\wosp_reg[2]_rep__3_4 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__2 
       (.I0(DQOut[50]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[54]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__1_6 ),
        .O(\wosp_reg[2]_rep__1_5 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__20 
       (.I0(DQOut[178]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[182]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_8 ),
        .O(\wosp_reg[2]_rep__3_7 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__21 
       (.I0(DQOut[170]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[174]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_11 ),
        .O(\wosp_reg[2]_rep__3_10 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__22 
       (.I0(DQOut[162]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[166]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_14 ),
        .O(\wosp_reg[2]_rep__3_13 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__23 
       (.I0(DQOut[154]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[158]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_17 ),
        .O(\wosp_reg[2]_rep__3_16 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__24 
       (.I0(DQOut[146]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[150]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_20 ),
        .O(\wosp_reg[2]_rep__3_19 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__25 
       (.I0(DQOut[138]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[142]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_23 ),
        .O(\wosp_reg[2]_rep__3_22 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__26 
       (.I0(DQOut[194]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[198]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4 ),
        .O(\wosp_reg[2]_rep__0 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__27 
       (.I0(DMOut[26]),
        .I1(\dReg_reg[10] ),
        .I2(DMOut[30]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_26 ),
        .O(\wosp_reg[2]_rep__3_25 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__28 
       (.I0(DQOut[250]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[254]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_29 ),
        .O(\wosp_reg[2]_rep__3_28 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__29 
       (.I0(DQOut[242]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[246]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_32 ),
        .O(\wosp_reg[2]_rep__3_31 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__3 
       (.I0(DQOut[42]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[46]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__1_9 ),
        .O(\wosp_reg[2]_rep__1_8 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__30 
       (.I0(DQOut[234]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[238]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_1 ),
        .O(\wosp_reg[2]_rep__4_0 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__31 
       (.I0(DQOut[226]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[230]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_4 ),
        .O(\wosp_reg[2]_rep__4_3 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__32 
       (.I0(DQOut[218]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[222]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_7 ),
        .O(\wosp_reg[2]_rep__4_6 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__33 
       (.I0(DQOut[210]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[214]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_10 ),
        .O(\wosp_reg[2]_rep__4_9 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__34 
       (.I0(DQOut[202]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[206]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_13 ),
        .O(\wosp_reg[2]_rep__4_12 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__35 
       (.I0(DQOut[258]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[262]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5 ),
        .O(\wosp_reg[2]_rep__0_1 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__36 
       (.I0(DMOut[34]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DMOut[38]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_16 ),
        .O(\wosp_reg[2]_rep__4_15 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__37 
       (.I0(DQOut[314]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[318]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_19 ),
        .O(\wosp_reg[2]_rep__4_18 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__38 
       (.I0(DQOut[306]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[310]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_22 ),
        .O(\wosp_reg[2]_rep__4_21 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__39 
       (.I0(DQOut[298]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[302]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_25 ),
        .O(\wosp_reg[2]_rep__4_24 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__4 
       (.I0(DQOut[34]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[38]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__1_11 ),
        .O(\wosp_reg[2]_rep__2_0 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__40 
       (.I0(DQOut[290]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[294]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_28 ),
        .O(\wosp_reg[2]_rep__4_27 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__41 
       (.I0(DQOut[282]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[286]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_31 ),
        .O(\wosp_reg[2]_rep__4_30 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__42 
       (.I0(DQOut[274]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[278]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_33 ),
        .O(\wosp_reg[2]_rep__5_0 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__43 
       (.I0(DQOut[266]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[270]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_3 ),
        .O(\wosp_reg[2]_rep__5_2 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__44 
       (.I0(DQOut[322]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[326]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_5 ),
        .O(\wosp_reg[2]_rep__0_3 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__45 
       (.I0(DMOut[42]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DMOut[46]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_7 ),
        .O(\wosp_reg[2]_rep__5_6 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__46 
       (.I0(DQOut[378]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[382]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_10 ),
        .O(\wosp_reg[2]_rep__5_9 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__47 
       (.I0(DQOut[370]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[374]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_13 ),
        .O(\wosp_reg[2]_rep__5_12 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__48 
       (.I0(DQOut[362]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[366]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_16 ),
        .O(\wosp_reg[2]_rep__5_15 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__49 
       (.I0(DQOut[354]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[358]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_19 ),
        .O(\wosp_reg[2]_rep__5_18 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__5 
       (.I0(DQOut[26]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[30]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_3 ),
        .O(\wosp_reg[2]_rep__2_2 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__50 
       (.I0(DQOut[346]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[350]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_22 ),
        .O(\wosp_reg[2]_rep__5_21 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__51 
       (.I0(DQOut[338]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[342]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_25 ),
        .O(\wosp_reg[2]_rep__5_24 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__52 
       (.I0(DQOut[330]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[334]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_28 ),
        .O(\wosp_reg[2]_rep__5_27 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__53 
       (.I0(DQOut[386]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[390]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6 ),
        .O(\wosp_reg[2]_rep__1_12 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__54 
       (.I0(DMOut[50]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DMOut[54]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_31 ),
        .O(\wosp_reg[2]_rep__5_30 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__55 
       (.I0(DQOut[442]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[446]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_33 ),
        .O(\wosp_reg[2]_rep__6_0 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__56 
       (.I0(DQOut[434]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[438]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_3 ),
        .O(\wosp_reg[2]_rep__6_2 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__57 
       (.I0(DQOut[426]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[430]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_6 ),
        .O(\wosp_reg[2]_rep__6_5 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__58 
       (.I0(DQOut[418]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[422]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_9 ),
        .O(\wosp_reg[2]_rep__6_8 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__59 
       (.I0(DQOut[410]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[414]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_12 ),
        .O(\wosp_reg[2]_rep__6_11 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__6 
       (.I0(DQOut[18]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[22]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_6 ),
        .O(\wosp_reg[2]_rep__2_5 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__60 
       (.I0(DQOut[402]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[406]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_15 ),
        .O(\wosp_reg[2]_rep__6_14 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__61 
       (.I0(DQOut[394]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[398]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_18 ),
        .O(\wosp_reg[2]_rep__6_17 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__62 
       (.I0(DQOut[450]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[454]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_20 ),
        .O(\wosp_reg[2] [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__63 
       (.I0(DMOut[58]),
        .I1(\dReg_reg[8]_0 ),
        .I2(DMOut[62]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__7_0 ),
        .O(\wosp_reg[2]_rep__7 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__64 
       (.I0(DQOut[506]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[510]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_23 ),
        .O(\wosp_reg[2]_rep__6_22 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__65 
       (.I0(DQOut[498]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[502]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_26 ),
        .O(\wosp_reg[2]_rep__6_25 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__66 
       (.I0(DQOut[490]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[494]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_29 ),
        .O(\wosp_reg[2]_rep__6_28 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__67 
       (.I0(DQOut[482]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[486]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_32 ),
        .O(\wosp_reg[2]_rep__6_31 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__68 
       (.I0(DQOut[474]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[478]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_35 ),
        .O(\wosp_reg[2]_rep__6_34 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__69 
       (.I0(DQOut[466]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[470]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_38 ),
        .O(\wosp_reg[2]_rep__6_37 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__7 
       (.I0(DQOut[10]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[14]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_9 ),
        .O(\wosp_reg[2]_rep__2_8 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__70 
       (.I0(DQOut[458]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[462]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_41 ),
        .O(\wosp_reg[2]_rep__6_40 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__8 
       (.I0(DQOut[66]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[70]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3 ),
        .O(\wosp_reg[2]_rep_1 [0]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[8]_i_1__9 
       (.I0(DMOut[10]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DMOut[14]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_12 ),
        .O(\wosp_reg[2]_rep__2_11 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1390" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2 
       (.I0(\dReg_reg[15] [471]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[506]),
        .O(DQOut[506]));
  (* SOFT_HLUTNM = "soft_lutpair1391" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__0 
       (.I0(\dReg_reg[15] [470]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[498]),
        .O(DQOut[498]));
  (* SOFT_HLUTNM = "soft_lutpair1392" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__1 
       (.I0(\dReg_reg[15] [469]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[490]),
        .O(DQOut[490]));
  (* SOFT_HLUTNM = "soft_lutpair1401" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__10 
       (.I0(\dReg_reg[15] [404]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[418]),
        .O(DQOut[418]));
  (* SOFT_HLUTNM = "soft_lutpair1402" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__11 
       (.I0(\dReg_reg[15] [403]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[410]),
        .O(DQOut[410]));
  (* SOFT_HLUTNM = "soft_lutpair1403" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__12 
       (.I0(\dReg_reg[15] [402]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[402]),
        .O(DQOut[402]));
  (* SOFT_HLUTNM = "soft_lutpair1404" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__13 
       (.I0(\dReg_reg[15] [401]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[394]),
        .O(DQOut[394]));
  (* SOFT_HLUTNM = "soft_lutpair1405" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__14 
       (.I0(\dReg_reg[15] [400]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[386]),
        .O(DQOut[386]));
  (* SOFT_HLUTNM = "soft_lutpair1406" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__15 
       (.I0(\dReg_reg[15] [343]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[378]),
        .O(DQOut[378]));
  (* SOFT_HLUTNM = "soft_lutpair1407" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__16 
       (.I0(\dReg_reg[15] [342]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[370]),
        .O(DQOut[370]));
  (* SOFT_HLUTNM = "soft_lutpair1408" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__17 
       (.I0(\dReg_reg[15] [341]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[362]),
        .O(DQOut[362]));
  (* SOFT_HLUTNM = "soft_lutpair1409" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__18 
       (.I0(\dReg_reg[15] [340]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[354]),
        .O(DQOut[354]));
  (* SOFT_HLUTNM = "soft_lutpair1410" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__19 
       (.I0(\dReg_reg[15] [339]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[346]),
        .O(DQOut[346]));
  (* SOFT_HLUTNM = "soft_lutpair1393" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__2 
       (.I0(\dReg_reg[15] [468]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[482]),
        .O(DQOut[482]));
  (* SOFT_HLUTNM = "soft_lutpair1411" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__20 
       (.I0(\dReg_reg[15] [338]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[338]),
        .O(DQOut[338]));
  (* SOFT_HLUTNM = "soft_lutpair1412" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__21 
       (.I0(\dReg_reg[15] [337]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[330]),
        .O(DQOut[330]));
  (* SOFT_HLUTNM = "soft_lutpair1413" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__22 
       (.I0(\dReg_reg[15] [336]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[322]),
        .O(DQOut[322]));
  (* SOFT_HLUTNM = "soft_lutpair1414" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__23 
       (.I0(\dReg_reg[15] [279]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[314]),
        .O(DQOut[314]));
  (* SOFT_HLUTNM = "soft_lutpair1415" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__24 
       (.I0(\dReg_reg[15] [278]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[306]),
        .O(DQOut[306]));
  (* SOFT_HLUTNM = "soft_lutpair1416" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__25 
       (.I0(\dReg_reg[15] [277]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[298]),
        .O(DQOut[298]));
  (* SOFT_HLUTNM = "soft_lutpair1417" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__26 
       (.I0(\dReg_reg[15] [276]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[290]),
        .O(DQOut[290]));
  (* SOFT_HLUTNM = "soft_lutpair1418" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__27 
       (.I0(\dReg_reg[15] [275]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[282]),
        .O(DQOut[282]));
  (* SOFT_HLUTNM = "soft_lutpair1419" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__28 
       (.I0(\dReg_reg[15] [274]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[274]),
        .O(DQOut[274]));
  (* SOFT_HLUTNM = "soft_lutpair1420" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__29 
       (.I0(\dReg_reg[15] [273]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[266]),
        .O(DQOut[266]));
  (* SOFT_HLUTNM = "soft_lutpair1394" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__3 
       (.I0(\dReg_reg[15] [467]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[474]),
        .O(DQOut[474]));
  (* SOFT_HLUTNM = "soft_lutpair1421" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__30 
       (.I0(\dReg_reg[15] [272]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[258]),
        .O(DQOut[258]));
  (* SOFT_HLUTNM = "soft_lutpair1422" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__31 
       (.I0(\dReg_reg[15] [215]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[250]),
        .O(DQOut[250]));
  (* SOFT_HLUTNM = "soft_lutpair1423" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__32 
       (.I0(\dReg_reg[15] [214]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[242]),
        .O(DQOut[242]));
  (* SOFT_HLUTNM = "soft_lutpair1424" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__33 
       (.I0(\dReg_reg[15] [213]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[234]),
        .O(DQOut[234]));
  (* SOFT_HLUTNM = "soft_lutpair1425" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__34 
       (.I0(\dReg_reg[15] [212]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[226]),
        .O(DQOut[226]));
  (* SOFT_HLUTNM = "soft_lutpair1426" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__35 
       (.I0(\dReg_reg[15] [211]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[218]),
        .O(DQOut[218]));
  (* SOFT_HLUTNM = "soft_lutpair1427" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__36 
       (.I0(\dReg_reg[15] [210]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[210]),
        .O(DQOut[210]));
  (* SOFT_HLUTNM = "soft_lutpair1428" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__37 
       (.I0(\dReg_reg[15] [209]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[202]),
        .O(DQOut[202]));
  (* SOFT_HLUTNM = "soft_lutpair1429" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__38 
       (.I0(\dReg_reg[15] [208]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[194]),
        .O(DQOut[194]));
  (* SOFT_HLUTNM = "soft_lutpair1430" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__39 
       (.I0(\dReg_reg[15] [151]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[186]),
        .O(DQOut[186]));
  (* SOFT_HLUTNM = "soft_lutpair1395" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__4 
       (.I0(\dReg_reg[15] [466]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[466]),
        .O(DQOut[466]));
  (* SOFT_HLUTNM = "soft_lutpair1431" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__40 
       (.I0(\dReg_reg[15] [150]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[178]),
        .O(DQOut[178]));
  (* SOFT_HLUTNM = "soft_lutpair1432" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__41 
       (.I0(\dReg_reg[15] [149]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[170]),
        .O(DQOut[170]));
  (* SOFT_HLUTNM = "soft_lutpair1433" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__42 
       (.I0(\dReg_reg[15] [148]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[162]),
        .O(DQOut[162]));
  (* SOFT_HLUTNM = "soft_lutpair1434" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__43 
       (.I0(\dReg_reg[15] [147]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[154]),
        .O(DQOut[154]));
  (* SOFT_HLUTNM = "soft_lutpair1435" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__44 
       (.I0(\dReg_reg[15] [146]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[146]),
        .O(DQOut[146]));
  (* SOFT_HLUTNM = "soft_lutpair1436" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__45 
       (.I0(\dReg_reg[15] [145]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[138]),
        .O(DQOut[138]));
  (* SOFT_HLUTNM = "soft_lutpair1437" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__46 
       (.I0(\dReg_reg[15] [144]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[130]),
        .O(DQOut[130]));
  (* SOFT_HLUTNM = "soft_lutpair1438" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__47 
       (.I0(\dReg_reg[15] [87]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[122]),
        .O(DQOut[122]));
  (* SOFT_HLUTNM = "soft_lutpair1439" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__48 
       (.I0(\dReg_reg[15] [86]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[114]),
        .O(DQOut[114]));
  (* SOFT_HLUTNM = "soft_lutpair1440" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__49 
       (.I0(\dReg_reg[15] [85]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[106]),
        .O(DQOut[106]));
  (* SOFT_HLUTNM = "soft_lutpair1396" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__5 
       (.I0(\dReg_reg[15] [465]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[458]),
        .O(DQOut[458]));
  (* SOFT_HLUTNM = "soft_lutpair1441" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__50 
       (.I0(\dReg_reg[15] [84]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[98]),
        .O(DQOut[98]));
  (* SOFT_HLUTNM = "soft_lutpair1442" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__51 
       (.I0(\dReg_reg[15] [83]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[90]),
        .O(DQOut[90]));
  (* SOFT_HLUTNM = "soft_lutpair1443" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__52 
       (.I0(\dReg_reg[15] [82]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[82]),
        .O(DQOut[82]));
  (* SOFT_HLUTNM = "soft_lutpair1444" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__53 
       (.I0(\dReg_reg[15] [81]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[74]),
        .O(DQOut[74]));
  (* SOFT_HLUTNM = "soft_lutpair1445" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__54 
       (.I0(\dReg_reg[15] [80]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[66]),
        .O(DQOut[66]));
  (* SOFT_HLUTNM = "soft_lutpair1446" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__55 
       (.I0(\dReg_reg[15] [23]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[58]),
        .O(DQOut[58]));
  (* SOFT_HLUTNM = "soft_lutpair1447" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__56 
       (.I0(\dReg_reg[15] [22]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[50]),
        .O(DQOut[50]));
  (* SOFT_HLUTNM = "soft_lutpair1448" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__57 
       (.I0(\dReg_reg[15] [21]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[42]),
        .O(DQOut[42]));
  (* SOFT_HLUTNM = "soft_lutpair1449" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__58 
       (.I0(\dReg_reg[15] [20]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[34]),
        .O(DQOut[34]));
  (* SOFT_HLUTNM = "soft_lutpair1450" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__59 
       (.I0(\dReg_reg[15] [19]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[26]),
        .O(DQOut[26]));
  (* SOFT_HLUTNM = "soft_lutpair1397" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__6 
       (.I0(\dReg_reg[15] [464]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[450]),
        .O(DQOut[450]));
  (* SOFT_HLUTNM = "soft_lutpair1451" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__60 
       (.I0(\dReg_reg[15] [18]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[18]),
        .O(DQOut[18]));
  (* SOFT_HLUTNM = "soft_lutpair1452" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__61 
       (.I0(\dReg_reg[15] [17]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[10]),
        .O(DQOut[10]));
  (* SOFT_HLUTNM = "soft_lutpair1453" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__62 
       (.I0(\dReg_reg[15] [16]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[2]),
        .O(DQOut[2]));
  (* SOFT_HLUTNM = "soft_lutpair1498" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[8]_i_2__63 
       (.I0(\dReg_reg[15] [570]),
        .I1(cal_DMOut_n[58]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[58]));
  (* SOFT_HLUTNM = "soft_lutpair1499" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[8]_i_2__64 
       (.I0(\dReg_reg[15] [562]),
        .I1(cal_DMOut_n[50]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[50]));
  (* SOFT_HLUTNM = "soft_lutpair1500" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[8]_i_2__65 
       (.I0(\dReg_reg[15] [554]),
        .I1(cal_DMOut_n[42]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[42]));
  (* SOFT_HLUTNM = "soft_lutpair1501" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[8]_i_2__66 
       (.I0(\dReg_reg[15] [546]),
        .I1(cal_DMOut_n[34]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[34]));
  (* SOFT_HLUTNM = "soft_lutpair1502" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[8]_i_2__67 
       (.I0(\dReg_reg[15] [538]),
        .I1(cal_DMOut_n[26]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[26]));
  (* SOFT_HLUTNM = "soft_lutpair1503" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[8]_i_2__68 
       (.I0(\dReg_reg[15] [530]),
        .I1(cal_DMOut_n[18]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[18]));
  (* SOFT_HLUTNM = "soft_lutpair1504" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[8]_i_2__69 
       (.I0(\dReg_reg[15] [522]),
        .I1(cal_DMOut_n[10]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[10]));
  (* SOFT_HLUTNM = "soft_lutpair1398" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__7 
       (.I0(\dReg_reg[15] [407]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[442]),
        .O(DQOut[442]));
  (* SOFT_HLUTNM = "soft_lutpair1505" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[8]_i_2__70 
       (.I0(\dReg_reg[15] [514]),
        .I1(cal_DMOut_n[2]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[2]));
  (* SOFT_HLUTNM = "soft_lutpair1399" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__8 
       (.I0(\dReg_reg[15] [406]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[434]),
        .O(DQOut[434]));
  (* SOFT_HLUTNM = "soft_lutpair1400" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_2__9 
       (.I0(\dReg_reg[15] [405]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[426]),
        .O(DQOut[426]));
  (* SOFT_HLUTNM = "soft_lutpair1237" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3 
       (.I0(DQOut[0]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[4]),
        .O(\wosp_reg[2]_rep__2 ));
  (* SOFT_HLUTNM = "soft_lutpair1238" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__0 
       (.I0(DQOut[8]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[12]),
        .O(\wosp_reg[2]_rep__2_9 ));
  (* SOFT_HLUTNM = "soft_lutpair1239" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__1 
       (.I0(DQOut[16]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[20]),
        .O(\wosp_reg[2]_rep__2_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1247" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__10 
       (.I0(DQOut[80]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[84]),
        .O(\wosp_reg[2]_rep__2_30 ));
  (* SOFT_HLUTNM = "soft_lutpair1248" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__11 
       (.I0(DQOut[88]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[92]),
        .O(\wosp_reg[2]_rep__2_27 ));
  (* SOFT_HLUTNM = "soft_lutpair1249" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__12 
       (.I0(DQOut[96]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[100]),
        .O(\wosp_reg[2]_rep__2_24 ));
  (* SOFT_HLUTNM = "soft_lutpair1250" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__13 
       (.I0(DQOut[104]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[108]),
        .O(\wosp_reg[2]_rep__2_21 ));
  (* SOFT_HLUTNM = "soft_lutpair1251" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__14 
       (.I0(DQOut[112]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[116]),
        .O(\wosp_reg[2]_rep__2_18 ));
  (* SOFT_HLUTNM = "soft_lutpair1252" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__15 
       (.I0(DQOut[120]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[124]),
        .O(\wosp_reg[2]_rep__2_15 ));
  (* SOFT_HLUTNM = "soft_lutpair1308" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__16 
       (.I0(DMOut[8]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DMOut[12]),
        .O(\wosp_reg[2]_rep__2_12 ));
  (* SOFT_HLUTNM = "soft_lutpair1245" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__17 
       (.I0(DQOut[128]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[132]),
        .O(\wosp_reg[2]_rep__3_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1253" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__18 
       (.I0(DQOut[136]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[140]),
        .O(\wosp_reg[2]_rep__3_23 ));
  (* SOFT_HLUTNM = "soft_lutpair1254" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__19 
       (.I0(DQOut[144]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[148]),
        .O(\wosp_reg[2]_rep__3_20 ));
  (* SOFT_HLUTNM = "soft_lutpair1240" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__2 
       (.I0(DQOut[24]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[28]),
        .O(\wosp_reg[2]_rep__2_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1255" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__20 
       (.I0(DQOut[152]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[156]),
        .O(\wosp_reg[2]_rep__3_17 ));
  (* SOFT_HLUTNM = "soft_lutpair1256" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__21 
       (.I0(DQOut[160]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[164]),
        .O(\wosp_reg[2]_rep__3_14 ));
  (* SOFT_HLUTNM = "soft_lutpair1257" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__22 
       (.I0(DQOut[168]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[172]),
        .O(\wosp_reg[2]_rep__3_11 ));
  (* SOFT_HLUTNM = "soft_lutpair1258" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__23 
       (.I0(DQOut[176]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[180]),
        .O(\wosp_reg[2]_rep__3_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1259" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__24 
       (.I0(DQOut[184]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[188]),
        .O(\wosp_reg[2]_rep__3_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1309" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__25 
       (.I0(DMOut[16]),
        .I1(\dReg_reg[10] ),
        .I2(DMOut[20]),
        .O(\wosp_reg[2]_rep__3_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1261" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__26 
       (.I0(DQOut[192]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[196]),
        .O(\wosp_reg[2]_rep__4 ));
  (* SOFT_HLUTNM = "soft_lutpair1262" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__27 
       (.I0(DQOut[200]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[204]),
        .O(\wosp_reg[2]_rep__4_13 ));
  (* SOFT_HLUTNM = "soft_lutpair1263" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__28 
       (.I0(DQOut[208]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[212]),
        .O(\wosp_reg[2]_rep__4_10 ));
  (* SOFT_HLUTNM = "soft_lutpair1264" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__29 
       (.I0(DQOut[216]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[220]),
        .O(\wosp_reg[2]_rep__4_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1241" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__3 
       (.I0(DQOut[32]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[36]),
        .O(\wosp_reg[2]_rep__1_11 ));
  (* SOFT_HLUTNM = "soft_lutpair1265" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__30 
       (.I0(DQOut[224]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[228]),
        .O(\wosp_reg[2]_rep__4_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1266" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__31 
       (.I0(DQOut[232]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[236]),
        .O(\wosp_reg[2]_rep__4_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1267" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__32 
       (.I0(DQOut[240]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[244]),
        .O(\wosp_reg[2]_rep__3_32 ));
  (* SOFT_HLUTNM = "soft_lutpair1268" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__33 
       (.I0(DQOut[248]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[252]),
        .O(\wosp_reg[2]_rep__3_29 ));
  (* SOFT_HLUTNM = "soft_lutpair1310" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__34 
       (.I0(DMOut[24]),
        .I1(\dReg_reg[10] ),
        .I2(DMOut[28]),
        .O(\wosp_reg[2]_rep__3_26 ));
  (* SOFT_HLUTNM = "soft_lutpair1269" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__35 
       (.I0(DQOut[256]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[260]),
        .O(\wosp_reg[2]_rep__5 ));
  (* SOFT_HLUTNM = "soft_lutpair1270" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__36 
       (.I0(DQOut[264]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[268]),
        .O(\wosp_reg[2]_rep__5_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1266" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__37 
       (.I0(DQOut[272]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[276]),
        .O(\wosp_reg[2]_rep__4_33 ));
  (* SOFT_HLUTNM = "soft_lutpair1271" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__38 
       (.I0(DQOut[280]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[284]),
        .O(\wosp_reg[2]_rep__4_31 ));
  (* SOFT_HLUTNM = "soft_lutpair1272" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__39 
       (.I0(DQOut[288]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[292]),
        .O(\wosp_reg[2]_rep__4_28 ));
  (* SOFT_HLUTNM = "soft_lutpair1242" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__4 
       (.I0(DQOut[40]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[44]),
        .O(\wosp_reg[2]_rep__1_9 ));
  (* SOFT_HLUTNM = "soft_lutpair1273" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__40 
       (.I0(DQOut[296]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[300]),
        .O(\wosp_reg[2]_rep__4_25 ));
  (* SOFT_HLUTNM = "soft_lutpair1274" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__41 
       (.I0(DQOut[304]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[308]),
        .O(\wosp_reg[2]_rep__4_22 ));
  (* SOFT_HLUTNM = "soft_lutpair1275" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__42 
       (.I0(DQOut[312]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[316]),
        .O(\wosp_reg[2]_rep__4_19 ));
  (* SOFT_HLUTNM = "soft_lutpair1311" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__43 
       (.I0(DMOut[32]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DMOut[36]),
        .O(\wosp_reg[2]_rep__4_16 ));
  (* SOFT_HLUTNM = "soft_lutpair1276" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__44 
       (.I0(DQOut[320]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[324]),
        .O(\wosp_reg[2]_rep__5_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1277" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__45 
       (.I0(DQOut[328]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[332]),
        .O(\wosp_reg[2]_rep__5_28 ));
  (* SOFT_HLUTNM = "soft_lutpair1278" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__46 
       (.I0(DQOut[336]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[340]),
        .O(\wosp_reg[2]_rep__5_25 ));
  (* SOFT_HLUTNM = "soft_lutpair1279" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__47 
       (.I0(DQOut[344]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[348]),
        .O(\wosp_reg[2]_rep__5_22 ));
  (* SOFT_HLUTNM = "soft_lutpair1280" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__48 
       (.I0(DQOut[352]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[356]),
        .O(\wosp_reg[2]_rep__5_19 ));
  (* SOFT_HLUTNM = "soft_lutpair1281" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__49 
       (.I0(DQOut[360]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[364]),
        .O(\wosp_reg[2]_rep__5_16 ));
  (* SOFT_HLUTNM = "soft_lutpair1243" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__5 
       (.I0(DQOut[48]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[52]),
        .O(\wosp_reg[2]_rep__1_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1282" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__50 
       (.I0(DQOut[368]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[372]),
        .O(\wosp_reg[2]_rep__5_13 ));
  (* SOFT_HLUTNM = "soft_lutpair1283" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__51 
       (.I0(DQOut[376]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[380]),
        .O(\wosp_reg[2]_rep__5_10 ));
  (* SOFT_HLUTNM = "soft_lutpair1312" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__52 
       (.I0(DMOut[40]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DMOut[44]),
        .O(\wosp_reg[2]_rep__5_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1284" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__53 
       (.I0(DQOut[384]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[388]),
        .O(\wosp_reg[2]_rep__6 ));
  (* SOFT_HLUTNM = "soft_lutpair1285" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__54 
       (.I0(DQOut[392]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[396]),
        .O(\wosp_reg[2]_rep__6_18 ));
  (* SOFT_HLUTNM = "soft_lutpair1286" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__55 
       (.I0(DQOut[400]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[404]),
        .O(\wosp_reg[2]_rep__6_15 ));
  (* SOFT_HLUTNM = "soft_lutpair1287" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__56 
       (.I0(DQOut[408]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[412]),
        .O(\wosp_reg[2]_rep__6_12 ));
  (* SOFT_HLUTNM = "soft_lutpair1288" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__57 
       (.I0(DQOut[416]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[420]),
        .O(\wosp_reg[2]_rep__6_9 ));
  (* SOFT_HLUTNM = "soft_lutpair1289" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__58 
       (.I0(DQOut[424]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[428]),
        .O(\wosp_reg[2]_rep__6_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1290" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__59 
       (.I0(DQOut[432]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[436]),
        .O(\wosp_reg[2]_rep__6_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1244" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__6 
       (.I0(DQOut[56]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[60]),
        .O(\wosp_reg[2]_rep__1_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1283" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__60 
       (.I0(DQOut[440]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[444]),
        .O(\wosp_reg[2]_rep__5_33 ));
  (* SOFT_HLUTNM = "soft_lutpair1313" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__61 
       (.I0(DMOut[48]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DMOut[52]),
        .O(\wosp_reg[2]_rep__5_31 ));
  (* SOFT_HLUTNM = "soft_lutpair1291" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__62 
       (.I0(DQOut[448]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[452]),
        .O(\wosp_reg[2]_rep__6_20 ));
  (* SOFT_HLUTNM = "soft_lutpair1292" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__63 
       (.I0(DQOut[456]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[460]),
        .O(\wosp_reg[2]_rep__6_41 ));
  (* SOFT_HLUTNM = "soft_lutpair1293" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__64 
       (.I0(DQOut[464]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[468]),
        .O(\wosp_reg[2]_rep__6_38 ));
  (* SOFT_HLUTNM = "soft_lutpair1294" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__65 
       (.I0(DQOut[472]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[476]),
        .O(\wosp_reg[2]_rep__6_35 ));
  (* SOFT_HLUTNM = "soft_lutpair1295" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__66 
       (.I0(DQOut[480]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[484]),
        .O(\wosp_reg[2]_rep__6_32 ));
  (* SOFT_HLUTNM = "soft_lutpair1296" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__67 
       (.I0(DQOut[488]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[492]),
        .O(\wosp_reg[2]_rep__6_29 ));
  (* SOFT_HLUTNM = "soft_lutpair1297" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__68 
       (.I0(DQOut[496]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[500]),
        .O(\wosp_reg[2]_rep__6_26 ));
  (* SOFT_HLUTNM = "soft_lutpair1298" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__69 
       (.I0(DQOut[504]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[508]),
        .O(\wosp_reg[2]_rep__6_23 ));
  (* SOFT_HLUTNM = "soft_lutpair1307" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__7 
       (.I0(DMOut[0]),
        .I1(\dReg_reg[11] ),
        .I2(DMOut[4]),
        .O(\wosp_reg[2]_rep__1_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__70 
       (.I0(DMOut[56]),
        .I1(\dReg_reg[8]_0 ),
        .I2(DMOut[60]),
        .O(\wosp_reg[2]_rep__7_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1245" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__8 
       (.I0(DQOut[64]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[68]),
        .O(\wosp_reg[2]_rep__3 ));
  (* SOFT_HLUTNM = "soft_lutpair1246" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[8]_i_3__9 
       (.I0(DQOut[72]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[76]),
        .O(\wosp_reg[2]_rep__2_33 ));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1 
       (.I0(DQOut[3]),
        .I1(\dReg_reg[9] ),
        .I2(DQOut[7]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep_0 ),
        .O(\wosp_reg[2]_rep [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__0 
       (.I0(DMOut[3]),
        .I1(\dReg_reg[11] ),
        .I2(DMOut[7]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__1_1 ),
        .O(\wosp_reg[2]_rep__1 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__1 
       (.I0(DQOut[59]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[63]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__1_4 ),
        .O(\wosp_reg[2]_rep__1_2 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__10 
       (.I0(DQOut[123]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[127]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_16 ),
        .O(\wosp_reg[2]_rep__2_14 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__11 
       (.I0(DQOut[115]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[119]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_19 ),
        .O(\wosp_reg[2]_rep__2_17 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__12 
       (.I0(DQOut[107]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[111]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_22 ),
        .O(\wosp_reg[2]_rep__2_20 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__13 
       (.I0(DQOut[99]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[103]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_25 ),
        .O(\wosp_reg[2]_rep__2_23 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__14 
       (.I0(DQOut[91]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[95]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_28 ),
        .O(\wosp_reg[2]_rep__2_26 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__15 
       (.I0(DQOut[83]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[87]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_31 ),
        .O(\wosp_reg[2]_rep__2_29 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__16 
       (.I0(DQOut[75]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[79]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_34 ),
        .O(\wosp_reg[2]_rep__2_32 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__17 
       (.I0(DQOut[131]),
        .I1(\dReg_reg[9] ),
        .I2(DQOut[135]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep_4 ),
        .O(\wosp_reg[2]_rep_3 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__18 
       (.I0(DMOut[19]),
        .I1(\dReg_reg[10] ),
        .I2(DMOut[23]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_3 ),
        .O(\wosp_reg[2]_rep__3_1 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__19 
       (.I0(DQOut[187]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[191]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_6 ),
        .O(\wosp_reg[2]_rep__3_4 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__2 
       (.I0(DQOut[51]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[55]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__1_7 ),
        .O(\wosp_reg[2]_rep__1_5 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__20 
       (.I0(DQOut[179]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[183]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_9 ),
        .O(\wosp_reg[2]_rep__3_7 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__21 
       (.I0(DQOut[171]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[175]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_12 ),
        .O(\wosp_reg[2]_rep__3_10 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__22 
       (.I0(DQOut[163]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[167]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_15 ),
        .O(\wosp_reg[2]_rep__3_13 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__23 
       (.I0(DQOut[155]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[159]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_18 ),
        .O(\wosp_reg[2]_rep__3_16 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__24 
       (.I0(DQOut[147]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[151]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_21 ),
        .O(\wosp_reg[2]_rep__3_19 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__25 
       (.I0(DQOut[139]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[143]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_24 ),
        .O(\wosp_reg[2]_rep__3_22 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__26 
       (.I0(DQOut[195]),
        .I1(\dReg_reg[9]_1 ),
        .I2(DQOut[199]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__0_0 ),
        .O(\wosp_reg[2]_rep__0 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__27 
       (.I0(DMOut[27]),
        .I1(\dReg_reg[10] ),
        .I2(DMOut[31]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_27 ),
        .O(\wosp_reg[2]_rep__3_25 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__28 
       (.I0(DQOut[251]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[255]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_30 ),
        .O(\wosp_reg[2]_rep__3_28 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__29 
       (.I0(DQOut[243]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[247]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__3_33 ),
        .O(\wosp_reg[2]_rep__3_31 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__3 
       (.I0(DQOut[43]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[47]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__1_10 ),
        .O(\wosp_reg[2]_rep__1_8 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__30 
       (.I0(DQOut[235]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[239]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_2 ),
        .O(\wosp_reg[2]_rep__4_0 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__31 
       (.I0(DQOut[227]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[231]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_5 ),
        .O(\wosp_reg[2]_rep__4_3 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__32 
       (.I0(DQOut[219]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[223]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_8 ),
        .O(\wosp_reg[2]_rep__4_6 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__33 
       (.I0(DQOut[211]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[215]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_11 ),
        .O(\wosp_reg[2]_rep__4_9 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__34 
       (.I0(DQOut[203]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[207]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_14 ),
        .O(\wosp_reg[2]_rep__4_12 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__35 
       (.I0(DQOut[259]),
        .I1(\dReg_reg[9]_1 ),
        .I2(DQOut[263]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__0_2 ),
        .O(\wosp_reg[2]_rep__0_1 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__36 
       (.I0(DMOut[35]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DMOut[39]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_17 ),
        .O(\wosp_reg[2]_rep__4_15 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__37 
       (.I0(DQOut[315]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[319]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_20 ),
        .O(\wosp_reg[2]_rep__4_18 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__38 
       (.I0(DQOut[307]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[311]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_23 ),
        .O(\wosp_reg[2]_rep__4_21 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__39 
       (.I0(DQOut[299]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[303]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_26 ),
        .O(\wosp_reg[2]_rep__4_24 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__4 
       (.I0(DQOut[35]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[39]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_1 ),
        .O(\wosp_reg[2]_rep__2_0 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__40 
       (.I0(DQOut[291]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[295]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_29 ),
        .O(\wosp_reg[2]_rep__4_27 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__41 
       (.I0(DQOut[283]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[287]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__4_32 ),
        .O(\wosp_reg[2]_rep__4_30 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__42 
       (.I0(DQOut[275]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[279]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_1 ),
        .O(\wosp_reg[2]_rep__5_0 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__43 
       (.I0(DQOut[267]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[271]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_4 ),
        .O(\wosp_reg[2]_rep__5_2 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__44 
       (.I0(DQOut[323]),
        .I1(\dReg_reg[9]_1 ),
        .I2(DQOut[327]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__0_4 ),
        .O(\wosp_reg[2]_rep__0_3 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__45 
       (.I0(DMOut[43]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DMOut[47]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_8 ),
        .O(\wosp_reg[2]_rep__5_6 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__46 
       (.I0(DQOut[379]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[383]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_11 ),
        .O(\wosp_reg[2]_rep__5_9 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__47 
       (.I0(DQOut[371]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[375]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_14 ),
        .O(\wosp_reg[2]_rep__5_12 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__48 
       (.I0(DQOut[363]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[367]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_17 ),
        .O(\wosp_reg[2]_rep__5_15 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__49 
       (.I0(DQOut[355]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[359]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_20 ),
        .O(\wosp_reg[2]_rep__5_18 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__5 
       (.I0(DQOut[27]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[31]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_4 ),
        .O(\wosp_reg[2]_rep__2_2 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__50 
       (.I0(DQOut[347]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[351]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_23 ),
        .O(\wosp_reg[2]_rep__5_21 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__51 
       (.I0(DQOut[339]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[343]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_26 ),
        .O(\wosp_reg[2]_rep__5_24 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__52 
       (.I0(DQOut[331]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[335]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_29 ),
        .O(\wosp_reg[2]_rep__5_27 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__53 
       (.I0(DQOut[387]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[391]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__1_13 ),
        .O(\wosp_reg[2]_rep__1_12 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__54 
       (.I0(DMOut[51]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DMOut[55]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__5_32 ),
        .O(\wosp_reg[2]_rep__5_30 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__55 
       (.I0(DQOut[443]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[447]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_1 ),
        .O(\wosp_reg[2]_rep__6_0 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__56 
       (.I0(DQOut[435]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[439]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_4 ),
        .O(\wosp_reg[2]_rep__6_2 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__57 
       (.I0(DQOut[427]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[431]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_7 ),
        .O(\wosp_reg[2]_rep__6_5 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__58 
       (.I0(DQOut[419]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[423]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_10 ),
        .O(\wosp_reg[2]_rep__6_8 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__59 
       (.I0(DQOut[411]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[415]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_13 ),
        .O(\wosp_reg[2]_rep__6_11 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__6 
       (.I0(DQOut[19]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[23]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_7 ),
        .O(\wosp_reg[2]_rep__2_5 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__60 
       (.I0(DQOut[403]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[407]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_16 ),
        .O(\wosp_reg[2]_rep__6_14 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__61 
       (.I0(DQOut[395]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[399]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_19 ),
        .O(\wosp_reg[2]_rep__6_17 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__62 
       (.I0(DQOut[451]),
        .I1(wosp[2]),
        .I2(DQOut[455]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_0 ),
        .O(\wosp_reg[2] [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__63 
       (.I0(DMOut[59]),
        .I1(\dReg_reg[8]_0 ),
        .I2(DMOut[63]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_21 ),
        .O(\wosp_reg[2]_rep__7 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__64 
       (.I0(DQOut[507]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[511]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_24 ),
        .O(\wosp_reg[2]_rep__6_22 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__65 
       (.I0(DQOut[499]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[503]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_27 ),
        .O(\wosp_reg[2]_rep__6_25 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__66 
       (.I0(DQOut[491]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[495]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_30 ),
        .O(\wosp_reg[2]_rep__6_28 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__67 
       (.I0(DQOut[483]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[487]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_33 ),
        .O(\wosp_reg[2]_rep__6_31 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__68 
       (.I0(DQOut[475]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[479]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_36 ),
        .O(\wosp_reg[2]_rep__6_34 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__69 
       (.I0(DQOut[467]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[471]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_39 ),
        .O(\wosp_reg[2]_rep__6_37 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__7 
       (.I0(DQOut[11]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[15]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_10 ),
        .O(\wosp_reg[2]_rep__2_8 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__70 
       (.I0(DQOut[459]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[463]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__6_42 ),
        .O(\wosp_reg[2]_rep__6_40 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__8 
       (.I0(DQOut[67]),
        .I1(\dReg_reg[9] ),
        .I2(DQOut[71]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep_2 ),
        .O(\wosp_reg[2]_rep_1 [1]));
  LUT6 #(
    .INIT(64'hFFB8000000B80000)) 
    \dReg[9]_i_1__9 
       (.I0(DMOut[11]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DMOut[15]),
        .I3(wosp[1]),
        .I4(wrDataVal),
        .I5(\wosp_reg[2]_rep__2_13 ),
        .O(\wosp_reg[2]_rep__2_11 [1]));
  (* SOFT_HLUTNM = "soft_lutpair1390" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2 
       (.I0(\dReg_reg[15] [479]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[507]),
        .O(DQOut[507]));
  (* SOFT_HLUTNM = "soft_lutpair1391" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__0 
       (.I0(\dReg_reg[15] [478]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[499]),
        .O(DQOut[499]));
  (* SOFT_HLUTNM = "soft_lutpair1392" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__1 
       (.I0(\dReg_reg[15] [477]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[491]),
        .O(DQOut[491]));
  (* SOFT_HLUTNM = "soft_lutpair1401" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__10 
       (.I0(\dReg_reg[15] [412]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[419]),
        .O(DQOut[419]));
  (* SOFT_HLUTNM = "soft_lutpair1402" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__11 
       (.I0(\dReg_reg[15] [411]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[411]),
        .O(DQOut[411]));
  (* SOFT_HLUTNM = "soft_lutpair1403" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__12 
       (.I0(\dReg_reg[15] [410]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[403]),
        .O(DQOut[403]));
  (* SOFT_HLUTNM = "soft_lutpair1404" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__13 
       (.I0(\dReg_reg[15] [409]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[395]),
        .O(DQOut[395]));
  (* SOFT_HLUTNM = "soft_lutpair1405" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__14 
       (.I0(\dReg_reg[15] [408]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[387]),
        .O(DQOut[387]));
  (* SOFT_HLUTNM = "soft_lutpair1406" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__15 
       (.I0(\dReg_reg[15] [351]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[379]),
        .O(DQOut[379]));
  (* SOFT_HLUTNM = "soft_lutpair1407" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__16 
       (.I0(\dReg_reg[15] [350]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[371]),
        .O(DQOut[371]));
  (* SOFT_HLUTNM = "soft_lutpair1408" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__17 
       (.I0(\dReg_reg[15] [349]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[363]),
        .O(DQOut[363]));
  (* SOFT_HLUTNM = "soft_lutpair1409" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__18 
       (.I0(\dReg_reg[15] [348]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[355]),
        .O(DQOut[355]));
  (* SOFT_HLUTNM = "soft_lutpair1410" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__19 
       (.I0(\dReg_reg[15] [347]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[347]),
        .O(DQOut[347]));
  (* SOFT_HLUTNM = "soft_lutpair1393" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__2 
       (.I0(\dReg_reg[15] [476]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[483]),
        .O(DQOut[483]));
  (* SOFT_HLUTNM = "soft_lutpair1411" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__20 
       (.I0(\dReg_reg[15] [346]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[339]),
        .O(DQOut[339]));
  (* SOFT_HLUTNM = "soft_lutpair1412" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__21 
       (.I0(\dReg_reg[15] [345]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[331]),
        .O(DQOut[331]));
  (* SOFT_HLUTNM = "soft_lutpair1413" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__22 
       (.I0(\dReg_reg[15] [344]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[323]),
        .O(DQOut[323]));
  (* SOFT_HLUTNM = "soft_lutpair1414" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__23 
       (.I0(\dReg_reg[15] [287]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[315]),
        .O(DQOut[315]));
  (* SOFT_HLUTNM = "soft_lutpair1415" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__24 
       (.I0(\dReg_reg[15] [286]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[307]),
        .O(DQOut[307]));
  (* SOFT_HLUTNM = "soft_lutpair1416" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__25 
       (.I0(\dReg_reg[15] [285]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[299]),
        .O(DQOut[299]));
  (* SOFT_HLUTNM = "soft_lutpair1417" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__26 
       (.I0(\dReg_reg[15] [284]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[291]),
        .O(DQOut[291]));
  (* SOFT_HLUTNM = "soft_lutpair1418" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__27 
       (.I0(\dReg_reg[15] [283]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[283]),
        .O(DQOut[283]));
  (* SOFT_HLUTNM = "soft_lutpair1419" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__28 
       (.I0(\dReg_reg[15] [282]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[275]),
        .O(DQOut[275]));
  (* SOFT_HLUTNM = "soft_lutpair1420" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__29 
       (.I0(\dReg_reg[15] [281]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[267]),
        .O(DQOut[267]));
  (* SOFT_HLUTNM = "soft_lutpair1394" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__3 
       (.I0(\dReg_reg[15] [475]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[475]),
        .O(DQOut[475]));
  (* SOFT_HLUTNM = "soft_lutpair1421" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__30 
       (.I0(\dReg_reg[15] [280]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[259]),
        .O(DQOut[259]));
  (* SOFT_HLUTNM = "soft_lutpair1422" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__31 
       (.I0(\dReg_reg[15] [223]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[251]),
        .O(DQOut[251]));
  (* SOFT_HLUTNM = "soft_lutpair1423" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__32 
       (.I0(\dReg_reg[15] [222]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[243]),
        .O(DQOut[243]));
  (* SOFT_HLUTNM = "soft_lutpair1424" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__33 
       (.I0(\dReg_reg[15] [221]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[235]),
        .O(DQOut[235]));
  (* SOFT_HLUTNM = "soft_lutpair1425" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__34 
       (.I0(\dReg_reg[15] [220]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[227]),
        .O(DQOut[227]));
  (* SOFT_HLUTNM = "soft_lutpair1426" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__35 
       (.I0(\dReg_reg[15] [219]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[219]),
        .O(DQOut[219]));
  (* SOFT_HLUTNM = "soft_lutpair1427" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__36 
       (.I0(\dReg_reg[15] [218]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[211]),
        .O(DQOut[211]));
  (* SOFT_HLUTNM = "soft_lutpair1428" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__37 
       (.I0(\dReg_reg[15] [217]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[203]),
        .O(DQOut[203]));
  (* SOFT_HLUTNM = "soft_lutpair1429" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__38 
       (.I0(\dReg_reg[15] [216]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[195]),
        .O(DQOut[195]));
  (* SOFT_HLUTNM = "soft_lutpair1430" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__39 
       (.I0(\dReg_reg[15] [159]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[187]),
        .O(DQOut[187]));
  (* SOFT_HLUTNM = "soft_lutpair1395" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__4 
       (.I0(\dReg_reg[15] [474]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[467]),
        .O(DQOut[467]));
  (* SOFT_HLUTNM = "soft_lutpair1431" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__40 
       (.I0(\dReg_reg[15] [158]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[179]),
        .O(DQOut[179]));
  (* SOFT_HLUTNM = "soft_lutpair1432" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__41 
       (.I0(\dReg_reg[15] [157]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[171]),
        .O(DQOut[171]));
  (* SOFT_HLUTNM = "soft_lutpair1433" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__42 
       (.I0(\dReg_reg[15] [156]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[163]),
        .O(DQOut[163]));
  (* SOFT_HLUTNM = "soft_lutpair1434" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__43 
       (.I0(\dReg_reg[15] [155]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[155]),
        .O(DQOut[155]));
  (* SOFT_HLUTNM = "soft_lutpair1435" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__44 
       (.I0(\dReg_reg[15] [154]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[147]),
        .O(DQOut[147]));
  (* SOFT_HLUTNM = "soft_lutpair1436" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__45 
       (.I0(\dReg_reg[15] [153]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[139]),
        .O(DQOut[139]));
  (* SOFT_HLUTNM = "soft_lutpair1437" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__46 
       (.I0(\dReg_reg[15] [152]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[131]),
        .O(DQOut[131]));
  (* SOFT_HLUTNM = "soft_lutpair1438" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__47 
       (.I0(\dReg_reg[15] [95]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[123]),
        .O(DQOut[123]));
  (* SOFT_HLUTNM = "soft_lutpair1439" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__48 
       (.I0(\dReg_reg[15] [94]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[115]),
        .O(DQOut[115]));
  (* SOFT_HLUTNM = "soft_lutpair1440" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__49 
       (.I0(\dReg_reg[15] [93]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[107]),
        .O(DQOut[107]));
  (* SOFT_HLUTNM = "soft_lutpair1396" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__5 
       (.I0(\dReg_reg[15] [473]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[459]),
        .O(DQOut[459]));
  (* SOFT_HLUTNM = "soft_lutpair1441" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__50 
       (.I0(\dReg_reg[15] [92]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[99]),
        .O(DQOut[99]));
  (* SOFT_HLUTNM = "soft_lutpair1442" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__51 
       (.I0(\dReg_reg[15] [91]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[91]),
        .O(DQOut[91]));
  (* SOFT_HLUTNM = "soft_lutpair1443" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__52 
       (.I0(\dReg_reg[15] [90]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[83]),
        .O(DQOut[83]));
  (* SOFT_HLUTNM = "soft_lutpair1444" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__53 
       (.I0(\dReg_reg[15] [89]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[75]),
        .O(DQOut[75]));
  (* SOFT_HLUTNM = "soft_lutpair1445" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__54 
       (.I0(\dReg_reg[15] [88]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[67]),
        .O(DQOut[67]));
  (* SOFT_HLUTNM = "soft_lutpair1446" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__55 
       (.I0(\dReg_reg[15] [31]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[59]),
        .O(DQOut[59]));
  (* SOFT_HLUTNM = "soft_lutpair1447" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__56 
       (.I0(\dReg_reg[15] [30]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[51]),
        .O(DQOut[51]));
  (* SOFT_HLUTNM = "soft_lutpair1448" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__57 
       (.I0(\dReg_reg[15] [29]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[43]),
        .O(DQOut[43]));
  (* SOFT_HLUTNM = "soft_lutpair1449" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__58 
       (.I0(\dReg_reg[15] [28]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[35]),
        .O(DQOut[35]));
  (* SOFT_HLUTNM = "soft_lutpair1450" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__59 
       (.I0(\dReg_reg[15] [27]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[27]),
        .O(DQOut[27]));
  (* SOFT_HLUTNM = "soft_lutpair1397" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__6 
       (.I0(\dReg_reg[15] [472]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[451]),
        .O(DQOut[451]));
  (* SOFT_HLUTNM = "soft_lutpair1451" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__60 
       (.I0(\dReg_reg[15] [26]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[19]),
        .O(DQOut[19]));
  (* SOFT_HLUTNM = "soft_lutpair1452" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__61 
       (.I0(\dReg_reg[15] [25]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[11]),
        .O(DQOut[11]));
  (* SOFT_HLUTNM = "soft_lutpair1453" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__62 
       (.I0(\dReg_reg[15] [24]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[3]),
        .O(DQOut[3]));
  (* SOFT_HLUTNM = "soft_lutpair1498" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[9]_i_2__63 
       (.I0(\dReg_reg[15] [571]),
        .I1(cal_DMOut_n[59]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[59]));
  (* SOFT_HLUTNM = "soft_lutpair1499" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[9]_i_2__64 
       (.I0(\dReg_reg[15] [563]),
        .I1(cal_DMOut_n[51]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[51]));
  (* SOFT_HLUTNM = "soft_lutpair1500" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[9]_i_2__65 
       (.I0(\dReg_reg[15] [555]),
        .I1(cal_DMOut_n[43]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[43]));
  (* SOFT_HLUTNM = "soft_lutpair1501" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[9]_i_2__66 
       (.I0(\dReg_reg[15] [547]),
        .I1(cal_DMOut_n[35]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[35]));
  (* SOFT_HLUTNM = "soft_lutpair1502" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[9]_i_2__67 
       (.I0(\dReg_reg[15] [539]),
        .I1(cal_DMOut_n[27]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[27]));
  (* SOFT_HLUTNM = "soft_lutpair1503" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[9]_i_2__68 
       (.I0(\dReg_reg[15] [531]),
        .I1(cal_DMOut_n[19]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[19]));
  (* SOFT_HLUTNM = "soft_lutpair1504" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[9]_i_2__69 
       (.I0(\dReg_reg[15] [523]),
        .I1(cal_DMOut_n[11]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[11]));
  (* SOFT_HLUTNM = "soft_lutpair1398" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__7 
       (.I0(\dReg_reg[15] [415]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[443]),
        .O(DQOut[443]));
  (* SOFT_HLUTNM = "soft_lutpair1505" *) 
  LUT3 #(
    .INIT(8'h53)) 
    \dReg[9]_i_2__70 
       (.I0(\dReg_reg[15] [515]),
        .I1(cal_DMOut_n[3]),
        .I2(\mcal_ODT_dly_reg[0][4] ),
        .O(DMOut[3]));
  (* SOFT_HLUTNM = "soft_lutpair1399" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__8 
       (.I0(\dReg_reg[15] [414]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[435]),
        .O(DQOut[435]));
  (* SOFT_HLUTNM = "soft_lutpair1400" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_2__9 
       (.I0(\dReg_reg[15] [413]),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(cal_DQOut[427]),
        .O(DQOut[427]));
  (* SOFT_HLUTNM = "soft_lutpair1236" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3 
       (.I0(DQOut[1]),
        .I1(\dReg_reg[9] ),
        .I2(DQOut[5]),
        .O(\wosp_reg[2]_rep_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1237" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__0 
       (.I0(DQOut[9]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[13]),
        .O(\wosp_reg[2]_rep__2_10 ));
  (* SOFT_HLUTNM = "soft_lutpair1238" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__1 
       (.I0(DQOut[17]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[21]),
        .O(\wosp_reg[2]_rep__2_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1247" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__10 
       (.I0(DQOut[81]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[85]),
        .O(\wosp_reg[2]_rep__2_31 ));
  (* SOFT_HLUTNM = "soft_lutpair1248" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__11 
       (.I0(DQOut[89]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[93]),
        .O(\wosp_reg[2]_rep__2_28 ));
  (* SOFT_HLUTNM = "soft_lutpair1249" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__12 
       (.I0(DQOut[97]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[101]),
        .O(\wosp_reg[2]_rep__2_25 ));
  (* SOFT_HLUTNM = "soft_lutpair1250" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__13 
       (.I0(DQOut[105]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[109]),
        .O(\wosp_reg[2]_rep__2_22 ));
  (* SOFT_HLUTNM = "soft_lutpair1251" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__14 
       (.I0(DQOut[113]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[117]),
        .O(\wosp_reg[2]_rep__2_19 ));
  (* SOFT_HLUTNM = "soft_lutpair1252" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__15 
       (.I0(DQOut[121]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[125]),
        .O(\wosp_reg[2]_rep__2_16 ));
  (* SOFT_HLUTNM = "soft_lutpair1308" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__16 
       (.I0(DMOut[9]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DMOut[13]),
        .O(\wosp_reg[2]_rep__2_13 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__17 
       (.I0(DQOut[129]),
        .I1(\dReg_reg[9] ),
        .I2(DQOut[133]),
        .O(\wosp_reg[2]_rep_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1253" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__18 
       (.I0(DQOut[137]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[141]),
        .O(\wosp_reg[2]_rep__3_24 ));
  (* SOFT_HLUTNM = "soft_lutpair1254" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__19 
       (.I0(DQOut[145]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[149]),
        .O(\wosp_reg[2]_rep__3_21 ));
  (* SOFT_HLUTNM = "soft_lutpair1239" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__2 
       (.I0(DQOut[25]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[29]),
        .O(\wosp_reg[2]_rep__2_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1255" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__20 
       (.I0(DQOut[153]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[157]),
        .O(\wosp_reg[2]_rep__3_18 ));
  (* SOFT_HLUTNM = "soft_lutpair1256" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__21 
       (.I0(DQOut[161]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[165]),
        .O(\wosp_reg[2]_rep__3_15 ));
  (* SOFT_HLUTNM = "soft_lutpair1257" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__22 
       (.I0(DQOut[169]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[173]),
        .O(\wosp_reg[2]_rep__3_12 ));
  (* SOFT_HLUTNM = "soft_lutpair1258" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__23 
       (.I0(DQOut[177]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[181]),
        .O(\wosp_reg[2]_rep__3_9 ));
  (* SOFT_HLUTNM = "soft_lutpair1259" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__24 
       (.I0(DQOut[185]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[189]),
        .O(\wosp_reg[2]_rep__3_6 ));
  (* SOFT_HLUTNM = "soft_lutpair1309" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__25 
       (.I0(DMOut[17]),
        .I1(\dReg_reg[10] ),
        .I2(DMOut[21]),
        .O(\wosp_reg[2]_rep__3_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1260" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__26 
       (.I0(DQOut[193]),
        .I1(\dReg_reg[9]_1 ),
        .I2(DQOut[197]),
        .O(\wosp_reg[2]_rep__0_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1261" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__27 
       (.I0(DQOut[201]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[205]),
        .O(\wosp_reg[2]_rep__4_14 ));
  (* SOFT_HLUTNM = "soft_lutpair1262" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__28 
       (.I0(DQOut[209]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[213]),
        .O(\wosp_reg[2]_rep__4_11 ));
  (* SOFT_HLUTNM = "soft_lutpair1263" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__29 
       (.I0(DQOut[217]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[221]),
        .O(\wosp_reg[2]_rep__4_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1240" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__3 
       (.I0(DQOut[33]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[37]),
        .O(\wosp_reg[2]_rep__2_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1264" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__30 
       (.I0(DQOut[225]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[229]),
        .O(\wosp_reg[2]_rep__4_5 ));
  (* SOFT_HLUTNM = "soft_lutpair1265" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__31 
       (.I0(DQOut[233]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[237]),
        .O(\wosp_reg[2]_rep__4_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1267" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__32 
       (.I0(DQOut[241]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[245]),
        .O(\wosp_reg[2]_rep__3_33 ));
  (* SOFT_HLUTNM = "soft_lutpair1268" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__33 
       (.I0(DQOut[249]),
        .I1(\dReg_reg[10] ),
        .I2(DQOut[253]),
        .O(\wosp_reg[2]_rep__3_30 ));
  (* SOFT_HLUTNM = "soft_lutpair1310" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__34 
       (.I0(DMOut[25]),
        .I1(\dReg_reg[10] ),
        .I2(DMOut[29]),
        .O(\wosp_reg[2]_rep__3_27 ));
  (* SOFT_HLUTNM = "soft_lutpair1260" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__35 
       (.I0(DQOut[257]),
        .I1(\dReg_reg[9]_1 ),
        .I2(DQOut[261]),
        .O(\wosp_reg[2]_rep__0_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1269" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__36 
       (.I0(DQOut[265]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[269]),
        .O(\wosp_reg[2]_rep__5_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1270" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__37 
       (.I0(DQOut[273]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[277]),
        .O(\wosp_reg[2]_rep__5_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1271" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__38 
       (.I0(DQOut[281]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[285]),
        .O(\wosp_reg[2]_rep__4_32 ));
  (* SOFT_HLUTNM = "soft_lutpair1272" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__39 
       (.I0(DQOut[289]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[293]),
        .O(\wosp_reg[2]_rep__4_29 ));
  (* SOFT_HLUTNM = "soft_lutpair1241" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__4 
       (.I0(DQOut[41]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[45]),
        .O(\wosp_reg[2]_rep__1_10 ));
  (* SOFT_HLUTNM = "soft_lutpair1273" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__40 
       (.I0(DQOut[297]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[301]),
        .O(\wosp_reg[2]_rep__4_26 ));
  (* SOFT_HLUTNM = "soft_lutpair1274" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__41 
       (.I0(DQOut[305]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[309]),
        .O(\wosp_reg[2]_rep__4_23 ));
  (* SOFT_HLUTNM = "soft_lutpair1275" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__42 
       (.I0(DQOut[313]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DQOut[317]),
        .O(\wosp_reg[2]_rep__4_20 ));
  (* SOFT_HLUTNM = "soft_lutpair1311" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__43 
       (.I0(DMOut[33]),
        .I1(\dReg_reg[11]_0 ),
        .I2(DMOut[37]),
        .O(\wosp_reg[2]_rep__4_17 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__44 
       (.I0(DQOut[321]),
        .I1(\dReg_reg[9]_1 ),
        .I2(DQOut[325]),
        .O(\wosp_reg[2]_rep__0_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1276" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__45 
       (.I0(DQOut[329]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[333]),
        .O(\wosp_reg[2]_rep__5_29 ));
  (* SOFT_HLUTNM = "soft_lutpair1277" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__46 
       (.I0(DQOut[337]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[341]),
        .O(\wosp_reg[2]_rep__5_26 ));
  (* SOFT_HLUTNM = "soft_lutpair1278" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__47 
       (.I0(DQOut[345]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[349]),
        .O(\wosp_reg[2]_rep__5_23 ));
  (* SOFT_HLUTNM = "soft_lutpair1279" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__48 
       (.I0(DQOut[353]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[357]),
        .O(\wosp_reg[2]_rep__5_20 ));
  (* SOFT_HLUTNM = "soft_lutpair1280" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__49 
       (.I0(DQOut[361]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[365]),
        .O(\wosp_reg[2]_rep__5_17 ));
  (* SOFT_HLUTNM = "soft_lutpair1242" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__5 
       (.I0(DQOut[49]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[53]),
        .O(\wosp_reg[2]_rep__1_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1281" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__50 
       (.I0(DQOut[369]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[373]),
        .O(\wosp_reg[2]_rep__5_14 ));
  (* SOFT_HLUTNM = "soft_lutpair1282" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__51 
       (.I0(DQOut[377]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DQOut[381]),
        .O(\wosp_reg[2]_rep__5_11 ));
  (* SOFT_HLUTNM = "soft_lutpair1312" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__52 
       (.I0(DMOut[41]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DMOut[45]),
        .O(\wosp_reg[2]_rep__5_8 ));
  (* SOFT_HLUTNM = "soft_lutpair1244" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__53 
       (.I0(DQOut[385]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[389]),
        .O(\wosp_reg[2]_rep__1_13 ));
  (* SOFT_HLUTNM = "soft_lutpair1284" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__54 
       (.I0(DQOut[393]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[397]),
        .O(\wosp_reg[2]_rep__6_19 ));
  (* SOFT_HLUTNM = "soft_lutpair1285" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__55 
       (.I0(DQOut[401]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[405]),
        .O(\wosp_reg[2]_rep__6_16 ));
  (* SOFT_HLUTNM = "soft_lutpair1286" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__56 
       (.I0(DQOut[409]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[413]),
        .O(\wosp_reg[2]_rep__6_13 ));
  (* SOFT_HLUTNM = "soft_lutpair1287" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__57 
       (.I0(DQOut[417]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[421]),
        .O(\wosp_reg[2]_rep__6_10 ));
  (* SOFT_HLUTNM = "soft_lutpair1288" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__58 
       (.I0(DQOut[425]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[429]),
        .O(\wosp_reg[2]_rep__6_7 ));
  (* SOFT_HLUTNM = "soft_lutpair1289" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__59 
       (.I0(DQOut[433]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[437]),
        .O(\wosp_reg[2]_rep__6_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1243" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__6 
       (.I0(DQOut[57]),
        .I1(\dReg_reg[11] ),
        .I2(DQOut[61]),
        .O(\wosp_reg[2]_rep__1_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1290" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__60 
       (.I0(DQOut[441]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[445]),
        .O(\wosp_reg[2]_rep__6_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1313" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__61 
       (.I0(DMOut[49]),
        .I1(\dReg_reg[11]_1 ),
        .I2(DMOut[53]),
        .O(\wosp_reg[2]_rep__5_32 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__62 
       (.I0(DQOut[449]),
        .I1(wosp[2]),
        .I2(DQOut[453]),
        .O(\wosp_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1291" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__63 
       (.I0(DQOut[457]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[461]),
        .O(\wosp_reg[2]_rep__6_42 ));
  (* SOFT_HLUTNM = "soft_lutpair1292" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__64 
       (.I0(DQOut[465]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[469]),
        .O(\wosp_reg[2]_rep__6_39 ));
  (* SOFT_HLUTNM = "soft_lutpair1293" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__65 
       (.I0(DQOut[473]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[477]),
        .O(\wosp_reg[2]_rep__6_36 ));
  (* SOFT_HLUTNM = "soft_lutpair1294" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__66 
       (.I0(DQOut[481]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[485]),
        .O(\wosp_reg[2]_rep__6_33 ));
  (* SOFT_HLUTNM = "soft_lutpair1295" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__67 
       (.I0(DQOut[489]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[493]),
        .O(\wosp_reg[2]_rep__6_30 ));
  (* SOFT_HLUTNM = "soft_lutpair1296" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__68 
       (.I0(DQOut[497]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[501]),
        .O(\wosp_reg[2]_rep__6_27 ));
  (* SOFT_HLUTNM = "soft_lutpair1297" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__69 
       (.I0(DQOut[505]),
        .I1(\dReg_reg[8] ),
        .I2(DQOut[509]),
        .O(\wosp_reg[2]_rep__6_24 ));
  (* SOFT_HLUTNM = "soft_lutpair1307" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__7 
       (.I0(DMOut[1]),
        .I1(\dReg_reg[11] ),
        .I2(DMOut[5]),
        .O(\wosp_reg[2]_rep__1_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1298" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__70 
       (.I0(DMOut[57]),
        .I1(\dReg_reg[8] ),
        .I2(DMOut[61]),
        .O(\wosp_reg[2]_rep__6_21 ));
  (* SOFT_HLUTNM = "soft_lutpair1236" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__8 
       (.I0(DQOut[65]),
        .I1(\dReg_reg[9] ),
        .I2(DQOut[69]),
        .O(\wosp_reg[2]_rep_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1246" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \dReg[9]_i_3__9 
       (.I0(DQOut[73]),
        .I1(\dReg_reg[9]_0 ),
        .I2(DQOut[77]),
        .O(\wosp_reg[2]_rep__2_34 ));
  LUT3 #(
    .INIT(8'hFD)) 
    \delay_cntr[0]_i_1 
       (.I0(\delay_cntr_reg[2]_0 [0]),
        .I1(traffic_clr_error_r2),
        .I2(rst_r1),
        .O(\delay_cntr[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \delay_cntr[2]_i_1 
       (.I0(\traffic_instr_nxt_instr_r1_reg_n_0_[1] ),
        .I1(\traffic_instr_nxt_instr_r1_reg_n_0_[2] ),
        .I2(\traffic_instr_nxt_instr_r1_reg_n_0_[0] ),
        .I3(\traffic_instr_nxt_instr_r1_reg_n_0_[3] ),
        .I4(\delay_cntr[2]_i_4_n_0 ),
        .O(\delay_cntr[2]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \delay_cntr[2]_i_2 
       (.I0(traffic_clr_error_r2),
        .I1(rst_r1),
        .O(delay_cntr_rd_valid0));
  LUT4 #(
    .INIT(16'h0009)) 
    \delay_cntr[2]_i_3 
       (.I0(\delay_cntr_reg[2]_0 [1]),
        .I1(\delay_cntr_reg[2]_0 [0]),
        .I2(traffic_clr_error_r2),
        .I3(rst_r1),
        .O(\delay_cntr[2]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFFF1)) 
    \delay_cntr[2]_i_4 
       (.I0(traffic_clr_error_r2),
        .I1(rst_r1),
        .I2(\traffic_instr_nxt_instr_r1_reg_n_0_[4] ),
        .I3(\traffic_instr_nxt_instr_r1_reg_n_0_[5] ),
        .O(\delay_cntr[2]_i_4_n_0 ));
  FDRE \delay_cntr_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(delay_cntr_rd_valid0),
        .D(\delay_cntr[0]_i_1_n_0 ),
        .Q(\delay_cntr_reg[2]_0 [0]),
        .R(\delay_cntr[2]_i_1_n_0 ));
  FDSE \delay_cntr_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(delay_cntr_rd_valid0),
        .D(\delay_cntr[2]_i_3_n_0 ),
        .Q(\delay_cntr_reg[2]_0 [1]),
        .S(\delay_cntr[2]_i_1_n_0 ));
  FDRE devices_dsel_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(E),
        .D(io_write_data[16]),
        .Q(devices_dsel),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair1559" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dqin_valid_shift[1]_i_1 
       (.I0(\dqin_valid_shift_reg_n_0_[0] ),
        .I1(cnt_clr_reg_0),
        .O(dqin_valid_shift_nxt[1]));
  (* SOFT_HLUTNM = "soft_lutpair1559" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dqin_valid_shift[2]_i_1 
       (.I0(p_0_in32_in),
        .I1(cnt_clr_reg_0),
        .O(dqin_valid_shift_nxt[2]));
  FDRE \dqin_valid_shift_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\dqin_valid_shift_reg[0]_0 ),
        .Q(\dqin_valid_shift_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \dqin_valid_shift_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(dqin_valid_shift_nxt[1]),
        .Q(p_0_in32_in),
        .R(1'b0));
  FDRE \dqin_valid_shift_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(dqin_valid_shift_nxt[2]),
        .Q(\dqin_valid_shift_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \dram_device_sel_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(E),
        .D(io_write_data[0]),
        .Q(\dram_device_sel_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \dram_device_sel_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(E),
        .D(io_write_data[1]),
        .Q(\dram_device_sel_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \dram_device_sel_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(E),
        .D(io_write_data[2]),
        .Q(\dram_device_sel_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \dram_device_sel_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(E),
        .D(io_write_data[3]),
        .Q(\dram_device_sel_reg_n_0_[3] ),
        .R(rst_r1));
  FDRE \dram_device_sel_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(E),
        .D(io_write_data[4]),
        .Q(\dram_device_sel_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE \dram_device_sel_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(E),
        .D(io_write_data[5]),
        .Q(\dram_device_sel_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE \dram_device_sel_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(E),
        .D(io_write_data[6]),
        .Q(\dram_device_sel_reg_n_0_[6] ),
        .R(rst_r1));
  FDRE \dram_device_sel_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(E),
        .D(io_write_data[7]),
        .Q(\dram_device_sel_reg_n_0_[7] ),
        .R(rst_r1));
  FDRE en_vtc_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(calDone_reg_14),
        .D(io_write_data[0]),
        .Q(en_vtc),
        .R(rst_r1));
  LUT2 #(
    .INIT(4'h8)) 
    \extended_write[0]_i_1 
       (.I0(cal_seq_cnt_gt_0),
        .I1(seq_cnt_dec),
        .O(cal_seq_cnt0));
  FDRE extended_write_mode_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\cal_seq_reg_n_0_[2] ),
        .Q(extended_write_mode),
        .R(1'b0));
  FDRE \extended_write_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(cal_seq_cnt0),
        .Q(extended_write[0]),
        .R(rst_r1));
  FDRE \extended_write_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(extended_write[0]),
        .Q(extended_write[1]),
        .R(rst_r1));
  FDRE \extended_write_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(extended_write[1]),
        .Q(extended_write[2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[0].cal_DMOut_n_A_r_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[0] ),
        .Q(\genblk10[0].cal_DMOut_n_A_r_reg [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[0].cal_DMOut_n_A_r_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[1] ),
        .Q(\genblk10[0].cal_DMOut_n_A_r_reg [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[0].cal_DMOut_n_A_r_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[2] ),
        .Q(\genblk10[0].cal_DMOut_n_A_r_reg [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[0].cal_DMOut_n_A_r_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[3] ),
        .Q(\genblk10[0].cal_DMOut_n_A_r_reg [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[0].cal_DMOut_n_A_r_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[4] ),
        .Q(\genblk10[0].cal_DMOut_n_A_r_reg [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[0].cal_DMOut_n_A_r_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[5] ),
        .Q(\genblk10[0].cal_DMOut_n_A_r_reg [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[0].cal_DMOut_n_A_r_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[6] ),
        .Q(\genblk10[0].cal_DMOut_n_A_r_reg [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[0].cal_DMOut_n_A_r_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[7] ),
        .Q(\genblk10[0].cal_DMOut_n_A_r_reg [7]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[1].cal_DMOut_n_A_r_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[10] ),
        .Q(\genblk10[1].cal_DMOut_n_A_r_reg [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[1].cal_DMOut_n_A_r_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[11] ),
        .Q(\genblk10[1].cal_DMOut_n_A_r_reg [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[1].cal_DMOut_n_A_r_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[12] ),
        .Q(\genblk10[1].cal_DMOut_n_A_r_reg [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[1].cal_DMOut_n_A_r_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[13] ),
        .Q(\genblk10[1].cal_DMOut_n_A_r_reg [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[1].cal_DMOut_n_A_r_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[14] ),
        .Q(\genblk10[1].cal_DMOut_n_A_r_reg [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[1].cal_DMOut_n_A_r_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[15] ),
        .Q(\genblk10[1].cal_DMOut_n_A_r_reg [7]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[1].cal_DMOut_n_A_r_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[8] ),
        .Q(\genblk10[1].cal_DMOut_n_A_r_reg [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[1].cal_DMOut_n_A_r_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[9] ),
        .Q(\genblk10[1].cal_DMOut_n_A_r_reg [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[2].cal_DMOut_n_A_r_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[16] ),
        .Q(\genblk10[2].cal_DMOut_n_A_r_reg [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[2].cal_DMOut_n_A_r_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[17] ),
        .Q(\genblk10[2].cal_DMOut_n_A_r_reg [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[2].cal_DMOut_n_A_r_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[18] ),
        .Q(\genblk10[2].cal_DMOut_n_A_r_reg [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[2].cal_DMOut_n_A_r_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[19] ),
        .Q(\genblk10[2].cal_DMOut_n_A_r_reg [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[2].cal_DMOut_n_A_r_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[20] ),
        .Q(\genblk10[2].cal_DMOut_n_A_r_reg [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[2].cal_DMOut_n_A_r_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[21] ),
        .Q(\genblk10[2].cal_DMOut_n_A_r_reg [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[2].cal_DMOut_n_A_r_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[22] ),
        .Q(\genblk10[2].cal_DMOut_n_A_r_reg [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[2].cal_DMOut_n_A_r_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[23] ),
        .Q(\genblk10[2].cal_DMOut_n_A_r_reg [7]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[3].cal_DMOut_n_A_r_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[24] ),
        .Q(\genblk10[3].cal_DMOut_n_A_r_reg [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[3].cal_DMOut_n_A_r_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[25] ),
        .Q(\genblk10[3].cal_DMOut_n_A_r_reg [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[3].cal_DMOut_n_A_r_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[26] ),
        .Q(\genblk10[3].cal_DMOut_n_A_r_reg [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[3].cal_DMOut_n_A_r_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[27] ),
        .Q(\genblk10[3].cal_DMOut_n_A_r_reg [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[3].cal_DMOut_n_A_r_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[28] ),
        .Q(\genblk10[3].cal_DMOut_n_A_r_reg [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[3].cal_DMOut_n_A_r_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[29] ),
        .Q(\genblk10[3].cal_DMOut_n_A_r_reg [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[3].cal_DMOut_n_A_r_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[30] ),
        .Q(\genblk10[3].cal_DMOut_n_A_r_reg [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[3].cal_DMOut_n_A_r_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[3].cal_DMOut_n_A_r_reg[24]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[31] ),
        .Q(\genblk10[3].cal_DMOut_n_A_r_reg [7]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[4].cal_DMOut_n_A_r_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[0] ),
        .Q(\genblk10[4].cal_DMOut_n_A_r_reg [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[4].cal_DMOut_n_A_r_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[1] ),
        .Q(\genblk10[4].cal_DMOut_n_A_r_reg [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[4].cal_DMOut_n_A_r_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[2] ),
        .Q(\genblk10[4].cal_DMOut_n_A_r_reg [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[4].cal_DMOut_n_A_r_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[3] ),
        .Q(\genblk10[4].cal_DMOut_n_A_r_reg [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[4].cal_DMOut_n_A_r_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[4] ),
        .Q(\genblk10[4].cal_DMOut_n_A_r_reg [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[4].cal_DMOut_n_A_r_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[5] ),
        .Q(\genblk10[4].cal_DMOut_n_A_r_reg [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[4].cal_DMOut_n_A_r_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[6] ),
        .Q(\genblk10[4].cal_DMOut_n_A_r_reg [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[4].cal_DMOut_n_A_r_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[7] ),
        .Q(\genblk10[4].cal_DMOut_n_A_r_reg [7]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[5].cal_DMOut_n_A_r_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[8] ),
        .Q(\genblk10[5].cal_DMOut_n_A_r_reg [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[5].cal_DMOut_n_A_r_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[9] ),
        .Q(\genblk10[5].cal_DMOut_n_A_r_reg [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[5].cal_DMOut_n_A_r_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[10] ),
        .Q(\genblk10[5].cal_DMOut_n_A_r_reg [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[5].cal_DMOut_n_A_r_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[11] ),
        .Q(\genblk10[5].cal_DMOut_n_A_r_reg [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[5].cal_DMOut_n_A_r_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[12] ),
        .Q(\genblk10[5].cal_DMOut_n_A_r_reg [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[5].cal_DMOut_n_A_r_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[13] ),
        .Q(\genblk10[5].cal_DMOut_n_A_r_reg [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[5].cal_DMOut_n_A_r_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[14] ),
        .Q(\genblk10[5].cal_DMOut_n_A_r_reg [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[5].cal_DMOut_n_A_r_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[15] ),
        .Q(\genblk10[5].cal_DMOut_n_A_r_reg [7]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[6].cal_DMOut_n_A_r_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[16] ),
        .Q(\genblk10[6].cal_DMOut_n_A_r_reg [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[6].cal_DMOut_n_A_r_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[17] ),
        .Q(\genblk10[6].cal_DMOut_n_A_r_reg [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[6].cal_DMOut_n_A_r_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[18] ),
        .Q(\genblk10[6].cal_DMOut_n_A_r_reg [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[6].cal_DMOut_n_A_r_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[19] ),
        .Q(\genblk10[6].cal_DMOut_n_A_r_reg [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[6].cal_DMOut_n_A_r_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[20] ),
        .Q(\genblk10[6].cal_DMOut_n_A_r_reg [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[6].cal_DMOut_n_A_r_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[21] ),
        .Q(\genblk10[6].cal_DMOut_n_A_r_reg [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[6].cal_DMOut_n_A_r_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[22] ),
        .Q(\genblk10[6].cal_DMOut_n_A_r_reg [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[6].cal_DMOut_n_A_r_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[23] ),
        .Q(\genblk10[6].cal_DMOut_n_A_r_reg [7]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[7].cal_DMOut_n_A_r_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[24] ),
        .Q(\genblk10[7].cal_DMOut_n_A_r_reg [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[7].cal_DMOut_n_A_r_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[25] ),
        .Q(\genblk10[7].cal_DMOut_n_A_r_reg [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[7].cal_DMOut_n_A_r_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[26] ),
        .Q(\genblk10[7].cal_DMOut_n_A_r_reg [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[7].cal_DMOut_n_A_r_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[27] ),
        .Q(\genblk10[7].cal_DMOut_n_A_r_reg [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[7].cal_DMOut_n_A_r_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[28] ),
        .Q(\genblk10[7].cal_DMOut_n_A_r_reg [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[7].cal_DMOut_n_A_r_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[29] ),
        .Q(\genblk10[7].cal_DMOut_n_A_r_reg [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[7].cal_DMOut_n_A_r_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[30] ),
        .Q(\genblk10[7].cal_DMOut_n_A_r_reg [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \genblk10[7].cal_DMOut_n_A_r_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\genblk10[6].cal_DMOut_n_A_r_reg[48]_0 ),
        .D(\cal_DMOut_n_A_reg_n_0_[31] ),
        .Q(\genblk10[7].cal_DMOut_n_A_r_reg [7]),
        .R(rst_r1));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[0].mcal_DQ0In_lrdimm_and_r[0]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[4] ),
        .I1(\mcal_DQIn_r_reg_n_0_[5] ),
        .I2(\mcal_DQIn_r_reg_n_0_[3] ),
        .I3(\genblk6[0].mcal_DQ0In_lrdimm_and_r[0]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_0));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[0].mcal_DQ0In_lrdimm_and_r[0]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[2] ),
        .I1(\mcal_DQIn_r_reg_n_0_[0] ),
        .I2(mcal_dq_cmp_lrdimm[32]),
        .I3(\mcal_DQIn_r_reg_n_0_[7] ),
        .I4(\mcal_DQIn_r_reg_n_0_[1] ),
        .I5(\mcal_DQIn_r_reg_n_0_[6] ),
        .O(\genblk6[0].mcal_DQ0In_lrdimm_and_r[0]_i_2_n_0 ));
  FDSE \genblk6[0].mcal_DQ0In_lrdimm_and_r_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_0),
        .Q(mcal_dq_cmp_lrdimm[32]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \genblk6[0].mcal_DQ0In_lrdimm_or_r[0]_i_1 
       (.I0(rst_r1),
        .I1(lrdimm_cmp_clr_reg_n_0),
        .O(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[0].mcal_DQ0In_lrdimm_or_r[0]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[4] ),
        .I1(\mcal_DQIn_r_reg_n_0_[5] ),
        .I2(\mcal_DQIn_r_reg_n_0_[3] ),
        .I3(\genblk6[0].mcal_DQ0In_lrdimm_or_r[0]_i_3_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[0].mcal_DQ0In_lrdimm_or_r[0]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[2] ),
        .I1(\mcal_DQIn_r_reg_n_0_[0] ),
        .I2(\mcal_DQIn_r_reg_n_0_[1] ),
        .I3(\mcal_DQIn_r_reg_n_0_[6] ),
        .I4(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_reg_n_0_[7] ),
        .O(\genblk6[0].mcal_DQ0In_lrdimm_or_r[0]_i_3_n_0 ));
  FDRE \genblk6[0].mcal_DQ0In_lrdimm_or_r_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_0),
        .Q(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg_n_0_[0] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[10].mcal_DQ0In_lrdimm_and_r[10]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[324] ),
        .I1(\mcal_DQIn_r_reg_n_0_[325] ),
        .I2(\mcal_DQIn_r_reg_n_0_[323] ),
        .I3(\genblk6[10].mcal_DQ0In_lrdimm_and_r[10]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_10));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[10].mcal_DQ0In_lrdimm_and_r[10]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[322] ),
        .I1(\mcal_DQIn_r_reg_n_0_[320] ),
        .I2(\mcal_DQIn_r_reg_n_0_[321] ),
        .I3(\mcal_DQIn_r_reg_n_0_[326] ),
        .I4(mcal_dq_cmp_lrdimm[42]),
        .I5(\mcal_DQIn_r_reg_n_0_[327] ),
        .O(\genblk6[10].mcal_DQ0In_lrdimm_and_r[10]_i_2_n_0 ));
  FDSE \genblk6[10].mcal_DQ0In_lrdimm_and_r_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_10),
        .Q(mcal_dq_cmp_lrdimm[42]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[10].mcal_DQ0In_lrdimm_or_r[10]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[324] ),
        .I1(\mcal_DQIn_r_reg_n_0_[325] ),
        .I2(\mcal_DQIn_r_reg_n_0_[323] ),
        .I3(\genblk6[10].mcal_DQ0In_lrdimm_or_r[10]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_10));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[10].mcal_DQ0In_lrdimm_or_r[10]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[322] ),
        .I1(\mcal_DQIn_r_reg_n_0_[320] ),
        .I2(\mcal_DQIn_r_reg_n_0_[321] ),
        .I3(\mcal_DQIn_r_reg_n_0_[326] ),
        .I4(\genblk6[10].mcal_DQ0In_lrdimm_or_r_reg_n_0_[10] ),
        .I5(\mcal_DQIn_r_reg_n_0_[327] ),
        .O(\genblk6[10].mcal_DQ0In_lrdimm_or_r[10]_i_2_n_0 ));
  FDRE \genblk6[10].mcal_DQ0In_lrdimm_or_r_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_10),
        .Q(\genblk6[10].mcal_DQ0In_lrdimm_or_r_reg_n_0_[10] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[11].mcal_DQ0In_lrdimm_and_r[11]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[356] ),
        .I1(\mcal_DQIn_r_reg_n_0_[357] ),
        .I2(\mcal_DQIn_r_reg_n_0_[355] ),
        .I3(\genblk6[11].mcal_DQ0In_lrdimm_and_r[11]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_11));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[11].mcal_DQ0In_lrdimm_and_r[11]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[354] ),
        .I1(\mcal_DQIn_r_reg_n_0_[352] ),
        .I2(mcal_dq_cmp_lrdimm[43]),
        .I3(\mcal_DQIn_r_reg_n_0_[359] ),
        .I4(\mcal_DQIn_r_reg_n_0_[353] ),
        .I5(\mcal_DQIn_r_reg_n_0_[358] ),
        .O(\genblk6[11].mcal_DQ0In_lrdimm_and_r[11]_i_2_n_0 ));
  FDSE \genblk6[11].mcal_DQ0In_lrdimm_and_r_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_11),
        .Q(mcal_dq_cmp_lrdimm[43]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[11].mcal_DQ0In_lrdimm_or_r[11]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[356] ),
        .I1(\mcal_DQIn_r_reg_n_0_[357] ),
        .I2(\mcal_DQIn_r_reg_n_0_[355] ),
        .I3(\genblk6[11].mcal_DQ0In_lrdimm_or_r[11]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_11));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[11].mcal_DQ0In_lrdimm_or_r[11]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[354] ),
        .I1(\mcal_DQIn_r_reg_n_0_[352] ),
        .I2(\mcal_DQIn_r_reg_n_0_[353] ),
        .I3(\mcal_DQIn_r_reg_n_0_[358] ),
        .I4(\genblk6[11].mcal_DQ0In_lrdimm_or_r_reg_n_0_[11] ),
        .I5(\mcal_DQIn_r_reg_n_0_[359] ),
        .O(\genblk6[11].mcal_DQ0In_lrdimm_or_r[11]_i_2_n_0 ));
  FDRE \genblk6[11].mcal_DQ0In_lrdimm_or_r_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_11),
        .Q(\genblk6[11].mcal_DQ0In_lrdimm_or_r_reg_n_0_[11] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[12].mcal_DQ0In_lrdimm_and_r[12]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[388] ),
        .I1(\mcal_DQIn_r_reg_n_0_[391] ),
        .I2(\mcal_DQIn_r_reg_n_0_[390] ),
        .I3(\genblk6[12].mcal_DQ0In_lrdimm_and_r[12]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_12));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[12].mcal_DQ0In_lrdimm_and_r[12]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[389] ),
        .I1(\mcal_DQIn_r_reg_n_0_[387] ),
        .I2(mcal_dq_cmp_lrdimm[44]),
        .I3(\mcal_DQIn_r_reg_n_0_[385] ),
        .I4(\mcal_DQIn_r_reg_n_0_[384] ),
        .I5(\mcal_DQIn_r_reg_n_0_[386] ),
        .O(\genblk6[12].mcal_DQ0In_lrdimm_and_r[12]_i_2_n_0 ));
  FDSE \genblk6[12].mcal_DQ0In_lrdimm_and_r_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_12),
        .Q(mcal_dq_cmp_lrdimm[44]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[12].mcal_DQ0In_lrdimm_or_r[12]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[388] ),
        .I1(\mcal_DQIn_r_reg_n_0_[389] ),
        .I2(\mcal_DQIn_r_reg_n_0_[387] ),
        .I3(\genblk6[12].mcal_DQ0In_lrdimm_or_r[12]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_12));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[12].mcal_DQ0In_lrdimm_or_r[12]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[386] ),
        .I1(\mcal_DQIn_r_reg_n_0_[384] ),
        .I2(\mcal_DQIn_r_reg_n_0_[385] ),
        .I3(\mcal_DQIn_r_reg_n_0_[390] ),
        .I4(\genblk6[12].mcal_DQ0In_lrdimm_or_r_reg_n_0_[12] ),
        .I5(\mcal_DQIn_r_reg_n_0_[391] ),
        .O(\genblk6[12].mcal_DQ0In_lrdimm_or_r[12]_i_2_n_0 ));
  FDRE \genblk6[12].mcal_DQ0In_lrdimm_or_r_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_12),
        .Q(\genblk6[12].mcal_DQ0In_lrdimm_or_r_reg_n_0_[12] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[13].mcal_DQ0In_lrdimm_and_r[13]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[420] ),
        .I1(\mcal_DQIn_r_reg_n_0_[423] ),
        .I2(\mcal_DQIn_r_reg_n_0_[422] ),
        .I3(\genblk6[13].mcal_DQ0In_lrdimm_and_r[13]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_13));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[13].mcal_DQ0In_lrdimm_and_r[13]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[421] ),
        .I1(\mcal_DQIn_r_reg_n_0_[419] ),
        .I2(mcal_dq_cmp_lrdimm[45]),
        .I3(\mcal_DQIn_r_reg_n_0_[417] ),
        .I4(\mcal_DQIn_r_reg_n_0_[416] ),
        .I5(\mcal_DQIn_r_reg_n_0_[418] ),
        .O(\genblk6[13].mcal_DQ0In_lrdimm_and_r[13]_i_2_n_0 ));
  FDSE \genblk6[13].mcal_DQ0In_lrdimm_and_r_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_13),
        .Q(mcal_dq_cmp_lrdimm[45]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[13].mcal_DQ0In_lrdimm_or_r[13]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[420] ),
        .I1(\mcal_DQIn_r_reg_n_0_[421] ),
        .I2(\mcal_DQIn_r_reg_n_0_[419] ),
        .I3(\genblk6[13].mcal_DQ0In_lrdimm_or_r[13]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_13));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[13].mcal_DQ0In_lrdimm_or_r[13]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[418] ),
        .I1(\mcal_DQIn_r_reg_n_0_[416] ),
        .I2(\mcal_DQIn_r_reg_n_0_[417] ),
        .I3(\mcal_DQIn_r_reg_n_0_[422] ),
        .I4(\genblk6[13].mcal_DQ0In_lrdimm_or_r_reg_n_0_[13] ),
        .I5(\mcal_DQIn_r_reg_n_0_[423] ),
        .O(\genblk6[13].mcal_DQ0In_lrdimm_or_r[13]_i_2_n_0 ));
  FDRE \genblk6[13].mcal_DQ0In_lrdimm_or_r_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_13),
        .Q(\genblk6[13].mcal_DQ0In_lrdimm_or_r_reg_n_0_[13] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[14].mcal_DQ0In_lrdimm_and_r[14]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[452] ),
        .I1(\mcal_DQIn_r_reg_n_0_[455] ),
        .I2(\mcal_DQIn_r_reg_n_0_[454] ),
        .I3(\genblk6[14].mcal_DQ0In_lrdimm_and_r[14]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_14));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[14].mcal_DQ0In_lrdimm_and_r[14]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[453] ),
        .I1(\mcal_DQIn_r_reg_n_0_[451] ),
        .I2(mcal_dq_cmp_lrdimm[46]),
        .I3(\mcal_DQIn_r_reg_n_0_[449] ),
        .I4(\mcal_DQIn_r_reg_n_0_[448] ),
        .I5(\mcal_DQIn_r_reg_n_0_[450] ),
        .O(\genblk6[14].mcal_DQ0In_lrdimm_and_r[14]_i_2_n_0 ));
  FDSE \genblk6[14].mcal_DQ0In_lrdimm_and_r_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_14),
        .Q(mcal_dq_cmp_lrdimm[46]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[14].mcal_DQ0In_lrdimm_or_r[14]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[452] ),
        .I1(\mcal_DQIn_r_reg_n_0_[453] ),
        .I2(\mcal_DQIn_r_reg_n_0_[451] ),
        .I3(\genblk6[14].mcal_DQ0In_lrdimm_or_r[14]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_14));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[14].mcal_DQ0In_lrdimm_or_r[14]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[450] ),
        .I1(\mcal_DQIn_r_reg_n_0_[448] ),
        .I2(\mcal_DQIn_r_reg_n_0_[449] ),
        .I3(\mcal_DQIn_r_reg_n_0_[454] ),
        .I4(\genblk6[14].mcal_DQ0In_lrdimm_or_r_reg_n_0_[14] ),
        .I5(\mcal_DQIn_r_reg_n_0_[455] ),
        .O(\genblk6[14].mcal_DQ0In_lrdimm_or_r[14]_i_2_n_0 ));
  FDRE \genblk6[14].mcal_DQ0In_lrdimm_or_r_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_14),
        .Q(\genblk6[14].mcal_DQ0In_lrdimm_or_r_reg_n_0_[14] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[15].mcal_DQ0In_lrdimm_and_r[15]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[484] ),
        .I1(\mcal_DQIn_r_reg_n_0_[487] ),
        .I2(\mcal_DQIn_r_reg_n_0_[486] ),
        .I3(\genblk6[15].mcal_DQ0In_lrdimm_and_r[15]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_15));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[15].mcal_DQ0In_lrdimm_and_r[15]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[485] ),
        .I1(\mcal_DQIn_r_reg_n_0_[483] ),
        .I2(mcal_dq_cmp_lrdimm[47]),
        .I3(\mcal_DQIn_r_reg_n_0_[481] ),
        .I4(\mcal_DQIn_r_reg_n_0_[480] ),
        .I5(\mcal_DQIn_r_reg_n_0_[482] ),
        .O(\genblk6[15].mcal_DQ0In_lrdimm_and_r[15]_i_2_n_0 ));
  FDSE \genblk6[15].mcal_DQ0In_lrdimm_and_r_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_15),
        .Q(mcal_dq_cmp_lrdimm[47]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[15].mcal_DQ0In_lrdimm_or_r[15]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[484] ),
        .I1(\mcal_DQIn_r_reg_n_0_[485] ),
        .I2(\mcal_DQIn_r_reg_n_0_[483] ),
        .I3(\genblk6[15].mcal_DQ0In_lrdimm_or_r[15]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_15));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[15].mcal_DQ0In_lrdimm_or_r[15]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[482] ),
        .I1(\mcal_DQIn_r_reg_n_0_[480] ),
        .I2(\mcal_DQIn_r_reg_n_0_[481] ),
        .I3(\mcal_DQIn_r_reg_n_0_[486] ),
        .I4(\genblk6[15].mcal_DQ0In_lrdimm_or_r_reg_n_0_[15] ),
        .I5(\mcal_DQIn_r_reg_n_0_[487] ),
        .O(\genblk6[15].mcal_DQ0In_lrdimm_or_r[15]_i_2_n_0 ));
  FDRE \genblk6[15].mcal_DQ0In_lrdimm_or_r_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_15),
        .Q(\genblk6[15].mcal_DQ0In_lrdimm_or_r_reg_n_0_[15] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[1].mcal_DQ0In_lrdimm_and_r[1]_i_1 
       (.I0(p_0_in[4]),
        .I1(p_0_in[5]),
        .I2(p_0_in[3]),
        .I3(\genblk6[1].mcal_DQ0In_lrdimm_and_r[1]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_1));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[1].mcal_DQ0In_lrdimm_and_r[1]_i_2 
       (.I0(p_0_in[2]),
        .I1(p_0_in[0]),
        .I2(mcal_dq_cmp_lrdimm[33]),
        .I3(p_0_in[7]),
        .I4(p_0_in[1]),
        .I5(p_0_in[6]),
        .O(\genblk6[1].mcal_DQ0In_lrdimm_and_r[1]_i_2_n_0 ));
  FDSE \genblk6[1].mcal_DQ0In_lrdimm_and_r_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_1),
        .Q(mcal_dq_cmp_lrdimm[33]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[1].mcal_DQ0In_lrdimm_or_r[1]_i_1 
       (.I0(p_0_in[4]),
        .I1(p_0_in[5]),
        .I2(p_0_in[3]),
        .I3(\genblk6[1].mcal_DQ0In_lrdimm_or_r[1]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_1));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[1].mcal_DQ0In_lrdimm_or_r[1]_i_2 
       (.I0(p_0_in[2]),
        .I1(p_0_in[0]),
        .I2(p_0_in[1]),
        .I3(p_0_in[6]),
        .I4(\genblk6[1].mcal_DQ0In_lrdimm_or_r_reg_n_0_[1] ),
        .I5(p_0_in[7]),
        .O(\genblk6[1].mcal_DQ0In_lrdimm_or_r[1]_i_2_n_0 ));
  FDRE \genblk6[1].mcal_DQ0In_lrdimm_or_r_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_1),
        .Q(\genblk6[1].mcal_DQ0In_lrdimm_or_r_reg_n_0_[1] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[2].mcal_DQ0In_lrdimm_and_r[2]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[68] ),
        .I1(\mcal_DQIn_r_reg_n_0_[69] ),
        .I2(\mcal_DQIn_r_reg_n_0_[67] ),
        .I3(\genblk6[2].mcal_DQ0In_lrdimm_and_r[2]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_2));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[2].mcal_DQ0In_lrdimm_and_r[2]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[66] ),
        .I1(\mcal_DQIn_r_reg_n_0_[64] ),
        .I2(mcal_dq_cmp_lrdimm[34]),
        .I3(\mcal_DQIn_r_reg_n_0_[71] ),
        .I4(\mcal_DQIn_r_reg_n_0_[65] ),
        .I5(\mcal_DQIn_r_reg_n_0_[70] ),
        .O(\genblk6[2].mcal_DQ0In_lrdimm_and_r[2]_i_2_n_0 ));
  FDSE \genblk6[2].mcal_DQ0In_lrdimm_and_r_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_2),
        .Q(mcal_dq_cmp_lrdimm[34]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[2].mcal_DQ0In_lrdimm_or_r[2]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[68] ),
        .I1(\mcal_DQIn_r_reg_n_0_[69] ),
        .I2(\mcal_DQIn_r_reg_n_0_[67] ),
        .I3(\genblk6[2].mcal_DQ0In_lrdimm_or_r[2]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_2));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[2].mcal_DQ0In_lrdimm_or_r[2]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[66] ),
        .I1(\mcal_DQIn_r_reg_n_0_[64] ),
        .I2(\mcal_DQIn_r_reg_n_0_[65] ),
        .I3(\mcal_DQIn_r_reg_n_0_[70] ),
        .I4(\genblk6[2].mcal_DQ0In_lrdimm_or_r_reg_n_0_[2] ),
        .I5(\mcal_DQIn_r_reg_n_0_[71] ),
        .O(\genblk6[2].mcal_DQ0In_lrdimm_or_r[2]_i_2_n_0 ));
  FDRE \genblk6[2].mcal_DQ0In_lrdimm_or_r_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_2),
        .Q(\genblk6[2].mcal_DQ0In_lrdimm_or_r_reg_n_0_[2] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[3].mcal_DQ0In_lrdimm_and_r[3]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[100] ),
        .I1(\mcal_DQIn_r_reg_n_0_[101] ),
        .I2(\mcal_DQIn_r_reg_n_0_[99] ),
        .I3(\genblk6[3].mcal_DQ0In_lrdimm_and_r[3]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_3));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[3].mcal_DQ0In_lrdimm_and_r[3]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[98] ),
        .I1(\mcal_DQIn_r_reg_n_0_[96] ),
        .I2(\mcal_DQIn_r_reg_n_0_[97] ),
        .I3(\mcal_DQIn_r_reg_n_0_[102] ),
        .I4(mcal_dq_cmp_lrdimm[35]),
        .I5(\mcal_DQIn_r_reg_n_0_[103] ),
        .O(\genblk6[3].mcal_DQ0In_lrdimm_and_r[3]_i_2_n_0 ));
  FDSE \genblk6[3].mcal_DQ0In_lrdimm_and_r_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_3),
        .Q(mcal_dq_cmp_lrdimm[35]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[3].mcal_DQ0In_lrdimm_or_r[3]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[100] ),
        .I1(\mcal_DQIn_r_reg_n_0_[101] ),
        .I2(\mcal_DQIn_r_reg_n_0_[99] ),
        .I3(\genblk6[3].mcal_DQ0In_lrdimm_or_r[3]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_3));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[3].mcal_DQ0In_lrdimm_or_r[3]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[98] ),
        .I1(\mcal_DQIn_r_reg_n_0_[96] ),
        .I2(\mcal_DQIn_r_reg_n_0_[97] ),
        .I3(\mcal_DQIn_r_reg_n_0_[102] ),
        .I4(\genblk6[3].mcal_DQ0In_lrdimm_or_r_reg_n_0_[3] ),
        .I5(\mcal_DQIn_r_reg_n_0_[103] ),
        .O(\genblk6[3].mcal_DQ0In_lrdimm_or_r[3]_i_2_n_0 ));
  FDRE \genblk6[3].mcal_DQ0In_lrdimm_or_r_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_3),
        .Q(\genblk6[3].mcal_DQ0In_lrdimm_or_r_reg_n_0_[3] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[4].mcal_DQ0In_lrdimm_and_r[4]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[132] ),
        .I1(\mcal_DQIn_r_reg_n_0_[135] ),
        .I2(\mcal_DQIn_r_reg_n_0_[134] ),
        .I3(\genblk6[4].mcal_DQ0In_lrdimm_and_r[4]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_4));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[4].mcal_DQ0In_lrdimm_and_r[4]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[133] ),
        .I1(\mcal_DQIn_r_reg_n_0_[131] ),
        .I2(mcal_dq_cmp_lrdimm[36]),
        .I3(\mcal_DQIn_r_reg_n_0_[129] ),
        .I4(\mcal_DQIn_r_reg_n_0_[128] ),
        .I5(\mcal_DQIn_r_reg_n_0_[130] ),
        .O(\genblk6[4].mcal_DQ0In_lrdimm_and_r[4]_i_2_n_0 ));
  FDSE \genblk6[4].mcal_DQ0In_lrdimm_and_r_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_4),
        .Q(mcal_dq_cmp_lrdimm[36]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[4].mcal_DQ0In_lrdimm_or_r[4]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[132] ),
        .I1(\mcal_DQIn_r_reg_n_0_[133] ),
        .I2(\mcal_DQIn_r_reg_n_0_[131] ),
        .I3(\genblk6[4].mcal_DQ0In_lrdimm_or_r[4]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_4));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[4].mcal_DQ0In_lrdimm_or_r[4]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[130] ),
        .I1(\mcal_DQIn_r_reg_n_0_[128] ),
        .I2(\mcal_DQIn_r_reg_n_0_[129] ),
        .I3(\mcal_DQIn_r_reg_n_0_[134] ),
        .I4(\genblk6[4].mcal_DQ0In_lrdimm_or_r_reg_n_0_[4] ),
        .I5(\mcal_DQIn_r_reg_n_0_[135] ),
        .O(\genblk6[4].mcal_DQ0In_lrdimm_or_r[4]_i_2_n_0 ));
  FDRE \genblk6[4].mcal_DQ0In_lrdimm_or_r_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_4),
        .Q(\genblk6[4].mcal_DQ0In_lrdimm_or_r_reg_n_0_[4] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[5].mcal_DQ0In_lrdimm_and_r[5]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[164] ),
        .I1(\mcal_DQIn_r_reg_n_0_[167] ),
        .I2(\mcal_DQIn_r_reg_n_0_[166] ),
        .I3(\genblk6[5].mcal_DQ0In_lrdimm_and_r[5]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_5));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[5].mcal_DQ0In_lrdimm_and_r[5]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[165] ),
        .I1(\mcal_DQIn_r_reg_n_0_[163] ),
        .I2(mcal_dq_cmp_lrdimm[37]),
        .I3(\mcal_DQIn_r_reg_n_0_[161] ),
        .I4(\mcal_DQIn_r_reg_n_0_[160] ),
        .I5(\mcal_DQIn_r_reg_n_0_[162] ),
        .O(\genblk6[5].mcal_DQ0In_lrdimm_and_r[5]_i_2_n_0 ));
  FDSE \genblk6[5].mcal_DQ0In_lrdimm_and_r_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_5),
        .Q(mcal_dq_cmp_lrdimm[37]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[5].mcal_DQ0In_lrdimm_or_r[5]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[164] ),
        .I1(\mcal_DQIn_r_reg_n_0_[165] ),
        .I2(\mcal_DQIn_r_reg_n_0_[163] ),
        .I3(\genblk6[5].mcal_DQ0In_lrdimm_or_r[5]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_5));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[5].mcal_DQ0In_lrdimm_or_r[5]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[162] ),
        .I1(\mcal_DQIn_r_reg_n_0_[160] ),
        .I2(\mcal_DQIn_r_reg_n_0_[161] ),
        .I3(\mcal_DQIn_r_reg_n_0_[166] ),
        .I4(\genblk6[5].mcal_DQ0In_lrdimm_or_r_reg_n_0_[5] ),
        .I5(\mcal_DQIn_r_reg_n_0_[167] ),
        .O(\genblk6[5].mcal_DQ0In_lrdimm_or_r[5]_i_2_n_0 ));
  FDRE \genblk6[5].mcal_DQ0In_lrdimm_or_r_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_5),
        .Q(\genblk6[5].mcal_DQ0In_lrdimm_or_r_reg_n_0_[5] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[6].mcal_DQ0In_lrdimm_and_r[6]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[196] ),
        .I1(\mcal_DQIn_r_reg_n_0_[197] ),
        .I2(\mcal_DQIn_r_reg_n_0_[195] ),
        .I3(\genblk6[6].mcal_DQ0In_lrdimm_and_r[6]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_6));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[6].mcal_DQ0In_lrdimm_and_r[6]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[194] ),
        .I1(\mcal_DQIn_r_reg_n_0_[192] ),
        .I2(\mcal_DQIn_r_reg_n_0_[193] ),
        .I3(\mcal_DQIn_r_reg_n_0_[198] ),
        .I4(mcal_dq_cmp_lrdimm[38]),
        .I5(\mcal_DQIn_r_reg_n_0_[199] ),
        .O(\genblk6[6].mcal_DQ0In_lrdimm_and_r[6]_i_2_n_0 ));
  FDSE \genblk6[6].mcal_DQ0In_lrdimm_and_r_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_6),
        .Q(mcal_dq_cmp_lrdimm[38]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[6].mcal_DQ0In_lrdimm_or_r[6]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[196] ),
        .I1(\mcal_DQIn_r_reg_n_0_[197] ),
        .I2(\mcal_DQIn_r_reg_n_0_[195] ),
        .I3(\genblk6[6].mcal_DQ0In_lrdimm_or_r[6]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_6));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[6].mcal_DQ0In_lrdimm_or_r[6]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[194] ),
        .I1(\mcal_DQIn_r_reg_n_0_[192] ),
        .I2(\mcal_DQIn_r_reg_n_0_[193] ),
        .I3(\mcal_DQIn_r_reg_n_0_[198] ),
        .I4(\genblk6[6].mcal_DQ0In_lrdimm_or_r_reg_n_0_[6] ),
        .I5(\mcal_DQIn_r_reg_n_0_[199] ),
        .O(\genblk6[6].mcal_DQ0In_lrdimm_or_r[6]_i_2_n_0 ));
  FDRE \genblk6[6].mcal_DQ0In_lrdimm_or_r_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_6),
        .Q(\genblk6[6].mcal_DQ0In_lrdimm_or_r_reg_n_0_[6] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[7].mcal_DQ0In_lrdimm_and_r[7]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[228] ),
        .I1(\mcal_DQIn_r_reg_n_0_[229] ),
        .I2(\mcal_DQIn_r_reg_n_0_[227] ),
        .I3(\genblk6[7].mcal_DQ0In_lrdimm_and_r[7]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_7));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[7].mcal_DQ0In_lrdimm_and_r[7]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[226] ),
        .I1(\mcal_DQIn_r_reg_n_0_[224] ),
        .I2(mcal_dq_cmp_lrdimm[39]),
        .I3(\mcal_DQIn_r_reg_n_0_[231] ),
        .I4(\mcal_DQIn_r_reg_n_0_[225] ),
        .I5(\mcal_DQIn_r_reg_n_0_[230] ),
        .O(\genblk6[7].mcal_DQ0In_lrdimm_and_r[7]_i_2_n_0 ));
  FDSE \genblk6[7].mcal_DQ0In_lrdimm_and_r_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_7),
        .Q(mcal_dq_cmp_lrdimm[39]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[7].mcal_DQ0In_lrdimm_or_r[7]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[228] ),
        .I1(\mcal_DQIn_r_reg_n_0_[229] ),
        .I2(\mcal_DQIn_r_reg_n_0_[227] ),
        .I3(\genblk6[7].mcal_DQ0In_lrdimm_or_r[7]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_7));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[7].mcal_DQ0In_lrdimm_or_r[7]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[226] ),
        .I1(\mcal_DQIn_r_reg_n_0_[224] ),
        .I2(\mcal_DQIn_r_reg_n_0_[225] ),
        .I3(\mcal_DQIn_r_reg_n_0_[230] ),
        .I4(\genblk6[7].mcal_DQ0In_lrdimm_or_r_reg_n_0_[7] ),
        .I5(\mcal_DQIn_r_reg_n_0_[231] ),
        .O(\genblk6[7].mcal_DQ0In_lrdimm_or_r[7]_i_2_n_0 ));
  FDRE \genblk6[7].mcal_DQ0In_lrdimm_or_r_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_7),
        .Q(\genblk6[7].mcal_DQ0In_lrdimm_or_r_reg_n_0_[7] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[8].mcal_DQ0In_lrdimm_and_r[8]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[260] ),
        .I1(\mcal_DQIn_r_reg_n_0_[261] ),
        .I2(\mcal_DQIn_r_reg_n_0_[259] ),
        .I3(\genblk6[8].mcal_DQ0In_lrdimm_and_r[8]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_8));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[8].mcal_DQ0In_lrdimm_and_r[8]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[258] ),
        .I1(\mcal_DQIn_r_reg_n_0_[256] ),
        .I2(\mcal_DQIn_r_reg_n_0_[257] ),
        .I3(\mcal_DQIn_r_reg_n_0_[262] ),
        .I4(mcal_dq_cmp_lrdimm[40]),
        .I5(\mcal_DQIn_r_reg_n_0_[263] ),
        .O(\genblk6[8].mcal_DQ0In_lrdimm_and_r[8]_i_2_n_0 ));
  FDSE \genblk6[8].mcal_DQ0In_lrdimm_and_r_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_8),
        .Q(mcal_dq_cmp_lrdimm[40]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[8].mcal_DQ0In_lrdimm_or_r[8]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[260] ),
        .I1(\mcal_DQIn_r_reg_n_0_[261] ),
        .I2(\mcal_DQIn_r_reg_n_0_[259] ),
        .I3(\genblk6[8].mcal_DQ0In_lrdimm_or_r[8]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_8));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[8].mcal_DQ0In_lrdimm_or_r[8]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[258] ),
        .I1(\mcal_DQIn_r_reg_n_0_[256] ),
        .I2(\mcal_DQIn_r_reg_n_0_[257] ),
        .I3(\mcal_DQIn_r_reg_n_0_[262] ),
        .I4(\genblk6[8].mcal_DQ0In_lrdimm_or_r_reg_n_0_[8] ),
        .I5(\mcal_DQIn_r_reg_n_0_[263] ),
        .O(\genblk6[8].mcal_DQ0In_lrdimm_or_r[8]_i_2_n_0 ));
  FDRE \genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_8),
        .Q(\genblk6[8].mcal_DQ0In_lrdimm_or_r_reg_n_0_[8] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'h0080)) 
    \genblk6[9].mcal_DQ0In_lrdimm_and_r[9]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[292] ),
        .I1(\mcal_DQIn_r_reg_n_0_[293] ),
        .I2(\mcal_DQIn_r_reg_n_0_[291] ),
        .I3(\genblk6[9].mcal_DQ0In_lrdimm_and_r[9]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_and_9));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \genblk6[9].mcal_DQ0In_lrdimm_and_r[9]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[290] ),
        .I1(\mcal_DQIn_r_reg_n_0_[288] ),
        .I2(mcal_dq_cmp_lrdimm[41]),
        .I3(\mcal_DQIn_r_reg_n_0_[295] ),
        .I4(\mcal_DQIn_r_reg_n_0_[289] ),
        .I5(\mcal_DQIn_r_reg_n_0_[294] ),
        .O(\genblk6[9].mcal_DQ0In_lrdimm_and_r[9]_i_2_n_0 ));
  FDSE \genblk6[9].mcal_DQ0In_lrdimm_and_r_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_and_9),
        .Q(mcal_dq_cmp_lrdimm[41]),
        .S(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk6[9].mcal_DQ0In_lrdimm_or_r[9]_i_1 
       (.I0(\mcal_DQIn_r_reg_n_0_[292] ),
        .I1(\mcal_DQIn_r_reg_n_0_[293] ),
        .I2(\mcal_DQIn_r_reg_n_0_[291] ),
        .I3(\genblk6[9].mcal_DQ0In_lrdimm_or_r[9]_i_2_n_0 ),
        .O(mcal_DQ0In_lrdimm_or_9));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \genblk6[9].mcal_DQ0In_lrdimm_or_r[9]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[290] ),
        .I1(\mcal_DQIn_r_reg_n_0_[288] ),
        .I2(\mcal_DQIn_r_reg_n_0_[289] ),
        .I3(\mcal_DQIn_r_reg_n_0_[294] ),
        .I4(\genblk6[9].mcal_DQ0In_lrdimm_or_r_reg_n_0_[9] ),
        .I5(\mcal_DQIn_r_reg_n_0_[295] ),
        .O(\genblk6[9].mcal_DQ0In_lrdimm_or_r[9]_i_2_n_0 ));
  FDRE \genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cmp_en_reg_0),
        .D(mcal_DQ0In_lrdimm_or_9),
        .Q(\genblk6[9].mcal_DQ0In_lrdimm_or_r_reg_n_0_[9] ),
        .R(\genblk6[0].mcal_DQ0In_lrdimm_or_r_reg0 ));
  FDRE gt_data_ready_flag_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(gt_data_ready_flag_nxt),
        .Q(gt_data_ready_flag),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hFFFFF7FF000F0000)) 
    \init_cal_RESET_n[7]_i_1 
       (.I0(ub_initDone_reg_0),
        .I1(pllGate),
        .I2(\init_cal_RESET_n_reg[7] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(init_cal_RESET_n),
        .O(ub_initDone_reg_1));
  FDRE io_addr_strobe_r1_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(io_addr_strobe_r1_reg_0),
        .Q(io_addr_strobe_r1),
        .R(1'b0));
  FDRE io_addr_strobe_r2_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(io_addr_strobe_r1),
        .Q(io_addr_strobe_r2),
        .R(1'b0));
  FDRE \io_read_data_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[0] ),
        .Q(\io_read_data_reg[31]_0 [0]),
        .R(1'b0));
  FDRE \io_read_data_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[10] ),
        .Q(\io_read_data_reg[31]_0 [10]),
        .R(1'b0));
  FDRE \io_read_data_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[11] ),
        .Q(\io_read_data_reg[31]_0 [11]),
        .R(1'b0));
  FDRE \io_read_data_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[12] ),
        .Q(\io_read_data_reg[31]_0 [12]),
        .R(1'b0));
  FDRE \io_read_data_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[13] ),
        .Q(\io_read_data_reg[31]_0 [13]),
        .R(1'b0));
  FDRE \io_read_data_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[14] ),
        .Q(\io_read_data_reg[31]_0 [14]),
        .R(1'b0));
  FDRE \io_read_data_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[15] ),
        .Q(\io_read_data_reg[31]_0 [15]),
        .R(1'b0));
  FDRE \io_read_data_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[16] ),
        .Q(\io_read_data_reg[31]_0 [16]),
        .R(1'b0));
  FDRE \io_read_data_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[17] ),
        .Q(\io_read_data_reg[31]_0 [17]),
        .R(1'b0));
  FDRE \io_read_data_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[18] ),
        .Q(\io_read_data_reg[31]_0 [18]),
        .R(1'b0));
  FDRE \io_read_data_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[19] ),
        .Q(\io_read_data_reg[31]_0 [19]),
        .R(1'b0));
  FDRE \io_read_data_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[1] ),
        .Q(\io_read_data_reg[31]_0 [1]),
        .R(1'b0));
  FDRE \io_read_data_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[20] ),
        .Q(\io_read_data_reg[31]_0 [20]),
        .R(1'b0));
  FDRE \io_read_data_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[21] ),
        .Q(\io_read_data_reg[31]_0 [21]),
        .R(1'b0));
  FDRE \io_read_data_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[22] ),
        .Q(\io_read_data_reg[31]_0 [22]),
        .R(1'b0));
  FDRE \io_read_data_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[23] ),
        .Q(\io_read_data_reg[31]_0 [23]),
        .R(1'b0));
  FDRE \io_read_data_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[24] ),
        .Q(\io_read_data_reg[31]_0 [24]),
        .R(1'b0));
  FDRE \io_read_data_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[25] ),
        .Q(\io_read_data_reg[31]_0 [25]),
        .R(1'b0));
  FDRE \io_read_data_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[26] ),
        .Q(\io_read_data_reg[31]_0 [26]),
        .R(1'b0));
  FDRE \io_read_data_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[27] ),
        .Q(\io_read_data_reg[31]_0 [27]),
        .R(1'b0));
  FDRE \io_read_data_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[28] ),
        .Q(\io_read_data_reg[31]_0 [28]),
        .R(1'b0));
  FDRE \io_read_data_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[29] ),
        .Q(\io_read_data_reg[31]_0 [29]),
        .R(1'b0));
  FDRE \io_read_data_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[2] ),
        .Q(\io_read_data_reg[31]_0 [2]),
        .R(1'b0));
  FDRE \io_read_data_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[30] ),
        .Q(\io_read_data_reg[31]_0 [30]),
        .R(1'b0));
  FDRE \io_read_data_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[31] ),
        .Q(\io_read_data_reg[31]_0 [31]),
        .R(1'b0));
  FDRE \io_read_data_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[3] ),
        .Q(\io_read_data_reg[31]_0 [3]),
        .R(1'b0));
  FDRE \io_read_data_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[4] ),
        .Q(\io_read_data_reg[31]_0 [4]),
        .R(1'b0));
  FDRE \io_read_data_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[5] ),
        .Q(\io_read_data_reg[31]_0 [5]),
        .R(1'b0));
  FDRE \io_read_data_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[6] ),
        .Q(\io_read_data_reg[31]_0 [6]),
        .R(1'b0));
  FDRE \io_read_data_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[7] ),
        .Q(\io_read_data_reg[31]_0 [7]),
        .R(1'b0));
  FDRE \io_read_data_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[8] ),
        .Q(\io_read_data_reg[31]_0 [8]),
        .R(1'b0));
  FDRE \io_read_data_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(\addr_dec_to_mb_data_reg_n_0_[9] ),
        .Q(\io_read_data_reg[31]_0 [9]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hBF80FFFFBF800000)) 
    io_ready_i_1
       (.I0(io_addr_strobe_r2),
        .I1(io_ready_reg_0),
        .I2(io_ready_reg_1),
        .I3(io_addr_strobe_r1_reg_0),
        .I4(io_ready_reg_2),
        .I5(config_rd_val),
        .O(io_ready_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    io_ready_lvl_i_1
       (.I0(io_ready_lvl_reg_0),
        .O(io_ready_lvl_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    io_ready_lvl_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(io_ready),
        .D(io_ready_lvl_i_1_n_0),
        .Q(io_ready_lvl_reg_0),
        .R(1'b0));
  FDRE io_ready_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(io_ready_i_1_n_0),
        .Q(io_ready),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair1386" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL0[32]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_2 ),
        .I1(io_address[0]),
        .I2(io_write_data[2]),
        .O(lowCL00[32]));
  (* SOFT_HLUTNM = "soft_lutpair1386" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL0[33]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1] ),
        .I1(io_address[0]),
        .I2(io_write_data[3]),
        .O(lowCL00[33]));
  (* SOFT_HLUTNM = "soft_lutpair1171" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL0[36]_i_1 
       (.I0(\lowCL0_reg[42]_i_2_n_0 ),
        .I1(io_address[0]),
        .I2(io_write_data[0]),
        .O(lowCL00[36]));
  (* SOFT_HLUTNM = "soft_lutpair1164" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL0[37]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_0 ),
        .I1(io_address[0]),
        .I2(io_write_data[1]),
        .O(lowCL00[37]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \lowCL0[42]_i_1 
       (.I0(\lowCL0_reg[42]_i_2_n_0 ),
        .I1(io_address[0]),
        .I2(io_write_data[0]),
        .I3(\SYNC[3].sync_reg_reg[1]_2 ),
        .I4(io_write_data[2]),
        .I5(io_address[1]),
        .O(lowCL00[42]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL0[42]_i_3 
       (.I0(\lowCL0_reg[45]_0 [12]),
        .I1(\lowCL0_reg[45]_0 [8]),
        .I2(io_address[2]),
        .I3(\lowCL0_reg[45]_0 [4]),
        .I4(io_address[1]),
        .I5(\lowCL0_reg[45]_0 [0]),
        .O(\lowCL0[42]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL0[42]_i_4 
       (.I0(\lowCL0_reg[45]_0 [28]),
        .I1(\lowCL0_reg[45]_0 [24]),
        .I2(io_address[2]),
        .I3(\lowCL0_reg[45]_0 [20]),
        .I4(io_address[1]),
        .I5(\lowCL0_reg[45]_0 [16]),
        .O(\lowCL0[42]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \lowCL0[43]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_0 ),
        .I1(io_address[0]),
        .I2(io_write_data[1]),
        .I3(\SYNC[3].sync_reg_reg[1] ),
        .I4(io_write_data[3]),
        .I5(io_address[1]),
        .O(lowCL00[43]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL0[43]_i_3 
       (.I0(\lowCL0_reg[45]_0 [13]),
        .I1(\lowCL0_reg[45]_0 [9]),
        .I2(io_address[2]),
        .I3(\lowCL0_reg[45]_0 [5]),
        .I4(io_address[1]),
        .I5(\lowCL0_reg[45]_0 [1]),
        .O(\lowCL0[43]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL0[43]_i_4 
       (.I0(\lowCL0_reg[45]_0 [29]),
        .I1(\lowCL0_reg[45]_0 [25]),
        .I2(io_address[2]),
        .I3(\lowCL0_reg[45]_0 [21]),
        .I4(io_address[1]),
        .I5(\lowCL0_reg[45]_0 [17]),
        .O(\lowCL0[43]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \lowCL0[44]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_3 ),
        .I1(io_address[0]),
        .I2(io_write_data[4]),
        .I3(\SYNC[3].sync_reg_reg[1]_2 ),
        .I4(io_write_data[2]),
        .I5(io_address[1]),
        .O(lowCL00[44]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL0[44]_i_3 
       (.I0(\lowCL0_reg[45]_0 [14]),
        .I1(\lowCL0_reg[45]_0 [10]),
        .I2(io_address[2]),
        .I3(\lowCL0_reg[45]_0 [6]),
        .I4(io_address[1]),
        .I5(\lowCL0_reg[45]_0 [2]),
        .O(\lowCL0[44]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL0[44]_i_4 
       (.I0(\lowCL0_reg[45]_0 [30]),
        .I1(\lowCL0_reg[45]_0 [26]),
        .I2(io_address[2]),
        .I3(\lowCL0_reg[45]_0 [22]),
        .I4(io_address[1]),
        .I5(\lowCL0_reg[45]_0 [18]),
        .O(\lowCL0[44]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \lowCL0[45]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_1 ),
        .I1(io_address[0]),
        .I2(io_write_data[5]),
        .I3(\SYNC[3].sync_reg_reg[1] ),
        .I4(io_write_data[3]),
        .I5(io_address[1]),
        .O(lowCL00[45]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL0[45]_i_3 
       (.I0(\lowCL0_reg[45]_0 [15]),
        .I1(\lowCL0_reg[45]_0 [11]),
        .I2(io_address[2]),
        .I3(\lowCL0_reg[45]_0 [7]),
        .I4(io_address[1]),
        .I5(\lowCL0_reg[45]_0 [3]),
        .O(\lowCL0[45]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL0[45]_i_4 
       (.I0(\lowCL0_reg[45]_0 [31]),
        .I1(\lowCL0_reg[45]_0 [27]),
        .I2(io_address[2]),
        .I3(\lowCL0_reg[45]_0 [23]),
        .I4(io_address[1]),
        .I5(\lowCL0_reg[45]_0 [19]),
        .O(\lowCL0[45]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1164" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL0[46]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_3 ),
        .I1(io_address[0]),
        .I2(io_write_data[4]),
        .O(lowCL00[46]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL0[46]_i_3 
       (.I0(\lowCL0_reg_n_0_[22] ),
        .I1(\lowCL0_reg_n_0_[16] ),
        .I2(io_address[2]),
        .I3(\lowCL0_reg_n_0_[10] ),
        .I4(io_address[1]),
        .I5(\lowCL0_reg_n_0_[4] ),
        .O(\lowCL0[46]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL0[46]_i_4 
       (.I0(\lowCL0_reg_n_0_[46] ),
        .I1(\lowCL0_reg_n_0_[40] ),
        .I2(io_address[2]),
        .I3(\lowCL0_reg_n_0_[34] ),
        .I4(io_address[1]),
        .I5(\lowCL0_reg_n_0_[28] ),
        .O(\lowCL0[46]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1165" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL0[47]_i_2 
       (.I0(\SYNC[3].sync_reg_reg[1]_1 ),
        .I1(io_address[0]),
        .I2(io_write_data[5]),
        .O(lowCL00[47]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL0[47]_i_6 
       (.I0(\lowCL0_reg_n_0_[23] ),
        .I1(\lowCL0_reg_n_0_[17] ),
        .I2(io_address[2]),
        .I3(\lowCL0_reg_n_0_[11] ),
        .I4(io_address[1]),
        .I5(\lowCL0_reg_n_0_[5] ),
        .O(\lowCL0[47]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL0[47]_i_7 
       (.I0(\lowCL0_reg_n_0_[47] ),
        .I1(\lowCL0_reg_n_0_[41] ),
        .I2(io_address[2]),
        .I3(\lowCL0_reg_n_0_[35] ),
        .I4(io_address[1]),
        .I5(\lowCL0_reg_n_0_[29] ),
        .O(\lowCL0[47]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL00[36]),
        .Q(\lowCL0_reg[45]_0 [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL00[46]),
        .Q(\lowCL0_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL00[47]),
        .Q(\lowCL0_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL00[36]),
        .Q(\lowCL0_reg[45]_0 [8]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL00[37]),
        .Q(\lowCL0_reg[45]_0 [9]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL00[42]),
        .Q(\lowCL0_reg[45]_0 [10]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL00[43]),
        .Q(\lowCL0_reg[45]_0 [11]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL00[44]),
        .Q(\lowCL0_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL00[45]),
        .Q(\lowCL0_reg_n_0_[17] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL00[42]),
        .Q(\lowCL0_reg[45]_0 [12]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL00[43]),
        .Q(\lowCL0_reg[45]_0 [13]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL00[37]),
        .Q(\lowCL0_reg[45]_0 [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL00[44]),
        .Q(\lowCL0_reg[45]_0 [14]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL00[45]),
        .Q(\lowCL0_reg[45]_0 [15]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL00[46]),
        .Q(\lowCL0_reg_n_0_[22] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL00[47]),
        .Q(\lowCL0_reg_n_0_[23] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL00[36]),
        .Q(\lowCL0_reg[45]_0 [16]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL00[37]),
        .Q(\lowCL0_reg[45]_0 [17]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL00[42]),
        .Q(\lowCL0_reg[45]_0 [18]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL00[43]),
        .Q(\lowCL0_reg[45]_0 [19]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL00[44]),
        .Q(\lowCL0_reg_n_0_[28] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL00[45]),
        .Q(\lowCL0_reg_n_0_[29] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL00[42]),
        .Q(\lowCL0_reg[45]_0 [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL00[42]),
        .Q(\lowCL0_reg[45]_0 [20]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL00[43]),
        .Q(\lowCL0_reg[45]_0 [21]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL00[32]),
        .Q(\lowCL0_reg[45]_0 [22]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL00[33]),
        .Q(\lowCL0_reg[45]_0 [23]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL00[46]),
        .Q(\lowCL0_reg_n_0_[34] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL00[47]),
        .Q(\lowCL0_reg_n_0_[35] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL00[36]),
        .Q(\lowCL0_reg[45]_0 [24]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL00[37]),
        .Q(\lowCL0_reg[45]_0 [25]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL00[42]),
        .Q(\lowCL0_reg[45]_0 [26]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL00[43]),
        .Q(\lowCL0_reg[45]_0 [27]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL00[43]),
        .Q(\lowCL0_reg[45]_0 [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL00[44]),
        .Q(\lowCL0_reg_n_0_[40] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL00[45]),
        .Q(\lowCL0_reg_n_0_[41] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL00[42]),
        .Q(\lowCL0_reg[45]_0 [28]),
        .R(rst_r1));
  MUXF7 \lowCL0_reg[42]_i_2 
       (.I0(\lowCL0[42]_i_3_n_0 ),
        .I1(\lowCL0[42]_i_4_n_0 ),
        .O(\lowCL0_reg[42]_i_2_n_0 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL00[43]),
        .Q(\lowCL0_reg[45]_0 [29]),
        .R(rst_r1));
  MUXF7 \lowCL0_reg[43]_i_2 
       (.I0(\lowCL0[43]_i_3_n_0 ),
        .I1(\lowCL0[43]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_0 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL00[44]),
        .Q(\lowCL0_reg[45]_0 [30]),
        .R(rst_r1));
  MUXF7 \lowCL0_reg[44]_i_2 
       (.I0(\lowCL0[44]_i_3_n_0 ),
        .I1(\lowCL0[44]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_2 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL00[45]),
        .Q(\lowCL0_reg[45]_0 [31]),
        .R(rst_r1));
  MUXF7 \lowCL0_reg[45]_i_2 
       (.I0(\lowCL0[45]_i_3_n_0 ),
        .I1(\lowCL0[45]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1] ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL00[46]),
        .Q(\lowCL0_reg_n_0_[46] ),
        .R(rst_r1));
  MUXF7 \lowCL0_reg[46]_i_2 
       (.I0(\lowCL0[46]_i_3_n_0 ),
        .I1(\lowCL0[46]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_3 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL00[47]),
        .Q(\lowCL0_reg_n_0_[47] ),
        .R(rst_r1));
  MUXF7 \lowCL0_reg[47]_i_4 
       (.I0(\lowCL0[47]_i_6_n_0 ),
        .I1(\lowCL0[47]_i_7_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_1 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL00[44]),
        .Q(\lowCL0_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL00[45]),
        .Q(\lowCL0_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL00[42]),
        .Q(\lowCL0_reg[45]_0 [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL00[43]),
        .Q(\lowCL0_reg[45]_0 [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL00[44]),
        .Q(\lowCL0_reg[45]_0 [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL0_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL00[45]),
        .Q(\lowCL0_reg[45]_0 [7]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair1387" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL1[32]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_7 ),
        .I1(io_address[0]),
        .I2(io_write_data[10]),
        .O(lowCL10[32]));
  (* SOFT_HLUTNM = "soft_lutpair1387" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL1[33]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_4 ),
        .I1(io_address[0]),
        .I2(io_write_data[11]),
        .O(lowCL10[33]));
  (* SOFT_HLUTNM = "soft_lutpair1166" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL1[36]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_8 ),
        .I1(io_address[0]),
        .I2(io_write_data[8]),
        .O(lowCL10[36]));
  (* SOFT_HLUTNM = "soft_lutpair1165" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL1[37]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_5 ),
        .I1(io_address[0]),
        .I2(io_write_data[9]),
        .O(lowCL10[37]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \lowCL1[42]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_8 ),
        .I1(io_address[0]),
        .I2(io_write_data[8]),
        .I3(\SYNC[3].sync_reg_reg[1]_7 ),
        .I4(io_write_data[10]),
        .I5(io_address[1]),
        .O(lowCL10[42]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL1[42]_i_3 
       (.I0(\lowCL1_reg[45]_0 [12]),
        .I1(\lowCL1_reg[45]_0 [8]),
        .I2(io_address[2]),
        .I3(\lowCL1_reg[45]_0 [4]),
        .I4(io_address[1]),
        .I5(\lowCL1_reg[45]_0 [0]),
        .O(\lowCL1[42]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL1[42]_i_4 
       (.I0(\lowCL1_reg[45]_0 [28]),
        .I1(\lowCL1_reg[45]_0 [24]),
        .I2(io_address[2]),
        .I3(\lowCL1_reg[45]_0 [20]),
        .I4(io_address[1]),
        .I5(\lowCL1_reg[45]_0 [16]),
        .O(\lowCL1[42]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \lowCL1[43]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_5 ),
        .I1(io_address[0]),
        .I2(io_write_data[9]),
        .I3(\SYNC[3].sync_reg_reg[1]_4 ),
        .I4(io_write_data[11]),
        .I5(io_address[1]),
        .O(lowCL10[43]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL1[43]_i_3 
       (.I0(\lowCL1_reg[45]_0 [13]),
        .I1(\lowCL1_reg[45]_0 [9]),
        .I2(io_address[2]),
        .I3(\lowCL1_reg[45]_0 [5]),
        .I4(io_address[1]),
        .I5(\lowCL1_reg[45]_0 [1]),
        .O(\lowCL1[43]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL1[43]_i_4 
       (.I0(\lowCL1_reg[45]_0 [29]),
        .I1(\lowCL1_reg[45]_0 [25]),
        .I2(io_address[2]),
        .I3(\lowCL1_reg[45]_0 [21]),
        .I4(io_address[1]),
        .I5(\lowCL1_reg[45]_0 [17]),
        .O(\lowCL1[43]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \lowCL1[44]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_9 ),
        .I1(io_address[0]),
        .I2(io_write_data[12]),
        .I3(\SYNC[3].sync_reg_reg[1]_7 ),
        .I4(io_write_data[10]),
        .I5(io_address[1]),
        .O(lowCL10[44]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL1[44]_i_3 
       (.I0(\lowCL1_reg[45]_0 [14]),
        .I1(\lowCL1_reg[45]_0 [10]),
        .I2(io_address[2]),
        .I3(\lowCL1_reg[45]_0 [6]),
        .I4(io_address[1]),
        .I5(\lowCL1_reg[45]_0 [2]),
        .O(\lowCL1[44]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL1[44]_i_4 
       (.I0(\lowCL1_reg[45]_0 [30]),
        .I1(\lowCL1_reg[45]_0 [26]),
        .I2(io_address[2]),
        .I3(\lowCL1_reg[45]_0 [22]),
        .I4(io_address[1]),
        .I5(\lowCL1_reg[45]_0 [18]),
        .O(\lowCL1[44]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \lowCL1[45]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_6 ),
        .I1(io_address[0]),
        .I2(io_write_data[13]),
        .I3(\SYNC[3].sync_reg_reg[1]_4 ),
        .I4(io_write_data[11]),
        .I5(io_address[1]),
        .O(lowCL10[45]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL1[45]_i_3 
       (.I0(\lowCL1_reg[45]_0 [15]),
        .I1(\lowCL1_reg[45]_0 [11]),
        .I2(io_address[2]),
        .I3(\lowCL1_reg[45]_0 [7]),
        .I4(io_address[1]),
        .I5(\lowCL1_reg[45]_0 [3]),
        .O(\lowCL1[45]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL1[45]_i_4 
       (.I0(\lowCL1_reg[45]_0 [31]),
        .I1(\lowCL1_reg[45]_0 [27]),
        .I2(io_address[2]),
        .I3(\lowCL1_reg[45]_0 [23]),
        .I4(io_address[1]),
        .I5(\lowCL1_reg[45]_0 [19]),
        .O(\lowCL1[45]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1167" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL1[46]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_9 ),
        .I1(io_address[0]),
        .I2(io_write_data[12]),
        .O(lowCL10[46]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL1[46]_i_3 
       (.I0(\lowCL1_reg_n_0_[22] ),
        .I1(\lowCL1_reg_n_0_[16] ),
        .I2(io_address[2]),
        .I3(\lowCL1_reg_n_0_[10] ),
        .I4(io_address[1]),
        .I5(\lowCL1_reg_n_0_[4] ),
        .O(\lowCL1[46]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL1[46]_i_4 
       (.I0(\lowCL1_reg_n_0_[46] ),
        .I1(\lowCL1_reg_n_0_[40] ),
        .I2(io_address[2]),
        .I3(\lowCL1_reg_n_0_[34] ),
        .I4(io_address[1]),
        .I5(\lowCL1_reg_n_0_[28] ),
        .O(\lowCL1[46]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1166" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL1[47]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_6 ),
        .I1(io_address[0]),
        .I2(io_write_data[13]),
        .O(lowCL10[47]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL1[47]_i_3 
       (.I0(\lowCL1_reg_n_0_[23] ),
        .I1(\lowCL1_reg_n_0_[17] ),
        .I2(io_address[2]),
        .I3(\lowCL1_reg_n_0_[11] ),
        .I4(io_address[1]),
        .I5(\lowCL1_reg_n_0_[5] ),
        .O(\lowCL1[47]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL1[47]_i_4 
       (.I0(\lowCL1_reg_n_0_[47] ),
        .I1(\lowCL1_reg_n_0_[41] ),
        .I2(io_address[2]),
        .I3(\lowCL1_reg_n_0_[35] ),
        .I4(io_address[1]),
        .I5(\lowCL1_reg_n_0_[29] ),
        .O(\lowCL1[47]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL10[36]),
        .Q(\lowCL1_reg[45]_0 [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL10[46]),
        .Q(\lowCL1_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL10[47]),
        .Q(\lowCL1_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL10[36]),
        .Q(\lowCL1_reg[45]_0 [8]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL10[37]),
        .Q(\lowCL1_reg[45]_0 [9]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL10[42]),
        .Q(\lowCL1_reg[45]_0 [10]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL10[43]),
        .Q(\lowCL1_reg[45]_0 [11]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL10[44]),
        .Q(\lowCL1_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL10[45]),
        .Q(\lowCL1_reg_n_0_[17] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL10[42]),
        .Q(\lowCL1_reg[45]_0 [12]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL10[43]),
        .Q(\lowCL1_reg[45]_0 [13]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL10[37]),
        .Q(\lowCL1_reg[45]_0 [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL10[44]),
        .Q(\lowCL1_reg[45]_0 [14]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL10[45]),
        .Q(\lowCL1_reg[45]_0 [15]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL10[46]),
        .Q(\lowCL1_reg_n_0_[22] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL10[47]),
        .Q(\lowCL1_reg_n_0_[23] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL10[36]),
        .Q(\lowCL1_reg[45]_0 [16]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL10[37]),
        .Q(\lowCL1_reg[45]_0 [17]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL10[42]),
        .Q(\lowCL1_reg[45]_0 [18]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL10[43]),
        .Q(\lowCL1_reg[45]_0 [19]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL10[44]),
        .Q(\lowCL1_reg_n_0_[28] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL10[45]),
        .Q(\lowCL1_reg_n_0_[29] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL10[42]),
        .Q(\lowCL1_reg[45]_0 [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL10[42]),
        .Q(\lowCL1_reg[45]_0 [20]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL10[43]),
        .Q(\lowCL1_reg[45]_0 [21]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL10[32]),
        .Q(\lowCL1_reg[45]_0 [22]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL10[33]),
        .Q(\lowCL1_reg[45]_0 [23]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL10[46]),
        .Q(\lowCL1_reg_n_0_[34] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL10[47]),
        .Q(\lowCL1_reg_n_0_[35] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL10[36]),
        .Q(\lowCL1_reg[45]_0 [24]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL10[37]),
        .Q(\lowCL1_reg[45]_0 [25]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL10[42]),
        .Q(\lowCL1_reg[45]_0 [26]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL10[43]),
        .Q(\lowCL1_reg[45]_0 [27]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL10[43]),
        .Q(\lowCL1_reg[45]_0 [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL10[44]),
        .Q(\lowCL1_reg_n_0_[40] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL10[45]),
        .Q(\lowCL1_reg_n_0_[41] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL10[42]),
        .Q(\lowCL1_reg[45]_0 [28]),
        .R(rst_r1));
  MUXF7 \lowCL1_reg[42]_i_2 
       (.I0(\lowCL1[42]_i_3_n_0 ),
        .I1(\lowCL1[42]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_8 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL10[43]),
        .Q(\lowCL1_reg[45]_0 [29]),
        .R(rst_r1));
  MUXF7 \lowCL1_reg[43]_i_2 
       (.I0(\lowCL1[43]_i_3_n_0 ),
        .I1(\lowCL1[43]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_5 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL10[44]),
        .Q(\lowCL1_reg[45]_0 [30]),
        .R(rst_r1));
  MUXF7 \lowCL1_reg[44]_i_2 
       (.I0(\lowCL1[44]_i_3_n_0 ),
        .I1(\lowCL1[44]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_7 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL10[45]),
        .Q(\lowCL1_reg[45]_0 [31]),
        .R(rst_r1));
  MUXF7 \lowCL1_reg[45]_i_2 
       (.I0(\lowCL1[45]_i_3_n_0 ),
        .I1(\lowCL1[45]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_4 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL10[46]),
        .Q(\lowCL1_reg_n_0_[46] ),
        .R(rst_r1));
  MUXF7 \lowCL1_reg[46]_i_2 
       (.I0(\lowCL1[46]_i_3_n_0 ),
        .I1(\lowCL1[46]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_9 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL10[47]),
        .Q(\lowCL1_reg_n_0_[47] ),
        .R(rst_r1));
  MUXF7 \lowCL1_reg[47]_i_2 
       (.I0(\lowCL1[47]_i_3_n_0 ),
        .I1(\lowCL1[47]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_6 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL10[44]),
        .Q(\lowCL1_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL10[45]),
        .Q(\lowCL1_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL10[42]),
        .Q(\lowCL1_reg[45]_0 [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL10[43]),
        .Q(\lowCL1_reg[45]_0 [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL10[44]),
        .Q(\lowCL1_reg[45]_0 [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL1_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL10[45]),
        .Q(\lowCL1_reg[45]_0 [7]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair1388" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL2[32]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_14 ),
        .I1(io_address[0]),
        .I2(io_write_data[18]),
        .O(lowCL20[32]));
  (* SOFT_HLUTNM = "soft_lutpair1388" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL2[33]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_11 ),
        .I1(io_address[0]),
        .I2(io_write_data[19]),
        .O(lowCL20[33]));
  (* SOFT_HLUTNM = "soft_lutpair1169" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL2[36]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_15 ),
        .I1(io_address[0]),
        .I2(io_write_data[16]),
        .O(lowCL20[36]));
  (* SOFT_HLUTNM = "soft_lutpair1168" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL2[37]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_12 ),
        .I1(io_address[0]),
        .I2(io_write_data[17]),
        .O(lowCL20[37]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \lowCL2[42]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_15 ),
        .I1(io_address[0]),
        .I2(io_write_data[16]),
        .I3(\SYNC[3].sync_reg_reg[1]_14 ),
        .I4(io_write_data[18]),
        .I5(io_address[1]),
        .O(lowCL20[42]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL2[42]_i_3 
       (.I0(\lowCL2_reg[45]_0 [12]),
        .I1(\lowCL2_reg[45]_0 [8]),
        .I2(io_address[2]),
        .I3(\lowCL2_reg[45]_0 [4]),
        .I4(io_address[1]),
        .I5(\lowCL2_reg[45]_0 [0]),
        .O(\lowCL2[42]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL2[42]_i_4 
       (.I0(\lowCL2_reg[45]_0 [28]),
        .I1(\lowCL2_reg[45]_0 [24]),
        .I2(io_address[2]),
        .I3(\lowCL2_reg[45]_0 [20]),
        .I4(io_address[1]),
        .I5(\lowCL2_reg[45]_0 [16]),
        .O(\lowCL2[42]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \lowCL2[43]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_12 ),
        .I1(io_address[0]),
        .I2(io_write_data[17]),
        .I3(\SYNC[3].sync_reg_reg[1]_11 ),
        .I4(io_write_data[19]),
        .I5(io_address[1]),
        .O(lowCL20[43]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL2[43]_i_3 
       (.I0(\lowCL2_reg[45]_0 [13]),
        .I1(\lowCL2_reg[45]_0 [9]),
        .I2(io_address[2]),
        .I3(\lowCL2_reg[45]_0 [5]),
        .I4(io_address[1]),
        .I5(\lowCL2_reg[45]_0 [1]),
        .O(\lowCL2[43]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL2[43]_i_4 
       (.I0(\lowCL2_reg[45]_0 [29]),
        .I1(\lowCL2_reg[45]_0 [25]),
        .I2(io_address[2]),
        .I3(\lowCL2_reg[45]_0 [21]),
        .I4(io_address[1]),
        .I5(\lowCL2_reg[45]_0 [17]),
        .O(\lowCL2[43]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \lowCL2[44]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_14 ),
        .I1(io_address[0]),
        .I2(io_write_data[18]),
        .I3(\SYNC[3].sync_reg_reg[1]_13 ),
        .I4(io_write_data[20]),
        .I5(io_address[1]),
        .O(lowCL20[44]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL2[44]_i_3 
       (.I0(\lowCL2_reg[45]_0 [14]),
        .I1(\lowCL2_reg[45]_0 [10]),
        .I2(io_address[2]),
        .I3(\lowCL2_reg[45]_0 [6]),
        .I4(io_address[1]),
        .I5(\lowCL2_reg[45]_0 [2]),
        .O(\lowCL2[44]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL2[44]_i_4 
       (.I0(\lowCL2_reg[45]_0 [30]),
        .I1(\lowCL2_reg[45]_0 [26]),
        .I2(io_address[2]),
        .I3(\lowCL2_reg[45]_0 [22]),
        .I4(io_address[1]),
        .I5(\lowCL2_reg[45]_0 [18]),
        .O(\lowCL2[44]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \lowCL2[45]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_11 ),
        .I1(io_address[0]),
        .I2(io_write_data[19]),
        .I3(\SYNC[3].sync_reg_reg[1]_10 ),
        .I4(io_write_data[21]),
        .I5(io_address[1]),
        .O(lowCL20[45]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL2[45]_i_3 
       (.I0(\lowCL2_reg[45]_0 [15]),
        .I1(\lowCL2_reg[45]_0 [11]),
        .I2(io_address[2]),
        .I3(\lowCL2_reg[45]_0 [7]),
        .I4(io_address[1]),
        .I5(\lowCL2_reg[45]_0 [3]),
        .O(\lowCL2[45]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL2[45]_i_4 
       (.I0(\lowCL2_reg[45]_0 [31]),
        .I1(\lowCL2_reg[45]_0 [27]),
        .I2(io_address[2]),
        .I3(\lowCL2_reg[45]_0 [23]),
        .I4(io_address[1]),
        .I5(\lowCL2_reg[45]_0 [19]),
        .O(\lowCL2[45]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1168" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL2[46]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_13 ),
        .I1(io_address[0]),
        .I2(io_write_data[20]),
        .O(lowCL20[46]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL2[46]_i_3 
       (.I0(\lowCL2_reg_n_0_[22] ),
        .I1(\lowCL2_reg_n_0_[16] ),
        .I2(io_address[2]),
        .I3(\lowCL2_reg_n_0_[10] ),
        .I4(io_address[1]),
        .I5(\lowCL2_reg_n_0_[4] ),
        .O(\lowCL2[46]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL2[46]_i_4 
       (.I0(\lowCL2_reg_n_0_[46] ),
        .I1(\lowCL2_reg_n_0_[40] ),
        .I2(io_address[2]),
        .I3(\lowCL2_reg_n_0_[34] ),
        .I4(io_address[1]),
        .I5(\lowCL2_reg_n_0_[28] ),
        .O(\lowCL2[46]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1167" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL2[47]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_10 ),
        .I1(io_address[0]),
        .I2(io_write_data[21]),
        .O(lowCL20[47]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL2[47]_i_3 
       (.I0(\lowCL2_reg_n_0_[23] ),
        .I1(\lowCL2_reg_n_0_[17] ),
        .I2(io_address[2]),
        .I3(\lowCL2_reg_n_0_[11] ),
        .I4(io_address[1]),
        .I5(\lowCL2_reg_n_0_[5] ),
        .O(\lowCL2[47]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL2[47]_i_4 
       (.I0(\lowCL2_reg_n_0_[47] ),
        .I1(\lowCL2_reg_n_0_[41] ),
        .I2(io_address[2]),
        .I3(\lowCL2_reg_n_0_[35] ),
        .I4(io_address[1]),
        .I5(\lowCL2_reg_n_0_[29] ),
        .O(\lowCL2[47]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL20[36]),
        .Q(\lowCL2_reg[45]_0 [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL20[46]),
        .Q(\lowCL2_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL20[47]),
        .Q(\lowCL2_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL20[36]),
        .Q(\lowCL2_reg[45]_0 [8]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL20[37]),
        .Q(\lowCL2_reg[45]_0 [9]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL20[42]),
        .Q(\lowCL2_reg[45]_0 [10]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL20[43]),
        .Q(\lowCL2_reg[45]_0 [11]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL20[44]),
        .Q(\lowCL2_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL20[45]),
        .Q(\lowCL2_reg_n_0_[17] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL20[42]),
        .Q(\lowCL2_reg[45]_0 [12]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL20[43]),
        .Q(\lowCL2_reg[45]_0 [13]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL20[37]),
        .Q(\lowCL2_reg[45]_0 [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL20[44]),
        .Q(\lowCL2_reg[45]_0 [14]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL20[45]),
        .Q(\lowCL2_reg[45]_0 [15]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL20[46]),
        .Q(\lowCL2_reg_n_0_[22] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL20[47]),
        .Q(\lowCL2_reg_n_0_[23] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL20[36]),
        .Q(\lowCL2_reg[45]_0 [16]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL20[37]),
        .Q(\lowCL2_reg[45]_0 [17]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL20[42]),
        .Q(\lowCL2_reg[45]_0 [18]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL20[43]),
        .Q(\lowCL2_reg[45]_0 [19]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL20[44]),
        .Q(\lowCL2_reg_n_0_[28] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL20[45]),
        .Q(\lowCL2_reg_n_0_[29] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL20[42]),
        .Q(\lowCL2_reg[45]_0 [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL20[42]),
        .Q(\lowCL2_reg[45]_0 [20]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL20[43]),
        .Q(\lowCL2_reg[45]_0 [21]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL20[32]),
        .Q(\lowCL2_reg[45]_0 [22]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL20[33]),
        .Q(\lowCL2_reg[45]_0 [23]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL20[46]),
        .Q(\lowCL2_reg_n_0_[34] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL20[47]),
        .Q(\lowCL2_reg_n_0_[35] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL20[36]),
        .Q(\lowCL2_reg[45]_0 [24]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL20[37]),
        .Q(\lowCL2_reg[45]_0 [25]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL20[42]),
        .Q(\lowCL2_reg[45]_0 [26]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL20[43]),
        .Q(\lowCL2_reg[45]_0 [27]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL20[43]),
        .Q(\lowCL2_reg[45]_0 [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL20[44]),
        .Q(\lowCL2_reg_n_0_[40] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL20[45]),
        .Q(\lowCL2_reg_n_0_[41] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL20[42]),
        .Q(\lowCL2_reg[45]_0 [28]),
        .R(rst_r1));
  MUXF7 \lowCL2_reg[42]_i_2 
       (.I0(\lowCL2[42]_i_3_n_0 ),
        .I1(\lowCL2[42]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_15 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL20[43]),
        .Q(\lowCL2_reg[45]_0 [29]),
        .R(rst_r1));
  MUXF7 \lowCL2_reg[43]_i_2 
       (.I0(\lowCL2[43]_i_3_n_0 ),
        .I1(\lowCL2[43]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_12 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL20[44]),
        .Q(\lowCL2_reg[45]_0 [30]),
        .R(rst_r1));
  MUXF7 \lowCL2_reg[44]_i_2 
       (.I0(\lowCL2[44]_i_3_n_0 ),
        .I1(\lowCL2[44]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_14 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL20[45]),
        .Q(\lowCL2_reg[45]_0 [31]),
        .R(rst_r1));
  MUXF7 \lowCL2_reg[45]_i_2 
       (.I0(\lowCL2[45]_i_3_n_0 ),
        .I1(\lowCL2[45]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_11 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL20[46]),
        .Q(\lowCL2_reg_n_0_[46] ),
        .R(rst_r1));
  MUXF7 \lowCL2_reg[46]_i_2 
       (.I0(\lowCL2[46]_i_3_n_0 ),
        .I1(\lowCL2[46]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_13 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL20[47]),
        .Q(\lowCL2_reg_n_0_[47] ),
        .R(rst_r1));
  MUXF7 \lowCL2_reg[47]_i_2 
       (.I0(\lowCL2[47]_i_3_n_0 ),
        .I1(\lowCL2[47]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_10 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL20[44]),
        .Q(\lowCL2_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL20[45]),
        .Q(\lowCL2_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL20[42]),
        .Q(\lowCL2_reg[45]_0 [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL20[43]),
        .Q(\lowCL2_reg[45]_0 [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL20[44]),
        .Q(\lowCL2_reg[45]_0 [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL2_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL20[45]),
        .Q(\lowCL2_reg[45]_0 [7]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair1389" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL3[32]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_19 ),
        .I1(io_address[0]),
        .I2(io_write_data[26]),
        .O(lowCL30[32]));
  (* SOFT_HLUTNM = "soft_lutpair1389" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL3[33]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_16 ),
        .I1(io_address[0]),
        .I2(io_write_data[27]),
        .O(lowCL30[33]));
  (* SOFT_HLUTNM = "soft_lutpair1170" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL3[36]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_20 ),
        .I1(io_address[0]),
        .I2(io_write_data[24]),
        .O(lowCL30[36]));
  (* SOFT_HLUTNM = "soft_lutpair1169" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL3[37]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_17 ),
        .I1(io_address[0]),
        .I2(io_write_data[25]),
        .O(lowCL30[37]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \lowCL3[42]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_20 ),
        .I1(io_address[0]),
        .I2(io_write_data[24]),
        .I3(\SYNC[3].sync_reg_reg[1]_19 ),
        .I4(io_write_data[26]),
        .I5(io_address[1]),
        .O(lowCL30[42]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL3[42]_i_3 
       (.I0(\lowCL3_reg[45]_0 [12]),
        .I1(\lowCL3_reg[45]_0 [8]),
        .I2(io_address[2]),
        .I3(\lowCL3_reg[45]_0 [4]),
        .I4(io_address[1]),
        .I5(\lowCL3_reg[45]_0 [0]),
        .O(\lowCL3[42]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL3[42]_i_4 
       (.I0(\lowCL3_reg[45]_0 [28]),
        .I1(\lowCL3_reg[45]_0 [24]),
        .I2(io_address[2]),
        .I3(\lowCL3_reg[45]_0 [20]),
        .I4(io_address[1]),
        .I5(\lowCL3_reg[45]_0 [16]),
        .O(\lowCL3[42]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \lowCL3[43]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_17 ),
        .I1(io_address[0]),
        .I2(io_write_data[25]),
        .I3(\SYNC[3].sync_reg_reg[1]_16 ),
        .I4(io_write_data[27]),
        .I5(io_address[1]),
        .O(lowCL30[43]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL3[43]_i_3 
       (.I0(\lowCL3_reg[45]_0 [13]),
        .I1(\lowCL3_reg[45]_0 [9]),
        .I2(io_address[2]),
        .I3(\lowCL3_reg[45]_0 [5]),
        .I4(io_address[1]),
        .I5(\lowCL3_reg[45]_0 [1]),
        .O(\lowCL3[43]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL3[43]_i_4 
       (.I0(\lowCL3_reg[45]_0 [29]),
        .I1(\lowCL3_reg[45]_0 [25]),
        .I2(io_address[2]),
        .I3(\lowCL3_reg[45]_0 [21]),
        .I4(io_address[1]),
        .I5(\lowCL3_reg[45]_0 [17]),
        .O(\lowCL3[43]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \lowCL3[44]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_21 ),
        .I1(io_address[0]),
        .I2(io_write_data[28]),
        .I3(\SYNC[3].sync_reg_reg[1]_19 ),
        .I4(io_write_data[26]),
        .I5(io_address[1]),
        .O(lowCL30[44]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL3[44]_i_3 
       (.I0(\lowCL3_reg[45]_0 [14]),
        .I1(\lowCL3_reg[45]_0 [10]),
        .I2(io_address[2]),
        .I3(\lowCL3_reg[45]_0 [6]),
        .I4(io_address[1]),
        .I5(\lowCL3_reg[45]_0 [2]),
        .O(\lowCL3[44]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL3[44]_i_4 
       (.I0(\lowCL3_reg[45]_0 [30]),
        .I1(\lowCL3_reg[45]_0 [26]),
        .I2(io_address[2]),
        .I3(\lowCL3_reg[45]_0 [22]),
        .I4(io_address[1]),
        .I5(\lowCL3_reg[45]_0 [18]),
        .O(\lowCL3[44]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \lowCL3[45]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_18 ),
        .I1(io_address[0]),
        .I2(io_write_data[29]),
        .I3(\SYNC[3].sync_reg_reg[1]_16 ),
        .I4(io_write_data[27]),
        .I5(io_address[1]),
        .O(lowCL30[45]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL3[45]_i_3 
       (.I0(\lowCL3_reg[45]_0 [15]),
        .I1(\lowCL3_reg[45]_0 [11]),
        .I2(io_address[2]),
        .I3(\lowCL3_reg[45]_0 [7]),
        .I4(io_address[1]),
        .I5(\lowCL3_reg[45]_0 [3]),
        .O(\lowCL3[45]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL3[45]_i_4 
       (.I0(\lowCL3_reg[45]_0 [31]),
        .I1(\lowCL3_reg[45]_0 [27]),
        .I2(io_address[2]),
        .I3(\lowCL3_reg[45]_0 [23]),
        .I4(io_address[1]),
        .I5(\lowCL3_reg[45]_0 [19]),
        .O(\lowCL3[45]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1171" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL3[46]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_21 ),
        .I1(io_address[0]),
        .I2(io_write_data[28]),
        .O(lowCL30[46]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL3[46]_i_3 
       (.I0(\lowCL3_reg_n_0_[22] ),
        .I1(\lowCL3_reg_n_0_[16] ),
        .I2(io_address[2]),
        .I3(\lowCL3_reg_n_0_[10] ),
        .I4(io_address[1]),
        .I5(\lowCL3_reg_n_0_[4] ),
        .O(\lowCL3[46]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL3[46]_i_4 
       (.I0(\lowCL3_reg_n_0_[46] ),
        .I1(\lowCL3_reg_n_0_[40] ),
        .I2(io_address[2]),
        .I3(\lowCL3_reg_n_0_[34] ),
        .I4(io_address[1]),
        .I5(\lowCL3_reg_n_0_[28] ),
        .O(\lowCL3[46]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1170" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \lowCL3[47]_i_1 
       (.I0(\SYNC[3].sync_reg_reg[1]_18 ),
        .I1(io_address[0]),
        .I2(io_write_data[29]),
        .O(lowCL30[47]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL3[47]_i_3 
       (.I0(\lowCL3_reg_n_0_[23] ),
        .I1(\lowCL3_reg_n_0_[17] ),
        .I2(io_address[2]),
        .I3(\lowCL3_reg_n_0_[11] ),
        .I4(io_address[1]),
        .I5(\lowCL3_reg_n_0_[5] ),
        .O(\lowCL3[47]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \lowCL3[47]_i_4 
       (.I0(\lowCL3_reg_n_0_[47] ),
        .I1(\lowCL3_reg_n_0_[41] ),
        .I2(io_address[2]),
        .I3(\lowCL3_reg_n_0_[35] ),
        .I4(io_address[1]),
        .I5(\lowCL3_reg_n_0_[29] ),
        .O(\lowCL3[47]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL30[36]),
        .Q(\lowCL3_reg[45]_0 [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL30[46]),
        .Q(\lowCL3_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL30[47]),
        .Q(\lowCL3_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL30[36]),
        .Q(\lowCL3_reg[45]_0 [8]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL30[37]),
        .Q(\lowCL3_reg[45]_0 [9]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL30[42]),
        .Q(\lowCL3_reg[45]_0 [10]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL30[43]),
        .Q(\lowCL3_reg[45]_0 [11]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL30[44]),
        .Q(\lowCL3_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(lowCL30[45]),
        .Q(\lowCL3_reg_n_0_[17] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL30[42]),
        .Q(\lowCL3_reg[45]_0 [12]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL30[43]),
        .Q(\lowCL3_reg[45]_0 [13]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL30[37]),
        .Q(\lowCL3_reg[45]_0 [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL30[44]),
        .Q(\lowCL3_reg[45]_0 [14]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL30[45]),
        .Q(\lowCL3_reg[45]_0 [15]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL30[46]),
        .Q(\lowCL3_reg_n_0_[22] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(lowCL30[47]),
        .Q(\lowCL3_reg_n_0_[23] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL30[36]),
        .Q(\lowCL3_reg[45]_0 [16]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL30[37]),
        .Q(\lowCL3_reg[45]_0 [17]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL30[42]),
        .Q(\lowCL3_reg[45]_0 [18]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL30[43]),
        .Q(\lowCL3_reg[45]_0 [19]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL30[44]),
        .Q(\lowCL3_reg_n_0_[28] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(lowCL30[45]),
        .Q(\lowCL3_reg_n_0_[29] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL30[42]),
        .Q(\lowCL3_reg[45]_0 [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL30[42]),
        .Q(\lowCL3_reg[45]_0 [20]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL30[43]),
        .Q(\lowCL3_reg[45]_0 [21]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL30[32]),
        .Q(\lowCL3_reg[45]_0 [22]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL30[33]),
        .Q(\lowCL3_reg[45]_0 [23]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL30[46]),
        .Q(\lowCL3_reg_n_0_[34] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(lowCL30[47]),
        .Q(\lowCL3_reg_n_0_[35] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL30[36]),
        .Q(\lowCL3_reg[45]_0 [24]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL30[37]),
        .Q(\lowCL3_reg[45]_0 [25]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL30[42]),
        .Q(\lowCL3_reg[45]_0 [26]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL30[43]),
        .Q(\lowCL3_reg[45]_0 [27]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL30[43]),
        .Q(\lowCL3_reg[45]_0 [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL30[44]),
        .Q(\lowCL3_reg_n_0_[40] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(lowCL30[45]),
        .Q(\lowCL3_reg_n_0_[41] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL30[42]),
        .Q(\lowCL3_reg[45]_0 [28]),
        .R(rst_r1));
  MUXF7 \lowCL3_reg[42]_i_2 
       (.I0(\lowCL3[42]_i_3_n_0 ),
        .I1(\lowCL3[42]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_20 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL30[43]),
        .Q(\lowCL3_reg[45]_0 [29]),
        .R(rst_r1));
  MUXF7 \lowCL3_reg[43]_i_2 
       (.I0(\lowCL3[43]_i_3_n_0 ),
        .I1(\lowCL3[43]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_17 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL30[44]),
        .Q(\lowCL3_reg[45]_0 [30]),
        .R(rst_r1));
  MUXF7 \lowCL3_reg[44]_i_2 
       (.I0(\lowCL3[44]_i_3_n_0 ),
        .I1(\lowCL3[44]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_19 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL30[45]),
        .Q(\lowCL3_reg[45]_0 [31]),
        .R(rst_r1));
  MUXF7 \lowCL3_reg[45]_i_2 
       (.I0(\lowCL3[45]_i_3_n_0 ),
        .I1(\lowCL3[45]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_16 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL30[46]),
        .Q(\lowCL3_reg_n_0_[46] ),
        .R(rst_r1));
  MUXF7 \lowCL3_reg[46]_i_2 
       (.I0(\lowCL3[46]_i_3_n_0 ),
        .I1(\lowCL3[46]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_21 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(lowCL30[47]),
        .Q(\lowCL3_reg_n_0_[47] ),
        .R(rst_r1));
  MUXF7 \lowCL3_reg[47]_i_2 
       (.I0(\lowCL3[47]_i_3_n_0 ),
        .I1(\lowCL3[47]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_18 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL30[44]),
        .Q(\lowCL3_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(lowCL30[45]),
        .Q(\lowCL3_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL30[42]),
        .Q(\lowCL3_reg[45]_0 [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL30[43]),
        .Q(\lowCL3_reg[45]_0 [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL30[44]),
        .Q(\lowCL3_reg[45]_0 [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \lowCL3_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(lowCL30[45]),
        .Q(\lowCL3_reg[45]_0 [7]),
        .R(rst_r1));
  FDRE lrdimm_cal_mode_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cal_mode_reg_2),
        .D(io_write_data[0]),
        .Q(lrdimm_cal_mode),
        .R(rst_r1));
  FDRE lrdimm_cmp_clr_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(lrdimm_cmp_clr),
        .Q(lrdimm_cmp_clr_reg_n_0),
        .R(rst_r1));
  FDRE lrdimm_cmp_en_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(lrdimm_cmp_en_reg_1),
        .Q(lrdimm_cmp_en_reg_0),
        .R(rst_r1));
  FDRE lrdimm_drive_dq_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(lrdimm_cal_mode_reg_2),
        .D(io_write_data[1]),
        .Q(lrdimm_drive_dq_reg_n_0),
        .R(rst_r1));
  FDRE \max_rd_lat_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\max_rd_lat_reg[5]_1 ),
        .D(io_write_data[0]),
        .Q(\max_rd_lat_reg[5]_0 [0]),
        .R(rst_r1));
  FDRE \max_rd_lat_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\max_rd_lat_reg[5]_1 ),
        .D(io_write_data[1]),
        .Q(\max_rd_lat_reg[5]_0 [1]),
        .R(rst_r1));
  FDRE \max_rd_lat_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\max_rd_lat_reg[5]_1 ),
        .D(io_write_data[2]),
        .Q(\max_rd_lat_reg[5]_0 [2]),
        .R(rst_r1));
  FDRE \max_rd_lat_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\max_rd_lat_reg[5]_1 ),
        .D(io_write_data[3]),
        .Q(\max_rd_lat_reg[5]_0 [3]),
        .R(rst_r1));
  FDRE \max_rd_lat_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\max_rd_lat_reg[5]_1 ),
        .D(io_write_data[4]),
        .Q(\max_rd_lat_reg[5]_0 [4]),
        .R(rst_r1));
  FDRE \max_rd_lat_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\max_rd_lat_reg[5]_1 ),
        .D(io_write_data[5]),
        .Q(\max_rd_lat_reg[5]_0 [5]),
        .R(rst_r1));
  FDRE \mc_cal_ODT_msb_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(ub_cal_ODT[7]),
        .Q(ub_cal_ODT[0]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFF00ACAC)) 
    \mcal_CKE_dly[0][0]_i_1 
       (.I0(ub_cal_CKE),
        .I1(init_cal_CKE),
        .I2(ub_ready),
        .I3(mc_CKE7),
        .I4(\mcal_ODT_dly_reg[0][4] ),
        .O(\cal_RST_CKE_ODT_PAR_reg[16]_0 [0]));
  LUT5 #(
    .INIT(32'hFF00ACAC)) 
    \mcal_CKE_dly[0][6]_i_1 
       (.I0(ub_cal_CKE),
        .I1(init_cal_CKE),
        .I2(ub_ready),
        .I3(mc_CKE[0]),
        .I4(\mcal_ODT_dly_reg[0][4] ),
        .O(\cal_RST_CKE_ODT_PAR_reg[16]_0 [1]));
  LUT5 #(
    .INIT(32'hFF00ACAC)) 
    \mcal_CKE_dly[0][7]_i_1 
       (.I0(ub_cal_CKE),
        .I1(init_cal_CKE),
        .I2(ub_ready),
        .I3(mc_CKE[1]),
        .I4(\mcal_ODT_dly_reg[0][4] ),
        .O(\cal_RST_CKE_ODT_PAR_reg[16]_0 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[0]_i_2 
       (.I0(mcal_DMIn_n_r[24]),
        .I1(mcal_DMIn_n_r[16]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[8]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[0]),
        .O(\mcal_DMIn_bit_r1[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[0]_i_3 
       (.I0(mcal_DMIn_n_r[56]),
        .I1(mcal_DMIn_n_r[48]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[40]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[32]),
        .O(\mcal_DMIn_bit_r1[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[1]_i_2 
       (.I0(mcal_DMIn_n_r[25]),
        .I1(mcal_DMIn_n_r[17]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[9]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[1]),
        .O(\mcal_DMIn_bit_r1[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[1]_i_3 
       (.I0(mcal_DMIn_n_r[57]),
        .I1(mcal_DMIn_n_r[49]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[41]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[33]),
        .O(\mcal_DMIn_bit_r1[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[2]_i_2 
       (.I0(mcal_DMIn_n_r[26]),
        .I1(mcal_DMIn_n_r[18]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[10]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[2]),
        .O(\mcal_DMIn_bit_r1[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[2]_i_3 
       (.I0(mcal_DMIn_n_r[58]),
        .I1(mcal_DMIn_n_r[50]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[42]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[34]),
        .O(\mcal_DMIn_bit_r1[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[3]_i_2 
       (.I0(mcal_DMIn_n_r[27]),
        .I1(mcal_DMIn_n_r[19]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[11]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[3]),
        .O(\mcal_DMIn_bit_r1[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[3]_i_3 
       (.I0(mcal_DMIn_n_r[59]),
        .I1(mcal_DMIn_n_r[51]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[43]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[35]),
        .O(\mcal_DMIn_bit_r1[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[4]_i_2 
       (.I0(mcal_DMIn_n_r[28]),
        .I1(mcal_DMIn_n_r[20]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[12]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[4]),
        .O(\mcal_DMIn_bit_r1[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[4]_i_3 
       (.I0(mcal_DMIn_n_r[60]),
        .I1(mcal_DMIn_n_r[52]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[44]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[36]),
        .O(\mcal_DMIn_bit_r1[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[5]_i_2 
       (.I0(mcal_DMIn_n_r[29]),
        .I1(mcal_DMIn_n_r[21]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[13]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[5]),
        .O(\mcal_DMIn_bit_r1[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[5]_i_3 
       (.I0(mcal_DMIn_n_r[61]),
        .I1(mcal_DMIn_n_r[53]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[45]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[37]),
        .O(\mcal_DMIn_bit_r1[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[6]_i_2 
       (.I0(mcal_DMIn_n_r[30]),
        .I1(mcal_DMIn_n_r[22]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[14]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[6]),
        .O(\mcal_DMIn_bit_r1[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[6]_i_3 
       (.I0(mcal_DMIn_n_r[62]),
        .I1(mcal_DMIn_n_r[54]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[46]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[38]),
        .O(\mcal_DMIn_bit_r1[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[7]_i_2 
       (.I0(mcal_DMIn_n_r[31]),
        .I1(mcal_DMIn_n_r[23]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[15]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[7]),
        .O(\mcal_DMIn_bit_r1[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DMIn_bit_r1[7]_i_3 
       (.I0(mcal_DMIn_n_r[63]),
        .I1(mcal_DMIn_n_r[55]),
        .I2(io_address[1]),
        .I3(mcal_DMIn_n_r[47]),
        .I4(io_address[0]),
        .I5(mcal_DMIn_n_r[39]),
        .O(\mcal_DMIn_bit_r1[7]_i_3_n_0 ));
  FDRE \mcal_DMIn_bit_r1_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_bit_r1_reg[0]_i_1_n_0 ),
        .Q(\mcal_DMIn_bit_r1_reg[7]_0 [0]),
        .R(1'b0));
  MUXF7 \mcal_DMIn_bit_r1_reg[0]_i_1 
       (.I0(\mcal_DMIn_bit_r1[0]_i_2_n_0 ),
        .I1(\mcal_DMIn_bit_r1[0]_i_3_n_0 ),
        .O(\mcal_DMIn_bit_r1_reg[0]_i_1_n_0 ),
        .S(io_address[2]));
  FDRE \mcal_DMIn_bit_r1_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_bit_r1_reg[1]_i_1_n_0 ),
        .Q(\mcal_DMIn_bit_r1_reg[7]_0 [1]),
        .R(1'b0));
  MUXF7 \mcal_DMIn_bit_r1_reg[1]_i_1 
       (.I0(\mcal_DMIn_bit_r1[1]_i_2_n_0 ),
        .I1(\mcal_DMIn_bit_r1[1]_i_3_n_0 ),
        .O(\mcal_DMIn_bit_r1_reg[1]_i_1_n_0 ),
        .S(io_address[2]));
  FDRE \mcal_DMIn_bit_r1_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_bit_r1_reg[2]_i_1_n_0 ),
        .Q(\mcal_DMIn_bit_r1_reg[7]_0 [2]),
        .R(1'b0));
  MUXF7 \mcal_DMIn_bit_r1_reg[2]_i_1 
       (.I0(\mcal_DMIn_bit_r1[2]_i_2_n_0 ),
        .I1(\mcal_DMIn_bit_r1[2]_i_3_n_0 ),
        .O(\mcal_DMIn_bit_r1_reg[2]_i_1_n_0 ),
        .S(io_address[2]));
  FDRE \mcal_DMIn_bit_r1_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_bit_r1_reg[3]_i_1_n_0 ),
        .Q(\mcal_DMIn_bit_r1_reg[7]_0 [3]),
        .R(1'b0));
  MUXF7 \mcal_DMIn_bit_r1_reg[3]_i_1 
       (.I0(\mcal_DMIn_bit_r1[3]_i_2_n_0 ),
        .I1(\mcal_DMIn_bit_r1[3]_i_3_n_0 ),
        .O(\mcal_DMIn_bit_r1_reg[3]_i_1_n_0 ),
        .S(io_address[2]));
  FDRE \mcal_DMIn_bit_r1_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_bit_r1_reg[4]_i_1_n_0 ),
        .Q(\mcal_DMIn_bit_r1_reg[7]_0 [4]),
        .R(1'b0));
  MUXF7 \mcal_DMIn_bit_r1_reg[4]_i_1 
       (.I0(\mcal_DMIn_bit_r1[4]_i_2_n_0 ),
        .I1(\mcal_DMIn_bit_r1[4]_i_3_n_0 ),
        .O(\mcal_DMIn_bit_r1_reg[4]_i_1_n_0 ),
        .S(io_address[2]));
  FDRE \mcal_DMIn_bit_r1_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_bit_r1_reg[5]_i_1_n_0 ),
        .Q(mcal_DMIn_bit_r1),
        .R(1'b0));
  MUXF7 \mcal_DMIn_bit_r1_reg[5]_i_1 
       (.I0(\mcal_DMIn_bit_r1[5]_i_2_n_0 ),
        .I1(\mcal_DMIn_bit_r1[5]_i_3_n_0 ),
        .O(\mcal_DMIn_bit_r1_reg[5]_i_1_n_0 ),
        .S(io_address[2]));
  FDRE \mcal_DMIn_bit_r1_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_bit_r1_reg[6]_i_1_n_0 ),
        .Q(\mcal_DMIn_bit_r1_reg[7]_0 [5]),
        .R(1'b0));
  MUXF7 \mcal_DMIn_bit_r1_reg[6]_i_1 
       (.I0(\mcal_DMIn_bit_r1[6]_i_2_n_0 ),
        .I1(\mcal_DMIn_bit_r1[6]_i_3_n_0 ),
        .O(\mcal_DMIn_bit_r1_reg[6]_i_1_n_0 ),
        .S(io_address[2]));
  FDRE \mcal_DMIn_bit_r1_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_bit_r1_reg[7]_i_1_n_0 ),
        .Q(\mcal_DMIn_bit_r1_reg[7]_0 [6]),
        .R(1'b0));
  MUXF7 \mcal_DMIn_bit_r1_reg[7]_i_1 
       (.I0(\mcal_DMIn_bit_r1[7]_i_2_n_0 ),
        .I1(\mcal_DMIn_bit_r1[7]_i_3_n_0 ),
        .O(\mcal_DMIn_bit_r1_reg[7]_i_1_n_0 ),
        .S(io_address[2]));
  FDRE \mcal_DMIn_n_r_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [0]),
        .Q(mcal_DMIn_n_r[0]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [10]),
        .Q(mcal_DMIn_n_r[10]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [11]),
        .Q(mcal_DMIn_n_r[11]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [12]),
        .Q(mcal_DMIn_n_r[12]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [13]),
        .Q(mcal_DMIn_n_r[13]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [14]),
        .Q(mcal_DMIn_n_r[14]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [15]),
        .Q(mcal_DMIn_n_r[15]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [16]),
        .Q(mcal_DMIn_n_r[16]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [17]),
        .Q(mcal_DMIn_n_r[17]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [18]),
        .Q(mcal_DMIn_n_r[18]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [19]),
        .Q(mcal_DMIn_n_r[19]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [1]),
        .Q(mcal_DMIn_n_r[1]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [20]),
        .Q(mcal_DMIn_n_r[20]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [21]),
        .Q(mcal_DMIn_n_r[21]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [22]),
        .Q(mcal_DMIn_n_r[22]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [23]),
        .Q(mcal_DMIn_n_r[23]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [24]),
        .Q(mcal_DMIn_n_r[24]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [25]),
        .Q(mcal_DMIn_n_r[25]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [26]),
        .Q(mcal_DMIn_n_r[26]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [27]),
        .Q(mcal_DMIn_n_r[27]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [28]),
        .Q(mcal_DMIn_n_r[28]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [29]),
        .Q(mcal_DMIn_n_r[29]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [2]),
        .Q(mcal_DMIn_n_r[2]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [30]),
        .Q(mcal_DMIn_n_r[30]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [31]),
        .Q(mcal_DMIn_n_r[31]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [32]),
        .Q(mcal_DMIn_n_r[32]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [33]),
        .Q(mcal_DMIn_n_r[33]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [34]),
        .Q(mcal_DMIn_n_r[34]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [35]),
        .Q(mcal_DMIn_n_r[35]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [36]),
        .Q(mcal_DMIn_n_r[36]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [37]),
        .Q(mcal_DMIn_n_r[37]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [38]),
        .Q(mcal_DMIn_n_r[38]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [39]),
        .Q(mcal_DMIn_n_r[39]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [3]),
        .Q(mcal_DMIn_n_r[3]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [40]),
        .Q(mcal_DMIn_n_r[40]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [41]),
        .Q(mcal_DMIn_n_r[41]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [42]),
        .Q(mcal_DMIn_n_r[42]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [43]),
        .Q(mcal_DMIn_n_r[43]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [44]),
        .Q(mcal_DMIn_n_r[44]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [45]),
        .Q(mcal_DMIn_n_r[45]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [46]),
        .Q(mcal_DMIn_n_r[46]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [47]),
        .Q(mcal_DMIn_n_r[47]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [48]),
        .Q(mcal_DMIn_n_r[48]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [49]),
        .Q(mcal_DMIn_n_r[49]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [4]),
        .Q(mcal_DMIn_n_r[4]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [50]),
        .Q(mcal_DMIn_n_r[50]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [51]),
        .Q(mcal_DMIn_n_r[51]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [52]),
        .Q(mcal_DMIn_n_r[52]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [53]),
        .Q(mcal_DMIn_n_r[53]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [54]),
        .Q(mcal_DMIn_n_r[54]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [55]),
        .Q(mcal_DMIn_n_r[55]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [56]),
        .Q(mcal_DMIn_n_r[56]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [57]),
        .Q(mcal_DMIn_n_r[57]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [58]),
        .Q(mcal_DMIn_n_r[58]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [59]),
        .Q(mcal_DMIn_n_r[59]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [5]),
        .Q(mcal_DMIn_n_r[5]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [60]),
        .Q(mcal_DMIn_n_r[60]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [61]),
        .Q(mcal_DMIn_n_r[61]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [62]),
        .Q(mcal_DMIn_n_r[62]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [63]),
        .Q(mcal_DMIn_n_r[63]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [6]),
        .Q(mcal_DMIn_n_r[6]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [7]),
        .Q(mcal_DMIn_n_r[7]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [8]),
        .Q(mcal_DMIn_n_r[8]),
        .R(1'b0));
  FDRE \mcal_DMIn_n_r_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DMIn_n_r_reg[63]_0 [9]),
        .Q(mcal_DMIn_n_r[9]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[0]_i_2 
       (.I0(data3[0]),
        .I1(data2[0]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[0]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[0] ),
        .O(\mcal_DQIn_byte_r1[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[0]_i_3 
       (.I0(data7[0]),
        .I1(data6[0]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[0]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[0]),
        .O(\mcal_DQIn_byte_r1[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[10]_i_2 
       (.I0(data3[10]),
        .I1(data2[10]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[10]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[10] ),
        .O(\mcal_DQIn_byte_r1[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[10]_i_3 
       (.I0(data7[10]),
        .I1(data6[10]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[10]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[10]),
        .O(\mcal_DQIn_byte_r1[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[11]_i_2 
       (.I0(data3[11]),
        .I1(data2[11]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[11]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[11] ),
        .O(\mcal_DQIn_byte_r1[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[11]_i_3 
       (.I0(data7[11]),
        .I1(data6[11]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[11]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[11]),
        .O(\mcal_DQIn_byte_r1[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[12]_i_2 
       (.I0(data3[12]),
        .I1(data2[12]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[12]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[12] ),
        .O(\mcal_DQIn_byte_r1[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[12]_i_3 
       (.I0(data7[12]),
        .I1(data6[12]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[12]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[12]),
        .O(\mcal_DQIn_byte_r1[12]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[13]_i_2 
       (.I0(data3[13]),
        .I1(data2[13]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[13]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[13] ),
        .O(\mcal_DQIn_byte_r1[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[13]_i_3 
       (.I0(data7[13]),
        .I1(data6[13]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[13]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[13]),
        .O(\mcal_DQIn_byte_r1[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[14]_i_2 
       (.I0(data3[14]),
        .I1(data2[14]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[14]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[14] ),
        .O(\mcal_DQIn_byte_r1[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[14]_i_3 
       (.I0(data7[14]),
        .I1(data6[14]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[14]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[14]),
        .O(\mcal_DQIn_byte_r1[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[15]_i_2 
       (.I0(data3[15]),
        .I1(data2[15]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[15]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[15] ),
        .O(\mcal_DQIn_byte_r1[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[15]_i_3 
       (.I0(data7[15]),
        .I1(data6[15]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[15]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[15]),
        .O(\mcal_DQIn_byte_r1[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[16]_i_2 
       (.I0(data3[16]),
        .I1(data2[16]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[16]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[16] ),
        .O(\mcal_DQIn_byte_r1[16]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[16]_i_3 
       (.I0(data7[16]),
        .I1(data6[16]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[16]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[16]),
        .O(\mcal_DQIn_byte_r1[16]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[17]_i_2 
       (.I0(data3[17]),
        .I1(data2[17]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[17]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[17] ),
        .O(\mcal_DQIn_byte_r1[17]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[17]_i_3 
       (.I0(data7[17]),
        .I1(data6[17]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[17]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[17]),
        .O(\mcal_DQIn_byte_r1[17]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[18]_i_2 
       (.I0(data3[18]),
        .I1(data2[18]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[18]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[18] ),
        .O(\mcal_DQIn_byte_r1[18]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[18]_i_3 
       (.I0(data7[18]),
        .I1(data6[18]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[18]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[18]),
        .O(\mcal_DQIn_byte_r1[18]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[19]_i_2 
       (.I0(data3[19]),
        .I1(data2[19]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[19]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[19] ),
        .O(\mcal_DQIn_byte_r1[19]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[19]_i_3 
       (.I0(data7[19]),
        .I1(data6[19]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[19]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[19]),
        .O(\mcal_DQIn_byte_r1[19]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[1]_i_2 
       (.I0(data3[1]),
        .I1(data2[1]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[1]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[1] ),
        .O(\mcal_DQIn_byte_r1[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[1]_i_3 
       (.I0(data7[1]),
        .I1(data6[1]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[1]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[1]),
        .O(\mcal_DQIn_byte_r1[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[20]_i_2 
       (.I0(data3[20]),
        .I1(data2[20]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[20]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[20] ),
        .O(\mcal_DQIn_byte_r1[20]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[20]_i_3 
       (.I0(data7[20]),
        .I1(data6[20]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[20]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[20]),
        .O(\mcal_DQIn_byte_r1[20]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[21]_i_2 
       (.I0(data3[21]),
        .I1(data2[21]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[21]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[21] ),
        .O(\mcal_DQIn_byte_r1[21]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[21]_i_3 
       (.I0(data7[21]),
        .I1(data6[21]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[21]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[21]),
        .O(\mcal_DQIn_byte_r1[21]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[22]_i_2 
       (.I0(data3[22]),
        .I1(data2[22]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[22]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[22] ),
        .O(\mcal_DQIn_byte_r1[22]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[22]_i_3 
       (.I0(data7[22]),
        .I1(data6[22]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[22]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[22]),
        .O(\mcal_DQIn_byte_r1[22]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[23]_i_2 
       (.I0(data3[23]),
        .I1(data2[23]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[23]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[23] ),
        .O(\mcal_DQIn_byte_r1[23]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[23]_i_3 
       (.I0(data7[23]),
        .I1(data6[23]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[23]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[23]),
        .O(\mcal_DQIn_byte_r1[23]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[24]_i_2 
       (.I0(data3[24]),
        .I1(data2[24]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[24]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[24] ),
        .O(\mcal_DQIn_byte_r1[24]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[24]_i_3 
       (.I0(data7[24]),
        .I1(data6[24]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[24]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[24]),
        .O(\mcal_DQIn_byte_r1[24]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[25]_i_2 
       (.I0(data3[25]),
        .I1(data2[25]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[25]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[25] ),
        .O(\mcal_DQIn_byte_r1[25]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[25]_i_3 
       (.I0(data7[25]),
        .I1(data6[25]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[25]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[25]),
        .O(\mcal_DQIn_byte_r1[25]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[26]_i_2 
       (.I0(data3[26]),
        .I1(data2[26]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[26]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[26] ),
        .O(\mcal_DQIn_byte_r1[26]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[26]_i_3 
       (.I0(data7[26]),
        .I1(data6[26]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[26]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[26]),
        .O(\mcal_DQIn_byte_r1[26]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[27]_i_2 
       (.I0(data3[27]),
        .I1(data2[27]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[27]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[27] ),
        .O(\mcal_DQIn_byte_r1[27]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[27]_i_3 
       (.I0(data7[27]),
        .I1(data6[27]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[27]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[27]),
        .O(\mcal_DQIn_byte_r1[27]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[28]_i_2 
       (.I0(data3[28]),
        .I1(data2[28]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[28]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[28] ),
        .O(\mcal_DQIn_byte_r1[28]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[28]_i_3 
       (.I0(data7[28]),
        .I1(data6[28]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[28]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[28]),
        .O(\mcal_DQIn_byte_r1[28]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[29]_i_2 
       (.I0(data3[29]),
        .I1(data2[29]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[29]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[29] ),
        .O(\mcal_DQIn_byte_r1[29]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[29]_i_3 
       (.I0(data7[29]),
        .I1(data6[29]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[29]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[29]),
        .O(\mcal_DQIn_byte_r1[29]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[2]_i_2 
       (.I0(data3[2]),
        .I1(data2[2]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[2]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[2] ),
        .O(\mcal_DQIn_byte_r1[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[2]_i_3 
       (.I0(data7[2]),
        .I1(data6[2]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[2]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[2]),
        .O(\mcal_DQIn_byte_r1[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[30]_i_2 
       (.I0(data3[30]),
        .I1(data2[30]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[30]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[30] ),
        .O(\mcal_DQIn_byte_r1[30]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[30]_i_3 
       (.I0(data7[30]),
        .I1(data6[30]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[30]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[30]),
        .O(\mcal_DQIn_byte_r1[30]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[31]_i_2 
       (.I0(data3[31]),
        .I1(data2[31]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[31]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[31] ),
        .O(\mcal_DQIn_byte_r1[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[31]_i_3 
       (.I0(data7[31]),
        .I1(data6[31]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[31]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[31]),
        .O(\mcal_DQIn_byte_r1[31]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[32]_i_2 
       (.I0(data3[32]),
        .I1(data2[32]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[32]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[32] ),
        .O(\mcal_DQIn_byte_r1[32]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[32]_i_3 
       (.I0(data7[32]),
        .I1(data6[32]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[32]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[32]),
        .O(\mcal_DQIn_byte_r1[32]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[33]_i_2 
       (.I0(data3[33]),
        .I1(data2[33]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[33]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[33] ),
        .O(\mcal_DQIn_byte_r1[33]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[33]_i_3 
       (.I0(data7[33]),
        .I1(data6[33]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[33]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[33]),
        .O(\mcal_DQIn_byte_r1[33]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[34]_i_2 
       (.I0(data3[34]),
        .I1(data2[34]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[34]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[34] ),
        .O(\mcal_DQIn_byte_r1[34]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[34]_i_3 
       (.I0(data7[34]),
        .I1(data6[34]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[34]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[34]),
        .O(\mcal_DQIn_byte_r1[34]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[35]_i_2 
       (.I0(data3[35]),
        .I1(data2[35]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[35]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[35] ),
        .O(\mcal_DQIn_byte_r1[35]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[35]_i_3 
       (.I0(data7[35]),
        .I1(data6[35]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[35]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[35]),
        .O(\mcal_DQIn_byte_r1[35]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[36]_i_2 
       (.I0(data3[36]),
        .I1(data2[36]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[36]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[36] ),
        .O(\mcal_DQIn_byte_r1[36]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[36]_i_3 
       (.I0(data7[36]),
        .I1(data6[36]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[36]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[36]),
        .O(\mcal_DQIn_byte_r1[36]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[37]_i_2 
       (.I0(data3[37]),
        .I1(data2[37]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[37]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[37] ),
        .O(\mcal_DQIn_byte_r1[37]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[37]_i_3 
       (.I0(data7[37]),
        .I1(data6[37]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[37]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[37]),
        .O(\mcal_DQIn_byte_r1[37]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[38]_i_2 
       (.I0(data3[38]),
        .I1(data2[38]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[38]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[38] ),
        .O(\mcal_DQIn_byte_r1[38]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[38]_i_3 
       (.I0(data7[38]),
        .I1(data6[38]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[38]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[38]),
        .O(\mcal_DQIn_byte_r1[38]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[39]_i_2 
       (.I0(data3[39]),
        .I1(data2[39]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[39]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[39] ),
        .O(\mcal_DQIn_byte_r1[39]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[39]_i_3 
       (.I0(data7[39]),
        .I1(data6[39]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[39]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[39]),
        .O(\mcal_DQIn_byte_r1[39]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[3]_i_2 
       (.I0(data3[3]),
        .I1(data2[3]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[3]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[3] ),
        .O(\mcal_DQIn_byte_r1[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[3]_i_3 
       (.I0(data7[3]),
        .I1(data6[3]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[3]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[3]),
        .O(\mcal_DQIn_byte_r1[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[40]_i_2 
       (.I0(data3[40]),
        .I1(data2[40]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[40]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[40] ),
        .O(\mcal_DQIn_byte_r1[40]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[40]_i_3 
       (.I0(data7[40]),
        .I1(data6[40]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[40]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[40]),
        .O(\mcal_DQIn_byte_r1[40]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[41]_i_2 
       (.I0(data3[41]),
        .I1(data2[41]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[41]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[41] ),
        .O(\mcal_DQIn_byte_r1[41]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[41]_i_3 
       (.I0(data7[41]),
        .I1(data6[41]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[41]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[41]),
        .O(\mcal_DQIn_byte_r1[41]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[42]_i_2 
       (.I0(data3[42]),
        .I1(data2[42]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[42]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[42] ),
        .O(\mcal_DQIn_byte_r1[42]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[42]_i_3 
       (.I0(data7[42]),
        .I1(data6[42]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[42]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[42]),
        .O(\mcal_DQIn_byte_r1[42]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[43]_i_2 
       (.I0(data3[43]),
        .I1(data2[43]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[43]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[43] ),
        .O(\mcal_DQIn_byte_r1[43]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[43]_i_3 
       (.I0(data7[43]),
        .I1(data6[43]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[43]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[43]),
        .O(\mcal_DQIn_byte_r1[43]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[44]_i_2 
       (.I0(data3[44]),
        .I1(data2[44]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[44]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[44] ),
        .O(\mcal_DQIn_byte_r1[44]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[44]_i_3 
       (.I0(data7[44]),
        .I1(data6[44]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[44]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[44]),
        .O(\mcal_DQIn_byte_r1[44]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[45]_i_2 
       (.I0(data3[45]),
        .I1(data2[45]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[45]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[45] ),
        .O(\mcal_DQIn_byte_r1[45]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[45]_i_3 
       (.I0(data7[45]),
        .I1(data6[45]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[45]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[45]),
        .O(\mcal_DQIn_byte_r1[45]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[46]_i_2 
       (.I0(data3[46]),
        .I1(data2[46]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[46]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[46] ),
        .O(\mcal_DQIn_byte_r1[46]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[46]_i_3 
       (.I0(data7[46]),
        .I1(data6[46]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[46]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[46]),
        .O(\mcal_DQIn_byte_r1[46]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[47]_i_2 
       (.I0(data3[47]),
        .I1(data2[47]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[47]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[47] ),
        .O(\mcal_DQIn_byte_r1[47]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[47]_i_3 
       (.I0(data7[47]),
        .I1(data6[47]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[47]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[47]),
        .O(\mcal_DQIn_byte_r1[47]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[48]_i_2 
       (.I0(data3[48]),
        .I1(data2[48]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[48]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[48] ),
        .O(\mcal_DQIn_byte_r1[48]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[48]_i_3 
       (.I0(data7[48]),
        .I1(data6[48]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[48]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[48]),
        .O(\mcal_DQIn_byte_r1[48]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[49]_i_2 
       (.I0(data3[49]),
        .I1(data2[49]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[49]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[49] ),
        .O(\mcal_DQIn_byte_r1[49]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[49]_i_3 
       (.I0(data7[49]),
        .I1(data6[49]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[49]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[49]),
        .O(\mcal_DQIn_byte_r1[49]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[4]_i_2 
       (.I0(data3[4]),
        .I1(data2[4]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[4]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[4] ),
        .O(\mcal_DQIn_byte_r1[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[4]_i_3 
       (.I0(data7[4]),
        .I1(data6[4]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[4]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[4]),
        .O(\mcal_DQIn_byte_r1[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[50]_i_2 
       (.I0(data3[50]),
        .I1(data2[50]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[50]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[50] ),
        .O(\mcal_DQIn_byte_r1[50]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[50]_i_3 
       (.I0(data7[50]),
        .I1(data6[50]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[50]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[50]),
        .O(\mcal_DQIn_byte_r1[50]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[51]_i_2 
       (.I0(data3[51]),
        .I1(data2[51]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[51]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[51] ),
        .O(\mcal_DQIn_byte_r1[51]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[51]_i_3 
       (.I0(data7[51]),
        .I1(data6[51]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[51]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[51]),
        .O(\mcal_DQIn_byte_r1[51]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[52]_i_2 
       (.I0(data3[52]),
        .I1(data2[52]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[52]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[52] ),
        .O(\mcal_DQIn_byte_r1[52]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[52]_i_3 
       (.I0(data7[52]),
        .I1(data6[52]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[52]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[52]),
        .O(\mcal_DQIn_byte_r1[52]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[53]_i_2 
       (.I0(data3[53]),
        .I1(data2[53]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[53]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[53] ),
        .O(\mcal_DQIn_byte_r1[53]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[53]_i_3 
       (.I0(data7[53]),
        .I1(data6[53]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[53]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[53]),
        .O(\mcal_DQIn_byte_r1[53]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[54]_i_2 
       (.I0(data3[54]),
        .I1(data2[54]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[54]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[54] ),
        .O(\mcal_DQIn_byte_r1[54]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[54]_i_3 
       (.I0(data7[54]),
        .I1(data6[54]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[54]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[54]),
        .O(\mcal_DQIn_byte_r1[54]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[55]_i_2 
       (.I0(data3[55]),
        .I1(data2[55]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[55]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[55] ),
        .O(\mcal_DQIn_byte_r1[55]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[55]_i_3 
       (.I0(data7[55]),
        .I1(data6[55]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[55]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[55]),
        .O(\mcal_DQIn_byte_r1[55]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[56]_i_2 
       (.I0(data3[56]),
        .I1(data2[56]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[56]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[56] ),
        .O(\mcal_DQIn_byte_r1[56]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[56]_i_3 
       (.I0(data7[56]),
        .I1(data6[56]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[56]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[56]),
        .O(\mcal_DQIn_byte_r1[56]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[57]_i_2 
       (.I0(data3[57]),
        .I1(data2[57]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[57]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[57] ),
        .O(\mcal_DQIn_byte_r1[57]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[57]_i_3 
       (.I0(data7[57]),
        .I1(data6[57]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[57]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[57]),
        .O(\mcal_DQIn_byte_r1[57]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[58]_i_2 
       (.I0(data3[58]),
        .I1(data2[58]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[58]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[58] ),
        .O(\mcal_DQIn_byte_r1[58]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[58]_i_3 
       (.I0(data7[58]),
        .I1(data6[58]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[58]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[58]),
        .O(\mcal_DQIn_byte_r1[58]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[59]_i_2 
       (.I0(data3[59]),
        .I1(data2[59]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[59]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[59] ),
        .O(\mcal_DQIn_byte_r1[59]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[59]_i_3 
       (.I0(data7[59]),
        .I1(data6[59]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[59]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[59]),
        .O(\mcal_DQIn_byte_r1[59]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[5]_i_2 
       (.I0(data3[5]),
        .I1(data2[5]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[5]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[5] ),
        .O(\mcal_DQIn_byte_r1[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[5]_i_3 
       (.I0(data7[5]),
        .I1(data6[5]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[5]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[5]),
        .O(\mcal_DQIn_byte_r1[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[60]_i_2 
       (.I0(data3[60]),
        .I1(data2[60]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[60]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[60] ),
        .O(\mcal_DQIn_byte_r1[60]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[60]_i_3 
       (.I0(data7[60]),
        .I1(data6[60]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[60]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[60]),
        .O(\mcal_DQIn_byte_r1[60]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[61]_i_2 
       (.I0(data3[61]),
        .I1(data2[61]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[61]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[61] ),
        .O(\mcal_DQIn_byte_r1[61]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[61]_i_3 
       (.I0(data7[61]),
        .I1(data6[61]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[61]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[61]),
        .O(\mcal_DQIn_byte_r1[61]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[62]_i_2 
       (.I0(data3[62]),
        .I1(data2[62]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[62]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[62] ),
        .O(\mcal_DQIn_byte_r1[62]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[62]_i_3 
       (.I0(data7[62]),
        .I1(data6[62]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[62]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[62]),
        .O(\mcal_DQIn_byte_r1[62]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[63]_i_2 
       (.I0(data3[63]),
        .I1(data2[63]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[63]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[63] ),
        .O(\mcal_DQIn_byte_r1[63]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[63]_i_3 
       (.I0(data7[63]),
        .I1(data6[63]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[63]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[63]),
        .O(\mcal_DQIn_byte_r1[63]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[6]_i_2 
       (.I0(data3[6]),
        .I1(data2[6]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[6]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[6] ),
        .O(\mcal_DQIn_byte_r1[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[6]_i_3 
       (.I0(data7[6]),
        .I1(data6[6]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[6]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[6]),
        .O(\mcal_DQIn_byte_r1[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[7]_i_2 
       (.I0(data3[7]),
        .I1(data2[7]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[7]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[7] ),
        .O(\mcal_DQIn_byte_r1[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[7]_i_3 
       (.I0(data7[7]),
        .I1(data6[7]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[7]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[7]),
        .O(\mcal_DQIn_byte_r1[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[8]_i_2 
       (.I0(data3[8]),
        .I1(data2[8]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[8]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[8] ),
        .O(\mcal_DQIn_byte_r1[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[8]_i_3 
       (.I0(data7[8]),
        .I1(data6[8]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[8]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[8]),
        .O(\mcal_DQIn_byte_r1[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[9]_i_2 
       (.I0(data3[9]),
        .I1(data2[9]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data1[9]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(\mcal_DQIn_r_valid_reg_n_0_[9] ),
        .O(\mcal_DQIn_byte_r1[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r1[9]_i_3 
       (.I0(data7[9]),
        .I1(data6[9]),
        .I2(\cmp_byte_reg_n_0_[1] ),
        .I3(data5[9]),
        .I4(\cmp_byte_reg_n_0_[0] ),
        .I5(data4[9]),
        .O(\mcal_DQIn_byte_r1[9]_i_3_n_0 ));
  FDRE \mcal_DQIn_byte_r1_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[0]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[0]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[0]_i_1 
       (.I0(\mcal_DQIn_byte_r1[0]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[0]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[0]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[10]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[10]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[10]_i_1 
       (.I0(\mcal_DQIn_byte_r1[10]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[10]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[10]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[11]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[11]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[11]_i_1 
       (.I0(\mcal_DQIn_byte_r1[11]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[11]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[11]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[12]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[12]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[12]_i_1 
       (.I0(\mcal_DQIn_byte_r1[12]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[12]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[12]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[13]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[13]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[13]_i_1 
       (.I0(\mcal_DQIn_byte_r1[13]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[13]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[13]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[14]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[14]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[14]_i_1 
       (.I0(\mcal_DQIn_byte_r1[14]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[14]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[14]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[15]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[15]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[15]_i_1 
       (.I0(\mcal_DQIn_byte_r1[15]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[15]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[15]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[16]_i_1_n_0 ),
        .Q(\mcal_DQIn_byte_r1_reg[48]_0 [4]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[16]_i_1 
       (.I0(\mcal_DQIn_byte_r1[16]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[16]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[16]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[17]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[17]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[17]_i_1 
       (.I0(\mcal_DQIn_byte_r1[17]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[17]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[17]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[18]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[18]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[18]_i_1 
       (.I0(\mcal_DQIn_byte_r1[18]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[18]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[18]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[19]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[19]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[19]_i_1 
       (.I0(\mcal_DQIn_byte_r1[19]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[19]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[19]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[1]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[1]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[1]_i_1 
       (.I0(\mcal_DQIn_byte_r1[1]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[1]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[1]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[20]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[20]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[20]_i_1 
       (.I0(\mcal_DQIn_byte_r1[20]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[20]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[20]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[21]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[21]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[21]_i_1 
       (.I0(\mcal_DQIn_byte_r1[21]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[21]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[21]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[22]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[22]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[22]_i_1 
       (.I0(\mcal_DQIn_byte_r1[22]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[22]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[22]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[23]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[23]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[23]_i_1 
       (.I0(\mcal_DQIn_byte_r1[23]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[23]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[23]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[24]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[24]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[24]_i_1 
       (.I0(\mcal_DQIn_byte_r1[24]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[24]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[24]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[25]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[25]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[25]_i_1 
       (.I0(\mcal_DQIn_byte_r1[25]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[25]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[25]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[26]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[26]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[26]_i_1 
       (.I0(\mcal_DQIn_byte_r1[26]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[26]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[26]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[27]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[27]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[27]_i_1 
       (.I0(\mcal_DQIn_byte_r1[27]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[27]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[27]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[28]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[28]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[28]_i_1 
       (.I0(\mcal_DQIn_byte_r1[28]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[28]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[28]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[29]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[29]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[29]_i_1 
       (.I0(\mcal_DQIn_byte_r1[29]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[29]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[29]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[2]_i_1_n_0 ),
        .Q(\mcal_DQIn_byte_r1_reg[48]_0 [0]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[2]_i_1 
       (.I0(\mcal_DQIn_byte_r1[2]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[2]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[2]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[30]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[30]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[30]_i_1 
       (.I0(\mcal_DQIn_byte_r1[30]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[30]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[30]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[31]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[31]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[31]_i_1 
       (.I0(\mcal_DQIn_byte_r1[31]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[31]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[31]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[32]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[32]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[32]_i_1 
       (.I0(\mcal_DQIn_byte_r1[32]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[32]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[32]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[33]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[33]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[33]_i_1 
       (.I0(\mcal_DQIn_byte_r1[33]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[33]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[33]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[34]_i_1_n_0 ),
        .Q(\mcal_DQIn_byte_r1_reg[48]_0 [5]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[34]_i_1 
       (.I0(\mcal_DQIn_byte_r1[34]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[34]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[34]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[35]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[35]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[35]_i_1 
       (.I0(\mcal_DQIn_byte_r1[35]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[35]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[35]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[36]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[36]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[36]_i_1 
       (.I0(\mcal_DQIn_byte_r1[36]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[36]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[36]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[37]_i_1_n_0 ),
        .Q(\mcal_DQIn_byte_r1_reg[48]_0 [6]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[37]_i_1 
       (.I0(\mcal_DQIn_byte_r1[37]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[37]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[37]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[38]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[38]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[38]_i_1 
       (.I0(\mcal_DQIn_byte_r1[38]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[38]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[38]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[39]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[39]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[39]_i_1 
       (.I0(\mcal_DQIn_byte_r1[39]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[39]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[39]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[3]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[3]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[3]_i_1 
       (.I0(\mcal_DQIn_byte_r1[3]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[3]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[3]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[40]_i_1_n_0 ),
        .Q(\mcal_DQIn_byte_r1_reg[48]_0 [7]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[40]_i_1 
       (.I0(\mcal_DQIn_byte_r1[40]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[40]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[40]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[41]_i_1_n_0 ),
        .Q(\mcal_DQIn_byte_r1_reg[48]_0 [8]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[41]_i_1 
       (.I0(\mcal_DQIn_byte_r1[41]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[41]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[41]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[42]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[42]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[42]_i_1 
       (.I0(\mcal_DQIn_byte_r1[42]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[42]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[42]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[43]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[43]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[43]_i_1 
       (.I0(\mcal_DQIn_byte_r1[43]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[43]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[43]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[44]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[44]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[44]_i_1 
       (.I0(\mcal_DQIn_byte_r1[44]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[44]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[44]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[45]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[45]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[45]_i_1 
       (.I0(\mcal_DQIn_byte_r1[45]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[45]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[45]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[46]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[46]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[46]_i_1 
       (.I0(\mcal_DQIn_byte_r1[46]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[46]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[46]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[47]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[47]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[47]_i_1 
       (.I0(\mcal_DQIn_byte_r1[47]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[47]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[47]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[48]_i_1_n_0 ),
        .Q(\mcal_DQIn_byte_r1_reg[48]_0 [9]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[48]_i_1 
       (.I0(\mcal_DQIn_byte_r1[48]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[48]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[48]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[49]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[49]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[49]_i_1 
       (.I0(\mcal_DQIn_byte_r1[49]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[49]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[49]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[4]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[4]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[4]_i_1 
       (.I0(\mcal_DQIn_byte_r1[4]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[4]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[4]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[50]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[50]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[50]_i_1 
       (.I0(\mcal_DQIn_byte_r1[50]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[50]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[50]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[51]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[51]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[51]_i_1 
       (.I0(\mcal_DQIn_byte_r1[51]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[51]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[51]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[52]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[52]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[52]_i_1 
       (.I0(\mcal_DQIn_byte_r1[52]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[52]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[52]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[53]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[53]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[53]_i_1 
       (.I0(\mcal_DQIn_byte_r1[53]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[53]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[53]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[54]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[54]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[54]_i_1 
       (.I0(\mcal_DQIn_byte_r1[54]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[54]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[54]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[55]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[55]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[55]_i_1 
       (.I0(\mcal_DQIn_byte_r1[55]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[55]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[55]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[56]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[56]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[56]_i_1 
       (.I0(\mcal_DQIn_byte_r1[56]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[56]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[56]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[57]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[57]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[57]_i_1 
       (.I0(\mcal_DQIn_byte_r1[57]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[57]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[57]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[58]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[58]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[58]_i_1 
       (.I0(\mcal_DQIn_byte_r1[58]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[58]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[58]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[59]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[59]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[59]_i_1 
       (.I0(\mcal_DQIn_byte_r1[59]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[59]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[59]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[5]_i_1_n_0 ),
        .Q(\mcal_DQIn_byte_r1_reg[48]_0 [1]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[5]_i_1 
       (.I0(\mcal_DQIn_byte_r1[5]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[5]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[5]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[60]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[60]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[60]_i_1 
       (.I0(\mcal_DQIn_byte_r1[60]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[60]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[60]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[61]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[61]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[61]_i_1 
       (.I0(\mcal_DQIn_byte_r1[61]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[61]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[61]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[62]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[62]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[62]_i_1 
       (.I0(\mcal_DQIn_byte_r1[62]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[62]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[62]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[63]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[63]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[63]_i_1 
       (.I0(\mcal_DQIn_byte_r1[63]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[63]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[63]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[6]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[6]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[6]_i_1 
       (.I0(\mcal_DQIn_byte_r1[6]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[6]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[6]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[7]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r1[7]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[7]_i_1 
       (.I0(\mcal_DQIn_byte_r1[7]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[7]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[7]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[8]_i_1_n_0 ),
        .Q(\mcal_DQIn_byte_r1_reg[48]_0 [2]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[8]_i_1 
       (.I0(\mcal_DQIn_byte_r1[8]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[8]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[8]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r1_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_byte_r1_reg[9]_i_1_n_0 ),
        .Q(\mcal_DQIn_byte_r1_reg[48]_0 [3]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r1_reg[9]_i_1 
       (.I0(\mcal_DQIn_byte_r1[9]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r1[9]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r1_reg[9]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[0]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[192] ),
        .I1(\mcal_DQIn_r_reg_n_0_[128] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[64] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[0] ),
        .O(\mcal_DQIn_byte_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[0]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[448] ),
        .I1(\mcal_DQIn_r_reg_n_0_[384] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[320] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[256] ),
        .O(\mcal_DQIn_byte_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[10]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[202] ),
        .I1(\mcal_DQIn_r_reg_n_0_[138] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[74] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[10] ),
        .O(\mcal_DQIn_byte_r[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[10]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[458] ),
        .I1(\mcal_DQIn_r_reg_n_0_[394] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[330] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[266] ),
        .O(\mcal_DQIn_byte_r[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[11]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[203] ),
        .I1(\mcal_DQIn_r_reg_n_0_[139] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[75] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[11] ),
        .O(\mcal_DQIn_byte_r[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[11]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[459] ),
        .I1(\mcal_DQIn_r_reg_n_0_[395] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[331] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[267] ),
        .O(\mcal_DQIn_byte_r[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[12]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[204] ),
        .I1(\mcal_DQIn_r_reg_n_0_[140] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[76] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[12] ),
        .O(\mcal_DQIn_byte_r[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[12]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[460] ),
        .I1(\mcal_DQIn_r_reg_n_0_[396] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[332] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[268] ),
        .O(\mcal_DQIn_byte_r[12]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[13]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[205] ),
        .I1(\mcal_DQIn_r_reg_n_0_[141] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[77] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[13] ),
        .O(\mcal_DQIn_byte_r[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[13]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[461] ),
        .I1(\mcal_DQIn_r_reg_n_0_[397] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[333] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[269] ),
        .O(\mcal_DQIn_byte_r[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[14]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[206] ),
        .I1(\mcal_DQIn_r_reg_n_0_[142] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[78] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[14] ),
        .O(\mcal_DQIn_byte_r[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[14]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[462] ),
        .I1(\mcal_DQIn_r_reg_n_0_[398] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[334] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[270] ),
        .O(\mcal_DQIn_byte_r[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[15]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[207] ),
        .I1(\mcal_DQIn_r_reg_n_0_[143] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[79] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[15] ),
        .O(\mcal_DQIn_byte_r[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[15]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[463] ),
        .I1(\mcal_DQIn_r_reg_n_0_[399] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[335] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[271] ),
        .O(\mcal_DQIn_byte_r[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[16]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[208] ),
        .I1(\mcal_DQIn_r_reg_n_0_[144] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[80] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[16] ),
        .O(\mcal_DQIn_byte_r[16]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[16]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[464] ),
        .I1(\mcal_DQIn_r_reg_n_0_[400] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[336] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[272] ),
        .O(\mcal_DQIn_byte_r[16]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[17]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[209] ),
        .I1(\mcal_DQIn_r_reg_n_0_[145] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[81] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[17] ),
        .O(\mcal_DQIn_byte_r[17]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[17]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[465] ),
        .I1(\mcal_DQIn_r_reg_n_0_[401] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[337] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[273] ),
        .O(\mcal_DQIn_byte_r[17]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[18]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[210] ),
        .I1(\mcal_DQIn_r_reg_n_0_[146] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[82] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[18] ),
        .O(\mcal_DQIn_byte_r[18]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[18]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[466] ),
        .I1(\mcal_DQIn_r_reg_n_0_[402] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[338] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[274] ),
        .O(\mcal_DQIn_byte_r[18]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[19]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[211] ),
        .I1(\mcal_DQIn_r_reg_n_0_[147] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[83] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[19] ),
        .O(\mcal_DQIn_byte_r[19]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[19]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[467] ),
        .I1(\mcal_DQIn_r_reg_n_0_[403] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[339] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[275] ),
        .O(\mcal_DQIn_byte_r[19]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[1]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[193] ),
        .I1(\mcal_DQIn_r_reg_n_0_[129] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[65] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[1] ),
        .O(\mcal_DQIn_byte_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[1]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[449] ),
        .I1(\mcal_DQIn_r_reg_n_0_[385] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[321] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[257] ),
        .O(\mcal_DQIn_byte_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[20]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[212] ),
        .I1(\mcal_DQIn_r_reg_n_0_[148] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[84] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[20] ),
        .O(\mcal_DQIn_byte_r[20]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[20]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[468] ),
        .I1(\mcal_DQIn_r_reg_n_0_[404] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[340] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[276] ),
        .O(\mcal_DQIn_byte_r[20]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[21]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[213] ),
        .I1(\mcal_DQIn_r_reg_n_0_[149] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[85] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[21] ),
        .O(\mcal_DQIn_byte_r[21]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[21]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[469] ),
        .I1(\mcal_DQIn_r_reg_n_0_[405] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[341] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[277] ),
        .O(\mcal_DQIn_byte_r[21]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[22]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[214] ),
        .I1(\mcal_DQIn_r_reg_n_0_[150] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[86] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[22] ),
        .O(\mcal_DQIn_byte_r[22]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[22]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[470] ),
        .I1(\mcal_DQIn_r_reg_n_0_[406] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[342] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[278] ),
        .O(\mcal_DQIn_byte_r[22]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[23]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[215] ),
        .I1(\mcal_DQIn_r_reg_n_0_[151] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[87] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[23] ),
        .O(\mcal_DQIn_byte_r[23]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[23]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[471] ),
        .I1(\mcal_DQIn_r_reg_n_0_[407] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[343] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[279] ),
        .O(\mcal_DQIn_byte_r[23]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[24]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[216] ),
        .I1(\mcal_DQIn_r_reg_n_0_[152] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[88] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[24] ),
        .O(\mcal_DQIn_byte_r[24]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[24]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[472] ),
        .I1(\mcal_DQIn_r_reg_n_0_[408] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[344] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[280] ),
        .O(\mcal_DQIn_byte_r[24]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[25]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[217] ),
        .I1(\mcal_DQIn_r_reg_n_0_[153] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[89] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[25] ),
        .O(\mcal_DQIn_byte_r[25]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[25]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[473] ),
        .I1(\mcal_DQIn_r_reg_n_0_[409] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[345] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[281] ),
        .O(\mcal_DQIn_byte_r[25]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[26]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[218] ),
        .I1(\mcal_DQIn_r_reg_n_0_[154] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[90] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[26] ),
        .O(\mcal_DQIn_byte_r[26]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[26]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[474] ),
        .I1(\mcal_DQIn_r_reg_n_0_[410] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[346] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[282] ),
        .O(\mcal_DQIn_byte_r[26]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[27]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[219] ),
        .I1(\mcal_DQIn_r_reg_n_0_[155] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[91] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[27] ),
        .O(\mcal_DQIn_byte_r[27]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[27]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[475] ),
        .I1(\mcal_DQIn_r_reg_n_0_[411] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[347] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[283] ),
        .O(\mcal_DQIn_byte_r[27]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[28]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[220] ),
        .I1(\mcal_DQIn_r_reg_n_0_[156] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[92] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[28] ),
        .O(\mcal_DQIn_byte_r[28]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[28]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[476] ),
        .I1(\mcal_DQIn_r_reg_n_0_[412] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[348] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[284] ),
        .O(\mcal_DQIn_byte_r[28]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[29]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[221] ),
        .I1(\mcal_DQIn_r_reg_n_0_[157] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[93] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[29] ),
        .O(\mcal_DQIn_byte_r[29]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[29]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[477] ),
        .I1(\mcal_DQIn_r_reg_n_0_[413] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[349] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[285] ),
        .O(\mcal_DQIn_byte_r[29]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[2]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[194] ),
        .I1(\mcal_DQIn_r_reg_n_0_[130] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[66] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[2] ),
        .O(\mcal_DQIn_byte_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[2]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[450] ),
        .I1(\mcal_DQIn_r_reg_n_0_[386] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[322] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[258] ),
        .O(\mcal_DQIn_byte_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[30]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[222] ),
        .I1(\mcal_DQIn_r_reg_n_0_[158] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[94] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[30] ),
        .O(\mcal_DQIn_byte_r[30]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[30]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[478] ),
        .I1(\mcal_DQIn_r_reg_n_0_[414] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[350] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[286] ),
        .O(\mcal_DQIn_byte_r[30]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[31]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[223] ),
        .I1(\mcal_DQIn_r_reg_n_0_[159] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[95] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[31] ),
        .O(\mcal_DQIn_byte_r[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[31]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[479] ),
        .I1(\mcal_DQIn_r_reg_n_0_[415] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[351] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[287] ),
        .O(\mcal_DQIn_byte_r[31]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[32]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[224] ),
        .I1(\mcal_DQIn_r_reg_n_0_[160] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[96] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(p_0_in[0]),
        .O(\mcal_DQIn_byte_r[32]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[32]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[480] ),
        .I1(\mcal_DQIn_r_reg_n_0_[416] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[352] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[288] ),
        .O(\mcal_DQIn_byte_r[32]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[33]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[225] ),
        .I1(\mcal_DQIn_r_reg_n_0_[161] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[97] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(p_0_in[1]),
        .O(\mcal_DQIn_byte_r[33]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[33]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[481] ),
        .I1(\mcal_DQIn_r_reg_n_0_[417] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[353] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[289] ),
        .O(\mcal_DQIn_byte_r[33]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[34]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[226] ),
        .I1(\mcal_DQIn_r_reg_n_0_[162] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[98] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(p_0_in[2]),
        .O(\mcal_DQIn_byte_r[34]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[34]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[482] ),
        .I1(\mcal_DQIn_r_reg_n_0_[418] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[354] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[290] ),
        .O(\mcal_DQIn_byte_r[34]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[35]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[227] ),
        .I1(\mcal_DQIn_r_reg_n_0_[163] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[99] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(p_0_in[3]),
        .O(\mcal_DQIn_byte_r[35]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[35]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[483] ),
        .I1(\mcal_DQIn_r_reg_n_0_[419] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[355] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[291] ),
        .O(\mcal_DQIn_byte_r[35]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[36]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[228] ),
        .I1(\mcal_DQIn_r_reg_n_0_[164] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[100] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(p_0_in[4]),
        .O(\mcal_DQIn_byte_r[36]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[36]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[484] ),
        .I1(\mcal_DQIn_r_reg_n_0_[420] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[356] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[292] ),
        .O(\mcal_DQIn_byte_r[36]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[37]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[229] ),
        .I1(\mcal_DQIn_r_reg_n_0_[165] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[101] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(p_0_in[5]),
        .O(\mcal_DQIn_byte_r[37]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[37]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[485] ),
        .I1(\mcal_DQIn_r_reg_n_0_[421] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[357] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[293] ),
        .O(\mcal_DQIn_byte_r[37]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[38]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[230] ),
        .I1(\mcal_DQIn_r_reg_n_0_[166] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[102] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(p_0_in[6]),
        .O(\mcal_DQIn_byte_r[38]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[38]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[486] ),
        .I1(\mcal_DQIn_r_reg_n_0_[422] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[358] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[294] ),
        .O(\mcal_DQIn_byte_r[38]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[39]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[231] ),
        .I1(\mcal_DQIn_r_reg_n_0_[167] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[103] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(p_0_in[7]),
        .O(\mcal_DQIn_byte_r[39]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[39]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[487] ),
        .I1(\mcal_DQIn_r_reg_n_0_[423] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[359] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[295] ),
        .O(\mcal_DQIn_byte_r[39]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[3]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[195] ),
        .I1(\mcal_DQIn_r_reg_n_0_[131] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[67] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[3] ),
        .O(\mcal_DQIn_byte_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[3]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[451] ),
        .I1(\mcal_DQIn_r_reg_n_0_[387] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[323] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[259] ),
        .O(\mcal_DQIn_byte_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[40]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[232] ),
        .I1(\mcal_DQIn_r_reg_n_0_[168] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[104] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[40] ),
        .O(\mcal_DQIn_byte_r[40]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[40]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[488] ),
        .I1(\mcal_DQIn_r_reg_n_0_[424] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[360] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[296] ),
        .O(\mcal_DQIn_byte_r[40]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[41]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[233] ),
        .I1(\mcal_DQIn_r_reg_n_0_[169] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[105] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[41] ),
        .O(\mcal_DQIn_byte_r[41]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[41]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[489] ),
        .I1(\mcal_DQIn_r_reg_n_0_[425] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[361] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[297] ),
        .O(\mcal_DQIn_byte_r[41]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[42]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[234] ),
        .I1(\mcal_DQIn_r_reg_n_0_[170] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[106] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[42] ),
        .O(\mcal_DQIn_byte_r[42]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[42]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[490] ),
        .I1(\mcal_DQIn_r_reg_n_0_[426] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[362] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[298] ),
        .O(\mcal_DQIn_byte_r[42]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[43]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[235] ),
        .I1(\mcal_DQIn_r_reg_n_0_[171] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[107] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[43] ),
        .O(\mcal_DQIn_byte_r[43]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[43]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[491] ),
        .I1(\mcal_DQIn_r_reg_n_0_[427] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[363] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[299] ),
        .O(\mcal_DQIn_byte_r[43]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[44]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[236] ),
        .I1(\mcal_DQIn_r_reg_n_0_[172] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[108] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[44] ),
        .O(\mcal_DQIn_byte_r[44]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[44]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[492] ),
        .I1(\mcal_DQIn_r_reg_n_0_[428] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[364] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[300] ),
        .O(\mcal_DQIn_byte_r[44]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[45]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[237] ),
        .I1(\mcal_DQIn_r_reg_n_0_[173] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[109] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[45] ),
        .O(\mcal_DQIn_byte_r[45]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[45]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[493] ),
        .I1(\mcal_DQIn_r_reg_n_0_[429] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[365] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[301] ),
        .O(\mcal_DQIn_byte_r[45]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[46]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[238] ),
        .I1(\mcal_DQIn_r_reg_n_0_[174] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[110] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[46] ),
        .O(\mcal_DQIn_byte_r[46]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[46]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[494] ),
        .I1(\mcal_DQIn_r_reg_n_0_[430] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[366] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[302] ),
        .O(\mcal_DQIn_byte_r[46]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[47]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[239] ),
        .I1(\mcal_DQIn_r_reg_n_0_[175] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[111] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[47] ),
        .O(\mcal_DQIn_byte_r[47]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[47]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[495] ),
        .I1(\mcal_DQIn_r_reg_n_0_[431] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[367] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[303] ),
        .O(\mcal_DQIn_byte_r[47]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[48]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[240] ),
        .I1(\mcal_DQIn_r_reg_n_0_[176] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[112] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[48] ),
        .O(\mcal_DQIn_byte_r[48]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[48]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[496] ),
        .I1(\mcal_DQIn_r_reg_n_0_[432] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[368] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[304] ),
        .O(\mcal_DQIn_byte_r[48]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[49]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[241] ),
        .I1(\mcal_DQIn_r_reg_n_0_[177] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[113] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[49] ),
        .O(\mcal_DQIn_byte_r[49]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[49]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[497] ),
        .I1(\mcal_DQIn_r_reg_n_0_[433] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[369] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[305] ),
        .O(\mcal_DQIn_byte_r[49]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[4]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[196] ),
        .I1(\mcal_DQIn_r_reg_n_0_[132] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[68] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[4] ),
        .O(\mcal_DQIn_byte_r[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[4]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[452] ),
        .I1(\mcal_DQIn_r_reg_n_0_[388] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[324] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[260] ),
        .O(\mcal_DQIn_byte_r[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[50]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[242] ),
        .I1(\mcal_DQIn_r_reg_n_0_[178] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[114] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[50] ),
        .O(\mcal_DQIn_byte_r[50]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[50]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[498] ),
        .I1(\mcal_DQIn_r_reg_n_0_[434] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[370] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[306] ),
        .O(\mcal_DQIn_byte_r[50]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[51]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[243] ),
        .I1(\mcal_DQIn_r_reg_n_0_[179] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[115] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[51] ),
        .O(\mcal_DQIn_byte_r[51]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[51]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[499] ),
        .I1(\mcal_DQIn_r_reg_n_0_[435] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[371] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[307] ),
        .O(\mcal_DQIn_byte_r[51]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[52]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[244] ),
        .I1(\mcal_DQIn_r_reg_n_0_[180] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[116] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[52] ),
        .O(\mcal_DQIn_byte_r[52]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[52]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[500] ),
        .I1(\mcal_DQIn_r_reg_n_0_[436] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[372] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[308] ),
        .O(\mcal_DQIn_byte_r[52]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[53]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[245] ),
        .I1(\mcal_DQIn_r_reg_n_0_[181] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[117] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[53] ),
        .O(\mcal_DQIn_byte_r[53]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[53]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[501] ),
        .I1(\mcal_DQIn_r_reg_n_0_[437] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[373] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[309] ),
        .O(\mcal_DQIn_byte_r[53]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[54]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[246] ),
        .I1(\mcal_DQIn_r_reg_n_0_[182] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[118] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[54] ),
        .O(\mcal_DQIn_byte_r[54]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[54]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[502] ),
        .I1(\mcal_DQIn_r_reg_n_0_[438] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[374] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[310] ),
        .O(\mcal_DQIn_byte_r[54]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[55]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[247] ),
        .I1(\mcal_DQIn_r_reg_n_0_[183] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[119] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[55] ),
        .O(\mcal_DQIn_byte_r[55]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[55]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[503] ),
        .I1(\mcal_DQIn_r_reg_n_0_[439] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[375] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[311] ),
        .O(\mcal_DQIn_byte_r[55]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[56]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[248] ),
        .I1(\mcal_DQIn_r_reg_n_0_[184] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[120] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[56] ),
        .O(\mcal_DQIn_byte_r[56]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[56]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[504] ),
        .I1(\mcal_DQIn_r_reg_n_0_[440] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[376] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[312] ),
        .O(\mcal_DQIn_byte_r[56]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[57]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[249] ),
        .I1(\mcal_DQIn_r_reg_n_0_[185] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[121] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[57] ),
        .O(\mcal_DQIn_byte_r[57]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[57]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[505] ),
        .I1(\mcal_DQIn_r_reg_n_0_[441] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[377] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[313] ),
        .O(\mcal_DQIn_byte_r[57]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[58]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[250] ),
        .I1(\mcal_DQIn_r_reg_n_0_[186] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[122] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[58] ),
        .O(\mcal_DQIn_byte_r[58]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[58]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[506] ),
        .I1(\mcal_DQIn_r_reg_n_0_[442] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[378] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[314] ),
        .O(\mcal_DQIn_byte_r[58]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[59]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[251] ),
        .I1(\mcal_DQIn_r_reg_n_0_[187] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[123] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[59] ),
        .O(\mcal_DQIn_byte_r[59]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[59]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[507] ),
        .I1(\mcal_DQIn_r_reg_n_0_[443] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[379] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[315] ),
        .O(\mcal_DQIn_byte_r[59]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[5]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[197] ),
        .I1(\mcal_DQIn_r_reg_n_0_[133] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[69] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[5] ),
        .O(\mcal_DQIn_byte_r[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[5]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[453] ),
        .I1(\mcal_DQIn_r_reg_n_0_[389] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[325] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[261] ),
        .O(\mcal_DQIn_byte_r[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[60]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[252] ),
        .I1(\mcal_DQIn_r_reg_n_0_[188] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[124] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[60] ),
        .O(\mcal_DQIn_byte_r[60]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[60]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[508] ),
        .I1(\mcal_DQIn_r_reg_n_0_[444] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[380] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[316] ),
        .O(\mcal_DQIn_byte_r[60]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[61]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[253] ),
        .I1(\mcal_DQIn_r_reg_n_0_[189] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[125] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[61] ),
        .O(\mcal_DQIn_byte_r[61]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[61]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[509] ),
        .I1(\mcal_DQIn_r_reg_n_0_[445] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[381] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[317] ),
        .O(\mcal_DQIn_byte_r[61]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[62]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[254] ),
        .I1(\mcal_DQIn_r_reg_n_0_[190] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[126] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[62] ),
        .O(\mcal_DQIn_byte_r[62]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[62]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[510] ),
        .I1(\mcal_DQIn_r_reg_n_0_[446] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[382] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[318] ),
        .O(\mcal_DQIn_byte_r[62]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \mcal_DQIn_byte_r[63]_i_1 
       (.I0(wrlvl_mode),
        .I1(p_0_in32_in),
        .O(mcal_DQIn_byte_r0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[63]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[255] ),
        .I1(\mcal_DQIn_r_reg_n_0_[191] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[127] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[63] ),
        .O(\mcal_DQIn_byte_r[63]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[63]_i_4 
       (.I0(\mcal_DQIn_r_reg_n_0_[511] ),
        .I1(\mcal_DQIn_r_reg_n_0_[447] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[383] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[319] ),
        .O(\mcal_DQIn_byte_r[63]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[6]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[198] ),
        .I1(\mcal_DQIn_r_reg_n_0_[134] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[70] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[6] ),
        .O(\mcal_DQIn_byte_r[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[6]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[454] ),
        .I1(\mcal_DQIn_r_reg_n_0_[390] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[326] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[262] ),
        .O(\mcal_DQIn_byte_r[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[7]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[199] ),
        .I1(\mcal_DQIn_r_reg_n_0_[135] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[71] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[7] ),
        .O(\mcal_DQIn_byte_r[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[7]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[455] ),
        .I1(\mcal_DQIn_r_reg_n_0_[391] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[327] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[263] ),
        .O(\mcal_DQIn_byte_r[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[8]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[200] ),
        .I1(\mcal_DQIn_r_reg_n_0_[136] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[72] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[8] ),
        .O(\mcal_DQIn_byte_r[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[8]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[456] ),
        .I1(\mcal_DQIn_r_reg_n_0_[392] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[328] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[264] ),
        .O(\mcal_DQIn_byte_r[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[9]_i_2 
       (.I0(\mcal_DQIn_r_reg_n_0_[201] ),
        .I1(\mcal_DQIn_r_reg_n_0_[137] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[73] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[9] ),
        .O(\mcal_DQIn_byte_r[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \mcal_DQIn_byte_r[9]_i_3 
       (.I0(\mcal_DQIn_r_reg_n_0_[457] ),
        .I1(\mcal_DQIn_r_reg_n_0_[393] ),
        .I2(\cmp_byte_reg[1]_rep_n_0 ),
        .I3(\mcal_DQIn_r_reg_n_0_[329] ),
        .I4(\cmp_byte_reg[0]_rep_n_0 ),
        .I5(\mcal_DQIn_r_reg_n_0_[265] ),
        .O(\mcal_DQIn_byte_r[9]_i_3_n_0 ));
  FDRE \mcal_DQIn_byte_r_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[0]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[0]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[0]_i_1 
       (.I0(\mcal_DQIn_byte_r[0]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[0]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[0]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[10]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[10]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[10]_i_1 
       (.I0(\mcal_DQIn_byte_r[10]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[10]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[10]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[11]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[11]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[11]_i_1 
       (.I0(\mcal_DQIn_byte_r[11]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[11]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[11]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[12]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[12]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[12]_i_1 
       (.I0(\mcal_DQIn_byte_r[12]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[12]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[12]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[13]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[13]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[13]_i_1 
       (.I0(\mcal_DQIn_byte_r[13]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[13]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[13]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[14]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[14]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[14]_i_1 
       (.I0(\mcal_DQIn_byte_r[14]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[14]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[14]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[15]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[15]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[15]_i_1 
       (.I0(\mcal_DQIn_byte_r[15]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[15]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[15]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[16]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[16]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[16]_i_1 
       (.I0(\mcal_DQIn_byte_r[16]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[16]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[16]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[17]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[17]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[17]_i_1 
       (.I0(\mcal_DQIn_byte_r[17]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[17]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[17]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[18]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[18]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[18]_i_1 
       (.I0(\mcal_DQIn_byte_r[18]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[18]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[18]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[19]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[19]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[19]_i_1 
       (.I0(\mcal_DQIn_byte_r[19]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[19]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[19]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[1]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[1]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[1]_i_1 
       (.I0(\mcal_DQIn_byte_r[1]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[1]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[1]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[20]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[20]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[20]_i_1 
       (.I0(\mcal_DQIn_byte_r[20]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[20]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[20]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[21]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[21]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[21]_i_1 
       (.I0(\mcal_DQIn_byte_r[21]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[21]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[21]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[22]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[22]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[22]_i_1 
       (.I0(\mcal_DQIn_byte_r[22]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[22]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[22]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[23]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[23]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[23]_i_1 
       (.I0(\mcal_DQIn_byte_r[23]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[23]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[23]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[24]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[24]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[24]_i_1 
       (.I0(\mcal_DQIn_byte_r[24]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[24]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[24]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[25]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[25]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[25]_i_1 
       (.I0(\mcal_DQIn_byte_r[25]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[25]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[25]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[26]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[26]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[26]_i_1 
       (.I0(\mcal_DQIn_byte_r[26]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[26]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[26]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[27]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[27]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[27]_i_1 
       (.I0(\mcal_DQIn_byte_r[27]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[27]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[27]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[28]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[28]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[28]_i_1 
       (.I0(\mcal_DQIn_byte_r[28]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[28]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[28]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[29]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[29]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[29]_i_1 
       (.I0(\mcal_DQIn_byte_r[29]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[29]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[29]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[2]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[2]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[2]_i_1 
       (.I0(\mcal_DQIn_byte_r[2]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[2]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[2]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[30]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[30]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[30]_i_1 
       (.I0(\mcal_DQIn_byte_r[30]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[30]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[30]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[31]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[31]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[31]_i_1 
       (.I0(\mcal_DQIn_byte_r[31]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[31]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[31]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[32]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[32]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[32]_i_1 
       (.I0(\mcal_DQIn_byte_r[32]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[32]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[32]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[33]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[33]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[33]_i_1 
       (.I0(\mcal_DQIn_byte_r[33]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[33]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[33]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[34]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[34]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[34]_i_1 
       (.I0(\mcal_DQIn_byte_r[34]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[34]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[34]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[35]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[35]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[35]_i_1 
       (.I0(\mcal_DQIn_byte_r[35]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[35]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[35]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[36]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[36]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[36]_i_1 
       (.I0(\mcal_DQIn_byte_r[36]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[36]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[36]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[37]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[37]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[37]_i_1 
       (.I0(\mcal_DQIn_byte_r[37]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[37]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[37]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[38]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[38]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[38]_i_1 
       (.I0(\mcal_DQIn_byte_r[38]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[38]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[38]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[39]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[39]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[39]_i_1 
       (.I0(\mcal_DQIn_byte_r[39]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[39]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[39]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[3]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[3]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[3]_i_1 
       (.I0(\mcal_DQIn_byte_r[3]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[3]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[3]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[40]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[40]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[40]_i_1 
       (.I0(\mcal_DQIn_byte_r[40]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[40]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[40]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[41]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[41]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[41]_i_1 
       (.I0(\mcal_DQIn_byte_r[41]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[41]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[41]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[42]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[42]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[42]_i_1 
       (.I0(\mcal_DQIn_byte_r[42]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[42]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[42]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[43]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[43]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[43]_i_1 
       (.I0(\mcal_DQIn_byte_r[43]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[43]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[43]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[44]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[44]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[44]_i_1 
       (.I0(\mcal_DQIn_byte_r[44]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[44]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[44]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[45]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[45]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[45]_i_1 
       (.I0(\mcal_DQIn_byte_r[45]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[45]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[45]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[46]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[46]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[46]_i_1 
       (.I0(\mcal_DQIn_byte_r[46]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[46]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[46]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[47]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[47]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[47]_i_1 
       (.I0(\mcal_DQIn_byte_r[47]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[47]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[47]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[48]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[48]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[48]_i_1 
       (.I0(\mcal_DQIn_byte_r[48]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[48]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[48]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[49]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[49]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[49]_i_1 
       (.I0(\mcal_DQIn_byte_r[49]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[49]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[49]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[4]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[4]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[4]_i_1 
       (.I0(\mcal_DQIn_byte_r[4]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[4]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[4]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[50]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[50]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[50]_i_1 
       (.I0(\mcal_DQIn_byte_r[50]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[50]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[50]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[51]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[51]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[51]_i_1 
       (.I0(\mcal_DQIn_byte_r[51]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[51]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[51]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[52]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[52]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[52]_i_1 
       (.I0(\mcal_DQIn_byte_r[52]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[52]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[52]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[53]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[53]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[53]_i_1 
       (.I0(\mcal_DQIn_byte_r[53]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[53]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[53]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[54]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[54]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[54]_i_1 
       (.I0(\mcal_DQIn_byte_r[54]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[54]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[54]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[55]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[55]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[55]_i_1 
       (.I0(\mcal_DQIn_byte_r[55]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[55]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[55]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[56]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[56]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[56]_i_1 
       (.I0(\mcal_DQIn_byte_r[56]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[56]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[56]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[57]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[57]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[57]_i_1 
       (.I0(\mcal_DQIn_byte_r[57]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[57]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[57]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[58]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[58]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[58]_i_1 
       (.I0(\mcal_DQIn_byte_r[58]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[58]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[58]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[59]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[59]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[59]_i_1 
       (.I0(\mcal_DQIn_byte_r[59]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[59]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[59]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[5]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[5]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[5]_i_1 
       (.I0(\mcal_DQIn_byte_r[5]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[5]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[5]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[60]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[60]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[60]_i_1 
       (.I0(\mcal_DQIn_byte_r[60]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[60]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[60]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[61]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[61]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[61]_i_1 
       (.I0(\mcal_DQIn_byte_r[61]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[61]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[61]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[62]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[62]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[62]_i_1 
       (.I0(\mcal_DQIn_byte_r[62]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[62]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[62]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[63]_i_2_n_0 ),
        .Q(mcal_DQIn_byte_r[63]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[63]_i_2 
       (.I0(\mcal_DQIn_byte_r[63]_i_3_n_0 ),
        .I1(\mcal_DQIn_byte_r[63]_i_4_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[63]_i_2_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[6]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[6]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[6]_i_1 
       (.I0(\mcal_DQIn_byte_r[6]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[6]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[6]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[7]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[7]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[7]_i_1 
       (.I0(\mcal_DQIn_byte_r[7]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[7]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[7]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[8]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[8]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[8]_i_1 
       (.I0(\mcal_DQIn_byte_r[8]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[8]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[8]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_byte_r_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_byte_r_reg[9]_i_1_n_0 ),
        .Q(mcal_DQIn_byte_r[9]),
        .R(1'b0));
  MUXF7 \mcal_DQIn_byte_r_reg[9]_i_1 
       (.I0(\mcal_DQIn_byte_r[9]_i_2_n_0 ),
        .I1(\mcal_DQIn_byte_r[9]_i_3_n_0 ),
        .O(\mcal_DQIn_byte_r_reg[9]_i_1_n_0 ),
        .S(\cmp_byte_reg_n_0_[2] ));
  FDRE \mcal_DQIn_r_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [0]),
        .Q(\mcal_DQIn_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[100] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [100]),
        .Q(\mcal_DQIn_r_reg_n_0_[100] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[101] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [101]),
        .Q(\mcal_DQIn_r_reg_n_0_[101] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[102] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [102]),
        .Q(\mcal_DQIn_r_reg_n_0_[102] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[103] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [103]),
        .Q(\mcal_DQIn_r_reg_n_0_[103] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[104] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [104]),
        .Q(\mcal_DQIn_r_reg_n_0_[104] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[105] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [105]),
        .Q(\mcal_DQIn_r_reg_n_0_[105] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[106] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [106]),
        .Q(\mcal_DQIn_r_reg_n_0_[106] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[107] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [107]),
        .Q(\mcal_DQIn_r_reg_n_0_[107] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[108] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [108]),
        .Q(\mcal_DQIn_r_reg_n_0_[108] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[109] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [109]),
        .Q(\mcal_DQIn_r_reg_n_0_[109] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [10]),
        .Q(\mcal_DQIn_r_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[110] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [110]),
        .Q(\mcal_DQIn_r_reg_n_0_[110] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[111] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [111]),
        .Q(\mcal_DQIn_r_reg_n_0_[111] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[112] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [112]),
        .Q(\mcal_DQIn_r_reg_n_0_[112] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[113] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [113]),
        .Q(\mcal_DQIn_r_reg_n_0_[113] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[114] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [114]),
        .Q(\mcal_DQIn_r_reg_n_0_[114] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[115] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [115]),
        .Q(\mcal_DQIn_r_reg_n_0_[115] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[116] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [116]),
        .Q(\mcal_DQIn_r_reg_n_0_[116] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[117] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [117]),
        .Q(\mcal_DQIn_r_reg_n_0_[117] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[118] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [118]),
        .Q(\mcal_DQIn_r_reg_n_0_[118] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[119] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [119]),
        .Q(\mcal_DQIn_r_reg_n_0_[119] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [11]),
        .Q(\mcal_DQIn_r_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[120] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [120]),
        .Q(\mcal_DQIn_r_reg_n_0_[120] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[121] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [121]),
        .Q(\mcal_DQIn_r_reg_n_0_[121] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[122] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [122]),
        .Q(\mcal_DQIn_r_reg_n_0_[122] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[123] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [123]),
        .Q(\mcal_DQIn_r_reg_n_0_[123] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[124] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [124]),
        .Q(\mcal_DQIn_r_reg_n_0_[124] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[125] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [125]),
        .Q(\mcal_DQIn_r_reg_n_0_[125] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[126] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [126]),
        .Q(\mcal_DQIn_r_reg_n_0_[126] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[127] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [127]),
        .Q(\mcal_DQIn_r_reg_n_0_[127] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[128] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [128]),
        .Q(\mcal_DQIn_r_reg_n_0_[128] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[129] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [129]),
        .Q(\mcal_DQIn_r_reg_n_0_[129] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [12]),
        .Q(\mcal_DQIn_r_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[130] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [130]),
        .Q(\mcal_DQIn_r_reg_n_0_[130] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[131] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [131]),
        .Q(\mcal_DQIn_r_reg_n_0_[131] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[132] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [132]),
        .Q(\mcal_DQIn_r_reg_n_0_[132] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[133] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [133]),
        .Q(\mcal_DQIn_r_reg_n_0_[133] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[134] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [134]),
        .Q(\mcal_DQIn_r_reg_n_0_[134] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[135] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [135]),
        .Q(\mcal_DQIn_r_reg_n_0_[135] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[136] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [136]),
        .Q(\mcal_DQIn_r_reg_n_0_[136] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[137] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [137]),
        .Q(\mcal_DQIn_r_reg_n_0_[137] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[138] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [138]),
        .Q(\mcal_DQIn_r_reg_n_0_[138] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[139] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [139]),
        .Q(\mcal_DQIn_r_reg_n_0_[139] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [13]),
        .Q(\mcal_DQIn_r_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[140] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [140]),
        .Q(\mcal_DQIn_r_reg_n_0_[140] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[141] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [141]),
        .Q(\mcal_DQIn_r_reg_n_0_[141] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[142] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [142]),
        .Q(\mcal_DQIn_r_reg_n_0_[142] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[143] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [143]),
        .Q(\mcal_DQIn_r_reg_n_0_[143] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[144] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [144]),
        .Q(\mcal_DQIn_r_reg_n_0_[144] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[145] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [145]),
        .Q(\mcal_DQIn_r_reg_n_0_[145] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[146] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [146]),
        .Q(\mcal_DQIn_r_reg_n_0_[146] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[147] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [147]),
        .Q(\mcal_DQIn_r_reg_n_0_[147] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[148] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [148]),
        .Q(\mcal_DQIn_r_reg_n_0_[148] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[149] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [149]),
        .Q(\mcal_DQIn_r_reg_n_0_[149] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [14]),
        .Q(\mcal_DQIn_r_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[150] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [150]),
        .Q(\mcal_DQIn_r_reg_n_0_[150] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[151] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [151]),
        .Q(\mcal_DQIn_r_reg_n_0_[151] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[152] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [152]),
        .Q(\mcal_DQIn_r_reg_n_0_[152] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[153] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [153]),
        .Q(\mcal_DQIn_r_reg_n_0_[153] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[154] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [154]),
        .Q(\mcal_DQIn_r_reg_n_0_[154] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[155] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [155]),
        .Q(\mcal_DQIn_r_reg_n_0_[155] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[156] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [156]),
        .Q(\mcal_DQIn_r_reg_n_0_[156] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[157] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [157]),
        .Q(\mcal_DQIn_r_reg_n_0_[157] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[158] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [158]),
        .Q(\mcal_DQIn_r_reg_n_0_[158] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[159] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [159]),
        .Q(\mcal_DQIn_r_reg_n_0_[159] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [15]),
        .Q(\mcal_DQIn_r_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[160] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [160]),
        .Q(\mcal_DQIn_r_reg_n_0_[160] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[161] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [161]),
        .Q(\mcal_DQIn_r_reg_n_0_[161] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[162] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [162]),
        .Q(\mcal_DQIn_r_reg_n_0_[162] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[163] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [163]),
        .Q(\mcal_DQIn_r_reg_n_0_[163] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[164] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [164]),
        .Q(\mcal_DQIn_r_reg_n_0_[164] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[165] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [165]),
        .Q(\mcal_DQIn_r_reg_n_0_[165] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[166] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [166]),
        .Q(\mcal_DQIn_r_reg_n_0_[166] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[167] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [167]),
        .Q(\mcal_DQIn_r_reg_n_0_[167] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[168] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [168]),
        .Q(\mcal_DQIn_r_reg_n_0_[168] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[169] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [169]),
        .Q(\mcal_DQIn_r_reg_n_0_[169] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [16]),
        .Q(\mcal_DQIn_r_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[170] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [170]),
        .Q(\mcal_DQIn_r_reg_n_0_[170] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[171] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [171]),
        .Q(\mcal_DQIn_r_reg_n_0_[171] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[172] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [172]),
        .Q(\mcal_DQIn_r_reg_n_0_[172] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[173] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [173]),
        .Q(\mcal_DQIn_r_reg_n_0_[173] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[174] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [174]),
        .Q(\mcal_DQIn_r_reg_n_0_[174] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[175] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [175]),
        .Q(\mcal_DQIn_r_reg_n_0_[175] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[176] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [176]),
        .Q(\mcal_DQIn_r_reg_n_0_[176] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[177] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [177]),
        .Q(\mcal_DQIn_r_reg_n_0_[177] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[178] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [178]),
        .Q(\mcal_DQIn_r_reg_n_0_[178] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[179] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [179]),
        .Q(\mcal_DQIn_r_reg_n_0_[179] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [17]),
        .Q(\mcal_DQIn_r_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[180] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [180]),
        .Q(\mcal_DQIn_r_reg_n_0_[180] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[181] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [181]),
        .Q(\mcal_DQIn_r_reg_n_0_[181] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[182] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [182]),
        .Q(\mcal_DQIn_r_reg_n_0_[182] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[183] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [183]),
        .Q(\mcal_DQIn_r_reg_n_0_[183] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[184] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [184]),
        .Q(\mcal_DQIn_r_reg_n_0_[184] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[185] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [185]),
        .Q(\mcal_DQIn_r_reg_n_0_[185] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[186] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [186]),
        .Q(\mcal_DQIn_r_reg_n_0_[186] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[187] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [187]),
        .Q(\mcal_DQIn_r_reg_n_0_[187] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[188] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [188]),
        .Q(\mcal_DQIn_r_reg_n_0_[188] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[189] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [189]),
        .Q(\mcal_DQIn_r_reg_n_0_[189] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [18]),
        .Q(\mcal_DQIn_r_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[190] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [190]),
        .Q(\mcal_DQIn_r_reg_n_0_[190] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[191] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [191]),
        .Q(\mcal_DQIn_r_reg_n_0_[191] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[192] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [192]),
        .Q(\mcal_DQIn_r_reg_n_0_[192] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[193] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [193]),
        .Q(\mcal_DQIn_r_reg_n_0_[193] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[194] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [194]),
        .Q(\mcal_DQIn_r_reg_n_0_[194] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[195] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [195]),
        .Q(\mcal_DQIn_r_reg_n_0_[195] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[196] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [196]),
        .Q(\mcal_DQIn_r_reg_n_0_[196] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[197] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [197]),
        .Q(\mcal_DQIn_r_reg_n_0_[197] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[198] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [198]),
        .Q(\mcal_DQIn_r_reg_n_0_[198] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[199] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [199]),
        .Q(\mcal_DQIn_r_reg_n_0_[199] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [19]),
        .Q(\mcal_DQIn_r_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [1]),
        .Q(\mcal_DQIn_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[200] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [200]),
        .Q(\mcal_DQIn_r_reg_n_0_[200] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[201] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [201]),
        .Q(\mcal_DQIn_r_reg_n_0_[201] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[202] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [202]),
        .Q(\mcal_DQIn_r_reg_n_0_[202] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[203] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [203]),
        .Q(\mcal_DQIn_r_reg_n_0_[203] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[204] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [204]),
        .Q(\mcal_DQIn_r_reg_n_0_[204] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[205] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [205]),
        .Q(\mcal_DQIn_r_reg_n_0_[205] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[206] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [206]),
        .Q(\mcal_DQIn_r_reg_n_0_[206] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[207] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [207]),
        .Q(\mcal_DQIn_r_reg_n_0_[207] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[208] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [208]),
        .Q(\mcal_DQIn_r_reg_n_0_[208] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[209] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [209]),
        .Q(\mcal_DQIn_r_reg_n_0_[209] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [20]),
        .Q(\mcal_DQIn_r_reg_n_0_[20] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[210] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [210]),
        .Q(\mcal_DQIn_r_reg_n_0_[210] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[211] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [211]),
        .Q(\mcal_DQIn_r_reg_n_0_[211] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[212] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [212]),
        .Q(\mcal_DQIn_r_reg_n_0_[212] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[213] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [213]),
        .Q(\mcal_DQIn_r_reg_n_0_[213] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[214] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [214]),
        .Q(\mcal_DQIn_r_reg_n_0_[214] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[215] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [215]),
        .Q(\mcal_DQIn_r_reg_n_0_[215] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[216] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [216]),
        .Q(\mcal_DQIn_r_reg_n_0_[216] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[217] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [217]),
        .Q(\mcal_DQIn_r_reg_n_0_[217] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[218] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [218]),
        .Q(\mcal_DQIn_r_reg_n_0_[218] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[219] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [219]),
        .Q(\mcal_DQIn_r_reg_n_0_[219] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [21]),
        .Q(\mcal_DQIn_r_reg_n_0_[21] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[220] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [220]),
        .Q(\mcal_DQIn_r_reg_n_0_[220] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[221] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [221]),
        .Q(\mcal_DQIn_r_reg_n_0_[221] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[222] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [222]),
        .Q(\mcal_DQIn_r_reg_n_0_[222] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[223] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [223]),
        .Q(\mcal_DQIn_r_reg_n_0_[223] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[224] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [224]),
        .Q(\mcal_DQIn_r_reg_n_0_[224] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[225] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [225]),
        .Q(\mcal_DQIn_r_reg_n_0_[225] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[226] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [226]),
        .Q(\mcal_DQIn_r_reg_n_0_[226] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[227] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [227]),
        .Q(\mcal_DQIn_r_reg_n_0_[227] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[228] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [228]),
        .Q(\mcal_DQIn_r_reg_n_0_[228] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[229] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [229]),
        .Q(\mcal_DQIn_r_reg_n_0_[229] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [22]),
        .Q(\mcal_DQIn_r_reg_n_0_[22] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[230] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [230]),
        .Q(\mcal_DQIn_r_reg_n_0_[230] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[231] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [231]),
        .Q(\mcal_DQIn_r_reg_n_0_[231] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[232] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [232]),
        .Q(\mcal_DQIn_r_reg_n_0_[232] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[233] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [233]),
        .Q(\mcal_DQIn_r_reg_n_0_[233] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[234] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [234]),
        .Q(\mcal_DQIn_r_reg_n_0_[234] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[235] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [235]),
        .Q(\mcal_DQIn_r_reg_n_0_[235] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[236] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [236]),
        .Q(\mcal_DQIn_r_reg_n_0_[236] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[237] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [237]),
        .Q(\mcal_DQIn_r_reg_n_0_[237] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[238] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [238]),
        .Q(\mcal_DQIn_r_reg_n_0_[238] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[239] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [239]),
        .Q(\mcal_DQIn_r_reg_n_0_[239] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [23]),
        .Q(\mcal_DQIn_r_reg_n_0_[23] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[240] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [240]),
        .Q(\mcal_DQIn_r_reg_n_0_[240] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[241] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [241]),
        .Q(\mcal_DQIn_r_reg_n_0_[241] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[242] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [242]),
        .Q(\mcal_DQIn_r_reg_n_0_[242] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[243] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [243]),
        .Q(\mcal_DQIn_r_reg_n_0_[243] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[244] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [244]),
        .Q(\mcal_DQIn_r_reg_n_0_[244] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[245] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [245]),
        .Q(\mcal_DQIn_r_reg_n_0_[245] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[246] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [246]),
        .Q(\mcal_DQIn_r_reg_n_0_[246] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[247] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [247]),
        .Q(\mcal_DQIn_r_reg_n_0_[247] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[248] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [248]),
        .Q(\mcal_DQIn_r_reg_n_0_[248] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[249] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [249]),
        .Q(\mcal_DQIn_r_reg_n_0_[249] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [24]),
        .Q(\mcal_DQIn_r_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[250] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [250]),
        .Q(\mcal_DQIn_r_reg_n_0_[250] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[251] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [251]),
        .Q(\mcal_DQIn_r_reg_n_0_[251] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[252] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [252]),
        .Q(\mcal_DQIn_r_reg_n_0_[252] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[253] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [253]),
        .Q(\mcal_DQIn_r_reg_n_0_[253] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[254] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [254]),
        .Q(\mcal_DQIn_r_reg_n_0_[254] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[255] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [255]),
        .Q(\mcal_DQIn_r_reg_n_0_[255] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[256] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [256]),
        .Q(\mcal_DQIn_r_reg_n_0_[256] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[257] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [257]),
        .Q(\mcal_DQIn_r_reg_n_0_[257] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[258] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [258]),
        .Q(\mcal_DQIn_r_reg_n_0_[258] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[259] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [259]),
        .Q(\mcal_DQIn_r_reg_n_0_[259] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [25]),
        .Q(\mcal_DQIn_r_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[260] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [260]),
        .Q(\mcal_DQIn_r_reg_n_0_[260] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[261] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [261]),
        .Q(\mcal_DQIn_r_reg_n_0_[261] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[262] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [262]),
        .Q(\mcal_DQIn_r_reg_n_0_[262] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[263] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [263]),
        .Q(\mcal_DQIn_r_reg_n_0_[263] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[264] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [264]),
        .Q(\mcal_DQIn_r_reg_n_0_[264] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[265] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [265]),
        .Q(\mcal_DQIn_r_reg_n_0_[265] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[266] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [266]),
        .Q(\mcal_DQIn_r_reg_n_0_[266] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[267] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [267]),
        .Q(\mcal_DQIn_r_reg_n_0_[267] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[268] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [268]),
        .Q(\mcal_DQIn_r_reg_n_0_[268] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[269] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [269]),
        .Q(\mcal_DQIn_r_reg_n_0_[269] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [26]),
        .Q(\mcal_DQIn_r_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[270] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [270]),
        .Q(\mcal_DQIn_r_reg_n_0_[270] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[271] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [271]),
        .Q(\mcal_DQIn_r_reg_n_0_[271] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[272] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [272]),
        .Q(\mcal_DQIn_r_reg_n_0_[272] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[273] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [273]),
        .Q(\mcal_DQIn_r_reg_n_0_[273] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[274] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [274]),
        .Q(\mcal_DQIn_r_reg_n_0_[274] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[275] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [275]),
        .Q(\mcal_DQIn_r_reg_n_0_[275] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[276] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [276]),
        .Q(\mcal_DQIn_r_reg_n_0_[276] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[277] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [277]),
        .Q(\mcal_DQIn_r_reg_n_0_[277] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[278] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [278]),
        .Q(\mcal_DQIn_r_reg_n_0_[278] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[279] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [279]),
        .Q(\mcal_DQIn_r_reg_n_0_[279] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [27]),
        .Q(\mcal_DQIn_r_reg_n_0_[27] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[280] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [280]),
        .Q(\mcal_DQIn_r_reg_n_0_[280] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[281] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [281]),
        .Q(\mcal_DQIn_r_reg_n_0_[281] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[282] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [282]),
        .Q(\mcal_DQIn_r_reg_n_0_[282] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[283] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [283]),
        .Q(\mcal_DQIn_r_reg_n_0_[283] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[284] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [284]),
        .Q(\mcal_DQIn_r_reg_n_0_[284] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[285] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [285]),
        .Q(\mcal_DQIn_r_reg_n_0_[285] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[286] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [286]),
        .Q(\mcal_DQIn_r_reg_n_0_[286] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[287] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [287]),
        .Q(\mcal_DQIn_r_reg_n_0_[287] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[288] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [288]),
        .Q(\mcal_DQIn_r_reg_n_0_[288] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[289] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [289]),
        .Q(\mcal_DQIn_r_reg_n_0_[289] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [28]),
        .Q(\mcal_DQIn_r_reg_n_0_[28] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[290] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [290]),
        .Q(\mcal_DQIn_r_reg_n_0_[290] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[291] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [291]),
        .Q(\mcal_DQIn_r_reg_n_0_[291] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[292] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [292]),
        .Q(\mcal_DQIn_r_reg_n_0_[292] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[293] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [293]),
        .Q(\mcal_DQIn_r_reg_n_0_[293] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[294] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [294]),
        .Q(\mcal_DQIn_r_reg_n_0_[294] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[295] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [295]),
        .Q(\mcal_DQIn_r_reg_n_0_[295] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[296] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [296]),
        .Q(\mcal_DQIn_r_reg_n_0_[296] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[297] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [297]),
        .Q(\mcal_DQIn_r_reg_n_0_[297] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[298] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [298]),
        .Q(\mcal_DQIn_r_reg_n_0_[298] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[299] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [299]),
        .Q(\mcal_DQIn_r_reg_n_0_[299] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [29]),
        .Q(\mcal_DQIn_r_reg_n_0_[29] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [2]),
        .Q(\mcal_DQIn_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[300] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [300]),
        .Q(\mcal_DQIn_r_reg_n_0_[300] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[301] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [301]),
        .Q(\mcal_DQIn_r_reg_n_0_[301] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[302] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [302]),
        .Q(\mcal_DQIn_r_reg_n_0_[302] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[303] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [303]),
        .Q(\mcal_DQIn_r_reg_n_0_[303] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[304] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [304]),
        .Q(\mcal_DQIn_r_reg_n_0_[304] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[305] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [305]),
        .Q(\mcal_DQIn_r_reg_n_0_[305] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[306] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [306]),
        .Q(\mcal_DQIn_r_reg_n_0_[306] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[307] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [307]),
        .Q(\mcal_DQIn_r_reg_n_0_[307] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[308] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [308]),
        .Q(\mcal_DQIn_r_reg_n_0_[308] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[309] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [309]),
        .Q(\mcal_DQIn_r_reg_n_0_[309] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [30]),
        .Q(\mcal_DQIn_r_reg_n_0_[30] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[310] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [310]),
        .Q(\mcal_DQIn_r_reg_n_0_[310] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[311] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [311]),
        .Q(\mcal_DQIn_r_reg_n_0_[311] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[312] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [312]),
        .Q(\mcal_DQIn_r_reg_n_0_[312] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[313] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [313]),
        .Q(\mcal_DQIn_r_reg_n_0_[313] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[314] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [314]),
        .Q(\mcal_DQIn_r_reg_n_0_[314] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[315] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [315]),
        .Q(\mcal_DQIn_r_reg_n_0_[315] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[316] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [316]),
        .Q(\mcal_DQIn_r_reg_n_0_[316] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[317] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [317]),
        .Q(\mcal_DQIn_r_reg_n_0_[317] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[318] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [318]),
        .Q(\mcal_DQIn_r_reg_n_0_[318] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[319] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [319]),
        .Q(\mcal_DQIn_r_reg_n_0_[319] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [31]),
        .Q(\mcal_DQIn_r_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[320] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [320]),
        .Q(\mcal_DQIn_r_reg_n_0_[320] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[321] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [321]),
        .Q(\mcal_DQIn_r_reg_n_0_[321] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[322] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [322]),
        .Q(\mcal_DQIn_r_reg_n_0_[322] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[323] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [323]),
        .Q(\mcal_DQIn_r_reg_n_0_[323] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[324] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [324]),
        .Q(\mcal_DQIn_r_reg_n_0_[324] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[325] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [325]),
        .Q(\mcal_DQIn_r_reg_n_0_[325] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[326] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [326]),
        .Q(\mcal_DQIn_r_reg_n_0_[326] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[327] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [327]),
        .Q(\mcal_DQIn_r_reg_n_0_[327] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[328] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [328]),
        .Q(\mcal_DQIn_r_reg_n_0_[328] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[329] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [329]),
        .Q(\mcal_DQIn_r_reg_n_0_[329] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [32]),
        .Q(p_0_in[0]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[330] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [330]),
        .Q(\mcal_DQIn_r_reg_n_0_[330] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[331] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [331]),
        .Q(\mcal_DQIn_r_reg_n_0_[331] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[332] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [332]),
        .Q(\mcal_DQIn_r_reg_n_0_[332] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[333] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [333]),
        .Q(\mcal_DQIn_r_reg_n_0_[333] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[334] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [334]),
        .Q(\mcal_DQIn_r_reg_n_0_[334] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[335] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [335]),
        .Q(\mcal_DQIn_r_reg_n_0_[335] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[336] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [336]),
        .Q(\mcal_DQIn_r_reg_n_0_[336] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[337] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [337]),
        .Q(\mcal_DQIn_r_reg_n_0_[337] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[338] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [338]),
        .Q(\mcal_DQIn_r_reg_n_0_[338] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[339] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [339]),
        .Q(\mcal_DQIn_r_reg_n_0_[339] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [33]),
        .Q(p_0_in[1]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[340] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [340]),
        .Q(\mcal_DQIn_r_reg_n_0_[340] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[341] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [341]),
        .Q(\mcal_DQIn_r_reg_n_0_[341] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[342] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [342]),
        .Q(\mcal_DQIn_r_reg_n_0_[342] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[343] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [343]),
        .Q(\mcal_DQIn_r_reg_n_0_[343] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[344] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [344]),
        .Q(\mcal_DQIn_r_reg_n_0_[344] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[345] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [345]),
        .Q(\mcal_DQIn_r_reg_n_0_[345] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[346] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [346]),
        .Q(\mcal_DQIn_r_reg_n_0_[346] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[347] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [347]),
        .Q(\mcal_DQIn_r_reg_n_0_[347] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[348] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [348]),
        .Q(\mcal_DQIn_r_reg_n_0_[348] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[349] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [349]),
        .Q(\mcal_DQIn_r_reg_n_0_[349] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [34]),
        .Q(p_0_in[2]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[350] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [350]),
        .Q(\mcal_DQIn_r_reg_n_0_[350] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[351] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [351]),
        .Q(\mcal_DQIn_r_reg_n_0_[351] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[352] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [352]),
        .Q(\mcal_DQIn_r_reg_n_0_[352] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[353] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [353]),
        .Q(\mcal_DQIn_r_reg_n_0_[353] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[354] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [354]),
        .Q(\mcal_DQIn_r_reg_n_0_[354] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[355] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [355]),
        .Q(\mcal_DQIn_r_reg_n_0_[355] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[356] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [356]),
        .Q(\mcal_DQIn_r_reg_n_0_[356] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[357] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [357]),
        .Q(\mcal_DQIn_r_reg_n_0_[357] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[358] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [358]),
        .Q(\mcal_DQIn_r_reg_n_0_[358] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[359] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [359]),
        .Q(\mcal_DQIn_r_reg_n_0_[359] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [35]),
        .Q(p_0_in[3]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[360] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [360]),
        .Q(\mcal_DQIn_r_reg_n_0_[360] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[361] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [361]),
        .Q(\mcal_DQIn_r_reg_n_0_[361] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[362] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [362]),
        .Q(\mcal_DQIn_r_reg_n_0_[362] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[363] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [363]),
        .Q(\mcal_DQIn_r_reg_n_0_[363] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[364] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [364]),
        .Q(\mcal_DQIn_r_reg_n_0_[364] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[365] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [365]),
        .Q(\mcal_DQIn_r_reg_n_0_[365] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[366] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [366]),
        .Q(\mcal_DQIn_r_reg_n_0_[366] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[367] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [367]),
        .Q(\mcal_DQIn_r_reg_n_0_[367] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[368] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [368]),
        .Q(\mcal_DQIn_r_reg_n_0_[368] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[369] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [369]),
        .Q(\mcal_DQIn_r_reg_n_0_[369] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [36]),
        .Q(p_0_in[4]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[370] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [370]),
        .Q(\mcal_DQIn_r_reg_n_0_[370] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[371] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [371]),
        .Q(\mcal_DQIn_r_reg_n_0_[371] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[372] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [372]),
        .Q(\mcal_DQIn_r_reg_n_0_[372] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[373] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [373]),
        .Q(\mcal_DQIn_r_reg_n_0_[373] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[374] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [374]),
        .Q(\mcal_DQIn_r_reg_n_0_[374] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[375] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [375]),
        .Q(\mcal_DQIn_r_reg_n_0_[375] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[376] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [376]),
        .Q(\mcal_DQIn_r_reg_n_0_[376] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[377] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [377]),
        .Q(\mcal_DQIn_r_reg_n_0_[377] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[378] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [378]),
        .Q(\mcal_DQIn_r_reg_n_0_[378] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[379] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [379]),
        .Q(\mcal_DQIn_r_reg_n_0_[379] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [37]),
        .Q(p_0_in[5]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[380] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [380]),
        .Q(\mcal_DQIn_r_reg_n_0_[380] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[381] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [381]),
        .Q(\mcal_DQIn_r_reg_n_0_[381] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[382] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [382]),
        .Q(\mcal_DQIn_r_reg_n_0_[382] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[383] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [383]),
        .Q(\mcal_DQIn_r_reg_n_0_[383] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[384] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [384]),
        .Q(\mcal_DQIn_r_reg_n_0_[384] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[385] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [385]),
        .Q(\mcal_DQIn_r_reg_n_0_[385] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[386] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [386]),
        .Q(\mcal_DQIn_r_reg_n_0_[386] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[387] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [387]),
        .Q(\mcal_DQIn_r_reg_n_0_[387] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[388] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [388]),
        .Q(\mcal_DQIn_r_reg_n_0_[388] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[389] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [389]),
        .Q(\mcal_DQIn_r_reg_n_0_[389] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [38]),
        .Q(p_0_in[6]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[390] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [390]),
        .Q(\mcal_DQIn_r_reg_n_0_[390] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[391] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [391]),
        .Q(\mcal_DQIn_r_reg_n_0_[391] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[392] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [392]),
        .Q(\mcal_DQIn_r_reg_n_0_[392] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[393] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [393]),
        .Q(\mcal_DQIn_r_reg_n_0_[393] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[394] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [394]),
        .Q(\mcal_DQIn_r_reg_n_0_[394] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[395] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [395]),
        .Q(\mcal_DQIn_r_reg_n_0_[395] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[396] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [396]),
        .Q(\mcal_DQIn_r_reg_n_0_[396] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[397] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [397]),
        .Q(\mcal_DQIn_r_reg_n_0_[397] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[398] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [398]),
        .Q(\mcal_DQIn_r_reg_n_0_[398] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[399] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [399]),
        .Q(\mcal_DQIn_r_reg_n_0_[399] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [39]),
        .Q(p_0_in[7]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [3]),
        .Q(\mcal_DQIn_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[400] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [400]),
        .Q(\mcal_DQIn_r_reg_n_0_[400] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[401] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [401]),
        .Q(\mcal_DQIn_r_reg_n_0_[401] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[402] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [402]),
        .Q(\mcal_DQIn_r_reg_n_0_[402] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[403] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [403]),
        .Q(\mcal_DQIn_r_reg_n_0_[403] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[404] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [404]),
        .Q(\mcal_DQIn_r_reg_n_0_[404] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[405] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [405]),
        .Q(\mcal_DQIn_r_reg_n_0_[405] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[406] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [406]),
        .Q(\mcal_DQIn_r_reg_n_0_[406] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[407] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [407]),
        .Q(\mcal_DQIn_r_reg_n_0_[407] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[408] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [408]),
        .Q(\mcal_DQIn_r_reg_n_0_[408] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[409] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [409]),
        .Q(\mcal_DQIn_r_reg_n_0_[409] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [40]),
        .Q(\mcal_DQIn_r_reg_n_0_[40] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[410] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [410]),
        .Q(\mcal_DQIn_r_reg_n_0_[410] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[411] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [411]),
        .Q(\mcal_DQIn_r_reg_n_0_[411] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[412] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [412]),
        .Q(\mcal_DQIn_r_reg_n_0_[412] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[413] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [413]),
        .Q(\mcal_DQIn_r_reg_n_0_[413] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[414] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [414]),
        .Q(\mcal_DQIn_r_reg_n_0_[414] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[415] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [415]),
        .Q(\mcal_DQIn_r_reg_n_0_[415] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[416] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [416]),
        .Q(\mcal_DQIn_r_reg_n_0_[416] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[417] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [417]),
        .Q(\mcal_DQIn_r_reg_n_0_[417] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[418] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [418]),
        .Q(\mcal_DQIn_r_reg_n_0_[418] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[419] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [419]),
        .Q(\mcal_DQIn_r_reg_n_0_[419] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [41]),
        .Q(\mcal_DQIn_r_reg_n_0_[41] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[420] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [420]),
        .Q(\mcal_DQIn_r_reg_n_0_[420] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[421] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [421]),
        .Q(\mcal_DQIn_r_reg_n_0_[421] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[422] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [422]),
        .Q(\mcal_DQIn_r_reg_n_0_[422] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[423] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [423]),
        .Q(\mcal_DQIn_r_reg_n_0_[423] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[424] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [424]),
        .Q(\mcal_DQIn_r_reg_n_0_[424] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[425] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [425]),
        .Q(\mcal_DQIn_r_reg_n_0_[425] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[426] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [426]),
        .Q(\mcal_DQIn_r_reg_n_0_[426] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[427] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [427]),
        .Q(\mcal_DQIn_r_reg_n_0_[427] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[428] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [428]),
        .Q(\mcal_DQIn_r_reg_n_0_[428] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[429] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [429]),
        .Q(\mcal_DQIn_r_reg_n_0_[429] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [42]),
        .Q(\mcal_DQIn_r_reg_n_0_[42] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[430] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [430]),
        .Q(\mcal_DQIn_r_reg_n_0_[430] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[431] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [431]),
        .Q(\mcal_DQIn_r_reg_n_0_[431] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[432] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [432]),
        .Q(\mcal_DQIn_r_reg_n_0_[432] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[433] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [433]),
        .Q(\mcal_DQIn_r_reg_n_0_[433] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[434] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [434]),
        .Q(\mcal_DQIn_r_reg_n_0_[434] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[435] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [435]),
        .Q(\mcal_DQIn_r_reg_n_0_[435] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[436] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [436]),
        .Q(\mcal_DQIn_r_reg_n_0_[436] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[437] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [437]),
        .Q(\mcal_DQIn_r_reg_n_0_[437] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[438] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [438]),
        .Q(\mcal_DQIn_r_reg_n_0_[438] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[439] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [439]),
        .Q(\mcal_DQIn_r_reg_n_0_[439] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [43]),
        .Q(\mcal_DQIn_r_reg_n_0_[43] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[440] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [440]),
        .Q(\mcal_DQIn_r_reg_n_0_[440] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[441] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [441]),
        .Q(\mcal_DQIn_r_reg_n_0_[441] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[442] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [442]),
        .Q(\mcal_DQIn_r_reg_n_0_[442] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[443] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [443]),
        .Q(\mcal_DQIn_r_reg_n_0_[443] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[444] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [444]),
        .Q(\mcal_DQIn_r_reg_n_0_[444] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[445] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [445]),
        .Q(\mcal_DQIn_r_reg_n_0_[445] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[446] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [446]),
        .Q(\mcal_DQIn_r_reg_n_0_[446] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[447] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [447]),
        .Q(\mcal_DQIn_r_reg_n_0_[447] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[448] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [448]),
        .Q(\mcal_DQIn_r_reg_n_0_[448] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[449] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [449]),
        .Q(\mcal_DQIn_r_reg_n_0_[449] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [44]),
        .Q(\mcal_DQIn_r_reg_n_0_[44] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[450] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [450]),
        .Q(\mcal_DQIn_r_reg_n_0_[450] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[451] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [451]),
        .Q(\mcal_DQIn_r_reg_n_0_[451] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[452] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [452]),
        .Q(\mcal_DQIn_r_reg_n_0_[452] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[453] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [453]),
        .Q(\mcal_DQIn_r_reg_n_0_[453] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[454] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [454]),
        .Q(\mcal_DQIn_r_reg_n_0_[454] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[455] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [455]),
        .Q(\mcal_DQIn_r_reg_n_0_[455] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[456] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [456]),
        .Q(\mcal_DQIn_r_reg_n_0_[456] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[457] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [457]),
        .Q(\mcal_DQIn_r_reg_n_0_[457] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[458] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [458]),
        .Q(\mcal_DQIn_r_reg_n_0_[458] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[459] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [459]),
        .Q(\mcal_DQIn_r_reg_n_0_[459] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [45]),
        .Q(\mcal_DQIn_r_reg_n_0_[45] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[460] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [460]),
        .Q(\mcal_DQIn_r_reg_n_0_[460] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[461] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [461]),
        .Q(\mcal_DQIn_r_reg_n_0_[461] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[462] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [462]),
        .Q(\mcal_DQIn_r_reg_n_0_[462] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[463] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [463]),
        .Q(\mcal_DQIn_r_reg_n_0_[463] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[464] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [464]),
        .Q(\mcal_DQIn_r_reg_n_0_[464] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[465] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [465]),
        .Q(\mcal_DQIn_r_reg_n_0_[465] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[466] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [466]),
        .Q(\mcal_DQIn_r_reg_n_0_[466] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[467] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [467]),
        .Q(\mcal_DQIn_r_reg_n_0_[467] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[468] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [468]),
        .Q(\mcal_DQIn_r_reg_n_0_[468] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[469] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [469]),
        .Q(\mcal_DQIn_r_reg_n_0_[469] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [46]),
        .Q(\mcal_DQIn_r_reg_n_0_[46] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[470] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [470]),
        .Q(\mcal_DQIn_r_reg_n_0_[470] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[471] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [471]),
        .Q(\mcal_DQIn_r_reg_n_0_[471] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[472] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [472]),
        .Q(\mcal_DQIn_r_reg_n_0_[472] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[473] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [473]),
        .Q(\mcal_DQIn_r_reg_n_0_[473] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[474] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [474]),
        .Q(\mcal_DQIn_r_reg_n_0_[474] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[475] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [475]),
        .Q(\mcal_DQIn_r_reg_n_0_[475] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[476] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [476]),
        .Q(\mcal_DQIn_r_reg_n_0_[476] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[477] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [477]),
        .Q(\mcal_DQIn_r_reg_n_0_[477] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[478] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [478]),
        .Q(\mcal_DQIn_r_reg_n_0_[478] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[479] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [479]),
        .Q(\mcal_DQIn_r_reg_n_0_[479] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [47]),
        .Q(\mcal_DQIn_r_reg_n_0_[47] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[480] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [480]),
        .Q(\mcal_DQIn_r_reg_n_0_[480] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[481] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [481]),
        .Q(\mcal_DQIn_r_reg_n_0_[481] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[482] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [482]),
        .Q(\mcal_DQIn_r_reg_n_0_[482] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[483] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [483]),
        .Q(\mcal_DQIn_r_reg_n_0_[483] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[484] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [484]),
        .Q(\mcal_DQIn_r_reg_n_0_[484] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[485] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [485]),
        .Q(\mcal_DQIn_r_reg_n_0_[485] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[486] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [486]),
        .Q(\mcal_DQIn_r_reg_n_0_[486] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[487] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [487]),
        .Q(\mcal_DQIn_r_reg_n_0_[487] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[488] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [488]),
        .Q(\mcal_DQIn_r_reg_n_0_[488] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[489] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [489]),
        .Q(\mcal_DQIn_r_reg_n_0_[489] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [48]),
        .Q(\mcal_DQIn_r_reg_n_0_[48] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[490] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [490]),
        .Q(\mcal_DQIn_r_reg_n_0_[490] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[491] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [491]),
        .Q(\mcal_DQIn_r_reg_n_0_[491] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[492] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [492]),
        .Q(\mcal_DQIn_r_reg_n_0_[492] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[493] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [493]),
        .Q(\mcal_DQIn_r_reg_n_0_[493] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[494] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [494]),
        .Q(\mcal_DQIn_r_reg_n_0_[494] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[495] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [495]),
        .Q(\mcal_DQIn_r_reg_n_0_[495] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[496] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [496]),
        .Q(\mcal_DQIn_r_reg_n_0_[496] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[497] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [497]),
        .Q(\mcal_DQIn_r_reg_n_0_[497] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[498] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [498]),
        .Q(\mcal_DQIn_r_reg_n_0_[498] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[499] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [499]),
        .Q(\mcal_DQIn_r_reg_n_0_[499] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [49]),
        .Q(\mcal_DQIn_r_reg_n_0_[49] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [4]),
        .Q(\mcal_DQIn_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[500] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [500]),
        .Q(\mcal_DQIn_r_reg_n_0_[500] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[501] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [501]),
        .Q(\mcal_DQIn_r_reg_n_0_[501] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[502] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [502]),
        .Q(\mcal_DQIn_r_reg_n_0_[502] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[503] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [503]),
        .Q(\mcal_DQIn_r_reg_n_0_[503] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[504] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [504]),
        .Q(\mcal_DQIn_r_reg_n_0_[504] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[505] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [505]),
        .Q(\mcal_DQIn_r_reg_n_0_[505] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[506] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [506]),
        .Q(\mcal_DQIn_r_reg_n_0_[506] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[507] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [507]),
        .Q(\mcal_DQIn_r_reg_n_0_[507] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[508] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [508]),
        .Q(\mcal_DQIn_r_reg_n_0_[508] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[509] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [509]),
        .Q(\mcal_DQIn_r_reg_n_0_[509] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [50]),
        .Q(\mcal_DQIn_r_reg_n_0_[50] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[510] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [510]),
        .Q(\mcal_DQIn_r_reg_n_0_[510] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[511] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [511]),
        .Q(\mcal_DQIn_r_reg_n_0_[511] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [51]),
        .Q(\mcal_DQIn_r_reg_n_0_[51] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [52]),
        .Q(\mcal_DQIn_r_reg_n_0_[52] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [53]),
        .Q(\mcal_DQIn_r_reg_n_0_[53] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [54]),
        .Q(\mcal_DQIn_r_reg_n_0_[54] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [55]),
        .Q(\mcal_DQIn_r_reg_n_0_[55] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [56]),
        .Q(\mcal_DQIn_r_reg_n_0_[56] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [57]),
        .Q(\mcal_DQIn_r_reg_n_0_[57] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [58]),
        .Q(\mcal_DQIn_r_reg_n_0_[58] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [59]),
        .Q(\mcal_DQIn_r_reg_n_0_[59] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [5]),
        .Q(\mcal_DQIn_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [60]),
        .Q(\mcal_DQIn_r_reg_n_0_[60] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [61]),
        .Q(\mcal_DQIn_r_reg_n_0_[61] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [62]),
        .Q(\mcal_DQIn_r_reg_n_0_[62] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [63]),
        .Q(\mcal_DQIn_r_reg_n_0_[63] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[64] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [64]),
        .Q(\mcal_DQIn_r_reg_n_0_[64] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[65] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [65]),
        .Q(\mcal_DQIn_r_reg_n_0_[65] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[66] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [66]),
        .Q(\mcal_DQIn_r_reg_n_0_[66] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[67] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [67]),
        .Q(\mcal_DQIn_r_reg_n_0_[67] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[68] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [68]),
        .Q(\mcal_DQIn_r_reg_n_0_[68] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[69] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [69]),
        .Q(\mcal_DQIn_r_reg_n_0_[69] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [6]),
        .Q(\mcal_DQIn_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[70] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [70]),
        .Q(\mcal_DQIn_r_reg_n_0_[70] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[71] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [71]),
        .Q(\mcal_DQIn_r_reg_n_0_[71] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[72] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [72]),
        .Q(\mcal_DQIn_r_reg_n_0_[72] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[73] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [73]),
        .Q(\mcal_DQIn_r_reg_n_0_[73] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[74] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [74]),
        .Q(\mcal_DQIn_r_reg_n_0_[74] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[75] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [75]),
        .Q(\mcal_DQIn_r_reg_n_0_[75] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[76] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [76]),
        .Q(\mcal_DQIn_r_reg_n_0_[76] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[77] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [77]),
        .Q(\mcal_DQIn_r_reg_n_0_[77] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[78] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [78]),
        .Q(\mcal_DQIn_r_reg_n_0_[78] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[79] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [79]),
        .Q(\mcal_DQIn_r_reg_n_0_[79] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [7]),
        .Q(\mcal_DQIn_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[80] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [80]),
        .Q(\mcal_DQIn_r_reg_n_0_[80] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[81] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [81]),
        .Q(\mcal_DQIn_r_reg_n_0_[81] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[82] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [82]),
        .Q(\mcal_DQIn_r_reg_n_0_[82] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[83] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [83]),
        .Q(\mcal_DQIn_r_reg_n_0_[83] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[84] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [84]),
        .Q(\mcal_DQIn_r_reg_n_0_[84] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[85] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [85]),
        .Q(\mcal_DQIn_r_reg_n_0_[85] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[86] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [86]),
        .Q(\mcal_DQIn_r_reg_n_0_[86] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[87] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [87]),
        .Q(\mcal_DQIn_r_reg_n_0_[87] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[88] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [88]),
        .Q(\mcal_DQIn_r_reg_n_0_[88] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[89] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [89]),
        .Q(\mcal_DQIn_r_reg_n_0_[89] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [8]),
        .Q(\mcal_DQIn_r_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[90] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [90]),
        .Q(\mcal_DQIn_r_reg_n_0_[90] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[91] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [91]),
        .Q(\mcal_DQIn_r_reg_n_0_[91] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[92] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [92]),
        .Q(\mcal_DQIn_r_reg_n_0_[92] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[93] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [93]),
        .Q(\mcal_DQIn_r_reg_n_0_[93] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[94] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [94]),
        .Q(\mcal_DQIn_r_reg_n_0_[94] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[95] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [95]),
        .Q(\mcal_DQIn_r_reg_n_0_[95] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[96] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [96]),
        .Q(\mcal_DQIn_r_reg_n_0_[96] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[97] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [97]),
        .Q(\mcal_DQIn_r_reg_n_0_[97] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[98] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [98]),
        .Q(\mcal_DQIn_r_reg_n_0_[98] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[99] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [99]),
        .Q(\mcal_DQIn_r_reg_n_0_[99] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(\mcal_DQIn_r_reg[511]_0 [9]),
        .Q(\mcal_DQIn_r_reg_n_0_[9] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[0] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[100] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[100] ),
        .Q(data1[36]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[101] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[101] ),
        .Q(data1[37]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[102] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[102] ),
        .Q(data1[38]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[103] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[103] ),
        .Q(data1[39]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[104] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[104] ),
        .Q(data1[40]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[105] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[105] ),
        .Q(data1[41]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[106] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[106] ),
        .Q(data1[42]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[107] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[107] ),
        .Q(data1[43]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[108] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[108] ),
        .Q(data1[44]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[109] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[109] ),
        .Q(data1[45]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[10] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[110] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[110] ),
        .Q(data1[46]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[111] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[111] ),
        .Q(data1[47]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[112] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[112] ),
        .Q(data1[48]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[113] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[113] ),
        .Q(data1[49]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[114] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[114] ),
        .Q(data1[50]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[115] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[115] ),
        .Q(data1[51]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[116] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[116] ),
        .Q(data1[52]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[117] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[117] ),
        .Q(data1[53]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[118] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[118] ),
        .Q(data1[54]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[119] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[119] ),
        .Q(data1[55]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[11] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[120] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[120] ),
        .Q(data1[56]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[121] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[121] ),
        .Q(data1[57]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[122] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[122] ),
        .Q(data1[58]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[123] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[123] ),
        .Q(data1[59]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[124] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[124] ),
        .Q(data1[60]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[125] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[125] ),
        .Q(data1[61]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[126] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[126] ),
        .Q(data1[62]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[127] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[127] ),
        .Q(data1[63]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[128] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[128] ),
        .Q(data2[0]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[129] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[129] ),
        .Q(data2[1]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[12] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[130] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[130] ),
        .Q(data2[2]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[131] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[131] ),
        .Q(data2[3]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[132] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[132] ),
        .Q(data2[4]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[133] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[133] ),
        .Q(data2[5]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[134] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[134] ),
        .Q(data2[6]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[135] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[135] ),
        .Q(data2[7]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[136] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[136] ),
        .Q(data2[8]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[137] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[137] ),
        .Q(data2[9]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[138] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[138] ),
        .Q(data2[10]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[139] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[139] ),
        .Q(data2[11]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[13] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[140] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[140] ),
        .Q(data2[12]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[141] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[141] ),
        .Q(data2[13]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[142] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[142] ),
        .Q(data2[14]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[143] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[143] ),
        .Q(data2[15]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[144] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[144] ),
        .Q(data2[16]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[145] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[145] ),
        .Q(data2[17]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[146] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[146] ),
        .Q(data2[18]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[147] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[147] ),
        .Q(data2[19]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[148] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[148] ),
        .Q(data2[20]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[149] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[149] ),
        .Q(data2[21]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[14] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[150] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[150] ),
        .Q(data2[22]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[151] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[151] ),
        .Q(data2[23]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[152] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[152] ),
        .Q(data2[24]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[153] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[153] ),
        .Q(data2[25]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[154] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[154] ),
        .Q(data2[26]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[155] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[155] ),
        .Q(data2[27]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[156] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[156] ),
        .Q(data2[28]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[157] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[157] ),
        .Q(data2[29]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[158] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[158] ),
        .Q(data2[30]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[159] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[159] ),
        .Q(data2[31]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[15] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[160] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[160] ),
        .Q(data2[32]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[161] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[161] ),
        .Q(data2[33]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[162] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[162] ),
        .Q(data2[34]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[163] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[163] ),
        .Q(data2[35]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[164] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[164] ),
        .Q(data2[36]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[165] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[165] ),
        .Q(data2[37]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[166] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[166] ),
        .Q(data2[38]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[167] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[167] ),
        .Q(data2[39]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[168] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[168] ),
        .Q(data2[40]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[169] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[169] ),
        .Q(data2[41]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[16] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[170] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[170] ),
        .Q(data2[42]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[171] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[171] ),
        .Q(data2[43]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[172] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[172] ),
        .Q(data2[44]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[173] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[173] ),
        .Q(data2[45]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[174] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[174] ),
        .Q(data2[46]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[175] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[175] ),
        .Q(data2[47]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[176] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[176] ),
        .Q(data2[48]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[177] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[177] ),
        .Q(data2[49]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[178] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[178] ),
        .Q(data2[50]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[179] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[179] ),
        .Q(data2[51]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[17] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[180] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[180] ),
        .Q(data2[52]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[181] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[181] ),
        .Q(data2[53]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[182] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[182] ),
        .Q(data2[54]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[183] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[183] ),
        .Q(data2[55]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[184] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[184] ),
        .Q(data2[56]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[185] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[185] ),
        .Q(data2[57]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[186] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[186] ),
        .Q(data2[58]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[187] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[187] ),
        .Q(data2[59]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[188] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[188] ),
        .Q(data2[60]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[189] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[189] ),
        .Q(data2[61]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[18] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[18] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[190] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[190] ),
        .Q(data2[62]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[191] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[191] ),
        .Q(data2[63]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[192] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[192] ),
        .Q(data3[0]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[193] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[193] ),
        .Q(data3[1]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[194] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[194] ),
        .Q(data3[2]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[195] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[195] ),
        .Q(data3[3]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[196] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[196] ),
        .Q(data3[4]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[197] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[197] ),
        .Q(data3[5]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[198] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[198] ),
        .Q(data3[6]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[199] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[199] ),
        .Q(data3[7]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[19] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[19] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[1] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[200] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[200] ),
        .Q(data3[8]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[201] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[201] ),
        .Q(data3[9]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[202] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[202] ),
        .Q(data3[10]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[203] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[203] ),
        .Q(data3[11]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[204] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[204] ),
        .Q(data3[12]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[205] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[205] ),
        .Q(data3[13]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[206] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[206] ),
        .Q(data3[14]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[207] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[207] ),
        .Q(data3[15]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[208] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[208] ),
        .Q(data3[16]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[209] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[209] ),
        .Q(data3[17]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[20] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[20] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[210] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[210] ),
        .Q(data3[18]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[211] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[211] ),
        .Q(data3[19]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[212] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[212] ),
        .Q(data3[20]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[213] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[213] ),
        .Q(data3[21]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[214] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[214] ),
        .Q(data3[22]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[215] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[215] ),
        .Q(data3[23]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[216] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[216] ),
        .Q(data3[24]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[217] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[217] ),
        .Q(data3[25]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[218] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[218] ),
        .Q(data3[26]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[219] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[219] ),
        .Q(data3[27]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[21] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[21] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[220] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[220] ),
        .Q(data3[28]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[221] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[221] ),
        .Q(data3[29]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[222] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[222] ),
        .Q(data3[30]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[223] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[223] ),
        .Q(data3[31]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[224] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[224] ),
        .Q(data3[32]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[225] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[225] ),
        .Q(data3[33]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[226] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[226] ),
        .Q(data3[34]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[227] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[227] ),
        .Q(data3[35]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[228] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[228] ),
        .Q(data3[36]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[229] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[229] ),
        .Q(data3[37]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[22] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[22] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[230] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[230] ),
        .Q(data3[38]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[231] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[231] ),
        .Q(data3[39]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[232] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[232] ),
        .Q(data3[40]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[233] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[233] ),
        .Q(data3[41]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[234] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[234] ),
        .Q(data3[42]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[235] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[235] ),
        .Q(data3[43]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[236] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[236] ),
        .Q(data3[44]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[237] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[237] ),
        .Q(data3[45]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[238] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[238] ),
        .Q(data3[46]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[239] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[239] ),
        .Q(data3[47]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[23] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[23] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[240] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[240] ),
        .Q(data3[48]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[241] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[241] ),
        .Q(data3[49]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[242] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[242] ),
        .Q(data3[50]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[243] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[243] ),
        .Q(data3[51]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[244] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[244] ),
        .Q(data3[52]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[245] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[245] ),
        .Q(data3[53]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[246] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[246] ),
        .Q(data3[54]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[247] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[247] ),
        .Q(data3[55]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[248] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[248] ),
        .Q(data3[56]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[249] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[249] ),
        .Q(data3[57]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[24] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[24] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[250] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[250] ),
        .Q(data3[58]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[251] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[251] ),
        .Q(data3[59]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[252] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[252] ),
        .Q(data3[60]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[253] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[253] ),
        .Q(data3[61]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[254] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[254] ),
        .Q(data3[62]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[255] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[255] ),
        .Q(data3[63]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[256] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[256] ),
        .Q(data4[0]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[257] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[257] ),
        .Q(data4[1]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[258] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[258] ),
        .Q(data4[2]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[259] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[259] ),
        .Q(data4[3]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[25] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[25] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[260] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[260] ),
        .Q(data4[4]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[261] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[261] ),
        .Q(data4[5]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[262] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[262] ),
        .Q(data4[6]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[263] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[263] ),
        .Q(data4[7]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[264] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[264] ),
        .Q(data4[8]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[265] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[265] ),
        .Q(data4[9]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[266] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[266] ),
        .Q(data4[10]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[267] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[267] ),
        .Q(data4[11]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[268] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[268] ),
        .Q(data4[12]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[269] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[269] ),
        .Q(data4[13]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[26] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[26] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[270] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[270] ),
        .Q(data4[14]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[271] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[271] ),
        .Q(data4[15]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[272] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[272] ),
        .Q(data4[16]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[273] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[273] ),
        .Q(data4[17]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[274] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[274] ),
        .Q(data4[18]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[275] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[275] ),
        .Q(data4[19]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[276] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[276] ),
        .Q(data4[20]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[277] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[277] ),
        .Q(data4[21]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[278] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[278] ),
        .Q(data4[22]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[279] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[279] ),
        .Q(data4[23]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[27] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[27] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[280] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[280] ),
        .Q(data4[24]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[281] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[281] ),
        .Q(data4[25]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[282] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[282] ),
        .Q(data4[26]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[283] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[283] ),
        .Q(data4[27]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[284] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[284] ),
        .Q(data4[28]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[285] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[285] ),
        .Q(data4[29]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[286] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[286] ),
        .Q(data4[30]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[287] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[287] ),
        .Q(data4[31]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[288] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[288] ),
        .Q(data4[32]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[289] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[289] ),
        .Q(data4[33]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[28] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[28] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[290] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[290] ),
        .Q(data4[34]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[291] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[291] ),
        .Q(data4[35]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[292] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[292] ),
        .Q(data4[36]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[293] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[293] ),
        .Q(data4[37]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[294] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[294] ),
        .Q(data4[38]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[295] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[295] ),
        .Q(data4[39]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[296] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[296] ),
        .Q(data4[40]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[297] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[297] ),
        .Q(data4[41]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[298] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[298] ),
        .Q(data4[42]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[299] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[299] ),
        .Q(data4[43]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[29] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[29] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[2] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[300] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[300] ),
        .Q(data4[44]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[301] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[301] ),
        .Q(data4[45]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[302] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[302] ),
        .Q(data4[46]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[303] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[303] ),
        .Q(data4[47]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[304] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[304] ),
        .Q(data4[48]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[305] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[305] ),
        .Q(data4[49]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[306] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[306] ),
        .Q(data4[50]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[307] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[307] ),
        .Q(data4[51]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[308] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[308] ),
        .Q(data4[52]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[309] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[309] ),
        .Q(data4[53]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[30] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[30] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[310] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[310] ),
        .Q(data4[54]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[311] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[311] ),
        .Q(data4[55]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[312] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[312] ),
        .Q(data4[56]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[313] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[313] ),
        .Q(data4[57]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[314] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[314] ),
        .Q(data4[58]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[315] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[315] ),
        .Q(data4[59]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[316] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[316] ),
        .Q(data4[60]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[317] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[317] ),
        .Q(data4[61]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[318] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[318] ),
        .Q(data4[62]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[319] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[319] ),
        .Q(data4[63]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[31] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[31] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[320] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[320] ),
        .Q(data5[0]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[321] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[321] ),
        .Q(data5[1]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[322] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[322] ),
        .Q(data5[2]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[323] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[323] ),
        .Q(data5[3]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[324] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[324] ),
        .Q(data5[4]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[325] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[325] ),
        .Q(data5[5]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[326] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[326] ),
        .Q(data5[6]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[327] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[327] ),
        .Q(data5[7]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[328] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[328] ),
        .Q(data5[8]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[329] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[329] ),
        .Q(data5[9]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(p_0_in[0]),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[32] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[330] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[330] ),
        .Q(data5[10]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[331] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[331] ),
        .Q(data5[11]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[332] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[332] ),
        .Q(data5[12]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[333] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[333] ),
        .Q(data5[13]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[334] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[334] ),
        .Q(data5[14]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[335] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[335] ),
        .Q(data5[15]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[336] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[336] ),
        .Q(data5[16]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[337] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[337] ),
        .Q(data5[17]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[338] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[338] ),
        .Q(data5[18]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[339] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[339] ),
        .Q(data5[19]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(p_0_in[1]),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[33] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[340] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[340] ),
        .Q(data5[20]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[341] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[341] ),
        .Q(data5[21]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[342] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[342] ),
        .Q(data5[22]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[343] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[343] ),
        .Q(data5[23]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[344] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[344] ),
        .Q(data5[24]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[345] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[345] ),
        .Q(data5[25]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[346] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[346] ),
        .Q(data5[26]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[347] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[347] ),
        .Q(data5[27]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[348] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[348] ),
        .Q(data5[28]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[349] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[349] ),
        .Q(data5[29]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(p_0_in[2]),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[34] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[350] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[350] ),
        .Q(data5[30]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[351] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[351] ),
        .Q(data5[31]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[352] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[352] ),
        .Q(data5[32]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[353] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[353] ),
        .Q(data5[33]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[354] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[354] ),
        .Q(data5[34]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[355] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[355] ),
        .Q(data5[35]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[356] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[356] ),
        .Q(data5[36]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[357] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[357] ),
        .Q(data5[37]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[358] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[358] ),
        .Q(data5[38]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[359] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[359] ),
        .Q(data5[39]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(p_0_in[3]),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[35] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[360] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[360] ),
        .Q(data5[40]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[361] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[361] ),
        .Q(data5[41]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[362] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[362] ),
        .Q(data5[42]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[363] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[363] ),
        .Q(data5[43]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[364] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[364] ),
        .Q(data5[44]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[365] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[365] ),
        .Q(data5[45]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[366] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[366] ),
        .Q(data5[46]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[367] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[367] ),
        .Q(data5[47]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[368] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[368] ),
        .Q(data5[48]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[369] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[369] ),
        .Q(data5[49]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(p_0_in[4]),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[36] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[370] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[370] ),
        .Q(data5[50]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[371] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[371] ),
        .Q(data5[51]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[372] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[372] ),
        .Q(data5[52]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[373] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[373] ),
        .Q(data5[53]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[374] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[374] ),
        .Q(data5[54]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[375] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[375] ),
        .Q(data5[55]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[376] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[376] ),
        .Q(data5[56]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[377] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[377] ),
        .Q(data5[57]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[378] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[378] ),
        .Q(data5[58]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[379] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[379] ),
        .Q(data5[59]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(p_0_in[5]),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[37] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[380] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[380] ),
        .Q(data5[60]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[381] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[381] ),
        .Q(data5[61]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[382] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[382] ),
        .Q(data5[62]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[383] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[383] ),
        .Q(data5[63]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[384] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[384] ),
        .Q(data6[0]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[385] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[385] ),
        .Q(data6[1]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[386] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[386] ),
        .Q(data6[2]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[387] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[387] ),
        .Q(data6[3]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[388] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[388] ),
        .Q(data6[4]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[389] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[389] ),
        .Q(data6[5]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(p_0_in[6]),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[38] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[390] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[390] ),
        .Q(data6[6]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[391] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[391] ),
        .Q(data6[7]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[392] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[392] ),
        .Q(data6[8]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[393] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[393] ),
        .Q(data6[9]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[394] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[394] ),
        .Q(data6[10]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[395] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[395] ),
        .Q(data6[11]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[396] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[396] ),
        .Q(data6[12]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[397] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[397] ),
        .Q(data6[13]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[398] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[398] ),
        .Q(data6[14]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[399] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[399] ),
        .Q(data6[15]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(p_0_in[7]),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[39] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[3] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[400] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[400] ),
        .Q(data6[16]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[401] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[401] ),
        .Q(data6[17]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[402] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[402] ),
        .Q(data6[18]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[403] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[403] ),
        .Q(data6[19]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[404] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[404] ),
        .Q(data6[20]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[405] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[405] ),
        .Q(data6[21]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[406] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[406] ),
        .Q(data6[22]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[407] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[407] ),
        .Q(data6[23]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[408] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[408] ),
        .Q(data6[24]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[409] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[409] ),
        .Q(data6[25]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[40] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[40] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[410] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[410] ),
        .Q(data6[26]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[411] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[411] ),
        .Q(data6[27]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[412] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[412] ),
        .Q(data6[28]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[413] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[413] ),
        .Q(data6[29]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[414] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[414] ),
        .Q(data6[30]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[415] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[415] ),
        .Q(data6[31]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[416] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[416] ),
        .Q(data6[32]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[417] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[417] ),
        .Q(data6[33]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[418] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[418] ),
        .Q(data6[34]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[419] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[419] ),
        .Q(data6[35]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[41] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[41] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[420] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[420] ),
        .Q(data6[36]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[421] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[421] ),
        .Q(data6[37]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[422] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[422] ),
        .Q(data6[38]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[423] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[423] ),
        .Q(data6[39]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[424] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[424] ),
        .Q(data6[40]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[425] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[425] ),
        .Q(data6[41]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[426] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[426] ),
        .Q(data6[42]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[427] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[427] ),
        .Q(data6[43]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[428] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[428] ),
        .Q(data6[44]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[429] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[429] ),
        .Q(data6[45]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[42] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[42] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[430] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[430] ),
        .Q(data6[46]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[431] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[431] ),
        .Q(data6[47]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[432] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[432] ),
        .Q(data6[48]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[433] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[433] ),
        .Q(data6[49]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[434] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[434] ),
        .Q(data6[50]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[435] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[435] ),
        .Q(data6[51]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[436] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[436] ),
        .Q(data6[52]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[437] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[437] ),
        .Q(data6[53]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[438] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[438] ),
        .Q(data6[54]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[439] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[439] ),
        .Q(data6[55]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[43] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[43] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[440] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[440] ),
        .Q(data6[56]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[441] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[441] ),
        .Q(data6[57]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[442] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[442] ),
        .Q(data6[58]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[443] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[443] ),
        .Q(data6[59]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[444] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[444] ),
        .Q(data6[60]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[445] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[445] ),
        .Q(data6[61]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[446] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[446] ),
        .Q(data6[62]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[447] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[447] ),
        .Q(data6[63]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[448] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[448] ),
        .Q(data7[0]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[449] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[449] ),
        .Q(data7[1]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[44] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[44] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[450] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[450] ),
        .Q(data7[2]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[451] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[451] ),
        .Q(data7[3]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[452] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[452] ),
        .Q(data7[4]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[453] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[453] ),
        .Q(data7[5]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[454] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[454] ),
        .Q(data7[6]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[455] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[455] ),
        .Q(data7[7]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[456] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[456] ),
        .Q(data7[8]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[457] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[457] ),
        .Q(data7[9]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[458] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[458] ),
        .Q(data7[10]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[459] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[459] ),
        .Q(data7[11]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[45] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[45] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[460] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[460] ),
        .Q(data7[12]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[461] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[461] ),
        .Q(data7[13]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[462] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[462] ),
        .Q(data7[14]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[463] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[463] ),
        .Q(data7[15]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[464] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[464] ),
        .Q(data7[16]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[465] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[465] ),
        .Q(data7[17]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[466] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[466] ),
        .Q(data7[18]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[467] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[467] ),
        .Q(data7[19]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[468] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[468] ),
        .Q(data7[20]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[469] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[469] ),
        .Q(data7[21]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[46] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[46] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[470] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[470] ),
        .Q(data7[22]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[471] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[471] ),
        .Q(data7[23]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[472] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[472] ),
        .Q(data7[24]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[473] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[473] ),
        .Q(data7[25]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[474] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[474] ),
        .Q(data7[26]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[475] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[475] ),
        .Q(data7[27]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[476] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[476] ),
        .Q(data7[28]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[477] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[477] ),
        .Q(data7[29]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[478] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[478] ),
        .Q(data7[30]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[479] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[479] ),
        .Q(data7[31]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[47] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[47] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[480] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[480] ),
        .Q(data7[32]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[481] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[481] ),
        .Q(data7[33]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[482] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[482] ),
        .Q(data7[34]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[483] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[483] ),
        .Q(data7[35]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[484] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[484] ),
        .Q(data7[36]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[485] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[485] ),
        .Q(data7[37]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[486] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[486] ),
        .Q(data7[38]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[487] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[487] ),
        .Q(data7[39]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[488] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[488] ),
        .Q(data7[40]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[489] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[489] ),
        .Q(data7[41]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[48] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[48] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[490] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[490] ),
        .Q(data7[42]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[491] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[491] ),
        .Q(data7[43]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[492] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[492] ),
        .Q(data7[44]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[493] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[493] ),
        .Q(data7[45]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[494] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[494] ),
        .Q(data7[46]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[495] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[495] ),
        .Q(data7[47]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[496] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[496] ),
        .Q(data7[48]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[497] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[497] ),
        .Q(data7[49]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[498] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[498] ),
        .Q(data7[50]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[499] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[499] ),
        .Q(data7[51]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[49] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[49] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[4] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[500] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[500] ),
        .Q(data7[52]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[501] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[501] ),
        .Q(data7[53]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[502] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[502] ),
        .Q(data7[54]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[503] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[503] ),
        .Q(data7[55]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[504] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[504] ),
        .Q(data7[56]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[505] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[505] ),
        .Q(data7[57]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[506] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[506] ),
        .Q(data7[58]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[507] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[507] ),
        .Q(data7[59]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[508] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[508] ),
        .Q(data7[60]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[509] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[509] ),
        .Q(data7[61]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[50] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[50] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[510] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[510] ),
        .Q(data7[62]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[511] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[511] ),
        .Q(data7[63]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[51] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[51] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[52] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[52] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[53] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[53] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[54] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[54] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[55] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[55] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[56] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[56] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[57] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[57] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[58] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[58] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[59] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[59] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[5] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[60] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[60] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[61] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[61] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[62] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[62] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[63] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[63] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[64] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[64] ),
        .Q(data1[0]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[65] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[65] ),
        .Q(data1[1]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[66] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[66] ),
        .Q(data1[2]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[67] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[67] ),
        .Q(data1[3]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[68] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[68] ),
        .Q(data1[4]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[69] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[69] ),
        .Q(data1[5]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[6] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[70] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[70] ),
        .Q(data1[6]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[71] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[71] ),
        .Q(data1[7]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[72] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[72] ),
        .Q(data1[8]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[73] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[73] ),
        .Q(data1[9]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[74] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[74] ),
        .Q(data1[10]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[75] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[75] ),
        .Q(data1[11]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[76] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[76] ),
        .Q(data1[12]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[77] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[77] ),
        .Q(data1[13]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[78] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[78] ),
        .Q(data1[14]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[79] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[79] ),
        .Q(data1[15]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[7] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[80] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[80] ),
        .Q(data1[16]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[81] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[81] ),
        .Q(data1[17]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[82] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[82] ),
        .Q(data1[18]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[83] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[83] ),
        .Q(data1[19]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[84] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[84] ),
        .Q(data1[20]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[85] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[85] ),
        .Q(data1[21]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[86] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[86] ),
        .Q(data1[22]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[87] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[87] ),
        .Q(data1[23]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[88] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[88] ),
        .Q(data1[24]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[89] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[89] ),
        .Q(data1[25]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[8] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[90] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[90] ),
        .Q(data1[26]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[91] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[91] ),
        .Q(data1[27]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[92] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[92] ),
        .Q(data1[28]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[93] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[93] ),
        .Q(data1[29]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[94] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[94] ),
        .Q(data1[30]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[95] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[95] ),
        .Q(data1[31]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[96] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[96] ),
        .Q(data1[32]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[97] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[97] ),
        .Q(data1[33]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[98] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[98] ),
        .Q(data1[34]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[99] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[99] ),
        .Q(data1[35]),
        .R(1'b0));
  FDRE \mcal_DQIn_r_valid_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(mcal_DQIn_byte_r0),
        .D(\mcal_DQIn_r_reg_n_0_[9] ),
        .Q(\mcal_DQIn_r_valid_reg_n_0_[9] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hF088)) 
    \mcal_ODT_dly[0][0]_i_1 
       (.I0(ub_cal_ODT[0]),
        .I1(ub_ready),
        .I2(mc_ODT7),
        .I3(\mcal_ODT_dly_reg[0][4] ),
        .O(ub_ready_reg_0[0]));
  LUT4 #(
    .INIT(16'h0100)) 
    \mcal_ODT_dly[0][4]_i_4 
       (.I0(rdCAS_reg_0),
        .I1(\clb2phy_wrcs0_low_reg_n_0_[31] ),
        .I2(\clb2phy_wrcs1_low_reg_n_0_[31] ),
        .I3(wrCAS_reg_0),
        .O(\mcal_ODT_dly[0][4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[0]_i_1 
       (.I0(mcal_dq_cmp[0]),
        .I1(mcal_DQIn_byte_r[0]),
        .I2(\cal_DQPat_A_reg_n_0_[0] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[0] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[0]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[10]_i_1 
       (.I0(mcal_dq_cmp[10]),
        .I1(mcal_DQIn_byte_r[10]),
        .I2(\cal_DQPat_A_reg_n_0_[10] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[10] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[10]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[11]_i_1 
       (.I0(mcal_dq_cmp[11]),
        .I1(mcal_DQIn_byte_r[11]),
        .I2(\cal_DQPat_A_reg_n_0_[11] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[11] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[11]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[12]_i_1 
       (.I0(mcal_dq_cmp[12]),
        .I1(mcal_DQIn_byte_r[12]),
        .I2(\cal_DQPat_A_reg_n_0_[12] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[12] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[12]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[13]_i_1 
       (.I0(mcal_dq_cmp[13]),
        .I1(mcal_DQIn_byte_r[13]),
        .I2(\cal_DQPat_A_reg_n_0_[13] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[13] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[13]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[14]_i_1 
       (.I0(mcal_dq_cmp[14]),
        .I1(mcal_DQIn_byte_r[14]),
        .I2(\cal_DQPat_A_reg_n_0_[14] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[14] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[14]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[15]_i_1 
       (.I0(mcal_dq_cmp[15]),
        .I1(mcal_DQIn_byte_r[15]),
        .I2(\cal_DQPat_A_reg_n_0_[15] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[15] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[15]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[16]_i_1 
       (.I0(mcal_dq_cmp[16]),
        .I1(mcal_DQIn_byte_r[16]),
        .I2(\cal_DQPat_A_reg_n_0_[16] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[16] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[16]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[17]_i_1 
       (.I0(mcal_dq_cmp[17]),
        .I1(mcal_DQIn_byte_r[17]),
        .I2(\cal_DQPat_A_reg_n_0_[17] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[17] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[17]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[18]_i_1 
       (.I0(mcal_dq_cmp[18]),
        .I1(mcal_DQIn_byte_r[18]),
        .I2(\cal_DQPat_A_reg_n_0_[18] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[18] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[18]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[19]_i_1 
       (.I0(mcal_dq_cmp[19]),
        .I1(mcal_DQIn_byte_r[19]),
        .I2(\cal_DQPat_A_reg_n_0_[19] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[19] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[19]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[1]_i_1 
       (.I0(mcal_dq_cmp[1]),
        .I1(mcal_DQIn_byte_r[1]),
        .I2(\cal_DQPat_A_reg_n_0_[1] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[1] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[1]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[20]_i_1 
       (.I0(mcal_dq_cmp[20]),
        .I1(mcal_DQIn_byte_r[20]),
        .I2(\cal_DQPat_A_reg_n_0_[20] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[20] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[20]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[21]_i_1 
       (.I0(mcal_dq_cmp[21]),
        .I1(mcal_DQIn_byte_r[21]),
        .I2(\cal_DQPat_A_reg_n_0_[21] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[21] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[21]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[22]_i_1 
       (.I0(mcal_dq_cmp[22]),
        .I1(mcal_DQIn_byte_r[22]),
        .I2(\cal_DQPat_A_reg_n_0_[22] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[22] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[22]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[23]_i_1 
       (.I0(mcal_dq_cmp[23]),
        .I1(mcal_DQIn_byte_r[23]),
        .I2(\cal_DQPat_A_reg_n_0_[23] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[23] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[23]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[24]_i_1 
       (.I0(mcal_dq_cmp[24]),
        .I1(mcal_DQIn_byte_r[24]),
        .I2(\cal_DQPat_A_reg_n_0_[24] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[24] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[24]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[25]_i_1 
       (.I0(mcal_dq_cmp[25]),
        .I1(mcal_DQIn_byte_r[25]),
        .I2(\cal_DQPat_A_reg_n_0_[25] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[25] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[25]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[26]_i_1 
       (.I0(mcal_dq_cmp[26]),
        .I1(mcal_DQIn_byte_r[26]),
        .I2(\cal_DQPat_A_reg_n_0_[26] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[26] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[26]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[27]_i_1 
       (.I0(mcal_dq_cmp[27]),
        .I1(mcal_DQIn_byte_r[27]),
        .I2(\cal_DQPat_A_reg_n_0_[27] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[27] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[27]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[28]_i_1 
       (.I0(mcal_dq_cmp[28]),
        .I1(mcal_DQIn_byte_r[28]),
        .I2(\cal_DQPat_A_reg_n_0_[28] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[28] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[28]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[29]_i_1 
       (.I0(mcal_dq_cmp[29]),
        .I1(mcal_DQIn_byte_r[29]),
        .I2(\cal_DQPat_A_reg_n_0_[29] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[29] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[29]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[2]_i_1 
       (.I0(mcal_dq_cmp[2]),
        .I1(mcal_DQIn_byte_r[2]),
        .I2(\cal_DQPat_A_reg_n_0_[2] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[2] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[2]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[30]_i_1 
       (.I0(mcal_dq_cmp[30]),
        .I1(mcal_DQIn_byte_r[30]),
        .I2(\cal_DQPat_A_reg_n_0_[30] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[30] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[30]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[31]_i_1 
       (.I0(mcal_dq_cmp[31]),
        .I1(mcal_DQIn_byte_r[31]),
        .I2(\cal_DQPat_A_reg_n_0_[31] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[31] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[31]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[32]_i_1 
       (.I0(mcal_dq_cmp[32]),
        .I1(mcal_DQIn_byte_r[32]),
        .I2(\cal_DQPat_A_reg_n_0_[32] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[32] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[32]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[33]_i_1 
       (.I0(mcal_dq_cmp[33]),
        .I1(mcal_DQIn_byte_r[33]),
        .I2(\cal_DQPat_A_reg_n_0_[33] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[33] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[33]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[34]_i_1 
       (.I0(mcal_dq_cmp[34]),
        .I1(mcal_DQIn_byte_r[34]),
        .I2(\cal_DQPat_A_reg_n_0_[34] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[34] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[34]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[35]_i_1 
       (.I0(mcal_dq_cmp[35]),
        .I1(mcal_DQIn_byte_r[35]),
        .I2(\cal_DQPat_A_reg_n_0_[35] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[35] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[35]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[36]_i_1 
       (.I0(mcal_dq_cmp[36]),
        .I1(mcal_DQIn_byte_r[36]),
        .I2(\cal_DQPat_A_reg_n_0_[36] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[36] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[36]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[37]_i_1 
       (.I0(mcal_dq_cmp[37]),
        .I1(mcal_DQIn_byte_r[37]),
        .I2(\cal_DQPat_A_reg_n_0_[37] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[37] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[37]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[38]_i_1 
       (.I0(mcal_dq_cmp[38]),
        .I1(mcal_DQIn_byte_r[38]),
        .I2(\cal_DQPat_A_reg_n_0_[38] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[38] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[38]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[39]_i_1 
       (.I0(mcal_dq_cmp[39]),
        .I1(mcal_DQIn_byte_r[39]),
        .I2(\cal_DQPat_A_reg_n_0_[39] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[39] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[39]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[3]_i_1 
       (.I0(mcal_dq_cmp[3]),
        .I1(mcal_DQIn_byte_r[3]),
        .I2(\cal_DQPat_A_reg_n_0_[3] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[3] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[3]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[40]_i_1 
       (.I0(mcal_dq_cmp[40]),
        .I1(mcal_DQIn_byte_r[40]),
        .I2(\cal_DQPat_A_reg_n_0_[40] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[40] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[40]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[41]_i_1 
       (.I0(mcal_dq_cmp[41]),
        .I1(mcal_DQIn_byte_r[41]),
        .I2(\cal_DQPat_A_reg_n_0_[41] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[41] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[41]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[42]_i_1 
       (.I0(mcal_dq_cmp[42]),
        .I1(mcal_DQIn_byte_r[42]),
        .I2(\cal_DQPat_A_reg_n_0_[42] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[42] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[42]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[43]_i_1 
       (.I0(mcal_dq_cmp[43]),
        .I1(mcal_DQIn_byte_r[43]),
        .I2(\cal_DQPat_A_reg_n_0_[43] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[43] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[43]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[44]_i_1 
       (.I0(mcal_dq_cmp[44]),
        .I1(mcal_DQIn_byte_r[44]),
        .I2(\cal_DQPat_A_reg_n_0_[44] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[44] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[44]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[45]_i_1 
       (.I0(mcal_dq_cmp[45]),
        .I1(mcal_DQIn_byte_r[45]),
        .I2(\cal_DQPat_A_reg_n_0_[45] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[45] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[45]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[46]_i_1 
       (.I0(mcal_dq_cmp[46]),
        .I1(mcal_DQIn_byte_r[46]),
        .I2(\cal_DQPat_A_reg_n_0_[46] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[46] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[46]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[47]_i_1 
       (.I0(mcal_dq_cmp[47]),
        .I1(mcal_DQIn_byte_r[47]),
        .I2(\cal_DQPat_A_reg_n_0_[47] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[47] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[47]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[48]_i_1 
       (.I0(mcal_dq_cmp[48]),
        .I1(mcal_DQIn_byte_r[48]),
        .I2(\cal_DQPat_A_reg_n_0_[48] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[48] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[48]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[49]_i_1 
       (.I0(mcal_dq_cmp[49]),
        .I1(mcal_DQIn_byte_r[49]),
        .I2(\cal_DQPat_A_reg_n_0_[49] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[49] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[49]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[4]_i_1 
       (.I0(mcal_dq_cmp[4]),
        .I1(mcal_DQIn_byte_r[4]),
        .I2(\cal_DQPat_A_reg_n_0_[4] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[4] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[4]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[50]_i_1 
       (.I0(mcal_dq_cmp[50]),
        .I1(mcal_DQIn_byte_r[50]),
        .I2(\cal_DQPat_A_reg_n_0_[50] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[50] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[50]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[51]_i_1 
       (.I0(mcal_dq_cmp[51]),
        .I1(mcal_DQIn_byte_r[51]),
        .I2(\cal_DQPat_A_reg_n_0_[51] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[51] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[51]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[52]_i_1 
       (.I0(mcal_dq_cmp[52]),
        .I1(mcal_DQIn_byte_r[52]),
        .I2(\cal_DQPat_A_reg_n_0_[52] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[52] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[52]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[53]_i_1 
       (.I0(mcal_dq_cmp[53]),
        .I1(mcal_DQIn_byte_r[53]),
        .I2(\cal_DQPat_A_reg_n_0_[53] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[53] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[53]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[54]_i_1 
       (.I0(mcal_dq_cmp[54]),
        .I1(mcal_DQIn_byte_r[54]),
        .I2(\cal_DQPat_A_reg_n_0_[54] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[54] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[54]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[55]_i_1 
       (.I0(mcal_dq_cmp[55]),
        .I1(mcal_DQIn_byte_r[55]),
        .I2(\cal_DQPat_A_reg_n_0_[55] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[55] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[55]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[56]_i_1 
       (.I0(mcal_dq_cmp[56]),
        .I1(mcal_DQIn_byte_r[56]),
        .I2(\cal_DQPat_A_reg_n_0_[56] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[56] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[56]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[57]_i_1 
       (.I0(mcal_dq_cmp[57]),
        .I1(mcal_DQIn_byte_r[57]),
        .I2(\cal_DQPat_A_reg_n_0_[57] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[57] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[57]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[58]_i_1 
       (.I0(mcal_dq_cmp[58]),
        .I1(mcal_DQIn_byte_r[58]),
        .I2(\cal_DQPat_A_reg_n_0_[58] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[58] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[58]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[59]_i_1 
       (.I0(mcal_dq_cmp[59]),
        .I1(mcal_DQIn_byte_r[59]),
        .I2(\cal_DQPat_A_reg_n_0_[59] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[59] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[59]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[5]_i_1 
       (.I0(mcal_dq_cmp[5]),
        .I1(mcal_DQIn_byte_r[5]),
        .I2(\cal_DQPat_A_reg_n_0_[5] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[5] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[5]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[60]_i_1 
       (.I0(mcal_dq_cmp[60]),
        .I1(mcal_DQIn_byte_r[60]),
        .I2(\cal_DQPat_A_reg_n_0_[60] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[60] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[60]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[61]_i_1 
       (.I0(mcal_dq_cmp[61]),
        .I1(mcal_DQIn_byte_r[61]),
        .I2(\cal_DQPat_A_reg_n_0_[61] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[61] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[61]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[62]_i_1 
       (.I0(mcal_dq_cmp[62]),
        .I1(mcal_DQIn_byte_r[62]),
        .I2(\cal_DQPat_A_reg_n_0_[62] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[62] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[62]));
  LUT2 #(
    .INIT(4'hE)) 
    \mcal_dq_cmp[63]_i_1 
       (.I0(cnt_clr_reg_0),
        .I1(rst_r1),
        .O(\mcal_dq_cmp[63]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[63]_i_2 
       (.I0(mcal_dq_cmp[63]),
        .I1(mcal_DQIn_byte_r[63]),
        .I2(\cal_DQPat_A_reg_n_0_[63] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[63] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[63]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[6]_i_1 
       (.I0(mcal_dq_cmp[6]),
        .I1(mcal_DQIn_byte_r[6]),
        .I2(\cal_DQPat_A_reg_n_0_[6] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[6] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[6]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[7]_i_1 
       (.I0(mcal_dq_cmp[7]),
        .I1(mcal_DQIn_byte_r[7]),
        .I2(\cal_DQPat_A_reg_n_0_[7] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[7] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[7]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[8]_i_1 
       (.I0(mcal_dq_cmp[8]),
        .I1(mcal_DQIn_byte_r[8]),
        .I2(\cal_DQPat_A_reg_n_0_[8] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[8] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[8]));
  LUT6 #(
    .INIT(64'hBBBEEEBEAAAAAAAA)) 
    \mcal_dq_cmp[9]_i_1 
       (.I0(mcal_dq_cmp[9]),
        .I1(mcal_DQIn_byte_r[9]),
        .I2(\cal_DQPat_A_reg_n_0_[9] ),
        .I3(a_b_rd_sel_r),
        .I4(\cal_DQPat_B_reg_n_0_[9] ),
        .I5(\dqin_valid_shift_reg_n_0_[2] ),
        .O(mcal_dq_cmp0[9]));
  FDRE \mcal_dq_cmp_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[0]),
        .Q(mcal_dq_cmp[0]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[10]),
        .Q(mcal_dq_cmp[10]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[11]),
        .Q(mcal_dq_cmp[11]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[12]),
        .Q(mcal_dq_cmp[12]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[13]),
        .Q(mcal_dq_cmp[13]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[14]),
        .Q(mcal_dq_cmp[14]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[15]),
        .Q(mcal_dq_cmp[15]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[16]),
        .Q(mcal_dq_cmp[16]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[17]),
        .Q(mcal_dq_cmp[17]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[18]),
        .Q(mcal_dq_cmp[18]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[19]),
        .Q(mcal_dq_cmp[19]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[1]),
        .Q(mcal_dq_cmp[1]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[20]),
        .Q(mcal_dq_cmp[20]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[21]),
        .Q(mcal_dq_cmp[21]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[22]),
        .Q(mcal_dq_cmp[22]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[23]),
        .Q(mcal_dq_cmp[23]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[24]),
        .Q(mcal_dq_cmp[24]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[25]),
        .Q(mcal_dq_cmp[25]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[26]),
        .Q(mcal_dq_cmp[26]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[27]),
        .Q(mcal_dq_cmp[27]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[28]),
        .Q(mcal_dq_cmp[28]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[29]),
        .Q(mcal_dq_cmp[29]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[2]),
        .Q(mcal_dq_cmp[2]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[30]),
        .Q(mcal_dq_cmp[30]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[31]),
        .Q(mcal_dq_cmp[31]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[32]),
        .Q(mcal_dq_cmp[32]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[33]),
        .Q(mcal_dq_cmp[33]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[34]),
        .Q(mcal_dq_cmp[34]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[35]),
        .Q(mcal_dq_cmp[35]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[36]),
        .Q(mcal_dq_cmp[36]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[37]),
        .Q(mcal_dq_cmp[37]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[38]),
        .Q(mcal_dq_cmp[38]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[39]),
        .Q(mcal_dq_cmp[39]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[3]),
        .Q(mcal_dq_cmp[3]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[40]),
        .Q(mcal_dq_cmp[40]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[41]),
        .Q(mcal_dq_cmp[41]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[42]),
        .Q(mcal_dq_cmp[42]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[43]),
        .Q(mcal_dq_cmp[43]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[44]),
        .Q(mcal_dq_cmp[44]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[45]),
        .Q(mcal_dq_cmp[45]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[46]),
        .Q(mcal_dq_cmp[46]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[47]),
        .Q(mcal_dq_cmp[47]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[48]),
        .Q(mcal_dq_cmp[48]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[49]),
        .Q(mcal_dq_cmp[49]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[4]),
        .Q(mcal_dq_cmp[4]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[50]),
        .Q(mcal_dq_cmp[50]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[51]),
        .Q(mcal_dq_cmp[51]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[52]),
        .Q(mcal_dq_cmp[52]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[53]),
        .Q(mcal_dq_cmp[53]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[54]),
        .Q(mcal_dq_cmp[54]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[55]),
        .Q(mcal_dq_cmp[55]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[56] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[56]),
        .Q(mcal_dq_cmp[56]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[57] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[57]),
        .Q(mcal_dq_cmp[57]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[58] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[58]),
        .Q(mcal_dq_cmp[58]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[59] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[59]),
        .Q(mcal_dq_cmp[59]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[5]),
        .Q(mcal_dq_cmp[5]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[60] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[60]),
        .Q(mcal_dq_cmp[60]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[61] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[61]),
        .Q(mcal_dq_cmp[61]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[62] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[62]),
        .Q(mcal_dq_cmp[62]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[63] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[63]),
        .Q(mcal_dq_cmp[63]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[6]),
        .Q(mcal_dq_cmp[6]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[7]),
        .Q(mcal_dq_cmp[7]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[8]),
        .Q(mcal_dq_cmp[8]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  FDRE \mcal_dq_cmp_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(mcal_dq_cmp0[9]),
        .Q(mcal_dq_cmp[9]),
        .R(\mcal_dq_cmp[63]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair901" *) 
  LUT3 #(
    .INIT(8'hBF)) 
    rdCAS_i_3
       (.I0(extended_write_mode),
        .I1(seq_cnt_dec),
        .I2(cal_seq_cnt_gt_0),
        .O(rdCAS_i_3_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rdCAS_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_n_136),
        .Q(rdCAS_reg_0),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair898" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1
       (.I0(calDone_reg_6),
        .I1(\rdEn_reg[29]_0 ),
        .I2(calDone_reg_9),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_1[1]));
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__0
       (.I0(calDone_reg_6),
        .I1(\rdEn_reg[29]_1 ),
        .I2(calDone_reg_9),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_2[1]));
  (* SOFT_HLUTNM = "soft_lutpair899" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__1
       (.I0(calDone_reg_7),
        .I1(\rdEn_reg[29]_2 ),
        .I2(calDone_reg_9),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_3[1]));
  (* SOFT_HLUTNM = "soft_lutpair894" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__10
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[29]_9 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_10[1]));
  (* SOFT_HLUTNM = "soft_lutpair894" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__11
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[29]_10 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_11[1]));
  (* SOFT_HLUTNM = "soft_lutpair895" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__12
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[29]_11 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_12[1]));
  (* SOFT_HLUTNM = "soft_lutpair896" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__13
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[29]_12 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_13[1]));
  (* SOFT_HLUTNM = "soft_lutpair897" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__14
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[29]_13 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_14[1]));
  (* SOFT_HLUTNM = "soft_lutpair900" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__2
       (.I0(calDone_reg_7),
        .I1(\rdEn_reg[29]_3 ),
        .I2(calDone_reg_9),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_4[1]));
  LUT6 #(
    .INIT(64'h000000000000DFD5)) 
    rdEn_nxt_inferred_i_1__3
       (.I0(calDone_reg_10),
        .I1(\rsMask_reg[7]_77 [1]),
        .I2(calDone_reg_12),
        .I3(\rsMask_reg[5]_75 [1]),
        .I4(rdEn_nxt_inferred_i_33__2_n_0),
        .I5(rdEn_nxt_inferred_i_34__3_n_0),
        .O(in0[1]));
  LUT6 #(
    .INIT(64'h000000000000DFD5)) 
    rdEn_nxt_inferred_i_1__4
       (.I0(calDone_reg_10),
        .I1(\rsMask_reg[7]_85 [1]),
        .I2(calDone_reg_12),
        .I3(\rsMask_reg[5]_83 [1]),
        .I4(rdEn_nxt_inferred_i_31__2_n_0),
        .I5(rdEn_nxt_inferred_i_34__3_n_0),
        .O(\rsMask_reg[7][18] [1]));
  (* SOFT_HLUTNM = "soft_lutpair888" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__5
       (.I0(calDone_reg_6),
        .I1(\rdEn_reg[29]_4 ),
        .I2(calDone_reg_8),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_5[1]));
  (* SOFT_HLUTNM = "soft_lutpair889" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__6
       (.I0(calDone_reg_6),
        .I1(\rdEn_reg[29]_5 ),
        .I2(calDone_reg_8),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_6[1]));
  (* SOFT_HLUTNM = "soft_lutpair890" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__7
       (.I0(calDone_reg_6),
        .I1(\rdEn_reg[29]_6 ),
        .I2(calDone_reg_8),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_7[1]));
  (* SOFT_HLUTNM = "soft_lutpair892" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__8
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[29]_7 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_8[1]));
  (* SOFT_HLUTNM = "soft_lutpair893" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_1__9
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[29]_8 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_9[1]));
  (* SOFT_HLUTNM = "soft_lutpair898" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2
       (.I0(calDone_reg_6),
        .I1(\rdEn_reg[28] ),
        .I2(calDone_reg_9),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_1[0]));
  (* SOFT_HLUTNM = "soft_lutpair899" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__0
       (.I0(calDone_reg_7),
        .I1(\rdEn_reg[28]_0 ),
        .I2(calDone_reg_9),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_2[0]));
  (* SOFT_HLUTNM = "soft_lutpair900" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__1
       (.I0(calDone_reg_7),
        .I1(\rdEn_reg[28]_1 ),
        .I2(calDone_reg_9),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_3[0]));
  (* SOFT_HLUTNM = "soft_lutpair891" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__10
       (.I0(calDone_reg_6),
        .I1(\rdEn_reg[28]_8 ),
        .I2(calDone_reg_8),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_10[0]));
  (* SOFT_HLUTNM = "soft_lutpair895" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__11
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[28]_9 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_11[0]));
  (* SOFT_HLUTNM = "soft_lutpair896" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__12
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[28]_10 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_12[0]));
  (* SOFT_HLUTNM = "soft_lutpair897" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__13
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[28]_11 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_13[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__14
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[28]_12 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_14[0]));
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__2
       (.I0(calDone_reg_7),
        .I1(\rdEn_reg[28]_2 ),
        .I2(calDone_reg_9),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_4[0]));
  LUT6 #(
    .INIT(64'h000000000000DFD5)) 
    rdEn_nxt_inferred_i_2__3
       (.I0(calDone_reg_10),
        .I1(\rsMask_reg[7]_85 [0]),
        .I2(calDone_reg_13),
        .I3(\rsMask_reg[5]_83 [0]),
        .I4(rdEn_nxt_inferred_i_33__3_n_0),
        .I5(rdEn_nxt_inferred_i_34__3_n_0),
        .O(\rsMask_reg[7][18] [0]));
  LUT6 #(
    .INIT(64'h000000000000DFD5)) 
    rdEn_nxt_inferred_i_2__4
       (.I0(calDone_reg_10),
        .I1(\rsMask_reg[7]_77 [0]),
        .I2(calDone_reg_12),
        .I3(\rsMask_reg[5]_75 [0]),
        .I4(rdEn_nxt_inferred_i_35__4_n_0),
        .I5(rdEn_nxt_inferred_i_34__3_n_0),
        .O(in0[0]));
  (* SOFT_HLUTNM = "soft_lutpair889" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__5
       (.I0(calDone_reg_6),
        .I1(\rdEn_reg[28]_3 ),
        .I2(calDone_reg_8),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_5[0]));
  (* SOFT_HLUTNM = "soft_lutpair890" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__6
       (.I0(calDone_reg_6),
        .I1(\rdEn_reg[28]_4 ),
        .I2(calDone_reg_8),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_6[0]));
  (* SOFT_HLUTNM = "soft_lutpair891" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__7
       (.I0(calDone_reg_6),
        .I1(\rdEn_reg[28]_5 ),
        .I2(calDone_reg_8),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_7[0]));
  (* SOFT_HLUTNM = "soft_lutpair892" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__8
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[28]_6 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_8[0]));
  (* SOFT_HLUTNM = "soft_lutpair893" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    rdEn_nxt_inferred_i_2__9
       (.I0(calDone_reg_1),
        .I1(\rdEn_reg[28]_7 ),
        .I2(calDone_reg_2),
        .I3(\rdEn_reg[29] ),
        .O(rst_r1_reg_9[0]));
  (* SOFT_HLUTNM = "soft_lutpair1161" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    rdEn_nxt_inferred_i_31__12
       (.I0(mcRdCAS),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(rdCAS_reg_0),
        .O(calDone_reg_1));
  LUT3 #(
    .INIT(8'hB8)) 
    rdEn_nxt_inferred_i_31__13
       (.I0(mcRdCAS),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(rdCAS_reg_0),
        .O(calDone_reg_6));
  LUT3 #(
    .INIT(8'hB8)) 
    rdEn_nxt_inferred_i_31__14
       (.I0(1'b0),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(\clb2phy_wrcs1_low_reg_n_0_[31] ),
        .O(calDone_reg_10));
  LUT4 #(
    .INIT(16'h0151)) 
    rdEn_nxt_inferred_i_31__2
       (.I0(calDone_reg_10),
        .I1(\rsMask_reg[1]_79 [1]),
        .I2(calDone_reg_12),
        .I3(\rsMask_reg[3]_81 [1]),
        .O(rdEn_nxt_inferred_i_31__2_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    rdEn_nxt_inferred_i_32__11
       (.I0(mcRdCAS),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(rdCAS_reg_0),
        .O(calDone_reg_7));
  LUT3 #(
    .INIT(8'hB8)) 
    rdEn_nxt_inferred_i_32__12
       (.I0(mcCasSlot2),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(calCasSlot),
        .O(calDone_reg_8));
  LUT3 #(
    .INIT(8'hB8)) 
    rdEn_nxt_inferred_i_32__13
       (.I0(1'b0),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(\clb2phy_wrcs0_low_reg_n_0_[31] ),
        .O(calDone_reg_12));
  LUT3 #(
    .INIT(8'hB8)) 
    rdEn_nxt_inferred_i_32__14
       (.I0(1'b0),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(\clb2phy_wrcs0_low_reg_n_0_[31] ),
        .O(calDone_reg_13));
  (* SOFT_HLUTNM = "soft_lutpair1161" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    rdEn_nxt_inferred_i_33__13
       (.I0(mcCasSlot2),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(calCasSlot),
        .O(calDone_reg_2));
  LUT3 #(
    .INIT(8'hB8)) 
    rdEn_nxt_inferred_i_33__14
       (.I0(mcCasSlot2),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(calCasSlot),
        .O(calDone_reg_9));
  LUT4 #(
    .INIT(16'h0151)) 
    rdEn_nxt_inferred_i_33__2
       (.I0(calDone_reg_10),
        .I1(\rsMask_reg[1]_71 [1]),
        .I2(calDone_reg_12),
        .I3(\rsMask_reg[3]_73 [1]),
        .O(rdEn_nxt_inferred_i_33__2_n_0));
  LUT4 #(
    .INIT(16'h0151)) 
    rdEn_nxt_inferred_i_33__3
       (.I0(calDone_reg_10),
        .I1(\rsMask_reg[1]_79 [0]),
        .I2(calDone_reg_13),
        .I3(\rsMask_reg[3]_81 [0]),
        .O(rdEn_nxt_inferred_i_33__3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair888" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    rdEn_nxt_inferred_i_34__3
       (.I0(calDone_reg_6),
        .I1(\rdEn_reg[29] ),
        .I2(calDone_reg_8),
        .O(rdEn_nxt_inferred_i_34__3_n_0));
  LUT4 #(
    .INIT(16'h0151)) 
    rdEn_nxt_inferred_i_35__4
       (.I0(calDone_reg_10),
        .I1(\rsMask_reg[1]_71 [0]),
        .I2(calDone_reg_12),
        .I3(\rsMask_reg[3]_73 [0]),
        .O(rdEn_nxt_inferred_i_35__4_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    rdEn_nxt_inferred_i_55__1
       (.I0(1'b0),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(\clb2phy_wrcs1_low_reg_n_0_[31] ),
        .O(mcalRank[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    rdEn_nxt_inferred_i_55__2
       (.I0(1'b0),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(\clb2phy_wrcs1_low_reg_n_0_[31] ),
        .O(calDone_reg_11));
  LUT3 #(
    .INIT(8'hB8)) 
    rdEn_nxt_inferred_i_56__1
       (.I0(1'b0),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(\clb2phy_wrcs0_low_reg_n_0_[31] ),
        .O(mcalRank[0]));
  FDSE \rd_vref_value_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[0]),
        .D(io_write_data[0]),
        .Q(mcal_rd_vref_value[0]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[1]),
        .D(io_write_data[3]),
        .Q(mcal_rd_vref_value[10]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[1]),
        .D(io_write_data[4]),
        .Q(mcal_rd_vref_value[11]),
        .S(rst_r1));
  FDRE \rd_vref_value_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[1]),
        .D(io_write_data[5]),
        .Q(mcal_rd_vref_value[12]),
        .R(rst_r1));
  FDRE \rd_vref_value_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[1]),
        .D(io_write_data[6]),
        .Q(mcal_rd_vref_value[13]),
        .R(rst_r1));
  FDSE \rd_vref_value_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[2]),
        .D(io_write_data[0]),
        .Q(mcal_rd_vref_value[14]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[2]),
        .D(io_write_data[1]),
        .Q(mcal_rd_vref_value[15]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[2]),
        .D(io_write_data[2]),
        .Q(mcal_rd_vref_value[16]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[2]),
        .D(io_write_data[3]),
        .Q(mcal_rd_vref_value[17]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[2]),
        .D(io_write_data[4]),
        .Q(mcal_rd_vref_value[18]),
        .S(rst_r1));
  FDRE \rd_vref_value_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[2]),
        .D(io_write_data[5]),
        .Q(mcal_rd_vref_value[19]),
        .R(rst_r1));
  FDSE \rd_vref_value_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[0]),
        .D(io_write_data[1]),
        .Q(mcal_rd_vref_value[1]),
        .S(rst_r1));
  FDRE \rd_vref_value_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[2]),
        .D(io_write_data[6]),
        .Q(mcal_rd_vref_value[20]),
        .R(rst_r1));
  FDSE \rd_vref_value_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[3]),
        .D(io_write_data[0]),
        .Q(mcal_rd_vref_value[21]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[3]),
        .D(io_write_data[1]),
        .Q(mcal_rd_vref_value[22]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[3]),
        .D(io_write_data[2]),
        .Q(mcal_rd_vref_value[23]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[3]),
        .D(io_write_data[3]),
        .Q(mcal_rd_vref_value[24]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[3]),
        .D(io_write_data[4]),
        .Q(mcal_rd_vref_value[25]),
        .S(rst_r1));
  FDRE \rd_vref_value_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[3]),
        .D(io_write_data[5]),
        .Q(mcal_rd_vref_value[26]),
        .R(rst_r1));
  FDRE \rd_vref_value_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[3]),
        .D(io_write_data[6]),
        .Q(mcal_rd_vref_value[27]),
        .R(rst_r1));
  FDSE \rd_vref_value_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[4]),
        .D(io_write_data[0]),
        .Q(mcal_rd_vref_value[28]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[4]),
        .D(io_write_data[1]),
        .Q(mcal_rd_vref_value[29]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[0]),
        .D(io_write_data[2]),
        .Q(mcal_rd_vref_value[2]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[4]),
        .D(io_write_data[2]),
        .Q(mcal_rd_vref_value[30]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[4]),
        .D(io_write_data[3]),
        .Q(mcal_rd_vref_value[31]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[4]),
        .D(io_write_data[4]),
        .Q(mcal_rd_vref_value[32]),
        .S(rst_r1));
  FDRE \rd_vref_value_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[4]),
        .D(io_write_data[5]),
        .Q(mcal_rd_vref_value[33]),
        .R(rst_r1));
  FDRE \rd_vref_value_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[4]),
        .D(io_write_data[6]),
        .Q(mcal_rd_vref_value[34]),
        .R(rst_r1));
  FDSE \rd_vref_value_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[5]),
        .D(io_write_data[0]),
        .Q(mcal_rd_vref_value[35]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[5]),
        .D(io_write_data[1]),
        .Q(mcal_rd_vref_value[36]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[5]),
        .D(io_write_data[2]),
        .Q(mcal_rd_vref_value[37]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[5]),
        .D(io_write_data[3]),
        .Q(mcal_rd_vref_value[38]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[5]),
        .D(io_write_data[4]),
        .Q(mcal_rd_vref_value[39]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[0]),
        .D(io_write_data[3]),
        .Q(mcal_rd_vref_value[3]),
        .S(rst_r1));
  FDRE \rd_vref_value_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[5]),
        .D(io_write_data[5]),
        .Q(mcal_rd_vref_value[40]),
        .R(rst_r1));
  FDRE \rd_vref_value_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[5]),
        .D(io_write_data[6]),
        .Q(mcal_rd_vref_value[41]),
        .R(rst_r1));
  FDSE \rd_vref_value_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[6]),
        .D(io_write_data[0]),
        .Q(mcal_rd_vref_value[42]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[6]),
        .D(io_write_data[1]),
        .Q(mcal_rd_vref_value[43]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[6]),
        .D(io_write_data[2]),
        .Q(mcal_rd_vref_value[44]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[6]),
        .D(io_write_data[3]),
        .Q(mcal_rd_vref_value[45]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[6]),
        .D(io_write_data[4]),
        .Q(mcal_rd_vref_value[46]),
        .S(rst_r1));
  FDRE \rd_vref_value_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[6]),
        .D(io_write_data[5]),
        .Q(mcal_rd_vref_value[47]),
        .R(rst_r1));
  FDRE \rd_vref_value_reg[48] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[6]),
        .D(io_write_data[6]),
        .Q(mcal_rd_vref_value[48]),
        .R(rst_r1));
  FDSE \rd_vref_value_reg[49] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[7]),
        .D(io_write_data[0]),
        .Q(mcal_rd_vref_value[49]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[0]),
        .D(io_write_data[4]),
        .Q(mcal_rd_vref_value[4]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[50] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[7]),
        .D(io_write_data[1]),
        .Q(mcal_rd_vref_value[50]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[51] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[7]),
        .D(io_write_data[2]),
        .Q(mcal_rd_vref_value[51]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[52] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[7]),
        .D(io_write_data[3]),
        .Q(mcal_rd_vref_value[52]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[53] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[7]),
        .D(io_write_data[4]),
        .Q(mcal_rd_vref_value[53]),
        .S(rst_r1));
  FDRE \rd_vref_value_reg[54] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[7]),
        .D(io_write_data[5]),
        .Q(mcal_rd_vref_value[54]),
        .R(rst_r1));
  FDRE \rd_vref_value_reg[55] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[7]),
        .D(io_write_data[6]),
        .Q(mcal_rd_vref_value[55]),
        .R(rst_r1));
  FDRE \rd_vref_value_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[0]),
        .D(io_write_data[5]),
        .Q(mcal_rd_vref_value[5]),
        .R(rst_r1));
  FDRE \rd_vref_value_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[0]),
        .D(io_write_data[6]),
        .Q(mcal_rd_vref_value[6]),
        .R(rst_r1));
  FDSE \rd_vref_value_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[1]),
        .D(io_write_data[0]),
        .Q(mcal_rd_vref_value[7]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[1]),
        .D(io_write_data[1]),
        .Q(mcal_rd_vref_value[8]),
        .S(rst_r1));
  FDSE \rd_vref_value_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(rd_vref_value0_out[1]),
        .D(io_write_data[2]),
        .Q(mcal_rd_vref_value[9]),
        .S(rst_r1));
  LUT6 #(
    .INIT(64'hAAFFFFAAFF55FFD5)) 
    \retSt[3]_i_1 
       (.I0(Q[0]),
        .I1(ub_initDone_reg_0),
        .I2(pllGate),
        .I3(Q[3]),
        .I4(Q[1]),
        .I5(Q[2]),
        .O(\calSt_reg[0] ));
  (* KEEP = "yes" *) 
  FDRE rst_r1_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(SR),
        .Q(rst_r1),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    seq_cnt_access_i_1
       (.I0(seq_cnt_access),
        .I1(rst_r1),
        .I2(a_b_cmd_sel_start0),
        .O(seq_cnt_access_i_1_n_0));
  FDRE seq_cnt_access_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(seq_cnt_access_i_1_n_0),
        .Q(seq_cnt_access),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0800)) 
    seq_cnt_dec_i_1
       (.I0(\cmd_gen_dly_reg[7]_i_3_n_0 ),
        .I1(cal_seq_cnt_gt_0),
        .I2(rst_r1),
        .I3(cmd_go_reg_n_0),
        .O(seq_cnt_dec_i_1_n_0));
  FDRE seq_cnt_dec_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(seq_cnt_dec_i_1_n_0),
        .Q(seq_cnt_dec),
        .R(1'b0));
  FDRE stop_gate_tracking_ack_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(stop_gate_tracking_ack_reg_1),
        .Q(stop_gate_tracking_ack_reg_0),
        .R(rst_r1));
  SRL16E traffic_clr_error_r1_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\odt_shift_reg[0][17] ),
        .D(cnt_clr_reg_0),
        .Q(traffic_clr_error_r1_reg_srl2_n_0));
  FDRE traffic_clr_error_r2_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(traffic_clr_error_r1_reg_srl2_n_0),
        .Q(traffic_clr_error_r2),
        .R(1'b0));
  FDRE \traffic_instr_nxt_instr_r1_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\traffic_instr_nxt_instr_r1_reg[5]_0 ),
        .D(io_write_data[0]),
        .Q(\traffic_instr_nxt_instr_r1_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \traffic_instr_nxt_instr_r1_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\traffic_instr_nxt_instr_r1_reg[5]_0 ),
        .D(io_write_data[1]),
        .Q(\traffic_instr_nxt_instr_r1_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \traffic_instr_nxt_instr_r1_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\traffic_instr_nxt_instr_r1_reg[5]_0 ),
        .D(io_write_data[2]),
        .Q(\traffic_instr_nxt_instr_r1_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \traffic_instr_nxt_instr_r1_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\traffic_instr_nxt_instr_r1_reg[5]_0 ),
        .D(io_write_data[3]),
        .Q(\traffic_instr_nxt_instr_r1_reg_n_0_[3] ),
        .R(rst_r1));
  FDRE \traffic_instr_nxt_instr_r1_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\traffic_instr_nxt_instr_r1_reg[5]_0 ),
        .D(io_write_data[4]),
        .Q(\traffic_instr_nxt_instr_r1_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE \traffic_instr_nxt_instr_r1_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\traffic_instr_nxt_instr_r1_reg[5]_0 ),
        .D(io_write_data[5]),
        .Q(\traffic_instr_nxt_instr_r1_reg_n_0_[5] ),
        .R(rst_r1));
  ddr4_0_ddr4_v2_2_17_cal_cplx u_ddr_cal_cplx
       (.D({extended_write[1:0],cal_seq_cnt0}),
        .\FSM_sequential_cplx_state_reg[1]_0 ({\cplx_config_reg_n_0_[16] ,\cplx_config_reg_n_0_[0] }),
        .\FSM_sequential_cplx_state_reg[2]_i_2_0 (\cplx_config_reg_n_0_[10] ),
        .\FSM_sequential_cplx_state_reg[2]_i_2_1 (\cplx_config_reg_n_0_[9] ),
        .\FSM_sequential_cplx_state_reg[2]_i_2_2 (\cplx_config_reg_n_0_[12] ),
        .\FSM_sequential_cplx_state_reg[2]_i_2_3 (\cplx_config_reg_n_0_[11] ),
        .\FSM_sequential_cplx_state_reg[2]_i_2_4 (\cplx_config_reg_n_0_[14] ),
        .\FSM_sequential_cplx_state_reg[2]_i_2_5 (\cplx_config_reg_n_0_[13] ),
        .\FSM_sequential_cplx_state_reg[2]_i_2_6 (\cplx_config_reg_n_0_[15] ),
        .\FSM_sequential_cplx_state_reg[3]_0 (\cplx_config_reg_n_0_[1] ),
        .Q(cal_CAS_pre),
        .SS(cal_CS_n_pre),
        .\SYNC[20].sync_reg_reg[1] (\SYNC[20].sync_reg_reg[1] ),
        .a_b_cmd_sel(a_b_cmd_sel),
        .\addr_dec_to_mb_data[0]_i_2 (\cal_CS_A_reg[0]_0 ),
        .\addr_dec_to_mb_data[0]_i_2_0 (io_ready_reg_0),
        .\addr_dec_to_mb_data[0]_i_2_1 (calDone_reg_0),
        .\addr_dec_to_mb_data_reg[12] (\cal_ADR_B_reg[12]_0 ),
        .\addr_dec_to_mb_data_reg[12]_0 (\addr_dec_to_mb_data_reg[12]_0 ),
        .\addr_dec_to_mb_data_reg[15] (\addr_dec_to_mb_data_reg[15]_0 ),
        .\addr_dec_to_mb_data_reg[19] (\addr_dec_to_mb_data_reg[19]_0 ),
        .calDone_reg(calDone_reg_3),
        .calDone_reg_0(calDone_reg_4),
        .calDone_reg_1(calDone_reg_5),
        .\cal_ACT_n_pre_reg[7] (\cal_ACT_n_pre_reg[7]_0 ),
        .cal_CS_n(cal_CS_n),
        .\cal_CS_n_pre_reg[0] (\cal_CS_n_pre[7]_i_3_n_0 ),
        .\cal_DMOut_n_reg[15] (\genblk10[1].cal_DMOut_n_A_r_reg ),
        .\cal_DMOut_n_reg[23] (\genblk10[2].cal_DMOut_n_A_r_reg ),
        .\cal_DMOut_n_reg[31] (\genblk10[3].cal_DMOut_n_A_r_reg ),
        .\cal_DMOut_n_reg[39] (\genblk10[4].cal_DMOut_n_A_r_reg ),
        .\cal_DMOut_n_reg[47] (\genblk10[5].cal_DMOut_n_A_r_reg ),
        .\cal_DMOut_n_reg[55] (\genblk10[6].cal_DMOut_n_A_r_reg ),
        .\cal_DMOut_n_reg[63] (\genblk10[7].cal_DMOut_n_A_r_reg ),
        .\cal_DMOut_n_reg[7] (\genblk10[0].cal_DMOut_n_A_r_reg ),
        .\cal_DQOut_reg[511] ({\cal_DQ_reg_n_0_[511] ,\cal_DQ_reg_n_0_[510] ,\cal_DQ_reg_n_0_[509] ,\cal_DQ_reg_n_0_[508] ,\cal_DQ_reg_n_0_[507] ,\cal_DQ_reg_n_0_[506] ,\cal_DQ_reg_n_0_[505] ,\cal_DQ_reg_n_0_[504] ,\cal_DQ_reg_n_0_[503] ,\cal_DQ_reg_n_0_[502] ,\cal_DQ_reg_n_0_[501] ,\cal_DQ_reg_n_0_[500] ,\cal_DQ_reg_n_0_[499] ,\cal_DQ_reg_n_0_[498] ,\cal_DQ_reg_n_0_[497] ,\cal_DQ_reg_n_0_[496] ,\cal_DQ_reg_n_0_[495] ,\cal_DQ_reg_n_0_[494] ,\cal_DQ_reg_n_0_[493] ,\cal_DQ_reg_n_0_[492] ,\cal_DQ_reg_n_0_[491] ,\cal_DQ_reg_n_0_[490] ,\cal_DQ_reg_n_0_[489] ,\cal_DQ_reg_n_0_[488] ,\cal_DQ_reg_n_0_[487] ,\cal_DQ_reg_n_0_[486] ,\cal_DQ_reg_n_0_[485] ,\cal_DQ_reg_n_0_[484] ,\cal_DQ_reg_n_0_[483] ,\cal_DQ_reg_n_0_[482] ,\cal_DQ_reg_n_0_[481] ,\cal_DQ_reg_n_0_[480] ,\cal_DQ_reg_n_0_[479] ,\cal_DQ_reg_n_0_[478] ,\cal_DQ_reg_n_0_[477] ,\cal_DQ_reg_n_0_[476] ,\cal_DQ_reg_n_0_[475] ,\cal_DQ_reg_n_0_[474] ,\cal_DQ_reg_n_0_[473] ,\cal_DQ_reg_n_0_[472] ,\cal_DQ_reg_n_0_[471] ,\cal_DQ_reg_n_0_[470] ,\cal_DQ_reg_n_0_[469] ,\cal_DQ_reg_n_0_[468] ,\cal_DQ_reg_n_0_[467] ,\cal_DQ_reg_n_0_[466] ,\cal_DQ_reg_n_0_[465] ,\cal_DQ_reg_n_0_[464] ,\cal_DQ_reg_n_0_[463] ,\cal_DQ_reg_n_0_[462] ,\cal_DQ_reg_n_0_[461] ,\cal_DQ_reg_n_0_[460] ,\cal_DQ_reg_n_0_[459] ,\cal_DQ_reg_n_0_[458] ,\cal_DQ_reg_n_0_[457] ,\cal_DQ_reg_n_0_[456] ,\cal_DQ_reg_n_0_[455] ,\cal_DQ_reg_n_0_[454] ,\cal_DQ_reg_n_0_[453] ,\cal_DQ_reg_n_0_[452] ,\cal_DQ_reg_n_0_[451] ,\cal_DQ_reg_n_0_[450] ,\cal_DQ_reg_n_0_[449] ,\cal_DQ_reg_n_0_[448] ,\cal_DQ_reg_n_0_[447] ,\cal_DQ_reg_n_0_[446] ,\cal_DQ_reg_n_0_[445] ,\cal_DQ_reg_n_0_[444] ,\cal_DQ_reg_n_0_[443] ,\cal_DQ_reg_n_0_[442] ,\cal_DQ_reg_n_0_[441] ,\cal_DQ_reg_n_0_[440] ,\cal_DQ_reg_n_0_[439] ,\cal_DQ_reg_n_0_[438] ,\cal_DQ_reg_n_0_[437] ,\cal_DQ_reg_n_0_[436] ,\cal_DQ_reg_n_0_[435] ,\cal_DQ_reg_n_0_[434] ,\cal_DQ_reg_n_0_[433] ,\cal_DQ_reg_n_0_[432] ,\cal_DQ_reg_n_0_[431] ,\cal_DQ_reg_n_0_[430] ,\cal_DQ_reg_n_0_[429] ,\cal_DQ_reg_n_0_[428] ,\cal_DQ_reg_n_0_[427] ,\cal_DQ_reg_n_0_[426] ,\cal_DQ_reg_n_0_[425] ,\cal_DQ_reg_n_0_[424] ,\cal_DQ_reg_n_0_[423] ,\cal_DQ_reg_n_0_[422] ,\cal_DQ_reg_n_0_[421] ,\cal_DQ_reg_n_0_[420] ,\cal_DQ_reg_n_0_[419] ,\cal_DQ_reg_n_0_[418] ,\cal_DQ_reg_n_0_[417] ,\cal_DQ_reg_n_0_[416] ,\cal_DQ_reg_n_0_[415] ,\cal_DQ_reg_n_0_[414] ,\cal_DQ_reg_n_0_[413] ,\cal_DQ_reg_n_0_[412] ,\cal_DQ_reg_n_0_[411] ,\cal_DQ_reg_n_0_[410] ,\cal_DQ_reg_n_0_[409] ,\cal_DQ_reg_n_0_[408] ,\cal_DQ_reg_n_0_[407] ,\cal_DQ_reg_n_0_[406] ,\cal_DQ_reg_n_0_[405] ,\cal_DQ_reg_n_0_[404] ,\cal_DQ_reg_n_0_[403] ,\cal_DQ_reg_n_0_[402] ,\cal_DQ_reg_n_0_[401] ,\cal_DQ_reg_n_0_[400] ,\cal_DQ_reg_n_0_[399] ,\cal_DQ_reg_n_0_[398] ,\cal_DQ_reg_n_0_[397] ,\cal_DQ_reg_n_0_[396] ,\cal_DQ_reg_n_0_[395] ,\cal_DQ_reg_n_0_[394] ,\cal_DQ_reg_n_0_[393] ,\cal_DQ_reg_n_0_[392] ,\cal_DQ_reg_n_0_[391] ,\cal_DQ_reg_n_0_[390] ,\cal_DQ_reg_n_0_[389] ,\cal_DQ_reg_n_0_[388] ,\cal_DQ_reg_n_0_[387] ,\cal_DQ_reg_n_0_[386] ,\cal_DQ_reg_n_0_[385] ,\cal_DQ_reg_n_0_[384] ,\cal_DQ_reg_n_0_[383] ,\cal_DQ_reg_n_0_[382] ,\cal_DQ_reg_n_0_[381] ,\cal_DQ_reg_n_0_[380] ,\cal_DQ_reg_n_0_[379] ,\cal_DQ_reg_n_0_[378] ,\cal_DQ_reg_n_0_[377] ,\cal_DQ_reg_n_0_[376] ,\cal_DQ_reg_n_0_[375] ,\cal_DQ_reg_n_0_[374] ,\cal_DQ_reg_n_0_[373] ,\cal_DQ_reg_n_0_[372] ,\cal_DQ_reg_n_0_[371] ,\cal_DQ_reg_n_0_[370] ,\cal_DQ_reg_n_0_[369] ,\cal_DQ_reg_n_0_[368] ,\cal_DQ_reg_n_0_[367] ,\cal_DQ_reg_n_0_[366] ,\cal_DQ_reg_n_0_[365] ,\cal_DQ_reg_n_0_[364] ,\cal_DQ_reg_n_0_[363] ,\cal_DQ_reg_n_0_[362] ,\cal_DQ_reg_n_0_[361] ,\cal_DQ_reg_n_0_[360] ,\cal_DQ_reg_n_0_[359] ,\cal_DQ_reg_n_0_[358] ,\cal_DQ_reg_n_0_[357] ,\cal_DQ_reg_n_0_[356] ,\cal_DQ_reg_n_0_[355] ,\cal_DQ_reg_n_0_[354] ,\cal_DQ_reg_n_0_[353] ,\cal_DQ_reg_n_0_[352] ,\cal_DQ_reg_n_0_[351] ,\cal_DQ_reg_n_0_[350] ,\cal_DQ_reg_n_0_[349] ,\cal_DQ_reg_n_0_[348] ,\cal_DQ_reg_n_0_[347] ,\cal_DQ_reg_n_0_[346] ,\cal_DQ_reg_n_0_[345] ,\cal_DQ_reg_n_0_[344] ,\cal_DQ_reg_n_0_[343] ,\cal_DQ_reg_n_0_[342] ,\cal_DQ_reg_n_0_[341] ,\cal_DQ_reg_n_0_[340] ,\cal_DQ_reg_n_0_[339] ,\cal_DQ_reg_n_0_[338] ,\cal_DQ_reg_n_0_[337] ,\cal_DQ_reg_n_0_[336] ,\cal_DQ_reg_n_0_[335] ,\cal_DQ_reg_n_0_[334] ,\cal_DQ_reg_n_0_[333] ,\cal_DQ_reg_n_0_[332] ,\cal_DQ_reg_n_0_[331] ,\cal_DQ_reg_n_0_[330] ,\cal_DQ_reg_n_0_[329] ,\cal_DQ_reg_n_0_[328] ,\cal_DQ_reg_n_0_[327] ,\cal_DQ_reg_n_0_[326] ,\cal_DQ_reg_n_0_[325] ,\cal_DQ_reg_n_0_[324] ,\cal_DQ_reg_n_0_[323] ,\cal_DQ_reg_n_0_[322] ,\cal_DQ_reg_n_0_[321] ,\cal_DQ_reg_n_0_[320] ,\cal_DQ_reg_n_0_[319] ,\cal_DQ_reg_n_0_[318] ,\cal_DQ_reg_n_0_[317] ,\cal_DQ_reg_n_0_[316] ,\cal_DQ_reg_n_0_[315] ,\cal_DQ_reg_n_0_[314] ,\cal_DQ_reg_n_0_[313] ,\cal_DQ_reg_n_0_[312] ,\cal_DQ_reg_n_0_[311] ,\cal_DQ_reg_n_0_[310] ,\cal_DQ_reg_n_0_[309] ,\cal_DQ_reg_n_0_[308] ,\cal_DQ_reg_n_0_[307] ,\cal_DQ_reg_n_0_[306] ,\cal_DQ_reg_n_0_[305] ,\cal_DQ_reg_n_0_[304] ,\cal_DQ_reg_n_0_[303] ,\cal_DQ_reg_n_0_[302] ,\cal_DQ_reg_n_0_[301] ,\cal_DQ_reg_n_0_[300] ,\cal_DQ_reg_n_0_[299] ,\cal_DQ_reg_n_0_[298] ,\cal_DQ_reg_n_0_[297] ,\cal_DQ_reg_n_0_[296] ,\cal_DQ_reg_n_0_[295] ,\cal_DQ_reg_n_0_[294] ,\cal_DQ_reg_n_0_[293] ,\cal_DQ_reg_n_0_[292] ,\cal_DQ_reg_n_0_[291] ,\cal_DQ_reg_n_0_[290] ,\cal_DQ_reg_n_0_[289] ,\cal_DQ_reg_n_0_[288] ,\cal_DQ_reg_n_0_[287] ,\cal_DQ_reg_n_0_[286] ,\cal_DQ_reg_n_0_[285] ,\cal_DQ_reg_n_0_[284] ,\cal_DQ_reg_n_0_[283] ,\cal_DQ_reg_n_0_[282] ,\cal_DQ_reg_n_0_[281] ,\cal_DQ_reg_n_0_[280] ,\cal_DQ_reg_n_0_[279] ,\cal_DQ_reg_n_0_[278] ,\cal_DQ_reg_n_0_[277] ,\cal_DQ_reg_n_0_[276] ,\cal_DQ_reg_n_0_[275] ,\cal_DQ_reg_n_0_[274] ,\cal_DQ_reg_n_0_[273] ,\cal_DQ_reg_n_0_[272] ,\cal_DQ_reg_n_0_[271] ,\cal_DQ_reg_n_0_[270] ,\cal_DQ_reg_n_0_[269] ,\cal_DQ_reg_n_0_[268] ,\cal_DQ_reg_n_0_[267] ,\cal_DQ_reg_n_0_[266] ,\cal_DQ_reg_n_0_[265] ,\cal_DQ_reg_n_0_[264] ,\cal_DQ_reg_n_0_[263] ,\cal_DQ_reg_n_0_[262] ,\cal_DQ_reg_n_0_[261] ,\cal_DQ_reg_n_0_[260] ,\cal_DQ_reg_n_0_[259] ,\cal_DQ_reg_n_0_[258] ,\cal_DQ_reg_n_0_[257] ,\cal_DQ_reg_n_0_[256] ,\cal_DQ_reg_n_0_[255] ,\cal_DQ_reg_n_0_[254] ,\cal_DQ_reg_n_0_[253] ,\cal_DQ_reg_n_0_[252] ,\cal_DQ_reg_n_0_[251] ,\cal_DQ_reg_n_0_[250] ,\cal_DQ_reg_n_0_[249] ,\cal_DQ_reg_n_0_[248] ,\cal_DQ_reg_n_0_[247] ,\cal_DQ_reg_n_0_[246] ,\cal_DQ_reg_n_0_[245] ,\cal_DQ_reg_n_0_[244] ,\cal_DQ_reg_n_0_[243] ,\cal_DQ_reg_n_0_[242] ,\cal_DQ_reg_n_0_[241] ,\cal_DQ_reg_n_0_[240] ,\cal_DQ_reg_n_0_[239] ,\cal_DQ_reg_n_0_[238] ,\cal_DQ_reg_n_0_[237] ,\cal_DQ_reg_n_0_[236] ,\cal_DQ_reg_n_0_[235] ,\cal_DQ_reg_n_0_[234] ,\cal_DQ_reg_n_0_[233] ,\cal_DQ_reg_n_0_[232] ,\cal_DQ_reg_n_0_[231] ,\cal_DQ_reg_n_0_[230] ,\cal_DQ_reg_n_0_[229] ,\cal_DQ_reg_n_0_[228] ,\cal_DQ_reg_n_0_[227] ,\cal_DQ_reg_n_0_[226] ,\cal_DQ_reg_n_0_[225] ,\cal_DQ_reg_n_0_[224] ,\cal_DQ_reg_n_0_[223] ,\cal_DQ_reg_n_0_[222] ,\cal_DQ_reg_n_0_[221] ,\cal_DQ_reg_n_0_[220] ,\cal_DQ_reg_n_0_[219] ,\cal_DQ_reg_n_0_[218] ,\cal_DQ_reg_n_0_[217] ,\cal_DQ_reg_n_0_[216] ,\cal_DQ_reg_n_0_[215] ,\cal_DQ_reg_n_0_[214] ,\cal_DQ_reg_n_0_[213] ,\cal_DQ_reg_n_0_[212] ,\cal_DQ_reg_n_0_[211] ,\cal_DQ_reg_n_0_[210] ,\cal_DQ_reg_n_0_[209] ,\cal_DQ_reg_n_0_[208] ,\cal_DQ_reg_n_0_[207] ,\cal_DQ_reg_n_0_[206] ,\cal_DQ_reg_n_0_[205] ,\cal_DQ_reg_n_0_[204] ,\cal_DQ_reg_n_0_[203] ,\cal_DQ_reg_n_0_[202] ,\cal_DQ_reg_n_0_[201] ,\cal_DQ_reg_n_0_[200] ,\cal_DQ_reg_n_0_[199] ,\cal_DQ_reg_n_0_[198] ,\cal_DQ_reg_n_0_[197] ,\cal_DQ_reg_n_0_[196] ,\cal_DQ_reg_n_0_[195] ,\cal_DQ_reg_n_0_[194] ,\cal_DQ_reg_n_0_[193] ,\cal_DQ_reg_n_0_[192] ,\cal_DQ_reg_n_0_[191] ,\cal_DQ_reg_n_0_[190] ,\cal_DQ_reg_n_0_[189] ,\cal_DQ_reg_n_0_[188] ,\cal_DQ_reg_n_0_[187] ,\cal_DQ_reg_n_0_[186] ,\cal_DQ_reg_n_0_[185] ,\cal_DQ_reg_n_0_[184] ,\cal_DQ_reg_n_0_[183] ,\cal_DQ_reg_n_0_[182] ,\cal_DQ_reg_n_0_[181] ,\cal_DQ_reg_n_0_[180] ,\cal_DQ_reg_n_0_[179] ,\cal_DQ_reg_n_0_[178] ,\cal_DQ_reg_n_0_[177] ,\cal_DQ_reg_n_0_[176] ,\cal_DQ_reg_n_0_[175] ,\cal_DQ_reg_n_0_[174] ,\cal_DQ_reg_n_0_[173] ,\cal_DQ_reg_n_0_[172] ,\cal_DQ_reg_n_0_[171] ,\cal_DQ_reg_n_0_[170] ,\cal_DQ_reg_n_0_[169] ,\cal_DQ_reg_n_0_[168] ,\cal_DQ_reg_n_0_[167] ,\cal_DQ_reg_n_0_[166] ,\cal_DQ_reg_n_0_[165] ,\cal_DQ_reg_n_0_[164] ,\cal_DQ_reg_n_0_[163] ,\cal_DQ_reg_n_0_[162] ,\cal_DQ_reg_n_0_[161] ,\cal_DQ_reg_n_0_[160] ,\cal_DQ_reg_n_0_[159] ,\cal_DQ_reg_n_0_[158] ,\cal_DQ_reg_n_0_[157] ,\cal_DQ_reg_n_0_[156] ,\cal_DQ_reg_n_0_[155] ,\cal_DQ_reg_n_0_[154] ,\cal_DQ_reg_n_0_[153] ,\cal_DQ_reg_n_0_[152] ,\cal_DQ_reg_n_0_[151] ,\cal_DQ_reg_n_0_[150] ,\cal_DQ_reg_n_0_[149] ,\cal_DQ_reg_n_0_[148] ,\cal_DQ_reg_n_0_[147] ,\cal_DQ_reg_n_0_[146] ,\cal_DQ_reg_n_0_[145] ,\cal_DQ_reg_n_0_[144] ,\cal_DQ_reg_n_0_[143] ,\cal_DQ_reg_n_0_[142] ,\cal_DQ_reg_n_0_[141] ,\cal_DQ_reg_n_0_[140] ,\cal_DQ_reg_n_0_[139] ,\cal_DQ_reg_n_0_[138] ,\cal_DQ_reg_n_0_[137] ,\cal_DQ_reg_n_0_[136] ,\cal_DQ_reg_n_0_[135] ,\cal_DQ_reg_n_0_[134] ,\cal_DQ_reg_n_0_[133] ,\cal_DQ_reg_n_0_[132] ,\cal_DQ_reg_n_0_[131] ,\cal_DQ_reg_n_0_[130] ,\cal_DQ_reg_n_0_[129] ,\cal_DQ_reg_n_0_[128] ,\cal_DQ_reg_n_0_[127] ,\cal_DQ_reg_n_0_[126] ,\cal_DQ_reg_n_0_[125] ,\cal_DQ_reg_n_0_[124] ,\cal_DQ_reg_n_0_[123] ,\cal_DQ_reg_n_0_[122] ,\cal_DQ_reg_n_0_[121] ,\cal_DQ_reg_n_0_[120] ,\cal_DQ_reg_n_0_[119] ,\cal_DQ_reg_n_0_[118] ,\cal_DQ_reg_n_0_[117] ,\cal_DQ_reg_n_0_[116] ,\cal_DQ_reg_n_0_[115] ,\cal_DQ_reg_n_0_[114] ,\cal_DQ_reg_n_0_[113] ,\cal_DQ_reg_n_0_[112] ,\cal_DQ_reg_n_0_[111] ,\cal_DQ_reg_n_0_[110] ,\cal_DQ_reg_n_0_[109] ,\cal_DQ_reg_n_0_[108] ,\cal_DQ_reg_n_0_[107] ,\cal_DQ_reg_n_0_[106] ,\cal_DQ_reg_n_0_[105] ,\cal_DQ_reg_n_0_[104] ,\cal_DQ_reg_n_0_[103] ,\cal_DQ_reg_n_0_[102] ,\cal_DQ_reg_n_0_[101] ,\cal_DQ_reg_n_0_[100] ,\cal_DQ_reg_n_0_[99] ,\cal_DQ_reg_n_0_[98] ,\cal_DQ_reg_n_0_[97] ,\cal_DQ_reg_n_0_[96] ,\cal_DQ_reg_n_0_[95] ,\cal_DQ_reg_n_0_[94] ,\cal_DQ_reg_n_0_[93] ,\cal_DQ_reg_n_0_[92] ,\cal_DQ_reg_n_0_[91] ,\cal_DQ_reg_n_0_[90] ,\cal_DQ_reg_n_0_[89] ,\cal_DQ_reg_n_0_[88] ,\cal_DQ_reg_n_0_[87] ,\cal_DQ_reg_n_0_[86] ,\cal_DQ_reg_n_0_[85] ,\cal_DQ_reg_n_0_[84] ,\cal_DQ_reg_n_0_[83] ,\cal_DQ_reg_n_0_[82] ,\cal_DQ_reg_n_0_[81] ,\cal_DQ_reg_n_0_[80] ,\cal_DQ_reg_n_0_[79] ,\cal_DQ_reg_n_0_[78] ,\cal_DQ_reg_n_0_[77] ,\cal_DQ_reg_n_0_[76] ,\cal_DQ_reg_n_0_[75] ,\cal_DQ_reg_n_0_[74] ,\cal_DQ_reg_n_0_[73] ,\cal_DQ_reg_n_0_[72] ,\cal_DQ_reg_n_0_[71] ,\cal_DQ_reg_n_0_[70] ,\cal_DQ_reg_n_0_[69] ,\cal_DQ_reg_n_0_[68] ,\cal_DQ_reg_n_0_[67] ,\cal_DQ_reg_n_0_[66] ,\cal_DQ_reg_n_0_[65] ,\cal_DQ_reg_n_0_[64] ,\cal_DQ_reg_n_0_[63] ,\cal_DQ_reg_n_0_[62] ,\cal_DQ_reg_n_0_[61] ,\cal_DQ_reg_n_0_[60] ,\cal_DQ_reg_n_0_[59] ,\cal_DQ_reg_n_0_[58] ,\cal_DQ_reg_n_0_[57] ,\cal_DQ_reg_n_0_[56] ,\cal_DQ_reg_n_0_[55] ,\cal_DQ_reg_n_0_[54] ,\cal_DQ_reg_n_0_[53] ,\cal_DQ_reg_n_0_[52] ,\cal_DQ_reg_n_0_[51] ,\cal_DQ_reg_n_0_[50] ,\cal_DQ_reg_n_0_[49] ,\cal_DQ_reg_n_0_[48] ,\cal_DQ_reg_n_0_[47] ,\cal_DQ_reg_n_0_[46] ,\cal_DQ_reg_n_0_[45] ,\cal_DQ_reg_n_0_[44] ,\cal_DQ_reg_n_0_[43] ,\cal_DQ_reg_n_0_[42] ,\cal_DQ_reg_n_0_[41] ,\cal_DQ_reg_n_0_[40] ,\cal_DQ_reg_n_0_[39] ,\cal_DQ_reg_n_0_[38] ,\cal_DQ_reg_n_0_[37] ,\cal_DQ_reg_n_0_[36] ,\cal_DQ_reg_n_0_[35] ,\cal_DQ_reg_n_0_[34] ,\cal_DQ_reg_n_0_[33] ,\cal_DQ_reg_n_0_[32] ,\cal_DQ_reg_n_0_[31] ,\cal_DQ_reg_n_0_[30] ,\cal_DQ_reg_n_0_[29] ,\cal_DQ_reg_n_0_[28] ,\cal_DQ_reg_n_0_[27] ,\cal_DQ_reg_n_0_[26] ,\cal_DQ_reg_n_0_[25] ,\cal_DQ_reg_n_0_[24] ,\cal_DQ_reg_n_0_[23] ,\cal_DQ_reg_n_0_[22] ,\cal_DQ_reg_n_0_[21] ,\cal_DQ_reg_n_0_[20] ,\cal_DQ_reg_n_0_[19] ,\cal_DQ_reg_n_0_[18] ,\cal_DQ_reg_n_0_[17] ,\cal_DQ_reg_n_0_[16] ,\cal_DQ_reg_n_0_[15] ,\cal_DQ_reg_n_0_[14] ,\cal_DQ_reg_n_0_[13] ,\cal_DQ_reg_n_0_[12] ,\cal_DQ_reg_n_0_[11] ,\cal_DQ_reg_n_0_[10] ,\cal_DQ_reg_n_0_[9] ,\cal_DQ_reg_n_0_[8] ,\cal_DQ_reg_n_0_[7] ,\cal_DQ_reg_n_0_[6] ,\cal_DQ_reg_n_0_[5] ,\cal_DQ_reg_n_0_[4] ,\cal_DQ_reg_n_0_[3] ,\cal_DQ_reg_n_0_[2] ,\cal_DQ_reg_n_0_[1] ,\cal_DQ_reg_n_0_[0] }),
        .\cal_RAS_pre_reg[1] (\cal_RAS_pre_reg[1]_0 ),
        .\cal_RAS_pre_reg[2] (\cal_RAS_pre_reg[2]_0 ),
        .\cplx_CAS_reg[6]_0 (\cplx_CAS_reg[6] ),
        .\cplx_CS_n_reg[6]_0 (\cplx_config_reg_n_0_[2] ),
        .\cplx_CS_n_reg[6]_1 (\cplx_config_reg_n_0_[3] ),
        .\cplx_DMOut_n_reg[63]_0 (cal_DMOut_n_nxt),
        .\cplx_DQOut_reg[511]_0 (cal_DQOut_nxt),
        .\cplx_RAS_reg[6]_0 (\cplx_RAS_reg[6] ),
        .\cplx_RAS_reg[6]_1 (\cplx_RAS_reg[6]_0 ),
        .cplx_cal(cplx_cal),
        .cplx_cal_reg_0(cplx_cal_reg),
        .\cplx_config_byte_select_reg[0]_0 (\cplx_config_reg_n_0_[7] ),
        .\cplx_config_byte_select_reg[0]_1 (\cplx_config_reg_n_0_[8] ),
        .\cplx_config_byte_select_reg[0]_2 (\cplx_config_reg_n_0_[4] ),
        .\cplx_config_byte_select_reg[1]_0 (\cplx_config_reg_n_0_[5] ),
        .\cplx_config_byte_select_reg[2]_0 (\cplx_config_reg_n_0_[6] ),
        .\cplx_dqin_byte_103_reg[63]_0 ({\mcal_DQIn_r_reg_n_0_[511] ,\mcal_DQIn_r_reg_n_0_[510] ,\mcal_DQIn_r_reg_n_0_[509] ,\mcal_DQIn_r_reg_n_0_[508] ,\mcal_DQIn_r_reg_n_0_[507] ,\mcal_DQIn_r_reg_n_0_[506] ,\mcal_DQIn_r_reg_n_0_[505] ,\mcal_DQIn_r_reg_n_0_[504] ,\mcal_DQIn_r_reg_n_0_[503] ,\mcal_DQIn_r_reg_n_0_[502] ,\mcal_DQIn_r_reg_n_0_[501] ,\mcal_DQIn_r_reg_n_0_[500] ,\mcal_DQIn_r_reg_n_0_[499] ,\mcal_DQIn_r_reg_n_0_[498] ,\mcal_DQIn_r_reg_n_0_[497] ,\mcal_DQIn_r_reg_n_0_[496] ,\mcal_DQIn_r_reg_n_0_[495] ,\mcal_DQIn_r_reg_n_0_[494] ,\mcal_DQIn_r_reg_n_0_[493] ,\mcal_DQIn_r_reg_n_0_[492] ,\mcal_DQIn_r_reg_n_0_[491] ,\mcal_DQIn_r_reg_n_0_[490] ,\mcal_DQIn_r_reg_n_0_[489] ,\mcal_DQIn_r_reg_n_0_[488] ,\mcal_DQIn_r_reg_n_0_[487] ,\mcal_DQIn_r_reg_n_0_[486] ,\mcal_DQIn_r_reg_n_0_[485] ,\mcal_DQIn_r_reg_n_0_[484] ,\mcal_DQIn_r_reg_n_0_[483] ,\mcal_DQIn_r_reg_n_0_[482] ,\mcal_DQIn_r_reg_n_0_[481] ,\mcal_DQIn_r_reg_n_0_[480] ,\mcal_DQIn_r_reg_n_0_[479] ,\mcal_DQIn_r_reg_n_0_[478] ,\mcal_DQIn_r_reg_n_0_[477] ,\mcal_DQIn_r_reg_n_0_[476] ,\mcal_DQIn_r_reg_n_0_[475] ,\mcal_DQIn_r_reg_n_0_[474] ,\mcal_DQIn_r_reg_n_0_[473] ,\mcal_DQIn_r_reg_n_0_[472] ,\mcal_DQIn_r_reg_n_0_[471] ,\mcal_DQIn_r_reg_n_0_[470] ,\mcal_DQIn_r_reg_n_0_[469] ,\mcal_DQIn_r_reg_n_0_[468] ,\mcal_DQIn_r_reg_n_0_[467] ,\mcal_DQIn_r_reg_n_0_[466] ,\mcal_DQIn_r_reg_n_0_[465] ,\mcal_DQIn_r_reg_n_0_[464] ,\mcal_DQIn_r_reg_n_0_[463] ,\mcal_DQIn_r_reg_n_0_[462] ,\mcal_DQIn_r_reg_n_0_[461] ,\mcal_DQIn_r_reg_n_0_[460] ,\mcal_DQIn_r_reg_n_0_[459] ,\mcal_DQIn_r_reg_n_0_[458] ,\mcal_DQIn_r_reg_n_0_[457] ,\mcal_DQIn_r_reg_n_0_[456] ,\mcal_DQIn_r_reg_n_0_[455] ,\mcal_DQIn_r_reg_n_0_[454] ,\mcal_DQIn_r_reg_n_0_[453] ,\mcal_DQIn_r_reg_n_0_[452] ,\mcal_DQIn_r_reg_n_0_[451] ,\mcal_DQIn_r_reg_n_0_[450] ,\mcal_DQIn_r_reg_n_0_[449] ,\mcal_DQIn_r_reg_n_0_[448] ,\mcal_DQIn_r_reg_n_0_[447] ,\mcal_DQIn_r_reg_n_0_[446] ,\mcal_DQIn_r_reg_n_0_[445] ,\mcal_DQIn_r_reg_n_0_[444] ,\mcal_DQIn_r_reg_n_0_[443] ,\mcal_DQIn_r_reg_n_0_[442] ,\mcal_DQIn_r_reg_n_0_[441] ,\mcal_DQIn_r_reg_n_0_[440] ,\mcal_DQIn_r_reg_n_0_[439] ,\mcal_DQIn_r_reg_n_0_[438] ,\mcal_DQIn_r_reg_n_0_[437] ,\mcal_DQIn_r_reg_n_0_[436] ,\mcal_DQIn_r_reg_n_0_[435] ,\mcal_DQIn_r_reg_n_0_[434] ,\mcal_DQIn_r_reg_n_0_[433] ,\mcal_DQIn_r_reg_n_0_[432] ,\mcal_DQIn_r_reg_n_0_[431] ,\mcal_DQIn_r_reg_n_0_[430] ,\mcal_DQIn_r_reg_n_0_[429] ,\mcal_DQIn_r_reg_n_0_[428] ,\mcal_DQIn_r_reg_n_0_[427] ,\mcal_DQIn_r_reg_n_0_[426] ,\mcal_DQIn_r_reg_n_0_[425] ,\mcal_DQIn_r_reg_n_0_[424] ,\mcal_DQIn_r_reg_n_0_[423] ,\mcal_DQIn_r_reg_n_0_[422] ,\mcal_DQIn_r_reg_n_0_[421] ,\mcal_DQIn_r_reg_n_0_[420] ,\mcal_DQIn_r_reg_n_0_[419] ,\mcal_DQIn_r_reg_n_0_[418] ,\mcal_DQIn_r_reg_n_0_[417] ,\mcal_DQIn_r_reg_n_0_[416] ,\mcal_DQIn_r_reg_n_0_[415] ,\mcal_DQIn_r_reg_n_0_[414] ,\mcal_DQIn_r_reg_n_0_[413] ,\mcal_DQIn_r_reg_n_0_[412] ,\mcal_DQIn_r_reg_n_0_[411] ,\mcal_DQIn_r_reg_n_0_[410] ,\mcal_DQIn_r_reg_n_0_[409] ,\mcal_DQIn_r_reg_n_0_[408] ,\mcal_DQIn_r_reg_n_0_[407] ,\mcal_DQIn_r_reg_n_0_[406] ,\mcal_DQIn_r_reg_n_0_[405] ,\mcal_DQIn_r_reg_n_0_[404] ,\mcal_DQIn_r_reg_n_0_[403] ,\mcal_DQIn_r_reg_n_0_[402] ,\mcal_DQIn_r_reg_n_0_[401] ,\mcal_DQIn_r_reg_n_0_[400] ,\mcal_DQIn_r_reg_n_0_[399] ,\mcal_DQIn_r_reg_n_0_[398] ,\mcal_DQIn_r_reg_n_0_[397] ,\mcal_DQIn_r_reg_n_0_[396] ,\mcal_DQIn_r_reg_n_0_[395] ,\mcal_DQIn_r_reg_n_0_[394] ,\mcal_DQIn_r_reg_n_0_[393] ,\mcal_DQIn_r_reg_n_0_[392] ,\mcal_DQIn_r_reg_n_0_[391] ,\mcal_DQIn_r_reg_n_0_[390] ,\mcal_DQIn_r_reg_n_0_[389] ,\mcal_DQIn_r_reg_n_0_[388] ,\mcal_DQIn_r_reg_n_0_[387] ,\mcal_DQIn_r_reg_n_0_[386] ,\mcal_DQIn_r_reg_n_0_[385] ,\mcal_DQIn_r_reg_n_0_[384] ,\mcal_DQIn_r_reg_n_0_[383] ,\mcal_DQIn_r_reg_n_0_[382] ,\mcal_DQIn_r_reg_n_0_[381] ,\mcal_DQIn_r_reg_n_0_[380] ,\mcal_DQIn_r_reg_n_0_[379] ,\mcal_DQIn_r_reg_n_0_[378] ,\mcal_DQIn_r_reg_n_0_[377] ,\mcal_DQIn_r_reg_n_0_[376] ,\mcal_DQIn_r_reg_n_0_[375] ,\mcal_DQIn_r_reg_n_0_[374] ,\mcal_DQIn_r_reg_n_0_[373] ,\mcal_DQIn_r_reg_n_0_[372] ,\mcal_DQIn_r_reg_n_0_[371] ,\mcal_DQIn_r_reg_n_0_[370] ,\mcal_DQIn_r_reg_n_0_[369] ,\mcal_DQIn_r_reg_n_0_[368] ,\mcal_DQIn_r_reg_n_0_[367] ,\mcal_DQIn_r_reg_n_0_[366] ,\mcal_DQIn_r_reg_n_0_[365] ,\mcal_DQIn_r_reg_n_0_[364] ,\mcal_DQIn_r_reg_n_0_[363] ,\mcal_DQIn_r_reg_n_0_[362] ,\mcal_DQIn_r_reg_n_0_[361] ,\mcal_DQIn_r_reg_n_0_[360] ,\mcal_DQIn_r_reg_n_0_[359] ,\mcal_DQIn_r_reg_n_0_[358] ,\mcal_DQIn_r_reg_n_0_[357] ,\mcal_DQIn_r_reg_n_0_[356] ,\mcal_DQIn_r_reg_n_0_[355] ,\mcal_DQIn_r_reg_n_0_[354] ,\mcal_DQIn_r_reg_n_0_[353] ,\mcal_DQIn_r_reg_n_0_[352] ,\mcal_DQIn_r_reg_n_0_[351] ,\mcal_DQIn_r_reg_n_0_[350] ,\mcal_DQIn_r_reg_n_0_[349] ,\mcal_DQIn_r_reg_n_0_[348] ,\mcal_DQIn_r_reg_n_0_[347] ,\mcal_DQIn_r_reg_n_0_[346] ,\mcal_DQIn_r_reg_n_0_[345] ,\mcal_DQIn_r_reg_n_0_[344] ,\mcal_DQIn_r_reg_n_0_[343] ,\mcal_DQIn_r_reg_n_0_[342] ,\mcal_DQIn_r_reg_n_0_[341] ,\mcal_DQIn_r_reg_n_0_[340] ,\mcal_DQIn_r_reg_n_0_[339] ,\mcal_DQIn_r_reg_n_0_[338] ,\mcal_DQIn_r_reg_n_0_[337] ,\mcal_DQIn_r_reg_n_0_[336] ,\mcal_DQIn_r_reg_n_0_[335] ,\mcal_DQIn_r_reg_n_0_[334] ,\mcal_DQIn_r_reg_n_0_[333] ,\mcal_DQIn_r_reg_n_0_[332] ,\mcal_DQIn_r_reg_n_0_[331] ,\mcal_DQIn_r_reg_n_0_[330] ,\mcal_DQIn_r_reg_n_0_[329] ,\mcal_DQIn_r_reg_n_0_[328] ,\mcal_DQIn_r_reg_n_0_[327] ,\mcal_DQIn_r_reg_n_0_[326] ,\mcal_DQIn_r_reg_n_0_[325] ,\mcal_DQIn_r_reg_n_0_[324] ,\mcal_DQIn_r_reg_n_0_[323] ,\mcal_DQIn_r_reg_n_0_[322] ,\mcal_DQIn_r_reg_n_0_[321] ,\mcal_DQIn_r_reg_n_0_[320] ,\mcal_DQIn_r_reg_n_0_[319] ,\mcal_DQIn_r_reg_n_0_[318] ,\mcal_DQIn_r_reg_n_0_[317] ,\mcal_DQIn_r_reg_n_0_[316] ,\mcal_DQIn_r_reg_n_0_[315] ,\mcal_DQIn_r_reg_n_0_[314] ,\mcal_DQIn_r_reg_n_0_[313] ,\mcal_DQIn_r_reg_n_0_[312] ,\mcal_DQIn_r_reg_n_0_[311] ,\mcal_DQIn_r_reg_n_0_[310] ,\mcal_DQIn_r_reg_n_0_[309] ,\mcal_DQIn_r_reg_n_0_[308] ,\mcal_DQIn_r_reg_n_0_[307] ,\mcal_DQIn_r_reg_n_0_[306] ,\mcal_DQIn_r_reg_n_0_[305] ,\mcal_DQIn_r_reg_n_0_[304] ,\mcal_DQIn_r_reg_n_0_[303] ,\mcal_DQIn_r_reg_n_0_[302] ,\mcal_DQIn_r_reg_n_0_[301] ,\mcal_DQIn_r_reg_n_0_[300] ,\mcal_DQIn_r_reg_n_0_[299] ,\mcal_DQIn_r_reg_n_0_[298] ,\mcal_DQIn_r_reg_n_0_[297] ,\mcal_DQIn_r_reg_n_0_[296] ,\mcal_DQIn_r_reg_n_0_[295] ,\mcal_DQIn_r_reg_n_0_[294] ,\mcal_DQIn_r_reg_n_0_[293] ,\mcal_DQIn_r_reg_n_0_[292] ,\mcal_DQIn_r_reg_n_0_[291] ,\mcal_DQIn_r_reg_n_0_[290] ,\mcal_DQIn_r_reg_n_0_[289] ,\mcal_DQIn_r_reg_n_0_[288] ,\mcal_DQIn_r_reg_n_0_[287] ,\mcal_DQIn_r_reg_n_0_[286] ,\mcal_DQIn_r_reg_n_0_[285] ,\mcal_DQIn_r_reg_n_0_[284] ,\mcal_DQIn_r_reg_n_0_[283] ,\mcal_DQIn_r_reg_n_0_[282] ,\mcal_DQIn_r_reg_n_0_[281] ,\mcal_DQIn_r_reg_n_0_[280] ,\mcal_DQIn_r_reg_n_0_[279] ,\mcal_DQIn_r_reg_n_0_[278] ,\mcal_DQIn_r_reg_n_0_[277] ,\mcal_DQIn_r_reg_n_0_[276] ,\mcal_DQIn_r_reg_n_0_[275] ,\mcal_DQIn_r_reg_n_0_[274] ,\mcal_DQIn_r_reg_n_0_[273] ,\mcal_DQIn_r_reg_n_0_[272] ,\mcal_DQIn_r_reg_n_0_[271] ,\mcal_DQIn_r_reg_n_0_[270] ,\mcal_DQIn_r_reg_n_0_[269] ,\mcal_DQIn_r_reg_n_0_[268] ,\mcal_DQIn_r_reg_n_0_[267] ,\mcal_DQIn_r_reg_n_0_[266] ,\mcal_DQIn_r_reg_n_0_[265] ,\mcal_DQIn_r_reg_n_0_[264] ,\mcal_DQIn_r_reg_n_0_[263] ,\mcal_DQIn_r_reg_n_0_[262] ,\mcal_DQIn_r_reg_n_0_[261] ,\mcal_DQIn_r_reg_n_0_[260] ,\mcal_DQIn_r_reg_n_0_[259] ,\mcal_DQIn_r_reg_n_0_[258] ,\mcal_DQIn_r_reg_n_0_[257] ,\mcal_DQIn_r_reg_n_0_[256] ,\mcal_DQIn_r_reg_n_0_[255] ,\mcal_DQIn_r_reg_n_0_[254] ,\mcal_DQIn_r_reg_n_0_[253] ,\mcal_DQIn_r_reg_n_0_[252] ,\mcal_DQIn_r_reg_n_0_[251] ,\mcal_DQIn_r_reg_n_0_[250] ,\mcal_DQIn_r_reg_n_0_[249] ,\mcal_DQIn_r_reg_n_0_[248] ,\mcal_DQIn_r_reg_n_0_[247] ,\mcal_DQIn_r_reg_n_0_[246] ,\mcal_DQIn_r_reg_n_0_[245] ,\mcal_DQIn_r_reg_n_0_[244] ,\mcal_DQIn_r_reg_n_0_[243] ,\mcal_DQIn_r_reg_n_0_[242] ,\mcal_DQIn_r_reg_n_0_[241] ,\mcal_DQIn_r_reg_n_0_[240] ,\mcal_DQIn_r_reg_n_0_[239] ,\mcal_DQIn_r_reg_n_0_[238] ,\mcal_DQIn_r_reg_n_0_[237] ,\mcal_DQIn_r_reg_n_0_[236] ,\mcal_DQIn_r_reg_n_0_[235] ,\mcal_DQIn_r_reg_n_0_[234] ,\mcal_DQIn_r_reg_n_0_[233] ,\mcal_DQIn_r_reg_n_0_[232] ,\mcal_DQIn_r_reg_n_0_[231] ,\mcal_DQIn_r_reg_n_0_[230] ,\mcal_DQIn_r_reg_n_0_[229] ,\mcal_DQIn_r_reg_n_0_[228] ,\mcal_DQIn_r_reg_n_0_[227] ,\mcal_DQIn_r_reg_n_0_[226] ,\mcal_DQIn_r_reg_n_0_[225] ,\mcal_DQIn_r_reg_n_0_[224] ,\mcal_DQIn_r_reg_n_0_[223] ,\mcal_DQIn_r_reg_n_0_[222] ,\mcal_DQIn_r_reg_n_0_[221] ,\mcal_DQIn_r_reg_n_0_[220] ,\mcal_DQIn_r_reg_n_0_[219] ,\mcal_DQIn_r_reg_n_0_[218] ,\mcal_DQIn_r_reg_n_0_[217] ,\mcal_DQIn_r_reg_n_0_[216] ,\mcal_DQIn_r_reg_n_0_[215] ,\mcal_DQIn_r_reg_n_0_[214] ,\mcal_DQIn_r_reg_n_0_[213] ,\mcal_DQIn_r_reg_n_0_[212] ,\mcal_DQIn_r_reg_n_0_[211] ,\mcal_DQIn_r_reg_n_0_[210] ,\mcal_DQIn_r_reg_n_0_[209] ,\mcal_DQIn_r_reg_n_0_[208] ,\mcal_DQIn_r_reg_n_0_[207] ,\mcal_DQIn_r_reg_n_0_[206] ,\mcal_DQIn_r_reg_n_0_[205] ,\mcal_DQIn_r_reg_n_0_[204] ,\mcal_DQIn_r_reg_n_0_[203] ,\mcal_DQIn_r_reg_n_0_[202] ,\mcal_DQIn_r_reg_n_0_[201] ,\mcal_DQIn_r_reg_n_0_[200] ,\mcal_DQIn_r_reg_n_0_[199] ,\mcal_DQIn_r_reg_n_0_[198] ,\mcal_DQIn_r_reg_n_0_[197] ,\mcal_DQIn_r_reg_n_0_[196] ,\mcal_DQIn_r_reg_n_0_[195] ,\mcal_DQIn_r_reg_n_0_[194] ,\mcal_DQIn_r_reg_n_0_[193] ,\mcal_DQIn_r_reg_n_0_[192] ,\mcal_DQIn_r_reg_n_0_[191] ,\mcal_DQIn_r_reg_n_0_[190] ,\mcal_DQIn_r_reg_n_0_[189] ,\mcal_DQIn_r_reg_n_0_[188] ,\mcal_DQIn_r_reg_n_0_[187] ,\mcal_DQIn_r_reg_n_0_[186] ,\mcal_DQIn_r_reg_n_0_[185] ,\mcal_DQIn_r_reg_n_0_[184] ,\mcal_DQIn_r_reg_n_0_[183] ,\mcal_DQIn_r_reg_n_0_[182] ,\mcal_DQIn_r_reg_n_0_[181] ,\mcal_DQIn_r_reg_n_0_[180] ,\mcal_DQIn_r_reg_n_0_[179] ,\mcal_DQIn_r_reg_n_0_[178] ,\mcal_DQIn_r_reg_n_0_[177] ,\mcal_DQIn_r_reg_n_0_[176] ,\mcal_DQIn_r_reg_n_0_[175] ,\mcal_DQIn_r_reg_n_0_[174] ,\mcal_DQIn_r_reg_n_0_[173] ,\mcal_DQIn_r_reg_n_0_[172] ,\mcal_DQIn_r_reg_n_0_[171] ,\mcal_DQIn_r_reg_n_0_[170] ,\mcal_DQIn_r_reg_n_0_[169] ,\mcal_DQIn_r_reg_n_0_[168] ,\mcal_DQIn_r_reg_n_0_[167] ,\mcal_DQIn_r_reg_n_0_[166] ,\mcal_DQIn_r_reg_n_0_[165] ,\mcal_DQIn_r_reg_n_0_[164] ,\mcal_DQIn_r_reg_n_0_[163] ,\mcal_DQIn_r_reg_n_0_[162] ,\mcal_DQIn_r_reg_n_0_[161] ,\mcal_DQIn_r_reg_n_0_[160] ,\mcal_DQIn_r_reg_n_0_[159] ,\mcal_DQIn_r_reg_n_0_[158] ,\mcal_DQIn_r_reg_n_0_[157] ,\mcal_DQIn_r_reg_n_0_[156] ,\mcal_DQIn_r_reg_n_0_[155] ,\mcal_DQIn_r_reg_n_0_[154] ,\mcal_DQIn_r_reg_n_0_[153] ,\mcal_DQIn_r_reg_n_0_[152] ,\mcal_DQIn_r_reg_n_0_[151] ,\mcal_DQIn_r_reg_n_0_[150] ,\mcal_DQIn_r_reg_n_0_[149] ,\mcal_DQIn_r_reg_n_0_[148] ,\mcal_DQIn_r_reg_n_0_[147] ,\mcal_DQIn_r_reg_n_0_[146] ,\mcal_DQIn_r_reg_n_0_[145] ,\mcal_DQIn_r_reg_n_0_[144] ,\mcal_DQIn_r_reg_n_0_[143] ,\mcal_DQIn_r_reg_n_0_[142] ,\mcal_DQIn_r_reg_n_0_[141] ,\mcal_DQIn_r_reg_n_0_[140] ,\mcal_DQIn_r_reg_n_0_[139] ,\mcal_DQIn_r_reg_n_0_[138] ,\mcal_DQIn_r_reg_n_0_[137] ,\mcal_DQIn_r_reg_n_0_[136] ,\mcal_DQIn_r_reg_n_0_[135] ,\mcal_DQIn_r_reg_n_0_[134] ,\mcal_DQIn_r_reg_n_0_[133] ,\mcal_DQIn_r_reg_n_0_[132] ,\mcal_DQIn_r_reg_n_0_[131] ,\mcal_DQIn_r_reg_n_0_[130] ,\mcal_DQIn_r_reg_n_0_[129] ,\mcal_DQIn_r_reg_n_0_[128] ,\mcal_DQIn_r_reg_n_0_[127] ,\mcal_DQIn_r_reg_n_0_[126] ,\mcal_DQIn_r_reg_n_0_[125] ,\mcal_DQIn_r_reg_n_0_[124] ,\mcal_DQIn_r_reg_n_0_[123] ,\mcal_DQIn_r_reg_n_0_[122] ,\mcal_DQIn_r_reg_n_0_[121] ,\mcal_DQIn_r_reg_n_0_[120] ,\mcal_DQIn_r_reg_n_0_[119] ,\mcal_DQIn_r_reg_n_0_[118] ,\mcal_DQIn_r_reg_n_0_[117] ,\mcal_DQIn_r_reg_n_0_[116] ,\mcal_DQIn_r_reg_n_0_[115] ,\mcal_DQIn_r_reg_n_0_[114] ,\mcal_DQIn_r_reg_n_0_[113] ,\mcal_DQIn_r_reg_n_0_[112] ,\mcal_DQIn_r_reg_n_0_[111] ,\mcal_DQIn_r_reg_n_0_[110] ,\mcal_DQIn_r_reg_n_0_[109] ,\mcal_DQIn_r_reg_n_0_[108] ,\mcal_DQIn_r_reg_n_0_[107] ,\mcal_DQIn_r_reg_n_0_[106] ,\mcal_DQIn_r_reg_n_0_[105] ,\mcal_DQIn_r_reg_n_0_[104] ,\mcal_DQIn_r_reg_n_0_[103] ,\mcal_DQIn_r_reg_n_0_[102] ,\mcal_DQIn_r_reg_n_0_[101] ,\mcal_DQIn_r_reg_n_0_[100] ,\mcal_DQIn_r_reg_n_0_[99] ,\mcal_DQIn_r_reg_n_0_[98] ,\mcal_DQIn_r_reg_n_0_[97] ,\mcal_DQIn_r_reg_n_0_[96] ,\mcal_DQIn_r_reg_n_0_[95] ,\mcal_DQIn_r_reg_n_0_[94] ,\mcal_DQIn_r_reg_n_0_[93] ,\mcal_DQIn_r_reg_n_0_[92] ,\mcal_DQIn_r_reg_n_0_[91] ,\mcal_DQIn_r_reg_n_0_[90] ,\mcal_DQIn_r_reg_n_0_[89] ,\mcal_DQIn_r_reg_n_0_[88] ,\mcal_DQIn_r_reg_n_0_[87] ,\mcal_DQIn_r_reg_n_0_[86] ,\mcal_DQIn_r_reg_n_0_[85] ,\mcal_DQIn_r_reg_n_0_[84] ,\mcal_DQIn_r_reg_n_0_[83] ,\mcal_DQIn_r_reg_n_0_[82] ,\mcal_DQIn_r_reg_n_0_[81] ,\mcal_DQIn_r_reg_n_0_[80] ,\mcal_DQIn_r_reg_n_0_[79] ,\mcal_DQIn_r_reg_n_0_[78] ,\mcal_DQIn_r_reg_n_0_[77] ,\mcal_DQIn_r_reg_n_0_[76] ,\mcal_DQIn_r_reg_n_0_[75] ,\mcal_DQIn_r_reg_n_0_[74] ,\mcal_DQIn_r_reg_n_0_[73] ,\mcal_DQIn_r_reg_n_0_[72] ,\mcal_DQIn_r_reg_n_0_[71] ,\mcal_DQIn_r_reg_n_0_[70] ,\mcal_DQIn_r_reg_n_0_[69] ,\mcal_DQIn_r_reg_n_0_[68] ,\mcal_DQIn_r_reg_n_0_[67] ,\mcal_DQIn_r_reg_n_0_[66] ,\mcal_DQIn_r_reg_n_0_[65] ,\mcal_DQIn_r_reg_n_0_[64] ,\mcal_DQIn_r_reg_n_0_[63] ,\mcal_DQIn_r_reg_n_0_[62] ,\mcal_DQIn_r_reg_n_0_[61] ,\mcal_DQIn_r_reg_n_0_[60] ,\mcal_DQIn_r_reg_n_0_[59] ,\mcal_DQIn_r_reg_n_0_[58] ,\mcal_DQIn_r_reg_n_0_[57] ,\mcal_DQIn_r_reg_n_0_[56] ,\mcal_DQIn_r_reg_n_0_[55] ,\mcal_DQIn_r_reg_n_0_[54] ,\mcal_DQIn_r_reg_n_0_[53] ,\mcal_DQIn_r_reg_n_0_[52] ,\mcal_DQIn_r_reg_n_0_[51] ,\mcal_DQIn_r_reg_n_0_[50] ,\mcal_DQIn_r_reg_n_0_[49] ,\mcal_DQIn_r_reg_n_0_[48] ,\mcal_DQIn_r_reg_n_0_[47] ,\mcal_DQIn_r_reg_n_0_[46] ,\mcal_DQIn_r_reg_n_0_[45] ,\mcal_DQIn_r_reg_n_0_[44] ,\mcal_DQIn_r_reg_n_0_[43] ,\mcal_DQIn_r_reg_n_0_[42] ,\mcal_DQIn_r_reg_n_0_[41] ,\mcal_DQIn_r_reg_n_0_[40] ,p_0_in,\mcal_DQIn_r_reg_n_0_[31] ,\mcal_DQIn_r_reg_n_0_[30] ,\mcal_DQIn_r_reg_n_0_[29] ,\mcal_DQIn_r_reg_n_0_[28] ,\mcal_DQIn_r_reg_n_0_[27] ,\mcal_DQIn_r_reg_n_0_[26] ,\mcal_DQIn_r_reg_n_0_[25] ,\mcal_DQIn_r_reg_n_0_[24] ,\mcal_DQIn_r_reg_n_0_[23] ,\mcal_DQIn_r_reg_n_0_[22] ,\mcal_DQIn_r_reg_n_0_[21] ,\mcal_DQIn_r_reg_n_0_[20] ,\mcal_DQIn_r_reg_n_0_[19] ,\mcal_DQIn_r_reg_n_0_[18] ,\mcal_DQIn_r_reg_n_0_[17] ,\mcal_DQIn_r_reg_n_0_[16] ,\mcal_DQIn_r_reg_n_0_[15] ,\mcal_DQIn_r_reg_n_0_[14] ,\mcal_DQIn_r_reg_n_0_[13] ,\mcal_DQIn_r_reg_n_0_[12] ,\mcal_DQIn_r_reg_n_0_[11] ,\mcal_DQIn_r_reg_n_0_[10] ,\mcal_DQIn_r_reg_n_0_[9] ,\mcal_DQIn_r_reg_n_0_[8] ,\mcal_DQIn_r_reg_n_0_[7] ,\mcal_DQIn_r_reg_n_0_[6] ,\mcal_DQIn_r_reg_n_0_[5] ,\mcal_DQIn_r_reg_n_0_[4] ,\mcal_DQIn_r_reg_n_0_[3] ,\mcal_DQIn_r_reg_n_0_[2] ,\mcal_DQIn_r_reg_n_0_[1] ,\mcal_DQIn_r_reg_n_0_[0] }),
        .\cplx_error_accum_reg[14]_0 (\cplx_error_accum_reg[14] ),
        .\cplx_error_accum_reg[15]_0 (\cplx_error_accum_reg[15] ),
        .\cplx_error_accum_reg[19]_0 (\cplx_error_accum_reg[19] ),
        .\cplx_error_accum_reg[44]_0 (\cplx_error_accum_reg[44] ),
        .\cplx_error_accum_reg[63]_0 (\cplx_error_accum_reg[63] ),
        .cplx_issue_cas_rd_reg_0(u_ddr_cal_cplx_n_136),
        .cplx_issue_cas_wr_reg_0(u_ddr_cal_cplx_n_134),
        .cplx_status(cplx_status),
        .extended_write_mode(extended_write_mode),
        .gt_data_ready_flag(gt_data_ready_flag),
        .gt_data_ready_flag_reg(gt_data_ready_flag_reg_0),
        .\init_cal_BA_reg[15] (\init_cal_BA_reg[15] ),
        .\init_cal_BA_reg[7] (\init_cal_BA_reg[7] ),
        .init_cal_BG(init_cal_BG),
        .\init_cal_BG_reg[7] (\init_cal_BG_reg[7] ),
        .init_cal_CS_n(init_cal_CS_n),
        .io_address({io_address[15],io_address[12],io_address[9:7],io_address[0]}),
        .mc_ADR(mc_ADR),
        .mc_BA(mc_BA),
        .mc_BG(mc_BG),
        .mc_CS_n(mc_CS_n),
        .mc_CS_n7(mc_CS_n7),
        .\mcal_ACT_n_dly_reg[0][7] (cal_ACT_n_pre),
        .\mcal_ADR_dly_reg[0][128] (\mcal_ADR_dly_reg[0][128] ),
        .\mcal_ADR_dly_reg[0][134] (\mcal_ADR_dly_reg[0][134] ),
        .\mcal_ADR_dly_reg[0][135] (cal_RAS_pre),
        .\mcal_ADR_dly_reg[0][135]_0 (\mcal_ADR_dly_reg[0][135] ),
        .\mcal_ADR_dly_reg[0][87] (\mcal_ADR_dly_reg[0][87] ),
        .\mcal_BA_dly_reg[0][15] (\mcal_BA_dly_reg[0][15] ),
        .\mcal_BA_dly_reg[0][8] (\mcal_BA_dly_reg[0][8] ),
        .\mcal_BG_dly[0][7]_i_2_0 ({\cal_ADR_A_reg[30]_0 [10],\cal_ADR_A_reg_n_0_[25] ,\cal_ADR_A_reg_n_0_[24] ,\cal_ADR_A_reg_n_0_[13] ,\cal_ADR_A_reg_n_0_[12] ,\cal_ADR_A_reg_n_0_[11] ,\cal_ADR_A_reg_n_0_[10] ,\cal_ADR_A_reg_n_0_[9] ,\cal_ADR_A_reg[30]_0 [7:0],\cal_ADR_A_reg_n_0_[0] }),
        .\mcal_BG_dly[0][7]_i_2_1 ({\cal_ADR_B_reg[30]_0 [11],\cal_ADR_B_reg_n_0_[25] ,\cal_ADR_B_reg_n_0_[24] ,\cal_ADR_B_reg_n_0_[13] ,\cal_ADR_B_reg_n_0_[12] ,\cal_ADR_B_reg_n_0_[11] ,\cal_ADR_B_reg_n_0_[10] ,\cal_ADR_B_reg_n_0_[9] ,\cal_ADR_B_reg[30]_0 [7:0],\cal_ADR_B_reg_n_0_[0] }),
        .\mcal_CS_n_dly_reg[0][0] (\mcal_ODT_dly_reg[0][4] ),
        .\mcal_CS_n_dly_reg[0][7] ({\cal_CS_n_pre_reg_n_0_[7] ,\cal_CS_n_pre_reg_n_0_[6] ,\cal_CS_n_pre_reg_n_0_[5] ,\cal_CS_n_pre_reg_n_0_[4] ,\cal_CS_n_pre_reg_n_0_[3] ,\cal_CS_n_pre_reg_n_0_[2] ,\cal_CS_n_pre_reg_n_0_[1] ,\cal_CS_n_pre_reg_n_0_[0] }),
        .\mcal_PAR_dly_reg[0][0] (\mcal_PAR_dly_reg[0][0] ),
        .\mcal_PAR_dly_reg[0][1] (\mcal_PAR_dly_reg[0][1] ),
        .\mcal_PAR_dly_reg[0][3] (\mcal_PAR_dly_reg[0][3] ),
        .\mcal_PAR_dly_reg[0][5] (\mcal_PAR_dly_reg[0][5] ),
        .\mcal_PAR_dly_reg[0][7] (\mcal_PAR_dly_reg[0][7] ),
        .out(rst_r1),
        .p_1_in(p_1_in),
        .rdCAS_reg(cal_WE_pre),
        .rdCAS_reg_0(rdCAS_i_3_n_0),
        .rdDataEn_pi(rdDataEn_pi),
        .\rd_addr_101_reg[7] (\odt_shift_reg[0][17] ),
        .ub_ready(ub_ready),
        .winAct(winAct),
        .winAct_reg(winAct_reg),
        .wrCAS_reg(lrdimm_drive_dq_reg_n_0),
        .wrCAS_reg_0(write_vref_mode_reg_n_0),
        .wrCAS_reg_1(wrlvl_mode),
        .wrCAS_reg_2(extended_write[2]),
        .wrDataEn_pi(wrDataEn_pi));
  ddr4_0_ddr4_v2_2_17_cal_mc_odt__parameterized0 u_ddr_cal_odt
       (.Q({calCasSlot,\casSlot_reg_n_0_[0] }),
        .mc_ODT(mc_ODT),
        .\mcal_ODT_dly_reg[0][4] (\mcal_ODT_dly_reg[0][4] ),
        .\mcal_ODT_dly_reg[0][4]_0 (\mcal_ODT_dly[0][4]_i_4_n_0 ),
        .\odt_shift_reg[0][17]_0 (wrCAS_reg_0),
        .\odt_shift_reg[0][17]_1 (\odt_shift_reg[0][17] ),
        .\odt_shift_reg[0][20]_0 (rdCAS_reg_0),
        .\odt_shift_reg[0][20]_1 (\clb2phy_wrcs0_low_reg_n_0_[31] ),
        .\odt_shift_reg[0][20]_2 (\clb2phy_wrcs1_low_reg_n_0_[31] ),
        .out(rst_r1),
        .rdCAS_reg(rdCAS_reg_1),
        .rdCAS_reg_0(ub_cal_ODT[7]),
        .ub_ready(ub_ready),
        .ub_ready_reg(ub_ready_reg_0[2:1]));
  FDRE ub_initDone_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(ub_ready_reg_1),
        .D(io_write_data[0]),
        .Q(ub_initDone_reg_0),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    ub_ready_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(ub_ready_reg_1),
        .D(io_write_data[1]),
        .Q(ub_ready),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL0[42]_i_3 
       (.I0(\uppCL0_reg[45]_0 [12]),
        .I1(\uppCL0_reg[45]_0 [8]),
        .I2(io_address[2]),
        .I3(\uppCL0_reg[45]_0 [4]),
        .I4(io_address[1]),
        .I5(\uppCL0_reg[45]_0 [0]),
        .O(\uppCL0[42]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL0[42]_i_4 
       (.I0(\uppCL0_reg[45]_0 [28]),
        .I1(\uppCL0_reg[45]_0 [24]),
        .I2(io_address[2]),
        .I3(\uppCL0_reg[45]_0 [20]),
        .I4(io_address[1]),
        .I5(\uppCL0_reg[45]_0 [16]),
        .O(\uppCL0[42]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL0[43]_i_3 
       (.I0(\uppCL0_reg[45]_0 [13]),
        .I1(\uppCL0_reg[45]_0 [9]),
        .I2(io_address[2]),
        .I3(\uppCL0_reg[45]_0 [5]),
        .I4(io_address[1]),
        .I5(\uppCL0_reg[45]_0 [1]),
        .O(\uppCL0[43]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL0[43]_i_4 
       (.I0(\uppCL0_reg[45]_0 [29]),
        .I1(\uppCL0_reg[45]_0 [25]),
        .I2(io_address[2]),
        .I3(\uppCL0_reg[45]_0 [21]),
        .I4(io_address[1]),
        .I5(\uppCL0_reg[45]_0 [17]),
        .O(\uppCL0[43]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL0[44]_i_3 
       (.I0(\uppCL0_reg[45]_0 [14]),
        .I1(\uppCL0_reg[45]_0 [10]),
        .I2(io_address[2]),
        .I3(\uppCL0_reg[45]_0 [6]),
        .I4(io_address[1]),
        .I5(\uppCL0_reg[45]_0 [2]),
        .O(\uppCL0[44]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL0[44]_i_4 
       (.I0(\uppCL0_reg[45]_0 [30]),
        .I1(\uppCL0_reg[45]_0 [26]),
        .I2(io_address[2]),
        .I3(\uppCL0_reg[45]_0 [22]),
        .I4(io_address[1]),
        .I5(\uppCL0_reg[45]_0 [18]),
        .O(\uppCL0[44]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL0[45]_i_3 
       (.I0(\uppCL0_reg[45]_0 [15]),
        .I1(\uppCL0_reg[45]_0 [11]),
        .I2(io_address[2]),
        .I3(\uppCL0_reg[45]_0 [7]),
        .I4(io_address[1]),
        .I5(\uppCL0_reg[45]_0 [3]),
        .O(\uppCL0[45]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL0[45]_i_4 
       (.I0(\uppCL0_reg[45]_0 [31]),
        .I1(\uppCL0_reg[45]_0 [27]),
        .I2(io_address[2]),
        .I3(\uppCL0_reg[45]_0 [23]),
        .I4(io_address[1]),
        .I5(\uppCL0_reg[45]_0 [19]),
        .O(\uppCL0[45]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL0[46]_i_3 
       (.I0(\uppCL0_reg_n_0_[22] ),
        .I1(\uppCL0_reg_n_0_[16] ),
        .I2(io_address[2]),
        .I3(\uppCL0_reg_n_0_[10] ),
        .I4(io_address[1]),
        .I5(\uppCL0_reg_n_0_[4] ),
        .O(\uppCL0[46]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL0[46]_i_4 
       (.I0(\uppCL0_reg_n_0_[46] ),
        .I1(\uppCL0_reg_n_0_[40] ),
        .I2(io_address[2]),
        .I3(\uppCL0_reg_n_0_[34] ),
        .I4(io_address[1]),
        .I5(\uppCL0_reg_n_0_[28] ),
        .O(\uppCL0[46]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL0[47]_i_3 
       (.I0(\uppCL0_reg_n_0_[23] ),
        .I1(\uppCL0_reg_n_0_[17] ),
        .I2(io_address[2]),
        .I3(\uppCL0_reg_n_0_[11] ),
        .I4(io_address[1]),
        .I5(\uppCL0_reg_n_0_[5] ),
        .O(\uppCL0[47]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL0[47]_i_4 
       (.I0(\uppCL0_reg_n_0_[47] ),
        .I1(\uppCL0_reg_n_0_[41] ),
        .I2(io_address[2]),
        .I3(\uppCL0_reg_n_0_[35] ),
        .I4(io_address[1]),
        .I5(\uppCL0_reg_n_0_[29] ),
        .O(\uppCL0[47]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL0_reg[47]_0 [2]),
        .Q(\uppCL0_reg[45]_0 [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL0_reg[47]_0 [8]),
        .Q(\uppCL0_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL0_reg[47]_0 [9]),
        .Q(\uppCL0_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL0_reg[47]_0 [2]),
        .Q(\uppCL0_reg[45]_0 [8]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL0_reg[47]_0 [3]),
        .Q(\uppCL0_reg[45]_0 [9]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL0_reg[47]_0 [4]),
        .Q(\uppCL0_reg[45]_0 [10]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL0_reg[47]_0 [5]),
        .Q(\uppCL0_reg[45]_0 [11]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL0_reg[47]_0 [6]),
        .Q(\uppCL0_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL0_reg[47]_0 [7]),
        .Q(\uppCL0_reg_n_0_[17] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL0_reg[47]_0 [4]),
        .Q(\uppCL0_reg[45]_0 [12]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL0_reg[47]_0 [5]),
        .Q(\uppCL0_reg[45]_0 [13]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL0_reg[47]_0 [3]),
        .Q(\uppCL0_reg[45]_0 [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL0_reg[47]_0 [6]),
        .Q(\uppCL0_reg[45]_0 [14]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL0_reg[47]_0 [7]),
        .Q(\uppCL0_reg[45]_0 [15]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL0_reg[47]_0 [8]),
        .Q(\uppCL0_reg_n_0_[22] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL0_reg[47]_0 [9]),
        .Q(\uppCL0_reg_n_0_[23] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL0_reg[47]_0 [2]),
        .Q(\uppCL0_reg[45]_0 [16]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL0_reg[47]_0 [3]),
        .Q(\uppCL0_reg[45]_0 [17]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL0_reg[47]_0 [4]),
        .Q(\uppCL0_reg[45]_0 [18]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL0_reg[47]_0 [5]),
        .Q(\uppCL0_reg[45]_0 [19]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL0_reg[47]_0 [6]),
        .Q(\uppCL0_reg_n_0_[28] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL0_reg[47]_0 [7]),
        .Q(\uppCL0_reg_n_0_[29] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL0_reg[47]_0 [4]),
        .Q(\uppCL0_reg[45]_0 [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL0_reg[47]_0 [4]),
        .Q(\uppCL0_reg[45]_0 [20]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL0_reg[47]_0 [5]),
        .Q(\uppCL0_reg[45]_0 [21]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL0_reg[47]_0 [0]),
        .Q(\uppCL0_reg[45]_0 [22]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL0_reg[47]_0 [1]),
        .Q(\uppCL0_reg[45]_0 [23]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL0_reg[47]_0 [8]),
        .Q(\uppCL0_reg_n_0_[34] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL0_reg[47]_0 [9]),
        .Q(\uppCL0_reg_n_0_[35] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL0_reg[47]_0 [2]),
        .Q(\uppCL0_reg[45]_0 [24]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL0_reg[47]_0 [3]),
        .Q(\uppCL0_reg[45]_0 [25]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL0_reg[47]_0 [4]),
        .Q(\uppCL0_reg[45]_0 [26]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL0_reg[47]_0 [5]),
        .Q(\uppCL0_reg[45]_0 [27]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL0_reg[47]_0 [5]),
        .Q(\uppCL0_reg[45]_0 [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL0_reg[47]_0 [6]),
        .Q(\uppCL0_reg_n_0_[40] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL0_reg[47]_0 [7]),
        .Q(\uppCL0_reg_n_0_[41] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL0_reg[47]_0 [4]),
        .Q(\uppCL0_reg[45]_0 [28]),
        .R(rst_r1));
  MUXF7 \uppCL0_reg[42]_i_2 
       (.I0(\uppCL0[42]_i_3_n_0 ),
        .I1(\uppCL0[42]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_26 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL0_reg[47]_0 [5]),
        .Q(\uppCL0_reg[45]_0 [29]),
        .R(rst_r1));
  MUXF7 \uppCL0_reg[43]_i_2 
       (.I0(\uppCL0[43]_i_3_n_0 ),
        .I1(\uppCL0[43]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_24 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL0_reg[47]_0 [6]),
        .Q(\uppCL0_reg[45]_0 [30]),
        .R(rst_r1));
  MUXF7 \uppCL0_reg[44]_i_2 
       (.I0(\uppCL0[44]_i_3_n_0 ),
        .I1(\uppCL0[44]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_25 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL0_reg[47]_0 [7]),
        .Q(\uppCL0_reg[45]_0 [31]),
        .R(rst_r1));
  MUXF7 \uppCL0_reg[45]_i_2 
       (.I0(\uppCL0[45]_i_3_n_0 ),
        .I1(\uppCL0[45]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_23 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL0_reg[47]_0 [8]),
        .Q(\uppCL0_reg_n_0_[46] ),
        .R(rst_r1));
  MUXF7 \uppCL0_reg[46]_i_2 
       (.I0(\uppCL0[46]_i_3_n_0 ),
        .I1(\uppCL0[46]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_27 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL0_reg[47]_0 [9]),
        .Q(\uppCL0_reg_n_0_[47] ),
        .R(rst_r1));
  MUXF7 \uppCL0_reg[47]_i_2 
       (.I0(\uppCL0[47]_i_3_n_0 ),
        .I1(\uppCL0[47]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_22 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL0_reg[47]_0 [6]),
        .Q(\uppCL0_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL0_reg[47]_0 [7]),
        .Q(\uppCL0_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL0_reg[47]_0 [4]),
        .Q(\uppCL0_reg[45]_0 [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL0_reg[47]_0 [5]),
        .Q(\uppCL0_reg[45]_0 [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL0_reg[47]_0 [6]),
        .Q(\uppCL0_reg[45]_0 [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL0_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL0_reg[47]_0 [7]),
        .Q(\uppCL0_reg[45]_0 [7]),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL1[42]_i_3 
       (.I0(\uppCL1_reg[45]_0 [12]),
        .I1(\uppCL1_reg[45]_0 [8]),
        .I2(io_address[2]),
        .I3(\uppCL1_reg[45]_0 [4]),
        .I4(io_address[1]),
        .I5(\uppCL1_reg[45]_0 [0]),
        .O(\uppCL1[42]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL1[42]_i_4 
       (.I0(\uppCL1_reg[45]_0 [28]),
        .I1(\uppCL1_reg[45]_0 [24]),
        .I2(io_address[2]),
        .I3(\uppCL1_reg[45]_0 [20]),
        .I4(io_address[1]),
        .I5(\uppCL1_reg[45]_0 [16]),
        .O(\uppCL1[42]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL1[43]_i_3 
       (.I0(\uppCL1_reg[45]_0 [13]),
        .I1(\uppCL1_reg[45]_0 [9]),
        .I2(io_address[2]),
        .I3(\uppCL1_reg[45]_0 [5]),
        .I4(io_address[1]),
        .I5(\uppCL1_reg[45]_0 [1]),
        .O(\uppCL1[43]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL1[43]_i_4 
       (.I0(\uppCL1_reg[45]_0 [29]),
        .I1(\uppCL1_reg[45]_0 [25]),
        .I2(io_address[2]),
        .I3(\uppCL1_reg[45]_0 [21]),
        .I4(io_address[1]),
        .I5(\uppCL1_reg[45]_0 [17]),
        .O(\uppCL1[43]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL1[44]_i_3 
       (.I0(\uppCL1_reg[45]_0 [14]),
        .I1(\uppCL1_reg[45]_0 [10]),
        .I2(io_address[2]),
        .I3(\uppCL1_reg[45]_0 [6]),
        .I4(io_address[1]),
        .I5(\uppCL1_reg[45]_0 [2]),
        .O(\uppCL1[44]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL1[44]_i_4 
       (.I0(\uppCL1_reg[45]_0 [30]),
        .I1(\uppCL1_reg[45]_0 [26]),
        .I2(io_address[2]),
        .I3(\uppCL1_reg[45]_0 [22]),
        .I4(io_address[1]),
        .I5(\uppCL1_reg[45]_0 [18]),
        .O(\uppCL1[44]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL1[45]_i_3 
       (.I0(\uppCL1_reg[45]_0 [15]),
        .I1(\uppCL1_reg[45]_0 [11]),
        .I2(io_address[2]),
        .I3(\uppCL1_reg[45]_0 [7]),
        .I4(io_address[1]),
        .I5(\uppCL1_reg[45]_0 [3]),
        .O(\uppCL1[45]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL1[45]_i_4 
       (.I0(\uppCL1_reg[45]_0 [31]),
        .I1(\uppCL1_reg[45]_0 [27]),
        .I2(io_address[2]),
        .I3(\uppCL1_reg[45]_0 [23]),
        .I4(io_address[1]),
        .I5(\uppCL1_reg[45]_0 [19]),
        .O(\uppCL1[45]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL1[46]_i_3 
       (.I0(\uppCL1_reg_n_0_[22] ),
        .I1(\uppCL1_reg_n_0_[16] ),
        .I2(io_address[2]),
        .I3(\uppCL1_reg_n_0_[10] ),
        .I4(io_address[1]),
        .I5(\uppCL1_reg_n_0_[4] ),
        .O(\uppCL1[46]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL1[46]_i_4 
       (.I0(\uppCL1_reg_n_0_[46] ),
        .I1(\uppCL1_reg_n_0_[40] ),
        .I2(io_address[2]),
        .I3(\uppCL1_reg_n_0_[34] ),
        .I4(io_address[1]),
        .I5(\uppCL1_reg_n_0_[28] ),
        .O(\uppCL1[46]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL1[47]_i_3 
       (.I0(\uppCL1_reg_n_0_[23] ),
        .I1(\uppCL1_reg_n_0_[17] ),
        .I2(io_address[2]),
        .I3(\uppCL1_reg_n_0_[11] ),
        .I4(io_address[1]),
        .I5(\uppCL1_reg_n_0_[5] ),
        .O(\uppCL1[47]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL1[47]_i_4 
       (.I0(\uppCL1_reg_n_0_[47] ),
        .I1(\uppCL1_reg_n_0_[41] ),
        .I2(io_address[2]),
        .I3(\uppCL1_reg_n_0_[35] ),
        .I4(io_address[1]),
        .I5(\uppCL1_reg_n_0_[29] ),
        .O(\uppCL1[47]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL1_reg[47]_0 [2]),
        .Q(\uppCL1_reg[45]_0 [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL1_reg[47]_0 [8]),
        .Q(\uppCL1_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL1_reg[47]_0 [9]),
        .Q(\uppCL1_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL1_reg[47]_0 [2]),
        .Q(\uppCL1_reg[45]_0 [8]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL1_reg[47]_0 [3]),
        .Q(\uppCL1_reg[45]_0 [9]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL1_reg[47]_0 [4]),
        .Q(\uppCL1_reg[45]_0 [10]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL1_reg[47]_0 [5]),
        .Q(\uppCL1_reg[45]_0 [11]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL1_reg[47]_0 [6]),
        .Q(\uppCL1_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL1_reg[47]_0 [7]),
        .Q(\uppCL1_reg_n_0_[17] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL1_reg[47]_0 [4]),
        .Q(\uppCL1_reg[45]_0 [12]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL1_reg[47]_0 [5]),
        .Q(\uppCL1_reg[45]_0 [13]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL1_reg[47]_0 [3]),
        .Q(\uppCL1_reg[45]_0 [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL1_reg[47]_0 [6]),
        .Q(\uppCL1_reg[45]_0 [14]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL1_reg[47]_0 [7]),
        .Q(\uppCL1_reg[45]_0 [15]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL1_reg[47]_0 [8]),
        .Q(\uppCL1_reg_n_0_[22] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL1_reg[47]_0 [9]),
        .Q(\uppCL1_reg_n_0_[23] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL1_reg[47]_0 [2]),
        .Q(\uppCL1_reg[45]_0 [16]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL1_reg[47]_0 [3]),
        .Q(\uppCL1_reg[45]_0 [17]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL1_reg[47]_0 [4]),
        .Q(\uppCL1_reg[45]_0 [18]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL1_reg[47]_0 [5]),
        .Q(\uppCL1_reg[45]_0 [19]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL1_reg[47]_0 [6]),
        .Q(\uppCL1_reg_n_0_[28] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL1_reg[47]_0 [7]),
        .Q(\uppCL1_reg_n_0_[29] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL1_reg[47]_0 [4]),
        .Q(\uppCL1_reg[45]_0 [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL1_reg[47]_0 [4]),
        .Q(\uppCL1_reg[45]_0 [20]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL1_reg[47]_0 [5]),
        .Q(\uppCL1_reg[45]_0 [21]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL1_reg[47]_0 [0]),
        .Q(\uppCL1_reg[45]_0 [22]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL1_reg[47]_0 [1]),
        .Q(\uppCL1_reg[45]_0 [23]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL1_reg[47]_0 [8]),
        .Q(\uppCL1_reg_n_0_[34] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL1_reg[47]_0 [9]),
        .Q(\uppCL1_reg_n_0_[35] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL1_reg[47]_0 [2]),
        .Q(\uppCL1_reg[45]_0 [24]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL1_reg[47]_0 [3]),
        .Q(\uppCL1_reg[45]_0 [25]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL1_reg[47]_0 [4]),
        .Q(\uppCL1_reg[45]_0 [26]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL1_reg[47]_0 [5]),
        .Q(\uppCL1_reg[45]_0 [27]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL1_reg[47]_0 [5]),
        .Q(\uppCL1_reg[45]_0 [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL1_reg[47]_0 [6]),
        .Q(\uppCL1_reg_n_0_[40] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL1_reg[47]_0 [7]),
        .Q(\uppCL1_reg_n_0_[41] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL1_reg[47]_0 [4]),
        .Q(\uppCL1_reg[45]_0 [28]),
        .R(rst_r1));
  MUXF7 \uppCL1_reg[42]_i_2 
       (.I0(\uppCL1[42]_i_3_n_0 ),
        .I1(\uppCL1[42]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_32 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL1_reg[47]_0 [5]),
        .Q(\uppCL1_reg[45]_0 [29]),
        .R(rst_r1));
  MUXF7 \uppCL1_reg[43]_i_2 
       (.I0(\uppCL1[43]_i_3_n_0 ),
        .I1(\uppCL1[43]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_29 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL1_reg[47]_0 [6]),
        .Q(\uppCL1_reg[45]_0 [30]),
        .R(rst_r1));
  MUXF7 \uppCL1_reg[44]_i_2 
       (.I0(\uppCL1[44]_i_3_n_0 ),
        .I1(\uppCL1[44]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_31 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL1_reg[47]_0 [7]),
        .Q(\uppCL1_reg[45]_0 [31]),
        .R(rst_r1));
  MUXF7 \uppCL1_reg[45]_i_2 
       (.I0(\uppCL1[45]_i_3_n_0 ),
        .I1(\uppCL1[45]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_28 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL1_reg[47]_0 [8]),
        .Q(\uppCL1_reg_n_0_[46] ),
        .R(rst_r1));
  MUXF7 \uppCL1_reg[46]_i_2 
       (.I0(\uppCL1[46]_i_3_n_0 ),
        .I1(\uppCL1[46]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_33 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL1_reg[47]_0 [9]),
        .Q(\uppCL1_reg_n_0_[47] ),
        .R(rst_r1));
  MUXF7 \uppCL1_reg[47]_i_2 
       (.I0(\uppCL1[47]_i_3_n_0 ),
        .I1(\uppCL1[47]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_30 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL1_reg[47]_0 [6]),
        .Q(\uppCL1_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL1_reg[47]_0 [7]),
        .Q(\uppCL1_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL1_reg[47]_0 [4]),
        .Q(\uppCL1_reg[45]_0 [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL1_reg[47]_0 [5]),
        .Q(\uppCL1_reg[45]_0 [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL1_reg[47]_0 [6]),
        .Q(\uppCL1_reg[45]_0 [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL1_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL1_reg[47]_0 [7]),
        .Q(\uppCL1_reg[45]_0 [7]),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL2[42]_i_3 
       (.I0(\uppCL2_reg[45]_0 [12]),
        .I1(\uppCL2_reg[45]_0 [8]),
        .I2(io_address[2]),
        .I3(\uppCL2_reg[45]_0 [4]),
        .I4(io_address[1]),
        .I5(\uppCL2_reg[45]_0 [0]),
        .O(\uppCL2[42]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL2[42]_i_4 
       (.I0(\uppCL2_reg[45]_0 [28]),
        .I1(\uppCL2_reg[45]_0 [24]),
        .I2(io_address[2]),
        .I3(\uppCL2_reg[45]_0 [20]),
        .I4(io_address[1]),
        .I5(\uppCL2_reg[45]_0 [16]),
        .O(\uppCL2[42]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL2[43]_i_3 
       (.I0(\uppCL2_reg[45]_0 [13]),
        .I1(\uppCL2_reg[45]_0 [9]),
        .I2(io_address[2]),
        .I3(\uppCL2_reg[45]_0 [5]),
        .I4(io_address[1]),
        .I5(\uppCL2_reg[45]_0 [1]),
        .O(\uppCL2[43]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL2[43]_i_4 
       (.I0(\uppCL2_reg[45]_0 [29]),
        .I1(\uppCL2_reg[45]_0 [25]),
        .I2(io_address[2]),
        .I3(\uppCL2_reg[45]_0 [21]),
        .I4(io_address[1]),
        .I5(\uppCL2_reg[45]_0 [17]),
        .O(\uppCL2[43]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL2[44]_i_3 
       (.I0(\uppCL2_reg[45]_0 [14]),
        .I1(\uppCL2_reg[45]_0 [10]),
        .I2(io_address[2]),
        .I3(\uppCL2_reg[45]_0 [6]),
        .I4(io_address[1]),
        .I5(\uppCL2_reg[45]_0 [2]),
        .O(\uppCL2[44]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL2[44]_i_4 
       (.I0(\uppCL2_reg[45]_0 [30]),
        .I1(\uppCL2_reg[45]_0 [26]),
        .I2(io_address[2]),
        .I3(\uppCL2_reg[45]_0 [22]),
        .I4(io_address[1]),
        .I5(\uppCL2_reg[45]_0 [18]),
        .O(\uppCL2[44]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL2[45]_i_3 
       (.I0(\uppCL2_reg[45]_0 [15]),
        .I1(\uppCL2_reg[45]_0 [11]),
        .I2(io_address[2]),
        .I3(\uppCL2_reg[45]_0 [7]),
        .I4(io_address[1]),
        .I5(\uppCL2_reg[45]_0 [3]),
        .O(\uppCL2[45]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL2[45]_i_4 
       (.I0(\uppCL2_reg[45]_0 [31]),
        .I1(\uppCL2_reg[45]_0 [27]),
        .I2(io_address[2]),
        .I3(\uppCL2_reg[45]_0 [23]),
        .I4(io_address[1]),
        .I5(\uppCL2_reg[45]_0 [19]),
        .O(\uppCL2[45]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL2[46]_i_3 
       (.I0(\uppCL2_reg_n_0_[22] ),
        .I1(\uppCL2_reg_n_0_[16] ),
        .I2(io_address[2]),
        .I3(\uppCL2_reg_n_0_[10] ),
        .I4(io_address[1]),
        .I5(\uppCL2_reg_n_0_[4] ),
        .O(\uppCL2[46]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL2[46]_i_4 
       (.I0(\uppCL2_reg_n_0_[46] ),
        .I1(\uppCL2_reg_n_0_[40] ),
        .I2(io_address[2]),
        .I3(\uppCL2_reg_n_0_[34] ),
        .I4(io_address[1]),
        .I5(\uppCL2_reg_n_0_[28] ),
        .O(\uppCL2[46]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL2[47]_i_3 
       (.I0(\uppCL2_reg_n_0_[23] ),
        .I1(\uppCL2_reg_n_0_[17] ),
        .I2(io_address[2]),
        .I3(\uppCL2_reg_n_0_[11] ),
        .I4(io_address[1]),
        .I5(\uppCL2_reg_n_0_[5] ),
        .O(\uppCL2[47]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL2[47]_i_4 
       (.I0(\uppCL2_reg_n_0_[47] ),
        .I1(\uppCL2_reg_n_0_[41] ),
        .I2(io_address[2]),
        .I3(\uppCL2_reg_n_0_[35] ),
        .I4(io_address[1]),
        .I5(\uppCL2_reg_n_0_[29] ),
        .O(\uppCL2[47]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL2_reg[47]_0 [2]),
        .Q(\uppCL2_reg[45]_0 [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL2_reg[47]_0 [8]),
        .Q(\uppCL2_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL2_reg[47]_0 [9]),
        .Q(\uppCL2_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL2_reg[47]_0 [2]),
        .Q(\uppCL2_reg[45]_0 [8]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL2_reg[47]_0 [3]),
        .Q(\uppCL2_reg[45]_0 [9]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL2_reg[47]_0 [4]),
        .Q(\uppCL2_reg[45]_0 [10]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL2_reg[47]_0 [5]),
        .Q(\uppCL2_reg[45]_0 [11]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL2_reg[47]_0 [6]),
        .Q(\uppCL2_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL2_reg[47]_0 [7]),
        .Q(\uppCL2_reg_n_0_[17] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL2_reg[47]_0 [4]),
        .Q(\uppCL2_reg[45]_0 [12]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL2_reg[47]_0 [5]),
        .Q(\uppCL2_reg[45]_0 [13]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL2_reg[47]_0 [3]),
        .Q(\uppCL2_reg[45]_0 [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL2_reg[47]_0 [6]),
        .Q(\uppCL2_reg[45]_0 [14]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL2_reg[47]_0 [7]),
        .Q(\uppCL2_reg[45]_0 [15]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL2_reg[47]_0 [8]),
        .Q(\uppCL2_reg_n_0_[22] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL2_reg[47]_0 [9]),
        .Q(\uppCL2_reg_n_0_[23] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL2_reg[47]_0 [2]),
        .Q(\uppCL2_reg[45]_0 [16]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL2_reg[47]_0 [3]),
        .Q(\uppCL2_reg[45]_0 [17]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL2_reg[47]_0 [4]),
        .Q(\uppCL2_reg[45]_0 [18]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL2_reg[47]_0 [5]),
        .Q(\uppCL2_reg[45]_0 [19]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL2_reg[47]_0 [6]),
        .Q(\uppCL2_reg_n_0_[28] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL2_reg[47]_0 [7]),
        .Q(\uppCL2_reg_n_0_[29] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL2_reg[47]_0 [4]),
        .Q(\uppCL2_reg[45]_0 [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL2_reg[47]_0 [4]),
        .Q(\uppCL2_reg[45]_0 [20]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL2_reg[47]_0 [5]),
        .Q(\uppCL2_reg[45]_0 [21]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL2_reg[47]_0 [0]),
        .Q(\uppCL2_reg[45]_0 [22]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL2_reg[47]_0 [1]),
        .Q(\uppCL2_reg[45]_0 [23]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL2_reg[47]_0 [8]),
        .Q(\uppCL2_reg_n_0_[34] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL2_reg[47]_0 [9]),
        .Q(\uppCL2_reg_n_0_[35] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL2_reg[47]_0 [2]),
        .Q(\uppCL2_reg[45]_0 [24]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL2_reg[47]_0 [3]),
        .Q(\uppCL2_reg[45]_0 [25]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL2_reg[47]_0 [4]),
        .Q(\uppCL2_reg[45]_0 [26]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL2_reg[47]_0 [5]),
        .Q(\uppCL2_reg[45]_0 [27]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL2_reg[47]_0 [5]),
        .Q(\uppCL2_reg[45]_0 [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL2_reg[47]_0 [6]),
        .Q(\uppCL2_reg_n_0_[40] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL2_reg[47]_0 [7]),
        .Q(\uppCL2_reg_n_0_[41] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL2_reg[47]_0 [4]),
        .Q(\uppCL2_reg[45]_0 [28]),
        .R(rst_r1));
  MUXF7 \uppCL2_reg[42]_i_2 
       (.I0(\uppCL2[42]_i_3_n_0 ),
        .I1(\uppCL2[42]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_38 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL2_reg[47]_0 [5]),
        .Q(\uppCL2_reg[45]_0 [29]),
        .R(rst_r1));
  MUXF7 \uppCL2_reg[43]_i_2 
       (.I0(\uppCL2[43]_i_3_n_0 ),
        .I1(\uppCL2[43]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_35 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL2_reg[47]_0 [6]),
        .Q(\uppCL2_reg[45]_0 [30]),
        .R(rst_r1));
  MUXF7 \uppCL2_reg[44]_i_2 
       (.I0(\uppCL2[44]_i_3_n_0 ),
        .I1(\uppCL2[44]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_37 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL2_reg[47]_0 [7]),
        .Q(\uppCL2_reg[45]_0 [31]),
        .R(rst_r1));
  MUXF7 \uppCL2_reg[45]_i_2 
       (.I0(\uppCL2[45]_i_3_n_0 ),
        .I1(\uppCL2[45]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_34 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL2_reg[47]_0 [8]),
        .Q(\uppCL2_reg_n_0_[46] ),
        .R(rst_r1));
  MUXF7 \uppCL2_reg[46]_i_2 
       (.I0(\uppCL2[46]_i_3_n_0 ),
        .I1(\uppCL2[46]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_39 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL2_reg[47]_0 [9]),
        .Q(\uppCL2_reg_n_0_[47] ),
        .R(rst_r1));
  MUXF7 \uppCL2_reg[47]_i_2 
       (.I0(\uppCL2[47]_i_3_n_0 ),
        .I1(\uppCL2[47]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_36 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL2_reg[47]_0 [6]),
        .Q(\uppCL2_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL2_reg[47]_0 [7]),
        .Q(\uppCL2_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL2_reg[47]_0 [4]),
        .Q(\uppCL2_reg[45]_0 [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL2_reg[47]_0 [5]),
        .Q(\uppCL2_reg[45]_0 [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL2_reg[47]_0 [6]),
        .Q(\uppCL2_reg[45]_0 [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL2_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL2_reg[47]_0 [7]),
        .Q(\uppCL2_reg[45]_0 [7]),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL3[42]_i_3 
       (.I0(\uppCL3_reg[45]_0 [12]),
        .I1(\uppCL3_reg[45]_0 [8]),
        .I2(io_address[2]),
        .I3(\uppCL3_reg[45]_0 [4]),
        .I4(io_address[1]),
        .I5(\uppCL3_reg[45]_0 [0]),
        .O(\uppCL3[42]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL3[42]_i_4 
       (.I0(\uppCL3_reg[45]_0 [28]),
        .I1(\uppCL3_reg[45]_0 [24]),
        .I2(io_address[2]),
        .I3(\uppCL3_reg[45]_0 [20]),
        .I4(io_address[1]),
        .I5(\uppCL3_reg[45]_0 [16]),
        .O(\uppCL3[42]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL3[43]_i_3 
       (.I0(\uppCL3_reg[45]_0 [13]),
        .I1(\uppCL3_reg[45]_0 [9]),
        .I2(io_address[2]),
        .I3(\uppCL3_reg[45]_0 [5]),
        .I4(io_address[1]),
        .I5(\uppCL3_reg[45]_0 [1]),
        .O(\uppCL3[43]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL3[43]_i_4 
       (.I0(\uppCL3_reg[45]_0 [29]),
        .I1(\uppCL3_reg[45]_0 [25]),
        .I2(io_address[2]),
        .I3(\uppCL3_reg[45]_0 [21]),
        .I4(io_address[1]),
        .I5(\uppCL3_reg[45]_0 [17]),
        .O(\uppCL3[43]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL3[44]_i_3 
       (.I0(\uppCL3_reg[45]_0 [14]),
        .I1(\uppCL3_reg[45]_0 [10]),
        .I2(io_address[2]),
        .I3(\uppCL3_reg[45]_0 [6]),
        .I4(io_address[1]),
        .I5(\uppCL3_reg[45]_0 [2]),
        .O(\uppCL3[44]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL3[44]_i_4 
       (.I0(\uppCL3_reg[45]_0 [30]),
        .I1(\uppCL3_reg[45]_0 [26]),
        .I2(io_address[2]),
        .I3(\uppCL3_reg[45]_0 [22]),
        .I4(io_address[1]),
        .I5(\uppCL3_reg[45]_0 [18]),
        .O(\uppCL3[44]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL3[45]_i_3 
       (.I0(\uppCL3_reg[45]_0 [15]),
        .I1(\uppCL3_reg[45]_0 [11]),
        .I2(io_address[2]),
        .I3(\uppCL3_reg[45]_0 [7]),
        .I4(io_address[1]),
        .I5(\uppCL3_reg[45]_0 [3]),
        .O(\uppCL3[45]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL3[45]_i_4 
       (.I0(\uppCL3_reg[45]_0 [31]),
        .I1(\uppCL3_reg[45]_0 [27]),
        .I2(io_address[2]),
        .I3(\uppCL3_reg[45]_0 [23]),
        .I4(io_address[1]),
        .I5(\uppCL3_reg[45]_0 [19]),
        .O(\uppCL3[45]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL3[46]_i_3 
       (.I0(\uppCL3_reg_n_0_[22] ),
        .I1(\uppCL3_reg_n_0_[16] ),
        .I2(io_address[2]),
        .I3(\uppCL3_reg_n_0_[10] ),
        .I4(io_address[1]),
        .I5(\uppCL3_reg_n_0_[4] ),
        .O(\uppCL3[46]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL3[46]_i_4 
       (.I0(\uppCL3_reg_n_0_[46] ),
        .I1(\uppCL3_reg_n_0_[40] ),
        .I2(io_address[2]),
        .I3(\uppCL3_reg_n_0_[34] ),
        .I4(io_address[1]),
        .I5(\uppCL3_reg_n_0_[28] ),
        .O(\uppCL3[46]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL3[47]_i_3 
       (.I0(\uppCL3_reg_n_0_[23] ),
        .I1(\uppCL3_reg_n_0_[17] ),
        .I2(io_address[2]),
        .I3(\uppCL3_reg_n_0_[11] ),
        .I4(io_address[1]),
        .I5(\uppCL3_reg_n_0_[5] ),
        .O(\uppCL3[47]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \uppCL3[47]_i_4 
       (.I0(\uppCL3_reg_n_0_[47] ),
        .I1(\uppCL3_reg_n_0_[41] ),
        .I2(io_address[2]),
        .I3(\uppCL3_reg_n_0_[35] ),
        .I4(io_address[1]),
        .I5(\uppCL3_reg_n_0_[29] ),
        .O(\uppCL3[47]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL3_reg[47]_0 [2]),
        .Q(\uppCL3_reg[45]_0 [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[10] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL3_reg[47]_0 [8]),
        .Q(\uppCL3_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[11] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL3_reg[47]_0 [9]),
        .Q(\uppCL3_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[12] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL3_reg[47]_0 [2]),
        .Q(\uppCL3_reg[45]_0 [8]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[13] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL3_reg[47]_0 [3]),
        .Q(\uppCL3_reg[45]_0 [9]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[14] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL3_reg[47]_0 [4]),
        .Q(\uppCL3_reg[45]_0 [10]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[15] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL3_reg[47]_0 [5]),
        .Q(\uppCL3_reg[45]_0 [11]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[16] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL3_reg[47]_0 [6]),
        .Q(\uppCL3_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[17] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [2]),
        .D(\uppCL3_reg[47]_0 [7]),
        .Q(\uppCL3_reg_n_0_[17] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[18] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL3_reg[47]_0 [4]),
        .Q(\uppCL3_reg[45]_0 [12]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[19] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL3_reg[47]_0 [5]),
        .Q(\uppCL3_reg[45]_0 [13]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL3_reg[47]_0 [3]),
        .Q(\uppCL3_reg[45]_0 [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[20] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL3_reg[47]_0 [6]),
        .Q(\uppCL3_reg[45]_0 [14]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[21] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL3_reg[47]_0 [7]),
        .Q(\uppCL3_reg[45]_0 [15]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[22] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL3_reg[47]_0 [8]),
        .Q(\uppCL3_reg_n_0_[22] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[23] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [3]),
        .D(\uppCL3_reg[47]_0 [9]),
        .Q(\uppCL3_reg_n_0_[23] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[24] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL3_reg[47]_0 [2]),
        .Q(\uppCL3_reg[45]_0 [16]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[25] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL3_reg[47]_0 [3]),
        .Q(\uppCL3_reg[45]_0 [17]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[26] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL3_reg[47]_0 [4]),
        .Q(\uppCL3_reg[45]_0 [18]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[27] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL3_reg[47]_0 [5]),
        .Q(\uppCL3_reg[45]_0 [19]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[28] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL3_reg[47]_0 [6]),
        .Q(\uppCL3_reg_n_0_[28] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[29] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [4]),
        .D(\uppCL3_reg[47]_0 [7]),
        .Q(\uppCL3_reg_n_0_[29] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL3_reg[47]_0 [4]),
        .Q(\uppCL3_reg[45]_0 [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[30] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL3_reg[47]_0 [4]),
        .Q(\uppCL3_reg[45]_0 [20]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[31] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL3_reg[47]_0 [5]),
        .Q(\uppCL3_reg[45]_0 [21]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[32] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL3_reg[47]_0 [0]),
        .Q(\uppCL3_reg[45]_0 [22]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[33] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL3_reg[47]_0 [1]),
        .Q(\uppCL3_reg[45]_0 [23]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[34] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL3_reg[47]_0 [8]),
        .Q(\uppCL3_reg_n_0_[34] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[35] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [5]),
        .D(\uppCL3_reg[47]_0 [9]),
        .Q(\uppCL3_reg_n_0_[35] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[36] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL3_reg[47]_0 [2]),
        .Q(\uppCL3_reg[45]_0 [24]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[37] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL3_reg[47]_0 [3]),
        .Q(\uppCL3_reg[45]_0 [25]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[38] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL3_reg[47]_0 [4]),
        .Q(\uppCL3_reg[45]_0 [26]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[39] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL3_reg[47]_0 [5]),
        .Q(\uppCL3_reg[45]_0 [27]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL3_reg[47]_0 [5]),
        .Q(\uppCL3_reg[45]_0 [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[40] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL3_reg[47]_0 [6]),
        .Q(\uppCL3_reg_n_0_[40] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[41] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [6]),
        .D(\uppCL3_reg[47]_0 [7]),
        .Q(\uppCL3_reg_n_0_[41] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[42] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL3_reg[47]_0 [4]),
        .Q(\uppCL3_reg[45]_0 [28]),
        .R(rst_r1));
  MUXF7 \uppCL3_reg[42]_i_2 
       (.I0(\uppCL3[42]_i_3_n_0 ),
        .I1(\uppCL3[42]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_44 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[43] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL3_reg[47]_0 [5]),
        .Q(\uppCL3_reg[45]_0 [29]),
        .R(rst_r1));
  MUXF7 \uppCL3_reg[43]_i_2 
       (.I0(\uppCL3[43]_i_3_n_0 ),
        .I1(\uppCL3[43]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_41 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[44] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL3_reg[47]_0 [6]),
        .Q(\uppCL3_reg[45]_0 [30]),
        .R(rst_r1));
  MUXF7 \uppCL3_reg[44]_i_2 
       (.I0(\uppCL3[44]_i_3_n_0 ),
        .I1(\uppCL3[44]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_43 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[45] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL3_reg[47]_0 [7]),
        .Q(\uppCL3_reg[45]_0 [31]),
        .R(rst_r1));
  MUXF7 \uppCL3_reg[45]_i_2 
       (.I0(\uppCL3[45]_i_3_n_0 ),
        .I1(\uppCL3[45]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_40 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[46] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL3_reg[47]_0 [8]),
        .Q(\uppCL3_reg_n_0_[46] ),
        .R(rst_r1));
  MUXF7 \uppCL3_reg[46]_i_2 
       (.I0(\uppCL3[46]_i_3_n_0 ),
        .I1(\uppCL3[46]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_45 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[47] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [7]),
        .D(\uppCL3_reg[47]_0 [9]),
        .Q(\uppCL3_reg_n_0_[47] ),
        .R(rst_r1));
  MUXF7 \uppCL3_reg[47]_i_2 
       (.I0(\uppCL3[47]_i_3_n_0 ),
        .I1(\uppCL3[47]_i_4_n_0 ),
        .O(\SYNC[3].sync_reg_reg[1]_42 ),
        .S(io_address[3]));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL3_reg[47]_0 [6]),
        .Q(\uppCL3_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [0]),
        .D(\uppCL3_reg[47]_0 [7]),
        .Q(\uppCL3_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL3_reg[47]_0 [4]),
        .Q(\uppCL3_reg[45]_0 [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL3_reg[47]_0 [5]),
        .Q(\uppCL3_reg[45]_0 [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL3_reg[47]_0 [6]),
        .Q(\uppCL3_reg[45]_0 [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \uppCL3_reg[9] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(\uppCL3_reg[42]_0 [1]),
        .D(\uppCL3_reg[47]_0 [7]),
        .Q(\uppCL3_reg[45]_0 [7]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    wrCAS_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_n_134),
        .Q(wrCAS_reg_0),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'hBABABA00)) 
    \wrQ[1][0]_i_1 
       (.I0(mcWrCAS),
        .I1(\mcal_ODT_dly_reg[0][4] ),
        .I2(wrCAS_reg_0),
        .I3(\wrQ_reg[1][0] ),
        .I4(mcCasSlot2),
        .O(\wrQ_nxt[1]_13 ));
  FDRE wren_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(wren_reg_0),
        .Q(wren),
        .R(rst_r1));
  FDRE write_vref_mode_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(E),
        .D(io_write_data[15]),
        .Q(write_vref_mode_reg_n_0),
        .R(rst_r1));
  FDRE \xsdb_wr_data_reg[0] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(xsdb_wr_en_reg_0),
        .D(io_write_data[0]),
        .Q(\xsdb_wr_data_reg[8]_0 [0]),
        .R(1'b0));
  FDRE \xsdb_wr_data_reg[1] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(xsdb_wr_en_reg_0),
        .D(io_write_data[1]),
        .Q(\xsdb_wr_data_reg[8]_0 [1]),
        .R(1'b0));
  FDRE \xsdb_wr_data_reg[2] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(xsdb_wr_en_reg_0),
        .D(io_write_data[2]),
        .Q(\xsdb_wr_data_reg[8]_0 [2]),
        .R(1'b0));
  FDRE \xsdb_wr_data_reg[3] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(xsdb_wr_en_reg_0),
        .D(io_write_data[3]),
        .Q(\xsdb_wr_data_reg[8]_0 [3]),
        .R(1'b0));
  FDRE \xsdb_wr_data_reg[4] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(xsdb_wr_en_reg_0),
        .D(io_write_data[4]),
        .Q(\xsdb_wr_data_reg[8]_0 [4]),
        .R(1'b0));
  FDRE \xsdb_wr_data_reg[5] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(xsdb_wr_en_reg_0),
        .D(io_write_data[5]),
        .Q(\xsdb_wr_data_reg[8]_0 [5]),
        .R(1'b0));
  FDRE \xsdb_wr_data_reg[6] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(xsdb_wr_en_reg_0),
        .D(io_write_data[6]),
        .Q(\xsdb_wr_data_reg[8]_0 [6]),
        .R(1'b0));
  FDRE \xsdb_wr_data_reg[7] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(xsdb_wr_en_reg_0),
        .D(io_write_data[7]),
        .Q(\xsdb_wr_data_reg[8]_0 [7]),
        .R(1'b0));
  FDRE \xsdb_wr_data_reg[8] 
       (.C(\odt_shift_reg[0][17] ),
        .CE(xsdb_wr_en_reg_0),
        .D(io_write_data[8]),
        .Q(\xsdb_wr_data_reg[8]_0 [8]),
        .R(1'b0));
  FDRE xsdb_wr_en_reg
       (.C(\odt_shift_reg[0][17] ),
        .CE(1'b1),
        .D(xsdb_wr_en_reg_0),
        .Q(wea),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_config_rom" *) 
module ddr4_0_ddr4_v2_2_17_cal_config_rom
   (\dout_o_reg[5]_0 ,
    \dout_o_reg[11]_0 ,
    \addr_dec_to_mb_data[5]_i_9 ,
    \dout_o_reg[11]_1 ,
    \dout_o_reg[11]_2 );
  output \dout_o_reg[5]_0 ;
  output [10:0]\dout_o_reg[11]_0 ;
  input \addr_dec_to_mb_data[5]_i_9 ;
  input [10:0]\dout_o_reg[11]_1 ;
  input \dout_o_reg[11]_2 ;

  wire \addr_dec_to_mb_data[5]_i_9 ;
  wire [10:0]\dout_o_reg[11]_0 ;
  wire [10:0]\dout_o_reg[11]_1 ;
  wire \dout_o_reg[11]_2 ;
  wire \dout_o_reg[5]_0 ;

  LUT2 #(
    .INIT(4'hD)) 
    \addr_dec_to_mb_data[5]_i_23 
       (.I0(\dout_o_reg[11]_0 [5]),
        .I1(\addr_dec_to_mb_data[5]_i_9 ),
        .O(\dout_o_reg[5]_0 ));
  FDRE \dout_o_reg[0] 
       (.C(\dout_o_reg[11]_2 ),
        .CE(1'b1),
        .D(\dout_o_reg[11]_1 [0]),
        .Q(\dout_o_reg[11]_0 [0]),
        .R(1'b0));
  FDRE \dout_o_reg[10] 
       (.C(\dout_o_reg[11]_2 ),
        .CE(1'b1),
        .D(\dout_o_reg[11]_1 [9]),
        .Q(\dout_o_reg[11]_0 [9]),
        .R(1'b0));
  FDRE \dout_o_reg[11] 
       (.C(\dout_o_reg[11]_2 ),
        .CE(1'b1),
        .D(\dout_o_reg[11]_1 [10]),
        .Q(\dout_o_reg[11]_0 [10]),
        .R(1'b0));
  FDRE \dout_o_reg[1] 
       (.C(\dout_o_reg[11]_2 ),
        .CE(1'b1),
        .D(\dout_o_reg[11]_1 [1]),
        .Q(\dout_o_reg[11]_0 [1]),
        .R(1'b0));
  FDRE \dout_o_reg[2] 
       (.C(\dout_o_reg[11]_2 ),
        .CE(1'b1),
        .D(\dout_o_reg[11]_1 [2]),
        .Q(\dout_o_reg[11]_0 [2]),
        .R(1'b0));
  FDRE \dout_o_reg[3] 
       (.C(\dout_o_reg[11]_2 ),
        .CE(1'b1),
        .D(\dout_o_reg[11]_1 [3]),
        .Q(\dout_o_reg[11]_0 [3]),
        .R(1'b0));
  FDRE \dout_o_reg[4] 
       (.C(\dout_o_reg[11]_2 ),
        .CE(1'b1),
        .D(\dout_o_reg[11]_1 [4]),
        .Q(\dout_o_reg[11]_0 [4]),
        .R(1'b0));
  FDRE \dout_o_reg[5] 
       (.C(\dout_o_reg[11]_2 ),
        .CE(1'b1),
        .D(\dout_o_reg[11]_1 [5]),
        .Q(\dout_o_reg[11]_0 [5]),
        .R(1'b0));
  FDRE \dout_o_reg[6] 
       (.C(\dout_o_reg[11]_2 ),
        .CE(1'b1),
        .D(\dout_o_reg[11]_1 [6]),
        .Q(\dout_o_reg[11]_0 [6]),
        .R(1'b0));
  FDRE \dout_o_reg[8] 
       (.C(\dout_o_reg[11]_2 ),
        .CE(1'b1),
        .D(\dout_o_reg[11]_1 [7]),
        .Q(\dout_o_reg[11]_0 [7]),
        .R(1'b0));
  FDRE \dout_o_reg[9] 
       (.C(\dout_o_reg[11]_2 ),
        .CE(1'b1),
        .D(\dout_o_reg[11]_1 [8]),
        .Q(\dout_o_reg[11]_0 [8]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_cplx" *) 
module ddr4_0_ddr4_v2_2_17_cal_cplx
   (\cplx_CAS_reg[6]_0 ,
    cplx_cal,
    \cal_RAS_pre_reg[1] ,
    \cal_RAS_pre_reg[2] ,
    \cplx_RAS_reg[6]_0 ,
    \cplx_RAS_reg[6]_1 ,
    \cal_ACT_n_pre_reg[7] ,
    cal_CS_n,
    \init_cal_BA_reg[15] ,
    winAct_reg,
    cplx_cal_reg_0,
    calDone_reg,
    \init_cal_BA_reg[7] ,
    calDone_reg_0,
    \init_cal_BG_reg[7] ,
    calDone_reg_1,
    \SYNC[20].sync_reg_reg[1] ,
    \cplx_error_accum_reg[14]_0 ,
    \cplx_error_accum_reg[15]_0 ,
    \cplx_error_accum_reg[44]_0 ,
    \cplx_error_accum_reg[19]_0 ,
    cplx_issue_cas_wr_reg_0,
    SS,
    cplx_issue_cas_rd_reg_0,
    gt_data_ready_flag_reg,
    cplx_status,
    \cplx_DQOut_reg[511]_0 ,
    \cplx_DMOut_n_reg[63]_0 ,
    \cplx_error_accum_reg[63]_0 ,
    Q,
    \mcal_ADR_dly_reg[0][134] ,
    ub_ready,
    rdCAS_reg,
    \mcal_ADR_dly_reg[0][135] ,
    \mcal_ACT_n_dly_reg[0][7] ,
    \mcal_BG_dly[0][7]_i_2_0 ,
    a_b_cmd_sel,
    \mcal_BG_dly[0][7]_i_2_1 ,
    \mcal_ADR_dly_reg[0][87] ,
    \mcal_CS_n_dly_reg[0][7] ,
    \mcal_BA_dly_reg[0][15] ,
    \mcal_BA_dly_reg[0][8] ,
    \mcal_CS_n_dly_reg[0][0] ,
    mc_BA,
    winAct,
    mc_CS_n,
    init_cal_CS_n,
    mc_CS_n7,
    \mcal_ADR_dly_reg[0][135]_0 ,
    mc_ADR,
    \mcal_ADR_dly_reg[0][128] ,
    mc_BG,
    p_1_in,
    \mcal_PAR_dly_reg[0][5] ,
    \mcal_PAR_dly_reg[0][3] ,
    \mcal_PAR_dly_reg[0][1] ,
    \mcal_PAR_dly_reg[0][0] ,
    \mcal_PAR_dly_reg[0][7] ,
    io_address,
    \addr_dec_to_mb_data[0]_i_2 ,
    \addr_dec_to_mb_data[0]_i_2_0 ,
    \addr_dec_to_mb_data[0]_i_2_1 ,
    \addr_dec_to_mb_data_reg[15] ,
    \addr_dec_to_mb_data_reg[19] ,
    \addr_dec_to_mb_data_reg[12] ,
    \addr_dec_to_mb_data_reg[12]_0 ,
    wrCAS_reg,
    extended_write_mode,
    D,
    wrCAS_reg_0,
    wrCAS_reg_1,
    rdCAS_reg_0,
    \cal_CS_n_pre_reg[0] ,
    out,
    wrCAS_reg_2,
    gt_data_ready_flag,
    \cal_DQOut_reg[511] ,
    wrDataEn_pi,
    \cal_DMOut_n_reg[63] ,
    \cal_DMOut_n_reg[55] ,
    \cal_DMOut_n_reg[47] ,
    \cal_DMOut_n_reg[39] ,
    \cal_DMOut_n_reg[31] ,
    \cal_DMOut_n_reg[23] ,
    \cal_DMOut_n_reg[15] ,
    \cal_DMOut_n_reg[7] ,
    rdDataEn_pi,
    init_cal_BG,
    \rd_addr_101_reg[7] ,
    \cplx_dqin_byte_103_reg[63]_0 ,
    \FSM_sequential_cplx_state_reg[3]_0 ,
    \FSM_sequential_cplx_state_reg[1]_0 ,
    \FSM_sequential_cplx_state_reg[2]_i_2_0 ,
    \FSM_sequential_cplx_state_reg[2]_i_2_1 ,
    \FSM_sequential_cplx_state_reg[2]_i_2_2 ,
    \FSM_sequential_cplx_state_reg[2]_i_2_3 ,
    \FSM_sequential_cplx_state_reg[2]_i_2_4 ,
    \FSM_sequential_cplx_state_reg[2]_i_2_5 ,
    \FSM_sequential_cplx_state_reg[2]_i_2_6 ,
    \cplx_config_byte_select_reg[0]_0 ,
    \cplx_config_byte_select_reg[0]_1 ,
    \cplx_config_byte_select_reg[0]_2 ,
    \cplx_config_byte_select_reg[1]_0 ,
    \cplx_config_byte_select_reg[2]_0 ,
    \cplx_CS_n_reg[6]_0 ,
    \cplx_CS_n_reg[6]_1 );
  output [7:0]\cplx_CAS_reg[6]_0 ;
  output cplx_cal;
  output \cal_RAS_pre_reg[1] ;
  output \cal_RAS_pre_reg[2] ;
  output \cplx_RAS_reg[6]_0 ;
  output \cplx_RAS_reg[6]_1 ;
  output [5:0]\cal_ACT_n_pre_reg[7] ;
  output [3:0]cal_CS_n;
  output [8:0]\init_cal_BA_reg[15] ;
  output [1:0]winAct_reg;
  output [3:0]cplx_cal_reg_0;
  output [76:0]calDone_reg;
  output \init_cal_BA_reg[7] ;
  output [3:0]calDone_reg_0;
  output \init_cal_BG_reg[7] ;
  output [7:0]calDone_reg_1;
  output \SYNC[20].sync_reg_reg[1] ;
  output \cplx_error_accum_reg[14]_0 ;
  output \cplx_error_accum_reg[15]_0 ;
  output \cplx_error_accum_reg[44]_0 ;
  output \cplx_error_accum_reg[19]_0 ;
  output cplx_issue_cas_wr_reg_0;
  output [0:0]SS;
  output cplx_issue_cas_rd_reg_0;
  output gt_data_ready_flag_reg;
  output [0:0]cplx_status;
  output [511:0]\cplx_DQOut_reg[511]_0 ;
  output [63:0]\cplx_DMOut_n_reg[63]_0 ;
  output [53:0]\cplx_error_accum_reg[63]_0 ;
  input [7:0]Q;
  input [14:0]\mcal_ADR_dly_reg[0][134] ;
  input ub_ready;
  input [7:0]rdCAS_reg;
  input [7:0]\mcal_ADR_dly_reg[0][135] ;
  input [7:0]\mcal_ACT_n_dly_reg[0][7] ;
  input [16:0]\mcal_BG_dly[0][7]_i_2_0 ;
  input a_b_cmd_sel;
  input [16:0]\mcal_BG_dly[0][7]_i_2_1 ;
  input \mcal_ADR_dly_reg[0][87] ;
  input [7:0]\mcal_CS_n_dly_reg[0][7] ;
  input [1:0]\mcal_BA_dly_reg[0][15] ;
  input [1:0]\mcal_BA_dly_reg[0][8] ;
  input \mcal_CS_n_dly_reg[0][0] ;
  input [6:0]mc_BA;
  input winAct;
  input [0:0]mc_CS_n;
  input [0:0]init_cal_CS_n;
  input mc_CS_n7;
  input [4:0]\mcal_ADR_dly_reg[0][135]_0 ;
  input [35:0]mc_ADR;
  input [4:0]\mcal_ADR_dly_reg[0][128] ;
  input [2:0]mc_BG;
  input [0:0]p_1_in;
  input \mcal_PAR_dly_reg[0][5] ;
  input \mcal_PAR_dly_reg[0][3] ;
  input \mcal_PAR_dly_reg[0][1] ;
  input \mcal_PAR_dly_reg[0][0] ;
  input \mcal_PAR_dly_reg[0][7] ;
  input [5:0]io_address;
  input \addr_dec_to_mb_data[0]_i_2 ;
  input \addr_dec_to_mb_data[0]_i_2_0 ;
  input \addr_dec_to_mb_data[0]_i_2_1 ;
  input \addr_dec_to_mb_data_reg[15] ;
  input \addr_dec_to_mb_data_reg[19] ;
  input \addr_dec_to_mb_data_reg[12] ;
  input \addr_dec_to_mb_data_reg[12]_0 ;
  input wrCAS_reg;
  input extended_write_mode;
  input [2:0]D;
  input wrCAS_reg_0;
  input [0:0]wrCAS_reg_1;
  input rdCAS_reg_0;
  input \cal_CS_n_pre_reg[0] ;
  input out;
  input [0:0]wrCAS_reg_2;
  input gt_data_ready_flag;
  input [511:0]\cal_DQOut_reg[511] ;
  input wrDataEn_pi;
  input [7:0]\cal_DMOut_n_reg[63] ;
  input [7:0]\cal_DMOut_n_reg[55] ;
  input [7:0]\cal_DMOut_n_reg[47] ;
  input [7:0]\cal_DMOut_n_reg[39] ;
  input [7:0]\cal_DMOut_n_reg[31] ;
  input [7:0]\cal_DMOut_n_reg[23] ;
  input [7:0]\cal_DMOut_n_reg[15] ;
  input [7:0]\cal_DMOut_n_reg[7] ;
  input rdDataEn_pi;
  input [0:0]init_cal_BG;
  input \rd_addr_101_reg[7] ;
  input [511:0]\cplx_dqin_byte_103_reg[63]_0 ;
  input \FSM_sequential_cplx_state_reg[3]_0 ;
  input [1:0]\FSM_sequential_cplx_state_reg[1]_0 ;
  input \FSM_sequential_cplx_state_reg[2]_i_2_0 ;
  input \FSM_sequential_cplx_state_reg[2]_i_2_1 ;
  input \FSM_sequential_cplx_state_reg[2]_i_2_2 ;
  input \FSM_sequential_cplx_state_reg[2]_i_2_3 ;
  input \FSM_sequential_cplx_state_reg[2]_i_2_4 ;
  input \FSM_sequential_cplx_state_reg[2]_i_2_5 ;
  input \FSM_sequential_cplx_state_reg[2]_i_2_6 ;
  input \cplx_config_byte_select_reg[0]_0 ;
  input \cplx_config_byte_select_reg[0]_1 ;
  input \cplx_config_byte_select_reg[0]_2 ;
  input \cplx_config_byte_select_reg[1]_0 ;
  input \cplx_config_byte_select_reg[2]_0 ;
  input \cplx_CS_n_reg[6]_0 ;
  input \cplx_CS_n_reg[6]_1 ;

  wire [2:0]D;
  wire \FSM_sequential_cplx_state[0]_i_1_n_0 ;
  wire \FSM_sequential_cplx_state[1]_i_2_n_0 ;
  wire \FSM_sequential_cplx_state[1]_i_3_n_0 ;
  wire \FSM_sequential_cplx_state[1]_i_4_n_0 ;
  wire \FSM_sequential_cplx_state[2]_i_10_n_0 ;
  wire \FSM_sequential_cplx_state[2]_i_3_n_0 ;
  wire \FSM_sequential_cplx_state[2]_i_4_n_0 ;
  wire \FSM_sequential_cplx_state[2]_i_5_n_0 ;
  wire \FSM_sequential_cplx_state[2]_i_6_n_0 ;
  wire \FSM_sequential_cplx_state[2]_i_7_n_0 ;
  wire \FSM_sequential_cplx_state[2]_i_8_n_0 ;
  wire \FSM_sequential_cplx_state[2]_i_9_n_0 ;
  wire \FSM_sequential_cplx_state[3]_i_1_n_0 ;
  wire \FSM_sequential_cplx_state[3]_i_3_n_0 ;
  wire \FSM_sequential_cplx_state[3]_i_4_n_0 ;
  wire [1:0]\FSM_sequential_cplx_state_reg[1]_0 ;
  wire \FSM_sequential_cplx_state_reg[2]_i_2_0 ;
  wire \FSM_sequential_cplx_state_reg[2]_i_2_1 ;
  wire \FSM_sequential_cplx_state_reg[2]_i_2_2 ;
  wire \FSM_sequential_cplx_state_reg[2]_i_2_3 ;
  wire \FSM_sequential_cplx_state_reg[2]_i_2_4 ;
  wire \FSM_sequential_cplx_state_reg[2]_i_2_5 ;
  wire \FSM_sequential_cplx_state_reg[2]_i_2_6 ;
  wire \FSM_sequential_cplx_state_reg[2]_i_2_n_5 ;
  wire \FSM_sequential_cplx_state_reg[2]_i_2_n_6 ;
  wire \FSM_sequential_cplx_state_reg[2]_i_2_n_7 ;
  wire \FSM_sequential_cplx_state_reg[3]_0 ;
  wire \FSM_sequential_seq_state[0]_i_2_n_0 ;
  wire \FSM_sequential_seq_state[0]_i_3_n_0 ;
  wire \FSM_sequential_seq_state[0]_i_4_n_0 ;
  wire \FSM_sequential_seq_state[1]_i_2_n_0 ;
  wire \FSM_sequential_seq_state[1]_i_3_n_0 ;
  wire \FSM_sequential_seq_state[1]_i_4_n_0 ;
  wire \FSM_sequential_seq_state[1]_i_5_n_0 ;
  wire \FSM_sequential_seq_state[2]_i_2_n_0 ;
  wire \FSM_sequential_seq_state[3]_i_1_n_0 ;
  wire \FSM_sequential_seq_state[3]_i_3_n_0 ;
  wire \FSM_sequential_seq_state[3]_i_4_n_0 ;
  wire \FSM_sequential_seq_state[3]_i_5_n_0 ;
  wire \FSM_sequential_seq_state[3]_i_6_n_0 ;
  wire \FSM_sequential_seq_state[3]_i_7_n_0 ;
  wire [7:0]Q;
  wire [0:0]SS;
  wire \SYNC[20].sync_reg_reg[1] ;
  wire a_b_cmd_sel;
  wire \addr_dec_to_mb_data[0]_i_2 ;
  wire \addr_dec_to_mb_data[0]_i_24_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_2_0 ;
  wire \addr_dec_to_mb_data[0]_i_2_1 ;
  wire \addr_dec_to_mb_data[0]_i_43_n_0 ;
  wire \addr_dec_to_mb_data_reg[12] ;
  wire \addr_dec_to_mb_data_reg[12]_0 ;
  wire \addr_dec_to_mb_data_reg[15] ;
  wire \addr_dec_to_mb_data_reg[19] ;
  wire [4:0]burst_count;
  wire \burst_count[0]_i_1_n_0 ;
  wire \burst_count[0]_i_2_n_0 ;
  wire \burst_count[0]_i_3_n_0 ;
  wire \burst_count[1]_i_1_n_0 ;
  wire \burst_count[1]_i_2_n_0 ;
  wire \burst_count[1]_i_3_n_0 ;
  wire \burst_count[2]_i_1_n_0 ;
  wire \burst_count[2]_i_2_n_0 ;
  wire \burst_count[2]_i_3_n_0 ;
  wire \burst_count[2]_i_4_n_0 ;
  wire \burst_count[2]_i_5_n_0 ;
  wire \burst_count[3]_i_1_n_0 ;
  wire \burst_count[3]_i_2_n_0 ;
  wire \burst_count[3]_i_3_n_0 ;
  wire \burst_count[3]_i_4_n_0 ;
  wire \burst_count[3]_i_5_n_0 ;
  wire \burst_count[3]_i_6_n_0 ;
  wire \burst_count[4]_i_1_n_0 ;
  wire \burst_count[4]_i_2_n_0 ;
  wire \burst_count[4]_i_3_n_0 ;
  wire \burst_count[4]_i_4_n_0 ;
  wire \burst_index[0]_i_1_n_0 ;
  wire \burst_index[1]_i_1_n_0 ;
  wire \burst_index[3]_i_1_n_0 ;
  wire [4:0]burst_index_reg;
  wire [76:0]calDone_reg;
  wire [3:0]calDone_reg_0;
  wire [7:0]calDone_reg_1;
  wire [4:3]cal_ACT_n;
  wire [5:0]\cal_ACT_n_pre_reg[7] ;
  wire [128:7]cal_ADR;
  wire [3:0]cal_CS_n;
  wire \cal_CS_n_pre_reg[0] ;
  wire [7:0]\cal_DMOut_n_reg[15] ;
  wire [7:0]\cal_DMOut_n_reg[23] ;
  wire [7:0]\cal_DMOut_n_reg[31] ;
  wire [7:0]\cal_DMOut_n_reg[39] ;
  wire [7:0]\cal_DMOut_n_reg[47] ;
  wire [7:0]\cal_DMOut_n_reg[55] ;
  wire [7:0]\cal_DMOut_n_reg[63] ;
  wire [7:0]\cal_DMOut_n_reg[7] ;
  wire [511:0]\cal_DQOut_reg[511] ;
  wire \cal_RAS_pre_reg[1] ;
  wire \cal_RAS_pre_reg[2] ;
  wire cas_is_bursty;
  wire cas_is_bursty_nxt;
  wire cas_is_read;
  wire cas_is_read_nxt;
  wire cas_uses_dm;
  wire cas_uses_dm_nxt;
  wire cplx_ACT_cmd;
  wire [6:6]cplx_ACT_n;
  wire cplx_ACT_n_nxt0;
  wire [8:0]cplx_ADR;
  wire [8:0]cplx_ADR_cmd;
  wire \cplx_ADR_cmd[2]_i_1_n_0 ;
  wire [8:3]cplx_ADR_cmd_nxt;
  wire [1:0]cplx_BA;
  wire [1:0]cplx_BA_cmd;
  wire [6:6]cplx_CAS;
  wire cplx_CAS_nxt0;
  wire [7:0]\cplx_CAS_reg[6]_0 ;
  wire cplx_CS_n_cmd;
  wire cplx_CS_n_cmd_nxt;
  wire cplx_CS_n_nxt0;
  wire \cplx_CS_n_reg[6]_0 ;
  wire \cplx_CS_n_reg[6]_1 ;
  wire \cplx_CS_n_reg_n_0_[6] ;
  wire [63:56]cplx_DMOut_n;
  wire [63:56]cplx_DMOut_n0;
  wire [63:0]\cplx_DMOut_n_reg[63]_0 ;
  wire [511:0]cplx_DQOut;
  wire \cplx_DQOut[511]_i_1_n_0 ;
  wire [511:0]\cplx_DQOut_reg[511]_0 ;
  wire [6:6]cplx_RAS;
  wire cplx_RAS_cmd_nxt;
  wire cplx_RAS_nxt0;
  wire \cplx_RAS_reg[6]_0 ;
  wire \cplx_RAS_reg[6]_1 ;
  wire [6:6]cplx_WE;
  wire cplx_WE_cmd_nxt;
  wire cplx_WE_nxt0;
  wire cplx_cal;
  wire [3:0]cplx_cal_reg_0;
  wire [4:0]cplx_config_byte_select;
  (* RTL_KEEP = "true" *) wire [4:0]cplx_config_byte_select_nxt;
  wire \cplx_config_byte_select_reg[0]_0 ;
  wire \cplx_config_byte_select_reg[0]_1 ;
  wire \cplx_config_byte_select_reg[0]_2 ;
  wire \cplx_config_byte_select_reg[1]_0 ;
  wire \cplx_config_byte_select_reg[2]_0 ;
  wire [63:0]cplx_data_byte_102;
  wire [63:0]cplx_data_byte_103;
  wire [63:0]cplx_dqin_byte_103;
  wire \cplx_dqin_byte_103[0]_i_1_n_0 ;
  wire \cplx_dqin_byte_103[0]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[0]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[10]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[10]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[11]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[11]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[12]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[12]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[13]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[13]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[14]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[14]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[15]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[15]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[16]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[16]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[17]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[17]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[18]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[18]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[19]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[19]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[1]_i_1_n_0 ;
  wire \cplx_dqin_byte_103[1]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[1]_i_4_n_0 ;
  wire \cplx_dqin_byte_103[20]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[20]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[21]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[21]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[22]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[22]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[23]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[23]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[24]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[24]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[25]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[25]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[26]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[26]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[27]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[27]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[28]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[28]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[29]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[29]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[2]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[2]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[30]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[30]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[31]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[31]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[32]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[32]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[33]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[33]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[34]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[34]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[35]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[35]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[36]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[36]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[37]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[37]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[38]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[38]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[39]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[39]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[3]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[3]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[40]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[40]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[41]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[41]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[42]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[42]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[43]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[43]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[44]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[44]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[45]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[45]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[46]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[46]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[47]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[47]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[48]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[48]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[49]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[49]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[4]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[4]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[50]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[50]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[51]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[51]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[52]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[52]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[53]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[53]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[54]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[54]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[55]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[55]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[56]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[56]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[57]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[57]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[58]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[58]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[59]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[59]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[5]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[5]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[60]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[60]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[61]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[61]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[62]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[62]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[63]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[63]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[6]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[6]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[7]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[7]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[8]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[8]_i_3_n_0 ;
  wire \cplx_dqin_byte_103[9]_i_2_n_0 ;
  wire \cplx_dqin_byte_103[9]_i_3_n_0 ;
  wire \cplx_dqin_byte_103_reg[10]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[11]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[12]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[13]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[14]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[15]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[16]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[17]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[18]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[19]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[1]_i_2_n_0 ;
  wire \cplx_dqin_byte_103_reg[20]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[21]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[22]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[23]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[24]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[25]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[26]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[27]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[28]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[29]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[2]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[30]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[31]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[32]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[33]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[34]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[35]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[36]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[37]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[38]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[39]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[3]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[40]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[41]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[42]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[43]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[44]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[45]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[46]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[47]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[48]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[49]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[4]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[50]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[51]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[52]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[53]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[54]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[55]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[56]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[57]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[58]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[59]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[5]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[60]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[61]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[62]_i_1_n_0 ;
  wire [511:0]\cplx_dqin_byte_103_reg[63]_0 ;
  wire \cplx_dqin_byte_103_reg[63]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[6]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[7]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[8]_i_1_n_0 ;
  wire \cplx_dqin_byte_103_reg[9]_i_1_n_0 ;
  wire cplx_dqin_valid_102;
  wire cplx_dqin_valid_103;
  wire [19:0]cplx_err_log30;
  wire [19:0]cplx_err_log74;
  wire cplx_error_accum;
  wire \cplx_error_accum[0]_i_1_n_0 ;
  wire \cplx_error_accum[10]_i_1_n_0 ;
  wire \cplx_error_accum[11]_i_1_n_0 ;
  wire \cplx_error_accum[12]_i_1_n_0 ;
  wire \cplx_error_accum[13]_i_1_n_0 ;
  wire \cplx_error_accum[14]_i_1_n_0 ;
  wire \cplx_error_accum[15]_i_1_n_0 ;
  wire \cplx_error_accum[16]_i_1_n_0 ;
  wire \cplx_error_accum[17]_i_1_n_0 ;
  wire \cplx_error_accum[18]_i_1_n_0 ;
  wire \cplx_error_accum[19]_i_1_n_0 ;
  wire \cplx_error_accum[1]_i_1_n_0 ;
  wire \cplx_error_accum[20]_i_1_n_0 ;
  wire \cplx_error_accum[21]_i_1_n_0 ;
  wire \cplx_error_accum[22]_i_1_n_0 ;
  wire \cplx_error_accum[23]_i_1_n_0 ;
  wire \cplx_error_accum[24]_i_1_n_0 ;
  wire \cplx_error_accum[25]_i_1_n_0 ;
  wire \cplx_error_accum[26]_i_1_n_0 ;
  wire \cplx_error_accum[27]_i_1_n_0 ;
  wire \cplx_error_accum[28]_i_1_n_0 ;
  wire \cplx_error_accum[29]_i_1_n_0 ;
  wire \cplx_error_accum[2]_i_1_n_0 ;
  wire \cplx_error_accum[30]_i_1_n_0 ;
  wire \cplx_error_accum[31]_i_1_n_0 ;
  wire \cplx_error_accum[32]_i_1_n_0 ;
  wire \cplx_error_accum[33]_i_1_n_0 ;
  wire \cplx_error_accum[34]_i_1_n_0 ;
  wire \cplx_error_accum[35]_i_1_n_0 ;
  wire \cplx_error_accum[36]_i_1_n_0 ;
  wire \cplx_error_accum[37]_i_1_n_0 ;
  wire \cplx_error_accum[38]_i_1_n_0 ;
  wire \cplx_error_accum[39]_i_1_n_0 ;
  wire \cplx_error_accum[3]_i_1_n_0 ;
  wire \cplx_error_accum[40]_i_1_n_0 ;
  wire \cplx_error_accum[41]_i_1_n_0 ;
  wire \cplx_error_accum[42]_i_1_n_0 ;
  wire \cplx_error_accum[43]_i_1_n_0 ;
  wire \cplx_error_accum[44]_i_1_n_0 ;
  wire \cplx_error_accum[45]_i_1_n_0 ;
  wire \cplx_error_accum[46]_i_1_n_0 ;
  wire \cplx_error_accum[47]_i_1_n_0 ;
  wire \cplx_error_accum[48]_i_1_n_0 ;
  wire \cplx_error_accum[49]_i_1_n_0 ;
  wire \cplx_error_accum[4]_i_1_n_0 ;
  wire \cplx_error_accum[50]_i_1_n_0 ;
  wire \cplx_error_accum[51]_i_1_n_0 ;
  wire \cplx_error_accum[52]_i_1_n_0 ;
  wire \cplx_error_accum[53]_i_1_n_0 ;
  wire \cplx_error_accum[54]_i_1_n_0 ;
  wire \cplx_error_accum[55]_i_1_n_0 ;
  wire \cplx_error_accum[56]_i_1_n_0 ;
  wire \cplx_error_accum[57]_i_1_n_0 ;
  wire \cplx_error_accum[58]_i_1_n_0 ;
  wire \cplx_error_accum[59]_i_1_n_0 ;
  wire \cplx_error_accum[5]_i_1_n_0 ;
  wire \cplx_error_accum[60]_i_1_n_0 ;
  wire \cplx_error_accum[61]_i_1_n_0 ;
  wire \cplx_error_accum[62]_i_1_n_0 ;
  wire \cplx_error_accum[63]_i_2_n_0 ;
  wire \cplx_error_accum[6]_i_1_n_0 ;
  wire \cplx_error_accum[7]_i_1_n_0 ;
  wire \cplx_error_accum[8]_i_1_n_0 ;
  wire \cplx_error_accum[9]_i_1_n_0 ;
  wire \cplx_error_accum_reg[14]_0 ;
  wire \cplx_error_accum_reg[15]_0 ;
  wire \cplx_error_accum_reg[19]_0 ;
  wire \cplx_error_accum_reg[44]_0 ;
  wire [53:0]\cplx_error_accum_reg[63]_0 ;
  wire cplx_issue_cas_rd;
  wire cplx_issue_cas_rd_reg_0;
  wire cplx_issue_cas_wr;
  wire cplx_issue_cas_wr_nxt;
  wire cplx_issue_cas_wr_reg_0;
  wire \cplx_loops[6]_i_2_n_0 ;
  wire [6:0]cplx_loops_reg;
  wire [3:0]cplx_state;
  wire cplx_state_nxt2;
  wire [3:1]cplx_state_nxt__0;
  wire [0:0]cplx_status;
  wire [0:0]cplx_status_nxt;
  wire early_wrDataEn;
  wire extended_write_mode;
  wire gt_data_ready_flag;
  wire gt_data_ready_flag_reg;
  wire [8:0]\init_cal_BA_reg[15] ;
  wire \init_cal_BA_reg[7] ;
  wire [0:0]init_cal_BG;
  wire \init_cal_BG_reg[7] ;
  wire [0:0]init_cal_CS_n;
  wire [5:0]io_address;
  wire [35:0]mc_ADR;
  wire [6:0]mc_BA;
  wire [2:0]mc_BG;
  wire [0:0]mc_CS_n;
  wire mc_CS_n7;
  wire [7:0]\mcal_ACT_n_dly_reg[0][7] ;
  wire \mcal_ADR_dly[0][131]_i_2_n_0 ;
  wire \mcal_ADR_dly[0][132]_i_3_n_0 ;
  wire \mcal_ADR_dly[0][135]_i_2_n_0 ;
  wire [4:0]\mcal_ADR_dly_reg[0][128] ;
  wire [14:0]\mcal_ADR_dly_reg[0][134] ;
  wire [7:0]\mcal_ADR_dly_reg[0][135] ;
  wire [4:0]\mcal_ADR_dly_reg[0][135]_0 ;
  wire \mcal_ADR_dly_reg[0][87] ;
  wire [1:0]\mcal_BA_dly_reg[0][15] ;
  wire [1:0]\mcal_BA_dly_reg[0][8] ;
  wire [16:0]\mcal_BG_dly[0][7]_i_2_0 ;
  wire [16:0]\mcal_BG_dly[0][7]_i_2_1 ;
  wire \mcal_CS_n_dly_reg[0][0] ;
  wire [7:0]\mcal_CS_n_dly_reg[0][7] ;
  wire \mcal_PAR_dly[0][0]_i_3_n_0 ;
  wire \mcal_PAR_dly[0][1]_i_2_n_0 ;
  wire \mcal_PAR_dly[0][2]_i_3_n_0 ;
  wire \mcal_PAR_dly[0][3]_i_2_n_0 ;
  wire \mcal_PAR_dly[0][4]_i_3_n_0 ;
  wire \mcal_PAR_dly[0][5]_i_2_n_0 ;
  wire \mcal_PAR_dly[0][6]_i_3_n_0 ;
  wire \mcal_PAR_dly[0][7]_i_3_n_0 ;
  wire \mcal_PAR_dly[0][7]_i_4_n_0 ;
  wire \mcal_PAR_dly[0][7]_i_6_n_0 ;
  wire \mcal_PAR_dly[0][7]_i_7_n_0 ;
  wire \mcal_PAR_dly[0][7]_i_8_n_0 ;
  wire \mcal_PAR_dly_reg[0][0] ;
  wire \mcal_PAR_dly_reg[0][1] ;
  wire \mcal_PAR_dly_reg[0][3] ;
  wire \mcal_PAR_dly_reg[0][5] ;
  wire \mcal_PAR_dly_reg[0][7] ;
  wire out;
  wire outstanding_reads;
  wire \outstanding_reads[0]_i_1_n_0 ;
  wire \outstanding_reads[1]_i_1_n_0 ;
  wire \outstanding_reads[2]_i_1_n_0 ;
  wire \outstanding_reads[3]_i_1_n_0 ;
  wire \outstanding_reads[4]_i_1_n_0 ;
  wire \outstanding_reads[4]_i_2_n_0 ;
  wire \outstanding_reads[4]_i_3_n_0 ;
  wire \outstanding_reads_reg_n_0_[0] ;
  wire \outstanding_reads_reg_n_0_[1] ;
  wire \outstanding_reads_reg_n_0_[2] ;
  wire \outstanding_reads_reg_n_0_[3] ;
  wire \outstanding_reads_reg_n_0_[4] ;
  wire [4:2]p_0_in;
  wire p_0_in0_out;
  wire p_0_in1_out;
  wire [2:0]p_0_in__0;
  wire [6:0]p_0_in__1;
  wire [5:0]p_0_in__2;
  wire [0:0]p_1_in;
  wire [1:0]p_1_in_0;
  wire p_5_in;
  wire rdCAS_i_10_n_0;
  wire rdCAS_i_11_n_0;
  wire rdCAS_i_2_n_0;
  wire rdCAS_i_4_n_0;
  wire rdCAS_i_5_n_0;
  wire rdCAS_i_6_n_0;
  wire rdCAS_i_7_n_0;
  wire rdCAS_i_8_n_0;
  wire rdCAS_i_9_n_0;
  wire [7:0]rdCAS_reg;
  wire rdCAS_reg_0;
  wire rdDataEn_pi;
  wire \rd_addr_101_reg[7] ;
  wire [1:0]seq_bg;
  wire \seq_bg[1]_i_1_n_0 ;
  wire \seq_col[5]_i_2_n_0 ;
  wire [5:0]seq_col_reg;
  wire \seq_row[2]_i_1_n_0 ;
  wire \seq_row[2]_i_3_n_0 ;
  wire [2:0]seq_row_reg;
  wire [3:0]seq_state;
  wire seq_state_issue_act;
  wire [3:0]seq_state_nxt;
  wire [4:1]seq_timer;
  wire [0:0]seq_timer0;
  wire \seq_timer[1]_i_2_n_0 ;
  wire \seq_timer[2]_i_1_n_0 ;
  wire \seq_timer[3]_i_1_n_0 ;
  wire \seq_timer[3]_i_2_n_0 ;
  wire \seq_timer[4]_i_2_n_0 ;
  wire \seq_timer[4]_i_3_n_0 ;
  wire \seq_timer_reg_n_0_[0] ;
  wire \seq_timer_reg_n_0_[1] ;
  wire \seq_timer_reg_n_0_[2] ;
  wire \seq_timer_reg_n_0_[3] ;
  wire \seq_timer_reg_n_0_[4] ;
  wire u_ddr_cal_cplx_data_n_0;
  wire u_ddr_cal_cplx_data_n_10;
  wire u_ddr_cal_cplx_data_n_100;
  wire u_ddr_cal_cplx_data_n_101;
  wire u_ddr_cal_cplx_data_n_102;
  wire u_ddr_cal_cplx_data_n_103;
  wire u_ddr_cal_cplx_data_n_104;
  wire u_ddr_cal_cplx_data_n_105;
  wire u_ddr_cal_cplx_data_n_106;
  wire u_ddr_cal_cplx_data_n_107;
  wire u_ddr_cal_cplx_data_n_108;
  wire u_ddr_cal_cplx_data_n_109;
  wire u_ddr_cal_cplx_data_n_11;
  wire u_ddr_cal_cplx_data_n_110;
  wire u_ddr_cal_cplx_data_n_111;
  wire u_ddr_cal_cplx_data_n_112;
  wire u_ddr_cal_cplx_data_n_113;
  wire u_ddr_cal_cplx_data_n_114;
  wire u_ddr_cal_cplx_data_n_115;
  wire u_ddr_cal_cplx_data_n_116;
  wire u_ddr_cal_cplx_data_n_117;
  wire u_ddr_cal_cplx_data_n_118;
  wire u_ddr_cal_cplx_data_n_119;
  wire u_ddr_cal_cplx_data_n_12;
  wire u_ddr_cal_cplx_data_n_120;
  wire u_ddr_cal_cplx_data_n_121;
  wire u_ddr_cal_cplx_data_n_122;
  wire u_ddr_cal_cplx_data_n_123;
  wire u_ddr_cal_cplx_data_n_124;
  wire u_ddr_cal_cplx_data_n_125;
  wire u_ddr_cal_cplx_data_n_126;
  wire u_ddr_cal_cplx_data_n_127;
  wire u_ddr_cal_cplx_data_n_128;
  wire u_ddr_cal_cplx_data_n_129;
  wire u_ddr_cal_cplx_data_n_13;
  wire u_ddr_cal_cplx_data_n_130;
  wire u_ddr_cal_cplx_data_n_131;
  wire u_ddr_cal_cplx_data_n_132;
  wire u_ddr_cal_cplx_data_n_133;
  wire u_ddr_cal_cplx_data_n_134;
  wire u_ddr_cal_cplx_data_n_135;
  wire u_ddr_cal_cplx_data_n_136;
  wire u_ddr_cal_cplx_data_n_137;
  wire u_ddr_cal_cplx_data_n_138;
  wire u_ddr_cal_cplx_data_n_139;
  wire u_ddr_cal_cplx_data_n_14;
  wire u_ddr_cal_cplx_data_n_140;
  wire u_ddr_cal_cplx_data_n_141;
  wire u_ddr_cal_cplx_data_n_142;
  wire u_ddr_cal_cplx_data_n_143;
  wire u_ddr_cal_cplx_data_n_144;
  wire u_ddr_cal_cplx_data_n_145;
  wire u_ddr_cal_cplx_data_n_146;
  wire u_ddr_cal_cplx_data_n_147;
  wire u_ddr_cal_cplx_data_n_148;
  wire u_ddr_cal_cplx_data_n_149;
  wire u_ddr_cal_cplx_data_n_15;
  wire u_ddr_cal_cplx_data_n_150;
  wire u_ddr_cal_cplx_data_n_151;
  wire u_ddr_cal_cplx_data_n_152;
  wire u_ddr_cal_cplx_data_n_153;
  wire u_ddr_cal_cplx_data_n_154;
  wire u_ddr_cal_cplx_data_n_155;
  wire u_ddr_cal_cplx_data_n_156;
  wire u_ddr_cal_cplx_data_n_157;
  wire u_ddr_cal_cplx_data_n_158;
  wire u_ddr_cal_cplx_data_n_159;
  wire u_ddr_cal_cplx_data_n_16;
  wire u_ddr_cal_cplx_data_n_160;
  wire u_ddr_cal_cplx_data_n_161;
  wire u_ddr_cal_cplx_data_n_162;
  wire u_ddr_cal_cplx_data_n_163;
  wire u_ddr_cal_cplx_data_n_164;
  wire u_ddr_cal_cplx_data_n_165;
  wire u_ddr_cal_cplx_data_n_166;
  wire u_ddr_cal_cplx_data_n_167;
  wire u_ddr_cal_cplx_data_n_168;
  wire u_ddr_cal_cplx_data_n_169;
  wire u_ddr_cal_cplx_data_n_17;
  wire u_ddr_cal_cplx_data_n_170;
  wire u_ddr_cal_cplx_data_n_171;
  wire u_ddr_cal_cplx_data_n_172;
  wire u_ddr_cal_cplx_data_n_173;
  wire u_ddr_cal_cplx_data_n_174;
  wire u_ddr_cal_cplx_data_n_175;
  wire u_ddr_cal_cplx_data_n_176;
  wire u_ddr_cal_cplx_data_n_177;
  wire u_ddr_cal_cplx_data_n_178;
  wire u_ddr_cal_cplx_data_n_179;
  wire u_ddr_cal_cplx_data_n_18;
  wire u_ddr_cal_cplx_data_n_180;
  wire u_ddr_cal_cplx_data_n_181;
  wire u_ddr_cal_cplx_data_n_182;
  wire u_ddr_cal_cplx_data_n_183;
  wire u_ddr_cal_cplx_data_n_184;
  wire u_ddr_cal_cplx_data_n_185;
  wire u_ddr_cal_cplx_data_n_186;
  wire u_ddr_cal_cplx_data_n_187;
  wire u_ddr_cal_cplx_data_n_188;
  wire u_ddr_cal_cplx_data_n_189;
  wire u_ddr_cal_cplx_data_n_19;
  wire u_ddr_cal_cplx_data_n_190;
  wire u_ddr_cal_cplx_data_n_191;
  wire u_ddr_cal_cplx_data_n_192;
  wire u_ddr_cal_cplx_data_n_193;
  wire u_ddr_cal_cplx_data_n_194;
  wire u_ddr_cal_cplx_data_n_195;
  wire u_ddr_cal_cplx_data_n_196;
  wire u_ddr_cal_cplx_data_n_197;
  wire u_ddr_cal_cplx_data_n_198;
  wire u_ddr_cal_cplx_data_n_199;
  wire u_ddr_cal_cplx_data_n_2;
  wire u_ddr_cal_cplx_data_n_20;
  wire u_ddr_cal_cplx_data_n_200;
  wire u_ddr_cal_cplx_data_n_201;
  wire u_ddr_cal_cplx_data_n_202;
  wire u_ddr_cal_cplx_data_n_203;
  wire u_ddr_cal_cplx_data_n_204;
  wire u_ddr_cal_cplx_data_n_205;
  wire u_ddr_cal_cplx_data_n_206;
  wire u_ddr_cal_cplx_data_n_207;
  wire u_ddr_cal_cplx_data_n_208;
  wire u_ddr_cal_cplx_data_n_209;
  wire u_ddr_cal_cplx_data_n_21;
  wire u_ddr_cal_cplx_data_n_210;
  wire u_ddr_cal_cplx_data_n_211;
  wire u_ddr_cal_cplx_data_n_212;
  wire u_ddr_cal_cplx_data_n_213;
  wire u_ddr_cal_cplx_data_n_214;
  wire u_ddr_cal_cplx_data_n_215;
  wire u_ddr_cal_cplx_data_n_216;
  wire u_ddr_cal_cplx_data_n_217;
  wire u_ddr_cal_cplx_data_n_218;
  wire u_ddr_cal_cplx_data_n_219;
  wire u_ddr_cal_cplx_data_n_22;
  wire u_ddr_cal_cplx_data_n_220;
  wire u_ddr_cal_cplx_data_n_221;
  wire u_ddr_cal_cplx_data_n_222;
  wire u_ddr_cal_cplx_data_n_223;
  wire u_ddr_cal_cplx_data_n_224;
  wire u_ddr_cal_cplx_data_n_225;
  wire u_ddr_cal_cplx_data_n_226;
  wire u_ddr_cal_cplx_data_n_227;
  wire u_ddr_cal_cplx_data_n_228;
  wire u_ddr_cal_cplx_data_n_229;
  wire u_ddr_cal_cplx_data_n_23;
  wire u_ddr_cal_cplx_data_n_230;
  wire u_ddr_cal_cplx_data_n_231;
  wire u_ddr_cal_cplx_data_n_232;
  wire u_ddr_cal_cplx_data_n_233;
  wire u_ddr_cal_cplx_data_n_234;
  wire u_ddr_cal_cplx_data_n_235;
  wire u_ddr_cal_cplx_data_n_236;
  wire u_ddr_cal_cplx_data_n_237;
  wire u_ddr_cal_cplx_data_n_238;
  wire u_ddr_cal_cplx_data_n_239;
  wire u_ddr_cal_cplx_data_n_24;
  wire u_ddr_cal_cplx_data_n_240;
  wire u_ddr_cal_cplx_data_n_241;
  wire u_ddr_cal_cplx_data_n_242;
  wire u_ddr_cal_cplx_data_n_243;
  wire u_ddr_cal_cplx_data_n_244;
  wire u_ddr_cal_cplx_data_n_245;
  wire u_ddr_cal_cplx_data_n_246;
  wire u_ddr_cal_cplx_data_n_247;
  wire u_ddr_cal_cplx_data_n_248;
  wire u_ddr_cal_cplx_data_n_249;
  wire u_ddr_cal_cplx_data_n_25;
  wire u_ddr_cal_cplx_data_n_250;
  wire u_ddr_cal_cplx_data_n_251;
  wire u_ddr_cal_cplx_data_n_252;
  wire u_ddr_cal_cplx_data_n_253;
  wire u_ddr_cal_cplx_data_n_254;
  wire u_ddr_cal_cplx_data_n_255;
  wire u_ddr_cal_cplx_data_n_256;
  wire u_ddr_cal_cplx_data_n_257;
  wire u_ddr_cal_cplx_data_n_258;
  wire u_ddr_cal_cplx_data_n_259;
  wire u_ddr_cal_cplx_data_n_26;
  wire u_ddr_cal_cplx_data_n_260;
  wire u_ddr_cal_cplx_data_n_261;
  wire u_ddr_cal_cplx_data_n_262;
  wire u_ddr_cal_cplx_data_n_263;
  wire u_ddr_cal_cplx_data_n_264;
  wire u_ddr_cal_cplx_data_n_265;
  wire u_ddr_cal_cplx_data_n_266;
  wire u_ddr_cal_cplx_data_n_267;
  wire u_ddr_cal_cplx_data_n_268;
  wire u_ddr_cal_cplx_data_n_269;
  wire u_ddr_cal_cplx_data_n_27;
  wire u_ddr_cal_cplx_data_n_270;
  wire u_ddr_cal_cplx_data_n_271;
  wire u_ddr_cal_cplx_data_n_272;
  wire u_ddr_cal_cplx_data_n_273;
  wire u_ddr_cal_cplx_data_n_274;
  wire u_ddr_cal_cplx_data_n_275;
  wire u_ddr_cal_cplx_data_n_276;
  wire u_ddr_cal_cplx_data_n_277;
  wire u_ddr_cal_cplx_data_n_278;
  wire u_ddr_cal_cplx_data_n_279;
  wire u_ddr_cal_cplx_data_n_28;
  wire u_ddr_cal_cplx_data_n_280;
  wire u_ddr_cal_cplx_data_n_281;
  wire u_ddr_cal_cplx_data_n_282;
  wire u_ddr_cal_cplx_data_n_283;
  wire u_ddr_cal_cplx_data_n_284;
  wire u_ddr_cal_cplx_data_n_285;
  wire u_ddr_cal_cplx_data_n_286;
  wire u_ddr_cal_cplx_data_n_287;
  wire u_ddr_cal_cplx_data_n_288;
  wire u_ddr_cal_cplx_data_n_289;
  wire u_ddr_cal_cplx_data_n_29;
  wire u_ddr_cal_cplx_data_n_290;
  wire u_ddr_cal_cplx_data_n_291;
  wire u_ddr_cal_cplx_data_n_292;
  wire u_ddr_cal_cplx_data_n_293;
  wire u_ddr_cal_cplx_data_n_294;
  wire u_ddr_cal_cplx_data_n_295;
  wire u_ddr_cal_cplx_data_n_296;
  wire u_ddr_cal_cplx_data_n_297;
  wire u_ddr_cal_cplx_data_n_298;
  wire u_ddr_cal_cplx_data_n_299;
  wire u_ddr_cal_cplx_data_n_3;
  wire u_ddr_cal_cplx_data_n_30;
  wire u_ddr_cal_cplx_data_n_300;
  wire u_ddr_cal_cplx_data_n_301;
  wire u_ddr_cal_cplx_data_n_302;
  wire u_ddr_cal_cplx_data_n_303;
  wire u_ddr_cal_cplx_data_n_304;
  wire u_ddr_cal_cplx_data_n_305;
  wire u_ddr_cal_cplx_data_n_306;
  wire u_ddr_cal_cplx_data_n_307;
  wire u_ddr_cal_cplx_data_n_308;
  wire u_ddr_cal_cplx_data_n_309;
  wire u_ddr_cal_cplx_data_n_31;
  wire u_ddr_cal_cplx_data_n_310;
  wire u_ddr_cal_cplx_data_n_311;
  wire u_ddr_cal_cplx_data_n_312;
  wire u_ddr_cal_cplx_data_n_313;
  wire u_ddr_cal_cplx_data_n_314;
  wire u_ddr_cal_cplx_data_n_315;
  wire u_ddr_cal_cplx_data_n_316;
  wire u_ddr_cal_cplx_data_n_317;
  wire u_ddr_cal_cplx_data_n_318;
  wire u_ddr_cal_cplx_data_n_319;
  wire u_ddr_cal_cplx_data_n_32;
  wire u_ddr_cal_cplx_data_n_320;
  wire u_ddr_cal_cplx_data_n_321;
  wire u_ddr_cal_cplx_data_n_322;
  wire u_ddr_cal_cplx_data_n_323;
  wire u_ddr_cal_cplx_data_n_324;
  wire u_ddr_cal_cplx_data_n_325;
  wire u_ddr_cal_cplx_data_n_326;
  wire u_ddr_cal_cplx_data_n_327;
  wire u_ddr_cal_cplx_data_n_328;
  wire u_ddr_cal_cplx_data_n_329;
  wire u_ddr_cal_cplx_data_n_33;
  wire u_ddr_cal_cplx_data_n_330;
  wire u_ddr_cal_cplx_data_n_331;
  wire u_ddr_cal_cplx_data_n_332;
  wire u_ddr_cal_cplx_data_n_333;
  wire u_ddr_cal_cplx_data_n_334;
  wire u_ddr_cal_cplx_data_n_335;
  wire u_ddr_cal_cplx_data_n_336;
  wire u_ddr_cal_cplx_data_n_337;
  wire u_ddr_cal_cplx_data_n_338;
  wire u_ddr_cal_cplx_data_n_339;
  wire u_ddr_cal_cplx_data_n_34;
  wire u_ddr_cal_cplx_data_n_340;
  wire u_ddr_cal_cplx_data_n_341;
  wire u_ddr_cal_cplx_data_n_342;
  wire u_ddr_cal_cplx_data_n_343;
  wire u_ddr_cal_cplx_data_n_344;
  wire u_ddr_cal_cplx_data_n_345;
  wire u_ddr_cal_cplx_data_n_346;
  wire u_ddr_cal_cplx_data_n_347;
  wire u_ddr_cal_cplx_data_n_348;
  wire u_ddr_cal_cplx_data_n_349;
  wire u_ddr_cal_cplx_data_n_35;
  wire u_ddr_cal_cplx_data_n_350;
  wire u_ddr_cal_cplx_data_n_351;
  wire u_ddr_cal_cplx_data_n_352;
  wire u_ddr_cal_cplx_data_n_353;
  wire u_ddr_cal_cplx_data_n_354;
  wire u_ddr_cal_cplx_data_n_355;
  wire u_ddr_cal_cplx_data_n_356;
  wire u_ddr_cal_cplx_data_n_357;
  wire u_ddr_cal_cplx_data_n_358;
  wire u_ddr_cal_cplx_data_n_359;
  wire u_ddr_cal_cplx_data_n_36;
  wire u_ddr_cal_cplx_data_n_360;
  wire u_ddr_cal_cplx_data_n_361;
  wire u_ddr_cal_cplx_data_n_362;
  wire u_ddr_cal_cplx_data_n_363;
  wire u_ddr_cal_cplx_data_n_364;
  wire u_ddr_cal_cplx_data_n_365;
  wire u_ddr_cal_cplx_data_n_366;
  wire u_ddr_cal_cplx_data_n_367;
  wire u_ddr_cal_cplx_data_n_368;
  wire u_ddr_cal_cplx_data_n_369;
  wire u_ddr_cal_cplx_data_n_37;
  wire u_ddr_cal_cplx_data_n_370;
  wire u_ddr_cal_cplx_data_n_371;
  wire u_ddr_cal_cplx_data_n_372;
  wire u_ddr_cal_cplx_data_n_373;
  wire u_ddr_cal_cplx_data_n_374;
  wire u_ddr_cal_cplx_data_n_375;
  wire u_ddr_cal_cplx_data_n_376;
  wire u_ddr_cal_cplx_data_n_377;
  wire u_ddr_cal_cplx_data_n_378;
  wire u_ddr_cal_cplx_data_n_379;
  wire u_ddr_cal_cplx_data_n_38;
  wire u_ddr_cal_cplx_data_n_380;
  wire u_ddr_cal_cplx_data_n_381;
  wire u_ddr_cal_cplx_data_n_382;
  wire u_ddr_cal_cplx_data_n_383;
  wire u_ddr_cal_cplx_data_n_384;
  wire u_ddr_cal_cplx_data_n_385;
  wire u_ddr_cal_cplx_data_n_386;
  wire u_ddr_cal_cplx_data_n_387;
  wire u_ddr_cal_cplx_data_n_388;
  wire u_ddr_cal_cplx_data_n_389;
  wire u_ddr_cal_cplx_data_n_39;
  wire u_ddr_cal_cplx_data_n_390;
  wire u_ddr_cal_cplx_data_n_391;
  wire u_ddr_cal_cplx_data_n_392;
  wire u_ddr_cal_cplx_data_n_393;
  wire u_ddr_cal_cplx_data_n_394;
  wire u_ddr_cal_cplx_data_n_395;
  wire u_ddr_cal_cplx_data_n_396;
  wire u_ddr_cal_cplx_data_n_397;
  wire u_ddr_cal_cplx_data_n_398;
  wire u_ddr_cal_cplx_data_n_399;
  wire u_ddr_cal_cplx_data_n_4;
  wire u_ddr_cal_cplx_data_n_40;
  wire u_ddr_cal_cplx_data_n_400;
  wire u_ddr_cal_cplx_data_n_401;
  wire u_ddr_cal_cplx_data_n_402;
  wire u_ddr_cal_cplx_data_n_403;
  wire u_ddr_cal_cplx_data_n_404;
  wire u_ddr_cal_cplx_data_n_405;
  wire u_ddr_cal_cplx_data_n_406;
  wire u_ddr_cal_cplx_data_n_407;
  wire u_ddr_cal_cplx_data_n_408;
  wire u_ddr_cal_cplx_data_n_409;
  wire u_ddr_cal_cplx_data_n_41;
  wire u_ddr_cal_cplx_data_n_410;
  wire u_ddr_cal_cplx_data_n_411;
  wire u_ddr_cal_cplx_data_n_412;
  wire u_ddr_cal_cplx_data_n_413;
  wire u_ddr_cal_cplx_data_n_414;
  wire u_ddr_cal_cplx_data_n_415;
  wire u_ddr_cal_cplx_data_n_416;
  wire u_ddr_cal_cplx_data_n_417;
  wire u_ddr_cal_cplx_data_n_418;
  wire u_ddr_cal_cplx_data_n_419;
  wire u_ddr_cal_cplx_data_n_42;
  wire u_ddr_cal_cplx_data_n_420;
  wire u_ddr_cal_cplx_data_n_421;
  wire u_ddr_cal_cplx_data_n_422;
  wire u_ddr_cal_cplx_data_n_423;
  wire u_ddr_cal_cplx_data_n_424;
  wire u_ddr_cal_cplx_data_n_425;
  wire u_ddr_cal_cplx_data_n_426;
  wire u_ddr_cal_cplx_data_n_427;
  wire u_ddr_cal_cplx_data_n_428;
  wire u_ddr_cal_cplx_data_n_429;
  wire u_ddr_cal_cplx_data_n_43;
  wire u_ddr_cal_cplx_data_n_430;
  wire u_ddr_cal_cplx_data_n_431;
  wire u_ddr_cal_cplx_data_n_432;
  wire u_ddr_cal_cplx_data_n_433;
  wire u_ddr_cal_cplx_data_n_434;
  wire u_ddr_cal_cplx_data_n_435;
  wire u_ddr_cal_cplx_data_n_436;
  wire u_ddr_cal_cplx_data_n_437;
  wire u_ddr_cal_cplx_data_n_438;
  wire u_ddr_cal_cplx_data_n_439;
  wire u_ddr_cal_cplx_data_n_44;
  wire u_ddr_cal_cplx_data_n_440;
  wire u_ddr_cal_cplx_data_n_441;
  wire u_ddr_cal_cplx_data_n_442;
  wire u_ddr_cal_cplx_data_n_443;
  wire u_ddr_cal_cplx_data_n_444;
  wire u_ddr_cal_cplx_data_n_445;
  wire u_ddr_cal_cplx_data_n_446;
  wire u_ddr_cal_cplx_data_n_447;
  wire u_ddr_cal_cplx_data_n_448;
  wire u_ddr_cal_cplx_data_n_449;
  wire u_ddr_cal_cplx_data_n_45;
  wire u_ddr_cal_cplx_data_n_450;
  wire u_ddr_cal_cplx_data_n_451;
  wire u_ddr_cal_cplx_data_n_452;
  wire u_ddr_cal_cplx_data_n_453;
  wire u_ddr_cal_cplx_data_n_454;
  wire u_ddr_cal_cplx_data_n_455;
  wire u_ddr_cal_cplx_data_n_456;
  wire u_ddr_cal_cplx_data_n_457;
  wire u_ddr_cal_cplx_data_n_458;
  wire u_ddr_cal_cplx_data_n_459;
  wire u_ddr_cal_cplx_data_n_46;
  wire u_ddr_cal_cplx_data_n_460;
  wire u_ddr_cal_cplx_data_n_461;
  wire u_ddr_cal_cplx_data_n_462;
  wire u_ddr_cal_cplx_data_n_463;
  wire u_ddr_cal_cplx_data_n_464;
  wire u_ddr_cal_cplx_data_n_465;
  wire u_ddr_cal_cplx_data_n_466;
  wire u_ddr_cal_cplx_data_n_467;
  wire u_ddr_cal_cplx_data_n_468;
  wire u_ddr_cal_cplx_data_n_469;
  wire u_ddr_cal_cplx_data_n_47;
  wire u_ddr_cal_cplx_data_n_470;
  wire u_ddr_cal_cplx_data_n_471;
  wire u_ddr_cal_cplx_data_n_472;
  wire u_ddr_cal_cplx_data_n_473;
  wire u_ddr_cal_cplx_data_n_474;
  wire u_ddr_cal_cplx_data_n_475;
  wire u_ddr_cal_cplx_data_n_476;
  wire u_ddr_cal_cplx_data_n_477;
  wire u_ddr_cal_cplx_data_n_478;
  wire u_ddr_cal_cplx_data_n_479;
  wire u_ddr_cal_cplx_data_n_48;
  wire u_ddr_cal_cplx_data_n_480;
  wire u_ddr_cal_cplx_data_n_481;
  wire u_ddr_cal_cplx_data_n_482;
  wire u_ddr_cal_cplx_data_n_483;
  wire u_ddr_cal_cplx_data_n_484;
  wire u_ddr_cal_cplx_data_n_485;
  wire u_ddr_cal_cplx_data_n_486;
  wire u_ddr_cal_cplx_data_n_487;
  wire u_ddr_cal_cplx_data_n_488;
  wire u_ddr_cal_cplx_data_n_489;
  wire u_ddr_cal_cplx_data_n_49;
  wire u_ddr_cal_cplx_data_n_490;
  wire u_ddr_cal_cplx_data_n_491;
  wire u_ddr_cal_cplx_data_n_492;
  wire u_ddr_cal_cplx_data_n_493;
  wire u_ddr_cal_cplx_data_n_494;
  wire u_ddr_cal_cplx_data_n_495;
  wire u_ddr_cal_cplx_data_n_496;
  wire u_ddr_cal_cplx_data_n_497;
  wire u_ddr_cal_cplx_data_n_498;
  wire u_ddr_cal_cplx_data_n_499;
  wire u_ddr_cal_cplx_data_n_5;
  wire u_ddr_cal_cplx_data_n_50;
  wire u_ddr_cal_cplx_data_n_500;
  wire u_ddr_cal_cplx_data_n_501;
  wire u_ddr_cal_cplx_data_n_502;
  wire u_ddr_cal_cplx_data_n_503;
  wire u_ddr_cal_cplx_data_n_504;
  wire u_ddr_cal_cplx_data_n_505;
  wire u_ddr_cal_cplx_data_n_506;
  wire u_ddr_cal_cplx_data_n_507;
  wire u_ddr_cal_cplx_data_n_508;
  wire u_ddr_cal_cplx_data_n_509;
  wire u_ddr_cal_cplx_data_n_51;
  wire u_ddr_cal_cplx_data_n_510;
  wire u_ddr_cal_cplx_data_n_511;
  wire u_ddr_cal_cplx_data_n_512;
  wire u_ddr_cal_cplx_data_n_513;
  wire u_ddr_cal_cplx_data_n_52;
  wire u_ddr_cal_cplx_data_n_53;
  wire u_ddr_cal_cplx_data_n_54;
  wire u_ddr_cal_cplx_data_n_55;
  wire u_ddr_cal_cplx_data_n_56;
  wire u_ddr_cal_cplx_data_n_57;
  wire u_ddr_cal_cplx_data_n_58;
  wire u_ddr_cal_cplx_data_n_59;
  wire u_ddr_cal_cplx_data_n_6;
  wire u_ddr_cal_cplx_data_n_60;
  wire u_ddr_cal_cplx_data_n_61;
  wire u_ddr_cal_cplx_data_n_62;
  wire u_ddr_cal_cplx_data_n_63;
  wire u_ddr_cal_cplx_data_n_64;
  wire u_ddr_cal_cplx_data_n_65;
  wire u_ddr_cal_cplx_data_n_66;
  wire u_ddr_cal_cplx_data_n_67;
  wire u_ddr_cal_cplx_data_n_68;
  wire u_ddr_cal_cplx_data_n_69;
  wire u_ddr_cal_cplx_data_n_7;
  wire u_ddr_cal_cplx_data_n_70;
  wire u_ddr_cal_cplx_data_n_71;
  wire u_ddr_cal_cplx_data_n_72;
  wire u_ddr_cal_cplx_data_n_73;
  wire u_ddr_cal_cplx_data_n_74;
  wire u_ddr_cal_cplx_data_n_75;
  wire u_ddr_cal_cplx_data_n_76;
  wire u_ddr_cal_cplx_data_n_77;
  wire u_ddr_cal_cplx_data_n_78;
  wire u_ddr_cal_cplx_data_n_79;
  wire u_ddr_cal_cplx_data_n_8;
  wire u_ddr_cal_cplx_data_n_80;
  wire u_ddr_cal_cplx_data_n_81;
  wire u_ddr_cal_cplx_data_n_82;
  wire u_ddr_cal_cplx_data_n_83;
  wire u_ddr_cal_cplx_data_n_84;
  wire u_ddr_cal_cplx_data_n_85;
  wire u_ddr_cal_cplx_data_n_86;
  wire u_ddr_cal_cplx_data_n_87;
  wire u_ddr_cal_cplx_data_n_88;
  wire u_ddr_cal_cplx_data_n_89;
  wire u_ddr_cal_cplx_data_n_9;
  wire u_ddr_cal_cplx_data_n_90;
  wire u_ddr_cal_cplx_data_n_91;
  wire u_ddr_cal_cplx_data_n_92;
  wire u_ddr_cal_cplx_data_n_93;
  wire u_ddr_cal_cplx_data_n_94;
  wire u_ddr_cal_cplx_data_n_95;
  wire u_ddr_cal_cplx_data_n_96;
  wire u_ddr_cal_cplx_data_n_97;
  wire u_ddr_cal_cplx_data_n_98;
  wire u_ddr_cal_cplx_data_n_99;
  wire [64:0]ub_cal_ADR;
  wire [8:0]ub_cal_BA;
  wire [0:0]ub_cal_BG;
  wire ub_ready;
  wire winAct;
  wire [1:0]winAct_reg;
  wire wrCAS_i_2_n_0;
  wire wrCAS_i_3_n_0;
  wire wrCAS_reg;
  wire wrCAS_reg_0;
  wire [0:0]wrCAS_reg_1;
  wire [0:0]wrCAS_reg_2;
  wire wrDataEn_pi;
  wire [7:4]\NLW_FSM_sequential_cplx_state_reg[2]_i_2_CO_UNCONNECTED ;
  wire [7:0]\NLW_FSM_sequential_cplx_state_reg[2]_i_2_O_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair517" *) 
  LUT3 #(
    .INIT(8'h15)) 
    \FSM_sequential_cplx_state[0]_i_1 
       (.I0(cplx_state[0]),
        .I1(cplx_state[3]),
        .I2(cplx_state[2]),
        .O(\FSM_sequential_cplx_state[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF2FF00000)) 
    \FSM_sequential_cplx_state[1]_i_1 
       (.I0(cplx_state_nxt2),
        .I1(\FSM_sequential_cplx_state[3]_i_3_n_0 ),
        .I2(cplx_state[1]),
        .I3(cplx_state[0]),
        .I4(\FSM_sequential_cplx_state[1]_i_2_n_0 ),
        .I5(\FSM_sequential_cplx_state[1]_i_3_n_0 ),
        .O(cplx_state_nxt__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair527" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \FSM_sequential_cplx_state[1]_i_2 
       (.I0(cplx_state[2]),
        .I1(cplx_state[3]),
        .O(\FSM_sequential_cplx_state[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF3FA0A000000000)) 
    \FSM_sequential_cplx_state[1]_i_3 
       (.I0(\FSM_sequential_cplx_state_reg[3]_0 ),
        .I1(\FSM_sequential_cplx_state_reg[1]_0 [1]),
        .I2(cplx_state[0]),
        .I3(\FSM_sequential_cplx_state[3]_i_3_n_0 ),
        .I4(cplx_state[1]),
        .I5(\FSM_sequential_cplx_state[1]_i_4_n_0 ),
        .O(\FSM_sequential_cplx_state[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair526" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_sequential_cplx_state[1]_i_4 
       (.I0(cplx_state[2]),
        .I1(cplx_state[3]),
        .O(\FSM_sequential_cplx_state[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000B000BFFFF000)) 
    \FSM_sequential_cplx_state[2]_i_1 
       (.I0(\FSM_sequential_cplx_state[3]_i_3_n_0 ),
        .I1(cplx_state_nxt2),
        .I2(cplx_state[1]),
        .I3(cplx_state[0]),
        .I4(cplx_state[2]),
        .I5(cplx_state[3]),
        .O(cplx_state_nxt__0[2]));
  LUT4 #(
    .INIT(16'h9009)) 
    \FSM_sequential_cplx_state[2]_i_10 
       (.I0(\FSM_sequential_cplx_state_reg[2]_i_2_0 ),
        .I1(cplx_loops_reg[1]),
        .I2(\FSM_sequential_cplx_state_reg[2]_i_2_1 ),
        .I3(cplx_loops_reg[0]),
        .O(\FSM_sequential_cplx_state[2]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_cplx_state[2]_i_3 
       (.I0(\FSM_sequential_cplx_state_reg[2]_i_2_6 ),
        .I1(cplx_loops_reg[6]),
        .O(\FSM_sequential_cplx_state[2]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \FSM_sequential_cplx_state[2]_i_4 
       (.I0(cplx_loops_reg[5]),
        .I1(\FSM_sequential_cplx_state_reg[2]_i_2_4 ),
        .I2(\FSM_sequential_cplx_state_reg[2]_i_2_5 ),
        .I3(cplx_loops_reg[4]),
        .O(\FSM_sequential_cplx_state[2]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \FSM_sequential_cplx_state[2]_i_5 
       (.I0(cplx_loops_reg[3]),
        .I1(\FSM_sequential_cplx_state_reg[2]_i_2_2 ),
        .I2(\FSM_sequential_cplx_state_reg[2]_i_2_3 ),
        .I3(cplx_loops_reg[2]),
        .O(\FSM_sequential_cplx_state[2]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \FSM_sequential_cplx_state[2]_i_6 
       (.I0(cplx_loops_reg[1]),
        .I1(\FSM_sequential_cplx_state_reg[2]_i_2_0 ),
        .I2(\FSM_sequential_cplx_state_reg[2]_i_2_1 ),
        .I3(cplx_loops_reg[0]),
        .O(\FSM_sequential_cplx_state[2]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \FSM_sequential_cplx_state[2]_i_7 
       (.I0(cplx_loops_reg[6]),
        .I1(\FSM_sequential_cplx_state_reg[2]_i_2_6 ),
        .O(\FSM_sequential_cplx_state[2]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \FSM_sequential_cplx_state[2]_i_8 
       (.I0(\FSM_sequential_cplx_state_reg[2]_i_2_4 ),
        .I1(cplx_loops_reg[5]),
        .I2(\FSM_sequential_cplx_state_reg[2]_i_2_5 ),
        .I3(cplx_loops_reg[4]),
        .O(\FSM_sequential_cplx_state[2]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \FSM_sequential_cplx_state[2]_i_9 
       (.I0(\FSM_sequential_cplx_state_reg[2]_i_2_2 ),
        .I1(cplx_loops_reg[3]),
        .I2(\FSM_sequential_cplx_state_reg[2]_i_2_3 ),
        .I3(cplx_loops_reg[2]),
        .O(\FSM_sequential_cplx_state[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h07770777377F377C)) 
    \FSM_sequential_cplx_state[3]_i_1 
       (.I0(\FSM_sequential_cplx_state[3]_i_3_n_0 ),
        .I1(cplx_state[0]),
        .I2(cplx_state[2]),
        .I3(cplx_state[3]),
        .I4(\FSM_sequential_cplx_state_reg[1]_0 [0]),
        .I5(cplx_state[1]),
        .O(\FSM_sequential_cplx_state[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00FF800000FF8030)) 
    \FSM_sequential_cplx_state[3]_i_2 
       (.I0(\FSM_sequential_cplx_state[3]_i_4_n_0 ),
        .I1(cplx_state[1]),
        .I2(cplx_state[0]),
        .I3(cplx_state[2]),
        .I4(cplx_state[3]),
        .I5(\FSM_sequential_cplx_state_reg[3]_0 ),
        .O(cplx_state_nxt__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair519" *) 
  LUT4 #(
    .INIT(16'hF7FF)) 
    \FSM_sequential_cplx_state[3]_i_3 
       (.I0(seq_state[2]),
        .I1(seq_state[3]),
        .I2(seq_state[1]),
        .I3(seq_state[0]),
        .O(\FSM_sequential_cplx_state[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair519" *) 
  LUT5 #(
    .INIT(32'hDFFFFFFF)) 
    \FSM_sequential_cplx_state[3]_i_4 
       (.I0(seq_state[0]),
        .I1(seq_state[1]),
        .I2(seq_state[3]),
        .I3(seq_state[2]),
        .I4(cplx_state_nxt2),
        .O(\FSM_sequential_cplx_state[3]_i_4_n_0 ));
  (* FSM_ENCODED_STATES = "RD_CAL_WR_WAIT_DONE:1001,RD_CAL_RD_START:1010,RD_CAL_WR_START:1000,UPDATE_LOGS:1100,WR_CAL_RD_WAIT_DONE:0111,WR_CAL_RD_START:0110,INIT:0001,IDLE:0000,WR_CAL_DM_WAIT_DONE:0101,WR_CAL_WR_WAIT_DONE:0011,WR_CAL_WR_START:0010,WR_CAL_DM_START:0100,RD_CAL_RD_WAIT_DONE:1011" *) 
  FDRE \FSM_sequential_cplx_state_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(\FSM_sequential_cplx_state[3]_i_1_n_0 ),
        .D(\FSM_sequential_cplx_state[0]_i_1_n_0 ),
        .Q(cplx_state[0]),
        .R(out));
  (* FSM_ENCODED_STATES = "RD_CAL_WR_WAIT_DONE:1001,RD_CAL_RD_START:1010,RD_CAL_WR_START:1000,UPDATE_LOGS:1100,WR_CAL_RD_WAIT_DONE:0111,WR_CAL_RD_START:0110,INIT:0001,IDLE:0000,WR_CAL_DM_WAIT_DONE:0101,WR_CAL_WR_WAIT_DONE:0011,WR_CAL_WR_START:0010,WR_CAL_DM_START:0100,RD_CAL_RD_WAIT_DONE:1011" *) 
  FDRE \FSM_sequential_cplx_state_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(\FSM_sequential_cplx_state[3]_i_1_n_0 ),
        .D(cplx_state_nxt__0[1]),
        .Q(cplx_state[1]),
        .R(out));
  (* FSM_ENCODED_STATES = "RD_CAL_WR_WAIT_DONE:1001,RD_CAL_RD_START:1010,RD_CAL_WR_START:1000,UPDATE_LOGS:1100,WR_CAL_RD_WAIT_DONE:0111,WR_CAL_RD_START:0110,INIT:0001,IDLE:0000,WR_CAL_DM_WAIT_DONE:0101,WR_CAL_WR_WAIT_DONE:0011,WR_CAL_WR_START:0010,WR_CAL_DM_START:0100,RD_CAL_RD_WAIT_DONE:1011" *) 
  FDRE \FSM_sequential_cplx_state_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(\FSM_sequential_cplx_state[3]_i_1_n_0 ),
        .D(cplx_state_nxt__0[2]),
        .Q(cplx_state[2]),
        .R(out));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY8 \FSM_sequential_cplx_state_reg[2]_i_2 
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({\NLW_FSM_sequential_cplx_state_reg[2]_i_2_CO_UNCONNECTED [7:4],cplx_state_nxt2,\FSM_sequential_cplx_state_reg[2]_i_2_n_5 ,\FSM_sequential_cplx_state_reg[2]_i_2_n_6 ,\FSM_sequential_cplx_state_reg[2]_i_2_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,\FSM_sequential_cplx_state[2]_i_3_n_0 ,\FSM_sequential_cplx_state[2]_i_4_n_0 ,\FSM_sequential_cplx_state[2]_i_5_n_0 ,\FSM_sequential_cplx_state[2]_i_6_n_0 }),
        .O(\NLW_FSM_sequential_cplx_state_reg[2]_i_2_O_UNCONNECTED [7:0]),
        .S({1'b0,1'b0,1'b0,1'b0,\FSM_sequential_cplx_state[2]_i_7_n_0 ,\FSM_sequential_cplx_state[2]_i_8_n_0 ,\FSM_sequential_cplx_state[2]_i_9_n_0 ,\FSM_sequential_cplx_state[2]_i_10_n_0 }));
  (* FSM_ENCODED_STATES = "RD_CAL_WR_WAIT_DONE:1001,RD_CAL_RD_START:1010,RD_CAL_WR_START:1000,UPDATE_LOGS:1100,WR_CAL_RD_WAIT_DONE:0111,WR_CAL_RD_START:0110,INIT:0001,IDLE:0000,WR_CAL_DM_WAIT_DONE:0101,WR_CAL_WR_WAIT_DONE:0011,WR_CAL_WR_START:0010,WR_CAL_DM_START:0100,RD_CAL_RD_WAIT_DONE:1011" *) 
  FDRE \FSM_sequential_cplx_state_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(\FSM_sequential_cplx_state[3]_i_1_n_0 ),
        .D(cplx_state_nxt__0[3]),
        .Q(cplx_state[3]),
        .R(out));
  LUT6 #(
    .INIT(64'hFFFFFFFFD9510000)) 
    \FSM_sequential_seq_state[0]_i_1 
       (.I0(seq_state[2]),
        .I1(seq_state[0]),
        .I2(\FSM_sequential_seq_state[0]_i_2_n_0 ),
        .I3(seq_state[1]),
        .I4(seq_state[3]),
        .I5(\FSM_sequential_seq_state[0]_i_3_n_0 ),
        .O(seq_state_nxt[0]));
  LUT6 #(
    .INIT(64'h0000000040000000)) 
    \FSM_sequential_seq_state[0]_i_2 
       (.I0(\FSM_sequential_seq_state[3]_i_4_n_0 ),
        .I1(seq_row_reg[2]),
        .I2(seq_row_reg[1]),
        .I3(seq_row_reg[0]),
        .I4(seq_state[1]),
        .I5(\FSM_sequential_seq_state[0]_i_4_n_0 ),
        .O(\FSM_sequential_seq_state[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000003F2E00FF)) 
    \FSM_sequential_seq_state[0]_i_3 
       (.I0(\FSM_sequential_seq_state[1]_i_4_n_0 ),
        .I1(seq_state[1]),
        .I2(\FSM_sequential_seq_state[2]_i_2_n_0 ),
        .I3(seq_state[0]),
        .I4(seq_state[2]),
        .I5(seq_state[3]),
        .O(\FSM_sequential_seq_state[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair597" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \FSM_sequential_seq_state[0]_i_4 
       (.I0(seq_bg[0]),
        .I1(seq_bg[1]),
        .O(\FSM_sequential_seq_state[0]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h752A757A)) 
    \FSM_sequential_seq_state[1]_i_2 
       (.I0(seq_state[1]),
        .I1(\FSM_sequential_seq_state[2]_i_2_n_0 ),
        .I2(seq_state[2]),
        .I3(seq_state[0]),
        .I4(\FSM_sequential_seq_state[1]_i_4_n_0 ),
        .O(\FSM_sequential_seq_state[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF1FF0FF0)) 
    \FSM_sequential_seq_state[1]_i_3 
       (.I0(\FSM_sequential_seq_state[1]_i_5_n_0 ),
        .I1(\FSM_sequential_seq_state[1]_i_4_n_0 ),
        .I2(seq_state[2]),
        .I3(seq_state[0]),
        .I4(seq_state[1]),
        .O(\FSM_sequential_seq_state[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair597" *) 
  LUT3 #(
    .INIT(8'h07)) 
    \FSM_sequential_seq_state[1]_i_4 
       (.I0(seq_bg[1]),
        .I1(seq_bg[0]),
        .I2(\FSM_sequential_seq_state[3]_i_4_n_0 ),
        .O(\FSM_sequential_seq_state[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair535" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \FSM_sequential_seq_state[1]_i_5 
       (.I0(seq_row_reg[0]),
        .I1(seq_row_reg[1]),
        .I2(seq_row_reg[2]),
        .I3(\FSM_sequential_seq_state[3]_i_4_n_0 ),
        .O(\FSM_sequential_seq_state[1]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair521" *) 
  LUT5 #(
    .INIT(32'h8080D1C0)) 
    \FSM_sequential_seq_state[2]_i_1 
       (.I0(seq_state[3]),
        .I1(seq_state[0]),
        .I2(seq_state[1]),
        .I3(seq_state[2]),
        .I4(\FSM_sequential_seq_state[2]_i_2_n_0 ),
        .O(seq_state_nxt[2]));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    \FSM_sequential_seq_state[2]_i_2 
       (.I0(burst_count[2]),
        .I1(burst_count[4]),
        .I2(burst_count[1]),
        .I3(burst_count[3]),
        .I4(\burst_count[1]_i_2_n_0 ),
        .I5(\burst_count[2]_i_3_n_0 ),
        .O(\FSM_sequential_seq_state[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0AA8AAAAAAAAAAAA)) 
    \FSM_sequential_seq_state[3]_i_1 
       (.I0(\FSM_sequential_seq_state[3]_i_3_n_0 ),
        .I1(seq_state[2]),
        .I2(seq_state[0]),
        .I3(seq_state[1]),
        .I4(seq_state[3]),
        .I5(\FSM_sequential_seq_state[3]_i_4_n_0 ),
        .O(\FSM_sequential_seq_state[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h1F80)) 
    \FSM_sequential_seq_state[3]_i_2 
       (.I0(seq_state[1]),
        .I1(seq_state[0]),
        .I2(seq_state[2]),
        .I3(seq_state[3]),
        .O(seq_state_nxt[3]));
  LUT6 #(
    .INIT(64'hFFFFFFFFF4FCF0FF)) 
    \FSM_sequential_seq_state[3]_i_3 
       (.I0(\FSM_sequential_seq_state[3]_i_4_n_0 ),
        .I1(\FSM_sequential_seq_state[3]_i_5_n_0 ),
        .I2(seq_state[3]),
        .I3(\FSM_sequential_seq_state[3]_i_6_n_0 ),
        .I4(seq_state[2]),
        .I5(\FSM_sequential_seq_state[3]_i_7_n_0 ),
        .O(\FSM_sequential_seq_state[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair516" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \FSM_sequential_seq_state[3]_i_4 
       (.I0(\seq_timer_reg_n_0_[0] ),
        .I1(\seq_timer_reg_n_0_[3] ),
        .I2(\seq_timer_reg_n_0_[4] ),
        .I3(\seq_timer_reg_n_0_[1] ),
        .I4(\seq_timer_reg_n_0_[2] ),
        .O(\FSM_sequential_seq_state[3]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hC8FFFFFF)) 
    \FSM_sequential_seq_state[3]_i_5 
       (.I0(\burst_count[2]_i_3_n_0 ),
        .I1(\burst_count[3]_i_5_n_0 ),
        .I2(cas_is_bursty),
        .I3(seq_state[0]),
        .I4(seq_state[1]),
        .O(\FSM_sequential_seq_state[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair528" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_sequential_seq_state[3]_i_6 
       (.I0(seq_state[0]),
        .I1(seq_state[1]),
        .O(\FSM_sequential_seq_state[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair517" *) 
  LUT5 #(
    .INIT(32'h00111110)) 
    \FSM_sequential_seq_state[3]_i_7 
       (.I0(seq_state[2]),
        .I1(cplx_state[0]),
        .I2(cplx_state[1]),
        .I3(cplx_state[3]),
        .I4(cplx_state[2]),
        .O(\FSM_sequential_seq_state[3]_i_7_n_0 ));
  (* FSM_ENCODED_STATES = "SEQ_ACT_WAIT:0100,SEQ_ISSUE_ACT:0011,SEQ_INIT_COL:0010,SEQ_INC_PREA:1100,SEQ_PREA_WAIT:1011,SEQ_ISSUE_PREA:1010,SEQ_INIT_PREA:1001,SEQ_INIT_ROW:0001,SEQ_IDLE:0000,SEQ_ISSUE_CAS:0111,SEQ_CAS_WAIT:1000,SEQ_INIT_BG:0110,SEQ_GAP_WAIT:1111,SEQ_DONE:1101,SEQ_INC_ROW:1110,SEQ_INC_BG:0101" *) 
  FDRE \FSM_sequential_seq_state_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(\FSM_sequential_seq_state[3]_i_1_n_0 ),
        .D(seq_state_nxt[0]),
        .Q(seq_state[0]),
        .R(out));
  (* FSM_ENCODED_STATES = "SEQ_ACT_WAIT:0100,SEQ_ISSUE_ACT:0011,SEQ_INIT_COL:0010,SEQ_INC_PREA:1100,SEQ_PREA_WAIT:1011,SEQ_ISSUE_PREA:1010,SEQ_INIT_PREA:1001,SEQ_INIT_ROW:0001,SEQ_IDLE:0000,SEQ_ISSUE_CAS:0111,SEQ_CAS_WAIT:1000,SEQ_INIT_BG:0110,SEQ_GAP_WAIT:1111,SEQ_DONE:1101,SEQ_INC_ROW:1110,SEQ_INC_BG:0101" *) 
  FDRE \FSM_sequential_seq_state_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(\FSM_sequential_seq_state[3]_i_1_n_0 ),
        .D(seq_state_nxt[1]),
        .Q(seq_state[1]),
        .R(out));
  MUXF7 \FSM_sequential_seq_state_reg[1]_i_1 
       (.I0(\FSM_sequential_seq_state[1]_i_2_n_0 ),
        .I1(\FSM_sequential_seq_state[1]_i_3_n_0 ),
        .O(seq_state_nxt[1]),
        .S(seq_state[3]));
  (* FSM_ENCODED_STATES = "SEQ_ACT_WAIT:0100,SEQ_ISSUE_ACT:0011,SEQ_INIT_COL:0010,SEQ_INC_PREA:1100,SEQ_PREA_WAIT:1011,SEQ_ISSUE_PREA:1010,SEQ_INIT_PREA:1001,SEQ_INIT_ROW:0001,SEQ_IDLE:0000,SEQ_ISSUE_CAS:0111,SEQ_CAS_WAIT:1000,SEQ_INIT_BG:0110,SEQ_GAP_WAIT:1111,SEQ_DONE:1101,SEQ_INC_ROW:1110,SEQ_INC_BG:0101" *) 
  FDRE \FSM_sequential_seq_state_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(\FSM_sequential_seq_state[3]_i_1_n_0 ),
        .D(seq_state_nxt[2]),
        .Q(seq_state[2]),
        .R(out));
  (* FSM_ENCODED_STATES = "SEQ_ACT_WAIT:0100,SEQ_ISSUE_ACT:0011,SEQ_INIT_COL:0010,SEQ_INC_PREA:1100,SEQ_PREA_WAIT:1011,SEQ_ISSUE_PREA:1010,SEQ_INIT_PREA:1001,SEQ_INIT_ROW:0001,SEQ_IDLE:0000,SEQ_ISSUE_CAS:0111,SEQ_CAS_WAIT:1000,SEQ_INIT_BG:0110,SEQ_GAP_WAIT:1111,SEQ_DONE:1101,SEQ_INC_ROW:1110,SEQ_INC_BG:0101" *) 
  FDRE \FSM_sequential_seq_state_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(\FSM_sequential_seq_state[3]_i_1_n_0 ),
        .D(seq_state_nxt[3]),
        .Q(seq_state[3]),
        .R(out));
  LUT6 #(
    .INIT(64'h4F4F4F7F7F7F4F7F)) 
    \addr_dec_to_mb_data[0]_i_24 
       (.I0(gt_data_ready_flag),
        .I1(io_address[1]),
        .I2(io_address[3]),
        .I3(cplx_err_log30[0]),
        .I4(io_address[0]),
        .I5(cplx_err_log74[0]),
        .O(\addr_dec_to_mb_data[0]_i_24_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \addr_dec_to_mb_data[0]_i_35 
       (.I0(gt_data_ready_flag),
        .I1(\addr_dec_to_mb_data[0]_i_43_n_0 ),
        .I2(io_address[2]),
        .I3(io_address[1]),
        .I4(cplx_status),
        .O(gt_data_ready_flag_reg));
  LUT3 #(
    .INIT(8'hB8)) 
    \addr_dec_to_mb_data[0]_i_43 
       (.I0(cplx_err_log74[0]),
        .I1(io_address[0]),
        .I2(cplx_err_log30[0]),
        .O(\addr_dec_to_mb_data[0]_i_43_n_0 ));
  LUT6 #(
    .INIT(64'hFF0F4F0F4F0F4F0F)) 
    \addr_dec_to_mb_data[0]_i_9 
       (.I0(\addr_dec_to_mb_data[0]_i_24_n_0 ),
        .I1(io_address[4]),
        .I2(\addr_dec_to_mb_data[0]_i_2 ),
        .I3(\addr_dec_to_mb_data[0]_i_2_0 ),
        .I4(io_address[5]),
        .I5(\addr_dec_to_mb_data[0]_i_2_1 ),
        .O(\SYNC[20].sync_reg_reg[1] ));
  LUT6 #(
    .INIT(64'hB800FFFFB800B800)) 
    \addr_dec_to_mb_data[12]_i_3 
       (.I0(cplx_err_log74[12]),
        .I1(io_address[0]),
        .I2(cplx_err_log30[12]),
        .I3(\addr_dec_to_mb_data_reg[19] ),
        .I4(\addr_dec_to_mb_data_reg[12] ),
        .I5(\addr_dec_to_mb_data_reg[12]_0 ),
        .O(\cplx_error_accum_reg[44]_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \addr_dec_to_mb_data[14]_i_4 
       (.I0(cplx_err_log30[14]),
        .I1(io_address[0]),
        .I2(cplx_err_log74[14]),
        .I3(\addr_dec_to_mb_data_reg[15] ),
        .O(\cplx_error_accum_reg[14]_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \addr_dec_to_mb_data[15]_i_2 
       (.I0(cplx_err_log30[15]),
        .I1(io_address[0]),
        .I2(cplx_err_log74[15]),
        .I3(\addr_dec_to_mb_data_reg[15] ),
        .O(\cplx_error_accum_reg[15]_0 ));
  LUT4 #(
    .INIT(16'h1DFF)) 
    \addr_dec_to_mb_data[19]_i_3 
       (.I0(cplx_err_log30[19]),
        .I1(io_address[0]),
        .I2(cplx_err_log74[19]),
        .I3(\addr_dec_to_mb_data_reg[19] ),
        .O(\cplx_error_accum_reg[19]_0 ));
  LUT6 #(
    .INIT(64'hFFA8FFAB00A800AB)) 
    \burst_count[0]_i_1 
       (.I0(\burst_count[0]_i_2_n_0 ),
        .I1(burst_index_reg[4]),
        .I2(burst_index_reg[3]),
        .I3(\burst_count[3]_i_2_n_0 ),
        .I4(burst_index_reg[0]),
        .I5(\burst_count[0]_i_3_n_0 ),
        .O(\burst_count[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h51115111403C003C)) 
    \burst_count[0]_i_2 
       (.I0(burst_index_reg[4]),
        .I1(burst_index_reg[0]),
        .I2(burst_index_reg[2]),
        .I3(burst_index_reg[1]),
        .I4(\burst_count[0]_i_3_n_0 ),
        .I5(burst_index_reg[3]),
        .O(\burst_count[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair520" *) 
  LUT5 #(
    .INIT(32'h9AAAAAAA)) 
    \burst_count[0]_i_3 
       (.I0(burst_count[0]),
        .I1(seq_state[3]),
        .I2(seq_state[2]),
        .I3(seq_state[0]),
        .I4(seq_state[1]),
        .O(\burst_count[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFA600)) 
    \burst_count[1]_i_1 
       (.I0(burst_count[1]),
        .I1(\burst_count[1]_i_2_n_0 ),
        .I2(burst_count[0]),
        .I3(\burst_count[4]_i_2_n_0 ),
        .I4(\burst_count[1]_i_3_n_0 ),
        .O(\burst_count[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair515" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \burst_count[1]_i_2 
       (.I0(seq_state[1]),
        .I1(seq_state[0]),
        .I2(seq_state[2]),
        .I3(seq_state[3]),
        .O(\burst_count[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FAEED926)) 
    \burst_count[1]_i_3 
       (.I0(burst_index_reg[3]),
        .I1(burst_index_reg[1]),
        .I2(burst_index_reg[2]),
        .I3(burst_index_reg[0]),
        .I4(burst_index_reg[4]),
        .I5(\burst_count[3]_i_2_n_0 ),
        .O(\burst_count[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFAAAAAAAAAA)) 
    \burst_count[2]_i_1 
       (.I0(\burst_count[2]_i_2_n_0 ),
        .I1(burst_index_reg[2]),
        .I2(\burst_count[2]_i_3_n_0 ),
        .I3(\burst_count[3]_i_2_n_0 ),
        .I4(burst_index_reg[4]),
        .I5(\burst_count[2]_i_4_n_0 ),
        .O(\burst_count[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1111101000505100)) 
    \burst_count[2]_i_2 
       (.I0(\burst_count[3]_i_2_n_0 ),
        .I1(burst_index_reg[4]),
        .I2(burst_index_reg[0]),
        .I3(burst_index_reg[2]),
        .I4(burst_index_reg[1]),
        .I5(burst_index_reg[3]),
        .O(\burst_count[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair514" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \burst_count[2]_i_3 
       (.I0(burst_index_reg[4]),
        .I1(burst_index_reg[0]),
        .I2(burst_index_reg[2]),
        .I3(burst_index_reg[1]),
        .I4(burst_index_reg[3]),
        .O(\burst_count[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF4FF44444F44)) 
    \burst_count[2]_i_4 
       (.I0(\burst_count[3]_i_2_n_0 ),
        .I1(\burst_count[2]_i_5_n_0 ),
        .I2(burst_count[1]),
        .I3(\burst_count[1]_i_2_n_0 ),
        .I4(burst_count[0]),
        .I5(burst_count[2]),
        .O(\burst_count[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair514" *) 
  LUT5 #(
    .INIT(32'hEA00FFFF)) 
    \burst_count[2]_i_5 
       (.I0(burst_index_reg[3]),
        .I1(burst_index_reg[1]),
        .I2(burst_index_reg[2]),
        .I3(burst_index_reg[4]),
        .I4(burst_index_reg[0]),
        .O(\burst_count[2]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h00002EE2)) 
    \burst_count[3]_i_1 
       (.I0(burst_index_reg[4]),
        .I1(\burst_count[3]_i_2_n_0 ),
        .I2(\burst_count[3]_i_3_n_0 ),
        .I3(burst_count[3]),
        .I4(\burst_count[3]_i_4_n_0 ),
        .O(\burst_count[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair515" *) 
  LUT5 #(
    .INIT(32'h0000FBDB)) 
    \burst_count[3]_i_2 
       (.I0(seq_state[3]),
        .I1(seq_state[1]),
        .I2(seq_state[0]),
        .I3(seq_state[2]),
        .I4(\burst_count[3]_i_5_n_0 ),
        .O(\burst_count[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0004)) 
    \burst_count[3]_i_3 
       (.I0(burst_count[0]),
        .I1(\burst_count[1]_i_2_n_0 ),
        .I2(burst_count[1]),
        .I3(burst_count[2]),
        .O(\burst_count[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000045450001)) 
    \burst_count[3]_i_4 
       (.I0(\burst_count[3]_i_2_n_0 ),
        .I1(burst_index_reg[3]),
        .I2(\burst_count[3]_i_6_n_0 ),
        .I3(burst_index_reg[0]),
        .I4(burst_index_reg[4]),
        .I5(\FSM_sequential_cplx_state_reg[3]_0 ),
        .O(\burst_count[3]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \burst_count[3]_i_5 
       (.I0(\burst_count[1]_i_2_n_0 ),
        .I1(burst_count[3]),
        .I2(burst_count[1]),
        .I3(burst_count[4]),
        .I4(burst_count[2]),
        .O(\burst_count[3]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \burst_count[3]_i_6 
       (.I0(burst_index_reg[1]),
        .I1(burst_index_reg[2]),
        .O(\burst_count[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA88888288)) 
    \burst_count[4]_i_1 
       (.I0(\burst_count[4]_i_2_n_0 ),
        .I1(burst_count[4]),
        .I2(burst_count[3]),
        .I3(\burst_count[4]_i_3_n_0 ),
        .I4(burst_count[2]),
        .I5(\burst_count[4]_i_4_n_0 ),
        .O(\burst_count[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFAAEAAA)) 
    \burst_count[4]_i_2 
       (.I0(\burst_count[3]_i_2_n_0 ),
        .I1(burst_index_reg[2]),
        .I2(burst_index_reg[1]),
        .I3(burst_index_reg[4]),
        .I4(burst_index_reg[3]),
        .O(\burst_count[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \burst_count[4]_i_3 
       (.I0(burst_count[1]),
        .I1(seq_state[1]),
        .I2(seq_state[0]),
        .I3(seq_state[2]),
        .I4(seq_state[3]),
        .I5(burst_count[0]),
        .O(\burst_count[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5555000040550055)) 
    \burst_count[4]_i_4 
       (.I0(\burst_count[3]_i_2_n_0 ),
        .I1(burst_index_reg[1]),
        .I2(burst_index_reg[2]),
        .I3(burst_index_reg[0]),
        .I4(burst_index_reg[4]),
        .I5(burst_index_reg[3]),
        .O(\burst_count[4]_i_4_n_0 ));
  FDRE \burst_count_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\burst_count[0]_i_1_n_0 ),
        .Q(burst_count[0]),
        .R(out));
  FDRE \burst_count_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\burst_count[1]_i_1_n_0 ),
        .Q(burst_count[1]),
        .R(out));
  FDRE \burst_count_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\burst_count[2]_i_1_n_0 ),
        .Q(burst_count[2]),
        .R(out));
  FDRE \burst_count_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\burst_count[3]_i_1_n_0 ),
        .Q(burst_count[3]),
        .R(out));
  FDRE \burst_count_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\burst_count[4]_i_1_n_0 ),
        .Q(burst_count[4]),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair596" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \burst_index[0]_i_1 
       (.I0(burst_index_reg[0]),
        .I1(\burst_count[3]_i_2_n_0 ),
        .O(\burst_index[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair596" *) 
  LUT3 #(
    .INIT(8'hA6)) 
    \burst_index[1]_i_1 
       (.I0(burst_index_reg[1]),
        .I1(burst_index_reg[0]),
        .I2(\burst_count[3]_i_2_n_0 ),
        .O(\burst_index[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair518" *) 
  LUT4 #(
    .INIT(16'h9AAA)) 
    \burst_index[2]_i_1 
       (.I0(burst_index_reg[2]),
        .I1(\burst_count[3]_i_2_n_0 ),
        .I2(burst_index_reg[0]),
        .I3(burst_index_reg[1]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair518" *) 
  LUT5 #(
    .INIT(32'hAAAA6AAA)) 
    \burst_index[3]_i_1 
       (.I0(burst_index_reg[3]),
        .I1(burst_index_reg[0]),
        .I2(burst_index_reg[2]),
        .I3(burst_index_reg[1]),
        .I4(\burst_count[3]_i_2_n_0 ),
        .O(\burst_index[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h9AAAAAAAAAAAAAAA)) 
    \burst_index[4]_i_1 
       (.I0(burst_index_reg[4]),
        .I1(\burst_count[3]_i_2_n_0 ),
        .I2(burst_index_reg[1]),
        .I3(burst_index_reg[2]),
        .I4(burst_index_reg[0]),
        .I5(burst_index_reg[3]),
        .O(p_0_in[4]));
  FDRE \burst_index_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\burst_index[0]_i_1_n_0 ),
        .Q(burst_index_reg[0]),
        .R(outstanding_reads));
  FDRE \burst_index_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\burst_index[1]_i_1_n_0 ),
        .Q(burst_index_reg[1]),
        .R(outstanding_reads));
  FDRE \burst_index_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(burst_index_reg[2]),
        .R(outstanding_reads));
  FDRE \burst_index_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\burst_index[3]_i_1_n_0 ),
        .Q(burst_index_reg[3]),
        .R(outstanding_reads));
  FDRE \burst_index_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(burst_index_reg[4]),
        .R(outstanding_reads));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF15)) 
    \cal_CS_n_pre[7]_i_1 
       (.I0(\cal_CS_n_pre_reg[0] ),
        .I1(extended_write_mode),
        .I2(D[2]),
        .I3(cplx_issue_cas_rd),
        .I4(cplx_issue_cas_wr),
        .I5(out),
        .O(SS));
  (* SOFT_HLUTNM = "soft_lutpair576" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[0]_i_1 
       (.I0(cplx_DMOut_n[56]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[7] [0]),
        .O(\cplx_DMOut_n_reg[63]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair574" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[10]_i_1 
       (.I0(cplx_DMOut_n[58]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[15] [2]),
        .O(\cplx_DMOut_n_reg[63]_0 [10]));
  (* SOFT_HLUTNM = "soft_lutpair573" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[11]_i_1 
       (.I0(cplx_DMOut_n[59]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[15] [3]),
        .O(\cplx_DMOut_n_reg[63]_0 [11]));
  (* SOFT_HLUTNM = "soft_lutpair572" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[12]_i_1 
       (.I0(cplx_DMOut_n[60]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[15] [4]),
        .O(\cplx_DMOut_n_reg[63]_0 [12]));
  (* SOFT_HLUTNM = "soft_lutpair571" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[13]_i_1 
       (.I0(cplx_DMOut_n[61]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[15] [5]),
        .O(\cplx_DMOut_n_reg[63]_0 [13]));
  (* SOFT_HLUTNM = "soft_lutpair570" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[14]_i_1 
       (.I0(cplx_DMOut_n[62]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[15] [6]),
        .O(\cplx_DMOut_n_reg[63]_0 [14]));
  (* SOFT_HLUTNM = "soft_lutpair569" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[15]_i_1 
       (.I0(cplx_DMOut_n[63]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[15] [7]),
        .O(\cplx_DMOut_n_reg[63]_0 [15]));
  (* SOFT_HLUTNM = "soft_lutpair568" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[16]_i_1 
       (.I0(cplx_DMOut_n[56]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[23] [0]),
        .O(\cplx_DMOut_n_reg[63]_0 [16]));
  (* SOFT_HLUTNM = "soft_lutpair567" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[17]_i_1 
       (.I0(cplx_DMOut_n[57]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[23] [1]),
        .O(\cplx_DMOut_n_reg[63]_0 [17]));
  (* SOFT_HLUTNM = "soft_lutpair566" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[18]_i_1 
       (.I0(cplx_DMOut_n[58]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[23] [2]),
        .O(\cplx_DMOut_n_reg[63]_0 [18]));
  (* SOFT_HLUTNM = "soft_lutpair565" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[19]_i_1 
       (.I0(cplx_DMOut_n[59]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[23] [3]),
        .O(\cplx_DMOut_n_reg[63]_0 [19]));
  (* SOFT_HLUTNM = "soft_lutpair575" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[1]_i_1 
       (.I0(cplx_DMOut_n[57]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[7] [1]),
        .O(\cplx_DMOut_n_reg[63]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair564" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[20]_i_1 
       (.I0(cplx_DMOut_n[60]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[23] [4]),
        .O(\cplx_DMOut_n_reg[63]_0 [20]));
  (* SOFT_HLUTNM = "soft_lutpair563" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[21]_i_1 
       (.I0(cplx_DMOut_n[61]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[23] [5]),
        .O(\cplx_DMOut_n_reg[63]_0 [21]));
  (* SOFT_HLUTNM = "soft_lutpair562" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[22]_i_1 
       (.I0(cplx_DMOut_n[62]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[23] [6]),
        .O(\cplx_DMOut_n_reg[63]_0 [22]));
  (* SOFT_HLUTNM = "soft_lutpair561" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[23]_i_1 
       (.I0(cplx_DMOut_n[63]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[23] [7]),
        .O(\cplx_DMOut_n_reg[63]_0 [23]));
  (* SOFT_HLUTNM = "soft_lutpair568" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[24]_i_1 
       (.I0(cplx_DMOut_n[56]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[31] [0]),
        .O(\cplx_DMOut_n_reg[63]_0 [24]));
  (* SOFT_HLUTNM = "soft_lutpair567" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[25]_i_1 
       (.I0(cplx_DMOut_n[57]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[31] [1]),
        .O(\cplx_DMOut_n_reg[63]_0 [25]));
  (* SOFT_HLUTNM = "soft_lutpair566" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[26]_i_1 
       (.I0(cplx_DMOut_n[58]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[31] [2]),
        .O(\cplx_DMOut_n_reg[63]_0 [26]));
  (* SOFT_HLUTNM = "soft_lutpair565" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[27]_i_1 
       (.I0(cplx_DMOut_n[59]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[31] [3]),
        .O(\cplx_DMOut_n_reg[63]_0 [27]));
  (* SOFT_HLUTNM = "soft_lutpair564" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[28]_i_1 
       (.I0(cplx_DMOut_n[60]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[31] [4]),
        .O(\cplx_DMOut_n_reg[63]_0 [28]));
  (* SOFT_HLUTNM = "soft_lutpair563" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[29]_i_1 
       (.I0(cplx_DMOut_n[61]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[31] [5]),
        .O(\cplx_DMOut_n_reg[63]_0 [29]));
  (* SOFT_HLUTNM = "soft_lutpair574" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[2]_i_1 
       (.I0(cplx_DMOut_n[58]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[7] [2]),
        .O(\cplx_DMOut_n_reg[63]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair562" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[30]_i_1 
       (.I0(cplx_DMOut_n[62]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[31] [6]),
        .O(\cplx_DMOut_n_reg[63]_0 [30]));
  (* SOFT_HLUTNM = "soft_lutpair561" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[31]_i_1 
       (.I0(cplx_DMOut_n[63]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[31] [7]),
        .O(\cplx_DMOut_n_reg[63]_0 [31]));
  (* SOFT_HLUTNM = "soft_lutpair560" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[32]_i_1 
       (.I0(cplx_DMOut_n[56]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[39] [0]),
        .O(\cplx_DMOut_n_reg[63]_0 [32]));
  (* SOFT_HLUTNM = "soft_lutpair559" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[33]_i_1 
       (.I0(cplx_DMOut_n[57]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[39] [1]),
        .O(\cplx_DMOut_n_reg[63]_0 [33]));
  (* SOFT_HLUTNM = "soft_lutpair558" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[34]_i_1 
       (.I0(cplx_DMOut_n[58]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[39] [2]),
        .O(\cplx_DMOut_n_reg[63]_0 [34]));
  (* SOFT_HLUTNM = "soft_lutpair557" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[35]_i_1 
       (.I0(cplx_DMOut_n[59]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[39] [3]),
        .O(\cplx_DMOut_n_reg[63]_0 [35]));
  (* SOFT_HLUTNM = "soft_lutpair556" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[36]_i_1 
       (.I0(cplx_DMOut_n[60]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[39] [4]),
        .O(\cplx_DMOut_n_reg[63]_0 [36]));
  (* SOFT_HLUTNM = "soft_lutpair555" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[37]_i_1 
       (.I0(cplx_DMOut_n[61]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[39] [5]),
        .O(\cplx_DMOut_n_reg[63]_0 [37]));
  (* SOFT_HLUTNM = "soft_lutpair554" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[38]_i_1 
       (.I0(cplx_DMOut_n[62]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[39] [6]),
        .O(\cplx_DMOut_n_reg[63]_0 [38]));
  (* SOFT_HLUTNM = "soft_lutpair553" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[39]_i_1 
       (.I0(cplx_DMOut_n[63]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[39] [7]),
        .O(\cplx_DMOut_n_reg[63]_0 [39]));
  (* SOFT_HLUTNM = "soft_lutpair573" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[3]_i_1 
       (.I0(cplx_DMOut_n[59]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[7] [3]),
        .O(\cplx_DMOut_n_reg[63]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair560" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[40]_i_1 
       (.I0(cplx_DMOut_n[56]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[47] [0]),
        .O(\cplx_DMOut_n_reg[63]_0 [40]));
  (* SOFT_HLUTNM = "soft_lutpair559" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[41]_i_1 
       (.I0(cplx_DMOut_n[57]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[47] [1]),
        .O(\cplx_DMOut_n_reg[63]_0 [41]));
  (* SOFT_HLUTNM = "soft_lutpair558" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[42]_i_1 
       (.I0(cplx_DMOut_n[58]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[47] [2]),
        .O(\cplx_DMOut_n_reg[63]_0 [42]));
  (* SOFT_HLUTNM = "soft_lutpair557" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[43]_i_1 
       (.I0(cplx_DMOut_n[59]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[47] [3]),
        .O(\cplx_DMOut_n_reg[63]_0 [43]));
  (* SOFT_HLUTNM = "soft_lutpair556" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[44]_i_1 
       (.I0(cplx_DMOut_n[60]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[47] [4]),
        .O(\cplx_DMOut_n_reg[63]_0 [44]));
  (* SOFT_HLUTNM = "soft_lutpair555" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[45]_i_1 
       (.I0(cplx_DMOut_n[61]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[47] [5]),
        .O(\cplx_DMOut_n_reg[63]_0 [45]));
  (* SOFT_HLUTNM = "soft_lutpair554" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[46]_i_1 
       (.I0(cplx_DMOut_n[62]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[47] [6]),
        .O(\cplx_DMOut_n_reg[63]_0 [46]));
  (* SOFT_HLUTNM = "soft_lutpair553" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[47]_i_1 
       (.I0(cplx_DMOut_n[63]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[47] [7]),
        .O(\cplx_DMOut_n_reg[63]_0 [47]));
  (* SOFT_HLUTNM = "soft_lutpair552" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[48]_i_1 
       (.I0(cplx_DMOut_n[56]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[55] [0]),
        .O(\cplx_DMOut_n_reg[63]_0 [48]));
  (* SOFT_HLUTNM = "soft_lutpair551" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[49]_i_1 
       (.I0(cplx_DMOut_n[57]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[55] [1]),
        .O(\cplx_DMOut_n_reg[63]_0 [49]));
  (* SOFT_HLUTNM = "soft_lutpair572" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[4]_i_1 
       (.I0(cplx_DMOut_n[60]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[7] [4]),
        .O(\cplx_DMOut_n_reg[63]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair550" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[50]_i_1 
       (.I0(cplx_DMOut_n[58]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[55] [2]),
        .O(\cplx_DMOut_n_reg[63]_0 [50]));
  (* SOFT_HLUTNM = "soft_lutpair549" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[51]_i_1 
       (.I0(cplx_DMOut_n[59]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[55] [3]),
        .O(\cplx_DMOut_n_reg[63]_0 [51]));
  (* SOFT_HLUTNM = "soft_lutpair548" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[52]_i_1 
       (.I0(cplx_DMOut_n[60]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[55] [4]),
        .O(\cplx_DMOut_n_reg[63]_0 [52]));
  (* SOFT_HLUTNM = "soft_lutpair547" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[53]_i_1 
       (.I0(cplx_DMOut_n[61]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[55] [5]),
        .O(\cplx_DMOut_n_reg[63]_0 [53]));
  (* SOFT_HLUTNM = "soft_lutpair546" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[54]_i_1 
       (.I0(cplx_DMOut_n[62]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[55] [6]),
        .O(\cplx_DMOut_n_reg[63]_0 [54]));
  (* SOFT_HLUTNM = "soft_lutpair545" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[55]_i_1 
       (.I0(cplx_DMOut_n[63]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[55] [7]),
        .O(\cplx_DMOut_n_reg[63]_0 [55]));
  (* SOFT_HLUTNM = "soft_lutpair552" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[56]_i_1 
       (.I0(cplx_DMOut_n[56]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[63] [0]),
        .O(\cplx_DMOut_n_reg[63]_0 [56]));
  (* SOFT_HLUTNM = "soft_lutpair551" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[57]_i_1 
       (.I0(cplx_DMOut_n[57]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[63] [1]),
        .O(\cplx_DMOut_n_reg[63]_0 [57]));
  (* SOFT_HLUTNM = "soft_lutpair550" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[58]_i_1 
       (.I0(cplx_DMOut_n[58]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[63] [2]),
        .O(\cplx_DMOut_n_reg[63]_0 [58]));
  (* SOFT_HLUTNM = "soft_lutpair549" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[59]_i_1 
       (.I0(cplx_DMOut_n[59]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[63] [3]),
        .O(\cplx_DMOut_n_reg[63]_0 [59]));
  (* SOFT_HLUTNM = "soft_lutpair571" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[5]_i_1 
       (.I0(cplx_DMOut_n[61]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[7] [5]),
        .O(\cplx_DMOut_n_reg[63]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair548" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[60]_i_1 
       (.I0(cplx_DMOut_n[60]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[63] [4]),
        .O(\cplx_DMOut_n_reg[63]_0 [60]));
  (* SOFT_HLUTNM = "soft_lutpair547" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[61]_i_1 
       (.I0(cplx_DMOut_n[61]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[63] [5]),
        .O(\cplx_DMOut_n_reg[63]_0 [61]));
  (* SOFT_HLUTNM = "soft_lutpair546" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[62]_i_1 
       (.I0(cplx_DMOut_n[62]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[63] [6]),
        .O(\cplx_DMOut_n_reg[63]_0 [62]));
  (* SOFT_HLUTNM = "soft_lutpair545" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[63]_i_1 
       (.I0(cplx_DMOut_n[63]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[63] [7]),
        .O(\cplx_DMOut_n_reg[63]_0 [63]));
  (* SOFT_HLUTNM = "soft_lutpair570" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[6]_i_1 
       (.I0(cplx_DMOut_n[62]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[7] [6]),
        .O(\cplx_DMOut_n_reg[63]_0 [6]));
  (* SOFT_HLUTNM = "soft_lutpair569" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[7]_i_1 
       (.I0(cplx_DMOut_n[63]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[7] [7]),
        .O(\cplx_DMOut_n_reg[63]_0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair576" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[8]_i_1 
       (.I0(cplx_DMOut_n[56]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[15] [0]),
        .O(\cplx_DMOut_n_reg[63]_0 [8]));
  (* SOFT_HLUTNM = "soft_lutpair575" *) 
  LUT4 #(
    .INIT(16'hB888)) 
    \cal_DMOut_n[9]_i_1 
       (.I0(cplx_DMOut_n[57]),
        .I1(cplx_cal),
        .I2(wrDataEn_pi),
        .I3(\cal_DMOut_n_reg[15] [1]),
        .O(\cplx_DMOut_n_reg[63]_0 [9]));
  (* SOFT_HLUTNM = "soft_lutpair882" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[0]_i_1 
       (.I0(cplx_DQOut[0]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [0]),
        .O(\cplx_DQOut_reg[511]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair832" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[100]_i_1 
       (.I0(cplx_DQOut[100]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [100]),
        .O(\cplx_DQOut_reg[511]_0 [100]));
  (* SOFT_HLUTNM = "soft_lutpair832" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[101]_i_1 
       (.I0(cplx_DQOut[101]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [101]),
        .O(\cplx_DQOut_reg[511]_0 [101]));
  (* SOFT_HLUTNM = "soft_lutpair831" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[102]_i_1 
       (.I0(cplx_DQOut[102]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [102]),
        .O(\cplx_DQOut_reg[511]_0 [102]));
  (* SOFT_HLUTNM = "soft_lutpair831" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[103]_i_1 
       (.I0(cplx_DQOut[103]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [103]),
        .O(\cplx_DQOut_reg[511]_0 [103]));
  (* SOFT_HLUTNM = "soft_lutpair830" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[104]_i_1 
       (.I0(cplx_DQOut[104]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [104]),
        .O(\cplx_DQOut_reg[511]_0 [104]));
  (* SOFT_HLUTNM = "soft_lutpair830" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[105]_i_1 
       (.I0(cplx_DQOut[105]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [105]),
        .O(\cplx_DQOut_reg[511]_0 [105]));
  (* SOFT_HLUTNM = "soft_lutpair829" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[106]_i_1 
       (.I0(cplx_DQOut[106]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [106]),
        .O(\cplx_DQOut_reg[511]_0 [106]));
  (* SOFT_HLUTNM = "soft_lutpair829" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[107]_i_1 
       (.I0(cplx_DQOut[107]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [107]),
        .O(\cplx_DQOut_reg[511]_0 [107]));
  (* SOFT_HLUTNM = "soft_lutpair828" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[108]_i_1 
       (.I0(cplx_DQOut[108]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [108]),
        .O(\cplx_DQOut_reg[511]_0 [108]));
  (* SOFT_HLUTNM = "soft_lutpair828" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[109]_i_1 
       (.I0(cplx_DQOut[109]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [109]),
        .O(\cplx_DQOut_reg[511]_0 [109]));
  (* SOFT_HLUTNM = "soft_lutpair877" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[10]_i_1 
       (.I0(cplx_DQOut[10]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [10]),
        .O(\cplx_DQOut_reg[511]_0 [10]));
  (* SOFT_HLUTNM = "soft_lutpair827" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[110]_i_1 
       (.I0(cplx_DQOut[110]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [110]),
        .O(\cplx_DQOut_reg[511]_0 [110]));
  (* SOFT_HLUTNM = "soft_lutpair827" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[111]_i_1 
       (.I0(cplx_DQOut[111]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [111]),
        .O(\cplx_DQOut_reg[511]_0 [111]));
  (* SOFT_HLUTNM = "soft_lutpair826" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[112]_i_1 
       (.I0(cplx_DQOut[112]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [112]),
        .O(\cplx_DQOut_reg[511]_0 [112]));
  (* SOFT_HLUTNM = "soft_lutpair826" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[113]_i_1 
       (.I0(cplx_DQOut[113]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [113]),
        .O(\cplx_DQOut_reg[511]_0 [113]));
  (* SOFT_HLUTNM = "soft_lutpair825" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[114]_i_1 
       (.I0(cplx_DQOut[114]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [114]),
        .O(\cplx_DQOut_reg[511]_0 [114]));
  (* SOFT_HLUTNM = "soft_lutpair825" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[115]_i_1 
       (.I0(cplx_DQOut[115]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [115]),
        .O(\cplx_DQOut_reg[511]_0 [115]));
  (* SOFT_HLUTNM = "soft_lutpair824" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[116]_i_1 
       (.I0(cplx_DQOut[116]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [116]),
        .O(\cplx_DQOut_reg[511]_0 [116]));
  (* SOFT_HLUTNM = "soft_lutpair824" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[117]_i_1 
       (.I0(cplx_DQOut[117]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [117]),
        .O(\cplx_DQOut_reg[511]_0 [117]));
  (* SOFT_HLUTNM = "soft_lutpair823" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[118]_i_1 
       (.I0(cplx_DQOut[118]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [118]),
        .O(\cplx_DQOut_reg[511]_0 [118]));
  (* SOFT_HLUTNM = "soft_lutpair823" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[119]_i_1 
       (.I0(cplx_DQOut[119]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [119]),
        .O(\cplx_DQOut_reg[511]_0 [119]));
  (* SOFT_HLUTNM = "soft_lutpair877" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[11]_i_1 
       (.I0(cplx_DQOut[11]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [11]),
        .O(\cplx_DQOut_reg[511]_0 [11]));
  (* SOFT_HLUTNM = "soft_lutpair822" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[120]_i_1 
       (.I0(cplx_DQOut[120]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [120]),
        .O(\cplx_DQOut_reg[511]_0 [120]));
  (* SOFT_HLUTNM = "soft_lutpair822" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[121]_i_1 
       (.I0(cplx_DQOut[121]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [121]),
        .O(\cplx_DQOut_reg[511]_0 [121]));
  (* SOFT_HLUTNM = "soft_lutpair821" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[122]_i_1 
       (.I0(cplx_DQOut[122]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [122]),
        .O(\cplx_DQOut_reg[511]_0 [122]));
  (* SOFT_HLUTNM = "soft_lutpair821" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[123]_i_1 
       (.I0(cplx_DQOut[123]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [123]),
        .O(\cplx_DQOut_reg[511]_0 [123]));
  (* SOFT_HLUTNM = "soft_lutpair820" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[124]_i_1 
       (.I0(cplx_DQOut[124]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [124]),
        .O(\cplx_DQOut_reg[511]_0 [124]));
  (* SOFT_HLUTNM = "soft_lutpair820" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[125]_i_1 
       (.I0(cplx_DQOut[125]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [125]),
        .O(\cplx_DQOut_reg[511]_0 [125]));
  (* SOFT_HLUTNM = "soft_lutpair819" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[126]_i_1 
       (.I0(cplx_DQOut[126]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [126]),
        .O(\cplx_DQOut_reg[511]_0 [126]));
  (* SOFT_HLUTNM = "soft_lutpair819" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[127]_i_1 
       (.I0(cplx_DQOut[127]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [127]),
        .O(\cplx_DQOut_reg[511]_0 [127]));
  (* SOFT_HLUTNM = "soft_lutpair818" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[128]_i_1 
       (.I0(cplx_DQOut[128]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [128]),
        .O(\cplx_DQOut_reg[511]_0 [128]));
  (* SOFT_HLUTNM = "soft_lutpair818" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[129]_i_1 
       (.I0(cplx_DQOut[129]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [129]),
        .O(\cplx_DQOut_reg[511]_0 [129]));
  (* SOFT_HLUTNM = "soft_lutpair876" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[12]_i_1 
       (.I0(cplx_DQOut[12]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [12]),
        .O(\cplx_DQOut_reg[511]_0 [12]));
  (* SOFT_HLUTNM = "soft_lutpair817" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[130]_i_1 
       (.I0(cplx_DQOut[130]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [130]),
        .O(\cplx_DQOut_reg[511]_0 [130]));
  (* SOFT_HLUTNM = "soft_lutpair817" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[131]_i_1 
       (.I0(cplx_DQOut[131]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [131]),
        .O(\cplx_DQOut_reg[511]_0 [131]));
  (* SOFT_HLUTNM = "soft_lutpair816" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[132]_i_1 
       (.I0(cplx_DQOut[132]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [132]),
        .O(\cplx_DQOut_reg[511]_0 [132]));
  (* SOFT_HLUTNM = "soft_lutpair816" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[133]_i_1 
       (.I0(cplx_DQOut[133]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [133]),
        .O(\cplx_DQOut_reg[511]_0 [133]));
  (* SOFT_HLUTNM = "soft_lutpair815" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[134]_i_1 
       (.I0(cplx_DQOut[134]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [134]),
        .O(\cplx_DQOut_reg[511]_0 [134]));
  (* SOFT_HLUTNM = "soft_lutpair815" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[135]_i_1 
       (.I0(cplx_DQOut[135]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [135]),
        .O(\cplx_DQOut_reg[511]_0 [135]));
  (* SOFT_HLUTNM = "soft_lutpair814" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[136]_i_1 
       (.I0(cplx_DQOut[136]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [136]),
        .O(\cplx_DQOut_reg[511]_0 [136]));
  (* SOFT_HLUTNM = "soft_lutpair814" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[137]_i_1 
       (.I0(cplx_DQOut[137]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [137]),
        .O(\cplx_DQOut_reg[511]_0 [137]));
  (* SOFT_HLUTNM = "soft_lutpair813" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[138]_i_1 
       (.I0(cplx_DQOut[138]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [138]),
        .O(\cplx_DQOut_reg[511]_0 [138]));
  (* SOFT_HLUTNM = "soft_lutpair813" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[139]_i_1 
       (.I0(cplx_DQOut[139]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [139]),
        .O(\cplx_DQOut_reg[511]_0 [139]));
  (* SOFT_HLUTNM = "soft_lutpair876" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[13]_i_1 
       (.I0(cplx_DQOut[13]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [13]),
        .O(\cplx_DQOut_reg[511]_0 [13]));
  (* SOFT_HLUTNM = "soft_lutpair812" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[140]_i_1 
       (.I0(cplx_DQOut[140]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [140]),
        .O(\cplx_DQOut_reg[511]_0 [140]));
  (* SOFT_HLUTNM = "soft_lutpair812" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[141]_i_1 
       (.I0(cplx_DQOut[141]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [141]),
        .O(\cplx_DQOut_reg[511]_0 [141]));
  (* SOFT_HLUTNM = "soft_lutpair811" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[142]_i_1 
       (.I0(cplx_DQOut[142]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [142]),
        .O(\cplx_DQOut_reg[511]_0 [142]));
  (* SOFT_HLUTNM = "soft_lutpair811" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[143]_i_1 
       (.I0(cplx_DQOut[143]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [143]),
        .O(\cplx_DQOut_reg[511]_0 [143]));
  (* SOFT_HLUTNM = "soft_lutpair810" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[144]_i_1 
       (.I0(cplx_DQOut[144]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [144]),
        .O(\cplx_DQOut_reg[511]_0 [144]));
  (* SOFT_HLUTNM = "soft_lutpair810" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[145]_i_1 
       (.I0(cplx_DQOut[145]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [145]),
        .O(\cplx_DQOut_reg[511]_0 [145]));
  (* SOFT_HLUTNM = "soft_lutpair809" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[146]_i_1 
       (.I0(cplx_DQOut[146]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [146]),
        .O(\cplx_DQOut_reg[511]_0 [146]));
  (* SOFT_HLUTNM = "soft_lutpair809" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[147]_i_1 
       (.I0(cplx_DQOut[147]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [147]),
        .O(\cplx_DQOut_reg[511]_0 [147]));
  (* SOFT_HLUTNM = "soft_lutpair808" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[148]_i_1 
       (.I0(cplx_DQOut[148]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [148]),
        .O(\cplx_DQOut_reg[511]_0 [148]));
  (* SOFT_HLUTNM = "soft_lutpair808" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[149]_i_1 
       (.I0(cplx_DQOut[149]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [149]),
        .O(\cplx_DQOut_reg[511]_0 [149]));
  (* SOFT_HLUTNM = "soft_lutpair875" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[14]_i_1 
       (.I0(cplx_DQOut[14]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [14]),
        .O(\cplx_DQOut_reg[511]_0 [14]));
  (* SOFT_HLUTNM = "soft_lutpair807" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[150]_i_1 
       (.I0(cplx_DQOut[150]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [150]),
        .O(\cplx_DQOut_reg[511]_0 [150]));
  (* SOFT_HLUTNM = "soft_lutpair807" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[151]_i_1 
       (.I0(cplx_DQOut[151]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [151]),
        .O(\cplx_DQOut_reg[511]_0 [151]));
  (* SOFT_HLUTNM = "soft_lutpair806" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[152]_i_1 
       (.I0(cplx_DQOut[152]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [152]),
        .O(\cplx_DQOut_reg[511]_0 [152]));
  (* SOFT_HLUTNM = "soft_lutpair806" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[153]_i_1 
       (.I0(cplx_DQOut[153]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [153]),
        .O(\cplx_DQOut_reg[511]_0 [153]));
  (* SOFT_HLUTNM = "soft_lutpair805" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[154]_i_1 
       (.I0(cplx_DQOut[154]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [154]),
        .O(\cplx_DQOut_reg[511]_0 [154]));
  (* SOFT_HLUTNM = "soft_lutpair805" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[155]_i_1 
       (.I0(cplx_DQOut[155]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [155]),
        .O(\cplx_DQOut_reg[511]_0 [155]));
  (* SOFT_HLUTNM = "soft_lutpair804" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[156]_i_1 
       (.I0(cplx_DQOut[156]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [156]),
        .O(\cplx_DQOut_reg[511]_0 [156]));
  (* SOFT_HLUTNM = "soft_lutpair804" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[157]_i_1 
       (.I0(cplx_DQOut[157]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [157]),
        .O(\cplx_DQOut_reg[511]_0 [157]));
  (* SOFT_HLUTNM = "soft_lutpair803" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[158]_i_1 
       (.I0(cplx_DQOut[158]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [158]),
        .O(\cplx_DQOut_reg[511]_0 [158]));
  (* SOFT_HLUTNM = "soft_lutpair803" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[159]_i_1 
       (.I0(cplx_DQOut[159]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [159]),
        .O(\cplx_DQOut_reg[511]_0 [159]));
  (* SOFT_HLUTNM = "soft_lutpair875" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[15]_i_1 
       (.I0(cplx_DQOut[15]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [15]),
        .O(\cplx_DQOut_reg[511]_0 [15]));
  (* SOFT_HLUTNM = "soft_lutpair802" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[160]_i_1 
       (.I0(cplx_DQOut[160]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [160]),
        .O(\cplx_DQOut_reg[511]_0 [160]));
  (* SOFT_HLUTNM = "soft_lutpair802" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[161]_i_1 
       (.I0(cplx_DQOut[161]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [161]),
        .O(\cplx_DQOut_reg[511]_0 [161]));
  (* SOFT_HLUTNM = "soft_lutpair801" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[162]_i_1 
       (.I0(cplx_DQOut[162]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [162]),
        .O(\cplx_DQOut_reg[511]_0 [162]));
  (* SOFT_HLUTNM = "soft_lutpair801" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[163]_i_1 
       (.I0(cplx_DQOut[163]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [163]),
        .O(\cplx_DQOut_reg[511]_0 [163]));
  (* SOFT_HLUTNM = "soft_lutpair800" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[164]_i_1 
       (.I0(cplx_DQOut[164]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [164]),
        .O(\cplx_DQOut_reg[511]_0 [164]));
  (* SOFT_HLUTNM = "soft_lutpair800" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[165]_i_1 
       (.I0(cplx_DQOut[165]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [165]),
        .O(\cplx_DQOut_reg[511]_0 [165]));
  (* SOFT_HLUTNM = "soft_lutpair799" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[166]_i_1 
       (.I0(cplx_DQOut[166]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [166]),
        .O(\cplx_DQOut_reg[511]_0 [166]));
  (* SOFT_HLUTNM = "soft_lutpair799" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[167]_i_1 
       (.I0(cplx_DQOut[167]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [167]),
        .O(\cplx_DQOut_reg[511]_0 [167]));
  (* SOFT_HLUTNM = "soft_lutpair798" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[168]_i_1 
       (.I0(cplx_DQOut[168]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [168]),
        .O(\cplx_DQOut_reg[511]_0 [168]));
  (* SOFT_HLUTNM = "soft_lutpair798" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[169]_i_1 
       (.I0(cplx_DQOut[169]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [169]),
        .O(\cplx_DQOut_reg[511]_0 [169]));
  (* SOFT_HLUTNM = "soft_lutpair874" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[16]_i_1 
       (.I0(cplx_DQOut[16]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [16]),
        .O(\cplx_DQOut_reg[511]_0 [16]));
  (* SOFT_HLUTNM = "soft_lutpair797" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[170]_i_1 
       (.I0(cplx_DQOut[170]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [170]),
        .O(\cplx_DQOut_reg[511]_0 [170]));
  (* SOFT_HLUTNM = "soft_lutpair797" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[171]_i_1 
       (.I0(cplx_DQOut[171]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [171]),
        .O(\cplx_DQOut_reg[511]_0 [171]));
  (* SOFT_HLUTNM = "soft_lutpair796" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[172]_i_1 
       (.I0(cplx_DQOut[172]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [172]),
        .O(\cplx_DQOut_reg[511]_0 [172]));
  (* SOFT_HLUTNM = "soft_lutpair796" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[173]_i_1 
       (.I0(cplx_DQOut[173]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [173]),
        .O(\cplx_DQOut_reg[511]_0 [173]));
  (* SOFT_HLUTNM = "soft_lutpair795" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[174]_i_1 
       (.I0(cplx_DQOut[174]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [174]),
        .O(\cplx_DQOut_reg[511]_0 [174]));
  (* SOFT_HLUTNM = "soft_lutpair795" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[175]_i_1 
       (.I0(cplx_DQOut[175]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [175]),
        .O(\cplx_DQOut_reg[511]_0 [175]));
  (* SOFT_HLUTNM = "soft_lutpair794" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[176]_i_1 
       (.I0(cplx_DQOut[176]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [176]),
        .O(\cplx_DQOut_reg[511]_0 [176]));
  (* SOFT_HLUTNM = "soft_lutpair794" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[177]_i_1 
       (.I0(cplx_DQOut[177]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [177]),
        .O(\cplx_DQOut_reg[511]_0 [177]));
  (* SOFT_HLUTNM = "soft_lutpair793" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[178]_i_1 
       (.I0(cplx_DQOut[178]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [178]),
        .O(\cplx_DQOut_reg[511]_0 [178]));
  (* SOFT_HLUTNM = "soft_lutpair793" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[179]_i_1 
       (.I0(cplx_DQOut[179]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [179]),
        .O(\cplx_DQOut_reg[511]_0 [179]));
  (* SOFT_HLUTNM = "soft_lutpair874" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[17]_i_1 
       (.I0(cplx_DQOut[17]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [17]),
        .O(\cplx_DQOut_reg[511]_0 [17]));
  (* SOFT_HLUTNM = "soft_lutpair792" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[180]_i_1 
       (.I0(cplx_DQOut[180]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [180]),
        .O(\cplx_DQOut_reg[511]_0 [180]));
  (* SOFT_HLUTNM = "soft_lutpair792" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[181]_i_1 
       (.I0(cplx_DQOut[181]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [181]),
        .O(\cplx_DQOut_reg[511]_0 [181]));
  (* SOFT_HLUTNM = "soft_lutpair791" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[182]_i_1 
       (.I0(cplx_DQOut[182]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [182]),
        .O(\cplx_DQOut_reg[511]_0 [182]));
  (* SOFT_HLUTNM = "soft_lutpair791" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[183]_i_1 
       (.I0(cplx_DQOut[183]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [183]),
        .O(\cplx_DQOut_reg[511]_0 [183]));
  (* SOFT_HLUTNM = "soft_lutpair790" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[184]_i_1 
       (.I0(cplx_DQOut[184]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [184]),
        .O(\cplx_DQOut_reg[511]_0 [184]));
  (* SOFT_HLUTNM = "soft_lutpair790" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[185]_i_1 
       (.I0(cplx_DQOut[185]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [185]),
        .O(\cplx_DQOut_reg[511]_0 [185]));
  (* SOFT_HLUTNM = "soft_lutpair789" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[186]_i_1 
       (.I0(cplx_DQOut[186]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [186]),
        .O(\cplx_DQOut_reg[511]_0 [186]));
  (* SOFT_HLUTNM = "soft_lutpair789" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[187]_i_1 
       (.I0(cplx_DQOut[187]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [187]),
        .O(\cplx_DQOut_reg[511]_0 [187]));
  (* SOFT_HLUTNM = "soft_lutpair788" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[188]_i_1 
       (.I0(cplx_DQOut[188]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [188]),
        .O(\cplx_DQOut_reg[511]_0 [188]));
  (* SOFT_HLUTNM = "soft_lutpair788" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[189]_i_1 
       (.I0(cplx_DQOut[189]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [189]),
        .O(\cplx_DQOut_reg[511]_0 [189]));
  (* SOFT_HLUTNM = "soft_lutpair873" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[18]_i_1 
       (.I0(cplx_DQOut[18]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [18]),
        .O(\cplx_DQOut_reg[511]_0 [18]));
  (* SOFT_HLUTNM = "soft_lutpair787" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[190]_i_1 
       (.I0(cplx_DQOut[190]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [190]),
        .O(\cplx_DQOut_reg[511]_0 [190]));
  (* SOFT_HLUTNM = "soft_lutpair787" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[191]_i_1 
       (.I0(cplx_DQOut[191]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [191]),
        .O(\cplx_DQOut_reg[511]_0 [191]));
  (* SOFT_HLUTNM = "soft_lutpair786" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[192]_i_1 
       (.I0(cplx_DQOut[192]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [192]),
        .O(\cplx_DQOut_reg[511]_0 [192]));
  (* SOFT_HLUTNM = "soft_lutpair786" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[193]_i_1 
       (.I0(cplx_DQOut[193]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [193]),
        .O(\cplx_DQOut_reg[511]_0 [193]));
  (* SOFT_HLUTNM = "soft_lutpair785" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[194]_i_1 
       (.I0(cplx_DQOut[194]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [194]),
        .O(\cplx_DQOut_reg[511]_0 [194]));
  (* SOFT_HLUTNM = "soft_lutpair785" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[195]_i_1 
       (.I0(cplx_DQOut[195]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [195]),
        .O(\cplx_DQOut_reg[511]_0 [195]));
  (* SOFT_HLUTNM = "soft_lutpair784" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[196]_i_1 
       (.I0(cplx_DQOut[196]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [196]),
        .O(\cplx_DQOut_reg[511]_0 [196]));
  (* SOFT_HLUTNM = "soft_lutpair784" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[197]_i_1 
       (.I0(cplx_DQOut[197]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [197]),
        .O(\cplx_DQOut_reg[511]_0 [197]));
  (* SOFT_HLUTNM = "soft_lutpair783" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[198]_i_1 
       (.I0(cplx_DQOut[198]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [198]),
        .O(\cplx_DQOut_reg[511]_0 [198]));
  (* SOFT_HLUTNM = "soft_lutpair783" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[199]_i_1 
       (.I0(cplx_DQOut[199]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [199]),
        .O(\cplx_DQOut_reg[511]_0 [199]));
  (* SOFT_HLUTNM = "soft_lutpair873" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[19]_i_1 
       (.I0(cplx_DQOut[19]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [19]),
        .O(\cplx_DQOut_reg[511]_0 [19]));
  (* SOFT_HLUTNM = "soft_lutpair882" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[1]_i_1 
       (.I0(cplx_DQOut[1]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [1]),
        .O(\cplx_DQOut_reg[511]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair782" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[200]_i_1 
       (.I0(cplx_DQOut[200]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [200]),
        .O(\cplx_DQOut_reg[511]_0 [200]));
  (* SOFT_HLUTNM = "soft_lutpair782" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[201]_i_1 
       (.I0(cplx_DQOut[201]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [201]),
        .O(\cplx_DQOut_reg[511]_0 [201]));
  (* SOFT_HLUTNM = "soft_lutpair781" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[202]_i_1 
       (.I0(cplx_DQOut[202]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [202]),
        .O(\cplx_DQOut_reg[511]_0 [202]));
  (* SOFT_HLUTNM = "soft_lutpair781" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[203]_i_1 
       (.I0(cplx_DQOut[203]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [203]),
        .O(\cplx_DQOut_reg[511]_0 [203]));
  (* SOFT_HLUTNM = "soft_lutpair780" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[204]_i_1 
       (.I0(cplx_DQOut[204]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [204]),
        .O(\cplx_DQOut_reg[511]_0 [204]));
  (* SOFT_HLUTNM = "soft_lutpair780" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[205]_i_1 
       (.I0(cplx_DQOut[205]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [205]),
        .O(\cplx_DQOut_reg[511]_0 [205]));
  (* SOFT_HLUTNM = "soft_lutpair779" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[206]_i_1 
       (.I0(cplx_DQOut[206]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [206]),
        .O(\cplx_DQOut_reg[511]_0 [206]));
  (* SOFT_HLUTNM = "soft_lutpair779" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[207]_i_1 
       (.I0(cplx_DQOut[207]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [207]),
        .O(\cplx_DQOut_reg[511]_0 [207]));
  (* SOFT_HLUTNM = "soft_lutpair778" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[208]_i_1 
       (.I0(cplx_DQOut[208]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [208]),
        .O(\cplx_DQOut_reg[511]_0 [208]));
  (* SOFT_HLUTNM = "soft_lutpair778" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[209]_i_1 
       (.I0(cplx_DQOut[209]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [209]),
        .O(\cplx_DQOut_reg[511]_0 [209]));
  (* SOFT_HLUTNM = "soft_lutpair872" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[20]_i_1 
       (.I0(cplx_DQOut[20]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [20]),
        .O(\cplx_DQOut_reg[511]_0 [20]));
  (* SOFT_HLUTNM = "soft_lutpair777" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[210]_i_1 
       (.I0(cplx_DQOut[210]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [210]),
        .O(\cplx_DQOut_reg[511]_0 [210]));
  (* SOFT_HLUTNM = "soft_lutpair777" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[211]_i_1 
       (.I0(cplx_DQOut[211]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [211]),
        .O(\cplx_DQOut_reg[511]_0 [211]));
  (* SOFT_HLUTNM = "soft_lutpair776" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[212]_i_1 
       (.I0(cplx_DQOut[212]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [212]),
        .O(\cplx_DQOut_reg[511]_0 [212]));
  (* SOFT_HLUTNM = "soft_lutpair776" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[213]_i_1 
       (.I0(cplx_DQOut[213]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [213]),
        .O(\cplx_DQOut_reg[511]_0 [213]));
  (* SOFT_HLUTNM = "soft_lutpair775" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[214]_i_1 
       (.I0(cplx_DQOut[214]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [214]),
        .O(\cplx_DQOut_reg[511]_0 [214]));
  (* SOFT_HLUTNM = "soft_lutpair775" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[215]_i_1 
       (.I0(cplx_DQOut[215]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [215]),
        .O(\cplx_DQOut_reg[511]_0 [215]));
  (* SOFT_HLUTNM = "soft_lutpair774" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[216]_i_1 
       (.I0(cplx_DQOut[216]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [216]),
        .O(\cplx_DQOut_reg[511]_0 [216]));
  (* SOFT_HLUTNM = "soft_lutpair774" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[217]_i_1 
       (.I0(cplx_DQOut[217]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [217]),
        .O(\cplx_DQOut_reg[511]_0 [217]));
  (* SOFT_HLUTNM = "soft_lutpair773" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[218]_i_1 
       (.I0(cplx_DQOut[218]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [218]),
        .O(\cplx_DQOut_reg[511]_0 [218]));
  (* SOFT_HLUTNM = "soft_lutpair773" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[219]_i_1 
       (.I0(cplx_DQOut[219]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [219]),
        .O(\cplx_DQOut_reg[511]_0 [219]));
  (* SOFT_HLUTNM = "soft_lutpair872" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[21]_i_1 
       (.I0(cplx_DQOut[21]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [21]),
        .O(\cplx_DQOut_reg[511]_0 [21]));
  (* SOFT_HLUTNM = "soft_lutpair772" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[220]_i_1 
       (.I0(cplx_DQOut[220]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [220]),
        .O(\cplx_DQOut_reg[511]_0 [220]));
  (* SOFT_HLUTNM = "soft_lutpair772" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[221]_i_1 
       (.I0(cplx_DQOut[221]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [221]),
        .O(\cplx_DQOut_reg[511]_0 [221]));
  (* SOFT_HLUTNM = "soft_lutpair771" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[222]_i_1 
       (.I0(cplx_DQOut[222]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [222]),
        .O(\cplx_DQOut_reg[511]_0 [222]));
  (* SOFT_HLUTNM = "soft_lutpair771" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[223]_i_1 
       (.I0(cplx_DQOut[223]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [223]),
        .O(\cplx_DQOut_reg[511]_0 [223]));
  (* SOFT_HLUTNM = "soft_lutpair770" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[224]_i_1 
       (.I0(cplx_DQOut[224]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [224]),
        .O(\cplx_DQOut_reg[511]_0 [224]));
  (* SOFT_HLUTNM = "soft_lutpair770" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[225]_i_1 
       (.I0(cplx_DQOut[225]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [225]),
        .O(\cplx_DQOut_reg[511]_0 [225]));
  (* SOFT_HLUTNM = "soft_lutpair769" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[226]_i_1 
       (.I0(cplx_DQOut[226]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [226]),
        .O(\cplx_DQOut_reg[511]_0 [226]));
  (* SOFT_HLUTNM = "soft_lutpair769" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[227]_i_1 
       (.I0(cplx_DQOut[227]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [227]),
        .O(\cplx_DQOut_reg[511]_0 [227]));
  (* SOFT_HLUTNM = "soft_lutpair768" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[228]_i_1 
       (.I0(cplx_DQOut[228]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [228]),
        .O(\cplx_DQOut_reg[511]_0 [228]));
  (* SOFT_HLUTNM = "soft_lutpair768" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[229]_i_1 
       (.I0(cplx_DQOut[229]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [229]),
        .O(\cplx_DQOut_reg[511]_0 [229]));
  (* SOFT_HLUTNM = "soft_lutpair871" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[22]_i_1 
       (.I0(cplx_DQOut[22]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [22]),
        .O(\cplx_DQOut_reg[511]_0 [22]));
  (* SOFT_HLUTNM = "soft_lutpair767" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[230]_i_1 
       (.I0(cplx_DQOut[230]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [230]),
        .O(\cplx_DQOut_reg[511]_0 [230]));
  (* SOFT_HLUTNM = "soft_lutpair767" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[231]_i_1 
       (.I0(cplx_DQOut[231]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [231]),
        .O(\cplx_DQOut_reg[511]_0 [231]));
  (* SOFT_HLUTNM = "soft_lutpair766" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[232]_i_1 
       (.I0(cplx_DQOut[232]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [232]),
        .O(\cplx_DQOut_reg[511]_0 [232]));
  (* SOFT_HLUTNM = "soft_lutpair766" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[233]_i_1 
       (.I0(cplx_DQOut[233]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [233]),
        .O(\cplx_DQOut_reg[511]_0 [233]));
  (* SOFT_HLUTNM = "soft_lutpair765" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[234]_i_1 
       (.I0(cplx_DQOut[234]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [234]),
        .O(\cplx_DQOut_reg[511]_0 [234]));
  (* SOFT_HLUTNM = "soft_lutpair765" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[235]_i_1 
       (.I0(cplx_DQOut[235]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [235]),
        .O(\cplx_DQOut_reg[511]_0 [235]));
  (* SOFT_HLUTNM = "soft_lutpair764" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[236]_i_1 
       (.I0(cplx_DQOut[236]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [236]),
        .O(\cplx_DQOut_reg[511]_0 [236]));
  (* SOFT_HLUTNM = "soft_lutpair764" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[237]_i_1 
       (.I0(cplx_DQOut[237]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [237]),
        .O(\cplx_DQOut_reg[511]_0 [237]));
  (* SOFT_HLUTNM = "soft_lutpair763" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[238]_i_1 
       (.I0(cplx_DQOut[238]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [238]),
        .O(\cplx_DQOut_reg[511]_0 [238]));
  (* SOFT_HLUTNM = "soft_lutpair763" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[239]_i_1 
       (.I0(cplx_DQOut[239]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [239]),
        .O(\cplx_DQOut_reg[511]_0 [239]));
  (* SOFT_HLUTNM = "soft_lutpair871" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[23]_i_1 
       (.I0(cplx_DQOut[23]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [23]),
        .O(\cplx_DQOut_reg[511]_0 [23]));
  (* SOFT_HLUTNM = "soft_lutpair762" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[240]_i_1 
       (.I0(cplx_DQOut[240]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [240]),
        .O(\cplx_DQOut_reg[511]_0 [240]));
  (* SOFT_HLUTNM = "soft_lutpair762" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[241]_i_1 
       (.I0(cplx_DQOut[241]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [241]),
        .O(\cplx_DQOut_reg[511]_0 [241]));
  (* SOFT_HLUTNM = "soft_lutpair761" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[242]_i_1 
       (.I0(cplx_DQOut[242]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [242]),
        .O(\cplx_DQOut_reg[511]_0 [242]));
  (* SOFT_HLUTNM = "soft_lutpair761" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[243]_i_1 
       (.I0(cplx_DQOut[243]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [243]),
        .O(\cplx_DQOut_reg[511]_0 [243]));
  (* SOFT_HLUTNM = "soft_lutpair760" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[244]_i_1 
       (.I0(cplx_DQOut[244]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [244]),
        .O(\cplx_DQOut_reg[511]_0 [244]));
  (* SOFT_HLUTNM = "soft_lutpair760" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[245]_i_1 
       (.I0(cplx_DQOut[245]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [245]),
        .O(\cplx_DQOut_reg[511]_0 [245]));
  (* SOFT_HLUTNM = "soft_lutpair759" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[246]_i_1 
       (.I0(cplx_DQOut[246]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [246]),
        .O(\cplx_DQOut_reg[511]_0 [246]));
  (* SOFT_HLUTNM = "soft_lutpair759" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[247]_i_1 
       (.I0(cplx_DQOut[247]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [247]),
        .O(\cplx_DQOut_reg[511]_0 [247]));
  (* SOFT_HLUTNM = "soft_lutpair758" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[248]_i_1 
       (.I0(cplx_DQOut[248]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [248]),
        .O(\cplx_DQOut_reg[511]_0 [248]));
  (* SOFT_HLUTNM = "soft_lutpair758" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[249]_i_1 
       (.I0(cplx_DQOut[249]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [249]),
        .O(\cplx_DQOut_reg[511]_0 [249]));
  (* SOFT_HLUTNM = "soft_lutpair870" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[24]_i_1 
       (.I0(cplx_DQOut[24]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [24]),
        .O(\cplx_DQOut_reg[511]_0 [24]));
  (* SOFT_HLUTNM = "soft_lutpair757" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[250]_i_1 
       (.I0(cplx_DQOut[250]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [250]),
        .O(\cplx_DQOut_reg[511]_0 [250]));
  (* SOFT_HLUTNM = "soft_lutpair757" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[251]_i_1 
       (.I0(cplx_DQOut[251]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [251]),
        .O(\cplx_DQOut_reg[511]_0 [251]));
  (* SOFT_HLUTNM = "soft_lutpair756" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[252]_i_1 
       (.I0(cplx_DQOut[252]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [252]),
        .O(\cplx_DQOut_reg[511]_0 [252]));
  (* SOFT_HLUTNM = "soft_lutpair756" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[253]_i_1 
       (.I0(cplx_DQOut[253]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [253]),
        .O(\cplx_DQOut_reg[511]_0 [253]));
  (* SOFT_HLUTNM = "soft_lutpair755" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[254]_i_1 
       (.I0(cplx_DQOut[254]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [254]),
        .O(\cplx_DQOut_reg[511]_0 [254]));
  (* SOFT_HLUTNM = "soft_lutpair755" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[255]_i_1 
       (.I0(cplx_DQOut[255]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [255]),
        .O(\cplx_DQOut_reg[511]_0 [255]));
  (* SOFT_HLUTNM = "soft_lutpair754" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[256]_i_1 
       (.I0(cplx_DQOut[256]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [256]),
        .O(\cplx_DQOut_reg[511]_0 [256]));
  (* SOFT_HLUTNM = "soft_lutpair754" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[257]_i_1 
       (.I0(cplx_DQOut[257]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [257]),
        .O(\cplx_DQOut_reg[511]_0 [257]));
  (* SOFT_HLUTNM = "soft_lutpair753" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[258]_i_1 
       (.I0(cplx_DQOut[258]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [258]),
        .O(\cplx_DQOut_reg[511]_0 [258]));
  (* SOFT_HLUTNM = "soft_lutpair753" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[259]_i_1 
       (.I0(cplx_DQOut[259]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [259]),
        .O(\cplx_DQOut_reg[511]_0 [259]));
  (* SOFT_HLUTNM = "soft_lutpair870" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[25]_i_1 
       (.I0(cplx_DQOut[25]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [25]),
        .O(\cplx_DQOut_reg[511]_0 [25]));
  (* SOFT_HLUTNM = "soft_lutpair752" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[260]_i_1 
       (.I0(cplx_DQOut[260]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [260]),
        .O(\cplx_DQOut_reg[511]_0 [260]));
  (* SOFT_HLUTNM = "soft_lutpair752" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[261]_i_1 
       (.I0(cplx_DQOut[261]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [261]),
        .O(\cplx_DQOut_reg[511]_0 [261]));
  (* SOFT_HLUTNM = "soft_lutpair751" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[262]_i_1 
       (.I0(cplx_DQOut[262]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [262]),
        .O(\cplx_DQOut_reg[511]_0 [262]));
  (* SOFT_HLUTNM = "soft_lutpair751" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[263]_i_1 
       (.I0(cplx_DQOut[263]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [263]),
        .O(\cplx_DQOut_reg[511]_0 [263]));
  (* SOFT_HLUTNM = "soft_lutpair750" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[264]_i_1 
       (.I0(cplx_DQOut[264]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [264]),
        .O(\cplx_DQOut_reg[511]_0 [264]));
  (* SOFT_HLUTNM = "soft_lutpair750" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[265]_i_1 
       (.I0(cplx_DQOut[265]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [265]),
        .O(\cplx_DQOut_reg[511]_0 [265]));
  (* SOFT_HLUTNM = "soft_lutpair749" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[266]_i_1 
       (.I0(cplx_DQOut[266]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [266]),
        .O(\cplx_DQOut_reg[511]_0 [266]));
  (* SOFT_HLUTNM = "soft_lutpair749" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[267]_i_1 
       (.I0(cplx_DQOut[267]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [267]),
        .O(\cplx_DQOut_reg[511]_0 [267]));
  (* SOFT_HLUTNM = "soft_lutpair748" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[268]_i_1 
       (.I0(cplx_DQOut[268]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [268]),
        .O(\cplx_DQOut_reg[511]_0 [268]));
  (* SOFT_HLUTNM = "soft_lutpair748" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[269]_i_1 
       (.I0(cplx_DQOut[269]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [269]),
        .O(\cplx_DQOut_reg[511]_0 [269]));
  (* SOFT_HLUTNM = "soft_lutpair869" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[26]_i_1 
       (.I0(cplx_DQOut[26]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [26]),
        .O(\cplx_DQOut_reg[511]_0 [26]));
  (* SOFT_HLUTNM = "soft_lutpair747" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[270]_i_1 
       (.I0(cplx_DQOut[270]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [270]),
        .O(\cplx_DQOut_reg[511]_0 [270]));
  (* SOFT_HLUTNM = "soft_lutpair747" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[271]_i_1 
       (.I0(cplx_DQOut[271]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [271]),
        .O(\cplx_DQOut_reg[511]_0 [271]));
  (* SOFT_HLUTNM = "soft_lutpair746" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[272]_i_1 
       (.I0(cplx_DQOut[272]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [272]),
        .O(\cplx_DQOut_reg[511]_0 [272]));
  (* SOFT_HLUTNM = "soft_lutpair746" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[273]_i_1 
       (.I0(cplx_DQOut[273]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [273]),
        .O(\cplx_DQOut_reg[511]_0 [273]));
  (* SOFT_HLUTNM = "soft_lutpair745" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[274]_i_1 
       (.I0(cplx_DQOut[274]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [274]),
        .O(\cplx_DQOut_reg[511]_0 [274]));
  (* SOFT_HLUTNM = "soft_lutpair745" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[275]_i_1 
       (.I0(cplx_DQOut[275]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [275]),
        .O(\cplx_DQOut_reg[511]_0 [275]));
  (* SOFT_HLUTNM = "soft_lutpair744" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[276]_i_1 
       (.I0(cplx_DQOut[276]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [276]),
        .O(\cplx_DQOut_reg[511]_0 [276]));
  (* SOFT_HLUTNM = "soft_lutpair744" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[277]_i_1 
       (.I0(cplx_DQOut[277]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [277]),
        .O(\cplx_DQOut_reg[511]_0 [277]));
  (* SOFT_HLUTNM = "soft_lutpair743" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[278]_i_1 
       (.I0(cplx_DQOut[278]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [278]),
        .O(\cplx_DQOut_reg[511]_0 [278]));
  (* SOFT_HLUTNM = "soft_lutpair743" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[279]_i_1 
       (.I0(cplx_DQOut[279]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [279]),
        .O(\cplx_DQOut_reg[511]_0 [279]));
  (* SOFT_HLUTNM = "soft_lutpair869" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[27]_i_1 
       (.I0(cplx_DQOut[27]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [27]),
        .O(\cplx_DQOut_reg[511]_0 [27]));
  (* SOFT_HLUTNM = "soft_lutpair742" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[280]_i_1 
       (.I0(cplx_DQOut[280]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [280]),
        .O(\cplx_DQOut_reg[511]_0 [280]));
  (* SOFT_HLUTNM = "soft_lutpair742" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[281]_i_1 
       (.I0(cplx_DQOut[281]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [281]),
        .O(\cplx_DQOut_reg[511]_0 [281]));
  (* SOFT_HLUTNM = "soft_lutpair741" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[282]_i_1 
       (.I0(cplx_DQOut[282]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [282]),
        .O(\cplx_DQOut_reg[511]_0 [282]));
  (* SOFT_HLUTNM = "soft_lutpair741" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[283]_i_1 
       (.I0(cplx_DQOut[283]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [283]),
        .O(\cplx_DQOut_reg[511]_0 [283]));
  (* SOFT_HLUTNM = "soft_lutpair740" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[284]_i_1 
       (.I0(cplx_DQOut[284]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [284]),
        .O(\cplx_DQOut_reg[511]_0 [284]));
  (* SOFT_HLUTNM = "soft_lutpair740" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[285]_i_1 
       (.I0(cplx_DQOut[285]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [285]),
        .O(\cplx_DQOut_reg[511]_0 [285]));
  (* SOFT_HLUTNM = "soft_lutpair739" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[286]_i_1 
       (.I0(cplx_DQOut[286]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [286]),
        .O(\cplx_DQOut_reg[511]_0 [286]));
  (* SOFT_HLUTNM = "soft_lutpair739" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[287]_i_1 
       (.I0(cplx_DQOut[287]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [287]),
        .O(\cplx_DQOut_reg[511]_0 [287]));
  (* SOFT_HLUTNM = "soft_lutpair738" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[288]_i_1 
       (.I0(cplx_DQOut[288]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [288]),
        .O(\cplx_DQOut_reg[511]_0 [288]));
  (* SOFT_HLUTNM = "soft_lutpair738" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[289]_i_1 
       (.I0(cplx_DQOut[289]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [289]),
        .O(\cplx_DQOut_reg[511]_0 [289]));
  (* SOFT_HLUTNM = "soft_lutpair868" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[28]_i_1 
       (.I0(cplx_DQOut[28]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [28]),
        .O(\cplx_DQOut_reg[511]_0 [28]));
  (* SOFT_HLUTNM = "soft_lutpair737" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[290]_i_1 
       (.I0(cplx_DQOut[290]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [290]),
        .O(\cplx_DQOut_reg[511]_0 [290]));
  (* SOFT_HLUTNM = "soft_lutpair737" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[291]_i_1 
       (.I0(cplx_DQOut[291]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [291]),
        .O(\cplx_DQOut_reg[511]_0 [291]));
  (* SOFT_HLUTNM = "soft_lutpair736" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[292]_i_1 
       (.I0(cplx_DQOut[292]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [292]),
        .O(\cplx_DQOut_reg[511]_0 [292]));
  (* SOFT_HLUTNM = "soft_lutpair736" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[293]_i_1 
       (.I0(cplx_DQOut[293]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [293]),
        .O(\cplx_DQOut_reg[511]_0 [293]));
  (* SOFT_HLUTNM = "soft_lutpair735" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[294]_i_1 
       (.I0(cplx_DQOut[294]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [294]),
        .O(\cplx_DQOut_reg[511]_0 [294]));
  (* SOFT_HLUTNM = "soft_lutpair735" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[295]_i_1 
       (.I0(cplx_DQOut[295]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [295]),
        .O(\cplx_DQOut_reg[511]_0 [295]));
  (* SOFT_HLUTNM = "soft_lutpair734" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[296]_i_1 
       (.I0(cplx_DQOut[296]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [296]),
        .O(\cplx_DQOut_reg[511]_0 [296]));
  (* SOFT_HLUTNM = "soft_lutpair734" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[297]_i_1 
       (.I0(cplx_DQOut[297]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [297]),
        .O(\cplx_DQOut_reg[511]_0 [297]));
  (* SOFT_HLUTNM = "soft_lutpair733" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[298]_i_1 
       (.I0(cplx_DQOut[298]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [298]),
        .O(\cplx_DQOut_reg[511]_0 [298]));
  (* SOFT_HLUTNM = "soft_lutpair733" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[299]_i_1 
       (.I0(cplx_DQOut[299]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [299]),
        .O(\cplx_DQOut_reg[511]_0 [299]));
  (* SOFT_HLUTNM = "soft_lutpair868" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[29]_i_1 
       (.I0(cplx_DQOut[29]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [29]),
        .O(\cplx_DQOut_reg[511]_0 [29]));
  (* SOFT_HLUTNM = "soft_lutpair881" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[2]_i_1 
       (.I0(cplx_DQOut[2]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [2]),
        .O(\cplx_DQOut_reg[511]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair732" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[300]_i_1 
       (.I0(cplx_DQOut[300]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [300]),
        .O(\cplx_DQOut_reg[511]_0 [300]));
  (* SOFT_HLUTNM = "soft_lutpair732" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[301]_i_1 
       (.I0(cplx_DQOut[301]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [301]),
        .O(\cplx_DQOut_reg[511]_0 [301]));
  (* SOFT_HLUTNM = "soft_lutpair731" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[302]_i_1 
       (.I0(cplx_DQOut[302]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [302]),
        .O(\cplx_DQOut_reg[511]_0 [302]));
  (* SOFT_HLUTNM = "soft_lutpair731" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[303]_i_1 
       (.I0(cplx_DQOut[303]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [303]),
        .O(\cplx_DQOut_reg[511]_0 [303]));
  (* SOFT_HLUTNM = "soft_lutpair730" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[304]_i_1 
       (.I0(cplx_DQOut[304]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [304]),
        .O(\cplx_DQOut_reg[511]_0 [304]));
  (* SOFT_HLUTNM = "soft_lutpair730" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[305]_i_1 
       (.I0(cplx_DQOut[305]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [305]),
        .O(\cplx_DQOut_reg[511]_0 [305]));
  (* SOFT_HLUTNM = "soft_lutpair729" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[306]_i_1 
       (.I0(cplx_DQOut[306]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [306]),
        .O(\cplx_DQOut_reg[511]_0 [306]));
  (* SOFT_HLUTNM = "soft_lutpair729" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[307]_i_1 
       (.I0(cplx_DQOut[307]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [307]),
        .O(\cplx_DQOut_reg[511]_0 [307]));
  (* SOFT_HLUTNM = "soft_lutpair728" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[308]_i_1 
       (.I0(cplx_DQOut[308]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [308]),
        .O(\cplx_DQOut_reg[511]_0 [308]));
  (* SOFT_HLUTNM = "soft_lutpair728" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[309]_i_1 
       (.I0(cplx_DQOut[309]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [309]),
        .O(\cplx_DQOut_reg[511]_0 [309]));
  (* SOFT_HLUTNM = "soft_lutpair867" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[30]_i_1 
       (.I0(cplx_DQOut[30]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [30]),
        .O(\cplx_DQOut_reg[511]_0 [30]));
  (* SOFT_HLUTNM = "soft_lutpair727" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[310]_i_1 
       (.I0(cplx_DQOut[310]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [310]),
        .O(\cplx_DQOut_reg[511]_0 [310]));
  (* SOFT_HLUTNM = "soft_lutpair727" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[311]_i_1 
       (.I0(cplx_DQOut[311]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [311]),
        .O(\cplx_DQOut_reg[511]_0 [311]));
  (* SOFT_HLUTNM = "soft_lutpair726" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[312]_i_1 
       (.I0(cplx_DQOut[312]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [312]),
        .O(\cplx_DQOut_reg[511]_0 [312]));
  (* SOFT_HLUTNM = "soft_lutpair726" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[313]_i_1 
       (.I0(cplx_DQOut[313]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [313]),
        .O(\cplx_DQOut_reg[511]_0 [313]));
  (* SOFT_HLUTNM = "soft_lutpair725" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[314]_i_1 
       (.I0(cplx_DQOut[314]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [314]),
        .O(\cplx_DQOut_reg[511]_0 [314]));
  (* SOFT_HLUTNM = "soft_lutpair725" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[315]_i_1 
       (.I0(cplx_DQOut[315]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [315]),
        .O(\cplx_DQOut_reg[511]_0 [315]));
  (* SOFT_HLUTNM = "soft_lutpair724" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[316]_i_1 
       (.I0(cplx_DQOut[316]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [316]),
        .O(\cplx_DQOut_reg[511]_0 [316]));
  (* SOFT_HLUTNM = "soft_lutpair724" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[317]_i_1 
       (.I0(cplx_DQOut[317]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [317]),
        .O(\cplx_DQOut_reg[511]_0 [317]));
  (* SOFT_HLUTNM = "soft_lutpair723" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[318]_i_1 
       (.I0(cplx_DQOut[318]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [318]),
        .O(\cplx_DQOut_reg[511]_0 [318]));
  (* SOFT_HLUTNM = "soft_lutpair723" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[319]_i_1 
       (.I0(cplx_DQOut[319]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [319]),
        .O(\cplx_DQOut_reg[511]_0 [319]));
  (* SOFT_HLUTNM = "soft_lutpair867" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[31]_i_1 
       (.I0(cplx_DQOut[31]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [31]),
        .O(\cplx_DQOut_reg[511]_0 [31]));
  (* SOFT_HLUTNM = "soft_lutpair722" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[320]_i_1 
       (.I0(cplx_DQOut[320]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [320]),
        .O(\cplx_DQOut_reg[511]_0 [320]));
  (* SOFT_HLUTNM = "soft_lutpair722" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[321]_i_1 
       (.I0(cplx_DQOut[321]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [321]),
        .O(\cplx_DQOut_reg[511]_0 [321]));
  (* SOFT_HLUTNM = "soft_lutpair721" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[322]_i_1 
       (.I0(cplx_DQOut[322]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [322]),
        .O(\cplx_DQOut_reg[511]_0 [322]));
  (* SOFT_HLUTNM = "soft_lutpair721" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[323]_i_1 
       (.I0(cplx_DQOut[323]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [323]),
        .O(\cplx_DQOut_reg[511]_0 [323]));
  (* SOFT_HLUTNM = "soft_lutpair720" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[324]_i_1 
       (.I0(cplx_DQOut[324]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [324]),
        .O(\cplx_DQOut_reg[511]_0 [324]));
  (* SOFT_HLUTNM = "soft_lutpair720" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[325]_i_1 
       (.I0(cplx_DQOut[325]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [325]),
        .O(\cplx_DQOut_reg[511]_0 [325]));
  (* SOFT_HLUTNM = "soft_lutpair719" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[326]_i_1 
       (.I0(cplx_DQOut[326]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [326]),
        .O(\cplx_DQOut_reg[511]_0 [326]));
  (* SOFT_HLUTNM = "soft_lutpair719" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[327]_i_1 
       (.I0(cplx_DQOut[327]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [327]),
        .O(\cplx_DQOut_reg[511]_0 [327]));
  (* SOFT_HLUTNM = "soft_lutpair718" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[328]_i_1 
       (.I0(cplx_DQOut[328]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [328]),
        .O(\cplx_DQOut_reg[511]_0 [328]));
  (* SOFT_HLUTNM = "soft_lutpair718" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[329]_i_1 
       (.I0(cplx_DQOut[329]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [329]),
        .O(\cplx_DQOut_reg[511]_0 [329]));
  (* SOFT_HLUTNM = "soft_lutpair866" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[32]_i_1 
       (.I0(cplx_DQOut[32]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [32]),
        .O(\cplx_DQOut_reg[511]_0 [32]));
  (* SOFT_HLUTNM = "soft_lutpair717" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[330]_i_1 
       (.I0(cplx_DQOut[330]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [330]),
        .O(\cplx_DQOut_reg[511]_0 [330]));
  (* SOFT_HLUTNM = "soft_lutpair717" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[331]_i_1 
       (.I0(cplx_DQOut[331]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [331]),
        .O(\cplx_DQOut_reg[511]_0 [331]));
  (* SOFT_HLUTNM = "soft_lutpair716" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[332]_i_1 
       (.I0(cplx_DQOut[332]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [332]),
        .O(\cplx_DQOut_reg[511]_0 [332]));
  (* SOFT_HLUTNM = "soft_lutpair716" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[333]_i_1 
       (.I0(cplx_DQOut[333]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [333]),
        .O(\cplx_DQOut_reg[511]_0 [333]));
  (* SOFT_HLUTNM = "soft_lutpair715" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[334]_i_1 
       (.I0(cplx_DQOut[334]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [334]),
        .O(\cplx_DQOut_reg[511]_0 [334]));
  (* SOFT_HLUTNM = "soft_lutpair715" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[335]_i_1 
       (.I0(cplx_DQOut[335]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [335]),
        .O(\cplx_DQOut_reg[511]_0 [335]));
  (* SOFT_HLUTNM = "soft_lutpair714" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[336]_i_1 
       (.I0(cplx_DQOut[336]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [336]),
        .O(\cplx_DQOut_reg[511]_0 [336]));
  (* SOFT_HLUTNM = "soft_lutpair714" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[337]_i_1 
       (.I0(cplx_DQOut[337]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [337]),
        .O(\cplx_DQOut_reg[511]_0 [337]));
  (* SOFT_HLUTNM = "soft_lutpair713" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[338]_i_1 
       (.I0(cplx_DQOut[338]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [338]),
        .O(\cplx_DQOut_reg[511]_0 [338]));
  (* SOFT_HLUTNM = "soft_lutpair713" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[339]_i_1 
       (.I0(cplx_DQOut[339]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [339]),
        .O(\cplx_DQOut_reg[511]_0 [339]));
  (* SOFT_HLUTNM = "soft_lutpair866" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[33]_i_1 
       (.I0(cplx_DQOut[33]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [33]),
        .O(\cplx_DQOut_reg[511]_0 [33]));
  (* SOFT_HLUTNM = "soft_lutpair712" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[340]_i_1 
       (.I0(cplx_DQOut[340]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [340]),
        .O(\cplx_DQOut_reg[511]_0 [340]));
  (* SOFT_HLUTNM = "soft_lutpair712" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[341]_i_1 
       (.I0(cplx_DQOut[341]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [341]),
        .O(\cplx_DQOut_reg[511]_0 [341]));
  (* SOFT_HLUTNM = "soft_lutpair711" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[342]_i_1 
       (.I0(cplx_DQOut[342]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [342]),
        .O(\cplx_DQOut_reg[511]_0 [342]));
  (* SOFT_HLUTNM = "soft_lutpair711" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[343]_i_1 
       (.I0(cplx_DQOut[343]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [343]),
        .O(\cplx_DQOut_reg[511]_0 [343]));
  (* SOFT_HLUTNM = "soft_lutpair710" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[344]_i_1 
       (.I0(cplx_DQOut[344]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [344]),
        .O(\cplx_DQOut_reg[511]_0 [344]));
  (* SOFT_HLUTNM = "soft_lutpair710" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[345]_i_1 
       (.I0(cplx_DQOut[345]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [345]),
        .O(\cplx_DQOut_reg[511]_0 [345]));
  (* SOFT_HLUTNM = "soft_lutpair709" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[346]_i_1 
       (.I0(cplx_DQOut[346]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [346]),
        .O(\cplx_DQOut_reg[511]_0 [346]));
  (* SOFT_HLUTNM = "soft_lutpair709" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[347]_i_1 
       (.I0(cplx_DQOut[347]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [347]),
        .O(\cplx_DQOut_reg[511]_0 [347]));
  (* SOFT_HLUTNM = "soft_lutpair708" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[348]_i_1 
       (.I0(cplx_DQOut[348]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [348]),
        .O(\cplx_DQOut_reg[511]_0 [348]));
  (* SOFT_HLUTNM = "soft_lutpair708" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[349]_i_1 
       (.I0(cplx_DQOut[349]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [349]),
        .O(\cplx_DQOut_reg[511]_0 [349]));
  (* SOFT_HLUTNM = "soft_lutpair865" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[34]_i_1 
       (.I0(cplx_DQOut[34]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [34]),
        .O(\cplx_DQOut_reg[511]_0 [34]));
  (* SOFT_HLUTNM = "soft_lutpair707" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[350]_i_1 
       (.I0(cplx_DQOut[350]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [350]),
        .O(\cplx_DQOut_reg[511]_0 [350]));
  (* SOFT_HLUTNM = "soft_lutpair707" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[351]_i_1 
       (.I0(cplx_DQOut[351]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [351]),
        .O(\cplx_DQOut_reg[511]_0 [351]));
  (* SOFT_HLUTNM = "soft_lutpair706" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[352]_i_1 
       (.I0(cplx_DQOut[352]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [352]),
        .O(\cplx_DQOut_reg[511]_0 [352]));
  (* SOFT_HLUTNM = "soft_lutpair706" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[353]_i_1 
       (.I0(cplx_DQOut[353]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [353]),
        .O(\cplx_DQOut_reg[511]_0 [353]));
  (* SOFT_HLUTNM = "soft_lutpair705" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[354]_i_1 
       (.I0(cplx_DQOut[354]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [354]),
        .O(\cplx_DQOut_reg[511]_0 [354]));
  (* SOFT_HLUTNM = "soft_lutpair705" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[355]_i_1 
       (.I0(cplx_DQOut[355]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [355]),
        .O(\cplx_DQOut_reg[511]_0 [355]));
  (* SOFT_HLUTNM = "soft_lutpair704" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[356]_i_1 
       (.I0(cplx_DQOut[356]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [356]),
        .O(\cplx_DQOut_reg[511]_0 [356]));
  (* SOFT_HLUTNM = "soft_lutpair704" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[357]_i_1 
       (.I0(cplx_DQOut[357]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [357]),
        .O(\cplx_DQOut_reg[511]_0 [357]));
  (* SOFT_HLUTNM = "soft_lutpair703" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[358]_i_1 
       (.I0(cplx_DQOut[358]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [358]),
        .O(\cplx_DQOut_reg[511]_0 [358]));
  (* SOFT_HLUTNM = "soft_lutpair703" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[359]_i_1 
       (.I0(cplx_DQOut[359]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [359]),
        .O(\cplx_DQOut_reg[511]_0 [359]));
  (* SOFT_HLUTNM = "soft_lutpair865" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[35]_i_1 
       (.I0(cplx_DQOut[35]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [35]),
        .O(\cplx_DQOut_reg[511]_0 [35]));
  (* SOFT_HLUTNM = "soft_lutpair702" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[360]_i_1 
       (.I0(cplx_DQOut[360]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [360]),
        .O(\cplx_DQOut_reg[511]_0 [360]));
  (* SOFT_HLUTNM = "soft_lutpair702" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[361]_i_1 
       (.I0(cplx_DQOut[361]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [361]),
        .O(\cplx_DQOut_reg[511]_0 [361]));
  (* SOFT_HLUTNM = "soft_lutpair701" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[362]_i_1 
       (.I0(cplx_DQOut[362]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [362]),
        .O(\cplx_DQOut_reg[511]_0 [362]));
  (* SOFT_HLUTNM = "soft_lutpair701" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[363]_i_1 
       (.I0(cplx_DQOut[363]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [363]),
        .O(\cplx_DQOut_reg[511]_0 [363]));
  (* SOFT_HLUTNM = "soft_lutpair700" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[364]_i_1 
       (.I0(cplx_DQOut[364]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [364]),
        .O(\cplx_DQOut_reg[511]_0 [364]));
  (* SOFT_HLUTNM = "soft_lutpair700" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[365]_i_1 
       (.I0(cplx_DQOut[365]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [365]),
        .O(\cplx_DQOut_reg[511]_0 [365]));
  (* SOFT_HLUTNM = "soft_lutpair699" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[366]_i_1 
       (.I0(cplx_DQOut[366]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [366]),
        .O(\cplx_DQOut_reg[511]_0 [366]));
  (* SOFT_HLUTNM = "soft_lutpair699" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[367]_i_1 
       (.I0(cplx_DQOut[367]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [367]),
        .O(\cplx_DQOut_reg[511]_0 [367]));
  (* SOFT_HLUTNM = "soft_lutpair698" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[368]_i_1 
       (.I0(cplx_DQOut[368]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [368]),
        .O(\cplx_DQOut_reg[511]_0 [368]));
  (* SOFT_HLUTNM = "soft_lutpair698" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[369]_i_1 
       (.I0(cplx_DQOut[369]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [369]),
        .O(\cplx_DQOut_reg[511]_0 [369]));
  (* SOFT_HLUTNM = "soft_lutpair864" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[36]_i_1 
       (.I0(cplx_DQOut[36]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [36]),
        .O(\cplx_DQOut_reg[511]_0 [36]));
  (* SOFT_HLUTNM = "soft_lutpair697" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[370]_i_1 
       (.I0(cplx_DQOut[370]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [370]),
        .O(\cplx_DQOut_reg[511]_0 [370]));
  (* SOFT_HLUTNM = "soft_lutpair697" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[371]_i_1 
       (.I0(cplx_DQOut[371]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [371]),
        .O(\cplx_DQOut_reg[511]_0 [371]));
  (* SOFT_HLUTNM = "soft_lutpair696" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[372]_i_1 
       (.I0(cplx_DQOut[372]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [372]),
        .O(\cplx_DQOut_reg[511]_0 [372]));
  (* SOFT_HLUTNM = "soft_lutpair696" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[373]_i_1 
       (.I0(cplx_DQOut[373]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [373]),
        .O(\cplx_DQOut_reg[511]_0 [373]));
  (* SOFT_HLUTNM = "soft_lutpair695" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[374]_i_1 
       (.I0(cplx_DQOut[374]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [374]),
        .O(\cplx_DQOut_reg[511]_0 [374]));
  (* SOFT_HLUTNM = "soft_lutpair695" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[375]_i_1 
       (.I0(cplx_DQOut[375]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [375]),
        .O(\cplx_DQOut_reg[511]_0 [375]));
  (* SOFT_HLUTNM = "soft_lutpair694" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[376]_i_1 
       (.I0(cplx_DQOut[376]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [376]),
        .O(\cplx_DQOut_reg[511]_0 [376]));
  (* SOFT_HLUTNM = "soft_lutpair694" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[377]_i_1 
       (.I0(cplx_DQOut[377]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [377]),
        .O(\cplx_DQOut_reg[511]_0 [377]));
  (* SOFT_HLUTNM = "soft_lutpair693" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[378]_i_1 
       (.I0(cplx_DQOut[378]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [378]),
        .O(\cplx_DQOut_reg[511]_0 [378]));
  (* SOFT_HLUTNM = "soft_lutpair693" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[379]_i_1 
       (.I0(cplx_DQOut[379]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [379]),
        .O(\cplx_DQOut_reg[511]_0 [379]));
  (* SOFT_HLUTNM = "soft_lutpair864" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[37]_i_1 
       (.I0(cplx_DQOut[37]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [37]),
        .O(\cplx_DQOut_reg[511]_0 [37]));
  (* SOFT_HLUTNM = "soft_lutpair692" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[380]_i_1 
       (.I0(cplx_DQOut[380]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [380]),
        .O(\cplx_DQOut_reg[511]_0 [380]));
  (* SOFT_HLUTNM = "soft_lutpair692" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[381]_i_1 
       (.I0(cplx_DQOut[381]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [381]),
        .O(\cplx_DQOut_reg[511]_0 [381]));
  (* SOFT_HLUTNM = "soft_lutpair691" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[382]_i_1 
       (.I0(cplx_DQOut[382]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [382]),
        .O(\cplx_DQOut_reg[511]_0 [382]));
  (* SOFT_HLUTNM = "soft_lutpair691" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[383]_i_1 
       (.I0(cplx_DQOut[383]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [383]),
        .O(\cplx_DQOut_reg[511]_0 [383]));
  (* SOFT_HLUTNM = "soft_lutpair690" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[384]_i_1 
       (.I0(cplx_DQOut[384]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [384]),
        .O(\cplx_DQOut_reg[511]_0 [384]));
  (* SOFT_HLUTNM = "soft_lutpair690" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[385]_i_1 
       (.I0(cplx_DQOut[385]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [385]),
        .O(\cplx_DQOut_reg[511]_0 [385]));
  (* SOFT_HLUTNM = "soft_lutpair689" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[386]_i_1 
       (.I0(cplx_DQOut[386]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [386]),
        .O(\cplx_DQOut_reg[511]_0 [386]));
  (* SOFT_HLUTNM = "soft_lutpair689" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[387]_i_1 
       (.I0(cplx_DQOut[387]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [387]),
        .O(\cplx_DQOut_reg[511]_0 [387]));
  (* SOFT_HLUTNM = "soft_lutpair688" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[388]_i_1 
       (.I0(cplx_DQOut[388]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [388]),
        .O(\cplx_DQOut_reg[511]_0 [388]));
  (* SOFT_HLUTNM = "soft_lutpair688" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[389]_i_1 
       (.I0(cplx_DQOut[389]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [389]),
        .O(\cplx_DQOut_reg[511]_0 [389]));
  (* SOFT_HLUTNM = "soft_lutpair863" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[38]_i_1 
       (.I0(cplx_DQOut[38]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [38]),
        .O(\cplx_DQOut_reg[511]_0 [38]));
  (* SOFT_HLUTNM = "soft_lutpair687" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[390]_i_1 
       (.I0(cplx_DQOut[390]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [390]),
        .O(\cplx_DQOut_reg[511]_0 [390]));
  (* SOFT_HLUTNM = "soft_lutpair687" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[391]_i_1 
       (.I0(cplx_DQOut[391]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [391]),
        .O(\cplx_DQOut_reg[511]_0 [391]));
  (* SOFT_HLUTNM = "soft_lutpair686" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[392]_i_1 
       (.I0(cplx_DQOut[392]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [392]),
        .O(\cplx_DQOut_reg[511]_0 [392]));
  (* SOFT_HLUTNM = "soft_lutpair686" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[393]_i_1 
       (.I0(cplx_DQOut[393]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [393]),
        .O(\cplx_DQOut_reg[511]_0 [393]));
  (* SOFT_HLUTNM = "soft_lutpair685" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[394]_i_1 
       (.I0(cplx_DQOut[394]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [394]),
        .O(\cplx_DQOut_reg[511]_0 [394]));
  (* SOFT_HLUTNM = "soft_lutpair685" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[395]_i_1 
       (.I0(cplx_DQOut[395]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [395]),
        .O(\cplx_DQOut_reg[511]_0 [395]));
  (* SOFT_HLUTNM = "soft_lutpair684" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[396]_i_1 
       (.I0(cplx_DQOut[396]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [396]),
        .O(\cplx_DQOut_reg[511]_0 [396]));
  (* SOFT_HLUTNM = "soft_lutpair684" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[397]_i_1 
       (.I0(cplx_DQOut[397]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [397]),
        .O(\cplx_DQOut_reg[511]_0 [397]));
  (* SOFT_HLUTNM = "soft_lutpair683" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[398]_i_1 
       (.I0(cplx_DQOut[398]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [398]),
        .O(\cplx_DQOut_reg[511]_0 [398]));
  (* SOFT_HLUTNM = "soft_lutpair683" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[399]_i_1 
       (.I0(cplx_DQOut[399]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [399]),
        .O(\cplx_DQOut_reg[511]_0 [399]));
  (* SOFT_HLUTNM = "soft_lutpair863" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[39]_i_1 
       (.I0(cplx_DQOut[39]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [39]),
        .O(\cplx_DQOut_reg[511]_0 [39]));
  (* SOFT_HLUTNM = "soft_lutpair881" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[3]_i_1 
       (.I0(cplx_DQOut[3]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [3]),
        .O(\cplx_DQOut_reg[511]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair682" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[400]_i_1 
       (.I0(cplx_DQOut[400]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [400]),
        .O(\cplx_DQOut_reg[511]_0 [400]));
  (* SOFT_HLUTNM = "soft_lutpair682" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[401]_i_1 
       (.I0(cplx_DQOut[401]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [401]),
        .O(\cplx_DQOut_reg[511]_0 [401]));
  (* SOFT_HLUTNM = "soft_lutpair681" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[402]_i_1 
       (.I0(cplx_DQOut[402]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [402]),
        .O(\cplx_DQOut_reg[511]_0 [402]));
  (* SOFT_HLUTNM = "soft_lutpair681" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[403]_i_1 
       (.I0(cplx_DQOut[403]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [403]),
        .O(\cplx_DQOut_reg[511]_0 [403]));
  (* SOFT_HLUTNM = "soft_lutpair680" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[404]_i_1 
       (.I0(cplx_DQOut[404]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [404]),
        .O(\cplx_DQOut_reg[511]_0 [404]));
  (* SOFT_HLUTNM = "soft_lutpair680" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[405]_i_1 
       (.I0(cplx_DQOut[405]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [405]),
        .O(\cplx_DQOut_reg[511]_0 [405]));
  (* SOFT_HLUTNM = "soft_lutpair679" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[406]_i_1 
       (.I0(cplx_DQOut[406]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [406]),
        .O(\cplx_DQOut_reg[511]_0 [406]));
  (* SOFT_HLUTNM = "soft_lutpair679" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[407]_i_1 
       (.I0(cplx_DQOut[407]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [407]),
        .O(\cplx_DQOut_reg[511]_0 [407]));
  (* SOFT_HLUTNM = "soft_lutpair678" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[408]_i_1 
       (.I0(cplx_DQOut[408]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [408]),
        .O(\cplx_DQOut_reg[511]_0 [408]));
  (* SOFT_HLUTNM = "soft_lutpair678" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[409]_i_1 
       (.I0(cplx_DQOut[409]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [409]),
        .O(\cplx_DQOut_reg[511]_0 [409]));
  (* SOFT_HLUTNM = "soft_lutpair862" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[40]_i_1 
       (.I0(cplx_DQOut[40]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [40]),
        .O(\cplx_DQOut_reg[511]_0 [40]));
  (* SOFT_HLUTNM = "soft_lutpair677" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[410]_i_1 
       (.I0(cplx_DQOut[410]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [410]),
        .O(\cplx_DQOut_reg[511]_0 [410]));
  (* SOFT_HLUTNM = "soft_lutpair677" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[411]_i_1 
       (.I0(cplx_DQOut[411]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [411]),
        .O(\cplx_DQOut_reg[511]_0 [411]));
  (* SOFT_HLUTNM = "soft_lutpair676" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[412]_i_1 
       (.I0(cplx_DQOut[412]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [412]),
        .O(\cplx_DQOut_reg[511]_0 [412]));
  (* SOFT_HLUTNM = "soft_lutpair676" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[413]_i_1 
       (.I0(cplx_DQOut[413]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [413]),
        .O(\cplx_DQOut_reg[511]_0 [413]));
  (* SOFT_HLUTNM = "soft_lutpair675" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[414]_i_1 
       (.I0(cplx_DQOut[414]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [414]),
        .O(\cplx_DQOut_reg[511]_0 [414]));
  (* SOFT_HLUTNM = "soft_lutpair675" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[415]_i_1 
       (.I0(cplx_DQOut[415]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [415]),
        .O(\cplx_DQOut_reg[511]_0 [415]));
  (* SOFT_HLUTNM = "soft_lutpair674" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[416]_i_1 
       (.I0(cplx_DQOut[416]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [416]),
        .O(\cplx_DQOut_reg[511]_0 [416]));
  (* SOFT_HLUTNM = "soft_lutpair674" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[417]_i_1 
       (.I0(cplx_DQOut[417]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [417]),
        .O(\cplx_DQOut_reg[511]_0 [417]));
  (* SOFT_HLUTNM = "soft_lutpair673" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[418]_i_1 
       (.I0(cplx_DQOut[418]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [418]),
        .O(\cplx_DQOut_reg[511]_0 [418]));
  (* SOFT_HLUTNM = "soft_lutpair673" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[419]_i_1 
       (.I0(cplx_DQOut[419]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [419]),
        .O(\cplx_DQOut_reg[511]_0 [419]));
  (* SOFT_HLUTNM = "soft_lutpair862" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[41]_i_1 
       (.I0(cplx_DQOut[41]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [41]),
        .O(\cplx_DQOut_reg[511]_0 [41]));
  (* SOFT_HLUTNM = "soft_lutpair672" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[420]_i_1 
       (.I0(cplx_DQOut[420]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [420]),
        .O(\cplx_DQOut_reg[511]_0 [420]));
  (* SOFT_HLUTNM = "soft_lutpair672" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[421]_i_1 
       (.I0(cplx_DQOut[421]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [421]),
        .O(\cplx_DQOut_reg[511]_0 [421]));
  (* SOFT_HLUTNM = "soft_lutpair671" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[422]_i_1 
       (.I0(cplx_DQOut[422]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [422]),
        .O(\cplx_DQOut_reg[511]_0 [422]));
  (* SOFT_HLUTNM = "soft_lutpair671" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[423]_i_1 
       (.I0(cplx_DQOut[423]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [423]),
        .O(\cplx_DQOut_reg[511]_0 [423]));
  (* SOFT_HLUTNM = "soft_lutpair670" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[424]_i_1 
       (.I0(cplx_DQOut[424]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [424]),
        .O(\cplx_DQOut_reg[511]_0 [424]));
  (* SOFT_HLUTNM = "soft_lutpair670" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[425]_i_1 
       (.I0(cplx_DQOut[425]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [425]),
        .O(\cplx_DQOut_reg[511]_0 [425]));
  (* SOFT_HLUTNM = "soft_lutpair669" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[426]_i_1 
       (.I0(cplx_DQOut[426]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [426]),
        .O(\cplx_DQOut_reg[511]_0 [426]));
  (* SOFT_HLUTNM = "soft_lutpair669" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[427]_i_1 
       (.I0(cplx_DQOut[427]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [427]),
        .O(\cplx_DQOut_reg[511]_0 [427]));
  (* SOFT_HLUTNM = "soft_lutpair668" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[428]_i_1 
       (.I0(cplx_DQOut[428]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [428]),
        .O(\cplx_DQOut_reg[511]_0 [428]));
  (* SOFT_HLUTNM = "soft_lutpair668" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[429]_i_1 
       (.I0(cplx_DQOut[429]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [429]),
        .O(\cplx_DQOut_reg[511]_0 [429]));
  (* SOFT_HLUTNM = "soft_lutpair861" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[42]_i_1 
       (.I0(cplx_DQOut[42]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [42]),
        .O(\cplx_DQOut_reg[511]_0 [42]));
  (* SOFT_HLUTNM = "soft_lutpair667" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[430]_i_1 
       (.I0(cplx_DQOut[430]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [430]),
        .O(\cplx_DQOut_reg[511]_0 [430]));
  (* SOFT_HLUTNM = "soft_lutpair667" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[431]_i_1 
       (.I0(cplx_DQOut[431]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [431]),
        .O(\cplx_DQOut_reg[511]_0 [431]));
  (* SOFT_HLUTNM = "soft_lutpair666" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[432]_i_1 
       (.I0(cplx_DQOut[432]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [432]),
        .O(\cplx_DQOut_reg[511]_0 [432]));
  (* SOFT_HLUTNM = "soft_lutpair666" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[433]_i_1 
       (.I0(cplx_DQOut[433]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [433]),
        .O(\cplx_DQOut_reg[511]_0 [433]));
  (* SOFT_HLUTNM = "soft_lutpair665" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[434]_i_1 
       (.I0(cplx_DQOut[434]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [434]),
        .O(\cplx_DQOut_reg[511]_0 [434]));
  (* SOFT_HLUTNM = "soft_lutpair665" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[435]_i_1 
       (.I0(cplx_DQOut[435]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [435]),
        .O(\cplx_DQOut_reg[511]_0 [435]));
  (* SOFT_HLUTNM = "soft_lutpair664" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[436]_i_1 
       (.I0(cplx_DQOut[436]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [436]),
        .O(\cplx_DQOut_reg[511]_0 [436]));
  (* SOFT_HLUTNM = "soft_lutpair664" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[437]_i_1 
       (.I0(cplx_DQOut[437]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [437]),
        .O(\cplx_DQOut_reg[511]_0 [437]));
  (* SOFT_HLUTNM = "soft_lutpair663" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[438]_i_1 
       (.I0(cplx_DQOut[438]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [438]),
        .O(\cplx_DQOut_reg[511]_0 [438]));
  (* SOFT_HLUTNM = "soft_lutpair663" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[439]_i_1 
       (.I0(cplx_DQOut[439]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [439]),
        .O(\cplx_DQOut_reg[511]_0 [439]));
  (* SOFT_HLUTNM = "soft_lutpair861" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[43]_i_1 
       (.I0(cplx_DQOut[43]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [43]),
        .O(\cplx_DQOut_reg[511]_0 [43]));
  (* SOFT_HLUTNM = "soft_lutpair662" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[440]_i_1 
       (.I0(cplx_DQOut[440]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [440]),
        .O(\cplx_DQOut_reg[511]_0 [440]));
  (* SOFT_HLUTNM = "soft_lutpair662" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[441]_i_1 
       (.I0(cplx_DQOut[441]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [441]),
        .O(\cplx_DQOut_reg[511]_0 [441]));
  (* SOFT_HLUTNM = "soft_lutpair661" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[442]_i_1 
       (.I0(cplx_DQOut[442]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [442]),
        .O(\cplx_DQOut_reg[511]_0 [442]));
  (* SOFT_HLUTNM = "soft_lutpair661" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[443]_i_1 
       (.I0(cplx_DQOut[443]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [443]),
        .O(\cplx_DQOut_reg[511]_0 [443]));
  (* SOFT_HLUTNM = "soft_lutpair660" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[444]_i_1 
       (.I0(cplx_DQOut[444]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [444]),
        .O(\cplx_DQOut_reg[511]_0 [444]));
  (* SOFT_HLUTNM = "soft_lutpair660" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[445]_i_1 
       (.I0(cplx_DQOut[445]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [445]),
        .O(\cplx_DQOut_reg[511]_0 [445]));
  (* SOFT_HLUTNM = "soft_lutpair659" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[446]_i_1 
       (.I0(cplx_DQOut[446]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [446]),
        .O(\cplx_DQOut_reg[511]_0 [446]));
  (* SOFT_HLUTNM = "soft_lutpair659" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[447]_i_1 
       (.I0(cplx_DQOut[447]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [447]),
        .O(\cplx_DQOut_reg[511]_0 [447]));
  (* SOFT_HLUTNM = "soft_lutpair658" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[448]_i_1 
       (.I0(cplx_DQOut[448]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [448]),
        .O(\cplx_DQOut_reg[511]_0 [448]));
  (* SOFT_HLUTNM = "soft_lutpair658" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[449]_i_1 
       (.I0(cplx_DQOut[449]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [449]),
        .O(\cplx_DQOut_reg[511]_0 [449]));
  (* SOFT_HLUTNM = "soft_lutpair860" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[44]_i_1 
       (.I0(cplx_DQOut[44]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [44]),
        .O(\cplx_DQOut_reg[511]_0 [44]));
  (* SOFT_HLUTNM = "soft_lutpair657" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[450]_i_1 
       (.I0(cplx_DQOut[450]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [450]),
        .O(\cplx_DQOut_reg[511]_0 [450]));
  (* SOFT_HLUTNM = "soft_lutpair657" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[451]_i_1 
       (.I0(cplx_DQOut[451]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [451]),
        .O(\cplx_DQOut_reg[511]_0 [451]));
  (* SOFT_HLUTNM = "soft_lutpair656" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[452]_i_1 
       (.I0(cplx_DQOut[452]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [452]),
        .O(\cplx_DQOut_reg[511]_0 [452]));
  (* SOFT_HLUTNM = "soft_lutpair656" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[453]_i_1 
       (.I0(cplx_DQOut[453]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [453]),
        .O(\cplx_DQOut_reg[511]_0 [453]));
  (* SOFT_HLUTNM = "soft_lutpair655" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[454]_i_1 
       (.I0(cplx_DQOut[454]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [454]),
        .O(\cplx_DQOut_reg[511]_0 [454]));
  (* SOFT_HLUTNM = "soft_lutpair655" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[455]_i_1 
       (.I0(cplx_DQOut[455]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [455]),
        .O(\cplx_DQOut_reg[511]_0 [455]));
  (* SOFT_HLUTNM = "soft_lutpair654" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[456]_i_1 
       (.I0(cplx_DQOut[456]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [456]),
        .O(\cplx_DQOut_reg[511]_0 [456]));
  (* SOFT_HLUTNM = "soft_lutpair654" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[457]_i_1 
       (.I0(cplx_DQOut[457]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [457]),
        .O(\cplx_DQOut_reg[511]_0 [457]));
  (* SOFT_HLUTNM = "soft_lutpair653" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[458]_i_1 
       (.I0(cplx_DQOut[458]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [458]),
        .O(\cplx_DQOut_reg[511]_0 [458]));
  (* SOFT_HLUTNM = "soft_lutpair653" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[459]_i_1 
       (.I0(cplx_DQOut[459]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [459]),
        .O(\cplx_DQOut_reg[511]_0 [459]));
  (* SOFT_HLUTNM = "soft_lutpair860" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[45]_i_1 
       (.I0(cplx_DQOut[45]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [45]),
        .O(\cplx_DQOut_reg[511]_0 [45]));
  (* SOFT_HLUTNM = "soft_lutpair652" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[460]_i_1 
       (.I0(cplx_DQOut[460]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [460]),
        .O(\cplx_DQOut_reg[511]_0 [460]));
  (* SOFT_HLUTNM = "soft_lutpair652" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[461]_i_1 
       (.I0(cplx_DQOut[461]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [461]),
        .O(\cplx_DQOut_reg[511]_0 [461]));
  (* SOFT_HLUTNM = "soft_lutpair651" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[462]_i_1 
       (.I0(cplx_DQOut[462]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [462]),
        .O(\cplx_DQOut_reg[511]_0 [462]));
  (* SOFT_HLUTNM = "soft_lutpair651" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[463]_i_1 
       (.I0(cplx_DQOut[463]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [463]),
        .O(\cplx_DQOut_reg[511]_0 [463]));
  (* SOFT_HLUTNM = "soft_lutpair650" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[464]_i_1 
       (.I0(cplx_DQOut[464]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [464]),
        .O(\cplx_DQOut_reg[511]_0 [464]));
  (* SOFT_HLUTNM = "soft_lutpair650" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[465]_i_1 
       (.I0(cplx_DQOut[465]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [465]),
        .O(\cplx_DQOut_reg[511]_0 [465]));
  (* SOFT_HLUTNM = "soft_lutpair649" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[466]_i_1 
       (.I0(cplx_DQOut[466]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [466]),
        .O(\cplx_DQOut_reg[511]_0 [466]));
  (* SOFT_HLUTNM = "soft_lutpair649" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[467]_i_1 
       (.I0(cplx_DQOut[467]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [467]),
        .O(\cplx_DQOut_reg[511]_0 [467]));
  (* SOFT_HLUTNM = "soft_lutpair648" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[468]_i_1 
       (.I0(cplx_DQOut[468]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [468]),
        .O(\cplx_DQOut_reg[511]_0 [468]));
  (* SOFT_HLUTNM = "soft_lutpair648" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[469]_i_1 
       (.I0(cplx_DQOut[469]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [469]),
        .O(\cplx_DQOut_reg[511]_0 [469]));
  (* SOFT_HLUTNM = "soft_lutpair859" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[46]_i_1 
       (.I0(cplx_DQOut[46]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [46]),
        .O(\cplx_DQOut_reg[511]_0 [46]));
  (* SOFT_HLUTNM = "soft_lutpair647" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[470]_i_1 
       (.I0(cplx_DQOut[470]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [470]),
        .O(\cplx_DQOut_reg[511]_0 [470]));
  (* SOFT_HLUTNM = "soft_lutpair647" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[471]_i_1 
       (.I0(cplx_DQOut[471]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [471]),
        .O(\cplx_DQOut_reg[511]_0 [471]));
  (* SOFT_HLUTNM = "soft_lutpair646" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[472]_i_1 
       (.I0(cplx_DQOut[472]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [472]),
        .O(\cplx_DQOut_reg[511]_0 [472]));
  (* SOFT_HLUTNM = "soft_lutpair646" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[473]_i_1 
       (.I0(cplx_DQOut[473]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [473]),
        .O(\cplx_DQOut_reg[511]_0 [473]));
  (* SOFT_HLUTNM = "soft_lutpair645" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[474]_i_1 
       (.I0(cplx_DQOut[474]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [474]),
        .O(\cplx_DQOut_reg[511]_0 [474]));
  (* SOFT_HLUTNM = "soft_lutpair645" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[475]_i_1 
       (.I0(cplx_DQOut[475]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [475]),
        .O(\cplx_DQOut_reg[511]_0 [475]));
  (* SOFT_HLUTNM = "soft_lutpair644" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[476]_i_1 
       (.I0(cplx_DQOut[476]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [476]),
        .O(\cplx_DQOut_reg[511]_0 [476]));
  (* SOFT_HLUTNM = "soft_lutpair644" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[477]_i_1 
       (.I0(cplx_DQOut[477]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [477]),
        .O(\cplx_DQOut_reg[511]_0 [477]));
  (* SOFT_HLUTNM = "soft_lutpair643" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[478]_i_1 
       (.I0(cplx_DQOut[478]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [478]),
        .O(\cplx_DQOut_reg[511]_0 [478]));
  (* SOFT_HLUTNM = "soft_lutpair643" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[479]_i_1 
       (.I0(cplx_DQOut[479]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [479]),
        .O(\cplx_DQOut_reg[511]_0 [479]));
  (* SOFT_HLUTNM = "soft_lutpair859" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[47]_i_1 
       (.I0(cplx_DQOut[47]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [47]),
        .O(\cplx_DQOut_reg[511]_0 [47]));
  (* SOFT_HLUTNM = "soft_lutpair642" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[480]_i_1 
       (.I0(cplx_DQOut[480]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [480]),
        .O(\cplx_DQOut_reg[511]_0 [480]));
  (* SOFT_HLUTNM = "soft_lutpair642" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[481]_i_1 
       (.I0(cplx_DQOut[481]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [481]),
        .O(\cplx_DQOut_reg[511]_0 [481]));
  (* SOFT_HLUTNM = "soft_lutpair641" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[482]_i_1 
       (.I0(cplx_DQOut[482]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [482]),
        .O(\cplx_DQOut_reg[511]_0 [482]));
  (* SOFT_HLUTNM = "soft_lutpair641" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[483]_i_1 
       (.I0(cplx_DQOut[483]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [483]),
        .O(\cplx_DQOut_reg[511]_0 [483]));
  (* SOFT_HLUTNM = "soft_lutpair640" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[484]_i_1 
       (.I0(cplx_DQOut[484]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [484]),
        .O(\cplx_DQOut_reg[511]_0 [484]));
  (* SOFT_HLUTNM = "soft_lutpair640" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[485]_i_1 
       (.I0(cplx_DQOut[485]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [485]),
        .O(\cplx_DQOut_reg[511]_0 [485]));
  (* SOFT_HLUTNM = "soft_lutpair639" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[486]_i_1 
       (.I0(cplx_DQOut[486]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [486]),
        .O(\cplx_DQOut_reg[511]_0 [486]));
  (* SOFT_HLUTNM = "soft_lutpair639" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[487]_i_1 
       (.I0(cplx_DQOut[487]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [487]),
        .O(\cplx_DQOut_reg[511]_0 [487]));
  (* SOFT_HLUTNM = "soft_lutpair638" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[488]_i_1 
       (.I0(cplx_DQOut[488]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [488]),
        .O(\cplx_DQOut_reg[511]_0 [488]));
  (* SOFT_HLUTNM = "soft_lutpair638" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[489]_i_1 
       (.I0(cplx_DQOut[489]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [489]),
        .O(\cplx_DQOut_reg[511]_0 [489]));
  (* SOFT_HLUTNM = "soft_lutpair858" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[48]_i_1 
       (.I0(cplx_DQOut[48]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [48]),
        .O(\cplx_DQOut_reg[511]_0 [48]));
  (* SOFT_HLUTNM = "soft_lutpair637" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[490]_i_1 
       (.I0(cplx_DQOut[490]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [490]),
        .O(\cplx_DQOut_reg[511]_0 [490]));
  (* SOFT_HLUTNM = "soft_lutpair637" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[491]_i_1 
       (.I0(cplx_DQOut[491]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [491]),
        .O(\cplx_DQOut_reg[511]_0 [491]));
  (* SOFT_HLUTNM = "soft_lutpair636" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[492]_i_1 
       (.I0(cplx_DQOut[492]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [492]),
        .O(\cplx_DQOut_reg[511]_0 [492]));
  (* SOFT_HLUTNM = "soft_lutpair636" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[493]_i_1 
       (.I0(cplx_DQOut[493]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [493]),
        .O(\cplx_DQOut_reg[511]_0 [493]));
  (* SOFT_HLUTNM = "soft_lutpair635" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[494]_i_1 
       (.I0(cplx_DQOut[494]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [494]),
        .O(\cplx_DQOut_reg[511]_0 [494]));
  (* SOFT_HLUTNM = "soft_lutpair635" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[495]_i_1 
       (.I0(cplx_DQOut[495]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [495]),
        .O(\cplx_DQOut_reg[511]_0 [495]));
  (* SOFT_HLUTNM = "soft_lutpair634" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[496]_i_1 
       (.I0(cplx_DQOut[496]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [496]),
        .O(\cplx_DQOut_reg[511]_0 [496]));
  (* SOFT_HLUTNM = "soft_lutpair634" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[497]_i_1 
       (.I0(cplx_DQOut[497]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [497]),
        .O(\cplx_DQOut_reg[511]_0 [497]));
  (* SOFT_HLUTNM = "soft_lutpair633" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[498]_i_1 
       (.I0(cplx_DQOut[498]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [498]),
        .O(\cplx_DQOut_reg[511]_0 [498]));
  (* SOFT_HLUTNM = "soft_lutpair633" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[499]_i_1 
       (.I0(cplx_DQOut[499]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [499]),
        .O(\cplx_DQOut_reg[511]_0 [499]));
  (* SOFT_HLUTNM = "soft_lutpair858" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[49]_i_1 
       (.I0(cplx_DQOut[49]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [49]),
        .O(\cplx_DQOut_reg[511]_0 [49]));
  (* SOFT_HLUTNM = "soft_lutpair880" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[4]_i_1 
       (.I0(cplx_DQOut[4]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [4]),
        .O(\cplx_DQOut_reg[511]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair632" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[500]_i_1 
       (.I0(cplx_DQOut[500]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [500]),
        .O(\cplx_DQOut_reg[511]_0 [500]));
  (* SOFT_HLUTNM = "soft_lutpair632" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[501]_i_1 
       (.I0(cplx_DQOut[501]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [501]),
        .O(\cplx_DQOut_reg[511]_0 [501]));
  (* SOFT_HLUTNM = "soft_lutpair631" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[502]_i_1 
       (.I0(cplx_DQOut[502]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [502]),
        .O(\cplx_DQOut_reg[511]_0 [502]));
  (* SOFT_HLUTNM = "soft_lutpair631" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[503]_i_1 
       (.I0(cplx_DQOut[503]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [503]),
        .O(\cplx_DQOut_reg[511]_0 [503]));
  (* SOFT_HLUTNM = "soft_lutpair630" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[504]_i_1 
       (.I0(cplx_DQOut[504]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [504]),
        .O(\cplx_DQOut_reg[511]_0 [504]));
  (* SOFT_HLUTNM = "soft_lutpair630" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[505]_i_1 
       (.I0(cplx_DQOut[505]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [505]),
        .O(\cplx_DQOut_reg[511]_0 [505]));
  (* SOFT_HLUTNM = "soft_lutpair629" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[506]_i_1 
       (.I0(cplx_DQOut[506]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [506]),
        .O(\cplx_DQOut_reg[511]_0 [506]));
  (* SOFT_HLUTNM = "soft_lutpair629" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[507]_i_1 
       (.I0(cplx_DQOut[507]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [507]),
        .O(\cplx_DQOut_reg[511]_0 [507]));
  (* SOFT_HLUTNM = "soft_lutpair628" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[508]_i_1 
       (.I0(cplx_DQOut[508]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [508]),
        .O(\cplx_DQOut_reg[511]_0 [508]));
  (* SOFT_HLUTNM = "soft_lutpair628" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[509]_i_1 
       (.I0(cplx_DQOut[509]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [509]),
        .O(\cplx_DQOut_reg[511]_0 [509]));
  (* SOFT_HLUTNM = "soft_lutpair857" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[50]_i_1 
       (.I0(cplx_DQOut[50]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [50]),
        .O(\cplx_DQOut_reg[511]_0 [50]));
  (* SOFT_HLUTNM = "soft_lutpair627" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[510]_i_1 
       (.I0(cplx_DQOut[510]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [510]),
        .O(\cplx_DQOut_reg[511]_0 [510]));
  (* SOFT_HLUTNM = "soft_lutpair627" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[511]_i_1 
       (.I0(cplx_DQOut[511]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [511]),
        .O(\cplx_DQOut_reg[511]_0 [511]));
  (* SOFT_HLUTNM = "soft_lutpair857" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[51]_i_1 
       (.I0(cplx_DQOut[51]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [51]),
        .O(\cplx_DQOut_reg[511]_0 [51]));
  (* SOFT_HLUTNM = "soft_lutpair856" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[52]_i_1 
       (.I0(cplx_DQOut[52]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [52]),
        .O(\cplx_DQOut_reg[511]_0 [52]));
  (* SOFT_HLUTNM = "soft_lutpair856" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[53]_i_1 
       (.I0(cplx_DQOut[53]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [53]),
        .O(\cplx_DQOut_reg[511]_0 [53]));
  (* SOFT_HLUTNM = "soft_lutpair855" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[54]_i_1 
       (.I0(cplx_DQOut[54]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [54]),
        .O(\cplx_DQOut_reg[511]_0 [54]));
  (* SOFT_HLUTNM = "soft_lutpair855" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[55]_i_1 
       (.I0(cplx_DQOut[55]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [55]),
        .O(\cplx_DQOut_reg[511]_0 [55]));
  (* SOFT_HLUTNM = "soft_lutpair854" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[56]_i_1 
       (.I0(cplx_DQOut[56]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [56]),
        .O(\cplx_DQOut_reg[511]_0 [56]));
  (* SOFT_HLUTNM = "soft_lutpair854" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[57]_i_1 
       (.I0(cplx_DQOut[57]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [57]),
        .O(\cplx_DQOut_reg[511]_0 [57]));
  (* SOFT_HLUTNM = "soft_lutpair853" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[58]_i_1 
       (.I0(cplx_DQOut[58]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [58]),
        .O(\cplx_DQOut_reg[511]_0 [58]));
  (* SOFT_HLUTNM = "soft_lutpair853" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[59]_i_1 
       (.I0(cplx_DQOut[59]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [59]),
        .O(\cplx_DQOut_reg[511]_0 [59]));
  (* SOFT_HLUTNM = "soft_lutpair880" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[5]_i_1 
       (.I0(cplx_DQOut[5]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [5]),
        .O(\cplx_DQOut_reg[511]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair852" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[60]_i_1 
       (.I0(cplx_DQOut[60]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [60]),
        .O(\cplx_DQOut_reg[511]_0 [60]));
  (* SOFT_HLUTNM = "soft_lutpair852" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[61]_i_1 
       (.I0(cplx_DQOut[61]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [61]),
        .O(\cplx_DQOut_reg[511]_0 [61]));
  (* SOFT_HLUTNM = "soft_lutpair851" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[62]_i_1 
       (.I0(cplx_DQOut[62]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [62]),
        .O(\cplx_DQOut_reg[511]_0 [62]));
  (* SOFT_HLUTNM = "soft_lutpair851" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[63]_i_1 
       (.I0(cplx_DQOut[63]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [63]),
        .O(\cplx_DQOut_reg[511]_0 [63]));
  (* SOFT_HLUTNM = "soft_lutpair850" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[64]_i_1 
       (.I0(cplx_DQOut[64]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [64]),
        .O(\cplx_DQOut_reg[511]_0 [64]));
  (* SOFT_HLUTNM = "soft_lutpair850" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[65]_i_1 
       (.I0(cplx_DQOut[65]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [65]),
        .O(\cplx_DQOut_reg[511]_0 [65]));
  (* SOFT_HLUTNM = "soft_lutpair849" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[66]_i_1 
       (.I0(cplx_DQOut[66]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [66]),
        .O(\cplx_DQOut_reg[511]_0 [66]));
  (* SOFT_HLUTNM = "soft_lutpair849" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[67]_i_1 
       (.I0(cplx_DQOut[67]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [67]),
        .O(\cplx_DQOut_reg[511]_0 [67]));
  (* SOFT_HLUTNM = "soft_lutpair848" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[68]_i_1 
       (.I0(cplx_DQOut[68]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [68]),
        .O(\cplx_DQOut_reg[511]_0 [68]));
  (* SOFT_HLUTNM = "soft_lutpair848" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[69]_i_1 
       (.I0(cplx_DQOut[69]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [69]),
        .O(\cplx_DQOut_reg[511]_0 [69]));
  (* SOFT_HLUTNM = "soft_lutpair879" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[6]_i_1 
       (.I0(cplx_DQOut[6]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [6]),
        .O(\cplx_DQOut_reg[511]_0 [6]));
  (* SOFT_HLUTNM = "soft_lutpair847" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[70]_i_1 
       (.I0(cplx_DQOut[70]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [70]),
        .O(\cplx_DQOut_reg[511]_0 [70]));
  (* SOFT_HLUTNM = "soft_lutpair847" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[71]_i_1 
       (.I0(cplx_DQOut[71]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [71]),
        .O(\cplx_DQOut_reg[511]_0 [71]));
  (* SOFT_HLUTNM = "soft_lutpair846" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[72]_i_1 
       (.I0(cplx_DQOut[72]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [72]),
        .O(\cplx_DQOut_reg[511]_0 [72]));
  (* SOFT_HLUTNM = "soft_lutpair846" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[73]_i_1 
       (.I0(cplx_DQOut[73]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [73]),
        .O(\cplx_DQOut_reg[511]_0 [73]));
  (* SOFT_HLUTNM = "soft_lutpair845" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[74]_i_1 
       (.I0(cplx_DQOut[74]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [74]),
        .O(\cplx_DQOut_reg[511]_0 [74]));
  (* SOFT_HLUTNM = "soft_lutpair845" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[75]_i_1 
       (.I0(cplx_DQOut[75]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [75]),
        .O(\cplx_DQOut_reg[511]_0 [75]));
  (* SOFT_HLUTNM = "soft_lutpair844" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[76]_i_1 
       (.I0(cplx_DQOut[76]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [76]),
        .O(\cplx_DQOut_reg[511]_0 [76]));
  (* SOFT_HLUTNM = "soft_lutpair844" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[77]_i_1 
       (.I0(cplx_DQOut[77]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [77]),
        .O(\cplx_DQOut_reg[511]_0 [77]));
  (* SOFT_HLUTNM = "soft_lutpair843" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[78]_i_1 
       (.I0(cplx_DQOut[78]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [78]),
        .O(\cplx_DQOut_reg[511]_0 [78]));
  (* SOFT_HLUTNM = "soft_lutpair843" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[79]_i_1 
       (.I0(cplx_DQOut[79]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [79]),
        .O(\cplx_DQOut_reg[511]_0 [79]));
  (* SOFT_HLUTNM = "soft_lutpair879" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[7]_i_1 
       (.I0(cplx_DQOut[7]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [7]),
        .O(\cplx_DQOut_reg[511]_0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair842" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[80]_i_1 
       (.I0(cplx_DQOut[80]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [80]),
        .O(\cplx_DQOut_reg[511]_0 [80]));
  (* SOFT_HLUTNM = "soft_lutpair842" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[81]_i_1 
       (.I0(cplx_DQOut[81]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [81]),
        .O(\cplx_DQOut_reg[511]_0 [81]));
  (* SOFT_HLUTNM = "soft_lutpair841" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[82]_i_1 
       (.I0(cplx_DQOut[82]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [82]),
        .O(\cplx_DQOut_reg[511]_0 [82]));
  (* SOFT_HLUTNM = "soft_lutpair841" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[83]_i_1 
       (.I0(cplx_DQOut[83]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [83]),
        .O(\cplx_DQOut_reg[511]_0 [83]));
  (* SOFT_HLUTNM = "soft_lutpair840" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[84]_i_1 
       (.I0(cplx_DQOut[84]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [84]),
        .O(\cplx_DQOut_reg[511]_0 [84]));
  (* SOFT_HLUTNM = "soft_lutpair840" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[85]_i_1 
       (.I0(cplx_DQOut[85]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [85]),
        .O(\cplx_DQOut_reg[511]_0 [85]));
  (* SOFT_HLUTNM = "soft_lutpair839" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[86]_i_1 
       (.I0(cplx_DQOut[86]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [86]),
        .O(\cplx_DQOut_reg[511]_0 [86]));
  (* SOFT_HLUTNM = "soft_lutpair839" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[87]_i_1 
       (.I0(cplx_DQOut[87]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [87]),
        .O(\cplx_DQOut_reg[511]_0 [87]));
  (* SOFT_HLUTNM = "soft_lutpair838" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[88]_i_1 
       (.I0(cplx_DQOut[88]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [88]),
        .O(\cplx_DQOut_reg[511]_0 [88]));
  (* SOFT_HLUTNM = "soft_lutpair838" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[89]_i_1 
       (.I0(cplx_DQOut[89]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [89]),
        .O(\cplx_DQOut_reg[511]_0 [89]));
  (* SOFT_HLUTNM = "soft_lutpair878" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[8]_i_1 
       (.I0(cplx_DQOut[8]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [8]),
        .O(\cplx_DQOut_reg[511]_0 [8]));
  (* SOFT_HLUTNM = "soft_lutpair837" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[90]_i_1 
       (.I0(cplx_DQOut[90]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [90]),
        .O(\cplx_DQOut_reg[511]_0 [90]));
  (* SOFT_HLUTNM = "soft_lutpair837" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[91]_i_1 
       (.I0(cplx_DQOut[91]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [91]),
        .O(\cplx_DQOut_reg[511]_0 [91]));
  (* SOFT_HLUTNM = "soft_lutpair836" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[92]_i_1 
       (.I0(cplx_DQOut[92]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [92]),
        .O(\cplx_DQOut_reg[511]_0 [92]));
  (* SOFT_HLUTNM = "soft_lutpair836" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[93]_i_1 
       (.I0(cplx_DQOut[93]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [93]),
        .O(\cplx_DQOut_reg[511]_0 [93]));
  (* SOFT_HLUTNM = "soft_lutpair835" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[94]_i_1 
       (.I0(cplx_DQOut[94]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [94]),
        .O(\cplx_DQOut_reg[511]_0 [94]));
  (* SOFT_HLUTNM = "soft_lutpair835" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[95]_i_1 
       (.I0(cplx_DQOut[95]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [95]),
        .O(\cplx_DQOut_reg[511]_0 [95]));
  (* SOFT_HLUTNM = "soft_lutpair834" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[96]_i_1 
       (.I0(cplx_DQOut[96]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [96]),
        .O(\cplx_DQOut_reg[511]_0 [96]));
  (* SOFT_HLUTNM = "soft_lutpair834" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[97]_i_1 
       (.I0(cplx_DQOut[97]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [97]),
        .O(\cplx_DQOut_reg[511]_0 [97]));
  (* SOFT_HLUTNM = "soft_lutpair833" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[98]_i_1 
       (.I0(cplx_DQOut[98]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [98]),
        .O(\cplx_DQOut_reg[511]_0 [98]));
  (* SOFT_HLUTNM = "soft_lutpair833" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[99]_i_1 
       (.I0(cplx_DQOut[99]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [99]),
        .O(\cplx_DQOut_reg[511]_0 [99]));
  (* SOFT_HLUTNM = "soft_lutpair878" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_DQOut[9]_i_1 
       (.I0(cplx_DQOut[9]),
        .I1(cplx_cal),
        .I2(\cal_DQOut_reg[511] [9]),
        .O(\cplx_DQOut_reg[511]_0 [9]));
  (* SOFT_HLUTNM = "soft_lutpair527" *) 
  LUT5 #(
    .INIT(32'hFFBD0030)) 
    cas_is_bursty_i_1
       (.I0(cplx_state[3]),
        .I1(cplx_state[2]),
        .I2(cplx_state[1]),
        .I3(cplx_state[0]),
        .I4(cas_is_bursty),
        .O(cas_is_bursty_nxt));
  FDRE cas_is_bursty_reg
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cas_is_bursty_nxt),
        .Q(cas_is_bursty),
        .R(out));
  LUT5 #(
    .INIT(32'hAAAEACA2)) 
    cas_is_read_i_1
       (.I0(cas_is_read),
        .I1(cplx_state[1]),
        .I2(cplx_state[0]),
        .I3(cplx_state[3]),
        .I4(cplx_state[2]),
        .O(cas_is_read_nxt));
  FDRE cas_is_read_reg
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cas_is_read_nxt),
        .Q(cas_is_read),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair526" *) 
  LUT5 #(
    .INIT(32'hFFEB0002)) 
    cas_uses_dm_i_1
       (.I0(cplx_state[2]),
        .I1(cplx_state[3]),
        .I2(cplx_state[1]),
        .I3(cplx_state[0]),
        .I4(cas_uses_dm),
        .O(cas_uses_dm_nxt));
  FDRE cas_uses_dm_reg
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cas_uses_dm_nxt),
        .Q(cas_uses_dm),
        .R(out));
  FDRE cplx_ACT_cmd_reg
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(seq_state_issue_act),
        .Q(cplx_ACT_cmd),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \cplx_ACT_n[6]_i_1 
       (.I0(cplx_ACT_cmd),
        .O(cplx_ACT_n_nxt0));
  FDRE \cplx_ACT_n_reg[6] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ACT_n_nxt0),
        .Q(cplx_ACT_n),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFF7)) 
    \cplx_ADR_cmd[2]_i_1 
       (.I0(seq_state[0]),
        .I1(seq_state[1]),
        .I2(seq_state[3]),
        .I3(seq_state[2]),
        .O(\cplx_ADR_cmd[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAA2A)) 
    \cplx_ADR_cmd[3]_i_1 
       (.I0(seq_col_reg[0]),
        .I1(seq_state[0]),
        .I2(seq_state[1]),
        .I3(seq_state[3]),
        .I4(seq_state[2]),
        .O(cplx_ADR_cmd_nxt[3]));
  LUT5 #(
    .INIT(32'hAAAAAA2A)) 
    \cplx_ADR_cmd[4]_i_1 
       (.I0(seq_col_reg[1]),
        .I1(seq_state[0]),
        .I2(seq_state[1]),
        .I3(seq_state[3]),
        .I4(seq_state[2]),
        .O(cplx_ADR_cmd_nxt[4]));
  LUT5 #(
    .INIT(32'hAAAAAA2A)) 
    \cplx_ADR_cmd[5]_i_1 
       (.I0(seq_col_reg[2]),
        .I1(seq_state[0]),
        .I2(seq_state[1]),
        .I3(seq_state[3]),
        .I4(seq_state[2]),
        .O(cplx_ADR_cmd_nxt[5]));
  LUT5 #(
    .INIT(32'hAAAAAA2A)) 
    \cplx_ADR_cmd[6]_i_1 
       (.I0(seq_col_reg[3]),
        .I1(seq_state[0]),
        .I2(seq_state[1]),
        .I3(seq_state[3]),
        .I4(seq_state[2]),
        .O(cplx_ADR_cmd_nxt[6]));
  LUT5 #(
    .INIT(32'hAAAAAA2A)) 
    \cplx_ADR_cmd[7]_i_1 
       (.I0(seq_col_reg[4]),
        .I1(seq_state[0]),
        .I2(seq_state[1]),
        .I3(seq_state[3]),
        .I4(seq_state[2]),
        .O(cplx_ADR_cmd_nxt[7]));
  LUT4 #(
    .INIT(16'h1000)) 
    \cplx_ADR_cmd[8]_i_1 
       (.I0(seq_state[2]),
        .I1(seq_state[3]),
        .I2(seq_state[1]),
        .I3(seq_state[0]),
        .O(seq_state_issue_act));
  LUT5 #(
    .INIT(32'hAAAAAA2A)) 
    \cplx_ADR_cmd[8]_i_2 
       (.I0(seq_col_reg[5]),
        .I1(seq_state[0]),
        .I2(seq_state[1]),
        .I3(seq_state[3]),
        .I4(seq_state[2]),
        .O(cplx_ADR_cmd_nxt[8]));
  FDRE \cplx_ADR_cmd_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(seq_row_reg[0]),
        .Q(cplx_ADR_cmd[0]),
        .R(\cplx_ADR_cmd[2]_i_1_n_0 ));
  FDRE \cplx_ADR_cmd_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(seq_row_reg[1]),
        .Q(cplx_ADR_cmd[1]),
        .R(\cplx_ADR_cmd[2]_i_1_n_0 ));
  FDRE \cplx_ADR_cmd_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(seq_row_reg[2]),
        .Q(cplx_ADR_cmd[2]),
        .R(\cplx_ADR_cmd[2]_i_1_n_0 ));
  FDRE \cplx_ADR_cmd_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd_nxt[3]),
        .Q(cplx_ADR_cmd[3]),
        .R(seq_state_issue_act));
  FDRE \cplx_ADR_cmd_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd_nxt[4]),
        .Q(cplx_ADR_cmd[4]),
        .R(seq_state_issue_act));
  FDRE \cplx_ADR_cmd_reg[5] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd_nxt[5]),
        .Q(cplx_ADR_cmd[5]),
        .R(seq_state_issue_act));
  FDRE \cplx_ADR_cmd_reg[6] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd_nxt[6]),
        .Q(cplx_ADR_cmd[6]),
        .R(seq_state_issue_act));
  FDRE \cplx_ADR_cmd_reg[7] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd_nxt[7]),
        .Q(cplx_ADR_cmd[7]),
        .R(seq_state_issue_act));
  FDRE \cplx_ADR_cmd_reg[8] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd_nxt[8]),
        .Q(cplx_ADR_cmd[8]),
        .R(seq_state_issue_act));
  FDRE \cplx_ADR_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd[0]),
        .Q(cplx_ADR[0]),
        .R(1'b0));
  FDRE \cplx_ADR_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd[1]),
        .Q(cplx_ADR[1]),
        .R(1'b0));
  FDRE \cplx_ADR_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd[2]),
        .Q(cplx_ADR[2]),
        .R(1'b0));
  FDRE \cplx_ADR_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd[3]),
        .Q(cplx_ADR[3]),
        .R(1'b0));
  FDRE \cplx_ADR_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd[4]),
        .Q(cplx_ADR[4]),
        .R(1'b0));
  FDRE \cplx_ADR_reg[5] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd[5]),
        .Q(cplx_ADR[5]),
        .R(1'b0));
  FDRE \cplx_ADR_reg[6] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd[6]),
        .Q(cplx_ADR[6]),
        .R(1'b0));
  FDRE \cplx_ADR_reg[7] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd[7]),
        .Q(cplx_ADR[7]),
        .R(1'b0));
  FDRE \cplx_ADR_reg[8] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_ADR_cmd[8]),
        .Q(cplx_ADR[8]),
        .R(1'b0));
  FDRE \cplx_BA_cmd_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(seq_bg[0]),
        .Q(cplx_BA_cmd[0]),
        .R(1'b0));
  FDRE \cplx_BA_cmd_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(seq_bg[1]),
        .Q(cplx_BA_cmd[1]),
        .R(1'b0));
  FDRE \cplx_BA_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_BA_cmd[0]),
        .Q(cplx_BA[0]),
        .R(1'b0));
  FDRE \cplx_BA_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_BA_cmd[1]),
        .Q(cplx_BA[1]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hF7)) 
    cplx_CAS_cmd_inv_i_1
       (.I0(seq_state[1]),
        .I1(seq_state[0]),
        .I2(seq_state[3]),
        .O(p_5_in));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    cplx_CAS_cmd_reg_inv
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_5_in),
        .Q(cplx_CAS_nxt0),
        .R(1'b0));
  FDRE \cplx_CAS_reg[6] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_CAS_nxt0),
        .Q(cplx_CAS),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFE)) 
    \cplx_CS_n[6]_i_1 
       (.I0(cplx_CS_n_cmd),
        .I1(\cplx_CS_n_reg[6]_0 ),
        .I2(\cplx_CS_n_reg[6]_1 ),
        .O(cplx_CS_n_nxt0));
  (* SOFT_HLUTNM = "soft_lutpair521" *) 
  LUT4 #(
    .INIT(16'hEF5F)) 
    cplx_CS_n_cmd_i_1
       (.I0(seq_state[0]),
        .I1(seq_state[2]),
        .I2(seq_state[1]),
        .I3(seq_state[3]),
        .O(cplx_CS_n_cmd_nxt));
  FDRE cplx_CS_n_cmd_reg
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_CS_n_cmd_nxt),
        .Q(cplx_CS_n_cmd),
        .R(1'b0));
  FDRE \cplx_CS_n_reg[6] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_CS_n_nxt0),
        .Q(\cplx_CS_n_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \cplx_DMOut_n_reg[56] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_DMOut_n0[56]),
        .Q(cplx_DMOut_n[56]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DMOut_n_reg[57] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_DMOut_n0[57]),
        .Q(cplx_DMOut_n[57]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DMOut_n_reg[58] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_DMOut_n0[58]),
        .Q(cplx_DMOut_n[58]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DMOut_n_reg[59] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_DMOut_n0[59]),
        .Q(cplx_DMOut_n[59]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DMOut_n_reg[60] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_DMOut_n0[60]),
        .Q(cplx_DMOut_n[60]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DMOut_n_reg[61] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_DMOut_n0[61]),
        .Q(cplx_DMOut_n[61]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DMOut_n_reg[62] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_DMOut_n0[62]),
        .Q(cplx_DMOut_n[62]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DMOut_n_reg[63] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_DMOut_n0[63]),
        .Q(cplx_DMOut_n[63]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cplx_DQOut[511]_i_1 
       (.I0(cplx_cal),
        .O(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_513),
        .Q(cplx_DQOut[0]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[100] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_413),
        .Q(cplx_DQOut[100]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[101] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_412),
        .Q(cplx_DQOut[101]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[102] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_411),
        .Q(cplx_DQOut[102]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[103] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_410),
        .Q(cplx_DQOut[103]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[104] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_409),
        .Q(cplx_DQOut[104]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[105] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_408),
        .Q(cplx_DQOut[105]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[106] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_407),
        .Q(cplx_DQOut[106]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[107] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_406),
        .Q(cplx_DQOut[107]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[108] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_405),
        .Q(cplx_DQOut[108]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[109] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_404),
        .Q(cplx_DQOut[109]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[10] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_503),
        .Q(cplx_DQOut[10]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[110] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_403),
        .Q(cplx_DQOut[110]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[111] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_402),
        .Q(cplx_DQOut[111]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[112] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_401),
        .Q(cplx_DQOut[112]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[113] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_400),
        .Q(cplx_DQOut[113]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[114] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_399),
        .Q(cplx_DQOut[114]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[115] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_398),
        .Q(cplx_DQOut[115]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[116] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_397),
        .Q(cplx_DQOut[116]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[117] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_396),
        .Q(cplx_DQOut[117]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[118] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_395),
        .Q(cplx_DQOut[118]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[119] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_394),
        .Q(cplx_DQOut[119]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[11] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_502),
        .Q(cplx_DQOut[11]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[120] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_393),
        .Q(cplx_DQOut[120]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[121] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_392),
        .Q(cplx_DQOut[121]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[122] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_391),
        .Q(cplx_DQOut[122]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[123] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_390),
        .Q(cplx_DQOut[123]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[124] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_389),
        .Q(cplx_DQOut[124]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[125] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_388),
        .Q(cplx_DQOut[125]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[126] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_387),
        .Q(cplx_DQOut[126]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[127] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_386),
        .Q(cplx_DQOut[127]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[128] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_385),
        .Q(cplx_DQOut[128]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[129] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_384),
        .Q(cplx_DQOut[129]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[12] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_501),
        .Q(cplx_DQOut[12]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[130] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_383),
        .Q(cplx_DQOut[130]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[131] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_382),
        .Q(cplx_DQOut[131]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[132] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_381),
        .Q(cplx_DQOut[132]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[133] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_380),
        .Q(cplx_DQOut[133]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[134] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_379),
        .Q(cplx_DQOut[134]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[135] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_378),
        .Q(cplx_DQOut[135]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[136] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_377),
        .Q(cplx_DQOut[136]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[137] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_376),
        .Q(cplx_DQOut[137]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[138] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_375),
        .Q(cplx_DQOut[138]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[139] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_374),
        .Q(cplx_DQOut[139]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[13] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_500),
        .Q(cplx_DQOut[13]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[140] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_373),
        .Q(cplx_DQOut[140]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[141] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_372),
        .Q(cplx_DQOut[141]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[142] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_371),
        .Q(cplx_DQOut[142]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[143] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_370),
        .Q(cplx_DQOut[143]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[144] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_369),
        .Q(cplx_DQOut[144]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[145] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_368),
        .Q(cplx_DQOut[145]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[146] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_367),
        .Q(cplx_DQOut[146]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[147] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_366),
        .Q(cplx_DQOut[147]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[148] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_365),
        .Q(cplx_DQOut[148]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[149] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_364),
        .Q(cplx_DQOut[149]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[14] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_499),
        .Q(cplx_DQOut[14]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[150] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_363),
        .Q(cplx_DQOut[150]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[151] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_362),
        .Q(cplx_DQOut[151]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[152] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_361),
        .Q(cplx_DQOut[152]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[153] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_360),
        .Q(cplx_DQOut[153]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[154] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_359),
        .Q(cplx_DQOut[154]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[155] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_358),
        .Q(cplx_DQOut[155]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[156] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_357),
        .Q(cplx_DQOut[156]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[157] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_356),
        .Q(cplx_DQOut[157]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[158] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_355),
        .Q(cplx_DQOut[158]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[159] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_354),
        .Q(cplx_DQOut[159]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[15] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_498),
        .Q(cplx_DQOut[15]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[160] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_353),
        .Q(cplx_DQOut[160]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[161] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_352),
        .Q(cplx_DQOut[161]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[162] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_351),
        .Q(cplx_DQOut[162]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[163] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_350),
        .Q(cplx_DQOut[163]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[164] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_349),
        .Q(cplx_DQOut[164]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[165] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_348),
        .Q(cplx_DQOut[165]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[166] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_347),
        .Q(cplx_DQOut[166]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[167] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_346),
        .Q(cplx_DQOut[167]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[168] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_345),
        .Q(cplx_DQOut[168]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[169] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_344),
        .Q(cplx_DQOut[169]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[16] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_497),
        .Q(cplx_DQOut[16]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[170] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_343),
        .Q(cplx_DQOut[170]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[171] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_342),
        .Q(cplx_DQOut[171]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[172] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_341),
        .Q(cplx_DQOut[172]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[173] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_340),
        .Q(cplx_DQOut[173]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[174] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_339),
        .Q(cplx_DQOut[174]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[175] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_338),
        .Q(cplx_DQOut[175]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[176] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_337),
        .Q(cplx_DQOut[176]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[177] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_336),
        .Q(cplx_DQOut[177]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[178] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_335),
        .Q(cplx_DQOut[178]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[179] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_334),
        .Q(cplx_DQOut[179]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[17] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_496),
        .Q(cplx_DQOut[17]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[180] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_333),
        .Q(cplx_DQOut[180]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[181] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_332),
        .Q(cplx_DQOut[181]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[182] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_331),
        .Q(cplx_DQOut[182]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[183] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_330),
        .Q(cplx_DQOut[183]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[184] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_329),
        .Q(cplx_DQOut[184]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[185] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_328),
        .Q(cplx_DQOut[185]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[186] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_327),
        .Q(cplx_DQOut[186]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[187] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_326),
        .Q(cplx_DQOut[187]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[188] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_325),
        .Q(cplx_DQOut[188]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[189] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_324),
        .Q(cplx_DQOut[189]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[18] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_495),
        .Q(cplx_DQOut[18]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[190] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_323),
        .Q(cplx_DQOut[190]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[191] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_322),
        .Q(cplx_DQOut[191]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[192] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_321),
        .Q(cplx_DQOut[192]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[193] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_320),
        .Q(cplx_DQOut[193]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[194] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_319),
        .Q(cplx_DQOut[194]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[195] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_318),
        .Q(cplx_DQOut[195]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[196] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_317),
        .Q(cplx_DQOut[196]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[197] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_316),
        .Q(cplx_DQOut[197]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[198] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_315),
        .Q(cplx_DQOut[198]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[199] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_314),
        .Q(cplx_DQOut[199]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[19] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_494),
        .Q(cplx_DQOut[19]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_512),
        .Q(cplx_DQOut[1]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[200] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_313),
        .Q(cplx_DQOut[200]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[201] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_312),
        .Q(cplx_DQOut[201]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[202] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_311),
        .Q(cplx_DQOut[202]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[203] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_310),
        .Q(cplx_DQOut[203]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[204] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_309),
        .Q(cplx_DQOut[204]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[205] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_308),
        .Q(cplx_DQOut[205]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[206] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_307),
        .Q(cplx_DQOut[206]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[207] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_306),
        .Q(cplx_DQOut[207]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[208] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_305),
        .Q(cplx_DQOut[208]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[209] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_304),
        .Q(cplx_DQOut[209]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[20] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_493),
        .Q(cplx_DQOut[20]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[210] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_303),
        .Q(cplx_DQOut[210]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[211] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_302),
        .Q(cplx_DQOut[211]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[212] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_301),
        .Q(cplx_DQOut[212]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[213] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_300),
        .Q(cplx_DQOut[213]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[214] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_299),
        .Q(cplx_DQOut[214]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[215] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_298),
        .Q(cplx_DQOut[215]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[216] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_297),
        .Q(cplx_DQOut[216]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[217] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_296),
        .Q(cplx_DQOut[217]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[218] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_295),
        .Q(cplx_DQOut[218]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[219] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_294),
        .Q(cplx_DQOut[219]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[21] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_492),
        .Q(cplx_DQOut[21]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[220] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_293),
        .Q(cplx_DQOut[220]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[221] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_292),
        .Q(cplx_DQOut[221]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[222] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_291),
        .Q(cplx_DQOut[222]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[223] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_290),
        .Q(cplx_DQOut[223]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[224] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_289),
        .Q(cplx_DQOut[224]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[225] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_288),
        .Q(cplx_DQOut[225]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[226] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_287),
        .Q(cplx_DQOut[226]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[227] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_286),
        .Q(cplx_DQOut[227]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[228] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_285),
        .Q(cplx_DQOut[228]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[229] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_284),
        .Q(cplx_DQOut[229]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[22] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_491),
        .Q(cplx_DQOut[22]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[230] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_283),
        .Q(cplx_DQOut[230]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[231] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_282),
        .Q(cplx_DQOut[231]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[232] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_281),
        .Q(cplx_DQOut[232]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[233] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_280),
        .Q(cplx_DQOut[233]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[234] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_279),
        .Q(cplx_DQOut[234]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[235] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_278),
        .Q(cplx_DQOut[235]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[236] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_277),
        .Q(cplx_DQOut[236]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[237] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_276),
        .Q(cplx_DQOut[237]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[238] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_275),
        .Q(cplx_DQOut[238]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[239] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_274),
        .Q(cplx_DQOut[239]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[23] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_490),
        .Q(cplx_DQOut[23]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[240] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_273),
        .Q(cplx_DQOut[240]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[241] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_272),
        .Q(cplx_DQOut[241]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[242] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_271),
        .Q(cplx_DQOut[242]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[243] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_270),
        .Q(cplx_DQOut[243]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[244] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_269),
        .Q(cplx_DQOut[244]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[245] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_268),
        .Q(cplx_DQOut[245]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[246] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_267),
        .Q(cplx_DQOut[246]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[247] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_266),
        .Q(cplx_DQOut[247]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[248] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_265),
        .Q(cplx_DQOut[248]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[249] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_264),
        .Q(cplx_DQOut[249]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[24] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_489),
        .Q(cplx_DQOut[24]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[250] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_263),
        .Q(cplx_DQOut[250]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[251] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_262),
        .Q(cplx_DQOut[251]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[252] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_261),
        .Q(cplx_DQOut[252]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[253] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_260),
        .Q(cplx_DQOut[253]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[254] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_259),
        .Q(cplx_DQOut[254]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[255] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_258),
        .Q(cplx_DQOut[255]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[256] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_257),
        .Q(cplx_DQOut[256]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[257] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_256),
        .Q(cplx_DQOut[257]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[258] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_255),
        .Q(cplx_DQOut[258]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[259] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_254),
        .Q(cplx_DQOut[259]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[25] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_488),
        .Q(cplx_DQOut[25]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[260] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_253),
        .Q(cplx_DQOut[260]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[261] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_252),
        .Q(cplx_DQOut[261]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[262] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_251),
        .Q(cplx_DQOut[262]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[263] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_250),
        .Q(cplx_DQOut[263]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[264] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_249),
        .Q(cplx_DQOut[264]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[265] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_248),
        .Q(cplx_DQOut[265]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[266] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_247),
        .Q(cplx_DQOut[266]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[267] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_246),
        .Q(cplx_DQOut[267]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[268] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_245),
        .Q(cplx_DQOut[268]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[269] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_244),
        .Q(cplx_DQOut[269]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[26] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_487),
        .Q(cplx_DQOut[26]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[270] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_243),
        .Q(cplx_DQOut[270]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[271] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_242),
        .Q(cplx_DQOut[271]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[272] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_241),
        .Q(cplx_DQOut[272]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[273] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_240),
        .Q(cplx_DQOut[273]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[274] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_239),
        .Q(cplx_DQOut[274]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[275] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_238),
        .Q(cplx_DQOut[275]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[276] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_237),
        .Q(cplx_DQOut[276]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[277] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_236),
        .Q(cplx_DQOut[277]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[278] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_235),
        .Q(cplx_DQOut[278]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[279] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_234),
        .Q(cplx_DQOut[279]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[27] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_486),
        .Q(cplx_DQOut[27]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[280] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_233),
        .Q(cplx_DQOut[280]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[281] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_232),
        .Q(cplx_DQOut[281]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[282] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_231),
        .Q(cplx_DQOut[282]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[283] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_230),
        .Q(cplx_DQOut[283]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[284] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_229),
        .Q(cplx_DQOut[284]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[285] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_228),
        .Q(cplx_DQOut[285]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[286] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_227),
        .Q(cplx_DQOut[286]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[287] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_226),
        .Q(cplx_DQOut[287]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[288] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_225),
        .Q(cplx_DQOut[288]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[289] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_224),
        .Q(cplx_DQOut[289]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[28] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_485),
        .Q(cplx_DQOut[28]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[290] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_223),
        .Q(cplx_DQOut[290]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[291] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_222),
        .Q(cplx_DQOut[291]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[292] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_221),
        .Q(cplx_DQOut[292]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[293] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_220),
        .Q(cplx_DQOut[293]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[294] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_219),
        .Q(cplx_DQOut[294]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[295] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_218),
        .Q(cplx_DQOut[295]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[296] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_217),
        .Q(cplx_DQOut[296]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[297] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_216),
        .Q(cplx_DQOut[297]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[298] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_215),
        .Q(cplx_DQOut[298]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[299] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_214),
        .Q(cplx_DQOut[299]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[29] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_484),
        .Q(cplx_DQOut[29]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_511),
        .Q(cplx_DQOut[2]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[300] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_213),
        .Q(cplx_DQOut[300]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[301] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_212),
        .Q(cplx_DQOut[301]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[302] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_211),
        .Q(cplx_DQOut[302]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[303] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_210),
        .Q(cplx_DQOut[303]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[304] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_209),
        .Q(cplx_DQOut[304]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[305] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_208),
        .Q(cplx_DQOut[305]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[306] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_207),
        .Q(cplx_DQOut[306]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[307] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_206),
        .Q(cplx_DQOut[307]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[308] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_205),
        .Q(cplx_DQOut[308]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[309] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_204),
        .Q(cplx_DQOut[309]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[30] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_483),
        .Q(cplx_DQOut[30]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[310] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_203),
        .Q(cplx_DQOut[310]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[311] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_202),
        .Q(cplx_DQOut[311]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[312] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_201),
        .Q(cplx_DQOut[312]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[313] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_200),
        .Q(cplx_DQOut[313]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[314] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_199),
        .Q(cplx_DQOut[314]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[315] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_198),
        .Q(cplx_DQOut[315]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[316] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_197),
        .Q(cplx_DQOut[316]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[317] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_196),
        .Q(cplx_DQOut[317]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[318] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_195),
        .Q(cplx_DQOut[318]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[319] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_194),
        .Q(cplx_DQOut[319]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[31] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_482),
        .Q(cplx_DQOut[31]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[320] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_193),
        .Q(cplx_DQOut[320]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[321] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_192),
        .Q(cplx_DQOut[321]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[322] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_191),
        .Q(cplx_DQOut[322]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[323] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_190),
        .Q(cplx_DQOut[323]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[324] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_189),
        .Q(cplx_DQOut[324]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[325] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_188),
        .Q(cplx_DQOut[325]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[326] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_187),
        .Q(cplx_DQOut[326]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[327] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_186),
        .Q(cplx_DQOut[327]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[328] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_185),
        .Q(cplx_DQOut[328]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[329] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_184),
        .Q(cplx_DQOut[329]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[32] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_481),
        .Q(cplx_DQOut[32]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[330] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_183),
        .Q(cplx_DQOut[330]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[331] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_182),
        .Q(cplx_DQOut[331]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[332] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_181),
        .Q(cplx_DQOut[332]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[333] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_180),
        .Q(cplx_DQOut[333]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[334] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_179),
        .Q(cplx_DQOut[334]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[335] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_178),
        .Q(cplx_DQOut[335]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[336] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_177),
        .Q(cplx_DQOut[336]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[337] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_176),
        .Q(cplx_DQOut[337]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[338] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_175),
        .Q(cplx_DQOut[338]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[339] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_174),
        .Q(cplx_DQOut[339]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[33] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_480),
        .Q(cplx_DQOut[33]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[340] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_173),
        .Q(cplx_DQOut[340]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[341] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_172),
        .Q(cplx_DQOut[341]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[342] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_171),
        .Q(cplx_DQOut[342]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[343] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_170),
        .Q(cplx_DQOut[343]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[344] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_169),
        .Q(cplx_DQOut[344]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[345] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_168),
        .Q(cplx_DQOut[345]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[346] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_167),
        .Q(cplx_DQOut[346]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[347] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_166),
        .Q(cplx_DQOut[347]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[348] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_165),
        .Q(cplx_DQOut[348]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[349] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_164),
        .Q(cplx_DQOut[349]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[34] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_479),
        .Q(cplx_DQOut[34]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[350] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_163),
        .Q(cplx_DQOut[350]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[351] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_162),
        .Q(cplx_DQOut[351]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[352] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_161),
        .Q(cplx_DQOut[352]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[353] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_160),
        .Q(cplx_DQOut[353]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[354] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_159),
        .Q(cplx_DQOut[354]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[355] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_158),
        .Q(cplx_DQOut[355]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[356] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_157),
        .Q(cplx_DQOut[356]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[357] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_156),
        .Q(cplx_DQOut[357]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[358] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_155),
        .Q(cplx_DQOut[358]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[359] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_154),
        .Q(cplx_DQOut[359]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[35] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_478),
        .Q(cplx_DQOut[35]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[360] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_153),
        .Q(cplx_DQOut[360]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[361] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_152),
        .Q(cplx_DQOut[361]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[362] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_151),
        .Q(cplx_DQOut[362]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[363] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_150),
        .Q(cplx_DQOut[363]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[364] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_149),
        .Q(cplx_DQOut[364]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[365] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_148),
        .Q(cplx_DQOut[365]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[366] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_147),
        .Q(cplx_DQOut[366]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[367] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_146),
        .Q(cplx_DQOut[367]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[368] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_145),
        .Q(cplx_DQOut[368]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[369] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_144),
        .Q(cplx_DQOut[369]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[36] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_477),
        .Q(cplx_DQOut[36]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[370] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_143),
        .Q(cplx_DQOut[370]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[371] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_142),
        .Q(cplx_DQOut[371]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[372] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_141),
        .Q(cplx_DQOut[372]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[373] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_140),
        .Q(cplx_DQOut[373]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[374] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_139),
        .Q(cplx_DQOut[374]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[375] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_138),
        .Q(cplx_DQOut[375]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[376] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_137),
        .Q(cplx_DQOut[376]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[377] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_136),
        .Q(cplx_DQOut[377]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[378] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_135),
        .Q(cplx_DQOut[378]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[379] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_134),
        .Q(cplx_DQOut[379]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[37] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_476),
        .Q(cplx_DQOut[37]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[380] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_133),
        .Q(cplx_DQOut[380]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[381] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_132),
        .Q(cplx_DQOut[381]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[382] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_131),
        .Q(cplx_DQOut[382]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[383] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_130),
        .Q(cplx_DQOut[383]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[384] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_129),
        .Q(cplx_DQOut[384]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[385] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_128),
        .Q(cplx_DQOut[385]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[386] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_127),
        .Q(cplx_DQOut[386]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[387] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_126),
        .Q(cplx_DQOut[387]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[388] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_125),
        .Q(cplx_DQOut[388]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[389] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_124),
        .Q(cplx_DQOut[389]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[38] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_475),
        .Q(cplx_DQOut[38]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[390] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_123),
        .Q(cplx_DQOut[390]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[391] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_122),
        .Q(cplx_DQOut[391]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[392] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_121),
        .Q(cplx_DQOut[392]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[393] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_120),
        .Q(cplx_DQOut[393]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[394] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_119),
        .Q(cplx_DQOut[394]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[395] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_118),
        .Q(cplx_DQOut[395]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[396] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_117),
        .Q(cplx_DQOut[396]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[397] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_116),
        .Q(cplx_DQOut[397]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[398] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_115),
        .Q(cplx_DQOut[398]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[399] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_114),
        .Q(cplx_DQOut[399]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[39] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_474),
        .Q(cplx_DQOut[39]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_510),
        .Q(cplx_DQOut[3]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[400] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_113),
        .Q(cplx_DQOut[400]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[401] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_112),
        .Q(cplx_DQOut[401]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[402] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_111),
        .Q(cplx_DQOut[402]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[403] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_110),
        .Q(cplx_DQOut[403]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[404] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_109),
        .Q(cplx_DQOut[404]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[405] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_108),
        .Q(cplx_DQOut[405]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[406] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_107),
        .Q(cplx_DQOut[406]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[407] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_106),
        .Q(cplx_DQOut[407]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[408] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_105),
        .Q(cplx_DQOut[408]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[409] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_104),
        .Q(cplx_DQOut[409]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[40] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_473),
        .Q(cplx_DQOut[40]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[410] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_103),
        .Q(cplx_DQOut[410]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[411] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_102),
        .Q(cplx_DQOut[411]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[412] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_101),
        .Q(cplx_DQOut[412]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[413] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_100),
        .Q(cplx_DQOut[413]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[414] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_99),
        .Q(cplx_DQOut[414]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[415] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_98),
        .Q(cplx_DQOut[415]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[416] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_97),
        .Q(cplx_DQOut[416]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[417] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_96),
        .Q(cplx_DQOut[417]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[418] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_95),
        .Q(cplx_DQOut[418]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[419] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_94),
        .Q(cplx_DQOut[419]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[41] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_472),
        .Q(cplx_DQOut[41]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[420] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_93),
        .Q(cplx_DQOut[420]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[421] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_92),
        .Q(cplx_DQOut[421]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[422] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_91),
        .Q(cplx_DQOut[422]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[423] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_90),
        .Q(cplx_DQOut[423]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[424] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_89),
        .Q(cplx_DQOut[424]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[425] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_88),
        .Q(cplx_DQOut[425]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[426] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_87),
        .Q(cplx_DQOut[426]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[427] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_86),
        .Q(cplx_DQOut[427]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[428] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_85),
        .Q(cplx_DQOut[428]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[429] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_84),
        .Q(cplx_DQOut[429]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[42] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_471),
        .Q(cplx_DQOut[42]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[430] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_83),
        .Q(cplx_DQOut[430]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[431] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_82),
        .Q(cplx_DQOut[431]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[432] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_81),
        .Q(cplx_DQOut[432]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[433] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_80),
        .Q(cplx_DQOut[433]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[434] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_79),
        .Q(cplx_DQOut[434]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[435] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_78),
        .Q(cplx_DQOut[435]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[436] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_77),
        .Q(cplx_DQOut[436]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[437] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_76),
        .Q(cplx_DQOut[437]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[438] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_75),
        .Q(cplx_DQOut[438]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[439] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_74),
        .Q(cplx_DQOut[439]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[43] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_470),
        .Q(cplx_DQOut[43]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[440] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_73),
        .Q(cplx_DQOut[440]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[441] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_72),
        .Q(cplx_DQOut[441]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[442] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_71),
        .Q(cplx_DQOut[442]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[443] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_70),
        .Q(cplx_DQOut[443]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[444] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_69),
        .Q(cplx_DQOut[444]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[445] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_68),
        .Q(cplx_DQOut[445]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[446] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_67),
        .Q(cplx_DQOut[446]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[447] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_66),
        .Q(cplx_DQOut[447]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[448] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_65),
        .Q(cplx_DQOut[448]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[449] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_64),
        .Q(cplx_DQOut[449]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[44] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_469),
        .Q(cplx_DQOut[44]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[450] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_63),
        .Q(cplx_DQOut[450]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[451] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_62),
        .Q(cplx_DQOut[451]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[452] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_61),
        .Q(cplx_DQOut[452]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[453] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_60),
        .Q(cplx_DQOut[453]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[454] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_59),
        .Q(cplx_DQOut[454]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[455] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_58),
        .Q(cplx_DQOut[455]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[456] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_57),
        .Q(cplx_DQOut[456]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[457] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_56),
        .Q(cplx_DQOut[457]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[458] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_55),
        .Q(cplx_DQOut[458]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[459] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_54),
        .Q(cplx_DQOut[459]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[45] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_468),
        .Q(cplx_DQOut[45]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[460] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_53),
        .Q(cplx_DQOut[460]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[461] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_52),
        .Q(cplx_DQOut[461]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[462] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_51),
        .Q(cplx_DQOut[462]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[463] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_50),
        .Q(cplx_DQOut[463]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[464] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_49),
        .Q(cplx_DQOut[464]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[465] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_48),
        .Q(cplx_DQOut[465]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[466] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_47),
        .Q(cplx_DQOut[466]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[467] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_46),
        .Q(cplx_DQOut[467]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[468] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_45),
        .Q(cplx_DQOut[468]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[469] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_44),
        .Q(cplx_DQOut[469]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[46] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_467),
        .Q(cplx_DQOut[46]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[470] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_43),
        .Q(cplx_DQOut[470]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[471] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_42),
        .Q(cplx_DQOut[471]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[472] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_41),
        .Q(cplx_DQOut[472]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[473] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_40),
        .Q(cplx_DQOut[473]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[474] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_39),
        .Q(cplx_DQOut[474]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[475] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_38),
        .Q(cplx_DQOut[475]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[476] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_37),
        .Q(cplx_DQOut[476]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[477] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_36),
        .Q(cplx_DQOut[477]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[478] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_35),
        .Q(cplx_DQOut[478]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[479] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_34),
        .Q(cplx_DQOut[479]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[47] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_466),
        .Q(cplx_DQOut[47]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[480] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_33),
        .Q(cplx_DQOut[480]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[481] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_32),
        .Q(cplx_DQOut[481]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[482] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_31),
        .Q(cplx_DQOut[482]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[483] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_30),
        .Q(cplx_DQOut[483]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[484] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_29),
        .Q(cplx_DQOut[484]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[485] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_28),
        .Q(cplx_DQOut[485]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[486] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_27),
        .Q(cplx_DQOut[486]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[487] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_26),
        .Q(cplx_DQOut[487]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[488] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_25),
        .Q(cplx_DQOut[488]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[489] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_24),
        .Q(cplx_DQOut[489]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[48] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_465),
        .Q(cplx_DQOut[48]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[490] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_23),
        .Q(cplx_DQOut[490]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[491] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_22),
        .Q(cplx_DQOut[491]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[492] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_21),
        .Q(cplx_DQOut[492]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[493] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_20),
        .Q(cplx_DQOut[493]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[494] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_19),
        .Q(cplx_DQOut[494]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[495] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_18),
        .Q(cplx_DQOut[495]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[496] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_17),
        .Q(cplx_DQOut[496]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[497] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_16),
        .Q(cplx_DQOut[497]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[498] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_15),
        .Q(cplx_DQOut[498]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[499] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_14),
        .Q(cplx_DQOut[499]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[49] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_464),
        .Q(cplx_DQOut[49]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_509),
        .Q(cplx_DQOut[4]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[500] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_13),
        .Q(cplx_DQOut[500]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[501] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_12),
        .Q(cplx_DQOut[501]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[502] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_11),
        .Q(cplx_DQOut[502]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[503] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_10),
        .Q(cplx_DQOut[503]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[504] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_9),
        .Q(cplx_DQOut[504]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[505] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_8),
        .Q(cplx_DQOut[505]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[506] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_7),
        .Q(cplx_DQOut[506]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[507] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_6),
        .Q(cplx_DQOut[507]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[508] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_5),
        .Q(cplx_DQOut[508]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[509] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_4),
        .Q(cplx_DQOut[509]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[50] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_463),
        .Q(cplx_DQOut[50]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[510] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_3),
        .Q(cplx_DQOut[510]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[511] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_2),
        .Q(cplx_DQOut[511]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[51] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_462),
        .Q(cplx_DQOut[51]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[52] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_461),
        .Q(cplx_DQOut[52]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[53] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_460),
        .Q(cplx_DQOut[53]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[54] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_459),
        .Q(cplx_DQOut[54]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[55] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_458),
        .Q(cplx_DQOut[55]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[56] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_457),
        .Q(cplx_DQOut[56]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[57] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_456),
        .Q(cplx_DQOut[57]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[58] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_455),
        .Q(cplx_DQOut[58]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[59] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_454),
        .Q(cplx_DQOut[59]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[5] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_508),
        .Q(cplx_DQOut[5]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[60] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_453),
        .Q(cplx_DQOut[60]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[61] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_452),
        .Q(cplx_DQOut[61]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[62] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_451),
        .Q(cplx_DQOut[62]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[63] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_450),
        .Q(cplx_DQOut[63]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[64] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_449),
        .Q(cplx_DQOut[64]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[65] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_448),
        .Q(cplx_DQOut[65]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[66] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_447),
        .Q(cplx_DQOut[66]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[67] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_446),
        .Q(cplx_DQOut[67]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[68] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_445),
        .Q(cplx_DQOut[68]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[69] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_444),
        .Q(cplx_DQOut[69]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[6] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_507),
        .Q(cplx_DQOut[6]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[70] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_443),
        .Q(cplx_DQOut[70]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[71] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_442),
        .Q(cplx_DQOut[71]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[72] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_441),
        .Q(cplx_DQOut[72]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[73] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_440),
        .Q(cplx_DQOut[73]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[74] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_439),
        .Q(cplx_DQOut[74]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[75] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_438),
        .Q(cplx_DQOut[75]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[76] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_437),
        .Q(cplx_DQOut[76]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[77] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_436),
        .Q(cplx_DQOut[77]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[78] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_435),
        .Q(cplx_DQOut[78]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[79] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_434),
        .Q(cplx_DQOut[79]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[7] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_506),
        .Q(cplx_DQOut[7]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[80] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_433),
        .Q(cplx_DQOut[80]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[81] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_432),
        .Q(cplx_DQOut[81]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[82] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_431),
        .Q(cplx_DQOut[82]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[83] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_430),
        .Q(cplx_DQOut[83]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[84] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_429),
        .Q(cplx_DQOut[84]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[85] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_428),
        .Q(cplx_DQOut[85]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[86] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_427),
        .Q(cplx_DQOut[86]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[87] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_426),
        .Q(cplx_DQOut[87]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[88] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_425),
        .Q(cplx_DQOut[88]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[89] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_424),
        .Q(cplx_DQOut[89]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[8] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_505),
        .Q(cplx_DQOut[8]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[90] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_423),
        .Q(cplx_DQOut[90]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[91] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_422),
        .Q(cplx_DQOut[91]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[92] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_421),
        .Q(cplx_DQOut[92]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[93] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_420),
        .Q(cplx_DQOut[93]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[94] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_419),
        .Q(cplx_DQOut[94]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[95] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_418),
        .Q(cplx_DQOut[95]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[96] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_417),
        .Q(cplx_DQOut[96]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[97] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_416),
        .Q(cplx_DQOut[97]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[98] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_415),
        .Q(cplx_DQOut[98]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[99] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_414),
        .Q(cplx_DQOut[99]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  FDRE \cplx_DQOut_reg[9] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(u_ddr_cal_cplx_data_n_504),
        .Q(cplx_DQOut[9]),
        .R(\cplx_DQOut[511]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair529" *) 
  LUT4 #(
    .INIT(16'hEFDF)) 
    cplx_RAS_cmd_inv_i_1
       (.I0(seq_state[0]),
        .I1(seq_state[2]),
        .I2(seq_state[1]),
        .I3(seq_state[3]),
        .O(cplx_RAS_cmd_nxt));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    cplx_RAS_cmd_reg_inv
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_RAS_cmd_nxt),
        .Q(cplx_RAS_nxt0),
        .R(1'b0));
  FDRE \cplx_RAS_reg[6] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_RAS_nxt0),
        .Q(cplx_RAS),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair529" *) 
  LUT5 #(
    .INIT(32'hFFF3BF3F)) 
    cplx_WE_cmd_inv_i_1
       (.I0(cas_is_read),
        .I1(seq_state[1]),
        .I2(seq_state[0]),
        .I3(seq_state[2]),
        .I4(seq_state[3]),
        .O(cplx_WE_cmd_nxt));
  (* inverted = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    cplx_WE_cmd_reg_inv
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_WE_cmd_nxt),
        .Q(cplx_WE_nxt0),
        .R(1'b0));
  FDRE \cplx_WE_reg[6] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_WE_nxt0),
        .Q(cplx_WE),
        .R(1'b0));
  FDRE cplx_cal_reg
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_status),
        .Q(cplx_cal),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h10)) 
    cplx_config_byte_select_nxt_inferred_i_1
       (.I0(\cplx_config_byte_select_reg[0]_0 ),
        .I1(\cplx_config_byte_select_reg[0]_1 ),
        .I2(\cplx_config_byte_select_reg[2]_0 ),
        .O(cplx_config_byte_select_nxt[2]));
  LUT3 #(
    .INIT(8'h10)) 
    cplx_config_byte_select_nxt_inferred_i_2
       (.I0(\cplx_config_byte_select_reg[0]_0 ),
        .I1(\cplx_config_byte_select_reg[0]_1 ),
        .I2(\cplx_config_byte_select_reg[1]_0 ),
        .O(cplx_config_byte_select_nxt[1]));
  LUT3 #(
    .INIT(8'h10)) 
    cplx_config_byte_select_nxt_inferred_i_3
       (.I0(\cplx_config_byte_select_reg[0]_0 ),
        .I1(\cplx_config_byte_select_reg[0]_1 ),
        .I2(\cplx_config_byte_select_reg[0]_2 ),
        .O(cplx_config_byte_select_nxt[0]));
  FDRE \cplx_config_byte_select_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_config_byte_select_nxt[0]),
        .Q(cplx_config_byte_select[0]),
        .R(1'b0));
  FDRE \cplx_config_byte_select_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_config_byte_select_nxt[1]),
        .Q(cplx_config_byte_select[1]),
        .R(1'b0));
  FDRE \cplx_config_byte_select_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_config_byte_select_nxt[2]),
        .Q(cplx_config_byte_select[2]),
        .R(1'b0));
  FDRE \cplx_config_byte_select_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_config_byte_select_nxt[3]),
        .Q(cplx_config_byte_select[3]),
        .R(1'b0));
  FDRE \cplx_config_byte_select_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_config_byte_select_nxt[4]),
        .Q(cplx_config_byte_select[4]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[0]),
        .Q(cplx_data_byte_103[0]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[10] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[10]),
        .Q(cplx_data_byte_103[10]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[11] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[11]),
        .Q(cplx_data_byte_103[11]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[12] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[12]),
        .Q(cplx_data_byte_103[12]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[13] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[13]),
        .Q(cplx_data_byte_103[13]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[14] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[14]),
        .Q(cplx_data_byte_103[14]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[15] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[15]),
        .Q(cplx_data_byte_103[15]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[16] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[16]),
        .Q(cplx_data_byte_103[16]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[17] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[17]),
        .Q(cplx_data_byte_103[17]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[18] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[18]),
        .Q(cplx_data_byte_103[18]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[19] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[19]),
        .Q(cplx_data_byte_103[19]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[1]),
        .Q(cplx_data_byte_103[1]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[20] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[20]),
        .Q(cplx_data_byte_103[20]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[21] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[21]),
        .Q(cplx_data_byte_103[21]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[22] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[22]),
        .Q(cplx_data_byte_103[22]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[23] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[23]),
        .Q(cplx_data_byte_103[23]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[24] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[24]),
        .Q(cplx_data_byte_103[24]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[25] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[25]),
        .Q(cplx_data_byte_103[25]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[26] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[26]),
        .Q(cplx_data_byte_103[26]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[27] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[27]),
        .Q(cplx_data_byte_103[27]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[28] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[28]),
        .Q(cplx_data_byte_103[28]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[29] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[29]),
        .Q(cplx_data_byte_103[29]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[2]),
        .Q(cplx_data_byte_103[2]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[30] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[30]),
        .Q(cplx_data_byte_103[30]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[31] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[31]),
        .Q(cplx_data_byte_103[31]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[32] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[32]),
        .Q(cplx_data_byte_103[32]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[33] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[33]),
        .Q(cplx_data_byte_103[33]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[34] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[34]),
        .Q(cplx_data_byte_103[34]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[35] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[35]),
        .Q(cplx_data_byte_103[35]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[36] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[36]),
        .Q(cplx_data_byte_103[36]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[37] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[37]),
        .Q(cplx_data_byte_103[37]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[38] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[38]),
        .Q(cplx_data_byte_103[38]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[39] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[39]),
        .Q(cplx_data_byte_103[39]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[3]),
        .Q(cplx_data_byte_103[3]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[40] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[40]),
        .Q(cplx_data_byte_103[40]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[41] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[41]),
        .Q(cplx_data_byte_103[41]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[42] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[42]),
        .Q(cplx_data_byte_103[42]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[43] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[43]),
        .Q(cplx_data_byte_103[43]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[44] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[44]),
        .Q(cplx_data_byte_103[44]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[45] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[45]),
        .Q(cplx_data_byte_103[45]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[46] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[46]),
        .Q(cplx_data_byte_103[46]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[47] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[47]),
        .Q(cplx_data_byte_103[47]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[48] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[48]),
        .Q(cplx_data_byte_103[48]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[49] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[49]),
        .Q(cplx_data_byte_103[49]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[4]),
        .Q(cplx_data_byte_103[4]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[50] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[50]),
        .Q(cplx_data_byte_103[50]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[51] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[51]),
        .Q(cplx_data_byte_103[51]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[52] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[52]),
        .Q(cplx_data_byte_103[52]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[53] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[53]),
        .Q(cplx_data_byte_103[53]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[54] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[54]),
        .Q(cplx_data_byte_103[54]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[55] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[55]),
        .Q(cplx_data_byte_103[55]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[56] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[56]),
        .Q(cplx_data_byte_103[56]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[57] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[57]),
        .Q(cplx_data_byte_103[57]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[58] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[58]),
        .Q(cplx_data_byte_103[58]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[59] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[59]),
        .Q(cplx_data_byte_103[59]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[5] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[5]),
        .Q(cplx_data_byte_103[5]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[60] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[60]),
        .Q(cplx_data_byte_103[60]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[61] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[61]),
        .Q(cplx_data_byte_103[61]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[62] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[62]),
        .Q(cplx_data_byte_103[62]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[63] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[63]),
        .Q(cplx_data_byte_103[63]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[6] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[6]),
        .Q(cplx_data_byte_103[6]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[7] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[7]),
        .Q(cplx_data_byte_103[7]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[8] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[8]),
        .Q(cplx_data_byte_103[8]),
        .R(1'b0));
  FDRE \cplx_data_byte_103_reg[9] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_data_byte_102[9]),
        .Q(cplx_data_byte_103[9]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00E2)) 
    \cplx_dqin_byte_103[0]_i_1 
       (.I0(\cplx_dqin_byte_103[0]_i_2_n_0 ),
        .I1(cplx_config_byte_select[2]),
        .I2(\cplx_dqin_byte_103[0]_i_3_n_0 ),
        .I3(cplx_config_byte_select[4]),
        .O(\cplx_dqin_byte_103[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[0]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [192]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [128]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [64]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [0]),
        .O(\cplx_dqin_byte_103[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[0]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [448]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [384]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [320]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [256]),
        .O(\cplx_dqin_byte_103[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[10]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [202]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [138]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [74]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [10]),
        .O(\cplx_dqin_byte_103[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[10]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [458]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [394]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [330]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [266]),
        .O(\cplx_dqin_byte_103[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[11]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [203]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [139]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [75]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [11]),
        .O(\cplx_dqin_byte_103[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[11]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [459]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [395]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [331]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [267]),
        .O(\cplx_dqin_byte_103[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[12]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [204]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [140]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [76]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [12]),
        .O(\cplx_dqin_byte_103[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[12]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [460]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [396]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [332]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [268]),
        .O(\cplx_dqin_byte_103[12]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[13]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [205]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [141]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [77]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [13]),
        .O(\cplx_dqin_byte_103[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[13]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [461]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [397]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [333]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [269]),
        .O(\cplx_dqin_byte_103[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[14]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [206]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [142]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [78]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [14]),
        .O(\cplx_dqin_byte_103[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[14]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [462]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [398]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [334]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [270]),
        .O(\cplx_dqin_byte_103[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[15]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [207]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [143]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [79]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [15]),
        .O(\cplx_dqin_byte_103[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[15]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [463]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [399]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [335]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [271]),
        .O(\cplx_dqin_byte_103[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[16]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [208]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [144]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [80]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [16]),
        .O(\cplx_dqin_byte_103[16]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[16]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [464]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [400]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [336]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [272]),
        .O(\cplx_dqin_byte_103[16]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[17]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [209]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [145]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [81]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [17]),
        .O(\cplx_dqin_byte_103[17]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[17]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [465]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [401]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [337]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [273]),
        .O(\cplx_dqin_byte_103[17]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[18]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [210]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [146]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [82]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [18]),
        .O(\cplx_dqin_byte_103[18]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[18]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [466]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [402]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [338]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [274]),
        .O(\cplx_dqin_byte_103[18]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[19]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [211]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [147]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [83]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [19]),
        .O(\cplx_dqin_byte_103[19]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[19]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [467]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [403]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [339]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [275]),
        .O(\cplx_dqin_byte_103[19]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h70)) 
    \cplx_dqin_byte_103[1]_i_1 
       (.I0(cplx_config_byte_select[3]),
        .I1(cplx_config_byte_select[4]),
        .I2(\cplx_dqin_byte_103_reg[1]_i_2_n_0 ),
        .O(\cplx_dqin_byte_103[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[1]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [193]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [129]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [65]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [1]),
        .O(\cplx_dqin_byte_103[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[1]_i_4 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [449]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [385]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [321]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [257]),
        .O(\cplx_dqin_byte_103[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[20]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [212]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [148]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [84]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [20]),
        .O(\cplx_dqin_byte_103[20]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[20]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [468]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [404]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [340]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [276]),
        .O(\cplx_dqin_byte_103[20]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[21]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [213]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [149]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [85]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [21]),
        .O(\cplx_dqin_byte_103[21]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[21]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [469]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [405]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [341]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [277]),
        .O(\cplx_dqin_byte_103[21]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[22]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [214]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [150]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [86]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [22]),
        .O(\cplx_dqin_byte_103[22]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[22]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [470]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [406]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [342]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [278]),
        .O(\cplx_dqin_byte_103[22]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[23]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [215]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [151]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [87]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [23]),
        .O(\cplx_dqin_byte_103[23]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[23]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [471]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [407]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [343]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [279]),
        .O(\cplx_dqin_byte_103[23]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[24]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [216]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [152]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [88]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [24]),
        .O(\cplx_dqin_byte_103[24]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[24]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [472]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [408]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [344]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [280]),
        .O(\cplx_dqin_byte_103[24]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[25]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [217]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [153]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [89]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [25]),
        .O(\cplx_dqin_byte_103[25]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[25]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [473]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [409]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [345]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [281]),
        .O(\cplx_dqin_byte_103[25]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[26]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [218]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [154]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [90]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [26]),
        .O(\cplx_dqin_byte_103[26]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[26]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [474]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [410]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [346]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [282]),
        .O(\cplx_dqin_byte_103[26]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[27]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [219]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [155]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [91]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [27]),
        .O(\cplx_dqin_byte_103[27]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[27]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [475]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [411]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [347]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [283]),
        .O(\cplx_dqin_byte_103[27]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[28]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [220]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [156]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [92]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [28]),
        .O(\cplx_dqin_byte_103[28]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[28]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [476]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [412]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [348]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [284]),
        .O(\cplx_dqin_byte_103[28]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[29]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [221]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [157]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [93]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [29]),
        .O(\cplx_dqin_byte_103[29]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[29]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [477]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [413]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [349]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [285]),
        .O(\cplx_dqin_byte_103[29]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[2]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [194]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [130]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [66]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [2]),
        .O(\cplx_dqin_byte_103[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[2]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [450]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [386]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [322]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [258]),
        .O(\cplx_dqin_byte_103[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[30]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [222]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [158]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [94]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [30]),
        .O(\cplx_dqin_byte_103[30]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[30]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [478]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [414]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [350]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [286]),
        .O(\cplx_dqin_byte_103[30]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[31]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [223]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [159]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [95]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [31]),
        .O(\cplx_dqin_byte_103[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[31]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [479]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [415]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [351]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [287]),
        .O(\cplx_dqin_byte_103[31]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[32]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [224]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [160]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [96]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [32]),
        .O(\cplx_dqin_byte_103[32]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[32]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [480]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [416]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [352]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [288]),
        .O(\cplx_dqin_byte_103[32]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[33]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [225]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [161]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [97]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [33]),
        .O(\cplx_dqin_byte_103[33]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[33]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [481]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [417]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [353]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [289]),
        .O(\cplx_dqin_byte_103[33]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[34]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [226]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [162]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [98]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [34]),
        .O(\cplx_dqin_byte_103[34]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[34]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [482]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [418]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [354]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [290]),
        .O(\cplx_dqin_byte_103[34]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[35]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [227]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [163]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [99]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [35]),
        .O(\cplx_dqin_byte_103[35]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[35]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [483]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [419]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [355]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [291]),
        .O(\cplx_dqin_byte_103[35]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[36]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [228]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [164]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [100]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [36]),
        .O(\cplx_dqin_byte_103[36]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[36]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [484]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [420]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [356]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [292]),
        .O(\cplx_dqin_byte_103[36]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[37]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [229]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [165]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [101]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [37]),
        .O(\cplx_dqin_byte_103[37]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[37]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [485]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [421]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [357]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [293]),
        .O(\cplx_dqin_byte_103[37]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[38]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [230]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [166]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [102]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [38]),
        .O(\cplx_dqin_byte_103[38]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[38]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [486]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [422]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [358]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [294]),
        .O(\cplx_dqin_byte_103[38]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[39]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [231]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [167]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [103]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [39]),
        .O(\cplx_dqin_byte_103[39]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[39]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [487]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [423]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [359]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [295]),
        .O(\cplx_dqin_byte_103[39]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[3]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [195]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [131]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [67]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [3]),
        .O(\cplx_dqin_byte_103[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[3]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [451]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [387]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [323]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [259]),
        .O(\cplx_dqin_byte_103[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[40]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [232]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [168]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [104]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [40]),
        .O(\cplx_dqin_byte_103[40]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[40]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [488]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [424]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [360]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [296]),
        .O(\cplx_dqin_byte_103[40]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[41]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [233]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [169]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [105]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [41]),
        .O(\cplx_dqin_byte_103[41]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[41]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [489]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [425]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [361]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [297]),
        .O(\cplx_dqin_byte_103[41]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[42]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [234]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [170]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [106]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [42]),
        .O(\cplx_dqin_byte_103[42]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[42]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [490]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [426]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [362]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [298]),
        .O(\cplx_dqin_byte_103[42]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[43]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [235]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [171]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [107]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [43]),
        .O(\cplx_dqin_byte_103[43]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[43]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [491]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [427]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [363]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [299]),
        .O(\cplx_dqin_byte_103[43]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[44]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [236]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [172]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [108]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [44]),
        .O(\cplx_dqin_byte_103[44]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[44]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [492]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [428]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [364]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [300]),
        .O(\cplx_dqin_byte_103[44]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[45]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [237]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [173]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [109]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [45]),
        .O(\cplx_dqin_byte_103[45]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[45]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [493]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [429]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [365]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [301]),
        .O(\cplx_dqin_byte_103[45]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[46]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [238]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [174]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [110]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [46]),
        .O(\cplx_dqin_byte_103[46]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[46]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [494]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [430]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [366]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [302]),
        .O(\cplx_dqin_byte_103[46]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[47]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [239]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [175]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [111]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [47]),
        .O(\cplx_dqin_byte_103[47]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[47]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [495]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [431]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [367]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [303]),
        .O(\cplx_dqin_byte_103[47]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[48]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [240]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [176]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [112]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [48]),
        .O(\cplx_dqin_byte_103[48]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[48]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [496]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [432]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [368]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [304]),
        .O(\cplx_dqin_byte_103[48]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[49]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [241]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [177]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [113]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [49]),
        .O(\cplx_dqin_byte_103[49]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[49]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [497]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [433]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [369]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [305]),
        .O(\cplx_dqin_byte_103[49]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[4]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [196]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [132]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [68]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [4]),
        .O(\cplx_dqin_byte_103[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[4]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [452]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [388]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [324]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [260]),
        .O(\cplx_dqin_byte_103[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[50]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [242]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [178]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [114]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [50]),
        .O(\cplx_dqin_byte_103[50]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[50]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [498]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [434]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [370]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [306]),
        .O(\cplx_dqin_byte_103[50]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[51]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [243]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [179]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [115]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [51]),
        .O(\cplx_dqin_byte_103[51]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[51]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [499]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [435]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [371]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [307]),
        .O(\cplx_dqin_byte_103[51]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[52]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [244]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [180]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [116]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [52]),
        .O(\cplx_dqin_byte_103[52]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[52]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [500]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [436]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [372]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [308]),
        .O(\cplx_dqin_byte_103[52]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[53]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [245]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [181]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [117]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [53]),
        .O(\cplx_dqin_byte_103[53]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[53]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [501]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [437]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [373]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [309]),
        .O(\cplx_dqin_byte_103[53]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[54]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [246]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [182]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [118]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [54]),
        .O(\cplx_dqin_byte_103[54]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[54]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [502]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [438]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [374]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [310]),
        .O(\cplx_dqin_byte_103[54]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[55]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [247]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [183]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [119]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [55]),
        .O(\cplx_dqin_byte_103[55]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[55]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [503]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [439]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [375]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [311]),
        .O(\cplx_dqin_byte_103[55]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[56]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [248]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [184]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [120]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [56]),
        .O(\cplx_dqin_byte_103[56]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[56]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [504]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [440]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [376]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [312]),
        .O(\cplx_dqin_byte_103[56]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[57]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [249]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [185]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [121]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [57]),
        .O(\cplx_dqin_byte_103[57]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[57]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [505]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [441]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [377]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [313]),
        .O(\cplx_dqin_byte_103[57]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[58]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [250]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [186]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [122]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [58]),
        .O(\cplx_dqin_byte_103[58]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[58]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [506]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [442]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [378]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [314]),
        .O(\cplx_dqin_byte_103[58]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[59]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [251]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [187]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [123]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [59]),
        .O(\cplx_dqin_byte_103[59]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[59]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [507]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [443]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [379]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [315]),
        .O(\cplx_dqin_byte_103[59]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[5]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [197]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [133]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [69]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [5]),
        .O(\cplx_dqin_byte_103[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[5]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [453]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [389]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [325]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [261]),
        .O(\cplx_dqin_byte_103[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[60]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [252]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [188]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [124]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [60]),
        .O(\cplx_dqin_byte_103[60]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[60]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [508]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [444]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [380]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [316]),
        .O(\cplx_dqin_byte_103[60]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[61]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [253]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [189]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [125]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [61]),
        .O(\cplx_dqin_byte_103[61]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[61]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [509]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [445]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [381]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [317]),
        .O(\cplx_dqin_byte_103[61]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[62]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [254]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [190]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [126]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [62]),
        .O(\cplx_dqin_byte_103[62]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[62]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [510]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [446]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [382]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [318]),
        .O(\cplx_dqin_byte_103[62]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[63]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [255]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [191]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [127]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [63]),
        .O(\cplx_dqin_byte_103[63]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[63]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [511]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [447]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [383]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [319]),
        .O(\cplx_dqin_byte_103[63]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[6]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [198]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [134]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [70]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [6]),
        .O(\cplx_dqin_byte_103[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[6]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [454]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [390]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [326]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [262]),
        .O(\cplx_dqin_byte_103[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[7]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [199]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [135]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [71]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [7]),
        .O(\cplx_dqin_byte_103[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[7]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [455]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [391]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [327]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [263]),
        .O(\cplx_dqin_byte_103[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[8]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [200]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [136]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [72]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [8]),
        .O(\cplx_dqin_byte_103[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[8]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [456]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [392]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [328]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [264]),
        .O(\cplx_dqin_byte_103[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[9]_i_2 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [201]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [137]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [73]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [9]),
        .O(\cplx_dqin_byte_103[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \cplx_dqin_byte_103[9]_i_3 
       (.I0(\cplx_dqin_byte_103_reg[63]_0 [457]),
        .I1(\cplx_dqin_byte_103_reg[63]_0 [393]),
        .I2(cplx_config_byte_select[1]),
        .I3(\cplx_dqin_byte_103_reg[63]_0 [329]),
        .I4(cplx_config_byte_select[0]),
        .I5(\cplx_dqin_byte_103_reg[63]_0 [265]),
        .O(\cplx_dqin_byte_103[9]_i_3_n_0 ));
  FDRE \cplx_dqin_byte_103_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103[0]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[0]),
        .R(1'b0));
  FDRE \cplx_dqin_byte_103_reg[10] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[10]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[10]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[10]_i_1 
       (.I0(\cplx_dqin_byte_103[10]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[10]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[10]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[11] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[11]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[11]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[11]_i_1 
       (.I0(\cplx_dqin_byte_103[11]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[11]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[11]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[12] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[12]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[12]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[12]_i_1 
       (.I0(\cplx_dqin_byte_103[12]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[12]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[12]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[13] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[13]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[13]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[13]_i_1 
       (.I0(\cplx_dqin_byte_103[13]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[13]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[13]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[14] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[14]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[14]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[14]_i_1 
       (.I0(\cplx_dqin_byte_103[14]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[14]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[14]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[15] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[15]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[15]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[15]_i_1 
       (.I0(\cplx_dqin_byte_103[15]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[15]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[15]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[16] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[16]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[16]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[16]_i_1 
       (.I0(\cplx_dqin_byte_103[16]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[16]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[16]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[17] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[17]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[17]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[17]_i_1 
       (.I0(\cplx_dqin_byte_103[17]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[17]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[17]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[18] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[18]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[18]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[18]_i_1 
       (.I0(\cplx_dqin_byte_103[18]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[18]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[18]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[19] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[19]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[19]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[19]_i_1 
       (.I0(\cplx_dqin_byte_103[19]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[19]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[19]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103[1]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[1]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[1]_i_2 
       (.I0(\cplx_dqin_byte_103[1]_i_3_n_0 ),
        .I1(\cplx_dqin_byte_103[1]_i_4_n_0 ),
        .O(\cplx_dqin_byte_103_reg[1]_i_2_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[20] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[20]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[20]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[20]_i_1 
       (.I0(\cplx_dqin_byte_103[20]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[20]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[20]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[21] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[21]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[21]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[21]_i_1 
       (.I0(\cplx_dqin_byte_103[21]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[21]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[21]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[22] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[22]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[22]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[22]_i_1 
       (.I0(\cplx_dqin_byte_103[22]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[22]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[22]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[23] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[23]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[23]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[23]_i_1 
       (.I0(\cplx_dqin_byte_103[23]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[23]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[23]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[24] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[24]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[24]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[24]_i_1 
       (.I0(\cplx_dqin_byte_103[24]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[24]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[24]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[25] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[25]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[25]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[25]_i_1 
       (.I0(\cplx_dqin_byte_103[25]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[25]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[25]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[26] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[26]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[26]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[26]_i_1 
       (.I0(\cplx_dqin_byte_103[26]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[26]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[26]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[27] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[27]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[27]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[27]_i_1 
       (.I0(\cplx_dqin_byte_103[27]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[27]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[27]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[28] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[28]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[28]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[28]_i_1 
       (.I0(\cplx_dqin_byte_103[28]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[28]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[28]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[29] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[29]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[29]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[29]_i_1 
       (.I0(\cplx_dqin_byte_103[29]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[29]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[29]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[2]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[2]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[2]_i_1 
       (.I0(\cplx_dqin_byte_103[2]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[2]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[2]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[30] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[30]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[30]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[30]_i_1 
       (.I0(\cplx_dqin_byte_103[30]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[30]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[30]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[31] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[31]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[31]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[31]_i_1 
       (.I0(\cplx_dqin_byte_103[31]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[31]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[31]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[32] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[32]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[32]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[32]_i_1 
       (.I0(\cplx_dqin_byte_103[32]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[32]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[32]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[33] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[33]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[33]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[33]_i_1 
       (.I0(\cplx_dqin_byte_103[33]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[33]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[33]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[34] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[34]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[34]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[34]_i_1 
       (.I0(\cplx_dqin_byte_103[34]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[34]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[34]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[35] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[35]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[35]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[35]_i_1 
       (.I0(\cplx_dqin_byte_103[35]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[35]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[35]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[36] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[36]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[36]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[36]_i_1 
       (.I0(\cplx_dqin_byte_103[36]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[36]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[36]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[37] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[37]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[37]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[37]_i_1 
       (.I0(\cplx_dqin_byte_103[37]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[37]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[37]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[38] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[38]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[38]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[38]_i_1 
       (.I0(\cplx_dqin_byte_103[38]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[38]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[38]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[39] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[39]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[39]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[39]_i_1 
       (.I0(\cplx_dqin_byte_103[39]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[39]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[39]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[3]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[3]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[3]_i_1 
       (.I0(\cplx_dqin_byte_103[3]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[3]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[3]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[40] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[40]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[40]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[40]_i_1 
       (.I0(\cplx_dqin_byte_103[40]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[40]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[40]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[41] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[41]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[41]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[41]_i_1 
       (.I0(\cplx_dqin_byte_103[41]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[41]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[41]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[42] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[42]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[42]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[42]_i_1 
       (.I0(\cplx_dqin_byte_103[42]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[42]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[42]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[43] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[43]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[43]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[43]_i_1 
       (.I0(\cplx_dqin_byte_103[43]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[43]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[43]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[44] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[44]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[44]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[44]_i_1 
       (.I0(\cplx_dqin_byte_103[44]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[44]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[44]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[45] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[45]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[45]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[45]_i_1 
       (.I0(\cplx_dqin_byte_103[45]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[45]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[45]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[46] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[46]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[46]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[46]_i_1 
       (.I0(\cplx_dqin_byte_103[46]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[46]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[46]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[47] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[47]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[47]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[47]_i_1 
       (.I0(\cplx_dqin_byte_103[47]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[47]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[47]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[48] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[48]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[48]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[48]_i_1 
       (.I0(\cplx_dqin_byte_103[48]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[48]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[48]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[49] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[49]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[49]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[49]_i_1 
       (.I0(\cplx_dqin_byte_103[49]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[49]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[49]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[4]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[4]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[4]_i_1 
       (.I0(\cplx_dqin_byte_103[4]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[4]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[4]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[50] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[50]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[50]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[50]_i_1 
       (.I0(\cplx_dqin_byte_103[50]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[50]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[50]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[51] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[51]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[51]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[51]_i_1 
       (.I0(\cplx_dqin_byte_103[51]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[51]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[51]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[52] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[52]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[52]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[52]_i_1 
       (.I0(\cplx_dqin_byte_103[52]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[52]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[52]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[53] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[53]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[53]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[53]_i_1 
       (.I0(\cplx_dqin_byte_103[53]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[53]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[53]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[54] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[54]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[54]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[54]_i_1 
       (.I0(\cplx_dqin_byte_103[54]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[54]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[54]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[55] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[55]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[55]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[55]_i_1 
       (.I0(\cplx_dqin_byte_103[55]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[55]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[55]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[56] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[56]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[56]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[56]_i_1 
       (.I0(\cplx_dqin_byte_103[56]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[56]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[56]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[57] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[57]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[57]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[57]_i_1 
       (.I0(\cplx_dqin_byte_103[57]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[57]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[57]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[58] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[58]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[58]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[58]_i_1 
       (.I0(\cplx_dqin_byte_103[58]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[58]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[58]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[59] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[59]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[59]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[59]_i_1 
       (.I0(\cplx_dqin_byte_103[59]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[59]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[59]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[5] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[5]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[5]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[5]_i_1 
       (.I0(\cplx_dqin_byte_103[5]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[5]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[5]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[60] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[60]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[60]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[60]_i_1 
       (.I0(\cplx_dqin_byte_103[60]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[60]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[60]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[61] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[61]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[61]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[61]_i_1 
       (.I0(\cplx_dqin_byte_103[61]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[61]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[61]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[62] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[62]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[62]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[62]_i_1 
       (.I0(\cplx_dqin_byte_103[62]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[62]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[62]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[63] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[63]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[63]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[63]_i_1 
       (.I0(\cplx_dqin_byte_103[63]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[63]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[63]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[6] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[6]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[6]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[6]_i_1 
       (.I0(\cplx_dqin_byte_103[6]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[6]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[6]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[7] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[7]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[7]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[7]_i_1 
       (.I0(\cplx_dqin_byte_103[7]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[7]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[7]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[8] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[8]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[8]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[8]_i_1 
       (.I0(\cplx_dqin_byte_103[8]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[8]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[8]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  FDRE \cplx_dqin_byte_103_reg[9] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_dqin_byte_103_reg[9]_i_1_n_0 ),
        .Q(cplx_dqin_byte_103[9]),
        .R(1'b0));
  MUXF7 \cplx_dqin_byte_103_reg[9]_i_1 
       (.I0(\cplx_dqin_byte_103[9]_i_2_n_0 ),
        .I1(\cplx_dqin_byte_103[9]_i_3_n_0 ),
        .O(\cplx_dqin_byte_103_reg[9]_i_1_n_0 ),
        .S(cplx_config_byte_select[2]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA8)) 
    cplx_dqin_valid_102_i_1
       (.I0(rdDataEn_pi),
        .I1(\outstanding_reads_reg_n_0_[2] ),
        .I2(\outstanding_reads_reg_n_0_[1] ),
        .I3(\outstanding_reads_reg_n_0_[3] ),
        .I4(\outstanding_reads_reg_n_0_[4] ),
        .I5(\outstanding_reads_reg_n_0_[0] ),
        .O(p_0_in0_out));
  FDRE cplx_dqin_valid_102_reg
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in0_out),
        .Q(cplx_dqin_valid_102),
        .R(1'b0));
  FDRE cplx_dqin_valid_103_reg
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_dqin_valid_102),
        .Q(cplx_dqin_valid_103),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[0]_i_1 
       (.I0(cplx_dqin_byte_103[0]),
        .I1(cplx_data_byte_103[0]),
        .I2(cplx_dqin_valid_103),
        .I3(cplx_err_log30[0]),
        .O(\cplx_error_accum[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[10]_i_1 
       (.I0(cplx_dqin_byte_103[10]),
        .I1(cplx_data_byte_103[10]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [9]),
        .O(\cplx_error_accum[10]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[11]_i_1 
       (.I0(cplx_dqin_byte_103[11]),
        .I1(cplx_data_byte_103[11]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [10]),
        .O(\cplx_error_accum[11]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[12]_i_1 
       (.I0(cplx_dqin_byte_103[12]),
        .I1(cplx_data_byte_103[12]),
        .I2(cplx_dqin_valid_103),
        .I3(cplx_err_log30[12]),
        .O(\cplx_error_accum[12]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[13]_i_1 
       (.I0(cplx_dqin_byte_103[13]),
        .I1(cplx_data_byte_103[13]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [11]),
        .O(\cplx_error_accum[13]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[14]_i_1 
       (.I0(cplx_dqin_byte_103[14]),
        .I1(cplx_data_byte_103[14]),
        .I2(cplx_dqin_valid_103),
        .I3(cplx_err_log30[14]),
        .O(\cplx_error_accum[14]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[15]_i_1 
       (.I0(cplx_dqin_byte_103[15]),
        .I1(cplx_data_byte_103[15]),
        .I2(cplx_dqin_valid_103),
        .I3(cplx_err_log30[15]),
        .O(\cplx_error_accum[15]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[16]_i_1 
       (.I0(cplx_dqin_byte_103[16]),
        .I1(cplx_data_byte_103[16]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [12]),
        .O(\cplx_error_accum[16]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[17]_i_1 
       (.I0(cplx_dqin_byte_103[17]),
        .I1(cplx_data_byte_103[17]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [13]),
        .O(\cplx_error_accum[17]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[18]_i_1 
       (.I0(cplx_dqin_byte_103[18]),
        .I1(cplx_data_byte_103[18]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [14]),
        .O(\cplx_error_accum[18]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[19]_i_1 
       (.I0(cplx_dqin_byte_103[19]),
        .I1(cplx_data_byte_103[19]),
        .I2(cplx_dqin_valid_103),
        .I3(cplx_err_log30[19]),
        .O(\cplx_error_accum[19]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[1]_i_1 
       (.I0(cplx_dqin_byte_103[1]),
        .I1(cplx_data_byte_103[1]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [0]),
        .O(\cplx_error_accum[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[20]_i_1 
       (.I0(cplx_dqin_byte_103[20]),
        .I1(cplx_data_byte_103[20]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [15]),
        .O(\cplx_error_accum[20]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[21]_i_1 
       (.I0(cplx_dqin_byte_103[21]),
        .I1(cplx_data_byte_103[21]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [16]),
        .O(\cplx_error_accum[21]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[22]_i_1 
       (.I0(cplx_dqin_byte_103[22]),
        .I1(cplx_data_byte_103[22]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [17]),
        .O(\cplx_error_accum[22]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[23]_i_1 
       (.I0(cplx_dqin_byte_103[23]),
        .I1(cplx_data_byte_103[23]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [18]),
        .O(\cplx_error_accum[23]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[24]_i_1 
       (.I0(cplx_dqin_byte_103[24]),
        .I1(cplx_data_byte_103[24]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [19]),
        .O(\cplx_error_accum[24]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[25]_i_1 
       (.I0(cplx_dqin_byte_103[25]),
        .I1(cplx_data_byte_103[25]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [20]),
        .O(\cplx_error_accum[25]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[26]_i_1 
       (.I0(cplx_dqin_byte_103[26]),
        .I1(cplx_data_byte_103[26]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [21]),
        .O(\cplx_error_accum[26]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[27]_i_1 
       (.I0(cplx_dqin_byte_103[27]),
        .I1(cplx_data_byte_103[27]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [22]),
        .O(\cplx_error_accum[27]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[28]_i_1 
       (.I0(cplx_dqin_byte_103[28]),
        .I1(cplx_data_byte_103[28]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [23]),
        .O(\cplx_error_accum[28]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[29]_i_1 
       (.I0(cplx_dqin_byte_103[29]),
        .I1(cplx_data_byte_103[29]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [24]),
        .O(\cplx_error_accum[29]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[2]_i_1 
       (.I0(cplx_dqin_byte_103[2]),
        .I1(cplx_data_byte_103[2]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [1]),
        .O(\cplx_error_accum[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[30]_i_1 
       (.I0(cplx_dqin_byte_103[30]),
        .I1(cplx_data_byte_103[30]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [25]),
        .O(\cplx_error_accum[30]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[31]_i_1 
       (.I0(cplx_dqin_byte_103[31]),
        .I1(cplx_data_byte_103[31]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [26]),
        .O(\cplx_error_accum[31]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[32]_i_1 
       (.I0(cplx_dqin_byte_103[32]),
        .I1(cplx_data_byte_103[32]),
        .I2(cplx_dqin_valid_103),
        .I3(cplx_err_log74[0]),
        .O(\cplx_error_accum[32]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[33]_i_1 
       (.I0(cplx_dqin_byte_103[33]),
        .I1(cplx_data_byte_103[33]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [27]),
        .O(\cplx_error_accum[33]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[34]_i_1 
       (.I0(cplx_dqin_byte_103[34]),
        .I1(cplx_data_byte_103[34]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [28]),
        .O(\cplx_error_accum[34]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[35]_i_1 
       (.I0(cplx_dqin_byte_103[35]),
        .I1(cplx_data_byte_103[35]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [29]),
        .O(\cplx_error_accum[35]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[36]_i_1 
       (.I0(cplx_dqin_byte_103[36]),
        .I1(cplx_data_byte_103[36]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [30]),
        .O(\cplx_error_accum[36]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[37]_i_1 
       (.I0(cplx_dqin_byte_103[37]),
        .I1(cplx_data_byte_103[37]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [31]),
        .O(\cplx_error_accum[37]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[38]_i_1 
       (.I0(cplx_dqin_byte_103[38]),
        .I1(cplx_data_byte_103[38]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [32]),
        .O(\cplx_error_accum[38]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[39]_i_1 
       (.I0(cplx_dqin_byte_103[39]),
        .I1(cplx_data_byte_103[39]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [33]),
        .O(\cplx_error_accum[39]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[3]_i_1 
       (.I0(cplx_dqin_byte_103[3]),
        .I1(cplx_data_byte_103[3]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [2]),
        .O(\cplx_error_accum[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[40]_i_1 
       (.I0(cplx_dqin_byte_103[40]),
        .I1(cplx_data_byte_103[40]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [34]),
        .O(\cplx_error_accum[40]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[41]_i_1 
       (.I0(cplx_dqin_byte_103[41]),
        .I1(cplx_data_byte_103[41]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [35]),
        .O(\cplx_error_accum[41]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[42]_i_1 
       (.I0(cplx_dqin_byte_103[42]),
        .I1(cplx_data_byte_103[42]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [36]),
        .O(\cplx_error_accum[42]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[43]_i_1 
       (.I0(cplx_dqin_byte_103[43]),
        .I1(cplx_data_byte_103[43]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [37]),
        .O(\cplx_error_accum[43]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[44]_i_1 
       (.I0(cplx_dqin_byte_103[44]),
        .I1(cplx_data_byte_103[44]),
        .I2(cplx_dqin_valid_103),
        .I3(cplx_err_log74[12]),
        .O(\cplx_error_accum[44]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[45]_i_1 
       (.I0(cplx_dqin_byte_103[45]),
        .I1(cplx_data_byte_103[45]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [38]),
        .O(\cplx_error_accum[45]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[46]_i_1 
       (.I0(cplx_dqin_byte_103[46]),
        .I1(cplx_data_byte_103[46]),
        .I2(cplx_dqin_valid_103),
        .I3(cplx_err_log74[14]),
        .O(\cplx_error_accum[46]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[47]_i_1 
       (.I0(cplx_dqin_byte_103[47]),
        .I1(cplx_data_byte_103[47]),
        .I2(cplx_dqin_valid_103),
        .I3(cplx_err_log74[15]),
        .O(\cplx_error_accum[47]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[48]_i_1 
       (.I0(cplx_dqin_byte_103[48]),
        .I1(cplx_data_byte_103[48]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [39]),
        .O(\cplx_error_accum[48]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[49]_i_1 
       (.I0(cplx_dqin_byte_103[49]),
        .I1(cplx_data_byte_103[49]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [40]),
        .O(\cplx_error_accum[49]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[4]_i_1 
       (.I0(cplx_dqin_byte_103[4]),
        .I1(cplx_data_byte_103[4]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [3]),
        .O(\cplx_error_accum[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[50]_i_1 
       (.I0(cplx_dqin_byte_103[50]),
        .I1(cplx_data_byte_103[50]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [41]),
        .O(\cplx_error_accum[50]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[51]_i_1 
       (.I0(cplx_dqin_byte_103[51]),
        .I1(cplx_data_byte_103[51]),
        .I2(cplx_dqin_valid_103),
        .I3(cplx_err_log74[19]),
        .O(\cplx_error_accum[51]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[52]_i_1 
       (.I0(cplx_dqin_byte_103[52]),
        .I1(cplx_data_byte_103[52]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [42]),
        .O(\cplx_error_accum[52]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[53]_i_1 
       (.I0(cplx_dqin_byte_103[53]),
        .I1(cplx_data_byte_103[53]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [43]),
        .O(\cplx_error_accum[53]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[54]_i_1 
       (.I0(cplx_dqin_byte_103[54]),
        .I1(cplx_data_byte_103[54]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [44]),
        .O(\cplx_error_accum[54]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[55]_i_1 
       (.I0(cplx_dqin_byte_103[55]),
        .I1(cplx_data_byte_103[55]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [45]),
        .O(\cplx_error_accum[55]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[56]_i_1 
       (.I0(cplx_dqin_byte_103[56]),
        .I1(cplx_data_byte_103[56]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [46]),
        .O(\cplx_error_accum[56]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[57]_i_1 
       (.I0(cplx_dqin_byte_103[57]),
        .I1(cplx_data_byte_103[57]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [47]),
        .O(\cplx_error_accum[57]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[58]_i_1 
       (.I0(cplx_dqin_byte_103[58]),
        .I1(cplx_data_byte_103[58]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [48]),
        .O(\cplx_error_accum[58]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[59]_i_1 
       (.I0(cplx_dqin_byte_103[59]),
        .I1(cplx_data_byte_103[59]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [49]),
        .O(\cplx_error_accum[59]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[5]_i_1 
       (.I0(cplx_dqin_byte_103[5]),
        .I1(cplx_data_byte_103[5]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [4]),
        .O(\cplx_error_accum[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[60]_i_1 
       (.I0(cplx_dqin_byte_103[60]),
        .I1(cplx_data_byte_103[60]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [50]),
        .O(\cplx_error_accum[60]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[61]_i_1 
       (.I0(cplx_dqin_byte_103[61]),
        .I1(cplx_data_byte_103[61]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [51]),
        .O(\cplx_error_accum[61]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[62]_i_1 
       (.I0(cplx_dqin_byte_103[62]),
        .I1(cplx_data_byte_103[62]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [52]),
        .O(\cplx_error_accum[62]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAABA)) 
    \cplx_error_accum[63]_i_1 
       (.I0(out),
        .I1(cplx_state[1]),
        .I2(cplx_state[0]),
        .I3(cplx_state[2]),
        .I4(cplx_state[3]),
        .O(cplx_error_accum));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[63]_i_2 
       (.I0(cplx_dqin_byte_103[63]),
        .I1(cplx_data_byte_103[63]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [53]),
        .O(\cplx_error_accum[63]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[6]_i_1 
       (.I0(cplx_dqin_byte_103[6]),
        .I1(cplx_data_byte_103[6]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [5]),
        .O(\cplx_error_accum[6]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[7]_i_1 
       (.I0(cplx_dqin_byte_103[7]),
        .I1(cplx_data_byte_103[7]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [6]),
        .O(\cplx_error_accum[7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[8]_i_1 
       (.I0(cplx_dqin_byte_103[8]),
        .I1(cplx_data_byte_103[8]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [7]),
        .O(\cplx_error_accum[8]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFF60)) 
    \cplx_error_accum[9]_i_1 
       (.I0(cplx_dqin_byte_103[9]),
        .I1(cplx_data_byte_103[9]),
        .I2(cplx_dqin_valid_103),
        .I3(\cplx_error_accum_reg[63]_0 [8]),
        .O(\cplx_error_accum[9]_i_1_n_0 ));
  FDRE \cplx_error_accum_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[0]_i_1_n_0 ),
        .Q(cplx_err_log30[0]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[10] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[10]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [9]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[11] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[11]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [10]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[12] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[12]_i_1_n_0 ),
        .Q(cplx_err_log30[12]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[13] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[13]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [11]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[14] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[14]_i_1_n_0 ),
        .Q(cplx_err_log30[14]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[15] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[15]_i_1_n_0 ),
        .Q(cplx_err_log30[15]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[16] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[16]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [12]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[17] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[17]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [13]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[18] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[18]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [14]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[19] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[19]_i_1_n_0 ),
        .Q(cplx_err_log30[19]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[1]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [0]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[20] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[20]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [15]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[21] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[21]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [16]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[22] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[22]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [17]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[23] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[23]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [18]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[24] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[24]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [19]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[25] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[25]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [20]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[26] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[26]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [21]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[27] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[27]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [22]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[28] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[28]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [23]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[29] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[29]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [24]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[2]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [1]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[30] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[30]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [25]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[31] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[31]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [26]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[32] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[32]_i_1_n_0 ),
        .Q(cplx_err_log74[0]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[33] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[33]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [27]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[34] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[34]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [28]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[35] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[35]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [29]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[36] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[36]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [30]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[37] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[37]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [31]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[38] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[38]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [32]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[39] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[39]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [33]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[3]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [2]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[40] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[40]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [34]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[41] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[41]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [35]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[42] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[42]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [36]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[43] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[43]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [37]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[44] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[44]_i_1_n_0 ),
        .Q(cplx_err_log74[12]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[45] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[45]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [38]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[46] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[46]_i_1_n_0 ),
        .Q(cplx_err_log74[14]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[47] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[47]_i_1_n_0 ),
        .Q(cplx_err_log74[15]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[48] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[48]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [39]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[49] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[49]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [40]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[4]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [3]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[50] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[50]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [41]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[51] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[51]_i_1_n_0 ),
        .Q(cplx_err_log74[19]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[52] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[52]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [42]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[53] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[53]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [43]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[54] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[54]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [44]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[55] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[55]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [45]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[56] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[56]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [46]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[57] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[57]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [47]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[58] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[58]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [48]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[59] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[59]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [49]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[5] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[5]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [4]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[60] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[60]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [50]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[61] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[61]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [51]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[62] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[62]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [52]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[63] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[63]_i_2_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [53]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[6] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[6]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [5]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[7] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[7]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [6]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[8] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[8]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [7]),
        .R(cplx_error_accum));
  FDRE \cplx_error_accum_reg[9] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\cplx_error_accum[9]_i_1_n_0 ),
        .Q(\cplx_error_accum_reg[63]_0 [8]),
        .R(cplx_error_accum));
  (* SOFT_HLUTNM = "soft_lutpair522" *) 
  LUT5 #(
    .INIT(32'h20000000)) 
    cplx_issue_cas_rd_i_1
       (.I0(cas_is_read),
        .I1(seq_state[3]),
        .I2(seq_state[2]),
        .I3(seq_state[0]),
        .I4(seq_state[1]),
        .O(p_0_in1_out));
  FDRE cplx_issue_cas_rd_reg
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in1_out),
        .Q(cplx_issue_cas_rd),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair522" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    cplx_issue_cas_wr_i_1
       (.I0(seq_state[3]),
        .I1(seq_state[2]),
        .I2(seq_state[0]),
        .I3(seq_state[1]),
        .I4(cas_is_read),
        .O(cplx_issue_cas_wr_nxt));
  FDRE cplx_issue_cas_wr_reg
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_issue_cas_wr_nxt),
        .Q(cplx_issue_cas_wr),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hAAA6A6AA)) 
    \cplx_loops[0]_i_1 
       (.I0(cplx_loops_reg[0]),
        .I1(cplx_state[1]),
        .I2(cplx_state[0]),
        .I3(cplx_state[3]),
        .I4(cplx_state[2]),
        .O(p_0_in__1[0]));
  LUT6 #(
    .INIT(64'hAA96AAAAAAAAAAAA)) 
    \cplx_loops[1]_i_1 
       (.I0(cplx_loops_reg[1]),
        .I1(cplx_state[2]),
        .I2(cplx_state[3]),
        .I3(cplx_state[0]),
        .I4(cplx_state[1]),
        .I5(cplx_loops_reg[0]),
        .O(p_0_in__1[1]));
  LUT6 #(
    .INIT(64'hAA6AAAAAAAAAAAAA)) 
    \cplx_loops[2]_i_1 
       (.I0(cplx_loops_reg[2]),
        .I1(cplx_loops_reg[0]),
        .I2(cplx_state[1]),
        .I3(cplx_state[0]),
        .I4(\FSM_sequential_cplx_state[1]_i_2_n_0 ),
        .I5(cplx_loops_reg[1]),
        .O(p_0_in__1[2]));
  LUT3 #(
    .INIT(8'hB4)) 
    \cplx_loops[3]_i_1 
       (.I0(\cplx_loops[6]_i_2_n_0 ),
        .I1(cplx_loops_reg[2]),
        .I2(cplx_loops_reg[3]),
        .O(p_0_in__1[3]));
  (* SOFT_HLUTNM = "soft_lutpair524" *) 
  LUT4 #(
    .INIT(16'h9AAA)) 
    \cplx_loops[4]_i_1 
       (.I0(cplx_loops_reg[4]),
        .I1(\cplx_loops[6]_i_2_n_0 ),
        .I2(cplx_loops_reg[2]),
        .I3(cplx_loops_reg[3]),
        .O(p_0_in__1[4]));
  (* SOFT_HLUTNM = "soft_lutpair524" *) 
  LUT5 #(
    .INIT(32'hAA6AAAAA)) 
    \cplx_loops[5]_i_1 
       (.I0(cplx_loops_reg[5]),
        .I1(cplx_loops_reg[3]),
        .I2(cplx_loops_reg[2]),
        .I3(\cplx_loops[6]_i_2_n_0 ),
        .I4(cplx_loops_reg[4]),
        .O(p_0_in__1[5]));
  LUT6 #(
    .INIT(64'hA6AAAAAAAAAAAAAA)) 
    \cplx_loops[6]_i_1 
       (.I0(cplx_loops_reg[6]),
        .I1(cplx_loops_reg[4]),
        .I2(\cplx_loops[6]_i_2_n_0 ),
        .I3(cplx_loops_reg[2]),
        .I4(cplx_loops_reg[3]),
        .I5(cplx_loops_reg[5]),
        .O(p_0_in__1[6]));
  LUT6 #(
    .INIT(64'hFFF7F7FFFFFFFFFF)) 
    \cplx_loops[6]_i_2 
       (.I0(cplx_loops_reg[0]),
        .I1(cplx_state[1]),
        .I2(cplx_state[0]),
        .I3(cplx_state[3]),
        .I4(cplx_state[2]),
        .I5(cplx_loops_reg[1]),
        .O(\cplx_loops[6]_i_2_n_0 ));
  FDRE \cplx_loops_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__1[0]),
        .Q(cplx_loops_reg[0]),
        .R(cplx_error_accum));
  FDRE \cplx_loops_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__1[1]),
        .Q(cplx_loops_reg[1]),
        .R(cplx_error_accum));
  FDRE \cplx_loops_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__1[2]),
        .Q(cplx_loops_reg[2]),
        .R(cplx_error_accum));
  FDRE \cplx_loops_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__1[3]),
        .Q(cplx_loops_reg[3]),
        .R(cplx_error_accum));
  FDRE \cplx_loops_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__1[4]),
        .Q(cplx_loops_reg[4]),
        .R(cplx_error_accum));
  FDRE \cplx_loops_reg[5] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__1[5]),
        .Q(cplx_loops_reg[5]),
        .R(cplx_error_accum));
  FDRE \cplx_loops_reg[6] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__1[6]),
        .Q(cplx_loops_reg[6]),
        .R(cplx_error_accum));
  LUT6 #(
    .INIT(64'hEEE0EEEEEEEEEEEE)) 
    \cplx_status[0]_i_1 
       (.I0(cplx_status),
        .I1(\FSM_sequential_cplx_state_reg[1]_0 [0]),
        .I2(cplx_state[0]),
        .I3(cplx_state[1]),
        .I4(cplx_state[2]),
        .I5(cplx_state[3]),
        .O(cplx_status_nxt));
  FDRE \cplx_status_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_status_nxt),
        .Q(cplx_status),
        .R(out));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(cplx_config_byte_select_nxt[4]));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(cplx_config_byte_select_nxt[3]));
  (* SOFT_HLUTNM = "soft_lutpair621" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \mcal_ACT_n_dly[0][0]_i_1 
       (.I0(\mcal_ACT_n_dly_reg[0][7] [0]),
        .I1(cplx_cal),
        .I2(ub_ready),
        .O(\cal_ACT_n_pre_reg[7] [0]));
  (* SOFT_HLUTNM = "soft_lutpair621" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \mcal_ACT_n_dly[0][1]_i_1 
       (.I0(\mcal_ACT_n_dly_reg[0][7] [1]),
        .I1(cplx_cal),
        .I2(ub_ready),
        .O(\cal_ACT_n_pre_reg[7] [1]));
  (* SOFT_HLUTNM = "soft_lutpair622" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \mcal_ACT_n_dly[0][2]_i_1 
       (.I0(\mcal_ACT_n_dly_reg[0][7] [2]),
        .I1(cplx_cal),
        .I2(ub_ready),
        .O(\cal_ACT_n_pre_reg[7] [2]));
  (* SOFT_HLUTNM = "soft_lutpair624" *) 
  LUT3 #(
    .INIT(8'h74)) 
    \mcal_ACT_n_dly[0][3]_i_1 
       (.I0(winAct),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ACT_n[3]),
        .O(winAct_reg[0]));
  (* SOFT_HLUTNM = "soft_lutpair614" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \mcal_ACT_n_dly[0][3]_i_2 
       (.I0(\mcal_ACT_n_dly_reg[0][7] [3]),
        .I1(cplx_cal),
        .I2(ub_ready),
        .O(cal_ACT_n[3]));
  (* SOFT_HLUTNM = "soft_lutpair624" *) 
  LUT3 #(
    .INIT(8'h74)) 
    \mcal_ACT_n_dly[0][4]_i_1 
       (.I0(winAct),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ACT_n[4]),
        .O(winAct_reg[1]));
  (* SOFT_HLUTNM = "soft_lutpair614" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \mcal_ACT_n_dly[0][4]_i_2 
       (.I0(cplx_cal),
        .I1(\mcal_ACT_n_dly_reg[0][7] [4]),
        .I2(ub_ready),
        .O(cal_ACT_n[4]));
  (* SOFT_HLUTNM = "soft_lutpair540" *) 
  LUT4 #(
    .INIT(16'hB8FF)) 
    \mcal_ACT_n_dly[0][5]_i_1 
       (.I0(cplx_ACT_n),
        .I1(cplx_cal),
        .I2(\mcal_ACT_n_dly_reg[0][7] [5]),
        .I3(ub_ready),
        .O(\cal_ACT_n_pre_reg[7] [3]));
  (* SOFT_HLUTNM = "soft_lutpair540" *) 
  LUT4 #(
    .INIT(16'hB8FF)) 
    \mcal_ACT_n_dly[0][6]_i_1 
       (.I0(cplx_ACT_n),
        .I1(cplx_cal),
        .I2(\mcal_ACT_n_dly_reg[0][7] [6]),
        .I3(ub_ready),
        .O(\cal_ACT_n_pre_reg[7] [4]));
  (* SOFT_HLUTNM = "soft_lutpair622" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \mcal_ACT_n_dly[0][7]_i_1 
       (.I0(\mcal_ACT_n_dly_reg[0][7] [7]),
        .I1(cplx_cal),
        .I2(ub_ready),
        .O(\cal_ACT_n_pre_reg[7] [5]));
  (* SOFT_HLUTNM = "soft_lutpair615" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][0]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[7]),
        .O(calDone_reg[0]));
  (* SOFT_HLUTNM = "soft_lutpair599" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][100]_i_1 
       (.I0(mc_ADR[30]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[103]),
        .O(calDone_reg[58]));
  (* SOFT_HLUTNM = "soft_lutpair599" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][102]_i_1 
       (.I0(mc_ADR[32]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[103]),
        .O(calDone_reg[59]));
  (* SOFT_HLUTNM = "soft_lutpair578" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][103]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[103]),
        .O(calDone_reg[60]));
  LUT6 #(
    .INIT(64'h00E200E2FFFF0000)) 
    \mcal_ADR_dly[0][103]_i_2 
       (.I0(\mcal_BG_dly[0][7]_i_2_0 [12]),
        .I1(a_b_cmd_sel),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [12]),
        .I3(cplx_cal),
        .I4(\mcal_ADR_dly_reg[0][134] [11]),
        .I5(ub_ready),
        .O(cal_ADR[103]));
  (* SOFT_HLUTNM = "soft_lutpair623" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][104]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[111]),
        .O(calDone_reg[61]));
  (* SOFT_HLUTNM = "soft_lutpair598" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][108]_i_1 
       (.I0(mc_ADR[31]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[111]),
        .O(calDone_reg[62]));
  (* SOFT_HLUTNM = "soft_lutpair598" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][110]_i_1 
       (.I0(mc_ADR[32]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[111]),
        .O(calDone_reg[63]));
  (* SOFT_HLUTNM = "soft_lutpair578" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][111]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[111]),
        .O(calDone_reg[64]));
  LUT5 #(
    .INIT(32'h00E20000)) 
    \mcal_ADR_dly[0][111]_i_2 
       (.I0(\mcal_BG_dly[0][7]_i_2_0 [13]),
        .I1(a_b_cmd_sel),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [13]),
        .I3(cplx_cal),
        .I4(ub_ready),
        .O(cal_ADR[111]));
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][112]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [2]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[112]),
        .O(calDone_reg[65]));
  (* SOFT_HLUTNM = "soft_lutpair531" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][112]_i_2 
       (.I0(rdCAS_reg[0]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [14]),
        .I3(ub_ready),
        .O(cal_ADR[112]));
  (* SOFT_HLUTNM = "soft_lutpair531" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][113]_i_2 
       (.I0(rdCAS_reg[1]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [14]),
        .I3(ub_ready),
        .O(\cplx_CAS_reg[6]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair532" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][114]_i_2 
       (.I0(rdCAS_reg[2]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [14]),
        .I3(ub_ready),
        .O(\cplx_CAS_reg[6]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair620" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][115]_i_1 
       (.I0(mc_ADR[33]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[115]),
        .O(calDone_reg[66]));
  (* SOFT_HLUTNM = "soft_lutpair533" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][115]_i_2 
       (.I0(rdCAS_reg[3]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [12]),
        .I3(ub_ready),
        .O(cal_ADR[115]));
  (* SOFT_HLUTNM = "soft_lutpair619" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][116]_i_1 
       (.I0(mc_ADR[33]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[116]),
        .O(calDone_reg[67]));
  (* SOFT_HLUTNM = "soft_lutpair533" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][116]_i_3 
       (.I0(rdCAS_reg[4]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [12]),
        .I3(ub_ready),
        .O(cal_ADR[116]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \mcal_ADR_dly[0][117]_i_2 
       (.I0(cplx_WE),
        .I1(cplx_cal),
        .I2(rdCAS_reg[5]),
        .I3(\mcal_ADR_dly_reg[0][134] [14]),
        .I4(ub_ready),
        .O(\cplx_CAS_reg[6]_0 [2]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \mcal_ADR_dly[0][118]_i_2 
       (.I0(cplx_WE),
        .I1(cplx_cal),
        .I2(rdCAS_reg[6]),
        .I3(\mcal_ADR_dly_reg[0][134] [14]),
        .I4(ub_ready),
        .O(\cplx_CAS_reg[6]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair613" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][119]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [2]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[119]),
        .O(calDone_reg[68]));
  (* SOFT_HLUTNM = "soft_lutpair532" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][119]_i_2 
       (.I0(rdCAS_reg[7]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [14]),
        .I3(ub_ready),
        .O(cal_ADR[119]));
  (* SOFT_HLUTNM = "soft_lutpair625" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][120]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [3]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[120]),
        .O(calDone_reg[69]));
  (* SOFT_HLUTNM = "soft_lutpair537" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][120]_i_2 
       (.I0(Q[0]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [14]),
        .I3(ub_ready),
        .O(cal_ADR[120]));
  (* SOFT_HLUTNM = "soft_lutpair537" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][121]_i_2 
       (.I0(Q[1]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [14]),
        .I3(ub_ready),
        .O(\cplx_CAS_reg[6]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair538" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][122]_i_2 
       (.I0(Q[2]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [14]),
        .I3(ub_ready),
        .O(\cplx_CAS_reg[6]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair619" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][123]_i_1 
       (.I0(mc_ADR[34]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[123]),
        .O(calDone_reg[70]));
  (* SOFT_HLUTNM = "soft_lutpair536" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][123]_i_2 
       (.I0(Q[3]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [13]),
        .I3(ub_ready),
        .O(cal_ADR[123]));
  (* SOFT_HLUTNM = "soft_lutpair618" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][124]_i_1 
       (.I0(mc_ADR[34]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[124]),
        .O(calDone_reg[71]));
  (* SOFT_HLUTNM = "soft_lutpair536" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][124]_i_3 
       (.I0(cplx_cal),
        .I1(Q[4]),
        .I2(\mcal_ADR_dly_reg[0][134] [13]),
        .I3(ub_ready),
        .O(cal_ADR[124]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \mcal_ADR_dly[0][125]_i_2 
       (.I0(cplx_CAS),
        .I1(cplx_cal),
        .I2(Q[5]),
        .I3(\mcal_ADR_dly_reg[0][134] [14]),
        .I4(ub_ready),
        .O(\cplx_CAS_reg[6]_0 [6]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \mcal_ADR_dly[0][126]_i_2 
       (.I0(cplx_CAS),
        .I1(cplx_cal),
        .I2(Q[6]),
        .I3(\mcal_ADR_dly_reg[0][134] [14]),
        .I4(ub_ready),
        .O(\cplx_CAS_reg[6]_0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair613" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][127]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [3]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[127]),
        .O(calDone_reg[72]));
  (* SOFT_HLUTNM = "soft_lutpair538" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][127]_i_2 
       (.I0(Q[7]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [14]),
        .I3(ub_ready),
        .O(cal_ADR[127]));
  (* SOFT_HLUTNM = "soft_lutpair625" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][128]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [4]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[128]),
        .O(calDone_reg[73]));
  (* SOFT_HLUTNM = "soft_lutpair542" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][128]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][135] [0]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [14]),
        .I3(ub_ready),
        .O(cal_ADR[128]));
  (* SOFT_HLUTNM = "soft_lutpair543" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][129]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135] [1]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [14]),
        .I3(ub_ready),
        .O(\cal_RAS_pre_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair609" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][12]_i_1 
       (.I0(mc_ADR[3]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[15]),
        .O(calDone_reg[6]));
  (* SOFT_HLUTNM = "soft_lutpair543" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][130]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135] [2]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [14]),
        .I3(ub_ready),
        .O(\cal_RAS_pre_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair618" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][131]_i_1 
       (.I0(mc_ADR[35]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(\mcal_ADR_dly[0][131]_i_2_n_0 ),
        .O(calDone_reg[74]));
  (* SOFT_HLUTNM = "soft_lutpair541" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][131]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][135] [3]),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][134] [13]),
        .I3(ub_ready),
        .O(\mcal_ADR_dly[0][131]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair617" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][132]_i_1 
       (.I0(mc_ADR[35]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(\mcal_ADR_dly[0][132]_i_3_n_0 ),
        .O(calDone_reg[75]));
  (* SOFT_HLUTNM = "soft_lutpair541" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][132]_i_3 
       (.I0(cplx_cal),
        .I1(\mcal_ADR_dly_reg[0][135] [4]),
        .I2(\mcal_ADR_dly_reg[0][134] [13]),
        .I3(ub_ready),
        .O(\mcal_ADR_dly[0][132]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \mcal_ADR_dly[0][133]_i_1 
       (.I0(cplx_RAS),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][135] [5]),
        .I3(\mcal_ADR_dly_reg[0][134] [14]),
        .I4(ub_ready),
        .O(\cplx_RAS_reg[6]_0 ));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    \mcal_ADR_dly[0][134]_i_1 
       (.I0(cplx_RAS),
        .I1(cplx_cal),
        .I2(\mcal_ADR_dly_reg[0][135] [6]),
        .I3(\mcal_ADR_dly_reg[0][134] [14]),
        .I4(ub_ready),
        .O(\cplx_RAS_reg[6]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair617" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][135]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [4]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(\mcal_ADR_dly[0][135]_i_2_n_0 ),
        .O(calDone_reg[76]));
  (* SOFT_HLUTNM = "soft_lutpair542" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    \mcal_ADR_dly[0][135]_i_2 
       (.I0(cplx_cal),
        .I1(\mcal_ADR_dly_reg[0][135] [7]),
        .I2(\mcal_ADR_dly_reg[0][134] [14]),
        .I3(ub_ready),
        .O(\mcal_ADR_dly[0][135]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair609" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][14]_i_1 
       (.I0(mc_ADR[32]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[15]),
        .O(calDone_reg[7]));
  (* SOFT_HLUTNM = "soft_lutpair583" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][15]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[15]),
        .O(calDone_reg[8]));
  LUT3 #(
    .INIT(8'hAC)) 
    \mcal_ADR_dly[0][15]_i_2 
       (.I0(ub_cal_ADR[8]),
        .I1(\mcal_ADR_dly_reg[0][134] [1]),
        .I2(ub_ready),
        .O(cal_ADR[15]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \mcal_ADR_dly[0][15]_i_3 
       (.I0(cplx_ADR[1]),
        .I1(cplx_cal),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [1]),
        .I3(a_b_cmd_sel),
        .I4(\mcal_BG_dly[0][7]_i_2_0 [1]),
        .O(ub_cal_ADR[8]));
  (* SOFT_HLUTNM = "soft_lutpair615" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][16]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[23]),
        .O(calDone_reg[9]));
  (* SOFT_HLUTNM = "soft_lutpair608" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][20]_i_1 
       (.I0(mc_ADR[4]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[23]),
        .O(calDone_reg[10]));
  (* SOFT_HLUTNM = "soft_lutpair608" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][22]_i_1 
       (.I0(mc_ADR[32]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[23]),
        .O(calDone_reg[11]));
  (* SOFT_HLUTNM = "soft_lutpair583" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][23]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[23]),
        .O(calDone_reg[12]));
  LUT3 #(
    .INIT(8'hAC)) 
    \mcal_ADR_dly[0][23]_i_2 
       (.I0(ub_cal_ADR[16]),
        .I1(\mcal_ADR_dly_reg[0][134] [2]),
        .I2(ub_ready),
        .O(cal_ADR[23]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \mcal_ADR_dly[0][23]_i_3 
       (.I0(cplx_ADR[2]),
        .I1(cplx_cal),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [2]),
        .I3(a_b_cmd_sel),
        .I4(\mcal_BG_dly[0][7]_i_2_0 [2]),
        .O(ub_cal_ADR[16]));
  (* SOFT_HLUTNM = "soft_lutpair607" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][24]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[31]),
        .O(calDone_reg[13]));
  (* SOFT_HLUTNM = "soft_lutpair594" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][26]_i_1 
       (.I0(mc_ADR[5]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[31]),
        .O(calDone_reg[14]));
  (* SOFT_HLUTNM = "soft_lutpair607" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][28]_i_1 
       (.I0(mc_ADR[6]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[31]),
        .O(calDone_reg[15]));
  (* SOFT_HLUTNM = "soft_lutpair577" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][2]_i_1 
       (.I0(mc_ADR[0]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[7]),
        .O(calDone_reg[1]));
  (* SOFT_HLUTNM = "soft_lutpair594" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][30]_i_1 
       (.I0(mc_ADR[7]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[31]),
        .O(calDone_reg[16]));
  (* SOFT_HLUTNM = "soft_lutpair582" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][31]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[31]),
        .O(calDone_reg[17]));
  LUT3 #(
    .INIT(8'hAC)) 
    \mcal_ADR_dly[0][31]_i_2 
       (.I0(ub_cal_ADR[24]),
        .I1(\mcal_ADR_dly_reg[0][134] [3]),
        .I2(ub_ready),
        .O(cal_ADR[31]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \mcal_ADR_dly[0][31]_i_3 
       (.I0(cplx_ADR[3]),
        .I1(cplx_cal),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [3]),
        .I3(a_b_cmd_sel),
        .I4(\mcal_BG_dly[0][7]_i_2_0 [3]),
        .O(ub_cal_ADR[24]));
  (* SOFT_HLUTNM = "soft_lutpair606" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][32]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[39]),
        .O(calDone_reg[18]));
  (* SOFT_HLUTNM = "soft_lutpair593" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][34]_i_1 
       (.I0(mc_ADR[8]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[39]),
        .O(calDone_reg[19]));
  (* SOFT_HLUTNM = "soft_lutpair606" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][36]_i_1 
       (.I0(mc_ADR[9]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[39]),
        .O(calDone_reg[20]));
  (* SOFT_HLUTNM = "soft_lutpair593" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][38]_i_1 
       (.I0(mc_ADR[10]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[39]),
        .O(calDone_reg[21]));
  (* SOFT_HLUTNM = "soft_lutpair582" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][39]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[39]),
        .O(calDone_reg[22]));
  LUT3 #(
    .INIT(8'hAC)) 
    \mcal_ADR_dly[0][39]_i_2 
       (.I0(ub_cal_ADR[32]),
        .I1(\mcal_ADR_dly_reg[0][134] [4]),
        .I2(ub_ready),
        .O(cal_ADR[39]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \mcal_ADR_dly[0][39]_i_3 
       (.I0(cplx_ADR[4]),
        .I1(cplx_cal),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [4]),
        .I3(a_b_cmd_sel),
        .I4(\mcal_BG_dly[0][7]_i_2_0 [4]),
        .O(ub_cal_ADR[32]));
  (* SOFT_HLUTNM = "soft_lutpair605" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][40]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[47]),
        .O(calDone_reg[23]));
  (* SOFT_HLUTNM = "soft_lutpair592" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][42]_i_1 
       (.I0(mc_ADR[11]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[47]),
        .O(calDone_reg[24]));
  (* SOFT_HLUTNM = "soft_lutpair605" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][44]_i_1 
       (.I0(mc_ADR[12]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[47]),
        .O(calDone_reg[25]));
  (* SOFT_HLUTNM = "soft_lutpair592" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][46]_i_1 
       (.I0(mc_ADR[13]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[47]),
        .O(calDone_reg[26]));
  (* SOFT_HLUTNM = "soft_lutpair581" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][47]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[47]),
        .O(calDone_reg[27]));
  LUT3 #(
    .INIT(8'hAC)) 
    \mcal_ADR_dly[0][47]_i_2 
       (.I0(ub_cal_ADR[40]),
        .I1(\mcal_ADR_dly_reg[0][134] [5]),
        .I2(ub_ready),
        .O(cal_ADR[47]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \mcal_ADR_dly[0][47]_i_3 
       (.I0(cplx_ADR[5]),
        .I1(cplx_cal),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [5]),
        .I3(a_b_cmd_sel),
        .I4(\mcal_BG_dly[0][7]_i_2_0 [5]),
        .O(ub_cal_ADR[40]));
  (* SOFT_HLUTNM = "soft_lutpair604" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][48]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[55]),
        .O(calDone_reg[28]));
  (* SOFT_HLUTNM = "soft_lutpair584" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][4]_i_1 
       (.I0(mc_ADR[1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[7]),
        .O(calDone_reg[2]));
  (* SOFT_HLUTNM = "soft_lutpair591" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][50]_i_1 
       (.I0(mc_ADR[14]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[55]),
        .O(calDone_reg[29]));
  (* SOFT_HLUTNM = "soft_lutpair604" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][52]_i_1 
       (.I0(mc_ADR[15]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[55]),
        .O(calDone_reg[30]));
  (* SOFT_HLUTNM = "soft_lutpair591" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][54]_i_1 
       (.I0(mc_ADR[16]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[55]),
        .O(calDone_reg[31]));
  (* SOFT_HLUTNM = "soft_lutpair581" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][55]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[55]),
        .O(calDone_reg[32]));
  LUT3 #(
    .INIT(8'hAC)) 
    \mcal_ADR_dly[0][55]_i_2 
       (.I0(ub_cal_ADR[48]),
        .I1(\mcal_ADR_dly_reg[0][134] [6]),
        .I2(ub_ready),
        .O(cal_ADR[55]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \mcal_ADR_dly[0][55]_i_3 
       (.I0(cplx_ADR[6]),
        .I1(cplx_cal),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [6]),
        .I3(a_b_cmd_sel),
        .I4(\mcal_BG_dly[0][7]_i_2_0 [6]),
        .O(ub_cal_ADR[48]));
  (* SOFT_HLUTNM = "soft_lutpair603" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][56]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[63]),
        .O(calDone_reg[33]));
  (* SOFT_HLUTNM = "soft_lutpair590" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][58]_i_1 
       (.I0(mc_ADR[17]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[63]),
        .O(calDone_reg[34]));
  (* SOFT_HLUTNM = "soft_lutpair603" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][60]_i_1 
       (.I0(mc_ADR[18]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[63]),
        .O(calDone_reg[35]));
  (* SOFT_HLUTNM = "soft_lutpair590" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][62]_i_1 
       (.I0(mc_ADR[19]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[63]),
        .O(calDone_reg[36]));
  (* SOFT_HLUTNM = "soft_lutpair580" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][63]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[63]),
        .O(calDone_reg[37]));
  LUT3 #(
    .INIT(8'hAC)) 
    \mcal_ADR_dly[0][63]_i_2 
       (.I0(ub_cal_ADR[56]),
        .I1(\mcal_ADR_dly_reg[0][134] [7]),
        .I2(ub_ready),
        .O(cal_ADR[63]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \mcal_ADR_dly[0][63]_i_3 
       (.I0(cplx_ADR[7]),
        .I1(cplx_cal),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [7]),
        .I3(a_b_cmd_sel),
        .I4(\mcal_BG_dly[0][7]_i_2_0 [7]),
        .O(ub_cal_ADR[56]));
  (* SOFT_HLUTNM = "soft_lutpair602" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][64]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[71]),
        .O(calDone_reg[38]));
  (* SOFT_HLUTNM = "soft_lutpair589" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][66]_i_1 
       (.I0(mc_ADR[20]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[71]),
        .O(calDone_reg[39]));
  (* SOFT_HLUTNM = "soft_lutpair602" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][68]_i_1 
       (.I0(mc_ADR[21]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[71]),
        .O(calDone_reg[40]));
  (* SOFT_HLUTNM = "soft_lutpair577" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][6]_i_1 
       (.I0(mc_ADR[2]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[7]),
        .O(calDone_reg[3]));
  (* SOFT_HLUTNM = "soft_lutpair589" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][70]_i_1 
       (.I0(mc_ADR[22]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[71]),
        .O(calDone_reg[41]));
  (* SOFT_HLUTNM = "soft_lutpair580" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][71]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[71]),
        .O(calDone_reg[42]));
  LUT3 #(
    .INIT(8'hAC)) 
    \mcal_ADR_dly[0][71]_i_2 
       (.I0(ub_cal_ADR[64]),
        .I1(\mcal_ADR_dly_reg[0][134] [8]),
        .I2(ub_ready),
        .O(cal_ADR[71]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \mcal_ADR_dly[0][71]_i_3 
       (.I0(cplx_ADR[8]),
        .I1(cplx_cal),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [8]),
        .I3(a_b_cmd_sel),
        .I4(\mcal_BG_dly[0][7]_i_2_0 [8]),
        .O(ub_cal_ADR[64]));
  (* SOFT_HLUTNM = "soft_lutpair601" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][72]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[79]),
        .O(calDone_reg[43]));
  (* SOFT_HLUTNM = "soft_lutpair588" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][74]_i_1 
       (.I0(mc_ADR[23]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[79]),
        .O(calDone_reg[44]));
  (* SOFT_HLUTNM = "soft_lutpair601" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][76]_i_1 
       (.I0(mc_ADR[24]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[79]),
        .O(calDone_reg[45]));
  (* SOFT_HLUTNM = "soft_lutpair588" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][78]_i_1 
       (.I0(mc_ADR[25]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[79]),
        .O(calDone_reg[46]));
  (* SOFT_HLUTNM = "soft_lutpair579" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][79]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[79]),
        .O(calDone_reg[47]));
  LUT6 #(
    .INIT(64'h00E200E2FFFF0000)) 
    \mcal_ADR_dly[0][79]_i_2 
       (.I0(\mcal_BG_dly[0][7]_i_2_0 [9]),
        .I1(a_b_cmd_sel),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [9]),
        .I3(cplx_cal),
        .I4(\mcal_ADR_dly_reg[0][134] [9]),
        .I5(ub_ready),
        .O(cal_ADR[79]));
  (* SOFT_HLUTNM = "soft_lutpair584" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][7]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[7]),
        .O(calDone_reg[4]));
  LUT3 #(
    .INIT(8'hAC)) 
    \mcal_ADR_dly[0][7]_i_2 
       (.I0(ub_cal_ADR[0]),
        .I1(\mcal_ADR_dly_reg[0][134] [0]),
        .I2(ub_ready),
        .O(cal_ADR[7]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \mcal_ADR_dly[0][7]_i_3 
       (.I0(cplx_ADR[0]),
        .I1(cplx_cal),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [0]),
        .I3(a_b_cmd_sel),
        .I4(\mcal_BG_dly[0][7]_i_2_0 [0]),
        .O(ub_cal_ADR[0]));
  (* SOFT_HLUTNM = "soft_lutpair620" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][80]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [0]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[87]),
        .O(calDone_reg[48]));
  (* SOFT_HLUTNM = "soft_lutpair585" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][82]_i_1 
       (.I0(mc_ADR[26]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[87]),
        .O(calDone_reg[49]));
  (* SOFT_HLUTNM = "soft_lutpair595" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][84]_i_1 
       (.I0(mc_ADR[27]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[87]),
        .O(calDone_reg[50]));
  (* SOFT_HLUTNM = "soft_lutpair585" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][86]_i_1 
       (.I0(mc_ADR[28]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[87]),
        .O(calDone_reg[51]));
  (* SOFT_HLUTNM = "soft_lutpair595" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][87]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [0]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[87]),
        .O(calDone_reg[52]));
  LUT6 #(
    .INIT(64'h00E200E2FFFF0000)) 
    \mcal_ADR_dly[0][87]_i_2 
       (.I0(\mcal_BG_dly[0][7]_i_2_0 [10]),
        .I1(a_b_cmd_sel),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [10]),
        .I3(cplx_cal),
        .I4(\mcal_ADR_dly_reg[0][87] ),
        .I5(ub_ready),
        .O(cal_ADR[87]));
  (* SOFT_HLUTNM = "soft_lutpair623" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][88]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[95]),
        .O(calDone_reg[53]));
  (* SOFT_HLUTNM = "soft_lutpair616" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][8]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[15]),
        .O(calDone_reg[5]));
  (* SOFT_HLUTNM = "soft_lutpair600" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][92]_i_1 
       (.I0(mc_ADR[29]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[95]),
        .O(calDone_reg[54]));
  (* SOFT_HLUTNM = "soft_lutpair600" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][94]_i_1 
       (.I0(mc_ADR[32]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[95]),
        .O(calDone_reg[55]));
  (* SOFT_HLUTNM = "soft_lutpair579" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][95]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][135]_0 [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[95]),
        .O(calDone_reg[56]));
  LUT6 #(
    .INIT(64'h00E200E2FFFF0000)) 
    \mcal_ADR_dly[0][95]_i_2 
       (.I0(\mcal_BG_dly[0][7]_i_2_0 [11]),
        .I1(a_b_cmd_sel),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [11]),
        .I3(cplx_cal),
        .I4(\mcal_ADR_dly_reg[0][134] [10]),
        .I5(ub_ready),
        .O(cal_ADR[95]));
  (* SOFT_HLUTNM = "soft_lutpair616" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_ADR_dly[0][96]_i_1 
       (.I0(\mcal_ADR_dly_reg[0][128] [1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(cal_ADR[103]),
        .O(calDone_reg[57]));
  (* SOFT_HLUTNM = "soft_lutpair612" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_BA_dly[0][0]_i_1 
       (.I0(\mcal_BA_dly_reg[0][8] [0]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(\init_cal_BA_reg[7] ),
        .O(\init_cal_BA_reg[15] [0]));
  LUT5 #(
    .INIT(32'hFF00ACAC)) 
    \mcal_BA_dly[0][10]_i_1 
       (.I0(ub_cal_BA[8]),
        .I1(\mcal_BA_dly_reg[0][15] [1]),
        .I2(ub_ready),
        .I3(mc_BA[3]),
        .I4(\mcal_CS_n_dly_reg[0][0] ),
        .O(\init_cal_BA_reg[15] [5]));
  LUT5 #(
    .INIT(32'hFF00ACAC)) 
    \mcal_BA_dly[0][12]_i_1 
       (.I0(ub_cal_BA[8]),
        .I1(\mcal_BA_dly_reg[0][15] [1]),
        .I2(ub_ready),
        .I3(mc_BA[4]),
        .I4(\mcal_CS_n_dly_reg[0][0] ),
        .O(\init_cal_BA_reg[15] [6]));
  LUT5 #(
    .INIT(32'hFF00ACAC)) 
    \mcal_BA_dly[0][14]_i_1 
       (.I0(ub_cal_BA[8]),
        .I1(\mcal_BA_dly_reg[0][15] [1]),
        .I2(ub_ready),
        .I3(mc_BA[5]),
        .I4(\mcal_CS_n_dly_reg[0][0] ),
        .O(\init_cal_BA_reg[15] [7]));
  LUT5 #(
    .INIT(32'hFF00ACAC)) 
    \mcal_BA_dly[0][15]_i_1 
       (.I0(ub_cal_BA[8]),
        .I1(\mcal_BA_dly_reg[0][15] [1]),
        .I2(ub_ready),
        .I3(mc_BA[6]),
        .I4(\mcal_CS_n_dly_reg[0][0] ),
        .O(\init_cal_BA_reg[15] [8]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \mcal_BA_dly[0][15]_i_2 
       (.I0(cplx_BA[1]),
        .I1(cplx_cal),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [15]),
        .I3(a_b_cmd_sel),
        .I4(\mcal_BG_dly[0][7]_i_2_0 [15]),
        .O(ub_cal_BA[8]));
  (* SOFT_HLUTNM = "soft_lutpair586" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_BA_dly[0][2]_i_1 
       (.I0(mc_BA[0]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(\init_cal_BA_reg[7] ),
        .O(\init_cal_BA_reg[15] [1]));
  (* SOFT_HLUTNM = "soft_lutpair586" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_BA_dly[0][6]_i_1 
       (.I0(mc_BA[1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(\init_cal_BA_reg[7] ),
        .O(\init_cal_BA_reg[15] [2]));
  (* SOFT_HLUTNM = "soft_lutpair612" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_BA_dly[0][7]_i_1 
       (.I0(mc_BA[2]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(\init_cal_BA_reg[7] ),
        .O(\init_cal_BA_reg[15] [3]));
  (* SOFT_HLUTNM = "soft_lutpair610" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \mcal_BA_dly[0][7]_i_2 
       (.I0(ub_cal_BA[0]),
        .I1(\mcal_BA_dly_reg[0][15] [0]),
        .I2(ub_ready),
        .O(\init_cal_BA_reg[7] ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \mcal_BA_dly[0][7]_i_3 
       (.I0(cplx_BA[0]),
        .I1(cplx_cal),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [14]),
        .I3(a_b_cmd_sel),
        .I4(\mcal_BG_dly[0][7]_i_2_0 [14]),
        .O(ub_cal_BA[0]));
  LUT5 #(
    .INIT(32'hFF00ACAC)) 
    \mcal_BA_dly[0][8]_i_1 
       (.I0(ub_cal_BA[8]),
        .I1(\mcal_BA_dly_reg[0][15] [1]),
        .I2(ub_ready),
        .I3(\mcal_BA_dly_reg[0][8] [1]),
        .I4(\mcal_CS_n_dly_reg[0][0] ),
        .O(\init_cal_BA_reg[15] [4]));
  (* SOFT_HLUTNM = "soft_lutpair611" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_BG_dly[0][0]_i_1 
       (.I0(p_1_in),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(\init_cal_BG_reg[7] ),
        .O(calDone_reg_0[0]));
  (* SOFT_HLUTNM = "soft_lutpair587" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_BG_dly[0][2]_i_1 
       (.I0(mc_BG[0]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(\init_cal_BG_reg[7] ),
        .O(calDone_reg_0[1]));
  (* SOFT_HLUTNM = "soft_lutpair587" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_BG_dly[0][6]_i_1 
       (.I0(mc_BG[1]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(\init_cal_BG_reg[7] ),
        .O(calDone_reg_0[2]));
  (* SOFT_HLUTNM = "soft_lutpair611" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \mcal_BG_dly[0][7]_i_1 
       (.I0(mc_BG[2]),
        .I1(\mcal_CS_n_dly_reg[0][0] ),
        .I2(\init_cal_BG_reg[7] ),
        .O(calDone_reg_0[3]));
  (* SOFT_HLUTNM = "soft_lutpair610" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \mcal_BG_dly[0][7]_i_2 
       (.I0(ub_cal_BG),
        .I1(init_cal_BG),
        .I2(ub_ready),
        .O(\init_cal_BG_reg[7] ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \mcal_BG_dly[0][7]_i_3 
       (.I0(cplx_BA[0]),
        .I1(cplx_cal),
        .I2(\mcal_BG_dly[0][7]_i_2_1 [16]),
        .I3(a_b_cmd_sel),
        .I4(\mcal_BG_dly[0][7]_i_2_0 [16]),
        .O(ub_cal_BG));
  LUT5 #(
    .INIT(32'hFF00EFEF)) 
    \mcal_CS_n_dly[0][0]_i_1 
       (.I0(cplx_cal),
        .I1(\mcal_CS_n_dly_reg[0][7] [0]),
        .I2(ub_ready),
        .I3(mc_CS_n7),
        .I4(\mcal_CS_n_dly_reg[0][0] ),
        .O(cplx_cal_reg_0[0]));
  (* SOFT_HLUTNM = "soft_lutpair626" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \mcal_CS_n_dly[0][1]_i_2 
       (.I0(cplx_cal),
        .I1(\mcal_CS_n_dly_reg[0][7] [1]),
        .I2(ub_ready),
        .O(cal_CS_n[0]));
  (* SOFT_HLUTNM = "soft_lutpair626" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \mcal_CS_n_dly[0][2]_i_2 
       (.I0(cplx_cal),
        .I1(\mcal_CS_n_dly_reg[0][7] [2]),
        .I2(ub_ready),
        .O(cal_CS_n[1]));
  LUT6 #(
    .INIT(64'h0000FFFFEEF0EEF0)) 
    \mcal_CS_n_dly[0][3]_i_1 
       (.I0(cplx_cal),
        .I1(\mcal_CS_n_dly_reg[0][7] [3]),
        .I2(init_cal_CS_n),
        .I3(ub_ready),
        .I4(winAct),
        .I5(\mcal_CS_n_dly_reg[0][0] ),
        .O(cplx_cal_reg_0[1]));
  LUT6 #(
    .INIT(64'h0000FFFFEEF0EEF0)) 
    \mcal_CS_n_dly[0][4]_i_1 
       (.I0(cplx_cal),
        .I1(\mcal_CS_n_dly_reg[0][7] [4]),
        .I2(init_cal_CS_n),
        .I3(ub_ready),
        .I4(winAct),
        .I5(\mcal_CS_n_dly_reg[0][0] ),
        .O(cplx_cal_reg_0[2]));
  (* SOFT_HLUTNM = "soft_lutpair544" *) 
  LUT4 #(
    .INIT(16'hB8FF)) 
    \mcal_CS_n_dly[0][5]_i_2 
       (.I0(\cplx_CS_n_reg_n_0_[6] ),
        .I1(cplx_cal),
        .I2(\mcal_CS_n_dly_reg[0][7] [5]),
        .I3(ub_ready),
        .O(cal_CS_n[2]));
  (* SOFT_HLUTNM = "soft_lutpair544" *) 
  LUT4 #(
    .INIT(16'hB8FF)) 
    \mcal_CS_n_dly[0][6]_i_2 
       (.I0(\cplx_CS_n_reg_n_0_[6] ),
        .I1(cplx_cal),
        .I2(\mcal_CS_n_dly_reg[0][7] [6]),
        .I3(ub_ready),
        .O(cal_CS_n[3]));
  LUT5 #(
    .INIT(32'hFF00EFEF)) 
    \mcal_CS_n_dly[0][7]_i_1 
       (.I0(cplx_cal),
        .I1(\mcal_CS_n_dly_reg[0][7] [7]),
        .I2(ub_ready),
        .I3(mc_CS_n),
        .I4(\mcal_CS_n_dly_reg[0][0] ),
        .O(cplx_cal_reg_0[3]));
  LUT6 #(
    .INIT(64'h555555557DD7D77D)) 
    \mcal_PAR_dly[0][0]_i_1 
       (.I0(\mcal_PAR_dly_reg[0][0] ),
        .I1(\init_cal_BA_reg[7] ),
        .I2(\init_cal_BG_reg[7] ),
        .I3(\mcal_PAR_dly[0][0]_i_3_n_0 ),
        .I4(\mcal_PAR_dly[0][7]_i_4_n_0 ),
        .I5(\mcal_CS_n_dly_reg[0][0] ),
        .O(calDone_reg_1[0]));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][0]_i_3 
       (.I0(\mcal_PAR_dly[0][7]_i_6_n_0 ),
        .I1(cal_ADR[112]),
        .I2(cal_ADR[120]),
        .I3(\mcal_PAR_dly[0][7]_i_7_n_0 ),
        .I4(\cal_ACT_n_pre_reg[7] [0]),
        .I5(cal_ADR[128]),
        .O(\mcal_PAR_dly[0][0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h555555557DD7D77D)) 
    \mcal_PAR_dly[0][1]_i_1 
       (.I0(\mcal_PAR_dly_reg[0][1] ),
        .I1(\init_cal_BA_reg[7] ),
        .I2(\init_cal_BG_reg[7] ),
        .I3(\mcal_PAR_dly[0][1]_i_2_n_0 ),
        .I4(\mcal_PAR_dly[0][7]_i_4_n_0 ),
        .I5(\mcal_CS_n_dly_reg[0][0] ),
        .O(calDone_reg_1[1]));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][1]_i_2 
       (.I0(\mcal_PAR_dly[0][7]_i_6_n_0 ),
        .I1(\cplx_CAS_reg[6]_0 [0]),
        .I2(\cplx_CAS_reg[6]_0 [4]),
        .I3(\mcal_PAR_dly[0][7]_i_7_n_0 ),
        .I4(\cal_ACT_n_pre_reg[7] [1]),
        .I5(\cal_RAS_pre_reg[1] ),
        .O(\mcal_PAR_dly[0][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h555555557DD7D77D)) 
    \mcal_PAR_dly[0][2]_i_1 
       (.I0(\mcal_PAR_dly_reg[0][1] ),
        .I1(\init_cal_BA_reg[7] ),
        .I2(\init_cal_BG_reg[7] ),
        .I3(\mcal_PAR_dly[0][2]_i_3_n_0 ),
        .I4(\mcal_PAR_dly[0][7]_i_4_n_0 ),
        .I5(\mcal_CS_n_dly_reg[0][0] ),
        .O(calDone_reg_1[2]));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][2]_i_3 
       (.I0(\mcal_PAR_dly[0][7]_i_6_n_0 ),
        .I1(\cplx_CAS_reg[6]_0 [1]),
        .I2(\cplx_CAS_reg[6]_0 [5]),
        .I3(\mcal_PAR_dly[0][7]_i_7_n_0 ),
        .I4(\cal_ACT_n_pre_reg[7] [2]),
        .I5(\cal_RAS_pre_reg[2] ),
        .O(\mcal_PAR_dly[0][2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h555555557DD7D77D)) 
    \mcal_PAR_dly[0][3]_i_1 
       (.I0(\mcal_PAR_dly_reg[0][3] ),
        .I1(\init_cal_BA_reg[7] ),
        .I2(\init_cal_BG_reg[7] ),
        .I3(\mcal_PAR_dly[0][3]_i_2_n_0 ),
        .I4(\mcal_PAR_dly[0][7]_i_4_n_0 ),
        .I5(\mcal_CS_n_dly_reg[0][0] ),
        .O(calDone_reg_1[3]));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][3]_i_2 
       (.I0(\mcal_PAR_dly[0][7]_i_6_n_0 ),
        .I1(cal_ADR[115]),
        .I2(cal_ADR[123]),
        .I3(\mcal_PAR_dly[0][7]_i_7_n_0 ),
        .I4(cal_ACT_n[3]),
        .I5(\mcal_ADR_dly[0][131]_i_2_n_0 ),
        .O(\mcal_PAR_dly[0][3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h555555557DD7D77D)) 
    \mcal_PAR_dly[0][4]_i_1 
       (.I0(\mcal_PAR_dly_reg[0][3] ),
        .I1(\init_cal_BA_reg[7] ),
        .I2(\init_cal_BG_reg[7] ),
        .I3(\mcal_PAR_dly[0][4]_i_3_n_0 ),
        .I4(\mcal_PAR_dly[0][7]_i_4_n_0 ),
        .I5(\mcal_CS_n_dly_reg[0][0] ),
        .O(calDone_reg_1[4]));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][4]_i_3 
       (.I0(\mcal_PAR_dly[0][7]_i_6_n_0 ),
        .I1(cal_ADR[116]),
        .I2(cal_ADR[124]),
        .I3(\mcal_PAR_dly[0][7]_i_7_n_0 ),
        .I4(cal_ACT_n[4]),
        .I5(\mcal_ADR_dly[0][132]_i_3_n_0 ),
        .O(\mcal_PAR_dly[0][4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h555555557DD7D77D)) 
    \mcal_PAR_dly[0][5]_i_1 
       (.I0(\mcal_PAR_dly_reg[0][5] ),
        .I1(\init_cal_BA_reg[7] ),
        .I2(\init_cal_BG_reg[7] ),
        .I3(\mcal_PAR_dly[0][5]_i_2_n_0 ),
        .I4(\mcal_PAR_dly[0][7]_i_4_n_0 ),
        .I5(\mcal_CS_n_dly_reg[0][0] ),
        .O(calDone_reg_1[5]));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][5]_i_2 
       (.I0(\mcal_PAR_dly[0][7]_i_6_n_0 ),
        .I1(\cplx_CAS_reg[6]_0 [2]),
        .I2(\cplx_CAS_reg[6]_0 [6]),
        .I3(\mcal_PAR_dly[0][7]_i_7_n_0 ),
        .I4(\cal_ACT_n_pre_reg[7] [3]),
        .I5(\cplx_RAS_reg[6]_0 ),
        .O(\mcal_PAR_dly[0][5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h555555557DD7D77D)) 
    \mcal_PAR_dly[0][6]_i_1 
       (.I0(\mcal_PAR_dly_reg[0][5] ),
        .I1(\init_cal_BA_reg[7] ),
        .I2(\init_cal_BG_reg[7] ),
        .I3(\mcal_PAR_dly[0][6]_i_3_n_0 ),
        .I4(\mcal_PAR_dly[0][7]_i_4_n_0 ),
        .I5(\mcal_CS_n_dly_reg[0][0] ),
        .O(calDone_reg_1[6]));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][6]_i_3 
       (.I0(\mcal_PAR_dly[0][7]_i_6_n_0 ),
        .I1(\cplx_CAS_reg[6]_0 [3]),
        .I2(\cplx_CAS_reg[6]_0 [7]),
        .I3(\mcal_PAR_dly[0][7]_i_7_n_0 ),
        .I4(\cal_ACT_n_pre_reg[7] [4]),
        .I5(\cplx_RAS_reg[6]_1 ),
        .O(\mcal_PAR_dly[0][6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h555555557DD7D77D)) 
    \mcal_PAR_dly[0][7]_i_1 
       (.I0(\mcal_PAR_dly_reg[0][7] ),
        .I1(\init_cal_BA_reg[7] ),
        .I2(\init_cal_BG_reg[7] ),
        .I3(\mcal_PAR_dly[0][7]_i_3_n_0 ),
        .I4(\mcal_PAR_dly[0][7]_i_4_n_0 ),
        .I5(\mcal_CS_n_dly_reg[0][0] ),
        .O(calDone_reg_1[7]));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][7]_i_3 
       (.I0(\mcal_PAR_dly[0][7]_i_6_n_0 ),
        .I1(cal_ADR[119]),
        .I2(cal_ADR[127]),
        .I3(\mcal_PAR_dly[0][7]_i_7_n_0 ),
        .I4(\cal_ACT_n_pre_reg[7] [5]),
        .I5(\mcal_ADR_dly[0][135]_i_2_n_0 ),
        .O(\mcal_PAR_dly[0][7]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h53AC)) 
    \mcal_PAR_dly[0][7]_i_4 
       (.I0(ub_cal_BA[8]),
        .I1(\mcal_BA_dly_reg[0][15] [1]),
        .I2(ub_ready),
        .I3(\mcal_PAR_dly[0][7]_i_8_n_0 ),
        .O(\mcal_PAR_dly[0][7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][7]_i_6 
       (.I0(cal_ADR[87]),
        .I1(cal_ADR[95]),
        .I2(cal_ADR[63]),
        .I3(cal_ADR[55]),
        .I4(cal_ADR[79]),
        .I5(cal_ADR[71]),
        .O(\mcal_PAR_dly[0][7]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \mcal_PAR_dly[0][7]_i_7 
       (.I0(cal_ADR[111]),
        .I1(cal_ADR[103]),
        .O(\mcal_PAR_dly[0][7]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][7]_i_8 
       (.I0(cal_ADR[39]),
        .I1(cal_ADR[47]),
        .I2(cal_ADR[15]),
        .I3(cal_ADR[7]),
        .I4(cal_ADR[31]),
        .I5(cal_ADR[23]),
        .O(\mcal_PAR_dly[0][7]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair534" *) 
  LUT4 #(
    .INIT(16'h6A95)) 
    \outstanding_reads[0]_i_1 
       (.I0(u_ddr_cal_cplx_data_n_0),
        .I1(cas_is_read),
        .I2(\burst_count[1]_i_2_n_0 ),
        .I3(\outstanding_reads_reg_n_0_[0] ),
        .O(\outstanding_reads[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAA9995AAAA999)) 
    \outstanding_reads[1]_i_1 
       (.I0(\outstanding_reads_reg_n_0_[1] ),
        .I1(u_ddr_cal_cplx_data_n_0),
        .I2(cas_is_read),
        .I3(\burst_count[1]_i_2_n_0 ),
        .I4(\outstanding_reads_reg_n_0_[0] ),
        .I5(rdDataEn_pi),
        .O(\outstanding_reads[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF3F00C0FEFE0101)) 
    \outstanding_reads[2]_i_1 
       (.I0(u_ddr_cal_cplx_data_n_0),
        .I1(p_0_in1_out),
        .I2(\outstanding_reads_reg_n_0_[0] ),
        .I3(rdDataEn_pi),
        .I4(\outstanding_reads_reg_n_0_[2] ),
        .I5(\outstanding_reads_reg_n_0_[1] ),
        .O(\outstanding_reads[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7EFE8101)) 
    \outstanding_reads[3]_i_1 
       (.I0(\outstanding_reads_reg_n_0_[2] ),
        .I1(\outstanding_reads[4]_i_2_n_0 ),
        .I2(\outstanding_reads_reg_n_0_[1] ),
        .I3(\outstanding_reads[4]_i_3_n_0 ),
        .I4(\outstanding_reads_reg_n_0_[3] ),
        .O(\outstanding_reads[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAA9AAA9)) 
    \outstanding_reads[4]_i_1 
       (.I0(\outstanding_reads_reg_n_0_[4] ),
        .I1(\outstanding_reads_reg_n_0_[2] ),
        .I2(\outstanding_reads_reg_n_0_[1] ),
        .I3(\outstanding_reads[4]_i_2_n_0 ),
        .I4(\outstanding_reads[4]_i_3_n_0 ),
        .I5(\outstanding_reads_reg_n_0_[3] ),
        .O(\outstanding_reads[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair534" *) 
  LUT4 #(
    .INIT(16'hFFEA)) 
    \outstanding_reads[4]_i_2 
       (.I0(u_ddr_cal_cplx_data_n_0),
        .I1(cas_is_read),
        .I2(\burst_count[1]_i_2_n_0 ),
        .I3(\outstanding_reads_reg_n_0_[0] ),
        .O(\outstanding_reads[4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \outstanding_reads[4]_i_3 
       (.I0(rdDataEn_pi),
        .I1(cas_is_read),
        .I2(\burst_count[1]_i_2_n_0 ),
        .I3(\outstanding_reads_reg_n_0_[0] ),
        .O(\outstanding_reads[4]_i_3_n_0 ));
  FDRE \outstanding_reads_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\outstanding_reads[0]_i_1_n_0 ),
        .Q(\outstanding_reads_reg_n_0_[0] ),
        .R(outstanding_reads));
  FDRE \outstanding_reads_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\outstanding_reads[1]_i_1_n_0 ),
        .Q(\outstanding_reads_reg_n_0_[1] ),
        .R(outstanding_reads));
  FDRE \outstanding_reads_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\outstanding_reads[2]_i_1_n_0 ),
        .Q(\outstanding_reads_reg_n_0_[2] ),
        .R(outstanding_reads));
  FDRE \outstanding_reads_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\outstanding_reads[3]_i_1_n_0 ),
        .Q(\outstanding_reads_reg_n_0_[3] ),
        .R(outstanding_reads));
  FDRE \outstanding_reads_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\outstanding_reads[4]_i_1_n_0 ),
        .Q(\outstanding_reads_reg_n_0_[4] ),
        .R(outstanding_reads));
  LUT6 #(
    .INIT(64'hAAAAAAAEAAAAAAAA)) 
    rdCAS_i_1
       (.I0(cplx_issue_cas_rd),
        .I1(rdCAS_i_2_n_0),
        .I2(cplx_issue_cas_wr),
        .I3(rdCAS_reg_0),
        .I4(rdCAS_i_4_n_0),
        .I5(rdCAS_i_5_n_0),
        .O(cplx_issue_cas_rd_reg_0));
  LUT5 #(
    .INIT(32'h070F0F0F)) 
    rdCAS_i_10
       (.I0(\mcal_ADR_dly_reg[0][135] [3]),
        .I1(\mcal_ADR_dly_reg[0][135] [2]),
        .I2(cplx_cal),
        .I3(\mcal_ADR_dly_reg[0][135] [1]),
        .I4(\mcal_ADR_dly_reg[0][135] [0]),
        .O(rdCAS_i_10_n_0));
  LUT6 #(
    .INIT(64'hF088F000F000F000)) 
    rdCAS_i_11
       (.I0(\mcal_ADR_dly_reg[0][135] [6]),
        .I1(\mcal_ADR_dly_reg[0][135] [7]),
        .I2(cplx_RAS),
        .I3(cplx_cal),
        .I4(\mcal_ADR_dly_reg[0][135] [5]),
        .I5(\mcal_ADR_dly_reg[0][135] [4]),
        .O(rdCAS_i_11_n_0));
  LUT6 #(
    .INIT(64'h00000000F8F0F0F0)) 
    rdCAS_i_2
       (.I0(rdCAS_reg[4]),
        .I1(rdCAS_reg[2]),
        .I2(cplx_cal),
        .I3(rdCAS_reg[7]),
        .I4(rdCAS_reg[3]),
        .I5(rdCAS_i_6_n_0),
        .O(rdCAS_i_2_n_0));
  LUT6 #(
    .INIT(64'hAA80AA00AA00AA00)) 
    rdCAS_i_4
       (.I0(rdCAS_i_7_n_0),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(cplx_cal),
        .I4(Q[2]),
        .I5(Q[3]),
        .O(rdCAS_i_4_n_0));
  LUT4 #(
    .INIT(16'h0400)) 
    rdCAS_i_5
       (.I0(rdCAS_i_8_n_0),
        .I1(rdCAS_i_9_n_0),
        .I2(rdCAS_i_10_n_0),
        .I3(rdCAS_i_11_n_0),
        .O(rdCAS_i_5_n_0));
  LUT6 #(
    .INIT(64'h0F770FFF0FFF0FFF)) 
    rdCAS_i_6
       (.I0(rdCAS_reg[0]),
        .I1(rdCAS_reg[1]),
        .I2(cplx_WE),
        .I3(cplx_cal),
        .I4(rdCAS_reg[6]),
        .I5(rdCAS_reg[5]),
        .O(rdCAS_i_6_n_0));
  LUT6 #(
    .INIT(64'hF088F000F000F000)) 
    rdCAS_i_7
       (.I0(Q[7]),
        .I1(Q[6]),
        .I2(cplx_CAS),
        .I3(cplx_cal),
        .I4(Q[5]),
        .I5(Q[4]),
        .O(rdCAS_i_7_n_0));
  LUT5 #(
    .INIT(32'h070F0F0F)) 
    rdCAS_i_8
       (.I0(\mcal_ACT_n_dly_reg[0][7] [2]),
        .I1(\mcal_ACT_n_dly_reg[0][7] [3]),
        .I2(cplx_cal),
        .I3(\mcal_ACT_n_dly_reg[0][7] [0]),
        .I4(\mcal_ACT_n_dly_reg[0][7] [1]),
        .O(rdCAS_i_8_n_0));
  LUT6 #(
    .INIT(64'hF088F000F000F000)) 
    rdCAS_i_9
       (.I0(\mcal_ACT_n_dly_reg[0][7] [7]),
        .I1(\mcal_ACT_n_dly_reg[0][7] [6]),
        .I2(cplx_ACT_n),
        .I3(cplx_cal),
        .I4(\mcal_ACT_n_dly_reg[0][7] [5]),
        .I5(\mcal_ACT_n_dly_reg[0][7] [4]),
        .O(rdCAS_i_9_n_0));
  (* SOFT_HLUTNM = "soft_lutpair528" *) 
  LUT5 #(
    .INIT(32'h9A96AAAA)) 
    \seq_bg[0]_i_1 
       (.I0(seq_bg[0]),
        .I1(seq_state[3]),
        .I2(seq_state[0]),
        .I3(seq_state[1]),
        .I4(seq_state[2]),
        .O(p_1_in_0[0]));
  LUT5 #(
    .INIT(32'hAABAAEBA)) 
    \seq_bg[1]_i_1 
       (.I0(out),
        .I1(seq_state[3]),
        .I2(seq_state[1]),
        .I3(seq_state[0]),
        .I4(seq_state[2]),
        .O(\seq_bg[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAA666AAAAAAAAAA)) 
    \seq_bg[1]_i_2 
       (.I0(seq_bg[1]),
        .I1(seq_state[2]),
        .I2(seq_state[1]),
        .I3(seq_state[0]),
        .I4(seq_state[3]),
        .I5(seq_bg[0]),
        .O(p_1_in_0[1]));
  FDRE \seq_bg_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_1_in_0[0]),
        .Q(seq_bg[0]),
        .R(\seq_bg[1]_i_1_n_0 ));
  FDRE \seq_bg_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_1_in_0[1]),
        .Q(seq_bg[1]),
        .R(\seq_bg[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair523" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \seq_col[0]_i_1 
       (.I0(seq_col_reg[0]),
        .I1(seq_bg[1]),
        .I2(seq_bg[0]),
        .I3(\burst_count[1]_i_2_n_0 ),
        .O(p_0_in__2[0]));
  (* SOFT_HLUTNM = "soft_lutpair523" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \seq_col[1]_i_1 
       (.I0(seq_col_reg[1]),
        .I1(\burst_count[1]_i_2_n_0 ),
        .I2(seq_bg[0]),
        .I3(seq_bg[1]),
        .I4(seq_col_reg[0]),
        .O(p_0_in__2[1]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \seq_col[2]_i_1 
       (.I0(seq_col_reg[0]),
        .I1(seq_bg[1]),
        .I2(seq_bg[0]),
        .I3(\burst_count[1]_i_2_n_0 ),
        .I4(seq_col_reg[1]),
        .I5(seq_col_reg[2]),
        .O(p_0_in__2[2]));
  LUT2 #(
    .INIT(4'h6)) 
    \seq_col[3]_i_1 
       (.I0(seq_col_reg[3]),
        .I1(\seq_col[5]_i_2_n_0 ),
        .O(p_0_in__2[3]));
  (* SOFT_HLUTNM = "soft_lutpair539" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \seq_col[4]_i_1 
       (.I0(seq_col_reg[4]),
        .I1(\seq_col[5]_i_2_n_0 ),
        .I2(seq_col_reg[3]),
        .O(p_0_in__2[4]));
  (* SOFT_HLUTNM = "soft_lutpair539" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \seq_col[5]_i_1 
       (.I0(seq_col_reg[5]),
        .I1(seq_col_reg[3]),
        .I2(\seq_col[5]_i_2_n_0 ),
        .I3(seq_col_reg[4]),
        .O(p_0_in__2[5]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \seq_col[5]_i_2 
       (.I0(seq_col_reg[2]),
        .I1(seq_col_reg[1]),
        .I2(\burst_count[1]_i_2_n_0 ),
        .I3(seq_bg[0]),
        .I4(seq_bg[1]),
        .I5(seq_col_reg[0]),
        .O(\seq_col[5]_i_2_n_0 ));
  FDRE \seq_col_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__2[0]),
        .Q(seq_col_reg[0]),
        .R(outstanding_reads));
  FDRE \seq_col_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__2[1]),
        .Q(seq_col_reg[1]),
        .R(outstanding_reads));
  FDRE \seq_col_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__2[2]),
        .Q(seq_col_reg[2]),
        .R(outstanding_reads));
  FDRE \seq_col_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__2[3]),
        .Q(seq_col_reg[3]),
        .R(outstanding_reads));
  FDRE \seq_col_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__2[4]),
        .Q(seq_col_reg[4]),
        .R(outstanding_reads));
  FDRE \seq_col_reg[5] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__2[5]),
        .Q(seq_col_reg[5]),
        .R(outstanding_reads));
  (* SOFT_HLUTNM = "soft_lutpair525" *) 
  LUT5 #(
    .INIT(32'hAA6AAAAA)) 
    \seq_row[0]_i_1 
       (.I0(seq_row_reg[0]),
        .I1(seq_state[3]),
        .I2(seq_state[2]),
        .I3(seq_state[0]),
        .I4(seq_state[1]),
        .O(p_0_in__0[0]));
  LUT6 #(
    .INIT(64'hA6AAAAAAAAAAAAAA)) 
    \seq_row[1]_i_1 
       (.I0(seq_row_reg[1]),
        .I1(seq_state[1]),
        .I2(seq_state[0]),
        .I3(seq_state[2]),
        .I4(seq_state[3]),
        .I5(seq_row_reg[0]),
        .O(p_0_in__0[1]));
  LUT5 #(
    .INIT(32'hAAAAAAAE)) 
    \seq_row[2]_i_1 
       (.I0(out),
        .I1(seq_state[0]),
        .I2(seq_state[1]),
        .I3(seq_state[3]),
        .I4(seq_state[2]),
        .O(\seq_row[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair535" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \seq_row[2]_i_2 
       (.I0(seq_row_reg[2]),
        .I1(seq_row_reg[0]),
        .I2(seq_row_reg[1]),
        .I3(\seq_row[2]_i_3_n_0 ),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair520" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    \seq_row[2]_i_3 
       (.I0(seq_state[1]),
        .I1(seq_state[0]),
        .I2(seq_state[2]),
        .I3(seq_state[3]),
        .O(\seq_row[2]_i_3_n_0 ));
  FDRE \seq_row_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(seq_row_reg[0]),
        .R(\seq_row[2]_i_1_n_0 ));
  FDRE \seq_row_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(seq_row_reg[1]),
        .R(\seq_row[2]_i_1_n_0 ));
  FDRE \seq_row_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(seq_row_reg[2]),
        .R(\seq_row[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair530" *) 
  LUT5 #(
    .INIT(32'h0000FFFE)) 
    \seq_timer[0]_i_1 
       (.I0(\seq_timer_reg_n_0_[2] ),
        .I1(\seq_timer_reg_n_0_[1] ),
        .I2(\seq_timer_reg_n_0_[4] ),
        .I3(\seq_timer_reg_n_0_[3] ),
        .I4(\seq_timer_reg_n_0_[0] ),
        .O(seq_timer0));
  LUT5 #(
    .INIT(32'hBABAAAEA)) 
    \seq_timer[1]_i_1 
       (.I0(out),
        .I1(seq_state[3]),
        .I2(seq_state[1]),
        .I3(seq_state[2]),
        .I4(seq_state[0]),
        .O(seq_timer[1]));
  (* SOFT_HLUTNM = "soft_lutpair530" *) 
  LUT5 #(
    .INIT(32'hCCCC3332)) 
    \seq_timer[1]_i_2 
       (.I0(\seq_timer_reg_n_0_[2] ),
        .I1(\seq_timer_reg_n_0_[1] ),
        .I2(\seq_timer_reg_n_0_[4] ),
        .I3(\seq_timer_reg_n_0_[3] ),
        .I4(\seq_timer_reg_n_0_[0] ),
        .O(\seq_timer[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFAA0054FFFFFFFF)) 
    \seq_timer[2]_i_1 
       (.I0(\seq_timer_reg_n_0_[0] ),
        .I1(\seq_timer_reg_n_0_[3] ),
        .I2(\seq_timer_reg_n_0_[4] ),
        .I3(\seq_timer_reg_n_0_[1] ),
        .I4(\seq_timer_reg_n_0_[2] ),
        .I5(cplx_CS_n_cmd_nxt),
        .O(\seq_timer[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h666F6666F6666666)) 
    \seq_timer[3]_i_1 
       (.I0(\seq_timer[3]_i_2_n_0 ),
        .I1(\seq_timer_reg_n_0_[3] ),
        .I2(seq_state[0]),
        .I3(seq_state[2]),
        .I4(seq_state[1]),
        .I5(seq_state[3]),
        .O(\seq_timer[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair516" *) 
  LUT5 #(
    .INIT(32'h00001110)) 
    \seq_timer[3]_i_2 
       (.I0(\seq_timer_reg_n_0_[2] ),
        .I1(\seq_timer_reg_n_0_[1] ),
        .I2(\seq_timer_reg_n_0_[4] ),
        .I3(\seq_timer_reg_n_0_[3] ),
        .I4(\seq_timer_reg_n_0_[0] ),
        .O(\seq_timer[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAAEA)) 
    \seq_timer[4]_i_1 
       (.I0(out),
        .I1(seq_state[0]),
        .I2(seq_state[1]),
        .I3(seq_state[3]),
        .I4(seq_state[2]),
        .O(seq_timer[4]));
  LUT6 #(
    .INIT(64'hFFFFFFFFCCCCCCC8)) 
    \seq_timer[4]_i_2 
       (.I0(\seq_timer_reg_n_0_[0] ),
        .I1(\seq_timer_reg_n_0_[4] ),
        .I2(\seq_timer_reg_n_0_[1] ),
        .I3(\seq_timer_reg_n_0_[2] ),
        .I4(\seq_timer_reg_n_0_[3] ),
        .I5(\seq_timer[4]_i_3_n_0 ),
        .O(\seq_timer[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair525" *) 
  LUT4 #(
    .INIT(16'h4008)) 
    \seq_timer[4]_i_3 
       (.I0(seq_state[3]),
        .I1(seq_state[1]),
        .I2(seq_state[2]),
        .I3(seq_state[0]),
        .O(\seq_timer[4]_i_3_n_0 ));
  FDRE \seq_timer_reg[0] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(seq_timer0),
        .Q(\seq_timer_reg_n_0_[0] ),
        .R(seq_timer[1]));
  FDRE \seq_timer_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\seq_timer[1]_i_2_n_0 ),
        .Q(\seq_timer_reg_n_0_[1] ),
        .R(seq_timer[1]));
  FDRE \seq_timer_reg[2] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\seq_timer[2]_i_1_n_0 ),
        .Q(\seq_timer_reg_n_0_[2] ),
        .R(out));
  FDRE \seq_timer_reg[3] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\seq_timer[3]_i_1_n_0 ),
        .Q(\seq_timer_reg_n_0_[3] ),
        .R(seq_timer[4]));
  FDRE \seq_timer_reg[4] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(\seq_timer[4]_i_2_n_0 ),
        .Q(\seq_timer_reg_n_0_[4] ),
        .R(seq_timer[4]));
  ddr4_0_ddr4_v2_2_17_cal_cplx_data u_ddr_cal_cplx_data
       (.D({u_ddr_cal_cplx_data_n_2,u_ddr_cal_cplx_data_n_3,u_ddr_cal_cplx_data_n_4,u_ddr_cal_cplx_data_n_5,u_ddr_cal_cplx_data_n_6,u_ddr_cal_cplx_data_n_7,u_ddr_cal_cplx_data_n_8,u_ddr_cal_cplx_data_n_9,u_ddr_cal_cplx_data_n_10,u_ddr_cal_cplx_data_n_11,u_ddr_cal_cplx_data_n_12,u_ddr_cal_cplx_data_n_13,u_ddr_cal_cplx_data_n_14,u_ddr_cal_cplx_data_n_15,u_ddr_cal_cplx_data_n_16,u_ddr_cal_cplx_data_n_17,u_ddr_cal_cplx_data_n_18,u_ddr_cal_cplx_data_n_19,u_ddr_cal_cplx_data_n_20,u_ddr_cal_cplx_data_n_21,u_ddr_cal_cplx_data_n_22,u_ddr_cal_cplx_data_n_23,u_ddr_cal_cplx_data_n_24,u_ddr_cal_cplx_data_n_25,u_ddr_cal_cplx_data_n_26,u_ddr_cal_cplx_data_n_27,u_ddr_cal_cplx_data_n_28,u_ddr_cal_cplx_data_n_29,u_ddr_cal_cplx_data_n_30,u_ddr_cal_cplx_data_n_31,u_ddr_cal_cplx_data_n_32,u_ddr_cal_cplx_data_n_33,u_ddr_cal_cplx_data_n_34,u_ddr_cal_cplx_data_n_35,u_ddr_cal_cplx_data_n_36,u_ddr_cal_cplx_data_n_37,u_ddr_cal_cplx_data_n_38,u_ddr_cal_cplx_data_n_39,u_ddr_cal_cplx_data_n_40,u_ddr_cal_cplx_data_n_41,u_ddr_cal_cplx_data_n_42,u_ddr_cal_cplx_data_n_43,u_ddr_cal_cplx_data_n_44,u_ddr_cal_cplx_data_n_45,u_ddr_cal_cplx_data_n_46,u_ddr_cal_cplx_data_n_47,u_ddr_cal_cplx_data_n_48,u_ddr_cal_cplx_data_n_49,u_ddr_cal_cplx_data_n_50,u_ddr_cal_cplx_data_n_51,u_ddr_cal_cplx_data_n_52,u_ddr_cal_cplx_data_n_53,u_ddr_cal_cplx_data_n_54,u_ddr_cal_cplx_data_n_55,u_ddr_cal_cplx_data_n_56,u_ddr_cal_cplx_data_n_57,u_ddr_cal_cplx_data_n_58,u_ddr_cal_cplx_data_n_59,u_ddr_cal_cplx_data_n_60,u_ddr_cal_cplx_data_n_61,u_ddr_cal_cplx_data_n_62,u_ddr_cal_cplx_data_n_63,u_ddr_cal_cplx_data_n_64,u_ddr_cal_cplx_data_n_65,u_ddr_cal_cplx_data_n_66,u_ddr_cal_cplx_data_n_67,u_ddr_cal_cplx_data_n_68,u_ddr_cal_cplx_data_n_69,u_ddr_cal_cplx_data_n_70,u_ddr_cal_cplx_data_n_71,u_ddr_cal_cplx_data_n_72,u_ddr_cal_cplx_data_n_73,u_ddr_cal_cplx_data_n_74,u_ddr_cal_cplx_data_n_75,u_ddr_cal_cplx_data_n_76,u_ddr_cal_cplx_data_n_77,u_ddr_cal_cplx_data_n_78,u_ddr_cal_cplx_data_n_79,u_ddr_cal_cplx_data_n_80,u_ddr_cal_cplx_data_n_81,u_ddr_cal_cplx_data_n_82,u_ddr_cal_cplx_data_n_83,u_ddr_cal_cplx_data_n_84,u_ddr_cal_cplx_data_n_85,u_ddr_cal_cplx_data_n_86,u_ddr_cal_cplx_data_n_87,u_ddr_cal_cplx_data_n_88,u_ddr_cal_cplx_data_n_89,u_ddr_cal_cplx_data_n_90,u_ddr_cal_cplx_data_n_91,u_ddr_cal_cplx_data_n_92,u_ddr_cal_cplx_data_n_93,u_ddr_cal_cplx_data_n_94,u_ddr_cal_cplx_data_n_95,u_ddr_cal_cplx_data_n_96,u_ddr_cal_cplx_data_n_97,u_ddr_cal_cplx_data_n_98,u_ddr_cal_cplx_data_n_99,u_ddr_cal_cplx_data_n_100,u_ddr_cal_cplx_data_n_101,u_ddr_cal_cplx_data_n_102,u_ddr_cal_cplx_data_n_103,u_ddr_cal_cplx_data_n_104,u_ddr_cal_cplx_data_n_105,u_ddr_cal_cplx_data_n_106,u_ddr_cal_cplx_data_n_107,u_ddr_cal_cplx_data_n_108,u_ddr_cal_cplx_data_n_109,u_ddr_cal_cplx_data_n_110,u_ddr_cal_cplx_data_n_111,u_ddr_cal_cplx_data_n_112,u_ddr_cal_cplx_data_n_113,u_ddr_cal_cplx_data_n_114,u_ddr_cal_cplx_data_n_115,u_ddr_cal_cplx_data_n_116,u_ddr_cal_cplx_data_n_117,u_ddr_cal_cplx_data_n_118,u_ddr_cal_cplx_data_n_119,u_ddr_cal_cplx_data_n_120,u_ddr_cal_cplx_data_n_121,u_ddr_cal_cplx_data_n_122,u_ddr_cal_cplx_data_n_123,u_ddr_cal_cplx_data_n_124,u_ddr_cal_cplx_data_n_125,u_ddr_cal_cplx_data_n_126,u_ddr_cal_cplx_data_n_127,u_ddr_cal_cplx_data_n_128,u_ddr_cal_cplx_data_n_129,u_ddr_cal_cplx_data_n_130,u_ddr_cal_cplx_data_n_131,u_ddr_cal_cplx_data_n_132,u_ddr_cal_cplx_data_n_133,u_ddr_cal_cplx_data_n_134,u_ddr_cal_cplx_data_n_135,u_ddr_cal_cplx_data_n_136,u_ddr_cal_cplx_data_n_137,u_ddr_cal_cplx_data_n_138,u_ddr_cal_cplx_data_n_139,u_ddr_cal_cplx_data_n_140,u_ddr_cal_cplx_data_n_141,u_ddr_cal_cplx_data_n_142,u_ddr_cal_cplx_data_n_143,u_ddr_cal_cplx_data_n_144,u_ddr_cal_cplx_data_n_145,u_ddr_cal_cplx_data_n_146,u_ddr_cal_cplx_data_n_147,u_ddr_cal_cplx_data_n_148,u_ddr_cal_cplx_data_n_149,u_ddr_cal_cplx_data_n_150,u_ddr_cal_cplx_data_n_151,u_ddr_cal_cplx_data_n_152,u_ddr_cal_cplx_data_n_153,u_ddr_cal_cplx_data_n_154,u_ddr_cal_cplx_data_n_155,u_ddr_cal_cplx_data_n_156,u_ddr_cal_cplx_data_n_157,u_ddr_cal_cplx_data_n_158,u_ddr_cal_cplx_data_n_159,u_ddr_cal_cplx_data_n_160,u_ddr_cal_cplx_data_n_161,u_ddr_cal_cplx_data_n_162,u_ddr_cal_cplx_data_n_163,u_ddr_cal_cplx_data_n_164,u_ddr_cal_cplx_data_n_165,u_ddr_cal_cplx_data_n_166,u_ddr_cal_cplx_data_n_167,u_ddr_cal_cplx_data_n_168,u_ddr_cal_cplx_data_n_169,u_ddr_cal_cplx_data_n_170,u_ddr_cal_cplx_data_n_171,u_ddr_cal_cplx_data_n_172,u_ddr_cal_cplx_data_n_173,u_ddr_cal_cplx_data_n_174,u_ddr_cal_cplx_data_n_175,u_ddr_cal_cplx_data_n_176,u_ddr_cal_cplx_data_n_177,u_ddr_cal_cplx_data_n_178,u_ddr_cal_cplx_data_n_179,u_ddr_cal_cplx_data_n_180,u_ddr_cal_cplx_data_n_181,u_ddr_cal_cplx_data_n_182,u_ddr_cal_cplx_data_n_183,u_ddr_cal_cplx_data_n_184,u_ddr_cal_cplx_data_n_185,u_ddr_cal_cplx_data_n_186,u_ddr_cal_cplx_data_n_187,u_ddr_cal_cplx_data_n_188,u_ddr_cal_cplx_data_n_189,u_ddr_cal_cplx_data_n_190,u_ddr_cal_cplx_data_n_191,u_ddr_cal_cplx_data_n_192,u_ddr_cal_cplx_data_n_193,u_ddr_cal_cplx_data_n_194,u_ddr_cal_cplx_data_n_195,u_ddr_cal_cplx_data_n_196,u_ddr_cal_cplx_data_n_197,u_ddr_cal_cplx_data_n_198,u_ddr_cal_cplx_data_n_199,u_ddr_cal_cplx_data_n_200,u_ddr_cal_cplx_data_n_201,u_ddr_cal_cplx_data_n_202,u_ddr_cal_cplx_data_n_203,u_ddr_cal_cplx_data_n_204,u_ddr_cal_cplx_data_n_205,u_ddr_cal_cplx_data_n_206,u_ddr_cal_cplx_data_n_207,u_ddr_cal_cplx_data_n_208,u_ddr_cal_cplx_data_n_209,u_ddr_cal_cplx_data_n_210,u_ddr_cal_cplx_data_n_211,u_ddr_cal_cplx_data_n_212,u_ddr_cal_cplx_data_n_213,u_ddr_cal_cplx_data_n_214,u_ddr_cal_cplx_data_n_215,u_ddr_cal_cplx_data_n_216,u_ddr_cal_cplx_data_n_217,u_ddr_cal_cplx_data_n_218,u_ddr_cal_cplx_data_n_219,u_ddr_cal_cplx_data_n_220,u_ddr_cal_cplx_data_n_221,u_ddr_cal_cplx_data_n_222,u_ddr_cal_cplx_data_n_223,u_ddr_cal_cplx_data_n_224,u_ddr_cal_cplx_data_n_225,u_ddr_cal_cplx_data_n_226,u_ddr_cal_cplx_data_n_227,u_ddr_cal_cplx_data_n_228,u_ddr_cal_cplx_data_n_229,u_ddr_cal_cplx_data_n_230,u_ddr_cal_cplx_data_n_231,u_ddr_cal_cplx_data_n_232,u_ddr_cal_cplx_data_n_233,u_ddr_cal_cplx_data_n_234,u_ddr_cal_cplx_data_n_235,u_ddr_cal_cplx_data_n_236,u_ddr_cal_cplx_data_n_237,u_ddr_cal_cplx_data_n_238,u_ddr_cal_cplx_data_n_239,u_ddr_cal_cplx_data_n_240,u_ddr_cal_cplx_data_n_241,u_ddr_cal_cplx_data_n_242,u_ddr_cal_cplx_data_n_243,u_ddr_cal_cplx_data_n_244,u_ddr_cal_cplx_data_n_245,u_ddr_cal_cplx_data_n_246,u_ddr_cal_cplx_data_n_247,u_ddr_cal_cplx_data_n_248,u_ddr_cal_cplx_data_n_249,u_ddr_cal_cplx_data_n_250,u_ddr_cal_cplx_data_n_251,u_ddr_cal_cplx_data_n_252,u_ddr_cal_cplx_data_n_253,u_ddr_cal_cplx_data_n_254,u_ddr_cal_cplx_data_n_255,u_ddr_cal_cplx_data_n_256,u_ddr_cal_cplx_data_n_257,u_ddr_cal_cplx_data_n_258,u_ddr_cal_cplx_data_n_259,u_ddr_cal_cplx_data_n_260,u_ddr_cal_cplx_data_n_261,u_ddr_cal_cplx_data_n_262,u_ddr_cal_cplx_data_n_263,u_ddr_cal_cplx_data_n_264,u_ddr_cal_cplx_data_n_265,u_ddr_cal_cplx_data_n_266,u_ddr_cal_cplx_data_n_267,u_ddr_cal_cplx_data_n_268,u_ddr_cal_cplx_data_n_269,u_ddr_cal_cplx_data_n_270,u_ddr_cal_cplx_data_n_271,u_ddr_cal_cplx_data_n_272,u_ddr_cal_cplx_data_n_273,u_ddr_cal_cplx_data_n_274,u_ddr_cal_cplx_data_n_275,u_ddr_cal_cplx_data_n_276,u_ddr_cal_cplx_data_n_277,u_ddr_cal_cplx_data_n_278,u_ddr_cal_cplx_data_n_279,u_ddr_cal_cplx_data_n_280,u_ddr_cal_cplx_data_n_281,u_ddr_cal_cplx_data_n_282,u_ddr_cal_cplx_data_n_283,u_ddr_cal_cplx_data_n_284,u_ddr_cal_cplx_data_n_285,u_ddr_cal_cplx_data_n_286,u_ddr_cal_cplx_data_n_287,u_ddr_cal_cplx_data_n_288,u_ddr_cal_cplx_data_n_289,u_ddr_cal_cplx_data_n_290,u_ddr_cal_cplx_data_n_291,u_ddr_cal_cplx_data_n_292,u_ddr_cal_cplx_data_n_293,u_ddr_cal_cplx_data_n_294,u_ddr_cal_cplx_data_n_295,u_ddr_cal_cplx_data_n_296,u_ddr_cal_cplx_data_n_297,u_ddr_cal_cplx_data_n_298,u_ddr_cal_cplx_data_n_299,u_ddr_cal_cplx_data_n_300,u_ddr_cal_cplx_data_n_301,u_ddr_cal_cplx_data_n_302,u_ddr_cal_cplx_data_n_303,u_ddr_cal_cplx_data_n_304,u_ddr_cal_cplx_data_n_305,u_ddr_cal_cplx_data_n_306,u_ddr_cal_cplx_data_n_307,u_ddr_cal_cplx_data_n_308,u_ddr_cal_cplx_data_n_309,u_ddr_cal_cplx_data_n_310,u_ddr_cal_cplx_data_n_311,u_ddr_cal_cplx_data_n_312,u_ddr_cal_cplx_data_n_313,u_ddr_cal_cplx_data_n_314,u_ddr_cal_cplx_data_n_315,u_ddr_cal_cplx_data_n_316,u_ddr_cal_cplx_data_n_317,u_ddr_cal_cplx_data_n_318,u_ddr_cal_cplx_data_n_319,u_ddr_cal_cplx_data_n_320,u_ddr_cal_cplx_data_n_321,u_ddr_cal_cplx_data_n_322,u_ddr_cal_cplx_data_n_323,u_ddr_cal_cplx_data_n_324,u_ddr_cal_cplx_data_n_325,u_ddr_cal_cplx_data_n_326,u_ddr_cal_cplx_data_n_327,u_ddr_cal_cplx_data_n_328,u_ddr_cal_cplx_data_n_329,u_ddr_cal_cplx_data_n_330,u_ddr_cal_cplx_data_n_331,u_ddr_cal_cplx_data_n_332,u_ddr_cal_cplx_data_n_333,u_ddr_cal_cplx_data_n_334,u_ddr_cal_cplx_data_n_335,u_ddr_cal_cplx_data_n_336,u_ddr_cal_cplx_data_n_337,u_ddr_cal_cplx_data_n_338,u_ddr_cal_cplx_data_n_339,u_ddr_cal_cplx_data_n_340,u_ddr_cal_cplx_data_n_341,u_ddr_cal_cplx_data_n_342,u_ddr_cal_cplx_data_n_343,u_ddr_cal_cplx_data_n_344,u_ddr_cal_cplx_data_n_345,u_ddr_cal_cplx_data_n_346,u_ddr_cal_cplx_data_n_347,u_ddr_cal_cplx_data_n_348,u_ddr_cal_cplx_data_n_349,u_ddr_cal_cplx_data_n_350,u_ddr_cal_cplx_data_n_351,u_ddr_cal_cplx_data_n_352,u_ddr_cal_cplx_data_n_353,u_ddr_cal_cplx_data_n_354,u_ddr_cal_cplx_data_n_355,u_ddr_cal_cplx_data_n_356,u_ddr_cal_cplx_data_n_357,u_ddr_cal_cplx_data_n_358,u_ddr_cal_cplx_data_n_359,u_ddr_cal_cplx_data_n_360,u_ddr_cal_cplx_data_n_361,u_ddr_cal_cplx_data_n_362,u_ddr_cal_cplx_data_n_363,u_ddr_cal_cplx_data_n_364,u_ddr_cal_cplx_data_n_365,u_ddr_cal_cplx_data_n_366,u_ddr_cal_cplx_data_n_367,u_ddr_cal_cplx_data_n_368,u_ddr_cal_cplx_data_n_369,u_ddr_cal_cplx_data_n_370,u_ddr_cal_cplx_data_n_371,u_ddr_cal_cplx_data_n_372,u_ddr_cal_cplx_data_n_373,u_ddr_cal_cplx_data_n_374,u_ddr_cal_cplx_data_n_375,u_ddr_cal_cplx_data_n_376,u_ddr_cal_cplx_data_n_377,u_ddr_cal_cplx_data_n_378,u_ddr_cal_cplx_data_n_379,u_ddr_cal_cplx_data_n_380,u_ddr_cal_cplx_data_n_381,u_ddr_cal_cplx_data_n_382,u_ddr_cal_cplx_data_n_383,u_ddr_cal_cplx_data_n_384,u_ddr_cal_cplx_data_n_385,u_ddr_cal_cplx_data_n_386,u_ddr_cal_cplx_data_n_387,u_ddr_cal_cplx_data_n_388,u_ddr_cal_cplx_data_n_389,u_ddr_cal_cplx_data_n_390,u_ddr_cal_cplx_data_n_391,u_ddr_cal_cplx_data_n_392,u_ddr_cal_cplx_data_n_393,u_ddr_cal_cplx_data_n_394,u_ddr_cal_cplx_data_n_395,u_ddr_cal_cplx_data_n_396,u_ddr_cal_cplx_data_n_397,u_ddr_cal_cplx_data_n_398,u_ddr_cal_cplx_data_n_399,u_ddr_cal_cplx_data_n_400,u_ddr_cal_cplx_data_n_401,u_ddr_cal_cplx_data_n_402,u_ddr_cal_cplx_data_n_403,u_ddr_cal_cplx_data_n_404,u_ddr_cal_cplx_data_n_405,u_ddr_cal_cplx_data_n_406,u_ddr_cal_cplx_data_n_407,u_ddr_cal_cplx_data_n_408,u_ddr_cal_cplx_data_n_409,u_ddr_cal_cplx_data_n_410,u_ddr_cal_cplx_data_n_411,u_ddr_cal_cplx_data_n_412,u_ddr_cal_cplx_data_n_413,u_ddr_cal_cplx_data_n_414,u_ddr_cal_cplx_data_n_415,u_ddr_cal_cplx_data_n_416,u_ddr_cal_cplx_data_n_417,u_ddr_cal_cplx_data_n_418,u_ddr_cal_cplx_data_n_419,u_ddr_cal_cplx_data_n_420,u_ddr_cal_cplx_data_n_421,u_ddr_cal_cplx_data_n_422,u_ddr_cal_cplx_data_n_423,u_ddr_cal_cplx_data_n_424,u_ddr_cal_cplx_data_n_425,u_ddr_cal_cplx_data_n_426,u_ddr_cal_cplx_data_n_427,u_ddr_cal_cplx_data_n_428,u_ddr_cal_cplx_data_n_429,u_ddr_cal_cplx_data_n_430,u_ddr_cal_cplx_data_n_431,u_ddr_cal_cplx_data_n_432,u_ddr_cal_cplx_data_n_433,u_ddr_cal_cplx_data_n_434,u_ddr_cal_cplx_data_n_435,u_ddr_cal_cplx_data_n_436,u_ddr_cal_cplx_data_n_437,u_ddr_cal_cplx_data_n_438,u_ddr_cal_cplx_data_n_439,u_ddr_cal_cplx_data_n_440,u_ddr_cal_cplx_data_n_441,u_ddr_cal_cplx_data_n_442,u_ddr_cal_cplx_data_n_443,u_ddr_cal_cplx_data_n_444,u_ddr_cal_cplx_data_n_445,u_ddr_cal_cplx_data_n_446,u_ddr_cal_cplx_data_n_447,u_ddr_cal_cplx_data_n_448,u_ddr_cal_cplx_data_n_449,u_ddr_cal_cplx_data_n_450,u_ddr_cal_cplx_data_n_451,u_ddr_cal_cplx_data_n_452,u_ddr_cal_cplx_data_n_453,u_ddr_cal_cplx_data_n_454,u_ddr_cal_cplx_data_n_455,u_ddr_cal_cplx_data_n_456,u_ddr_cal_cplx_data_n_457,u_ddr_cal_cplx_data_n_458,u_ddr_cal_cplx_data_n_459,u_ddr_cal_cplx_data_n_460,u_ddr_cal_cplx_data_n_461,u_ddr_cal_cplx_data_n_462,u_ddr_cal_cplx_data_n_463,u_ddr_cal_cplx_data_n_464,u_ddr_cal_cplx_data_n_465,u_ddr_cal_cplx_data_n_466,u_ddr_cal_cplx_data_n_467,u_ddr_cal_cplx_data_n_468,u_ddr_cal_cplx_data_n_469,u_ddr_cal_cplx_data_n_470,u_ddr_cal_cplx_data_n_471,u_ddr_cal_cplx_data_n_472,u_ddr_cal_cplx_data_n_473,u_ddr_cal_cplx_data_n_474,u_ddr_cal_cplx_data_n_475,u_ddr_cal_cplx_data_n_476,u_ddr_cal_cplx_data_n_477,u_ddr_cal_cplx_data_n_478,u_ddr_cal_cplx_data_n_479,u_ddr_cal_cplx_data_n_480,u_ddr_cal_cplx_data_n_481,u_ddr_cal_cplx_data_n_482,u_ddr_cal_cplx_data_n_483,u_ddr_cal_cplx_data_n_484,u_ddr_cal_cplx_data_n_485,u_ddr_cal_cplx_data_n_486,u_ddr_cal_cplx_data_n_487,u_ddr_cal_cplx_data_n_488,u_ddr_cal_cplx_data_n_489,u_ddr_cal_cplx_data_n_490,u_ddr_cal_cplx_data_n_491,u_ddr_cal_cplx_data_n_492,u_ddr_cal_cplx_data_n_493,u_ddr_cal_cplx_data_n_494,u_ddr_cal_cplx_data_n_495,u_ddr_cal_cplx_data_n_496,u_ddr_cal_cplx_data_n_497,u_ddr_cal_cplx_data_n_498,u_ddr_cal_cplx_data_n_499,u_ddr_cal_cplx_data_n_500,u_ddr_cal_cplx_data_n_501,u_ddr_cal_cplx_data_n_502,u_ddr_cal_cplx_data_n_503,u_ddr_cal_cplx_data_n_504,u_ddr_cal_cplx_data_n_505,u_ddr_cal_cplx_data_n_506,u_ddr_cal_cplx_data_n_507,u_ddr_cal_cplx_data_n_508,u_ddr_cal_cplx_data_n_509,u_ddr_cal_cplx_data_n_510,u_ddr_cal_cplx_data_n_511,u_ddr_cal_cplx_data_n_512,u_ddr_cal_cplx_data_n_513}),
        .Q(seq_state),
        .SR(outstanding_reads),
        .cas_uses_dm(cas_uses_dm),
        .cas_uses_dm_reg(cplx_DMOut_n0),
        .early_wrDataEn(early_wrDataEn),
        .out(out),
        .\outstanding_reads_reg[0] (u_ddr_cal_cplx_data_n_0),
        .rdDataEn_pi(rdDataEn_pi),
        .\rd_addr_101_reg[7]_0 (\rd_addr_101_reg[7] ),
        .rd_addr_101_reg_rep_0(cplx_data_byte_102),
        .rd_addr_101_reg_rep_1({\outstanding_reads_reg_n_0_[4] ,\outstanding_reads_reg_n_0_[3] ,\outstanding_reads_reg_n_0_[2] ,\outstanding_reads_reg_n_0_[1] ,\outstanding_reads_reg_n_0_[0] }),
        .\sel_reg[0]_0 (seq_row_reg),
        .\sel_reg[30]_0 (cplx_config_byte_select));
  LUT6 #(
    .INIT(64'hBABBBABBBABBBABA)) 
    wrCAS_i_1
       (.I0(cplx_issue_cas_wr),
        .I1(wrCAS_i_2_n_0),
        .I2(wrCAS_reg),
        .I3(wrCAS_i_3_n_0),
        .I4(extended_write_mode),
        .I5(D[0]),
        .O(cplx_issue_cas_wr_reg_0));
  LUT5 #(
    .INIT(32'hAAAAAABA)) 
    wrCAS_i_2
       (.I0(cplx_issue_cas_rd),
        .I1(D[1]),
        .I2(extended_write_mode),
        .I3(D[2]),
        .I4(wrCAS_reg_2),
        .O(wrCAS_i_2_n_0));
  LUT6 #(
    .INIT(64'h0101010001010101)) 
    wrCAS_i_3
       (.I0(wrCAS_reg_0),
        .I1(wrCAS_reg_1),
        .I2(rdCAS_reg_0),
        .I3(rdCAS_i_2_n_0),
        .I4(rdCAS_i_4_n_0),
        .I5(rdCAS_i_5_n_0),
        .O(wrCAS_i_3_n_0));
  FDRE \wr_cas_delay_line_ff_reg[1] 
       (.C(\rd_addr_101_reg[7] ),
        .CE(1'b1),
        .D(cplx_issue_cas_wr),
        .Q(early_wrDataEn),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_cplx_data" *) 
module ddr4_0_ddr4_v2_2_17_cal_cplx_data
   (\outstanding_reads_reg[0] ,
    SR,
    D,
    rd_addr_101_reg_rep_0,
    cas_uses_dm_reg,
    early_wrDataEn,
    Q,
    out,
    rd_addr_101_reg_rep_1,
    rdDataEn_pi,
    cas_uses_dm,
    \rd_addr_101_reg[7]_0 ,
    \sel_reg[0]_0 ,
    \sel_reg[30]_0 );
  output \outstanding_reads_reg[0] ;
  output [0:0]SR;
  output [511:0]D;
  output [63:0]rd_addr_101_reg_rep_0;
  output [7:0]cas_uses_dm_reg;
  input early_wrDataEn;
  input [3:0]Q;
  input out;
  input [4:0]rd_addr_101_reg_rep_1;
  input rdDataEn_pi;
  input cas_uses_dm;
  input \rd_addr_101_reg[7]_0 ;
  input [2:0]\sel_reg[0]_0 ;
  input [4:0]\sel_reg[30]_0 ;

  wire [511:0]D;
  wire [3:0]Q;
  wire [0:0]SR;
  wire cas_uses_dm;
  wire [7:0]cas_uses_dm_reg;
  wire \cplx_data_byte_103[56]_i_2_n_0 ;
  wire \cplx_data_byte_103[57]_i_2_n_0 ;
  wire \cplx_data_byte_103[58]_i_2_n_0 ;
  wire \cplx_data_byte_103[59]_i_2_n_0 ;
  wire \cplx_data_byte_103[60]_i_2_n_0 ;
  wire \cplx_data_byte_103[61]_i_2_n_0 ;
  wire \cplx_data_byte_103[62]_i_2_n_0 ;
  wire \cplx_data_byte_103[63]_i_2_n_0 ;
  wire early_wrDataEn;
  wire out;
  wire \outstanding_reads_reg[0] ;
  wire p_0_in;
  wire p_0_in1016_in;
  wire p_0_in101_in;
  wire p_0_in1034_in;
  wire p_0_in1052_in;
  wire p_0_in1070_in;
  wire p_0_in1088_in;
  wire p_0_in1106_in;
  wire p_0_in1124_in;
  wire p_0_in1142_in;
  wire p_0_in1160_in;
  wire p_0_in1178_in;
  wire p_0_in1196_in;
  wire p_0_in119_in;
  wire p_0_in1214_in;
  wire p_0_in1232_in;
  wire p_0_in1250_in;
  wire p_0_in1268_in;
  wire p_0_in1286_in;
  wire p_0_in137_in;
  wire p_0_in170_in;
  wire p_0_in188_in;
  wire p_0_in206_in;
  wire p_0_in224_in;
  wire p_0_in242_in;
  wire p_0_in260_in;
  wire p_0_in278_in;
  wire p_0_in296_in;
  wire p_0_in314_in;
  wire p_0_in332_in;
  wire p_0_in350_in;
  wire p_0_in368_in;
  wire p_0_in386_in;
  wire p_0_in404_in;
  wire p_0_in422_in;
  wire p_0_in440_in;
  wire p_0_in458_in;
  wire p_0_in476_in;
  wire p_0_in47_in;
  wire p_0_in494_in;
  wire p_0_in512_in;
  wire p_0_in530_in;
  wire p_0_in548_in;
  wire p_0_in566_in;
  wire p_0_in584_in;
  wire p_0_in602_in;
  wire p_0_in620_in;
  wire p_0_in638_in;
  wire p_0_in656_in;
  wire p_0_in65_in;
  wire p_0_in674_in;
  wire p_0_in692_in;
  wire p_0_in710_in;
  wire p_0_in728_in;
  wire p_0_in746_in;
  wire p_0_in764_in;
  wire p_0_in782_in;
  wire p_0_in800_in;
  wire p_0_in818_in;
  wire p_0_in836_in;
  wire p_0_in83_in;
  wire p_0_in854_in;
  wire p_0_in872_in;
  wire p_0_in890_in;
  wire p_0_in908_in;
  wire p_0_in926_in;
  wire p_0_in944_in;
  wire p_0_in962_in;
  wire p_0_in980_in;
  wire p_0_in998_in;
  wire p_1_in;
  wire p_1_in13_in;
  wire p_1_in17_in;
  wire p_1_in1_in;
  wire p_1_in21_in;
  wire p_1_in25_in;
  wire p_1_in5_in;
  wire p_1_in9_in;
  wire p_2_in;
  wire p_2_in11_in;
  wire p_2_in15_in;
  wire p_2_in19_in;
  wire p_2_in23_in;
  wire p_2_in3_in;
  wire p_2_in7_in;
  wire rdDataEn_pi;
  wire \rd_addr_101[0]_i_1_n_0 ;
  wire \rd_addr_101[1]_i_1_n_0 ;
  wire \rd_addr_101[2]_i_1_n_0 ;
  wire \rd_addr_101[3]_i_1_n_0 ;
  wire \rd_addr_101[4]_i_1_n_0 ;
  wire \rd_addr_101[5]_i_1_n_0 ;
  wire \rd_addr_101[6]_i_1_n_0 ;
  wire \rd_addr_101[7]_i_2_n_0 ;
  wire [7:0]rd_addr_101_reg;
  wire \rd_addr_101_reg[7]_0 ;
  wire [63:0]rd_addr_101_reg_rep_0;
  wire [4:0]rd_addr_101_reg_rep_1;
  wire rd_addr_101_reg_rep_i_1_n_0;
  wire rd_addr_101_reg_rep_i_2_n_0;
  wire rd_addr_101_reg_rep_i_3_n_0;
  wire rd_addr_101_reg_rep_i_4_n_0;
  wire rd_addr_101_reg_rep_i_5_n_0;
  wire rd_addr_101_reg_rep_i_6_n_0;
  wire rd_addr_101_reg_rep_i_7_n_0;
  wire rd_addr_101_reg_rep_i_8_n_0;
  wire rd_addr_101_reg_rep_i_9_n_0;
  wire rd_addr_101_reg_rep_n_47;
  wire \sel[0]_i_1_n_0 ;
  wire \sel[10]_i_1_n_0 ;
  wire \sel[11]_i_1_n_0 ;
  wire \sel[12]_i_1_n_0 ;
  wire \sel[13]_i_1_n_0 ;
  wire \sel[14]_i_1_n_0 ;
  wire \sel[15]_i_1_n_0 ;
  wire \sel[16]_i_1_n_0 ;
  wire \sel[17]_i_1_n_0 ;
  wire \sel[18]_i_1_n_0 ;
  wire \sel[19]_i_1_n_0 ;
  wire \sel[1]_i_1_n_0 ;
  wire \sel[20]_i_1_n_0 ;
  wire \sel[21]_i_1_n_0 ;
  wire \sel[22]_i_1_n_0 ;
  wire \sel[23]_i_1_n_0 ;
  wire \sel[24]_i_1_n_0 ;
  wire \sel[25]_i_1_n_0 ;
  wire \sel[26]_i_1_n_0 ;
  wire \sel[27]_i_1_n_0 ;
  wire \sel[28]_i_1_n_0 ;
  wire \sel[29]_i_1_n_0 ;
  wire \sel[2]_i_1_n_0 ;
  wire \sel[30]_i_1_n_0 ;
  wire \sel[30]_i_2_n_0 ;
  wire \sel[31]_i_1_n_0 ;
  wire \sel[31]_i_2_n_0 ;
  wire \sel[32]_i_1_n_0 ;
  wire \sel[33]_i_1_n_0 ;
  wire \sel[34]_i_1_n_0 ;
  wire \sel[35]_i_1_n_0 ;
  wire \sel[36]_i_1_n_0 ;
  wire \sel[37]_i_1_n_0 ;
  wire \sel[38]_i_1_n_0 ;
  wire \sel[39]_i_1_n_0 ;
  wire \sel[3]_i_1_n_0 ;
  wire \sel[40]_i_1_n_0 ;
  wire \sel[41]_i_1_n_0 ;
  wire \sel[42]_i_1_n_0 ;
  wire \sel[43]_i_1_n_0 ;
  wire \sel[44]_i_1_n_0 ;
  wire \sel[45]_i_1_n_0 ;
  wire \sel[46]_i_1_n_0 ;
  wire \sel[47]_i_1_n_0 ;
  wire \sel[48]_i_1_n_0 ;
  wire \sel[49]_i_1_n_0 ;
  wire \sel[4]_i_1_n_0 ;
  wire \sel[50]_i_1_n_0 ;
  wire \sel[51]_i_1_n_0 ;
  wire \sel[52]_i_1_n_0 ;
  wire \sel[53]_i_1_n_0 ;
  wire \sel[54]_i_1_n_0 ;
  wire \sel[55]_i_1_n_0 ;
  wire \sel[56]_i_1_n_0 ;
  wire \sel[57]_i_1_n_0 ;
  wire \sel[58]_i_1_n_0 ;
  wire \sel[59]_i_1_n_0 ;
  wire \sel[5]_i_1_n_0 ;
  wire \sel[60]_i_1_n_0 ;
  wire \sel[61]_i_1_n_0 ;
  wire \sel[62]_i_1_n_0 ;
  wire \sel[62]_i_2_n_0 ;
  wire \sel[63]_i_1_n_0 ;
  wire \sel[63]_i_2_n_0 ;
  wire \sel[6]_i_1_n_0 ;
  wire \sel[7]_i_1_n_0 ;
  wire \sel[8]_i_1_n_0 ;
  wire \sel[9]_i_1_n_0 ;
  wire [2:0]\sel_reg[0]_0 ;
  wire [4:0]\sel_reg[30]_0 ;
  wire \sel_reg_n_0_[0] ;
  wire \victim_bit_decode[0]_i_1_n_0 ;
  wire \victim_bit_decode[1]_i_1_n_0 ;
  wire \victim_bit_decode[2]_i_1_n_0 ;
  wire \victim_bit_decode[3]_i_1_n_0 ;
  wire \victim_bit_decode[4]_i_1_n_0 ;
  wire \victim_bit_decode[5]_i_1_n_0 ;
  wire \victim_bit_decode[6]_i_1_n_0 ;
  wire \victim_bit_decode[7]_i_1_n_0 ;
  wire \victim_bit_decode_reg_n_0_[0] ;
  wire [15:0]NLW_rd_addr_101_reg_rep_CASDOUTA_UNCONNECTED;
  wire [15:0]NLW_rd_addr_101_reg_rep_CASDOUTB_UNCONNECTED;
  wire [1:0]NLW_rd_addr_101_reg_rep_CASDOUTPA_UNCONNECTED;
  wire [1:0]NLW_rd_addr_101_reg_rep_CASDOUTPB_UNCONNECTED;
  wire [15:0]NLW_rd_addr_101_reg_rep_DOUTBDOUT_UNCONNECTED;
  wire [1:0]NLW_rd_addr_101_reg_rep_DOUTPADOUTP_UNCONNECTED;
  wire [1:0]NLW_rd_addr_101_reg_rep_DOUTPBDOUTP_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair247" *) 
  LUT4 #(
    .INIT(16'hE200)) 
    \cplx_DMOut_n[56]_i_1 
       (.I0(p_1_in1_in),
        .I1(\victim_bit_decode_reg_n_0_[0] ),
        .I2(p_2_in3_in),
        .I3(cas_uses_dm),
        .O(cas_uses_dm_reg[0]));
  (* SOFT_HLUTNM = "soft_lutpair243" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \cplx_DMOut_n[57]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in7_in),
        .O(cas_uses_dm_reg[1]));
  (* SOFT_HLUTNM = "soft_lutpair239" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \cplx_DMOut_n[58]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in11_in),
        .O(cas_uses_dm_reg[2]));
  (* SOFT_HLUTNM = "soft_lutpair235" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \cplx_DMOut_n[59]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in15_in),
        .O(cas_uses_dm_reg[3]));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \cplx_DMOut_n[60]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in19_in),
        .O(cas_uses_dm_reg[4]));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \cplx_DMOut_n[61]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in23_in),
        .O(cas_uses_dm_reg[5]));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \cplx_DMOut_n[62]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(cas_uses_dm_reg[6]));
  (* SOFT_HLUTNM = "soft_lutpair251" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \cplx_DMOut_n[63]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in),
        .O(cas_uses_dm_reg[7]));
  (* SOFT_HLUTNM = "soft_lutpair476" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[0]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(\sel_reg_n_0_[0] ),
        .I3(p_2_in),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair354" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[100]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in368_in),
        .I3(p_2_in15_in),
        .O(D[100]));
  (* SOFT_HLUTNM = "soft_lutpair322" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[101]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in368_in),
        .I3(p_2_in19_in),
        .O(D[101]));
  (* SOFT_HLUTNM = "soft_lutpair290" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[102]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in368_in),
        .I3(p_2_in23_in),
        .O(D[102]));
  (* SOFT_HLUTNM = "soft_lutpair258" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[103]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in368_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[103]));
  (* SOFT_HLUTNM = "soft_lutpair482" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[104]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in386_in),
        .I3(p_2_in),
        .O(D[104]));
  (* SOFT_HLUTNM = "soft_lutpair450" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[105]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in386_in),
        .I3(p_2_in3_in),
        .O(D[105]));
  (* SOFT_HLUTNM = "soft_lutpair418" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[106]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in386_in),
        .I3(p_2_in7_in),
        .O(D[106]));
  (* SOFT_HLUTNM = "soft_lutpair386" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[107]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in386_in),
        .I3(p_2_in11_in),
        .O(D[107]));
  (* SOFT_HLUTNM = "soft_lutpair354" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[108]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in386_in),
        .I3(p_2_in15_in),
        .O(D[108]));
  (* SOFT_HLUTNM = "soft_lutpair322" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[109]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in386_in),
        .I3(p_2_in19_in),
        .O(D[109]));
  (* SOFT_HLUTNM = "soft_lutpair412" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[10]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in170_in),
        .I3(p_2_in7_in),
        .O(D[10]));
  (* SOFT_HLUTNM = "soft_lutpair290" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[110]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in386_in),
        .I3(p_2_in23_in),
        .O(D[110]));
  (* SOFT_HLUTNM = "soft_lutpair258" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[111]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in386_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[111]));
  (* SOFT_HLUTNM = "soft_lutpair483" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[112]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in404_in),
        .I3(p_2_in),
        .O(D[112]));
  (* SOFT_HLUTNM = "soft_lutpair451" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[113]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in404_in),
        .I3(p_2_in3_in),
        .O(D[113]));
  (* SOFT_HLUTNM = "soft_lutpair419" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[114]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in404_in),
        .I3(p_2_in7_in),
        .O(D[114]));
  (* SOFT_HLUTNM = "soft_lutpair387" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[115]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in404_in),
        .I3(p_2_in11_in),
        .O(D[115]));
  (* SOFT_HLUTNM = "soft_lutpair355" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[116]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in404_in),
        .I3(p_2_in15_in),
        .O(D[116]));
  (* SOFT_HLUTNM = "soft_lutpair323" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[117]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in404_in),
        .I3(p_2_in19_in),
        .O(D[117]));
  (* SOFT_HLUTNM = "soft_lutpair291" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[118]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in404_in),
        .I3(p_2_in23_in),
        .O(D[118]));
  (* SOFT_HLUTNM = "soft_lutpair259" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[119]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in404_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[119]));
  (* SOFT_HLUTNM = "soft_lutpair380" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[11]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in170_in),
        .I3(p_2_in11_in),
        .O(D[11]));
  (* SOFT_HLUTNM = "soft_lutpair483" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[120]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in422_in),
        .I3(p_2_in),
        .O(D[120]));
  (* SOFT_HLUTNM = "soft_lutpair451" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[121]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in422_in),
        .I3(p_2_in3_in),
        .O(D[121]));
  (* SOFT_HLUTNM = "soft_lutpair419" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[122]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in422_in),
        .I3(p_2_in7_in),
        .O(D[122]));
  (* SOFT_HLUTNM = "soft_lutpair387" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[123]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in422_in),
        .I3(p_2_in11_in),
        .O(D[123]));
  (* SOFT_HLUTNM = "soft_lutpair355" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[124]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in422_in),
        .I3(p_2_in15_in),
        .O(D[124]));
  (* SOFT_HLUTNM = "soft_lutpair323" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[125]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in422_in),
        .I3(p_2_in19_in),
        .O(D[125]));
  (* SOFT_HLUTNM = "soft_lutpair291" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[126]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in422_in),
        .I3(p_2_in23_in),
        .O(D[126]));
  (* SOFT_HLUTNM = "soft_lutpair259" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[127]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in422_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[127]));
  (* SOFT_HLUTNM = "soft_lutpair484" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[128]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in440_in),
        .I3(p_2_in),
        .O(D[128]));
  (* SOFT_HLUTNM = "soft_lutpair452" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[129]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in440_in),
        .I3(p_2_in3_in),
        .O(D[129]));
  (* SOFT_HLUTNM = "soft_lutpair348" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[12]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in170_in),
        .I3(p_2_in15_in),
        .O(D[12]));
  (* SOFT_HLUTNM = "soft_lutpair420" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[130]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in440_in),
        .I3(p_2_in7_in),
        .O(D[130]));
  (* SOFT_HLUTNM = "soft_lutpair388" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[131]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in440_in),
        .I3(p_2_in11_in),
        .O(D[131]));
  (* SOFT_HLUTNM = "soft_lutpair356" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[132]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in440_in),
        .I3(p_2_in15_in),
        .O(D[132]));
  (* SOFT_HLUTNM = "soft_lutpair324" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[133]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in440_in),
        .I3(p_2_in19_in),
        .O(D[133]));
  (* SOFT_HLUTNM = "soft_lutpair292" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[134]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in440_in),
        .I3(p_2_in23_in),
        .O(D[134]));
  (* SOFT_HLUTNM = "soft_lutpair260" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[135]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in440_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[135]));
  (* SOFT_HLUTNM = "soft_lutpair484" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[136]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in458_in),
        .I3(p_2_in),
        .O(D[136]));
  (* SOFT_HLUTNM = "soft_lutpair452" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[137]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in458_in),
        .I3(p_2_in3_in),
        .O(D[137]));
  (* SOFT_HLUTNM = "soft_lutpair420" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[138]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in458_in),
        .I3(p_2_in7_in),
        .O(D[138]));
  (* SOFT_HLUTNM = "soft_lutpair388" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[139]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in458_in),
        .I3(p_2_in11_in),
        .O(D[139]));
  (* SOFT_HLUTNM = "soft_lutpair316" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[13]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in170_in),
        .I3(p_2_in19_in),
        .O(D[13]));
  (* SOFT_HLUTNM = "soft_lutpair356" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[140]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in458_in),
        .I3(p_2_in15_in),
        .O(D[140]));
  (* SOFT_HLUTNM = "soft_lutpair324" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[141]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in458_in),
        .I3(p_2_in19_in),
        .O(D[141]));
  (* SOFT_HLUTNM = "soft_lutpair292" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[142]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in458_in),
        .I3(p_2_in23_in),
        .O(D[142]));
  (* SOFT_HLUTNM = "soft_lutpair260" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[143]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in458_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[143]));
  (* SOFT_HLUTNM = "soft_lutpair485" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[144]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in476_in),
        .I3(p_2_in),
        .O(D[144]));
  (* SOFT_HLUTNM = "soft_lutpair453" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[145]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in476_in),
        .I3(p_2_in3_in),
        .O(D[145]));
  (* SOFT_HLUTNM = "soft_lutpair421" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[146]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in476_in),
        .I3(p_2_in7_in),
        .O(D[146]));
  (* SOFT_HLUTNM = "soft_lutpair389" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[147]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in476_in),
        .I3(p_2_in11_in),
        .O(D[147]));
  (* SOFT_HLUTNM = "soft_lutpair357" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[148]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in476_in),
        .I3(p_2_in15_in),
        .O(D[148]));
  (* SOFT_HLUTNM = "soft_lutpair325" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[149]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in476_in),
        .I3(p_2_in19_in),
        .O(D[149]));
  (* SOFT_HLUTNM = "soft_lutpair284" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[14]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in170_in),
        .I3(p_2_in23_in),
        .O(D[14]));
  (* SOFT_HLUTNM = "soft_lutpair293" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[150]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in476_in),
        .I3(p_2_in23_in),
        .O(D[150]));
  (* SOFT_HLUTNM = "soft_lutpair261" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[151]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in476_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[151]));
  (* SOFT_HLUTNM = "soft_lutpair485" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[152]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in494_in),
        .I3(p_2_in),
        .O(D[152]));
  (* SOFT_HLUTNM = "soft_lutpair453" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[153]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in494_in),
        .I3(p_2_in3_in),
        .O(D[153]));
  (* SOFT_HLUTNM = "soft_lutpair421" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[154]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in494_in),
        .I3(p_2_in7_in),
        .O(D[154]));
  (* SOFT_HLUTNM = "soft_lutpair389" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[155]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in494_in),
        .I3(p_2_in11_in),
        .O(D[155]));
  (* SOFT_HLUTNM = "soft_lutpair357" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[156]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in494_in),
        .I3(p_2_in15_in),
        .O(D[156]));
  (* SOFT_HLUTNM = "soft_lutpair325" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[157]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in494_in),
        .I3(p_2_in19_in),
        .O(D[157]));
  (* SOFT_HLUTNM = "soft_lutpair293" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[158]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in494_in),
        .I3(p_2_in23_in),
        .O(D[158]));
  (* SOFT_HLUTNM = "soft_lutpair261" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[159]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in494_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[159]));
  (* SOFT_HLUTNM = "soft_lutpair252" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[15]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in170_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[15]));
  (* SOFT_HLUTNM = "soft_lutpair486" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[160]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in512_in),
        .I3(p_2_in),
        .O(D[160]));
  (* SOFT_HLUTNM = "soft_lutpair454" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[161]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in512_in),
        .I3(p_2_in3_in),
        .O(D[161]));
  (* SOFT_HLUTNM = "soft_lutpair422" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[162]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in512_in),
        .I3(p_2_in7_in),
        .O(D[162]));
  (* SOFT_HLUTNM = "soft_lutpair390" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[163]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in512_in),
        .I3(p_2_in11_in),
        .O(D[163]));
  (* SOFT_HLUTNM = "soft_lutpair358" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[164]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in512_in),
        .I3(p_2_in15_in),
        .O(D[164]));
  (* SOFT_HLUTNM = "soft_lutpair326" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[165]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in512_in),
        .I3(p_2_in19_in),
        .O(D[165]));
  (* SOFT_HLUTNM = "soft_lutpair294" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[166]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in512_in),
        .I3(p_2_in23_in),
        .O(D[166]));
  (* SOFT_HLUTNM = "soft_lutpair262" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[167]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in512_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[167]));
  (* SOFT_HLUTNM = "soft_lutpair486" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[168]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in530_in),
        .I3(p_2_in),
        .O(D[168]));
  (* SOFT_HLUTNM = "soft_lutpair454" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[169]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in530_in),
        .I3(p_2_in3_in),
        .O(D[169]));
  (* SOFT_HLUTNM = "soft_lutpair477" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[16]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in188_in),
        .I3(p_2_in),
        .O(D[16]));
  (* SOFT_HLUTNM = "soft_lutpair422" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[170]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in530_in),
        .I3(p_2_in7_in),
        .O(D[170]));
  (* SOFT_HLUTNM = "soft_lutpair390" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[171]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in530_in),
        .I3(p_2_in11_in),
        .O(D[171]));
  (* SOFT_HLUTNM = "soft_lutpair358" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[172]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in530_in),
        .I3(p_2_in15_in),
        .O(D[172]));
  (* SOFT_HLUTNM = "soft_lutpair326" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[173]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in530_in),
        .I3(p_2_in19_in),
        .O(D[173]));
  (* SOFT_HLUTNM = "soft_lutpair294" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[174]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in530_in),
        .I3(p_2_in23_in),
        .O(D[174]));
  (* SOFT_HLUTNM = "soft_lutpair262" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[175]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in530_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[175]));
  (* SOFT_HLUTNM = "soft_lutpair487" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[176]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in548_in),
        .I3(p_2_in),
        .O(D[176]));
  (* SOFT_HLUTNM = "soft_lutpair455" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[177]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in548_in),
        .I3(p_2_in3_in),
        .O(D[177]));
  (* SOFT_HLUTNM = "soft_lutpair423" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[178]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in548_in),
        .I3(p_2_in7_in),
        .O(D[178]));
  (* SOFT_HLUTNM = "soft_lutpair391" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[179]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in548_in),
        .I3(p_2_in11_in),
        .O(D[179]));
  (* SOFT_HLUTNM = "soft_lutpair445" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[17]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in188_in),
        .I3(p_2_in3_in),
        .O(D[17]));
  (* SOFT_HLUTNM = "soft_lutpair359" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[180]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in548_in),
        .I3(p_2_in15_in),
        .O(D[180]));
  (* SOFT_HLUTNM = "soft_lutpair327" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[181]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in548_in),
        .I3(p_2_in19_in),
        .O(D[181]));
  (* SOFT_HLUTNM = "soft_lutpair295" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[182]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in548_in),
        .I3(p_2_in23_in),
        .O(D[182]));
  (* SOFT_HLUTNM = "soft_lutpair263" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[183]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in548_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[183]));
  (* SOFT_HLUTNM = "soft_lutpair487" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[184]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in566_in),
        .I3(p_2_in),
        .O(D[184]));
  (* SOFT_HLUTNM = "soft_lutpair455" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[185]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in566_in),
        .I3(p_2_in3_in),
        .O(D[185]));
  (* SOFT_HLUTNM = "soft_lutpair423" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[186]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in566_in),
        .I3(p_2_in7_in),
        .O(D[186]));
  (* SOFT_HLUTNM = "soft_lutpair391" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[187]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in566_in),
        .I3(p_2_in11_in),
        .O(D[187]));
  (* SOFT_HLUTNM = "soft_lutpair359" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[188]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in566_in),
        .I3(p_2_in15_in),
        .O(D[188]));
  (* SOFT_HLUTNM = "soft_lutpair327" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[189]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in566_in),
        .I3(p_2_in19_in),
        .O(D[189]));
  (* SOFT_HLUTNM = "soft_lutpair413" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[18]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in188_in),
        .I3(p_2_in7_in),
        .O(D[18]));
  (* SOFT_HLUTNM = "soft_lutpair295" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[190]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in566_in),
        .I3(p_2_in23_in),
        .O(D[190]));
  (* SOFT_HLUTNM = "soft_lutpair263" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[191]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in566_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[191]));
  (* SOFT_HLUTNM = "soft_lutpair488" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[192]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in584_in),
        .I3(p_2_in),
        .O(D[192]));
  (* SOFT_HLUTNM = "soft_lutpair456" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[193]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in584_in),
        .I3(p_2_in3_in),
        .O(D[193]));
  (* SOFT_HLUTNM = "soft_lutpair424" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[194]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in584_in),
        .I3(p_2_in7_in),
        .O(D[194]));
  (* SOFT_HLUTNM = "soft_lutpair392" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[195]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in584_in),
        .I3(p_2_in11_in),
        .O(D[195]));
  (* SOFT_HLUTNM = "soft_lutpair360" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[196]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in584_in),
        .I3(p_2_in15_in),
        .O(D[196]));
  (* SOFT_HLUTNM = "soft_lutpair328" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[197]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in584_in),
        .I3(p_2_in19_in),
        .O(D[197]));
  (* SOFT_HLUTNM = "soft_lutpair296" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[198]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in584_in),
        .I3(p_2_in23_in),
        .O(D[198]));
  (* SOFT_HLUTNM = "soft_lutpair264" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[199]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in584_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[199]));
  (* SOFT_HLUTNM = "soft_lutpair381" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[19]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in188_in),
        .I3(p_2_in11_in),
        .O(D[19]));
  (* SOFT_HLUTNM = "soft_lutpair444" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[1]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(\sel_reg_n_0_[0] ),
        .I3(p_2_in3_in),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair488" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[200]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in602_in),
        .I3(p_2_in),
        .O(D[200]));
  (* SOFT_HLUTNM = "soft_lutpair456" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[201]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in602_in),
        .I3(p_2_in3_in),
        .O(D[201]));
  (* SOFT_HLUTNM = "soft_lutpair424" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[202]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in602_in),
        .I3(p_2_in7_in),
        .O(D[202]));
  (* SOFT_HLUTNM = "soft_lutpair392" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[203]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in602_in),
        .I3(p_2_in11_in),
        .O(D[203]));
  (* SOFT_HLUTNM = "soft_lutpair360" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[204]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in602_in),
        .I3(p_2_in15_in),
        .O(D[204]));
  (* SOFT_HLUTNM = "soft_lutpair328" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[205]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in602_in),
        .I3(p_2_in19_in),
        .O(D[205]));
  (* SOFT_HLUTNM = "soft_lutpair296" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[206]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in602_in),
        .I3(p_2_in23_in),
        .O(D[206]));
  (* SOFT_HLUTNM = "soft_lutpair264" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[207]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in602_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[207]));
  (* SOFT_HLUTNM = "soft_lutpair489" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[208]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in620_in),
        .I3(p_2_in),
        .O(D[208]));
  (* SOFT_HLUTNM = "soft_lutpair457" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[209]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in620_in),
        .I3(p_2_in3_in),
        .O(D[209]));
  (* SOFT_HLUTNM = "soft_lutpair349" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[20]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in188_in),
        .I3(p_2_in15_in),
        .O(D[20]));
  (* SOFT_HLUTNM = "soft_lutpair425" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[210]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in620_in),
        .I3(p_2_in7_in),
        .O(D[210]));
  (* SOFT_HLUTNM = "soft_lutpair393" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[211]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in620_in),
        .I3(p_2_in11_in),
        .O(D[211]));
  (* SOFT_HLUTNM = "soft_lutpair361" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[212]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in620_in),
        .I3(p_2_in15_in),
        .O(D[212]));
  (* SOFT_HLUTNM = "soft_lutpair329" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[213]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in620_in),
        .I3(p_2_in19_in),
        .O(D[213]));
  (* SOFT_HLUTNM = "soft_lutpair297" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[214]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in620_in),
        .I3(p_2_in23_in),
        .O(D[214]));
  (* SOFT_HLUTNM = "soft_lutpair265" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[215]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in620_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[215]));
  (* SOFT_HLUTNM = "soft_lutpair489" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[216]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in638_in),
        .I3(p_2_in),
        .O(D[216]));
  (* SOFT_HLUTNM = "soft_lutpair457" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[217]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in638_in),
        .I3(p_2_in3_in),
        .O(D[217]));
  (* SOFT_HLUTNM = "soft_lutpair425" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[218]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in638_in),
        .I3(p_2_in7_in),
        .O(D[218]));
  (* SOFT_HLUTNM = "soft_lutpair393" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[219]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in638_in),
        .I3(p_2_in11_in),
        .O(D[219]));
  (* SOFT_HLUTNM = "soft_lutpair317" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[21]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in188_in),
        .I3(p_2_in19_in),
        .O(D[21]));
  (* SOFT_HLUTNM = "soft_lutpair361" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[220]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in638_in),
        .I3(p_2_in15_in),
        .O(D[220]));
  (* SOFT_HLUTNM = "soft_lutpair329" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[221]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in638_in),
        .I3(p_2_in19_in),
        .O(D[221]));
  (* SOFT_HLUTNM = "soft_lutpair297" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[222]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in638_in),
        .I3(p_2_in23_in),
        .O(D[222]));
  (* SOFT_HLUTNM = "soft_lutpair265" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[223]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in638_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[223]));
  (* SOFT_HLUTNM = "soft_lutpair490" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[224]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in656_in),
        .I3(p_2_in),
        .O(D[224]));
  (* SOFT_HLUTNM = "soft_lutpair458" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[225]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in656_in),
        .I3(p_2_in3_in),
        .O(D[225]));
  (* SOFT_HLUTNM = "soft_lutpair426" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[226]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in656_in),
        .I3(p_2_in7_in),
        .O(D[226]));
  (* SOFT_HLUTNM = "soft_lutpair394" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[227]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in656_in),
        .I3(p_2_in11_in),
        .O(D[227]));
  (* SOFT_HLUTNM = "soft_lutpair362" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[228]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in656_in),
        .I3(p_2_in15_in),
        .O(D[228]));
  (* SOFT_HLUTNM = "soft_lutpair330" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[229]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in656_in),
        .I3(p_2_in19_in),
        .O(D[229]));
  (* SOFT_HLUTNM = "soft_lutpair285" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[22]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in188_in),
        .I3(p_2_in23_in),
        .O(D[22]));
  (* SOFT_HLUTNM = "soft_lutpair298" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[230]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in656_in),
        .I3(p_2_in23_in),
        .O(D[230]));
  (* SOFT_HLUTNM = "soft_lutpair266" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[231]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in656_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[231]));
  (* SOFT_HLUTNM = "soft_lutpair490" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[232]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in674_in),
        .I3(p_2_in),
        .O(D[232]));
  (* SOFT_HLUTNM = "soft_lutpair458" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[233]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in674_in),
        .I3(p_2_in3_in),
        .O(D[233]));
  (* SOFT_HLUTNM = "soft_lutpair426" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[234]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in674_in),
        .I3(p_2_in7_in),
        .O(D[234]));
  (* SOFT_HLUTNM = "soft_lutpair394" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[235]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in674_in),
        .I3(p_2_in11_in),
        .O(D[235]));
  (* SOFT_HLUTNM = "soft_lutpair362" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[236]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in674_in),
        .I3(p_2_in15_in),
        .O(D[236]));
  (* SOFT_HLUTNM = "soft_lutpair330" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[237]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in674_in),
        .I3(p_2_in19_in),
        .O(D[237]));
  (* SOFT_HLUTNM = "soft_lutpair298" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[238]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in674_in),
        .I3(p_2_in23_in),
        .O(D[238]));
  (* SOFT_HLUTNM = "soft_lutpair266" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[239]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in674_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[239]));
  (* SOFT_HLUTNM = "soft_lutpair253" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[23]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in188_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[23]));
  (* SOFT_HLUTNM = "soft_lutpair491" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[240]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in692_in),
        .I3(p_2_in),
        .O(D[240]));
  (* SOFT_HLUTNM = "soft_lutpair459" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[241]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in692_in),
        .I3(p_2_in3_in),
        .O(D[241]));
  (* SOFT_HLUTNM = "soft_lutpair427" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[242]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in692_in),
        .I3(p_2_in7_in),
        .O(D[242]));
  (* SOFT_HLUTNM = "soft_lutpair395" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[243]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in692_in),
        .I3(p_2_in11_in),
        .O(D[243]));
  (* SOFT_HLUTNM = "soft_lutpair363" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[244]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in692_in),
        .I3(p_2_in15_in),
        .O(D[244]));
  (* SOFT_HLUTNM = "soft_lutpair331" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[245]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in692_in),
        .I3(p_2_in19_in),
        .O(D[245]));
  (* SOFT_HLUTNM = "soft_lutpair299" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[246]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in692_in),
        .I3(p_2_in23_in),
        .O(D[246]));
  (* SOFT_HLUTNM = "soft_lutpair267" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[247]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in692_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[247]));
  (* SOFT_HLUTNM = "soft_lutpair491" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[248]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in710_in),
        .I3(p_2_in),
        .O(D[248]));
  (* SOFT_HLUTNM = "soft_lutpair459" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[249]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in710_in),
        .I3(p_2_in3_in),
        .O(D[249]));
  (* SOFT_HLUTNM = "soft_lutpair477" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[24]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in206_in),
        .I3(p_2_in),
        .O(D[24]));
  (* SOFT_HLUTNM = "soft_lutpair427" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[250]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in710_in),
        .I3(p_2_in7_in),
        .O(D[250]));
  (* SOFT_HLUTNM = "soft_lutpair395" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[251]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in710_in),
        .I3(p_2_in11_in),
        .O(D[251]));
  (* SOFT_HLUTNM = "soft_lutpair363" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[252]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in710_in),
        .I3(p_2_in15_in),
        .O(D[252]));
  (* SOFT_HLUTNM = "soft_lutpair331" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[253]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in710_in),
        .I3(p_2_in19_in),
        .O(D[253]));
  (* SOFT_HLUTNM = "soft_lutpair299" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[254]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in710_in),
        .I3(p_2_in23_in),
        .O(D[254]));
  (* SOFT_HLUTNM = "soft_lutpair267" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[255]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in710_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[255]));
  (* SOFT_HLUTNM = "soft_lutpair492" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[256]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in728_in),
        .I3(p_2_in),
        .O(D[256]));
  (* SOFT_HLUTNM = "soft_lutpair460" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[257]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in728_in),
        .I3(p_2_in3_in),
        .O(D[257]));
  (* SOFT_HLUTNM = "soft_lutpair428" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[258]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in728_in),
        .I3(p_2_in7_in),
        .O(D[258]));
  (* SOFT_HLUTNM = "soft_lutpair396" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[259]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in728_in),
        .I3(p_2_in11_in),
        .O(D[259]));
  (* SOFT_HLUTNM = "soft_lutpair445" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[25]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in206_in),
        .I3(p_2_in3_in),
        .O(D[25]));
  (* SOFT_HLUTNM = "soft_lutpair364" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[260]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in728_in),
        .I3(p_2_in15_in),
        .O(D[260]));
  (* SOFT_HLUTNM = "soft_lutpair332" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[261]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in728_in),
        .I3(p_2_in19_in),
        .O(D[261]));
  (* SOFT_HLUTNM = "soft_lutpair300" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[262]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in728_in),
        .I3(p_2_in23_in),
        .O(D[262]));
  (* SOFT_HLUTNM = "soft_lutpair268" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[263]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in728_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[263]));
  (* SOFT_HLUTNM = "soft_lutpair492" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[264]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in746_in),
        .I3(p_2_in),
        .O(D[264]));
  (* SOFT_HLUTNM = "soft_lutpair460" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[265]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in746_in),
        .I3(p_2_in3_in),
        .O(D[265]));
  (* SOFT_HLUTNM = "soft_lutpair428" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[266]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in746_in),
        .I3(p_2_in7_in),
        .O(D[266]));
  (* SOFT_HLUTNM = "soft_lutpair396" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[267]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in746_in),
        .I3(p_2_in11_in),
        .O(D[267]));
  (* SOFT_HLUTNM = "soft_lutpair364" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[268]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in746_in),
        .I3(p_2_in15_in),
        .O(D[268]));
  (* SOFT_HLUTNM = "soft_lutpair332" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[269]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in746_in),
        .I3(p_2_in19_in),
        .O(D[269]));
  (* SOFT_HLUTNM = "soft_lutpair413" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[26]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in206_in),
        .I3(p_2_in7_in),
        .O(D[26]));
  (* SOFT_HLUTNM = "soft_lutpair300" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[270]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in746_in),
        .I3(p_2_in23_in),
        .O(D[270]));
  (* SOFT_HLUTNM = "soft_lutpair268" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[271]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in746_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[271]));
  (* SOFT_HLUTNM = "soft_lutpair493" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[272]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in764_in),
        .I3(p_2_in),
        .O(D[272]));
  (* SOFT_HLUTNM = "soft_lutpair461" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[273]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in764_in),
        .I3(p_2_in3_in),
        .O(D[273]));
  (* SOFT_HLUTNM = "soft_lutpair429" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[274]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in764_in),
        .I3(p_2_in7_in),
        .O(D[274]));
  (* SOFT_HLUTNM = "soft_lutpair397" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[275]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in764_in),
        .I3(p_2_in11_in),
        .O(D[275]));
  (* SOFT_HLUTNM = "soft_lutpair365" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[276]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in764_in),
        .I3(p_2_in15_in),
        .O(D[276]));
  (* SOFT_HLUTNM = "soft_lutpair333" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[277]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in764_in),
        .I3(p_2_in19_in),
        .O(D[277]));
  (* SOFT_HLUTNM = "soft_lutpair301" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[278]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in764_in),
        .I3(p_2_in23_in),
        .O(D[278]));
  (* SOFT_HLUTNM = "soft_lutpair269" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[279]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in764_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[279]));
  (* SOFT_HLUTNM = "soft_lutpair381" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[27]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in206_in),
        .I3(p_2_in11_in),
        .O(D[27]));
  (* SOFT_HLUTNM = "soft_lutpair493" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[280]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in782_in),
        .I3(p_2_in),
        .O(D[280]));
  (* SOFT_HLUTNM = "soft_lutpair461" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[281]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in782_in),
        .I3(p_2_in3_in),
        .O(D[281]));
  (* SOFT_HLUTNM = "soft_lutpair429" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[282]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in782_in),
        .I3(p_2_in7_in),
        .O(D[282]));
  (* SOFT_HLUTNM = "soft_lutpair397" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[283]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in782_in),
        .I3(p_2_in11_in),
        .O(D[283]));
  (* SOFT_HLUTNM = "soft_lutpair365" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[284]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in782_in),
        .I3(p_2_in15_in),
        .O(D[284]));
  (* SOFT_HLUTNM = "soft_lutpair333" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[285]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in782_in),
        .I3(p_2_in19_in),
        .O(D[285]));
  (* SOFT_HLUTNM = "soft_lutpair301" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[286]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in782_in),
        .I3(p_2_in23_in),
        .O(D[286]));
  (* SOFT_HLUTNM = "soft_lutpair269" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[287]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in782_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[287]));
  (* SOFT_HLUTNM = "soft_lutpair494" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[288]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in800_in),
        .I3(p_2_in),
        .O(D[288]));
  (* SOFT_HLUTNM = "soft_lutpair462" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[289]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in800_in),
        .I3(p_2_in3_in),
        .O(D[289]));
  (* SOFT_HLUTNM = "soft_lutpair349" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[28]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in206_in),
        .I3(p_2_in15_in),
        .O(D[28]));
  (* SOFT_HLUTNM = "soft_lutpair430" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[290]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in800_in),
        .I3(p_2_in7_in),
        .O(D[290]));
  (* SOFT_HLUTNM = "soft_lutpair398" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[291]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in800_in),
        .I3(p_2_in11_in),
        .O(D[291]));
  (* SOFT_HLUTNM = "soft_lutpair366" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[292]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in800_in),
        .I3(p_2_in15_in),
        .O(D[292]));
  (* SOFT_HLUTNM = "soft_lutpair334" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[293]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in800_in),
        .I3(p_2_in19_in),
        .O(D[293]));
  (* SOFT_HLUTNM = "soft_lutpair302" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[294]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in800_in),
        .I3(p_2_in23_in),
        .O(D[294]));
  (* SOFT_HLUTNM = "soft_lutpair270" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[295]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in800_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[295]));
  (* SOFT_HLUTNM = "soft_lutpair494" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[296]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in818_in),
        .I3(p_2_in),
        .O(D[296]));
  (* SOFT_HLUTNM = "soft_lutpair462" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[297]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in818_in),
        .I3(p_2_in3_in),
        .O(D[297]));
  (* SOFT_HLUTNM = "soft_lutpair430" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[298]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in818_in),
        .I3(p_2_in7_in),
        .O(D[298]));
  (* SOFT_HLUTNM = "soft_lutpair398" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[299]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in818_in),
        .I3(p_2_in11_in),
        .O(D[299]));
  (* SOFT_HLUTNM = "soft_lutpair317" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[29]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in206_in),
        .I3(p_2_in19_in),
        .O(D[29]));
  (* SOFT_HLUTNM = "soft_lutpair412" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[2]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(\sel_reg_n_0_[0] ),
        .I3(p_2_in7_in),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair366" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[300]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in818_in),
        .I3(p_2_in15_in),
        .O(D[300]));
  (* SOFT_HLUTNM = "soft_lutpair334" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[301]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in818_in),
        .I3(p_2_in19_in),
        .O(D[301]));
  (* SOFT_HLUTNM = "soft_lutpair302" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[302]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in818_in),
        .I3(p_2_in23_in),
        .O(D[302]));
  (* SOFT_HLUTNM = "soft_lutpair270" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[303]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in818_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[303]));
  (* SOFT_HLUTNM = "soft_lutpair495" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[304]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in836_in),
        .I3(p_2_in),
        .O(D[304]));
  (* SOFT_HLUTNM = "soft_lutpair463" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[305]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in836_in),
        .I3(p_2_in3_in),
        .O(D[305]));
  (* SOFT_HLUTNM = "soft_lutpair431" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[306]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in836_in),
        .I3(p_2_in7_in),
        .O(D[306]));
  (* SOFT_HLUTNM = "soft_lutpair399" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[307]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in836_in),
        .I3(p_2_in11_in),
        .O(D[307]));
  (* SOFT_HLUTNM = "soft_lutpair367" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[308]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in836_in),
        .I3(p_2_in15_in),
        .O(D[308]));
  (* SOFT_HLUTNM = "soft_lutpair335" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[309]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in836_in),
        .I3(p_2_in19_in),
        .O(D[309]));
  (* SOFT_HLUTNM = "soft_lutpair285" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[30]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in206_in),
        .I3(p_2_in23_in),
        .O(D[30]));
  (* SOFT_HLUTNM = "soft_lutpair303" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[310]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in836_in),
        .I3(p_2_in23_in),
        .O(D[310]));
  (* SOFT_HLUTNM = "soft_lutpair271" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[311]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in836_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[311]));
  (* SOFT_HLUTNM = "soft_lutpair495" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[312]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in854_in),
        .I3(p_2_in),
        .O(D[312]));
  (* SOFT_HLUTNM = "soft_lutpair463" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[313]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in854_in),
        .I3(p_2_in3_in),
        .O(D[313]));
  (* SOFT_HLUTNM = "soft_lutpair431" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[314]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in854_in),
        .I3(p_2_in7_in),
        .O(D[314]));
  (* SOFT_HLUTNM = "soft_lutpair399" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[315]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in854_in),
        .I3(p_2_in11_in),
        .O(D[315]));
  (* SOFT_HLUTNM = "soft_lutpair367" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[316]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in854_in),
        .I3(p_2_in15_in),
        .O(D[316]));
  (* SOFT_HLUTNM = "soft_lutpair335" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[317]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in854_in),
        .I3(p_2_in19_in),
        .O(D[317]));
  (* SOFT_HLUTNM = "soft_lutpair303" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[318]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in854_in),
        .I3(p_2_in23_in),
        .O(D[318]));
  (* SOFT_HLUTNM = "soft_lutpair271" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[319]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in854_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[319]));
  (* SOFT_HLUTNM = "soft_lutpair253" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[31]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in206_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[31]));
  (* SOFT_HLUTNM = "soft_lutpair496" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[320]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in872_in),
        .I3(p_2_in),
        .O(D[320]));
  (* SOFT_HLUTNM = "soft_lutpair464" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[321]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in872_in),
        .I3(p_2_in3_in),
        .O(D[321]));
  (* SOFT_HLUTNM = "soft_lutpair432" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[322]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in872_in),
        .I3(p_2_in7_in),
        .O(D[322]));
  (* SOFT_HLUTNM = "soft_lutpair400" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[323]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in872_in),
        .I3(p_2_in11_in),
        .O(D[323]));
  (* SOFT_HLUTNM = "soft_lutpair368" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[324]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in872_in),
        .I3(p_2_in15_in),
        .O(D[324]));
  (* SOFT_HLUTNM = "soft_lutpair336" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[325]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in872_in),
        .I3(p_2_in19_in),
        .O(D[325]));
  (* SOFT_HLUTNM = "soft_lutpair304" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[326]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in872_in),
        .I3(p_2_in23_in),
        .O(D[326]));
  (* SOFT_HLUTNM = "soft_lutpair272" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[327]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in872_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[327]));
  (* SOFT_HLUTNM = "soft_lutpair496" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[328]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in890_in),
        .I3(p_2_in),
        .O(D[328]));
  (* SOFT_HLUTNM = "soft_lutpair464" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[329]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in890_in),
        .I3(p_2_in3_in),
        .O(D[329]));
  (* SOFT_HLUTNM = "soft_lutpair478" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[32]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in224_in),
        .I3(p_2_in),
        .O(D[32]));
  (* SOFT_HLUTNM = "soft_lutpair432" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[330]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in890_in),
        .I3(p_2_in7_in),
        .O(D[330]));
  (* SOFT_HLUTNM = "soft_lutpair400" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[331]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in890_in),
        .I3(p_2_in11_in),
        .O(D[331]));
  (* SOFT_HLUTNM = "soft_lutpair368" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[332]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in890_in),
        .I3(p_2_in15_in),
        .O(D[332]));
  (* SOFT_HLUTNM = "soft_lutpair336" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[333]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in890_in),
        .I3(p_2_in19_in),
        .O(D[333]));
  (* SOFT_HLUTNM = "soft_lutpair304" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[334]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in890_in),
        .I3(p_2_in23_in),
        .O(D[334]));
  (* SOFT_HLUTNM = "soft_lutpair272" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[335]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in890_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[335]));
  (* SOFT_HLUTNM = "soft_lutpair497" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[336]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in908_in),
        .I3(p_2_in),
        .O(D[336]));
  (* SOFT_HLUTNM = "soft_lutpair465" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[337]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in908_in),
        .I3(p_2_in3_in),
        .O(D[337]));
  (* SOFT_HLUTNM = "soft_lutpair433" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[338]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in908_in),
        .I3(p_2_in7_in),
        .O(D[338]));
  (* SOFT_HLUTNM = "soft_lutpair401" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[339]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in908_in),
        .I3(p_2_in11_in),
        .O(D[339]));
  (* SOFT_HLUTNM = "soft_lutpair446" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[33]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in224_in),
        .I3(p_2_in3_in),
        .O(D[33]));
  (* SOFT_HLUTNM = "soft_lutpair369" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[340]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in908_in),
        .I3(p_2_in15_in),
        .O(D[340]));
  (* SOFT_HLUTNM = "soft_lutpair337" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[341]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in908_in),
        .I3(p_2_in19_in),
        .O(D[341]));
  (* SOFT_HLUTNM = "soft_lutpair305" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[342]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in908_in),
        .I3(p_2_in23_in),
        .O(D[342]));
  (* SOFT_HLUTNM = "soft_lutpair273" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[343]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in908_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[343]));
  (* SOFT_HLUTNM = "soft_lutpair497" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[344]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in926_in),
        .I3(p_2_in),
        .O(D[344]));
  (* SOFT_HLUTNM = "soft_lutpair465" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[345]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in926_in),
        .I3(p_2_in3_in),
        .O(D[345]));
  (* SOFT_HLUTNM = "soft_lutpair433" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[346]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in926_in),
        .I3(p_2_in7_in),
        .O(D[346]));
  (* SOFT_HLUTNM = "soft_lutpair401" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[347]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in926_in),
        .I3(p_2_in11_in),
        .O(D[347]));
  (* SOFT_HLUTNM = "soft_lutpair369" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[348]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in926_in),
        .I3(p_2_in15_in),
        .O(D[348]));
  (* SOFT_HLUTNM = "soft_lutpair337" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[349]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in926_in),
        .I3(p_2_in19_in),
        .O(D[349]));
  (* SOFT_HLUTNM = "soft_lutpair414" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[34]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in224_in),
        .I3(p_2_in7_in),
        .O(D[34]));
  (* SOFT_HLUTNM = "soft_lutpair305" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[350]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in926_in),
        .I3(p_2_in23_in),
        .O(D[350]));
  (* SOFT_HLUTNM = "soft_lutpair273" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[351]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in926_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[351]));
  (* SOFT_HLUTNM = "soft_lutpair498" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[352]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in944_in),
        .I3(p_2_in),
        .O(D[352]));
  (* SOFT_HLUTNM = "soft_lutpair466" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[353]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in944_in),
        .I3(p_2_in3_in),
        .O(D[353]));
  (* SOFT_HLUTNM = "soft_lutpair434" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[354]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in944_in),
        .I3(p_2_in7_in),
        .O(D[354]));
  (* SOFT_HLUTNM = "soft_lutpair402" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[355]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in944_in),
        .I3(p_2_in11_in),
        .O(D[355]));
  (* SOFT_HLUTNM = "soft_lutpair370" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[356]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in944_in),
        .I3(p_2_in15_in),
        .O(D[356]));
  (* SOFT_HLUTNM = "soft_lutpair338" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[357]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in944_in),
        .I3(p_2_in19_in),
        .O(D[357]));
  (* SOFT_HLUTNM = "soft_lutpair306" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[358]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in944_in),
        .I3(p_2_in23_in),
        .O(D[358]));
  (* SOFT_HLUTNM = "soft_lutpair274" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[359]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in944_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[359]));
  (* SOFT_HLUTNM = "soft_lutpair382" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[35]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in224_in),
        .I3(p_2_in11_in),
        .O(D[35]));
  (* SOFT_HLUTNM = "soft_lutpair498" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[360]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in962_in),
        .I3(p_2_in),
        .O(D[360]));
  (* SOFT_HLUTNM = "soft_lutpair466" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[361]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in962_in),
        .I3(p_2_in3_in),
        .O(D[361]));
  (* SOFT_HLUTNM = "soft_lutpair434" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[362]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in962_in),
        .I3(p_2_in7_in),
        .O(D[362]));
  (* SOFT_HLUTNM = "soft_lutpair402" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[363]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in962_in),
        .I3(p_2_in11_in),
        .O(D[363]));
  (* SOFT_HLUTNM = "soft_lutpair370" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[364]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in962_in),
        .I3(p_2_in15_in),
        .O(D[364]));
  (* SOFT_HLUTNM = "soft_lutpair338" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[365]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in962_in),
        .I3(p_2_in19_in),
        .O(D[365]));
  (* SOFT_HLUTNM = "soft_lutpair306" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[366]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in962_in),
        .I3(p_2_in23_in),
        .O(D[366]));
  (* SOFT_HLUTNM = "soft_lutpair274" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[367]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in962_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[367]));
  (* SOFT_HLUTNM = "soft_lutpair499" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[368]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in980_in),
        .I3(p_2_in),
        .O(D[368]));
  (* SOFT_HLUTNM = "soft_lutpair467" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[369]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in980_in),
        .I3(p_2_in3_in),
        .O(D[369]));
  (* SOFT_HLUTNM = "soft_lutpair350" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[36]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in224_in),
        .I3(p_2_in15_in),
        .O(D[36]));
  (* SOFT_HLUTNM = "soft_lutpair435" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[370]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in980_in),
        .I3(p_2_in7_in),
        .O(D[370]));
  (* SOFT_HLUTNM = "soft_lutpair403" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[371]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in980_in),
        .I3(p_2_in11_in),
        .O(D[371]));
  (* SOFT_HLUTNM = "soft_lutpair371" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[372]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in980_in),
        .I3(p_2_in15_in),
        .O(D[372]));
  (* SOFT_HLUTNM = "soft_lutpair339" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[373]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in980_in),
        .I3(p_2_in19_in),
        .O(D[373]));
  (* SOFT_HLUTNM = "soft_lutpair307" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[374]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in980_in),
        .I3(p_2_in23_in),
        .O(D[374]));
  (* SOFT_HLUTNM = "soft_lutpair275" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[375]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in980_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[375]));
  (* SOFT_HLUTNM = "soft_lutpair499" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[376]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in998_in),
        .I3(p_2_in),
        .O(D[376]));
  (* SOFT_HLUTNM = "soft_lutpair467" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[377]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in998_in),
        .I3(p_2_in3_in),
        .O(D[377]));
  (* SOFT_HLUTNM = "soft_lutpair435" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[378]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in998_in),
        .I3(p_2_in7_in),
        .O(D[378]));
  (* SOFT_HLUTNM = "soft_lutpair403" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[379]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in998_in),
        .I3(p_2_in11_in),
        .O(D[379]));
  (* SOFT_HLUTNM = "soft_lutpair318" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[37]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in224_in),
        .I3(p_2_in19_in),
        .O(D[37]));
  (* SOFT_HLUTNM = "soft_lutpair371" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[380]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in998_in),
        .I3(p_2_in15_in),
        .O(D[380]));
  (* SOFT_HLUTNM = "soft_lutpair339" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[381]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in998_in),
        .I3(p_2_in19_in),
        .O(D[381]));
  (* SOFT_HLUTNM = "soft_lutpair307" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[382]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in998_in),
        .I3(p_2_in23_in),
        .O(D[382]));
  (* SOFT_HLUTNM = "soft_lutpair275" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[383]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in998_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[383]));
  (* SOFT_HLUTNM = "soft_lutpair500" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[384]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1016_in),
        .I3(p_2_in),
        .O(D[384]));
  (* SOFT_HLUTNM = "soft_lutpair468" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[385]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1016_in),
        .I3(p_2_in3_in),
        .O(D[385]));
  (* SOFT_HLUTNM = "soft_lutpair436" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[386]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1016_in),
        .I3(p_2_in7_in),
        .O(D[386]));
  (* SOFT_HLUTNM = "soft_lutpair404" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[387]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1016_in),
        .I3(p_2_in11_in),
        .O(D[387]));
  (* SOFT_HLUTNM = "soft_lutpair372" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[388]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1016_in),
        .I3(p_2_in15_in),
        .O(D[388]));
  (* SOFT_HLUTNM = "soft_lutpair340" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[389]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1016_in),
        .I3(p_2_in19_in),
        .O(D[389]));
  (* SOFT_HLUTNM = "soft_lutpair286" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[38]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in224_in),
        .I3(p_2_in23_in),
        .O(D[38]));
  (* SOFT_HLUTNM = "soft_lutpair308" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[390]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1016_in),
        .I3(p_2_in23_in),
        .O(D[390]));
  (* SOFT_HLUTNM = "soft_lutpair276" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[391]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1016_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[391]));
  (* SOFT_HLUTNM = "soft_lutpair500" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[392]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1034_in),
        .I3(p_2_in),
        .O(D[392]));
  (* SOFT_HLUTNM = "soft_lutpair468" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[393]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1034_in),
        .I3(p_2_in3_in),
        .O(D[393]));
  (* SOFT_HLUTNM = "soft_lutpair436" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[394]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1034_in),
        .I3(p_2_in7_in),
        .O(D[394]));
  (* SOFT_HLUTNM = "soft_lutpair404" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[395]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1034_in),
        .I3(p_2_in11_in),
        .O(D[395]));
  (* SOFT_HLUTNM = "soft_lutpair372" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[396]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1034_in),
        .I3(p_2_in15_in),
        .O(D[396]));
  (* SOFT_HLUTNM = "soft_lutpair340" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[397]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1034_in),
        .I3(p_2_in19_in),
        .O(D[397]));
  (* SOFT_HLUTNM = "soft_lutpair308" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[398]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1034_in),
        .I3(p_2_in23_in),
        .O(D[398]));
  (* SOFT_HLUTNM = "soft_lutpair276" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[399]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1034_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[399]));
  (* SOFT_HLUTNM = "soft_lutpair254" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[39]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in224_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[39]));
  (* SOFT_HLUTNM = "soft_lutpair380" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[3]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(\sel_reg_n_0_[0] ),
        .I3(p_2_in11_in),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair501" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[400]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1052_in),
        .I3(p_2_in),
        .O(D[400]));
  (* SOFT_HLUTNM = "soft_lutpair469" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[401]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1052_in),
        .I3(p_2_in3_in),
        .O(D[401]));
  (* SOFT_HLUTNM = "soft_lutpair437" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[402]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1052_in),
        .I3(p_2_in7_in),
        .O(D[402]));
  (* SOFT_HLUTNM = "soft_lutpair405" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[403]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1052_in),
        .I3(p_2_in11_in),
        .O(D[403]));
  (* SOFT_HLUTNM = "soft_lutpair373" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[404]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1052_in),
        .I3(p_2_in15_in),
        .O(D[404]));
  (* SOFT_HLUTNM = "soft_lutpair341" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[405]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1052_in),
        .I3(p_2_in19_in),
        .O(D[405]));
  (* SOFT_HLUTNM = "soft_lutpair309" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[406]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1052_in),
        .I3(p_2_in23_in),
        .O(D[406]));
  (* SOFT_HLUTNM = "soft_lutpair277" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[407]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1052_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[407]));
  (* SOFT_HLUTNM = "soft_lutpair501" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[408]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1070_in),
        .I3(p_2_in),
        .O(D[408]));
  (* SOFT_HLUTNM = "soft_lutpair469" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[409]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1070_in),
        .I3(p_2_in3_in),
        .O(D[409]));
  (* SOFT_HLUTNM = "soft_lutpair478" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[40]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in242_in),
        .I3(p_2_in),
        .O(D[40]));
  (* SOFT_HLUTNM = "soft_lutpair437" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[410]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1070_in),
        .I3(p_2_in7_in),
        .O(D[410]));
  (* SOFT_HLUTNM = "soft_lutpair405" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[411]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1070_in),
        .I3(p_2_in11_in),
        .O(D[411]));
  (* SOFT_HLUTNM = "soft_lutpair373" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[412]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1070_in),
        .I3(p_2_in15_in),
        .O(D[412]));
  (* SOFT_HLUTNM = "soft_lutpair341" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[413]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1070_in),
        .I3(p_2_in19_in),
        .O(D[413]));
  (* SOFT_HLUTNM = "soft_lutpair309" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[414]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1070_in),
        .I3(p_2_in23_in),
        .O(D[414]));
  (* SOFT_HLUTNM = "soft_lutpair277" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[415]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1070_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[415]));
  (* SOFT_HLUTNM = "soft_lutpair502" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[416]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1088_in),
        .I3(p_2_in),
        .O(D[416]));
  (* SOFT_HLUTNM = "soft_lutpair470" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[417]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1088_in),
        .I3(p_2_in3_in),
        .O(D[417]));
  (* SOFT_HLUTNM = "soft_lutpair438" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[418]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1088_in),
        .I3(p_2_in7_in),
        .O(D[418]));
  (* SOFT_HLUTNM = "soft_lutpair406" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[419]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1088_in),
        .I3(p_2_in11_in),
        .O(D[419]));
  (* SOFT_HLUTNM = "soft_lutpair446" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[41]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in242_in),
        .I3(p_2_in3_in),
        .O(D[41]));
  (* SOFT_HLUTNM = "soft_lutpair374" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[420]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1088_in),
        .I3(p_2_in15_in),
        .O(D[420]));
  (* SOFT_HLUTNM = "soft_lutpair342" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[421]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1088_in),
        .I3(p_2_in19_in),
        .O(D[421]));
  (* SOFT_HLUTNM = "soft_lutpair310" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[422]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1088_in),
        .I3(p_2_in23_in),
        .O(D[422]));
  (* SOFT_HLUTNM = "soft_lutpair278" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[423]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1088_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[423]));
  (* SOFT_HLUTNM = "soft_lutpair502" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[424]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1106_in),
        .I3(p_2_in),
        .O(D[424]));
  (* SOFT_HLUTNM = "soft_lutpair470" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[425]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1106_in),
        .I3(p_2_in3_in),
        .O(D[425]));
  (* SOFT_HLUTNM = "soft_lutpair438" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[426]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1106_in),
        .I3(p_2_in7_in),
        .O(D[426]));
  (* SOFT_HLUTNM = "soft_lutpair406" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[427]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1106_in),
        .I3(p_2_in11_in),
        .O(D[427]));
  (* SOFT_HLUTNM = "soft_lutpair374" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[428]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1106_in),
        .I3(p_2_in15_in),
        .O(D[428]));
  (* SOFT_HLUTNM = "soft_lutpair342" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[429]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1106_in),
        .I3(p_2_in19_in),
        .O(D[429]));
  (* SOFT_HLUTNM = "soft_lutpair414" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[42]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in242_in),
        .I3(p_2_in7_in),
        .O(D[42]));
  (* SOFT_HLUTNM = "soft_lutpair310" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[430]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1106_in),
        .I3(p_2_in23_in),
        .O(D[430]));
  (* SOFT_HLUTNM = "soft_lutpair278" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[431]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1106_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[431]));
  (* SOFT_HLUTNM = "soft_lutpair503" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[432]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1124_in),
        .I3(p_2_in),
        .O(D[432]));
  (* SOFT_HLUTNM = "soft_lutpair471" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[433]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1124_in),
        .I3(p_2_in3_in),
        .O(D[433]));
  (* SOFT_HLUTNM = "soft_lutpair439" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[434]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1124_in),
        .I3(p_2_in7_in),
        .O(D[434]));
  (* SOFT_HLUTNM = "soft_lutpair407" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[435]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1124_in),
        .I3(p_2_in11_in),
        .O(D[435]));
  (* SOFT_HLUTNM = "soft_lutpair375" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[436]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1124_in),
        .I3(p_2_in15_in),
        .O(D[436]));
  (* SOFT_HLUTNM = "soft_lutpair343" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[437]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1124_in),
        .I3(p_2_in19_in),
        .O(D[437]));
  (* SOFT_HLUTNM = "soft_lutpair311" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[438]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1124_in),
        .I3(p_2_in23_in),
        .O(D[438]));
  (* SOFT_HLUTNM = "soft_lutpair279" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[439]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1124_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[439]));
  (* SOFT_HLUTNM = "soft_lutpair382" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[43]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in242_in),
        .I3(p_2_in11_in),
        .O(D[43]));
  (* SOFT_HLUTNM = "soft_lutpair503" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[440]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1142_in),
        .I3(p_2_in),
        .O(D[440]));
  (* SOFT_HLUTNM = "soft_lutpair471" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[441]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1142_in),
        .I3(p_2_in3_in),
        .O(D[441]));
  (* SOFT_HLUTNM = "soft_lutpair439" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[442]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1142_in),
        .I3(p_2_in7_in),
        .O(D[442]));
  (* SOFT_HLUTNM = "soft_lutpair407" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[443]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1142_in),
        .I3(p_2_in11_in),
        .O(D[443]));
  (* SOFT_HLUTNM = "soft_lutpair375" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[444]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1142_in),
        .I3(p_2_in15_in),
        .O(D[444]));
  (* SOFT_HLUTNM = "soft_lutpair343" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[445]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1142_in),
        .I3(p_2_in19_in),
        .O(D[445]));
  (* SOFT_HLUTNM = "soft_lutpair311" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[446]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1142_in),
        .I3(p_2_in23_in),
        .O(D[446]));
  (* SOFT_HLUTNM = "soft_lutpair279" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[447]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1142_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[447]));
  (* SOFT_HLUTNM = "soft_lutpair504" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[448]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1160_in),
        .I3(p_2_in),
        .O(D[448]));
  (* SOFT_HLUTNM = "soft_lutpair472" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[449]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1160_in),
        .I3(p_2_in3_in),
        .O(D[449]));
  (* SOFT_HLUTNM = "soft_lutpair350" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[44]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in242_in),
        .I3(p_2_in15_in),
        .O(D[44]));
  (* SOFT_HLUTNM = "soft_lutpair440" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[450]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1160_in),
        .I3(p_2_in7_in),
        .O(D[450]));
  (* SOFT_HLUTNM = "soft_lutpair408" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[451]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1160_in),
        .I3(p_2_in11_in),
        .O(D[451]));
  (* SOFT_HLUTNM = "soft_lutpair376" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[452]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1160_in),
        .I3(p_2_in15_in),
        .O(D[452]));
  (* SOFT_HLUTNM = "soft_lutpair344" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[453]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1160_in),
        .I3(p_2_in19_in),
        .O(D[453]));
  (* SOFT_HLUTNM = "soft_lutpair312" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[454]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1160_in),
        .I3(p_2_in23_in),
        .O(D[454]));
  (* SOFT_HLUTNM = "soft_lutpair280" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[455]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1160_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[455]));
  (* SOFT_HLUTNM = "soft_lutpair504" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[456]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1178_in),
        .I3(p_2_in),
        .O(D[456]));
  (* SOFT_HLUTNM = "soft_lutpair472" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[457]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1178_in),
        .I3(p_2_in3_in),
        .O(D[457]));
  (* SOFT_HLUTNM = "soft_lutpair440" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[458]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1178_in),
        .I3(p_2_in7_in),
        .O(D[458]));
  (* SOFT_HLUTNM = "soft_lutpair408" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[459]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1178_in),
        .I3(p_2_in11_in),
        .O(D[459]));
  (* SOFT_HLUTNM = "soft_lutpair318" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[45]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in242_in),
        .I3(p_2_in19_in),
        .O(D[45]));
  (* SOFT_HLUTNM = "soft_lutpair376" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[460]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1178_in),
        .I3(p_2_in15_in),
        .O(D[460]));
  (* SOFT_HLUTNM = "soft_lutpair344" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[461]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1178_in),
        .I3(p_2_in19_in),
        .O(D[461]));
  (* SOFT_HLUTNM = "soft_lutpair312" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[462]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1178_in),
        .I3(p_2_in23_in),
        .O(D[462]));
  (* SOFT_HLUTNM = "soft_lutpair280" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[463]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1178_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[463]));
  (* SOFT_HLUTNM = "soft_lutpair505" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[464]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1196_in),
        .I3(p_2_in),
        .O(D[464]));
  (* SOFT_HLUTNM = "soft_lutpair473" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[465]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1196_in),
        .I3(p_2_in3_in),
        .O(D[465]));
  (* SOFT_HLUTNM = "soft_lutpair441" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[466]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1196_in),
        .I3(p_2_in7_in),
        .O(D[466]));
  (* SOFT_HLUTNM = "soft_lutpair409" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[467]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1196_in),
        .I3(p_2_in11_in),
        .O(D[467]));
  (* SOFT_HLUTNM = "soft_lutpair377" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[468]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1196_in),
        .I3(p_2_in15_in),
        .O(D[468]));
  (* SOFT_HLUTNM = "soft_lutpair345" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[469]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1196_in),
        .I3(p_2_in19_in),
        .O(D[469]));
  (* SOFT_HLUTNM = "soft_lutpair286" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[46]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in242_in),
        .I3(p_2_in23_in),
        .O(D[46]));
  (* SOFT_HLUTNM = "soft_lutpair313" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[470]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1196_in),
        .I3(p_2_in23_in),
        .O(D[470]));
  (* SOFT_HLUTNM = "soft_lutpair281" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[471]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1196_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[471]));
  (* SOFT_HLUTNM = "soft_lutpair505" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[472]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1214_in),
        .I3(p_2_in),
        .O(D[472]));
  (* SOFT_HLUTNM = "soft_lutpair473" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[473]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1214_in),
        .I3(p_2_in3_in),
        .O(D[473]));
  (* SOFT_HLUTNM = "soft_lutpair441" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[474]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1214_in),
        .I3(p_2_in7_in),
        .O(D[474]));
  (* SOFT_HLUTNM = "soft_lutpair409" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[475]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1214_in),
        .I3(p_2_in11_in),
        .O(D[475]));
  (* SOFT_HLUTNM = "soft_lutpair377" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[476]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1214_in),
        .I3(p_2_in15_in),
        .O(D[476]));
  (* SOFT_HLUTNM = "soft_lutpair345" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[477]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1214_in),
        .I3(p_2_in19_in),
        .O(D[477]));
  (* SOFT_HLUTNM = "soft_lutpair313" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[478]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1214_in),
        .I3(p_2_in23_in),
        .O(D[478]));
  (* SOFT_HLUTNM = "soft_lutpair281" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[479]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1214_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[479]));
  (* SOFT_HLUTNM = "soft_lutpair254" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[47]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in242_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[47]));
  (* SOFT_HLUTNM = "soft_lutpair506" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[480]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1232_in),
        .I3(p_2_in),
        .O(D[480]));
  (* SOFT_HLUTNM = "soft_lutpair474" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[481]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1232_in),
        .I3(p_2_in3_in),
        .O(D[481]));
  (* SOFT_HLUTNM = "soft_lutpair442" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[482]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1232_in),
        .I3(p_2_in7_in),
        .O(D[482]));
  (* SOFT_HLUTNM = "soft_lutpair410" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[483]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1232_in),
        .I3(p_2_in11_in),
        .O(D[483]));
  (* SOFT_HLUTNM = "soft_lutpair378" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[484]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1232_in),
        .I3(p_2_in15_in),
        .O(D[484]));
  (* SOFT_HLUTNM = "soft_lutpair346" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[485]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1232_in),
        .I3(p_2_in19_in),
        .O(D[485]));
  (* SOFT_HLUTNM = "soft_lutpair314" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[486]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1232_in),
        .I3(p_2_in23_in),
        .O(D[486]));
  (* SOFT_HLUTNM = "soft_lutpair282" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[487]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1232_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[487]));
  (* SOFT_HLUTNM = "soft_lutpair506" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[488]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1250_in),
        .I3(p_2_in),
        .O(D[488]));
  (* SOFT_HLUTNM = "soft_lutpair474" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[489]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1250_in),
        .I3(p_2_in3_in),
        .O(D[489]));
  (* SOFT_HLUTNM = "soft_lutpair479" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[48]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in260_in),
        .I3(p_2_in),
        .O(D[48]));
  (* SOFT_HLUTNM = "soft_lutpair442" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[490]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1250_in),
        .I3(p_2_in7_in),
        .O(D[490]));
  (* SOFT_HLUTNM = "soft_lutpair410" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[491]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1250_in),
        .I3(p_2_in11_in),
        .O(D[491]));
  (* SOFT_HLUTNM = "soft_lutpair378" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[492]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1250_in),
        .I3(p_2_in15_in),
        .O(D[492]));
  (* SOFT_HLUTNM = "soft_lutpair346" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[493]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1250_in),
        .I3(p_2_in19_in),
        .O(D[493]));
  (* SOFT_HLUTNM = "soft_lutpair314" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[494]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1250_in),
        .I3(p_2_in23_in),
        .O(D[494]));
  (* SOFT_HLUTNM = "soft_lutpair282" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[495]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1250_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[495]));
  (* SOFT_HLUTNM = "soft_lutpair507" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[496]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1268_in),
        .I3(p_2_in),
        .O(D[496]));
  (* SOFT_HLUTNM = "soft_lutpair475" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[497]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1268_in),
        .I3(p_2_in3_in),
        .O(D[497]));
  (* SOFT_HLUTNM = "soft_lutpair443" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[498]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1268_in),
        .I3(p_2_in7_in),
        .O(D[498]));
  (* SOFT_HLUTNM = "soft_lutpair411" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[499]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1268_in),
        .I3(p_2_in11_in),
        .O(D[499]));
  (* SOFT_HLUTNM = "soft_lutpair447" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[49]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in260_in),
        .I3(p_2_in3_in),
        .O(D[49]));
  (* SOFT_HLUTNM = "soft_lutpair348" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[4]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(\sel_reg_n_0_[0] ),
        .I3(p_2_in15_in),
        .O(D[4]));
  (* SOFT_HLUTNM = "soft_lutpair379" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[500]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1268_in),
        .I3(p_2_in15_in),
        .O(D[500]));
  (* SOFT_HLUTNM = "soft_lutpair347" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[501]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1268_in),
        .I3(p_2_in19_in),
        .O(D[501]));
  (* SOFT_HLUTNM = "soft_lutpair315" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[502]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1268_in),
        .I3(p_2_in23_in),
        .O(D[502]));
  (* SOFT_HLUTNM = "soft_lutpair283" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[503]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1268_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[503]));
  (* SOFT_HLUTNM = "soft_lutpair507" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[504]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in1286_in),
        .I3(p_2_in),
        .O(D[504]));
  (* SOFT_HLUTNM = "soft_lutpair475" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[505]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in1286_in),
        .I3(p_2_in3_in),
        .O(D[505]));
  (* SOFT_HLUTNM = "soft_lutpair443" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[506]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in1286_in),
        .I3(p_2_in7_in),
        .O(D[506]));
  (* SOFT_HLUTNM = "soft_lutpair411" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[507]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in1286_in),
        .I3(p_2_in11_in),
        .O(D[507]));
  (* SOFT_HLUTNM = "soft_lutpair379" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[508]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in1286_in),
        .I3(p_2_in15_in),
        .O(D[508]));
  (* SOFT_HLUTNM = "soft_lutpair347" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[509]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in1286_in),
        .I3(p_2_in19_in),
        .O(D[509]));
  (* SOFT_HLUTNM = "soft_lutpair415" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[50]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in260_in),
        .I3(p_2_in7_in),
        .O(D[50]));
  (* SOFT_HLUTNM = "soft_lutpair315" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[510]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in1286_in),
        .I3(p_2_in23_in),
        .O(D[510]));
  (* SOFT_HLUTNM = "soft_lutpair283" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[511]_i_2 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in1286_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[511]));
  (* SOFT_HLUTNM = "soft_lutpair383" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[51]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in260_in),
        .I3(p_2_in11_in),
        .O(D[51]));
  (* SOFT_HLUTNM = "soft_lutpair351" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[52]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in260_in),
        .I3(p_2_in15_in),
        .O(D[52]));
  (* SOFT_HLUTNM = "soft_lutpair319" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[53]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in260_in),
        .I3(p_2_in19_in),
        .O(D[53]));
  (* SOFT_HLUTNM = "soft_lutpair287" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[54]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in260_in),
        .I3(p_2_in23_in),
        .O(D[54]));
  (* SOFT_HLUTNM = "soft_lutpair255" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[55]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in260_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[55]));
  (* SOFT_HLUTNM = "soft_lutpair479" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[56]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in278_in),
        .I3(p_2_in),
        .O(D[56]));
  (* SOFT_HLUTNM = "soft_lutpair447" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[57]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in278_in),
        .I3(p_2_in3_in),
        .O(D[57]));
  (* SOFT_HLUTNM = "soft_lutpair415" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[58]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in278_in),
        .I3(p_2_in7_in),
        .O(D[58]));
  (* SOFT_HLUTNM = "soft_lutpair383" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[59]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in278_in),
        .I3(p_2_in11_in),
        .O(D[59]));
  (* SOFT_HLUTNM = "soft_lutpair316" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[5]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(\sel_reg_n_0_[0] ),
        .I3(p_2_in19_in),
        .O(D[5]));
  (* SOFT_HLUTNM = "soft_lutpair351" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[60]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in278_in),
        .I3(p_2_in15_in),
        .O(D[60]));
  (* SOFT_HLUTNM = "soft_lutpair319" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[61]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in278_in),
        .I3(p_2_in19_in),
        .O(D[61]));
  (* SOFT_HLUTNM = "soft_lutpair287" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[62]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in278_in),
        .I3(p_2_in23_in),
        .O(D[62]));
  (* SOFT_HLUTNM = "soft_lutpair255" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[63]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in278_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[63]));
  (* SOFT_HLUTNM = "soft_lutpair480" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[64]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in296_in),
        .I3(p_2_in),
        .O(D[64]));
  (* SOFT_HLUTNM = "soft_lutpair448" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[65]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in296_in),
        .I3(p_2_in3_in),
        .O(D[65]));
  (* SOFT_HLUTNM = "soft_lutpair416" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[66]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in296_in),
        .I3(p_2_in7_in),
        .O(D[66]));
  (* SOFT_HLUTNM = "soft_lutpair384" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[67]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in296_in),
        .I3(p_2_in11_in),
        .O(D[67]));
  (* SOFT_HLUTNM = "soft_lutpair352" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[68]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in296_in),
        .I3(p_2_in15_in),
        .O(D[68]));
  (* SOFT_HLUTNM = "soft_lutpair320" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[69]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in296_in),
        .I3(p_2_in19_in),
        .O(D[69]));
  (* SOFT_HLUTNM = "soft_lutpair284" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[6]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(\sel_reg_n_0_[0] ),
        .I3(p_2_in23_in),
        .O(D[6]));
  (* SOFT_HLUTNM = "soft_lutpair288" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[70]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in296_in),
        .I3(p_2_in23_in),
        .O(D[70]));
  (* SOFT_HLUTNM = "soft_lutpair256" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[71]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in296_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[71]));
  (* SOFT_HLUTNM = "soft_lutpair480" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[72]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in314_in),
        .I3(p_2_in),
        .O(D[72]));
  (* SOFT_HLUTNM = "soft_lutpair448" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[73]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in314_in),
        .I3(p_2_in3_in),
        .O(D[73]));
  (* SOFT_HLUTNM = "soft_lutpair416" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[74]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in314_in),
        .I3(p_2_in7_in),
        .O(D[74]));
  (* SOFT_HLUTNM = "soft_lutpair384" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[75]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in314_in),
        .I3(p_2_in11_in),
        .O(D[75]));
  (* SOFT_HLUTNM = "soft_lutpair352" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[76]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in314_in),
        .I3(p_2_in15_in),
        .O(D[76]));
  (* SOFT_HLUTNM = "soft_lutpair320" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[77]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in314_in),
        .I3(p_2_in19_in),
        .O(D[77]));
  (* SOFT_HLUTNM = "soft_lutpair288" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[78]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in314_in),
        .I3(p_2_in23_in),
        .O(D[78]));
  (* SOFT_HLUTNM = "soft_lutpair256" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[79]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in314_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[79]));
  (* SOFT_HLUTNM = "soft_lutpair252" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[7]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(\sel_reg_n_0_[0] ),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[7]));
  (* SOFT_HLUTNM = "soft_lutpair481" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[80]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in332_in),
        .I3(p_2_in),
        .O(D[80]));
  (* SOFT_HLUTNM = "soft_lutpair449" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[81]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in332_in),
        .I3(p_2_in3_in),
        .O(D[81]));
  (* SOFT_HLUTNM = "soft_lutpair417" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[82]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in332_in),
        .I3(p_2_in7_in),
        .O(D[82]));
  (* SOFT_HLUTNM = "soft_lutpair385" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[83]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in332_in),
        .I3(p_2_in11_in),
        .O(D[83]));
  (* SOFT_HLUTNM = "soft_lutpair353" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[84]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in332_in),
        .I3(p_2_in15_in),
        .O(D[84]));
  (* SOFT_HLUTNM = "soft_lutpair321" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[85]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in332_in),
        .I3(p_2_in19_in),
        .O(D[85]));
  (* SOFT_HLUTNM = "soft_lutpair289" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[86]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in332_in),
        .I3(p_2_in23_in),
        .O(D[86]));
  (* SOFT_HLUTNM = "soft_lutpair257" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[87]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in332_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[87]));
  (* SOFT_HLUTNM = "soft_lutpair481" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[88]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in350_in),
        .I3(p_2_in),
        .O(D[88]));
  (* SOFT_HLUTNM = "soft_lutpair449" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[89]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in350_in),
        .I3(p_2_in3_in),
        .O(D[89]));
  (* SOFT_HLUTNM = "soft_lutpair476" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[8]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in170_in),
        .I3(p_2_in),
        .O(D[8]));
  (* SOFT_HLUTNM = "soft_lutpair417" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[90]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in350_in),
        .I3(p_2_in7_in),
        .O(D[90]));
  (* SOFT_HLUTNM = "soft_lutpair385" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[91]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in350_in),
        .I3(p_2_in11_in),
        .O(D[91]));
  (* SOFT_HLUTNM = "soft_lutpair353" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[92]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(p_0_in350_in),
        .I3(p_2_in15_in),
        .O(D[92]));
  (* SOFT_HLUTNM = "soft_lutpair321" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[93]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(p_0_in350_in),
        .I3(p_2_in19_in),
        .O(D[93]));
  (* SOFT_HLUTNM = "soft_lutpair289" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[94]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(p_0_in350_in),
        .I3(p_2_in23_in),
        .O(D[94]));
  (* SOFT_HLUTNM = "soft_lutpair257" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[95]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(p_0_in350_in),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(D[95]));
  (* SOFT_HLUTNM = "soft_lutpair482" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[96]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(p_0_in368_in),
        .I3(p_2_in),
        .O(D[96]));
  (* SOFT_HLUTNM = "soft_lutpair450" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[97]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in368_in),
        .I3(p_2_in3_in),
        .O(D[97]));
  (* SOFT_HLUTNM = "soft_lutpair418" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[98]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(p_0_in368_in),
        .I3(p_2_in7_in),
        .O(D[98]));
  (* SOFT_HLUTNM = "soft_lutpair386" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[99]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(p_0_in368_in),
        .I3(p_2_in11_in),
        .O(D[99]));
  (* SOFT_HLUTNM = "soft_lutpair444" *) 
  LUT4 #(
    .INIT(16'h56A6)) 
    \cplx_DQOut[9]_i_1 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(p_0_in170_in),
        .I3(p_2_in3_in),
        .O(D[9]));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \cplx_data_byte_103[0]_i_1 
       (.I0(p_1_in),
        .I1(p_2_in),
        .I2(p_2_in3_in),
        .I3(\victim_bit_decode_reg_n_0_[0] ),
        .I4(p_1_in1_in),
        .I5(cas_uses_dm),
        .O(rd_addr_101_reg_rep_0[0]));
  (* SOFT_HLUTNM = "soft_lutpair236" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[10]_i_1 
       (.I0(p_1_in5_in),
        .I1(p_0_in),
        .I2(p_2_in7_in),
        .I3(\cplx_data_byte_103[58]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[10]));
  (* SOFT_HLUTNM = "soft_lutpair232" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[11]_i_1 
       (.I0(p_1_in9_in),
        .I1(p_0_in),
        .I2(p_2_in11_in),
        .I3(\cplx_data_byte_103[59]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[11]));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[12]_i_1 
       (.I0(p_1_in13_in),
        .I1(p_0_in),
        .I2(p_2_in15_in),
        .I3(\cplx_data_byte_103[60]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[12]));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[13]_i_1 
       (.I0(p_1_in17_in),
        .I1(p_0_in),
        .I2(p_2_in19_in),
        .I3(\cplx_data_byte_103[61]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[13]));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[14]_i_1 
       (.I0(p_1_in21_in),
        .I1(p_0_in),
        .I2(p_2_in23_in),
        .I3(\cplx_data_byte_103[62]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[14]));
  (* SOFT_HLUTNM = "soft_lutpair248" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[15]_i_1 
       (.I0(p_1_in25_in),
        .I1(p_0_in),
        .I2(rd_addr_101_reg_rep_n_47),
        .I3(\cplx_data_byte_103[63]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[15]));
  (* SOFT_HLUTNM = "soft_lutpair244" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[16]_i_1 
       (.I0(p_1_in),
        .I1(p_0_in47_in),
        .I2(p_2_in),
        .I3(\cplx_data_byte_103[56]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[16]));
  (* SOFT_HLUTNM = "soft_lutpair240" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[17]_i_1 
       (.I0(p_1_in1_in),
        .I1(p_0_in47_in),
        .I2(p_2_in3_in),
        .I3(\cplx_data_byte_103[57]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[17]));
  (* SOFT_HLUTNM = "soft_lutpair236" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[18]_i_1 
       (.I0(p_1_in5_in),
        .I1(p_0_in47_in),
        .I2(p_2_in7_in),
        .I3(\cplx_data_byte_103[58]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[18]));
  (* SOFT_HLUTNM = "soft_lutpair232" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[19]_i_1 
       (.I0(p_1_in9_in),
        .I1(p_0_in47_in),
        .I2(p_2_in11_in),
        .I3(\cplx_data_byte_103[59]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[19]));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \cplx_data_byte_103[1]_i_1 
       (.I0(p_1_in1_in),
        .I1(p_2_in3_in),
        .I2(p_2_in7_in),
        .I3(\victim_bit_decode_reg_n_0_[0] ),
        .I4(p_1_in5_in),
        .I5(cas_uses_dm),
        .O(rd_addr_101_reg_rep_0[1]));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[20]_i_1 
       (.I0(p_1_in13_in),
        .I1(p_0_in47_in),
        .I2(p_2_in15_in),
        .I3(\cplx_data_byte_103[60]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[20]));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[21]_i_1 
       (.I0(p_1_in17_in),
        .I1(p_0_in47_in),
        .I2(p_2_in19_in),
        .I3(\cplx_data_byte_103[61]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[21]));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[22]_i_1 
       (.I0(p_1_in21_in),
        .I1(p_0_in47_in),
        .I2(p_2_in23_in),
        .I3(\cplx_data_byte_103[62]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[22]));
  (* SOFT_HLUTNM = "soft_lutpair248" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[23]_i_1 
       (.I0(p_1_in25_in),
        .I1(p_0_in47_in),
        .I2(rd_addr_101_reg_rep_n_47),
        .I3(\cplx_data_byte_103[63]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[23]));
  (* SOFT_HLUTNM = "soft_lutpair245" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[24]_i_1 
       (.I0(p_1_in),
        .I1(p_0_in65_in),
        .I2(p_2_in),
        .I3(\cplx_data_byte_103[56]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[24]));
  (* SOFT_HLUTNM = "soft_lutpair241" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[25]_i_1 
       (.I0(p_1_in1_in),
        .I1(p_0_in65_in),
        .I2(p_2_in3_in),
        .I3(\cplx_data_byte_103[57]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[25]));
  (* SOFT_HLUTNM = "soft_lutpair237" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[26]_i_1 
       (.I0(p_1_in5_in),
        .I1(p_0_in65_in),
        .I2(p_2_in7_in),
        .I3(\cplx_data_byte_103[58]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[26]));
  (* SOFT_HLUTNM = "soft_lutpair233" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[27]_i_1 
       (.I0(p_1_in9_in),
        .I1(p_0_in65_in),
        .I2(p_2_in11_in),
        .I3(\cplx_data_byte_103[59]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[27]));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[28]_i_1 
       (.I0(p_1_in13_in),
        .I1(p_0_in65_in),
        .I2(p_2_in15_in),
        .I3(\cplx_data_byte_103[60]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[28]));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[29]_i_1 
       (.I0(p_1_in17_in),
        .I1(p_0_in65_in),
        .I2(p_2_in19_in),
        .I3(\cplx_data_byte_103[61]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[29]));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \cplx_data_byte_103[2]_i_1 
       (.I0(p_1_in5_in),
        .I1(p_2_in7_in),
        .I2(p_2_in11_in),
        .I3(\victim_bit_decode_reg_n_0_[0] ),
        .I4(p_1_in9_in),
        .I5(cas_uses_dm),
        .O(rd_addr_101_reg_rep_0[2]));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[30]_i_1 
       (.I0(p_1_in21_in),
        .I1(p_0_in65_in),
        .I2(p_2_in23_in),
        .I3(\cplx_data_byte_103[62]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[30]));
  (* SOFT_HLUTNM = "soft_lutpair249" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[31]_i_1 
       (.I0(p_1_in25_in),
        .I1(p_0_in65_in),
        .I2(rd_addr_101_reg_rep_n_47),
        .I3(\cplx_data_byte_103[63]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[31]));
  (* SOFT_HLUTNM = "soft_lutpair245" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[32]_i_1 
       (.I0(p_1_in),
        .I1(p_0_in83_in),
        .I2(p_2_in),
        .I3(\cplx_data_byte_103[56]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[32]));
  (* SOFT_HLUTNM = "soft_lutpair241" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[33]_i_1 
       (.I0(p_1_in1_in),
        .I1(p_0_in83_in),
        .I2(p_2_in3_in),
        .I3(\cplx_data_byte_103[57]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[33]));
  (* SOFT_HLUTNM = "soft_lutpair237" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[34]_i_1 
       (.I0(p_1_in5_in),
        .I1(p_0_in83_in),
        .I2(p_2_in7_in),
        .I3(\cplx_data_byte_103[58]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[34]));
  (* SOFT_HLUTNM = "soft_lutpair233" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[35]_i_1 
       (.I0(p_1_in9_in),
        .I1(p_0_in83_in),
        .I2(p_2_in11_in),
        .I3(\cplx_data_byte_103[59]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[35]));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[36]_i_1 
       (.I0(p_1_in13_in),
        .I1(p_0_in83_in),
        .I2(p_2_in15_in),
        .I3(\cplx_data_byte_103[60]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[36]));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[37]_i_1 
       (.I0(p_1_in17_in),
        .I1(p_0_in83_in),
        .I2(p_2_in19_in),
        .I3(\cplx_data_byte_103[61]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[37]));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[38]_i_1 
       (.I0(p_1_in21_in),
        .I1(p_0_in83_in),
        .I2(p_2_in23_in),
        .I3(\cplx_data_byte_103[62]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[38]));
  (* SOFT_HLUTNM = "soft_lutpair249" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[39]_i_1 
       (.I0(p_1_in25_in),
        .I1(p_0_in83_in),
        .I2(rd_addr_101_reg_rep_n_47),
        .I3(\cplx_data_byte_103[63]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[39]));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \cplx_data_byte_103[3]_i_1 
       (.I0(p_1_in9_in),
        .I1(p_2_in11_in),
        .I2(p_2_in15_in),
        .I3(\victim_bit_decode_reg_n_0_[0] ),
        .I4(p_1_in13_in),
        .I5(cas_uses_dm),
        .O(rd_addr_101_reg_rep_0[3]));
  (* SOFT_HLUTNM = "soft_lutpair246" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[40]_i_1 
       (.I0(p_1_in),
        .I1(p_0_in101_in),
        .I2(p_2_in),
        .I3(\cplx_data_byte_103[56]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[40]));
  (* SOFT_HLUTNM = "soft_lutpair242" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[41]_i_1 
       (.I0(p_1_in1_in),
        .I1(p_0_in101_in),
        .I2(p_2_in3_in),
        .I3(\cplx_data_byte_103[57]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[41]));
  (* SOFT_HLUTNM = "soft_lutpair238" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[42]_i_1 
       (.I0(p_1_in5_in),
        .I1(p_0_in101_in),
        .I2(p_2_in7_in),
        .I3(\cplx_data_byte_103[58]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[42]));
  (* SOFT_HLUTNM = "soft_lutpair234" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[43]_i_1 
       (.I0(p_1_in9_in),
        .I1(p_0_in101_in),
        .I2(p_2_in11_in),
        .I3(\cplx_data_byte_103[59]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[43]));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[44]_i_1 
       (.I0(p_1_in13_in),
        .I1(p_0_in101_in),
        .I2(p_2_in15_in),
        .I3(\cplx_data_byte_103[60]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[44]));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[45]_i_1 
       (.I0(p_1_in17_in),
        .I1(p_0_in101_in),
        .I2(p_2_in19_in),
        .I3(\cplx_data_byte_103[61]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[45]));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[46]_i_1 
       (.I0(p_1_in21_in),
        .I1(p_0_in101_in),
        .I2(p_2_in23_in),
        .I3(\cplx_data_byte_103[62]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[46]));
  (* SOFT_HLUTNM = "soft_lutpair250" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[47]_i_1 
       (.I0(p_1_in25_in),
        .I1(p_0_in101_in),
        .I2(rd_addr_101_reg_rep_n_47),
        .I3(\cplx_data_byte_103[63]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[47]));
  (* SOFT_HLUTNM = "soft_lutpair246" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[48]_i_1 
       (.I0(p_1_in),
        .I1(p_0_in119_in),
        .I2(p_2_in),
        .I3(\cplx_data_byte_103[56]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[48]));
  (* SOFT_HLUTNM = "soft_lutpair242" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[49]_i_1 
       (.I0(p_1_in1_in),
        .I1(p_0_in119_in),
        .I2(p_2_in3_in),
        .I3(\cplx_data_byte_103[57]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[49]));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \cplx_data_byte_103[4]_i_1 
       (.I0(p_1_in13_in),
        .I1(p_2_in15_in),
        .I2(p_2_in19_in),
        .I3(\victim_bit_decode_reg_n_0_[0] ),
        .I4(p_1_in17_in),
        .I5(cas_uses_dm),
        .O(rd_addr_101_reg_rep_0[4]));
  (* SOFT_HLUTNM = "soft_lutpair238" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[50]_i_1 
       (.I0(p_1_in5_in),
        .I1(p_0_in119_in),
        .I2(p_2_in7_in),
        .I3(\cplx_data_byte_103[58]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[50]));
  (* SOFT_HLUTNM = "soft_lutpair234" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[51]_i_1 
       (.I0(p_1_in9_in),
        .I1(p_0_in119_in),
        .I2(p_2_in11_in),
        .I3(\cplx_data_byte_103[59]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[51]));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[52]_i_1 
       (.I0(p_1_in13_in),
        .I1(p_0_in119_in),
        .I2(p_2_in15_in),
        .I3(\cplx_data_byte_103[60]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[52]));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[53]_i_1 
       (.I0(p_1_in17_in),
        .I1(p_0_in119_in),
        .I2(p_2_in19_in),
        .I3(\cplx_data_byte_103[61]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[53]));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[54]_i_1 
       (.I0(p_1_in21_in),
        .I1(p_0_in119_in),
        .I2(p_2_in23_in),
        .I3(\cplx_data_byte_103[62]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[54]));
  (* SOFT_HLUTNM = "soft_lutpair250" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[55]_i_1 
       (.I0(p_1_in25_in),
        .I1(p_0_in119_in),
        .I2(rd_addr_101_reg_rep_n_47),
        .I3(\cplx_data_byte_103[63]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[55]));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[56]_i_1 
       (.I0(p_1_in),
        .I1(p_0_in137_in),
        .I2(p_2_in),
        .I3(\cplx_data_byte_103[56]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[56]));
  (* SOFT_HLUTNM = "soft_lutpair247" *) 
  LUT4 #(
    .INIT(16'h02A2)) 
    \cplx_data_byte_103[56]_i_2 
       (.I0(cas_uses_dm),
        .I1(p_1_in1_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in3_in),
        .O(\cplx_data_byte_103[56]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[57]_i_1 
       (.I0(p_1_in1_in),
        .I1(p_0_in137_in),
        .I2(p_2_in3_in),
        .I3(\cplx_data_byte_103[57]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[57]));
  (* SOFT_HLUTNM = "soft_lutpair243" *) 
  LUT4 #(
    .INIT(16'h02A2)) 
    \cplx_data_byte_103[57]_i_2 
       (.I0(cas_uses_dm),
        .I1(p_1_in5_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in7_in),
        .O(\cplx_data_byte_103[57]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[58]_i_1 
       (.I0(p_1_in5_in),
        .I1(p_0_in137_in),
        .I2(p_2_in7_in),
        .I3(\cplx_data_byte_103[58]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[58]));
  (* SOFT_HLUTNM = "soft_lutpair239" *) 
  LUT4 #(
    .INIT(16'h02A2)) 
    \cplx_data_byte_103[58]_i_2 
       (.I0(cas_uses_dm),
        .I1(p_1_in9_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in11_in),
        .O(\cplx_data_byte_103[58]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[59]_i_1 
       (.I0(p_1_in9_in),
        .I1(p_0_in137_in),
        .I2(p_2_in11_in),
        .I3(\cplx_data_byte_103[59]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[59]));
  (* SOFT_HLUTNM = "soft_lutpair235" *) 
  LUT4 #(
    .INIT(16'h02A2)) 
    \cplx_data_byte_103[59]_i_2 
       (.I0(cas_uses_dm),
        .I1(p_1_in13_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in15_in),
        .O(\cplx_data_byte_103[59]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \cplx_data_byte_103[5]_i_1 
       (.I0(p_1_in17_in),
        .I1(p_2_in19_in),
        .I2(p_2_in23_in),
        .I3(\victim_bit_decode_reg_n_0_[0] ),
        .I4(p_1_in21_in),
        .I5(cas_uses_dm),
        .O(rd_addr_101_reg_rep_0[5]));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[60]_i_1 
       (.I0(p_1_in13_in),
        .I1(p_0_in137_in),
        .I2(p_2_in15_in),
        .I3(\cplx_data_byte_103[60]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[60]));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT4 #(
    .INIT(16'h02A2)) 
    \cplx_data_byte_103[60]_i_2 
       (.I0(cas_uses_dm),
        .I1(p_1_in17_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in19_in),
        .O(\cplx_data_byte_103[60]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[61]_i_1 
       (.I0(p_1_in17_in),
        .I1(p_0_in137_in),
        .I2(p_2_in19_in),
        .I3(\cplx_data_byte_103[61]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[61]));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT4 #(
    .INIT(16'h02A2)) 
    \cplx_data_byte_103[61]_i_2 
       (.I0(cas_uses_dm),
        .I1(p_1_in21_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in23_in),
        .O(\cplx_data_byte_103[61]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[62]_i_1 
       (.I0(p_1_in21_in),
        .I1(p_0_in137_in),
        .I2(p_2_in23_in),
        .I3(\cplx_data_byte_103[62]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[62]));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT4 #(
    .INIT(16'h02A2)) 
    \cplx_data_byte_103[62]_i_2 
       (.I0(cas_uses_dm),
        .I1(p_1_in25_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(rd_addr_101_reg_rep_n_47),
        .O(\cplx_data_byte_103[62]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[63]_i_1 
       (.I0(p_1_in25_in),
        .I1(p_0_in137_in),
        .I2(rd_addr_101_reg_rep_n_47),
        .I3(\cplx_data_byte_103[63]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[63]));
  (* SOFT_HLUTNM = "soft_lutpair251" *) 
  LUT4 #(
    .INIT(16'h02A2)) 
    \cplx_data_byte_103[63]_i_2 
       (.I0(cas_uses_dm),
        .I1(p_1_in),
        .I2(\victim_bit_decode_reg_n_0_[0] ),
        .I3(p_2_in),
        .O(\cplx_data_byte_103[63]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \cplx_data_byte_103[6]_i_1 
       (.I0(p_1_in21_in),
        .I1(p_2_in23_in),
        .I2(rd_addr_101_reg_rep_n_47),
        .I3(\victim_bit_decode_reg_n_0_[0] ),
        .I4(p_1_in25_in),
        .I5(cas_uses_dm),
        .O(rd_addr_101_reg_rep_0[6]));
  LUT6 #(
    .INIT(64'hC3AAC355CCAACCAA)) 
    \cplx_data_byte_103[7]_i_1 
       (.I0(p_1_in25_in),
        .I1(rd_addr_101_reg_rep_n_47),
        .I2(p_2_in),
        .I3(\victim_bit_decode_reg_n_0_[0] ),
        .I4(p_1_in),
        .I5(cas_uses_dm),
        .O(rd_addr_101_reg_rep_0[7]));
  (* SOFT_HLUTNM = "soft_lutpair244" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[8]_i_1 
       (.I0(p_1_in),
        .I1(p_0_in),
        .I2(p_2_in),
        .I3(\cplx_data_byte_103[56]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[8]));
  (* SOFT_HLUTNM = "soft_lutpair240" *) 
  LUT4 #(
    .INIT(16'h1DE2)) 
    \cplx_data_byte_103[9]_i_1 
       (.I0(p_1_in1_in),
        .I1(p_0_in),
        .I2(p_2_in3_in),
        .I3(\cplx_data_byte_103[57]_i_2_n_0 ),
        .O(rd_addr_101_reg_rep_0[9]));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT3 #(
    .INIT(8'h59)) 
    \rd_addr_101[0]_i_1 
       (.I0(rd_addr_101_reg[0]),
        .I1(\outstanding_reads_reg[0] ),
        .I2(early_wrDataEn),
        .O(\rd_addr_101[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT4 #(
    .INIT(16'h758A)) 
    \rd_addr_101[1]_i_1 
       (.I0(rd_addr_101_reg[0]),
        .I1(early_wrDataEn),
        .I2(\outstanding_reads_reg[0] ),
        .I3(rd_addr_101_reg[1]),
        .O(\rd_addr_101[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT5 #(
    .INIT(32'h5DFFA200)) 
    \rd_addr_101[2]_i_1 
       (.I0(rd_addr_101_reg[1]),
        .I1(\outstanding_reads_reg[0] ),
        .I2(early_wrDataEn),
        .I3(rd_addr_101_reg[0]),
        .I4(rd_addr_101_reg[2]),
        .O(\rd_addr_101[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7F77FFFF80880000)) 
    \rd_addr_101[3]_i_1 
       (.I0(rd_addr_101_reg[2]),
        .I1(rd_addr_101_reg[0]),
        .I2(early_wrDataEn),
        .I3(\outstanding_reads_reg[0] ),
        .I4(rd_addr_101_reg[1]),
        .I5(rd_addr_101_reg[3]),
        .O(\rd_addr_101[3]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \rd_addr_101[4]_i_1 
       (.I0(rd_addr_101_reg_rep_i_9_n_0),
        .I1(rd_addr_101_reg[4]),
        .O(\rd_addr_101[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rd_addr_101[5]_i_1 
       (.I0(rd_addr_101_reg[4]),
        .I1(rd_addr_101_reg_rep_i_9_n_0),
        .I2(rd_addr_101_reg[5]),
        .O(\rd_addr_101[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT4 #(
    .INIT(16'hDF20)) 
    \rd_addr_101[6]_i_1 
       (.I0(rd_addr_101_reg[5]),
        .I1(rd_addr_101_reg_rep_i_9_n_0),
        .I2(rd_addr_101_reg[4]),
        .I3(rd_addr_101_reg[6]),
        .O(\rd_addr_101[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAABA)) 
    \rd_addr_101[7]_i_1 
       (.I0(out),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[2]),
        .O(SR));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT5 #(
    .INIT(32'hF7FF0800)) 
    \rd_addr_101[7]_i_2 
       (.I0(rd_addr_101_reg[6]),
        .I1(rd_addr_101_reg[4]),
        .I2(rd_addr_101_reg_rep_i_9_n_0),
        .I3(rd_addr_101_reg[5]),
        .I4(rd_addr_101_reg[7]),
        .O(\rd_addr_101[7]_i_2_n_0 ));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_addr_101_reg[0] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\rd_addr_101[0]_i_1_n_0 ),
        .Q(rd_addr_101_reg[0]),
        .R(SR));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_addr_101_reg[1] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\rd_addr_101[1]_i_1_n_0 ),
        .Q(rd_addr_101_reg[1]),
        .R(SR));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_addr_101_reg[2] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\rd_addr_101[2]_i_1_n_0 ),
        .Q(rd_addr_101_reg[2]),
        .R(SR));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_addr_101_reg[3] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\rd_addr_101[3]_i_1_n_0 ),
        .Q(rd_addr_101_reg[3]),
        .R(SR));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_addr_101_reg[4] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\rd_addr_101[4]_i_1_n_0 ),
        .Q(rd_addr_101_reg[4]),
        .R(SR));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_addr_101_reg[5] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\rd_addr_101[5]_i_1_n_0 ),
        .Q(rd_addr_101_reg[5]),
        .R(SR));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_addr_101_reg[6] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\rd_addr_101[6]_i_1_n_0 ),
        .Q(rd_addr_101_reg[6]),
        .R(SR));
  (* equivalent_register_removal = "no" *) 
  FDRE \rd_addr_101_reg[7] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\rd_addr_101[7]_i_2_n_0 ),
        .Q(rd_addr_101_reg[7]),
        .R(SR));
  (* \MEM.PORTA.DATA_BIT_LAYOUT  = "p0_d16" *) 
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RDADDR_COLLISION_HWCONFIG = "PERFORMANCE" *) 
  (* RTL_RAM_BITS = "4096" *) 
  (* RTL_RAM_NAME = "inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/u_ddr_cal_cplx/u_ddr_cal_cplx_data/rd_addr_101_reg_rep" *) 
  (* RTL_RAM_TYPE = "RAM_SP" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "1023" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "15" *) 
  RAMB18E2 #(
    .CASCADE_ORDER_A("NONE"),
    .CASCADE_ORDER_B("NONE"),
    .CLOCK_DOMAINS("INDEPENDENT"),
    .DOA_REG(1),
    .DOB_REG(0),
    .ENADDRENA("FALSE"),
    .ENADDRENB("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'hFCFCE0E083830F0F3E3EF8F8F0F0F0F0F0F0F0F038388E8EE3E3CCCCCCCCAAAA),
    .INIT_01(256'hF807F00FF00FF00FF00F38C78E71E31CCC33CC33AA55C0C00F0FFCFCC0C00F0F),
    .INIT_02(256'h28478A31A284B4C0B46FB457C03F0FF0FC03C03F0FF0FC03E01F837C0FF03EC1),
    .INIT_03(256'h4084F5C0AB6F2A57A8BFA07A829A0A252A8AA821AFF050DBAF95507AAF9AA225),
    .INIT_04(256'hFF6FAA5702BFAA7A809A2A25A08A0A21A8F002DBAA95F57AAB9A4025F547AB31),
    .INIT_05(256'hAABF027AA89A0A25A08A2A2180F0AADBFF95AA7A009A5525FF47AA31008455C0),
    .INIT_06(256'hBF9AAA25008A5421F5F0BFDBAA95007A549AF525BF47AA312A8480C0AA6F0057),
    .INIT_07(256'h57570221A0F0AADB0095A87A2A9A0025AA470A318084AAC0026FA057AABFF57A),
    .INIT_08(256'hBC431FE048B7D42B0AF5E31C8798B555B5554F9BB325E44728318684C0C06F6F),
    .INIT_09(256'h010101010101008055AA552A0000000055555555000080000AF5CB34B44B8F14),
    .INIT_0A(256'h0101010101010101010101010101010101010101010101010101010101010101),
    .INIT_0B(256'h0101010101010101010101010101010101010101010101010101010101010101),
    .INIT_0C(256'h0101010101010101010101010101010101010101010101010101010101010101),
    .INIT_0D(256'h0101010101010101010101010101010101010101010101010101010101010101),
    .INIT_0E(256'h0101010101010101010101010101010101010101010101010101010101010101),
    .INIT_0F(256'h0101010101010101010101010101010101010101010101010101010101010101),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(18'h00000),
    .INIT_B(18'h00000),
    .INIT_FILE("NONE"),
    .RDADDRCHANGEA("FALSE"),
    .RDADDRCHANGEB("FALSE"),
    .READ_WIDTH_A(18),
    .READ_WIDTH_B(0),
    .RSTREG_PRIORITY_A("RSTREG"),
    .RSTREG_PRIORITY_B("RSTREG"),
    .SIM_COLLISION_CHECK("ALL"),
    .SLEEP_ASYNC("FALSE"),
    .SRVAL_A(18'h00000),
    .SRVAL_B(18'h00000),
    .WRITE_MODE_A("WRITE_FIRST"),
    .WRITE_MODE_B("WRITE_FIRST"),
    .WRITE_WIDTH_A(18),
    .WRITE_WIDTH_B(0)) 
    rd_addr_101_reg_rep
       (.ADDRARDADDR({1'b0,1'b0,rd_addr_101_reg_rep_i_1_n_0,rd_addr_101_reg_rep_i_2_n_0,rd_addr_101_reg_rep_i_3_n_0,rd_addr_101_reg_rep_i_4_n_0,rd_addr_101_reg_rep_i_5_n_0,rd_addr_101_reg_rep_i_6_n_0,rd_addr_101_reg_rep_i_7_n_0,rd_addr_101_reg_rep_i_8_n_0,1'b0,1'b0,1'b0,1'b0}),
        .ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRENA(1'b1),
        .ADDRENB(1'b1),
        .CASDIMUXA(1'b0),
        .CASDIMUXB(1'b0),
        .CASDINA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CASDINB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CASDINPA({1'b0,1'b0}),
        .CASDINPB({1'b0,1'b0}),
        .CASDOMUXA(1'b0),
        .CASDOMUXB(1'b0),
        .CASDOMUXEN_A(1'b1),
        .CASDOMUXEN_B(1'b1),
        .CASDOUTA(NLW_rd_addr_101_reg_rep_CASDOUTA_UNCONNECTED[15:0]),
        .CASDOUTB(NLW_rd_addr_101_reg_rep_CASDOUTB_UNCONNECTED[15:0]),
        .CASDOUTPA(NLW_rd_addr_101_reg_rep_CASDOUTPA_UNCONNECTED[1:0]),
        .CASDOUTPB(NLW_rd_addr_101_reg_rep_CASDOUTPB_UNCONNECTED[1:0]),
        .CASOREGIMUXA(1'b0),
        .CASOREGIMUXB(1'b0),
        .CASOREGIMUXEN_A(1'b1),
        .CASOREGIMUXEN_B(1'b1),
        .CLKARDCLK(\rd_addr_101_reg[7]_0 ),
        .CLKBWRCLK(1'b0),
        .DINADIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DINBDIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .DINPADINP({1'b0,1'b0}),
        .DINPBDINP({1'b1,1'b1}),
        .DOUTADOUT({p_1_in,p_1_in1_in,p_1_in5_in,p_1_in9_in,p_1_in13_in,p_1_in17_in,p_1_in21_in,p_1_in25_in,p_2_in,p_2_in3_in,p_2_in7_in,p_2_in11_in,p_2_in15_in,p_2_in19_in,p_2_in23_in,rd_addr_101_reg_rep_n_47}),
        .DOUTBDOUT(NLW_rd_addr_101_reg_rep_DOUTBDOUT_UNCONNECTED[15:0]),
        .DOUTPADOUTP(NLW_rd_addr_101_reg_rep_DOUTPADOUTP_UNCONNECTED[1:0]),
        .DOUTPBDOUTP(NLW_rd_addr_101_reg_rep_DOUTPBDOUTP_UNCONNECTED[1:0]),
        .ENARDEN(1'b1),
        .ENBWREN(1'b0),
        .REGCEAREGCE(1'b1),
        .REGCEB(1'b1),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SLEEP(1'b0),
        .WEA({1'b0,1'b0}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0}));
  LUT6 #(
    .INIT(64'h00000000A6AAAAAA)) 
    rd_addr_101_reg_rep_i_1
       (.I0(rd_addr_101_reg[7]),
        .I1(rd_addr_101_reg[5]),
        .I2(rd_addr_101_reg_rep_i_9_n_0),
        .I3(rd_addr_101_reg[4]),
        .I4(rd_addr_101_reg[6]),
        .I5(SR),
        .O(rd_addr_101_reg_rep_i_1_n_0));
  LUT6 #(
    .INIT(64'h00000001FFFFFFFF)) 
    rd_addr_101_reg_rep_i_10
       (.I0(rd_addr_101_reg_rep_1[0]),
        .I1(rd_addr_101_reg_rep_1[4]),
        .I2(rd_addr_101_reg_rep_1[3]),
        .I3(rd_addr_101_reg_rep_1[1]),
        .I4(rd_addr_101_reg_rep_1[2]),
        .I5(rdDataEn_pi),
        .O(\outstanding_reads_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT5 #(
    .INIT(32'h0000A6AA)) 
    rd_addr_101_reg_rep_i_2
       (.I0(rd_addr_101_reg[6]),
        .I1(rd_addr_101_reg[4]),
        .I2(rd_addr_101_reg_rep_i_9_n_0),
        .I3(rd_addr_101_reg[5]),
        .I4(SR),
        .O(rd_addr_101_reg_rep_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT4 #(
    .INIT(16'h009A)) 
    rd_addr_101_reg_rep_i_3
       (.I0(rd_addr_101_reg[5]),
        .I1(rd_addr_101_reg_rep_i_9_n_0),
        .I2(rd_addr_101_reg[4]),
        .I3(SR),
        .O(rd_addr_101_reg_rep_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT3 #(
    .INIT(8'h09)) 
    rd_addr_101_reg_rep_i_4
       (.I0(rd_addr_101_reg[4]),
        .I1(rd_addr_101_reg_rep_i_9_n_0),
        .I2(SR),
        .O(rd_addr_101_reg_rep_i_4_n_0));
  LUT6 #(
    .INIT(64'h00000000AAAAA8AA)) 
    rd_addr_101_reg_rep_i_5
       (.I0(\rd_addr_101[3]_i_1_n_0 ),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(out),
        .O(rd_addr_101_reg_rep_i_5_n_0));
  LUT6 #(
    .INIT(64'h000000006A66AAAA)) 
    rd_addr_101_reg_rep_i_6
       (.I0(rd_addr_101_reg[2]),
        .I1(rd_addr_101_reg[0]),
        .I2(early_wrDataEn),
        .I3(\outstanding_reads_reg[0] ),
        .I4(rd_addr_101_reg[1]),
        .I5(SR),
        .O(rd_addr_101_reg_rep_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT5 #(
    .INIT(32'h000059AA)) 
    rd_addr_101_reg_rep_i_7
       (.I0(rd_addr_101_reg[1]),
        .I1(\outstanding_reads_reg[0] ),
        .I2(early_wrDataEn),
        .I3(rd_addr_101_reg[0]),
        .I4(SR),
        .O(rd_addr_101_reg_rep_i_7_n_0));
  LUT4 #(
    .INIT(16'h004B)) 
    rd_addr_101_reg_rep_i_8
       (.I0(early_wrDataEn),
        .I1(\outstanding_reads_reg[0] ),
        .I2(rd_addr_101_reg[0]),
        .I3(SR),
        .O(rd_addr_101_reg_rep_i_8_n_0));
  LUT6 #(
    .INIT(64'h7F77FFFFFFFFFFFF)) 
    rd_addr_101_reg_rep_i_9
       (.I0(rd_addr_101_reg[2]),
        .I1(rd_addr_101_reg[0]),
        .I2(early_wrDataEn),
        .I3(\outstanding_reads_reg[0] ),
        .I4(rd_addr_101_reg[1]),
        .I5(rd_addr_101_reg[3]),
        .O(rd_addr_101_reg_rep_i_9_n_0));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT5 #(
    .INIT(32'h00010000)) 
    \sel[0]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[10]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[11]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[12]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[13]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \sel[14]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \sel[15]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT5 #(
    .INIT(32'h00100000)) 
    \sel[16]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT5 #(
    .INIT(32'h00100000)) 
    \sel[17]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[17]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[18]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[18]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[19]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[19]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT5 #(
    .INIT(32'h00010000)) 
    \sel[1]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[20]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[21]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \sel[22]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \sel[23]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[23]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT5 #(
    .INIT(32'h10000000)) 
    \sel[24]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[24]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT5 #(
    .INIT(32'h10000000)) 
    \sel[25]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[25]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT5 #(
    .INIT(32'h20000000)) 
    \sel[26]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[26]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT5 #(
    .INIT(32'h20000000)) 
    \sel[27]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[27]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT5 #(
    .INIT(32'h20000000)) 
    \sel[28]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT5 #(
    .INIT(32'h20000000)) 
    \sel[29]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT5 #(
    .INIT(32'h00020000)) 
    \sel[2]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \sel[30]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[30]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair508" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \sel[30]_i_2 
       (.I0(\sel_reg[0]_0 [0]),
        .I1(\sel_reg[30]_0 [3]),
        .I2(\sel_reg[30]_0 [4]),
        .I3(\sel_reg[30]_0 [2]),
        .O(\sel[30]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \sel[31]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair509" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \sel[31]_i_2 
       (.I0(\sel_reg[0]_0 [0]),
        .I1(\sel_reg[30]_0 [3]),
        .I2(\sel_reg[30]_0 [4]),
        .I3(\sel_reg[30]_0 [2]),
        .O(\sel[31]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT5 #(
    .INIT(32'h00010000)) 
    \sel[32]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[32]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT5 #(
    .INIT(32'h00010000)) 
    \sel[33]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[33]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT5 #(
    .INIT(32'h00020000)) 
    \sel[34]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[34]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT5 #(
    .INIT(32'h00020000)) 
    \sel[35]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[35]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT5 #(
    .INIT(32'h00020000)) 
    \sel[36]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[36]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT5 #(
    .INIT(32'h00020000)) 
    \sel[37]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[37]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT5 #(
    .INIT(32'h00080000)) 
    \sel[38]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[38]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT5 #(
    .INIT(32'h00080000)) 
    \sel[39]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[39]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT5 #(
    .INIT(32'h00020000)) 
    \sel[3]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT5 #(
    .INIT(32'h00100000)) 
    \sel[40]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[40]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT5 #(
    .INIT(32'h00100000)) 
    \sel[41]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[41]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[42]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[42]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[43]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[43]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[44]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[44]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[45]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[45]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \sel[46]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[46]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \sel[47]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT5 #(
    .INIT(32'h00100000)) 
    \sel[48]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[48]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT5 #(
    .INIT(32'h00100000)) 
    \sel[49]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[49]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT5 #(
    .INIT(32'h00020000)) 
    \sel[4]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[50]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[50]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[51]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[51]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[52]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[52]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT5 #(
    .INIT(32'h00200000)) 
    \sel[53]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[53]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \sel[54]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[54]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \sel[55]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [1]),
        .I3(\sel_reg[30]_0 [0]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[55]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT5 #(
    .INIT(32'h10000000)) 
    \sel[56]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[56]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT5 #(
    .INIT(32'h10000000)) 
    \sel[57]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[57]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT5 #(
    .INIT(32'h20000000)) 
    \sel[58]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[58]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT5 #(
    .INIT(32'h20000000)) 
    \sel[59]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[59]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT5 #(
    .INIT(32'h00020000)) 
    \sel[5]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT5 #(
    .INIT(32'h20000000)) 
    \sel[60]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[60]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT5 #(
    .INIT(32'h20000000)) 
    \sel[61]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[61]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \sel[62]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[62]_i_2_n_0 ),
        .O(\sel[62]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair508" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \sel[62]_i_2 
       (.I0(\sel_reg[0]_0 [0]),
        .I1(\sel_reg[30]_0 [3]),
        .I2(\sel_reg[30]_0 [4]),
        .I3(\sel_reg[30]_0 [2]),
        .O(\sel[62]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \sel[63]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[63]_i_2_n_0 ),
        .O(\sel[63]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair509" *) 
  LUT4 #(
    .INIT(16'h0200)) 
    \sel[63]_i_2 
       (.I0(\sel_reg[0]_0 [0]),
        .I1(\sel_reg[30]_0 [3]),
        .I2(\sel_reg[30]_0 [4]),
        .I3(\sel_reg[30]_0 [2]),
        .O(\sel[63]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT5 #(
    .INIT(32'h00080000)) 
    \sel[6]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT5 #(
    .INIT(32'h00080000)) 
    \sel[7]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT5 #(
    .INIT(32'h00100000)) 
    \sel[8]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[30]_i_2_n_0 ),
        .O(\sel[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT5 #(
    .INIT(32'h00100000)) 
    \sel[9]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[30]_0 [0]),
        .I3(\sel_reg[30]_0 [1]),
        .I4(\sel[31]_i_2_n_0 ),
        .O(\sel[9]_i_1_n_0 ));
  FDRE \sel_reg[0] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[0]_i_1_n_0 ),
        .Q(\sel_reg_n_0_[0] ),
        .R(out));
  FDRE \sel_reg[10] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[10]_i_1_n_0 ),
        .Q(p_0_in332_in),
        .R(out));
  FDRE \sel_reg[11] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[11]_i_1_n_0 ),
        .Q(p_0_in350_in),
        .R(out));
  FDRE \sel_reg[12] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[12]_i_1_n_0 ),
        .Q(p_0_in368_in),
        .R(out));
  FDRE \sel_reg[13] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[13]_i_1_n_0 ),
        .Q(p_0_in386_in),
        .R(out));
  FDRE \sel_reg[14] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[14]_i_1_n_0 ),
        .Q(p_0_in404_in),
        .R(out));
  FDRE \sel_reg[15] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[15]_i_1_n_0 ),
        .Q(p_0_in422_in),
        .R(out));
  FDRE \sel_reg[16] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[16]_i_1_n_0 ),
        .Q(p_0_in440_in),
        .R(out));
  FDRE \sel_reg[17] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[17]_i_1_n_0 ),
        .Q(p_0_in458_in),
        .R(out));
  FDRE \sel_reg[18] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[18]_i_1_n_0 ),
        .Q(p_0_in476_in),
        .R(out));
  FDRE \sel_reg[19] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[19]_i_1_n_0 ),
        .Q(p_0_in494_in),
        .R(out));
  FDRE \sel_reg[1] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[1]_i_1_n_0 ),
        .Q(p_0_in170_in),
        .R(out));
  FDRE \sel_reg[20] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[20]_i_1_n_0 ),
        .Q(p_0_in512_in),
        .R(out));
  FDRE \sel_reg[21] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[21]_i_1_n_0 ),
        .Q(p_0_in530_in),
        .R(out));
  FDRE \sel_reg[22] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[22]_i_1_n_0 ),
        .Q(p_0_in548_in),
        .R(out));
  FDRE \sel_reg[23] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[23]_i_1_n_0 ),
        .Q(p_0_in566_in),
        .R(out));
  FDRE \sel_reg[24] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[24]_i_1_n_0 ),
        .Q(p_0_in584_in),
        .R(out));
  FDRE \sel_reg[25] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[25]_i_1_n_0 ),
        .Q(p_0_in602_in),
        .R(out));
  FDRE \sel_reg[26] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[26]_i_1_n_0 ),
        .Q(p_0_in620_in),
        .R(out));
  FDRE \sel_reg[27] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[27]_i_1_n_0 ),
        .Q(p_0_in638_in),
        .R(out));
  FDRE \sel_reg[28] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[28]_i_1_n_0 ),
        .Q(p_0_in656_in),
        .R(out));
  FDRE \sel_reg[29] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[29]_i_1_n_0 ),
        .Q(p_0_in674_in),
        .R(out));
  FDRE \sel_reg[2] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[2]_i_1_n_0 ),
        .Q(p_0_in188_in),
        .R(out));
  FDRE \sel_reg[30] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[30]_i_1_n_0 ),
        .Q(p_0_in692_in),
        .R(out));
  FDRE \sel_reg[31] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[31]_i_1_n_0 ),
        .Q(p_0_in710_in),
        .R(out));
  FDRE \sel_reg[32] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[32]_i_1_n_0 ),
        .Q(p_0_in728_in),
        .R(out));
  FDRE \sel_reg[33] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[33]_i_1_n_0 ),
        .Q(p_0_in746_in),
        .R(out));
  FDRE \sel_reg[34] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[34]_i_1_n_0 ),
        .Q(p_0_in764_in),
        .R(out));
  FDRE \sel_reg[35] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[35]_i_1_n_0 ),
        .Q(p_0_in782_in),
        .R(out));
  FDRE \sel_reg[36] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[36]_i_1_n_0 ),
        .Q(p_0_in800_in),
        .R(out));
  FDRE \sel_reg[37] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[37]_i_1_n_0 ),
        .Q(p_0_in818_in),
        .R(out));
  FDRE \sel_reg[38] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[38]_i_1_n_0 ),
        .Q(p_0_in836_in),
        .R(out));
  FDRE \sel_reg[39] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[39]_i_1_n_0 ),
        .Q(p_0_in854_in),
        .R(out));
  FDRE \sel_reg[3] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[3]_i_1_n_0 ),
        .Q(p_0_in206_in),
        .R(out));
  FDRE \sel_reg[40] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[40]_i_1_n_0 ),
        .Q(p_0_in872_in),
        .R(out));
  FDRE \sel_reg[41] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[41]_i_1_n_0 ),
        .Q(p_0_in890_in),
        .R(out));
  FDRE \sel_reg[42] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[42]_i_1_n_0 ),
        .Q(p_0_in908_in),
        .R(out));
  FDRE \sel_reg[43] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[43]_i_1_n_0 ),
        .Q(p_0_in926_in),
        .R(out));
  FDRE \sel_reg[44] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[44]_i_1_n_0 ),
        .Q(p_0_in944_in),
        .R(out));
  FDRE \sel_reg[45] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[45]_i_1_n_0 ),
        .Q(p_0_in962_in),
        .R(out));
  FDRE \sel_reg[46] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[46]_i_1_n_0 ),
        .Q(p_0_in980_in),
        .R(out));
  FDRE \sel_reg[47] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[47]_i_1_n_0 ),
        .Q(p_0_in998_in),
        .R(out));
  FDRE \sel_reg[48] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[48]_i_1_n_0 ),
        .Q(p_0_in1016_in),
        .R(out));
  FDRE \sel_reg[49] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[49]_i_1_n_0 ),
        .Q(p_0_in1034_in),
        .R(out));
  FDRE \sel_reg[4] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[4]_i_1_n_0 ),
        .Q(p_0_in224_in),
        .R(out));
  FDRE \sel_reg[50] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[50]_i_1_n_0 ),
        .Q(p_0_in1052_in),
        .R(out));
  FDRE \sel_reg[51] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[51]_i_1_n_0 ),
        .Q(p_0_in1070_in),
        .R(out));
  FDRE \sel_reg[52] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[52]_i_1_n_0 ),
        .Q(p_0_in1088_in),
        .R(out));
  FDRE \sel_reg[53] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[53]_i_1_n_0 ),
        .Q(p_0_in1106_in),
        .R(out));
  FDRE \sel_reg[54] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[54]_i_1_n_0 ),
        .Q(p_0_in1124_in),
        .R(out));
  FDRE \sel_reg[55] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[55]_i_1_n_0 ),
        .Q(p_0_in1142_in),
        .R(out));
  FDRE \sel_reg[56] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[56]_i_1_n_0 ),
        .Q(p_0_in1160_in),
        .R(out));
  FDRE \sel_reg[57] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[57]_i_1_n_0 ),
        .Q(p_0_in1178_in),
        .R(out));
  FDRE \sel_reg[58] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[58]_i_1_n_0 ),
        .Q(p_0_in1196_in),
        .R(out));
  FDRE \sel_reg[59] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[59]_i_1_n_0 ),
        .Q(p_0_in1214_in),
        .R(out));
  FDRE \sel_reg[5] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[5]_i_1_n_0 ),
        .Q(p_0_in242_in),
        .R(out));
  FDRE \sel_reg[60] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[60]_i_1_n_0 ),
        .Q(p_0_in1232_in),
        .R(out));
  FDRE \sel_reg[61] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[61]_i_1_n_0 ),
        .Q(p_0_in1250_in),
        .R(out));
  FDRE \sel_reg[62] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[62]_i_1_n_0 ),
        .Q(p_0_in1268_in),
        .R(out));
  FDRE \sel_reg[63] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[63]_i_1_n_0 ),
        .Q(p_0_in1286_in),
        .R(out));
  FDRE \sel_reg[6] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[6]_i_1_n_0 ),
        .Q(p_0_in260_in),
        .R(out));
  FDRE \sel_reg[7] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[7]_i_1_n_0 ),
        .Q(p_0_in278_in),
        .R(out));
  FDRE \sel_reg[8] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[8]_i_1_n_0 ),
        .Q(p_0_in296_in),
        .R(out));
  FDRE \sel_reg[9] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\sel[9]_i_1_n_0 ),
        .Q(p_0_in314_in),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair513" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \victim_bit_decode[0]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[0]_0 [0]),
        .O(\victim_bit_decode[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair513" *) 
  LUT3 #(
    .INIT(8'h10)) 
    \victim_bit_decode[1]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[0]_0 [0]),
        .O(\victim_bit_decode[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair512" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \victim_bit_decode[2]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[0]_0 [0]),
        .O(\victim_bit_decode[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair512" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \victim_bit_decode[3]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[0]_0 [0]),
        .O(\victim_bit_decode[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair511" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \victim_bit_decode[4]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[0]_0 [0]),
        .O(\victim_bit_decode[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair511" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \victim_bit_decode[5]_i_1 
       (.I0(\sel_reg[0]_0 [1]),
        .I1(\sel_reg[0]_0 [2]),
        .I2(\sel_reg[0]_0 [0]),
        .O(\victim_bit_decode[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair510" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \victim_bit_decode[6]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[0]_0 [0]),
        .O(\victim_bit_decode[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair510" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \victim_bit_decode[7]_i_1 
       (.I0(\sel_reg[0]_0 [2]),
        .I1(\sel_reg[0]_0 [1]),
        .I2(\sel_reg[0]_0 [0]),
        .O(\victim_bit_decode[7]_i_1_n_0 ));
  FDRE \victim_bit_decode_reg[0] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\victim_bit_decode[0]_i_1_n_0 ),
        .Q(\victim_bit_decode_reg_n_0_[0] ),
        .R(out));
  FDRE \victim_bit_decode_reg[1] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\victim_bit_decode[1]_i_1_n_0 ),
        .Q(p_0_in),
        .R(out));
  FDRE \victim_bit_decode_reg[2] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\victim_bit_decode[2]_i_1_n_0 ),
        .Q(p_0_in47_in),
        .R(out));
  FDRE \victim_bit_decode_reg[3] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\victim_bit_decode[3]_i_1_n_0 ),
        .Q(p_0_in65_in),
        .R(out));
  FDRE \victim_bit_decode_reg[4] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\victim_bit_decode[4]_i_1_n_0 ),
        .Q(p_0_in83_in),
        .R(out));
  FDRE \victim_bit_decode_reg[5] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\victim_bit_decode[5]_i_1_n_0 ),
        .Q(p_0_in101_in),
        .R(out));
  FDRE \victim_bit_decode_reg[6] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\victim_bit_decode[6]_i_1_n_0 ),
        .Q(p_0_in119_in),
        .R(out));
  FDRE \victim_bit_decode_reg[7] 
       (.C(\rd_addr_101_reg[7]_0 ),
        .CE(1'b1),
        .D(\victim_bit_decode[7]_i_1_n_0 ),
        .Q(p_0_in137_in),
        .R(out));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_mc_odt" *) 
module ddr4_0_ddr4_v2_2_17_cal_mc_odt
   (mc_ODT,
    \odt_shift_reg[0][18]_0 ,
    \odt_shift_reg[0][18]_1 ,
    \odt_shift_reg[0][18]_2 ,
    winWrite,
    winRead,
    out,
    \odt_shift_reg[0][20]_0 ,
    \odt_shift_reg[0][20]_1 );
  output [0:0]mc_ODT;
  output [1:0]\odt_shift_reg[0][18]_0 ;
  input \odt_shift_reg[0][18]_1 ;
  input \odt_shift_reg[0][18]_2 ;
  input winWrite;
  input winRead;
  input out;
  input [0:0]\odt_shift_reg[0][20]_0 ;
  input \odt_shift_reg[0][20]_1 ;

  wire [0:0]mc_ODT;
  wire [18:16]\odt_shift_nxt[0]_189 ;
  wire [1:0]\odt_shift_reg[0][18]_0 ;
  wire \odt_shift_reg[0][18]_1 ;
  wire \odt_shift_reg[0][18]_2 ;
  wire [0:0]\odt_shift_reg[0][20]_0 ;
  wire \odt_shift_reg[0][20]_1 ;
  wire out;
  wire [4:4]p_0_in;
  wire winRead;
  wire winWrite;

  (* SOFT_HLUTNM = "soft_lutpair2826" *) 
  LUT5 #(
    .INIT(32'hFFFF0040)) 
    \mcal_ODT_dly[0][4]_i_3 
       (.I0(\odt_shift_reg[0][18]_1 ),
        .I1(\odt_shift_reg[0][18]_2 ),
        .I2(winWrite),
        .I3(winRead),
        .I4(p_0_in),
        .O(mc_ODT));
  (* SOFT_HLUTNM = "soft_lutpair2826" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    \odt_shift[0][16]_i_1 
       (.I0(\odt_shift_reg[0][18]_1 ),
        .I1(winRead),
        .I2(winWrite),
        .I3(\odt_shift_reg[0][18]_2 ),
        .O(\odt_shift_nxt[0]_189 [16]));
  LUT4 #(
    .INIT(16'h0080)) 
    \odt_shift[0][18]_i_1 
       (.I0(\odt_shift_reg[0][18]_1 ),
        .I1(\odt_shift_reg[0][18]_2 ),
        .I2(winWrite),
        .I3(winRead),
        .O(\odt_shift_nxt[0]_189 [18]));
  FDRE \odt_shift_reg[0][16] 
       (.C(\odt_shift_reg[0][20]_1 ),
        .CE(1'b1),
        .D(\odt_shift_nxt[0]_189 [16]),
        .Q(\odt_shift_reg[0][18]_0 [0]),
        .R(out));
  FDRE \odt_shift_reg[0][18] 
       (.C(\odt_shift_reg[0][20]_1 ),
        .CE(1'b1),
        .D(\odt_shift_nxt[0]_189 [18]),
        .Q(\odt_shift_reg[0][18]_0 [1]),
        .R(out));
  FDRE \odt_shift_reg[0][20] 
       (.C(\odt_shift_reg[0][20]_1 ),
        .CE(1'b1),
        .D(\odt_shift_reg[0][20]_0 ),
        .Q(p_0_in),
        .R(out));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_mc_odt" *) 
module ddr4_0_ddr4_v2_2_17_cal_mc_odt__parameterized0
   (rdCAS_reg,
    ub_ready_reg,
    rdCAS_reg_0,
    \odt_shift_reg[0][20]_0 ,
    \odt_shift_reg[0][17]_0 ,
    \odt_shift_reg[0][20]_1 ,
    \odt_shift_reg[0][20]_2 ,
    ub_ready,
    mc_ODT,
    \mcal_ODT_dly_reg[0][4] ,
    \mcal_ODT_dly_reg[0][4]_0 ,
    Q,
    out,
    \odt_shift_reg[0][17]_1 );
  output rdCAS_reg;
  output [1:0]ub_ready_reg;
  output [0:0]rdCAS_reg_0;
  input \odt_shift_reg[0][20]_0 ;
  input \odt_shift_reg[0][17]_0 ;
  input \odt_shift_reg[0][20]_1 ;
  input \odt_shift_reg[0][20]_2 ;
  input ub_ready;
  input [0:0]mc_ODT;
  input \mcal_ODT_dly_reg[0][4] ;
  input \mcal_ODT_dly_reg[0][4]_0 ;
  input [1:0]Q;
  input out;
  input \odt_shift_reg[0][17]_1 ;

  wire [1:0]Q;
  wire [0:0]mc_ODT;
  wire \mcal_ODT_dly_reg[0][4] ;
  wire \mcal_ODT_dly_reg[0][4]_0 ;
  wire [20:17]\odt_shift_nxt[0]_279 ;
  wire \odt_shift_reg[0][17]_0 ;
  wire \odt_shift_reg[0][17]_1 ;
  wire \odt_shift_reg[0][20]_0 ;
  wire \odt_shift_reg[0][20]_1 ;
  wire \odt_shift_reg[0][20]_2 ;
  wire out;
  wire [4:1]p_0_in;
  wire rdCAS_reg;
  wire [0:0]rdCAS_reg_0;
  wire [4:4]ub_cal_ODT;
  wire ub_ready;
  wire [1:0]ub_ready_reg;

  (* SOFT_HLUTNM = "soft_lutpair883" *) 
  LUT5 #(
    .INIT(32'hFFFF0004)) 
    \mc_cal_ODT_msb[0]_i_1 
       (.I0(\odt_shift_reg[0][20]_0 ),
        .I1(\odt_shift_reg[0][17]_0 ),
        .I2(\odt_shift_reg[0][20]_1 ),
        .I3(\odt_shift_reg[0][20]_2 ),
        .I4(p_0_in[1]),
        .O(rdCAS_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair884" *) 
  LUT4 #(
    .INIT(16'hF088)) 
    \mcal_ODT_dly[0][2]_i_1 
       (.I0(ub_cal_ODT),
        .I1(ub_ready),
        .I2(mc_ODT),
        .I3(\mcal_ODT_dly_reg[0][4] ),
        .O(ub_ready_reg[0]));
  (* SOFT_HLUTNM = "soft_lutpair884" *) 
  LUT4 #(
    .INIT(16'hF088)) 
    \mcal_ODT_dly[0][4]_i_1 
       (.I0(ub_cal_ODT),
        .I1(ub_ready),
        .I2(mc_ODT),
        .I3(\mcal_ODT_dly_reg[0][4] ),
        .O(ub_ready_reg[1]));
  LUT6 #(
    .INIT(64'hFFFFFFFFE000E0E0)) 
    \mcal_ODT_dly[0][4]_i_2 
       (.I0(\odt_shift_reg[0][20]_0 ),
        .I1(\odt_shift_reg[0][17]_0 ),
        .I2(\mcal_ODT_dly_reg[0][4]_0 ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(p_0_in[4]),
        .O(ub_cal_ODT));
  LUT6 #(
    .INIT(64'hFFFF000400000000)) 
    \mcal_ODT_dly[0][7]_i_2 
       (.I0(\odt_shift_reg[0][20]_0 ),
        .I1(\odt_shift_reg[0][17]_0 ),
        .I2(\odt_shift_reg[0][20]_1 ),
        .I3(\odt_shift_reg[0][20]_2 ),
        .I4(p_0_in[1]),
        .I5(ub_ready),
        .O(rdCAS_reg));
  LUT6 #(
    .INIT(64'h0000000000020000)) 
    \odt_shift[0][17]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(\odt_shift_reg[0][20]_1 ),
        .I3(\odt_shift_reg[0][20]_2 ),
        .I4(\odt_shift_reg[0][17]_0 ),
        .I5(\odt_shift_reg[0][20]_0 ),
        .O(\odt_shift_nxt[0]_279 [17]));
  (* SOFT_HLUTNM = "soft_lutpair883" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \odt_shift[0][20]_i_1 
       (.I0(\odt_shift_reg[0][20]_2 ),
        .I1(\odt_shift_reg[0][20]_1 ),
        .I2(\odt_shift_reg[0][17]_0 ),
        .I3(\odt_shift_reg[0][20]_0 ),
        .O(\odt_shift_nxt[0]_279 [20]));
  FDRE \odt_shift_reg[0][17] 
       (.C(\odt_shift_reg[0][17]_1 ),
        .CE(1'b1),
        .D(\odt_shift_nxt[0]_279 [17]),
        .Q(p_0_in[1]),
        .R(out));
  FDRE \odt_shift_reg[0][20] 
       (.C(\odt_shift_reg[0][17]_1 ),
        .CE(1'b1),
        .D(\odt_shift_nxt[0]_279 [20]),
        .Q(p_0_in[4]),
        .R(out));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_pi" *) 
module ddr4_0_ddr4_v2_2_17_cal_pi
   (mc_clb2phy_fifo_rden_nxt,
    rdDataEn_pi,
    wrDataVal,
    out,
    wrDataEn_pi,
    wosp,
    \oe_0_mux_cal_reg[0] ,
    \wosp_reg[2]_rep ,
    \wosp_reg[2]_rep__0 ,
    \wosp_reg[2]_rep__1 ,
    \wosp_reg[2]_rep__2 ,
    \wosp_reg[2]_rep__3 ,
    \wosp_reg[2]_rep__4 ,
    \wosp_reg[2]_rep__5 ,
    \wosp_reg[2]_rep__6 ,
    \wosp_reg[2]_rep__7 ,
    \rsMask_reg[7][18] ,
    \rsMask_reg[5][18] ,
    \rsMask_reg[3][18] ,
    \rsMask_reg[1][18] ,
    \rsMask_reg[7][18]_0 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[1][18]_0 ,
    pointer_we,
    calDone_reg,
    per_rd_done,
    \wrQ_reg[0][0] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] ,
    \not_strict_mode.status_ram_0.RAM32M0 ,
    \not_strict_mode.bypass_cpy2 ,
    Q,
    \rdData_reg[5] ,
    match6_13_return,
    \rdDataAddr_reg[3]_rep ,
    \rdDataAddr_reg[4]_rep ,
    match4_13_return,
    \rdData_reg[11] ,
    match6_14_return,
    \rdDataAddr_reg[3]_rep__0 ,
    \rdDataAddr_reg[4]_rep__0 ,
    match4_14_return,
    \rdData_reg[17] ,
    match6_15_return,
    \rdDataAddr_reg[3]_rep__1 ,
    \rdDataAddr_reg[4]_rep__1 ,
    match4_15_return,
    \rdData_reg[23] ,
    match6_16_return,
    match4_16_return,
    \rdData_reg[29] ,
    match6_17_return,
    match4_17_return,
    \rdData_reg[35] ,
    match6_18_return,
    match4_18_return,
    \rdData_reg[41] ,
    match6_19_return,
    match4_19_return,
    \rdData_reg[47] ,
    match6_110_return,
    match4_110_return,
    \rdData_reg[53] ,
    match6_111_return,
    match4_111_return,
    \rdData_reg[59] ,
    match6_112_return,
    match4_112_return,
    \rdData_reg[65] ,
    match6_113_return,
    match4_113_return,
    \rdData_reg[71] ,
    match6_114_return,
    match4_114_return,
    \rdData_reg[77] ,
    match6_115_return,
    match4_115_return,
    \rdData_reg[83] ,
    match6_116_return,
    match4_116_return,
    \rdData_reg[89] ,
    match6_117_return,
    match4_117_return,
    \rdData_reg[95] ,
    match6_118_return,
    match4_118_return,
    \rdData_reg[101] ,
    match6_119_return,
    match4_119_return,
    \rdData_reg[107] ,
    match6_120_return,
    match4_120_return,
    \rdData_reg[113] ,
    match6_121_return,
    match4_121_return,
    \rdData_reg[119] ,
    match6_122_return,
    match4_122_return,
    \rdData_reg[125] ,
    match6_123_return,
    match4_123_return,
    \rdData_reg[131] ,
    match6_124_return,
    match4_124_return,
    \rdData_reg[137] ,
    match6_125_return,
    match4_125_return,
    \rdData_reg[143] ,
    match6_126_return,
    match4_126_return,
    \rdData_reg[149] ,
    match6_127_return,
    match4_127_return,
    \rdData_reg[155] ,
    match6_128_return,
    match4_128_return,
    \rdData_reg[161] ,
    match6_129_return,
    match4_129_return,
    \rdData_reg[167] ,
    match6_130_return,
    match4_130_return,
    \rdData_reg[173] ,
    match6_131_return,
    match4_131_return,
    \rdData_reg[179] ,
    match6_132_return,
    match4_132_return,
    \rdData_reg[185] ,
    match6_133_return,
    match4_133_return,
    \rdData_reg[191] ,
    match6_134_return,
    match4_134_return,
    \rdData_reg[197] ,
    match6_135_return,
    match4_135_return,
    \rdData_reg[203] ,
    match6_136_return,
    match4_136_return,
    \rdData_reg[209] ,
    match6_137_return,
    match4_137_return,
    \rdData_reg[215] ,
    match6_138_return,
    match4_138_return,
    \rdData_reg[221] ,
    match6_139_return,
    match4_139_return,
    \rdData_reg[227] ,
    match6_140_return,
    match4_140_return,
    \rdData_reg[233] ,
    match6_141_return,
    match4_141_return,
    \rdData_reg[239] ,
    match6_142_return,
    match4_142_return,
    \rdData_reg[245] ,
    match6_143_return,
    match4_143_return,
    \rdData_reg[251] ,
    match6_144_return,
    match4_144_return,
    \rdData_reg[257] ,
    match6_145_return,
    match4_145_return,
    \rdData_reg[263] ,
    match6_146_return,
    match4_146_return,
    \rdData_reg[269] ,
    match6_147_return,
    match4_147_return,
    \rdData_reg[275] ,
    match6_148_return,
    match4_148_return,
    \rdData_reg[281] ,
    match6_149_return,
    match4_149_return,
    \rdData_reg[287] ,
    match6_150_return,
    match4_150_return,
    \rdData_reg[293] ,
    match6_151_return,
    match4_151_return,
    \rdData_reg[299] ,
    match6_152_return,
    match4_152_return,
    \rdData_reg[305] ,
    match6_153_return,
    match4_153_return,
    \rdData_reg[311] ,
    match6_154_return,
    match4_154_return,
    \rdData_reg[317] ,
    match6_155_return,
    match4_155_return,
    \rdData_reg[323] ,
    match6_156_return,
    match4_156_return,
    \rdData_reg[329] ,
    match6_157_return,
    match4_157_return,
    \rdData_reg[335] ,
    match6_158_return,
    match4_158_return,
    \rdData_reg[341] ,
    match6_159_return,
    match4_159_return,
    \rdData_reg[347] ,
    match6_160_return,
    match4_160_return,
    \rdData_reg[353] ,
    match6_161_return,
    match4_161_return,
    \rdData_reg[359] ,
    match6_162_return,
    match4_162_return,
    \rdData_reg[365] ,
    match6_163_return,
    match4_163_return,
    \rdData_reg[371] ,
    match6_164_return,
    match4_164_return,
    \rdData_reg[377] ,
    match6_165_return,
    match4_165_return,
    \rdData_reg[383] ,
    match6_166_return,
    match4_166_return,
    \rdData_reg[389] ,
    match6_167_return,
    match4_167_return,
    \rdData_reg[395] ,
    match6_168_return,
    match4_168_return,
    \rdData_reg[401] ,
    match6_169_return,
    match4_169_return,
    \rdData_reg[407] ,
    match6_170_return,
    match4_170_return,
    \rdData_reg[413] ,
    match6_171_return,
    match4_171_return,
    \rdData_reg[419] ,
    match6_172_return,
    match4_172_return,
    \rdData_reg[425] ,
    match6_173_return,
    match4_173_return,
    \rdData_reg[431] ,
    match6_174_return,
    match4_174_return,
    \rdData_reg[437] ,
    match6_175_return,
    match4_175_return,
    \rdData_reg[443] ,
    match6_176_return,
    match4_176_return,
    \rdData_reg[449] ,
    match6_177_return,
    match4_177_return,
    \rdData_reg[455] ,
    match6_178_return,
    match4_178_return,
    \rdData_reg[461] ,
    match6_179_return,
    match4_179_return,
    \rdData_reg[467] ,
    match6_180_return,
    match4_180_return,
    \rdData_reg[473] ,
    match6_181_return,
    match4_181_return,
    \rdData_reg[479] ,
    match6_182_return,
    match4_182_return,
    \rdData_reg[485] ,
    match6_183_return,
    match4_183_return,
    \rdData_reg[491] ,
    match6_184_return,
    match4_184_return,
    \rdData_reg[497] ,
    match6_185_return,
    match4_185_return,
    \rdData_reg[503] ,
    match6_186_return,
    match4_186_return,
    \rdData_reg[509] ,
    match6_187_return,
    match4_187_return,
    \rdData_reg[511] ,
    match6_188_return,
    match4_188_return,
    match4_1_return,
    match6_1_return,
    match4_10_return,
    match6_10_return,
    match4_11_return,
    match6_11_return,
    match4_12_return,
    match6_12_return,
    pop_read_lat_fifo_reg,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][17] ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][17]_0 ,
    \rsMask_reg[7][18]_3 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_4 ,
    \rsMask_reg[7][17]_2 ,
    \rsMask_reg[7][18]_5 ,
    \rsMask_reg[7][17]_3 ,
    \rsMask_reg[7][18]_6 ,
    \rsMask_reg[7][17]_4 ,
    \rsMask_reg[7][18]_7 ,
    \rsMask_reg[7][17]_5 ,
    \rsMask_reg[7][18]_8 ,
    \rsMask_reg[7][17]_6 ,
    \rsMask_reg[7][18]_9 ,
    \rsMask_reg[7][17]_7 ,
    \rsMask_reg[7][18]_10 ,
    \rsMask_reg[7][17]_8 ,
    \rsMask_reg[7][18]_11 ,
    \rsMask_reg[7][17]_9 ,
    \rsMask_reg[7][18]_12 ,
    \rsMask_reg[7][17]_10 ,
    \rsMask_reg[7][18]_13 ,
    \rsMask_reg[7][17]_11 ,
    \rsMask_reg[7][18]_14 ,
    \rsMask_reg[7][17]_12 ,
    \wrQ_reg[1][8] ,
    ADDRC,
    \wrQ_reg[0][0]_rep ,
    ADDRA,
    \wrQ_reg[0][8]_rep__0 ,
    \wrQ_reg[0][8]_rep__1 ,
    \oe_upp_reg[3] ,
    \oe_low_reg[3] ,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_DQOut,
    ch0_mcal_DMOut_n,
    ch0_mcal_clb2phy_rden_low,
    \read_lat_shift_reg[31] ,
    phy_rden_or,
    phy_rden_and,
    underfill_done_nxt,
    \rdDataAddr_reg[4] ,
    \rdDataAddr_reg[4]_0 ,
    \rdDataAddr_reg[4]_1 ,
    \dReg_reg[10] ,
    cal_oe_dis_upp,
    cal_oe_dis_low,
    \oe_0_mux_cal_reg[0]_0 ,
    in0,
    \rdEn_reg[29] ,
    \rsMask_reg[7][2] ,
    \rsMask_reg[5][2] ,
    \rsMask_reg[3][2] ,
    \rsMask_reg[1][12] ,
    \rsMask_reg[7][3] ,
    \rsMask_reg[5][3] ,
    \rsMask_reg[3][3] ,
    \rsMask_reg[7][10] ,
    \rsMask_reg[5][10] ,
    \rsMask_reg[3][10] ,
    \rsMask_reg[7][12] ,
    \rsMask_reg[5][12] ,
    \rsMask_reg[3][12] ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    \rsMask_reg[1][12]_0 ,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_1 ,
    \rsMask_reg[1][6] ,
    \rsMask_reg[1][15] ,
    \rsMask_reg[1][16] ,
    \rsMask_reg[1][17] ,
    \rsMask_reg[1][18]_2 ,
    \blk1.(null)[0].diff ,
    \rsMask_reg[1][8] ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][6] ,
    \rsMask_reg[3][15] ,
    \rsMask_reg[3][16] ,
    \rsMask_reg[3][17] ,
    \rsMask_reg[3][18]_2 ,
    \rsMask_reg[3][9] ,
    \rsMask_reg[3][8] ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][6] ,
    \rsMask_reg[5][15] ,
    \rsMask_reg[5][16] ,
    \rsMask_reg[5][17] ,
    \rsMask_reg[5][18]_2 ,
    \rsMask_reg[5][9] ,
    \rsMask_reg[5][8] ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[7][18]_15 ,
    \rsMask_reg[7][6] ,
    \rsMask_reg[7][15] ,
    \rsMask_reg[7][16] ,
    \rsMask_reg[7][17]_13 ,
    \rsMask_reg[7][18]_16 ,
    \rsMask_reg[7][9] ,
    \rsMask_reg[7][8] ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[1][18]_3 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_4 ,
    \blk1.(null)[0].diff_0 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_3 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_4 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_2 ,
    \rsMask_reg[5][18]_3 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_4 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_2 ,
    \rsMask_reg[7][18]_17 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_14 ,
    \rsMask_reg[7][18]_18 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_2 ,
    SR,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_1 ,
    \rsMask_reg[5][2]_1 ,
    \rsMask_reg[3][2]_1 ,
    rs2mask0,
    \rsMask_reg[7][3]_1 ,
    \rsMask_reg[5][3]_1 ,
    \rsMask_reg[3][3]_1 ,
    \rsMask_reg[7][10]_1 ,
    \rsMask_reg[5][10]_1 ,
    \rsMask_reg[3][10]_1 ,
    \rsMask_reg[7][12]_1 ,
    \rsMask_reg[5][12]_1 ,
    \rsMask_reg[3][12]_1 ,
    \rsMask_reg[1][18]_5 ,
    \rsMask_reg[1][6]_1 ,
    \rsMask_reg[1][15]_1 ,
    \rsMask_reg[1][16]_1 ,
    \rsMask_reg[1][17]_1 ,
    \rsMask_reg[1][18]_6 ,
    \blk1.(null)[0].diff_1 ,
    \rsMask_reg[1][8]_1 ,
    \rsMask_reg[3][18]_5 ,
    \rsMask_reg[3][6]_1 ,
    \rsMask_reg[3][15]_1 ,
    \rsMask_reg[3][16]_1 ,
    \rsMask_reg[3][17]_1 ,
    \rsMask_reg[3][18]_6 ,
    \rsMask_reg[3][9]_3 ,
    \rsMask_reg[3][8]_1 ,
    \rsMask_reg[3][9]_4 ,
    \rsMask_reg[5][18]_5 ,
    \rsMask_reg[5][6]_1 ,
    \rsMask_reg[5][15]_1 ,
    \rsMask_reg[5][16]_1 ,
    \rsMask_reg[5][17]_1 ,
    \rsMask_reg[5][18]_6 ,
    \rsMask_reg[5][9]_3 ,
    \rsMask_reg[5][8]_1 ,
    \rsMask_reg[5][9]_4 ,
    \rsMask_reg[7][18]_19 ,
    \rsMask_reg[7][6]_1 ,
    \rsMask_reg[7][15]_1 ,
    \rsMask_reg[7][16]_1 ,
    \rsMask_reg[7][17]_15 ,
    \rsMask_reg[7][18]_20 ,
    \rsMask_reg[7][9]_3 ,
    \rsMask_reg[7][8]_1 ,
    \rsMask_reg[7][9]_4 ,
    \rdEn_reg[29]_1 ,
    \rsMask_reg[7][2]_2 ,
    \rsMask_reg[5][2]_2 ,
    \rsMask_reg[3][2]_2 ,
    rs2mask0_2,
    \rsMask_reg[7][3]_2 ,
    \rsMask_reg[5][3]_2 ,
    \rsMask_reg[3][3]_2 ,
    \rsMask_reg[7][10]_2 ,
    \rsMask_reg[5][10]_2 ,
    \rsMask_reg[3][10]_2 ,
    \rsMask_reg[7][12]_2 ,
    \rsMask_reg[5][12]_2 ,
    \rsMask_reg[3][12]_2 ,
    \rsMask_reg[1][18]_7 ,
    \rsMask_reg[1][6]_2 ,
    \rsMask_reg[1][15]_2 ,
    \rsMask_reg[1][16]_2 ,
    \rsMask_reg[1][17]_2 ,
    \rsMask_reg[1][18]_8 ,
    \blk1.(null)[0].diff_3 ,
    \rsMask_reg[1][8]_2 ,
    \rsMask_reg[3][18]_7 ,
    \rsMask_reg[3][6]_2 ,
    \rsMask_reg[3][15]_2 ,
    \rsMask_reg[3][16]_2 ,
    \rsMask_reg[3][17]_2 ,
    \rsMask_reg[3][18]_8 ,
    \rsMask_reg[3][9]_5 ,
    \rsMask_reg[3][8]_2 ,
    \rsMask_reg[3][9]_6 ,
    \rsMask_reg[5][18]_7 ,
    \rsMask_reg[5][6]_2 ,
    \rsMask_reg[5][15]_2 ,
    \rsMask_reg[5][16]_2 ,
    \rsMask_reg[5][17]_2 ,
    \rsMask_reg[5][18]_8 ,
    \rsMask_reg[5][9]_5 ,
    \rsMask_reg[5][8]_2 ,
    \rsMask_reg[5][9]_6 ,
    \rsMask_reg[7][18]_21 ,
    \rsMask_reg[7][6]_2 ,
    \rsMask_reg[7][15]_2 ,
    \rsMask_reg[7][16]_2 ,
    \rsMask_reg[7][17]_16 ,
    \rsMask_reg[7][18]_22 ,
    \rsMask_reg[7][9]_5 ,
    \rsMask_reg[7][8]_2 ,
    \rsMask_reg[7][9]_6 ,
    \rdEn_reg[29]_2 ,
    \rsMask_reg[7][2]_3 ,
    \rsMask_reg[5][2]_3 ,
    \rsMask_reg[3][2]_3 ,
    rs2mask0_4,
    \rsMask_reg[7][3]_3 ,
    \rsMask_reg[5][3]_3 ,
    \rsMask_reg[3][3]_3 ,
    \rsMask_reg[7][10]_3 ,
    \rsMask_reg[5][10]_3 ,
    \rsMask_reg[3][10]_3 ,
    \rsMask_reg[7][12]_3 ,
    \rsMask_reg[5][12]_3 ,
    \rsMask_reg[3][12]_3 ,
    \rsMask_reg[1][18]_9 ,
    \rsMask_reg[1][6]_3 ,
    \rsMask_reg[1][15]_3 ,
    \rsMask_reg[1][16]_3 ,
    \rsMask_reg[1][17]_3 ,
    \rsMask_reg[1][18]_10 ,
    \blk1.(null)[0].diff_5 ,
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    \rsMask_reg[3][18]_9 ,
    \rsMask_reg[3][6]_3 ,
    \rsMask_reg[3][15]_3 ,
    \rsMask_reg[3][16]_3 ,
    \rsMask_reg[3][17]_3 ,
    \rsMask_reg[3][18]_10 ,
    \rsMask_reg[3][9]_7 ,
    \rsMask_reg[3][8]_3 ,
    \rsMask_reg[3][9]_8 ,
    \rsMask_reg[5][18]_9 ,
    \rsMask_reg[5][6]_3 ,
    \rsMask_reg[5][15]_3 ,
    \rsMask_reg[5][16]_3 ,
    \rsMask_reg[5][17]_3 ,
    \rsMask_reg[5][18]_10 ,
    \rsMask_reg[5][9]_7 ,
    \rsMask_reg[5][8]_3 ,
    \rsMask_reg[5][9]_8 ,
    \rsMask_reg[7][18]_23 ,
    \rsMask_reg[7][6]_3 ,
    \rsMask_reg[7][15]_3 ,
    \rsMask_reg[7][16]_3 ,
    \rsMask_reg[7][17]_17 ,
    \rsMask_reg[7][18]_24 ,
    \rsMask_reg[7][9]_7 ,
    \rsMask_reg[7][8]_3 ,
    \rsMask_reg[7][9]_8 ,
    \rdEn_reg[29]_3 ,
    \rsMask_reg[7][2]_4 ,
    \rsMask_reg[5][2]_4 ,
    \rsMask_reg[3][2]_4 ,
    rs2mask0_6,
    \rsMask_reg[7][3]_4 ,
    \rsMask_reg[5][3]_4 ,
    \rsMask_reg[3][3]_4 ,
    \rsMask_reg[7][10]_4 ,
    \rsMask_reg[5][10]_4 ,
    \rsMask_reg[3][10]_4 ,
    \rsMask_reg[7][12]_4 ,
    \rsMask_reg[5][12]_4 ,
    \rsMask_reg[3][12]_4 ,
    \rsMask_reg[1][18]_11 ,
    \rsMask_reg[1][6]_4 ,
    \rsMask_reg[1][15]_4 ,
    \rsMask_reg[1][16]_4 ,
    \rsMask_reg[1][17]_4 ,
    \rsMask_reg[1][18]_12 ,
    \blk1.(null)[0].diff_7 ,
    \rsMask_reg[1][8]_4 ,
    \rsMask_reg[3][18]_11 ,
    \rsMask_reg[3][6]_4 ,
    \rsMask_reg[3][15]_4 ,
    \rsMask_reg[3][16]_4 ,
    \rsMask_reg[3][17]_4 ,
    \rsMask_reg[3][18]_12 ,
    \rsMask_reg[3][9]_9 ,
    \rsMask_reg[3][8]_4 ,
    \rsMask_reg[3][9]_10 ,
    \rsMask_reg[5][18]_11 ,
    \rsMask_reg[5][6]_4 ,
    \rsMask_reg[5][15]_4 ,
    \rsMask_reg[5][16]_4 ,
    \rsMask_reg[5][17]_4 ,
    \rsMask_reg[5][18]_12 ,
    \rsMask_reg[5][9]_9 ,
    \rsMask_reg[5][8]_4 ,
    \rsMask_reg[5][9]_10 ,
    \rsMask_reg[7][18]_25 ,
    \rsMask_reg[7][6]_4 ,
    \rsMask_reg[7][15]_4 ,
    \rsMask_reg[7][16]_4 ,
    \rsMask_reg[7][17]_18 ,
    \rsMask_reg[7][18]_26 ,
    \rsMask_reg[7][9]_9 ,
    \rsMask_reg[7][8]_4 ,
    \rsMask_reg[7][9]_10 ,
    \rdEn_reg[29]_4 ,
    \rsMask_reg[7][2]_5 ,
    \rsMask_reg[5][2]_5 ,
    \rsMask_reg[3][2]_5 ,
    rs2mask0_8,
    \rsMask_reg[7][3]_5 ,
    \rsMask_reg[5][3]_5 ,
    \rsMask_reg[3][3]_5 ,
    \rsMask_reg[7][10]_5 ,
    \rsMask_reg[5][10]_5 ,
    \rsMask_reg[3][10]_5 ,
    \rsMask_reg[7][12]_5 ,
    \rsMask_reg[5][12]_5 ,
    \rsMask_reg[3][12]_5 ,
    \rsMask_reg[1][18]_13 ,
    \rsMask_reg[1][6]_5 ,
    \rsMask_reg[1][15]_5 ,
    \rsMask_reg[1][16]_5 ,
    \rsMask_reg[1][17]_5 ,
    \rsMask_reg[1][18]_14 ,
    \blk1.(null)[0].diff_9 ,
    \rsMask_reg[1][8]_5 ,
    \rsMask_reg[3][18]_13 ,
    \rsMask_reg[3][6]_5 ,
    \rsMask_reg[3][15]_5 ,
    \rsMask_reg[3][16]_5 ,
    \rsMask_reg[3][17]_5 ,
    \rsMask_reg[3][18]_14 ,
    \rsMask_reg[3][9]_11 ,
    \rsMask_reg[3][8]_5 ,
    \rsMask_reg[3][9]_12 ,
    \rsMask_reg[5][18]_13 ,
    \rsMask_reg[5][6]_5 ,
    \rsMask_reg[5][15]_5 ,
    \rsMask_reg[5][16]_5 ,
    \rsMask_reg[5][17]_5 ,
    \rsMask_reg[5][18]_14 ,
    \rsMask_reg[5][9]_11 ,
    \rsMask_reg[5][8]_5 ,
    \rsMask_reg[5][9]_12 ,
    \rsMask_reg[7][18]_27 ,
    \rsMask_reg[7][6]_5 ,
    \rsMask_reg[7][15]_5 ,
    \rsMask_reg[7][16]_5 ,
    \rsMask_reg[7][17]_19 ,
    \rsMask_reg[7][18]_28 ,
    \rsMask_reg[7][9]_11 ,
    \rsMask_reg[7][8]_5 ,
    \rsMask_reg[7][9]_12 ,
    \rdEn_reg[29]_5 ,
    \rsMask_reg[7][2]_6 ,
    \rsMask_reg[5][2]_6 ,
    \rsMask_reg[3][2]_6 ,
    rs2mask0_10,
    \rsMask_reg[7][3]_6 ,
    \rsMask_reg[5][3]_6 ,
    \rsMask_reg[3][3]_6 ,
    \rsMask_reg[7][10]_6 ,
    \rsMask_reg[5][10]_6 ,
    \rsMask_reg[3][10]_6 ,
    \rsMask_reg[7][12]_6 ,
    \rsMask_reg[5][12]_6 ,
    \rsMask_reg[3][12]_6 ,
    \rsMask_reg[1][18]_15 ,
    \rsMask_reg[1][6]_6 ,
    \rsMask_reg[1][15]_6 ,
    \rsMask_reg[1][16]_6 ,
    \rsMask_reg[1][17]_6 ,
    \rsMask_reg[1][18]_16 ,
    \blk1.(null)[0].diff_11 ,
    \rsMask_reg[1][8]_6 ,
    \rsMask_reg[3][18]_15 ,
    \rsMask_reg[3][6]_6 ,
    \rsMask_reg[3][15]_6 ,
    \rsMask_reg[3][16]_6 ,
    \rsMask_reg[3][17]_6 ,
    \rsMask_reg[3][18]_16 ,
    \rsMask_reg[3][9]_13 ,
    \rsMask_reg[3][8]_6 ,
    \rsMask_reg[3][9]_14 ,
    \rsMask_reg[5][18]_15 ,
    \rsMask_reg[5][6]_6 ,
    \rsMask_reg[5][15]_6 ,
    \rsMask_reg[5][16]_6 ,
    \rsMask_reg[5][17]_6 ,
    \rsMask_reg[5][18]_16 ,
    \rsMask_reg[5][9]_13 ,
    \rsMask_reg[5][8]_6 ,
    \rsMask_reg[5][9]_14 ,
    \rsMask_reg[7][18]_29 ,
    \rsMask_reg[7][6]_6 ,
    \rsMask_reg[7][15]_6 ,
    \rsMask_reg[7][16]_6 ,
    \rsMask_reg[7][17]_20 ,
    \rsMask_reg[7][18]_30 ,
    \rsMask_reg[7][9]_13 ,
    \rsMask_reg[7][8]_6 ,
    \rsMask_reg[7][9]_14 ,
    \rdEn_reg[29]_6 ,
    \rsMask_reg[7][2]_7 ,
    \rsMask_reg[5][2]_7 ,
    \rsMask_reg[3][2]_7 ,
    rs2mask0_12,
    \rsMask_reg[7][3]_7 ,
    \rsMask_reg[5][3]_7 ,
    \rsMask_reg[3][3]_7 ,
    \rsMask_reg[7][10]_7 ,
    \rsMask_reg[5][10]_7 ,
    \rsMask_reg[3][10]_7 ,
    \rsMask_reg[7][12]_7 ,
    \rsMask_reg[5][12]_7 ,
    \rsMask_reg[3][12]_7 ,
    \rsMask_reg[1][18]_17 ,
    \rsMask_reg[1][6]_7 ,
    \rsMask_reg[1][15]_7 ,
    \rsMask_reg[1][16]_7 ,
    \rsMask_reg[1][17]_7 ,
    \rsMask_reg[1][18]_18 ,
    \blk1.(null)[0].diff_13 ,
    \rsMask_reg[1][8]_7 ,
    \rsMask_reg[3][18]_17 ,
    \rsMask_reg[3][6]_7 ,
    \rsMask_reg[3][15]_7 ,
    \rsMask_reg[3][16]_7 ,
    \rsMask_reg[3][17]_7 ,
    \rsMask_reg[3][18]_18 ,
    \rsMask_reg[3][9]_15 ,
    \rsMask_reg[3][8]_7 ,
    \rsMask_reg[3][9]_16 ,
    \rsMask_reg[5][18]_17 ,
    \rsMask_reg[5][6]_7 ,
    \rsMask_reg[5][15]_7 ,
    \rsMask_reg[5][16]_7 ,
    \rsMask_reg[5][17]_7 ,
    \rsMask_reg[5][18]_18 ,
    \rsMask_reg[5][9]_15 ,
    \rsMask_reg[5][8]_7 ,
    \rsMask_reg[5][9]_16 ,
    \rsMask_reg[7][18]_31 ,
    \rsMask_reg[7][6]_7 ,
    \rsMask_reg[7][15]_7 ,
    \rsMask_reg[7][16]_7 ,
    \rsMask_reg[7][17]_21 ,
    \rsMask_reg[7][18]_32 ,
    \rsMask_reg[7][9]_15 ,
    \rsMask_reg[7][8]_7 ,
    \rsMask_reg[7][9]_16 ,
    \rdEn_reg[29]_7 ,
    \rsMask_reg[7][2]_8 ,
    \rsMask_reg[5][2]_8 ,
    \rsMask_reg[3][2]_8 ,
    rs2mask0_14,
    \rsMask_reg[7][3]_8 ,
    \rsMask_reg[5][3]_8 ,
    \rsMask_reg[3][3]_8 ,
    \rsMask_reg[7][10]_8 ,
    \rsMask_reg[5][10]_8 ,
    \rsMask_reg[3][10]_8 ,
    \rsMask_reg[7][12]_8 ,
    \rsMask_reg[5][12]_8 ,
    \rsMask_reg[3][12]_8 ,
    \rsMask_reg[1][18]_19 ,
    \rsMask_reg[1][6]_8 ,
    \rsMask_reg[1][15]_8 ,
    \rsMask_reg[1][16]_8 ,
    \rsMask_reg[1][17]_8 ,
    \rsMask_reg[1][18]_20 ,
    \blk1.(null)[0].diff_15 ,
    \rsMask_reg[1][8]_8 ,
    \rsMask_reg[3][18]_19 ,
    \rsMask_reg[3][6]_8 ,
    \rsMask_reg[3][15]_8 ,
    \rsMask_reg[3][16]_8 ,
    \rsMask_reg[3][17]_8 ,
    \rsMask_reg[3][18]_20 ,
    \rsMask_reg[3][9]_17 ,
    \rsMask_reg[3][8]_8 ,
    \rsMask_reg[3][9]_18 ,
    \rsMask_reg[5][18]_19 ,
    \rsMask_reg[5][6]_8 ,
    \rsMask_reg[5][15]_8 ,
    \rsMask_reg[5][16]_8 ,
    \rsMask_reg[5][17]_8 ,
    \rsMask_reg[5][18]_20 ,
    \rsMask_reg[5][9]_17 ,
    \rsMask_reg[5][8]_8 ,
    \rsMask_reg[5][9]_18 ,
    \rsMask_reg[7][18]_33 ,
    \rsMask_reg[7][6]_8 ,
    \rsMask_reg[7][15]_8 ,
    \rsMask_reg[7][16]_8 ,
    \rsMask_reg[7][17]_22 ,
    \rsMask_reg[7][18]_34 ,
    \rsMask_reg[7][9]_17 ,
    \rsMask_reg[7][8]_8 ,
    \rsMask_reg[7][9]_18 ,
    \rdEn_reg[29]_8 ,
    \rsMask_reg[7][2]_9 ,
    \rsMask_reg[5][2]_9 ,
    \rsMask_reg[3][2]_9 ,
    rs2mask0_16,
    \rsMask_reg[7][3]_9 ,
    \rsMask_reg[5][3]_9 ,
    \rsMask_reg[3][3]_9 ,
    \rsMask_reg[7][10]_9 ,
    \rsMask_reg[5][10]_9 ,
    \rsMask_reg[3][10]_9 ,
    \rsMask_reg[7][12]_9 ,
    \rsMask_reg[5][12]_9 ,
    \rsMask_reg[3][12]_9 ,
    \rsMask_reg[1][18]_21 ,
    \rsMask_reg[1][6]_9 ,
    \rsMask_reg[1][15]_9 ,
    \rsMask_reg[1][16]_9 ,
    \rsMask_reg[1][17]_9 ,
    \rsMask_reg[1][18]_22 ,
    \blk1.(null)[0].diff_17 ,
    \rsMask_reg[1][8]_9 ,
    \rsMask_reg[3][18]_21 ,
    \rsMask_reg[3][6]_9 ,
    \rsMask_reg[3][15]_9 ,
    \rsMask_reg[3][16]_9 ,
    \rsMask_reg[3][17]_9 ,
    \rsMask_reg[3][18]_22 ,
    \rsMask_reg[3][9]_19 ,
    \rsMask_reg[3][8]_9 ,
    \rsMask_reg[3][9]_20 ,
    \rsMask_reg[5][18]_21 ,
    \rsMask_reg[5][6]_9 ,
    \rsMask_reg[5][15]_9 ,
    \rsMask_reg[5][16]_9 ,
    \rsMask_reg[5][17]_9 ,
    \rsMask_reg[5][18]_22 ,
    \rsMask_reg[5][9]_19 ,
    \rsMask_reg[5][8]_9 ,
    \rsMask_reg[5][9]_20 ,
    \rsMask_reg[7][18]_35 ,
    \rsMask_reg[7][6]_9 ,
    \rsMask_reg[7][15]_9 ,
    \rsMask_reg[7][16]_9 ,
    \rsMask_reg[7][17]_23 ,
    \rsMask_reg[7][18]_36 ,
    \rsMask_reg[7][9]_19 ,
    \rsMask_reg[7][8]_9 ,
    \rsMask_reg[7][9]_20 ,
    \rdEn_reg[29]_9 ,
    \rsMask_reg[7][2]_10 ,
    \rsMask_reg[5][2]_10 ,
    \rsMask_reg[3][2]_10 ,
    rs2mask0_18,
    \rsMask_reg[7][3]_10 ,
    \rsMask_reg[5][3]_10 ,
    \rsMask_reg[3][3]_10 ,
    \rsMask_reg[7][10]_10 ,
    \rsMask_reg[5][10]_10 ,
    \rsMask_reg[3][10]_10 ,
    \rsMask_reg[7][12]_10 ,
    \rsMask_reg[5][12]_10 ,
    \rsMask_reg[3][12]_10 ,
    \rsMask_reg[1][18]_23 ,
    \rsMask_reg[1][6]_10 ,
    \rsMask_reg[1][15]_10 ,
    \rsMask_reg[1][16]_10 ,
    \rsMask_reg[1][17]_10 ,
    \rsMask_reg[1][18]_24 ,
    \blk1.(null)[0].diff_19 ,
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    \rsMask_reg[3][18]_23 ,
    \rsMask_reg[3][6]_10 ,
    \rsMask_reg[3][15]_10 ,
    \rsMask_reg[3][16]_10 ,
    \rsMask_reg[3][17]_10 ,
    \rsMask_reg[3][18]_24 ,
    \rsMask_reg[3][9]_21 ,
    \rsMask_reg[3][8]_10 ,
    \rsMask_reg[3][9]_22 ,
    \rsMask_reg[5][18]_23 ,
    \rsMask_reg[5][6]_10 ,
    \rsMask_reg[5][15]_10 ,
    \rsMask_reg[5][16]_10 ,
    \rsMask_reg[5][17]_10 ,
    \rsMask_reg[5][18]_24 ,
    \rsMask_reg[5][9]_21 ,
    \rsMask_reg[5][8]_10 ,
    \rsMask_reg[5][9]_22 ,
    \rsMask_reg[7][18]_37 ,
    \rsMask_reg[7][6]_10 ,
    \rsMask_reg[7][15]_10 ,
    \rsMask_reg[7][16]_10 ,
    \rsMask_reg[7][17]_24 ,
    \rsMask_reg[7][18]_38 ,
    \rsMask_reg[7][9]_21 ,
    \rsMask_reg[7][8]_10 ,
    \rsMask_reg[7][9]_22 ,
    \rdEn_reg[29]_10 ,
    \rsMask_reg[7][2]_11 ,
    \rsMask_reg[5][2]_11 ,
    \rsMask_reg[3][2]_11 ,
    rs2mask0_20,
    \rsMask_reg[7][3]_11 ,
    \rsMask_reg[5][3]_11 ,
    \rsMask_reg[3][3]_11 ,
    \rsMask_reg[7][10]_11 ,
    \rsMask_reg[5][10]_11 ,
    \rsMask_reg[3][10]_11 ,
    \rsMask_reg[7][12]_11 ,
    \rsMask_reg[5][12]_11 ,
    \rsMask_reg[3][12]_11 ,
    \rsMask_reg[1][18]_25 ,
    \rsMask_reg[1][6]_11 ,
    \rsMask_reg[1][15]_11 ,
    \rsMask_reg[1][16]_11 ,
    \rsMask_reg[1][17]_11 ,
    \rsMask_reg[1][18]_26 ,
    \blk1.(null)[0].diff_21 ,
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    \rsMask_reg[3][18]_25 ,
    \rsMask_reg[3][6]_11 ,
    \rsMask_reg[3][15]_11 ,
    \rsMask_reg[3][16]_11 ,
    \rsMask_reg[3][17]_11 ,
    \rsMask_reg[3][18]_26 ,
    \rsMask_reg[3][9]_23 ,
    \rsMask_reg[3][8]_11 ,
    \rsMask_reg[3][9]_24 ,
    \rsMask_reg[5][18]_25 ,
    \rsMask_reg[5][6]_11 ,
    \rsMask_reg[5][15]_11 ,
    \rsMask_reg[5][16]_11 ,
    \rsMask_reg[5][17]_11 ,
    \rsMask_reg[5][18]_26 ,
    \rsMask_reg[5][9]_23 ,
    \rsMask_reg[5][8]_11 ,
    \rsMask_reg[5][9]_24 ,
    \rsMask_reg[7][18]_39 ,
    \rsMask_reg[7][6]_11 ,
    \rsMask_reg[7][15]_11 ,
    \rsMask_reg[7][16]_11 ,
    \rsMask_reg[7][17]_25 ,
    \rsMask_reg[7][18]_40 ,
    \rsMask_reg[7][9]_23 ,
    \rsMask_reg[7][8]_11 ,
    \rsMask_reg[7][9]_24 ,
    \rdEn_reg[29]_11 ,
    \rsMask_reg[7][2]_12 ,
    \rsMask_reg[5][2]_12 ,
    \rsMask_reg[3][2]_12 ,
    rs2mask0_22,
    \rsMask_reg[7][3]_12 ,
    \rsMask_reg[5][3]_12 ,
    \rsMask_reg[3][3]_12 ,
    \rsMask_reg[7][10]_12 ,
    \rsMask_reg[5][10]_12 ,
    \rsMask_reg[3][10]_12 ,
    \rsMask_reg[7][12]_12 ,
    \rsMask_reg[5][12]_12 ,
    \rsMask_reg[3][12]_12 ,
    \rsMask_reg[1][18]_27 ,
    \rsMask_reg[1][6]_12 ,
    \rsMask_reg[1][15]_12 ,
    \rsMask_reg[1][16]_12 ,
    \rsMask_reg[1][17]_12 ,
    \rsMask_reg[1][18]_28 ,
    \blk1.(null)[0].diff_23 ,
    \rsMask_reg[1][8]_12 ,
    \rsMask_reg[3][18]_27 ,
    \rsMask_reg[3][6]_12 ,
    \rsMask_reg[3][15]_12 ,
    \rsMask_reg[3][16]_12 ,
    \rsMask_reg[3][17]_12 ,
    \rsMask_reg[3][18]_28 ,
    \rsMask_reg[3][9]_25 ,
    \rsMask_reg[3][8]_12 ,
    \rsMask_reg[3][9]_26 ,
    \rsMask_reg[5][18]_27 ,
    \rsMask_reg[5][6]_12 ,
    \rsMask_reg[5][15]_12 ,
    \rsMask_reg[5][16]_12 ,
    \rsMask_reg[5][17]_12 ,
    \rsMask_reg[5][18]_28 ,
    \rsMask_reg[5][9]_25 ,
    \rsMask_reg[5][8]_12 ,
    \rsMask_reg[5][9]_26 ,
    \rsMask_reg[7][18]_41 ,
    \rsMask_reg[7][6]_12 ,
    \rsMask_reg[7][15]_12 ,
    \rsMask_reg[7][16]_12 ,
    \rsMask_reg[7][17]_26 ,
    \rsMask_reg[7][18]_42 ,
    \rsMask_reg[7][9]_25 ,
    \rsMask_reg[7][8]_12 ,
    \rsMask_reg[7][9]_26 ,
    \rdEn_reg[29]_12 ,
    \rsMask_reg[7][2]_13 ,
    \rsMask_reg[5][2]_13 ,
    \rsMask_reg[3][2]_13 ,
    rs2mask0_24,
    \rsMask_reg[7][3]_13 ,
    \rsMask_reg[5][3]_13 ,
    \rsMask_reg[3][3]_13 ,
    \rsMask_reg[7][10]_13 ,
    \rsMask_reg[5][10]_13 ,
    \rsMask_reg[3][10]_13 ,
    \rsMask_reg[7][12]_13 ,
    \rsMask_reg[5][12]_13 ,
    \rsMask_reg[3][12]_13 ,
    \rsMask_reg[1][18]_29 ,
    \rsMask_reg[1][6]_13 ,
    \rsMask_reg[1][15]_13 ,
    \rsMask_reg[1][16]_13 ,
    \rsMask_reg[1][17]_13 ,
    \rsMask_reg[1][18]_30 ,
    \blk1.(null)[0].diff_25 ,
    \rsMask_reg[1][8]_13 ,
    \rsMask_reg[3][18]_29 ,
    \rsMask_reg[3][6]_13 ,
    \rsMask_reg[3][15]_13 ,
    \rsMask_reg[3][16]_13 ,
    \rsMask_reg[3][17]_13 ,
    \rsMask_reg[3][18]_30 ,
    \rsMask_reg[3][9]_27 ,
    \rsMask_reg[3][8]_13 ,
    \rsMask_reg[3][9]_28 ,
    \rsMask_reg[5][18]_29 ,
    \rsMask_reg[5][6]_13 ,
    \rsMask_reg[5][15]_13 ,
    \rsMask_reg[5][16]_13 ,
    \rsMask_reg[5][17]_13 ,
    \rsMask_reg[5][18]_30 ,
    \rsMask_reg[5][9]_27 ,
    \rsMask_reg[5][8]_13 ,
    \rsMask_reg[5][9]_28 ,
    \rsMask_reg[7][18]_43 ,
    \rsMask_reg[7][6]_13 ,
    \rsMask_reg[7][15]_13 ,
    \rsMask_reg[7][16]_13 ,
    \rsMask_reg[7][17]_27 ,
    \rsMask_reg[7][18]_44 ,
    \rsMask_reg[7][9]_27 ,
    \rsMask_reg[7][8]_13 ,
    \rsMask_reg[7][9]_28 ,
    \rdEn_reg[29]_13 ,
    \rsMask_reg[7][2]_14 ,
    \rsMask_reg[5][2]_14 ,
    \rsMask_reg[3][2]_14 ,
    rs2mask0_26,
    \rsMask_reg[7][3]_14 ,
    \rsMask_reg[5][3]_14 ,
    \rsMask_reg[3][3]_14 ,
    \rsMask_reg[7][10]_14 ,
    \rsMask_reg[5][10]_14 ,
    \rsMask_reg[3][10]_14 ,
    \rsMask_reg[7][12]_14 ,
    \rsMask_reg[5][12]_14 ,
    \rsMask_reg[3][12]_14 ,
    \rsMask_reg[1][18]_31 ,
    \rsMask_reg[1][6]_14 ,
    \rsMask_reg[1][15]_14 ,
    \rsMask_reg[1][16]_14 ,
    \rsMask_reg[1][17]_14 ,
    \rsMask_reg[1][18]_32 ,
    \blk1.(null)[0].diff_27 ,
    \rsMask_reg[1][8]_14 ,
    \rsMask_reg[3][18]_31 ,
    \rsMask_reg[3][6]_14 ,
    \rsMask_reg[3][15]_14 ,
    \rsMask_reg[3][16]_14 ,
    \rsMask_reg[3][17]_14 ,
    \rsMask_reg[3][18]_32 ,
    \rsMask_reg[3][9]_29 ,
    \rsMask_reg[3][8]_14 ,
    \rsMask_reg[3][9]_30 ,
    \rsMask_reg[5][18]_31 ,
    \rsMask_reg[5][6]_14 ,
    \rsMask_reg[5][15]_14 ,
    \rsMask_reg[5][16]_14 ,
    \rsMask_reg[5][17]_14 ,
    \rsMask_reg[5][18]_32 ,
    \rsMask_reg[5][9]_29 ,
    \rsMask_reg[5][8]_14 ,
    \rsMask_reg[5][9]_30 ,
    \rsMask_reg[7][18]_45 ,
    \rsMask_reg[7][6]_14 ,
    \rsMask_reg[7][15]_14 ,
    \rsMask_reg[7][16]_14 ,
    \rsMask_reg[7][17]_28 ,
    \rsMask_reg[7][18]_46 ,
    \rsMask_reg[7][9]_29 ,
    \rsMask_reg[7][8]_14 ,
    \rsMask_reg[7][9]_30 ,
    \rsMask_reg[1][11] ,
    \rsMask_reg[3][11] ,
    \rsMask_reg[5][11] ,
    \rsMask_reg[7][11] ,
    mcRdCAS,
    \oe_low_reg[5] ,
    calRdCAS,
    read_lat_shift_cal_dq_valid_nxt,
    \rams[1].RAM32M0 ,
    mcWrCAS,
    mcCasSlot2,
    \wrQ_reg[0][2] ,
    \rdEn_reg[12] ,
    \rdEn_reg[12]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ,
    DOA,
    \not_strict_mode.app_rd_data_end_reg ,
    D,
    DOC,
    DOB,
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ,
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] ,
    \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] ,
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] ,
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] ,
    cnt_clr,
    \rdEn_reg[13] ,
    \rdEn_reg[12]_1 ,
    \rdEn_reg[14] ,
    \rdEn_reg[12]_2 ,
    \rdEn_reg[14]_0 ,
    \dReg_reg[9] ,
    DQOut,
    DMOut,
    \dReg_reg[7] ,
    \dReg_reg[6] ,
    \dReg_reg[7]_0 ,
    \dReg_reg[6]_0 ,
    \dReg_reg[7]_1 ,
    \dReg_reg[6]_1 ,
    \dReg_reg[7]_2 ,
    \dReg_reg[6]_2 ,
    \dReg_reg[7]_3 ,
    \dReg_reg[6]_3 ,
    \dReg_reg[7]_4 ,
    \dReg_reg[6]_4 ,
    \dReg_reg[7]_5 ,
    \dReg_reg[6]_5 ,
    \dReg_reg[7]_6 ,
    \dReg_reg[6]_6 ,
    \dReg_reg[7]_7 ,
    \dReg_reg[6]_7 ,
    \dReg_reg[9]_0 ,
    \dReg_reg[7]_8 ,
    \dReg_reg[6]_8 ,
    \dReg_reg[7]_9 ,
    \dReg_reg[6]_9 ,
    \dReg_reg[7]_10 ,
    \dReg_reg[6]_10 ,
    \dReg_reg[7]_11 ,
    \dReg_reg[6]_11 ,
    \dReg_reg[7]_12 ,
    \dReg_reg[6]_12 ,
    \dReg_reg[7]_13 ,
    \dReg_reg[6]_13 ,
    \dReg_reg[7]_14 ,
    \dReg_reg[6]_14 ,
    \dReg_reg[7]_15 ,
    \dReg_reg[6]_15 ,
    \dReg_reg[7]_16 ,
    \dReg_reg[6]_16 ,
    \dReg_reg[9]_1 ,
    \dReg_reg[7]_17 ,
    \dReg_reg[6]_17 ,
    \dReg_reg[7]_18 ,
    \dReg_reg[6]_18 ,
    \dReg_reg[7]_19 ,
    \dReg_reg[6]_19 ,
    \dReg_reg[7]_20 ,
    \dReg_reg[6]_20 ,
    \dReg_reg[7]_21 ,
    \dReg_reg[6]_21 ,
    \dReg_reg[7]_22 ,
    \dReg_reg[6]_22 ,
    \dReg_reg[7]_23 ,
    \dReg_reg[6]_23 ,
    \dReg_reg[7]_24 ,
    \dReg_reg[6]_24 ,
    \dReg_reg[7]_25 ,
    \dReg_reg[6]_25 ,
    \dReg_reg[9]_2 ,
    \dReg_reg[7]_26 ,
    \dReg_reg[6]_26 ,
    \dReg_reg[7]_27 ,
    \dReg_reg[6]_27 ,
    \dReg_reg[7]_28 ,
    \dReg_reg[6]_28 ,
    \dReg_reg[7]_29 ,
    \dReg_reg[6]_29 ,
    \dReg_reg[7]_30 ,
    \dReg_reg[6]_30 ,
    \dReg_reg[7]_31 ,
    \dReg_reg[6]_31 ,
    \dReg_reg[7]_32 ,
    \dReg_reg[6]_32 ,
    \dReg_reg[7]_33 ,
    \dReg_reg[6]_33 ,
    \dReg_reg[7]_34 ,
    \dReg_reg[6]_34 ,
    \dReg_reg[9]_3 ,
    \dReg_reg[7]_35 ,
    \dReg_reg[6]_35 ,
    \dReg_reg[7]_36 ,
    \dReg_reg[6]_36 ,
    \dReg_reg[7]_37 ,
    \dReg_reg[6]_37 ,
    \dReg_reg[7]_38 ,
    \dReg_reg[6]_38 ,
    \dReg_reg[7]_39 ,
    \dReg_reg[6]_39 ,
    \dReg_reg[7]_40 ,
    \dReg_reg[6]_40 ,
    \dReg_reg[7]_41 ,
    \dReg_reg[6]_41 ,
    \dReg_reg[7]_42 ,
    \dReg_reg[6]_42 ,
    \dReg_reg[7]_43 ,
    \dReg_reg[6]_43 ,
    \dReg_reg[9]_4 ,
    \dReg_reg[7]_44 ,
    \dReg_reg[6]_44 ,
    \dReg_reg[7]_45 ,
    \dReg_reg[6]_45 ,
    \dReg_reg[7]_46 ,
    \dReg_reg[6]_46 ,
    \dReg_reg[7]_47 ,
    \dReg_reg[6]_47 ,
    \dReg_reg[7]_48 ,
    \dReg_reg[6]_48 ,
    \dReg_reg[7]_49 ,
    \dReg_reg[6]_49 ,
    \dReg_reg[7]_50 ,
    \dReg_reg[6]_50 ,
    \dReg_reg[7]_51 ,
    \dReg_reg[6]_51 ,
    \dReg_reg[7]_52 ,
    \dReg_reg[6]_52 ,
    \dReg_reg[9]_5 ,
    \dReg_reg[7]_53 ,
    \dReg_reg[6]_53 ,
    \dReg_reg[7]_54 ,
    \dReg_reg[6]_54 ,
    \dReg_reg[7]_55 ,
    \dReg_reg[6]_55 ,
    \dReg_reg[7]_56 ,
    \dReg_reg[6]_56 ,
    \dReg_reg[7]_57 ,
    \dReg_reg[6]_57 ,
    \dReg_reg[7]_58 ,
    \dReg_reg[6]_58 ,
    \dReg_reg[7]_59 ,
    \dReg_reg[6]_59 ,
    \dReg_reg[7]_60 ,
    \dReg_reg[6]_60 ,
    \dReg_reg[7]_61 ,
    \dReg_reg[6]_61 ,
    \dReg_reg[9]_6 ,
    \dReg_reg[7]_62 ,
    \dReg_reg[6]_62 ,
    \dReg_reg[7]_63 ,
    \dReg_reg[6]_63 ,
    \dReg_reg[7]_64 ,
    \dReg_reg[6]_64 ,
    \dReg_reg[7]_65 ,
    \dReg_reg[6]_65 ,
    \dReg_reg[7]_66 ,
    \dReg_reg[6]_66 ,
    \dReg_reg[7]_67 ,
    \dReg_reg[6]_67 ,
    \dReg_reg[7]_68 ,
    \dReg_reg[6]_68 ,
    \dReg_reg[7]_69 ,
    \dReg_reg[6]_69 ,
    \dReg_reg[7]_70 ,
    \dReg_reg[6]_70 ,
    \rdEn_reg[12]_3 ,
    mcalRdCAS,
    mcalCasSlot,
    mcalRank,
    \wrQ_reg[1][8]_0 ,
    \wrQ_nxt[1]_13 ,
    \wrQ_reg[0][8] ,
    \wrQ_reg[0][7]_rep ,
    \wrQ_reg[0][7]_rep__0 ,
    \wrQ_reg[0][7]_rep__1 ,
    \wrQ_reg[0][5]_rep ,
    \wrQ_reg[0][5]_rep__0 ,
    \wrQ_reg[0][5]_rep__1 ,
    \wrQ_reg[0][6]_rep ,
    \wrQ_reg[0][6]_rep__0 ,
    \wrQ_reg[0][6]_rep__1 ,
    \wrQ_reg[0][8]_rep ,
    \wrQ_reg[0][8]_rep__0_0 ,
    \wrQ_reg[0][8]_rep__1_0 ,
    \rsMask_reg[0][9] ,
    \rsMask_reg[0][11] ,
    \rsMask_reg[1][5] ,
    \rsMask_reg[1][1] ,
    \rsMask_reg[1][4] ,
    \rsMask_reg[2][9] ,
    \rsMask_reg[2][11] ,
    \rsMask_reg[3][5] ,
    \rsMask_reg[3][1] ,
    \rsMask_reg[3][4] ,
    \rsMask_reg[4][9] ,
    \rsMask_reg[4][11] ,
    \rsMask_reg[5][5] ,
    \rsMask_reg[5][1] ,
    \rsMask_reg[5][4] ,
    \rsMask_reg[6][9] ,
    \rsMask_reg[6][11] ,
    \rsMask_reg[7][5] ,
    \rsMask_reg[7][1] ,
    \rsMask_reg[7][4] ,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 ,
    \rsMask_reg[0][9]_1 ,
    \rsMask_reg[0][11]_1 ,
    \rsMask_reg[1][5]_1 ,
    \rsMask_reg[1][1]_1 ,
    \rsMask_reg[1][4]_1 ,
    \rsMask_reg[2][9]_1 ,
    \rsMask_reg[2][11]_1 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_1 ,
    \rsMask_reg[3][1]_1 ,
    \rsMask_reg[3][4]_1 ,
    \rsMask_reg[4][9]_1 ,
    \rsMask_reg[4][11]_1 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_1 ,
    \rsMask_reg[5][1]_1 ,
    \rsMask_reg[5][4]_1 ,
    \rsMask_reg[6][9]_1 ,
    \rsMask_reg[6][11]_1 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_1 ,
    \rsMask_reg[7][1]_1 ,
    \rsMask_reg[7][4]_1 ,
    \dReg_reg[11] ,
    \dReg_reg[10]_0 ,
    \dReg_reg[9]_7 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_1 ,
    \dReg_reg[9]_8 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_2 ,
    \dReg_reg[9]_9 ,
    \dReg_reg[11]_2 ,
    \dReg_reg[10]_3 ,
    \dReg_reg[9]_10 ,
    \dReg_reg[11]_3 ,
    \dReg_reg[10]_4 ,
    \dReg_reg[9]_11 ,
    \dReg_reg[11]_4 ,
    \dReg_reg[10]_5 ,
    \dReg_reg[9]_12 ,
    \dReg_reg[11]_5 ,
    \dReg_reg[10]_6 ,
    \dReg_reg[9]_13 ,
    \dReg_reg[11]_6 ,
    \dReg_reg[10]_7 ,
    \dReg_reg[9]_14 ,
    \dReg_reg[11]_7 ,
    \dReg_reg[10]_8 ,
    \dReg_reg[11]_8 ,
    \dReg_reg[10]_9 ,
    \dReg_reg[9]_15 ,
    \dReg_reg[11]_9 ,
    \dReg_reg[10]_10 ,
    \dReg_reg[9]_16 ,
    \dReg_reg[11]_10 ,
    \dReg_reg[10]_11 ,
    \dReg_reg[9]_17 ,
    \dReg_reg[11]_11 ,
    \dReg_reg[10]_12 ,
    \dReg_reg[9]_18 ,
    \dReg_reg[11]_12 ,
    \dReg_reg[10]_13 ,
    \dReg_reg[9]_19 ,
    \dReg_reg[11]_13 ,
    \dReg_reg[10]_14 ,
    \dReg_reg[9]_20 ,
    \dReg_reg[11]_14 ,
    \dReg_reg[10]_15 ,
    \dReg_reg[9]_21 ,
    \dReg_reg[11]_15 ,
    \dReg_reg[10]_16 ,
    \dReg_reg[9]_22 ,
    \dReg_reg[11]_16 ,
    \dReg_reg[10]_17 ,
    \dReg_reg[11]_17 ,
    \dReg_reg[10]_18 ,
    \dReg_reg[9]_23 ,
    \dReg_reg[11]_18 ,
    \dReg_reg[10]_19 ,
    \dReg_reg[9]_24 ,
    \dReg_reg[11]_19 ,
    \dReg_reg[10]_20 ,
    \dReg_reg[9]_25 ,
    \dReg_reg[11]_20 ,
    \dReg_reg[10]_21 ,
    \dReg_reg[9]_26 ,
    \dReg_reg[11]_21 ,
    \dReg_reg[10]_22 ,
    \dReg_reg[9]_27 ,
    \dReg_reg[11]_22 ,
    \dReg_reg[10]_23 ,
    \dReg_reg[9]_28 ,
    \dReg_reg[11]_23 ,
    \dReg_reg[10]_24 ,
    \dReg_reg[9]_29 ,
    \dReg_reg[11]_24 ,
    \dReg_reg[10]_25 ,
    \dReg_reg[9]_30 ,
    \dReg_reg[11]_25 ,
    \dReg_reg[10]_26 ,
    \dReg_reg[11]_26 ,
    \dReg_reg[10]_27 ,
    \dReg_reg[9]_31 ,
    \dReg_reg[11]_27 ,
    \dReg_reg[10]_28 ,
    \dReg_reg[9]_32 ,
    \dReg_reg[11]_28 ,
    \dReg_reg[10]_29 ,
    \dReg_reg[9]_33 ,
    \dReg_reg[11]_29 ,
    \dReg_reg[10]_30 ,
    \dReg_reg[9]_34 ,
    \dReg_reg[11]_30 ,
    \dReg_reg[10]_31 ,
    \dReg_reg[9]_35 ,
    \dReg_reg[11]_31 ,
    \dReg_reg[10]_32 ,
    \dReg_reg[9]_36 ,
    \dReg_reg[11]_32 ,
    \dReg_reg[10]_33 ,
    \dReg_reg[9]_37 ,
    \dReg_reg[11]_33 ,
    \dReg_reg[10]_34 ,
    \dReg_reg[9]_38 ,
    \dReg_reg[11]_34 ,
    \dReg_reg[10]_35 ,
    \dReg_reg[11]_35 ,
    \dReg_reg[10]_36 ,
    \dReg_reg[9]_39 ,
    \dReg_reg[11]_36 ,
    \dReg_reg[10]_37 ,
    \dReg_reg[9]_40 ,
    \dReg_reg[11]_37 ,
    \dReg_reg[10]_38 ,
    \dReg_reg[9]_41 ,
    \dReg_reg[11]_38 ,
    \dReg_reg[10]_39 ,
    \dReg_reg[9]_42 ,
    \dReg_reg[11]_39 ,
    \dReg_reg[10]_40 ,
    \dReg_reg[9]_43 ,
    \dReg_reg[11]_40 ,
    \dReg_reg[10]_41 ,
    \dReg_reg[9]_44 ,
    \dReg_reg[11]_41 ,
    \dReg_reg[10]_42 ,
    \dReg_reg[9]_45 ,
    \dReg_reg[11]_42 ,
    \dReg_reg[10]_43 ,
    \dReg_reg[9]_46 ,
    \dReg_reg[11]_43 ,
    \dReg_reg[10]_44 ,
    \dReg_reg[11]_44 ,
    \dReg_reg[10]_45 ,
    \dReg_reg[9]_47 ,
    \dReg_reg[11]_45 ,
    \dReg_reg[10]_46 ,
    \dReg_reg[9]_48 ,
    \dReg_reg[11]_46 ,
    \dReg_reg[10]_47 ,
    \dReg_reg[9]_49 ,
    \dReg_reg[11]_47 ,
    \dReg_reg[10]_48 ,
    \dReg_reg[9]_50 ,
    \dReg_reg[11]_48 ,
    \dReg_reg[10]_49 ,
    \dReg_reg[9]_51 ,
    \dReg_reg[11]_49 ,
    \dReg_reg[10]_50 ,
    \dReg_reg[9]_52 ,
    \dReg_reg[11]_50 ,
    \dReg_reg[10]_51 ,
    \dReg_reg[9]_53 ,
    \dReg_reg[11]_51 ,
    \dReg_reg[10]_52 ,
    \dReg_reg[9]_54 ,
    \dReg_reg[11]_52 ,
    \dReg_reg[10]_53 ,
    \dReg_reg[11]_53 ,
    \dReg_reg[10]_54 ,
    \dReg_reg[9]_55 ,
    \dReg_reg[11]_54 ,
    \dReg_reg[10]_55 ,
    \dReg_reg[9]_56 ,
    \dReg_reg[11]_55 ,
    \dReg_reg[10]_56 ,
    \dReg_reg[9]_57 ,
    \dReg_reg[11]_56 ,
    \dReg_reg[10]_57 ,
    \dReg_reg[9]_58 ,
    \dReg_reg[11]_57 ,
    \dReg_reg[10]_58 ,
    \dReg_reg[9]_59 ,
    \dReg_reg[11]_58 ,
    \dReg_reg[10]_59 ,
    \dReg_reg[9]_60 ,
    \dReg_reg[11]_59 ,
    \dReg_reg[10]_60 ,
    \dReg_reg[9]_61 ,
    \dReg_reg[11]_60 ,
    \dReg_reg[10]_61 ,
    \dReg_reg[9]_62 ,
    \dReg_reg[11]_61 ,
    \dReg_reg[10]_62 ,
    \dReg_reg[11]_62 ,
    \dReg_reg[10]_63 ,
    \dReg_reg[9]_63 ,
    \dReg_reg[11]_63 ,
    \dReg_reg[10]_64 ,
    \dReg_reg[9]_64 ,
    \dReg_reg[11]_64 ,
    \dReg_reg[10]_65 ,
    \dReg_reg[9]_65 ,
    \dReg_reg[11]_65 ,
    \dReg_reg[10]_66 ,
    \dReg_reg[9]_66 ,
    \dReg_reg[11]_66 ,
    \dReg_reg[10]_67 ,
    \dReg_reg[9]_67 ,
    \dReg_reg[11]_67 ,
    \dReg_reg[10]_68 ,
    \dReg_reg[9]_68 ,
    \dReg_reg[11]_68 ,
    \dReg_reg[10]_69 ,
    \dReg_reg[9]_69 ,
    \dReg_reg[11]_69 ,
    \dReg_reg[10]_70 ,
    \dReg_reg[9]_70 ,
    \dReg_reg[11]_70 ,
    \dReg_reg[10]_71 ,
    \rsMask_reg[0][9]_2 ,
    \rsMask_reg[0][11]_2 ,
    \rsMask_reg[1][5]_2 ,
    \rsMask_reg[1][1]_2 ,
    \rsMask_reg[1][4]_2 ,
    \rsMask_reg[2][9]_2 ,
    \rsMask_reg[2][11]_2 ,
    \rsMask_reg[3][11]_1 ,
    \rsMask_reg[3][5]_2 ,
    \rsMask_reg[3][1]_2 ,
    \rsMask_reg[3][4]_2 ,
    \rsMask_reg[4][9]_2 ,
    \rsMask_reg[4][11]_2 ,
    \rsMask_reg[5][11]_1 ,
    \rsMask_reg[5][5]_2 ,
    \rsMask_reg[5][1]_2 ,
    \rsMask_reg[5][4]_2 ,
    \rsMask_reg[6][9]_2 ,
    \rsMask_reg[6][11]_2 ,
    \rsMask_reg[7][11]_1 ,
    \rsMask_reg[7][5]_2 ,
    \rsMask_reg[7][1]_2 ,
    \rsMask_reg[7][4]_2 ,
    \rsMask_reg[0][9]_3 ,
    \rsMask_reg[0][11]_3 ,
    \rsMask_reg[1][5]_3 ,
    \rsMask_reg[1][1]_3 ,
    \rsMask_reg[1][4]_3 ,
    \rsMask_reg[2][9]_3 ,
    \rsMask_reg[2][11]_3 ,
    \rsMask_reg[3][11]_2 ,
    \rsMask_reg[3][5]_3 ,
    \rsMask_reg[3][1]_3 ,
    \rsMask_reg[3][4]_3 ,
    \rsMask_reg[4][9]_3 ,
    \rsMask_reg[4][11]_3 ,
    \rsMask_reg[5][11]_2 ,
    \rsMask_reg[5][5]_3 ,
    \rsMask_reg[5][1]_3 ,
    \rsMask_reg[5][4]_3 ,
    \rsMask_reg[6][9]_3 ,
    \rsMask_reg[6][11]_3 ,
    \rsMask_reg[7][11]_2 ,
    \rsMask_reg[7][5]_3 ,
    \rsMask_reg[7][1]_3 ,
    \rsMask_reg[7][4]_3 ,
    \rsMask_reg[0][9]_4 ,
    \rsMask_reg[0][11]_4 ,
    \rsMask_reg[1][5]_4 ,
    \rsMask_reg[1][1]_4 ,
    \rsMask_reg[1][4]_4 ,
    \rsMask_reg[2][9]_4 ,
    \rsMask_reg[2][11]_4 ,
    \rsMask_reg[3][11]_3 ,
    \rsMask_reg[3][5]_4 ,
    \rsMask_reg[3][1]_4 ,
    \rsMask_reg[3][4]_4 ,
    \rsMask_reg[4][9]_4 ,
    \rsMask_reg[4][11]_4 ,
    \rsMask_reg[5][11]_3 ,
    \rsMask_reg[5][5]_4 ,
    \rsMask_reg[5][1]_4 ,
    \rsMask_reg[5][4]_4 ,
    \rsMask_reg[6][9]_4 ,
    \rsMask_reg[6][11]_4 ,
    \rsMask_reg[7][11]_3 ,
    \rsMask_reg[7][5]_4 ,
    \rsMask_reg[7][1]_4 ,
    \rsMask_reg[7][4]_4 ,
    \rsMask_reg[0][9]_5 ,
    \rsMask_reg[0][11]_5 ,
    \rsMask_reg[1][5]_5 ,
    \rsMask_reg[1][1]_5 ,
    \rsMask_reg[1][4]_5 ,
    \rsMask_reg[2][9]_5 ,
    \rsMask_reg[2][11]_5 ,
    \rsMask_reg[3][11]_4 ,
    \rsMask_reg[3][5]_5 ,
    \rsMask_reg[3][1]_5 ,
    \rsMask_reg[3][4]_5 ,
    \rsMask_reg[4][9]_5 ,
    \rsMask_reg[4][11]_5 ,
    \rsMask_reg[5][11]_4 ,
    \rsMask_reg[5][5]_5 ,
    \rsMask_reg[5][1]_5 ,
    \rsMask_reg[5][4]_5 ,
    \rsMask_reg[6][9]_5 ,
    \rsMask_reg[6][11]_5 ,
    \rsMask_reg[7][11]_4 ,
    \rsMask_reg[7][5]_5 ,
    \rsMask_reg[7][1]_5 ,
    \rsMask_reg[7][4]_5 ,
    \rsMask_reg[0][9]_6 ,
    \rsMask_reg[0][11]_6 ,
    \rsMask_reg[1][5]_6 ,
    \rsMask_reg[1][1]_6 ,
    \rsMask_reg[1][4]_6 ,
    \rsMask_reg[2][9]_6 ,
    \rsMask_reg[2][11]_6 ,
    \rsMask_reg[3][11]_5 ,
    \rsMask_reg[3][5]_6 ,
    \rsMask_reg[3][1]_6 ,
    \rsMask_reg[3][4]_6 ,
    \rsMask_reg[4][9]_6 ,
    \rsMask_reg[4][11]_6 ,
    \rsMask_reg[5][11]_5 ,
    \rsMask_reg[5][5]_6 ,
    \rsMask_reg[5][1]_6 ,
    \rsMask_reg[5][4]_6 ,
    \rsMask_reg[6][9]_6 ,
    \rsMask_reg[6][11]_6 ,
    \rsMask_reg[7][11]_5 ,
    \rsMask_reg[7][5]_6 ,
    \rsMask_reg[7][1]_6 ,
    \rsMask_reg[7][4]_6 ,
    \rsMask_reg[0][9]_7 ,
    \rsMask_reg[0][11]_7 ,
    \rsMask_reg[1][5]_7 ,
    \rsMask_reg[1][1]_7 ,
    \rsMask_reg[1][4]_7 ,
    \rsMask_reg[2][9]_7 ,
    \rsMask_reg[2][11]_7 ,
    \rsMask_reg[3][11]_6 ,
    \rsMask_reg[3][5]_7 ,
    \rsMask_reg[3][1]_7 ,
    \rsMask_reg[3][4]_7 ,
    \rsMask_reg[4][9]_7 ,
    \rsMask_reg[4][11]_7 ,
    \rsMask_reg[5][11]_6 ,
    \rsMask_reg[5][5]_7 ,
    \rsMask_reg[5][1]_7 ,
    \rsMask_reg[5][4]_7 ,
    \rsMask_reg[6][9]_7 ,
    \rsMask_reg[6][11]_7 ,
    \rsMask_reg[7][11]_6 ,
    \rsMask_reg[7][5]_7 ,
    \rsMask_reg[7][1]_7 ,
    \rsMask_reg[7][4]_7 ,
    \rsMask_reg[0][9]_8 ,
    \rsMask_reg[0][11]_8 ,
    \rsMask_reg[1][5]_8 ,
    \rsMask_reg[1][1]_8 ,
    \rsMask_reg[1][4]_8 ,
    \rsMask_reg[2][9]_8 ,
    \rsMask_reg[2][11]_8 ,
    \rsMask_reg[3][11]_7 ,
    \rsMask_reg[3][5]_8 ,
    \rsMask_reg[3][1]_8 ,
    \rsMask_reg[3][4]_8 ,
    \rsMask_reg[4][9]_8 ,
    \rsMask_reg[4][11]_8 ,
    \rsMask_reg[5][11]_7 ,
    \rsMask_reg[5][5]_8 ,
    \rsMask_reg[5][1]_8 ,
    \rsMask_reg[5][4]_8 ,
    \rsMask_reg[6][9]_8 ,
    \rsMask_reg[6][11]_8 ,
    \rsMask_reg[7][11]_7 ,
    \rsMask_reg[7][5]_8 ,
    \rsMask_reg[7][1]_8 ,
    \rsMask_reg[7][4]_8 ,
    \rsMask_reg[0][9]_9 ,
    \rsMask_reg[0][11]_9 ,
    \rsMask_reg[1][5]_9 ,
    \rsMask_reg[1][1]_9 ,
    \rsMask_reg[1][4]_9 ,
    \rsMask_reg[2][9]_9 ,
    \rsMask_reg[2][11]_9 ,
    \rsMask_reg[3][11]_8 ,
    \rsMask_reg[3][5]_9 ,
    \rsMask_reg[3][1]_9 ,
    \rsMask_reg[3][4]_9 ,
    \rsMask_reg[4][9]_9 ,
    \rsMask_reg[4][11]_9 ,
    \rsMask_reg[5][11]_8 ,
    \rsMask_reg[5][5]_9 ,
    \rsMask_reg[5][1]_9 ,
    \rsMask_reg[5][4]_9 ,
    \rsMask_reg[6][9]_9 ,
    \rsMask_reg[6][11]_9 ,
    \rsMask_reg[7][11]_8 ,
    \rsMask_reg[7][5]_9 ,
    \rsMask_reg[7][1]_9 ,
    \rsMask_reg[7][4]_9 ,
    \rsMask_reg[0][9]_10 ,
    \rsMask_reg[0][11]_10 ,
    \rsMask_reg[1][5]_10 ,
    \rsMask_reg[1][1]_10 ,
    \rsMask_reg[1][4]_10 ,
    \rsMask_reg[2][9]_10 ,
    \rsMask_reg[2][11]_10 ,
    \rsMask_reg[3][11]_9 ,
    \rsMask_reg[3][5]_10 ,
    \rsMask_reg[3][1]_10 ,
    \rsMask_reg[3][4]_10 ,
    \rsMask_reg[4][9]_10 ,
    \rsMask_reg[4][11]_10 ,
    \rsMask_reg[5][11]_9 ,
    \rsMask_reg[5][5]_10 ,
    \rsMask_reg[5][1]_10 ,
    \rsMask_reg[5][4]_10 ,
    \rsMask_reg[6][9]_10 ,
    \rsMask_reg[6][11]_10 ,
    \rsMask_reg[7][11]_9 ,
    \rsMask_reg[7][5]_10 ,
    \rsMask_reg[7][1]_10 ,
    \rsMask_reg[7][4]_10 ,
    \rsMask_reg[0][9]_11 ,
    \rsMask_reg[0][11]_11 ,
    \rsMask_reg[1][5]_11 ,
    \rsMask_reg[1][1]_11 ,
    \rsMask_reg[1][4]_11 ,
    \rsMask_reg[2][9]_11 ,
    \rsMask_reg[2][11]_11 ,
    \rsMask_reg[3][11]_10 ,
    \rsMask_reg[3][5]_11 ,
    \rsMask_reg[3][1]_11 ,
    \rsMask_reg[3][4]_11 ,
    \rsMask_reg[4][9]_11 ,
    \rsMask_reg[4][11]_11 ,
    \rsMask_reg[5][11]_10 ,
    \rsMask_reg[5][5]_11 ,
    \rsMask_reg[5][1]_11 ,
    \rsMask_reg[5][4]_11 ,
    \rsMask_reg[6][9]_11 ,
    \rsMask_reg[6][11]_11 ,
    \rsMask_reg[7][11]_10 ,
    \rsMask_reg[7][5]_11 ,
    \rsMask_reg[7][1]_11 ,
    \rsMask_reg[7][4]_11 ,
    \rsMask_reg[0][9]_12 ,
    \rsMask_reg[0][11]_12 ,
    \rsMask_reg[1][5]_12 ,
    \rsMask_reg[1][1]_12 ,
    \rsMask_reg[1][4]_12 ,
    \rsMask_reg[2][9]_12 ,
    \rsMask_reg[2][11]_12 ,
    \rsMask_reg[3][11]_11 ,
    \rsMask_reg[3][5]_12 ,
    \rsMask_reg[3][1]_12 ,
    \rsMask_reg[3][4]_12 ,
    \rsMask_reg[4][9]_12 ,
    \rsMask_reg[4][11]_12 ,
    \rsMask_reg[5][11]_11 ,
    \rsMask_reg[5][5]_12 ,
    \rsMask_reg[5][1]_12 ,
    \rsMask_reg[5][4]_12 ,
    \rsMask_reg[6][9]_12 ,
    \rsMask_reg[6][11]_12 ,
    \rsMask_reg[7][11]_11 ,
    \rsMask_reg[7][5]_12 ,
    \rsMask_reg[7][1]_12 ,
    \rsMask_reg[7][4]_12 ,
    \rsMask_reg[0][9]_13 ,
    \rsMask_reg[0][11]_13 ,
    \rsMask_reg[1][5]_13 ,
    \rsMask_reg[1][1]_13 ,
    \rsMask_reg[1][4]_13 ,
    \rsMask_reg[2][9]_13 ,
    \rsMask_reg[2][11]_13 ,
    \rsMask_reg[3][11]_12 ,
    \rsMask_reg[3][5]_13 ,
    \rsMask_reg[3][1]_13 ,
    \rsMask_reg[3][4]_13 ,
    \rsMask_reg[4][9]_13 ,
    \rsMask_reg[4][11]_13 ,
    \rsMask_reg[5][11]_12 ,
    \rsMask_reg[5][5]_13 ,
    \rsMask_reg[5][1]_13 ,
    \rsMask_reg[5][4]_13 ,
    \rsMask_reg[6][9]_13 ,
    \rsMask_reg[6][11]_13 ,
    \rsMask_reg[7][11]_12 ,
    \rsMask_reg[7][5]_13 ,
    \rsMask_reg[7][1]_13 ,
    \rsMask_reg[7][4]_13 ,
    \rsMask_reg[0][9]_14 ,
    \rsMask_reg[0][11]_14 ,
    \rsMask_reg[1][5]_14 ,
    \rsMask_reg[1][1]_14 ,
    \rsMask_reg[1][4]_14 ,
    \rsMask_reg[2][9]_14 ,
    \rsMask_reg[2][11]_14 ,
    \rsMask_reg[3][11]_13 ,
    \rsMask_reg[3][5]_14 ,
    \rsMask_reg[3][1]_14 ,
    \rsMask_reg[3][4]_14 ,
    \rsMask_reg[4][9]_14 ,
    \rsMask_reg[4][11]_14 ,
    \rsMask_reg[5][11]_13 ,
    \rsMask_reg[5][5]_14 ,
    \rsMask_reg[5][1]_14 ,
    \rsMask_reg[5][4]_14 ,
    \rsMask_reg[6][9]_14 ,
    \rsMask_reg[6][11]_14 ,
    \rsMask_reg[7][11]_13 ,
    \rsMask_reg[7][5]_14 ,
    \rsMask_reg[7][1]_14 ,
    \rsMask_reg[7][4]_14 ,
    \read_lat_fifo_in_reg[6] ,
    cmdBuf,
    cal_clear_fifo_rden);
  output [0:0]mc_clb2phy_fifo_rden_nxt;
  output rdDataEn_pi;
  output wrDataVal;
  output out;
  output wrDataEn_pi;
  output [2:1]wosp;
  output \oe_0_mux_cal_reg[0] ;
  output \wosp_reg[2]_rep ;
  output \wosp_reg[2]_rep__0 ;
  output \wosp_reg[2]_rep__1 ;
  output \wosp_reg[2]_rep__2 ;
  output \wosp_reg[2]_rep__3 ;
  output \wosp_reg[2]_rep__4 ;
  output \wosp_reg[2]_rep__5 ;
  output \wosp_reg[2]_rep__6 ;
  output \wosp_reg[2]_rep__7 ;
  output [1:0]\rsMask_reg[7][18] ;
  output [1:0]\rsMask_reg[5][18] ;
  output [1:0]\rsMask_reg[3][18] ;
  output [1:0]\rsMask_reg[1][18] ;
  output [1:0]\rsMask_reg[7][18]_0 ;
  output [1:0]\rsMask_reg[5][18]_0 ;
  output [1:0]\rsMask_reg[3][18]_0 ;
  output [1:0]\rsMask_reg[1][18]_0 ;
  output pointer_we;
  output calDone_reg;
  output per_rd_done;
  output [0:0]\wrQ_reg[0][0] ;
  output [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] ;
  output \not_strict_mode.status_ram_0.RAM32M0 ;
  output \not_strict_mode.bypass_cpy2 ;
  output [4:0]Q;
  output [5:0]\rdData_reg[5] ;
  output match6_13_return;
  output \rdDataAddr_reg[3]_rep ;
  output \rdDataAddr_reg[4]_rep ;
  output match4_13_return;
  output [5:0]\rdData_reg[11] ;
  output match6_14_return;
  output \rdDataAddr_reg[3]_rep__0 ;
  output \rdDataAddr_reg[4]_rep__0 ;
  output match4_14_return;
  output [5:0]\rdData_reg[17] ;
  output match6_15_return;
  output \rdDataAddr_reg[3]_rep__1 ;
  output \rdDataAddr_reg[4]_rep__1 ;
  output match4_15_return;
  output [5:0]\rdData_reg[23] ;
  output match6_16_return;
  output match4_16_return;
  output [5:0]\rdData_reg[29] ;
  output match6_17_return;
  output match4_17_return;
  output [5:0]\rdData_reg[35] ;
  output match6_18_return;
  output match4_18_return;
  output [5:0]\rdData_reg[41] ;
  output match6_19_return;
  output match4_19_return;
  output [5:0]\rdData_reg[47] ;
  output match6_110_return;
  output match4_110_return;
  output [5:0]\rdData_reg[53] ;
  output match6_111_return;
  output match4_111_return;
  output [5:0]\rdData_reg[59] ;
  output match6_112_return;
  output match4_112_return;
  output [5:0]\rdData_reg[65] ;
  output match6_113_return;
  output match4_113_return;
  output [5:0]\rdData_reg[71] ;
  output match6_114_return;
  output match4_114_return;
  output [5:0]\rdData_reg[77] ;
  output match6_115_return;
  output match4_115_return;
  output [5:0]\rdData_reg[83] ;
  output match6_116_return;
  output match4_116_return;
  output [5:0]\rdData_reg[89] ;
  output match6_117_return;
  output match4_117_return;
  output [5:0]\rdData_reg[95] ;
  output match6_118_return;
  output match4_118_return;
  output [5:0]\rdData_reg[101] ;
  output match6_119_return;
  output match4_119_return;
  output [5:0]\rdData_reg[107] ;
  output match6_120_return;
  output match4_120_return;
  output [5:0]\rdData_reg[113] ;
  output match6_121_return;
  output match4_121_return;
  output [5:0]\rdData_reg[119] ;
  output match6_122_return;
  output match4_122_return;
  output [5:0]\rdData_reg[125] ;
  output match6_123_return;
  output match4_123_return;
  output [5:0]\rdData_reg[131] ;
  output match6_124_return;
  output match4_124_return;
  output [5:0]\rdData_reg[137] ;
  output match6_125_return;
  output match4_125_return;
  output [5:0]\rdData_reg[143] ;
  output match6_126_return;
  output match4_126_return;
  output [5:0]\rdData_reg[149] ;
  output match6_127_return;
  output match4_127_return;
  output [5:0]\rdData_reg[155] ;
  output match6_128_return;
  output match4_128_return;
  output [5:0]\rdData_reg[161] ;
  output match6_129_return;
  output match4_129_return;
  output [5:0]\rdData_reg[167] ;
  output match6_130_return;
  output match4_130_return;
  output [5:0]\rdData_reg[173] ;
  output match6_131_return;
  output match4_131_return;
  output [5:0]\rdData_reg[179] ;
  output match6_132_return;
  output match4_132_return;
  output [5:0]\rdData_reg[185] ;
  output match6_133_return;
  output match4_133_return;
  output [5:0]\rdData_reg[191] ;
  output match6_134_return;
  output match4_134_return;
  output [5:0]\rdData_reg[197] ;
  output match6_135_return;
  output match4_135_return;
  output [5:0]\rdData_reg[203] ;
  output match6_136_return;
  output match4_136_return;
  output [5:0]\rdData_reg[209] ;
  output match6_137_return;
  output match4_137_return;
  output [5:0]\rdData_reg[215] ;
  output match6_138_return;
  output match4_138_return;
  output [5:0]\rdData_reg[221] ;
  output match6_139_return;
  output match4_139_return;
  output [5:0]\rdData_reg[227] ;
  output match6_140_return;
  output match4_140_return;
  output [5:0]\rdData_reg[233] ;
  output match6_141_return;
  output match4_141_return;
  output [5:0]\rdData_reg[239] ;
  output match6_142_return;
  output match4_142_return;
  output [5:0]\rdData_reg[245] ;
  output match6_143_return;
  output match4_143_return;
  output [5:0]\rdData_reg[251] ;
  output match6_144_return;
  output match4_144_return;
  output [5:0]\rdData_reg[257] ;
  output match6_145_return;
  output match4_145_return;
  output [5:0]\rdData_reg[263] ;
  output match6_146_return;
  output match4_146_return;
  output [5:0]\rdData_reg[269] ;
  output match6_147_return;
  output match4_147_return;
  output [5:0]\rdData_reg[275] ;
  output match6_148_return;
  output match4_148_return;
  output [5:0]\rdData_reg[281] ;
  output match6_149_return;
  output match4_149_return;
  output [5:0]\rdData_reg[287] ;
  output match6_150_return;
  output match4_150_return;
  output [5:0]\rdData_reg[293] ;
  output match6_151_return;
  output match4_151_return;
  output [5:0]\rdData_reg[299] ;
  output match6_152_return;
  output match4_152_return;
  output [5:0]\rdData_reg[305] ;
  output match6_153_return;
  output match4_153_return;
  output [5:0]\rdData_reg[311] ;
  output match6_154_return;
  output match4_154_return;
  output [5:0]\rdData_reg[317] ;
  output match6_155_return;
  output match4_155_return;
  output [5:0]\rdData_reg[323] ;
  output match6_156_return;
  output match4_156_return;
  output [5:0]\rdData_reg[329] ;
  output match6_157_return;
  output match4_157_return;
  output [5:0]\rdData_reg[335] ;
  output match6_158_return;
  output match4_158_return;
  output [5:0]\rdData_reg[341] ;
  output match6_159_return;
  output match4_159_return;
  output [5:0]\rdData_reg[347] ;
  output match6_160_return;
  output match4_160_return;
  output [5:0]\rdData_reg[353] ;
  output match6_161_return;
  output match4_161_return;
  output [5:0]\rdData_reg[359] ;
  output match6_162_return;
  output match4_162_return;
  output [5:0]\rdData_reg[365] ;
  output match6_163_return;
  output match4_163_return;
  output [5:0]\rdData_reg[371] ;
  output match6_164_return;
  output match4_164_return;
  output [5:0]\rdData_reg[377] ;
  output match6_165_return;
  output match4_165_return;
  output [5:0]\rdData_reg[383] ;
  output match6_166_return;
  output match4_166_return;
  output [5:0]\rdData_reg[389] ;
  output match6_167_return;
  output match4_167_return;
  output [5:0]\rdData_reg[395] ;
  output match6_168_return;
  output match4_168_return;
  output [5:0]\rdData_reg[401] ;
  output match6_169_return;
  output match4_169_return;
  output [5:0]\rdData_reg[407] ;
  output match6_170_return;
  output match4_170_return;
  output [5:0]\rdData_reg[413] ;
  output match6_171_return;
  output match4_171_return;
  output [5:0]\rdData_reg[419] ;
  output match6_172_return;
  output match4_172_return;
  output [5:0]\rdData_reg[425] ;
  output match6_173_return;
  output match4_173_return;
  output [5:0]\rdData_reg[431] ;
  output match6_174_return;
  output match4_174_return;
  output [5:0]\rdData_reg[437] ;
  output match6_175_return;
  output match4_175_return;
  output [5:0]\rdData_reg[443] ;
  output match6_176_return;
  output match4_176_return;
  output [5:0]\rdData_reg[449] ;
  output match6_177_return;
  output match4_177_return;
  output [5:0]\rdData_reg[455] ;
  output match6_178_return;
  output match4_178_return;
  output [5:0]\rdData_reg[461] ;
  output match6_179_return;
  output match4_179_return;
  output [5:0]\rdData_reg[467] ;
  output match6_180_return;
  output match4_180_return;
  output [5:0]\rdData_reg[473] ;
  output match6_181_return;
  output match4_181_return;
  output [5:0]\rdData_reg[479] ;
  output match6_182_return;
  output match4_182_return;
  output [5:0]\rdData_reg[485] ;
  output match6_183_return;
  output match4_183_return;
  output [5:0]\rdData_reg[491] ;
  output match6_184_return;
  output match4_184_return;
  output [5:0]\rdData_reg[497] ;
  output match6_185_return;
  output match4_185_return;
  output [5:0]\rdData_reg[503] ;
  output match6_186_return;
  output match4_186_return;
  output [5:0]\rdData_reg[509] ;
  output match6_187_return;
  output match4_187_return;
  output [1:0]\rdData_reg[511] ;
  output match6_188_return;
  output match4_188_return;
  output match4_1_return;
  output match6_1_return;
  output match4_10_return;
  output match6_10_return;
  output match4_11_return;
  output match6_11_return;
  output match4_12_return;
  output match6_12_return;
  output [0:0]pop_read_lat_fifo_reg;
  output \rsMask_reg[7][18]_1 ;
  output \rsMask_reg[7][17] ;
  output \rsMask_reg[7][18]_2 ;
  output \rsMask_reg[7][17]_0 ;
  output \rsMask_reg[7][18]_3 ;
  output \rsMask_reg[7][17]_1 ;
  output \rsMask_reg[7][18]_4 ;
  output \rsMask_reg[7][17]_2 ;
  output \rsMask_reg[7][18]_5 ;
  output \rsMask_reg[7][17]_3 ;
  output \rsMask_reg[7][18]_6 ;
  output \rsMask_reg[7][17]_4 ;
  output \rsMask_reg[7][18]_7 ;
  output \rsMask_reg[7][17]_5 ;
  output \rsMask_reg[7][18]_8 ;
  output \rsMask_reg[7][17]_6 ;
  output \rsMask_reg[7][18]_9 ;
  output \rsMask_reg[7][17]_7 ;
  output \rsMask_reg[7][18]_10 ;
  output \rsMask_reg[7][17]_8 ;
  output \rsMask_reg[7][18]_11 ;
  output \rsMask_reg[7][17]_9 ;
  output \rsMask_reg[7][18]_12 ;
  output \rsMask_reg[7][17]_10 ;
  output \rsMask_reg[7][18]_13 ;
  output \rsMask_reg[7][17]_11 ;
  output \rsMask_reg[7][18]_14 ;
  output \rsMask_reg[7][17]_12 ;
  output [3:0]\wrQ_reg[1][8] ;
  output [3:0]ADDRC;
  output \wrQ_reg[0][0]_rep ;
  output [3:0]ADDRA;
  output [3:0]\wrQ_reg[0][8]_rep__0 ;
  output [3:0]\wrQ_reg[0][8]_rep__1 ;
  output [3:0]\oe_upp_reg[3] ;
  output [3:0]\oe_low_reg[3] ;
  output [31:0]ch0_mcal_clb2phy_rden_upp;
  output [511:0]ch0_mcal_DQOut;
  output [63:0]ch0_mcal_DMOut_n;
  output [31:0]ch0_mcal_clb2phy_rden_low;
  output [31:0]\read_lat_shift_reg[31] ;
  output phy_rden_or;
  output phy_rden_and;
  output underfill_done_nxt;
  output \rdDataAddr_reg[4] ;
  output \rdDataAddr_reg[4]_0 ;
  output \rdDataAddr_reg[4]_1 ;
  input \dReg_reg[10] ;
  input [0:0]cal_oe_dis_upp;
  input [0:0]cal_oe_dis_low;
  input \oe_0_mux_cal_reg[0]_0 ;
  input [1:0]in0;
  input [1:0]\rdEn_reg[29] ;
  input \rsMask_reg[7][2] ;
  input \rsMask_reg[5][2] ;
  input \rsMask_reg[3][2] ;
  input [3:0]\rsMask_reg[1][12] ;
  input \rsMask_reg[7][3] ;
  input \rsMask_reg[5][3] ;
  input \rsMask_reg[3][3] ;
  input \rsMask_reg[7][10] ;
  input \rsMask_reg[5][10] ;
  input \rsMask_reg[3][10] ;
  input \rsMask_reg[7][12] ;
  input \rsMask_reg[5][12] ;
  input \rsMask_reg[3][12] ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [3:0]\rsMask_reg[1][12]_0 ;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input \rsMask_reg[1][6] ;
  input \rsMask_reg[1][15] ;
  input \rsMask_reg[1][16] ;
  input \rsMask_reg[1][17] ;
  input \rsMask_reg[1][18]_2 ;
  input [1:0]\blk1.(null)[0].diff ;
  input \rsMask_reg[1][8] ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][6] ;
  input \rsMask_reg[3][15] ;
  input \rsMask_reg[3][16] ;
  input \rsMask_reg[3][17] ;
  input \rsMask_reg[3][18]_2 ;
  input \rsMask_reg[3][9] ;
  input \rsMask_reg[3][8] ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][6] ;
  input \rsMask_reg[5][15] ;
  input \rsMask_reg[5][16] ;
  input \rsMask_reg[5][17] ;
  input \rsMask_reg[5][18]_2 ;
  input \rsMask_reg[5][9] ;
  input \rsMask_reg[5][8] ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[7][18]_15 ;
  input \rsMask_reg[7][6] ;
  input \rsMask_reg[7][15] ;
  input \rsMask_reg[7][16] ;
  input \rsMask_reg[7][17]_13 ;
  input \rsMask_reg[7][18]_16 ;
  input \rsMask_reg[7][9] ;
  input \rsMask_reg[7][8] ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[1][18]_3 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_4 ;
  input [1:0]\blk1.(null)[0].diff_0 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_3 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_4 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_2 ;
  input \rsMask_reg[5][18]_3 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_4 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_2 ;
  input \rsMask_reg[7][18]_17 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_14 ;
  input \rsMask_reg[7][18]_18 ;
  input \rsMask_reg[7][9]_1 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_2 ;
  input [0:0]SR;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_1 ;
  input \rsMask_reg[5][2]_1 ;
  input \rsMask_reg[3][2]_1 ;
  input [4:0]rs2mask0;
  input \rsMask_reg[7][3]_1 ;
  input \rsMask_reg[5][3]_1 ;
  input \rsMask_reg[3][3]_1 ;
  input \rsMask_reg[7][10]_1 ;
  input \rsMask_reg[5][10]_1 ;
  input \rsMask_reg[3][10]_1 ;
  input \rsMask_reg[7][12]_1 ;
  input \rsMask_reg[5][12]_1 ;
  input \rsMask_reg[3][12]_1 ;
  input \rsMask_reg[1][18]_5 ;
  input \rsMask_reg[1][6]_1 ;
  input \rsMask_reg[1][15]_1 ;
  input \rsMask_reg[1][16]_1 ;
  input \rsMask_reg[1][17]_1 ;
  input \rsMask_reg[1][18]_6 ;
  input [1:0]\blk1.(null)[0].diff_1 ;
  input \rsMask_reg[1][8]_1 ;
  input \rsMask_reg[3][18]_5 ;
  input \rsMask_reg[3][6]_1 ;
  input \rsMask_reg[3][15]_1 ;
  input \rsMask_reg[3][16]_1 ;
  input \rsMask_reg[3][17]_1 ;
  input \rsMask_reg[3][18]_6 ;
  input \rsMask_reg[3][9]_3 ;
  input \rsMask_reg[3][8]_1 ;
  input \rsMask_reg[3][9]_4 ;
  input \rsMask_reg[5][18]_5 ;
  input \rsMask_reg[5][6]_1 ;
  input \rsMask_reg[5][15]_1 ;
  input \rsMask_reg[5][16]_1 ;
  input \rsMask_reg[5][17]_1 ;
  input \rsMask_reg[5][18]_6 ;
  input \rsMask_reg[5][9]_3 ;
  input \rsMask_reg[5][8]_1 ;
  input \rsMask_reg[5][9]_4 ;
  input \rsMask_reg[7][18]_19 ;
  input \rsMask_reg[7][6]_1 ;
  input \rsMask_reg[7][15]_1 ;
  input \rsMask_reg[7][16]_1 ;
  input \rsMask_reg[7][17]_15 ;
  input \rsMask_reg[7][18]_20 ;
  input \rsMask_reg[7][9]_3 ;
  input \rsMask_reg[7][8]_1 ;
  input \rsMask_reg[7][9]_4 ;
  input [1:0]\rdEn_reg[29]_1 ;
  input \rsMask_reg[7][2]_2 ;
  input \rsMask_reg[5][2]_2 ;
  input \rsMask_reg[3][2]_2 ;
  input [4:0]rs2mask0_2;
  input \rsMask_reg[7][3]_2 ;
  input \rsMask_reg[5][3]_2 ;
  input \rsMask_reg[3][3]_2 ;
  input \rsMask_reg[7][10]_2 ;
  input \rsMask_reg[5][10]_2 ;
  input \rsMask_reg[3][10]_2 ;
  input \rsMask_reg[7][12]_2 ;
  input \rsMask_reg[5][12]_2 ;
  input \rsMask_reg[3][12]_2 ;
  input \rsMask_reg[1][18]_7 ;
  input \rsMask_reg[1][6]_2 ;
  input \rsMask_reg[1][15]_2 ;
  input \rsMask_reg[1][16]_2 ;
  input \rsMask_reg[1][17]_2 ;
  input \rsMask_reg[1][18]_8 ;
  input [1:0]\blk1.(null)[0].diff_3 ;
  input \rsMask_reg[1][8]_2 ;
  input \rsMask_reg[3][18]_7 ;
  input \rsMask_reg[3][6]_2 ;
  input \rsMask_reg[3][15]_2 ;
  input \rsMask_reg[3][16]_2 ;
  input \rsMask_reg[3][17]_2 ;
  input \rsMask_reg[3][18]_8 ;
  input \rsMask_reg[3][9]_5 ;
  input \rsMask_reg[3][8]_2 ;
  input \rsMask_reg[3][9]_6 ;
  input \rsMask_reg[5][18]_7 ;
  input \rsMask_reg[5][6]_2 ;
  input \rsMask_reg[5][15]_2 ;
  input \rsMask_reg[5][16]_2 ;
  input \rsMask_reg[5][17]_2 ;
  input \rsMask_reg[5][18]_8 ;
  input \rsMask_reg[5][9]_5 ;
  input \rsMask_reg[5][8]_2 ;
  input \rsMask_reg[5][9]_6 ;
  input \rsMask_reg[7][18]_21 ;
  input \rsMask_reg[7][6]_2 ;
  input \rsMask_reg[7][15]_2 ;
  input \rsMask_reg[7][16]_2 ;
  input \rsMask_reg[7][17]_16 ;
  input \rsMask_reg[7][18]_22 ;
  input \rsMask_reg[7][9]_5 ;
  input \rsMask_reg[7][8]_2 ;
  input \rsMask_reg[7][9]_6 ;
  input [1:0]\rdEn_reg[29]_2 ;
  input \rsMask_reg[7][2]_3 ;
  input \rsMask_reg[5][2]_3 ;
  input \rsMask_reg[3][2]_3 ;
  input [4:0]rs2mask0_4;
  input \rsMask_reg[7][3]_3 ;
  input \rsMask_reg[5][3]_3 ;
  input \rsMask_reg[3][3]_3 ;
  input \rsMask_reg[7][10]_3 ;
  input \rsMask_reg[5][10]_3 ;
  input \rsMask_reg[3][10]_3 ;
  input \rsMask_reg[7][12]_3 ;
  input \rsMask_reg[5][12]_3 ;
  input \rsMask_reg[3][12]_3 ;
  input \rsMask_reg[1][18]_9 ;
  input \rsMask_reg[1][6]_3 ;
  input \rsMask_reg[1][15]_3 ;
  input \rsMask_reg[1][16]_3 ;
  input \rsMask_reg[1][17]_3 ;
  input \rsMask_reg[1][18]_10 ;
  input [1:0]\blk1.(null)[0].diff_5 ;
  input \rsMask_reg[1][8]_3 ;
  input \rsMask_reg[3][18]_9 ;
  input \rsMask_reg[3][6]_3 ;
  input \rsMask_reg[3][15]_3 ;
  input \rsMask_reg[3][16]_3 ;
  input \rsMask_reg[3][17]_3 ;
  input \rsMask_reg[3][18]_10 ;
  input \rsMask_reg[3][9]_7 ;
  input \rsMask_reg[3][8]_3 ;
  input \rsMask_reg[3][9]_8 ;
  input \rsMask_reg[5][18]_9 ;
  input \rsMask_reg[5][6]_3 ;
  input \rsMask_reg[5][15]_3 ;
  input \rsMask_reg[5][16]_3 ;
  input \rsMask_reg[5][17]_3 ;
  input \rsMask_reg[5][18]_10 ;
  input \rsMask_reg[5][9]_7 ;
  input \rsMask_reg[5][8]_3 ;
  input \rsMask_reg[5][9]_8 ;
  input \rsMask_reg[7][18]_23 ;
  input \rsMask_reg[7][6]_3 ;
  input \rsMask_reg[7][15]_3 ;
  input \rsMask_reg[7][16]_3 ;
  input \rsMask_reg[7][17]_17 ;
  input \rsMask_reg[7][18]_24 ;
  input \rsMask_reg[7][9]_7 ;
  input \rsMask_reg[7][8]_3 ;
  input \rsMask_reg[7][9]_8 ;
  input [1:0]\rdEn_reg[29]_3 ;
  input \rsMask_reg[7][2]_4 ;
  input \rsMask_reg[5][2]_4 ;
  input \rsMask_reg[3][2]_4 ;
  input [4:0]rs2mask0_6;
  input \rsMask_reg[7][3]_4 ;
  input \rsMask_reg[5][3]_4 ;
  input \rsMask_reg[3][3]_4 ;
  input \rsMask_reg[7][10]_4 ;
  input \rsMask_reg[5][10]_4 ;
  input \rsMask_reg[3][10]_4 ;
  input \rsMask_reg[7][12]_4 ;
  input \rsMask_reg[5][12]_4 ;
  input \rsMask_reg[3][12]_4 ;
  input \rsMask_reg[1][18]_11 ;
  input \rsMask_reg[1][6]_4 ;
  input \rsMask_reg[1][15]_4 ;
  input \rsMask_reg[1][16]_4 ;
  input \rsMask_reg[1][17]_4 ;
  input \rsMask_reg[1][18]_12 ;
  input [1:0]\blk1.(null)[0].diff_7 ;
  input \rsMask_reg[1][8]_4 ;
  input \rsMask_reg[3][18]_11 ;
  input \rsMask_reg[3][6]_4 ;
  input \rsMask_reg[3][15]_4 ;
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  input \rsMask_reg[5][9]_30 ;
  input \rsMask_reg[7][18]_45 ;
  input \rsMask_reg[7][6]_14 ;
  input \rsMask_reg[7][15]_14 ;
  input \rsMask_reg[7][16]_14 ;
  input \rsMask_reg[7][17]_28 ;
  input \rsMask_reg[7][18]_46 ;
  input \rsMask_reg[7][9]_29 ;
  input \rsMask_reg[7][8]_14 ;
  input \rsMask_reg[7][9]_30 ;
  input [5:0]\rsMask_reg[1][11] ;
  input [5:0]\rsMask_reg[3][11] ;
  input [5:0]\rsMask_reg[5][11] ;
  input [5:0]\rsMask_reg[7][11] ;
  input mcRdCAS;
  input \oe_low_reg[5] ;
  input calRdCAS;
  input read_lat_shift_cal_dq_valid_nxt;
  input [0:0]\rams[1].RAM32M0 ;
  input mcWrCAS;
  input mcCasSlot2;
  input \wrQ_reg[0][2] ;
  input \rdEn_reg[12] ;
  input \rdEn_reg[12]_0 ;
  input [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ;
  input [0:0]DOA;
  input [4:0]\not_strict_mode.app_rd_data_end_reg ;
  input [511:0]D;
  input [1:0]DOC;
  input [1:0]DOB;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ;
  input [4:0]\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] ;
  input [4:0]\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] ;
  input [4:0]\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] ;
  input [4:0]\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] ;
  input cnt_clr;
  input \rdEn_reg[13] ;
  input \rdEn_reg[12]_1 ;
  input \rdEn_reg[14] ;
  input \rdEn_reg[12]_2 ;
  input \rdEn_reg[14]_0 ;
  input [1:0]\dReg_reg[9] ;
  input [511:0]DQOut;
  input [63:0]DMOut;
  input \dReg_reg[7] ;
  input \dReg_reg[6] ;
  input \dReg_reg[7]_0 ;
  input \dReg_reg[6]_0 ;
  input \dReg_reg[7]_1 ;
  input \dReg_reg[6]_1 ;
  input \dReg_reg[7]_2 ;
  input \dReg_reg[6]_2 ;
  input \dReg_reg[7]_3 ;
  input \dReg_reg[6]_3 ;
  input \dReg_reg[7]_4 ;
  input \dReg_reg[6]_4 ;
  input \dReg_reg[7]_5 ;
  input \dReg_reg[6]_5 ;
  input \dReg_reg[7]_6 ;
  input \dReg_reg[6]_6 ;
  input \dReg_reg[7]_7 ;
  input \dReg_reg[6]_7 ;
  input [1:0]\dReg_reg[9]_0 ;
  input \dReg_reg[7]_8 ;
  input \dReg_reg[6]_8 ;
  input \dReg_reg[7]_9 ;
  input \dReg_reg[6]_9 ;
  input \dReg_reg[7]_10 ;
  input \dReg_reg[6]_10 ;
  input \dReg_reg[7]_11 ;
  input \dReg_reg[6]_11 ;
  input \dReg_reg[7]_12 ;
  input \dReg_reg[6]_12 ;
  input \dReg_reg[7]_13 ;
  input \dReg_reg[6]_13 ;
  input \dReg_reg[7]_14 ;
  input \dReg_reg[6]_14 ;
  input \dReg_reg[7]_15 ;
  input \dReg_reg[6]_15 ;
  input \dReg_reg[7]_16 ;
  input \dReg_reg[6]_16 ;
  input [1:0]\dReg_reg[9]_1 ;
  input \dReg_reg[7]_17 ;
  input \dReg_reg[6]_17 ;
  input \dReg_reg[7]_18 ;
  input \dReg_reg[6]_18 ;
  input \dReg_reg[7]_19 ;
  input \dReg_reg[6]_19 ;
  input \dReg_reg[7]_20 ;
  input \dReg_reg[6]_20 ;
  input \dReg_reg[7]_21 ;
  input \dReg_reg[6]_21 ;
  input \dReg_reg[7]_22 ;
  input \dReg_reg[6]_22 ;
  input \dReg_reg[7]_23 ;
  input \dReg_reg[6]_23 ;
  input \dReg_reg[7]_24 ;
  input \dReg_reg[6]_24 ;
  input \dReg_reg[7]_25 ;
  input \dReg_reg[6]_25 ;
  input [1:0]\dReg_reg[9]_2 ;
  input \dReg_reg[7]_26 ;
  input \dReg_reg[6]_26 ;
  input \dReg_reg[7]_27 ;
  input \dReg_reg[6]_27 ;
  input \dReg_reg[7]_28 ;
  input \dReg_reg[6]_28 ;
  input \dReg_reg[7]_29 ;
  input \dReg_reg[6]_29 ;
  input \dReg_reg[7]_30 ;
  input \dReg_reg[6]_30 ;
  input \dReg_reg[7]_31 ;
  input \dReg_reg[6]_31 ;
  input \dReg_reg[7]_32 ;
  input \dReg_reg[6]_32 ;
  input \dReg_reg[7]_33 ;
  input \dReg_reg[6]_33 ;
  input \dReg_reg[7]_34 ;
  input \dReg_reg[6]_34 ;
  input [1:0]\dReg_reg[9]_3 ;
  input \dReg_reg[7]_35 ;
  input \dReg_reg[6]_35 ;
  input \dReg_reg[7]_36 ;
  input \dReg_reg[6]_36 ;
  input \dReg_reg[7]_37 ;
  input \dReg_reg[6]_37 ;
  input \dReg_reg[7]_38 ;
  input \dReg_reg[6]_38 ;
  input \dReg_reg[7]_39 ;
  input \dReg_reg[6]_39 ;
  input \dReg_reg[7]_40 ;
  input \dReg_reg[6]_40 ;
  input \dReg_reg[7]_41 ;
  input \dReg_reg[6]_41 ;
  input \dReg_reg[7]_42 ;
  input \dReg_reg[6]_42 ;
  input \dReg_reg[7]_43 ;
  input \dReg_reg[6]_43 ;
  input [1:0]\dReg_reg[9]_4 ;
  input \dReg_reg[7]_44 ;
  input \dReg_reg[6]_44 ;
  input \dReg_reg[7]_45 ;
  input \dReg_reg[6]_45 ;
  input \dReg_reg[7]_46 ;
  input \dReg_reg[6]_46 ;
  input \dReg_reg[7]_47 ;
  input \dReg_reg[6]_47 ;
  input \dReg_reg[7]_48 ;
  input \dReg_reg[6]_48 ;
  input \dReg_reg[7]_49 ;
  input \dReg_reg[6]_49 ;
  input \dReg_reg[7]_50 ;
  input \dReg_reg[6]_50 ;
  input \dReg_reg[7]_51 ;
  input \dReg_reg[6]_51 ;
  input \dReg_reg[7]_52 ;
  input \dReg_reg[6]_52 ;
  input [1:0]\dReg_reg[9]_5 ;
  input \dReg_reg[7]_53 ;
  input \dReg_reg[6]_53 ;
  input \dReg_reg[7]_54 ;
  input \dReg_reg[6]_54 ;
  input \dReg_reg[7]_55 ;
  input \dReg_reg[6]_55 ;
  input \dReg_reg[7]_56 ;
  input \dReg_reg[6]_56 ;
  input \dReg_reg[7]_57 ;
  input \dReg_reg[6]_57 ;
  input \dReg_reg[7]_58 ;
  input \dReg_reg[6]_58 ;
  input \dReg_reg[7]_59 ;
  input \dReg_reg[6]_59 ;
  input \dReg_reg[7]_60 ;
  input \dReg_reg[6]_60 ;
  input \dReg_reg[7]_61 ;
  input \dReg_reg[6]_61 ;
  input [1:0]\dReg_reg[9]_6 ;
  input \dReg_reg[7]_62 ;
  input \dReg_reg[6]_62 ;
  input \dReg_reg[7]_63 ;
  input \dReg_reg[6]_63 ;
  input \dReg_reg[7]_64 ;
  input \dReg_reg[6]_64 ;
  input \dReg_reg[7]_65 ;
  input \dReg_reg[6]_65 ;
  input \dReg_reg[7]_66 ;
  input \dReg_reg[6]_66 ;
  input \dReg_reg[7]_67 ;
  input \dReg_reg[6]_67 ;
  input \dReg_reg[7]_68 ;
  input \dReg_reg[6]_68 ;
  input \dReg_reg[7]_69 ;
  input \dReg_reg[6]_69 ;
  input \dReg_reg[7]_70 ;
  input \dReg_reg[6]_70 ;
  input \rdEn_reg[12]_3 ;
  input mcalRdCAS;
  input [0:0]mcalCasSlot;
  input [1:0]mcalRank;
  input [4:0]\wrQ_reg[1][8]_0 ;
  input [0:0]\wrQ_nxt[1]_13 ;
  input [3:0]\wrQ_reg[0][8] ;
  input \wrQ_reg[0][7]_rep ;
  input \wrQ_reg[0][7]_rep__0 ;
  input \wrQ_reg[0][7]_rep__1 ;
  input \wrQ_reg[0][5]_rep ;
  input \wrQ_reg[0][5]_rep__0 ;
  input \wrQ_reg[0][5]_rep__1 ;
  input \wrQ_reg[0][6]_rep ;
  input \wrQ_reg[0][6]_rep__0 ;
  input \wrQ_reg[0][6]_rep__1 ;
  input \wrQ_reg[0][8]_rep ;
  input \wrQ_reg[0][8]_rep__0_0 ;
  input \wrQ_reg[0][8]_rep__1_0 ;
  input [2:0]\rsMask_reg[0][9] ;
  input \rsMask_reg[0][11] ;
  input \rsMask_reg[1][5] ;
  input \rsMask_reg[1][1] ;
  input \rsMask_reg[1][4] ;
  input [2:0]\rsMask_reg[2][9] ;
  input \rsMask_reg[2][11] ;
  input \rsMask_reg[3][5] ;
  input \rsMask_reg[3][1] ;
  input \rsMask_reg[3][4] ;
  input [2:0]\rsMask_reg[4][9] ;
  input \rsMask_reg[4][11] ;
  input \rsMask_reg[5][5] ;
  input \rsMask_reg[5][1] ;
  input \rsMask_reg[5][4] ;
  input [2:0]\rsMask_reg[6][9] ;
  input \rsMask_reg[6][11] ;
  input \rsMask_reg[7][5] ;
  input \rsMask_reg[7][1] ;
  input \rsMask_reg[7][4] ;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;
  input [2:0]\rsMask_reg[0][9]_1 ;
  input \rsMask_reg[0][11]_1 ;
  input \rsMask_reg[1][5]_1 ;
  input \rsMask_reg[1][1]_1 ;
  input \rsMask_reg[1][4]_1 ;
  input [2:0]\rsMask_reg[2][9]_1 ;
  input \rsMask_reg[2][11]_1 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_1 ;
  input \rsMask_reg[3][1]_1 ;
  input \rsMask_reg[3][4]_1 ;
  input [2:0]\rsMask_reg[4][9]_1 ;
  input \rsMask_reg[4][11]_1 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_1 ;
  input \rsMask_reg[5][1]_1 ;
  input \rsMask_reg[5][4]_1 ;
  input [2:0]\rsMask_reg[6][9]_1 ;
  input \rsMask_reg[6][11]_1 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_1 ;
  input \rsMask_reg[7][1]_1 ;
  input \rsMask_reg[7][4]_1 ;
  input \dReg_reg[11] ;
  input \dReg_reg[10]_0 ;
  input [1:0]\dReg_reg[9]_7 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_1 ;
  input [1:0]\dReg_reg[9]_8 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_2 ;
  input [1:0]\dReg_reg[9]_9 ;
  input \dReg_reg[11]_2 ;
  input \dReg_reg[10]_3 ;
  input [1:0]\dReg_reg[9]_10 ;
  input \dReg_reg[11]_3 ;
  input \dReg_reg[10]_4 ;
  input [1:0]\dReg_reg[9]_11 ;
  input \dReg_reg[11]_4 ;
  input \dReg_reg[10]_5 ;
  input [1:0]\dReg_reg[9]_12 ;
  input \dReg_reg[11]_5 ;
  input \dReg_reg[10]_6 ;
  input [1:0]\dReg_reg[9]_13 ;
  input \dReg_reg[11]_6 ;
  input \dReg_reg[10]_7 ;
  input [1:0]\dReg_reg[9]_14 ;
  input \dReg_reg[11]_7 ;
  input \dReg_reg[10]_8 ;
  input \dReg_reg[11]_8 ;
  input \dReg_reg[10]_9 ;
  input [1:0]\dReg_reg[9]_15 ;
  input \dReg_reg[11]_9 ;
  input \dReg_reg[10]_10 ;
  input [1:0]\dReg_reg[9]_16 ;
  input \dReg_reg[11]_10 ;
  input \dReg_reg[10]_11 ;
  input [1:0]\dReg_reg[9]_17 ;
  input \dReg_reg[11]_11 ;
  input \dReg_reg[10]_12 ;
  input [1:0]\dReg_reg[9]_18 ;
  input \dReg_reg[11]_12 ;
  input \dReg_reg[10]_13 ;
  input [1:0]\dReg_reg[9]_19 ;
  input \dReg_reg[11]_13 ;
  input \dReg_reg[10]_14 ;
  input [1:0]\dReg_reg[9]_20 ;
  input \dReg_reg[11]_14 ;
  input \dReg_reg[10]_15 ;
  input [1:0]\dReg_reg[9]_21 ;
  input \dReg_reg[11]_15 ;
  input \dReg_reg[10]_16 ;
  input [1:0]\dReg_reg[9]_22 ;
  input \dReg_reg[11]_16 ;
  input \dReg_reg[10]_17 ;
  input \dReg_reg[11]_17 ;
  input \dReg_reg[10]_18 ;
  input [1:0]\dReg_reg[9]_23 ;
  input \dReg_reg[11]_18 ;
  input \dReg_reg[10]_19 ;
  input [1:0]\dReg_reg[9]_24 ;
  input \dReg_reg[11]_19 ;
  input \dReg_reg[10]_20 ;
  input [1:0]\dReg_reg[9]_25 ;
  input \dReg_reg[11]_20 ;
  input \dReg_reg[10]_21 ;
  input [1:0]\dReg_reg[9]_26 ;
  input \dReg_reg[11]_21 ;
  input \dReg_reg[10]_22 ;
  input [1:0]\dReg_reg[9]_27 ;
  input \dReg_reg[11]_22 ;
  input \dReg_reg[10]_23 ;
  input [1:0]\dReg_reg[9]_28 ;
  input \dReg_reg[11]_23 ;
  input \dReg_reg[10]_24 ;
  input [1:0]\dReg_reg[9]_29 ;
  input \dReg_reg[11]_24 ;
  input \dReg_reg[10]_25 ;
  input [1:0]\dReg_reg[9]_30 ;
  input \dReg_reg[11]_25 ;
  input \dReg_reg[10]_26 ;
  input \dReg_reg[11]_26 ;
  input \dReg_reg[10]_27 ;
  input [1:0]\dReg_reg[9]_31 ;
  input \dReg_reg[11]_27 ;
  input \dReg_reg[10]_28 ;
  input [1:0]\dReg_reg[9]_32 ;
  input \dReg_reg[11]_28 ;
  input \dReg_reg[10]_29 ;
  input [1:0]\dReg_reg[9]_33 ;
  input \dReg_reg[11]_29 ;
  input \dReg_reg[10]_30 ;
  input [1:0]\dReg_reg[9]_34 ;
  input \dReg_reg[11]_30 ;
  input \dReg_reg[10]_31 ;
  input [1:0]\dReg_reg[9]_35 ;
  input \dReg_reg[11]_31 ;
  input \dReg_reg[10]_32 ;
  input [1:0]\dReg_reg[9]_36 ;
  input \dReg_reg[11]_32 ;
  input \dReg_reg[10]_33 ;
  input [1:0]\dReg_reg[9]_37 ;
  input \dReg_reg[11]_33 ;
  input \dReg_reg[10]_34 ;
  input [1:0]\dReg_reg[9]_38 ;
  input \dReg_reg[11]_34 ;
  input \dReg_reg[10]_35 ;
  input \dReg_reg[11]_35 ;
  input \dReg_reg[10]_36 ;
  input [1:0]\dReg_reg[9]_39 ;
  input \dReg_reg[11]_36 ;
  input \dReg_reg[10]_37 ;
  input [1:0]\dReg_reg[9]_40 ;
  input \dReg_reg[11]_37 ;
  input \dReg_reg[10]_38 ;
  input [1:0]\dReg_reg[9]_41 ;
  input \dReg_reg[11]_38 ;
  input \dReg_reg[10]_39 ;
  input [1:0]\dReg_reg[9]_42 ;
  input \dReg_reg[11]_39 ;
  input \dReg_reg[10]_40 ;
  input [1:0]\dReg_reg[9]_43 ;
  input \dReg_reg[11]_40 ;
  input \dReg_reg[10]_41 ;
  input [1:0]\dReg_reg[9]_44 ;
  input \dReg_reg[11]_41 ;
  input \dReg_reg[10]_42 ;
  input [1:0]\dReg_reg[9]_45 ;
  input \dReg_reg[11]_42 ;
  input \dReg_reg[10]_43 ;
  input [1:0]\dReg_reg[9]_46 ;
  input \dReg_reg[11]_43 ;
  input \dReg_reg[10]_44 ;
  input \dReg_reg[11]_44 ;
  input \dReg_reg[10]_45 ;
  input [1:0]\dReg_reg[9]_47 ;
  input \dReg_reg[11]_45 ;
  input \dReg_reg[10]_46 ;
  input [1:0]\dReg_reg[9]_48 ;
  input \dReg_reg[11]_46 ;
  input \dReg_reg[10]_47 ;
  input [1:0]\dReg_reg[9]_49 ;
  input \dReg_reg[11]_47 ;
  input \dReg_reg[10]_48 ;
  input [1:0]\dReg_reg[9]_50 ;
  input \dReg_reg[11]_48 ;
  input \dReg_reg[10]_49 ;
  input [1:0]\dReg_reg[9]_51 ;
  input \dReg_reg[11]_49 ;
  input \dReg_reg[10]_50 ;
  input [1:0]\dReg_reg[9]_52 ;
  input \dReg_reg[11]_50 ;
  input \dReg_reg[10]_51 ;
  input [1:0]\dReg_reg[9]_53 ;
  input \dReg_reg[11]_51 ;
  input \dReg_reg[10]_52 ;
  input [1:0]\dReg_reg[9]_54 ;
  input \dReg_reg[11]_52 ;
  input \dReg_reg[10]_53 ;
  input \dReg_reg[11]_53 ;
  input \dReg_reg[10]_54 ;
  input [1:0]\dReg_reg[9]_55 ;
  input \dReg_reg[11]_54 ;
  input \dReg_reg[10]_55 ;
  input [1:0]\dReg_reg[9]_56 ;
  input \dReg_reg[11]_55 ;
  input \dReg_reg[10]_56 ;
  input [1:0]\dReg_reg[9]_57 ;
  input \dReg_reg[11]_56 ;
  input \dReg_reg[10]_57 ;
  input [1:0]\dReg_reg[9]_58 ;
  input \dReg_reg[11]_57 ;
  input \dReg_reg[10]_58 ;
  input [1:0]\dReg_reg[9]_59 ;
  input \dReg_reg[11]_58 ;
  input \dReg_reg[10]_59 ;
  input [1:0]\dReg_reg[9]_60 ;
  input \dReg_reg[11]_59 ;
  input \dReg_reg[10]_60 ;
  input [1:0]\dReg_reg[9]_61 ;
  input \dReg_reg[11]_60 ;
  input \dReg_reg[10]_61 ;
  input [1:0]\dReg_reg[9]_62 ;
  input \dReg_reg[11]_61 ;
  input \dReg_reg[10]_62 ;
  input \dReg_reg[11]_62 ;
  input \dReg_reg[10]_63 ;
  input [1:0]\dReg_reg[9]_63 ;
  input \dReg_reg[11]_63 ;
  input \dReg_reg[10]_64 ;
  input [1:0]\dReg_reg[9]_64 ;
  input \dReg_reg[11]_64 ;
  input \dReg_reg[10]_65 ;
  input [1:0]\dReg_reg[9]_65 ;
  input \dReg_reg[11]_65 ;
  input \dReg_reg[10]_66 ;
  input [1:0]\dReg_reg[9]_66 ;
  input \dReg_reg[11]_66 ;
  input \dReg_reg[10]_67 ;
  input [1:0]\dReg_reg[9]_67 ;
  input \dReg_reg[11]_67 ;
  input \dReg_reg[10]_68 ;
  input [1:0]\dReg_reg[9]_68 ;
  input \dReg_reg[11]_68 ;
  input \dReg_reg[10]_69 ;
  input [1:0]\dReg_reg[9]_69 ;
  input \dReg_reg[11]_69 ;
  input \dReg_reg[10]_70 ;
  input [1:0]\dReg_reg[9]_70 ;
  input \dReg_reg[11]_70 ;
  input \dReg_reg[10]_71 ;
  input [2:0]\rsMask_reg[0][9]_2 ;
  input \rsMask_reg[0][11]_2 ;
  input \rsMask_reg[1][5]_2 ;
  input \rsMask_reg[1][1]_2 ;
  input \rsMask_reg[1][4]_2 ;
  input [2:0]\rsMask_reg[2][9]_2 ;
  input \rsMask_reg[2][11]_2 ;
  input [0:0]\rsMask_reg[3][11]_1 ;
  input \rsMask_reg[3][5]_2 ;
  input \rsMask_reg[3][1]_2 ;
  input \rsMask_reg[3][4]_2 ;
  input [2:0]\rsMask_reg[4][9]_2 ;
  input \rsMask_reg[4][11]_2 ;
  input [0:0]\rsMask_reg[5][11]_1 ;
  input \rsMask_reg[5][5]_2 ;
  input \rsMask_reg[5][1]_2 ;
  input \rsMask_reg[5][4]_2 ;
  input [2:0]\rsMask_reg[6][9]_2 ;
  input \rsMask_reg[6][11]_2 ;
  input [0:0]\rsMask_reg[7][11]_1 ;
  input \rsMask_reg[7][5]_2 ;
  input \rsMask_reg[7][1]_2 ;
  input \rsMask_reg[7][4]_2 ;
  input [2:0]\rsMask_reg[0][9]_3 ;
  input \rsMask_reg[0][11]_3 ;
  input \rsMask_reg[1][5]_3 ;
  input \rsMask_reg[1][1]_3 ;
  input \rsMask_reg[1][4]_3 ;
  input [2:0]\rsMask_reg[2][9]_3 ;
  input \rsMask_reg[2][11]_3 ;
  input [0:0]\rsMask_reg[3][11]_2 ;
  input \rsMask_reg[3][5]_3 ;
  input \rsMask_reg[3][1]_3 ;
  input \rsMask_reg[3][4]_3 ;
  input [2:0]\rsMask_reg[4][9]_3 ;
  input \rsMask_reg[4][11]_3 ;
  input [0:0]\rsMask_reg[5][11]_2 ;
  input \rsMask_reg[5][5]_3 ;
  input \rsMask_reg[5][1]_3 ;
  input \rsMask_reg[5][4]_3 ;
  input [2:0]\rsMask_reg[6][9]_3 ;
  input \rsMask_reg[6][11]_3 ;
  input [0:0]\rsMask_reg[7][11]_2 ;
  input \rsMask_reg[7][5]_3 ;
  input \rsMask_reg[7][1]_3 ;
  input \rsMask_reg[7][4]_3 ;
  input [2:0]\rsMask_reg[0][9]_4 ;
  input \rsMask_reg[0][11]_4 ;
  input \rsMask_reg[1][5]_4 ;
  input \rsMask_reg[1][1]_4 ;
  input \rsMask_reg[1][4]_4 ;
  input [2:0]\rsMask_reg[2][9]_4 ;
  input \rsMask_reg[2][11]_4 ;
  input [0:0]\rsMask_reg[3][11]_3 ;
  input \rsMask_reg[3][5]_4 ;
  input \rsMask_reg[3][1]_4 ;
  input \rsMask_reg[3][4]_4 ;
  input [2:0]\rsMask_reg[4][9]_4 ;
  input \rsMask_reg[4][11]_4 ;
  input [0:0]\rsMask_reg[5][11]_3 ;
  input \rsMask_reg[5][5]_4 ;
  input \rsMask_reg[5][1]_4 ;
  input \rsMask_reg[5][4]_4 ;
  input [2:0]\rsMask_reg[6][9]_4 ;
  input \rsMask_reg[6][11]_4 ;
  input [0:0]\rsMask_reg[7][11]_3 ;
  input \rsMask_reg[7][5]_4 ;
  input \rsMask_reg[7][1]_4 ;
  input \rsMask_reg[7][4]_4 ;
  input [2:0]\rsMask_reg[0][9]_5 ;
  input \rsMask_reg[0][11]_5 ;
  input \rsMask_reg[1][5]_5 ;
  input \rsMask_reg[1][1]_5 ;
  input \rsMask_reg[1][4]_5 ;
  input [2:0]\rsMask_reg[2][9]_5 ;
  input \rsMask_reg[2][11]_5 ;
  input [0:0]\rsMask_reg[3][11]_4 ;
  input \rsMask_reg[3][5]_5 ;
  input \rsMask_reg[3][1]_5 ;
  input \rsMask_reg[3][4]_5 ;
  input [2:0]\rsMask_reg[4][9]_5 ;
  input \rsMask_reg[4][11]_5 ;
  input [0:0]\rsMask_reg[5][11]_4 ;
  input \rsMask_reg[5][5]_5 ;
  input \rsMask_reg[5][1]_5 ;
  input \rsMask_reg[5][4]_5 ;
  input [2:0]\rsMask_reg[6][9]_5 ;
  input \rsMask_reg[6][11]_5 ;
  input [0:0]\rsMask_reg[7][11]_4 ;
  input \rsMask_reg[7][5]_5 ;
  input \rsMask_reg[7][1]_5 ;
  input \rsMask_reg[7][4]_5 ;
  input [2:0]\rsMask_reg[0][9]_6 ;
  input \rsMask_reg[0][11]_6 ;
  input \rsMask_reg[1][5]_6 ;
  input \rsMask_reg[1][1]_6 ;
  input \rsMask_reg[1][4]_6 ;
  input [2:0]\rsMask_reg[2][9]_6 ;
  input \rsMask_reg[2][11]_6 ;
  input [0:0]\rsMask_reg[3][11]_5 ;
  input \rsMask_reg[3][5]_6 ;
  input \rsMask_reg[3][1]_6 ;
  input \rsMask_reg[3][4]_6 ;
  input [2:0]\rsMask_reg[4][9]_6 ;
  input \rsMask_reg[4][11]_6 ;
  input [0:0]\rsMask_reg[5][11]_5 ;
  input \rsMask_reg[5][5]_6 ;
  input \rsMask_reg[5][1]_6 ;
  input \rsMask_reg[5][4]_6 ;
  input [2:0]\rsMask_reg[6][9]_6 ;
  input \rsMask_reg[6][11]_6 ;
  input [0:0]\rsMask_reg[7][11]_5 ;
  input \rsMask_reg[7][5]_6 ;
  input \rsMask_reg[7][1]_6 ;
  input \rsMask_reg[7][4]_6 ;
  input [2:0]\rsMask_reg[0][9]_7 ;
  input \rsMask_reg[0][11]_7 ;
  input \rsMask_reg[1][5]_7 ;
  input \rsMask_reg[1][1]_7 ;
  input \rsMask_reg[1][4]_7 ;
  input [2:0]\rsMask_reg[2][9]_7 ;
  input \rsMask_reg[2][11]_7 ;
  input [0:0]\rsMask_reg[3][11]_6 ;
  input \rsMask_reg[3][5]_7 ;
  input \rsMask_reg[3][1]_7 ;
  input \rsMask_reg[3][4]_7 ;
  input [2:0]\rsMask_reg[4][9]_7 ;
  input \rsMask_reg[4][11]_7 ;
  input [0:0]\rsMask_reg[5][11]_6 ;
  input \rsMask_reg[5][5]_7 ;
  input \rsMask_reg[5][1]_7 ;
  input \rsMask_reg[5][4]_7 ;
  input [2:0]\rsMask_reg[6][9]_7 ;
  input \rsMask_reg[6][11]_7 ;
  input [0:0]\rsMask_reg[7][11]_6 ;
  input \rsMask_reg[7][5]_7 ;
  input \rsMask_reg[7][1]_7 ;
  input \rsMask_reg[7][4]_7 ;
  input [2:0]\rsMask_reg[0][9]_8 ;
  input \rsMask_reg[0][11]_8 ;
  input \rsMask_reg[1][5]_8 ;
  input \rsMask_reg[1][1]_8 ;
  input \rsMask_reg[1][4]_8 ;
  input [2:0]\rsMask_reg[2][9]_8 ;
  input \rsMask_reg[2][11]_8 ;
  input [0:0]\rsMask_reg[3][11]_7 ;
  input \rsMask_reg[3][5]_8 ;
  input \rsMask_reg[3][1]_8 ;
  input \rsMask_reg[3][4]_8 ;
  input [2:0]\rsMask_reg[4][9]_8 ;
  input \rsMask_reg[4][11]_8 ;
  input [0:0]\rsMask_reg[5][11]_7 ;
  input \rsMask_reg[5][5]_8 ;
  input \rsMask_reg[5][1]_8 ;
  input \rsMask_reg[5][4]_8 ;
  input [2:0]\rsMask_reg[6][9]_8 ;
  input \rsMask_reg[6][11]_8 ;
  input [0:0]\rsMask_reg[7][11]_7 ;
  input \rsMask_reg[7][5]_8 ;
  input \rsMask_reg[7][1]_8 ;
  input \rsMask_reg[7][4]_8 ;
  input [2:0]\rsMask_reg[0][9]_9 ;
  input \rsMask_reg[0][11]_9 ;
  input \rsMask_reg[1][5]_9 ;
  input \rsMask_reg[1][1]_9 ;
  input \rsMask_reg[1][4]_9 ;
  input [2:0]\rsMask_reg[2][9]_9 ;
  input \rsMask_reg[2][11]_9 ;
  input [0:0]\rsMask_reg[3][11]_8 ;
  input \rsMask_reg[3][5]_9 ;
  input \rsMask_reg[3][1]_9 ;
  input \rsMask_reg[3][4]_9 ;
  input [2:0]\rsMask_reg[4][9]_9 ;
  input \rsMask_reg[4][11]_9 ;
  input [0:0]\rsMask_reg[5][11]_8 ;
  input \rsMask_reg[5][5]_9 ;
  input \rsMask_reg[5][1]_9 ;
  input \rsMask_reg[5][4]_9 ;
  input [2:0]\rsMask_reg[6][9]_9 ;
  input \rsMask_reg[6][11]_9 ;
  input [0:0]\rsMask_reg[7][11]_8 ;
  input \rsMask_reg[7][5]_9 ;
  input \rsMask_reg[7][1]_9 ;
  input \rsMask_reg[7][4]_9 ;
  input [2:0]\rsMask_reg[0][9]_10 ;
  input \rsMask_reg[0][11]_10 ;
  input \rsMask_reg[1][5]_10 ;
  input \rsMask_reg[1][1]_10 ;
  input \rsMask_reg[1][4]_10 ;
  input [2:0]\rsMask_reg[2][9]_10 ;
  input \rsMask_reg[2][11]_10 ;
  input [0:0]\rsMask_reg[3][11]_9 ;
  input \rsMask_reg[3][5]_10 ;
  input \rsMask_reg[3][1]_10 ;
  input \rsMask_reg[3][4]_10 ;
  input [2:0]\rsMask_reg[4][9]_10 ;
  input \rsMask_reg[4][11]_10 ;
  input [0:0]\rsMask_reg[5][11]_9 ;
  input \rsMask_reg[5][5]_10 ;
  input \rsMask_reg[5][1]_10 ;
  input \rsMask_reg[5][4]_10 ;
  input [2:0]\rsMask_reg[6][9]_10 ;
  input \rsMask_reg[6][11]_10 ;
  input [0:0]\rsMask_reg[7][11]_9 ;
  input \rsMask_reg[7][5]_10 ;
  input \rsMask_reg[7][1]_10 ;
  input \rsMask_reg[7][4]_10 ;
  input [2:0]\rsMask_reg[0][9]_11 ;
  input \rsMask_reg[0][11]_11 ;
  input \rsMask_reg[1][5]_11 ;
  input \rsMask_reg[1][1]_11 ;
  input \rsMask_reg[1][4]_11 ;
  input [2:0]\rsMask_reg[2][9]_11 ;
  input \rsMask_reg[2][11]_11 ;
  input [0:0]\rsMask_reg[3][11]_10 ;
  input \rsMask_reg[3][5]_11 ;
  input \rsMask_reg[3][1]_11 ;
  input \rsMask_reg[3][4]_11 ;
  input [2:0]\rsMask_reg[4][9]_11 ;
  input \rsMask_reg[4][11]_11 ;
  input [0:0]\rsMask_reg[5][11]_10 ;
  input \rsMask_reg[5][5]_11 ;
  input \rsMask_reg[5][1]_11 ;
  input \rsMask_reg[5][4]_11 ;
  input [2:0]\rsMask_reg[6][9]_11 ;
  input \rsMask_reg[6][11]_11 ;
  input [0:0]\rsMask_reg[7][11]_10 ;
  input \rsMask_reg[7][5]_11 ;
  input \rsMask_reg[7][1]_11 ;
  input \rsMask_reg[7][4]_11 ;
  input [2:0]\rsMask_reg[0][9]_12 ;
  input \rsMask_reg[0][11]_12 ;
  input \rsMask_reg[1][5]_12 ;
  input \rsMask_reg[1][1]_12 ;
  input \rsMask_reg[1][4]_12 ;
  input [2:0]\rsMask_reg[2][9]_12 ;
  input \rsMask_reg[2][11]_12 ;
  input [0:0]\rsMask_reg[3][11]_11 ;
  input \rsMask_reg[3][5]_12 ;
  input \rsMask_reg[3][1]_12 ;
  input \rsMask_reg[3][4]_12 ;
  input [2:0]\rsMask_reg[4][9]_12 ;
  input \rsMask_reg[4][11]_12 ;
  input [0:0]\rsMask_reg[5][11]_11 ;
  input \rsMask_reg[5][5]_12 ;
  input \rsMask_reg[5][1]_12 ;
  input \rsMask_reg[5][4]_12 ;
  input [2:0]\rsMask_reg[6][9]_12 ;
  input \rsMask_reg[6][11]_12 ;
  input [0:0]\rsMask_reg[7][11]_11 ;
  input \rsMask_reg[7][5]_12 ;
  input \rsMask_reg[7][1]_12 ;
  input \rsMask_reg[7][4]_12 ;
  input [2:0]\rsMask_reg[0][9]_13 ;
  input \rsMask_reg[0][11]_13 ;
  input \rsMask_reg[1][5]_13 ;
  input \rsMask_reg[1][1]_13 ;
  input \rsMask_reg[1][4]_13 ;
  input [2:0]\rsMask_reg[2][9]_13 ;
  input \rsMask_reg[2][11]_13 ;
  input [0:0]\rsMask_reg[3][11]_12 ;
  input \rsMask_reg[3][5]_13 ;
  input \rsMask_reg[3][1]_13 ;
  input \rsMask_reg[3][4]_13 ;
  input [2:0]\rsMask_reg[4][9]_13 ;
  input \rsMask_reg[4][11]_13 ;
  input [0:0]\rsMask_reg[5][11]_12 ;
  input \rsMask_reg[5][5]_13 ;
  input \rsMask_reg[5][1]_13 ;
  input \rsMask_reg[5][4]_13 ;
  input [2:0]\rsMask_reg[6][9]_13 ;
  input \rsMask_reg[6][11]_13 ;
  input [0:0]\rsMask_reg[7][11]_12 ;
  input \rsMask_reg[7][5]_13 ;
  input \rsMask_reg[7][1]_13 ;
  input \rsMask_reg[7][4]_13 ;
  input [2:0]\rsMask_reg[0][9]_14 ;
  input \rsMask_reg[0][11]_14 ;
  input \rsMask_reg[1][5]_14 ;
  input \rsMask_reg[1][1]_14 ;
  input \rsMask_reg[1][4]_14 ;
  input [2:0]\rsMask_reg[2][9]_14 ;
  input \rsMask_reg[2][11]_14 ;
  input [0:0]\rsMask_reg[3][11]_13 ;
  input \rsMask_reg[3][5]_14 ;
  input \rsMask_reg[3][1]_14 ;
  input \rsMask_reg[3][4]_14 ;
  input [2:0]\rsMask_reg[4][9]_14 ;
  input \rsMask_reg[4][11]_14 ;
  input [0:0]\rsMask_reg[5][11]_13 ;
  input \rsMask_reg[5][5]_14 ;
  input \rsMask_reg[5][1]_14 ;
  input \rsMask_reg[5][4]_14 ;
  input [2:0]\rsMask_reg[6][9]_14 ;
  input \rsMask_reg[6][11]_14 ;
  input [0:0]\rsMask_reg[7][11]_13 ;
  input \rsMask_reg[7][5]_14 ;
  input \rsMask_reg[7][1]_14 ;
  input \rsMask_reg[7][4]_14 ;
  input [6:0]\read_lat_fifo_in_reg[6] ;
  input [19:0]cmdBuf;
  input cal_clear_fifo_rden;

  wire [3:0]ADDRA;
  wire [3:0]ADDRC;
  wire [511:0]D;
  wire [63:0]DMOut;
  wire [0:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire [511:0]DQOut;
  wire [4:0]Q;
  wire [0:0]SR;
  wire [1:0]\blk1.(null)[0].diff ;
  wire [1:0]\blk1.(null)[0].diff_0 ;
  wire [1:0]\blk1.(null)[0].diff_1 ;
  wire [1:0]\blk1.(null)[0].diff_11 ;
  wire [1:0]\blk1.(null)[0].diff_13 ;
  wire [1:0]\blk1.(null)[0].diff_15 ;
  wire [1:0]\blk1.(null)[0].diff_17 ;
  wire [1:0]\blk1.(null)[0].diff_19 ;
  wire [1:0]\blk1.(null)[0].diff_21 ;
  wire [1:0]\blk1.(null)[0].diff_23 ;
  wire [1:0]\blk1.(null)[0].diff_25 ;
  wire [1:0]\blk1.(null)[0].diff_27 ;
  wire [1:0]\blk1.(null)[0].diff_3 ;
  wire [1:0]\blk1.(null)[0].diff_5 ;
  wire [1:0]\blk1.(null)[0].diff_7 ;
  wire [1:0]\blk1.(null)[0].diff_9 ;
  wire calDone_reg;
  wire calRdCAS;
  wire cal_clear_fifo_rden;
  wire [0:0]cal_oe_dis_low;
  wire [0:0]cal_oe_dis_upp;
  wire [63:0]ch0_mcal_DMOut_n;
  wire [511:0]ch0_mcal_DQOut;
  wire [31:0]ch0_mcal_clb2phy_rden_low;
  wire [31:0]ch0_mcal_clb2phy_rden_upp;
  wire [19:0]cmdBuf;
  wire cnt_clr;
  wire \dReg_reg[10] ;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_10 ;
  wire \dReg_reg[10]_11 ;
  wire \dReg_reg[10]_12 ;
  wire \dReg_reg[10]_13 ;
  wire \dReg_reg[10]_14 ;
  wire \dReg_reg[10]_15 ;
  wire \dReg_reg[10]_16 ;
  wire \dReg_reg[10]_17 ;
  wire \dReg_reg[10]_18 ;
  wire \dReg_reg[10]_19 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[10]_20 ;
  wire \dReg_reg[10]_21 ;
  wire \dReg_reg[10]_22 ;
  wire \dReg_reg[10]_23 ;
  wire \dReg_reg[10]_24 ;
  wire \dReg_reg[10]_25 ;
  wire \dReg_reg[10]_26 ;
  wire \dReg_reg[10]_27 ;
  wire \dReg_reg[10]_28 ;
  wire \dReg_reg[10]_29 ;
  wire \dReg_reg[10]_3 ;
  wire \dReg_reg[10]_30 ;
  wire \dReg_reg[10]_31 ;
  wire \dReg_reg[10]_32 ;
  wire \dReg_reg[10]_33 ;
  wire \dReg_reg[10]_34 ;
  wire \dReg_reg[10]_35 ;
  wire \dReg_reg[10]_36 ;
  wire \dReg_reg[10]_37 ;
  wire \dReg_reg[10]_38 ;
  wire \dReg_reg[10]_39 ;
  wire \dReg_reg[10]_4 ;
  wire \dReg_reg[10]_40 ;
  wire \dReg_reg[10]_41 ;
  wire \dReg_reg[10]_42 ;
  wire \dReg_reg[10]_43 ;
  wire \dReg_reg[10]_44 ;
  wire \dReg_reg[10]_45 ;
  wire \dReg_reg[10]_46 ;
  wire \dReg_reg[10]_47 ;
  wire \dReg_reg[10]_48 ;
  wire \dReg_reg[10]_49 ;
  wire \dReg_reg[10]_5 ;
  wire \dReg_reg[10]_50 ;
  wire \dReg_reg[10]_51 ;
  wire \dReg_reg[10]_52 ;
  wire \dReg_reg[10]_53 ;
  wire \dReg_reg[10]_54 ;
  wire \dReg_reg[10]_55 ;
  wire \dReg_reg[10]_56 ;
  wire \dReg_reg[10]_57 ;
  wire \dReg_reg[10]_58 ;
  wire \dReg_reg[10]_59 ;
  wire \dReg_reg[10]_6 ;
  wire \dReg_reg[10]_60 ;
  wire \dReg_reg[10]_61 ;
  wire \dReg_reg[10]_62 ;
  wire \dReg_reg[10]_63 ;
  wire \dReg_reg[10]_64 ;
  wire \dReg_reg[10]_65 ;
  wire \dReg_reg[10]_66 ;
  wire \dReg_reg[10]_67 ;
  wire \dReg_reg[10]_68 ;
  wire \dReg_reg[10]_69 ;
  wire \dReg_reg[10]_7 ;
  wire \dReg_reg[10]_70 ;
  wire \dReg_reg[10]_71 ;
  wire \dReg_reg[10]_8 ;
  wire \dReg_reg[10]_9 ;
  wire \dReg_reg[11] ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire \dReg_reg[11]_10 ;
  wire \dReg_reg[11]_11 ;
  wire \dReg_reg[11]_12 ;
  wire \dReg_reg[11]_13 ;
  wire \dReg_reg[11]_14 ;
  wire \dReg_reg[11]_15 ;
  wire \dReg_reg[11]_16 ;
  wire \dReg_reg[11]_17 ;
  wire \dReg_reg[11]_18 ;
  wire \dReg_reg[11]_19 ;
  wire \dReg_reg[11]_2 ;
  wire \dReg_reg[11]_20 ;
  wire \dReg_reg[11]_21 ;
  wire \dReg_reg[11]_22 ;
  wire \dReg_reg[11]_23 ;
  wire \dReg_reg[11]_24 ;
  wire \dReg_reg[11]_25 ;
  wire \dReg_reg[11]_26 ;
  wire \dReg_reg[11]_27 ;
  wire \dReg_reg[11]_28 ;
  wire \dReg_reg[11]_29 ;
  wire \dReg_reg[11]_3 ;
  wire \dReg_reg[11]_30 ;
  wire \dReg_reg[11]_31 ;
  wire \dReg_reg[11]_32 ;
  wire \dReg_reg[11]_33 ;
  wire \dReg_reg[11]_34 ;
  wire \dReg_reg[11]_35 ;
  wire \dReg_reg[11]_36 ;
  wire \dReg_reg[11]_37 ;
  wire \dReg_reg[11]_38 ;
  wire \dReg_reg[11]_39 ;
  wire \dReg_reg[11]_4 ;
  wire \dReg_reg[11]_40 ;
  wire \dReg_reg[11]_41 ;
  wire \dReg_reg[11]_42 ;
  wire \dReg_reg[11]_43 ;
  wire \dReg_reg[11]_44 ;
  wire \dReg_reg[11]_45 ;
  wire \dReg_reg[11]_46 ;
  wire \dReg_reg[11]_47 ;
  wire \dReg_reg[11]_48 ;
  wire \dReg_reg[11]_49 ;
  wire \dReg_reg[11]_5 ;
  wire \dReg_reg[11]_50 ;
  wire \dReg_reg[11]_51 ;
  wire \dReg_reg[11]_52 ;
  wire \dReg_reg[11]_53 ;
  wire \dReg_reg[11]_54 ;
  wire \dReg_reg[11]_55 ;
  wire \dReg_reg[11]_56 ;
  wire \dReg_reg[11]_57 ;
  wire \dReg_reg[11]_58 ;
  wire \dReg_reg[11]_59 ;
  wire \dReg_reg[11]_6 ;
  wire \dReg_reg[11]_60 ;
  wire \dReg_reg[11]_61 ;
  wire \dReg_reg[11]_62 ;
  wire \dReg_reg[11]_63 ;
  wire \dReg_reg[11]_64 ;
  wire \dReg_reg[11]_65 ;
  wire \dReg_reg[11]_66 ;
  wire \dReg_reg[11]_67 ;
  wire \dReg_reg[11]_68 ;
  wire \dReg_reg[11]_69 ;
  wire \dReg_reg[11]_7 ;
  wire \dReg_reg[11]_70 ;
  wire \dReg_reg[11]_8 ;
  wire \dReg_reg[11]_9 ;
  wire \dReg_reg[6] ;
  wire \dReg_reg[6]_0 ;
  wire \dReg_reg[6]_1 ;
  wire \dReg_reg[6]_10 ;
  wire \dReg_reg[6]_11 ;
  wire \dReg_reg[6]_12 ;
  wire \dReg_reg[6]_13 ;
  wire \dReg_reg[6]_14 ;
  wire \dReg_reg[6]_15 ;
  wire \dReg_reg[6]_16 ;
  wire \dReg_reg[6]_17 ;
  wire \dReg_reg[6]_18 ;
  wire \dReg_reg[6]_19 ;
  wire \dReg_reg[6]_2 ;
  wire \dReg_reg[6]_20 ;
  wire \dReg_reg[6]_21 ;
  wire \dReg_reg[6]_22 ;
  wire \dReg_reg[6]_23 ;
  wire \dReg_reg[6]_24 ;
  wire \dReg_reg[6]_25 ;
  wire \dReg_reg[6]_26 ;
  wire \dReg_reg[6]_27 ;
  wire \dReg_reg[6]_28 ;
  wire \dReg_reg[6]_29 ;
  wire \dReg_reg[6]_3 ;
  wire \dReg_reg[6]_30 ;
  wire \dReg_reg[6]_31 ;
  wire \dReg_reg[6]_32 ;
  wire \dReg_reg[6]_33 ;
  wire \dReg_reg[6]_34 ;
  wire \dReg_reg[6]_35 ;
  wire \dReg_reg[6]_36 ;
  wire \dReg_reg[6]_37 ;
  wire \dReg_reg[6]_38 ;
  wire \dReg_reg[6]_39 ;
  wire \dReg_reg[6]_4 ;
  wire \dReg_reg[6]_40 ;
  wire \dReg_reg[6]_41 ;
  wire \dReg_reg[6]_42 ;
  wire \dReg_reg[6]_43 ;
  wire \dReg_reg[6]_44 ;
  wire \dReg_reg[6]_45 ;
  wire \dReg_reg[6]_46 ;
  wire \dReg_reg[6]_47 ;
  wire \dReg_reg[6]_48 ;
  wire \dReg_reg[6]_49 ;
  wire \dReg_reg[6]_5 ;
  wire \dReg_reg[6]_50 ;
  wire \dReg_reg[6]_51 ;
  wire \dReg_reg[6]_52 ;
  wire \dReg_reg[6]_53 ;
  wire \dReg_reg[6]_54 ;
  wire \dReg_reg[6]_55 ;
  wire \dReg_reg[6]_56 ;
  wire \dReg_reg[6]_57 ;
  wire \dReg_reg[6]_58 ;
  wire \dReg_reg[6]_59 ;
  wire \dReg_reg[6]_6 ;
  wire \dReg_reg[6]_60 ;
  wire \dReg_reg[6]_61 ;
  wire \dReg_reg[6]_62 ;
  wire \dReg_reg[6]_63 ;
  wire \dReg_reg[6]_64 ;
  wire \dReg_reg[6]_65 ;
  wire \dReg_reg[6]_66 ;
  wire \dReg_reg[6]_67 ;
  wire \dReg_reg[6]_68 ;
  wire \dReg_reg[6]_69 ;
  wire \dReg_reg[6]_7 ;
  wire \dReg_reg[6]_70 ;
  wire \dReg_reg[6]_8 ;
  wire \dReg_reg[6]_9 ;
  wire \dReg_reg[7] ;
  wire \dReg_reg[7]_0 ;
  wire \dReg_reg[7]_1 ;
  wire \dReg_reg[7]_10 ;
  wire \dReg_reg[7]_11 ;
  wire \dReg_reg[7]_12 ;
  wire \dReg_reg[7]_13 ;
  wire \dReg_reg[7]_14 ;
  wire \dReg_reg[7]_15 ;
  wire \dReg_reg[7]_16 ;
  wire \dReg_reg[7]_17 ;
  wire \dReg_reg[7]_18 ;
  wire \dReg_reg[7]_19 ;
  wire \dReg_reg[7]_2 ;
  wire \dReg_reg[7]_20 ;
  wire \dReg_reg[7]_21 ;
  wire \dReg_reg[7]_22 ;
  wire \dReg_reg[7]_23 ;
  wire \dReg_reg[7]_24 ;
  wire \dReg_reg[7]_25 ;
  wire \dReg_reg[7]_26 ;
  wire \dReg_reg[7]_27 ;
  wire \dReg_reg[7]_28 ;
  wire \dReg_reg[7]_29 ;
  wire \dReg_reg[7]_3 ;
  wire \dReg_reg[7]_30 ;
  wire \dReg_reg[7]_31 ;
  wire \dReg_reg[7]_32 ;
  wire \dReg_reg[7]_33 ;
  wire \dReg_reg[7]_34 ;
  wire \dReg_reg[7]_35 ;
  wire \dReg_reg[7]_36 ;
  wire \dReg_reg[7]_37 ;
  wire \dReg_reg[7]_38 ;
  wire \dReg_reg[7]_39 ;
  wire \dReg_reg[7]_4 ;
  wire \dReg_reg[7]_40 ;
  wire \dReg_reg[7]_41 ;
  wire \dReg_reg[7]_42 ;
  wire \dReg_reg[7]_43 ;
  wire \dReg_reg[7]_44 ;
  wire \dReg_reg[7]_45 ;
  wire \dReg_reg[7]_46 ;
  wire \dReg_reg[7]_47 ;
  wire \dReg_reg[7]_48 ;
  wire \dReg_reg[7]_49 ;
  wire \dReg_reg[7]_5 ;
  wire \dReg_reg[7]_50 ;
  wire \dReg_reg[7]_51 ;
  wire \dReg_reg[7]_52 ;
  wire \dReg_reg[7]_53 ;
  wire \dReg_reg[7]_54 ;
  wire \dReg_reg[7]_55 ;
  wire \dReg_reg[7]_56 ;
  wire \dReg_reg[7]_57 ;
  wire \dReg_reg[7]_58 ;
  wire \dReg_reg[7]_59 ;
  wire \dReg_reg[7]_6 ;
  wire \dReg_reg[7]_60 ;
  wire \dReg_reg[7]_61 ;
  wire \dReg_reg[7]_62 ;
  wire \dReg_reg[7]_63 ;
  wire \dReg_reg[7]_64 ;
  wire \dReg_reg[7]_65 ;
  wire \dReg_reg[7]_66 ;
  wire \dReg_reg[7]_67 ;
  wire \dReg_reg[7]_68 ;
  wire \dReg_reg[7]_69 ;
  wire \dReg_reg[7]_7 ;
  wire \dReg_reg[7]_70 ;
  wire \dReg_reg[7]_8 ;
  wire \dReg_reg[7]_9 ;
  wire [1:0]\dReg_reg[9] ;
  wire [1:0]\dReg_reg[9]_0 ;
  wire [1:0]\dReg_reg[9]_1 ;
  wire [1:0]\dReg_reg[9]_10 ;
  wire [1:0]\dReg_reg[9]_11 ;
  wire [1:0]\dReg_reg[9]_12 ;
  wire [1:0]\dReg_reg[9]_13 ;
  wire [1:0]\dReg_reg[9]_14 ;
  wire [1:0]\dReg_reg[9]_15 ;
  wire [1:0]\dReg_reg[9]_16 ;
  wire [1:0]\dReg_reg[9]_17 ;
  wire [1:0]\dReg_reg[9]_18 ;
  wire [1:0]\dReg_reg[9]_19 ;
  wire [1:0]\dReg_reg[9]_2 ;
  wire [1:0]\dReg_reg[9]_20 ;
  wire [1:0]\dReg_reg[9]_21 ;
  wire [1:0]\dReg_reg[9]_22 ;
  wire [1:0]\dReg_reg[9]_23 ;
  wire [1:0]\dReg_reg[9]_24 ;
  wire [1:0]\dReg_reg[9]_25 ;
  wire [1:0]\dReg_reg[9]_26 ;
  wire [1:0]\dReg_reg[9]_27 ;
  wire [1:0]\dReg_reg[9]_28 ;
  wire [1:0]\dReg_reg[9]_29 ;
  wire [1:0]\dReg_reg[9]_3 ;
  wire [1:0]\dReg_reg[9]_30 ;
  wire [1:0]\dReg_reg[9]_31 ;
  wire [1:0]\dReg_reg[9]_32 ;
  wire [1:0]\dReg_reg[9]_33 ;
  wire [1:0]\dReg_reg[9]_34 ;
  wire [1:0]\dReg_reg[9]_35 ;
  wire [1:0]\dReg_reg[9]_36 ;
  wire [1:0]\dReg_reg[9]_37 ;
  wire [1:0]\dReg_reg[9]_38 ;
  wire [1:0]\dReg_reg[9]_39 ;
  wire [1:0]\dReg_reg[9]_4 ;
  wire [1:0]\dReg_reg[9]_40 ;
  wire [1:0]\dReg_reg[9]_41 ;
  wire [1:0]\dReg_reg[9]_42 ;
  wire [1:0]\dReg_reg[9]_43 ;
  wire [1:0]\dReg_reg[9]_44 ;
  wire [1:0]\dReg_reg[9]_45 ;
  wire [1:0]\dReg_reg[9]_46 ;
  wire [1:0]\dReg_reg[9]_47 ;
  wire [1:0]\dReg_reg[9]_48 ;
  wire [1:0]\dReg_reg[9]_49 ;
  wire [1:0]\dReg_reg[9]_5 ;
  wire [1:0]\dReg_reg[9]_50 ;
  wire [1:0]\dReg_reg[9]_51 ;
  wire [1:0]\dReg_reg[9]_52 ;
  wire [1:0]\dReg_reg[9]_53 ;
  wire [1:0]\dReg_reg[9]_54 ;
  wire [1:0]\dReg_reg[9]_55 ;
  wire [1:0]\dReg_reg[9]_56 ;
  wire [1:0]\dReg_reg[9]_57 ;
  wire [1:0]\dReg_reg[9]_58 ;
  wire [1:0]\dReg_reg[9]_59 ;
  wire [1:0]\dReg_reg[9]_6 ;
  wire [1:0]\dReg_reg[9]_60 ;
  wire [1:0]\dReg_reg[9]_61 ;
  wire [1:0]\dReg_reg[9]_62 ;
  wire [1:0]\dReg_reg[9]_63 ;
  wire [1:0]\dReg_reg[9]_64 ;
  wire [1:0]\dReg_reg[9]_65 ;
  wire [1:0]\dReg_reg[9]_66 ;
  wire [1:0]\dReg_reg[9]_67 ;
  wire [1:0]\dReg_reg[9]_68 ;
  wire [1:0]\dReg_reg[9]_69 ;
  wire [1:0]\dReg_reg[9]_7 ;
  wire [1:0]\dReg_reg[9]_70 ;
  wire [1:0]\dReg_reg[9]_8 ;
  wire [1:0]\dReg_reg[9]_9 ;
  wire [1:0]in0;
  wire match4_10_return;
  wire match4_110_return;
  wire match4_111_return;
  wire match4_112_return;
  wire match4_113_return;
  wire match4_114_return;
  wire match4_115_return;
  wire match4_116_return;
  wire match4_117_return;
  wire match4_118_return;
  wire match4_119_return;
  wire match4_11_return;
  wire match4_120_return;
  wire match4_121_return;
  wire match4_122_return;
  wire match4_123_return;
  wire match4_124_return;
  wire match4_125_return;
  wire match4_126_return;
  wire match4_127_return;
  wire match4_128_return;
  wire match4_129_return;
  wire match4_12_return;
  wire match4_130_return;
  wire match4_131_return;
  wire match4_132_return;
  wire match4_133_return;
  wire match4_134_return;
  wire match4_135_return;
  wire match4_136_return;
  wire match4_137_return;
  wire match4_138_return;
  wire match4_139_return;
  wire match4_13_return;
  wire match4_140_return;
  wire match4_141_return;
  wire match4_142_return;
  wire match4_143_return;
  wire match4_144_return;
  wire match4_145_return;
  wire match4_146_return;
  wire match4_147_return;
  wire match4_148_return;
  wire match4_149_return;
  wire match4_14_return;
  wire match4_150_return;
  wire match4_151_return;
  wire match4_152_return;
  wire match4_153_return;
  wire match4_154_return;
  wire match4_155_return;
  wire match4_156_return;
  wire match4_157_return;
  wire match4_158_return;
  wire match4_159_return;
  wire match4_15_return;
  wire match4_160_return;
  wire match4_161_return;
  wire match4_162_return;
  wire match4_163_return;
  wire match4_164_return;
  wire match4_165_return;
  wire match4_166_return;
  wire match4_167_return;
  wire match4_168_return;
  wire match4_169_return;
  wire match4_16_return;
  wire match4_170_return;
  wire match4_171_return;
  wire match4_172_return;
  wire match4_173_return;
  wire match4_174_return;
  wire match4_175_return;
  wire match4_176_return;
  wire match4_177_return;
  wire match4_178_return;
  wire match4_179_return;
  wire match4_17_return;
  wire match4_180_return;
  wire match4_181_return;
  wire match4_182_return;
  wire match4_183_return;
  wire match4_184_return;
  wire match4_185_return;
  wire match4_186_return;
  wire match4_187_return;
  wire match4_188_return;
  wire match4_18_return;
  wire match4_19_return;
  wire match4_1_return;
  wire match6_10_return;
  wire match6_110_return;
  wire match6_111_return;
  wire match6_112_return;
  wire match6_113_return;
  wire match6_114_return;
  wire match6_115_return;
  wire match6_116_return;
  wire match6_117_return;
  wire match6_118_return;
  wire match6_119_return;
  wire match6_11_return;
  wire match6_120_return;
  wire match6_121_return;
  wire match6_122_return;
  wire match6_123_return;
  wire match6_124_return;
  wire match6_125_return;
  wire match6_126_return;
  wire match6_127_return;
  wire match6_128_return;
  wire match6_129_return;
  wire match6_12_return;
  wire match6_130_return;
  wire match6_131_return;
  wire match6_132_return;
  wire match6_133_return;
  wire match6_134_return;
  wire match6_135_return;
  wire match6_136_return;
  wire match6_137_return;
  wire match6_138_return;
  wire match6_139_return;
  wire match6_13_return;
  wire match6_140_return;
  wire match6_141_return;
  wire match6_142_return;
  wire match6_143_return;
  wire match6_144_return;
  wire match6_145_return;
  wire match6_146_return;
  wire match6_147_return;
  wire match6_148_return;
  wire match6_149_return;
  wire match6_14_return;
  wire match6_150_return;
  wire match6_151_return;
  wire match6_152_return;
  wire match6_153_return;
  wire match6_154_return;
  wire match6_155_return;
  wire match6_156_return;
  wire match6_157_return;
  wire match6_158_return;
  wire match6_159_return;
  wire match6_15_return;
  wire match6_160_return;
  wire match6_161_return;
  wire match6_162_return;
  wire match6_163_return;
  wire match6_164_return;
  wire match6_165_return;
  wire match6_166_return;
  wire match6_167_return;
  wire match6_168_return;
  wire match6_169_return;
  wire match6_16_return;
  wire match6_170_return;
  wire match6_171_return;
  wire match6_172_return;
  wire match6_173_return;
  wire match6_174_return;
  wire match6_175_return;
  wire match6_176_return;
  wire match6_177_return;
  wire match6_178_return;
  wire match6_179_return;
  wire match6_17_return;
  wire match6_180_return;
  wire match6_181_return;
  wire match6_182_return;
  wire match6_183_return;
  wire match6_184_return;
  wire match6_185_return;
  wire match6_186_return;
  wire match6_187_return;
  wire match6_188_return;
  wire match6_18_return;
  wire match6_19_return;
  wire match6_1_return;
  wire mcCasSlot2;
  wire mcRdCAS;
  wire mcWrCAS;
  wire [0:0]mc_clb2phy_fifo_rden_nxt;
  wire [0:0]mcalCasSlot;
  wire [1:0]mcalRank;
  wire mcalRdCAS;
  wire [4:0]\not_strict_mode.app_rd_data_end_reg ;
  wire \not_strict_mode.bypass_cpy2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ;
  wire [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ;
  wire [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ;
  wire \not_strict_mode.status_ram_0.RAM32M0 ;
  wire [4:0]\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] ;
  wire [4:0]\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] ;
  wire [4:0]\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] ;
  wire [4:0]\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] ;
  wire \oe_0_mux_cal_reg[0] ;
  wire \oe_0_mux_cal_reg[0]_0 ;
  wire [3:0]\oe_low_reg[3] ;
  wire \oe_low_reg[5] ;
  wire [3:0]\oe_upp_reg[3] ;
  wire per_rd_done;
  wire phy_rden_and;
  wire phy_rden_or;
  wire pointer_we;
  wire [0:0]pop_read_lat_fifo_reg;
  wire [0:0]\rams[1].RAM32M0 ;
  wire \rdDataAddr_reg[3]_rep ;
  wire \rdDataAddr_reg[3]_rep__0 ;
  wire \rdDataAddr_reg[3]_rep__1 ;
  wire \rdDataAddr_reg[4] ;
  wire \rdDataAddr_reg[4]_0 ;
  wire \rdDataAddr_reg[4]_1 ;
  wire \rdDataAddr_reg[4]_rep ;
  wire \rdDataAddr_reg[4]_rep__0 ;
  wire \rdDataAddr_reg[4]_rep__1 ;
  wire rdDataEn_pi;
  wire [5:0]\rdData_reg[101] ;
  wire [5:0]\rdData_reg[107] ;
  wire [5:0]\rdData_reg[113] ;
  wire [5:0]\rdData_reg[119] ;
  wire [5:0]\rdData_reg[11] ;
  wire [5:0]\rdData_reg[125] ;
  wire [5:0]\rdData_reg[131] ;
  wire [5:0]\rdData_reg[137] ;
  wire [5:0]\rdData_reg[143] ;
  wire [5:0]\rdData_reg[149] ;
  wire [5:0]\rdData_reg[155] ;
  wire [5:0]\rdData_reg[161] ;
  wire [5:0]\rdData_reg[167] ;
  wire [5:0]\rdData_reg[173] ;
  wire [5:0]\rdData_reg[179] ;
  wire [5:0]\rdData_reg[17] ;
  wire [5:0]\rdData_reg[185] ;
  wire [5:0]\rdData_reg[191] ;
  wire [5:0]\rdData_reg[197] ;
  wire [5:0]\rdData_reg[203] ;
  wire [5:0]\rdData_reg[209] ;
  wire [5:0]\rdData_reg[215] ;
  wire [5:0]\rdData_reg[221] ;
  wire [5:0]\rdData_reg[227] ;
  wire [5:0]\rdData_reg[233] ;
  wire [5:0]\rdData_reg[239] ;
  wire [5:0]\rdData_reg[23] ;
  wire [5:0]\rdData_reg[245] ;
  wire [5:0]\rdData_reg[251] ;
  wire [5:0]\rdData_reg[257] ;
  wire [5:0]\rdData_reg[263] ;
  wire [5:0]\rdData_reg[269] ;
  wire [5:0]\rdData_reg[275] ;
  wire [5:0]\rdData_reg[281] ;
  wire [5:0]\rdData_reg[287] ;
  wire [5:0]\rdData_reg[293] ;
  wire [5:0]\rdData_reg[299] ;
  wire [5:0]\rdData_reg[29] ;
  wire [5:0]\rdData_reg[305] ;
  wire [5:0]\rdData_reg[311] ;
  wire [5:0]\rdData_reg[317] ;
  wire [5:0]\rdData_reg[323] ;
  wire [5:0]\rdData_reg[329] ;
  wire [5:0]\rdData_reg[335] ;
  wire [5:0]\rdData_reg[341] ;
  wire [5:0]\rdData_reg[347] ;
  wire [5:0]\rdData_reg[353] ;
  wire [5:0]\rdData_reg[359] ;
  wire [5:0]\rdData_reg[35] ;
  wire [5:0]\rdData_reg[365] ;
  wire [5:0]\rdData_reg[371] ;
  wire [5:0]\rdData_reg[377] ;
  wire [5:0]\rdData_reg[383] ;
  wire [5:0]\rdData_reg[389] ;
  wire [5:0]\rdData_reg[395] ;
  wire [5:0]\rdData_reg[401] ;
  wire [5:0]\rdData_reg[407] ;
  wire [5:0]\rdData_reg[413] ;
  wire [5:0]\rdData_reg[419] ;
  wire [5:0]\rdData_reg[41] ;
  wire [5:0]\rdData_reg[425] ;
  wire [5:0]\rdData_reg[431] ;
  wire [5:0]\rdData_reg[437] ;
  wire [5:0]\rdData_reg[443] ;
  wire [5:0]\rdData_reg[449] ;
  wire [5:0]\rdData_reg[455] ;
  wire [5:0]\rdData_reg[461] ;
  wire [5:0]\rdData_reg[467] ;
  wire [5:0]\rdData_reg[473] ;
  wire [5:0]\rdData_reg[479] ;
  wire [5:0]\rdData_reg[47] ;
  wire [5:0]\rdData_reg[485] ;
  wire [5:0]\rdData_reg[491] ;
  wire [5:0]\rdData_reg[497] ;
  wire [5:0]\rdData_reg[503] ;
  wire [5:0]\rdData_reg[509] ;
  wire [1:0]\rdData_reg[511] ;
  wire [5:0]\rdData_reg[53] ;
  wire [5:0]\rdData_reg[59] ;
  wire [5:0]\rdData_reg[5] ;
  wire [5:0]\rdData_reg[65] ;
  wire [5:0]\rdData_reg[71] ;
  wire [5:0]\rdData_reg[77] ;
  wire [5:0]\rdData_reg[83] ;
  wire [5:0]\rdData_reg[89] ;
  wire [5:0]\rdData_reg[95] ;
  wire \rdEn_reg[12] ;
  wire \rdEn_reg[12]_0 ;
  wire \rdEn_reg[12]_1 ;
  wire \rdEn_reg[12]_2 ;
  wire \rdEn_reg[12]_3 ;
  wire \rdEn_reg[13] ;
  wire \rdEn_reg[14] ;
  wire \rdEn_reg[14]_0 ;
  wire [1:0]\rdEn_reg[29] ;
  wire [1:0]\rdEn_reg[29]_0 ;
  wire [1:0]\rdEn_reg[29]_1 ;
  wire [1:0]\rdEn_reg[29]_10 ;
  wire [1:0]\rdEn_reg[29]_11 ;
  wire [1:0]\rdEn_reg[29]_12 ;
  wire [1:0]\rdEn_reg[29]_13 ;
  wire [1:0]\rdEn_reg[29]_2 ;
  wire [1:0]\rdEn_reg[29]_3 ;
  wire [1:0]\rdEn_reg[29]_4 ;
  wire [1:0]\rdEn_reg[29]_5 ;
  wire [1:0]\rdEn_reg[29]_6 ;
  wire [1:0]\rdEn_reg[29]_7 ;
  wire [1:0]\rdEn_reg[29]_8 ;
  wire [1:0]\rdEn_reg[29]_9 ;
  wire [6:0]\read_lat_fifo_in_reg[6] ;
  wire read_lat_shift_cal_dq_valid_nxt;
  wire [31:0]\read_lat_shift_reg[31] ;
  wire [4:0]rs2mask0;
  wire [4:0]rs2mask0_10;
  wire [4:0]rs2mask0_12;
  wire [4:0]rs2mask0_14;
  wire [4:0]rs2mask0_16;
  wire [4:0]rs2mask0_18;
  wire [4:0]rs2mask0_2;
  wire [4:0]rs2mask0_20;
  wire [4:0]rs2mask0_22;
  wire [4:0]rs2mask0_24;
  wire [4:0]rs2mask0_26;
  wire [4:0]rs2mask0_4;
  wire [4:0]rs2mask0_6;
  wire [4:0]rs2mask0_8;
  wire \rsMask_reg[0][11] ;
  wire \rsMask_reg[0][11]_0 ;
  wire \rsMask_reg[0][11]_1 ;
  wire \rsMask_reg[0][11]_10 ;
  wire \rsMask_reg[0][11]_11 ;
  wire \rsMask_reg[0][11]_12 ;
  wire \rsMask_reg[0][11]_13 ;
  wire \rsMask_reg[0][11]_14 ;
  wire \rsMask_reg[0][11]_2 ;
  wire \rsMask_reg[0][11]_3 ;
  wire \rsMask_reg[0][11]_4 ;
  wire \rsMask_reg[0][11]_5 ;
  wire \rsMask_reg[0][11]_6 ;
  wire \rsMask_reg[0][11]_7 ;
  wire \rsMask_reg[0][11]_8 ;
  wire \rsMask_reg[0][11]_9 ;
  wire [2:0]\rsMask_reg[0][9] ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [2:0]\rsMask_reg[0][9]_1 ;
  wire [2:0]\rsMask_reg[0][9]_10 ;
  wire [2:0]\rsMask_reg[0][9]_11 ;
  wire [2:0]\rsMask_reg[0][9]_12 ;
  wire [2:0]\rsMask_reg[0][9]_13 ;
  wire [2:0]\rsMask_reg[0][9]_14 ;
  wire [2:0]\rsMask_reg[0][9]_2 ;
  wire [2:0]\rsMask_reg[0][9]_3 ;
  wire [2:0]\rsMask_reg[0][9]_4 ;
  wire [2:0]\rsMask_reg[0][9]_5 ;
  wire [2:0]\rsMask_reg[0][9]_6 ;
  wire [2:0]\rsMask_reg[0][9]_7 ;
  wire [2:0]\rsMask_reg[0][9]_8 ;
  wire [2:0]\rsMask_reg[0][9]_9 ;
  wire [5:0]\rsMask_reg[1][11] ;
  wire [3:0]\rsMask_reg[1][12] ;
  wire [3:0]\rsMask_reg[1][12]_0 ;
  wire \rsMask_reg[1][15] ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][15]_1 ;
  wire \rsMask_reg[1][15]_10 ;
  wire \rsMask_reg[1][15]_11 ;
  wire \rsMask_reg[1][15]_12 ;
  wire \rsMask_reg[1][15]_13 ;
  wire \rsMask_reg[1][15]_14 ;
  wire \rsMask_reg[1][15]_2 ;
  wire \rsMask_reg[1][15]_3 ;
  wire \rsMask_reg[1][15]_4 ;
  wire \rsMask_reg[1][15]_5 ;
  wire \rsMask_reg[1][15]_6 ;
  wire \rsMask_reg[1][15]_7 ;
  wire \rsMask_reg[1][15]_8 ;
  wire \rsMask_reg[1][15]_9 ;
  wire \rsMask_reg[1][16] ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][16]_1 ;
  wire \rsMask_reg[1][16]_10 ;
  wire \rsMask_reg[1][16]_11 ;
  wire \rsMask_reg[1][16]_12 ;
  wire \rsMask_reg[1][16]_13 ;
  wire \rsMask_reg[1][16]_14 ;
  wire \rsMask_reg[1][16]_2 ;
  wire \rsMask_reg[1][16]_3 ;
  wire \rsMask_reg[1][16]_4 ;
  wire \rsMask_reg[1][16]_5 ;
  wire \rsMask_reg[1][16]_6 ;
  wire \rsMask_reg[1][16]_7 ;
  wire \rsMask_reg[1][16]_8 ;
  wire \rsMask_reg[1][16]_9 ;
  wire \rsMask_reg[1][17] ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][17]_1 ;
  wire \rsMask_reg[1][17]_10 ;
  wire \rsMask_reg[1][17]_11 ;
  wire \rsMask_reg[1][17]_12 ;
  wire \rsMask_reg[1][17]_13 ;
  wire \rsMask_reg[1][17]_14 ;
  wire \rsMask_reg[1][17]_2 ;
  wire \rsMask_reg[1][17]_3 ;
  wire \rsMask_reg[1][17]_4 ;
  wire \rsMask_reg[1][17]_5 ;
  wire \rsMask_reg[1][17]_6 ;
  wire \rsMask_reg[1][17]_7 ;
  wire \rsMask_reg[1][17]_8 ;
  wire \rsMask_reg[1][17]_9 ;
  wire [1:0]\rsMask_reg[1][18] ;
  wire [1:0]\rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][18]_10 ;
  wire \rsMask_reg[1][18]_11 ;
  wire \rsMask_reg[1][18]_12 ;
  wire \rsMask_reg[1][18]_13 ;
  wire \rsMask_reg[1][18]_14 ;
  wire \rsMask_reg[1][18]_15 ;
  wire \rsMask_reg[1][18]_16 ;
  wire \rsMask_reg[1][18]_17 ;
  wire \rsMask_reg[1][18]_18 ;
  wire \rsMask_reg[1][18]_19 ;
  wire \rsMask_reg[1][18]_2 ;
  wire \rsMask_reg[1][18]_20 ;
  wire \rsMask_reg[1][18]_21 ;
  wire \rsMask_reg[1][18]_22 ;
  wire \rsMask_reg[1][18]_23 ;
  wire \rsMask_reg[1][18]_24 ;
  wire \rsMask_reg[1][18]_25 ;
  wire \rsMask_reg[1][18]_26 ;
  wire \rsMask_reg[1][18]_27 ;
  wire \rsMask_reg[1][18]_28 ;
  wire \rsMask_reg[1][18]_29 ;
  wire \rsMask_reg[1][18]_3 ;
  wire \rsMask_reg[1][18]_30 ;
  wire \rsMask_reg[1][18]_31 ;
  wire \rsMask_reg[1][18]_32 ;
  wire \rsMask_reg[1][18]_4 ;
  wire \rsMask_reg[1][18]_5 ;
  wire \rsMask_reg[1][18]_6 ;
  wire \rsMask_reg[1][18]_7 ;
  wire \rsMask_reg[1][18]_8 ;
  wire \rsMask_reg[1][18]_9 ;
  wire \rsMask_reg[1][1] ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][1]_1 ;
  wire \rsMask_reg[1][1]_10 ;
  wire \rsMask_reg[1][1]_11 ;
  wire \rsMask_reg[1][1]_12 ;
  wire \rsMask_reg[1][1]_13 ;
  wire \rsMask_reg[1][1]_14 ;
  wire \rsMask_reg[1][1]_2 ;
  wire \rsMask_reg[1][1]_3 ;
  wire \rsMask_reg[1][1]_4 ;
  wire \rsMask_reg[1][1]_5 ;
  wire \rsMask_reg[1][1]_6 ;
  wire \rsMask_reg[1][1]_7 ;
  wire \rsMask_reg[1][1]_8 ;
  wire \rsMask_reg[1][1]_9 ;
  wire \rsMask_reg[1][4] ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][4]_1 ;
  wire \rsMask_reg[1][4]_10 ;
  wire \rsMask_reg[1][4]_11 ;
  wire \rsMask_reg[1][4]_12 ;
  wire \rsMask_reg[1][4]_13 ;
  wire \rsMask_reg[1][4]_14 ;
  wire \rsMask_reg[1][4]_2 ;
  wire \rsMask_reg[1][4]_3 ;
  wire \rsMask_reg[1][4]_4 ;
  wire \rsMask_reg[1][4]_5 ;
  wire \rsMask_reg[1][4]_6 ;
  wire \rsMask_reg[1][4]_7 ;
  wire \rsMask_reg[1][4]_8 ;
  wire \rsMask_reg[1][4]_9 ;
  wire \rsMask_reg[1][5] ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][5]_1 ;
  wire \rsMask_reg[1][5]_10 ;
  wire \rsMask_reg[1][5]_11 ;
  wire \rsMask_reg[1][5]_12 ;
  wire \rsMask_reg[1][5]_13 ;
  wire \rsMask_reg[1][5]_14 ;
  wire \rsMask_reg[1][5]_2 ;
  wire \rsMask_reg[1][5]_3 ;
  wire \rsMask_reg[1][5]_4 ;
  wire \rsMask_reg[1][5]_5 ;
  wire \rsMask_reg[1][5]_6 ;
  wire \rsMask_reg[1][5]_7 ;
  wire \rsMask_reg[1][5]_8 ;
  wire \rsMask_reg[1][5]_9 ;
  wire \rsMask_reg[1][6] ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][6]_1 ;
  wire \rsMask_reg[1][6]_10 ;
  wire \rsMask_reg[1][6]_11 ;
  wire \rsMask_reg[1][6]_12 ;
  wire \rsMask_reg[1][6]_13 ;
  wire \rsMask_reg[1][6]_14 ;
  wire \rsMask_reg[1][6]_2 ;
  wire \rsMask_reg[1][6]_3 ;
  wire \rsMask_reg[1][6]_4 ;
  wire \rsMask_reg[1][6]_5 ;
  wire \rsMask_reg[1][6]_6 ;
  wire \rsMask_reg[1][6]_7 ;
  wire \rsMask_reg[1][6]_8 ;
  wire \rsMask_reg[1][6]_9 ;
  wire \rsMask_reg[1][8] ;
  wire \rsMask_reg[1][8]_0 ;
  wire \rsMask_reg[1][8]_1 ;
  wire \rsMask_reg[1][8]_10 ;
  wire \rsMask_reg[1][8]_11 ;
  wire \rsMask_reg[1][8]_12 ;
  wire \rsMask_reg[1][8]_13 ;
  wire \rsMask_reg[1][8]_14 ;
  wire \rsMask_reg[1][8]_2 ;
  wire \rsMask_reg[1][8]_3 ;
  wire \rsMask_reg[1][8]_4 ;
  wire \rsMask_reg[1][8]_5 ;
  wire \rsMask_reg[1][8]_6 ;
  wire \rsMask_reg[1][8]_7 ;
  wire \rsMask_reg[1][8]_8 ;
  wire \rsMask_reg[1][8]_9 ;
  wire \rsMask_reg[2][11] ;
  wire \rsMask_reg[2][11]_0 ;
  wire \rsMask_reg[2][11]_1 ;
  wire \rsMask_reg[2][11]_10 ;
  wire \rsMask_reg[2][11]_11 ;
  wire \rsMask_reg[2][11]_12 ;
  wire \rsMask_reg[2][11]_13 ;
  wire \rsMask_reg[2][11]_14 ;
  wire \rsMask_reg[2][11]_2 ;
  wire \rsMask_reg[2][11]_3 ;
  wire \rsMask_reg[2][11]_4 ;
  wire \rsMask_reg[2][11]_5 ;
  wire \rsMask_reg[2][11]_6 ;
  wire \rsMask_reg[2][11]_7 ;
  wire \rsMask_reg[2][11]_8 ;
  wire \rsMask_reg[2][11]_9 ;
  wire [2:0]\rsMask_reg[2][9] ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [2:0]\rsMask_reg[2][9]_1 ;
  wire [2:0]\rsMask_reg[2][9]_10 ;
  wire [2:0]\rsMask_reg[2][9]_11 ;
  wire [2:0]\rsMask_reg[2][9]_12 ;
  wire [2:0]\rsMask_reg[2][9]_13 ;
  wire [2:0]\rsMask_reg[2][9]_14 ;
  wire [2:0]\rsMask_reg[2][9]_2 ;
  wire [2:0]\rsMask_reg[2][9]_3 ;
  wire [2:0]\rsMask_reg[2][9]_4 ;
  wire [2:0]\rsMask_reg[2][9]_5 ;
  wire [2:0]\rsMask_reg[2][9]_6 ;
  wire [2:0]\rsMask_reg[2][9]_7 ;
  wire [2:0]\rsMask_reg[2][9]_8 ;
  wire [2:0]\rsMask_reg[2][9]_9 ;
  wire \rsMask_reg[3][10] ;
  wire \rsMask_reg[3][10]_0 ;
  wire \rsMask_reg[3][10]_1 ;
  wire \rsMask_reg[3][10]_10 ;
  wire \rsMask_reg[3][10]_11 ;
  wire \rsMask_reg[3][10]_12 ;
  wire \rsMask_reg[3][10]_13 ;
  wire \rsMask_reg[3][10]_14 ;
  wire \rsMask_reg[3][10]_2 ;
  wire \rsMask_reg[3][10]_3 ;
  wire \rsMask_reg[3][10]_4 ;
  wire \rsMask_reg[3][10]_5 ;
  wire \rsMask_reg[3][10]_6 ;
  wire \rsMask_reg[3][10]_7 ;
  wire \rsMask_reg[3][10]_8 ;
  wire \rsMask_reg[3][10]_9 ;
  wire [5:0]\rsMask_reg[3][11] ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire [0:0]\rsMask_reg[3][11]_1 ;
  wire [0:0]\rsMask_reg[3][11]_10 ;
  wire [0:0]\rsMask_reg[3][11]_11 ;
  wire [0:0]\rsMask_reg[3][11]_12 ;
  wire [0:0]\rsMask_reg[3][11]_13 ;
  wire [0:0]\rsMask_reg[3][11]_2 ;
  wire [0:0]\rsMask_reg[3][11]_3 ;
  wire [0:0]\rsMask_reg[3][11]_4 ;
  wire [0:0]\rsMask_reg[3][11]_5 ;
  wire [0:0]\rsMask_reg[3][11]_6 ;
  wire [0:0]\rsMask_reg[3][11]_7 ;
  wire [0:0]\rsMask_reg[3][11]_8 ;
  wire [0:0]\rsMask_reg[3][11]_9 ;
  wire \rsMask_reg[3][12] ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][12]_1 ;
  wire \rsMask_reg[3][12]_10 ;
  wire \rsMask_reg[3][12]_11 ;
  wire \rsMask_reg[3][12]_12 ;
  wire \rsMask_reg[3][12]_13 ;
  wire \rsMask_reg[3][12]_14 ;
  wire \rsMask_reg[3][12]_2 ;
  wire \rsMask_reg[3][12]_3 ;
  wire \rsMask_reg[3][12]_4 ;
  wire \rsMask_reg[3][12]_5 ;
  wire \rsMask_reg[3][12]_6 ;
  wire \rsMask_reg[3][12]_7 ;
  wire \rsMask_reg[3][12]_8 ;
  wire \rsMask_reg[3][12]_9 ;
  wire \rsMask_reg[3][15] ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][15]_1 ;
  wire \rsMask_reg[3][15]_10 ;
  wire \rsMask_reg[3][15]_11 ;
  wire \rsMask_reg[3][15]_12 ;
  wire \rsMask_reg[3][15]_13 ;
  wire \rsMask_reg[3][15]_14 ;
  wire \rsMask_reg[3][15]_2 ;
  wire \rsMask_reg[3][15]_3 ;
  wire \rsMask_reg[3][15]_4 ;
  wire \rsMask_reg[3][15]_5 ;
  wire \rsMask_reg[3][15]_6 ;
  wire \rsMask_reg[3][15]_7 ;
  wire \rsMask_reg[3][15]_8 ;
  wire \rsMask_reg[3][15]_9 ;
  wire \rsMask_reg[3][16] ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][16]_1 ;
  wire \rsMask_reg[3][16]_10 ;
  wire \rsMask_reg[3][16]_11 ;
  wire \rsMask_reg[3][16]_12 ;
  wire \rsMask_reg[3][16]_13 ;
  wire \rsMask_reg[3][16]_14 ;
  wire \rsMask_reg[3][16]_2 ;
  wire \rsMask_reg[3][16]_3 ;
  wire \rsMask_reg[3][16]_4 ;
  wire \rsMask_reg[3][16]_5 ;
  wire \rsMask_reg[3][16]_6 ;
  wire \rsMask_reg[3][16]_7 ;
  wire \rsMask_reg[3][16]_8 ;
  wire \rsMask_reg[3][16]_9 ;
  wire \rsMask_reg[3][17] ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][17]_1 ;
  wire \rsMask_reg[3][17]_10 ;
  wire \rsMask_reg[3][17]_11 ;
  wire \rsMask_reg[3][17]_12 ;
  wire \rsMask_reg[3][17]_13 ;
  wire \rsMask_reg[3][17]_14 ;
  wire \rsMask_reg[3][17]_2 ;
  wire \rsMask_reg[3][17]_3 ;
  wire \rsMask_reg[3][17]_4 ;
  wire \rsMask_reg[3][17]_5 ;
  wire \rsMask_reg[3][17]_6 ;
  wire \rsMask_reg[3][17]_7 ;
  wire \rsMask_reg[3][17]_8 ;
  wire \rsMask_reg[3][17]_9 ;
  wire [1:0]\rsMask_reg[3][18] ;
  wire [1:0]\rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][18]_10 ;
  wire \rsMask_reg[3][18]_11 ;
  wire \rsMask_reg[3][18]_12 ;
  wire \rsMask_reg[3][18]_13 ;
  wire \rsMask_reg[3][18]_14 ;
  wire \rsMask_reg[3][18]_15 ;
  wire \rsMask_reg[3][18]_16 ;
  wire \rsMask_reg[3][18]_17 ;
  wire \rsMask_reg[3][18]_18 ;
  wire \rsMask_reg[3][18]_19 ;
  wire \rsMask_reg[3][18]_2 ;
  wire \rsMask_reg[3][18]_20 ;
  wire \rsMask_reg[3][18]_21 ;
  wire \rsMask_reg[3][18]_22 ;
  wire \rsMask_reg[3][18]_23 ;
  wire \rsMask_reg[3][18]_24 ;
  wire \rsMask_reg[3][18]_25 ;
  wire \rsMask_reg[3][18]_26 ;
  wire \rsMask_reg[3][18]_27 ;
  wire \rsMask_reg[3][18]_28 ;
  wire \rsMask_reg[3][18]_29 ;
  wire \rsMask_reg[3][18]_3 ;
  wire \rsMask_reg[3][18]_30 ;
  wire \rsMask_reg[3][18]_31 ;
  wire \rsMask_reg[3][18]_32 ;
  wire \rsMask_reg[3][18]_4 ;
  wire \rsMask_reg[3][18]_5 ;
  wire \rsMask_reg[3][18]_6 ;
  wire \rsMask_reg[3][18]_7 ;
  wire \rsMask_reg[3][18]_8 ;
  wire \rsMask_reg[3][18]_9 ;
  wire \rsMask_reg[3][1] ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][1]_1 ;
  wire \rsMask_reg[3][1]_10 ;
  wire \rsMask_reg[3][1]_11 ;
  wire \rsMask_reg[3][1]_12 ;
  wire \rsMask_reg[3][1]_13 ;
  wire \rsMask_reg[3][1]_14 ;
  wire \rsMask_reg[3][1]_2 ;
  wire \rsMask_reg[3][1]_3 ;
  wire \rsMask_reg[3][1]_4 ;
  wire \rsMask_reg[3][1]_5 ;
  wire \rsMask_reg[3][1]_6 ;
  wire \rsMask_reg[3][1]_7 ;
  wire \rsMask_reg[3][1]_8 ;
  wire \rsMask_reg[3][1]_9 ;
  wire \rsMask_reg[3][2] ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][2]_1 ;
  wire \rsMask_reg[3][2]_10 ;
  wire \rsMask_reg[3][2]_11 ;
  wire \rsMask_reg[3][2]_12 ;
  wire \rsMask_reg[3][2]_13 ;
  wire \rsMask_reg[3][2]_14 ;
  wire \rsMask_reg[3][2]_2 ;
  wire \rsMask_reg[3][2]_3 ;
  wire \rsMask_reg[3][2]_4 ;
  wire \rsMask_reg[3][2]_5 ;
  wire \rsMask_reg[3][2]_6 ;
  wire \rsMask_reg[3][2]_7 ;
  wire \rsMask_reg[3][2]_8 ;
  wire \rsMask_reg[3][2]_9 ;
  wire \rsMask_reg[3][3] ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][3]_1 ;
  wire \rsMask_reg[3][3]_10 ;
  wire \rsMask_reg[3][3]_11 ;
  wire \rsMask_reg[3][3]_12 ;
  wire \rsMask_reg[3][3]_13 ;
  wire \rsMask_reg[3][3]_14 ;
  wire \rsMask_reg[3][3]_2 ;
  wire \rsMask_reg[3][3]_3 ;
  wire \rsMask_reg[3][3]_4 ;
  wire \rsMask_reg[3][3]_5 ;
  wire \rsMask_reg[3][3]_6 ;
  wire \rsMask_reg[3][3]_7 ;
  wire \rsMask_reg[3][3]_8 ;
  wire \rsMask_reg[3][3]_9 ;
  wire \rsMask_reg[3][4] ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][4]_1 ;
  wire \rsMask_reg[3][4]_10 ;
  wire \rsMask_reg[3][4]_11 ;
  wire \rsMask_reg[3][4]_12 ;
  wire \rsMask_reg[3][4]_13 ;
  wire \rsMask_reg[3][4]_14 ;
  wire \rsMask_reg[3][4]_2 ;
  wire \rsMask_reg[3][4]_3 ;
  wire \rsMask_reg[3][4]_4 ;
  wire \rsMask_reg[3][4]_5 ;
  wire \rsMask_reg[3][4]_6 ;
  wire \rsMask_reg[3][4]_7 ;
  wire \rsMask_reg[3][4]_8 ;
  wire \rsMask_reg[3][4]_9 ;
  wire \rsMask_reg[3][5] ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][5]_1 ;
  wire \rsMask_reg[3][5]_10 ;
  wire \rsMask_reg[3][5]_11 ;
  wire \rsMask_reg[3][5]_12 ;
  wire \rsMask_reg[3][5]_13 ;
  wire \rsMask_reg[3][5]_14 ;
  wire \rsMask_reg[3][5]_2 ;
  wire \rsMask_reg[3][5]_3 ;
  wire \rsMask_reg[3][5]_4 ;
  wire \rsMask_reg[3][5]_5 ;
  wire \rsMask_reg[3][5]_6 ;
  wire \rsMask_reg[3][5]_7 ;
  wire \rsMask_reg[3][5]_8 ;
  wire \rsMask_reg[3][5]_9 ;
  wire \rsMask_reg[3][6] ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][6]_1 ;
  wire \rsMask_reg[3][6]_10 ;
  wire \rsMask_reg[3][6]_11 ;
  wire \rsMask_reg[3][6]_12 ;
  wire \rsMask_reg[3][6]_13 ;
  wire \rsMask_reg[3][6]_14 ;
  wire \rsMask_reg[3][6]_2 ;
  wire \rsMask_reg[3][6]_3 ;
  wire \rsMask_reg[3][6]_4 ;
  wire \rsMask_reg[3][6]_5 ;
  wire \rsMask_reg[3][6]_6 ;
  wire \rsMask_reg[3][6]_7 ;
  wire \rsMask_reg[3][6]_8 ;
  wire \rsMask_reg[3][6]_9 ;
  wire \rsMask_reg[3][8] ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][8]_1 ;
  wire \rsMask_reg[3][8]_10 ;
  wire \rsMask_reg[3][8]_11 ;
  wire \rsMask_reg[3][8]_12 ;
  wire \rsMask_reg[3][8]_13 ;
  wire \rsMask_reg[3][8]_14 ;
  wire \rsMask_reg[3][8]_2 ;
  wire \rsMask_reg[3][8]_3 ;
  wire \rsMask_reg[3][8]_4 ;
  wire \rsMask_reg[3][8]_5 ;
  wire \rsMask_reg[3][8]_6 ;
  wire \rsMask_reg[3][8]_7 ;
  wire \rsMask_reg[3][8]_8 ;
  wire \rsMask_reg[3][8]_9 ;
  wire \rsMask_reg[3][9] ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire \rsMask_reg[3][9]_10 ;
  wire \rsMask_reg[3][9]_11 ;
  wire \rsMask_reg[3][9]_12 ;
  wire \rsMask_reg[3][9]_13 ;
  wire \rsMask_reg[3][9]_14 ;
  wire \rsMask_reg[3][9]_15 ;
  wire \rsMask_reg[3][9]_16 ;
  wire \rsMask_reg[3][9]_17 ;
  wire \rsMask_reg[3][9]_18 ;
  wire \rsMask_reg[3][9]_19 ;
  wire \rsMask_reg[3][9]_2 ;
  wire \rsMask_reg[3][9]_20 ;
  wire \rsMask_reg[3][9]_21 ;
  wire \rsMask_reg[3][9]_22 ;
  wire \rsMask_reg[3][9]_23 ;
  wire \rsMask_reg[3][9]_24 ;
  wire \rsMask_reg[3][9]_25 ;
  wire \rsMask_reg[3][9]_26 ;
  wire \rsMask_reg[3][9]_27 ;
  wire \rsMask_reg[3][9]_28 ;
  wire \rsMask_reg[3][9]_29 ;
  wire \rsMask_reg[3][9]_3 ;
  wire \rsMask_reg[3][9]_30 ;
  wire \rsMask_reg[3][9]_4 ;
  wire \rsMask_reg[3][9]_5 ;
  wire \rsMask_reg[3][9]_6 ;
  wire \rsMask_reg[3][9]_7 ;
  wire \rsMask_reg[3][9]_8 ;
  wire \rsMask_reg[3][9]_9 ;
  wire \rsMask_reg[4][11] ;
  wire \rsMask_reg[4][11]_0 ;
  wire \rsMask_reg[4][11]_1 ;
  wire \rsMask_reg[4][11]_10 ;
  wire \rsMask_reg[4][11]_11 ;
  wire \rsMask_reg[4][11]_12 ;
  wire \rsMask_reg[4][11]_13 ;
  wire \rsMask_reg[4][11]_14 ;
  wire \rsMask_reg[4][11]_2 ;
  wire \rsMask_reg[4][11]_3 ;
  wire \rsMask_reg[4][11]_4 ;
  wire \rsMask_reg[4][11]_5 ;
  wire \rsMask_reg[4][11]_6 ;
  wire \rsMask_reg[4][11]_7 ;
  wire \rsMask_reg[4][11]_8 ;
  wire \rsMask_reg[4][11]_9 ;
  wire [2:0]\rsMask_reg[4][9] ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [2:0]\rsMask_reg[4][9]_1 ;
  wire [2:0]\rsMask_reg[4][9]_10 ;
  wire [2:0]\rsMask_reg[4][9]_11 ;
  wire [2:0]\rsMask_reg[4][9]_12 ;
  wire [2:0]\rsMask_reg[4][9]_13 ;
  wire [2:0]\rsMask_reg[4][9]_14 ;
  wire [2:0]\rsMask_reg[4][9]_2 ;
  wire [2:0]\rsMask_reg[4][9]_3 ;
  wire [2:0]\rsMask_reg[4][9]_4 ;
  wire [2:0]\rsMask_reg[4][9]_5 ;
  wire [2:0]\rsMask_reg[4][9]_6 ;
  wire [2:0]\rsMask_reg[4][9]_7 ;
  wire [2:0]\rsMask_reg[4][9]_8 ;
  wire [2:0]\rsMask_reg[4][9]_9 ;
  wire \rsMask_reg[5][10] ;
  wire \rsMask_reg[5][10]_0 ;
  wire \rsMask_reg[5][10]_1 ;
  wire \rsMask_reg[5][10]_10 ;
  wire \rsMask_reg[5][10]_11 ;
  wire \rsMask_reg[5][10]_12 ;
  wire \rsMask_reg[5][10]_13 ;
  wire \rsMask_reg[5][10]_14 ;
  wire \rsMask_reg[5][10]_2 ;
  wire \rsMask_reg[5][10]_3 ;
  wire \rsMask_reg[5][10]_4 ;
  wire \rsMask_reg[5][10]_5 ;
  wire \rsMask_reg[5][10]_6 ;
  wire \rsMask_reg[5][10]_7 ;
  wire \rsMask_reg[5][10]_8 ;
  wire \rsMask_reg[5][10]_9 ;
  wire [5:0]\rsMask_reg[5][11] ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire [0:0]\rsMask_reg[5][11]_1 ;
  wire [0:0]\rsMask_reg[5][11]_10 ;
  wire [0:0]\rsMask_reg[5][11]_11 ;
  wire [0:0]\rsMask_reg[5][11]_12 ;
  wire [0:0]\rsMask_reg[5][11]_13 ;
  wire [0:0]\rsMask_reg[5][11]_2 ;
  wire [0:0]\rsMask_reg[5][11]_3 ;
  wire [0:0]\rsMask_reg[5][11]_4 ;
  wire [0:0]\rsMask_reg[5][11]_5 ;
  wire [0:0]\rsMask_reg[5][11]_6 ;
  wire [0:0]\rsMask_reg[5][11]_7 ;
  wire [0:0]\rsMask_reg[5][11]_8 ;
  wire [0:0]\rsMask_reg[5][11]_9 ;
  wire \rsMask_reg[5][12] ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][12]_1 ;
  wire \rsMask_reg[5][12]_10 ;
  wire \rsMask_reg[5][12]_11 ;
  wire \rsMask_reg[5][12]_12 ;
  wire \rsMask_reg[5][12]_13 ;
  wire \rsMask_reg[5][12]_14 ;
  wire \rsMask_reg[5][12]_2 ;
  wire \rsMask_reg[5][12]_3 ;
  wire \rsMask_reg[5][12]_4 ;
  wire \rsMask_reg[5][12]_5 ;
  wire \rsMask_reg[5][12]_6 ;
  wire \rsMask_reg[5][12]_7 ;
  wire \rsMask_reg[5][12]_8 ;
  wire \rsMask_reg[5][12]_9 ;
  wire \rsMask_reg[5][15] ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][15]_1 ;
  wire \rsMask_reg[5][15]_10 ;
  wire \rsMask_reg[5][15]_11 ;
  wire \rsMask_reg[5][15]_12 ;
  wire \rsMask_reg[5][15]_13 ;
  wire \rsMask_reg[5][15]_14 ;
  wire \rsMask_reg[5][15]_2 ;
  wire \rsMask_reg[5][15]_3 ;
  wire \rsMask_reg[5][15]_4 ;
  wire \rsMask_reg[5][15]_5 ;
  wire \rsMask_reg[5][15]_6 ;
  wire \rsMask_reg[5][15]_7 ;
  wire \rsMask_reg[5][15]_8 ;
  wire \rsMask_reg[5][15]_9 ;
  wire \rsMask_reg[5][16] ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][16]_1 ;
  wire \rsMask_reg[5][16]_10 ;
  wire \rsMask_reg[5][16]_11 ;
  wire \rsMask_reg[5][16]_12 ;
  wire \rsMask_reg[5][16]_13 ;
  wire \rsMask_reg[5][16]_14 ;
  wire \rsMask_reg[5][16]_2 ;
  wire \rsMask_reg[5][16]_3 ;
  wire \rsMask_reg[5][16]_4 ;
  wire \rsMask_reg[5][16]_5 ;
  wire \rsMask_reg[5][16]_6 ;
  wire \rsMask_reg[5][16]_7 ;
  wire \rsMask_reg[5][16]_8 ;
  wire \rsMask_reg[5][16]_9 ;
  wire \rsMask_reg[5][17] ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][17]_1 ;
  wire \rsMask_reg[5][17]_10 ;
  wire \rsMask_reg[5][17]_11 ;
  wire \rsMask_reg[5][17]_12 ;
  wire \rsMask_reg[5][17]_13 ;
  wire \rsMask_reg[5][17]_14 ;
  wire \rsMask_reg[5][17]_2 ;
  wire \rsMask_reg[5][17]_3 ;
  wire \rsMask_reg[5][17]_4 ;
  wire \rsMask_reg[5][17]_5 ;
  wire \rsMask_reg[5][17]_6 ;
  wire \rsMask_reg[5][17]_7 ;
  wire \rsMask_reg[5][17]_8 ;
  wire \rsMask_reg[5][17]_9 ;
  wire [1:0]\rsMask_reg[5][18] ;
  wire [1:0]\rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][18]_10 ;
  wire \rsMask_reg[5][18]_11 ;
  wire \rsMask_reg[5][18]_12 ;
  wire \rsMask_reg[5][18]_13 ;
  wire \rsMask_reg[5][18]_14 ;
  wire \rsMask_reg[5][18]_15 ;
  wire \rsMask_reg[5][18]_16 ;
  wire \rsMask_reg[5][18]_17 ;
  wire \rsMask_reg[5][18]_18 ;
  wire \rsMask_reg[5][18]_19 ;
  wire \rsMask_reg[5][18]_2 ;
  wire \rsMask_reg[5][18]_20 ;
  wire \rsMask_reg[5][18]_21 ;
  wire \rsMask_reg[5][18]_22 ;
  wire \rsMask_reg[5][18]_23 ;
  wire \rsMask_reg[5][18]_24 ;
  wire \rsMask_reg[5][18]_25 ;
  wire \rsMask_reg[5][18]_26 ;
  wire \rsMask_reg[5][18]_27 ;
  wire \rsMask_reg[5][18]_28 ;
  wire \rsMask_reg[5][18]_29 ;
  wire \rsMask_reg[5][18]_3 ;
  wire \rsMask_reg[5][18]_30 ;
  wire \rsMask_reg[5][18]_31 ;
  wire \rsMask_reg[5][18]_32 ;
  wire \rsMask_reg[5][18]_4 ;
  wire \rsMask_reg[5][18]_5 ;
  wire \rsMask_reg[5][18]_6 ;
  wire \rsMask_reg[5][18]_7 ;
  wire \rsMask_reg[5][18]_8 ;
  wire \rsMask_reg[5][18]_9 ;
  wire \rsMask_reg[5][1] ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][1]_1 ;
  wire \rsMask_reg[5][1]_10 ;
  wire \rsMask_reg[5][1]_11 ;
  wire \rsMask_reg[5][1]_12 ;
  wire \rsMask_reg[5][1]_13 ;
  wire \rsMask_reg[5][1]_14 ;
  wire \rsMask_reg[5][1]_2 ;
  wire \rsMask_reg[5][1]_3 ;
  wire \rsMask_reg[5][1]_4 ;
  wire \rsMask_reg[5][1]_5 ;
  wire \rsMask_reg[5][1]_6 ;
  wire \rsMask_reg[5][1]_7 ;
  wire \rsMask_reg[5][1]_8 ;
  wire \rsMask_reg[5][1]_9 ;
  wire \rsMask_reg[5][2] ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][2]_1 ;
  wire \rsMask_reg[5][2]_10 ;
  wire \rsMask_reg[5][2]_11 ;
  wire \rsMask_reg[5][2]_12 ;
  wire \rsMask_reg[5][2]_13 ;
  wire \rsMask_reg[5][2]_14 ;
  wire \rsMask_reg[5][2]_2 ;
  wire \rsMask_reg[5][2]_3 ;
  wire \rsMask_reg[5][2]_4 ;
  wire \rsMask_reg[5][2]_5 ;
  wire \rsMask_reg[5][2]_6 ;
  wire \rsMask_reg[5][2]_7 ;
  wire \rsMask_reg[5][2]_8 ;
  wire \rsMask_reg[5][2]_9 ;
  wire \rsMask_reg[5][3] ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][3]_1 ;
  wire \rsMask_reg[5][3]_10 ;
  wire \rsMask_reg[5][3]_11 ;
  wire \rsMask_reg[5][3]_12 ;
  wire \rsMask_reg[5][3]_13 ;
  wire \rsMask_reg[5][3]_14 ;
  wire \rsMask_reg[5][3]_2 ;
  wire \rsMask_reg[5][3]_3 ;
  wire \rsMask_reg[5][3]_4 ;
  wire \rsMask_reg[5][3]_5 ;
  wire \rsMask_reg[5][3]_6 ;
  wire \rsMask_reg[5][3]_7 ;
  wire \rsMask_reg[5][3]_8 ;
  wire \rsMask_reg[5][3]_9 ;
  wire \rsMask_reg[5][4] ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][4]_1 ;
  wire \rsMask_reg[5][4]_10 ;
  wire \rsMask_reg[5][4]_11 ;
  wire \rsMask_reg[5][4]_12 ;
  wire \rsMask_reg[5][4]_13 ;
  wire \rsMask_reg[5][4]_14 ;
  wire \rsMask_reg[5][4]_2 ;
  wire \rsMask_reg[5][4]_3 ;
  wire \rsMask_reg[5][4]_4 ;
  wire \rsMask_reg[5][4]_5 ;
  wire \rsMask_reg[5][4]_6 ;
  wire \rsMask_reg[5][4]_7 ;
  wire \rsMask_reg[5][4]_8 ;
  wire \rsMask_reg[5][4]_9 ;
  wire \rsMask_reg[5][5] ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][5]_1 ;
  wire \rsMask_reg[5][5]_10 ;
  wire \rsMask_reg[5][5]_11 ;
  wire \rsMask_reg[5][5]_12 ;
  wire \rsMask_reg[5][5]_13 ;
  wire \rsMask_reg[5][5]_14 ;
  wire \rsMask_reg[5][5]_2 ;
  wire \rsMask_reg[5][5]_3 ;
  wire \rsMask_reg[5][5]_4 ;
  wire \rsMask_reg[5][5]_5 ;
  wire \rsMask_reg[5][5]_6 ;
  wire \rsMask_reg[5][5]_7 ;
  wire \rsMask_reg[5][5]_8 ;
  wire \rsMask_reg[5][5]_9 ;
  wire \rsMask_reg[5][6] ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][6]_1 ;
  wire \rsMask_reg[5][6]_10 ;
  wire \rsMask_reg[5][6]_11 ;
  wire \rsMask_reg[5][6]_12 ;
  wire \rsMask_reg[5][6]_13 ;
  wire \rsMask_reg[5][6]_14 ;
  wire \rsMask_reg[5][6]_2 ;
  wire \rsMask_reg[5][6]_3 ;
  wire \rsMask_reg[5][6]_4 ;
  wire \rsMask_reg[5][6]_5 ;
  wire \rsMask_reg[5][6]_6 ;
  wire \rsMask_reg[5][6]_7 ;
  wire \rsMask_reg[5][6]_8 ;
  wire \rsMask_reg[5][6]_9 ;
  wire \rsMask_reg[5][8] ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][8]_1 ;
  wire \rsMask_reg[5][8]_10 ;
  wire \rsMask_reg[5][8]_11 ;
  wire \rsMask_reg[5][8]_12 ;
  wire \rsMask_reg[5][8]_13 ;
  wire \rsMask_reg[5][8]_14 ;
  wire \rsMask_reg[5][8]_2 ;
  wire \rsMask_reg[5][8]_3 ;
  wire \rsMask_reg[5][8]_4 ;
  wire \rsMask_reg[5][8]_5 ;
  wire \rsMask_reg[5][8]_6 ;
  wire \rsMask_reg[5][8]_7 ;
  wire \rsMask_reg[5][8]_8 ;
  wire \rsMask_reg[5][8]_9 ;
  wire \rsMask_reg[5][9] ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire \rsMask_reg[5][9]_10 ;
  wire \rsMask_reg[5][9]_11 ;
  wire \rsMask_reg[5][9]_12 ;
  wire \rsMask_reg[5][9]_13 ;
  wire \rsMask_reg[5][9]_14 ;
  wire \rsMask_reg[5][9]_15 ;
  wire \rsMask_reg[5][9]_16 ;
  wire \rsMask_reg[5][9]_17 ;
  wire \rsMask_reg[5][9]_18 ;
  wire \rsMask_reg[5][9]_19 ;
  wire \rsMask_reg[5][9]_2 ;
  wire \rsMask_reg[5][9]_20 ;
  wire \rsMask_reg[5][9]_21 ;
  wire \rsMask_reg[5][9]_22 ;
  wire \rsMask_reg[5][9]_23 ;
  wire \rsMask_reg[5][9]_24 ;
  wire \rsMask_reg[5][9]_25 ;
  wire \rsMask_reg[5][9]_26 ;
  wire \rsMask_reg[5][9]_27 ;
  wire \rsMask_reg[5][9]_28 ;
  wire \rsMask_reg[5][9]_29 ;
  wire \rsMask_reg[5][9]_3 ;
  wire \rsMask_reg[5][9]_30 ;
  wire \rsMask_reg[5][9]_4 ;
  wire \rsMask_reg[5][9]_5 ;
  wire \rsMask_reg[5][9]_6 ;
  wire \rsMask_reg[5][9]_7 ;
  wire \rsMask_reg[5][9]_8 ;
  wire \rsMask_reg[5][9]_9 ;
  wire \rsMask_reg[6][11] ;
  wire \rsMask_reg[6][11]_0 ;
  wire \rsMask_reg[6][11]_1 ;
  wire \rsMask_reg[6][11]_10 ;
  wire \rsMask_reg[6][11]_11 ;
  wire \rsMask_reg[6][11]_12 ;
  wire \rsMask_reg[6][11]_13 ;
  wire \rsMask_reg[6][11]_14 ;
  wire \rsMask_reg[6][11]_2 ;
  wire \rsMask_reg[6][11]_3 ;
  wire \rsMask_reg[6][11]_4 ;
  wire \rsMask_reg[6][11]_5 ;
  wire \rsMask_reg[6][11]_6 ;
  wire \rsMask_reg[6][11]_7 ;
  wire \rsMask_reg[6][11]_8 ;
  wire \rsMask_reg[6][11]_9 ;
  wire [2:0]\rsMask_reg[6][9] ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [2:0]\rsMask_reg[6][9]_1 ;
  wire [2:0]\rsMask_reg[6][9]_10 ;
  wire [2:0]\rsMask_reg[6][9]_11 ;
  wire [2:0]\rsMask_reg[6][9]_12 ;
  wire [2:0]\rsMask_reg[6][9]_13 ;
  wire [2:0]\rsMask_reg[6][9]_14 ;
  wire [2:0]\rsMask_reg[6][9]_2 ;
  wire [2:0]\rsMask_reg[6][9]_3 ;
  wire [2:0]\rsMask_reg[6][9]_4 ;
  wire [2:0]\rsMask_reg[6][9]_5 ;
  wire [2:0]\rsMask_reg[6][9]_6 ;
  wire [2:0]\rsMask_reg[6][9]_7 ;
  wire [2:0]\rsMask_reg[6][9]_8 ;
  wire [2:0]\rsMask_reg[6][9]_9 ;
  wire \rsMask_reg[7][10] ;
  wire \rsMask_reg[7][10]_0 ;
  wire \rsMask_reg[7][10]_1 ;
  wire \rsMask_reg[7][10]_10 ;
  wire \rsMask_reg[7][10]_11 ;
  wire \rsMask_reg[7][10]_12 ;
  wire \rsMask_reg[7][10]_13 ;
  wire \rsMask_reg[7][10]_14 ;
  wire \rsMask_reg[7][10]_2 ;
  wire \rsMask_reg[7][10]_3 ;
  wire \rsMask_reg[7][10]_4 ;
  wire \rsMask_reg[7][10]_5 ;
  wire \rsMask_reg[7][10]_6 ;
  wire \rsMask_reg[7][10]_7 ;
  wire \rsMask_reg[7][10]_8 ;
  wire \rsMask_reg[7][10]_9 ;
  wire [5:0]\rsMask_reg[7][11] ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire [0:0]\rsMask_reg[7][11]_1 ;
  wire [0:0]\rsMask_reg[7][11]_10 ;
  wire [0:0]\rsMask_reg[7][11]_11 ;
  wire [0:0]\rsMask_reg[7][11]_12 ;
  wire [0:0]\rsMask_reg[7][11]_13 ;
  wire [0:0]\rsMask_reg[7][11]_2 ;
  wire [0:0]\rsMask_reg[7][11]_3 ;
  wire [0:0]\rsMask_reg[7][11]_4 ;
  wire [0:0]\rsMask_reg[7][11]_5 ;
  wire [0:0]\rsMask_reg[7][11]_6 ;
  wire [0:0]\rsMask_reg[7][11]_7 ;
  wire [0:0]\rsMask_reg[7][11]_8 ;
  wire [0:0]\rsMask_reg[7][11]_9 ;
  wire \rsMask_reg[7][12] ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][12]_1 ;
  wire \rsMask_reg[7][12]_10 ;
  wire \rsMask_reg[7][12]_11 ;
  wire \rsMask_reg[7][12]_12 ;
  wire \rsMask_reg[7][12]_13 ;
  wire \rsMask_reg[7][12]_14 ;
  wire \rsMask_reg[7][12]_2 ;
  wire \rsMask_reg[7][12]_3 ;
  wire \rsMask_reg[7][12]_4 ;
  wire \rsMask_reg[7][12]_5 ;
  wire \rsMask_reg[7][12]_6 ;
  wire \rsMask_reg[7][12]_7 ;
  wire \rsMask_reg[7][12]_8 ;
  wire \rsMask_reg[7][12]_9 ;
  wire \rsMask_reg[7][15] ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][15]_1 ;
  wire \rsMask_reg[7][15]_10 ;
  wire \rsMask_reg[7][15]_11 ;
  wire \rsMask_reg[7][15]_12 ;
  wire \rsMask_reg[7][15]_13 ;
  wire \rsMask_reg[7][15]_14 ;
  wire \rsMask_reg[7][15]_2 ;
  wire \rsMask_reg[7][15]_3 ;
  wire \rsMask_reg[7][15]_4 ;
  wire \rsMask_reg[7][15]_5 ;
  wire \rsMask_reg[7][15]_6 ;
  wire \rsMask_reg[7][15]_7 ;
  wire \rsMask_reg[7][15]_8 ;
  wire \rsMask_reg[7][15]_9 ;
  wire \rsMask_reg[7][16] ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][16]_1 ;
  wire \rsMask_reg[7][16]_10 ;
  wire \rsMask_reg[7][16]_11 ;
  wire \rsMask_reg[7][16]_12 ;
  wire \rsMask_reg[7][16]_13 ;
  wire \rsMask_reg[7][16]_14 ;
  wire \rsMask_reg[7][16]_2 ;
  wire \rsMask_reg[7][16]_3 ;
  wire \rsMask_reg[7][16]_4 ;
  wire \rsMask_reg[7][16]_5 ;
  wire \rsMask_reg[7][16]_6 ;
  wire \rsMask_reg[7][16]_7 ;
  wire \rsMask_reg[7][16]_8 ;
  wire \rsMask_reg[7][16]_9 ;
  wire \rsMask_reg[7][17] ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][17]_10 ;
  wire \rsMask_reg[7][17]_11 ;
  wire \rsMask_reg[7][17]_12 ;
  wire \rsMask_reg[7][17]_13 ;
  wire \rsMask_reg[7][17]_14 ;
  wire \rsMask_reg[7][17]_15 ;
  wire \rsMask_reg[7][17]_16 ;
  wire \rsMask_reg[7][17]_17 ;
  wire \rsMask_reg[7][17]_18 ;
  wire \rsMask_reg[7][17]_19 ;
  wire \rsMask_reg[7][17]_2 ;
  wire \rsMask_reg[7][17]_20 ;
  wire \rsMask_reg[7][17]_21 ;
  wire \rsMask_reg[7][17]_22 ;
  wire \rsMask_reg[7][17]_23 ;
  wire \rsMask_reg[7][17]_24 ;
  wire \rsMask_reg[7][17]_25 ;
  wire \rsMask_reg[7][17]_26 ;
  wire \rsMask_reg[7][17]_27 ;
  wire \rsMask_reg[7][17]_28 ;
  wire \rsMask_reg[7][17]_3 ;
  wire \rsMask_reg[7][17]_4 ;
  wire \rsMask_reg[7][17]_5 ;
  wire \rsMask_reg[7][17]_6 ;
  wire \rsMask_reg[7][17]_7 ;
  wire \rsMask_reg[7][17]_8 ;
  wire \rsMask_reg[7][17]_9 ;
  wire [1:0]\rsMask_reg[7][18] ;
  wire [1:0]\rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_10 ;
  wire \rsMask_reg[7][18]_11 ;
  wire \rsMask_reg[7][18]_12 ;
  wire \rsMask_reg[7][18]_13 ;
  wire \rsMask_reg[7][18]_14 ;
  wire \rsMask_reg[7][18]_15 ;
  wire \rsMask_reg[7][18]_16 ;
  wire \rsMask_reg[7][18]_17 ;
  wire \rsMask_reg[7][18]_18 ;
  wire \rsMask_reg[7][18]_19 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][18]_20 ;
  wire \rsMask_reg[7][18]_21 ;
  wire \rsMask_reg[7][18]_22 ;
  wire \rsMask_reg[7][18]_23 ;
  wire \rsMask_reg[7][18]_24 ;
  wire \rsMask_reg[7][18]_25 ;
  wire \rsMask_reg[7][18]_26 ;
  wire \rsMask_reg[7][18]_27 ;
  wire \rsMask_reg[7][18]_28 ;
  wire \rsMask_reg[7][18]_29 ;
  wire \rsMask_reg[7][18]_3 ;
  wire \rsMask_reg[7][18]_30 ;
  wire \rsMask_reg[7][18]_31 ;
  wire \rsMask_reg[7][18]_32 ;
  wire \rsMask_reg[7][18]_33 ;
  wire \rsMask_reg[7][18]_34 ;
  wire \rsMask_reg[7][18]_35 ;
  wire \rsMask_reg[7][18]_36 ;
  wire \rsMask_reg[7][18]_37 ;
  wire \rsMask_reg[7][18]_38 ;
  wire \rsMask_reg[7][18]_39 ;
  wire \rsMask_reg[7][18]_4 ;
  wire \rsMask_reg[7][18]_40 ;
  wire \rsMask_reg[7][18]_41 ;
  wire \rsMask_reg[7][18]_42 ;
  wire \rsMask_reg[7][18]_43 ;
  wire \rsMask_reg[7][18]_44 ;
  wire \rsMask_reg[7][18]_45 ;
  wire \rsMask_reg[7][18]_46 ;
  wire \rsMask_reg[7][18]_5 ;
  wire \rsMask_reg[7][18]_6 ;
  wire \rsMask_reg[7][18]_7 ;
  wire \rsMask_reg[7][18]_8 ;
  wire \rsMask_reg[7][18]_9 ;
  wire \rsMask_reg[7][1] ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][1]_1 ;
  wire \rsMask_reg[7][1]_10 ;
  wire \rsMask_reg[7][1]_11 ;
  wire \rsMask_reg[7][1]_12 ;
  wire \rsMask_reg[7][1]_13 ;
  wire \rsMask_reg[7][1]_14 ;
  wire \rsMask_reg[7][1]_2 ;
  wire \rsMask_reg[7][1]_3 ;
  wire \rsMask_reg[7][1]_4 ;
  wire \rsMask_reg[7][1]_5 ;
  wire \rsMask_reg[7][1]_6 ;
  wire \rsMask_reg[7][1]_7 ;
  wire \rsMask_reg[7][1]_8 ;
  wire \rsMask_reg[7][1]_9 ;
  wire \rsMask_reg[7][2] ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][2]_1 ;
  wire \rsMask_reg[7][2]_10 ;
  wire \rsMask_reg[7][2]_11 ;
  wire \rsMask_reg[7][2]_12 ;
  wire \rsMask_reg[7][2]_13 ;
  wire \rsMask_reg[7][2]_14 ;
  wire \rsMask_reg[7][2]_2 ;
  wire \rsMask_reg[7][2]_3 ;
  wire \rsMask_reg[7][2]_4 ;
  wire \rsMask_reg[7][2]_5 ;
  wire \rsMask_reg[7][2]_6 ;
  wire \rsMask_reg[7][2]_7 ;
  wire \rsMask_reg[7][2]_8 ;
  wire \rsMask_reg[7][2]_9 ;
  wire \rsMask_reg[7][3] ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][3]_1 ;
  wire \rsMask_reg[7][3]_10 ;
  wire \rsMask_reg[7][3]_11 ;
  wire \rsMask_reg[7][3]_12 ;
  wire \rsMask_reg[7][3]_13 ;
  wire \rsMask_reg[7][3]_14 ;
  wire \rsMask_reg[7][3]_2 ;
  wire \rsMask_reg[7][3]_3 ;
  wire \rsMask_reg[7][3]_4 ;
  wire \rsMask_reg[7][3]_5 ;
  wire \rsMask_reg[7][3]_6 ;
  wire \rsMask_reg[7][3]_7 ;
  wire \rsMask_reg[7][3]_8 ;
  wire \rsMask_reg[7][3]_9 ;
  wire \rsMask_reg[7][4] ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][4]_1 ;
  wire \rsMask_reg[7][4]_10 ;
  wire \rsMask_reg[7][4]_11 ;
  wire \rsMask_reg[7][4]_12 ;
  wire \rsMask_reg[7][4]_13 ;
  wire \rsMask_reg[7][4]_14 ;
  wire \rsMask_reg[7][4]_2 ;
  wire \rsMask_reg[7][4]_3 ;
  wire \rsMask_reg[7][4]_4 ;
  wire \rsMask_reg[7][4]_5 ;
  wire \rsMask_reg[7][4]_6 ;
  wire \rsMask_reg[7][4]_7 ;
  wire \rsMask_reg[7][4]_8 ;
  wire \rsMask_reg[7][4]_9 ;
  wire \rsMask_reg[7][5] ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][5]_1 ;
  wire \rsMask_reg[7][5]_10 ;
  wire \rsMask_reg[7][5]_11 ;
  wire \rsMask_reg[7][5]_12 ;
  wire \rsMask_reg[7][5]_13 ;
  wire \rsMask_reg[7][5]_14 ;
  wire \rsMask_reg[7][5]_2 ;
  wire \rsMask_reg[7][5]_3 ;
  wire \rsMask_reg[7][5]_4 ;
  wire \rsMask_reg[7][5]_5 ;
  wire \rsMask_reg[7][5]_6 ;
  wire \rsMask_reg[7][5]_7 ;
  wire \rsMask_reg[7][5]_8 ;
  wire \rsMask_reg[7][5]_9 ;
  wire \rsMask_reg[7][6] ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][6]_1 ;
  wire \rsMask_reg[7][6]_10 ;
  wire \rsMask_reg[7][6]_11 ;
  wire \rsMask_reg[7][6]_12 ;
  wire \rsMask_reg[7][6]_13 ;
  wire \rsMask_reg[7][6]_14 ;
  wire \rsMask_reg[7][6]_2 ;
  wire \rsMask_reg[7][6]_3 ;
  wire \rsMask_reg[7][6]_4 ;
  wire \rsMask_reg[7][6]_5 ;
  wire \rsMask_reg[7][6]_6 ;
  wire \rsMask_reg[7][6]_7 ;
  wire \rsMask_reg[7][6]_8 ;
  wire \rsMask_reg[7][6]_9 ;
  wire \rsMask_reg[7][8] ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][8]_1 ;
  wire \rsMask_reg[7][8]_10 ;
  wire \rsMask_reg[7][8]_11 ;
  wire \rsMask_reg[7][8]_12 ;
  wire \rsMask_reg[7][8]_13 ;
  wire \rsMask_reg[7][8]_14 ;
  wire \rsMask_reg[7][8]_2 ;
  wire \rsMask_reg[7][8]_3 ;
  wire \rsMask_reg[7][8]_4 ;
  wire \rsMask_reg[7][8]_5 ;
  wire \rsMask_reg[7][8]_6 ;
  wire \rsMask_reg[7][8]_7 ;
  wire \rsMask_reg[7][8]_8 ;
  wire \rsMask_reg[7][8]_9 ;
  wire \rsMask_reg[7][9] ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire \rsMask_reg[7][9]_10 ;
  wire \rsMask_reg[7][9]_11 ;
  wire \rsMask_reg[7][9]_12 ;
  wire \rsMask_reg[7][9]_13 ;
  wire \rsMask_reg[7][9]_14 ;
  wire \rsMask_reg[7][9]_15 ;
  wire \rsMask_reg[7][9]_16 ;
  wire \rsMask_reg[7][9]_17 ;
  wire \rsMask_reg[7][9]_18 ;
  wire \rsMask_reg[7][9]_19 ;
  wire \rsMask_reg[7][9]_2 ;
  wire \rsMask_reg[7][9]_20 ;
  wire \rsMask_reg[7][9]_21 ;
  wire \rsMask_reg[7][9]_22 ;
  wire \rsMask_reg[7][9]_23 ;
  wire \rsMask_reg[7][9]_24 ;
  wire \rsMask_reg[7][9]_25 ;
  wire \rsMask_reg[7][9]_26 ;
  wire \rsMask_reg[7][9]_27 ;
  wire \rsMask_reg[7][9]_28 ;
  wire \rsMask_reg[7][9]_29 ;
  wire \rsMask_reg[7][9]_3 ;
  wire \rsMask_reg[7][9]_30 ;
  wire \rsMask_reg[7][9]_4 ;
  wire \rsMask_reg[7][9]_5 ;
  wire \rsMask_reg[7][9]_6 ;
  wire \rsMask_reg[7][9]_7 ;
  wire \rsMask_reg[7][9]_8 ;
  wire \rsMask_reg[7][9]_9 ;
  (* RTL_KEEP = "true" *) wire rst_r1;
  wire underfill_done_nxt;
  wire [2:1]wosp;
  wire \wosp_reg[2]_rep ;
  wire \wosp_reg[2]_rep__0 ;
  wire \wosp_reg[2]_rep__1 ;
  wire \wosp_reg[2]_rep__2 ;
  wire \wosp_reg[2]_rep__3 ;
  wire \wosp_reg[2]_rep__4 ;
  wire \wosp_reg[2]_rep__5 ;
  wire \wosp_reg[2]_rep__6 ;
  wire \wosp_reg[2]_rep__7 ;
  wire wrDataEn_pi;
  wire wrDataVal;
  wire [0:0]\wrQ_nxt[1]_13 ;
  wire [0:0]\wrQ_reg[0][0] ;
  wire \wrQ_reg[0][0]_rep ;
  wire \wrQ_reg[0][2] ;
  wire \wrQ_reg[0][5]_rep ;
  wire \wrQ_reg[0][5]_rep__0 ;
  wire \wrQ_reg[0][5]_rep__1 ;
  wire \wrQ_reg[0][6]_rep ;
  wire \wrQ_reg[0][6]_rep__0 ;
  wire \wrQ_reg[0][6]_rep__1 ;
  wire \wrQ_reg[0][7]_rep ;
  wire \wrQ_reg[0][7]_rep__0 ;
  wire \wrQ_reg[0][7]_rep__1 ;
  wire [3:0]\wrQ_reg[0][8] ;
  wire \wrQ_reg[0][8]_rep ;
  wire [3:0]\wrQ_reg[0][8]_rep__0 ;
  wire \wrQ_reg[0][8]_rep__0_0 ;
  wire [3:0]\wrQ_reg[0][8]_rep__1 ;
  wire \wrQ_reg[0][8]_rep__1_0 ;
  wire [3:0]\wrQ_reg[1][8] ;
  wire [4:0]\wrQ_reg[1][8]_0 ;

  assign out = rst_r1;
  ddr4_0_ddr4_v2_2_17_cal_rd_en \rdEn[0].u_ddr_mc_rd_en_low 
       (.\blk1.(null)[0].diff_27 (\blk1.(null)[0].diff_27 ),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[3:0]),
        .mcalCasSlot(mcalCasSlot),
        .mcalRank(mcalRank),
        .mcalRdCAS(mcalRdCAS),
        .out(rst_r1),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_13 ),
        .rs2mask0_26(rs2mask0_26),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_14 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_14 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_14 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_14 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_14 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_31 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_32 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_14 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_14 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_14 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_14 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_14 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_14 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_14 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_14 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_13 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_14 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_14 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_14 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_14 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_31 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_32 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_14 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_14 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_14 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_14 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_14 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_14 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_14 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_29 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_30 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_14 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_14 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_14 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_13 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_14 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_14 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_14 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_14 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_31 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_32 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_14 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_14 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_14 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_14 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_14 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_14 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_14 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_29 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_30 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_14 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_14 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_14 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_13 ),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12]_14 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_14 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_14 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_12 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_28 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_14 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_45 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_46 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_14 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_14 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_14 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_14 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_14 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_14 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_14 ),
        .\rsMask_reg[7][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_29 ),
        .\rsMask_reg[7][9]_2 (\rsMask_reg[7][9]_30 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_12 \rdEn[0].u_ddr_mc_rd_en_upp 
       (.\blk1.(null)[0].diff_11 (\blk1.(null)[0].diff_11 ),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[3:0]),
        .out(rst_r1),
        .phy_rden_and(phy_rden_and),
        .phy_rden_or(phy_rden_or),
        .\rdEn_reg[12]_0 (\rdEn_reg[12] ),
        .\rdEn_reg[12]_1 (\rdEn_reg[12]_1 ),
        .\rdEn_reg[14]_0 (\rdEn_reg[12]_0 ),
        .\rdEn_reg[14]_1 (\rdEn_reg[13] ),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_5 ),
        .rs2mask0_10(rs2mask0_10),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_6 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_6 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_6 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_6 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_6 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_15 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_16 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_6 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_6 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_6 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_6 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_6 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_6 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_6 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_6 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_5 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_6 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_6 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_6 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_6 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_15 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_16 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_6 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_6 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_6 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_6 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_6 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_6 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_6 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_13 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_14 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_6 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_6 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_6 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_5 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_6 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_6 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_6 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_6 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_15 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_16 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_6 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_6 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_6 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_6 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_6 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_6 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_6 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_13 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_14 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_6 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_6 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_6 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_5 ),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12]_6 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_6 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_6 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_4 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_20 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_6 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_29 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_30 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_6 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_6 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_6 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_6 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_6 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_6 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_6 ),
        .\rsMask_reg[7][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_13 ),
        .\rsMask_reg[7][9]_2 (\rsMask_reg[7][9]_14 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_13 \rdEn[1].u_ddr_mc_rd_en_low 
       (.\blk1.(null)[0].diff_25 (\blk1.(null)[0].diff_25 ),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[7:4]),
        .mcalCasSlot(mcalCasSlot),
        .mcalRank(mcalRank),
        .mcalRdCAS(mcalRdCAS),
        .out(rst_r1),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_12 ),
        .rs2mask0_24(rs2mask0_24),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_13 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_13 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_13 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_13 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_13 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_29 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_30 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_13 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_13 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_13 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_13 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_13 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_13 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_13 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_13 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_12 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_13 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_13 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_13 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_13 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_29 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_30 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_13 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_13 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_13 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_13 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_13 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_13 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_13 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_27 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_28 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_13 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_13 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_13 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_12 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_13 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_13 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_13 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_13 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_29 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_30 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_13 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_13 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_13 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_13 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_13 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_13 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_13 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_27 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_28 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_13 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_13 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_13 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_12 ),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12]_13 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_13 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_13 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_11 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_27 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_13 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_43 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_44 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_13 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_13 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_13 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_13 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_13 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_13 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_13 ),
        .\rsMask_reg[7][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_27 ),
        .\rsMask_reg[7][9]_2 (\rsMask_reg[7][9]_28 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_14 \rdEn[1].u_ddr_mc_rd_en_upp 
       (.\blk1.(null)[0].diff (\blk1.(null)[0].diff ),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[7:4]),
        .in0(in0),
        .out(rst_r1),
        .\rdEn_reg[12]_0 (\rdEn_reg[12] ),
        .\rdEn_reg[12]_1 (\rdEn_reg[12]_0 ),
        .\rdEn_reg[14]_0 (\rdEn_reg[13] ),
        .\rdEn_reg[14]_1 (\rdEn_reg[12]_1 ),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11] ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9] ),
        .\rsMask_reg[1][11]_0 (\rsMask_reg[1][11] [2:0]),
        .\rsMask_reg[1][12]_0 (\rsMask_reg[1][12] ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15] ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16] ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17] ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18] ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_1 ),
        .\rsMask_reg[1][18]_2 (\rsMask_reg[1][18]_2 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1] ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4] ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5] ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6] ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8] ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11] ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9] ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10] ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11] [2:0]),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12] ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15] ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16] ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17] ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18] ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_1 ),
        .\rsMask_reg[3][18]_2 (\rsMask_reg[3][18]_2 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1] ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2] ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3] ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4] ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5] ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6] ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8] ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9] ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_0 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11] ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9] ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10] ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11] [2:0]),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12] ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15] ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16] ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17] ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18] ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_1 ),
        .\rsMask_reg[5][18]_2 (\rsMask_reg[5][18]_2 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1] ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2] ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3] ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4] ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5] ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6] ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8] ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9] ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_0 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11] ),
        .\rsMask_reg[6][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[6][9]_1 (\rsMask_reg[6][9] ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10] ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11] [2:0]),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12] ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15] ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16] ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_13 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18] ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_15 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_16 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1] ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2] ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3] ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4] ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5] ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6] ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8] ),
        .\rsMask_reg[7][9]_0 (\rsMask_reg[7][9] ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_15 \rdEn[2].u_ddr_mc_rd_en_low 
       (.\blk1.(null)[0].diff_23 (\blk1.(null)[0].diff_23 ),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[11:8]),
        .mcalCasSlot(mcalCasSlot),
        .mcalRank(mcalRank),
        .mcalRdCAS(mcalRdCAS),
        .out(rst_r1),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_11 ),
        .rs2mask0_22(rs2mask0_22),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_12 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_12 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_12 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_12 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_12 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_27 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_28 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_12 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_12 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_12 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_12 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_12 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_12 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_12 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_12 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_11 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_12 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_12 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_12 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_12 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_27 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_28 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_12 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_12 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_12 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_12 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_12 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_12 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_12 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_25 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_26 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_12 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_12 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_12 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_11 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_12 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_12 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_12 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_12 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_27 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_28 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_12 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_12 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_12 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_12 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_12 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_12 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_12 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_25 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_26 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_12 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_12 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_12 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_11 ),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12]_12 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_12 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_12 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_10 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_26 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_12 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_41 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_42 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_12 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_12 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_12 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_12 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_12 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_12 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_12 ),
        .\rsMask_reg[7][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_25 ),
        .\rsMask_reg[7][9]_2 (\rsMask_reg[7][9]_26 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_16 \rdEn[2].u_ddr_mc_rd_en_upp 
       (.\blk1.(null)[0].diff_5 (\blk1.(null)[0].diff_5 ),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[11:8]),
        .out(rst_r1),
        .\rdEn_reg[12]_0 (\rdEn_reg[12]_3 ),
        .\rdEn_reg[12]_1 (\rdEn_reg[12]_2 ),
        .\rdEn_reg[14]_0 (\rdEn_reg[14]_0 ),
        .\rdEn_reg[14]_1 (\rdEn_reg[14] ),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_2 ),
        .rs2mask0_4(rs2mask0_4),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_3 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_3 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_3 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_3 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_3 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_9 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_10 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_3 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_3 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_3 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_3 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_3 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_3 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_3 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_3 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_2 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_3 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_3 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_3 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_3 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_9 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_10 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_3 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_3 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_3 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_3 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_3 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_3 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_3 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_7 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_8 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_3 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_3 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_3 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_2 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_3 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_3 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_3 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_3 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_9 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_10 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_3 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_3 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_3 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_3 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_3 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_3 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_3 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_7 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_8 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_3 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_3 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_3 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_2 ),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12]_3 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_3 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_3 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_1 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_17 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_3 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_23 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_24 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_3 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_3 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_3 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_3 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_3 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_3 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_3 ),
        .\rsMask_reg[7][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_7 ),
        .\rsMask_reg[7][9]_2 (\rsMask_reg[7][9]_8 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_17 \rdEn[3].u_ddr_mc_rd_en_low 
       (.\blk1.(null)[0].diff_21 (\blk1.(null)[0].diff_21 ),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[15:12]),
        .mcalCasSlot(mcalCasSlot),
        .mcalRank(mcalRank),
        .mcalRdCAS(mcalRdCAS),
        .out(rst_r1),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_10 ),
        .rs2mask0_20(rs2mask0_20),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_11 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_11 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_11 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_11 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_11 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_25 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_26 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_11 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_11 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_11 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_11 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_11 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_11 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_11 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_11 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_10 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_11 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_11 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_11 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_11 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_25 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_26 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_11 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_11 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_11 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_11 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_11 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_11 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_11 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_23 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_24 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_11 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_11 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_11 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_10 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_11 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_11 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_11 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_11 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_25 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_26 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_11 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_11 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_11 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_11 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_11 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_11 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_11 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_23 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_24 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_11 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_11 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_11 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_10 ),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12]_11 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_11 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_11 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_9 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_25 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_11 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_39 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_40 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_11 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_11 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_11 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_11 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_11 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_11 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_11 ),
        .\rsMask_reg[7][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_23 ),
        .\rsMask_reg[7][9]_2 (\rsMask_reg[7][9]_24 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_18 \rdEn[3].u_ddr_mc_rd_en_upp 
       (.\blk1.(null)[0].diff_3 (\blk1.(null)[0].diff_3 ),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[15:12]),
        .out(rst_r1),
        .\rdEn_reg[12]_0 (\rdEn_reg[12]_2 ),
        .\rdEn_reg[12]_1 (\rdEn_reg[12]_3 ),
        .\rdEn_reg[14]_0 (\rdEn_reg[12] ),
        .\rdEn_reg[14]_1 (\rdEn_reg[14]_0 ),
        .\rdEn_reg[14]_2 (\rdEn_reg[14] ),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_1 ),
        .rs2mask0_2(rs2mask0_2),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_2 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_2 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_2 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_2 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_2 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_7 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_8 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_2 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_2 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_2 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_2 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_2 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_2 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_2 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_2 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_1 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_2 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_2 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_2 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_2 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_7 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_8 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_2 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_2 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_2 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_2 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_2 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_2 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_2 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_5 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_6 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_2 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_2 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_2 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_1 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_2 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_2 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_2 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_2 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_7 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_8 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_2 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_2 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_2 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_2 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_2 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_2 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_2 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_5 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_6 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_2 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_2 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_2 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_1 ),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12]_2 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_2 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_2 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_0 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_16 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_2 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_21 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_22 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_2 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_2 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_2 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_2 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_2 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_2 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_2 ),
        .\rsMask_reg[7][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_5 ),
        .\rsMask_reg[7][9]_2 (\rsMask_reg[7][9]_6 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_19 \rdEn[4].u_ddr_mc_rd_en_low 
       (.\blk1.(null)[0].diff_17 (\blk1.(null)[0].diff_17 ),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[19:16]),
        .mcalCasSlot(mcalCasSlot),
        .mcalRank(mcalRank),
        .mcalRdCAS(mcalRdCAS),
        .out(rst_r1),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_8 ),
        .rs2mask0_16(rs2mask0_16),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_9 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_9 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_9 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_9 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_9 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_21 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_22 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_9 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_9 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_9 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_9 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_9 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_9 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_9 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_9 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_8 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_9 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_9 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_9 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_9 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_21 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_22 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_9 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_9 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_9 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_9 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_9 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_9 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_9 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_19 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_20 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_9 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_9 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_9 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_8 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_9 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_9 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_9 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_9 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_21 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_22 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_9 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_9 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_9 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_9 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_9 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_9 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_9 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_19 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_20 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_9 ),
        .\rsMask_reg[6][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[6][9]_1 (\rsMask_reg[6][9]_9 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_9 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_8 ),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12]_9 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_9 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_9 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_7 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_23 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_9 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_35 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_36 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_9 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_9 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_9 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_9 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_9 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_9 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_9 ),
        .\rsMask_reg[7][9]_0 (\rsMask_reg[7][9]_19 ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_20 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_20 \rdEn[4].u_ddr_mc_rd_en_upp 
       (.\blk1.(null)[0].diff_7 (\blk1.(null)[0].diff_7 ),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[19:16]),
        .out(rst_r1),
        .\rdEn_reg[12]_0 (\rdEn_reg[12]_3 ),
        .\rdEn_reg[12]_1 (\rdEn_reg[12]_2 ),
        .\rdEn_reg[14]_0 (\rdEn_reg[14]_0 ),
        .\rdEn_reg[14]_1 (\rdEn_reg[14] ),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_3 ),
        .rs2mask0_6(rs2mask0_6),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_4 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_4 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_4 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_4 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_4 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_11 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_12 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_4 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_4 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_4 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_4 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_4 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_4 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_4 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_4 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_3 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_4 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_4 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_4 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_4 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_11 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_12 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_4 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_4 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_4 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_4 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_4 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_4 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_4 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_9 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_10 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_4 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_4 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_4 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_3 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_4 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_4 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_4 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_4 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_11 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_12 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_4 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_4 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_4 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_4 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_4 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_4 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_4 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_9 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_10 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_4 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_4 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_4 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_3 ),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12]_4 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_4 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_4 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_2 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_18 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_4 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_25 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_26 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_4 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_4 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_4 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_4 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_4 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_4 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_4 ),
        .\rsMask_reg[7][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_9 ),
        .\rsMask_reg[7][9]_2 (\rsMask_reg[7][9]_10 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_21 \rdEn[5].u_ddr_mc_rd_en_low 
       (.\blk1.(null)[0].diff_15 (\blk1.(null)[0].diff_15 ),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[23:20]),
        .mcalCasSlot(mcalCasSlot),
        .mcalRank(mcalRank),
        .mcalRdCAS(mcalRdCAS),
        .out(rst_r1),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_7 ),
        .rs2mask0_14(rs2mask0_14),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_8 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_8 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_8 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_8 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_8 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_19 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_20 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_8 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_8 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_8 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_8 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_8 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_8 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_8 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_8 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_7 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_8 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_8 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_8 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_8 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_19 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_20 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_8 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_8 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_8 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_8 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_8 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_8 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_8 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_17 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_18 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_8 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_8 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_8 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_7 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_8 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_8 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_8 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_8 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_19 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_20 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_8 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_8 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_8 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_8 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_8 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_8 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_8 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_17 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_18 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_8 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_8 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_8 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_7 ),
        .\rsMask_reg[7][12]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][12]_1 (\rsMask_reg[7][12]_8 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_8 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_8 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_6 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_22 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_8 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_33 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_34 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_8 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_8 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_8 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_8 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_8 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_8 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_8 ),
        .\rsMask_reg[7][9]_0 (\rsMask_reg[7][9]_17 ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_18 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_22 \rdEn[5].u_ddr_mc_rd_en_upp 
       (.\blk1.(null)[0].diff_13 (\blk1.(null)[0].diff_13 ),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[23:20]),
        .out(rst_r1),
        .\rdEn_reg[12]_0 (\rdEn_reg[12] ),
        .\rdEn_reg[12]_1 (\rdEn_reg[12]_1 ),
        .\rdEn_reg[14]_0 (\rdEn_reg[12]_0 ),
        .\rdEn_reg[14]_1 (\rdEn_reg[13] ),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_6 ),
        .rs2mask0_12(rs2mask0_12),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_7 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_7 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_7 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_7 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_7 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_17 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_18 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_7 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_7 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_7 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_7 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_7 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_7 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_7 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_7 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_6 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_7 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_7 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_7 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_7 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_17 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_18 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_7 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_7 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_7 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_7 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_7 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_7 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_7 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_15 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_16 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_7 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_7 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_7 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_6 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_7 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_7 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_7 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_7 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_17 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_18 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_7 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_7 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_7 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_7 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_7 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_7 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_7 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_15 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_16 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_7 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_7 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_7 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_6 ),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12]_7 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_7 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_7 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_5 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_21 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_7 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_31 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_32 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_7 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_7 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_7 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_7 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_7 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_7 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_7 ),
        .\rsMask_reg[7][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_15 ),
        .\rsMask_reg[7][9]_2 (\rsMask_reg[7][9]_16 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_23 \rdEn[6].u_ddr_mc_rd_en_low 
       (.\blk1.(null)[0].diff_19 (\blk1.(null)[0].diff_19 ),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[27:24]),
        .mcalCasSlot(mcalCasSlot),
        .mcalRdCAS(mcalRdCAS),
        .out(rst_r1),
        .\rdEn_reg[12]_0 (\rdEn_reg[12]_1 ),
        .\rdEn_reg[12]_1 (\rdEn_reg[12] ),
        .\rdEn_reg[14]_0 (\rdEn_reg[12]_0 ),
        .\rdEn_reg[14]_1 (\rdEn_reg[13] ),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_9 ),
        .rs2mask0_18(rs2mask0_18),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_10 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_10 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_10 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_10 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_10 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_23 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_24 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_10 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_10 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_10 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_10 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_10 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_10 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_10 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_10 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_9 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_10 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_10 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_10 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_10 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_23 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_24 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_10 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_10 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_10 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_10 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_10 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_10 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_10 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_21 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_22 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_10 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_10 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_10 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_9 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_10 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_10 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_10 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_10 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_23 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_24 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_10 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_10 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_10 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_10 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_10 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_10 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_10 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_21 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_22 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_10 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_10 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_10 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_9 ),
        .\rsMask_reg[7][12]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][12]_1 (\rsMask_reg[7][12]_10 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_10 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_10 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_8 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_24 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_10 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_37 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_38 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_10 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_10 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_10 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_10 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_10 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_10 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_10 ),
        .\rsMask_reg[7][9]_0 (\rsMask_reg[7][9]_21 ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_22 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_24 \rdEn[6].u_ddr_mc_rd_en_upp 
       (.\blk1.(null)[0].diff_1 (\blk1.(null)[0].diff_1 ),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[27:24]),
        .out(rst_r1),
        .\rdEn_reg[12]_0 (\rdEn_reg[12] ),
        .\rdEn_reg[12]_1 (\rdEn_reg[12]_2 ),
        .\rdEn_reg[14]_0 (\rdEn_reg[14]_0 ),
        .\rdEn_reg[14]_1 (\rdEn_reg[14] ),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_0 ),
        .rs2mask0(rs2mask0),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_1 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_1 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_1 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_1 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_1 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_5 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_6 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_1 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_1 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_1 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_1 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_1 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_1 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_1 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_1 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_0 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_1 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_1 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_1 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_1 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_5 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_6 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_1 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_1 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_1 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_1 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_1 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_1 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_1 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_3 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_4 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_1 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_1 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_1 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_0 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_1 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_1 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_1 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_1 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_5 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_6 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_1 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_1 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_1 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_1 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_1 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_1 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_1 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_3 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_4 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_1 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_1 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_1 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_0 ),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12]_1 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_1 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_1 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17] ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_15 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_1 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_19 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_20 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_1 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_1 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_1 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_1 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_1 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_1 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_1 ),
        .\rsMask_reg[7][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_3 ),
        .\rsMask_reg[7][9]_2 (\rsMask_reg[7][9]_4 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_25 \rdEn[7].u_ddr_mc_rd_en_low 
       (.\blk1.(null)[0].diff_9 (\blk1.(null)[0].diff_9 ),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low[31:28]),
        .out(rst_r1),
        .\rdEn_reg[12]_0 (\rdEn_reg[12] ),
        .\rdEn_reg[12]_1 (\rdEn_reg[12]_1 ),
        .\rdEn_reg[14]_0 (\rdEn_reg[12]_0 ),
        .\rdEn_reg[14]_1 (\rdEn_reg[13] ),
        .\rdEn_reg[29]_0 (\rdEn_reg[29]_4 ),
        .rs2mask0_8(rs2mask0_8),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_5 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_5 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_5 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_5 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_5 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_13 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_14 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_5 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_5 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_5 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_5 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_5 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_5 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_5 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_5 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11]_4 ),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_5 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_5 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_5 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_5 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_13 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_14 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_5 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_5 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_5 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_5 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_5 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_5 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_5 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_11 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_12 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_5 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_5 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_5 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11]_4 ),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_5 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_5 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_5 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_5 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_13 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_14 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_5 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_5 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_5 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_5 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_5 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_5 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_5 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_11 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_12 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_5 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_5 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_5 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11]_4 ),
        .\rsMask_reg[7][12]_0 (\rsMask_reg[7][12]_5 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_5 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_5 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_3 ),
        .\rsMask_reg[7][17]_1 (\rsMask_reg[7][17]_19 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_5 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_27 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_28 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_5 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_5 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_5 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_5 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_5 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_5 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_5 ),
        .\rsMask_reg[7][9]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_11 ),
        .\rsMask_reg[7][9]_2 (\rsMask_reg[7][9]_12 ));
  ddr4_0_ddr4_v2_2_17_cal_rd_en_26 \rdEn[7].u_ddr_mc_rd_en_upp 
       (.\blk1.(null)[0].diff_0 (\blk1.(null)[0].diff_0 ),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp[31:28]),
        .out(rst_r1),
        .\rdEn_reg[12]_0 (\rdEn_reg[12] ),
        .\rdEn_reg[12]_1 (\rdEn_reg[12]_0 ),
        .\rdEn_reg[13]_0 (\rdEn_reg[13] ),
        .\rdEn_reg[14]_0 (\rdEn_reg[14] ),
        .\rdEn_reg[14]_1 (\rdEn_reg[12]_1 ),
        .\rdEn_reg[29]_0 (\rdEn_reg[29] ),
        .\rsMask_reg[0][11]_0 (\rsMask_reg[0][11]_0 ),
        .\rsMask_reg[0][9]_0 (\rsMask_reg[0][9]_0 ),
        .\rsMask_reg[1][11]_0 (\rsMask_reg[1][11] [5:3]),
        .\rsMask_reg[1][12]_0 (\rsMask_reg[1][12]_0 ),
        .\rsMask_reg[1][15]_0 (\rsMask_reg[1][15]_0 ),
        .\rsMask_reg[1][16]_0 (\rsMask_reg[1][16]_0 ),
        .\rsMask_reg[1][17]_0 (\rsMask_reg[1][17]_0 ),
        .\rsMask_reg[1][18]_0 (\rsMask_reg[1][18]_0 ),
        .\rsMask_reg[1][18]_1 (\rsMask_reg[1][18]_3 ),
        .\rsMask_reg[1][18]_2 (\rsMask_reg[1][18]_4 ),
        .\rsMask_reg[1][1]_0 (\rsMask_reg[1][1]_0 ),
        .\rsMask_reg[1][4]_0 (\rsMask_reg[1][4]_0 ),
        .\rsMask_reg[1][5]_0 (\rsMask_reg[1][5]_0 ),
        .\rsMask_reg[1][6]_0 (\rsMask_reg[1][6]_0 ),
        .\rsMask_reg[1][8]_0 (\rsMask_reg[1][8]_0 ),
        .\rsMask_reg[2][11]_0 (\rsMask_reg[2][11]_0 ),
        .\rsMask_reg[2][9]_0 (\rsMask_reg[2][9]_0 ),
        .\rsMask_reg[3][10]_0 (\rsMask_reg[3][10]_0 ),
        .\rsMask_reg[3][11]_0 (\rsMask_reg[3][11] [5:3]),
        .\rsMask_reg[3][12]_0 (\rsMask_reg[3][12]_0 ),
        .\rsMask_reg[3][15]_0 (\rsMask_reg[3][15]_0 ),
        .\rsMask_reg[3][16]_0 (\rsMask_reg[3][16]_0 ),
        .\rsMask_reg[3][17]_0 (\rsMask_reg[3][17]_0 ),
        .\rsMask_reg[3][18]_0 (\rsMask_reg[3][18]_0 ),
        .\rsMask_reg[3][18]_1 (\rsMask_reg[3][18]_3 ),
        .\rsMask_reg[3][18]_2 (\rsMask_reg[3][18]_4 ),
        .\rsMask_reg[3][1]_0 (\rsMask_reg[3][1]_0 ),
        .\rsMask_reg[3][2]_0 (\rsMask_reg[3][2]_0 ),
        .\rsMask_reg[3][3]_0 (\rsMask_reg[3][3]_0 ),
        .\rsMask_reg[3][4]_0 (\rsMask_reg[3][4]_0 ),
        .\rsMask_reg[3][5]_0 (\rsMask_reg[3][5]_0 ),
        .\rsMask_reg[3][6]_0 (\rsMask_reg[3][6]_0 ),
        .\rsMask_reg[3][8]_0 (\rsMask_reg[3][8]_0 ),
        .\rsMask_reg[3][9]_0 (\rsMask_reg[3][9]_1 ),
        .\rsMask_reg[3][9]_1 (\rsMask_reg[3][9]_2 ),
        .\rsMask_reg[4][11]_0 (\rsMask_reg[4][11]_0 ),
        .\rsMask_reg[4][9]_0 (\rsMask_reg[4][9]_0 ),
        .\rsMask_reg[5][10]_0 (\rsMask_reg[5][10]_0 ),
        .\rsMask_reg[5][11]_0 (\rsMask_reg[5][11] [5:3]),
        .\rsMask_reg[5][12]_0 (\rsMask_reg[5][12]_0 ),
        .\rsMask_reg[5][15]_0 (\rsMask_reg[5][15]_0 ),
        .\rsMask_reg[5][16]_0 (\rsMask_reg[5][16]_0 ),
        .\rsMask_reg[5][17]_0 (\rsMask_reg[5][17]_0 ),
        .\rsMask_reg[5][18]_0 (\rsMask_reg[5][18]_0 ),
        .\rsMask_reg[5][18]_1 (\rsMask_reg[5][18]_3 ),
        .\rsMask_reg[5][18]_2 (\rsMask_reg[5][18]_4 ),
        .\rsMask_reg[5][1]_0 (\rsMask_reg[5][1]_0 ),
        .\rsMask_reg[5][2]_0 (\rsMask_reg[5][2]_0 ),
        .\rsMask_reg[5][3]_0 (\rsMask_reg[5][3]_0 ),
        .\rsMask_reg[5][4]_0 (\rsMask_reg[5][4]_0 ),
        .\rsMask_reg[5][5]_0 (\rsMask_reg[5][5]_0 ),
        .\rsMask_reg[5][6]_0 (\rsMask_reg[5][6]_0 ),
        .\rsMask_reg[5][8]_0 (\rsMask_reg[5][8]_0 ),
        .\rsMask_reg[5][9]_0 (\rsMask_reg[5][9]_1 ),
        .\rsMask_reg[5][9]_1 (\rsMask_reg[5][9]_2 ),
        .\rsMask_reg[6][11]_0 (\rsMask_reg[6][11]_0 ),
        .\rsMask_reg[6][9]_0 (\rsMask_reg[6][9]_0 ),
        .\rsMask_reg[7][10]_0 (\rsMask_reg[7][10]_0 ),
        .\rsMask_reg[7][11]_0 (\rsMask_reg[7][11] [5:3]),
        .\rsMask_reg[7][12]_0 (\dReg_reg[10] ),
        .\rsMask_reg[7][12]_1 (\rsMask_reg[7][12]_0 ),
        .\rsMask_reg[7][15]_0 (\rsMask_reg[7][15]_0 ),
        .\rsMask_reg[7][16]_0 (\rsMask_reg[7][16]_0 ),
        .\rsMask_reg[7][17]_0 (\rsMask_reg[7][17]_14 ),
        .\rsMask_reg[7][18]_0 (\rsMask_reg[7][18]_0 ),
        .\rsMask_reg[7][18]_1 (\rsMask_reg[7][18]_17 ),
        .\rsMask_reg[7][18]_2 (\rsMask_reg[7][18]_18 ),
        .\rsMask_reg[7][1]_0 (\rsMask_reg[7][1]_0 ),
        .\rsMask_reg[7][2]_0 (\rsMask_reg[7][2]_0 ),
        .\rsMask_reg[7][3]_0 (\rsMask_reg[7][3]_0 ),
        .\rsMask_reg[7][4]_0 (\rsMask_reg[7][4]_0 ),
        .\rsMask_reg[7][5]_0 (\rsMask_reg[7][5]_0 ),
        .\rsMask_reg[7][6]_0 (\rsMask_reg[7][6]_0 ),
        .\rsMask_reg[7][8]_0 (\rsMask_reg[7][8]_0 ),
        .\rsMask_reg[7][9]_0 (\rsMask_reg[7][9]_1 ),
        .\rsMask_reg[7][9]_1 (\rsMask_reg[7][9]_2 ));
  (* KEEP = "yes" *) 
  FDRE rst_r1_reg
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(SR),
        .Q(rst_r1),
        .R(1'b0));
  ddr4_0_ddr4_v2_2_17_cal_read u_ddr_mc_read
       (.D(D),
        .DOA(DOA),
        .DOB(DOB),
        .DOC(DOC),
        .Q(Q),
        .calDone_reg(calDone_reg),
        .calRdCAS(calRdCAS),
        .cal_clear_fifo_rden(cal_clear_fifo_rden),
        .cmdBuf(cmdBuf),
        .cnt_clr(cnt_clr),
        .match4_10_return(match4_10_return),
        .match4_110_return(match4_110_return),
        .match4_111_return(match4_111_return),
        .match4_112_return(match4_112_return),
        .match4_113_return(match4_113_return),
        .match4_114_return(match4_114_return),
        .match4_115_return(match4_115_return),
        .match4_116_return(match4_116_return),
        .match4_117_return(match4_117_return),
        .match4_118_return(match4_118_return),
        .match4_119_return(match4_119_return),
        .match4_11_return(match4_11_return),
        .match4_120_return(match4_120_return),
        .match4_121_return(match4_121_return),
        .match4_122_return(match4_122_return),
        .match4_123_return(match4_123_return),
        .match4_124_return(match4_124_return),
        .match4_125_return(match4_125_return),
        .match4_126_return(match4_126_return),
        .match4_127_return(match4_127_return),
        .match4_128_return(match4_128_return),
        .match4_129_return(match4_129_return),
        .match4_12_return(match4_12_return),
        .match4_130_return(match4_130_return),
        .match4_131_return(match4_131_return),
        .match4_132_return(match4_132_return),
        .match4_133_return(match4_133_return),
        .match4_134_return(match4_134_return),
        .match4_135_return(match4_135_return),
        .match4_136_return(match4_136_return),
        .match4_137_return(match4_137_return),
        .match4_138_return(match4_138_return),
        .match4_139_return(match4_139_return),
        .match4_13_return(match4_13_return),
        .match4_140_return(match4_140_return),
        .match4_141_return(match4_141_return),
        .match4_142_return(match4_142_return),
        .match4_143_return(match4_143_return),
        .match4_144_return(match4_144_return),
        .match4_145_return(match4_145_return),
        .match4_146_return(match4_146_return),
        .match4_147_return(match4_147_return),
        .match4_148_return(match4_148_return),
        .match4_149_return(match4_149_return),
        .match4_14_return(match4_14_return),
        .match4_150_return(match4_150_return),
        .match4_151_return(match4_151_return),
        .match4_152_return(match4_152_return),
        .match4_153_return(match4_153_return),
        .match4_154_return(match4_154_return),
        .match4_155_return(match4_155_return),
        .match4_156_return(match4_156_return),
        .match4_157_return(match4_157_return),
        .match4_158_return(match4_158_return),
        .match4_159_return(match4_159_return),
        .match4_15_return(match4_15_return),
        .match4_160_return(match4_160_return),
        .match4_161_return(match4_161_return),
        .match4_162_return(match4_162_return),
        .match4_163_return(match4_163_return),
        .match4_164_return(match4_164_return),
        .match4_165_return(match4_165_return),
        .match4_166_return(match4_166_return),
        .match4_167_return(match4_167_return),
        .match4_168_return(match4_168_return),
        .match4_169_return(match4_169_return),
        .match4_16_return(match4_16_return),
        .match4_170_return(match4_170_return),
        .match4_171_return(match4_171_return),
        .match4_172_return(match4_172_return),
        .match4_173_return(match4_173_return),
        .match4_174_return(match4_174_return),
        .match4_175_return(match4_175_return),
        .match4_176_return(match4_176_return),
        .match4_177_return(match4_177_return),
        .match4_178_return(match4_178_return),
        .match4_179_return(match4_179_return),
        .match4_17_return(match4_17_return),
        .match4_180_return(match4_180_return),
        .match4_181_return(match4_181_return),
        .match4_182_return(match4_182_return),
        .match4_183_return(match4_183_return),
        .match4_184_return(match4_184_return),
        .match4_185_return(match4_185_return),
        .match4_186_return(match4_186_return),
        .match4_187_return(match4_187_return),
        .match4_188_return(match4_188_return),
        .match4_18_return(match4_18_return),
        .match4_19_return(match4_19_return),
        .match4_1_return(match4_1_return),
        .match6_10_return(match6_10_return),
        .match6_110_return(match6_110_return),
        .match6_111_return(match6_111_return),
        .match6_112_return(match6_112_return),
        .match6_113_return(match6_113_return),
        .match6_114_return(match6_114_return),
        .match6_115_return(match6_115_return),
        .match6_116_return(match6_116_return),
        .match6_117_return(match6_117_return),
        .match6_118_return(match6_118_return),
        .match6_119_return(match6_119_return),
        .match6_11_return(match6_11_return),
        .match6_120_return(match6_120_return),
        .match6_121_return(match6_121_return),
        .match6_122_return(match6_122_return),
        .match6_123_return(match6_123_return),
        .match6_124_return(match6_124_return),
        .match6_125_return(match6_125_return),
        .match6_126_return(match6_126_return),
        .match6_127_return(match6_127_return),
        .match6_128_return(match6_128_return),
        .match6_129_return(match6_129_return),
        .match6_12_return(match6_12_return),
        .match6_130_return(match6_130_return),
        .match6_131_return(match6_131_return),
        .match6_132_return(match6_132_return),
        .match6_133_return(match6_133_return),
        .match6_134_return(match6_134_return),
        .match6_135_return(match6_135_return),
        .match6_136_return(match6_136_return),
        .match6_137_return(match6_137_return),
        .match6_138_return(match6_138_return),
        .match6_139_return(match6_139_return),
        .match6_13_return(match6_13_return),
        .match6_140_return(match6_140_return),
        .match6_141_return(match6_141_return),
        .match6_142_return(match6_142_return),
        .match6_143_return(match6_143_return),
        .match6_144_return(match6_144_return),
        .match6_145_return(match6_145_return),
        .match6_146_return(match6_146_return),
        .match6_147_return(match6_147_return),
        .match6_148_return(match6_148_return),
        .match6_149_return(match6_149_return),
        .match6_14_return(match6_14_return),
        .match6_150_return(match6_150_return),
        .match6_151_return(match6_151_return),
        .match6_152_return(match6_152_return),
        .match6_153_return(match6_153_return),
        .match6_154_return(match6_154_return),
        .match6_155_return(match6_155_return),
        .match6_156_return(match6_156_return),
        .match6_157_return(match6_157_return),
        .match6_158_return(match6_158_return),
        .match6_159_return(match6_159_return),
        .match6_15_return(match6_15_return),
        .match6_160_return(match6_160_return),
        .match6_161_return(match6_161_return),
        .match6_162_return(match6_162_return),
        .match6_163_return(match6_163_return),
        .match6_164_return(match6_164_return),
        .match6_165_return(match6_165_return),
        .match6_166_return(match6_166_return),
        .match6_167_return(match6_167_return),
        .match6_168_return(match6_168_return),
        .match6_169_return(match6_169_return),
        .match6_16_return(match6_16_return),
        .match6_170_return(match6_170_return),
        .match6_171_return(match6_171_return),
        .match6_172_return(match6_172_return),
        .match6_173_return(match6_173_return),
        .match6_174_return(match6_174_return),
        .match6_175_return(match6_175_return),
        .match6_176_return(match6_176_return),
        .match6_177_return(match6_177_return),
        .match6_178_return(match6_178_return),
        .match6_179_return(match6_179_return),
        .match6_17_return(match6_17_return),
        .match6_180_return(match6_180_return),
        .match6_181_return(match6_181_return),
        .match6_182_return(match6_182_return),
        .match6_183_return(match6_183_return),
        .match6_184_return(match6_184_return),
        .match6_185_return(match6_185_return),
        .match6_186_return(match6_186_return),
        .match6_187_return(match6_187_return),
        .match6_188_return(match6_188_return),
        .match6_18_return(match6_18_return),
        .match6_19_return(match6_19_return),
        .match6_1_return(match6_1_return),
        .mcRdCAS(mcRdCAS),
        .mc_clb2phy_fifo_rden_nxt(mc_clb2phy_fifo_rden_nxt),
        .\not_strict_mode.app_rd_data_end_reg (\not_strict_mode.app_rd_data_end_reg ),
        .\not_strict_mode.bypass_cpy2 (\not_strict_mode.bypass_cpy2 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] (\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] (\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] (\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] (\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] (\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] (\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] (\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] (\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] (\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] (\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] (\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] (\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] (\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] (\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] (\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] (\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] (\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] (\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] (\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] (\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] (\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] (\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] (\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] (\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] (\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] (\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] (\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] (\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] (\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] (\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] (\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] (\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] (\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] (\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] (\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] (\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] (\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] (\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] (\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] (\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] (\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] (\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] (\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] (\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] (\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] (\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] (\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] (\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] (\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] (\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] (\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] (\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] (\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] (\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] (\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] (\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] (\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] (\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] (\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] (\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] (\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] (\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] (\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] (\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] (\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] (\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] (\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] (\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] (\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] (\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] (\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] (\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] (\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] (\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] (\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] (\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] (\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] (\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] (\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] (\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] (\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] (\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] (\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] (\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] (\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] (\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] (\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] (\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] (\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] (\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] (\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] (\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] (\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] (\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] (\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] (\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] (\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] (\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] (\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] (\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] (\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] (\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] (\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] (\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] (\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] (\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] (\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] (\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] (\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] (\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] (\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] (\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] (\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] (\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] (\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] (\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] (\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] (\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] (\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] (\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] (\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] (\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] (\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] (\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] (\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] (\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] (\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] (\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] (\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] (\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] (\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] (\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] (\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] (\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] (\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] (\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] (\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] (\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] (\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] (\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] (\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] (\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] (\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] (\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] (\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] (\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] (\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] (\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] (\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] (\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] (\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] (\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] (\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] (\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] (\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] (\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] (\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] (\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] (\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] (\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] (\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] (\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] (\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] (\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] (\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] (\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] (\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] (\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] (\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] (\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] (\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] (\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] (\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] (\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] (\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] (\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] (\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] (\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] (\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] (\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] (\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] (\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] (\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] (\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] (\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] (\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] (\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] (\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] (\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] (\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] (\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] (\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] (\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] (\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] (\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] (\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] (\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] (\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] (\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] (\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] (\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] (\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] (\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] (\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] (\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] (\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] (\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] (\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] (\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] (\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] (\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] (\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] (\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] (\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] (\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] (\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] (\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] (\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] (\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] (\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] (\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] (\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] (\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] (\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] (\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] (\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] (\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] (\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] (\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] (\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] (\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] (\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] (\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] (\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] (\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] (\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] (\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] (\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] (\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] (\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] (\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] (\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] (\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] (\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] (\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] (\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] (\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 (\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] (\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] (\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] (\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] (\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] (\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] (\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] (\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] (\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ),
        .\not_strict_mode.status_ram_0.RAM32M0 (\not_strict_mode.status_ram_0.RAM32M0 ),
        .\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] (\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] ),
        .\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] (\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] ),
        .\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] (\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] ),
        .\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] (\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] ),
        .out(rst_r1),
        .per_rd_done(per_rd_done),
        .pop_read_lat_fifo_reg_0(pop_read_lat_fifo_reg),
        .rdCAS_reg_0(\oe_low_reg[5] ),
        .\rdDataAddr_reg[3]_rep_0 (\rdDataAddr_reg[3]_rep ),
        .\rdDataAddr_reg[3]_rep__0_0 (\rdDataAddr_reg[3]_rep__0 ),
        .\rdDataAddr_reg[3]_rep__1_0 (\rdDataAddr_reg[3]_rep__1 ),
        .\rdDataAddr_reg[4]_0 (\rdDataAddr_reg[4] ),
        .\rdDataAddr_reg[4]_1 (\rdDataAddr_reg[4]_0 ),
        .\rdDataAddr_reg[4]_2 (\rdDataAddr_reg[4]_1 ),
        .\rdDataAddr_reg[4]_rep_0 (\rdDataAddr_reg[4]_rep ),
        .\rdDataAddr_reg[4]_rep__0_0 (\rdDataAddr_reg[4]_rep__0 ),
        .\rdDataAddr_reg[4]_rep__1_0 (\rdDataAddr_reg[4]_rep__1 ),
        .\rdDataAddr_reg[4]_rep__1_1 (\dReg_reg[10] ),
        .\rdData_reg[101] (\rdData_reg[101] ),
        .\rdData_reg[107] (\rdData_reg[107] ),
        .\rdData_reg[113] (\rdData_reg[113] ),
        .\rdData_reg[119] (\rdData_reg[119] ),
        .\rdData_reg[11] (\rdData_reg[11] ),
        .\rdData_reg[125] (\rdData_reg[125] ),
        .\rdData_reg[131] (\rdData_reg[131] ),
        .\rdData_reg[137] (\rdData_reg[137] ),
        .\rdData_reg[143] (\rdData_reg[143] ),
        .\rdData_reg[149] (\rdData_reg[149] ),
        .\rdData_reg[155] (\rdData_reg[155] ),
        .\rdData_reg[161] (\rdData_reg[161] ),
        .\rdData_reg[167] (\rdData_reg[167] ),
        .\rdData_reg[173] (\rdData_reg[173] ),
        .\rdData_reg[179] (\rdData_reg[179] ),
        .\rdData_reg[17] (\rdData_reg[17] ),
        .\rdData_reg[185] (\rdData_reg[185] ),
        .\rdData_reg[191] (\rdData_reg[191] ),
        .\rdData_reg[197] (\rdData_reg[197] ),
        .\rdData_reg[203] (\rdData_reg[203] ),
        .\rdData_reg[209] (\rdData_reg[209] ),
        .\rdData_reg[215] (\rdData_reg[215] ),
        .\rdData_reg[221] (\rdData_reg[221] ),
        .\rdData_reg[227] (\rdData_reg[227] ),
        .\rdData_reg[233] (\rdData_reg[233] ),
        .\rdData_reg[239] (\rdData_reg[239] ),
        .\rdData_reg[23] (\rdData_reg[23] ),
        .\rdData_reg[245] (\rdData_reg[245] ),
        .\rdData_reg[251] (\rdData_reg[251] ),
        .\rdData_reg[257] (\rdData_reg[257] ),
        .\rdData_reg[263] (\rdData_reg[263] ),
        .\rdData_reg[269] (\rdData_reg[269] ),
        .\rdData_reg[275] (\rdData_reg[275] ),
        .\rdData_reg[281] (\rdData_reg[281] ),
        .\rdData_reg[287] (\rdData_reg[287] ),
        .\rdData_reg[293] (\rdData_reg[293] ),
        .\rdData_reg[299] (\rdData_reg[299] ),
        .\rdData_reg[29] (\rdData_reg[29] ),
        .\rdData_reg[305] (\rdData_reg[305] ),
        .\rdData_reg[311] (\rdData_reg[311] ),
        .\rdData_reg[317] (\rdData_reg[317] ),
        .\rdData_reg[323] (\rdData_reg[323] ),
        .\rdData_reg[329] (\rdData_reg[329] ),
        .\rdData_reg[335] (\rdData_reg[335] ),
        .\rdData_reg[341] (\rdData_reg[341] ),
        .\rdData_reg[347] (\rdData_reg[347] ),
        .\rdData_reg[353] (\rdData_reg[353] ),
        .\rdData_reg[359] (\rdData_reg[359] ),
        .\rdData_reg[35] (\rdData_reg[35] ),
        .\rdData_reg[365] (\rdData_reg[365] ),
        .\rdData_reg[371] (\rdData_reg[371] ),
        .\rdData_reg[377] (\rdData_reg[377] ),
        .\rdData_reg[383] (\rdData_reg[383] ),
        .\rdData_reg[389] (\rdData_reg[389] ),
        .\rdData_reg[395] (\rdData_reg[395] ),
        .\rdData_reg[401] (\rdData_reg[401] ),
        .\rdData_reg[407] (\rdData_reg[407] ),
        .\rdData_reg[413] (\rdData_reg[413] ),
        .\rdData_reg[419] (\rdData_reg[419] ),
        .\rdData_reg[41] (\rdData_reg[41] ),
        .\rdData_reg[425] (\rdData_reg[425] ),
        .\rdData_reg[431] (\rdData_reg[431] ),
        .\rdData_reg[437] (\rdData_reg[437] ),
        .\rdData_reg[443] (\rdData_reg[443] ),
        .\rdData_reg[449] (\rdData_reg[449] ),
        .\rdData_reg[455] (\rdData_reg[455] ),
        .\rdData_reg[461] (\rdData_reg[461] ),
        .\rdData_reg[467] (\rdData_reg[467] ),
        .\rdData_reg[473] (\rdData_reg[473] ),
        .\rdData_reg[479] (\rdData_reg[479] ),
        .\rdData_reg[47] (\rdData_reg[47] ),
        .\rdData_reg[485] (\rdData_reg[485] ),
        .\rdData_reg[491] (\rdData_reg[491] ),
        .\rdData_reg[497] (\rdData_reg[497] ),
        .\rdData_reg[503] (\rdData_reg[503] ),
        .\rdData_reg[509] (\rdData_reg[509] ),
        .\rdData_reg[511] (\rdData_reg[511] ),
        .\rdData_reg[53] (\rdData_reg[53] ),
        .\rdData_reg[59] (\rdData_reg[59] ),
        .\rdData_reg[5] (\rdData_reg[5] ),
        .\rdData_reg[65] (\rdData_reg[65] ),
        .\rdData_reg[71] (\rdData_reg[71] ),
        .\rdData_reg[77] (\rdData_reg[77] ),
        .\rdData_reg[83] (\rdData_reg[83] ),
        .\rdData_reg[89] (\rdData_reg[89] ),
        .\rdData_reg[95] (\rdData_reg[95] ),
        .read_data_en_reg_0(rdDataEn_pi),
        .\read_lat_fifo_in_reg[6]_0 (\read_lat_fifo_in_reg[6] ),
        .read_lat_shift_cal_dq_valid_nxt(read_lat_shift_cal_dq_valid_nxt),
        .\read_lat_shift_reg[31]_0 (\read_lat_shift_reg[31] ),
        .underfill_done_nxt(underfill_done_nxt));
  ddr4_0_ddr4_v2_2_17_cal_write u_ddr_mc_write
       (.ADDRA(ADDRA),
        .ADDRC(ADDRC),
        .DMOut(DMOut),
        .DQOut(DQOut),
        .cal_oe_dis_low(cal_oe_dis_low),
        .cal_oe_dis_upp(cal_oe_dis_upp),
        .ch0_mcal_DMOut_n(ch0_mcal_DMOut_n),
        .ch0_mcal_DQOut(ch0_mcal_DQOut),
        .\dReg_reg[10] (\dReg_reg[10] ),
        .\dReg_reg[10]_0 (\dReg_reg[10]_0 ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_1 ),
        .\dReg_reg[10]_10 (\dReg_reg[10]_10 ),
        .\dReg_reg[10]_11 (\dReg_reg[10]_11 ),
        .\dReg_reg[10]_12 (\dReg_reg[10]_12 ),
        .\dReg_reg[10]_13 (\dReg_reg[10]_13 ),
        .\dReg_reg[10]_14 (\dReg_reg[10]_14 ),
        .\dReg_reg[10]_15 (\dReg_reg[10]_15 ),
        .\dReg_reg[10]_16 (\dReg_reg[10]_16 ),
        .\dReg_reg[10]_17 (\dReg_reg[10]_17 ),
        .\dReg_reg[10]_18 (\dReg_reg[10]_18 ),
        .\dReg_reg[10]_19 (\dReg_reg[10]_19 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_2 ),
        .\dReg_reg[10]_20 (\dReg_reg[10]_20 ),
        .\dReg_reg[10]_21 (\dReg_reg[10]_21 ),
        .\dReg_reg[10]_22 (\dReg_reg[10]_22 ),
        .\dReg_reg[10]_23 (\dReg_reg[10]_23 ),
        .\dReg_reg[10]_24 (\dReg_reg[10]_24 ),
        .\dReg_reg[10]_25 (\dReg_reg[10]_25 ),
        .\dReg_reg[10]_26 (\dReg_reg[10]_26 ),
        .\dReg_reg[10]_27 (\dReg_reg[10]_27 ),
        .\dReg_reg[10]_28 (\dReg_reg[10]_28 ),
        .\dReg_reg[10]_29 (\dReg_reg[10]_29 ),
        .\dReg_reg[10]_3 (\dReg_reg[10]_3 ),
        .\dReg_reg[10]_30 (\dReg_reg[10]_30 ),
        .\dReg_reg[10]_31 (\dReg_reg[10]_31 ),
        .\dReg_reg[10]_32 (\dReg_reg[10]_32 ),
        .\dReg_reg[10]_33 (\dReg_reg[10]_33 ),
        .\dReg_reg[10]_34 (\dReg_reg[10]_34 ),
        .\dReg_reg[10]_35 (\dReg_reg[10]_35 ),
        .\dReg_reg[10]_36 (\dReg_reg[10]_36 ),
        .\dReg_reg[10]_37 (\dReg_reg[10]_37 ),
        .\dReg_reg[10]_38 (\dReg_reg[10]_38 ),
        .\dReg_reg[10]_39 (\dReg_reg[10]_39 ),
        .\dReg_reg[10]_4 (\dReg_reg[10]_4 ),
        .\dReg_reg[10]_40 (\dReg_reg[10]_40 ),
        .\dReg_reg[10]_41 (\dReg_reg[10]_41 ),
        .\dReg_reg[10]_42 (\dReg_reg[10]_42 ),
        .\dReg_reg[10]_43 (\dReg_reg[10]_43 ),
        .\dReg_reg[10]_44 (\dReg_reg[10]_44 ),
        .\dReg_reg[10]_45 (\dReg_reg[10]_45 ),
        .\dReg_reg[10]_46 (\dReg_reg[10]_46 ),
        .\dReg_reg[10]_47 (\dReg_reg[10]_47 ),
        .\dReg_reg[10]_48 (\dReg_reg[10]_48 ),
        .\dReg_reg[10]_49 (\dReg_reg[10]_49 ),
        .\dReg_reg[10]_5 (\dReg_reg[10]_5 ),
        .\dReg_reg[10]_50 (\dReg_reg[10]_50 ),
        .\dReg_reg[10]_51 (\dReg_reg[10]_51 ),
        .\dReg_reg[10]_52 (\dReg_reg[10]_52 ),
        .\dReg_reg[10]_53 (\dReg_reg[10]_53 ),
        .\dReg_reg[10]_54 (\dReg_reg[10]_54 ),
        .\dReg_reg[10]_55 (\dReg_reg[10]_55 ),
        .\dReg_reg[10]_56 (\dReg_reg[10]_56 ),
        .\dReg_reg[10]_57 (\dReg_reg[10]_57 ),
        .\dReg_reg[10]_58 (\dReg_reg[10]_58 ),
        .\dReg_reg[10]_59 (\dReg_reg[10]_59 ),
        .\dReg_reg[10]_6 (\dReg_reg[10]_6 ),
        .\dReg_reg[10]_60 (\dReg_reg[10]_60 ),
        .\dReg_reg[10]_61 (\dReg_reg[10]_61 ),
        .\dReg_reg[10]_62 (\dReg_reg[10]_62 ),
        .\dReg_reg[10]_63 (\dReg_reg[10]_63 ),
        .\dReg_reg[10]_64 (\dReg_reg[10]_64 ),
        .\dReg_reg[10]_65 (\dReg_reg[10]_65 ),
        .\dReg_reg[10]_66 (\dReg_reg[10]_66 ),
        .\dReg_reg[10]_67 (\dReg_reg[10]_67 ),
        .\dReg_reg[10]_68 (\dReg_reg[10]_68 ),
        .\dReg_reg[10]_69 (\dReg_reg[10]_69 ),
        .\dReg_reg[10]_7 (\dReg_reg[10]_7 ),
        .\dReg_reg[10]_70 (\dReg_reg[10]_70 ),
        .\dReg_reg[10]_71 (\dReg_reg[10]_71 ),
        .\dReg_reg[10]_8 (\dReg_reg[10]_8 ),
        .\dReg_reg[10]_9 (\dReg_reg[10]_9 ),
        .\dReg_reg[11] (\dReg_reg[11] ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_0 ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_1 ),
        .\dReg_reg[11]_10 (\dReg_reg[11]_10 ),
        .\dReg_reg[11]_11 (\dReg_reg[11]_11 ),
        .\dReg_reg[11]_12 (\dReg_reg[11]_12 ),
        .\dReg_reg[11]_13 (\dReg_reg[11]_13 ),
        .\dReg_reg[11]_14 (\dReg_reg[11]_14 ),
        .\dReg_reg[11]_15 (\dReg_reg[11]_15 ),
        .\dReg_reg[11]_16 (\dReg_reg[11]_16 ),
        .\dReg_reg[11]_17 (\dReg_reg[11]_17 ),
        .\dReg_reg[11]_18 (\dReg_reg[11]_18 ),
        .\dReg_reg[11]_19 (\dReg_reg[11]_19 ),
        .\dReg_reg[11]_2 (\dReg_reg[11]_2 ),
        .\dReg_reg[11]_20 (\dReg_reg[11]_20 ),
        .\dReg_reg[11]_21 (\dReg_reg[11]_21 ),
        .\dReg_reg[11]_22 (\dReg_reg[11]_22 ),
        .\dReg_reg[11]_23 (\dReg_reg[11]_23 ),
        .\dReg_reg[11]_24 (\dReg_reg[11]_24 ),
        .\dReg_reg[11]_25 (\dReg_reg[11]_25 ),
        .\dReg_reg[11]_26 (\dReg_reg[11]_26 ),
        .\dReg_reg[11]_27 (\dReg_reg[11]_27 ),
        .\dReg_reg[11]_28 (\dReg_reg[11]_28 ),
        .\dReg_reg[11]_29 (\dReg_reg[11]_29 ),
        .\dReg_reg[11]_3 (\dReg_reg[11]_3 ),
        .\dReg_reg[11]_30 (\dReg_reg[11]_30 ),
        .\dReg_reg[11]_31 (\dReg_reg[11]_31 ),
        .\dReg_reg[11]_32 (\dReg_reg[11]_32 ),
        .\dReg_reg[11]_33 (\dReg_reg[11]_33 ),
        .\dReg_reg[11]_34 (\dReg_reg[11]_34 ),
        .\dReg_reg[11]_35 (\dReg_reg[11]_35 ),
        .\dReg_reg[11]_36 (\dReg_reg[11]_36 ),
        .\dReg_reg[11]_37 (\dReg_reg[11]_37 ),
        .\dReg_reg[11]_38 (\dReg_reg[11]_38 ),
        .\dReg_reg[11]_39 (\dReg_reg[11]_39 ),
        .\dReg_reg[11]_4 (\dReg_reg[11]_4 ),
        .\dReg_reg[11]_40 (\dReg_reg[11]_40 ),
        .\dReg_reg[11]_41 (\dReg_reg[11]_41 ),
        .\dReg_reg[11]_42 (\dReg_reg[11]_42 ),
        .\dReg_reg[11]_43 (\dReg_reg[11]_43 ),
        .\dReg_reg[11]_44 (\dReg_reg[11]_44 ),
        .\dReg_reg[11]_45 (\dReg_reg[11]_45 ),
        .\dReg_reg[11]_46 (\dReg_reg[11]_46 ),
        .\dReg_reg[11]_47 (\dReg_reg[11]_47 ),
        .\dReg_reg[11]_48 (\dReg_reg[11]_48 ),
        .\dReg_reg[11]_49 (\dReg_reg[11]_49 ),
        .\dReg_reg[11]_5 (\dReg_reg[11]_5 ),
        .\dReg_reg[11]_50 (\dReg_reg[11]_50 ),
        .\dReg_reg[11]_51 (\dReg_reg[11]_51 ),
        .\dReg_reg[11]_52 (\dReg_reg[11]_52 ),
        .\dReg_reg[11]_53 (\dReg_reg[11]_53 ),
        .\dReg_reg[11]_54 (\dReg_reg[11]_54 ),
        .\dReg_reg[11]_55 (\dReg_reg[11]_55 ),
        .\dReg_reg[11]_56 (\dReg_reg[11]_56 ),
        .\dReg_reg[11]_57 (\dReg_reg[11]_57 ),
        .\dReg_reg[11]_58 (\dReg_reg[11]_58 ),
        .\dReg_reg[11]_59 (\dReg_reg[11]_59 ),
        .\dReg_reg[11]_6 (\dReg_reg[11]_6 ),
        .\dReg_reg[11]_60 (\dReg_reg[11]_60 ),
        .\dReg_reg[11]_61 (\dReg_reg[11]_61 ),
        .\dReg_reg[11]_62 (\dReg_reg[11]_62 ),
        .\dReg_reg[11]_63 (\dReg_reg[11]_63 ),
        .\dReg_reg[11]_64 (\dReg_reg[11]_64 ),
        .\dReg_reg[11]_65 (\dReg_reg[11]_65 ),
        .\dReg_reg[11]_66 (\dReg_reg[11]_66 ),
        .\dReg_reg[11]_67 (\dReg_reg[11]_67 ),
        .\dReg_reg[11]_68 (\dReg_reg[11]_68 ),
        .\dReg_reg[11]_69 (\dReg_reg[11]_69 ),
        .\dReg_reg[11]_7 (\dReg_reg[11]_7 ),
        .\dReg_reg[11]_70 (\dReg_reg[11]_70 ),
        .\dReg_reg[11]_8 (\dReg_reg[11]_8 ),
        .\dReg_reg[11]_9 (\dReg_reg[11]_9 ),
        .\dReg_reg[6] (\dReg_reg[6] ),
        .\dReg_reg[6]_0 (\dReg_reg[6]_0 ),
        .\dReg_reg[6]_1 (\dReg_reg[6]_1 ),
        .\dReg_reg[6]_10 (\dReg_reg[6]_10 ),
        .\dReg_reg[6]_11 (\dReg_reg[6]_11 ),
        .\dReg_reg[6]_12 (\dReg_reg[6]_12 ),
        .\dReg_reg[6]_13 (\dReg_reg[6]_13 ),
        .\dReg_reg[6]_14 (\dReg_reg[6]_14 ),
        .\dReg_reg[6]_15 (\dReg_reg[6]_15 ),
        .\dReg_reg[6]_16 (\dReg_reg[6]_16 ),
        .\dReg_reg[6]_17 (\dReg_reg[6]_17 ),
        .\dReg_reg[6]_18 (\dReg_reg[6]_18 ),
        .\dReg_reg[6]_19 (\dReg_reg[6]_19 ),
        .\dReg_reg[6]_2 (\dReg_reg[6]_2 ),
        .\dReg_reg[6]_20 (\dReg_reg[6]_20 ),
        .\dReg_reg[6]_21 (\dReg_reg[6]_21 ),
        .\dReg_reg[6]_22 (\dReg_reg[6]_22 ),
        .\dReg_reg[6]_23 (\dReg_reg[6]_23 ),
        .\dReg_reg[6]_24 (\dReg_reg[6]_24 ),
        .\dReg_reg[6]_25 (\dReg_reg[6]_25 ),
        .\dReg_reg[6]_26 (\dReg_reg[6]_26 ),
        .\dReg_reg[6]_27 (\dReg_reg[6]_27 ),
        .\dReg_reg[6]_28 (\dReg_reg[6]_28 ),
        .\dReg_reg[6]_29 (\dReg_reg[6]_29 ),
        .\dReg_reg[6]_3 (\dReg_reg[6]_3 ),
        .\dReg_reg[6]_30 (\dReg_reg[6]_30 ),
        .\dReg_reg[6]_31 (\dReg_reg[6]_31 ),
        .\dReg_reg[6]_32 (\dReg_reg[6]_32 ),
        .\dReg_reg[6]_33 (\dReg_reg[6]_33 ),
        .\dReg_reg[6]_34 (\dReg_reg[6]_34 ),
        .\dReg_reg[6]_35 (\dReg_reg[6]_35 ),
        .\dReg_reg[6]_36 (\dReg_reg[6]_36 ),
        .\dReg_reg[6]_37 (\dReg_reg[6]_37 ),
        .\dReg_reg[6]_38 (\dReg_reg[6]_38 ),
        .\dReg_reg[6]_39 (\dReg_reg[6]_39 ),
        .\dReg_reg[6]_4 (\dReg_reg[6]_4 ),
        .\dReg_reg[6]_40 (\dReg_reg[6]_40 ),
        .\dReg_reg[6]_41 (\dReg_reg[6]_41 ),
        .\dReg_reg[6]_42 (\dReg_reg[6]_42 ),
        .\dReg_reg[6]_43 (\dReg_reg[6]_43 ),
        .\dReg_reg[6]_44 (\dReg_reg[6]_44 ),
        .\dReg_reg[6]_45 (\dReg_reg[6]_45 ),
        .\dReg_reg[6]_46 (\dReg_reg[6]_46 ),
        .\dReg_reg[6]_47 (\dReg_reg[6]_47 ),
        .\dReg_reg[6]_48 (\dReg_reg[6]_48 ),
        .\dReg_reg[6]_49 (\dReg_reg[6]_49 ),
        .\dReg_reg[6]_5 (\dReg_reg[6]_5 ),
        .\dReg_reg[6]_50 (\dReg_reg[6]_50 ),
        .\dReg_reg[6]_51 (\dReg_reg[6]_51 ),
        .\dReg_reg[6]_52 (\dReg_reg[6]_52 ),
        .\dReg_reg[6]_53 (\dReg_reg[6]_53 ),
        .\dReg_reg[6]_54 (\dReg_reg[6]_54 ),
        .\dReg_reg[6]_55 (\dReg_reg[6]_55 ),
        .\dReg_reg[6]_56 (\dReg_reg[6]_56 ),
        .\dReg_reg[6]_57 (\dReg_reg[6]_57 ),
        .\dReg_reg[6]_58 (\dReg_reg[6]_58 ),
        .\dReg_reg[6]_59 (\dReg_reg[6]_59 ),
        .\dReg_reg[6]_6 (\dReg_reg[6]_6 ),
        .\dReg_reg[6]_60 (\dReg_reg[6]_60 ),
        .\dReg_reg[6]_61 (\dReg_reg[6]_61 ),
        .\dReg_reg[6]_62 (\dReg_reg[6]_62 ),
        .\dReg_reg[6]_63 (\dReg_reg[6]_63 ),
        .\dReg_reg[6]_64 (\dReg_reg[6]_64 ),
        .\dReg_reg[6]_65 (\dReg_reg[6]_65 ),
        .\dReg_reg[6]_66 (\dReg_reg[6]_66 ),
        .\dReg_reg[6]_67 (\dReg_reg[6]_67 ),
        .\dReg_reg[6]_68 (\dReg_reg[6]_68 ),
        .\dReg_reg[6]_69 (\dReg_reg[6]_69 ),
        .\dReg_reg[6]_7 (\dReg_reg[6]_7 ),
        .\dReg_reg[6]_70 (\dReg_reg[6]_70 ),
        .\dReg_reg[6]_8 (\dReg_reg[6]_8 ),
        .\dReg_reg[6]_9 (\dReg_reg[6]_9 ),
        .\dReg_reg[7] (\dReg_reg[7] ),
        .\dReg_reg[7]_0 (\dReg_reg[7]_0 ),
        .\dReg_reg[7]_1 (\dReg_reg[7]_1 ),
        .\dReg_reg[7]_10 (\dReg_reg[7]_10 ),
        .\dReg_reg[7]_11 (\dReg_reg[7]_11 ),
        .\dReg_reg[7]_12 (\dReg_reg[7]_12 ),
        .\dReg_reg[7]_13 (\dReg_reg[7]_13 ),
        .\dReg_reg[7]_14 (\dReg_reg[7]_14 ),
        .\dReg_reg[7]_15 (\dReg_reg[7]_15 ),
        .\dReg_reg[7]_16 (\dReg_reg[7]_16 ),
        .\dReg_reg[7]_17 (\dReg_reg[7]_17 ),
        .\dReg_reg[7]_18 (\dReg_reg[7]_18 ),
        .\dReg_reg[7]_19 (\dReg_reg[7]_19 ),
        .\dReg_reg[7]_2 (\dReg_reg[7]_2 ),
        .\dReg_reg[7]_20 (\dReg_reg[7]_20 ),
        .\dReg_reg[7]_21 (\dReg_reg[7]_21 ),
        .\dReg_reg[7]_22 (\dReg_reg[7]_22 ),
        .\dReg_reg[7]_23 (\dReg_reg[7]_23 ),
        .\dReg_reg[7]_24 (\dReg_reg[7]_24 ),
        .\dReg_reg[7]_25 (\dReg_reg[7]_25 ),
        .\dReg_reg[7]_26 (\dReg_reg[7]_26 ),
        .\dReg_reg[7]_27 (\dReg_reg[7]_27 ),
        .\dReg_reg[7]_28 (\dReg_reg[7]_28 ),
        .\dReg_reg[7]_29 (\dReg_reg[7]_29 ),
        .\dReg_reg[7]_3 (\dReg_reg[7]_3 ),
        .\dReg_reg[7]_30 (\dReg_reg[7]_30 ),
        .\dReg_reg[7]_31 (\dReg_reg[7]_31 ),
        .\dReg_reg[7]_32 (\dReg_reg[7]_32 ),
        .\dReg_reg[7]_33 (\dReg_reg[7]_33 ),
        .\dReg_reg[7]_34 (\dReg_reg[7]_34 ),
        .\dReg_reg[7]_35 (\dReg_reg[7]_35 ),
        .\dReg_reg[7]_36 (\dReg_reg[7]_36 ),
        .\dReg_reg[7]_37 (\dReg_reg[7]_37 ),
        .\dReg_reg[7]_38 (\dReg_reg[7]_38 ),
        .\dReg_reg[7]_39 (\dReg_reg[7]_39 ),
        .\dReg_reg[7]_4 (\dReg_reg[7]_4 ),
        .\dReg_reg[7]_40 (\dReg_reg[7]_40 ),
        .\dReg_reg[7]_41 (\dReg_reg[7]_41 ),
        .\dReg_reg[7]_42 (\dReg_reg[7]_42 ),
        .\dReg_reg[7]_43 (\dReg_reg[7]_43 ),
        .\dReg_reg[7]_44 (\dReg_reg[7]_44 ),
        .\dReg_reg[7]_45 (\dReg_reg[7]_45 ),
        .\dReg_reg[7]_46 (\dReg_reg[7]_46 ),
        .\dReg_reg[7]_47 (\dReg_reg[7]_47 ),
        .\dReg_reg[7]_48 (\dReg_reg[7]_48 ),
        .\dReg_reg[7]_49 (\dReg_reg[7]_49 ),
        .\dReg_reg[7]_5 (\dReg_reg[7]_5 ),
        .\dReg_reg[7]_50 (\dReg_reg[7]_50 ),
        .\dReg_reg[7]_51 (\dReg_reg[7]_51 ),
        .\dReg_reg[7]_52 (\dReg_reg[7]_52 ),
        .\dReg_reg[7]_53 (\dReg_reg[7]_53 ),
        .\dReg_reg[7]_54 (\dReg_reg[7]_54 ),
        .\dReg_reg[7]_55 (\dReg_reg[7]_55 ),
        .\dReg_reg[7]_56 (\dReg_reg[7]_56 ),
        .\dReg_reg[7]_57 (\dReg_reg[7]_57 ),
        .\dReg_reg[7]_58 (\dReg_reg[7]_58 ),
        .\dReg_reg[7]_59 (\dReg_reg[7]_59 ),
        .\dReg_reg[7]_6 (\dReg_reg[7]_6 ),
        .\dReg_reg[7]_60 (\dReg_reg[7]_60 ),
        .\dReg_reg[7]_61 (\dReg_reg[7]_61 ),
        .\dReg_reg[7]_62 (\dReg_reg[7]_62 ),
        .\dReg_reg[7]_63 (\dReg_reg[7]_63 ),
        .\dReg_reg[7]_64 (\dReg_reg[7]_64 ),
        .\dReg_reg[7]_65 (\dReg_reg[7]_65 ),
        .\dReg_reg[7]_66 (\dReg_reg[7]_66 ),
        .\dReg_reg[7]_67 (\dReg_reg[7]_67 ),
        .\dReg_reg[7]_68 (\dReg_reg[7]_68 ),
        .\dReg_reg[7]_69 (\dReg_reg[7]_69 ),
        .\dReg_reg[7]_7 (\dReg_reg[7]_7 ),
        .\dReg_reg[7]_70 (\dReg_reg[7]_70 ),
        .\dReg_reg[7]_8 (\dReg_reg[7]_8 ),
        .\dReg_reg[7]_9 (\dReg_reg[7]_9 ),
        .\dReg_reg[9] (\dReg_reg[9] ),
        .\dReg_reg[9]_0 (\dReg_reg[9]_7 ),
        .\dReg_reg[9]_1 (\dReg_reg[9]_8 ),
        .\dReg_reg[9]_10 (\dReg_reg[9]_16 ),
        .\dReg_reg[9]_11 (\dReg_reg[9]_17 ),
        .\dReg_reg[9]_12 (\dReg_reg[9]_18 ),
        .\dReg_reg[9]_13 (\dReg_reg[9]_19 ),
        .\dReg_reg[9]_14 (\dReg_reg[9]_20 ),
        .\dReg_reg[9]_15 (\dReg_reg[9]_21 ),
        .\dReg_reg[9]_16 (\dReg_reg[9]_22 ),
        .\dReg_reg[9]_17 (\dReg_reg[9]_1 ),
        .\dReg_reg[9]_18 (\dReg_reg[9]_23 ),
        .\dReg_reg[9]_19 (\dReg_reg[9]_24 ),
        .\dReg_reg[9]_2 (\dReg_reg[9]_9 ),
        .\dReg_reg[9]_20 (\dReg_reg[9]_25 ),
        .\dReg_reg[9]_21 (\dReg_reg[9]_26 ),
        .\dReg_reg[9]_22 (\dReg_reg[9]_27 ),
        .\dReg_reg[9]_23 (\dReg_reg[9]_28 ),
        .\dReg_reg[9]_24 (\dReg_reg[9]_29 ),
        .\dReg_reg[9]_25 (\dReg_reg[9]_30 ),
        .\dReg_reg[9]_26 (\dReg_reg[9]_2 ),
        .\dReg_reg[9]_27 (\dReg_reg[9]_31 ),
        .\dReg_reg[9]_28 (\dReg_reg[9]_32 ),
        .\dReg_reg[9]_29 (\dReg_reg[9]_33 ),
        .\dReg_reg[9]_3 (\dReg_reg[9]_10 ),
        .\dReg_reg[9]_30 (\dReg_reg[9]_34 ),
        .\dReg_reg[9]_31 (\dReg_reg[9]_35 ),
        .\dReg_reg[9]_32 (\dReg_reg[9]_36 ),
        .\dReg_reg[9]_33 (\dReg_reg[9]_37 ),
        .\dReg_reg[9]_34 (\dReg_reg[9]_38 ),
        .\dReg_reg[9]_35 (\dReg_reg[9]_3 ),
        .\dReg_reg[9]_36 (\dReg_reg[9]_39 ),
        .\dReg_reg[9]_37 (\dReg_reg[9]_40 ),
        .\dReg_reg[9]_38 (\dReg_reg[9]_41 ),
        .\dReg_reg[9]_39 (\dReg_reg[9]_42 ),
        .\dReg_reg[9]_4 (\dReg_reg[9]_11 ),
        .\dReg_reg[9]_40 (\dReg_reg[9]_43 ),
        .\dReg_reg[9]_41 (\dReg_reg[9]_44 ),
        .\dReg_reg[9]_42 (\dReg_reg[9]_45 ),
        .\dReg_reg[9]_43 (\dReg_reg[9]_46 ),
        .\dReg_reg[9]_44 (\dReg_reg[9]_4 ),
        .\dReg_reg[9]_45 (\dReg_reg[9]_47 ),
        .\dReg_reg[9]_46 (\dReg_reg[9]_48 ),
        .\dReg_reg[9]_47 (\dReg_reg[9]_49 ),
        .\dReg_reg[9]_48 (\dReg_reg[9]_50 ),
        .\dReg_reg[9]_49 (\dReg_reg[9]_51 ),
        .\dReg_reg[9]_5 (\dReg_reg[9]_12 ),
        .\dReg_reg[9]_50 (\dReg_reg[9]_52 ),
        .\dReg_reg[9]_51 (\dReg_reg[9]_53 ),
        .\dReg_reg[9]_52 (\dReg_reg[9]_54 ),
        .\dReg_reg[9]_53 (\dReg_reg[9]_5 ),
        .\dReg_reg[9]_54 (\dReg_reg[9]_55 ),
        .\dReg_reg[9]_55 (\dReg_reg[9]_56 ),
        .\dReg_reg[9]_56 (\dReg_reg[9]_57 ),
        .\dReg_reg[9]_57 (\dReg_reg[9]_58 ),
        .\dReg_reg[9]_58 (\dReg_reg[9]_59 ),
        .\dReg_reg[9]_59 (\dReg_reg[9]_60 ),
        .\dReg_reg[9]_6 (\dReg_reg[9]_13 ),
        .\dReg_reg[9]_60 (\dReg_reg[9]_61 ),
        .\dReg_reg[9]_61 (\dReg_reg[9]_62 ),
        .\dReg_reg[9]_62 (\dReg_reg[9]_6 ),
        .\dReg_reg[9]_63 (\dReg_reg[9]_63 ),
        .\dReg_reg[9]_64 (\dReg_reg[9]_64 ),
        .\dReg_reg[9]_65 (\dReg_reg[9]_65 ),
        .\dReg_reg[9]_66 (\dReg_reg[9]_66 ),
        .\dReg_reg[9]_67 (\dReg_reg[9]_67 ),
        .\dReg_reg[9]_68 (\dReg_reg[9]_68 ),
        .\dReg_reg[9]_69 (\dReg_reg[9]_69 ),
        .\dReg_reg[9]_7 (\dReg_reg[9]_14 ),
        .\dReg_reg[9]_70 (\dReg_reg[9]_70 ),
        .\dReg_reg[9]_8 (\dReg_reg[9]_0 ),
        .\dReg_reg[9]_9 (\dReg_reg[9]_15 ),
        .mcCasSlot2(mcCasSlot2),
        .mcWrCAS(mcWrCAS),
        .\oe_0_mux_cal_reg[0]_0 (\oe_0_mux_cal_reg[0] ),
        .\oe_0_mux_cal_reg[0]_1 (\oe_0_mux_cal_reg[0]_0 ),
        .\oe_low_reg[3]_0 (\oe_low_reg[3] ),
        .\oe_low_reg[5]_0 (\oe_low_reg[5] ),
        .\oe_upp_reg[3]_0 (\oe_upp_reg[3] ),
        .out(rst_r1),
        .pointer_we(pointer_we),
        .\rams[1].RAM32M0 (\rams[1].RAM32M0 ),
        .\wosp_reg[1] (wosp[1]),
        .\wosp_reg[2] (wosp[2]),
        .\wosp_reg[2]_rep (\wosp_reg[2]_rep ),
        .\wosp_reg[2]_rep__0 (\wosp_reg[2]_rep__0 ),
        .\wosp_reg[2]_rep__1 (\wosp_reg[2]_rep__1 ),
        .\wosp_reg[2]_rep__2 (\wosp_reg[2]_rep__2 ),
        .\wosp_reg[2]_rep__3 (\wosp_reg[2]_rep__3 ),
        .\wosp_reg[2]_rep__4 (\wosp_reg[2]_rep__4 ),
        .\wosp_reg[2]_rep__5 (\wosp_reg[2]_rep__5 ),
        .\wosp_reg[2]_rep__6 (\wosp_reg[2]_rep__6 ),
        .\wosp_reg[2]_rep__7 (\wosp_reg[2]_rep__7 ),
        .wrDataVal_reg_0(wrDataVal),
        .\wrQ_nxt[1]_13 (\wrQ_nxt[1]_13 ),
        .\wrQ_reg[0][0]_0 (wrDataEn_pi),
        .\wrQ_reg[0][0]_1 (\wrQ_reg[0][0] ),
        .\wrQ_reg[0][0]_rep_0 (\wrQ_reg[0][0]_rep ),
        .\wrQ_reg[0][2]_0 (\wrQ_reg[0][2] ),
        .\wrQ_reg[0][5]_rep_0 (\wrQ_reg[0][5]_rep ),
        .\wrQ_reg[0][5]_rep__0_0 (\wrQ_reg[0][5]_rep__0 ),
        .\wrQ_reg[0][5]_rep__1_0 (\wrQ_reg[0][5]_rep__1 ),
        .\wrQ_reg[0][6]_rep_0 (\wrQ_reg[0][6]_rep ),
        .\wrQ_reg[0][6]_rep__0_0 (\wrQ_reg[0][6]_rep__0 ),
        .\wrQ_reg[0][6]_rep__1_0 (\wrQ_reg[0][6]_rep__1 ),
        .\wrQ_reg[0][7]_rep_0 (\wrQ_reg[0][7]_rep ),
        .\wrQ_reg[0][7]_rep__0_0 (\wrQ_reg[0][7]_rep__0 ),
        .\wrQ_reg[0][7]_rep__1_0 (\wrQ_reg[0][7]_rep__1 ),
        .\wrQ_reg[0][8]_0 (\wrQ_reg[0][8] ),
        .\wrQ_reg[0][8]_rep_0 (\wrQ_reg[0][8]_rep ),
        .\wrQ_reg[0][8]_rep__0_0 (\wrQ_reg[0][8]_rep__0 ),
        .\wrQ_reg[0][8]_rep__0_1 (\wrQ_reg[0][8]_rep__0_0 ),
        .\wrQ_reg[0][8]_rep__1_0 (\wrQ_reg[0][8]_rep__1 ),
        .\wrQ_reg[0][8]_rep__1_1 (\wrQ_reg[0][8]_rep__1_0 ),
        .\wrQ_reg[1][8]_0 (\wrQ_reg[1][8] ),
        .\wrQ_reg[1][8]_1 (\wrQ_reg[1][8]_0 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_low,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_26,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_27 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_2 ,
    mcalRdCAS,
    mcalCasSlot,
    out,
    mcalRank,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_low;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_26;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_27 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_1 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_2 ;
  input mcalRdCAS;
  input [0:0]mcalCasSlot;
  input out;
  input [1:0]mcalRank;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_27 ;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [0:0]mcalCasSlot;
  wire [1:0]mcalRank;
  wire mcalRdCAS;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_33__12_n_0;
  wire rdEn_nxt_inferred_i_34__14_n_0;
  wire rdEn_nxt_inferred_i_35__14_n_0;
  wire rdEn_nxt_inferred_i_36__14_n_0;
  wire rdEn_nxt_inferred_i_37__14_n_0;
  wire rdEn_nxt_inferred_i_38__14_n_0;
  wire rdEn_nxt_inferred_i_39__14_n_0;
  wire rdEn_nxt_inferred_i_40__14_n_0;
  wire rdEn_nxt_inferred_i_41__14_n_0;
  wire rdEn_nxt_inferred_i_42__14_n_0;
  wire rdEn_nxt_inferred_i_43__14_n_0;
  wire rdEn_nxt_inferred_i_44__14_n_0;
  wire rdEn_nxt_inferred_i_45__14_n_0;
  wire rdEn_nxt_inferred_i_46__14_n_0;
  wire rdEn_nxt_inferred_i_47__14_n_0;
  wire rdEn_nxt_inferred_i_48__14_n_0;
  wire rdEn_nxt_inferred_i_49__14_n_0;
  wire rdEn_nxt_inferred_i_50__14_n_0;
  wire rdEn_nxt_inferred_i_51__14_n_0;
  wire rdEn_nxt_inferred_i_52__14_n_0;
  wire [4:0]rs2mask0_26;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_158 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_159 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_160 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_161 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_162 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_163 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_164 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire \rsMask_reg[7][9]_2 ;
  wire [18:1]\rsMask_reg[7]_165 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__14
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_41__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_42__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__14
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_40__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_43__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__14
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_42__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_44__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__14
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_43__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_45__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__14
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_44__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_46__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__14
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_45__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_47__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__14
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_48__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_49__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__14
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_50__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_51__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__14
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_49__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_52__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__14
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_51__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_52__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__14
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__14
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__14
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__14
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__14
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__14
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__14
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__14
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__14
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__14
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__14
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_31__11
       (.I0(\rsMask_reg[7]_165 [18]),
        .I1(\rsMask_reg[5]_163 [18]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [18]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_32__10
       (.I0(\rsMask_reg[7]_165 [17]),
        .I1(\rsMask_reg[5]_163 [17]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [17]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_33__12
       (.I0(\rsMask_reg[7]_165 [16]),
        .I1(\rsMask_reg[5]_163 [16]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [16]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [16]),
        .O(rdEn_nxt_inferred_i_33__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__14
       (.I0(\rsMask_reg[7]_165 [15]),
        .I1(\rsMask_reg[5]_163 [15]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [15]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [15]),
        .O(rdEn_nxt_inferred_i_34__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__14
       (.I0(\rsMask_reg[7]_165 [14]),
        .I1(\rsMask_reg[5]_163 [14]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [14]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [14]),
        .O(rdEn_nxt_inferred_i_35__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__14
       (.I0(\rsMask_reg[7]_165 [13]),
        .I1(\rsMask_reg[5]_163 [13]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [13]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [13]),
        .O(rdEn_nxt_inferred_i_36__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__14
       (.I0(\rsMask_reg[7]_165 [12]),
        .I1(\rsMask_reg[5]_163 [12]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [12]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [12]),
        .O(rdEn_nxt_inferred_i_37__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__14
       (.I0(\rsMask_reg[6]_164 [11]),
        .I1(\rsMask_reg[4]_162 [11]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_160 [11]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_158 [11]),
        .O(rdEn_nxt_inferred_i_38__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__14
       (.I0(\rsMask_reg[7]_165 [11]),
        .I1(\rsMask_reg[5]_163 [11]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [11]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [11]),
        .O(rdEn_nxt_inferred_i_39__14_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__14
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_33__12_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__14
       (.I0(\rsMask_reg[7]_165 [10]),
        .I1(\rsMask_reg[5]_163 [10]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [10]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [10]),
        .O(rdEn_nxt_inferred_i_40__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__14
       (.I0(\rsMask_reg[6]_164 [9]),
        .I1(\rsMask_reg[4]_162 [9]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_160 [9]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_158 [9]),
        .O(rdEn_nxt_inferred_i_41__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__14
       (.I0(\rsMask_reg[7]_165 [9]),
        .I1(\rsMask_reg[5]_163 [9]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [9]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [9]),
        .O(rdEn_nxt_inferred_i_42__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__14
       (.I0(\rsMask_reg[7]_165 [8]),
        .I1(\rsMask_reg[5]_163 [8]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [8]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [8]),
        .O(rdEn_nxt_inferred_i_43__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__14
       (.I0(\rsMask_reg[7]_165 [7]),
        .I1(\rsMask_reg[5]_163 [7]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [7]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [7]),
        .O(rdEn_nxt_inferred_i_44__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__14
       (.I0(\rsMask_reg[7]_165 [6]),
        .I1(\rsMask_reg[5]_163 [6]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [6]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [6]),
        .O(rdEn_nxt_inferred_i_45__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__14
       (.I0(\rsMask_reg[7]_165 [5]),
        .I1(\rsMask_reg[5]_163 [5]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [5]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [5]),
        .O(rdEn_nxt_inferred_i_46__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__14
       (.I0(\rsMask_reg[7]_165 [4]),
        .I1(\rsMask_reg[5]_163 [4]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [4]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [4]),
        .O(rdEn_nxt_inferred_i_47__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__14
       (.I0(\rsMask_reg[6]_164 [3]),
        .I1(\rsMask_reg[4]_162 [3]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_160 [3]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_158 [3]),
        .O(rdEn_nxt_inferred_i_48__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__14
       (.I0(\rsMask_reg[7]_165 [3]),
        .I1(\rsMask_reg[5]_163 [3]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [3]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [3]),
        .O(rdEn_nxt_inferred_i_49__14_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__14
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_34__14_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__14
       (.I0(\rsMask_reg[6]_164 [2]),
        .I1(\rsMask_reg[4]_162 [2]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_160 [2]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_158 [2]),
        .O(rdEn_nxt_inferred_i_50__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__14
       (.I0(\rsMask_reg[7]_165 [2]),
        .I1(\rsMask_reg[5]_163 [2]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [2]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [2]),
        .O(rdEn_nxt_inferred_i_51__14_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__14
       (.I0(\rsMask_reg[7]_165 [1]),
        .I1(\rsMask_reg[5]_163 [1]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_161 [1]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_159 [1]),
        .O(rdEn_nxt_inferred_i_52__14_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__14
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_33__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_35__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__14
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_34__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_36__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__14
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_35__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_37__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__14
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_38__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_39__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__14
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_37__14_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_40__14_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_low[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_low[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_low[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_low[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_158 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_158 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_158 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_158 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_26[2]),
        .Q(\rsMask_reg[1]_159 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_26[3]),
        .Q(\rsMask_reg[1]_159 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_26[4]),
        .Q(\rsMask_reg[1]_159 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_159 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_159 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_159 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_159 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_159 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_159 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_159 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_26[0]),
        .Q(\rsMask_reg[1]_159 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_26[1]),
        .Q(\rsMask_reg[1]_159 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_159 [4]),
        .R(\blk1.(null)[0].diff_27 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_159 [5]),
        .R(\blk1.(null)[0].diff_27 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_159 [6]),
        .R(\blk1.(null)[0].diff_27 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_159 [7]),
        .R(\blk1.(null)[0].diff_27 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_159 [8]),
        .R(\blk1.(null)[0].diff_27 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_27 [0]),
        .Q(\rsMask_reg[1]_159 [9]),
        .R(\blk1.(null)[0].diff_27 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_160 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_160 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_160 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_160 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_161 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_161 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_161 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_161 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_161 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_161 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_161 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_161 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_161 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_161 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_161 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_161 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_161 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_161 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_161 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_161 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_161 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_161 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_162 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_162 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_162 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_162 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_163 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_163 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_163 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_163 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_163 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_163 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_163 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_163 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_163 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_163 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_163 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_163 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_163 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_163 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_163 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_163 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_163 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_163 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_164 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_164 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_164 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_164 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_165 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_165 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_165 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_165 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_165 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_165 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_165 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_165 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_165 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_165 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_165 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_165 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_165 [4]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_165 [5]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_165 [6]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_165 [7]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_165 [8]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_2 ),
        .Q(\rsMask_reg[7]_165 [9]),
        .R(\rsMask_reg[7][9]_1 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_12
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_upp,
    phy_rden_or,
    phy_rden_and,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_10,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_11 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_2 ,
    \rdEn_reg[12]_0 ,
    \rdEn_reg[12]_1 ,
    out,
    \rdEn_reg[14]_0 ,
    \rdEn_reg[14]_1 ,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_upp;
  output phy_rden_or;
  output phy_rden_and;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_10;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_11 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_1 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_2 ;
  input \rdEn_reg[12]_0 ;
  input \rdEn_reg[12]_1 ;
  input out;
  input \rdEn_reg[14]_0 ;
  input \rdEn_reg[14]_1 ;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_11 ;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire out;
  wire phy_rden_and;
  wire phy_rden_or;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_33__5_n_0;
  wire rdEn_nxt_inferred_i_34__6_n_0;
  wire rdEn_nxt_inferred_i_35__6_n_0;
  wire rdEn_nxt_inferred_i_36__6_n_0;
  wire rdEn_nxt_inferred_i_37__6_n_0;
  wire rdEn_nxt_inferred_i_38__6_n_0;
  wire rdEn_nxt_inferred_i_39__6_n_0;
  wire rdEn_nxt_inferred_i_40__6_n_0;
  wire rdEn_nxt_inferred_i_41__6_n_0;
  wire rdEn_nxt_inferred_i_42__6_n_0;
  wire rdEn_nxt_inferred_i_43__6_n_0;
  wire rdEn_nxt_inferred_i_44__6_n_0;
  wire rdEn_nxt_inferred_i_45__6_n_0;
  wire rdEn_nxt_inferred_i_46__6_n_0;
  wire rdEn_nxt_inferred_i_47__6_n_0;
  wire rdEn_nxt_inferred_i_48__6_n_0;
  wire rdEn_nxt_inferred_i_49__6_n_0;
  wire rdEn_nxt_inferred_i_50__6_n_0;
  wire rdEn_nxt_inferred_i_51__6_n_0;
  wire rdEn_nxt_inferred_i_52__6_n_0;
  wire \rdEn_reg[12]_0 ;
  wire \rdEn_reg[12]_1 ;
  wire \rdEn_reg[14]_0 ;
  wire \rdEn_reg[14]_1 ;
  wire [4:0]rs2mask0_10;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_94 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_95 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_96 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_97 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_98 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_99 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_100 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire \rsMask_reg[7][9]_2 ;
  wire [18:1]\rsMask_reg[7]_101 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  (* SOFT_HLUTNM = "soft_lutpair2220" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \phy_rden_and_stg_reg[2]_srl3_i_1 
       (.I0(ch0_mcal_clb2phy_rden_upp[1]),
        .I1(ch0_mcal_clb2phy_rden_upp[0]),
        .I2(ch0_mcal_clb2phy_rden_upp[3]),
        .I3(ch0_mcal_clb2phy_rden_upp[2]),
        .O(phy_rden_and));
  (* SOFT_HLUTNM = "soft_lutpair2220" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \phy_rden_or_stg_reg[2]_srl3_i_1 
       (.I0(ch0_mcal_clb2phy_rden_upp[1]),
        .I1(ch0_mcal_clb2phy_rden_upp[0]),
        .I2(ch0_mcal_clb2phy_rden_upp[3]),
        .I3(ch0_mcal_clb2phy_rden_upp[2]),
        .O(phy_rden_or));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__6
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_41__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_42__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__6
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_40__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_43__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__6
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_42__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_44__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__6
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_43__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_45__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__6
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_44__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_46__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__6
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_45__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_47__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__6
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_48__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_49__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__6
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_50__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_51__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__6
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_49__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_52__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__6
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_51__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_52__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__6
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__6
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__6
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__6
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__6
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__6
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__6
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__6
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__6
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__6
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__6
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_31__4
       (.I0(\rsMask_reg[7]_101 [18]),
        .I1(\rsMask_reg[5]_99 [18]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [18]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_32__2
       (.I0(\rsMask_reg[7]_101 [17]),
        .I1(\rsMask_reg[5]_99 [17]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [17]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_33__5
       (.I0(\rsMask_reg[7]_101 [16]),
        .I1(\rsMask_reg[5]_99 [16]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [16]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [16]),
        .O(rdEn_nxt_inferred_i_33__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__6
       (.I0(\rsMask_reg[7]_101 [15]),
        .I1(\rsMask_reg[5]_99 [15]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [15]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [15]),
        .O(rdEn_nxt_inferred_i_34__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__6
       (.I0(\rsMask_reg[7]_101 [14]),
        .I1(\rsMask_reg[5]_99 [14]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [14]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [14]),
        .O(rdEn_nxt_inferred_i_35__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__6
       (.I0(\rsMask_reg[7]_101 [13]),
        .I1(\rsMask_reg[5]_99 [13]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [13]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [13]),
        .O(rdEn_nxt_inferred_i_36__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__6
       (.I0(\rsMask_reg[7]_101 [12]),
        .I1(\rsMask_reg[5]_99 [12]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [12]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [12]),
        .O(rdEn_nxt_inferred_i_37__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__6
       (.I0(\rsMask_reg[6]_100 [11]),
        .I1(\rsMask_reg[4]_98 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_96 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_94 [11]),
        .O(rdEn_nxt_inferred_i_38__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__6
       (.I0(\rsMask_reg[7]_101 [11]),
        .I1(\rsMask_reg[5]_99 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [11]),
        .O(rdEn_nxt_inferred_i_39__6_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__6
       (.I0(\rdEn_reg[12]_0 ),
        .I1(rdEn_nxt_inferred_i_33__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__6
       (.I0(\rsMask_reg[7]_101 [10]),
        .I1(\rsMask_reg[5]_99 [10]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [10]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [10]),
        .O(rdEn_nxt_inferred_i_40__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__6
       (.I0(\rsMask_reg[6]_100 [9]),
        .I1(\rsMask_reg[4]_98 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_96 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_94 [9]),
        .O(rdEn_nxt_inferred_i_41__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__6
       (.I0(\rsMask_reg[7]_101 [9]),
        .I1(\rsMask_reg[5]_99 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [9]),
        .O(rdEn_nxt_inferred_i_42__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__6
       (.I0(\rsMask_reg[7]_101 [8]),
        .I1(\rsMask_reg[5]_99 [8]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [8]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [8]),
        .O(rdEn_nxt_inferred_i_43__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__6
       (.I0(\rsMask_reg[7]_101 [7]),
        .I1(\rsMask_reg[5]_99 [7]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [7]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [7]),
        .O(rdEn_nxt_inferred_i_44__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__6
       (.I0(\rsMask_reg[7]_101 [6]),
        .I1(\rsMask_reg[5]_99 [6]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [6]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [6]),
        .O(rdEn_nxt_inferred_i_45__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__6
       (.I0(\rsMask_reg[7]_101 [5]),
        .I1(\rsMask_reg[5]_99 [5]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [5]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [5]),
        .O(rdEn_nxt_inferred_i_46__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__6
       (.I0(\rsMask_reg[7]_101 [4]),
        .I1(\rsMask_reg[5]_99 [4]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [4]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [4]),
        .O(rdEn_nxt_inferred_i_47__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__6
       (.I0(\rsMask_reg[6]_100 [3]),
        .I1(\rsMask_reg[4]_98 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_96 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_94 [3]),
        .O(rdEn_nxt_inferred_i_48__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__6
       (.I0(\rsMask_reg[7]_101 [3]),
        .I1(\rsMask_reg[5]_99 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [3]),
        .O(rdEn_nxt_inferred_i_49__6_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__6
       (.I0(\rdEn_reg[12]_0 ),
        .I1(rdEn_nxt_inferred_i_34__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__6
       (.I0(\rsMask_reg[6]_100 [2]),
        .I1(\rsMask_reg[4]_98 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_96 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_94 [2]),
        .O(rdEn_nxt_inferred_i_50__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__6
       (.I0(\rsMask_reg[7]_101 [2]),
        .I1(\rsMask_reg[5]_99 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [2]),
        .O(rdEn_nxt_inferred_i_51__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__6
       (.I0(\rsMask_reg[7]_101 [1]),
        .I1(\rsMask_reg[5]_99 [1]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_97 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_95 [1]),
        .O(rdEn_nxt_inferred_i_52__6_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__6
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_33__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_35__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__6
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_34__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_36__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__6
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_35__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_37__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__6
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_38__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_39__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__6
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_37__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_40__6_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_upp[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_upp[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_upp[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_upp[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_94 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_94 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_94 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_94 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_10[2]),
        .Q(\rsMask_reg[1]_95 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_10[3]),
        .Q(\rsMask_reg[1]_95 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_10[4]),
        .Q(\rsMask_reg[1]_95 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_95 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_95 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_95 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_95 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_95 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_95 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_95 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_10[0]),
        .Q(\rsMask_reg[1]_95 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_10[1]),
        .Q(\rsMask_reg[1]_95 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_95 [4]),
        .R(\blk1.(null)[0].diff_11 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_95 [5]),
        .R(\blk1.(null)[0].diff_11 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_95 [6]),
        .R(\blk1.(null)[0].diff_11 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_95 [7]),
        .R(\blk1.(null)[0].diff_11 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_95 [8]),
        .R(\blk1.(null)[0].diff_11 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_11 [0]),
        .Q(\rsMask_reg[1]_95 [9]),
        .R(\blk1.(null)[0].diff_11 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_96 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_96 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_96 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_96 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_97 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_97 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_97 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_97 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_97 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_97 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_97 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_97 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_97 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_97 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_97 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_97 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_97 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_97 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_97 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_97 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_97 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_97 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_98 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_98 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_98 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_98 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_99 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_99 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_99 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_99 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_99 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_99 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_99 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_99 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_99 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_99 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_99 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_99 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_99 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_99 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_99 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_99 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_99 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_99 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_100 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_100 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_100 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_100 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_101 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_101 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_101 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_101 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_101 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_101 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_101 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_101 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_101 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_101 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_101 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_101 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_101 [4]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_101 [5]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_101 [6]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_101 [7]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_101 [8]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_2 ),
        .Q(\rsMask_reg[7]_101 [9]),
        .R(\rsMask_reg[7][9]_1 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_13
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_low,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_24,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_25 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_2 ,
    mcalRdCAS,
    mcalCasSlot,
    out,
    mcalRank,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_low;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_24;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_25 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_1 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_2 ;
  input mcalRdCAS;
  input [0:0]mcalCasSlot;
  input out;
  input [1:0]mcalRank;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_25 ;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [0:0]mcalCasSlot;
  wire [1:0]mcalRank;
  wire mcalRdCAS;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_33__11_n_0;
  wire rdEn_nxt_inferred_i_34__13_n_0;
  wire rdEn_nxt_inferred_i_35__13_n_0;
  wire rdEn_nxt_inferred_i_36__13_n_0;
  wire rdEn_nxt_inferred_i_37__13_n_0;
  wire rdEn_nxt_inferred_i_38__13_n_0;
  wire rdEn_nxt_inferred_i_39__13_n_0;
  wire rdEn_nxt_inferred_i_40__13_n_0;
  wire rdEn_nxt_inferred_i_41__13_n_0;
  wire rdEn_nxt_inferred_i_42__13_n_0;
  wire rdEn_nxt_inferred_i_43__13_n_0;
  wire rdEn_nxt_inferred_i_44__13_n_0;
  wire rdEn_nxt_inferred_i_45__13_n_0;
  wire rdEn_nxt_inferred_i_46__13_n_0;
  wire rdEn_nxt_inferred_i_47__13_n_0;
  wire rdEn_nxt_inferred_i_48__13_n_0;
  wire rdEn_nxt_inferred_i_49__13_n_0;
  wire rdEn_nxt_inferred_i_50__13_n_0;
  wire rdEn_nxt_inferred_i_51__13_n_0;
  wire rdEn_nxt_inferred_i_52__13_n_0;
  wire [4:0]rs2mask0_24;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_150 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_151 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_152 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_153 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_154 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_155 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_156 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire \rsMask_reg[7][9]_2 ;
  wire [18:1]\rsMask_reg[7]_157 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__13
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_41__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_42__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__13
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_40__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_43__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__13
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_42__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_44__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__13
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_43__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_45__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__13
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_44__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_46__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__13
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_45__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_47__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__13
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_48__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_49__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__13
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_50__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_51__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__13
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_49__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_52__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__13
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_51__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_52__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__13
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__13
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__13
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__13
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__13
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__13
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__13
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__13
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__13
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__13
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__13
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_31__10
       (.I0(\rsMask_reg[7]_157 [18]),
        .I1(\rsMask_reg[5]_155 [18]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [18]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_32__9
       (.I0(\rsMask_reg[7]_157 [17]),
        .I1(\rsMask_reg[5]_155 [17]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [17]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_33__11
       (.I0(\rsMask_reg[7]_157 [16]),
        .I1(\rsMask_reg[5]_155 [16]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [16]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [16]),
        .O(rdEn_nxt_inferred_i_33__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__13
       (.I0(\rsMask_reg[7]_157 [15]),
        .I1(\rsMask_reg[5]_155 [15]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [15]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [15]),
        .O(rdEn_nxt_inferred_i_34__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__13
       (.I0(\rsMask_reg[7]_157 [14]),
        .I1(\rsMask_reg[5]_155 [14]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [14]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [14]),
        .O(rdEn_nxt_inferred_i_35__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__13
       (.I0(\rsMask_reg[7]_157 [13]),
        .I1(\rsMask_reg[5]_155 [13]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [13]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [13]),
        .O(rdEn_nxt_inferred_i_36__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__13
       (.I0(\rsMask_reg[7]_157 [12]),
        .I1(\rsMask_reg[5]_155 [12]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [12]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [12]),
        .O(rdEn_nxt_inferred_i_37__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__13
       (.I0(\rsMask_reg[6]_156 [11]),
        .I1(\rsMask_reg[4]_154 [11]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_152 [11]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_150 [11]),
        .O(rdEn_nxt_inferred_i_38__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__13
       (.I0(\rsMask_reg[7]_157 [11]),
        .I1(\rsMask_reg[5]_155 [11]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [11]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [11]),
        .O(rdEn_nxt_inferred_i_39__13_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__13
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_33__11_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__13
       (.I0(\rsMask_reg[7]_157 [10]),
        .I1(\rsMask_reg[5]_155 [10]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [10]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [10]),
        .O(rdEn_nxt_inferred_i_40__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__13
       (.I0(\rsMask_reg[6]_156 [9]),
        .I1(\rsMask_reg[4]_154 [9]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_152 [9]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_150 [9]),
        .O(rdEn_nxt_inferred_i_41__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__13
       (.I0(\rsMask_reg[7]_157 [9]),
        .I1(\rsMask_reg[5]_155 [9]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [9]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [9]),
        .O(rdEn_nxt_inferred_i_42__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__13
       (.I0(\rsMask_reg[7]_157 [8]),
        .I1(\rsMask_reg[5]_155 [8]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [8]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [8]),
        .O(rdEn_nxt_inferred_i_43__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__13
       (.I0(\rsMask_reg[7]_157 [7]),
        .I1(\rsMask_reg[5]_155 [7]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [7]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [7]),
        .O(rdEn_nxt_inferred_i_44__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__13
       (.I0(\rsMask_reg[7]_157 [6]),
        .I1(\rsMask_reg[5]_155 [6]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [6]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [6]),
        .O(rdEn_nxt_inferred_i_45__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__13
       (.I0(\rsMask_reg[7]_157 [5]),
        .I1(\rsMask_reg[5]_155 [5]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [5]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [5]),
        .O(rdEn_nxt_inferred_i_46__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__13
       (.I0(\rsMask_reg[7]_157 [4]),
        .I1(\rsMask_reg[5]_155 [4]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [4]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [4]),
        .O(rdEn_nxt_inferred_i_47__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__13
       (.I0(\rsMask_reg[6]_156 [3]),
        .I1(\rsMask_reg[4]_154 [3]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_152 [3]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_150 [3]),
        .O(rdEn_nxt_inferred_i_48__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__13
       (.I0(\rsMask_reg[7]_157 [3]),
        .I1(\rsMask_reg[5]_155 [3]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [3]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [3]),
        .O(rdEn_nxt_inferred_i_49__13_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__13
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_34__13_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__13
       (.I0(\rsMask_reg[6]_156 [2]),
        .I1(\rsMask_reg[4]_154 [2]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_152 [2]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_150 [2]),
        .O(rdEn_nxt_inferred_i_50__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__13
       (.I0(\rsMask_reg[7]_157 [2]),
        .I1(\rsMask_reg[5]_155 [2]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [2]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [2]),
        .O(rdEn_nxt_inferred_i_51__13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__13
       (.I0(\rsMask_reg[7]_157 [1]),
        .I1(\rsMask_reg[5]_155 [1]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_153 [1]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_151 [1]),
        .O(rdEn_nxt_inferred_i_52__13_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__13
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_33__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_35__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__13
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_34__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_36__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__13
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_35__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_37__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__13
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_38__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_39__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__13
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_37__13_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_40__13_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_low[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_low[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_low[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_low[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_150 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_150 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_150 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_150 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_24[2]),
        .Q(\rsMask_reg[1]_151 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_24[3]),
        .Q(\rsMask_reg[1]_151 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_24[4]),
        .Q(\rsMask_reg[1]_151 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_151 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_151 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_151 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_151 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_151 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_151 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_151 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_24[0]),
        .Q(\rsMask_reg[1]_151 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_24[1]),
        .Q(\rsMask_reg[1]_151 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_151 [4]),
        .R(\blk1.(null)[0].diff_25 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_151 [5]),
        .R(\blk1.(null)[0].diff_25 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_151 [6]),
        .R(\blk1.(null)[0].diff_25 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_151 [7]),
        .R(\blk1.(null)[0].diff_25 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_151 [8]),
        .R(\blk1.(null)[0].diff_25 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_25 [0]),
        .Q(\rsMask_reg[1]_151 [9]),
        .R(\blk1.(null)[0].diff_25 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_152 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_152 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_152 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_152 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_153 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_153 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_153 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_153 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_153 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_153 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_153 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_153 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_153 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_153 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_153 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_153 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_153 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_153 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_153 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_153 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_153 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_153 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_154 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_154 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_154 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_154 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_155 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_155 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_155 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_155 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_155 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_155 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_155 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_155 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_155 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_155 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_155 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_155 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_155 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_155 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_155 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_155 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_155 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_155 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_156 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_156 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_156 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_156 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_157 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_157 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_157 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_157 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_157 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_157 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_157 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_157 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_157 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_157 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_157 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_157 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_157 [4]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_157 [5]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_157 [6]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_157 [7]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_157 [8]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_2 ),
        .Q(\rsMask_reg[7]_157 [9]),
        .R(\rsMask_reg[7][9]_1 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_14
   (\rsMask_reg[1][18]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[7][18]_0 ,
    ch0_mcal_clb2phy_rden_upp,
    in0,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    \rsMask_reg[1][12]_0 ,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_1 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_2 ,
    \blk1.(null)[0].diff ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_2 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_2 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_0 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[1][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    out,
    \rdEn_reg[12]_0 ,
    \rdEn_reg[12]_1 ,
    \rdEn_reg[14]_0 ,
    \rdEn_reg[14]_1 ,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_1 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output [1:0]\rsMask_reg[1][18]_0 ;
  output [1:0]\rsMask_reg[3][18]_0 ;
  output [1:0]\rsMask_reg[5][18]_0 ;
  output [1:0]\rsMask_reg[7][18]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_upp;
  input [1:0]in0;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[6][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [3:0]\rsMask_reg[1][12]_0 ;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_2 ;
  input [1:0]\blk1.(null)[0].diff ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_2 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_2 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_0 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_1 ;
  input [2:0]\rsMask_reg[1][11]_0 ;
  input [2:0]\rsMask_reg[3][11]_0 ;
  input [2:0]\rsMask_reg[5][11]_0 ;
  input [2:0]\rsMask_reg[7][11]_0 ;
  input out;
  input \rdEn_reg[12]_0 ;
  input \rdEn_reg[12]_1 ;
  input \rdEn_reg[14]_0 ;
  input \rdEn_reg[14]_1 ;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_1 ;
  input \rsMask_reg[6][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff ;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_36__3_n_0;
  wire rdEn_nxt_inferred_i_37__3_n_0;
  wire rdEn_nxt_inferred_i_38__3_n_0;
  wire rdEn_nxt_inferred_i_39__3_n_0;
  wire rdEn_nxt_inferred_i_40__3_n_0;
  wire rdEn_nxt_inferred_i_41__3_n_0;
  wire rdEn_nxt_inferred_i_42__3_n_0;
  wire rdEn_nxt_inferred_i_43__3_n_0;
  wire rdEn_nxt_inferred_i_44__3_n_0;
  wire rdEn_nxt_inferred_i_45__3_n_0;
  wire rdEn_nxt_inferred_i_46__3_n_0;
  wire rdEn_nxt_inferred_i_47__3_n_0;
  wire rdEn_nxt_inferred_i_48__3_n_0;
  wire rdEn_nxt_inferred_i_49__3_n_0;
  wire rdEn_nxt_inferred_i_50__3_n_0;
  wire rdEn_nxt_inferred_i_51__3_n_0;
  wire rdEn_nxt_inferred_i_52__3_n_0;
  wire rdEn_nxt_inferred_i_53__1_n_0;
  wire rdEn_nxt_inferred_i_54__0_n_0;
  wire rdEn_nxt_inferred_i_55_n_0;
  wire rdEn_nxt_inferred_i_56_n_0;
  wire rdEn_nxt_inferred_i_57_n_0;
  wire rdEn_nxt_inferred_i_58_n_0;
  wire rdEn_nxt_inferred_i_59_n_0;
  wire rdEn_nxt_inferred_i_60_n_0;
  wire rdEn_nxt_inferred_i_61_n_0;
  wire rdEn_nxt_inferred_i_62_n_0;
  wire rdEn_nxt_inferred_i_63_n_0;
  wire rdEn_nxt_inferred_i_64_n_0;
  wire rdEn_nxt_inferred_i_65_n_0;
  wire rdEn_nxt_inferred_i_66_n_0;
  wire rdEn_nxt_inferred_i_67_n_0;
  wire rdEn_nxt_inferred_i_68_n_0;
  wire rdEn_nxt_inferred_i_69_n_0;
  wire \rdEn_reg[12]_0 ;
  wire \rdEn_reg[12]_1 ;
  wire \rdEn_reg[14]_0 ;
  wire \rdEn_reg[14]_1 ;
  wire [11:11]rs2mask0__0;
  wire \rs2mask0_inferred__0/i__n_0 ;
  wire \rs2mask0_inferred__1/i__n_0 ;
  wire \rs2mask0_inferred__2/i__n_0 ;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_70 ;
  wire [2:0]\rsMask_reg[1][11]_0 ;
  wire [3:0]\rsMask_reg[1][12]_0 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire [1:0]\rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][18]_2 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [16:1]\rsMask_reg[1]_71 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_72 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [2:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire [1:0]\rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][18]_2 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [16:1]\rsMask_reg[3]_73 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_74 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [2:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire [1:0]\rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][18]_2 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [16:1]\rsMask_reg[5]_75 ;
  wire \rsMask_reg[6][11]_0 ;
  wire \rsMask_reg[6][9]_0 ;
  wire [2:0]\rsMask_reg[6][9]_1 ;
  wire [11:2]\rsMask_reg[6]_76 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [2:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire [1:0]\rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire [16:1]\rsMask_reg[7]_77 ;

  assign rdEn_nxt[29:28] = in0[1:0];
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_10__3
       (.I0(out),
        .I1(rdEn[24]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_50__3_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_51__3_n_0),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_11__4
       (.I0(rdEn[23]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_52__3_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_53__1_n_0),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_12__3
       (.I0(out),
        .I1(rdEn[22]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_54__0_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_55_n_0),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_13__4
       (.I0(rdEn[21]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_56_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_57_n_0),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_14__3
       (.I0(out),
        .I1(rdEn[20]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_58_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_59_n_0),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_15__3
       (.I0(out),
        .I1(rdEn[19]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_60_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_61_n_0),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_16__3
       (.I0(out),
        .I1(rdEn[18]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_62_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_63_n_0),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_17__3
       (.I0(out),
        .I1(rdEn[17]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_64_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_65_n_0),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_18__4
       (.I0(rdEn[16]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_66_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_67_n_0),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_19__4
       (.I0(rdEn[15]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_68_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_69_n_0),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__3
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__3
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__3
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__3
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__3
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__3
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__3
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__3
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__3
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__3
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__3
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__3
       (.I0(\rsMask_reg[3]_73 [16]),
        .I1(\rsMask_reg[3][18]_0 [1]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [16]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1][18]_0 [1]),
        .O(rdEn_nxt_inferred_i_36__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__3
       (.I0(\rsMask_reg[7]_77 [16]),
        .I1(\rsMask_reg[7][18]_0 [1]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [16]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5][18]_0 [1]),
        .O(rdEn_nxt_inferred_i_37__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__3
       (.I0(\rsMask_reg[3]_73 [15]),
        .I1(\rsMask_reg[3][18]_0 [0]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [15]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1][18]_0 [0]),
        .O(rdEn_nxt_inferred_i_38__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__3
       (.I0(\rsMask_reg[7]_77 [15]),
        .I1(\rsMask_reg[7][18]_0 [0]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [15]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5][18]_0 [0]),
        .O(rdEn_nxt_inferred_i_39__3_n_0));
  LUT5 #(
    .INIT(32'h0000E200)) 
    rdEn_nxt_inferred_i_3__4
       (.I0(rdEn_nxt_inferred_i_36__3_n_0),
        .I1(\rdEn_reg[12]_1 ),
        .I2(rdEn_nxt_inferred_i_37__3_n_0),
        .I3(\rdEn_reg[12]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__3
       (.I0(\rsMask_reg[7]_77 [14]),
        .I1(\rsMask_reg[7]_77 [16]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [14]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_75 [16]),
        .O(rdEn_nxt_inferred_i_40__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__3
       (.I0(\rsMask_reg[3]_73 [14]),
        .I1(\rsMask_reg[3]_73 [16]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [14]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_71 [16]),
        .O(rdEn_nxt_inferred_i_41__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__3
       (.I0(\rsMask_reg[3]_73 [13]),
        .I1(\rsMask_reg[3]_73 [15]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [13]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_71 [15]),
        .O(rdEn_nxt_inferred_i_42__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__3
       (.I0(\rsMask_reg[7]_77 [13]),
        .I1(\rsMask_reg[7]_77 [15]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [13]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_75 [15]),
        .O(rdEn_nxt_inferred_i_43__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__3
       (.I0(\rsMask_reg[7]_77 [12]),
        .I1(\rsMask_reg[7]_77 [14]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [12]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_75 [14]),
        .O(rdEn_nxt_inferred_i_44__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__3
       (.I0(\rsMask_reg[3]_73 [12]),
        .I1(\rsMask_reg[3]_73 [14]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [12]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_71 [14]),
        .O(rdEn_nxt_inferred_i_45__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__3
       (.I0(\rsMask_reg[3]_73 [11]),
        .I1(\rsMask_reg[2]_72 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_70 [11]),
        .O(rdEn_nxt_inferred_i_46__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__3
       (.I0(\rsMask_reg[7]_77 [11]),
        .I1(\rsMask_reg[6]_76 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[4]_74 [11]),
        .O(rdEn_nxt_inferred_i_47__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__3
       (.I0(\rsMask_reg[7]_77 [10]),
        .I1(\rsMask_reg[7]_77 [12]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [10]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_75 [12]),
        .O(rdEn_nxt_inferred_i_48__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__3
       (.I0(\rsMask_reg[3]_73 [10]),
        .I1(\rsMask_reg[3]_73 [12]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [10]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_71 [12]),
        .O(rdEn_nxt_inferred_i_49__3_n_0));
  LUT5 #(
    .INIT(32'h0000E200)) 
    rdEn_nxt_inferred_i_4__4
       (.I0(rdEn_nxt_inferred_i_38__3_n_0),
        .I1(\rdEn_reg[12]_1 ),
        .I2(rdEn_nxt_inferred_i_39__3_n_0),
        .I3(\rdEn_reg[12]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__3
       (.I0(\rsMask_reg[3]_73 [9]),
        .I1(\rsMask_reg[2]_72 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_70 [9]),
        .O(rdEn_nxt_inferred_i_50__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__3
       (.I0(\rsMask_reg[7]_77 [9]),
        .I1(\rsMask_reg[6]_76 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[4]_74 [9]),
        .O(rdEn_nxt_inferred_i_51__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__3
       (.I0(\rsMask_reg[7]_77 [8]),
        .I1(\rsMask_reg[7]_77 [10]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [8]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_75 [10]),
        .O(rdEn_nxt_inferred_i_52__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_53__1
       (.I0(\rsMask_reg[3]_73 [8]),
        .I1(\rsMask_reg[3]_73 [10]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [8]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_71 [10]),
        .O(rdEn_nxt_inferred_i_53__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_54__0
       (.I0(\rsMask_reg[3]_73 [7]),
        .I1(\rsMask_reg[3]_73 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [7]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_71 [9]),
        .O(rdEn_nxt_inferred_i_54__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_55
       (.I0(\rsMask_reg[7]_77 [7]),
        .I1(\rsMask_reg[7]_77 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [7]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_75 [9]),
        .O(rdEn_nxt_inferred_i_55_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_56
       (.I0(\rsMask_reg[7]_77 [6]),
        .I1(\rsMask_reg[7]_77 [8]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [6]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_75 [8]),
        .O(rdEn_nxt_inferred_i_56_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_57
       (.I0(\rsMask_reg[3]_73 [6]),
        .I1(\rsMask_reg[3]_73 [8]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [6]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_71 [8]),
        .O(rdEn_nxt_inferred_i_57_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_58
       (.I0(\rsMask_reg[3]_73 [5]),
        .I1(\rsMask_reg[3]_73 [7]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [5]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_71 [7]),
        .O(rdEn_nxt_inferred_i_58_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_59
       (.I0(\rsMask_reg[7]_77 [5]),
        .I1(\rsMask_reg[7]_77 [7]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [5]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_75 [7]),
        .O(rdEn_nxt_inferred_i_59_n_0));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_5__4
       (.I0(rdEn[29]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_40__3_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_41__3_n_0),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_60
       (.I0(\rsMask_reg[3]_73 [4]),
        .I1(\rsMask_reg[3]_73 [6]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [4]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_71 [6]),
        .O(rdEn_nxt_inferred_i_60_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_61
       (.I0(\rsMask_reg[7]_77 [4]),
        .I1(\rsMask_reg[7]_77 [6]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [4]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_75 [6]),
        .O(rdEn_nxt_inferred_i_61_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_62
       (.I0(\rsMask_reg[3]_73 [3]),
        .I1(\rsMask_reg[2]_72 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_70 [3]),
        .O(rdEn_nxt_inferred_i_62_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_63
       (.I0(\rsMask_reg[7]_77 [3]),
        .I1(\rsMask_reg[6]_76 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[4]_74 [3]),
        .O(rdEn_nxt_inferred_i_63_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_64
       (.I0(\rsMask_reg[3]_73 [2]),
        .I1(\rsMask_reg[2]_72 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_70 [2]),
        .O(rdEn_nxt_inferred_i_64_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_65
       (.I0(\rsMask_reg[7]_77 [2]),
        .I1(\rsMask_reg[6]_76 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[4]_74 [2]),
        .O(rdEn_nxt_inferred_i_65_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_66
       (.I0(\rsMask_reg[7]_77 [1]),
        .I1(\rsMask_reg[7]_77 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_75 [3]),
        .O(rdEn_nxt_inferred_i_66_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_67
       (.I0(\rsMask_reg[3]_73 [1]),
        .I1(\rsMask_reg[3]_73 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_71 [3]),
        .O(rdEn_nxt_inferred_i_67_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_68
       (.I0(\rsMask_reg[7]_77 [1]),
        .I1(\rsMask_reg[7]_77 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_75 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_75 [2]),
        .O(rdEn_nxt_inferred_i_68_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_69
       (.I0(\rsMask_reg[3]_73 [1]),
        .I1(\rsMask_reg[3]_73 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_71 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_71 [2]),
        .O(rdEn_nxt_inferred_i_69_n_0));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_6__3
       (.I0(out),
        .I1(rdEn[28]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_42__3_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_43__3_n_0),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_7__4
       (.I0(rdEn[27]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_44__3_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_45__3_n_0),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_8__3
       (.I0(out),
        .I1(rdEn[26]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_46__3_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_47__3_n_0),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_9__4
       (.I0(rdEn[25]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_48__3_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_49__3_n_0),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_upp[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_upp[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_upp[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_upp[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h4C)) 
    rs2mask0
       (.I0(\rsMask_reg[1][11]_0 [0]),
        .I1(\rsMask_reg[1][11]_0 [1]),
        .I2(\rsMask_reg[1][11]_0 [2]),
        .O(rs2mask0__0));
  LUT3 #(
    .INIT(8'h4C)) 
    \rs2mask0_inferred__0/i_ 
       (.I0(\rsMask_reg[3][11]_0 [0]),
        .I1(\rsMask_reg[3][11]_0 [1]),
        .I2(\rsMask_reg[3][11]_0 [2]),
        .O(\rs2mask0_inferred__0/i__n_0 ));
  LUT3 #(
    .INIT(8'h4C)) 
    \rs2mask0_inferred__1/i_ 
       (.I0(\rsMask_reg[5][11]_0 [0]),
        .I1(\rsMask_reg[5][11]_0 [1]),
        .I2(\rsMask_reg[5][11]_0 [2]),
        .O(\rs2mask0_inferred__1/i__n_0 ));
  LUT3 #(
    .INIT(8'h4C)) 
    \rs2mask0_inferred__2/i_ 
       (.I0(\rsMask_reg[7][11]_0 [0]),
        .I1(\rsMask_reg[7][11]_0 [1]),
        .I2(\rsMask_reg[7][11]_0 [2]),
        .O(\rs2mask0_inferred__2/i__n_0 ));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_70 [11]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_70 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_70 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_70 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][12]_0 [2]),
        .Q(\rsMask_reg[1]_71 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0__0),
        .Q(\rsMask_reg[1]_71 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][12]_0 [3]),
        .Q(\rsMask_reg[1]_71 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_71 [13]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_71 [14]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_71 [15]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_71 [16]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1][18]_0 [0]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_2 ),
        .Q(\rsMask_reg[1][18]_0 [1]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_71 [1]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][12]_0 [0]),
        .Q(\rsMask_reg[1]_71 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][12]_0 [1]),
        .Q(\rsMask_reg[1]_71 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_71 [4]),
        .R(\blk1.(null)[0].diff [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_71 [5]),
        .R(\blk1.(null)[0].diff [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_71 [6]),
        .R(\blk1.(null)[0].diff [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_71 [7]),
        .R(\blk1.(null)[0].diff [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_71 [8]),
        .R(\blk1.(null)[0].diff [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff [0]),
        .Q(\rsMask_reg[1]_71 [9]),
        .R(\blk1.(null)[0].diff [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_72 [11]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_72 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_72 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_72 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_73 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rs2mask0_inferred__0/i__n_0 ),
        .Q(\rsMask_reg[3]_73 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_73 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_73 [13]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_73 [14]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_73 [15]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_73 [16]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3][18]_0 [0]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_2 ),
        .Q(\rsMask_reg[3][18]_0 [1]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_73 [1]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_73 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_73 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_73 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_73 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_73 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_73 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_73 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_73 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_74 [11]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_74 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_74 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_74 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_75 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rs2mask0_inferred__1/i__n_0 ),
        .Q(\rsMask_reg[5]_75 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_75 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_75 [13]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_75 [14]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_75 [15]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_75 [16]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5][18]_0 [0]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_2 ),
        .Q(\rsMask_reg[5][18]_0 [1]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_75 [1]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_75 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_75 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_75 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_75 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_75 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_75 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_75 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_75 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_76 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_1 [0]),
        .Q(\rsMask_reg[6]_76 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_1 [1]),
        .Q(\rsMask_reg[6]_76 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_1 [2]),
        .Q(\rsMask_reg[6]_76 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_77 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rs2mask0_inferred__2/i__n_0 ),
        .Q(\rsMask_reg[7]_77 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_77 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_77 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_77 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_77 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_77 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_0 ),
        .Q(\rsMask_reg[7][18]_0 [0]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7][18]_0 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_77 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_77 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_77 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_77 [4]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_77 [5]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_77 [6]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_77 [7]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_77 [8]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_1 ),
        .Q(\rsMask_reg[7]_77 [9]),
        .R(\rsMask_reg[7][9]_0 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_15
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_low,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_22,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_23 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_2 ,
    mcalRdCAS,
    mcalCasSlot,
    out,
    mcalRank,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_low;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_22;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_23 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_1 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_2 ;
  input mcalRdCAS;
  input [0:0]mcalCasSlot;
  input out;
  input [1:0]mcalRank;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_23 ;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [0:0]mcalCasSlot;
  wire [1:0]mcalRank;
  wire mcalRdCAS;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_33__10_n_0;
  wire rdEn_nxt_inferred_i_34__12_n_0;
  wire rdEn_nxt_inferred_i_35__12_n_0;
  wire rdEn_nxt_inferred_i_36__12_n_0;
  wire rdEn_nxt_inferred_i_37__12_n_0;
  wire rdEn_nxt_inferred_i_38__12_n_0;
  wire rdEn_nxt_inferred_i_39__12_n_0;
  wire rdEn_nxt_inferred_i_40__12_n_0;
  wire rdEn_nxt_inferred_i_41__12_n_0;
  wire rdEn_nxt_inferred_i_42__12_n_0;
  wire rdEn_nxt_inferred_i_43__12_n_0;
  wire rdEn_nxt_inferred_i_44__12_n_0;
  wire rdEn_nxt_inferred_i_45__12_n_0;
  wire rdEn_nxt_inferred_i_46__12_n_0;
  wire rdEn_nxt_inferred_i_47__12_n_0;
  wire rdEn_nxt_inferred_i_48__12_n_0;
  wire rdEn_nxt_inferred_i_49__12_n_0;
  wire rdEn_nxt_inferred_i_50__12_n_0;
  wire rdEn_nxt_inferred_i_51__12_n_0;
  wire rdEn_nxt_inferred_i_52__12_n_0;
  wire [4:0]rs2mask0_22;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_142 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_143 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_144 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_145 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_146 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_147 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_148 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire \rsMask_reg[7][9]_2 ;
  wire [18:1]\rsMask_reg[7]_149 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__12
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_41__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_42__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__12
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_40__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_43__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__12
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_42__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_44__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__12
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_43__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_45__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__12
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_44__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_46__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__12
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_45__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_47__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__12
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_48__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_49__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__12
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_50__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_51__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__12
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_49__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_52__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__12
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_51__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_52__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__12
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__12
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__12
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__12
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__12
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__12
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__12
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__12
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__12
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__12
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__12
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_31__9
       (.I0(\rsMask_reg[7]_149 [18]),
        .I1(\rsMask_reg[5]_147 [18]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [18]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_32__8
       (.I0(\rsMask_reg[7]_149 [17]),
        .I1(\rsMask_reg[5]_147 [17]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [17]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_33__10
       (.I0(\rsMask_reg[7]_149 [16]),
        .I1(\rsMask_reg[5]_147 [16]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [16]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [16]),
        .O(rdEn_nxt_inferred_i_33__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__12
       (.I0(\rsMask_reg[7]_149 [15]),
        .I1(\rsMask_reg[5]_147 [15]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [15]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [15]),
        .O(rdEn_nxt_inferred_i_34__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__12
       (.I0(\rsMask_reg[7]_149 [14]),
        .I1(\rsMask_reg[5]_147 [14]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [14]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [14]),
        .O(rdEn_nxt_inferred_i_35__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__12
       (.I0(\rsMask_reg[7]_149 [13]),
        .I1(\rsMask_reg[5]_147 [13]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [13]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [13]),
        .O(rdEn_nxt_inferred_i_36__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__12
       (.I0(\rsMask_reg[7]_149 [12]),
        .I1(\rsMask_reg[5]_147 [12]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [12]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [12]),
        .O(rdEn_nxt_inferred_i_37__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__12
       (.I0(\rsMask_reg[6]_148 [11]),
        .I1(\rsMask_reg[4]_146 [11]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_144 [11]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_142 [11]),
        .O(rdEn_nxt_inferred_i_38__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__12
       (.I0(\rsMask_reg[7]_149 [11]),
        .I1(\rsMask_reg[5]_147 [11]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [11]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [11]),
        .O(rdEn_nxt_inferred_i_39__12_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__12
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_33__10_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__12
       (.I0(\rsMask_reg[7]_149 [10]),
        .I1(\rsMask_reg[5]_147 [10]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [10]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [10]),
        .O(rdEn_nxt_inferred_i_40__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__12
       (.I0(\rsMask_reg[6]_148 [9]),
        .I1(\rsMask_reg[4]_146 [9]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_144 [9]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_142 [9]),
        .O(rdEn_nxt_inferred_i_41__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__12
       (.I0(\rsMask_reg[7]_149 [9]),
        .I1(\rsMask_reg[5]_147 [9]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [9]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [9]),
        .O(rdEn_nxt_inferred_i_42__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__12
       (.I0(\rsMask_reg[7]_149 [8]),
        .I1(\rsMask_reg[5]_147 [8]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [8]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [8]),
        .O(rdEn_nxt_inferred_i_43__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__12
       (.I0(\rsMask_reg[7]_149 [7]),
        .I1(\rsMask_reg[5]_147 [7]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [7]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [7]),
        .O(rdEn_nxt_inferred_i_44__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__12
       (.I0(\rsMask_reg[7]_149 [6]),
        .I1(\rsMask_reg[5]_147 [6]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [6]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [6]),
        .O(rdEn_nxt_inferred_i_45__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__12
       (.I0(\rsMask_reg[7]_149 [5]),
        .I1(\rsMask_reg[5]_147 [5]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [5]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [5]),
        .O(rdEn_nxt_inferred_i_46__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__12
       (.I0(\rsMask_reg[7]_149 [4]),
        .I1(\rsMask_reg[5]_147 [4]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [4]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [4]),
        .O(rdEn_nxt_inferred_i_47__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__12
       (.I0(\rsMask_reg[6]_148 [3]),
        .I1(\rsMask_reg[4]_146 [3]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_144 [3]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_142 [3]),
        .O(rdEn_nxt_inferred_i_48__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__12
       (.I0(\rsMask_reg[7]_149 [3]),
        .I1(\rsMask_reg[5]_147 [3]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [3]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [3]),
        .O(rdEn_nxt_inferred_i_49__12_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__12
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_34__12_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__12
       (.I0(\rsMask_reg[6]_148 [2]),
        .I1(\rsMask_reg[4]_146 [2]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_144 [2]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_142 [2]),
        .O(rdEn_nxt_inferred_i_50__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__12
       (.I0(\rsMask_reg[7]_149 [2]),
        .I1(\rsMask_reg[5]_147 [2]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [2]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [2]),
        .O(rdEn_nxt_inferred_i_51__12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__12
       (.I0(\rsMask_reg[7]_149 [1]),
        .I1(\rsMask_reg[5]_147 [1]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_145 [1]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_143 [1]),
        .O(rdEn_nxt_inferred_i_52__12_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__12
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_33__10_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_35__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__12
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_34__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_36__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__12
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_35__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_37__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__12
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_38__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_39__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__12
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_37__12_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_40__12_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_low[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_low[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_low[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_low[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_142 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_142 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_142 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_142 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_22[2]),
        .Q(\rsMask_reg[1]_143 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_22[3]),
        .Q(\rsMask_reg[1]_143 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_22[4]),
        .Q(\rsMask_reg[1]_143 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_143 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_143 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_143 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_143 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_143 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_143 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_143 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_22[0]),
        .Q(\rsMask_reg[1]_143 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_22[1]),
        .Q(\rsMask_reg[1]_143 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_143 [4]),
        .R(\blk1.(null)[0].diff_23 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_143 [5]),
        .R(\blk1.(null)[0].diff_23 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_143 [6]),
        .R(\blk1.(null)[0].diff_23 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_143 [7]),
        .R(\blk1.(null)[0].diff_23 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_143 [8]),
        .R(\blk1.(null)[0].diff_23 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_23 [0]),
        .Q(\rsMask_reg[1]_143 [9]),
        .R(\blk1.(null)[0].diff_23 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_144 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_144 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_144 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_144 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_145 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_145 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_145 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_145 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_145 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_145 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_145 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_145 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_145 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_145 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_145 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_145 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_145 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_145 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_145 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_145 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_145 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_145 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_146 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_146 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_146 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_146 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_147 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_147 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_147 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_147 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_147 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_147 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_147 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_147 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_147 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_147 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_147 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_147 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_147 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_147 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_147 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_147 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_147 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_147 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_148 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_148 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_148 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_148 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_149 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_149 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_149 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_149 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_149 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_149 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_149 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_149 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_149 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_149 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_149 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_149 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_149 [4]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_149 [5]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_149 [6]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_149 [7]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_149 [8]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_2 ),
        .Q(\rsMask_reg[7]_149 [9]),
        .R(\rsMask_reg[7][9]_1 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_16
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_upp,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_4,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_5 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_2 ,
    \rdEn_reg[12]_0 ,
    \rdEn_reg[12]_1 ,
    out,
    \rdEn_reg[14]_0 ,
    \rdEn_reg[14]_1 ,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_upp;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_4;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_5 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_1 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_2 ;
  input \rdEn_reg[12]_0 ;
  input \rdEn_reg[12]_1 ;
  input out;
  input \rdEn_reg[14]_0 ;
  input \rdEn_reg[14]_1 ;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_5 ;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_33__0_n_0;
  wire rdEn_nxt_inferred_i_34__1_n_0;
  wire rdEn_nxt_inferred_i_35__1_n_0;
  wire rdEn_nxt_inferred_i_36__1_n_0;
  wire rdEn_nxt_inferred_i_37__1_n_0;
  wire rdEn_nxt_inferred_i_38__1_n_0;
  wire rdEn_nxt_inferred_i_39__1_n_0;
  wire rdEn_nxt_inferred_i_40__1_n_0;
  wire rdEn_nxt_inferred_i_41__1_n_0;
  wire rdEn_nxt_inferred_i_42__1_n_0;
  wire rdEn_nxt_inferred_i_43__1_n_0;
  wire rdEn_nxt_inferred_i_44__1_n_0;
  wire rdEn_nxt_inferred_i_45__1_n_0;
  wire rdEn_nxt_inferred_i_46__1_n_0;
  wire rdEn_nxt_inferred_i_47__1_n_0;
  wire rdEn_nxt_inferred_i_48__1_n_0;
  wire rdEn_nxt_inferred_i_49__1_n_0;
  wire rdEn_nxt_inferred_i_50__1_n_0;
  wire rdEn_nxt_inferred_i_51__1_n_0;
  wire rdEn_nxt_inferred_i_52__1_n_0;
  wire \rdEn_reg[12]_0 ;
  wire \rdEn_reg[12]_1 ;
  wire \rdEn_reg[14]_0 ;
  wire \rdEn_reg[14]_1 ;
  wire [4:0]rs2mask0_4;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_54 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_55 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_56 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_57 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_58 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_59 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_60 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire \rsMask_reg[7][9]_2 ;
  wire [18:1]\rsMask_reg[7]_61 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__1
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_41__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_42__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__1
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_40__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_43__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__1
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_42__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_44__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__1
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_43__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_45__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__1
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_44__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_46__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__1
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_45__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_47__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__1
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_48__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_49__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__1
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_50__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_51__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__1
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_49__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_52__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__1
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_51__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_52__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__1
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__1
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__1
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__1
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__1
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__1
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__1
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__1
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__1
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__1
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__1
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_31__0
       (.I0(\rsMask_reg[7]_61 [18]),
        .I1(\rsMask_reg[5]_59 [18]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [18]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_32__0
       (.I0(\rsMask_reg[7]_61 [17]),
        .I1(\rsMask_reg[5]_59 [17]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [17]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_33__0
       (.I0(\rsMask_reg[7]_61 [16]),
        .I1(\rsMask_reg[5]_59 [16]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [16]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [16]),
        .O(rdEn_nxt_inferred_i_33__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__1
       (.I0(\rsMask_reg[7]_61 [15]),
        .I1(\rsMask_reg[5]_59 [15]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [15]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [15]),
        .O(rdEn_nxt_inferred_i_34__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__1
       (.I0(\rsMask_reg[7]_61 [14]),
        .I1(\rsMask_reg[5]_59 [14]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [14]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [14]),
        .O(rdEn_nxt_inferred_i_35__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__1
       (.I0(\rsMask_reg[7]_61 [13]),
        .I1(\rsMask_reg[5]_59 [13]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [13]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [13]),
        .O(rdEn_nxt_inferred_i_36__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__1
       (.I0(\rsMask_reg[7]_61 [12]),
        .I1(\rsMask_reg[5]_59 [12]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [12]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [12]),
        .O(rdEn_nxt_inferred_i_37__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__1
       (.I0(\rsMask_reg[6]_60 [11]),
        .I1(\rsMask_reg[4]_58 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_56 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_54 [11]),
        .O(rdEn_nxt_inferred_i_38__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__1
       (.I0(\rsMask_reg[7]_61 [11]),
        .I1(\rsMask_reg[5]_59 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [11]),
        .O(rdEn_nxt_inferred_i_39__1_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__1
       (.I0(\rdEn_reg[12]_0 ),
        .I1(rdEn_nxt_inferred_i_33__0_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__1
       (.I0(\rsMask_reg[7]_61 [10]),
        .I1(\rsMask_reg[5]_59 [10]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [10]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [10]),
        .O(rdEn_nxt_inferred_i_40__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__1
       (.I0(\rsMask_reg[6]_60 [9]),
        .I1(\rsMask_reg[4]_58 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_56 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_54 [9]),
        .O(rdEn_nxt_inferred_i_41__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__1
       (.I0(\rsMask_reg[7]_61 [9]),
        .I1(\rsMask_reg[5]_59 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [9]),
        .O(rdEn_nxt_inferred_i_42__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__1
       (.I0(\rsMask_reg[7]_61 [8]),
        .I1(\rsMask_reg[5]_59 [8]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [8]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [8]),
        .O(rdEn_nxt_inferred_i_43__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__1
       (.I0(\rsMask_reg[7]_61 [7]),
        .I1(\rsMask_reg[5]_59 [7]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [7]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [7]),
        .O(rdEn_nxt_inferred_i_44__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__1
       (.I0(\rsMask_reg[7]_61 [6]),
        .I1(\rsMask_reg[5]_59 [6]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [6]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [6]),
        .O(rdEn_nxt_inferred_i_45__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__1
       (.I0(\rsMask_reg[7]_61 [5]),
        .I1(\rsMask_reg[5]_59 [5]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [5]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [5]),
        .O(rdEn_nxt_inferred_i_46__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__1
       (.I0(\rsMask_reg[7]_61 [4]),
        .I1(\rsMask_reg[5]_59 [4]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [4]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [4]),
        .O(rdEn_nxt_inferred_i_47__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__1
       (.I0(\rsMask_reg[6]_60 [3]),
        .I1(\rsMask_reg[4]_58 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_56 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_54 [3]),
        .O(rdEn_nxt_inferred_i_48__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__1
       (.I0(\rsMask_reg[7]_61 [3]),
        .I1(\rsMask_reg[5]_59 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [3]),
        .O(rdEn_nxt_inferred_i_49__1_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__1
       (.I0(\rdEn_reg[12]_0 ),
        .I1(rdEn_nxt_inferred_i_34__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__1
       (.I0(\rsMask_reg[6]_60 [2]),
        .I1(\rsMask_reg[4]_58 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_56 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_54 [2]),
        .O(rdEn_nxt_inferred_i_50__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__1
       (.I0(\rsMask_reg[7]_61 [2]),
        .I1(\rsMask_reg[5]_59 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [2]),
        .O(rdEn_nxt_inferred_i_51__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__1
       (.I0(\rsMask_reg[7]_61 [1]),
        .I1(\rsMask_reg[5]_59 [1]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_57 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_55 [1]),
        .O(rdEn_nxt_inferred_i_52__1_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__1
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_33__0_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_35__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__1
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_34__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_36__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__1
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_35__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_37__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__1
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_38__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_39__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__1
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_37__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_40__1_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_upp[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_upp[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_upp[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_upp[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_54 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_54 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_54 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_54 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_4[2]),
        .Q(\rsMask_reg[1]_55 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_4[3]),
        .Q(\rsMask_reg[1]_55 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_4[4]),
        .Q(\rsMask_reg[1]_55 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_55 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_55 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_55 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_55 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_55 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_55 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_55 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_4[0]),
        .Q(\rsMask_reg[1]_55 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_4[1]),
        .Q(\rsMask_reg[1]_55 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_55 [4]),
        .R(\blk1.(null)[0].diff_5 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_55 [5]),
        .R(\blk1.(null)[0].diff_5 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_55 [6]),
        .R(\blk1.(null)[0].diff_5 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_55 [7]),
        .R(\blk1.(null)[0].diff_5 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_55 [8]),
        .R(\blk1.(null)[0].diff_5 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_5 [0]),
        .Q(\rsMask_reg[1]_55 [9]),
        .R(\blk1.(null)[0].diff_5 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_56 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_56 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_56 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_56 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_57 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_57 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_57 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_57 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_57 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_57 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_57 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_57 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_57 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_57 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_57 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_57 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_57 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_57 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_57 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_57 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_57 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_57 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_58 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_58 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_58 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_58 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_59 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_59 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_59 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_59 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_59 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_59 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_59 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_59 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_59 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_59 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_59 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_59 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_59 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_59 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_59 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_59 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_59 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_59 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_60 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_60 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_60 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_60 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_61 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_61 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_61 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_61 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_61 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_61 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_61 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_61 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_61 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_61 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_61 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_61 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_61 [4]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_61 [5]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_61 [6]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_61 [7]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_61 [8]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_2 ),
        .Q(\rsMask_reg[7]_61 [9]),
        .R(\rsMask_reg[7][9]_1 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_17
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_low,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_20,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_21 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_2 ,
    mcalRdCAS,
    mcalCasSlot,
    out,
    mcalRank,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_low;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_20;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_21 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_1 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_2 ;
  input mcalRdCAS;
  input [0:0]mcalCasSlot;
  input out;
  input [1:0]mcalRank;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_21 ;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [0:0]mcalCasSlot;
  wire [1:0]mcalRank;
  wire mcalRdCAS;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_33__9_n_0;
  wire rdEn_nxt_inferred_i_34__11_n_0;
  wire rdEn_nxt_inferred_i_35__11_n_0;
  wire rdEn_nxt_inferred_i_36__11_n_0;
  wire rdEn_nxt_inferred_i_37__11_n_0;
  wire rdEn_nxt_inferred_i_38__11_n_0;
  wire rdEn_nxt_inferred_i_39__11_n_0;
  wire rdEn_nxt_inferred_i_40__11_n_0;
  wire rdEn_nxt_inferred_i_41__11_n_0;
  wire rdEn_nxt_inferred_i_42__11_n_0;
  wire rdEn_nxt_inferred_i_43__11_n_0;
  wire rdEn_nxt_inferred_i_44__11_n_0;
  wire rdEn_nxt_inferred_i_45__11_n_0;
  wire rdEn_nxt_inferred_i_46__11_n_0;
  wire rdEn_nxt_inferred_i_47__11_n_0;
  wire rdEn_nxt_inferred_i_48__11_n_0;
  wire rdEn_nxt_inferred_i_49__11_n_0;
  wire rdEn_nxt_inferred_i_50__11_n_0;
  wire rdEn_nxt_inferred_i_51__11_n_0;
  wire rdEn_nxt_inferred_i_52__11_n_0;
  wire [4:0]rs2mask0_20;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_134 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_135 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_136 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_137 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_138 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_139 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_140 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire \rsMask_reg[7][9]_2 ;
  wire [18:1]\rsMask_reg[7]_141 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__11
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_41__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_42__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__11
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_40__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_43__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__11
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_42__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_44__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__11
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_43__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_45__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__11
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_44__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_46__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__11
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_45__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_47__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__11
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_48__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_49__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__11
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_50__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_51__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__11
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_49__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_52__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__11
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_51__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_52__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__11
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__11
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__11
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__11
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__11
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__11
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__11
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__11
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__11
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__11
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__11
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_31__8
       (.I0(\rsMask_reg[7]_141 [18]),
        .I1(\rsMask_reg[5]_139 [18]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [18]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_32__7
       (.I0(\rsMask_reg[7]_141 [17]),
        .I1(\rsMask_reg[5]_139 [17]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [17]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_33__9
       (.I0(\rsMask_reg[7]_141 [16]),
        .I1(\rsMask_reg[5]_139 [16]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [16]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [16]),
        .O(rdEn_nxt_inferred_i_33__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__11
       (.I0(\rsMask_reg[7]_141 [15]),
        .I1(\rsMask_reg[5]_139 [15]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [15]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [15]),
        .O(rdEn_nxt_inferred_i_34__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__11
       (.I0(\rsMask_reg[7]_141 [14]),
        .I1(\rsMask_reg[5]_139 [14]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [14]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [14]),
        .O(rdEn_nxt_inferred_i_35__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__11
       (.I0(\rsMask_reg[7]_141 [13]),
        .I1(\rsMask_reg[5]_139 [13]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [13]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [13]),
        .O(rdEn_nxt_inferred_i_36__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__11
       (.I0(\rsMask_reg[7]_141 [12]),
        .I1(\rsMask_reg[5]_139 [12]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [12]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [12]),
        .O(rdEn_nxt_inferred_i_37__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__11
       (.I0(\rsMask_reg[6]_140 [11]),
        .I1(\rsMask_reg[4]_138 [11]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_136 [11]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_134 [11]),
        .O(rdEn_nxt_inferred_i_38__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__11
       (.I0(\rsMask_reg[7]_141 [11]),
        .I1(\rsMask_reg[5]_139 [11]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [11]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [11]),
        .O(rdEn_nxt_inferred_i_39__11_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__11
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_33__9_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__11
       (.I0(\rsMask_reg[7]_141 [10]),
        .I1(\rsMask_reg[5]_139 [10]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [10]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [10]),
        .O(rdEn_nxt_inferred_i_40__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__11
       (.I0(\rsMask_reg[6]_140 [9]),
        .I1(\rsMask_reg[4]_138 [9]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_136 [9]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_134 [9]),
        .O(rdEn_nxt_inferred_i_41__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__11
       (.I0(\rsMask_reg[7]_141 [9]),
        .I1(\rsMask_reg[5]_139 [9]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [9]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [9]),
        .O(rdEn_nxt_inferred_i_42__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__11
       (.I0(\rsMask_reg[7]_141 [8]),
        .I1(\rsMask_reg[5]_139 [8]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [8]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [8]),
        .O(rdEn_nxt_inferred_i_43__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__11
       (.I0(\rsMask_reg[7]_141 [7]),
        .I1(\rsMask_reg[5]_139 [7]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [7]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [7]),
        .O(rdEn_nxt_inferred_i_44__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__11
       (.I0(\rsMask_reg[7]_141 [6]),
        .I1(\rsMask_reg[5]_139 [6]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [6]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [6]),
        .O(rdEn_nxt_inferred_i_45__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__11
       (.I0(\rsMask_reg[7]_141 [5]),
        .I1(\rsMask_reg[5]_139 [5]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [5]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [5]),
        .O(rdEn_nxt_inferred_i_46__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__11
       (.I0(\rsMask_reg[7]_141 [4]),
        .I1(\rsMask_reg[5]_139 [4]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [4]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [4]),
        .O(rdEn_nxt_inferred_i_47__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__11
       (.I0(\rsMask_reg[6]_140 [3]),
        .I1(\rsMask_reg[4]_138 [3]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_136 [3]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_134 [3]),
        .O(rdEn_nxt_inferred_i_48__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__11
       (.I0(\rsMask_reg[7]_141 [3]),
        .I1(\rsMask_reg[5]_139 [3]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [3]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [3]),
        .O(rdEn_nxt_inferred_i_49__11_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__11
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_34__11_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__11
       (.I0(\rsMask_reg[6]_140 [2]),
        .I1(\rsMask_reg[4]_138 [2]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_136 [2]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_134 [2]),
        .O(rdEn_nxt_inferred_i_50__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__11
       (.I0(\rsMask_reg[7]_141 [2]),
        .I1(\rsMask_reg[5]_139 [2]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [2]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [2]),
        .O(rdEn_nxt_inferred_i_51__11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__11
       (.I0(\rsMask_reg[7]_141 [1]),
        .I1(\rsMask_reg[5]_139 [1]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_137 [1]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_135 [1]),
        .O(rdEn_nxt_inferred_i_52__11_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__11
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_33__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_35__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__11
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_34__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_36__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__11
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_35__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_37__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__11
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_38__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_39__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__11
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_37__11_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_40__11_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_low[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_low[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_low[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_low[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_134 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_134 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_134 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_134 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_20[2]),
        .Q(\rsMask_reg[1]_135 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_20[3]),
        .Q(\rsMask_reg[1]_135 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_20[4]),
        .Q(\rsMask_reg[1]_135 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_135 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_135 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_135 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_135 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_135 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_135 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_135 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_20[0]),
        .Q(\rsMask_reg[1]_135 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_20[1]),
        .Q(\rsMask_reg[1]_135 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_135 [4]),
        .R(\blk1.(null)[0].diff_21 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_135 [5]),
        .R(\blk1.(null)[0].diff_21 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_135 [6]),
        .R(\blk1.(null)[0].diff_21 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_135 [7]),
        .R(\blk1.(null)[0].diff_21 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_135 [8]),
        .R(\blk1.(null)[0].diff_21 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_21 [0]),
        .Q(\rsMask_reg[1]_135 [9]),
        .R(\blk1.(null)[0].diff_21 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_136 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_136 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_136 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_136 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_137 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_137 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_137 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_137 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_137 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_137 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_137 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_137 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_137 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_137 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_137 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_137 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_137 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_137 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_137 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_137 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_137 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_137 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_138 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_138 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_138 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_138 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_139 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_139 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_139 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_139 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_139 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_139 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_139 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_139 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_139 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_139 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_139 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_139 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_139 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_139 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_139 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_139 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_139 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_139 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_140 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_140 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_140 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_140 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_141 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_141 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_141 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_141 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_141 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_141 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_141 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_141 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_141 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_141 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_141 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_141 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_141 [4]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_141 [5]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_141 [6]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_141 [7]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_141 [8]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_2 ),
        .Q(\rsMask_reg[7]_141 [9]),
        .R(\rsMask_reg[7][9]_1 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_18
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_upp,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_2,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_3 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_2 ,
    \rdEn_reg[14]_0 ,
    \rdEn_reg[12]_0 ,
    out,
    \rdEn_reg[14]_1 ,
    \rdEn_reg[14]_2 ,
    \rdEn_reg[12]_1 ,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_upp;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_2;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_3 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_1 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_2 ;
  input \rdEn_reg[14]_0 ;
  input \rdEn_reg[12]_0 ;
  input out;
  input \rdEn_reg[14]_1 ;
  input \rdEn_reg[14]_2 ;
  input \rdEn_reg[12]_1 ;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_3 ;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_34__0_n_0;
  wire rdEn_nxt_inferred_i_35__0_n_0;
  wire rdEn_nxt_inferred_i_36__0_n_0;
  wire rdEn_nxt_inferred_i_37__0_n_0;
  wire rdEn_nxt_inferred_i_38__0_n_0;
  wire rdEn_nxt_inferred_i_39__0_n_0;
  wire rdEn_nxt_inferred_i_40__0_n_0;
  wire rdEn_nxt_inferred_i_41__0_n_0;
  wire rdEn_nxt_inferred_i_42__0_n_0;
  wire rdEn_nxt_inferred_i_43__0_n_0;
  wire rdEn_nxt_inferred_i_44__0_n_0;
  wire rdEn_nxt_inferred_i_45__0_n_0;
  wire rdEn_nxt_inferred_i_46__0_n_0;
  wire rdEn_nxt_inferred_i_47__0_n_0;
  wire rdEn_nxt_inferred_i_48__0_n_0;
  wire rdEn_nxt_inferred_i_49__0_n_0;
  wire rdEn_nxt_inferred_i_50__0_n_0;
  wire rdEn_nxt_inferred_i_51__0_n_0;
  wire rdEn_nxt_inferred_i_52__0_n_0;
  wire rdEn_nxt_inferred_i_53__0_n_0;
  wire \rdEn_reg[12]_0 ;
  wire \rdEn_reg[12]_1 ;
  wire \rdEn_reg[14]_0 ;
  wire \rdEn_reg[14]_1 ;
  wire \rdEn_reg[14]_2 ;
  wire [4:0]rs2mask0_2;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_14 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_15 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_16 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_17 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_18 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_19 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_20 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire \rsMask_reg[7][9]_2 ;
  wire [18:1]\rsMask_reg[7]_21 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__0
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_42__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_43__0_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__0
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_41__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_44__0_n_0),
        .I4(\rdEn_reg[14]_0 ),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__0
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_43__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_45__0_n_0),
        .I4(\rdEn_reg[14]_0 ),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__0
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_44__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_46__0_n_0),
        .I4(\rdEn_reg[14]_0 ),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__0
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_45__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_47__0_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__0
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_46__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_48__0_n_0),
        .I4(\rdEn_reg[14]_0 ),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__0
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_49__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_50__0_n_0),
        .I4(\rdEn_reg[14]_0 ),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__0
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_51__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_52__0_n_0),
        .I4(\rdEn_reg[14]_0 ),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__0
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_50__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_53__0_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__0
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_52__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_53__0_n_0),
        .I4(\rdEn_reg[14]_0 ),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__0
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__0
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__0
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__0
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__0
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__0
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__0
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__0
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__0
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__0
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__0
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_31
       (.I0(\rsMask_reg[7]_21 [18]),
        .I1(\rsMask_reg[5]_19 [18]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [18]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_33
       (.I0(\rsMask_reg[7]_21 [17]),
        .I1(\rsMask_reg[5]_19 [17]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [17]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__0
       (.I0(\rsMask_reg[7]_21 [16]),
        .I1(\rsMask_reg[5]_19 [16]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [16]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [16]),
        .O(rdEn_nxt_inferred_i_34__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__0
       (.I0(\rsMask_reg[7]_21 [15]),
        .I1(\rsMask_reg[5]_19 [15]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [15]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [15]),
        .O(rdEn_nxt_inferred_i_35__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__0
       (.I0(\rsMask_reg[7]_21 [14]),
        .I1(\rsMask_reg[5]_19 [14]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [14]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [14]),
        .O(rdEn_nxt_inferred_i_36__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__0
       (.I0(\rsMask_reg[7]_21 [13]),
        .I1(\rsMask_reg[5]_19 [13]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [13]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [13]),
        .O(rdEn_nxt_inferred_i_37__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__0
       (.I0(\rsMask_reg[7]_21 [12]),
        .I1(\rsMask_reg[5]_19 [12]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [12]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [12]),
        .O(rdEn_nxt_inferred_i_38__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__0
       (.I0(\rsMask_reg[6]_20 [11]),
        .I1(\rsMask_reg[4]_18 [11]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[2]_16 [11]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[0]_14 [11]),
        .O(rdEn_nxt_inferred_i_39__0_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__0
       (.I0(\rdEn_reg[14]_0 ),
        .I1(rdEn_nxt_inferred_i_34__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__0
       (.I0(\rsMask_reg[7]_21 [11]),
        .I1(\rsMask_reg[5]_19 [11]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [11]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [11]),
        .O(rdEn_nxt_inferred_i_40__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__0
       (.I0(\rsMask_reg[7]_21 [10]),
        .I1(\rsMask_reg[5]_19 [10]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [10]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [10]),
        .O(rdEn_nxt_inferred_i_41__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__0
       (.I0(\rsMask_reg[6]_20 [9]),
        .I1(\rsMask_reg[4]_18 [9]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[2]_16 [9]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[0]_14 [9]),
        .O(rdEn_nxt_inferred_i_42__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__0
       (.I0(\rsMask_reg[7]_21 [9]),
        .I1(\rsMask_reg[5]_19 [9]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [9]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [9]),
        .O(rdEn_nxt_inferred_i_43__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__0
       (.I0(\rsMask_reg[7]_21 [8]),
        .I1(\rsMask_reg[5]_19 [8]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [8]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [8]),
        .O(rdEn_nxt_inferred_i_44__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__0
       (.I0(\rsMask_reg[7]_21 [7]),
        .I1(\rsMask_reg[5]_19 [7]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [7]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [7]),
        .O(rdEn_nxt_inferred_i_45__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__0
       (.I0(\rsMask_reg[7]_21 [6]),
        .I1(\rsMask_reg[5]_19 [6]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [6]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [6]),
        .O(rdEn_nxt_inferred_i_46__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__0
       (.I0(\rsMask_reg[7]_21 [5]),
        .I1(\rsMask_reg[5]_19 [5]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [5]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [5]),
        .O(rdEn_nxt_inferred_i_47__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__0
       (.I0(\rsMask_reg[7]_21 [4]),
        .I1(\rsMask_reg[5]_19 [4]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [4]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [4]),
        .O(rdEn_nxt_inferred_i_48__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__0
       (.I0(\rsMask_reg[6]_20 [3]),
        .I1(\rsMask_reg[4]_18 [3]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[2]_16 [3]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[0]_14 [3]),
        .O(rdEn_nxt_inferred_i_49__0_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__0
       (.I0(\rdEn_reg[14]_0 ),
        .I1(rdEn_nxt_inferred_i_35__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__0
       (.I0(\rsMask_reg[7]_21 [3]),
        .I1(\rsMask_reg[5]_19 [3]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [3]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [3]),
        .O(rdEn_nxt_inferred_i_50__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__0
       (.I0(\rsMask_reg[6]_20 [2]),
        .I1(\rsMask_reg[4]_18 [2]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[2]_16 [2]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[0]_14 [2]),
        .O(rdEn_nxt_inferred_i_51__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__0
       (.I0(\rsMask_reg[7]_21 [2]),
        .I1(\rsMask_reg[5]_19 [2]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [2]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [2]),
        .O(rdEn_nxt_inferred_i_52__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_53__0
       (.I0(\rsMask_reg[7]_21 [1]),
        .I1(\rsMask_reg[5]_19 [1]),
        .I2(\rdEn_reg[14]_1 ),
        .I3(\rsMask_reg[3]_17 [1]),
        .I4(\rdEn_reg[14]_2 ),
        .I5(\rsMask_reg[1]_15 [1]),
        .O(rdEn_nxt_inferred_i_53__0_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__0
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_34__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_36__0_n_0),
        .I4(\rdEn_reg[14]_0 ),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__0
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_35__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_37__0_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__0
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_36__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_38__0_n_0),
        .I4(\rdEn_reg[14]_0 ),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__0
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_39__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_40__0_n_0),
        .I4(\rdEn_reg[14]_0 ),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__0
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_38__0_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_41__0_n_0),
        .I4(\rdEn_reg[14]_0 ),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_upp[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_upp[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_upp[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_upp[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_14 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_14 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_14 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_14 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_2[2]),
        .Q(\rsMask_reg[1]_15 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_2[3]),
        .Q(\rsMask_reg[1]_15 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_2[4]),
        .Q(\rsMask_reg[1]_15 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_15 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_15 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_15 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_15 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_15 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_15 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_15 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_2[0]),
        .Q(\rsMask_reg[1]_15 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_2[1]),
        .Q(\rsMask_reg[1]_15 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_15 [4]),
        .R(\blk1.(null)[0].diff_3 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_15 [5]),
        .R(\blk1.(null)[0].diff_3 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_15 [6]),
        .R(\blk1.(null)[0].diff_3 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_15 [7]),
        .R(\blk1.(null)[0].diff_3 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_15 [8]),
        .R(\blk1.(null)[0].diff_3 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_3 [0]),
        .Q(\rsMask_reg[1]_15 [9]),
        .R(\blk1.(null)[0].diff_3 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_16 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_16 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_16 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_16 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_17 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_17 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_17 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_17 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_17 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_17 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_17 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_17 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_17 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_17 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_17 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_17 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_17 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_17 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_17 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_17 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_17 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_17 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_18 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_18 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_18 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_18 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_19 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_19 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_19 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_19 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_19 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_19 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_19 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_19 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_19 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_19 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_19 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_19 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_19 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_19 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_19 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_19 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_19 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_19 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_20 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_20 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_20 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_20 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_21 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_21 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_21 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_21 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_21 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_21 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_21 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_21 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_21 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_21 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_21 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_21 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_21 [4]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_21 [5]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_21 [6]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_21 [7]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_21 [8]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_2 ),
        .Q(\rsMask_reg[7]_21 [9]),
        .R(\rsMask_reg[7][9]_1 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_19
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_low,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_16,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_17 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_1 ,
    mcalRdCAS,
    mcalCasSlot,
    out,
    mcalRank,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_1 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_low;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[6][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_16;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_17 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_1 ;
  input mcalRdCAS;
  input [0:0]mcalCasSlot;
  input out;
  input [1:0]mcalRank;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_1 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_17 ;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [0:0]mcalCasSlot;
  wire [1:0]mcalRank;
  wire mcalRdCAS;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_33__7_n_0;
  wire rdEn_nxt_inferred_i_34__9_n_0;
  wire rdEn_nxt_inferred_i_35__9_n_0;
  wire rdEn_nxt_inferred_i_36__9_n_0;
  wire rdEn_nxt_inferred_i_37__9_n_0;
  wire rdEn_nxt_inferred_i_38__9_n_0;
  wire rdEn_nxt_inferred_i_39__9_n_0;
  wire rdEn_nxt_inferred_i_40__9_n_0;
  wire rdEn_nxt_inferred_i_41__9_n_0;
  wire rdEn_nxt_inferred_i_42__9_n_0;
  wire rdEn_nxt_inferred_i_43__9_n_0;
  wire rdEn_nxt_inferred_i_44__9_n_0;
  wire rdEn_nxt_inferred_i_45__9_n_0;
  wire rdEn_nxt_inferred_i_46__9_n_0;
  wire rdEn_nxt_inferred_i_47__9_n_0;
  wire rdEn_nxt_inferred_i_48__9_n_0;
  wire rdEn_nxt_inferred_i_49__9_n_0;
  wire rdEn_nxt_inferred_i_50__9_n_0;
  wire rdEn_nxt_inferred_i_51__9_n_0;
  wire rdEn_nxt_inferred_i_52__9_n_0;
  wire [4:0]rs2mask0_16;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_118 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_119 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_120 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_121 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_122 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_123 ;
  wire \rsMask_reg[6][11]_0 ;
  wire \rsMask_reg[6][9]_0 ;
  wire [2:0]\rsMask_reg[6][9]_1 ;
  wire [11:2]\rsMask_reg[6]_124 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire [18:1]\rsMask_reg[7]_125 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__9
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_41__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_42__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__9
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_40__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_43__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__9
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_42__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_44__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__9
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_43__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_45__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__9
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_44__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_46__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__9
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_45__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_47__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__9
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_48__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_49__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__9
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_50__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_51__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__9
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_49__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_52__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__9
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_51__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_52__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__9
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__9
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__9
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__9
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__9
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__9
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__9
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__9
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__9
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__9
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__9
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_31__6
       (.I0(\rsMask_reg[7]_125 [18]),
        .I1(\rsMask_reg[5]_123 [18]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [18]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_32__5
       (.I0(\rsMask_reg[7]_125 [17]),
        .I1(\rsMask_reg[5]_123 [17]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [17]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_33__7
       (.I0(\rsMask_reg[7]_125 [16]),
        .I1(\rsMask_reg[5]_123 [16]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [16]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [16]),
        .O(rdEn_nxt_inferred_i_33__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__9
       (.I0(\rsMask_reg[7]_125 [15]),
        .I1(\rsMask_reg[5]_123 [15]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [15]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [15]),
        .O(rdEn_nxt_inferred_i_34__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__9
       (.I0(\rsMask_reg[7]_125 [14]),
        .I1(\rsMask_reg[5]_123 [14]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [14]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [14]),
        .O(rdEn_nxt_inferred_i_35__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__9
       (.I0(\rsMask_reg[7]_125 [13]),
        .I1(\rsMask_reg[5]_123 [13]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [13]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [13]),
        .O(rdEn_nxt_inferred_i_36__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__9
       (.I0(\rsMask_reg[7]_125 [12]),
        .I1(\rsMask_reg[5]_123 [12]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [12]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [12]),
        .O(rdEn_nxt_inferred_i_37__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__9
       (.I0(\rsMask_reg[6]_124 [11]),
        .I1(\rsMask_reg[4]_122 [11]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_120 [11]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_118 [11]),
        .O(rdEn_nxt_inferred_i_38__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__9
       (.I0(\rsMask_reg[7]_125 [11]),
        .I1(\rsMask_reg[5]_123 [11]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [11]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [11]),
        .O(rdEn_nxt_inferred_i_39__9_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__9
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_33__7_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__9
       (.I0(\rsMask_reg[7]_125 [10]),
        .I1(\rsMask_reg[5]_123 [10]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [10]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [10]),
        .O(rdEn_nxt_inferred_i_40__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__9
       (.I0(\rsMask_reg[6]_124 [9]),
        .I1(\rsMask_reg[4]_122 [9]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_120 [9]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_118 [9]),
        .O(rdEn_nxt_inferred_i_41__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__9
       (.I0(\rsMask_reg[7]_125 [9]),
        .I1(\rsMask_reg[5]_123 [9]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [9]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [9]),
        .O(rdEn_nxt_inferred_i_42__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__9
       (.I0(\rsMask_reg[7]_125 [8]),
        .I1(\rsMask_reg[5]_123 [8]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [8]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [8]),
        .O(rdEn_nxt_inferred_i_43__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__9
       (.I0(\rsMask_reg[7]_125 [7]),
        .I1(\rsMask_reg[5]_123 [7]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [7]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [7]),
        .O(rdEn_nxt_inferred_i_44__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__9
       (.I0(\rsMask_reg[7]_125 [6]),
        .I1(\rsMask_reg[5]_123 [6]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [6]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [6]),
        .O(rdEn_nxt_inferred_i_45__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__9
       (.I0(\rsMask_reg[7]_125 [5]),
        .I1(\rsMask_reg[5]_123 [5]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [5]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [5]),
        .O(rdEn_nxt_inferred_i_46__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__9
       (.I0(\rsMask_reg[7]_125 [4]),
        .I1(\rsMask_reg[5]_123 [4]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [4]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [4]),
        .O(rdEn_nxt_inferred_i_47__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__9
       (.I0(\rsMask_reg[6]_124 [3]),
        .I1(\rsMask_reg[4]_122 [3]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_120 [3]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_118 [3]),
        .O(rdEn_nxt_inferred_i_48__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__9
       (.I0(\rsMask_reg[7]_125 [3]),
        .I1(\rsMask_reg[5]_123 [3]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [3]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [3]),
        .O(rdEn_nxt_inferred_i_49__9_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__9
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_34__9_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__9
       (.I0(\rsMask_reg[6]_124 [2]),
        .I1(\rsMask_reg[4]_122 [2]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_120 [2]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_118 [2]),
        .O(rdEn_nxt_inferred_i_50__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__9
       (.I0(\rsMask_reg[7]_125 [2]),
        .I1(\rsMask_reg[5]_123 [2]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [2]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [2]),
        .O(rdEn_nxt_inferred_i_51__9_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__9
       (.I0(\rsMask_reg[7]_125 [1]),
        .I1(\rsMask_reg[5]_123 [1]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_121 [1]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_119 [1]),
        .O(rdEn_nxt_inferred_i_52__9_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__9
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_33__7_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_35__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__9
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_34__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_36__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__9
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_35__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_37__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__9
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_38__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_39__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__9
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_37__9_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_40__9_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_low[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_low[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_low[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_low[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_118 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_118 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_118 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_118 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_16[2]),
        .Q(\rsMask_reg[1]_119 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_16[3]),
        .Q(\rsMask_reg[1]_119 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_16[4]),
        .Q(\rsMask_reg[1]_119 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_119 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_119 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_119 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_119 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_119 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_119 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_119 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_16[0]),
        .Q(\rsMask_reg[1]_119 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_16[1]),
        .Q(\rsMask_reg[1]_119 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_119 [4]),
        .R(\blk1.(null)[0].diff_17 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_119 [5]),
        .R(\blk1.(null)[0].diff_17 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_119 [6]),
        .R(\blk1.(null)[0].diff_17 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_119 [7]),
        .R(\blk1.(null)[0].diff_17 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_119 [8]),
        .R(\blk1.(null)[0].diff_17 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_17 [0]),
        .Q(\rsMask_reg[1]_119 [9]),
        .R(\blk1.(null)[0].diff_17 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_120 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_120 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_120 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_120 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_121 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_121 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_121 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_121 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_121 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_121 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_121 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_121 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_121 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_121 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_121 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_121 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_121 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_121 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_121 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_121 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_121 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_121 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_122 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_122 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_122 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_122 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_123 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_123 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_123 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_123 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_123 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_123 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_123 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_123 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_123 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_123 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_123 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_123 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_123 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_123 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_123 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_123 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_123 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_123 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_124 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_1 [0]),
        .Q(\rsMask_reg[6]_124 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_1 [1]),
        .Q(\rsMask_reg[6]_124 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_1 [2]),
        .Q(\rsMask_reg[6]_124 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_125 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_125 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_125 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_125 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_125 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_125 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_125 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_125 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_125 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_125 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_125 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_125 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_125 [4]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_125 [5]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_125 [6]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_125 [7]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_125 [8]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[6][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_1 ),
        .Q(\rsMask_reg[7]_125 [9]),
        .R(\rsMask_reg[7][9]_0 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_20
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_upp,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_6,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_7 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_2 ,
    \rdEn_reg[12]_0 ,
    \rdEn_reg[12]_1 ,
    out,
    \rdEn_reg[14]_0 ,
    \rdEn_reg[14]_1 ,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_upp;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_6;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_7 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_1 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_2 ;
  input \rdEn_reg[12]_0 ;
  input \rdEn_reg[12]_1 ;
  input out;
  input \rdEn_reg[14]_0 ;
  input \rdEn_reg[14]_1 ;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_7 ;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_33__1_n_0;
  wire rdEn_nxt_inferred_i_34__2_n_0;
  wire rdEn_nxt_inferred_i_35__2_n_0;
  wire rdEn_nxt_inferred_i_36__2_n_0;
  wire rdEn_nxt_inferred_i_37__2_n_0;
  wire rdEn_nxt_inferred_i_38__2_n_0;
  wire rdEn_nxt_inferred_i_39__2_n_0;
  wire rdEn_nxt_inferred_i_40__2_n_0;
  wire rdEn_nxt_inferred_i_41__2_n_0;
  wire rdEn_nxt_inferred_i_42__2_n_0;
  wire rdEn_nxt_inferred_i_43__2_n_0;
  wire rdEn_nxt_inferred_i_44__2_n_0;
  wire rdEn_nxt_inferred_i_45__2_n_0;
  wire rdEn_nxt_inferred_i_46__2_n_0;
  wire rdEn_nxt_inferred_i_47__2_n_0;
  wire rdEn_nxt_inferred_i_48__2_n_0;
  wire rdEn_nxt_inferred_i_49__2_n_0;
  wire rdEn_nxt_inferred_i_50__2_n_0;
  wire rdEn_nxt_inferred_i_51__2_n_0;
  wire rdEn_nxt_inferred_i_52__2_n_0;
  wire \rdEn_reg[12]_0 ;
  wire \rdEn_reg[12]_1 ;
  wire \rdEn_reg[14]_0 ;
  wire \rdEn_reg[14]_1 ;
  wire [4:0]rs2mask0_6;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_62 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_63 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_64 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_65 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_66 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_67 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_68 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire \rsMask_reg[7][9]_2 ;
  wire [18:1]\rsMask_reg[7]_69 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__2
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_41__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_42__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__2
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_40__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_43__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__2
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_42__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_44__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__2
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_43__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_45__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__2
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_44__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_46__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__2
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_45__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_47__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__2
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_48__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_49__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__2
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_50__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_51__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__2
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_49__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_52__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__2
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_51__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_52__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__2
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__2
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__2
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__2
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__2
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__2
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__2
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__2
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__2
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__2
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__2
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_31__1
       (.I0(\rsMask_reg[7]_69 [18]),
        .I1(\rsMask_reg[5]_67 [18]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [18]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_32__1
       (.I0(\rsMask_reg[7]_69 [17]),
        .I1(\rsMask_reg[5]_67 [17]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [17]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_33__1
       (.I0(\rsMask_reg[7]_69 [16]),
        .I1(\rsMask_reg[5]_67 [16]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [16]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [16]),
        .O(rdEn_nxt_inferred_i_33__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__2
       (.I0(\rsMask_reg[7]_69 [15]),
        .I1(\rsMask_reg[5]_67 [15]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [15]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [15]),
        .O(rdEn_nxt_inferred_i_34__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__2
       (.I0(\rsMask_reg[7]_69 [14]),
        .I1(\rsMask_reg[5]_67 [14]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [14]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [14]),
        .O(rdEn_nxt_inferred_i_35__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__2
       (.I0(\rsMask_reg[7]_69 [13]),
        .I1(\rsMask_reg[5]_67 [13]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [13]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [13]),
        .O(rdEn_nxt_inferred_i_36__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__2
       (.I0(\rsMask_reg[7]_69 [12]),
        .I1(\rsMask_reg[5]_67 [12]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [12]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [12]),
        .O(rdEn_nxt_inferred_i_37__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__2
       (.I0(\rsMask_reg[6]_68 [11]),
        .I1(\rsMask_reg[4]_66 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_64 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_62 [11]),
        .O(rdEn_nxt_inferred_i_38__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__2
       (.I0(\rsMask_reg[7]_69 [11]),
        .I1(\rsMask_reg[5]_67 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [11]),
        .O(rdEn_nxt_inferred_i_39__2_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__2
       (.I0(\rdEn_reg[12]_0 ),
        .I1(rdEn_nxt_inferred_i_33__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__2
       (.I0(\rsMask_reg[7]_69 [10]),
        .I1(\rsMask_reg[5]_67 [10]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [10]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [10]),
        .O(rdEn_nxt_inferred_i_40__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__2
       (.I0(\rsMask_reg[6]_68 [9]),
        .I1(\rsMask_reg[4]_66 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_64 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_62 [9]),
        .O(rdEn_nxt_inferred_i_41__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__2
       (.I0(\rsMask_reg[7]_69 [9]),
        .I1(\rsMask_reg[5]_67 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [9]),
        .O(rdEn_nxt_inferred_i_42__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__2
       (.I0(\rsMask_reg[7]_69 [8]),
        .I1(\rsMask_reg[5]_67 [8]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [8]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [8]),
        .O(rdEn_nxt_inferred_i_43__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__2
       (.I0(\rsMask_reg[7]_69 [7]),
        .I1(\rsMask_reg[5]_67 [7]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [7]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [7]),
        .O(rdEn_nxt_inferred_i_44__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__2
       (.I0(\rsMask_reg[7]_69 [6]),
        .I1(\rsMask_reg[5]_67 [6]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [6]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [6]),
        .O(rdEn_nxt_inferred_i_45__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__2
       (.I0(\rsMask_reg[7]_69 [5]),
        .I1(\rsMask_reg[5]_67 [5]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [5]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [5]),
        .O(rdEn_nxt_inferred_i_46__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__2
       (.I0(\rsMask_reg[7]_69 [4]),
        .I1(\rsMask_reg[5]_67 [4]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [4]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [4]),
        .O(rdEn_nxt_inferred_i_47__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__2
       (.I0(\rsMask_reg[6]_68 [3]),
        .I1(\rsMask_reg[4]_66 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_64 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_62 [3]),
        .O(rdEn_nxt_inferred_i_48__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__2
       (.I0(\rsMask_reg[7]_69 [3]),
        .I1(\rsMask_reg[5]_67 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [3]),
        .O(rdEn_nxt_inferred_i_49__2_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__2
       (.I0(\rdEn_reg[12]_0 ),
        .I1(rdEn_nxt_inferred_i_34__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__2
       (.I0(\rsMask_reg[6]_68 [2]),
        .I1(\rsMask_reg[4]_66 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_64 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_62 [2]),
        .O(rdEn_nxt_inferred_i_50__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__2
       (.I0(\rsMask_reg[7]_69 [2]),
        .I1(\rsMask_reg[5]_67 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [2]),
        .O(rdEn_nxt_inferred_i_51__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__2
       (.I0(\rsMask_reg[7]_69 [1]),
        .I1(\rsMask_reg[5]_67 [1]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_65 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_63 [1]),
        .O(rdEn_nxt_inferred_i_52__2_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__2
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_33__1_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_35__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__2
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_34__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_36__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__2
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_35__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_37__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__2
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_38__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_39__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__2
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_37__2_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_40__2_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_upp[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_upp[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_upp[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_upp[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_62 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_62 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_62 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_62 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_6[2]),
        .Q(\rsMask_reg[1]_63 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_6[3]),
        .Q(\rsMask_reg[1]_63 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_6[4]),
        .Q(\rsMask_reg[1]_63 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_63 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_63 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_63 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_63 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_63 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_63 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_63 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_6[0]),
        .Q(\rsMask_reg[1]_63 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_6[1]),
        .Q(\rsMask_reg[1]_63 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_63 [4]),
        .R(\blk1.(null)[0].diff_7 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_63 [5]),
        .R(\blk1.(null)[0].diff_7 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_63 [6]),
        .R(\blk1.(null)[0].diff_7 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_63 [7]),
        .R(\blk1.(null)[0].diff_7 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_63 [8]),
        .R(\blk1.(null)[0].diff_7 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_7 [0]),
        .Q(\rsMask_reg[1]_63 [9]),
        .R(\blk1.(null)[0].diff_7 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_64 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_64 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_64 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_64 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_65 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_65 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_65 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_65 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_65 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_65 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_65 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_65 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_65 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_65 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_65 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_65 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_65 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_65 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_65 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_65 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_65 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_65 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_66 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_66 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_66 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_66 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_67 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_67 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_67 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_67 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_67 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_67 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_67 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_67 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_67 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_67 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_67 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_67 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_67 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_67 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_67 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_67 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_67 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_67 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_68 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_68 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_68 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_68 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_69 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_69 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_69 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_69 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_69 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_69 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_69 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_69 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_69 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_69 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_69 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_69 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_69 [4]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_69 [5]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_69 [6]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_69 [7]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_69 [8]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_2 ),
        .Q(\rsMask_reg[7]_69 [9]),
        .R(\rsMask_reg[7][9]_1 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_21
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_low,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_14,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_1 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_15 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_1 ,
    mcalRdCAS,
    mcalCasSlot,
    out,
    mcalRank,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_low;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_14;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_1 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_15 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_1 ;
  input mcalRdCAS;
  input [0:0]mcalCasSlot;
  input out;
  input [1:0]mcalRank;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_15 ;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [0:0]mcalCasSlot;
  wire [1:0]mcalRank;
  wire mcalRdCAS;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_35__8_n_0;
  wire rdEn_nxt_inferred_i_36__8_n_0;
  wire rdEn_nxt_inferred_i_37__8_n_0;
  wire rdEn_nxt_inferred_i_38__8_n_0;
  wire rdEn_nxt_inferred_i_39__8_n_0;
  wire rdEn_nxt_inferred_i_40__8_n_0;
  wire rdEn_nxt_inferred_i_41__8_n_0;
  wire rdEn_nxt_inferred_i_42__8_n_0;
  wire rdEn_nxt_inferred_i_43__8_n_0;
  wire rdEn_nxt_inferred_i_44__8_n_0;
  wire rdEn_nxt_inferred_i_45__8_n_0;
  wire rdEn_nxt_inferred_i_46__8_n_0;
  wire rdEn_nxt_inferred_i_47__8_n_0;
  wire rdEn_nxt_inferred_i_48__8_n_0;
  wire rdEn_nxt_inferred_i_49__8_n_0;
  wire rdEn_nxt_inferred_i_50__8_n_0;
  wire rdEn_nxt_inferred_i_51__8_n_0;
  wire rdEn_nxt_inferred_i_52__8_n_0;
  wire rdEn_nxt_inferred_i_53__4_n_0;
  wire rdEn_nxt_inferred_i_54__2_n_0;
  wire [4:0]rs2mask0_14;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_110 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_111 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_112 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_113 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_114 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_115 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_116 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][12]_1 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire [18:1]\rsMask_reg[7]_117 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__8
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_43__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_44__8_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__8
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_42__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_45__8_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__8
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_44__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_46__8_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__8
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_45__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_47__8_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__8
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_46__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_48__8_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__8
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_47__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_49__8_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__8
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_50__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_51__8_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__8
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_52__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_53__4_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__8
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_51__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_54__2_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__8
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_53__4_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_54__2_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__8
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__8
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__8
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__8
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__8
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__8
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__8
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__8
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__8
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__8
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__8
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_32__4
       (.I0(\rsMask_reg[7]_117 [18]),
        .I1(\rsMask_reg[5]_115 [18]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [18]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__8
       (.I0(\rsMask_reg[7]_117 [17]),
        .I1(\rsMask_reg[5]_115 [17]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [17]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__8
       (.I0(\rsMask_reg[7]_117 [16]),
        .I1(\rsMask_reg[5]_115 [16]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [16]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [16]),
        .O(rdEn_nxt_inferred_i_35__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__8
       (.I0(\rsMask_reg[7]_117 [15]),
        .I1(\rsMask_reg[5]_115 [15]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [15]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [15]),
        .O(rdEn_nxt_inferred_i_36__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__8
       (.I0(\rsMask_reg[7]_117 [14]),
        .I1(\rsMask_reg[5]_115 [14]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [14]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [14]),
        .O(rdEn_nxt_inferred_i_37__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__8
       (.I0(\rsMask_reg[7]_117 [13]),
        .I1(\rsMask_reg[5]_115 [13]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [13]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [13]),
        .O(rdEn_nxt_inferred_i_38__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__8
       (.I0(\rsMask_reg[7]_117 [12]),
        .I1(\rsMask_reg[5]_115 [12]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [12]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [12]),
        .O(rdEn_nxt_inferred_i_39__8_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__8
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_35__8_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__8
       (.I0(\rsMask_reg[6]_116 [11]),
        .I1(\rsMask_reg[4]_114 [11]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_112 [11]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_110 [11]),
        .O(rdEn_nxt_inferred_i_40__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__8
       (.I0(\rsMask_reg[7]_117 [11]),
        .I1(\rsMask_reg[5]_115 [11]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [11]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [11]),
        .O(rdEn_nxt_inferred_i_41__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__8
       (.I0(\rsMask_reg[7]_117 [10]),
        .I1(\rsMask_reg[5]_115 [10]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [10]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [10]),
        .O(rdEn_nxt_inferred_i_42__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__8
       (.I0(\rsMask_reg[6]_116 [9]),
        .I1(\rsMask_reg[4]_114 [9]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_112 [9]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_110 [9]),
        .O(rdEn_nxt_inferred_i_43__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__8
       (.I0(\rsMask_reg[7]_117 [9]),
        .I1(\rsMask_reg[5]_115 [9]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [9]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [9]),
        .O(rdEn_nxt_inferred_i_44__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__8
       (.I0(\rsMask_reg[7]_117 [8]),
        .I1(\rsMask_reg[5]_115 [8]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [8]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [8]),
        .O(rdEn_nxt_inferred_i_45__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__8
       (.I0(\rsMask_reg[7]_117 [7]),
        .I1(\rsMask_reg[5]_115 [7]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [7]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [7]),
        .O(rdEn_nxt_inferred_i_46__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__8
       (.I0(\rsMask_reg[7]_117 [6]),
        .I1(\rsMask_reg[5]_115 [6]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [6]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [6]),
        .O(rdEn_nxt_inferred_i_47__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__8
       (.I0(\rsMask_reg[7]_117 [5]),
        .I1(\rsMask_reg[5]_115 [5]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [5]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [5]),
        .O(rdEn_nxt_inferred_i_48__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__8
       (.I0(\rsMask_reg[7]_117 [4]),
        .I1(\rsMask_reg[5]_115 [4]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [4]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [4]),
        .O(rdEn_nxt_inferred_i_49__8_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__8
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_36__8_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__8
       (.I0(\rsMask_reg[6]_116 [3]),
        .I1(\rsMask_reg[4]_114 [3]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_112 [3]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_110 [3]),
        .O(rdEn_nxt_inferred_i_50__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__8
       (.I0(\rsMask_reg[7]_117 [3]),
        .I1(\rsMask_reg[5]_115 [3]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [3]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [3]),
        .O(rdEn_nxt_inferred_i_51__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__8
       (.I0(\rsMask_reg[6]_116 [2]),
        .I1(\rsMask_reg[4]_114 [2]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[2]_112 [2]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[0]_110 [2]),
        .O(rdEn_nxt_inferred_i_52__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_53__4
       (.I0(\rsMask_reg[7]_117 [2]),
        .I1(\rsMask_reg[5]_115 [2]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [2]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [2]),
        .O(rdEn_nxt_inferred_i_53__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_54__2
       (.I0(\rsMask_reg[7]_117 [1]),
        .I1(\rsMask_reg[5]_115 [1]),
        .I2(mcalRank[1]),
        .I3(\rsMask_reg[3]_113 [1]),
        .I4(mcalRank[0]),
        .I5(\rsMask_reg[1]_111 [1]),
        .O(rdEn_nxt_inferred_i_54__2_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__8
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_35__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_37__8_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__8
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_36__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_38__8_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__8
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_37__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_39__8_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__8
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_40__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_41__8_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__8
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_39__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_42__8_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_low[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_low[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_low[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_low[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_110 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_110 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_110 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_110 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rs2mask0_14[2]),
        .Q(\rsMask_reg[1]_111 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rs2mask0_14[3]),
        .Q(\rsMask_reg[1]_111 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rs2mask0_14[4]),
        .Q(\rsMask_reg[1]_111 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_111 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_111 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_111 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_111 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_111 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_111 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_111 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rs2mask0_14[0]),
        .Q(\rsMask_reg[1]_111 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rs2mask0_14[1]),
        .Q(\rsMask_reg[1]_111 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_111 [4]),
        .R(\blk1.(null)[0].diff_15 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_111 [5]),
        .R(\blk1.(null)[0].diff_15 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_111 [6]),
        .R(\blk1.(null)[0].diff_15 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_111 [7]),
        .R(\blk1.(null)[0].diff_15 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_111 [8]),
        .R(\blk1.(null)[0].diff_15 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_15 [0]),
        .Q(\rsMask_reg[1]_111 [9]),
        .R(\blk1.(null)[0].diff_15 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_112 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_112 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_112 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_112 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_113 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_113 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_113 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_113 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_113 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_113 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_113 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_113 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_113 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_113 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_113 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_113 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_113 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_113 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_113 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_113 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_113 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_113 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_114 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_114 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_114 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_114 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_115 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_115 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_115 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_115 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_115 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_115 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_115 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_115 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_115 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_115 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_115 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_115 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_115 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_115 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_115 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_115 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_115 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_115 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_116 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_116 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_116 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_116 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_117 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_117 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_1 ),
        .Q(\rsMask_reg[7]_117 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_117 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_117 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_117 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_117 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_117 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_117 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_117 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_117 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_117 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_117 [4]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_117 [5]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_117 [6]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_117 [7]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_117 [8]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_1 ),
        .Q(\rsMask_reg[7]_117 [9]),
        .R(\rsMask_reg[7][9]_0 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_22
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_upp,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_12,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_13 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_2 ,
    \rdEn_reg[12]_0 ,
    \rdEn_reg[12]_1 ,
    out,
    \rdEn_reg[14]_0 ,
    \rdEn_reg[14]_1 ,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_upp;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_12;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_13 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_1 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_2 ;
  input \rdEn_reg[12]_0 ;
  input \rdEn_reg[12]_1 ;
  input out;
  input \rdEn_reg[14]_0 ;
  input \rdEn_reg[14]_1 ;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_13 ;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_33__6_n_0;
  wire rdEn_nxt_inferred_i_34__7_n_0;
  wire rdEn_nxt_inferred_i_35__7_n_0;
  wire rdEn_nxt_inferred_i_36__7_n_0;
  wire rdEn_nxt_inferred_i_37__7_n_0;
  wire rdEn_nxt_inferred_i_38__7_n_0;
  wire rdEn_nxt_inferred_i_39__7_n_0;
  wire rdEn_nxt_inferred_i_40__7_n_0;
  wire rdEn_nxt_inferred_i_41__7_n_0;
  wire rdEn_nxt_inferred_i_42__7_n_0;
  wire rdEn_nxt_inferred_i_43__7_n_0;
  wire rdEn_nxt_inferred_i_44__7_n_0;
  wire rdEn_nxt_inferred_i_45__7_n_0;
  wire rdEn_nxt_inferred_i_46__7_n_0;
  wire rdEn_nxt_inferred_i_47__7_n_0;
  wire rdEn_nxt_inferred_i_48__7_n_0;
  wire rdEn_nxt_inferred_i_49__7_n_0;
  wire rdEn_nxt_inferred_i_50__7_n_0;
  wire rdEn_nxt_inferred_i_51__7_n_0;
  wire rdEn_nxt_inferred_i_52__7_n_0;
  wire \rdEn_reg[12]_0 ;
  wire \rdEn_reg[12]_1 ;
  wire \rdEn_reg[14]_0 ;
  wire \rdEn_reg[14]_1 ;
  wire [4:0]rs2mask0_12;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_102 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_103 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_104 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_105 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_106 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_107 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_108 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire \rsMask_reg[7][9]_2 ;
  wire [18:1]\rsMask_reg[7]_109 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__7
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_41__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_42__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__7
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_40__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_43__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__7
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_42__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_44__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__7
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_43__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_45__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__7
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_44__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_46__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__7
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_45__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_47__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__7
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_48__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_49__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__7
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_50__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_51__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__7
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_49__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_52__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__7
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_51__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_52__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__7
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__7
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__7
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__7
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__7
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__7
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__7
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__7
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__7
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__7
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__7
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_31__5
       (.I0(\rsMask_reg[7]_109 [18]),
        .I1(\rsMask_reg[5]_107 [18]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [18]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_32__3
       (.I0(\rsMask_reg[7]_109 [17]),
        .I1(\rsMask_reg[5]_107 [17]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [17]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_33__6
       (.I0(\rsMask_reg[7]_109 [16]),
        .I1(\rsMask_reg[5]_107 [16]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [16]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [16]),
        .O(rdEn_nxt_inferred_i_33__6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__7
       (.I0(\rsMask_reg[7]_109 [15]),
        .I1(\rsMask_reg[5]_107 [15]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [15]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [15]),
        .O(rdEn_nxt_inferred_i_34__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__7
       (.I0(\rsMask_reg[7]_109 [14]),
        .I1(\rsMask_reg[5]_107 [14]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [14]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [14]),
        .O(rdEn_nxt_inferred_i_35__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__7
       (.I0(\rsMask_reg[7]_109 [13]),
        .I1(\rsMask_reg[5]_107 [13]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [13]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [13]),
        .O(rdEn_nxt_inferred_i_36__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__7
       (.I0(\rsMask_reg[7]_109 [12]),
        .I1(\rsMask_reg[5]_107 [12]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [12]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [12]),
        .O(rdEn_nxt_inferred_i_37__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__7
       (.I0(\rsMask_reg[6]_108 [11]),
        .I1(\rsMask_reg[4]_106 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_104 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_102 [11]),
        .O(rdEn_nxt_inferred_i_38__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__7
       (.I0(\rsMask_reg[7]_109 [11]),
        .I1(\rsMask_reg[5]_107 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [11]),
        .O(rdEn_nxt_inferred_i_39__7_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__7
       (.I0(\rdEn_reg[12]_0 ),
        .I1(rdEn_nxt_inferred_i_33__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__7
       (.I0(\rsMask_reg[7]_109 [10]),
        .I1(\rsMask_reg[5]_107 [10]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [10]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [10]),
        .O(rdEn_nxt_inferred_i_40__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__7
       (.I0(\rsMask_reg[6]_108 [9]),
        .I1(\rsMask_reg[4]_106 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_104 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_102 [9]),
        .O(rdEn_nxt_inferred_i_41__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__7
       (.I0(\rsMask_reg[7]_109 [9]),
        .I1(\rsMask_reg[5]_107 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [9]),
        .O(rdEn_nxt_inferred_i_42__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__7
       (.I0(\rsMask_reg[7]_109 [8]),
        .I1(\rsMask_reg[5]_107 [8]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [8]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [8]),
        .O(rdEn_nxt_inferred_i_43__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__7
       (.I0(\rsMask_reg[7]_109 [7]),
        .I1(\rsMask_reg[5]_107 [7]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [7]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [7]),
        .O(rdEn_nxt_inferred_i_44__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__7
       (.I0(\rsMask_reg[7]_109 [6]),
        .I1(\rsMask_reg[5]_107 [6]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [6]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [6]),
        .O(rdEn_nxt_inferred_i_45__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__7
       (.I0(\rsMask_reg[7]_109 [5]),
        .I1(\rsMask_reg[5]_107 [5]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [5]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [5]),
        .O(rdEn_nxt_inferred_i_46__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__7
       (.I0(\rsMask_reg[7]_109 [4]),
        .I1(\rsMask_reg[5]_107 [4]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [4]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [4]),
        .O(rdEn_nxt_inferred_i_47__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__7
       (.I0(\rsMask_reg[6]_108 [3]),
        .I1(\rsMask_reg[4]_106 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_104 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_102 [3]),
        .O(rdEn_nxt_inferred_i_48__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__7
       (.I0(\rsMask_reg[7]_109 [3]),
        .I1(\rsMask_reg[5]_107 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [3]),
        .O(rdEn_nxt_inferred_i_49__7_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__7
       (.I0(\rdEn_reg[12]_0 ),
        .I1(rdEn_nxt_inferred_i_34__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__7
       (.I0(\rsMask_reg[6]_108 [2]),
        .I1(\rsMask_reg[4]_106 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_104 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_102 [2]),
        .O(rdEn_nxt_inferred_i_50__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__7
       (.I0(\rsMask_reg[7]_109 [2]),
        .I1(\rsMask_reg[5]_107 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [2]),
        .O(rdEn_nxt_inferred_i_51__7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__7
       (.I0(\rsMask_reg[7]_109 [1]),
        .I1(\rsMask_reg[5]_107 [1]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_105 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_103 [1]),
        .O(rdEn_nxt_inferred_i_52__7_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__7
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_33__6_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_35__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__7
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_34__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_36__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__7
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_35__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_37__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__7
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_38__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_39__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__7
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_37__7_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_40__7_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_upp[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_upp[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_upp[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_upp[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_102 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_102 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_102 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_102 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_12[2]),
        .Q(\rsMask_reg[1]_103 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_12[3]),
        .Q(\rsMask_reg[1]_103 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_12[4]),
        .Q(\rsMask_reg[1]_103 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_103 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_103 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_103 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_103 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_103 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_103 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_103 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_12[0]),
        .Q(\rsMask_reg[1]_103 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_12[1]),
        .Q(\rsMask_reg[1]_103 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_103 [4]),
        .R(\blk1.(null)[0].diff_13 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_103 [5]),
        .R(\blk1.(null)[0].diff_13 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_103 [6]),
        .R(\blk1.(null)[0].diff_13 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_103 [7]),
        .R(\blk1.(null)[0].diff_13 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_103 [8]),
        .R(\blk1.(null)[0].diff_13 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_13 [0]),
        .Q(\rsMask_reg[1]_103 [9]),
        .R(\blk1.(null)[0].diff_13 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_104 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_104 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_104 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_104 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_105 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_105 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_105 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_105 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_105 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_105 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_105 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_105 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_105 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_105 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_105 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_105 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_105 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_105 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_105 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_105 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_105 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_105 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_106 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_106 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_106 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_106 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_107 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_107 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_107 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_107 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_107 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_107 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_107 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_107 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_107 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_107 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_107 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_107 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_107 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_107 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_107 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_107 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_107 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_107 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_108 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_108 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_108 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_108 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_109 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_109 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_109 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_109 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_109 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_109 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_109 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_109 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_109 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_109 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_109 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_109 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_109 [4]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_109 [5]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_109 [6]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_109 [7]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_109 [8]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_2 ),
        .Q(\rsMask_reg[7]_109 [9]),
        .R(\rsMask_reg[7][9]_1 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_23
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_low,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_18,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_1 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_19 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_1 ,
    mcalRdCAS,
    mcalCasSlot,
    out,
    \rdEn_reg[14]_0 ,
    \rdEn_reg[14]_1 ,
    \rdEn_reg[12]_0 ,
    \rdEn_reg[12]_1 ,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_low;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_18;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_1 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_19 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_1 ;
  input mcalRdCAS;
  input [0:0]mcalCasSlot;
  input out;
  input \rdEn_reg[14]_0 ;
  input \rdEn_reg[14]_1 ;
  input \rdEn_reg[12]_0 ;
  input \rdEn_reg[12]_1 ;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_19 ;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire [0:0]mcalCasSlot;
  wire mcalRdCAS;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_33__8_n_0;
  wire rdEn_nxt_inferred_i_34__10_n_0;
  wire rdEn_nxt_inferred_i_35__10_n_0;
  wire rdEn_nxt_inferred_i_36__10_n_0;
  wire rdEn_nxt_inferred_i_37__10_n_0;
  wire rdEn_nxt_inferred_i_38__10_n_0;
  wire rdEn_nxt_inferred_i_39__10_n_0;
  wire rdEn_nxt_inferred_i_40__10_n_0;
  wire rdEn_nxt_inferred_i_41__10_n_0;
  wire rdEn_nxt_inferred_i_42__10_n_0;
  wire rdEn_nxt_inferred_i_43__10_n_0;
  wire rdEn_nxt_inferred_i_44__10_n_0;
  wire rdEn_nxt_inferred_i_45__10_n_0;
  wire rdEn_nxt_inferred_i_46__10_n_0;
  wire rdEn_nxt_inferred_i_47__10_n_0;
  wire rdEn_nxt_inferred_i_48__10_n_0;
  wire rdEn_nxt_inferred_i_49__10_n_0;
  wire rdEn_nxt_inferred_i_50__10_n_0;
  wire rdEn_nxt_inferred_i_51__10_n_0;
  wire rdEn_nxt_inferred_i_52__10_n_0;
  wire \rdEn_reg[12]_0 ;
  wire \rdEn_reg[12]_1 ;
  wire \rdEn_reg[14]_0 ;
  wire \rdEn_reg[14]_1 ;
  wire [4:0]rs2mask0_18;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_126 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_127 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_128 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_129 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_130 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_131 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_132 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][12]_1 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire [18:1]\rsMask_reg[7]_133 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__10
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_41__10_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_42__10_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__10
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_40__10_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_43__10_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__10
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_42__10_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_44__10_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__10
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_43__10_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_45__10_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__10
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_44__10_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_46__10_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__10
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_45__10_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_47__10_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__10
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_48__10_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_49__10_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__10
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_50__10_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_51__10_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__10
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_49__10_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_52__10_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__10
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_51__10_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_52__10_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__10
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__10
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__10
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__10
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__10
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__10
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__10
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__10
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__10
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__10
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__10
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_31__7
       (.I0(\rsMask_reg[7]_133 [18]),
        .I1(\rsMask_reg[5]_131 [18]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [18]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_32__6
       (.I0(\rsMask_reg[7]_133 [17]),
        .I1(\rsMask_reg[5]_131 [17]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [17]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_33__8
       (.I0(\rsMask_reg[7]_133 [16]),
        .I1(\rsMask_reg[5]_131 [16]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [16]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [16]),
        .O(rdEn_nxt_inferred_i_33__8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__10
       (.I0(\rsMask_reg[7]_133 [15]),
        .I1(\rsMask_reg[5]_131 [15]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [15]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [15]),
        .O(rdEn_nxt_inferred_i_34__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__10
       (.I0(\rsMask_reg[7]_133 [14]),
        .I1(\rsMask_reg[5]_131 [14]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [14]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [14]),
        .O(rdEn_nxt_inferred_i_35__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__10
       (.I0(\rsMask_reg[7]_133 [13]),
        .I1(\rsMask_reg[5]_131 [13]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [13]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [13]),
        .O(rdEn_nxt_inferred_i_36__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__10
       (.I0(\rsMask_reg[7]_133 [12]),
        .I1(\rsMask_reg[5]_131 [12]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [12]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [12]),
        .O(rdEn_nxt_inferred_i_37__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__10
       (.I0(\rsMask_reg[6]_132 [11]),
        .I1(\rsMask_reg[4]_130 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_128 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_126 [11]),
        .O(rdEn_nxt_inferred_i_38__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__10
       (.I0(\rsMask_reg[7]_133 [11]),
        .I1(\rsMask_reg[5]_131 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [11]),
        .O(rdEn_nxt_inferred_i_39__10_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__10
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_33__8_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__10
       (.I0(\rsMask_reg[7]_133 [10]),
        .I1(\rsMask_reg[5]_131 [10]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [10]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [10]),
        .O(rdEn_nxt_inferred_i_40__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__10
       (.I0(\rsMask_reg[6]_132 [9]),
        .I1(\rsMask_reg[4]_130 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_128 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_126 [9]),
        .O(rdEn_nxt_inferred_i_41__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__10
       (.I0(\rsMask_reg[7]_133 [9]),
        .I1(\rsMask_reg[5]_131 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [9]),
        .O(rdEn_nxt_inferred_i_42__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__10
       (.I0(\rsMask_reg[7]_133 [8]),
        .I1(\rsMask_reg[5]_131 [8]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [8]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [8]),
        .O(rdEn_nxt_inferred_i_43__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__10
       (.I0(\rsMask_reg[7]_133 [7]),
        .I1(\rsMask_reg[5]_131 [7]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [7]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [7]),
        .O(rdEn_nxt_inferred_i_44__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__10
       (.I0(\rsMask_reg[7]_133 [6]),
        .I1(\rsMask_reg[5]_131 [6]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [6]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [6]),
        .O(rdEn_nxt_inferred_i_45__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__10
       (.I0(\rsMask_reg[7]_133 [5]),
        .I1(\rsMask_reg[5]_131 [5]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [5]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [5]),
        .O(rdEn_nxt_inferred_i_46__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__10
       (.I0(\rsMask_reg[7]_133 [4]),
        .I1(\rsMask_reg[5]_131 [4]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [4]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [4]),
        .O(rdEn_nxt_inferred_i_47__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__10
       (.I0(\rsMask_reg[6]_132 [3]),
        .I1(\rsMask_reg[4]_130 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_128 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_126 [3]),
        .O(rdEn_nxt_inferred_i_48__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__10
       (.I0(\rsMask_reg[7]_133 [3]),
        .I1(\rsMask_reg[5]_131 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [3]),
        .O(rdEn_nxt_inferred_i_49__10_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__10
       (.I0(mcalRdCAS),
        .I1(rdEn_nxt_inferred_i_34__10_n_0),
        .I2(mcalCasSlot),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__10
       (.I0(\rsMask_reg[6]_132 [2]),
        .I1(\rsMask_reg[4]_130 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_128 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_126 [2]),
        .O(rdEn_nxt_inferred_i_50__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__10
       (.I0(\rsMask_reg[7]_133 [2]),
        .I1(\rsMask_reg[5]_131 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [2]),
        .O(rdEn_nxt_inferred_i_51__10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__10
       (.I0(\rsMask_reg[7]_133 [1]),
        .I1(\rsMask_reg[5]_131 [1]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_129 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_127 [1]),
        .O(rdEn_nxt_inferred_i_52__10_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__10
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_33__8_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_35__10_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__10
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_34__10_n_0),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_36__10_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__10
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_35__10_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_37__10_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__10
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_38__10_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_39__10_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__10
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_37__10_n_0),
        .I2(mcalCasSlot),
        .I3(rdEn_nxt_inferred_i_40__10_n_0),
        .I4(mcalRdCAS),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_low[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_low[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_low[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_low[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_126 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_126 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_126 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_126 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rs2mask0_18[2]),
        .Q(\rsMask_reg[1]_127 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rs2mask0_18[3]),
        .Q(\rsMask_reg[1]_127 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rs2mask0_18[4]),
        .Q(\rsMask_reg[1]_127 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_127 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_127 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_127 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_127 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_127 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_127 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_127 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rs2mask0_18[0]),
        .Q(\rsMask_reg[1]_127 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rs2mask0_18[1]),
        .Q(\rsMask_reg[1]_127 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_127 [4]),
        .R(\blk1.(null)[0].diff_19 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_127 [5]),
        .R(\blk1.(null)[0].diff_19 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_127 [6]),
        .R(\blk1.(null)[0].diff_19 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_127 [7]),
        .R(\blk1.(null)[0].diff_19 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_127 [8]),
        .R(\blk1.(null)[0].diff_19 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_19 [0]),
        .Q(\rsMask_reg[1]_127 [9]),
        .R(\blk1.(null)[0].diff_19 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_128 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_128 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_128 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_128 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_129 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_129 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_129 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_129 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_129 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_129 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_129 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_129 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_129 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_129 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_129 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_129 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_129 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_129 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_129 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_129 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_129 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_129 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_130 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_130 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_130 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_130 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_131 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_131 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_131 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_131 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_131 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_131 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_131 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_131 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_131 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_131 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_131 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_131 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_131 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_131 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_131 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_131 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_131 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_131 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_132 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_132 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_132 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_132 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_133 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_133 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_1 ),
        .Q(\rsMask_reg[7]_133 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_133 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_133 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_133 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_133 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_133 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_133 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_133 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_133 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_133 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_133 [4]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_133 [5]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_133 [6]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_133 [7]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_133 [8]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_1 ),
        .Q(\rsMask_reg[7]_133 [9]),
        .R(\rsMask_reg[7][9]_0 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_24
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_upp,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_1 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_2 ,
    \rdEn_reg[12]_0 ,
    \rdEn_reg[12]_1 ,
    out,
    \rdEn_reg[14]_0 ,
    \rdEn_reg[14]_1 ,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_upp;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_1 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_1 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_2 ;
  input \rdEn_reg[12]_0 ;
  input \rdEn_reg[12]_1 ;
  input out;
  input \rdEn_reg[14]_0 ;
  input \rdEn_reg[14]_1 ;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_1 ;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_35_n_0;
  wire rdEn_nxt_inferred_i_36_n_0;
  wire rdEn_nxt_inferred_i_37_n_0;
  wire rdEn_nxt_inferred_i_38_n_0;
  wire rdEn_nxt_inferred_i_39_n_0;
  wire rdEn_nxt_inferred_i_40_n_0;
  wire rdEn_nxt_inferred_i_41_n_0;
  wire rdEn_nxt_inferred_i_42_n_0;
  wire rdEn_nxt_inferred_i_43_n_0;
  wire rdEn_nxt_inferred_i_44_n_0;
  wire rdEn_nxt_inferred_i_45_n_0;
  wire rdEn_nxt_inferred_i_46_n_0;
  wire rdEn_nxt_inferred_i_47_n_0;
  wire rdEn_nxt_inferred_i_48_n_0;
  wire rdEn_nxt_inferred_i_49_n_0;
  wire rdEn_nxt_inferred_i_50_n_0;
  wire rdEn_nxt_inferred_i_51_n_0;
  wire rdEn_nxt_inferred_i_52_n_0;
  wire rdEn_nxt_inferred_i_53_n_0;
  wire rdEn_nxt_inferred_i_54_n_0;
  wire \rdEn_reg[12]_0 ;
  wire \rdEn_reg[12]_1 ;
  wire \rdEn_reg[14]_0 ;
  wire \rdEn_reg[14]_1 ;
  wire [4:0]rs2mask0;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_3 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_4 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_5 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_6 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_7 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_8 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_9 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire \rsMask_reg[7][9]_2 ;
  wire [18:1]\rsMask_reg[7]_10 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_43_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_44_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_42_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_45_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_44_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_46_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_45_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_47_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_46_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_48_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_47_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_49_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_50_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_51_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_52_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_53_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_51_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_54_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_53_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_54_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3
       (.I0(\rdEn_reg[12]_0 ),
        .I1(rdEn_nxt_inferred_i_35_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_32
       (.I0(\rsMask_reg[7]_10 [18]),
        .I1(\rsMask_reg[5]_8 [18]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [18]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34
       (.I0(\rsMask_reg[7]_10 [17]),
        .I1(\rsMask_reg[5]_8 [17]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [17]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35
       (.I0(\rsMask_reg[7]_10 [16]),
        .I1(\rsMask_reg[5]_8 [16]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [16]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [16]),
        .O(rdEn_nxt_inferred_i_35_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36
       (.I0(\rsMask_reg[7]_10 [15]),
        .I1(\rsMask_reg[5]_8 [15]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [15]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [15]),
        .O(rdEn_nxt_inferred_i_36_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37
       (.I0(\rsMask_reg[7]_10 [14]),
        .I1(\rsMask_reg[5]_8 [14]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [14]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [14]),
        .O(rdEn_nxt_inferred_i_37_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38
       (.I0(\rsMask_reg[7]_10 [13]),
        .I1(\rsMask_reg[5]_8 [13]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [13]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [13]),
        .O(rdEn_nxt_inferred_i_38_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39
       (.I0(\rsMask_reg[7]_10 [12]),
        .I1(\rsMask_reg[5]_8 [12]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [12]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [12]),
        .O(rdEn_nxt_inferred_i_39_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4
       (.I0(\rdEn_reg[12]_0 ),
        .I1(rdEn_nxt_inferred_i_36_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40
       (.I0(\rsMask_reg[6]_9 [11]),
        .I1(\rsMask_reg[4]_7 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_5 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_3 [11]),
        .O(rdEn_nxt_inferred_i_40_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41
       (.I0(\rsMask_reg[7]_10 [11]),
        .I1(\rsMask_reg[5]_8 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [11]),
        .O(rdEn_nxt_inferred_i_41_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42
       (.I0(\rsMask_reg[7]_10 [10]),
        .I1(\rsMask_reg[5]_8 [10]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [10]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [10]),
        .O(rdEn_nxt_inferred_i_42_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43
       (.I0(\rsMask_reg[6]_9 [9]),
        .I1(\rsMask_reg[4]_7 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_5 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_3 [9]),
        .O(rdEn_nxt_inferred_i_43_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44
       (.I0(\rsMask_reg[7]_10 [9]),
        .I1(\rsMask_reg[5]_8 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [9]),
        .O(rdEn_nxt_inferred_i_44_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45
       (.I0(\rsMask_reg[7]_10 [8]),
        .I1(\rsMask_reg[5]_8 [8]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [8]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [8]),
        .O(rdEn_nxt_inferred_i_45_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46
       (.I0(\rsMask_reg[7]_10 [7]),
        .I1(\rsMask_reg[5]_8 [7]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [7]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [7]),
        .O(rdEn_nxt_inferred_i_46_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47
       (.I0(\rsMask_reg[7]_10 [6]),
        .I1(\rsMask_reg[5]_8 [6]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [6]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [6]),
        .O(rdEn_nxt_inferred_i_47_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48
       (.I0(\rsMask_reg[7]_10 [5]),
        .I1(\rsMask_reg[5]_8 [5]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [5]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [5]),
        .O(rdEn_nxt_inferred_i_48_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49
       (.I0(\rsMask_reg[7]_10 [4]),
        .I1(\rsMask_reg[5]_8 [4]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [4]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [4]),
        .O(rdEn_nxt_inferred_i_49_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_35_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_37_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50
       (.I0(\rsMask_reg[6]_9 [3]),
        .I1(\rsMask_reg[4]_7 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_5 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_3 [3]),
        .O(rdEn_nxt_inferred_i_50_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51
       (.I0(\rsMask_reg[7]_10 [3]),
        .I1(\rsMask_reg[5]_8 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [3]),
        .O(rdEn_nxt_inferred_i_51_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52
       (.I0(\rsMask_reg[6]_9 [2]),
        .I1(\rsMask_reg[4]_7 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_5 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_3 [2]),
        .O(rdEn_nxt_inferred_i_52_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_53
       (.I0(\rsMask_reg[7]_10 [2]),
        .I1(\rsMask_reg[5]_8 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [2]),
        .O(rdEn_nxt_inferred_i_53_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_54
       (.I0(\rsMask_reg[7]_10 [1]),
        .I1(\rsMask_reg[5]_8 [1]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_6 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_4 [1]),
        .O(rdEn_nxt_inferred_i_54_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_36_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_38_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_37_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_39_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_40_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_41_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_39_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_42_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_upp[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_upp[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_upp[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_upp[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_3 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_3 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_3 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_3 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0[2]),
        .Q(\rsMask_reg[1]_4 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0[3]),
        .Q(\rsMask_reg[1]_4 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0[4]),
        .Q(\rsMask_reg[1]_4 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_4 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_4 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_4 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_4 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_4 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_4 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_4 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0[0]),
        .Q(\rsMask_reg[1]_4 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0[1]),
        .Q(\rsMask_reg[1]_4 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_4 [4]),
        .R(\blk1.(null)[0].diff_1 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_4 [5]),
        .R(\blk1.(null)[0].diff_1 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_4 [6]),
        .R(\blk1.(null)[0].diff_1 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_4 [7]),
        .R(\blk1.(null)[0].diff_1 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_4 [8]),
        .R(\blk1.(null)[0].diff_1 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_1 [0]),
        .Q(\rsMask_reg[1]_4 [9]),
        .R(\blk1.(null)[0].diff_1 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_5 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_5 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_5 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_5 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_6 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_6 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_6 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_6 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_6 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_6 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_6 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_6 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_6 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_6 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_6 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_6 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_6 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_6 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_6 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_6 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_6 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_6 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_7 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_7 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_7 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_7 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_8 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_8 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_8 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_8 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_8 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_8 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_8 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_8 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_8 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_8 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_8 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_8 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_8 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_8 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_8 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_8 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_8 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_8 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_9 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_9 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_9 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_9 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_10 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_10 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_10 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_10 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_10 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_10 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_10 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_10 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_10 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_10 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_10 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_10 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_10 [4]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_10 [5]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_10 [6]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_10 [7]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_10 [8]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_2 ),
        .Q(\rsMask_reg[7]_10 [9]),
        .R(\rsMask_reg[7][9]_1 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_25
   (\rsMask_reg[7][18]_0 ,
    \rsMask_reg[7][17]_0 ,
    ch0_mcal_clb2phy_rden_low,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    rs2mask0_8,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_0 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_1 ,
    \blk1.(null)[0].diff_9 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_1 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_2 ,
    \rdEn_reg[12]_0 ,
    \rdEn_reg[12]_1 ,
    out,
    \rdEn_reg[14]_0 ,
    \rdEn_reg[14]_1 ,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output \rsMask_reg[7][18]_0 ;
  output \rsMask_reg[7][17]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_low;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [4:0]rs2mask0_8;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_0 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input [1:0]\blk1.(null)[0].diff_9 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_0 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_0 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_1 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_1 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_2 ;
  input \rdEn_reg[12]_0 ;
  input \rdEn_reg[12]_1 ;
  input out;
  input \rdEn_reg[14]_0 ;
  input \rdEn_reg[14]_1 ;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input [0:0]\rsMask_reg[3][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input [0:0]\rsMask_reg[5][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input [0:0]\rsMask_reg[7][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_9 ;
  wire [3:0]ch0_mcal_clb2phy_rden_low;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_34__5_n_0;
  wire rdEn_nxt_inferred_i_35__5_n_0;
  wire rdEn_nxt_inferred_i_36__5_n_0;
  wire rdEn_nxt_inferred_i_37__5_n_0;
  wire rdEn_nxt_inferred_i_38__5_n_0;
  wire rdEn_nxt_inferred_i_39__5_n_0;
  wire rdEn_nxt_inferred_i_40__5_n_0;
  wire rdEn_nxt_inferred_i_41__5_n_0;
  wire rdEn_nxt_inferred_i_42__5_n_0;
  wire rdEn_nxt_inferred_i_43__5_n_0;
  wire rdEn_nxt_inferred_i_44__5_n_0;
  wire rdEn_nxt_inferred_i_45__5_n_0;
  wire rdEn_nxt_inferred_i_46__5_n_0;
  wire rdEn_nxt_inferred_i_47__5_n_0;
  wire rdEn_nxt_inferred_i_48__5_n_0;
  wire rdEn_nxt_inferred_i_49__5_n_0;
  wire rdEn_nxt_inferred_i_50__5_n_0;
  wire rdEn_nxt_inferred_i_51__5_n_0;
  wire rdEn_nxt_inferred_i_52__5_n_0;
  wire rdEn_nxt_inferred_i_53__3_n_0;
  wire \rdEn_reg[12]_0 ;
  wire \rdEn_reg[12]_1 ;
  wire \rdEn_reg[14]_0 ;
  wire \rdEn_reg[14]_1 ;
  wire [4:0]rs2mask0_8;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_86 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire \rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [18:1]\rsMask_reg[1]_87 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_88 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [0:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire \rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [18:1]\rsMask_reg[3]_89 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_90 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [0:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire \rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [18:1]\rsMask_reg[5]_91 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_92 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [0:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire \rsMask_reg[7][17]_1 ;
  wire \rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire \rsMask_reg[7][9]_2 ;
  wire [18:1]\rsMask_reg[7]_93 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_10__5
       (.I0(rdEn[24]),
        .I1(rdEn_nxt_inferred_i_42__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_43__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_11__5
       (.I0(rdEn[23]),
        .I1(rdEn_nxt_inferred_i_41__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_44__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_12__5
       (.I0(rdEn[22]),
        .I1(rdEn_nxt_inferred_i_43__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_45__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_13__5
       (.I0(rdEn[21]),
        .I1(rdEn_nxt_inferred_i_44__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_46__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_14__5
       (.I0(rdEn[20]),
        .I1(rdEn_nxt_inferred_i_45__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_47__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_15__5
       (.I0(rdEn[19]),
        .I1(rdEn_nxt_inferred_i_46__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_48__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_16__5
       (.I0(rdEn[18]),
        .I1(rdEn_nxt_inferred_i_49__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_50__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_17__5
       (.I0(rdEn[17]),
        .I1(rdEn_nxt_inferred_i_51__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_52__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_18__5
       (.I0(rdEn[16]),
        .I1(rdEn_nxt_inferred_i_50__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_53__3_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_19__5
       (.I0(rdEn[15]),
        .I1(rdEn_nxt_inferred_i_52__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_53__3_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__5
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__5
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__5
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__5
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__5
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__5
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__5
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__5
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__5
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__5
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__5
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_31__3
       (.I0(\rsMask_reg[7]_93 [18]),
        .I1(\rsMask_reg[5]_91 [18]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [18]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [18]),
        .O(\rsMask_reg[7][18]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_33__4
       (.I0(\rsMask_reg[7]_93 [17]),
        .I1(\rsMask_reg[5]_91 [17]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [17]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [17]),
        .O(\rsMask_reg[7][17]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__5
       (.I0(\rsMask_reg[7]_93 [16]),
        .I1(\rsMask_reg[5]_91 [16]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [16]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [16]),
        .O(rdEn_nxt_inferred_i_34__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__5
       (.I0(\rsMask_reg[7]_93 [15]),
        .I1(\rsMask_reg[5]_91 [15]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [15]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [15]),
        .O(rdEn_nxt_inferred_i_35__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__5
       (.I0(\rsMask_reg[7]_93 [14]),
        .I1(\rsMask_reg[5]_91 [14]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [14]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [14]),
        .O(rdEn_nxt_inferred_i_36__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__5
       (.I0(\rsMask_reg[7]_93 [13]),
        .I1(\rsMask_reg[5]_91 [13]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [13]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [13]),
        .O(rdEn_nxt_inferred_i_37__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__5
       (.I0(\rsMask_reg[7]_93 [12]),
        .I1(\rsMask_reg[5]_91 [12]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [12]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [12]),
        .O(rdEn_nxt_inferred_i_38__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__5
       (.I0(\rsMask_reg[6]_92 [11]),
        .I1(\rsMask_reg[4]_90 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_88 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_86 [11]),
        .O(rdEn_nxt_inferred_i_39__5_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_3__5
       (.I0(\rdEn_reg[12]_0 ),
        .I1(rdEn_nxt_inferred_i_34__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(\rsMask_reg[7][18]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__5
       (.I0(\rsMask_reg[7]_93 [11]),
        .I1(\rsMask_reg[5]_91 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [11]),
        .O(rdEn_nxt_inferred_i_40__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__5
       (.I0(\rsMask_reg[7]_93 [10]),
        .I1(\rsMask_reg[5]_91 [10]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [10]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [10]),
        .O(rdEn_nxt_inferred_i_41__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__5
       (.I0(\rsMask_reg[6]_92 [9]),
        .I1(\rsMask_reg[4]_90 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_88 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_86 [9]),
        .O(rdEn_nxt_inferred_i_42__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__5
       (.I0(\rsMask_reg[7]_93 [9]),
        .I1(\rsMask_reg[5]_91 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [9]),
        .O(rdEn_nxt_inferred_i_43__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__5
       (.I0(\rsMask_reg[7]_93 [8]),
        .I1(\rsMask_reg[5]_91 [8]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [8]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [8]),
        .O(rdEn_nxt_inferred_i_44__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__5
       (.I0(\rsMask_reg[7]_93 [7]),
        .I1(\rsMask_reg[5]_91 [7]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [7]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [7]),
        .O(rdEn_nxt_inferred_i_45__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__5
       (.I0(\rsMask_reg[7]_93 [6]),
        .I1(\rsMask_reg[5]_91 [6]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [6]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [6]),
        .O(rdEn_nxt_inferred_i_46__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__5
       (.I0(\rsMask_reg[7]_93 [5]),
        .I1(\rsMask_reg[5]_91 [5]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [5]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [5]),
        .O(rdEn_nxt_inferred_i_47__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__5
       (.I0(\rsMask_reg[7]_93 [4]),
        .I1(\rsMask_reg[5]_91 [4]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [4]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [4]),
        .O(rdEn_nxt_inferred_i_48__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__5
       (.I0(\rsMask_reg[6]_92 [3]),
        .I1(\rsMask_reg[4]_90 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_88 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_86 [3]),
        .O(rdEn_nxt_inferred_i_49__5_n_0));
  LUT5 #(
    .INIT(32'h00008A80)) 
    rdEn_nxt_inferred_i_4__5
       (.I0(\rdEn_reg[12]_0 ),
        .I1(rdEn_nxt_inferred_i_35__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(\rsMask_reg[7][17]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__5
       (.I0(\rsMask_reg[7]_93 [3]),
        .I1(\rsMask_reg[5]_91 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [3]),
        .O(rdEn_nxt_inferred_i_50__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__5
       (.I0(\rsMask_reg[6]_92 [2]),
        .I1(\rsMask_reg[4]_90 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[2]_88 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_86 [2]),
        .O(rdEn_nxt_inferred_i_51__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__5
       (.I0(\rsMask_reg[7]_93 [2]),
        .I1(\rsMask_reg[5]_91 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [2]),
        .O(rdEn_nxt_inferred_i_52__5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_53__3
       (.I0(\rsMask_reg[7]_93 [1]),
        .I1(\rsMask_reg[5]_91 [1]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[3]_89 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_87 [1]),
        .O(rdEn_nxt_inferred_i_53__3_n_0));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_5__5
       (.I0(rdEn[29]),
        .I1(rdEn_nxt_inferred_i_34__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_36__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_6__5
       (.I0(rdEn[28]),
        .I1(rdEn_nxt_inferred_i_35__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_37__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_7__5
       (.I0(rdEn[27]),
        .I1(rdEn_nxt_inferred_i_36__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_38__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_8__5
       (.I0(rdEn[26]),
        .I1(rdEn_nxt_inferred_i_39__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_40__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h00000000FEAEAAAA)) 
    rdEn_nxt_inferred_i_9__5
       (.I0(rdEn[25]),
        .I1(rdEn_nxt_inferred_i_38__5_n_0),
        .I2(\rdEn_reg[12]_1 ),
        .I3(rdEn_nxt_inferred_i_41__5_n_0),
        .I4(\rdEn_reg[12]_0 ),
        .I5(out),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_low[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_low[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_low[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_low[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_86 [11]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_86 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_86 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_86 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_8[2]),
        .Q(\rsMask_reg[1]_87 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_8[3]),
        .Q(\rsMask_reg[1]_87 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_8[4]),
        .Q(\rsMask_reg[1]_87 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_87 [13]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_87 [14]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_87 [15]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_87 [16]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1]_87 [17]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_1 ),
        .Q(\rsMask_reg[1]_87 [18]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_87 [1]),
        .R(\rsMask_reg[1][18]_0 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_8[0]),
        .Q(\rsMask_reg[1]_87 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(rs2mask0_8[1]),
        .Q(\rsMask_reg[1]_87 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_87 [4]),
        .R(\blk1.(null)[0].diff_9 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_87 [5]),
        .R(\blk1.(null)[0].diff_9 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_87 [6]),
        .R(\blk1.(null)[0].diff_9 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_87 [7]),
        .R(\blk1.(null)[0].diff_9 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_87 [8]),
        .R(\blk1.(null)[0].diff_9 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_9 [0]),
        .Q(\rsMask_reg[1]_87 [9]),
        .R(\blk1.(null)[0].diff_9 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_88 [11]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_88 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_88 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_88 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_89 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][11]_0 ),
        .Q(\rsMask_reg[3]_89 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_89 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_89 [13]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_89 [14]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_89 [15]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_89 [16]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3]_89 [17]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_1 ),
        .Q(\rsMask_reg[3]_89 [18]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_89 [1]),
        .R(\rsMask_reg[3][18]_0 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_89 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_89 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_89 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_89 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_89 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_89 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_89 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_89 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_90 [11]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_90 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_90 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_90 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_91 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][11]_0 ),
        .Q(\rsMask_reg[5]_91 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_91 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_91 [13]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_91 [14]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_91 [15]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_91 [16]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5]_91 [17]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_1 ),
        .Q(\rsMask_reg[5]_91 [18]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_91 [1]),
        .R(\rsMask_reg[5][18]_0 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_91 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_91 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_91 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_91 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_91 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_91 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_91 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_91 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_92 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_92 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_92 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_92 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_93 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][11]_0 ),
        .Q(\rsMask_reg[7]_93 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_0 ),
        .Q(\rsMask_reg[7]_93 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_93 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_93 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_93 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_93 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_1 ),
        .Q(\rsMask_reg[7]_93 [17]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7]_93 [18]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_93 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_93 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_93 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_93 [4]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_93 [5]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_93 [6]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_93 [7]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_93 [8]),
        .R(\rsMask_reg[7][9]_1 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][9]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_2 ),
        .Q(\rsMask_reg[7]_93 [9]),
        .R(\rsMask_reg[7][9]_1 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_rd_en" *) 
module ddr4_0_ddr4_v2_2_17_cal_rd_en_26
   (\rsMask_reg[1][18]_0 ,
    \rsMask_reg[3][18]_0 ,
    \rsMask_reg[5][18]_0 ,
    \rsMask_reg[7][18]_0 ,
    ch0_mcal_clb2phy_rden_upp,
    \rdEn_reg[29]_0 ,
    \rsMask_reg[7][2]_0 ,
    \rsMask_reg[7][12]_0 ,
    \rsMask_reg[5][2]_0 ,
    \rsMask_reg[3][2]_0 ,
    \rsMask_reg[1][12]_0 ,
    \rsMask_reg[7][3]_0 ,
    \rsMask_reg[5][3]_0 ,
    \rsMask_reg[3][3]_0 ,
    \rsMask_reg[7][10]_0 ,
    \rsMask_reg[5][10]_0 ,
    \rsMask_reg[3][10]_0 ,
    \rsMask_reg[7][12]_1 ,
    \rsMask_reg[5][12]_0 ,
    \rsMask_reg[3][12]_0 ,
    \rsMask_reg[1][18]_1 ,
    \rsMask_reg[1][6]_0 ,
    \rsMask_reg[1][15]_0 ,
    \rsMask_reg[1][16]_0 ,
    \rsMask_reg[1][17]_0 ,
    \rsMask_reg[1][18]_2 ,
    \blk1.(null)[0].diff_0 ,
    \rsMask_reg[1][8]_0 ,
    \rsMask_reg[3][18]_1 ,
    \rsMask_reg[3][6]_0 ,
    \rsMask_reg[3][15]_0 ,
    \rsMask_reg[3][16]_0 ,
    \rsMask_reg[3][17]_0 ,
    \rsMask_reg[3][18]_2 ,
    \rsMask_reg[3][9]_0 ,
    \rsMask_reg[3][8]_0 ,
    \rsMask_reg[3][9]_1 ,
    \rsMask_reg[5][18]_1 ,
    \rsMask_reg[5][6]_0 ,
    \rsMask_reg[5][15]_0 ,
    \rsMask_reg[5][16]_0 ,
    \rsMask_reg[5][17]_0 ,
    \rsMask_reg[5][18]_2 ,
    \rsMask_reg[5][9]_0 ,
    \rsMask_reg[5][8]_0 ,
    \rsMask_reg[5][9]_1 ,
    \rsMask_reg[7][18]_1 ,
    \rsMask_reg[7][6]_0 ,
    \rsMask_reg[7][15]_0 ,
    \rsMask_reg[7][16]_0 ,
    \rsMask_reg[7][17]_0 ,
    \rsMask_reg[7][18]_2 ,
    \rsMask_reg[7][9]_0 ,
    \rsMask_reg[7][8]_0 ,
    \rsMask_reg[7][9]_1 ,
    \rsMask_reg[1][11]_0 ,
    \rsMask_reg[3][11]_0 ,
    \rsMask_reg[5][11]_0 ,
    \rsMask_reg[7][11]_0 ,
    out,
    \rdEn_reg[12]_0 ,
    \rdEn_reg[12]_1 ,
    \rdEn_reg[14]_0 ,
    \rdEn_reg[14]_1 ,
    \rdEn_reg[13]_0 ,
    \rsMask_reg[0][9]_0 ,
    \rsMask_reg[0][11]_0 ,
    \rsMask_reg[1][5]_0 ,
    \rsMask_reg[1][1]_0 ,
    \rsMask_reg[1][4]_0 ,
    \rsMask_reg[2][9]_0 ,
    \rsMask_reg[2][11]_0 ,
    \rsMask_reg[3][5]_0 ,
    \rsMask_reg[3][1]_0 ,
    \rsMask_reg[3][4]_0 ,
    \rsMask_reg[4][9]_0 ,
    \rsMask_reg[4][11]_0 ,
    \rsMask_reg[5][5]_0 ,
    \rsMask_reg[5][1]_0 ,
    \rsMask_reg[5][4]_0 ,
    \rsMask_reg[6][9]_0 ,
    \rsMask_reg[6][11]_0 ,
    \rsMask_reg[7][5]_0 ,
    \rsMask_reg[7][1]_0 ,
    \rsMask_reg[7][4]_0 );
  output [1:0]\rsMask_reg[1][18]_0 ;
  output [1:0]\rsMask_reg[3][18]_0 ;
  output [1:0]\rsMask_reg[5][18]_0 ;
  output [1:0]\rsMask_reg[7][18]_0 ;
  output [3:0]ch0_mcal_clb2phy_rden_upp;
  input [1:0]\rdEn_reg[29]_0 ;
  input \rsMask_reg[7][2]_0 ;
  input \rsMask_reg[7][12]_0 ;
  input \rsMask_reg[5][2]_0 ;
  input \rsMask_reg[3][2]_0 ;
  input [3:0]\rsMask_reg[1][12]_0 ;
  input \rsMask_reg[7][3]_0 ;
  input \rsMask_reg[5][3]_0 ;
  input \rsMask_reg[3][3]_0 ;
  input \rsMask_reg[7][10]_0 ;
  input \rsMask_reg[5][10]_0 ;
  input \rsMask_reg[3][10]_0 ;
  input \rsMask_reg[7][12]_1 ;
  input \rsMask_reg[5][12]_0 ;
  input \rsMask_reg[3][12]_0 ;
  input \rsMask_reg[1][18]_1 ;
  input \rsMask_reg[1][6]_0 ;
  input \rsMask_reg[1][15]_0 ;
  input \rsMask_reg[1][16]_0 ;
  input \rsMask_reg[1][17]_0 ;
  input \rsMask_reg[1][18]_2 ;
  input [1:0]\blk1.(null)[0].diff_0 ;
  input \rsMask_reg[1][8]_0 ;
  input \rsMask_reg[3][18]_1 ;
  input \rsMask_reg[3][6]_0 ;
  input \rsMask_reg[3][15]_0 ;
  input \rsMask_reg[3][16]_0 ;
  input \rsMask_reg[3][17]_0 ;
  input \rsMask_reg[3][18]_2 ;
  input \rsMask_reg[3][9]_0 ;
  input \rsMask_reg[3][8]_0 ;
  input \rsMask_reg[3][9]_1 ;
  input \rsMask_reg[5][18]_1 ;
  input \rsMask_reg[5][6]_0 ;
  input \rsMask_reg[5][15]_0 ;
  input \rsMask_reg[5][16]_0 ;
  input \rsMask_reg[5][17]_0 ;
  input \rsMask_reg[5][18]_2 ;
  input \rsMask_reg[5][9]_0 ;
  input \rsMask_reg[5][8]_0 ;
  input \rsMask_reg[5][9]_1 ;
  input \rsMask_reg[7][18]_1 ;
  input \rsMask_reg[7][6]_0 ;
  input \rsMask_reg[7][15]_0 ;
  input \rsMask_reg[7][16]_0 ;
  input \rsMask_reg[7][17]_0 ;
  input \rsMask_reg[7][18]_2 ;
  input \rsMask_reg[7][9]_0 ;
  input \rsMask_reg[7][8]_0 ;
  input \rsMask_reg[7][9]_1 ;
  input [2:0]\rsMask_reg[1][11]_0 ;
  input [2:0]\rsMask_reg[3][11]_0 ;
  input [2:0]\rsMask_reg[5][11]_0 ;
  input [2:0]\rsMask_reg[7][11]_0 ;
  input out;
  input \rdEn_reg[12]_0 ;
  input \rdEn_reg[12]_1 ;
  input \rdEn_reg[14]_0 ;
  input \rdEn_reg[14]_1 ;
  input \rdEn_reg[13]_0 ;
  input [2:0]\rsMask_reg[0][9]_0 ;
  input \rsMask_reg[0][11]_0 ;
  input \rsMask_reg[1][5]_0 ;
  input \rsMask_reg[1][1]_0 ;
  input \rsMask_reg[1][4]_0 ;
  input [2:0]\rsMask_reg[2][9]_0 ;
  input \rsMask_reg[2][11]_0 ;
  input \rsMask_reg[3][5]_0 ;
  input \rsMask_reg[3][1]_0 ;
  input \rsMask_reg[3][4]_0 ;
  input [2:0]\rsMask_reg[4][9]_0 ;
  input \rsMask_reg[4][11]_0 ;
  input \rsMask_reg[5][5]_0 ;
  input \rsMask_reg[5][1]_0 ;
  input \rsMask_reg[5][4]_0 ;
  input [2:0]\rsMask_reg[6][9]_0 ;
  input \rsMask_reg[6][11]_0 ;
  input \rsMask_reg[7][5]_0 ;
  input \rsMask_reg[7][1]_0 ;
  input \rsMask_reg[7][4]_0 ;

  wire [1:0]\blk1.(null)[0].diff_0 ;
  wire [3:0]ch0_mcal_clb2phy_rden_upp;
  wire out;
  wire [29:4]rdEn;
  (* RTL_KEEP = "true" *) wire [29:0]rdEn_nxt;
  wire rdEn_nxt_inferred_i_34__4_n_0;
  wire rdEn_nxt_inferred_i_35__3_n_0;
  wire rdEn_nxt_inferred_i_36__4_n_0;
  wire rdEn_nxt_inferred_i_37__4_n_0;
  wire rdEn_nxt_inferred_i_38__4_n_0;
  wire rdEn_nxt_inferred_i_39__4_n_0;
  wire rdEn_nxt_inferred_i_40__4_n_0;
  wire rdEn_nxt_inferred_i_41__4_n_0;
  wire rdEn_nxt_inferred_i_42__4_n_0;
  wire rdEn_nxt_inferred_i_43__4_n_0;
  wire rdEn_nxt_inferred_i_44__4_n_0;
  wire rdEn_nxt_inferred_i_45__4_n_0;
  wire rdEn_nxt_inferred_i_46__4_n_0;
  wire rdEn_nxt_inferred_i_47__4_n_0;
  wire rdEn_nxt_inferred_i_48__4_n_0;
  wire rdEn_nxt_inferred_i_49__4_n_0;
  wire rdEn_nxt_inferred_i_50__4_n_0;
  wire rdEn_nxt_inferred_i_51__4_n_0;
  wire rdEn_nxt_inferred_i_52__4_n_0;
  wire rdEn_nxt_inferred_i_53__2_n_0;
  wire rdEn_nxt_inferred_i_54__1_n_0;
  wire rdEn_nxt_inferred_i_55__0_n_0;
  wire rdEn_nxt_inferred_i_56__0_n_0;
  wire rdEn_nxt_inferred_i_57__0_n_0;
  wire rdEn_nxt_inferred_i_58__0_n_0;
  wire rdEn_nxt_inferred_i_59__0_n_0;
  wire rdEn_nxt_inferred_i_60__0_n_0;
  wire rdEn_nxt_inferred_i_61__0_n_0;
  wire rdEn_nxt_inferred_i_62__0_n_0;
  wire rdEn_nxt_inferred_i_63__0_n_0;
  wire rdEn_nxt_inferred_i_64__0_n_0;
  wire rdEn_nxt_inferred_i_65__0_n_0;
  wire rdEn_nxt_inferred_i_66__0_n_0;
  wire rdEn_nxt_inferred_i_67__0_n_0;
  wire \rdEn_reg[12]_0 ;
  wire \rdEn_reg[12]_1 ;
  wire \rdEn_reg[13]_0 ;
  wire \rdEn_reg[14]_0 ;
  wire \rdEn_reg[14]_1 ;
  wire [11:11]rs2mask0__0;
  wire \rs2mask0_inferred__0/i__n_0 ;
  wire \rs2mask0_inferred__1/i__n_0 ;
  wire \rs2mask0_inferred__2/i__n_0 ;
  wire \rsMask_reg[0][11]_0 ;
  wire [2:0]\rsMask_reg[0][9]_0 ;
  wire [11:2]\rsMask_reg[0]_78 ;
  wire [2:0]\rsMask_reg[1][11]_0 ;
  wire [3:0]\rsMask_reg[1][12]_0 ;
  wire \rsMask_reg[1][15]_0 ;
  wire \rsMask_reg[1][16]_0 ;
  wire \rsMask_reg[1][17]_0 ;
  wire [1:0]\rsMask_reg[1][18]_0 ;
  wire \rsMask_reg[1][18]_1 ;
  wire \rsMask_reg[1][18]_2 ;
  wire \rsMask_reg[1][1]_0 ;
  wire \rsMask_reg[1][4]_0 ;
  wire \rsMask_reg[1][5]_0 ;
  wire \rsMask_reg[1][6]_0 ;
  wire \rsMask_reg[1][8]_0 ;
  wire [16:1]\rsMask_reg[1]_79 ;
  wire \rsMask_reg[2][11]_0 ;
  wire [2:0]\rsMask_reg[2][9]_0 ;
  wire [11:2]\rsMask_reg[2]_80 ;
  wire \rsMask_reg[3][10]_0 ;
  wire [2:0]\rsMask_reg[3][11]_0 ;
  wire \rsMask_reg[3][12]_0 ;
  wire \rsMask_reg[3][15]_0 ;
  wire \rsMask_reg[3][16]_0 ;
  wire \rsMask_reg[3][17]_0 ;
  wire [1:0]\rsMask_reg[3][18]_0 ;
  wire \rsMask_reg[3][18]_1 ;
  wire \rsMask_reg[3][18]_2 ;
  wire \rsMask_reg[3][1]_0 ;
  wire \rsMask_reg[3][2]_0 ;
  wire \rsMask_reg[3][3]_0 ;
  wire \rsMask_reg[3][4]_0 ;
  wire \rsMask_reg[3][5]_0 ;
  wire \rsMask_reg[3][6]_0 ;
  wire \rsMask_reg[3][8]_0 ;
  wire \rsMask_reg[3][9]_0 ;
  wire \rsMask_reg[3][9]_1 ;
  wire [16:1]\rsMask_reg[3]_81 ;
  wire \rsMask_reg[4][11]_0 ;
  wire [2:0]\rsMask_reg[4][9]_0 ;
  wire [11:2]\rsMask_reg[4]_82 ;
  wire \rsMask_reg[5][10]_0 ;
  wire [2:0]\rsMask_reg[5][11]_0 ;
  wire \rsMask_reg[5][12]_0 ;
  wire \rsMask_reg[5][15]_0 ;
  wire \rsMask_reg[5][16]_0 ;
  wire \rsMask_reg[5][17]_0 ;
  wire [1:0]\rsMask_reg[5][18]_0 ;
  wire \rsMask_reg[5][18]_1 ;
  wire \rsMask_reg[5][18]_2 ;
  wire \rsMask_reg[5][1]_0 ;
  wire \rsMask_reg[5][2]_0 ;
  wire \rsMask_reg[5][3]_0 ;
  wire \rsMask_reg[5][4]_0 ;
  wire \rsMask_reg[5][5]_0 ;
  wire \rsMask_reg[5][6]_0 ;
  wire \rsMask_reg[5][8]_0 ;
  wire \rsMask_reg[5][9]_0 ;
  wire \rsMask_reg[5][9]_1 ;
  wire [16:1]\rsMask_reg[5]_83 ;
  wire \rsMask_reg[6][11]_0 ;
  wire [2:0]\rsMask_reg[6][9]_0 ;
  wire [11:2]\rsMask_reg[6]_84 ;
  wire \rsMask_reg[7][10]_0 ;
  wire [2:0]\rsMask_reg[7][11]_0 ;
  wire \rsMask_reg[7][12]_0 ;
  wire \rsMask_reg[7][12]_1 ;
  wire \rsMask_reg[7][15]_0 ;
  wire \rsMask_reg[7][16]_0 ;
  wire \rsMask_reg[7][17]_0 ;
  wire [1:0]\rsMask_reg[7][18]_0 ;
  wire \rsMask_reg[7][18]_1 ;
  wire \rsMask_reg[7][18]_2 ;
  wire \rsMask_reg[7][1]_0 ;
  wire \rsMask_reg[7][2]_0 ;
  wire \rsMask_reg[7][3]_0 ;
  wire \rsMask_reg[7][4]_0 ;
  wire \rsMask_reg[7][5]_0 ;
  wire \rsMask_reg[7][6]_0 ;
  wire \rsMask_reg[7][8]_0 ;
  wire \rsMask_reg[7][9]_0 ;
  wire \rsMask_reg[7][9]_1 ;
  wire [16:1]\rsMask_reg[7]_85 ;

  assign rdEn_nxt[29:28] = \rdEn_reg[29]_0 [1:0];
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_10__4
       (.I0(out),
        .I1(rdEn[24]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_48__4_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_49__4_n_0),
        .O(rdEn_nxt[20]));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_11__3
       (.I0(rdEn[23]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_50__4_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_51__4_n_0),
        .O(rdEn_nxt[19]));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_12__4
       (.I0(out),
        .I1(rdEn[22]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_52__4_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_53__2_n_0),
        .O(rdEn_nxt[18]));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_13__3
       (.I0(rdEn[21]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_54__1_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_55__0_n_0),
        .O(rdEn_nxt[17]));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_14__4
       (.I0(out),
        .I1(rdEn[20]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_56__0_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_57__0_n_0),
        .O(rdEn_nxt[16]));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_15__4
       (.I0(out),
        .I1(rdEn[19]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_58__0_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_59__0_n_0),
        .O(rdEn_nxt[15]));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_16__4
       (.I0(out),
        .I1(rdEn[18]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_60__0_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_61__0_n_0),
        .O(rdEn_nxt[14]));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_17__4
       (.I0(out),
        .I1(rdEn[17]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_62__0_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_63__0_n_0),
        .O(rdEn_nxt[13]));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_18__3
       (.I0(rdEn[16]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_64__0_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_65__0_n_0),
        .O(rdEn_nxt[12]));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_19__3
       (.I0(rdEn[15]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_66__0_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_67__0_n_0),
        .O(rdEn_nxt[11]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_20__4
       (.I0(rdEn[14]),
        .I1(out),
        .O(rdEn_nxt[10]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_21__4
       (.I0(rdEn[13]),
        .I1(out),
        .O(rdEn_nxt[9]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_22__4
       (.I0(rdEn[12]),
        .I1(out),
        .O(rdEn_nxt[8]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_23__4
       (.I0(rdEn[11]),
        .I1(out),
        .O(rdEn_nxt[7]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_24__4
       (.I0(rdEn[10]),
        .I1(out),
        .O(rdEn_nxt[6]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_25__4
       (.I0(rdEn[9]),
        .I1(out),
        .O(rdEn_nxt[5]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_26__4
       (.I0(rdEn[8]),
        .I1(out),
        .O(rdEn_nxt[4]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_27__4
       (.I0(rdEn[7]),
        .I1(out),
        .O(rdEn_nxt[3]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_28__4
       (.I0(rdEn[6]),
        .I1(out),
        .O(rdEn_nxt[2]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_29__4
       (.I0(rdEn[5]),
        .I1(out),
        .O(rdEn_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    rdEn_nxt_inferred_i_30__4
       (.I0(rdEn[4]),
        .I1(out),
        .O(rdEn_nxt[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_34__4
       (.I0(\rsMask_reg[3]_81 [16]),
        .I1(\rsMask_reg[3][18]_0 [1]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [16]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1][18]_0 [1]),
        .O(rdEn_nxt_inferred_i_34__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_35__3
       (.I0(\rsMask_reg[7]_85 [16]),
        .I1(\rsMask_reg[7][18]_0 [1]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [16]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5][18]_0 [1]),
        .O(rdEn_nxt_inferred_i_35__3_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_36__4
       (.I0(\rsMask_reg[3]_81 [15]),
        .I1(\rsMask_reg[3][18]_0 [0]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [15]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1][18]_0 [0]),
        .O(rdEn_nxt_inferred_i_36__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_37__4
       (.I0(\rsMask_reg[7]_85 [15]),
        .I1(\rsMask_reg[7][18]_0 [0]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [15]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5][18]_0 [0]),
        .O(rdEn_nxt_inferred_i_37__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_38__4
       (.I0(\rsMask_reg[7]_85 [14]),
        .I1(\rsMask_reg[7]_85 [16]),
        .I2(\rdEn_reg[13]_0 ),
        .I3(\rsMask_reg[5]_83 [14]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_83 [16]),
        .O(rdEn_nxt_inferred_i_38__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_39__4
       (.I0(\rsMask_reg[3]_81 [14]),
        .I1(\rsMask_reg[3]_81 [16]),
        .I2(\rdEn_reg[13]_0 ),
        .I3(\rsMask_reg[1]_79 [14]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_79 [16]),
        .O(rdEn_nxt_inferred_i_39__4_n_0));
  LUT5 #(
    .INIT(32'h0000E200)) 
    rdEn_nxt_inferred_i_3__3
       (.I0(rdEn_nxt_inferred_i_34__4_n_0),
        .I1(\rdEn_reg[12]_1 ),
        .I2(rdEn_nxt_inferred_i_35__3_n_0),
        .I3(\rdEn_reg[12]_0 ),
        .I4(out),
        .O(rdEn_nxt[27]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_40__4
       (.I0(\rsMask_reg[3]_81 [13]),
        .I1(\rsMask_reg[3]_81 [15]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [13]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_79 [15]),
        .O(rdEn_nxt_inferred_i_40__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_41__4
       (.I0(\rsMask_reg[7]_85 [13]),
        .I1(\rsMask_reg[7]_85 [15]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [13]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_83 [15]),
        .O(rdEn_nxt_inferred_i_41__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_42__4
       (.I0(\rsMask_reg[7]_85 [12]),
        .I1(\rsMask_reg[7]_85 [14]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [12]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_83 [14]),
        .O(rdEn_nxt_inferred_i_42__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_43__4
       (.I0(\rsMask_reg[3]_81 [12]),
        .I1(\rsMask_reg[3]_81 [14]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [12]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_79 [14]),
        .O(rdEn_nxt_inferred_i_43__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_44__4
       (.I0(\rsMask_reg[3]_81 [11]),
        .I1(\rsMask_reg[2]_80 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_78 [11]),
        .O(rdEn_nxt_inferred_i_44__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_45__4
       (.I0(\rsMask_reg[7]_85 [11]),
        .I1(\rsMask_reg[6]_84 [11]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [11]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[4]_82 [11]),
        .O(rdEn_nxt_inferred_i_45__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_46__4
       (.I0(\rsMask_reg[7]_85 [10]),
        .I1(\rsMask_reg[7]_85 [12]),
        .I2(\rdEn_reg[13]_0 ),
        .I3(\rsMask_reg[5]_83 [10]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_83 [12]),
        .O(rdEn_nxt_inferred_i_46__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_47__4
       (.I0(\rsMask_reg[3]_81 [10]),
        .I1(\rsMask_reg[3]_81 [12]),
        .I2(\rdEn_reg[13]_0 ),
        .I3(\rsMask_reg[1]_79 [10]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_79 [12]),
        .O(rdEn_nxt_inferred_i_47__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_48__4
       (.I0(\rsMask_reg[3]_81 [9]),
        .I1(\rsMask_reg[2]_80 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_78 [9]),
        .O(rdEn_nxt_inferred_i_48__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_49__4
       (.I0(\rsMask_reg[7]_85 [9]),
        .I1(\rsMask_reg[6]_84 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [9]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[4]_82 [9]),
        .O(rdEn_nxt_inferred_i_49__4_n_0));
  LUT5 #(
    .INIT(32'h0000E200)) 
    rdEn_nxt_inferred_i_4__3
       (.I0(rdEn_nxt_inferred_i_36__4_n_0),
        .I1(\rdEn_reg[12]_1 ),
        .I2(rdEn_nxt_inferred_i_37__4_n_0),
        .I3(\rdEn_reg[12]_0 ),
        .I4(out),
        .O(rdEn_nxt[26]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_50__4
       (.I0(\rsMask_reg[7]_85 [8]),
        .I1(\rsMask_reg[7]_85 [10]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [8]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_83 [10]),
        .O(rdEn_nxt_inferred_i_50__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_51__4
       (.I0(\rsMask_reg[3]_81 [8]),
        .I1(\rsMask_reg[3]_81 [10]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [8]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_79 [10]),
        .O(rdEn_nxt_inferred_i_51__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_52__4
       (.I0(\rsMask_reg[3]_81 [7]),
        .I1(\rsMask_reg[3]_81 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [7]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_79 [9]),
        .O(rdEn_nxt_inferred_i_52__4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_53__2
       (.I0(\rsMask_reg[7]_85 [7]),
        .I1(\rsMask_reg[7]_85 [9]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [7]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_83 [9]),
        .O(rdEn_nxt_inferred_i_53__2_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_54__1
       (.I0(\rsMask_reg[7]_85 [6]),
        .I1(\rsMask_reg[7]_85 [8]),
        .I2(\rdEn_reg[13]_0 ),
        .I3(\rsMask_reg[5]_83 [6]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_83 [8]),
        .O(rdEn_nxt_inferred_i_54__1_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_55__0
       (.I0(\rsMask_reg[3]_81 [6]),
        .I1(\rsMask_reg[3]_81 [8]),
        .I2(\rdEn_reg[13]_0 ),
        .I3(\rsMask_reg[1]_79 [6]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_79 [8]),
        .O(rdEn_nxt_inferred_i_55__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_56__0
       (.I0(\rsMask_reg[3]_81 [5]),
        .I1(\rsMask_reg[3]_81 [7]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [5]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_79 [7]),
        .O(rdEn_nxt_inferred_i_56__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_57__0
       (.I0(\rsMask_reg[7]_85 [5]),
        .I1(\rsMask_reg[7]_85 [7]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [5]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_83 [7]),
        .O(rdEn_nxt_inferred_i_57__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_58__0
       (.I0(\rsMask_reg[3]_81 [4]),
        .I1(\rsMask_reg[3]_81 [6]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [4]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_79 [6]),
        .O(rdEn_nxt_inferred_i_58__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_59__0
       (.I0(\rsMask_reg[7]_85 [4]),
        .I1(\rsMask_reg[7]_85 [6]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [4]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_83 [6]),
        .O(rdEn_nxt_inferred_i_59__0_n_0));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_5__3
       (.I0(rdEn[29]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_38__4_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_39__4_n_0),
        .O(rdEn_nxt[25]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_60__0
       (.I0(\rsMask_reg[3]_81 [3]),
        .I1(\rsMask_reg[2]_80 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_78 [3]),
        .O(rdEn_nxt_inferred_i_60__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_61__0
       (.I0(\rsMask_reg[7]_85 [3]),
        .I1(\rsMask_reg[6]_84 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [3]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[4]_82 [3]),
        .O(rdEn_nxt_inferred_i_61__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_62__0
       (.I0(\rsMask_reg[3]_81 [2]),
        .I1(\rsMask_reg[2]_80 [2]),
        .I2(\rdEn_reg[13]_0 ),
        .I3(\rsMask_reg[1]_79 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[0]_78 [2]),
        .O(rdEn_nxt_inferred_i_62__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_63__0
       (.I0(\rsMask_reg[7]_85 [2]),
        .I1(\rsMask_reg[6]_84 [2]),
        .I2(\rdEn_reg[13]_0 ),
        .I3(\rsMask_reg[5]_83 [2]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[4]_82 [2]),
        .O(rdEn_nxt_inferred_i_63__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_64__0
       (.I0(\rsMask_reg[7]_85 [1]),
        .I1(\rsMask_reg[7]_85 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_83 [3]),
        .O(rdEn_nxt_inferred_i_64__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_65__0
       (.I0(\rsMask_reg[3]_81 [1]),
        .I1(\rsMask_reg[3]_81 [3]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_79 [3]),
        .O(rdEn_nxt_inferred_i_65__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_66__0
       (.I0(\rsMask_reg[7]_85 [1]),
        .I1(\rsMask_reg[7]_85 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[5]_83 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[5]_83 [2]),
        .O(rdEn_nxt_inferred_i_66__0_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdEn_nxt_inferred_i_67__0
       (.I0(\rsMask_reg[3]_81 [1]),
        .I1(\rsMask_reg[3]_81 [2]),
        .I2(\rdEn_reg[14]_0 ),
        .I3(\rsMask_reg[1]_79 [1]),
        .I4(\rdEn_reg[14]_1 ),
        .I5(\rsMask_reg[1]_79 [2]),
        .O(rdEn_nxt_inferred_i_67__0_n_0));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_6__4
       (.I0(out),
        .I1(rdEn[28]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_40__4_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_41__4_n_0),
        .O(rdEn_nxt[24]));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_7__3
       (.I0(rdEn[27]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_42__4_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_43__4_n_0),
        .O(rdEn_nxt[23]));
  LUT6 #(
    .INIT(64'h5454544444445444)) 
    rdEn_nxt_inferred_i_8__4
       (.I0(out),
        .I1(rdEn[26]),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_44__4_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_45__4_n_0),
        .O(rdEn_nxt[22]));
  LUT6 #(
    .INIT(64'h3222323232222222)) 
    rdEn_nxt_inferred_i_9__3
       (.I0(rdEn[25]),
        .I1(out),
        .I2(\rdEn_reg[12]_0 ),
        .I3(rdEn_nxt_inferred_i_46__4_n_0),
        .I4(\rdEn_reg[12]_1 ),
        .I5(rdEn_nxt_inferred_i_47__4_n_0),
        .O(rdEn_nxt[21]));
  FDRE \rdEn_reg[0] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[0]),
        .Q(ch0_mcal_clb2phy_rden_upp[0]),
        .R(1'b0));
  FDRE \rdEn_reg[10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[10]),
        .Q(rdEn[10]),
        .R(1'b0));
  FDRE \rdEn_reg[11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[11]),
        .Q(rdEn[11]),
        .R(1'b0));
  FDRE \rdEn_reg[12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[12]),
        .Q(rdEn[12]),
        .R(1'b0));
  FDRE \rdEn_reg[13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[13]),
        .Q(rdEn[13]),
        .R(1'b0));
  FDRE \rdEn_reg[14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[14]),
        .Q(rdEn[14]),
        .R(1'b0));
  FDRE \rdEn_reg[15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[15]),
        .Q(rdEn[15]),
        .R(1'b0));
  FDRE \rdEn_reg[16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[16]),
        .Q(rdEn[16]),
        .R(1'b0));
  FDRE \rdEn_reg[17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[17]),
        .Q(rdEn[17]),
        .R(1'b0));
  FDRE \rdEn_reg[18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[18]),
        .Q(rdEn[18]),
        .R(1'b0));
  FDRE \rdEn_reg[19] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[19]),
        .Q(rdEn[19]),
        .R(1'b0));
  FDRE \rdEn_reg[1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[1]),
        .Q(ch0_mcal_clb2phy_rden_upp[1]),
        .R(1'b0));
  FDRE \rdEn_reg[20] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[20]),
        .Q(rdEn[20]),
        .R(1'b0));
  FDRE \rdEn_reg[21] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[21]),
        .Q(rdEn[21]),
        .R(1'b0));
  FDRE \rdEn_reg[22] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[22]),
        .Q(rdEn[22]),
        .R(1'b0));
  FDRE \rdEn_reg[23] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[23]),
        .Q(rdEn[23]),
        .R(1'b0));
  FDRE \rdEn_reg[24] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[24]),
        .Q(rdEn[24]),
        .R(1'b0));
  FDRE \rdEn_reg[25] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[25]),
        .Q(rdEn[25]),
        .R(1'b0));
  FDRE \rdEn_reg[26] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[26]),
        .Q(rdEn[26]),
        .R(1'b0));
  FDRE \rdEn_reg[27] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[27]),
        .Q(rdEn[27]),
        .R(1'b0));
  FDRE \rdEn_reg[28] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[28]),
        .Q(rdEn[28]),
        .R(1'b0));
  FDRE \rdEn_reg[29] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[29]),
        .Q(rdEn[29]),
        .R(1'b0));
  FDRE \rdEn_reg[2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[2]),
        .Q(ch0_mcal_clb2phy_rden_upp[2]),
        .R(1'b0));
  FDRE \rdEn_reg[3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[3]),
        .Q(ch0_mcal_clb2phy_rden_upp[3]),
        .R(1'b0));
  FDRE \rdEn_reg[4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[4]),
        .Q(rdEn[4]),
        .R(1'b0));
  FDRE \rdEn_reg[5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[5]),
        .Q(rdEn[5]),
        .R(1'b0));
  FDRE \rdEn_reg[6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[6]),
        .Q(rdEn[6]),
        .R(1'b0));
  FDRE \rdEn_reg[7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[7]),
        .Q(rdEn[7]),
        .R(1'b0));
  FDRE \rdEn_reg[8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[8]),
        .Q(rdEn[8]),
        .R(1'b0));
  FDRE \rdEn_reg[9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rdEn_nxt[9]),
        .Q(rdEn[9]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h4C)) 
    rs2mask0
       (.I0(\rsMask_reg[1][11]_0 [0]),
        .I1(\rsMask_reg[1][11]_0 [1]),
        .I2(\rsMask_reg[1][11]_0 [2]),
        .O(rs2mask0__0));
  LUT3 #(
    .INIT(8'h4C)) 
    \rs2mask0_inferred__0/i_ 
       (.I0(\rsMask_reg[3][11]_0 [0]),
        .I1(\rsMask_reg[3][11]_0 [1]),
        .I2(\rsMask_reg[3][11]_0 [2]),
        .O(\rs2mask0_inferred__0/i__n_0 ));
  LUT3 #(
    .INIT(8'h4C)) 
    \rs2mask0_inferred__1/i_ 
       (.I0(\rsMask_reg[5][11]_0 [0]),
        .I1(\rsMask_reg[5][11]_0 [1]),
        .I2(\rsMask_reg[5][11]_0 [2]),
        .O(\rs2mask0_inferred__1/i__n_0 ));
  LUT3 #(
    .INIT(8'h4C)) 
    \rs2mask0_inferred__2/i_ 
       (.I0(\rsMask_reg[7][11]_0 [0]),
        .I1(\rsMask_reg[7][11]_0 [1]),
        .I2(\rsMask_reg[7][11]_0 [2]),
        .O(\rs2mask0_inferred__2/i__n_0 ));
  FDRE \rsMask_reg[0][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][11]_0 ),
        .Q(\rsMask_reg[0]_78 [11]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[0][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [0]),
        .Q(\rsMask_reg[0]_78 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[0][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [1]),
        .Q(\rsMask_reg[0]_78 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[0][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[0][9]_0 [2]),
        .Q(\rsMask_reg[0]_78 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[1][10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][12]_0 [2]),
        .Q(\rsMask_reg[1]_79 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[1][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(rs2mask0__0),
        .Q(\rsMask_reg[1]_79 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[1][12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][12]_0 [3]),
        .Q(\rsMask_reg[1]_79 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[1][13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_79 [13]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_79 [14]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_79 [15]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][16]_0 ),
        .Q(\rsMask_reg[1]_79 [16]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][17]_0 ),
        .Q(\rsMask_reg[1][18]_0 [0]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][18]_2 ),
        .Q(\rsMask_reg[1][18]_0 [1]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][1]_0 ),
        .Q(\rsMask_reg[1]_79 [1]),
        .R(\rsMask_reg[1][18]_1 ));
  FDRE \rsMask_reg[1][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][12]_0 [0]),
        .Q(\rsMask_reg[1]_79 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[1][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][12]_0 [1]),
        .Q(\rsMask_reg[1]_79 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[1][4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][4]_0 ),
        .Q(\rsMask_reg[1]_79 [4]),
        .R(\blk1.(null)[0].diff_0 [1]));
  FDRE \rsMask_reg[1][5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][5]_0 ),
        .Q(\rsMask_reg[1]_79 [5]),
        .R(\blk1.(null)[0].diff_0 [1]));
  FDRE \rsMask_reg[1][6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][6]_0 ),
        .Q(\rsMask_reg[1]_79 [6]),
        .R(\blk1.(null)[0].diff_0 [1]));
  FDRE \rsMask_reg[1][7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][15]_0 ),
        .Q(\rsMask_reg[1]_79 [7]),
        .R(\blk1.(null)[0].diff_0 [1]));
  FDRE \rsMask_reg[1][8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[1][8]_0 ),
        .Q(\rsMask_reg[1]_79 [8]),
        .R(\blk1.(null)[0].diff_0 [1]));
  FDRE \rsMask_reg[1][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\blk1.(null)[0].diff_0 [0]),
        .Q(\rsMask_reg[1]_79 [9]),
        .R(\blk1.(null)[0].diff_0 [1]));
  FDRE \rsMask_reg[2][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][11]_0 ),
        .Q(\rsMask_reg[2]_80 [11]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[2][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [0]),
        .Q(\rsMask_reg[2]_80 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[2][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [1]),
        .Q(\rsMask_reg[2]_80 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[2][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[2][9]_0 [2]),
        .Q(\rsMask_reg[2]_80 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[3][10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][10]_0 ),
        .Q(\rsMask_reg[3]_81 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[3][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rs2mask0_inferred__0/i__n_0 ),
        .Q(\rsMask_reg[3]_81 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[3][12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][12]_0 ),
        .Q(\rsMask_reg[3]_81 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[3][13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_81 [13]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_81 [14]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_81 [15]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][16]_0 ),
        .Q(\rsMask_reg[3]_81 [16]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][17]_0 ),
        .Q(\rsMask_reg[3][18]_0 [0]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][18]_2 ),
        .Q(\rsMask_reg[3][18]_0 [1]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][1]_0 ),
        .Q(\rsMask_reg[3]_81 [1]),
        .R(\rsMask_reg[3][18]_1 ));
  FDRE \rsMask_reg[3][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][2]_0 ),
        .Q(\rsMask_reg[3]_81 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[3][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][3]_0 ),
        .Q(\rsMask_reg[3]_81 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[3][4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][4]_0 ),
        .Q(\rsMask_reg[3]_81 [4]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][5]_0 ),
        .Q(\rsMask_reg[3]_81 [5]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][6]_0 ),
        .Q(\rsMask_reg[3]_81 [6]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][15]_0 ),
        .Q(\rsMask_reg[3]_81 [7]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][8]_0 ),
        .Q(\rsMask_reg[3]_81 [8]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[3][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[3][9]_1 ),
        .Q(\rsMask_reg[3]_81 [9]),
        .R(\rsMask_reg[3][9]_0 ));
  FDRE \rsMask_reg[4][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][11]_0 ),
        .Q(\rsMask_reg[4]_82 [11]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[4][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [0]),
        .Q(\rsMask_reg[4]_82 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[4][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [1]),
        .Q(\rsMask_reg[4]_82 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[4][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[4][9]_0 [2]),
        .Q(\rsMask_reg[4]_82 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[5][10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][10]_0 ),
        .Q(\rsMask_reg[5]_83 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[5][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rs2mask0_inferred__1/i__n_0 ),
        .Q(\rsMask_reg[5]_83 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[5][12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][12]_0 ),
        .Q(\rsMask_reg[5]_83 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[5][13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_83 [13]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_83 [14]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_83 [15]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][16]_0 ),
        .Q(\rsMask_reg[5]_83 [16]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][17]_0 ),
        .Q(\rsMask_reg[5][18]_0 [0]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][18]_2 ),
        .Q(\rsMask_reg[5][18]_0 [1]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][1]_0 ),
        .Q(\rsMask_reg[5]_83 [1]),
        .R(\rsMask_reg[5][18]_1 ));
  FDRE \rsMask_reg[5][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][2]_0 ),
        .Q(\rsMask_reg[5]_83 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[5][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][3]_0 ),
        .Q(\rsMask_reg[5]_83 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[5][4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][4]_0 ),
        .Q(\rsMask_reg[5]_83 [4]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][5]_0 ),
        .Q(\rsMask_reg[5]_83 [5]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][6]_0 ),
        .Q(\rsMask_reg[5]_83 [6]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][15]_0 ),
        .Q(\rsMask_reg[5]_83 [7]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][8]_0 ),
        .Q(\rsMask_reg[5]_83 [8]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[5][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[5][9]_1 ),
        .Q(\rsMask_reg[5]_83 [9]),
        .R(\rsMask_reg[5][9]_0 ));
  FDRE \rsMask_reg[6][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][11]_0 ),
        .Q(\rsMask_reg[6]_84 [11]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[6][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [0]),
        .Q(\rsMask_reg[6]_84 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[6][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [1]),
        .Q(\rsMask_reg[6]_84 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[6][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[6][9]_0 [2]),
        .Q(\rsMask_reg[6]_84 [9]),
        .R(1'b0));
  FDRE \rsMask_reg[7][10] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][10]_0 ),
        .Q(\rsMask_reg[7]_85 [10]),
        .R(1'b0));
  FDRE \rsMask_reg[7][11] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rs2mask0_inferred__2/i__n_0 ),
        .Q(\rsMask_reg[7]_85 [11]),
        .R(1'b0));
  FDRE \rsMask_reg[7][12] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][12]_1 ),
        .Q(\rsMask_reg[7]_85 [12]),
        .R(1'b0));
  FDRE \rsMask_reg[7][13] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_85 [13]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][14] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_85 [14]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][15] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_85 [15]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][16] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][16]_0 ),
        .Q(\rsMask_reg[7]_85 [16]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][17] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][17]_0 ),
        .Q(\rsMask_reg[7][18]_0 [0]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][18] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][18]_2 ),
        .Q(\rsMask_reg[7][18]_0 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][1] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][1]_0 ),
        .Q(\rsMask_reg[7]_85 [1]),
        .R(\rsMask_reg[7][18]_1 ));
  FDRE \rsMask_reg[7][2] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][2]_0 ),
        .Q(\rsMask_reg[7]_85 [2]),
        .R(1'b0));
  FDRE \rsMask_reg[7][3] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][3]_0 ),
        .Q(\rsMask_reg[7]_85 [3]),
        .R(1'b0));
  FDRE \rsMask_reg[7][4] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][4]_0 ),
        .Q(\rsMask_reg[7]_85 [4]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][5] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][5]_0 ),
        .Q(\rsMask_reg[7]_85 [5]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][6] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][6]_0 ),
        .Q(\rsMask_reg[7]_85 [6]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][7] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][15]_0 ),
        .Q(\rsMask_reg[7]_85 [7]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][8] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][8]_0 ),
        .Q(\rsMask_reg[7]_85 [8]),
        .R(\rsMask_reg[7][9]_0 ));
  FDRE \rsMask_reg[7][9] 
       (.C(\rsMask_reg[7][12]_0 ),
        .CE(1'b1),
        .D(\rsMask_reg[7][9]_1 ),
        .Q(\rsMask_reg[7]_85 [9]),
        .R(\rsMask_reg[7][9]_0 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_read" *) 
module ddr4_0_ddr4_v2_2_17_cal_read
   (mc_clb2phy_fifo_rden_nxt,
    read_data_en_reg_0,
    calDone_reg,
    per_rd_done,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] ,
    \not_strict_mode.status_ram_0.RAM32M0 ,
    \not_strict_mode.bypass_cpy2 ,
    Q,
    \rdData_reg[5] ,
    match6_13_return,
    \rdDataAddr_reg[3]_rep_0 ,
    \rdDataAddr_reg[4]_rep_0 ,
    match4_13_return,
    \rdData_reg[11] ,
    match6_14_return,
    \rdDataAddr_reg[3]_rep__0_0 ,
    \rdDataAddr_reg[4]_rep__0_0 ,
    match4_14_return,
    \rdData_reg[17] ,
    match6_15_return,
    \rdDataAddr_reg[3]_rep__1_0 ,
    \rdDataAddr_reg[4]_rep__1_0 ,
    match4_15_return,
    \rdData_reg[23] ,
    match6_16_return,
    match4_16_return,
    \rdData_reg[29] ,
    match6_17_return,
    match4_17_return,
    \rdData_reg[35] ,
    match6_18_return,
    match4_18_return,
    \rdData_reg[41] ,
    match6_19_return,
    match4_19_return,
    \rdData_reg[47] ,
    match6_110_return,
    match4_110_return,
    \rdData_reg[53] ,
    match6_111_return,
    match4_111_return,
    \rdData_reg[59] ,
    match6_112_return,
    match4_112_return,
    \rdData_reg[65] ,
    match6_113_return,
    match4_113_return,
    \rdData_reg[71] ,
    match6_114_return,
    match4_114_return,
    \rdData_reg[77] ,
    match6_115_return,
    match4_115_return,
    \rdData_reg[83] ,
    match6_116_return,
    match4_116_return,
    \rdData_reg[89] ,
    match6_117_return,
    match4_117_return,
    \rdData_reg[95] ,
    match6_118_return,
    match4_118_return,
    \rdData_reg[101] ,
    match6_119_return,
    match4_119_return,
    \rdData_reg[107] ,
    match6_120_return,
    match4_120_return,
    \rdData_reg[113] ,
    match6_121_return,
    match4_121_return,
    \rdData_reg[119] ,
    match6_122_return,
    match4_122_return,
    \rdData_reg[125] ,
    match6_123_return,
    match4_123_return,
    \rdData_reg[131] ,
    match6_124_return,
    match4_124_return,
    \rdData_reg[137] ,
    match6_125_return,
    match4_125_return,
    \rdData_reg[143] ,
    match6_126_return,
    match4_126_return,
    \rdData_reg[149] ,
    match6_127_return,
    match4_127_return,
    \rdData_reg[155] ,
    match6_128_return,
    match4_128_return,
    \rdData_reg[161] ,
    match6_129_return,
    match4_129_return,
    \rdData_reg[167] ,
    match6_130_return,
    match4_130_return,
    \rdData_reg[173] ,
    match6_131_return,
    match4_131_return,
    \rdData_reg[179] ,
    match6_132_return,
    match4_132_return,
    \rdData_reg[185] ,
    match6_133_return,
    match4_133_return,
    \rdData_reg[191] ,
    match6_134_return,
    match4_134_return,
    \rdData_reg[197] ,
    match6_135_return,
    match4_135_return,
    \rdData_reg[203] ,
    match6_136_return,
    match4_136_return,
    \rdData_reg[209] ,
    match6_137_return,
    match4_137_return,
    \rdData_reg[215] ,
    match6_138_return,
    match4_138_return,
    \rdData_reg[221] ,
    match6_139_return,
    match4_139_return,
    \rdData_reg[227] ,
    match6_140_return,
    match4_140_return,
    \rdData_reg[233] ,
    match6_141_return,
    match4_141_return,
    \rdData_reg[239] ,
    match6_142_return,
    match4_142_return,
    \rdData_reg[245] ,
    match6_143_return,
    match4_143_return,
    \rdData_reg[251] ,
    match6_144_return,
    match4_144_return,
    \rdData_reg[257] ,
    match6_145_return,
    match4_145_return,
    \rdData_reg[263] ,
    match6_146_return,
    match4_146_return,
    \rdData_reg[269] ,
    match6_147_return,
    match4_147_return,
    \rdData_reg[275] ,
    match6_148_return,
    match4_148_return,
    \rdData_reg[281] ,
    match6_149_return,
    match4_149_return,
    \rdData_reg[287] ,
    match6_150_return,
    match4_150_return,
    \rdData_reg[293] ,
    match6_151_return,
    match4_151_return,
    \rdData_reg[299] ,
    match6_152_return,
    match4_152_return,
    \rdData_reg[305] ,
    match6_153_return,
    match4_153_return,
    \rdData_reg[311] ,
    match6_154_return,
    match4_154_return,
    \rdData_reg[317] ,
    match6_155_return,
    match4_155_return,
    \rdData_reg[323] ,
    match6_156_return,
    match4_156_return,
    \rdData_reg[329] ,
    match6_157_return,
    match4_157_return,
    \rdData_reg[335] ,
    match6_158_return,
    match4_158_return,
    \rdData_reg[341] ,
    match6_159_return,
    match4_159_return,
    \rdData_reg[347] ,
    match6_160_return,
    match4_160_return,
    \rdData_reg[353] ,
    match6_161_return,
    match4_161_return,
    \rdData_reg[359] ,
    match6_162_return,
    match4_162_return,
    \rdData_reg[365] ,
    match6_163_return,
    match4_163_return,
    \rdData_reg[371] ,
    match6_164_return,
    match4_164_return,
    \rdData_reg[377] ,
    match6_165_return,
    match4_165_return,
    \rdData_reg[383] ,
    match6_166_return,
    match4_166_return,
    \rdData_reg[389] ,
    match6_167_return,
    match4_167_return,
    \rdData_reg[395] ,
    match6_168_return,
    match4_168_return,
    \rdData_reg[401] ,
    match6_169_return,
    match4_169_return,
    \rdData_reg[407] ,
    match6_170_return,
    match4_170_return,
    \rdData_reg[413] ,
    match6_171_return,
    match4_171_return,
    \rdData_reg[419] ,
    match6_172_return,
    match4_172_return,
    \rdData_reg[425] ,
    match6_173_return,
    match4_173_return,
    \rdData_reg[431] ,
    match6_174_return,
    match4_174_return,
    \rdData_reg[437] ,
    match6_175_return,
    match4_175_return,
    \rdData_reg[443] ,
    match6_176_return,
    match4_176_return,
    \rdData_reg[449] ,
    match6_177_return,
    match4_177_return,
    \rdData_reg[455] ,
    match6_178_return,
    match4_178_return,
    \rdData_reg[461] ,
    match6_179_return,
    match4_179_return,
    \rdData_reg[467] ,
    match6_180_return,
    match4_180_return,
    \rdData_reg[473] ,
    match6_181_return,
    match4_181_return,
    \rdData_reg[479] ,
    match6_182_return,
    match4_182_return,
    \rdData_reg[485] ,
    match6_183_return,
    match4_183_return,
    \rdData_reg[491] ,
    match6_184_return,
    match4_184_return,
    \rdData_reg[497] ,
    match6_185_return,
    match4_185_return,
    \rdData_reg[503] ,
    match6_186_return,
    match4_186_return,
    \rdData_reg[509] ,
    match6_187_return,
    match4_187_return,
    \rdData_reg[511] ,
    match6_188_return,
    match4_188_return,
    match4_1_return,
    match6_1_return,
    match4_10_return,
    match6_10_return,
    match4_11_return,
    match6_11_return,
    match4_12_return,
    match6_12_return,
    pop_read_lat_fifo_reg_0,
    \read_lat_shift_reg[31]_0 ,
    underfill_done_nxt,
    \rdDataAddr_reg[4]_0 ,
    \rdDataAddr_reg[4]_1 ,
    \rdDataAddr_reg[4]_2 ,
    \rdDataAddr_reg[4]_rep__1_1 ,
    mcRdCAS,
    rdCAS_reg_0,
    calRdCAS,
    read_lat_shift_cal_dq_valid_nxt,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ,
    DOA,
    \not_strict_mode.app_rd_data_end_reg ,
    D,
    DOC,
    DOB,
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ,
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] ,
    \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] ,
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] ,
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] ,
    cnt_clr,
    out,
    \read_lat_fifo_in_reg[6]_0 ,
    cmdBuf,
    cal_clear_fifo_rden);
  output [0:0]mc_clb2phy_fifo_rden_nxt;
  output read_data_en_reg_0;
  output calDone_reg;
  output per_rd_done;
  output [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] ;
  output \not_strict_mode.status_ram_0.RAM32M0 ;
  output \not_strict_mode.bypass_cpy2 ;
  output [4:0]Q;
  output [5:0]\rdData_reg[5] ;
  output match6_13_return;
  output \rdDataAddr_reg[3]_rep_0 ;
  output \rdDataAddr_reg[4]_rep_0 ;
  output match4_13_return;
  output [5:0]\rdData_reg[11] ;
  output match6_14_return;
  output \rdDataAddr_reg[3]_rep__0_0 ;
  output \rdDataAddr_reg[4]_rep__0_0 ;
  output match4_14_return;
  output [5:0]\rdData_reg[17] ;
  output match6_15_return;
  output \rdDataAddr_reg[3]_rep__1_0 ;
  output \rdDataAddr_reg[4]_rep__1_0 ;
  output match4_15_return;
  output [5:0]\rdData_reg[23] ;
  output match6_16_return;
  output match4_16_return;
  output [5:0]\rdData_reg[29] ;
  output match6_17_return;
  output match4_17_return;
  output [5:0]\rdData_reg[35] ;
  output match6_18_return;
  output match4_18_return;
  output [5:0]\rdData_reg[41] ;
  output match6_19_return;
  output match4_19_return;
  output [5:0]\rdData_reg[47] ;
  output match6_110_return;
  output match4_110_return;
  output [5:0]\rdData_reg[53] ;
  output match6_111_return;
  output match4_111_return;
  output [5:0]\rdData_reg[59] ;
  output match6_112_return;
  output match4_112_return;
  output [5:0]\rdData_reg[65] ;
  output match6_113_return;
  output match4_113_return;
  output [5:0]\rdData_reg[71] ;
  output match6_114_return;
  output match4_114_return;
  output [5:0]\rdData_reg[77] ;
  output match6_115_return;
  output match4_115_return;
  output [5:0]\rdData_reg[83] ;
  output match6_116_return;
  output match4_116_return;
  output [5:0]\rdData_reg[89] ;
  output match6_117_return;
  output match4_117_return;
  output [5:0]\rdData_reg[95] ;
  output match6_118_return;
  output match4_118_return;
  output [5:0]\rdData_reg[101] ;
  output match6_119_return;
  output match4_119_return;
  output [5:0]\rdData_reg[107] ;
  output match6_120_return;
  output match4_120_return;
  output [5:0]\rdData_reg[113] ;
  output match6_121_return;
  output match4_121_return;
  output [5:0]\rdData_reg[119] ;
  output match6_122_return;
  output match4_122_return;
  output [5:0]\rdData_reg[125] ;
  output match6_123_return;
  output match4_123_return;
  output [5:0]\rdData_reg[131] ;
  output match6_124_return;
  output match4_124_return;
  output [5:0]\rdData_reg[137] ;
  output match6_125_return;
  output match4_125_return;
  output [5:0]\rdData_reg[143] ;
  output match6_126_return;
  output match4_126_return;
  output [5:0]\rdData_reg[149] ;
  output match6_127_return;
  output match4_127_return;
  output [5:0]\rdData_reg[155] ;
  output match6_128_return;
  output match4_128_return;
  output [5:0]\rdData_reg[161] ;
  output match6_129_return;
  output match4_129_return;
  output [5:0]\rdData_reg[167] ;
  output match6_130_return;
  output match4_130_return;
  output [5:0]\rdData_reg[173] ;
  output match6_131_return;
  output match4_131_return;
  output [5:0]\rdData_reg[179] ;
  output match6_132_return;
  output match4_132_return;
  output [5:0]\rdData_reg[185] ;
  output match6_133_return;
  output match4_133_return;
  output [5:0]\rdData_reg[191] ;
  output match6_134_return;
  output match4_134_return;
  output [5:0]\rdData_reg[197] ;
  output match6_135_return;
  output match4_135_return;
  output [5:0]\rdData_reg[203] ;
  output match6_136_return;
  output match4_136_return;
  output [5:0]\rdData_reg[209] ;
  output match6_137_return;
  output match4_137_return;
  output [5:0]\rdData_reg[215] ;
  output match6_138_return;
  output match4_138_return;
  output [5:0]\rdData_reg[221] ;
  output match6_139_return;
  output match4_139_return;
  output [5:0]\rdData_reg[227] ;
  output match6_140_return;
  output match4_140_return;
  output [5:0]\rdData_reg[233] ;
  output match6_141_return;
  output match4_141_return;
  output [5:0]\rdData_reg[239] ;
  output match6_142_return;
  output match4_142_return;
  output [5:0]\rdData_reg[245] ;
  output match6_143_return;
  output match4_143_return;
  output [5:0]\rdData_reg[251] ;
  output match6_144_return;
  output match4_144_return;
  output [5:0]\rdData_reg[257] ;
  output match6_145_return;
  output match4_145_return;
  output [5:0]\rdData_reg[263] ;
  output match6_146_return;
  output match4_146_return;
  output [5:0]\rdData_reg[269] ;
  output match6_147_return;
  output match4_147_return;
  output [5:0]\rdData_reg[275] ;
  output match6_148_return;
  output match4_148_return;
  output [5:0]\rdData_reg[281] ;
  output match6_149_return;
  output match4_149_return;
  output [5:0]\rdData_reg[287] ;
  output match6_150_return;
  output match4_150_return;
  output [5:0]\rdData_reg[293] ;
  output match6_151_return;
  output match4_151_return;
  output [5:0]\rdData_reg[299] ;
  output match6_152_return;
  output match4_152_return;
  output [5:0]\rdData_reg[305] ;
  output match6_153_return;
  output match4_153_return;
  output [5:0]\rdData_reg[311] ;
  output match6_154_return;
  output match4_154_return;
  output [5:0]\rdData_reg[317] ;
  output match6_155_return;
  output match4_155_return;
  output [5:0]\rdData_reg[323] ;
  output match6_156_return;
  output match4_156_return;
  output [5:0]\rdData_reg[329] ;
  output match6_157_return;
  output match4_157_return;
  output [5:0]\rdData_reg[335] ;
  output match6_158_return;
  output match4_158_return;
  output [5:0]\rdData_reg[341] ;
  output match6_159_return;
  output match4_159_return;
  output [5:0]\rdData_reg[347] ;
  output match6_160_return;
  output match4_160_return;
  output [5:0]\rdData_reg[353] ;
  output match6_161_return;
  output match4_161_return;
  output [5:0]\rdData_reg[359] ;
  output match6_162_return;
  output match4_162_return;
  output [5:0]\rdData_reg[365] ;
  output match6_163_return;
  output match4_163_return;
  output [5:0]\rdData_reg[371] ;
  output match6_164_return;
  output match4_164_return;
  output [5:0]\rdData_reg[377] ;
  output match6_165_return;
  output match4_165_return;
  output [5:0]\rdData_reg[383] ;
  output match6_166_return;
  output match4_166_return;
  output [5:0]\rdData_reg[389] ;
  output match6_167_return;
  output match4_167_return;
  output [5:0]\rdData_reg[395] ;
  output match6_168_return;
  output match4_168_return;
  output [5:0]\rdData_reg[401] ;
  output match6_169_return;
  output match4_169_return;
  output [5:0]\rdData_reg[407] ;
  output match6_170_return;
  output match4_170_return;
  output [5:0]\rdData_reg[413] ;
  output match6_171_return;
  output match4_171_return;
  output [5:0]\rdData_reg[419] ;
  output match6_172_return;
  output match4_172_return;
  output [5:0]\rdData_reg[425] ;
  output match6_173_return;
  output match4_173_return;
  output [5:0]\rdData_reg[431] ;
  output match6_174_return;
  output match4_174_return;
  output [5:0]\rdData_reg[437] ;
  output match6_175_return;
  output match4_175_return;
  output [5:0]\rdData_reg[443] ;
  output match6_176_return;
  output match4_176_return;
  output [5:0]\rdData_reg[449] ;
  output match6_177_return;
  output match4_177_return;
  output [5:0]\rdData_reg[455] ;
  output match6_178_return;
  output match4_178_return;
  output [5:0]\rdData_reg[461] ;
  output match6_179_return;
  output match4_179_return;
  output [5:0]\rdData_reg[467] ;
  output match6_180_return;
  output match4_180_return;
  output [5:0]\rdData_reg[473] ;
  output match6_181_return;
  output match4_181_return;
  output [5:0]\rdData_reg[479] ;
  output match6_182_return;
  output match4_182_return;
  output [5:0]\rdData_reg[485] ;
  output match6_183_return;
  output match4_183_return;
  output [5:0]\rdData_reg[491] ;
  output match6_184_return;
  output match4_184_return;
  output [5:0]\rdData_reg[497] ;
  output match6_185_return;
  output match4_185_return;
  output [5:0]\rdData_reg[503] ;
  output match6_186_return;
  output match4_186_return;
  output [5:0]\rdData_reg[509] ;
  output match6_187_return;
  output match4_187_return;
  output [1:0]\rdData_reg[511] ;
  output match6_188_return;
  output match4_188_return;
  output match4_1_return;
  output match6_1_return;
  output match4_10_return;
  output match6_10_return;
  output match4_11_return;
  output match6_11_return;
  output match4_12_return;
  output match6_12_return;
  output [0:0]pop_read_lat_fifo_reg_0;
  output [31:0]\read_lat_shift_reg[31]_0 ;
  output underfill_done_nxt;
  output \rdDataAddr_reg[4]_0 ;
  output \rdDataAddr_reg[4]_1 ;
  output \rdDataAddr_reg[4]_2 ;
  input \rdDataAddr_reg[4]_rep__1_1 ;
  input mcRdCAS;
  input rdCAS_reg_0;
  input calRdCAS;
  input read_lat_shift_cal_dq_valid_nxt;
  input [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ;
  input [0:0]DOA;
  input [4:0]\not_strict_mode.app_rd_data_end_reg ;
  input [511:0]D;
  input [1:0]DOC;
  input [1:0]DOB;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ;
  input [4:0]\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] ;
  input [4:0]\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] ;
  input [4:0]\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] ;
  input [4:0]\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] ;
  input cnt_clr;
  input out;
  input [6:0]\read_lat_fifo_in_reg[6]_0 ;
  input [19:0]cmdBuf;
  input cal_clear_fifo_rden;

  wire [511:0]D;
  wire [0:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire [4:0]Q;
  wire calDone_reg;
  wire calRdCAS;
  wire cal_clear_fifo_rden;
  wire [19:0]cmdBuf;
  wire cnt_clr;
  wire match4_10_return;
  wire match4_110_return;
  wire match4_111_return;
  wire match4_112_return;
  wire match4_113_return;
  wire match4_114_return;
  wire match4_115_return;
  wire match4_116_return;
  wire match4_117_return;
  wire match4_118_return;
  wire match4_119_return;
  wire match4_11_return;
  wire match4_120_return;
  wire match4_121_return;
  wire match4_122_return;
  wire match4_123_return;
  wire match4_124_return;
  wire match4_125_return;
  wire match4_126_return;
  wire match4_127_return;
  wire match4_128_return;
  wire match4_129_return;
  wire match4_12_return;
  wire match4_130_return;
  wire match4_131_return;
  wire match4_132_return;
  wire match4_133_return;
  wire match4_134_return;
  wire match4_135_return;
  wire match4_136_return;
  wire match4_137_return;
  wire match4_138_return;
  wire match4_139_return;
  wire match4_13_return;
  wire match4_140_return;
  wire match4_141_return;
  wire match4_142_return;
  wire match4_143_return;
  wire match4_144_return;
  wire match4_145_return;
  wire match4_146_return;
  wire match4_147_return;
  wire match4_148_return;
  wire match4_149_return;
  wire match4_14_return;
  wire match4_150_return;
  wire match4_151_return;
  wire match4_152_return;
  wire match4_153_return;
  wire match4_154_return;
  wire match4_155_return;
  wire match4_156_return;
  wire match4_157_return;
  wire match4_158_return;
  wire match4_159_return;
  wire match4_15_return;
  wire match4_160_return;
  wire match4_161_return;
  wire match4_162_return;
  wire match4_163_return;
  wire match4_164_return;
  wire match4_165_return;
  wire match4_166_return;
  wire match4_167_return;
  wire match4_168_return;
  wire match4_169_return;
  wire match4_16_return;
  wire match4_170_return;
  wire match4_171_return;
  wire match4_172_return;
  wire match4_173_return;
  wire match4_174_return;
  wire match4_175_return;
  wire match4_176_return;
  wire match4_177_return;
  wire match4_178_return;
  wire match4_179_return;
  wire match4_17_return;
  wire match4_180_return;
  wire match4_181_return;
  wire match4_182_return;
  wire match4_183_return;
  wire match4_184_return;
  wire match4_185_return;
  wire match4_186_return;
  wire match4_187_return;
  wire match4_188_return;
  wire match4_18_return;
  wire match4_19_return;
  wire match4_1_return;
  wire match6_10_return;
  wire match6_110_return;
  wire match6_111_return;
  wire match6_112_return;
  wire match6_113_return;
  wire match6_114_return;
  wire match6_115_return;
  wire match6_116_return;
  wire match6_117_return;
  wire match6_118_return;
  wire match6_119_return;
  wire match6_11_return;
  wire match6_120_return;
  wire match6_121_return;
  wire match6_122_return;
  wire match6_123_return;
  wire match6_124_return;
  wire match6_125_return;
  wire match6_126_return;
  wire match6_127_return;
  wire match6_128_return;
  wire match6_129_return;
  wire match6_12_return;
  wire match6_130_return;
  wire match6_131_return;
  wire match6_132_return;
  wire match6_133_return;
  wire match6_134_return;
  wire match6_135_return;
  wire match6_136_return;
  wire match6_137_return;
  wire match6_138_return;
  wire match6_139_return;
  wire match6_13_return;
  wire match6_140_return;
  wire match6_141_return;
  wire match6_142_return;
  wire match6_143_return;
  wire match6_144_return;
  wire match6_145_return;
  wire match6_146_return;
  wire match6_147_return;
  wire match6_148_return;
  wire match6_149_return;
  wire match6_14_return;
  wire match6_150_return;
  wire match6_151_return;
  wire match6_152_return;
  wire match6_153_return;
  wire match6_154_return;
  wire match6_155_return;
  wire match6_156_return;
  wire match6_157_return;
  wire match6_158_return;
  wire match6_159_return;
  wire match6_15_return;
  wire match6_160_return;
  wire match6_161_return;
  wire match6_162_return;
  wire match6_163_return;
  wire match6_164_return;
  wire match6_165_return;
  wire match6_166_return;
  wire match6_167_return;
  wire match6_168_return;
  wire match6_169_return;
  wire match6_16_return;
  wire match6_170_return;
  wire match6_171_return;
  wire match6_172_return;
  wire match6_173_return;
  wire match6_174_return;
  wire match6_175_return;
  wire match6_176_return;
  wire match6_177_return;
  wire match6_178_return;
  wire match6_179_return;
  wire match6_17_return;
  wire match6_180_return;
  wire match6_181_return;
  wire match6_182_return;
  wire match6_183_return;
  wire match6_184_return;
  wire match6_185_return;
  wire match6_186_return;
  wire match6_187_return;
  wire match6_188_return;
  wire match6_18_return;
  wire match6_19_return;
  wire match6_1_return;
  wire mcRdCAS;
  wire [0:0]mc_clb2phy_fifo_rden_nxt;
  wire [4:0]\not_strict_mode.app_rd_data_end_reg ;
  wire \not_strict_mode.bypass_cpy2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ;
  wire [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ;
  wire [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ;
  wire \not_strict_mode.status_ram_0.RAM32M0 ;
  wire [4:0]\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] ;
  wire [4:0]\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] ;
  wire [4:0]\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] ;
  wire [4:0]\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] ;
  wire out;
  wire [4:0]p_0_in;
  wire [4:0]p_0_in__0;
  wire per_rd_done;
  wire pop_read_lat_fifo;
  wire [0:0]pop_read_lat_fifo_reg_0;
  wire rdCAS_nxt__0;
  wire rdCAS_reg_0;
  wire \rdDataAddr[0]_i_10_n_0 ;
  wire \rdDataAddr[0]_i_11_n_0 ;
  wire \rdDataAddr[0]_i_12_n_0 ;
  wire \rdDataAddr[0]_i_13_n_0 ;
  wire \rdDataAddr[0]_i_6_n_0 ;
  wire \rdDataAddr[0]_i_7_n_0 ;
  wire \rdDataAddr[0]_i_8_n_0 ;
  wire \rdDataAddr[0]_i_9_n_0 ;
  wire \rdDataAddr[1]_i_10_n_0 ;
  wire \rdDataAddr[1]_i_11_n_0 ;
  wire \rdDataAddr[1]_i_12_n_0 ;
  wire \rdDataAddr[1]_i_13_n_0 ;
  wire \rdDataAddr[1]_i_6_n_0 ;
  wire \rdDataAddr[1]_i_7_n_0 ;
  wire \rdDataAddr[1]_i_8_n_0 ;
  wire \rdDataAddr[1]_i_9_n_0 ;
  wire \rdDataAddr[2]_i_10_n_0 ;
  wire \rdDataAddr[2]_i_11_n_0 ;
  wire \rdDataAddr[2]_i_12_n_0 ;
  wire \rdDataAddr[2]_i_13_n_0 ;
  wire \rdDataAddr[2]_i_6_n_0 ;
  wire \rdDataAddr[2]_i_7_n_0 ;
  wire \rdDataAddr[2]_i_8_n_0 ;
  wire \rdDataAddr[2]_i_9_n_0 ;
  wire \rdDataAddr[3]_i_10_n_0 ;
  wire \rdDataAddr[3]_i_11_n_0 ;
  wire \rdDataAddr[3]_i_12_n_0 ;
  wire \rdDataAddr[3]_i_13_n_0 ;
  wire \rdDataAddr[3]_i_6_n_0 ;
  wire \rdDataAddr[3]_i_7_n_0 ;
  wire \rdDataAddr[3]_i_8_n_0 ;
  wire \rdDataAddr[3]_i_9_n_0 ;
  wire \rdDataAddr[3]_rep_i_1__0_n_0 ;
  wire \rdDataAddr[3]_rep_i_1__1_n_0 ;
  wire \rdDataAddr[3]_rep_i_1_n_0 ;
  wire \rdDataAddr[4]_i_10_n_0 ;
  wire \rdDataAddr[4]_i_11_n_0 ;
  wire \rdDataAddr[4]_i_12_n_0 ;
  wire \rdDataAddr[4]_i_13_n_0 ;
  wire \rdDataAddr[4]_i_6_n_0 ;
  wire \rdDataAddr[4]_i_7_n_0 ;
  wire \rdDataAddr[4]_i_8_n_0 ;
  wire \rdDataAddr[4]_i_9_n_0 ;
  wire \rdDataAddr[4]_rep_i_1__0_n_0 ;
  wire \rdDataAddr[4]_rep_i_1__1_n_0 ;
  wire \rdDataAddr[4]_rep_i_1_n_0 ;
  wire \rdDataAddr_reg[0]_i_2_n_0 ;
  wire \rdDataAddr_reg[0]_i_3_n_0 ;
  wire \rdDataAddr_reg[0]_i_4_n_0 ;
  wire \rdDataAddr_reg[0]_i_5_n_0 ;
  wire \rdDataAddr_reg[1]_i_2_n_0 ;
  wire \rdDataAddr_reg[1]_i_3_n_0 ;
  wire \rdDataAddr_reg[1]_i_4_n_0 ;
  wire \rdDataAddr_reg[1]_i_5_n_0 ;
  wire \rdDataAddr_reg[2]_i_2_n_0 ;
  wire \rdDataAddr_reg[2]_i_3_n_0 ;
  wire \rdDataAddr_reg[2]_i_4_n_0 ;
  wire \rdDataAddr_reg[2]_i_5_n_0 ;
  wire \rdDataAddr_reg[3]_i_2_n_0 ;
  wire \rdDataAddr_reg[3]_i_3_n_0 ;
  wire \rdDataAddr_reg[3]_i_4_n_0 ;
  wire \rdDataAddr_reg[3]_i_5_n_0 ;
  wire \rdDataAddr_reg[3]_rep_0 ;
  wire \rdDataAddr_reg[3]_rep__0_0 ;
  wire \rdDataAddr_reg[3]_rep__1_0 ;
  wire \rdDataAddr_reg[4]_0 ;
  wire \rdDataAddr_reg[4]_1 ;
  wire \rdDataAddr_reg[4]_2 ;
  wire \rdDataAddr_reg[4]_i_2_n_0 ;
  wire \rdDataAddr_reg[4]_i_3_n_0 ;
  wire \rdDataAddr_reg[4]_i_4_n_0 ;
  wire \rdDataAddr_reg[4]_i_5_n_0 ;
  wire \rdDataAddr_reg[4]_rep_0 ;
  wire \rdDataAddr_reg[4]_rep__0_0 ;
  wire \rdDataAddr_reg[4]_rep__1_0 ;
  wire \rdDataAddr_reg[4]_rep__1_1 ;
  wire [5:0]\rdData_reg[101] ;
  wire [5:0]\rdData_reg[107] ;
  wire [5:0]\rdData_reg[113] ;
  wire [5:0]\rdData_reg[119] ;
  wire [5:0]\rdData_reg[11] ;
  wire [5:0]\rdData_reg[125] ;
  wire [5:0]\rdData_reg[131] ;
  wire [5:0]\rdData_reg[137] ;
  wire [5:0]\rdData_reg[143] ;
  wire [5:0]\rdData_reg[149] ;
  wire [5:0]\rdData_reg[155] ;
  wire [5:0]\rdData_reg[161] ;
  wire [5:0]\rdData_reg[167] ;
  wire [5:0]\rdData_reg[173] ;
  wire [5:0]\rdData_reg[179] ;
  wire [5:0]\rdData_reg[17] ;
  wire [5:0]\rdData_reg[185] ;
  wire [5:0]\rdData_reg[191] ;
  wire [5:0]\rdData_reg[197] ;
  wire [5:0]\rdData_reg[203] ;
  wire [5:0]\rdData_reg[209] ;
  wire [5:0]\rdData_reg[215] ;
  wire [5:0]\rdData_reg[221] ;
  wire [5:0]\rdData_reg[227] ;
  wire [5:0]\rdData_reg[233] ;
  wire [5:0]\rdData_reg[239] ;
  wire [5:0]\rdData_reg[23] ;
  wire [5:0]\rdData_reg[245] ;
  wire [5:0]\rdData_reg[251] ;
  wire [5:0]\rdData_reg[257] ;
  wire [5:0]\rdData_reg[263] ;
  wire [5:0]\rdData_reg[269] ;
  wire [5:0]\rdData_reg[275] ;
  wire [5:0]\rdData_reg[281] ;
  wire [5:0]\rdData_reg[287] ;
  wire [5:0]\rdData_reg[293] ;
  wire [5:0]\rdData_reg[299] ;
  wire [5:0]\rdData_reg[29] ;
  wire [5:0]\rdData_reg[305] ;
  wire [5:0]\rdData_reg[311] ;
  wire [5:0]\rdData_reg[317] ;
  wire [5:0]\rdData_reg[323] ;
  wire [5:0]\rdData_reg[329] ;
  wire [5:0]\rdData_reg[335] ;
  wire [5:0]\rdData_reg[341] ;
  wire [5:0]\rdData_reg[347] ;
  wire [5:0]\rdData_reg[353] ;
  wire [5:0]\rdData_reg[359] ;
  wire [5:0]\rdData_reg[35] ;
  wire [5:0]\rdData_reg[365] ;
  wire [5:0]\rdData_reg[371] ;
  wire [5:0]\rdData_reg[377] ;
  wire [5:0]\rdData_reg[383] ;
  wire [5:0]\rdData_reg[389] ;
  wire [5:0]\rdData_reg[395] ;
  wire [5:0]\rdData_reg[401] ;
  wire [5:0]\rdData_reg[407] ;
  wire [5:0]\rdData_reg[413] ;
  wire [5:0]\rdData_reg[419] ;
  wire [5:0]\rdData_reg[41] ;
  wire [5:0]\rdData_reg[425] ;
  wire [5:0]\rdData_reg[431] ;
  wire [5:0]\rdData_reg[437] ;
  wire [5:0]\rdData_reg[443] ;
  wire [5:0]\rdData_reg[449] ;
  wire [5:0]\rdData_reg[455] ;
  wire [5:0]\rdData_reg[461] ;
  wire [5:0]\rdData_reg[467] ;
  wire [5:0]\rdData_reg[473] ;
  wire [5:0]\rdData_reg[479] ;
  wire [5:0]\rdData_reg[47] ;
  wire [5:0]\rdData_reg[485] ;
  wire [5:0]\rdData_reg[491] ;
  wire [5:0]\rdData_reg[497] ;
  wire [5:0]\rdData_reg[503] ;
  wire [5:0]\rdData_reg[509] ;
  wire [1:0]\rdData_reg[511] ;
  wire [5:0]\rdData_reg[53] ;
  wire [5:0]\rdData_reg[59] ;
  wire [5:0]\rdData_reg[5] ;
  wire [5:0]\rdData_reg[65] ;
  wire [5:0]\rdData_reg[71] ;
  wire [5:0]\rdData_reg[77] ;
  wire [5:0]\rdData_reg[83] ;
  wire [5:0]\rdData_reg[89] ;
  wire [5:0]\rdData_reg[95] ;
  wire rdInj;
  wire rdInj_i_10_n_0;
  wire rdInj_i_11_n_0;
  wire rdInj_i_12_n_0;
  wire rdInj_i_13_n_0;
  wire rdInj_i_6_n_0;
  wire rdInj_i_7_n_0;
  wire rdInj_i_8_n_0;
  wire rdInj_i_9_n_0;
  wire rdInj_nxt;
  wire rdInj_reg_i_2_n_0;
  wire rdInj_reg_i_3_n_0;
  wire rdInj_reg_i_4_n_0;
  wire rdInj_reg_i_5_n_0;
  wire rdRmw;
  wire rdRmw_i_10_n_0;
  wire rdRmw_i_11_n_0;
  wire rdRmw_i_12_n_0;
  wire rdRmw_i_13_n_0;
  wire rdRmw_i_6_n_0;
  wire rdRmw_i_7_n_0;
  wire rdRmw_i_8_n_0;
  wire rdRmw_i_9_n_0;
  wire rdRmw_nxt;
  wire rdRmw_reg_i_2_n_0;
  wire rdRmw_reg_i_3_n_0;
  wire rdRmw_reg_i_4_n_0;
  wire rdRmw_reg_i_5_n_0;
  wire read_data_en_reg_0;
  wire [4:0]read_lat_fifo;
  wire \read_lat_fifo[0][6]_i_1_n_0 ;
  wire \read_lat_fifo[10][6]_i_1_n_0 ;
  wire \read_lat_fifo[11][6]_i_1_n_0 ;
  wire \read_lat_fifo[12][6]_i_1_n_0 ;
  wire \read_lat_fifo[13][6]_i_1_n_0 ;
  wire \read_lat_fifo[14][6]_i_1_n_0 ;
  wire \read_lat_fifo[15][6]_i_1_n_0 ;
  wire \read_lat_fifo[16][6]_i_1_n_0 ;
  wire \read_lat_fifo[17][6]_i_1_n_0 ;
  wire \read_lat_fifo[18][6]_i_1_n_0 ;
  wire \read_lat_fifo[19][6]_i_1_n_0 ;
  wire \read_lat_fifo[1][6]_i_1_n_0 ;
  wire \read_lat_fifo[20][6]_i_1_n_0 ;
  wire \read_lat_fifo[21][6]_i_1_n_0 ;
  wire \read_lat_fifo[22][6]_i_1_n_0 ;
  wire \read_lat_fifo[23][6]_i_1_n_0 ;
  wire \read_lat_fifo[24][6]_i_1_n_0 ;
  wire \read_lat_fifo[25][6]_i_1_n_0 ;
  wire \read_lat_fifo[26][6]_i_1_n_0 ;
  wire \read_lat_fifo[27][6]_i_1_n_0 ;
  wire \read_lat_fifo[28][6]_i_1_n_0 ;
  wire \read_lat_fifo[29][6]_i_1_n_0 ;
  wire \read_lat_fifo[2][6]_i_1_n_0 ;
  wire \read_lat_fifo[30][6]_i_1_n_0 ;
  wire \read_lat_fifo[31][6]_i_1_n_0 ;
  wire \read_lat_fifo[3][6]_i_1_n_0 ;
  wire \read_lat_fifo[4][6]_i_1_n_0 ;
  wire \read_lat_fifo[5][6]_i_1_n_0 ;
  wire \read_lat_fifo[6][6]_i_1_n_0 ;
  wire \read_lat_fifo[7][6]_i_1_n_0 ;
  wire \read_lat_fifo[8][6]_i_1_n_0 ;
  wire \read_lat_fifo[9][6]_i_1_n_0 ;
  wire [6:0]read_lat_fifo_in;
  wire [6:0]\read_lat_fifo_in_reg[6]_0 ;
  wire [6:0]\read_lat_fifo_reg[0]_53 ;
  wire [6:0]\read_lat_fifo_reg[10]_43 ;
  wire [6:0]\read_lat_fifo_reg[11]_42 ;
  wire [6:0]\read_lat_fifo_reg[12]_41 ;
  wire [6:0]\read_lat_fifo_reg[13]_40 ;
  wire [6:0]\read_lat_fifo_reg[14]_39 ;
  wire [6:0]\read_lat_fifo_reg[15]_38 ;
  wire [6:0]\read_lat_fifo_reg[16]_37 ;
  wire [6:0]\read_lat_fifo_reg[17]_36 ;
  wire [6:0]\read_lat_fifo_reg[18]_35 ;
  wire [6:0]\read_lat_fifo_reg[19]_34 ;
  wire [6:0]\read_lat_fifo_reg[1]_52 ;
  wire [6:0]\read_lat_fifo_reg[20]_33 ;
  wire [6:0]\read_lat_fifo_reg[21]_32 ;
  wire [6:0]\read_lat_fifo_reg[22]_31 ;
  wire [6:0]\read_lat_fifo_reg[23]_30 ;
  wire [6:0]\read_lat_fifo_reg[24]_29 ;
  wire [6:0]\read_lat_fifo_reg[25]_28 ;
  wire [6:0]\read_lat_fifo_reg[26]_27 ;
  wire [6:0]\read_lat_fifo_reg[27]_26 ;
  wire [6:0]\read_lat_fifo_reg[28]_25 ;
  wire [6:0]\read_lat_fifo_reg[29]_24 ;
  wire [6:0]\read_lat_fifo_reg[2]_51 ;
  wire [6:0]\read_lat_fifo_reg[30]_23 ;
  wire [6:0]\read_lat_fifo_reg[31]_22 ;
  wire [6:0]\read_lat_fifo_reg[3]_50 ;
  wire [6:0]\read_lat_fifo_reg[4]_49 ;
  wire [6:0]\read_lat_fifo_reg[5]_48 ;
  wire [6:0]\read_lat_fifo_reg[6]_47 ;
  wire [6:0]\read_lat_fifo_reg[7]_46 ;
  wire [6:0]\read_lat_fifo_reg[8]_45 ;
  wire [6:0]\read_lat_fifo_reg[9]_44 ;
  wire [4:0]read_lat_rptr_reg;
  wire read_lat_shift_cal_dq_valid_nxt;
  wire [0:0]read_lat_shift_nxt;
  wire [31:0]\read_lat_shift_reg[31]_0 ;
  wire read_lat_wptr;
  wire [4:0]read_lat_wptr_reg;
  wire rmw_rd_done;
  wire \u_ddr_ui/u_ddr_ui_rd_data/match6_189_return2_in ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns1 ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns110_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns111_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns112_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns113_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns114_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns115_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns116_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns117_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns118_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns119_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns120_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns121_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns122_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns123_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns124_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns125_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns126_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns127_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns128_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns129_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns130_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns131_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns132_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns133_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns134_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns135_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns136_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns137_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns138_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns139_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns140_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns141_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns142_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns143_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns144_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns145_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns146_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns147_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns148_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns149_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns14_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns150_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns151_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns152_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns153_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns154_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns155_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns156_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns157_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns158_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns159_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns15_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns160_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns161_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns162_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns163_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns164_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns165_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns166_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns167_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns168_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns169_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns16_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns170_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns171_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns172_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns173_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns174_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns175_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns176_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns177_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns178_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns179_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns17_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns180_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns181_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns182_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns183_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns184_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns185_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns186_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns187_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns188_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns18_out ;
  wire \u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns19_out ;
  wire underfill_done_i_2__0_n_0;
  wire underfill_done_i_2__1_n_0;
  wire underfill_done_i_2__2_n_0;
  wire underfill_done_i_3_n_0;
  wire underfill_done_nxt;

  LUT3 #(
    .INIT(8'h80)) 
    \FSM_sequential_inject_state[3]_i_8 
       (.I0(rdCAS_reg_0),
        .I1(read_data_en_reg_0),
        .I2(rdInj),
        .O(per_rd_done));
  LUT2 #(
    .INIT(4'h2)) 
    \dqin_valid_shift[0]_i_1 
       (.I0(pop_read_lat_fifo),
        .I1(cnt_clr),
        .O(pop_read_lat_fifo_reg_0));
  FDRE \mc_clb2phy_fifo_rden_nxt_reg[103] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(read_lat_shift_cal_dq_valid_nxt),
        .Q(mc_clb2phy_fifo_rden_nxt),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \not_strict_mode.app_rd_data_end_i_1 
       (.I0(\not_strict_mode.bypass_cpy2 ),
        .I1(DOA),
        .O(\not_strict_mode.status_ram_0.RAM32M0 ));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.app_rd_data_end_i_2 
       (.I0(calDone_reg),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/match6_189_return2_in ),
        .I2(Q[3]),
        .I3(\not_strict_mode.app_rd_data_end_reg [3]),
        .I4(Q[4]),
        .I5(\not_strict_mode.app_rd_data_end_reg [4]),
        .O(\not_strict_mode.bypass_cpy2 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.app_rd_data_end_i_3 
       (.I0(Q[1]),
        .I1(\not_strict_mode.app_rd_data_end_reg [1]),
        .I2(\not_strict_mode.app_rd_data_end_reg [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.app_rd_data_end_reg [2]),
        .I5(Q[2]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/match6_189_return2_in ));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_1 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [85]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [85]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_10 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [76]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [76]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_11 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [75]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [75]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_12 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [74]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [74]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_13 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [73]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [73]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_14 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [72]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [72]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_15 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [71]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [71]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_16 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [70]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [70]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_17 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [69]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [69]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_18 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [68]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [68]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_19 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [67]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [67]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_2 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [84]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [84]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_20 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [66]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [66]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_21 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [65]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [65]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_22 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [64]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [64]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_23 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [63]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [63]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_24 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [62]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [62]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_25 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [61]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [61]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_26 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [60]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [60]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_27 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [59]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [59]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_28 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [58]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [58]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_29 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [57]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [57]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_3 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [83]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [83]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_30 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [56]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [56]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_31 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [55]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [55]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_32 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [54]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [54]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_33 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [53]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [53]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_34 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [52]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [52]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_35 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [51]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [51]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_36 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [50]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [50]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_37 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [49]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [49]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_38 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [48]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [48]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_39 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [47]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [47]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_4 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [82]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [82]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_40 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [46]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [46]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_41 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [45]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [45]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_42 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [44]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [44]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_43 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [43]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [43]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_44 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [42]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [42]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_45 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [41]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [41]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_46 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [40]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [40]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_47 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [39]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [39]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_48 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [38]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [38]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_49 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [37]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [37]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_5 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [81]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [81]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_50 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [36]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [36]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_51 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [35]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [35]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_52 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [34]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [34]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_53 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [33]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [33]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_54 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [32]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [32]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_55 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [31]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [31]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_56 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [30]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [30]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_57 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [29]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [29]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_58 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [28]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [28]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_59 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [27]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [27]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_6 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [80]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [80]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_60 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [26]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [26]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_61 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [25]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [25]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_62 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [24]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [24]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_63 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [23]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [23]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_64 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [22]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [22]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_65 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [21]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [21]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_66 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [20]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [20]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_67 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [19]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [19]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_68 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [18]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [18]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_69 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [17]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [17]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_7 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [79]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [79]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_70 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [16]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [16]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_71 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [15]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [15]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_72 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [14]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [14]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_73 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [13]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [13]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_74 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [12]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [12]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_75 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [11]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [11]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_76 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [10]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [10]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_77 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [9]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [9]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_78 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [8]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [8]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_79 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [7]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [7]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_8 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [78]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [78]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_80 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [6]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [6]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_81 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [5]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [5]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_82 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [4]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_83 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [3]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_84 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [2]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_85 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [1]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_86 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [0]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [0]));
  LUT2 #(
    .INIT(4'hB)) 
    \not_strict_mode.rd_buf.rd_buf_we_inferred_i_9 
       (.I0(calDone_reg),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 [77]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] [77]));
  (* SOFT_HLUTNM = "soft_lutpair2223" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns[0]_i_1 
       (.I0(D[0]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns188_out ),
        .I2(DOC[0]),
        .O(\rdData_reg[5] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2223" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns[1]_i_1 
       (.I0(D[8]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns188_out ),
        .I2(DOC[1]),
        .O(\rdData_reg[5] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2224" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns[2]_i_1 
       (.I0(D[16]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns188_out ),
        .I2(DOB[0]),
        .O(\rdData_reg[5] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2224" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns[3]_i_1 
       (.I0(D[24]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns188_out ),
        .I2(DOB[1]),
        .O(\rdData_reg[5] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2225" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns[4]_i_1 
       (.I0(D[32]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns188_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] [0]),
        .O(\rdData_reg[5] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2225" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns[5]_i_1 
       (.I0(D[40]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns188_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] [1]),
        .O(\rdData_reg[5] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns[5]_i_2 
       (.I0(calDone_reg),
        .I1(match6_13_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns188_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r[0][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [4]),
        .O(match4_13_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r[0][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [2]),
        .I5(Q[2]),
        .O(match6_13_return));
  (* SOFT_HLUTNM = "soft_lutpair2253" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns[60]_i_1 
       (.I0(D[39]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns178_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] [0]),
        .O(\rdData_reg[65] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2253" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns[61]_i_1 
       (.I0(D[47]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns178_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] [1]),
        .O(\rdData_reg[65] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2254" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns[62]_i_1 
       (.I0(D[55]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns178_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] [0]),
        .O(\rdData_reg[65] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2254" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns[63]_i_1 
       (.I0(D[63]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns178_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] [1]),
        .O(\rdData_reg[65] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2255" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns[64]_i_1 
       (.I0(D[64]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns178_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] [0]),
        .O(\rdData_reg[65] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2255" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns[65]_i_1 
       (.I0(D[72]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns178_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] [1]),
        .O(\rdData_reg[65] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns[65]_i_2 
       (.I0(calDone_reg),
        .I1(match6_113_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns178_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r[10][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [4]),
        .O(match4_113_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r[10][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [2]),
        .I5(Q[2]),
        .O(match6_113_return));
  (* SOFT_HLUTNM = "soft_lutpair2256" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns[66]_i_1 
       (.I0(D[80]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns177_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] [0]),
        .O(\rdData_reg[71] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2256" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns[67]_i_1 
       (.I0(D[88]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns177_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] [1]),
        .O(\rdData_reg[71] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2257" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns[68]_i_1 
       (.I0(D[96]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns177_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] [0]),
        .O(\rdData_reg[71] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2257" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns[69]_i_1 
       (.I0(D[104]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns177_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] [1]),
        .O(\rdData_reg[71] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2258" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns[70]_i_1 
       (.I0(D[112]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns177_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] [0]),
        .O(\rdData_reg[71] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2258" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns[71]_i_1 
       (.I0(D[120]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns177_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] [1]),
        .O(\rdData_reg[71] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns[71]_i_2 
       (.I0(calDone_reg),
        .I1(match6_114_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns177_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r[11][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [4]),
        .O(match4_114_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r[11][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [2]),
        .I5(Q[2]),
        .O(match6_114_return));
  (* SOFT_HLUTNM = "soft_lutpair2259" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns[72]_i_1 
       (.I0(D[65]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns176_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] [0]),
        .O(\rdData_reg[77] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2259" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns[73]_i_1 
       (.I0(D[73]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns176_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] [1]),
        .O(\rdData_reg[77] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2260" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns[74]_i_1 
       (.I0(D[81]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns176_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] [0]),
        .O(\rdData_reg[77] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2260" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns[75]_i_1 
       (.I0(D[89]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns176_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] [1]),
        .O(\rdData_reg[77] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2261" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns[76]_i_1 
       (.I0(D[97]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns176_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] [0]),
        .O(\rdData_reg[77] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2261" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns[77]_i_1 
       (.I0(D[105]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns176_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] [1]),
        .O(\rdData_reg[77] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns[77]_i_2 
       (.I0(calDone_reg),
        .I1(match6_115_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns176_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r[12][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [4]),
        .O(match4_115_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r[12][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [2]),
        .I5(Q[2]),
        .O(match6_115_return));
  (* SOFT_HLUTNM = "soft_lutpair2262" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns[78]_i_1 
       (.I0(D[113]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns175_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] [0]),
        .O(\rdData_reg[83] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2262" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns[79]_i_1 
       (.I0(D[121]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns175_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] [1]),
        .O(\rdData_reg[83] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2263" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns[80]_i_1 
       (.I0(D[66]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns175_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] [0]),
        .O(\rdData_reg[83] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2263" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns[81]_i_1 
       (.I0(D[74]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns175_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] [1]),
        .O(\rdData_reg[83] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2264" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns[82]_i_1 
       (.I0(D[82]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns175_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] [0]),
        .O(\rdData_reg[83] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2264" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns[83]_i_1 
       (.I0(D[90]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns175_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] [1]),
        .O(\rdData_reg[83] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns[83]_i_2 
       (.I0(calDone_reg),
        .I1(match6_116_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns175_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r[13][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [4]),
        .O(match4_116_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r[13][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [2]),
        .I5(Q[2]),
        .O(match6_116_return));
  (* SOFT_HLUTNM = "soft_lutpair2265" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns[84]_i_1 
       (.I0(D[98]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns174_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] [0]),
        .O(\rdData_reg[89] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2265" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns[85]_i_1 
       (.I0(D[106]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns174_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] [1]),
        .O(\rdData_reg[89] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2266" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns[86]_i_1 
       (.I0(D[114]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns174_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] [0]),
        .O(\rdData_reg[89] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2266" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns[87]_i_1 
       (.I0(D[122]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns174_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] [1]),
        .O(\rdData_reg[89] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2267" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns[88]_i_1 
       (.I0(D[67]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns174_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] [0]),
        .O(\rdData_reg[89] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2267" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns[89]_i_1 
       (.I0(D[75]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns174_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] [1]),
        .O(\rdData_reg[89] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns[89]_i_2 
       (.I0(calDone_reg),
        .I1(match6_117_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns174_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r[14][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [4]),
        .O(match4_117_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r[14][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [2]),
        .I5(Q[2]),
        .O(match6_117_return));
  (* SOFT_HLUTNM = "soft_lutpair2268" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns[90]_i_1 
       (.I0(D[83]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns173_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] [0]),
        .O(\rdData_reg[95] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2268" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns[91]_i_1 
       (.I0(D[91]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns173_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] [1]),
        .O(\rdData_reg[95] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2269" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns[92]_i_1 
       (.I0(D[99]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns173_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] [0]),
        .O(\rdData_reg[95] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2269" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns[93]_i_1 
       (.I0(D[107]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns173_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] [1]),
        .O(\rdData_reg[95] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2270" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns[94]_i_1 
       (.I0(D[115]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns173_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] [0]),
        .O(\rdData_reg[95] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2270" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns[95]_i_1 
       (.I0(D[123]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns173_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] [1]),
        .O(\rdData_reg[95] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns[95]_i_2 
       (.I0(calDone_reg),
        .I1(match6_118_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns173_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r[15][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [4]),
        .O(match4_118_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r[15][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [2]),
        .I5(Q[2]),
        .O(match6_118_return));
  (* SOFT_HLUTNM = "soft_lutpair2273" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns[100]_i_1 
       (.I0(D[100]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns172_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] [0]),
        .O(\rdData_reg[101] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2273" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns[101]_i_1 
       (.I0(D[108]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns172_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] [1]),
        .O(\rdData_reg[101] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns[101]_i_2 
       (.I0(calDone_reg),
        .I1(match6_119_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns172_out ));
  (* SOFT_HLUTNM = "soft_lutpair2271" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns[96]_i_1 
       (.I0(D[68]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns172_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] [0]),
        .O(\rdData_reg[101] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2271" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns[97]_i_1 
       (.I0(D[76]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns172_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] [1]),
        .O(\rdData_reg[101] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2272" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns[98]_i_1 
       (.I0(D[84]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns172_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] [0]),
        .O(\rdData_reg[101] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2272" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns[99]_i_1 
       (.I0(D[92]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns172_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] [1]),
        .O(\rdData_reg[101] [3]));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r[16][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [4]),
        .O(match4_119_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r[16][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [2]),
        .I5(Q[2]),
        .O(match6_119_return));
  (* SOFT_HLUTNM = "soft_lutpair2274" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns[102]_i_1 
       (.I0(D[116]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns171_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] [0]),
        .O(\rdData_reg[107] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2274" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns[103]_i_1 
       (.I0(D[124]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns171_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] [1]),
        .O(\rdData_reg[107] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2275" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns[104]_i_1 
       (.I0(D[69]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns171_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] [0]),
        .O(\rdData_reg[107] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2275" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns[105]_i_1 
       (.I0(D[77]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns171_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] [1]),
        .O(\rdData_reg[107] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2276" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns[106]_i_1 
       (.I0(D[85]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns171_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] [0]),
        .O(\rdData_reg[107] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2276" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns[107]_i_1 
       (.I0(D[93]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns171_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] [1]),
        .O(\rdData_reg[107] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns[107]_i_2 
       (.I0(calDone_reg),
        .I1(match6_120_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns171_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r[17][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [4]),
        .O(match4_120_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r[17][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [2]),
        .I5(Q[2]),
        .O(match6_120_return));
  (* SOFT_HLUTNM = "soft_lutpair2277" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns[108]_i_1 
       (.I0(D[101]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns170_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] [0]),
        .O(\rdData_reg[113] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2277" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns[109]_i_1 
       (.I0(D[109]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns170_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] [1]),
        .O(\rdData_reg[113] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2278" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns[110]_i_1 
       (.I0(D[117]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns170_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] [0]),
        .O(\rdData_reg[113] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2278" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns[111]_i_1 
       (.I0(D[125]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns170_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] [1]),
        .O(\rdData_reg[113] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2279" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns[112]_i_1 
       (.I0(D[70]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns170_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] [0]),
        .O(\rdData_reg[113] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2279" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns[113]_i_1 
       (.I0(D[78]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns170_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] [1]),
        .O(\rdData_reg[113] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns[113]_i_2 
       (.I0(calDone_reg),
        .I1(match6_121_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns170_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r[18][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [4]),
        .O(match4_121_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r[18][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [2]),
        .I5(Q[2]),
        .O(match6_121_return));
  (* SOFT_HLUTNM = "soft_lutpair2280" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns[114]_i_1 
       (.I0(D[86]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns169_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] [0]),
        .O(\rdData_reg[119] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2280" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns[115]_i_1 
       (.I0(D[94]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns169_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] [1]),
        .O(\rdData_reg[119] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2281" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns[116]_i_1 
       (.I0(D[102]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns169_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] [0]),
        .O(\rdData_reg[119] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2281" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns[117]_i_1 
       (.I0(D[110]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns169_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] [1]),
        .O(\rdData_reg[119] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2282" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns[118]_i_1 
       (.I0(D[118]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns169_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] [0]),
        .O(\rdData_reg[119] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2282" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns[119]_i_1 
       (.I0(D[126]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns169_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] [1]),
        .O(\rdData_reg[119] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns[119]_i_2 
       (.I0(calDone_reg),
        .I1(match6_122_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns169_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r[19][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [4]),
        .O(match4_122_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r[19][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [2]),
        .I5(Q[2]),
        .O(match6_122_return));
  (* SOFT_HLUTNM = "soft_lutpair2228" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns[10]_i_1 
       (.I0(D[17]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns187_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] [0]),
        .O(\rdData_reg[11] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2228" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns[11]_i_1 
       (.I0(D[25]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns187_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] [1]),
        .O(\rdData_reg[11] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns[11]_i_2 
       (.I0(calDone_reg),
        .I1(match6_14_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns187_out ));
  (* SOFT_HLUTNM = "soft_lutpair2226" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns[6]_i_1 
       (.I0(D[48]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns187_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] [0]),
        .O(\rdData_reg[11] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2226" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns[7]_i_1 
       (.I0(D[56]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns187_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] [1]),
        .O(\rdData_reg[11] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2227" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns[8]_i_1 
       (.I0(D[1]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns187_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] [0]),
        .O(\rdData_reg[11] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2227" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns[9]_i_1 
       (.I0(D[9]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns187_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] [1]),
        .O(\rdData_reg[11] [3]));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r[1][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [4]),
        .O(match4_14_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r[1][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [2]),
        .I5(Q[2]),
        .O(match6_14_return));
  (* SOFT_HLUTNM = "soft_lutpair2283" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns[120]_i_1 
       (.I0(D[71]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns168_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] [0]),
        .O(\rdData_reg[125] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2283" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns[121]_i_1 
       (.I0(D[79]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns168_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] [1]),
        .O(\rdData_reg[125] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2284" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns[122]_i_1 
       (.I0(D[87]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns168_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] [0]),
        .O(\rdData_reg[125] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2284" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns[123]_i_1 
       (.I0(D[95]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns168_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] [1]),
        .O(\rdData_reg[125] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2285" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns[124]_i_1 
       (.I0(D[103]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns168_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] [0]),
        .O(\rdData_reg[125] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2285" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns[125]_i_1 
       (.I0(D[111]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns168_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] [1]),
        .O(\rdData_reg[125] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns[125]_i_2 
       (.I0(calDone_reg),
        .I1(match6_123_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns168_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r[20][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [4]),
        .O(match4_123_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r[20][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [2]),
        .I5(Q[2]),
        .O(match6_123_return));
  (* SOFT_HLUTNM = "soft_lutpair2286" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns[126]_i_1 
       (.I0(D[119]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns167_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] [0]),
        .O(\rdData_reg[131] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2286" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns[127]_i_1 
       (.I0(D[127]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns167_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] [1]),
        .O(\rdData_reg[131] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2287" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns[128]_i_1 
       (.I0(D[128]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns167_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] [0]),
        .O(\rdData_reg[131] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2287" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns[129]_i_1 
       (.I0(D[136]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns167_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] [1]),
        .O(\rdData_reg[131] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2288" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns[130]_i_1 
       (.I0(D[144]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns167_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] [0]),
        .O(\rdData_reg[131] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2288" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns[131]_i_1 
       (.I0(D[152]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns167_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] [1]),
        .O(\rdData_reg[131] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns[131]_i_2 
       (.I0(calDone_reg),
        .I1(match6_124_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns167_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r[21][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [4]),
        .O(match4_124_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r[21][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [2]),
        .I5(Q[2]),
        .O(match6_124_return));
  (* SOFT_HLUTNM = "soft_lutpair2289" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns[132]_i_1 
       (.I0(D[160]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns166_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] [0]),
        .O(\rdData_reg[137] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2289" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns[133]_i_1 
       (.I0(D[168]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns166_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] [1]),
        .O(\rdData_reg[137] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2290" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns[134]_i_1 
       (.I0(D[176]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns166_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] [0]),
        .O(\rdData_reg[137] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2290" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns[135]_i_1 
       (.I0(D[184]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns166_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] [1]),
        .O(\rdData_reg[137] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2291" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns[136]_i_1 
       (.I0(D[129]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns166_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] [0]),
        .O(\rdData_reg[137] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2291" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns[137]_i_1 
       (.I0(D[137]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns166_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] [1]),
        .O(\rdData_reg[137] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns[137]_i_2 
       (.I0(calDone_reg),
        .I1(match6_125_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns166_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r[22][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [4]),
        .O(match4_125_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r[22][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [2]),
        .I5(Q[2]),
        .O(match6_125_return));
  (* SOFT_HLUTNM = "soft_lutpair2292" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns[138]_i_1 
       (.I0(D[145]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns165_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] [0]),
        .O(\rdData_reg[143] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2292" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns[139]_i_1 
       (.I0(D[153]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns165_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] [1]),
        .O(\rdData_reg[143] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2293" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns[140]_i_1 
       (.I0(D[161]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns165_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] [0]),
        .O(\rdData_reg[143] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2293" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns[141]_i_1 
       (.I0(D[169]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns165_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] [1]),
        .O(\rdData_reg[143] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2294" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns[142]_i_1 
       (.I0(D[177]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns165_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] [0]),
        .O(\rdData_reg[143] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2294" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns[143]_i_1 
       (.I0(D[185]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns165_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] [1]),
        .O(\rdData_reg[143] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns[143]_i_2 
       (.I0(calDone_reg),
        .I1(match6_126_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns165_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r[23][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [4]),
        .O(match4_126_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r[23][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [2]),
        .I5(Q[2]),
        .O(match6_126_return));
  (* SOFT_HLUTNM = "soft_lutpair2295" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns[144]_i_1 
       (.I0(D[130]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns164_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] [0]),
        .O(\rdData_reg[149] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2295" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns[145]_i_1 
       (.I0(D[138]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns164_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] [1]),
        .O(\rdData_reg[149] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2296" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns[146]_i_1 
       (.I0(D[146]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns164_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] [0]),
        .O(\rdData_reg[149] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2296" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns[147]_i_1 
       (.I0(D[154]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns164_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] [1]),
        .O(\rdData_reg[149] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2297" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns[148]_i_1 
       (.I0(D[162]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns164_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] [0]),
        .O(\rdData_reg[149] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2297" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns[149]_i_1 
       (.I0(D[170]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns164_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] [1]),
        .O(\rdData_reg[149] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns[149]_i_2 
       (.I0(calDone_reg),
        .I1(match6_127_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns164_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r[24][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [4]),
        .O(match4_127_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r[24][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [2]),
        .I5(Q[2]),
        .O(match6_127_return));
  (* SOFT_HLUTNM = "soft_lutpair2298" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns[150]_i_1 
       (.I0(D[178]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns163_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] [0]),
        .O(\rdData_reg[155] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2298" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns[151]_i_1 
       (.I0(D[186]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns163_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] [1]),
        .O(\rdData_reg[155] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2299" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns[152]_i_1 
       (.I0(D[131]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns163_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] [0]),
        .O(\rdData_reg[155] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2299" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns[153]_i_1 
       (.I0(D[139]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns163_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] [1]),
        .O(\rdData_reg[155] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2300" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns[154]_i_1 
       (.I0(D[147]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns163_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] [0]),
        .O(\rdData_reg[155] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2300" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns[155]_i_1 
       (.I0(D[155]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns163_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] [1]),
        .O(\rdData_reg[155] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns[155]_i_2 
       (.I0(calDone_reg),
        .I1(match6_128_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns163_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r[25][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [4]),
        .O(match4_128_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r[25][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [2]),
        .I5(Q[2]),
        .O(match6_128_return));
  (* SOFT_HLUTNM = "soft_lutpair2301" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns[156]_i_1 
       (.I0(D[163]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns162_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] [0]),
        .O(\rdData_reg[161] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2301" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns[157]_i_1 
       (.I0(D[171]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns162_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] [1]),
        .O(\rdData_reg[161] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2302" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns[158]_i_1 
       (.I0(D[179]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns162_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] [0]),
        .O(\rdData_reg[161] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2302" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns[159]_i_1 
       (.I0(D[187]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns162_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] [1]),
        .O(\rdData_reg[161] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2303" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns[160]_i_1 
       (.I0(D[132]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns162_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] [0]),
        .O(\rdData_reg[161] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2303" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns[161]_i_1 
       (.I0(D[140]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns162_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] [1]),
        .O(\rdData_reg[161] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns[161]_i_2 
       (.I0(calDone_reg),
        .I1(match6_129_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns162_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r[26][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [4]),
        .O(match4_129_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r[26][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [2]),
        .I5(Q[2]),
        .O(match6_129_return));
  (* SOFT_HLUTNM = "soft_lutpair2304" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns[162]_i_1 
       (.I0(D[148]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns161_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] [0]),
        .O(\rdData_reg[167] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2304" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns[163]_i_1 
       (.I0(D[156]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns161_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] [1]),
        .O(\rdData_reg[167] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2305" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns[164]_i_1 
       (.I0(D[164]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns161_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] [0]),
        .O(\rdData_reg[167] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2305" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns[165]_i_1 
       (.I0(D[172]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns161_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] [1]),
        .O(\rdData_reg[167] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2306" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns[166]_i_1 
       (.I0(D[180]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns161_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] [0]),
        .O(\rdData_reg[167] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2306" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns[167]_i_1 
       (.I0(D[188]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns161_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] [1]),
        .O(\rdData_reg[167] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns[167]_i_2 
       (.I0(calDone_reg),
        .I1(match6_130_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns161_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r[27][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [4]),
        .O(match4_130_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r[27][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [2]),
        .I5(Q[2]),
        .O(match6_130_return));
  (* SOFT_HLUTNM = "soft_lutpair2307" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns[168]_i_1 
       (.I0(D[133]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns160_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] [0]),
        .O(\rdData_reg[173] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2307" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns[169]_i_1 
       (.I0(D[141]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns160_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] [1]),
        .O(\rdData_reg[173] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2308" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns[170]_i_1 
       (.I0(D[149]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns160_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] [0]),
        .O(\rdData_reg[173] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2308" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns[171]_i_1 
       (.I0(D[157]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns160_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] [1]),
        .O(\rdData_reg[173] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2309" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns[172]_i_1 
       (.I0(D[165]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns160_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] [0]),
        .O(\rdData_reg[173] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2309" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns[173]_i_1 
       (.I0(D[173]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns160_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] [1]),
        .O(\rdData_reg[173] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns[173]_i_2 
       (.I0(calDone_reg),
        .I1(match6_131_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns160_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r[28][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [4]),
        .O(match4_131_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r[28][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [2]),
        .I5(Q[2]),
        .O(match6_131_return));
  (* SOFT_HLUTNM = "soft_lutpair2310" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns[174]_i_1 
       (.I0(D[181]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns159_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] [0]),
        .O(\rdData_reg[179] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2310" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns[175]_i_1 
       (.I0(D[189]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns159_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] [1]),
        .O(\rdData_reg[179] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2311" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns[176]_i_1 
       (.I0(D[134]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns159_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] [0]),
        .O(\rdData_reg[179] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2311" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns[177]_i_1 
       (.I0(D[142]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns159_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] [1]),
        .O(\rdData_reg[179] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2312" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns[178]_i_1 
       (.I0(D[150]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns159_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] [0]),
        .O(\rdData_reg[179] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2312" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns[179]_i_1 
       (.I0(D[158]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns159_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] [1]),
        .O(\rdData_reg[179] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns[179]_i_2 
       (.I0(calDone_reg),
        .I1(match6_132_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns159_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r[29][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [4]),
        .O(match4_132_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r[29][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [2]),
        .I5(Q[2]),
        .O(match6_132_return));
  (* SOFT_HLUTNM = "soft_lutpair2229" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns[12]_i_1 
       (.I0(D[33]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns186_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] [0]),
        .O(\rdData_reg[17] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2229" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns[13]_i_1 
       (.I0(D[41]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns186_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] [1]),
        .O(\rdData_reg[17] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2230" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns[14]_i_1 
       (.I0(D[49]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns186_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] [0]),
        .O(\rdData_reg[17] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2230" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns[15]_i_1 
       (.I0(D[57]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns186_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] [1]),
        .O(\rdData_reg[17] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2231" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns[16]_i_1 
       (.I0(D[2]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns186_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] [0]),
        .O(\rdData_reg[17] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2231" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns[17]_i_1 
       (.I0(D[10]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns186_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] [1]),
        .O(\rdData_reg[17] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns[17]_i_2 
       (.I0(calDone_reg),
        .I1(match6_15_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns186_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r[2][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [4]),
        .O(match4_15_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r[2][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [2]),
        .I5(Q[2]),
        .O(match6_15_return));
  (* SOFT_HLUTNM = "soft_lutpair2313" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns[180]_i_1 
       (.I0(D[166]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns158_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] [0]),
        .O(\rdData_reg[185] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2313" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns[181]_i_1 
       (.I0(D[174]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns158_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] [1]),
        .O(\rdData_reg[185] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2314" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns[182]_i_1 
       (.I0(D[182]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns158_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] [0]),
        .O(\rdData_reg[185] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2314" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns[183]_i_1 
       (.I0(D[190]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns158_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] [1]),
        .O(\rdData_reg[185] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2315" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns[184]_i_1 
       (.I0(D[135]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns158_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] [0]),
        .O(\rdData_reg[185] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2315" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns[185]_i_1 
       (.I0(D[143]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns158_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] [1]),
        .O(\rdData_reg[185] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns[185]_i_2 
       (.I0(calDone_reg),
        .I1(match6_133_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns158_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r[30][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [4]),
        .O(match4_133_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r[30][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [2]),
        .I5(Q[2]),
        .O(match6_133_return));
  (* SOFT_HLUTNM = "soft_lutpair2316" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns[186]_i_1 
       (.I0(D[151]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns157_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] [0]),
        .O(\rdData_reg[191] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2316" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns[187]_i_1 
       (.I0(D[159]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns157_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] [1]),
        .O(\rdData_reg[191] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2317" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns[188]_i_1 
       (.I0(D[167]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns157_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] [0]),
        .O(\rdData_reg[191] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2317" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns[189]_i_1 
       (.I0(D[175]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns157_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] [1]),
        .O(\rdData_reg[191] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2318" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns[190]_i_1 
       (.I0(D[183]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns157_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] [0]),
        .O(\rdData_reg[191] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2318" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns[191]_i_1 
       (.I0(D[191]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns157_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] [1]),
        .O(\rdData_reg[191] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns[191]_i_2 
       (.I0(calDone_reg),
        .I1(match6_134_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns157_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r[31][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [4]),
        .O(match4_134_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r[31][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [2]),
        .I5(Q[2]),
        .O(match6_134_return));
  (* SOFT_HLUTNM = "soft_lutpair2319" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns[192]_i_1 
       (.I0(D[192]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns156_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] [0]),
        .O(\rdData_reg[197] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2319" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns[193]_i_1 
       (.I0(D[200]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns156_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] [1]),
        .O(\rdData_reg[197] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2320" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns[194]_i_1 
       (.I0(D[208]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns156_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] [0]),
        .O(\rdData_reg[197] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2320" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns[195]_i_1 
       (.I0(D[216]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns156_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] [1]),
        .O(\rdData_reg[197] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2321" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns[196]_i_1 
       (.I0(D[224]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns156_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] [0]),
        .O(\rdData_reg[197] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2321" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns[197]_i_1 
       (.I0(D[232]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns156_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] [1]),
        .O(\rdData_reg[197] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns[197]_i_2 
       (.I0(calDone_reg),
        .I1(match6_135_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns156_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r[32][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [4]),
        .O(match4_135_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r[32][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [2]),
        .I5(Q[2]),
        .O(match6_135_return));
  (* SOFT_HLUTNM = "soft_lutpair2322" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns[198]_i_1 
       (.I0(D[240]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns155_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] [0]),
        .O(\rdData_reg[203] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2322" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns[199]_i_1 
       (.I0(D[248]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns155_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] [1]),
        .O(\rdData_reg[203] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2323" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns[200]_i_1 
       (.I0(D[193]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns155_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] [0]),
        .O(\rdData_reg[203] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2323" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns[201]_i_1 
       (.I0(D[201]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns155_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] [1]),
        .O(\rdData_reg[203] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2324" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns[202]_i_1 
       (.I0(D[209]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns155_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] [0]),
        .O(\rdData_reg[203] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2324" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns[203]_i_1 
       (.I0(D[217]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns155_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] [1]),
        .O(\rdData_reg[203] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns[203]_i_2 
       (.I0(calDone_reg),
        .I1(match6_136_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns155_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r[33][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [4]),
        .O(match4_136_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r[33][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [2]),
        .I5(Q[2]),
        .O(match6_136_return));
  (* SOFT_HLUTNM = "soft_lutpair2325" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns[204]_i_1 
       (.I0(D[225]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns154_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] [0]),
        .O(\rdData_reg[209] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2325" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns[205]_i_1 
       (.I0(D[233]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns154_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] [1]),
        .O(\rdData_reg[209] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2326" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns[206]_i_1 
       (.I0(D[241]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns154_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] [0]),
        .O(\rdData_reg[209] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2326" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns[207]_i_1 
       (.I0(D[249]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns154_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] [1]),
        .O(\rdData_reg[209] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2327" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns[208]_i_1 
       (.I0(D[194]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns154_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] [0]),
        .O(\rdData_reg[209] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2327" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns[209]_i_1 
       (.I0(D[202]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns154_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] [1]),
        .O(\rdData_reg[209] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns[209]_i_2 
       (.I0(calDone_reg),
        .I1(match6_137_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns154_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r[34][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [4]),
        .O(match4_137_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r[34][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [2]),
        .I5(Q[2]),
        .O(match6_137_return));
  (* SOFT_HLUTNM = "soft_lutpair2328" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns[210]_i_1 
       (.I0(D[210]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns153_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] [0]),
        .O(\rdData_reg[215] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2328" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns[211]_i_1 
       (.I0(D[218]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns153_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] [1]),
        .O(\rdData_reg[215] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2329" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns[212]_i_1 
       (.I0(D[226]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns153_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] [0]),
        .O(\rdData_reg[215] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2329" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns[213]_i_1 
       (.I0(D[234]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns153_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] [1]),
        .O(\rdData_reg[215] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2330" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns[214]_i_1 
       (.I0(D[242]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns153_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] [0]),
        .O(\rdData_reg[215] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2330" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns[215]_i_1 
       (.I0(D[250]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns153_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] [1]),
        .O(\rdData_reg[215] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns[215]_i_2 
       (.I0(calDone_reg),
        .I1(match6_138_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns153_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r[35][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [4]),
        .O(match4_138_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r[35][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [2]),
        .I5(Q[2]),
        .O(match6_138_return));
  (* SOFT_HLUTNM = "soft_lutpair2331" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns[216]_i_1 
       (.I0(D[195]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns152_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] [0]),
        .O(\rdData_reg[221] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2331" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns[217]_i_1 
       (.I0(D[203]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns152_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] [1]),
        .O(\rdData_reg[221] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2332" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns[218]_i_1 
       (.I0(D[211]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns152_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] [0]),
        .O(\rdData_reg[221] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2332" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns[219]_i_1 
       (.I0(D[219]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns152_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] [1]),
        .O(\rdData_reg[221] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2333" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns[220]_i_1 
       (.I0(D[227]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns152_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] [0]),
        .O(\rdData_reg[221] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2333" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns[221]_i_1 
       (.I0(D[235]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns152_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] [1]),
        .O(\rdData_reg[221] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns[221]_i_2 
       (.I0(calDone_reg),
        .I1(match6_139_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns152_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r[36][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [4]),
        .O(match4_139_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r[36][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [2]),
        .I5(Q[2]),
        .O(match6_139_return));
  (* SOFT_HLUTNM = "soft_lutpair2334" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns[222]_i_1 
       (.I0(D[243]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns151_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] [0]),
        .O(\rdData_reg[227] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2334" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns[223]_i_1 
       (.I0(D[251]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns151_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] [1]),
        .O(\rdData_reg[227] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2335" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns[224]_i_1 
       (.I0(D[196]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns151_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] [0]),
        .O(\rdData_reg[227] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2335" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns[225]_i_1 
       (.I0(D[204]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns151_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] [1]),
        .O(\rdData_reg[227] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2336" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns[226]_i_1 
       (.I0(D[212]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns151_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] [0]),
        .O(\rdData_reg[227] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2336" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns[227]_i_1 
       (.I0(D[220]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns151_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] [1]),
        .O(\rdData_reg[227] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns[227]_i_2 
       (.I0(calDone_reg),
        .I1(match6_140_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns151_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r[37][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [4]),
        .O(match4_140_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r[37][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [2]),
        .I5(Q[2]),
        .O(match6_140_return));
  (* SOFT_HLUTNM = "soft_lutpair2337" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns[228]_i_1 
       (.I0(D[228]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns150_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] [0]),
        .O(\rdData_reg[233] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2337" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns[229]_i_1 
       (.I0(D[236]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns150_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] [1]),
        .O(\rdData_reg[233] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2338" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns[230]_i_1 
       (.I0(D[244]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns150_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] [0]),
        .O(\rdData_reg[233] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2338" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns[231]_i_1 
       (.I0(D[252]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns150_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] [1]),
        .O(\rdData_reg[233] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2339" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns[232]_i_1 
       (.I0(D[197]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns150_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] [0]),
        .O(\rdData_reg[233] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2339" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns[233]_i_1 
       (.I0(D[205]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns150_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] [1]),
        .O(\rdData_reg[233] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns[233]_i_2 
       (.I0(calDone_reg),
        .I1(match6_141_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns150_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r[38][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [4]),
        .O(match4_141_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r[38][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [2]),
        .I5(Q[2]),
        .O(match6_141_return));
  (* SOFT_HLUTNM = "soft_lutpair2340" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns[234]_i_1 
       (.I0(D[213]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns149_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] [0]),
        .O(\rdData_reg[239] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2340" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns[235]_i_1 
       (.I0(D[221]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns149_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] [1]),
        .O(\rdData_reg[239] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2341" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns[236]_i_1 
       (.I0(D[229]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns149_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] [0]),
        .O(\rdData_reg[239] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2341" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns[237]_i_1 
       (.I0(D[237]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns149_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] [1]),
        .O(\rdData_reg[239] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2342" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns[238]_i_1 
       (.I0(D[245]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns149_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] [0]),
        .O(\rdData_reg[239] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2342" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns[239]_i_1 
       (.I0(D[253]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns149_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] [1]),
        .O(\rdData_reg[239] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns[239]_i_2 
       (.I0(calDone_reg),
        .I1(match6_142_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns149_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r[39][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [4]),
        .O(match4_142_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r[39][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [2]),
        .I5(Q[2]),
        .O(match6_142_return));
  (* SOFT_HLUTNM = "soft_lutpair2232" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns[18]_i_1 
       (.I0(D[18]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns185_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] [0]),
        .O(\rdData_reg[23] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2232" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns[19]_i_1 
       (.I0(D[26]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns185_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] [1]),
        .O(\rdData_reg[23] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2233" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns[20]_i_1 
       (.I0(D[34]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns185_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] [0]),
        .O(\rdData_reg[23] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2233" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns[21]_i_1 
       (.I0(D[42]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns185_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] [1]),
        .O(\rdData_reg[23] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2234" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns[22]_i_1 
       (.I0(D[50]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns185_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] [0]),
        .O(\rdData_reg[23] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2234" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns[23]_i_1 
       (.I0(D[58]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns185_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] [1]),
        .O(\rdData_reg[23] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns[23]_i_2 
       (.I0(calDone_reg),
        .I1(match6_16_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns185_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r[3][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [4]),
        .O(match4_16_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r[3][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [2]),
        .I5(Q[2]),
        .O(match6_16_return));
  (* SOFT_HLUTNM = "soft_lutpair2343" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns[240]_i_1 
       (.I0(D[198]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns148_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] [0]),
        .O(\rdData_reg[245] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2343" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns[241]_i_1 
       (.I0(D[206]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns148_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] [1]),
        .O(\rdData_reg[245] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2344" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns[242]_i_1 
       (.I0(D[214]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns148_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] [0]),
        .O(\rdData_reg[245] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2344" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns[243]_i_1 
       (.I0(D[222]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns148_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] [1]),
        .O(\rdData_reg[245] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2345" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns[244]_i_1 
       (.I0(D[230]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns148_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] [0]),
        .O(\rdData_reg[245] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2345" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns[245]_i_1 
       (.I0(D[238]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns148_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] [1]),
        .O(\rdData_reg[245] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns[245]_i_2 
       (.I0(calDone_reg),
        .I1(match6_143_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns148_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r[40][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [4]),
        .O(match4_143_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r[40][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [2]),
        .I5(Q[2]),
        .O(match6_143_return));
  (* SOFT_HLUTNM = "soft_lutpair2346" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns[246]_i_1 
       (.I0(D[246]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns147_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] [0]),
        .O(\rdData_reg[251] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2346" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns[247]_i_1 
       (.I0(D[254]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns147_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] [1]),
        .O(\rdData_reg[251] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2347" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns[248]_i_1 
       (.I0(D[199]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns147_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] [0]),
        .O(\rdData_reg[251] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2347" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns[249]_i_1 
       (.I0(D[207]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns147_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] [1]),
        .O(\rdData_reg[251] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2348" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns[250]_i_1 
       (.I0(D[215]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns147_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] [0]),
        .O(\rdData_reg[251] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2348" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns[251]_i_1 
       (.I0(D[223]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns147_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] [1]),
        .O(\rdData_reg[251] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns[251]_i_2 
       (.I0(calDone_reg),
        .I1(match6_144_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns147_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r[41][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [4]),
        .O(match4_144_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r[41][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [2]),
        .I5(Q[2]),
        .O(match6_144_return));
  (* SOFT_HLUTNM = "soft_lutpair2349" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns[252]_i_1 
       (.I0(D[231]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns146_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] [0]),
        .O(\rdData_reg[257] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2349" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns[253]_i_1 
       (.I0(D[239]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns146_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] [1]),
        .O(\rdData_reg[257] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2350" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns[254]_i_1 
       (.I0(D[247]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns146_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] [0]),
        .O(\rdData_reg[257] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2350" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns[255]_i_1 
       (.I0(D[255]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns146_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] [1]),
        .O(\rdData_reg[257] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2351" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns[256]_i_1 
       (.I0(D[256]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns146_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] [0]),
        .O(\rdData_reg[257] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2351" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns[257]_i_1 
       (.I0(D[264]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns146_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] [1]),
        .O(\rdData_reg[257] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns[257]_i_2 
       (.I0(calDone_reg),
        .I1(match6_145_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns146_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r[42][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [4]),
        .O(match4_145_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r[42][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [2]),
        .I5(Q[2]),
        .O(match6_145_return));
  (* SOFT_HLUTNM = "soft_lutpair2352" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns[258]_i_1 
       (.I0(D[272]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns145_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] [0]),
        .O(\rdData_reg[263] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2352" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns[259]_i_1 
       (.I0(D[280]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns145_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] [1]),
        .O(\rdData_reg[263] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2353" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns[260]_i_1 
       (.I0(D[288]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns145_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] [0]),
        .O(\rdData_reg[263] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2353" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns[261]_i_1 
       (.I0(D[296]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns145_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] [1]),
        .O(\rdData_reg[263] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2354" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns[262]_i_1 
       (.I0(D[304]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns145_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] [0]),
        .O(\rdData_reg[263] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2354" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns[263]_i_1 
       (.I0(D[312]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns145_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] [1]),
        .O(\rdData_reg[263] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns[263]_i_2 
       (.I0(calDone_reg),
        .I1(match6_146_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns145_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r[43][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [4]),
        .O(match4_146_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r[43][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [2]),
        .I5(Q[2]),
        .O(match6_146_return));
  (* SOFT_HLUTNM = "soft_lutpair2355" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns[264]_i_1 
       (.I0(D[257]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns144_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] [0]),
        .O(\rdData_reg[269] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2355" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns[265]_i_1 
       (.I0(D[265]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns144_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] [1]),
        .O(\rdData_reg[269] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2356" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns[266]_i_1 
       (.I0(D[273]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns144_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] [0]),
        .O(\rdData_reg[269] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2356" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns[267]_i_1 
       (.I0(D[281]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns144_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] [1]),
        .O(\rdData_reg[269] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2357" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns[268]_i_1 
       (.I0(D[289]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns144_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] [0]),
        .O(\rdData_reg[269] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2357" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns[269]_i_1 
       (.I0(D[297]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns144_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] [1]),
        .O(\rdData_reg[269] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns[269]_i_2 
       (.I0(calDone_reg),
        .I1(match6_147_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns144_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r[44][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [4]),
        .O(match4_147_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r[44][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [2]),
        .I5(Q[2]),
        .O(match6_147_return));
  (* SOFT_HLUTNM = "soft_lutpair2358" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns[270]_i_1 
       (.I0(D[305]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns143_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] [0]),
        .O(\rdData_reg[275] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2358" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns[271]_i_1 
       (.I0(D[313]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns143_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] [1]),
        .O(\rdData_reg[275] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2359" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns[272]_i_1 
       (.I0(D[258]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns143_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] [0]),
        .O(\rdData_reg[275] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2359" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns[273]_i_1 
       (.I0(D[266]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns143_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] [1]),
        .O(\rdData_reg[275] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2360" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns[274]_i_1 
       (.I0(D[274]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns143_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] [0]),
        .O(\rdData_reg[275] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2360" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns[275]_i_1 
       (.I0(D[282]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns143_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] [1]),
        .O(\rdData_reg[275] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns[275]_i_2 
       (.I0(calDone_reg),
        .I1(match6_148_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns143_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r[45][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [4]),
        .O(match4_148_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r[45][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [2]),
        .I5(Q[2]),
        .O(match6_148_return));
  (* SOFT_HLUTNM = "soft_lutpair2361" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns[276]_i_1 
       (.I0(D[290]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns142_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] [0]),
        .O(\rdData_reg[281] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2361" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns[277]_i_1 
       (.I0(D[298]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns142_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] [1]),
        .O(\rdData_reg[281] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2362" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns[278]_i_1 
       (.I0(D[306]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns142_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] [0]),
        .O(\rdData_reg[281] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2362" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns[279]_i_1 
       (.I0(D[314]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns142_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] [1]),
        .O(\rdData_reg[281] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2363" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns[280]_i_1 
       (.I0(D[259]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns142_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] [0]),
        .O(\rdData_reg[281] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2363" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns[281]_i_1 
       (.I0(D[267]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns142_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] [1]),
        .O(\rdData_reg[281] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns[281]_i_2 
       (.I0(calDone_reg),
        .I1(match6_149_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns142_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r[46][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [4]),
        .O(match4_149_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r[46][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [2]),
        .I5(Q[2]),
        .O(match6_149_return));
  (* SOFT_HLUTNM = "soft_lutpair2364" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns[282]_i_1 
       (.I0(D[275]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns141_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] [0]),
        .O(\rdData_reg[287] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2364" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns[283]_i_1 
       (.I0(D[283]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns141_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] [1]),
        .O(\rdData_reg[287] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2365" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns[284]_i_1 
       (.I0(D[291]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns141_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] [0]),
        .O(\rdData_reg[287] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2365" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns[285]_i_1 
       (.I0(D[299]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns141_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] [1]),
        .O(\rdData_reg[287] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2366" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns[286]_i_1 
       (.I0(D[307]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns141_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] [0]),
        .O(\rdData_reg[287] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2366" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns[287]_i_1 
       (.I0(D[315]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns141_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] [1]),
        .O(\rdData_reg[287] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns[287]_i_2 
       (.I0(calDone_reg),
        .I1(match6_150_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns141_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r[47][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [4]),
        .O(match4_150_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r[47][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [2]),
        .I5(Q[2]),
        .O(match6_150_return));
  (* SOFT_HLUTNM = "soft_lutpair2367" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns[288]_i_1 
       (.I0(D[260]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns140_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] [0]),
        .O(\rdData_reg[293] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2367" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns[289]_i_1 
       (.I0(D[268]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns140_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] [1]),
        .O(\rdData_reg[293] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2368" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns[290]_i_1 
       (.I0(D[276]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns140_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] [0]),
        .O(\rdData_reg[293] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2368" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns[291]_i_1 
       (.I0(D[284]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns140_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] [1]),
        .O(\rdData_reg[293] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2369" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns[292]_i_1 
       (.I0(D[292]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns140_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] [0]),
        .O(\rdData_reg[293] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2369" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns[293]_i_1 
       (.I0(D[300]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns140_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] [1]),
        .O(\rdData_reg[293] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns[293]_i_2 
       (.I0(calDone_reg),
        .I1(match6_151_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns140_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r[48][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [4]),
        .O(match4_151_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r[48][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [2]),
        .I5(Q[2]),
        .O(match6_151_return));
  (* SOFT_HLUTNM = "soft_lutpair2370" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns[294]_i_1 
       (.I0(D[308]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns139_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] [0]),
        .O(\rdData_reg[299] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2370" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns[295]_i_1 
       (.I0(D[316]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns139_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] [1]),
        .O(\rdData_reg[299] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2371" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns[296]_i_1 
       (.I0(D[261]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns139_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] [0]),
        .O(\rdData_reg[299] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2371" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns[297]_i_1 
       (.I0(D[269]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns139_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] [1]),
        .O(\rdData_reg[299] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2372" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns[298]_i_1 
       (.I0(D[277]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns139_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] [0]),
        .O(\rdData_reg[299] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2372" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns[299]_i_1 
       (.I0(D[285]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns139_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] [1]),
        .O(\rdData_reg[299] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns[299]_i_2 
       (.I0(calDone_reg),
        .I1(match6_152_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns139_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r[49][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [4]),
        .O(match4_152_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r[49][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [2]),
        .I5(Q[2]),
        .O(match6_152_return));
  (* SOFT_HLUTNM = "soft_lutpair2235" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns[24]_i_1 
       (.I0(D[3]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns184_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] [0]),
        .O(\rdData_reg[29] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2235" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns[25]_i_1 
       (.I0(D[11]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns184_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] [1]),
        .O(\rdData_reg[29] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2236" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns[26]_i_1 
       (.I0(D[19]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns184_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] [0]),
        .O(\rdData_reg[29] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2236" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns[27]_i_1 
       (.I0(D[27]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns184_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] [1]),
        .O(\rdData_reg[29] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2237" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns[28]_i_1 
       (.I0(D[35]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns184_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] [0]),
        .O(\rdData_reg[29] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2237" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns[29]_i_1 
       (.I0(D[43]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns184_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] [1]),
        .O(\rdData_reg[29] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns[29]_i_2 
       (.I0(calDone_reg),
        .I1(match6_17_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns184_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r[4][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [4]),
        .O(match4_17_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r[4][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [2]),
        .I5(Q[2]),
        .O(match6_17_return));
  (* SOFT_HLUTNM = "soft_lutpair2373" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns[300]_i_1 
       (.I0(D[293]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns138_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] [0]),
        .O(\rdData_reg[305] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2373" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns[301]_i_1 
       (.I0(D[301]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns138_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] [1]),
        .O(\rdData_reg[305] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2374" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns[302]_i_1 
       (.I0(D[309]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns138_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] [0]),
        .O(\rdData_reg[305] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2374" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns[303]_i_1 
       (.I0(D[317]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns138_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] [1]),
        .O(\rdData_reg[305] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2375" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns[304]_i_1 
       (.I0(D[262]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns138_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] [0]),
        .O(\rdData_reg[305] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2375" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns[305]_i_1 
       (.I0(D[270]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns138_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] [1]),
        .O(\rdData_reg[305] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns[305]_i_2 
       (.I0(calDone_reg),
        .I1(match6_153_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns138_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r[50][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [4]),
        .O(match4_153_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r[50][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [2]),
        .I5(Q[2]),
        .O(match6_153_return));
  (* SOFT_HLUTNM = "soft_lutpair2376" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns[306]_i_1 
       (.I0(D[278]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns137_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] [0]),
        .O(\rdData_reg[311] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2376" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns[307]_i_1 
       (.I0(D[286]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns137_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] [1]),
        .O(\rdData_reg[311] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2377" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns[308]_i_1 
       (.I0(D[294]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns137_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] [0]),
        .O(\rdData_reg[311] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2377" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns[309]_i_1 
       (.I0(D[302]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns137_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] [1]),
        .O(\rdData_reg[311] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2378" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns[310]_i_1 
       (.I0(D[310]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns137_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] [0]),
        .O(\rdData_reg[311] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2378" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns[311]_i_1 
       (.I0(D[318]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns137_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] [1]),
        .O(\rdData_reg[311] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns[311]_i_2 
       (.I0(calDone_reg),
        .I1(match6_154_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns137_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r[51][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [4]),
        .O(match4_154_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r[51][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [2]),
        .I5(Q[2]),
        .O(match6_154_return));
  (* SOFT_HLUTNM = "soft_lutpair2379" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns[312]_i_1 
       (.I0(D[263]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns136_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] [0]),
        .O(\rdData_reg[317] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2379" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns[313]_i_1 
       (.I0(D[271]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns136_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] [1]),
        .O(\rdData_reg[317] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2380" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns[314]_i_1 
       (.I0(D[279]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns136_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] [0]),
        .O(\rdData_reg[317] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2380" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns[315]_i_1 
       (.I0(D[287]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns136_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] [1]),
        .O(\rdData_reg[317] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2381" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns[316]_i_1 
       (.I0(D[295]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns136_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] [0]),
        .O(\rdData_reg[317] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2381" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns[317]_i_1 
       (.I0(D[303]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns136_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] [1]),
        .O(\rdData_reg[317] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns[317]_i_2 
       (.I0(calDone_reg),
        .I1(match6_155_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns136_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r[52][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [4]),
        .O(match4_155_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r[52][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [2]),
        .I5(Q[2]),
        .O(match6_155_return));
  (* SOFT_HLUTNM = "soft_lutpair2382" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns[318]_i_1 
       (.I0(D[311]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns135_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] [0]),
        .O(\rdData_reg[323] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2382" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns[319]_i_1 
       (.I0(D[319]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns135_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] [1]),
        .O(\rdData_reg[323] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2383" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns[320]_i_1 
       (.I0(D[320]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns135_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] [0]),
        .O(\rdData_reg[323] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2383" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns[321]_i_1 
       (.I0(D[328]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns135_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] [1]),
        .O(\rdData_reg[323] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2384" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns[322]_i_1 
       (.I0(D[336]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns135_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] [0]),
        .O(\rdData_reg[323] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2384" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns[323]_i_1 
       (.I0(D[344]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns135_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] [1]),
        .O(\rdData_reg[323] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns[323]_i_2 
       (.I0(calDone_reg),
        .I1(match6_156_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns135_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r[53][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [4]),
        .O(match4_156_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r[53][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [2]),
        .I5(Q[2]),
        .O(match6_156_return));
  (* SOFT_HLUTNM = "soft_lutpair2385" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns[324]_i_1 
       (.I0(D[352]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns134_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] [0]),
        .O(\rdData_reg[329] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2385" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns[325]_i_1 
       (.I0(D[360]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns134_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] [1]),
        .O(\rdData_reg[329] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2386" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns[326]_i_1 
       (.I0(D[368]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns134_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] [0]),
        .O(\rdData_reg[329] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2386" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns[327]_i_1 
       (.I0(D[376]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns134_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] [1]),
        .O(\rdData_reg[329] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2387" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns[328]_i_1 
       (.I0(D[321]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns134_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] [0]),
        .O(\rdData_reg[329] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2387" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns[329]_i_1 
       (.I0(D[329]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns134_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] [1]),
        .O(\rdData_reg[329] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns[329]_i_2 
       (.I0(calDone_reg),
        .I1(match6_157_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns134_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r[54][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [4]),
        .O(match4_157_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r[54][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [2]),
        .I5(Q[2]),
        .O(match6_157_return));
  (* SOFT_HLUTNM = "soft_lutpair2388" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns[330]_i_1 
       (.I0(D[337]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns133_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] [0]),
        .O(\rdData_reg[335] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2388" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns[331]_i_1 
       (.I0(D[345]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns133_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] [1]),
        .O(\rdData_reg[335] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2389" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns[332]_i_1 
       (.I0(D[353]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns133_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] [0]),
        .O(\rdData_reg[335] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2389" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns[333]_i_1 
       (.I0(D[361]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns133_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] [1]),
        .O(\rdData_reg[335] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2390" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns[334]_i_1 
       (.I0(D[369]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns133_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] [0]),
        .O(\rdData_reg[335] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2390" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns[335]_i_1 
       (.I0(D[377]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns133_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] [1]),
        .O(\rdData_reg[335] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns[335]_i_2 
       (.I0(calDone_reg),
        .I1(match6_158_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns133_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r[55][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [4]),
        .O(match4_158_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r[55][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [2]),
        .I5(Q[2]),
        .O(match6_158_return));
  (* SOFT_HLUTNM = "soft_lutpair2391" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns[336]_i_1 
       (.I0(D[322]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns132_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] [0]),
        .O(\rdData_reg[341] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2391" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns[337]_i_1 
       (.I0(D[330]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns132_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] [1]),
        .O(\rdData_reg[341] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2392" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns[338]_i_1 
       (.I0(D[338]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns132_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] [0]),
        .O(\rdData_reg[341] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2392" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns[339]_i_1 
       (.I0(D[346]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns132_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] [1]),
        .O(\rdData_reg[341] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2393" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns[340]_i_1 
       (.I0(D[354]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns132_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] [0]),
        .O(\rdData_reg[341] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2393" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns[341]_i_1 
       (.I0(D[362]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns132_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] [1]),
        .O(\rdData_reg[341] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns[341]_i_2 
       (.I0(calDone_reg),
        .I1(match6_159_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns132_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r[56][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [4]),
        .O(match4_159_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r[56][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [2]),
        .I5(Q[2]),
        .O(match6_159_return));
  (* SOFT_HLUTNM = "soft_lutpair2394" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns[342]_i_1 
       (.I0(D[370]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns131_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] [0]),
        .O(\rdData_reg[347] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2394" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns[343]_i_1 
       (.I0(D[378]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns131_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] [1]),
        .O(\rdData_reg[347] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2395" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns[344]_i_1 
       (.I0(D[323]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns131_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] [0]),
        .O(\rdData_reg[347] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2395" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns[345]_i_1 
       (.I0(D[331]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns131_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] [1]),
        .O(\rdData_reg[347] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2396" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns[346]_i_1 
       (.I0(D[339]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns131_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] [0]),
        .O(\rdData_reg[347] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2396" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns[347]_i_1 
       (.I0(D[347]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns131_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] [1]),
        .O(\rdData_reg[347] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns[347]_i_2 
       (.I0(calDone_reg),
        .I1(match6_160_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns131_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r[57][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [4]),
        .O(match4_160_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r[57][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [2]),
        .I5(Q[2]),
        .O(match6_160_return));
  (* SOFT_HLUTNM = "soft_lutpair2397" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns[348]_i_1 
       (.I0(D[355]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns130_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] [0]),
        .O(\rdData_reg[353] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2397" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns[349]_i_1 
       (.I0(D[363]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns130_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] [1]),
        .O(\rdData_reg[353] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2398" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns[350]_i_1 
       (.I0(D[371]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns130_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] [0]),
        .O(\rdData_reg[353] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2398" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns[351]_i_1 
       (.I0(D[379]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns130_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] [1]),
        .O(\rdData_reg[353] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2399" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns[352]_i_1 
       (.I0(D[324]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns130_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] [0]),
        .O(\rdData_reg[353] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2399" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns[353]_i_1 
       (.I0(D[332]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns130_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] [1]),
        .O(\rdData_reg[353] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns[353]_i_2 
       (.I0(calDone_reg),
        .I1(match6_161_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns130_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r[58][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [4]),
        .O(match4_161_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r[58][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [2]),
        .I5(Q[2]),
        .O(match6_161_return));
  (* SOFT_HLUTNM = "soft_lutpair2400" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns[354]_i_1 
       (.I0(D[340]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns129_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] [0]),
        .O(\rdData_reg[359] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2400" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns[355]_i_1 
       (.I0(D[348]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns129_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] [1]),
        .O(\rdData_reg[359] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2401" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns[356]_i_1 
       (.I0(D[356]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns129_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] [0]),
        .O(\rdData_reg[359] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2401" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns[357]_i_1 
       (.I0(D[364]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns129_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] [1]),
        .O(\rdData_reg[359] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2402" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns[358]_i_1 
       (.I0(D[372]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns129_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] [0]),
        .O(\rdData_reg[359] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2402" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns[359]_i_1 
       (.I0(D[380]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns129_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] [1]),
        .O(\rdData_reg[359] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns[359]_i_2 
       (.I0(calDone_reg),
        .I1(match6_162_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns129_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r[59][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [4]),
        .O(match4_162_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r[59][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [2]),
        .I5(Q[2]),
        .O(match6_162_return));
  (* SOFT_HLUTNM = "soft_lutpair2238" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns[30]_i_1 
       (.I0(D[51]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns183_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] [0]),
        .O(\rdData_reg[35] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2238" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns[31]_i_1 
       (.I0(D[59]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns183_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] [1]),
        .O(\rdData_reg[35] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2239" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns[32]_i_1 
       (.I0(D[4]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns183_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] [0]),
        .O(\rdData_reg[35] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2239" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns[33]_i_1 
       (.I0(D[12]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns183_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] [1]),
        .O(\rdData_reg[35] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2240" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns[34]_i_1 
       (.I0(D[20]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns183_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] [0]),
        .O(\rdData_reg[35] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2240" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns[35]_i_1 
       (.I0(D[28]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns183_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] [1]),
        .O(\rdData_reg[35] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns[35]_i_2 
       (.I0(calDone_reg),
        .I1(match6_18_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns183_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r[5][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [4]),
        .O(match4_18_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r[5][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [2]),
        .I5(Q[2]),
        .O(match6_18_return));
  (* SOFT_HLUTNM = "soft_lutpair2403" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns[360]_i_1 
       (.I0(D[325]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns128_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] [0]),
        .O(\rdData_reg[365] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2403" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns[361]_i_1 
       (.I0(D[333]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns128_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] [1]),
        .O(\rdData_reg[365] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2404" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns[362]_i_1 
       (.I0(D[341]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns128_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] [0]),
        .O(\rdData_reg[365] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2404" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns[363]_i_1 
       (.I0(D[349]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns128_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] [1]),
        .O(\rdData_reg[365] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2405" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns[364]_i_1 
       (.I0(D[357]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns128_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] [0]),
        .O(\rdData_reg[365] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2405" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns[365]_i_1 
       (.I0(D[365]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns128_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] [1]),
        .O(\rdData_reg[365] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns[365]_i_2 
       (.I0(calDone_reg),
        .I1(match6_163_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns128_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r[60][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [4]),
        .O(match4_163_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r[60][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [2]),
        .I5(Q[2]),
        .O(match6_163_return));
  (* SOFT_HLUTNM = "soft_lutpair2406" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns[366]_i_1 
       (.I0(D[373]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns127_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] [0]),
        .O(\rdData_reg[371] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2406" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns[367]_i_1 
       (.I0(D[381]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns127_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] [1]),
        .O(\rdData_reg[371] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2407" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns[368]_i_1 
       (.I0(D[326]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns127_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] [0]),
        .O(\rdData_reg[371] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2407" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns[369]_i_1 
       (.I0(D[334]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns127_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] [1]),
        .O(\rdData_reg[371] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2408" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns[370]_i_1 
       (.I0(D[342]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns127_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] [0]),
        .O(\rdData_reg[371] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2408" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns[371]_i_1 
       (.I0(D[350]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns127_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] [1]),
        .O(\rdData_reg[371] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns[371]_i_2 
       (.I0(calDone_reg),
        .I1(match6_164_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns127_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r[61][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [4]),
        .O(match4_164_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r[61][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [2]),
        .I5(Q[2]),
        .O(match6_164_return));
  (* SOFT_HLUTNM = "soft_lutpair2409" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns[372]_i_1 
       (.I0(D[358]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns126_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] [0]),
        .O(\rdData_reg[377] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2409" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns[373]_i_1 
       (.I0(D[366]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns126_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] [1]),
        .O(\rdData_reg[377] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2410" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns[374]_i_1 
       (.I0(D[374]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns126_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] [0]),
        .O(\rdData_reg[377] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2410" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns[375]_i_1 
       (.I0(D[382]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns126_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] [1]),
        .O(\rdData_reg[377] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2411" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns[376]_i_1 
       (.I0(D[327]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns126_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] [0]),
        .O(\rdData_reg[377] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2411" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns[377]_i_1 
       (.I0(D[335]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns126_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] [1]),
        .O(\rdData_reg[377] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns[377]_i_2 
       (.I0(calDone_reg),
        .I1(match6_165_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns126_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r[62][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [4]),
        .O(match4_165_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r[62][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [2]),
        .I5(Q[2]),
        .O(match6_165_return));
  (* SOFT_HLUTNM = "soft_lutpair2412" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns[378]_i_1 
       (.I0(D[343]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns125_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] [0]),
        .O(\rdData_reg[383] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2412" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns[379]_i_1 
       (.I0(D[351]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns125_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] [1]),
        .O(\rdData_reg[383] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2413" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns[380]_i_1 
       (.I0(D[359]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns125_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] [0]),
        .O(\rdData_reg[383] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2413" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns[381]_i_1 
       (.I0(D[367]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns125_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] [1]),
        .O(\rdData_reg[383] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2414" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns[382]_i_1 
       (.I0(D[375]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns125_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] [0]),
        .O(\rdData_reg[383] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2414" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns[383]_i_1 
       (.I0(D[383]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns125_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] [1]),
        .O(\rdData_reg[383] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns[383]_i_2 
       (.I0(calDone_reg),
        .I1(match6_166_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns125_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r[63][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [4]),
        .O(match4_166_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r[63][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [2]),
        .I5(Q[2]),
        .O(match6_166_return));
  (* SOFT_HLUTNM = "soft_lutpair2415" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns[384]_i_1 
       (.I0(D[384]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns124_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] [0]),
        .O(\rdData_reg[389] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2415" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns[385]_i_1 
       (.I0(D[392]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns124_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] [1]),
        .O(\rdData_reg[389] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2416" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns[386]_i_1 
       (.I0(D[400]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns124_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] [0]),
        .O(\rdData_reg[389] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2416" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns[387]_i_1 
       (.I0(D[408]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns124_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] [1]),
        .O(\rdData_reg[389] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2417" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns[388]_i_1 
       (.I0(D[416]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns124_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] [0]),
        .O(\rdData_reg[389] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2417" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns[389]_i_1 
       (.I0(D[424]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns124_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] [1]),
        .O(\rdData_reg[389] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns[389]_i_2 
       (.I0(calDone_reg),
        .I1(match6_167_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns124_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r[64][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [4]),
        .O(match4_167_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r[64][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [2]),
        .I5(Q[2]),
        .O(match6_167_return));
  (* SOFT_HLUTNM = "soft_lutpair2418" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns[390]_i_1 
       (.I0(D[432]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns123_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] [0]),
        .O(\rdData_reg[395] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2418" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns[391]_i_1 
       (.I0(D[440]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns123_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] [1]),
        .O(\rdData_reg[395] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2419" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns[392]_i_1 
       (.I0(D[385]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns123_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] [0]),
        .O(\rdData_reg[395] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2419" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns[393]_i_1 
       (.I0(D[393]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns123_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] [1]),
        .O(\rdData_reg[395] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2420" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns[394]_i_1 
       (.I0(D[401]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns123_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] [0]),
        .O(\rdData_reg[395] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2420" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns[395]_i_1 
       (.I0(D[409]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns123_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] [1]),
        .O(\rdData_reg[395] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns[395]_i_2 
       (.I0(calDone_reg),
        .I1(match6_168_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns123_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r[65][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [4]),
        .O(match4_168_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r[65][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [2]),
        .I5(Q[2]),
        .O(match6_168_return));
  (* SOFT_HLUTNM = "soft_lutpair2421" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns[396]_i_1 
       (.I0(D[417]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns122_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] [0]),
        .O(\rdData_reg[401] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2421" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns[397]_i_1 
       (.I0(D[425]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns122_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] [1]),
        .O(\rdData_reg[401] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2422" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns[398]_i_1 
       (.I0(D[433]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns122_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] [0]),
        .O(\rdData_reg[401] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2422" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns[399]_i_1 
       (.I0(D[441]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns122_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] [1]),
        .O(\rdData_reg[401] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2423" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns[400]_i_1 
       (.I0(D[386]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns122_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] [0]),
        .O(\rdData_reg[401] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2423" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns[401]_i_1 
       (.I0(D[394]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns122_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] [1]),
        .O(\rdData_reg[401] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns[401]_i_2 
       (.I0(calDone_reg),
        .I1(match6_169_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns122_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r[66][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [4]),
        .O(match4_169_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r[66][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [2]),
        .I5(Q[2]),
        .O(match6_169_return));
  (* SOFT_HLUTNM = "soft_lutpair2424" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns[402]_i_1 
       (.I0(D[402]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns121_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] [0]),
        .O(\rdData_reg[407] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2424" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns[403]_i_1 
       (.I0(D[410]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns121_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] [1]),
        .O(\rdData_reg[407] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2425" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns[404]_i_1 
       (.I0(D[418]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns121_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] [0]),
        .O(\rdData_reg[407] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2425" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns[405]_i_1 
       (.I0(D[426]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns121_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] [1]),
        .O(\rdData_reg[407] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2426" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns[406]_i_1 
       (.I0(D[434]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns121_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] [0]),
        .O(\rdData_reg[407] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2426" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns[407]_i_1 
       (.I0(D[442]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns121_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] [1]),
        .O(\rdData_reg[407] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns[407]_i_2 
       (.I0(calDone_reg),
        .I1(match6_170_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns121_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r[67][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [4]),
        .O(match4_170_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r[67][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [2]),
        .I5(Q[2]),
        .O(match6_170_return));
  (* SOFT_HLUTNM = "soft_lutpair2427" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns[408]_i_1 
       (.I0(D[387]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns120_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] [0]),
        .O(\rdData_reg[413] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2427" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns[409]_i_1 
       (.I0(D[395]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns120_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] [1]),
        .O(\rdData_reg[413] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2428" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns[410]_i_1 
       (.I0(D[403]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns120_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] [0]),
        .O(\rdData_reg[413] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2428" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns[411]_i_1 
       (.I0(D[411]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns120_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] [1]),
        .O(\rdData_reg[413] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2429" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns[412]_i_1 
       (.I0(D[419]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns120_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] [0]),
        .O(\rdData_reg[413] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2429" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns[413]_i_1 
       (.I0(D[427]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns120_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] [1]),
        .O(\rdData_reg[413] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns[413]_i_2 
       (.I0(calDone_reg),
        .I1(match6_171_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns120_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r[68][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [4]),
        .O(match4_171_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r[68][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [2]),
        .I5(Q[2]),
        .O(match6_171_return));
  (* SOFT_HLUTNM = "soft_lutpair2430" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns[414]_i_1 
       (.I0(D[435]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns119_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] [0]),
        .O(\rdData_reg[419] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2430" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns[415]_i_1 
       (.I0(D[443]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns119_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] [1]),
        .O(\rdData_reg[419] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2431" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns[416]_i_1 
       (.I0(D[388]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns119_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] [0]),
        .O(\rdData_reg[419] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2431" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns[417]_i_1 
       (.I0(D[396]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns119_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] [1]),
        .O(\rdData_reg[419] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2432" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns[418]_i_1 
       (.I0(D[404]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns119_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] [0]),
        .O(\rdData_reg[419] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2432" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns[419]_i_1 
       (.I0(D[412]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns119_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] [1]),
        .O(\rdData_reg[419] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns[419]_i_2 
       (.I0(calDone_reg),
        .I1(match6_172_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns119_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r[69][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [4]),
        .O(match4_172_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r[69][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [2]),
        .I5(Q[2]),
        .O(match6_172_return));
  (* SOFT_HLUTNM = "soft_lutpair2241" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns[36]_i_1 
       (.I0(D[36]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns182_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] [0]),
        .O(\rdData_reg[41] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2241" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns[37]_i_1 
       (.I0(D[44]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns182_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] [1]),
        .O(\rdData_reg[41] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2242" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns[38]_i_1 
       (.I0(D[52]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns182_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] [0]),
        .O(\rdData_reg[41] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2242" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns[39]_i_1 
       (.I0(D[60]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns182_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] [1]),
        .O(\rdData_reg[41] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2243" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns[40]_i_1 
       (.I0(D[5]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns182_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] [0]),
        .O(\rdData_reg[41] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2243" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns[41]_i_1 
       (.I0(D[13]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns182_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] [1]),
        .O(\rdData_reg[41] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns[41]_i_2 
       (.I0(calDone_reg),
        .I1(match6_19_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns182_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r[6][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [4]),
        .O(match4_19_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r[6][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [2]),
        .I5(Q[2]),
        .O(match6_19_return));
  (* SOFT_HLUTNM = "soft_lutpair2433" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns[420]_i_1 
       (.I0(D[420]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns118_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] [0]),
        .O(\rdData_reg[425] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2433" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns[421]_i_1 
       (.I0(D[428]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns118_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] [1]),
        .O(\rdData_reg[425] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2434" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns[422]_i_1 
       (.I0(D[436]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns118_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] [0]),
        .O(\rdData_reg[425] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2434" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns[423]_i_1 
       (.I0(D[444]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns118_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] [1]),
        .O(\rdData_reg[425] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2435" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns[424]_i_1 
       (.I0(D[389]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns118_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] [0]),
        .O(\rdData_reg[425] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2435" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns[425]_i_1 
       (.I0(D[397]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns118_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] [1]),
        .O(\rdData_reg[425] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns[425]_i_2 
       (.I0(calDone_reg),
        .I1(match6_173_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns118_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r[70][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [4]),
        .O(match4_173_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r[70][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [2]),
        .I5(Q[2]),
        .O(match6_173_return));
  (* SOFT_HLUTNM = "soft_lutpair2436" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns[426]_i_1 
       (.I0(D[405]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns117_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] [0]),
        .O(\rdData_reg[431] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2436" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns[427]_i_1 
       (.I0(D[413]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns117_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] [1]),
        .O(\rdData_reg[431] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2437" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns[428]_i_1 
       (.I0(D[421]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns117_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] [0]),
        .O(\rdData_reg[431] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2437" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns[429]_i_1 
       (.I0(D[429]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns117_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] [1]),
        .O(\rdData_reg[431] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2438" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns[430]_i_1 
       (.I0(D[437]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns117_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] [0]),
        .O(\rdData_reg[431] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2438" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns[431]_i_1 
       (.I0(D[445]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns117_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] [1]),
        .O(\rdData_reg[431] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns[431]_i_2 
       (.I0(calDone_reg),
        .I1(match6_174_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns117_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r[71][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [4]),
        .O(match4_174_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r[71][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [2]),
        .I5(Q[2]),
        .O(match6_174_return));
  (* SOFT_HLUTNM = "soft_lutpair2439" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns[432]_i_1 
       (.I0(D[390]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns116_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] [0]),
        .O(\rdData_reg[437] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2439" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns[433]_i_1 
       (.I0(D[398]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns116_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] [1]),
        .O(\rdData_reg[437] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2440" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns[434]_i_1 
       (.I0(D[406]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns116_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] [0]),
        .O(\rdData_reg[437] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2440" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns[435]_i_1 
       (.I0(D[414]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns116_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] [1]),
        .O(\rdData_reg[437] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2441" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns[436]_i_1 
       (.I0(D[422]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns116_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] [0]),
        .O(\rdData_reg[437] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2441" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns[437]_i_1 
       (.I0(D[430]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns116_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] [1]),
        .O(\rdData_reg[437] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns[437]_i_2 
       (.I0(calDone_reg),
        .I1(match6_175_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns116_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r[72][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [4]),
        .O(match4_175_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r[72][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [2]),
        .I5(Q[2]),
        .O(match6_175_return));
  (* SOFT_HLUTNM = "soft_lutpair2442" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns[438]_i_1 
       (.I0(D[438]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns115_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] [0]),
        .O(\rdData_reg[443] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2442" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns[439]_i_1 
       (.I0(D[446]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns115_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] [1]),
        .O(\rdData_reg[443] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2443" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns[440]_i_1 
       (.I0(D[391]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns115_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] [0]),
        .O(\rdData_reg[443] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2443" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns[441]_i_1 
       (.I0(D[399]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns115_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] [1]),
        .O(\rdData_reg[443] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2444" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns[442]_i_1 
       (.I0(D[407]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns115_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] [0]),
        .O(\rdData_reg[443] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2444" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns[443]_i_1 
       (.I0(D[415]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns115_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] [1]),
        .O(\rdData_reg[443] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns[443]_i_2 
       (.I0(calDone_reg),
        .I1(match6_176_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns115_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r[73][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [4]),
        .O(match4_176_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r[73][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [2]),
        .I5(Q[2]),
        .O(match6_176_return));
  (* SOFT_HLUTNM = "soft_lutpair2445" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns[444]_i_1 
       (.I0(D[423]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns114_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] [0]),
        .O(\rdData_reg[449] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2445" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns[445]_i_1 
       (.I0(D[431]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns114_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] [1]),
        .O(\rdData_reg[449] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2446" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns[446]_i_1 
       (.I0(D[439]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns114_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] [0]),
        .O(\rdData_reg[449] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2446" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns[447]_i_1 
       (.I0(D[447]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns114_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] [1]),
        .O(\rdData_reg[449] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2447" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns[448]_i_1 
       (.I0(D[448]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns114_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] [0]),
        .O(\rdData_reg[449] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2447" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns[449]_i_1 
       (.I0(D[456]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns114_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] [1]),
        .O(\rdData_reg[449] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns[449]_i_2 
       (.I0(calDone_reg),
        .I1(match6_177_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns114_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r[74][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [4]),
        .O(match4_177_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r[74][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [2]),
        .I5(Q[2]),
        .O(match6_177_return));
  (* SOFT_HLUTNM = "soft_lutpair2448" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns[450]_i_1 
       (.I0(D[464]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns113_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] [0]),
        .O(\rdData_reg[455] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2448" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns[451]_i_1 
       (.I0(D[472]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns113_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] [1]),
        .O(\rdData_reg[455] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2449" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns[452]_i_1 
       (.I0(D[480]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns113_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] [0]),
        .O(\rdData_reg[455] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2449" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns[453]_i_1 
       (.I0(D[488]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns113_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] [1]),
        .O(\rdData_reg[455] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2450" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns[454]_i_1 
       (.I0(D[496]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns113_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] [0]),
        .O(\rdData_reg[455] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2450" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns[455]_i_1 
       (.I0(D[504]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns113_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] [1]),
        .O(\rdData_reg[455] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns[455]_i_2 
       (.I0(calDone_reg),
        .I1(match6_178_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns113_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r[75][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [4]),
        .O(match4_178_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r[75][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [2]),
        .I5(Q[2]),
        .O(match6_178_return));
  (* SOFT_HLUTNM = "soft_lutpair2451" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns[456]_i_1 
       (.I0(D[449]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns112_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] [0]),
        .O(\rdData_reg[461] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2451" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns[457]_i_1 
       (.I0(D[457]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns112_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] [1]),
        .O(\rdData_reg[461] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2452" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns[458]_i_1 
       (.I0(D[465]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns112_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] [0]),
        .O(\rdData_reg[461] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2452" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns[459]_i_1 
       (.I0(D[473]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns112_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] [1]),
        .O(\rdData_reg[461] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2453" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns[460]_i_1 
       (.I0(D[481]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns112_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] [0]),
        .O(\rdData_reg[461] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2453" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns[461]_i_1 
       (.I0(D[489]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns112_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] [1]),
        .O(\rdData_reg[461] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns[461]_i_2 
       (.I0(calDone_reg),
        .I1(match6_179_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns112_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r[76][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [4]),
        .O(match4_179_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r[76][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [2]),
        .I5(Q[2]),
        .O(match6_179_return));
  (* SOFT_HLUTNM = "soft_lutpair2454" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns[462]_i_1 
       (.I0(D[497]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns111_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] [0]),
        .O(\rdData_reg[467] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2454" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns[463]_i_1 
       (.I0(D[505]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns111_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] [1]),
        .O(\rdData_reg[467] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2455" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns[464]_i_1 
       (.I0(D[450]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns111_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] [0]),
        .O(\rdData_reg[467] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2455" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns[465]_i_1 
       (.I0(D[458]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns111_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] [1]),
        .O(\rdData_reg[467] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2456" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns[466]_i_1 
       (.I0(D[466]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns111_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] [0]),
        .O(\rdData_reg[467] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2456" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns[467]_i_1 
       (.I0(D[474]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns111_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] [1]),
        .O(\rdData_reg[467] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns[467]_i_2 
       (.I0(calDone_reg),
        .I1(match6_180_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns111_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r[77][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [4]),
        .O(match4_180_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r[77][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [2]),
        .I5(Q[2]),
        .O(match6_180_return));
  (* SOFT_HLUTNM = "soft_lutpair2457" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns[468]_i_1 
       (.I0(D[482]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns110_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] [0]),
        .O(\rdData_reg[473] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2457" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns[469]_i_1 
       (.I0(D[490]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns110_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] [1]),
        .O(\rdData_reg[473] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2458" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns[470]_i_1 
       (.I0(D[498]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns110_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] [0]),
        .O(\rdData_reg[473] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2458" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns[471]_i_1 
       (.I0(D[506]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns110_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] [1]),
        .O(\rdData_reg[473] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2459" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns[472]_i_1 
       (.I0(D[451]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns110_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] [0]),
        .O(\rdData_reg[473] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2459" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns[473]_i_1 
       (.I0(D[459]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns110_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] [1]),
        .O(\rdData_reg[473] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns[473]_i_2 
       (.I0(calDone_reg),
        .I1(match6_181_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns110_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r[78][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [4]),
        .O(match4_181_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r[78][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [2]),
        .I5(Q[2]),
        .O(match6_181_return));
  (* SOFT_HLUTNM = "soft_lutpair2460" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns[474]_i_1 
       (.I0(D[467]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns19_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] [0]),
        .O(\rdData_reg[479] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2460" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns[475]_i_1 
       (.I0(D[475]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns19_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] [1]),
        .O(\rdData_reg[479] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2461" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns[476]_i_1 
       (.I0(D[483]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns19_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] [0]),
        .O(\rdData_reg[479] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2461" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns[477]_i_1 
       (.I0(D[491]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns19_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] [1]),
        .O(\rdData_reg[479] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2462" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns[478]_i_1 
       (.I0(D[499]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns19_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] [0]),
        .O(\rdData_reg[479] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2462" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns[479]_i_1 
       (.I0(D[507]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns19_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] [1]),
        .O(\rdData_reg[479] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns[479]_i_2 
       (.I0(calDone_reg),
        .I1(match6_182_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns19_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r[79][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [4]),
        .O(match4_182_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r[79][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [2]),
        .I5(Q[2]),
        .O(match6_182_return));
  (* SOFT_HLUTNM = "soft_lutpair2244" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns[42]_i_1 
       (.I0(D[21]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns181_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] [0]),
        .O(\rdData_reg[47] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2244" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns[43]_i_1 
       (.I0(D[29]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns181_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] [1]),
        .O(\rdData_reg[47] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2245" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns[44]_i_1 
       (.I0(D[37]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns181_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] [0]),
        .O(\rdData_reg[47] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2245" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns[45]_i_1 
       (.I0(D[45]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns181_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] [1]),
        .O(\rdData_reg[47] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2246" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns[46]_i_1 
       (.I0(D[53]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns181_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] [0]),
        .O(\rdData_reg[47] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2246" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns[47]_i_1 
       (.I0(D[61]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns181_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] [1]),
        .O(\rdData_reg[47] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns[47]_i_2 
       (.I0(calDone_reg),
        .I1(match6_110_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns181_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r[7][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [4]),
        .O(match4_110_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r[7][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [2]),
        .I5(Q[2]),
        .O(match6_110_return));
  (* SOFT_HLUTNM = "soft_lutpair2463" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns[480]_i_1 
       (.I0(D[452]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns18_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] [0]),
        .O(\rdData_reg[485] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2463" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns[481]_i_1 
       (.I0(D[460]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns18_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] [1]),
        .O(\rdData_reg[485] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2464" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns[482]_i_1 
       (.I0(D[468]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns18_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] [0]),
        .O(\rdData_reg[485] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2464" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns[483]_i_1 
       (.I0(D[476]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns18_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] [1]),
        .O(\rdData_reg[485] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2465" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns[484]_i_1 
       (.I0(D[484]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns18_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] [0]),
        .O(\rdData_reg[485] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2465" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns[485]_i_1 
       (.I0(D[492]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns18_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] [1]),
        .O(\rdData_reg[485] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns[485]_i_2 
       (.I0(calDone_reg),
        .I1(match6_183_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns18_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r[80][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [4]),
        .O(match4_183_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r[80][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [2]),
        .I5(Q[2]),
        .O(match6_183_return));
  (* SOFT_HLUTNM = "soft_lutpair2466" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns[486]_i_1 
       (.I0(D[500]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns17_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] [0]),
        .O(\rdData_reg[491] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2466" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns[487]_i_1 
       (.I0(D[508]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns17_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] [1]),
        .O(\rdData_reg[491] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2467" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns[488]_i_1 
       (.I0(D[453]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns17_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] [0]),
        .O(\rdData_reg[491] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2467" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns[489]_i_1 
       (.I0(D[461]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns17_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] [1]),
        .O(\rdData_reg[491] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2468" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns[490]_i_1 
       (.I0(D[469]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns17_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] [0]),
        .O(\rdData_reg[491] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2468" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns[491]_i_1 
       (.I0(D[477]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns17_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] [1]),
        .O(\rdData_reg[491] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns[491]_i_2 
       (.I0(calDone_reg),
        .I1(match6_184_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns17_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r[81][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [4]),
        .O(match4_184_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r[81][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [2]),
        .I5(Q[2]),
        .O(match6_184_return));
  (* SOFT_HLUTNM = "soft_lutpair2469" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns[492]_i_1 
       (.I0(D[485]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns16_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] [0]),
        .O(\rdData_reg[497] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2469" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns[493]_i_1 
       (.I0(D[493]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns16_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] [1]),
        .O(\rdData_reg[497] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2470" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns[494]_i_1 
       (.I0(D[501]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns16_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] [0]),
        .O(\rdData_reg[497] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2470" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns[495]_i_1 
       (.I0(D[509]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns16_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] [1]),
        .O(\rdData_reg[497] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2471" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns[496]_i_1 
       (.I0(D[454]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns16_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] [0]),
        .O(\rdData_reg[497] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2471" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns[497]_i_1 
       (.I0(D[462]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns16_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] [1]),
        .O(\rdData_reg[497] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns[497]_i_2 
       (.I0(calDone_reg),
        .I1(match6_185_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns16_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r[82][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [4]),
        .O(match4_185_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r[82][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [2]),
        .I5(Q[2]),
        .O(match6_185_return));
  (* SOFT_HLUTNM = "soft_lutpair2472" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns[498]_i_1 
       (.I0(D[470]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns15_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] [0]),
        .O(\rdData_reg[503] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2472" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns[499]_i_1 
       (.I0(D[478]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns15_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] [1]),
        .O(\rdData_reg[503] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2473" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns[500]_i_1 
       (.I0(D[486]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns15_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] [0]),
        .O(\rdData_reg[503] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2473" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns[501]_i_1 
       (.I0(D[494]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns15_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] [1]),
        .O(\rdData_reg[503] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2474" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns[502]_i_1 
       (.I0(D[502]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns15_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] [0]),
        .O(\rdData_reg[503] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2474" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns[503]_i_1 
       (.I0(D[510]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns15_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] [1]),
        .O(\rdData_reg[503] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns[503]_i_2 
       (.I0(calDone_reg),
        .I1(match6_186_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns15_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r[83][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [4]),
        .O(match4_186_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r[83][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [2]),
        .I5(Q[2]),
        .O(match6_186_return));
  (* SOFT_HLUTNM = "soft_lutpair2475" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns[504]_i_1 
       (.I0(D[455]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns14_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] [0]),
        .O(\rdData_reg[509] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2475" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns[505]_i_1 
       (.I0(D[463]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns14_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] [1]),
        .O(\rdData_reg[509] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2476" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns[506]_i_1 
       (.I0(D[471]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns14_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] [0]),
        .O(\rdData_reg[509] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2476" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns[507]_i_1 
       (.I0(D[479]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns14_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] [1]),
        .O(\rdData_reg[509] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2477" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns[508]_i_1 
       (.I0(D[487]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns14_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] [0]),
        .O(\rdData_reg[509] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2477" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns[509]_i_1 
       (.I0(D[495]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns14_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] [1]),
        .O(\rdData_reg[509] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns[509]_i_2 
       (.I0(calDone_reg),
        .I1(match6_187_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns14_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r[84][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [4]),
        .O(match4_187_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r[84][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [2]),
        .I5(Q[2]),
        .O(match6_187_return));
  (* SOFT_HLUTNM = "soft_lutpair2478" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns[510]_i_1 
       (.I0(D[503]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns1 ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] [0]),
        .O(\rdData_reg[511] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2478" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns[511]_i_1 
       (.I0(D[511]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns1 ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] [1]),
        .O(\rdData_reg[511] [1]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns[511]_i_2 
       (.I0(calDone_reg),
        .I1(match6_188_return),
        .I2(\rdDataAddr_reg[3]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__0_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns1 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r[85][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 [4]),
        .O(match4_188_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r[85][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 [2]),
        .I5(Q[2]),
        .O(match6_188_return));
  (* SOFT_HLUTNM = "soft_lutpair2247" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns[48]_i_1 
       (.I0(D[6]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns180_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] [0]),
        .O(\rdData_reg[53] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2247" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns[49]_i_1 
       (.I0(D[14]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns180_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] [1]),
        .O(\rdData_reg[53] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2248" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns[50]_i_1 
       (.I0(D[22]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns180_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] [0]),
        .O(\rdData_reg[53] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2248" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns[51]_i_1 
       (.I0(D[30]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns180_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] [1]),
        .O(\rdData_reg[53] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2249" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns[52]_i_1 
       (.I0(D[38]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns180_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] [0]),
        .O(\rdData_reg[53] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2249" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns[53]_i_1 
       (.I0(D[46]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns180_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] [1]),
        .O(\rdData_reg[53] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns[53]_i_2 
       (.I0(calDone_reg),
        .I1(match6_111_return),
        .I2(\rdDataAddr_reg[3]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep__1_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns180_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r[8][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [4]),
        .O(match4_111_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r[8][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [2]),
        .I5(Q[2]),
        .O(match6_111_return));
  (* SOFT_HLUTNM = "soft_lutpair2250" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns[54]_i_1 
       (.I0(D[54]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns179_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] [0]),
        .O(\rdData_reg[59] [0]));
  (* SOFT_HLUTNM = "soft_lutpair2250" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns[55]_i_1 
       (.I0(D[62]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns179_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] [1]),
        .O(\rdData_reg[59] [1]));
  (* SOFT_HLUTNM = "soft_lutpair2251" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns[56]_i_1 
       (.I0(D[7]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns179_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] [0]),
        .O(\rdData_reg[59] [2]));
  (* SOFT_HLUTNM = "soft_lutpair2251" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns[57]_i_1 
       (.I0(D[15]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns179_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] [1]),
        .O(\rdData_reg[59] [3]));
  (* SOFT_HLUTNM = "soft_lutpair2252" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns[58]_i_1 
       (.I0(D[23]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns179_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] [0]),
        .O(\rdData_reg[59] [4]));
  (* SOFT_HLUTNM = "soft_lutpair2252" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns[59]_i_1 
       (.I0(D[31]),
        .I1(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns179_out ),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] [1]),
        .O(\rdData_reg[59] [5]));
  LUT6 #(
    .INIT(64'h8008000000008008)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns[59]_i_2 
       (.I0(calDone_reg),
        .I1(match6_112_return),
        .I2(\rdDataAddr_reg[3]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [3]),
        .I4(\rdDataAddr_reg[4]_rep_0 ),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [4]),
        .O(\u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.app_rd_data_ns179_out ));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r[9][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [4]),
        .O(match4_112_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r[9][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [2]),
        .I5(Q[2]),
        .O(match6_112_return));
  LUT4 #(
    .INIT(16'h0008)) 
    \not_strict_mode.status_ram_0.rd_buf_we_r1_i_1 
       (.I0(rdCAS_reg_0),
        .I1(read_data_en_reg_0),
        .I2(rdRmw),
        .I3(rdInj),
        .O(calDone_reg));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r[0][5]_i_3 
       (.I0(Q[3]),
        .I1(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] [3]),
        .I2(Q[4]),
        .I3(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] [4]),
        .O(match4_1_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r[0][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] [1]),
        .I2(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] [2]),
        .I5(Q[2]),
        .O(match6_1_return));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r[1][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep_0 ),
        .I1(\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] [3]),
        .I2(\rdDataAddr_reg[4]_rep_0 ),
        .I3(\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] [4]),
        .O(match4_10_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r[1][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] [1]),
        .I2(\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] [2]),
        .I5(Q[2]),
        .O(match6_10_return));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r[2][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__0_0 ),
        .I1(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] [3]),
        .I2(\rdDataAddr_reg[4]_rep__0_0 ),
        .I3(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] [4]),
        .O(match4_11_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r[2][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] [1]),
        .I2(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] [2]),
        .I5(Q[2]),
        .O(match6_11_return));
  LUT4 #(
    .INIT(16'h9009)) 
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r[3][5]_i_3 
       (.I0(\rdDataAddr_reg[3]_rep__1_0 ),
        .I1(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] [3]),
        .I2(\rdDataAddr_reg[4]_rep__1_0 ),
        .I3(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] [4]),
        .O(match4_12_return));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r[3][5]_i_4 
       (.I0(Q[1]),
        .I1(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] [1]),
        .I2(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] [0]),
        .I3(Q[0]),
        .I4(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] [2]),
        .I5(Q[2]),
        .O(match6_12_return));
  FDRE pop_read_lat_fifo_reg
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(pop_read_lat_fifo),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hBA)) 
    rdCAS_nxt
       (.I0(mcRdCAS),
        .I1(rdCAS_reg_0),
        .I2(calRdCAS),
        .O(rdCAS_nxt__0));
  FDRE rdCAS_reg
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(rdCAS_nxt__0),
        .Q(read_lat_shift_nxt),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[0]_i_1 
       (.I0(\rdDataAddr_reg[0]_i_2_n_0 ),
        .I1(\rdDataAddr_reg[0]_i_3_n_0 ),
        .I2(read_lat_rptr_reg[4]),
        .I3(\rdDataAddr_reg[0]_i_4_n_0 ),
        .I4(read_lat_rptr_reg[3]),
        .I5(\rdDataAddr_reg[0]_i_5_n_0 ),
        .O(read_lat_fifo[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[0]_i_10 
       (.I0(\read_lat_fifo_reg[11]_42 [0]),
        .I1(\read_lat_fifo_reg[10]_43 [0]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[9]_44 [0]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[8]_45 [0]),
        .O(\rdDataAddr[0]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[0]_i_11 
       (.I0(\read_lat_fifo_reg[15]_38 [0]),
        .I1(\read_lat_fifo_reg[14]_39 [0]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[13]_40 [0]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[12]_41 [0]),
        .O(\rdDataAddr[0]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[0]_i_12 
       (.I0(\read_lat_fifo_reg[3]_50 [0]),
        .I1(\read_lat_fifo_reg[2]_51 [0]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[1]_52 [0]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[0]_53 [0]),
        .O(\rdDataAddr[0]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[0]_i_13 
       (.I0(\read_lat_fifo_reg[7]_46 [0]),
        .I1(\read_lat_fifo_reg[6]_47 [0]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[5]_48 [0]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[4]_49 [0]),
        .O(\rdDataAddr[0]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[0]_i_6 
       (.I0(\read_lat_fifo_reg[27]_26 [0]),
        .I1(\read_lat_fifo_reg[26]_27 [0]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[25]_28 [0]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[24]_29 [0]),
        .O(\rdDataAddr[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[0]_i_7 
       (.I0(\read_lat_fifo_reg[31]_22 [0]),
        .I1(\read_lat_fifo_reg[30]_23 [0]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[29]_24 [0]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[28]_25 [0]),
        .O(\rdDataAddr[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[0]_i_8 
       (.I0(\read_lat_fifo_reg[19]_34 [0]),
        .I1(\read_lat_fifo_reg[18]_35 [0]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[17]_36 [0]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[16]_37 [0]),
        .O(\rdDataAddr[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[0]_i_9 
       (.I0(\read_lat_fifo_reg[23]_30 [0]),
        .I1(\read_lat_fifo_reg[22]_31 [0]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[21]_32 [0]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[20]_33 [0]),
        .O(\rdDataAddr[0]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[1]_i_1 
       (.I0(\rdDataAddr_reg[1]_i_2_n_0 ),
        .I1(\rdDataAddr_reg[1]_i_3_n_0 ),
        .I2(read_lat_rptr_reg[4]),
        .I3(\rdDataAddr_reg[1]_i_4_n_0 ),
        .I4(read_lat_rptr_reg[3]),
        .I5(\rdDataAddr_reg[1]_i_5_n_0 ),
        .O(read_lat_fifo[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[1]_i_10 
       (.I0(\read_lat_fifo_reg[11]_42 [1]),
        .I1(\read_lat_fifo_reg[10]_43 [1]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[9]_44 [1]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[8]_45 [1]),
        .O(\rdDataAddr[1]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[1]_i_11 
       (.I0(\read_lat_fifo_reg[15]_38 [1]),
        .I1(\read_lat_fifo_reg[14]_39 [1]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[13]_40 [1]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[12]_41 [1]),
        .O(\rdDataAddr[1]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[1]_i_12 
       (.I0(\read_lat_fifo_reg[3]_50 [1]),
        .I1(\read_lat_fifo_reg[2]_51 [1]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[1]_52 [1]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[0]_53 [1]),
        .O(\rdDataAddr[1]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[1]_i_13 
       (.I0(\read_lat_fifo_reg[7]_46 [1]),
        .I1(\read_lat_fifo_reg[6]_47 [1]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[5]_48 [1]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[4]_49 [1]),
        .O(\rdDataAddr[1]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[1]_i_6 
       (.I0(\read_lat_fifo_reg[27]_26 [1]),
        .I1(\read_lat_fifo_reg[26]_27 [1]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[25]_28 [1]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[24]_29 [1]),
        .O(\rdDataAddr[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[1]_i_7 
       (.I0(\read_lat_fifo_reg[31]_22 [1]),
        .I1(\read_lat_fifo_reg[30]_23 [1]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[29]_24 [1]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[28]_25 [1]),
        .O(\rdDataAddr[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[1]_i_8 
       (.I0(\read_lat_fifo_reg[19]_34 [1]),
        .I1(\read_lat_fifo_reg[18]_35 [1]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[17]_36 [1]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[16]_37 [1]),
        .O(\rdDataAddr[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[1]_i_9 
       (.I0(\read_lat_fifo_reg[23]_30 [1]),
        .I1(\read_lat_fifo_reg[22]_31 [1]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[21]_32 [1]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[20]_33 [1]),
        .O(\rdDataAddr[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[2]_i_1 
       (.I0(\rdDataAddr_reg[2]_i_2_n_0 ),
        .I1(\rdDataAddr_reg[2]_i_3_n_0 ),
        .I2(read_lat_rptr_reg[4]),
        .I3(\rdDataAddr_reg[2]_i_4_n_0 ),
        .I4(read_lat_rptr_reg[3]),
        .I5(\rdDataAddr_reg[2]_i_5_n_0 ),
        .O(read_lat_fifo[2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[2]_i_10 
       (.I0(\read_lat_fifo_reg[11]_42 [2]),
        .I1(\read_lat_fifo_reg[10]_43 [2]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[9]_44 [2]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[8]_45 [2]),
        .O(\rdDataAddr[2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[2]_i_11 
       (.I0(\read_lat_fifo_reg[15]_38 [2]),
        .I1(\read_lat_fifo_reg[14]_39 [2]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[13]_40 [2]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[12]_41 [2]),
        .O(\rdDataAddr[2]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[2]_i_12 
       (.I0(\read_lat_fifo_reg[3]_50 [2]),
        .I1(\read_lat_fifo_reg[2]_51 [2]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[1]_52 [2]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[0]_53 [2]),
        .O(\rdDataAddr[2]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[2]_i_13 
       (.I0(\read_lat_fifo_reg[7]_46 [2]),
        .I1(\read_lat_fifo_reg[6]_47 [2]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[5]_48 [2]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[4]_49 [2]),
        .O(\rdDataAddr[2]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[2]_i_6 
       (.I0(\read_lat_fifo_reg[27]_26 [2]),
        .I1(\read_lat_fifo_reg[26]_27 [2]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[25]_28 [2]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[24]_29 [2]),
        .O(\rdDataAddr[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[2]_i_7 
       (.I0(\read_lat_fifo_reg[31]_22 [2]),
        .I1(\read_lat_fifo_reg[30]_23 [2]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[29]_24 [2]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[28]_25 [2]),
        .O(\rdDataAddr[2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[2]_i_8 
       (.I0(\read_lat_fifo_reg[19]_34 [2]),
        .I1(\read_lat_fifo_reg[18]_35 [2]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[17]_36 [2]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[16]_37 [2]),
        .O(\rdDataAddr[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[2]_i_9 
       (.I0(\read_lat_fifo_reg[23]_30 [2]),
        .I1(\read_lat_fifo_reg[22]_31 [2]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[21]_32 [2]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[20]_33 [2]),
        .O(\rdDataAddr[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[3]_i_1 
       (.I0(\rdDataAddr_reg[3]_i_2_n_0 ),
        .I1(\rdDataAddr_reg[3]_i_3_n_0 ),
        .I2(read_lat_rptr_reg[4]),
        .I3(\rdDataAddr_reg[3]_i_4_n_0 ),
        .I4(read_lat_rptr_reg[3]),
        .I5(\rdDataAddr_reg[3]_i_5_n_0 ),
        .O(read_lat_fifo[3]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[3]_i_10 
       (.I0(\read_lat_fifo_reg[11]_42 [3]),
        .I1(\read_lat_fifo_reg[10]_43 [3]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[9]_44 [3]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[8]_45 [3]),
        .O(\rdDataAddr[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[3]_i_11 
       (.I0(\read_lat_fifo_reg[15]_38 [3]),
        .I1(\read_lat_fifo_reg[14]_39 [3]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[13]_40 [3]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[12]_41 [3]),
        .O(\rdDataAddr[3]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[3]_i_12 
       (.I0(\read_lat_fifo_reg[3]_50 [3]),
        .I1(\read_lat_fifo_reg[2]_51 [3]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[1]_52 [3]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[0]_53 [3]),
        .O(\rdDataAddr[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[3]_i_13 
       (.I0(\read_lat_fifo_reg[7]_46 [3]),
        .I1(\read_lat_fifo_reg[6]_47 [3]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[5]_48 [3]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[4]_49 [3]),
        .O(\rdDataAddr[3]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[3]_i_6 
       (.I0(\read_lat_fifo_reg[27]_26 [3]),
        .I1(\read_lat_fifo_reg[26]_27 [3]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[25]_28 [3]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[24]_29 [3]),
        .O(\rdDataAddr[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[3]_i_7 
       (.I0(\read_lat_fifo_reg[31]_22 [3]),
        .I1(\read_lat_fifo_reg[30]_23 [3]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[29]_24 [3]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[28]_25 [3]),
        .O(\rdDataAddr[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[3]_i_8 
       (.I0(\read_lat_fifo_reg[19]_34 [3]),
        .I1(\read_lat_fifo_reg[18]_35 [3]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[17]_36 [3]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[16]_37 [3]),
        .O(\rdDataAddr[3]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[3]_i_9 
       (.I0(\read_lat_fifo_reg[23]_30 [3]),
        .I1(\read_lat_fifo_reg[22]_31 [3]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[21]_32 [3]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[20]_33 [3]),
        .O(\rdDataAddr[3]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[3]_rep_i_1 
       (.I0(\rdDataAddr_reg[3]_i_2_n_0 ),
        .I1(\rdDataAddr_reg[3]_i_3_n_0 ),
        .I2(read_lat_rptr_reg[4]),
        .I3(\rdDataAddr_reg[3]_i_4_n_0 ),
        .I4(read_lat_rptr_reg[3]),
        .I5(\rdDataAddr_reg[3]_i_5_n_0 ),
        .O(\rdDataAddr[3]_rep_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[3]_rep_i_1__0 
       (.I0(\rdDataAddr_reg[3]_i_2_n_0 ),
        .I1(\rdDataAddr_reg[3]_i_3_n_0 ),
        .I2(read_lat_rptr_reg[4]),
        .I3(\rdDataAddr_reg[3]_i_4_n_0 ),
        .I4(read_lat_rptr_reg[3]),
        .I5(\rdDataAddr_reg[3]_i_5_n_0 ),
        .O(\rdDataAddr[3]_rep_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[3]_rep_i_1__1 
       (.I0(\rdDataAddr_reg[3]_i_2_n_0 ),
        .I1(\rdDataAddr_reg[3]_i_3_n_0 ),
        .I2(read_lat_rptr_reg[4]),
        .I3(\rdDataAddr_reg[3]_i_4_n_0 ),
        .I4(read_lat_rptr_reg[3]),
        .I5(\rdDataAddr_reg[3]_i_5_n_0 ),
        .O(\rdDataAddr[3]_rep_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[4]_i_1 
       (.I0(\rdDataAddr_reg[4]_i_2_n_0 ),
        .I1(\rdDataAddr_reg[4]_i_3_n_0 ),
        .I2(read_lat_rptr_reg[4]),
        .I3(\rdDataAddr_reg[4]_i_4_n_0 ),
        .I4(read_lat_rptr_reg[3]),
        .I5(\rdDataAddr_reg[4]_i_5_n_0 ),
        .O(read_lat_fifo[4]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[4]_i_10 
       (.I0(\read_lat_fifo_reg[11]_42 [4]),
        .I1(\read_lat_fifo_reg[10]_43 [4]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[9]_44 [4]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[8]_45 [4]),
        .O(\rdDataAddr[4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[4]_i_11 
       (.I0(\read_lat_fifo_reg[15]_38 [4]),
        .I1(\read_lat_fifo_reg[14]_39 [4]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[13]_40 [4]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[12]_41 [4]),
        .O(\rdDataAddr[4]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[4]_i_12 
       (.I0(\read_lat_fifo_reg[3]_50 [4]),
        .I1(\read_lat_fifo_reg[2]_51 [4]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[1]_52 [4]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[0]_53 [4]),
        .O(\rdDataAddr[4]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[4]_i_13 
       (.I0(\read_lat_fifo_reg[7]_46 [4]),
        .I1(\read_lat_fifo_reg[6]_47 [4]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[5]_48 [4]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[4]_49 [4]),
        .O(\rdDataAddr[4]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[4]_i_6 
       (.I0(\read_lat_fifo_reg[27]_26 [4]),
        .I1(\read_lat_fifo_reg[26]_27 [4]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[25]_28 [4]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[24]_29 [4]),
        .O(\rdDataAddr[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[4]_i_7 
       (.I0(\read_lat_fifo_reg[31]_22 [4]),
        .I1(\read_lat_fifo_reg[30]_23 [4]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[29]_24 [4]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[28]_25 [4]),
        .O(\rdDataAddr[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[4]_i_8 
       (.I0(\read_lat_fifo_reg[19]_34 [4]),
        .I1(\read_lat_fifo_reg[18]_35 [4]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[17]_36 [4]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[16]_37 [4]),
        .O(\rdDataAddr[4]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[4]_i_9 
       (.I0(\read_lat_fifo_reg[23]_30 [4]),
        .I1(\read_lat_fifo_reg[22]_31 [4]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[21]_32 [4]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[20]_33 [4]),
        .O(\rdDataAddr[4]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[4]_rep_i_1 
       (.I0(\rdDataAddr_reg[4]_i_2_n_0 ),
        .I1(\rdDataAddr_reg[4]_i_3_n_0 ),
        .I2(read_lat_rptr_reg[4]),
        .I3(\rdDataAddr_reg[4]_i_4_n_0 ),
        .I4(read_lat_rptr_reg[3]),
        .I5(\rdDataAddr_reg[4]_i_5_n_0 ),
        .O(\rdDataAddr[4]_rep_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[4]_rep_i_1__0 
       (.I0(\rdDataAddr_reg[4]_i_2_n_0 ),
        .I1(\rdDataAddr_reg[4]_i_3_n_0 ),
        .I2(read_lat_rptr_reg[4]),
        .I3(\rdDataAddr_reg[4]_i_4_n_0 ),
        .I4(read_lat_rptr_reg[3]),
        .I5(\rdDataAddr_reg[4]_i_5_n_0 ),
        .O(\rdDataAddr[4]_rep_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rdDataAddr[4]_rep_i_1__1 
       (.I0(\rdDataAddr_reg[4]_i_2_n_0 ),
        .I1(\rdDataAddr_reg[4]_i_3_n_0 ),
        .I2(read_lat_rptr_reg[4]),
        .I3(\rdDataAddr_reg[4]_i_4_n_0 ),
        .I4(read_lat_rptr_reg[3]),
        .I5(\rdDataAddr_reg[4]_i_5_n_0 ),
        .O(\rdDataAddr[4]_rep_i_1__1_n_0 ));
  FDRE \rdDataAddr_reg[0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(read_lat_fifo[0]),
        .Q(Q[0]),
        .R(1'b0));
  MUXF7 \rdDataAddr_reg[0]_i_2 
       (.I0(\rdDataAddr[0]_i_6_n_0 ),
        .I1(\rdDataAddr[0]_i_7_n_0 ),
        .O(\rdDataAddr_reg[0]_i_2_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[0]_i_3 
       (.I0(\rdDataAddr[0]_i_8_n_0 ),
        .I1(\rdDataAddr[0]_i_9_n_0 ),
        .O(\rdDataAddr_reg[0]_i_3_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[0]_i_4 
       (.I0(\rdDataAddr[0]_i_10_n_0 ),
        .I1(\rdDataAddr[0]_i_11_n_0 ),
        .O(\rdDataAddr_reg[0]_i_4_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[0]_i_5 
       (.I0(\rdDataAddr[0]_i_12_n_0 ),
        .I1(\rdDataAddr[0]_i_13_n_0 ),
        .O(\rdDataAddr_reg[0]_i_5_n_0 ),
        .S(read_lat_rptr_reg[2]));
  FDRE \rdDataAddr_reg[1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(read_lat_fifo[1]),
        .Q(Q[1]),
        .R(1'b0));
  MUXF7 \rdDataAddr_reg[1]_i_2 
       (.I0(\rdDataAddr[1]_i_6_n_0 ),
        .I1(\rdDataAddr[1]_i_7_n_0 ),
        .O(\rdDataAddr_reg[1]_i_2_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[1]_i_3 
       (.I0(\rdDataAddr[1]_i_8_n_0 ),
        .I1(\rdDataAddr[1]_i_9_n_0 ),
        .O(\rdDataAddr_reg[1]_i_3_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[1]_i_4 
       (.I0(\rdDataAddr[1]_i_10_n_0 ),
        .I1(\rdDataAddr[1]_i_11_n_0 ),
        .O(\rdDataAddr_reg[1]_i_4_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[1]_i_5 
       (.I0(\rdDataAddr[1]_i_12_n_0 ),
        .I1(\rdDataAddr[1]_i_13_n_0 ),
        .O(\rdDataAddr_reg[1]_i_5_n_0 ),
        .S(read_lat_rptr_reg[2]));
  FDRE \rdDataAddr_reg[2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(read_lat_fifo[2]),
        .Q(Q[2]),
        .R(1'b0));
  MUXF7 \rdDataAddr_reg[2]_i_2 
       (.I0(\rdDataAddr[2]_i_6_n_0 ),
        .I1(\rdDataAddr[2]_i_7_n_0 ),
        .O(\rdDataAddr_reg[2]_i_2_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[2]_i_3 
       (.I0(\rdDataAddr[2]_i_8_n_0 ),
        .I1(\rdDataAddr[2]_i_9_n_0 ),
        .O(\rdDataAddr_reg[2]_i_3_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[2]_i_4 
       (.I0(\rdDataAddr[2]_i_10_n_0 ),
        .I1(\rdDataAddr[2]_i_11_n_0 ),
        .O(\rdDataAddr_reg[2]_i_4_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[2]_i_5 
       (.I0(\rdDataAddr[2]_i_12_n_0 ),
        .I1(\rdDataAddr[2]_i_13_n_0 ),
        .O(\rdDataAddr_reg[2]_i_5_n_0 ),
        .S(read_lat_rptr_reg[2]));
  (* ORIG_CELL_NAME = "rdDataAddr_reg[3]" *) 
  FDRE \rdDataAddr_reg[3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(read_lat_fifo[3]),
        .Q(Q[3]),
        .R(1'b0));
  MUXF7 \rdDataAddr_reg[3]_i_2 
       (.I0(\rdDataAddr[3]_i_6_n_0 ),
        .I1(\rdDataAddr[3]_i_7_n_0 ),
        .O(\rdDataAddr_reg[3]_i_2_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[3]_i_3 
       (.I0(\rdDataAddr[3]_i_8_n_0 ),
        .I1(\rdDataAddr[3]_i_9_n_0 ),
        .O(\rdDataAddr_reg[3]_i_3_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[3]_i_4 
       (.I0(\rdDataAddr[3]_i_10_n_0 ),
        .I1(\rdDataAddr[3]_i_11_n_0 ),
        .O(\rdDataAddr_reg[3]_i_4_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[3]_i_5 
       (.I0(\rdDataAddr[3]_i_12_n_0 ),
        .I1(\rdDataAddr[3]_i_13_n_0 ),
        .O(\rdDataAddr_reg[3]_i_5_n_0 ),
        .S(read_lat_rptr_reg[2]));
  (* ORIG_CELL_NAME = "rdDataAddr_reg[3]" *) 
  FDRE \rdDataAddr_reg[3]_rep 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\rdDataAddr[3]_rep_i_1_n_0 ),
        .Q(\rdDataAddr_reg[3]_rep_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "rdDataAddr_reg[3]" *) 
  FDRE \rdDataAddr_reg[3]_rep__0 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\rdDataAddr[3]_rep_i_1__0_n_0 ),
        .Q(\rdDataAddr_reg[3]_rep__0_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "rdDataAddr_reg[3]" *) 
  FDRE \rdDataAddr_reg[3]_rep__1 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\rdDataAddr[3]_rep_i_1__1_n_0 ),
        .Q(\rdDataAddr_reg[3]_rep__1_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "rdDataAddr_reg[4]" *) 
  FDRE \rdDataAddr_reg[4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(read_lat_fifo[4]),
        .Q(Q[4]),
        .R(1'b0));
  MUXF7 \rdDataAddr_reg[4]_i_2 
       (.I0(\rdDataAddr[4]_i_6_n_0 ),
        .I1(\rdDataAddr[4]_i_7_n_0 ),
        .O(\rdDataAddr_reg[4]_i_2_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[4]_i_3 
       (.I0(\rdDataAddr[4]_i_8_n_0 ),
        .I1(\rdDataAddr[4]_i_9_n_0 ),
        .O(\rdDataAddr_reg[4]_i_3_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[4]_i_4 
       (.I0(\rdDataAddr[4]_i_10_n_0 ),
        .I1(\rdDataAddr[4]_i_11_n_0 ),
        .O(\rdDataAddr_reg[4]_i_4_n_0 ),
        .S(read_lat_rptr_reg[2]));
  MUXF7 \rdDataAddr_reg[4]_i_5 
       (.I0(\rdDataAddr[4]_i_12_n_0 ),
        .I1(\rdDataAddr[4]_i_13_n_0 ),
        .O(\rdDataAddr_reg[4]_i_5_n_0 ),
        .S(read_lat_rptr_reg[2]));
  (* ORIG_CELL_NAME = "rdDataAddr_reg[4]" *) 
  FDRE \rdDataAddr_reg[4]_rep 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\rdDataAddr[4]_rep_i_1_n_0 ),
        .Q(\rdDataAddr_reg[4]_rep_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "rdDataAddr_reg[4]" *) 
  FDRE \rdDataAddr_reg[4]_rep__0 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\rdDataAddr[4]_rep_i_1__0_n_0 ),
        .Q(\rdDataAddr_reg[4]_rep__0_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "rdDataAddr_reg[4]" *) 
  FDRE \rdDataAddr_reg[4]_rep__1 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\rdDataAddr[4]_rep_i_1__1_n_0 ),
        .Q(\rdDataAddr_reg[4]_rep__1_0 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdInj_i_1
       (.I0(rdInj_reg_i_2_n_0),
        .I1(rdInj_reg_i_3_n_0),
        .I2(read_lat_rptr_reg[4]),
        .I3(rdInj_reg_i_4_n_0),
        .I4(read_lat_rptr_reg[3]),
        .I5(rdInj_reg_i_5_n_0),
        .O(rdInj_nxt));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdInj_i_10
       (.I0(\read_lat_fifo_reg[11]_42 [6]),
        .I1(\read_lat_fifo_reg[10]_43 [6]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[9]_44 [6]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[8]_45 [6]),
        .O(rdInj_i_10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdInj_i_11
       (.I0(\read_lat_fifo_reg[15]_38 [6]),
        .I1(\read_lat_fifo_reg[14]_39 [6]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[13]_40 [6]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[12]_41 [6]),
        .O(rdInj_i_11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdInj_i_12
       (.I0(\read_lat_fifo_reg[3]_50 [6]),
        .I1(\read_lat_fifo_reg[2]_51 [6]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[1]_52 [6]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[0]_53 [6]),
        .O(rdInj_i_12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdInj_i_13
       (.I0(\read_lat_fifo_reg[7]_46 [6]),
        .I1(\read_lat_fifo_reg[6]_47 [6]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[5]_48 [6]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[4]_49 [6]),
        .O(rdInj_i_13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdInj_i_6
       (.I0(\read_lat_fifo_reg[27]_26 [6]),
        .I1(\read_lat_fifo_reg[26]_27 [6]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[25]_28 [6]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[24]_29 [6]),
        .O(rdInj_i_6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdInj_i_7
       (.I0(\read_lat_fifo_reg[31]_22 [6]),
        .I1(\read_lat_fifo_reg[30]_23 [6]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[29]_24 [6]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[28]_25 [6]),
        .O(rdInj_i_7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdInj_i_8
       (.I0(\read_lat_fifo_reg[19]_34 [6]),
        .I1(\read_lat_fifo_reg[18]_35 [6]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[17]_36 [6]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[16]_37 [6]),
        .O(rdInj_i_8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdInj_i_9
       (.I0(\read_lat_fifo_reg[23]_30 [6]),
        .I1(\read_lat_fifo_reg[22]_31 [6]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[21]_32 [6]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[20]_33 [6]),
        .O(rdInj_i_9_n_0));
  FDRE rdInj_reg
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(rdInj_nxt),
        .Q(rdInj),
        .R(1'b0));
  MUXF7 rdInj_reg_i_2
       (.I0(rdInj_i_6_n_0),
        .I1(rdInj_i_7_n_0),
        .O(rdInj_reg_i_2_n_0),
        .S(read_lat_rptr_reg[2]));
  MUXF7 rdInj_reg_i_3
       (.I0(rdInj_i_8_n_0),
        .I1(rdInj_i_9_n_0),
        .O(rdInj_reg_i_3_n_0),
        .S(read_lat_rptr_reg[2]));
  MUXF7 rdInj_reg_i_4
       (.I0(rdInj_i_10_n_0),
        .I1(rdInj_i_11_n_0),
        .O(rdInj_reg_i_4_n_0),
        .S(read_lat_rptr_reg[2]));
  MUXF7 rdInj_reg_i_5
       (.I0(rdInj_i_12_n_0),
        .I1(rdInj_i_13_n_0),
        .O(rdInj_reg_i_5_n_0),
        .S(read_lat_rptr_reg[2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdRmw_i_1
       (.I0(rdRmw_reg_i_2_n_0),
        .I1(rdRmw_reg_i_3_n_0),
        .I2(read_lat_rptr_reg[4]),
        .I3(rdRmw_reg_i_4_n_0),
        .I4(read_lat_rptr_reg[3]),
        .I5(rdRmw_reg_i_5_n_0),
        .O(rdRmw_nxt));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdRmw_i_10
       (.I0(\read_lat_fifo_reg[11]_42 [5]),
        .I1(\read_lat_fifo_reg[10]_43 [5]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[9]_44 [5]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[8]_45 [5]),
        .O(rdRmw_i_10_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdRmw_i_11
       (.I0(\read_lat_fifo_reg[15]_38 [5]),
        .I1(\read_lat_fifo_reg[14]_39 [5]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[13]_40 [5]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[12]_41 [5]),
        .O(rdRmw_i_11_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdRmw_i_12
       (.I0(\read_lat_fifo_reg[3]_50 [5]),
        .I1(\read_lat_fifo_reg[2]_51 [5]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[1]_52 [5]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[0]_53 [5]),
        .O(rdRmw_i_12_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdRmw_i_13
       (.I0(\read_lat_fifo_reg[7]_46 [5]),
        .I1(\read_lat_fifo_reg[6]_47 [5]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[5]_48 [5]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[4]_49 [5]),
        .O(rdRmw_i_13_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdRmw_i_6
       (.I0(\read_lat_fifo_reg[27]_26 [5]),
        .I1(\read_lat_fifo_reg[26]_27 [5]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[25]_28 [5]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[24]_29 [5]),
        .O(rdRmw_i_6_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdRmw_i_7
       (.I0(\read_lat_fifo_reg[31]_22 [5]),
        .I1(\read_lat_fifo_reg[30]_23 [5]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[29]_24 [5]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[28]_25 [5]),
        .O(rdRmw_i_7_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdRmw_i_8
       (.I0(\read_lat_fifo_reg[19]_34 [5]),
        .I1(\read_lat_fifo_reg[18]_35 [5]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[17]_36 [5]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[16]_37 [5]),
        .O(rdRmw_i_8_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    rdRmw_i_9
       (.I0(\read_lat_fifo_reg[23]_30 [5]),
        .I1(\read_lat_fifo_reg[22]_31 [5]),
        .I2(read_lat_rptr_reg[1]),
        .I3(\read_lat_fifo_reg[21]_32 [5]),
        .I4(read_lat_rptr_reg[0]),
        .I5(\read_lat_fifo_reg[20]_33 [5]),
        .O(rdRmw_i_9_n_0));
  FDRE rdRmw_reg
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(rdRmw_nxt),
        .Q(rdRmw),
        .R(1'b0));
  MUXF7 rdRmw_reg_i_2
       (.I0(rdRmw_i_6_n_0),
        .I1(rdRmw_i_7_n_0),
        .O(rdRmw_reg_i_2_n_0),
        .S(read_lat_rptr_reg[2]));
  MUXF7 rdRmw_reg_i_3
       (.I0(rdRmw_i_8_n_0),
        .I1(rdRmw_i_9_n_0),
        .O(rdRmw_reg_i_3_n_0),
        .S(read_lat_rptr_reg[2]));
  MUXF7 rdRmw_reg_i_4
       (.I0(rdRmw_i_10_n_0),
        .I1(rdRmw_i_11_n_0),
        .O(rdRmw_reg_i_4_n_0),
        .S(read_lat_rptr_reg[2]));
  MUXF7 rdRmw_reg_i_5
       (.I0(rdRmw_i_12_n_0),
        .I1(rdRmw_i_13_n_0),
        .O(rdRmw_reg_i_5_n_0),
        .S(read_lat_rptr_reg[2]));
  FDRE read_data_en_reg
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(pop_read_lat_fifo),
        .Q(read_data_en_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00000001)) 
    \read_lat_fifo[0][6]_i_1 
       (.I0(read_lat_wptr_reg[3]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[4]),
        .I4(read_lat_wptr_reg[2]),
        .O(\read_lat_fifo[0][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \read_lat_fifo[10][6]_i_1 
       (.I0(read_lat_wptr_reg[1]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[3]),
        .I3(read_lat_wptr_reg[0]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[10][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00400000)) 
    \read_lat_fifo[11][6]_i_1 
       (.I0(read_lat_wptr_reg[2]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[4]),
        .I4(read_lat_wptr_reg[3]),
        .O(\read_lat_fifo[11][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \read_lat_fifo[12][6]_i_1 
       (.I0(read_lat_wptr_reg[2]),
        .I1(read_lat_wptr_reg[0]),
        .I2(read_lat_wptr_reg[3]),
        .I3(read_lat_wptr_reg[1]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[12][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00400000)) 
    \read_lat_fifo[13][6]_i_1 
       (.I0(read_lat_wptr_reg[1]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[4]),
        .I4(read_lat_wptr_reg[3]),
        .O(\read_lat_fifo[13][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00400000)) 
    \read_lat_fifo[14][6]_i_1 
       (.I0(read_lat_wptr_reg[0]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[2]),
        .I3(read_lat_wptr_reg[4]),
        .I4(read_lat_wptr_reg[3]),
        .O(\read_lat_fifo[14][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h40000000)) 
    \read_lat_fifo[15][6]_i_1 
       (.I0(read_lat_wptr_reg[4]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[2]),
        .O(\read_lat_fifo[15][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \read_lat_fifo[16][6]_i_1 
       (.I0(read_lat_wptr_reg[4]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[1]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[0]),
        .O(\read_lat_fifo[16][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \read_lat_fifo[17][6]_i_1 
       (.I0(read_lat_wptr_reg[0]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[4]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[1]),
        .O(\read_lat_fifo[17][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \read_lat_fifo[18][6]_i_1 
       (.I0(read_lat_wptr_reg[1]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[4]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[0]),
        .O(\read_lat_fifo[18][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00400000)) 
    \read_lat_fifo[19][6]_i_1 
       (.I0(read_lat_wptr_reg[3]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[2]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[19][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \read_lat_fifo[1][6]_i_1 
       (.I0(read_lat_wptr_reg[0]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[1]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[1][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \read_lat_fifo[20][6]_i_1 
       (.I0(read_lat_wptr_reg[2]),
        .I1(read_lat_wptr_reg[0]),
        .I2(read_lat_wptr_reg[4]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[1]),
        .O(\read_lat_fifo[20][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00400000)) 
    \read_lat_fifo[21][6]_i_1 
       (.I0(read_lat_wptr_reg[3]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[1]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[21][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00400000)) 
    \read_lat_fifo[22][6]_i_1 
       (.I0(read_lat_wptr_reg[3]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[2]),
        .I3(read_lat_wptr_reg[0]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[22][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h40000000)) 
    \read_lat_fifo[23][6]_i_1 
       (.I0(read_lat_wptr_reg[3]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[4]),
        .I4(read_lat_wptr_reg[2]),
        .O(\read_lat_fifo[23][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \read_lat_fifo[24][6]_i_1 
       (.I0(read_lat_wptr_reg[4]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[3]),
        .I3(read_lat_wptr_reg[1]),
        .I4(read_lat_wptr_reg[0]),
        .O(\read_lat_fifo[24][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00400000)) 
    \read_lat_fifo[25][6]_i_1 
       (.I0(read_lat_wptr_reg[2]),
        .I1(read_lat_wptr_reg[4]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[1]),
        .I4(read_lat_wptr_reg[3]),
        .O(\read_lat_fifo[25][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00400000)) 
    \read_lat_fifo[26][6]_i_1 
       (.I0(read_lat_wptr_reg[2]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[4]),
        .I3(read_lat_wptr_reg[0]),
        .I4(read_lat_wptr_reg[3]),
        .O(\read_lat_fifo[26][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h40000000)) 
    \read_lat_fifo[27][6]_i_1 
       (.I0(read_lat_wptr_reg[2]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[27][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00400000)) 
    \read_lat_fifo[28][6]_i_1 
       (.I0(read_lat_wptr_reg[1]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[4]),
        .I3(read_lat_wptr_reg[0]),
        .I4(read_lat_wptr_reg[3]),
        .O(\read_lat_fifo[28][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h40000000)) 
    \read_lat_fifo[29][6]_i_1 
       (.I0(read_lat_wptr_reg[1]),
        .I1(read_lat_wptr_reg[4]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[2]),
        .O(\read_lat_fifo[29][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \read_lat_fifo[2][6]_i_1 
       (.I0(read_lat_wptr_reg[1]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[2][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h40000000)) 
    \read_lat_fifo[30][6]_i_1 
       (.I0(read_lat_wptr_reg[0]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[4]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[2]),
        .O(\read_lat_fifo[30][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    \read_lat_fifo[31][6]_i_1 
       (.I0(read_lat_wptr_reg[3]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[4]),
        .I4(read_lat_wptr_reg[2]),
        .O(\read_lat_fifo[31][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \read_lat_fifo[3][6]_i_1 
       (.I0(read_lat_wptr_reg[0]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[1]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[3][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \read_lat_fifo[4][6]_i_1 
       (.I0(read_lat_wptr_reg[2]),
        .I1(read_lat_wptr_reg[0]),
        .I2(read_lat_wptr_reg[1]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[4][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \read_lat_fifo[5][6]_i_1 
       (.I0(read_lat_wptr_reg[0]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[2]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[5][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \read_lat_fifo[6][6]_i_1 
       (.I0(read_lat_wptr_reg[1]),
        .I1(read_lat_wptr_reg[0]),
        .I2(read_lat_wptr_reg[2]),
        .I3(read_lat_wptr_reg[3]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[6][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00400000)) 
    \read_lat_fifo[7][6]_i_1 
       (.I0(read_lat_wptr_reg[3]),
        .I1(read_lat_wptr_reg[1]),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[4]),
        .I4(read_lat_wptr_reg[2]),
        .O(\read_lat_fifo[7][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \read_lat_fifo[8][6]_i_1 
       (.I0(read_lat_wptr_reg[3]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[1]),
        .I3(read_lat_wptr_reg[0]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[8][6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \read_lat_fifo[9][6]_i_1 
       (.I0(read_lat_wptr_reg[0]),
        .I1(read_lat_wptr_reg[2]),
        .I2(read_lat_wptr_reg[3]),
        .I3(read_lat_wptr_reg[1]),
        .I4(read_lat_wptr_reg[4]),
        .O(\read_lat_fifo[9][6]_i_1_n_0 ));
  FDRE \read_lat_fifo_in_reg[0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_fifo_in_reg[6]_0 [0]),
        .Q(read_lat_fifo_in[0]),
        .R(1'b0));
  FDRE \read_lat_fifo_in_reg[1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_fifo_in_reg[6]_0 [1]),
        .Q(read_lat_fifo_in[1]),
        .R(1'b0));
  FDRE \read_lat_fifo_in_reg[2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_fifo_in_reg[6]_0 [2]),
        .Q(read_lat_fifo_in[2]),
        .R(1'b0));
  FDRE \read_lat_fifo_in_reg[3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_fifo_in_reg[6]_0 [3]),
        .Q(read_lat_fifo_in[3]),
        .R(1'b0));
  FDRE \read_lat_fifo_in_reg[4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_fifo_in_reg[6]_0 [4]),
        .Q(read_lat_fifo_in[4]),
        .R(1'b0));
  FDRE \read_lat_fifo_in_reg[5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_fifo_in_reg[6]_0 [5]),
        .Q(read_lat_fifo_in[5]),
        .R(1'b0));
  FDRE \read_lat_fifo_in_reg[6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_fifo_in_reg[6]_0 [6]),
        .Q(read_lat_fifo_in[6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[0][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[0][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[0]_53 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[0][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[0][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[0]_53 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[0][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[0][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[0]_53 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[0][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[0][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[0]_53 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[0][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[0][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[0]_53 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[0][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[0][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[0]_53 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[0][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[0][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[0]_53 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[10][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[10][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[10]_43 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[10][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[10][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[10]_43 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[10][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[10][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[10]_43 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[10][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[10][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[10]_43 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[10][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[10][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[10]_43 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[10][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[10][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[10]_43 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[10][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[10][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[10]_43 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[11][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[11][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[11]_42 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[11][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[11][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[11]_42 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[11][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[11][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[11]_42 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[11][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[11][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[11]_42 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[11][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[11][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[11]_42 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[11][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[11][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[11]_42 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[11][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[11][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[11]_42 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[12][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[12][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[12]_41 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[12][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[12][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[12]_41 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[12][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[12][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[12]_41 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[12][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[12][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[12]_41 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[12][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[12][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[12]_41 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[12][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[12][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[12]_41 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[12][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[12][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[12]_41 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[13][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[13][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[13]_40 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[13][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[13][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[13]_40 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[13][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[13][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[13]_40 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[13][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[13][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[13]_40 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[13][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[13][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[13]_40 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[13][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[13][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[13]_40 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[13][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[13][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[13]_40 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[14][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[14][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[14]_39 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[14][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[14][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[14]_39 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[14][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[14][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[14]_39 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[14][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[14][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[14]_39 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[14][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[14][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[14]_39 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[14][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[14][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[14]_39 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[14][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[14][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[14]_39 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[15][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[15][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[15]_38 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[15][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[15][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[15]_38 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[15][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[15][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[15]_38 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[15][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[15][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[15]_38 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[15][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[15][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[15]_38 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[15][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[15][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[15]_38 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[15][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[15][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[15]_38 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[16][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[16][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[16]_37 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[16][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[16][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[16]_37 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[16][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[16][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[16]_37 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[16][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[16][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[16]_37 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[16][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[16][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[16]_37 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[16][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[16][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[16]_37 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[16][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[16][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[16]_37 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[17][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[17][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[17]_36 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[17][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[17][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[17]_36 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[17][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[17][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[17]_36 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[17][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[17][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[17]_36 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[17][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[17][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[17]_36 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[17][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[17][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[17]_36 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[17][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[17][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[17]_36 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[18][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[18][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[18]_35 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[18][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[18][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[18]_35 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[18][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[18][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[18]_35 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[18][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[18][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[18]_35 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[18][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[18][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[18]_35 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[18][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[18][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[18]_35 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[18][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[18][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[18]_35 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[19][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[19][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[19]_34 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[19][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[19][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[19]_34 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[19][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[19][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[19]_34 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[19][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[19][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[19]_34 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[19][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[19][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[19]_34 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[19][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[19][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[19]_34 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[19][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[19][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[19]_34 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[1][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[1][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[1]_52 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[1][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[1][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[1]_52 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[1][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[1][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[1]_52 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[1][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[1][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[1]_52 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[1][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[1][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[1]_52 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[1][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[1][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[1]_52 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[1][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[1][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[1]_52 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[20][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[20][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[20]_33 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[20][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[20][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[20]_33 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[20][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[20][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[20]_33 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[20][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[20][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[20]_33 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[20][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[20][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[20]_33 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[20][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[20][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[20]_33 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[20][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[20][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[20]_33 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[21][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[21][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[21]_32 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[21][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[21][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[21]_32 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[21][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[21][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[21]_32 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[21][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[21][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[21]_32 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[21][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[21][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[21]_32 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[21][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[21][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[21]_32 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[21][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[21][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[21]_32 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[22][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[22][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[22]_31 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[22][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[22][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[22]_31 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[22][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[22][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[22]_31 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[22][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[22][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[22]_31 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[22][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[22][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[22]_31 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[22][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[22][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[22]_31 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[22][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[22][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[22]_31 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[23][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[23][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[23]_30 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[23][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[23][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[23]_30 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[23][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[23][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[23]_30 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[23][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[23][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[23]_30 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[23][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[23][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[23]_30 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[23][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[23][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[23]_30 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[23][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[23][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[23]_30 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[24][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[24][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[24]_29 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[24][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[24][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[24]_29 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[24][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[24][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[24]_29 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[24][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[24][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[24]_29 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[24][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[24][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[24]_29 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[24][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[24][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[24]_29 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[24][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[24][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[24]_29 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[25][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[25][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[25]_28 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[25][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[25][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[25]_28 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[25][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[25][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[25]_28 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[25][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[25][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[25]_28 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[25][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[25][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[25]_28 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[25][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[25][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[25]_28 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[25][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[25][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[25]_28 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[26][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[26][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[26]_27 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[26][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[26][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[26]_27 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[26][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[26][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[26]_27 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[26][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[26][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[26]_27 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[26][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[26][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[26]_27 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[26][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[26][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[26]_27 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[26][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[26][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[26]_27 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[27][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[27][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[27]_26 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[27][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[27][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[27]_26 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[27][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[27][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[27]_26 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[27][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[27][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[27]_26 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[27][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[27][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[27]_26 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[27][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[27][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[27]_26 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[27][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[27][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[27]_26 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[28][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[28][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[28]_25 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[28][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[28][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[28]_25 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[28][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[28][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[28]_25 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[28][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[28][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[28]_25 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[28][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[28][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[28]_25 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[28][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[28][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[28]_25 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[28][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[28][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[28]_25 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[29][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[29][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[29]_24 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[29][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[29][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[29]_24 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[29][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[29][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[29]_24 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[29][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[29][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[29]_24 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[29][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[29][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[29]_24 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[29][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[29][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[29]_24 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[29][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[29][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[29]_24 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[2][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[2][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[2]_51 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[2][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[2][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[2]_51 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[2][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[2][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[2]_51 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[2][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[2][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[2]_51 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[2][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[2][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[2]_51 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[2][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[2][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[2]_51 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[2][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[2][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[2]_51 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[30][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[30][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[30]_23 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[30][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[30][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[30]_23 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[30][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[30][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[30]_23 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[30][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[30][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[30]_23 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[30][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[30][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[30]_23 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[30][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[30][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[30]_23 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[30][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[30][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[30]_23 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[31][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[31][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[31]_22 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[31][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[31][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[31]_22 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[31][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[31][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[31]_22 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[31][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[31][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[31]_22 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[31][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[31][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[31]_22 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[31][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[31][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[31]_22 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[31][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[31][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[31]_22 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[3][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[3][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[3]_50 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[3][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[3][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[3]_50 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[3][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[3][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[3]_50 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[3][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[3][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[3]_50 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[3][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[3][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[3]_50 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[3][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[3][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[3]_50 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[3][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[3][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[3]_50 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[4][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[4][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[4]_49 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[4][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[4][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[4]_49 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[4][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[4][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[4]_49 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[4][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[4][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[4]_49 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[4][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[4][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[4]_49 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[4][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[4][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[4]_49 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[4][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[4][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[4]_49 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[5][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[5][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[5]_48 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[5][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[5][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[5]_48 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[5][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[5][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[5]_48 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[5][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[5][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[5]_48 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[5][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[5][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[5]_48 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[5][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[5][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[5]_48 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[5][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[5][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[5]_48 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[6][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[6][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[6]_47 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[6][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[6][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[6]_47 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[6][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[6][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[6]_47 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[6][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[6][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[6]_47 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[6][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[6][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[6]_47 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[6][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[6][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[6]_47 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[6][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[6][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[6]_47 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[7][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[7][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[7]_46 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[7][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[7][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[7]_46 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[7][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[7][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[7]_46 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[7][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[7][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[7]_46 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[7][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[7][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[7]_46 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[7][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[7][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[7]_46 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[7][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[7][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[7]_46 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[8][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[8][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[8]_45 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[8][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[8][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[8]_45 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[8][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[8][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[8]_45 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[8][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[8][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[8]_45 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[8][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[8][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[8]_45 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[8][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[8][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[8]_45 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[8][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[8][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[8]_45 [6]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[9][0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[9][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[0]),
        .Q(\read_lat_fifo_reg[9]_44 [0]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[9][1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[9][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[1]),
        .Q(\read_lat_fifo_reg[9]_44 [1]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[9][2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[9][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[2]),
        .Q(\read_lat_fifo_reg[9]_44 [2]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[9][3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[9][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[3]),
        .Q(\read_lat_fifo_reg[9]_44 [3]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[9][4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[9][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[4]),
        .Q(\read_lat_fifo_reg[9]_44 [4]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[9][5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[9][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[5]),
        .Q(\read_lat_fifo_reg[9]_44 [5]),
        .R(1'b0));
  FDRE \read_lat_fifo_reg[9][6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(\read_lat_fifo[9][6]_i_1_n_0 ),
        .D(read_lat_fifo_in[6]),
        .Q(\read_lat_fifo_reg[9]_44 [6]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2479" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \read_lat_rptr[0]_i_1 
       (.I0(read_lat_rptr_reg[0]),
        .I1(pop_read_lat_fifo),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair2479" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \read_lat_rptr[1]_i_1 
       (.I0(read_lat_rptr_reg[0]),
        .I1(pop_read_lat_fifo),
        .I2(read_lat_rptr_reg[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair2221" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \read_lat_rptr[2]_i_1 
       (.I0(pop_read_lat_fifo),
        .I1(read_lat_rptr_reg[0]),
        .I2(read_lat_rptr_reg[1]),
        .I3(read_lat_rptr_reg[2]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair2221" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \read_lat_rptr[3]_i_1 
       (.I0(read_lat_rptr_reg[1]),
        .I1(read_lat_rptr_reg[0]),
        .I2(pop_read_lat_fifo),
        .I3(read_lat_rptr_reg[2]),
        .I4(read_lat_rptr_reg[3]),
        .O(p_0_in__0[3]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \read_lat_rptr[4]_i_1 
       (.I0(read_lat_rptr_reg[2]),
        .I1(pop_read_lat_fifo),
        .I2(read_lat_rptr_reg[0]),
        .I3(read_lat_rptr_reg[1]),
        .I4(read_lat_rptr_reg[3]),
        .I5(read_lat_rptr_reg[4]),
        .O(p_0_in__0[4]));
  FDRE \read_lat_rptr_reg[0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(read_lat_rptr_reg[0]),
        .R(read_lat_wptr));
  FDRE \read_lat_rptr_reg[1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(read_lat_rptr_reg[1]),
        .R(read_lat_wptr));
  FDRE \read_lat_rptr_reg[2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(read_lat_rptr_reg[2]),
        .R(read_lat_wptr));
  FDRE \read_lat_rptr_reg[3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(read_lat_rptr_reg[3]),
        .R(read_lat_wptr));
  FDRE \read_lat_rptr_reg[4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(p_0_in__0[4]),
        .Q(read_lat_rptr_reg[4]),
        .R(read_lat_wptr));
  FDRE \read_lat_shift_reg[0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(read_lat_shift_nxt),
        .Q(\read_lat_shift_reg[31]_0 [0]),
        .R(out));
  FDRE \read_lat_shift_reg[10] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [9]),
        .Q(\read_lat_shift_reg[31]_0 [10]),
        .R(out));
  FDRE \read_lat_shift_reg[11] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [10]),
        .Q(\read_lat_shift_reg[31]_0 [11]),
        .R(out));
  FDRE \read_lat_shift_reg[12] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [11]),
        .Q(\read_lat_shift_reg[31]_0 [12]),
        .R(out));
  FDRE \read_lat_shift_reg[13] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [12]),
        .Q(\read_lat_shift_reg[31]_0 [13]),
        .R(out));
  FDRE \read_lat_shift_reg[14] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [13]),
        .Q(\read_lat_shift_reg[31]_0 [14]),
        .R(out));
  FDRE \read_lat_shift_reg[15] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [14]),
        .Q(\read_lat_shift_reg[31]_0 [15]),
        .R(out));
  FDRE \read_lat_shift_reg[16] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [15]),
        .Q(\read_lat_shift_reg[31]_0 [16]),
        .R(out));
  FDRE \read_lat_shift_reg[17] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [16]),
        .Q(\read_lat_shift_reg[31]_0 [17]),
        .R(out));
  FDRE \read_lat_shift_reg[18] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [17]),
        .Q(\read_lat_shift_reg[31]_0 [18]),
        .R(out));
  FDRE \read_lat_shift_reg[19] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [18]),
        .Q(\read_lat_shift_reg[31]_0 [19]),
        .R(out));
  FDRE \read_lat_shift_reg[1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [0]),
        .Q(\read_lat_shift_reg[31]_0 [1]),
        .R(out));
  FDRE \read_lat_shift_reg[20] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [19]),
        .Q(\read_lat_shift_reg[31]_0 [20]),
        .R(out));
  FDRE \read_lat_shift_reg[21] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [20]),
        .Q(\read_lat_shift_reg[31]_0 [21]),
        .R(out));
  FDRE \read_lat_shift_reg[22] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [21]),
        .Q(\read_lat_shift_reg[31]_0 [22]),
        .R(out));
  FDRE \read_lat_shift_reg[23] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [22]),
        .Q(\read_lat_shift_reg[31]_0 [23]),
        .R(out));
  FDRE \read_lat_shift_reg[24] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [23]),
        .Q(\read_lat_shift_reg[31]_0 [24]),
        .R(out));
  FDRE \read_lat_shift_reg[25] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [24]),
        .Q(\read_lat_shift_reg[31]_0 [25]),
        .R(out));
  FDRE \read_lat_shift_reg[26] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [25]),
        .Q(\read_lat_shift_reg[31]_0 [26]),
        .R(out));
  FDRE \read_lat_shift_reg[27] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [26]),
        .Q(\read_lat_shift_reg[31]_0 [27]),
        .R(out));
  FDRE \read_lat_shift_reg[28] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [27]),
        .Q(\read_lat_shift_reg[31]_0 [28]),
        .R(out));
  FDRE \read_lat_shift_reg[29] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [28]),
        .Q(\read_lat_shift_reg[31]_0 [29]),
        .R(out));
  FDRE \read_lat_shift_reg[2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [1]),
        .Q(\read_lat_shift_reg[31]_0 [2]),
        .R(out));
  FDRE \read_lat_shift_reg[30] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [29]),
        .Q(\read_lat_shift_reg[31]_0 [30]),
        .R(out));
  FDRE \read_lat_shift_reg[31] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [30]),
        .Q(\read_lat_shift_reg[31]_0 [31]),
        .R(out));
  FDRE \read_lat_shift_reg[3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [2]),
        .Q(\read_lat_shift_reg[31]_0 [3]),
        .R(out));
  FDRE \read_lat_shift_reg[4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [3]),
        .Q(\read_lat_shift_reg[31]_0 [4]),
        .R(out));
  FDRE \read_lat_shift_reg[5] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [4]),
        .Q(\read_lat_shift_reg[31]_0 [5]),
        .R(out));
  FDRE \read_lat_shift_reg[6] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [5]),
        .Q(\read_lat_shift_reg[31]_0 [6]),
        .R(out));
  FDRE \read_lat_shift_reg[7] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [6]),
        .Q(\read_lat_shift_reg[31]_0 [7]),
        .R(out));
  FDRE \read_lat_shift_reg[8] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [7]),
        .Q(\read_lat_shift_reg[31]_0 [8]),
        .R(out));
  FDRE \read_lat_shift_reg[9] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(\read_lat_shift_reg[31]_0 [8]),
        .Q(\read_lat_shift_reg[31]_0 [9]),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2480" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \read_lat_wptr[0]_i_1 
       (.I0(read_lat_wptr_reg[0]),
        .I1(read_lat_shift_nxt),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair2480" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \read_lat_wptr[1]_i_1 
       (.I0(read_lat_wptr_reg[0]),
        .I1(read_lat_shift_nxt),
        .I2(read_lat_wptr_reg[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair2222" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \read_lat_wptr[2]_i_1 
       (.I0(read_lat_shift_nxt),
        .I1(read_lat_wptr_reg[0]),
        .I2(read_lat_wptr_reg[1]),
        .I3(read_lat_wptr_reg[2]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair2222" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \read_lat_wptr[3]_i_1 
       (.I0(read_lat_wptr_reg[1]),
        .I1(read_lat_wptr_reg[0]),
        .I2(read_lat_shift_nxt),
        .I3(read_lat_wptr_reg[2]),
        .I4(read_lat_wptr_reg[3]),
        .O(p_0_in[3]));
  LUT2 #(
    .INIT(4'hE)) 
    \read_lat_wptr[4]_i_1 
       (.I0(out),
        .I1(cal_clear_fifo_rden),
        .O(read_lat_wptr));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \read_lat_wptr[4]_i_2 
       (.I0(read_lat_wptr_reg[2]),
        .I1(read_lat_shift_nxt),
        .I2(read_lat_wptr_reg[0]),
        .I3(read_lat_wptr_reg[1]),
        .I4(read_lat_wptr_reg[3]),
        .I5(read_lat_wptr_reg[4]),
        .O(p_0_in[4]));
  FDRE \read_lat_wptr_reg[0] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(read_lat_wptr_reg[0]),
        .R(read_lat_wptr));
  FDRE \read_lat_wptr_reg[1] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(read_lat_wptr_reg[1]),
        .R(read_lat_wptr));
  FDRE \read_lat_wptr_reg[2] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(read_lat_wptr_reg[2]),
        .R(read_lat_wptr));
  FDRE \read_lat_wptr_reg[3] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(read_lat_wptr_reg[3]),
        .R(read_lat_wptr));
  FDRE \read_lat_wptr_reg[4] 
       (.C(\rdDataAddr_reg[4]_rep__1_1 ),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(read_lat_wptr_reg[4]),
        .R(read_lat_wptr));
  LUT6 #(
    .INIT(64'h8200000000008200)) 
    underfill_done_i_1
       (.I0(rmw_rd_done),
        .I1(Q[4]),
        .I2(cmdBuf[4]),
        .I3(underfill_done_i_3_n_0),
        .I4(cmdBuf[3]),
        .I5(Q[3]),
        .O(underfill_done_nxt));
  LUT6 #(
    .INIT(64'h8200000000008200)) 
    underfill_done_i_1__0
       (.I0(rmw_rd_done),
        .I1(Q[4]),
        .I2(cmdBuf[9]),
        .I3(underfill_done_i_2__0_n_0),
        .I4(cmdBuf[8]),
        .I5(Q[3]),
        .O(\rdDataAddr_reg[4]_0 ));
  LUT6 #(
    .INIT(64'h8200000000008200)) 
    underfill_done_i_1__1
       (.I0(rmw_rd_done),
        .I1(Q[4]),
        .I2(cmdBuf[14]),
        .I3(underfill_done_i_2__1_n_0),
        .I4(cmdBuf[13]),
        .I5(Q[3]),
        .O(\rdDataAddr_reg[4]_1 ));
  LUT6 #(
    .INIT(64'h8200000000008200)) 
    underfill_done_i_1__2
       (.I0(rmw_rd_done),
        .I1(Q[4]),
        .I2(cmdBuf[19]),
        .I3(underfill_done_i_2__2_n_0),
        .I4(cmdBuf[18]),
        .I5(Q[3]),
        .O(\rdDataAddr_reg[4]_2 ));
  LUT2 #(
    .INIT(4'h8)) 
    underfill_done_i_2
       (.I0(read_data_en_reg_0),
        .I1(rdRmw),
        .O(rmw_rd_done));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    underfill_done_i_2__0
       (.I0(Q[0]),
        .I1(cmdBuf[5]),
        .I2(cmdBuf[7]),
        .I3(Q[2]),
        .I4(cmdBuf[6]),
        .I5(Q[1]),
        .O(underfill_done_i_2__0_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    underfill_done_i_2__1
       (.I0(Q[0]),
        .I1(cmdBuf[10]),
        .I2(cmdBuf[12]),
        .I3(Q[2]),
        .I4(cmdBuf[11]),
        .I5(Q[1]),
        .O(underfill_done_i_2__1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    underfill_done_i_2__2
       (.I0(Q[0]),
        .I1(cmdBuf[15]),
        .I2(cmdBuf[17]),
        .I3(Q[2]),
        .I4(cmdBuf[16]),
        .I5(Q[1]),
        .O(underfill_done_i_2__2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    underfill_done_i_3
       (.I0(Q[0]),
        .I1(cmdBuf[0]),
        .I2(cmdBuf[2]),
        .I3(Q[2]),
        .I4(cmdBuf[1]),
        .I5(Q[1]),
        .O(underfill_done_i_3_n_0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync
   (out,
    \SYNC[0].sync_reg_reg[0]_0 ,
    D);
  output [0:0]out;
  input \SYNC[0].sync_reg_reg[0]_0 ;
  input [0:0]D;

  wire [0:0]D;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  wire \SYNC[0].sync_reg_reg[0]_0 ;

  assign out[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[0]_0 ),
        .CE(1'b1),
        .D(D),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[0]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync_105
   (slave_rdy_fclk_r_reg,
    slave_rdy_fclk_r,
    E,
    D,
    \SYNC[0].sync_reg_reg[1]_0 ,
    \SYNC[0].sync_reg_reg[0]_0 );
  output slave_rdy_fclk_r_reg;
  input slave_rdy_fclk_r;
  input [0:0]E;
  input [0:0]D;
  input \SYNC[0].sync_reg_reg[1]_0 ;
  input [0:0]\SYNC[0].sync_reg_reg[0]_0 ;

  wire [0:0]D;
  wire [0:0]E;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  wire [0:0]\SYNC[0].sync_reg_reg[0]_0 ;
  wire \SYNC[0].sync_reg_reg[1]_0 ;
  wire slave_rdy_fclk_r;
  wire slave_rdy_fclk_r_reg;

  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg_reg[0]_0 ),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4F44)) 
    slave_rdy_lvl_fclk_i_1
       (.I0(slave_rdy_fclk_r),
        .I1(E),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(D),
        .O(slave_rdy_fclk_r_reg));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync_106
   (out,
    \SYNC[0].sync_reg_reg[1]_0 ,
    D);
  output [0:0]out;
  input \SYNC[0].sync_reg_reg[1]_0 ;
  input [0:0]D;

  wire [0:0]D;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  wire \SYNC[0].sync_reg_reg[1]_0 ;

  assign out[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(D),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized0
   (D,
    \SYNC[15].sync_reg_reg[1]_0 ,
    out);
  output [15:0]D;
  input \SYNC[15].sync_reg_reg[1]_0 ;
  input [15:0]out;

  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[10].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[11].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[12].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[13].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[14].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[15].sync_reg ;
  wire \SYNC[15].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[1].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[2].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[3].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[4].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[5].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[6].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[7].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[8].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[9].sync_reg ;
  wire [15:0]out;

  assign D[15] = \SYNC[15].sync_reg [1];
  assign D[14] = \SYNC[14].sync_reg [1];
  assign D[13] = \SYNC[13].sync_reg [1];
  assign D[12] = \SYNC[12].sync_reg [1];
  assign D[11] = \SYNC[11].sync_reg [1];
  assign D[10] = \SYNC[10].sync_reg [1];
  assign D[9] = \SYNC[9].sync_reg [1];
  assign D[8] = \SYNC[8].sync_reg [1];
  assign D[7] = \SYNC[7].sync_reg [1];
  assign D[6] = \SYNC[6].sync_reg [1];
  assign D[5] = \SYNC[5].sync_reg [1];
  assign D[4] = \SYNC[4].sync_reg [1];
  assign D[3] = \SYNC[3].sync_reg [1];
  assign D[2] = \SYNC[2].sync_reg [1];
  assign D[1] = \SYNC[1].sync_reg [1];
  assign D[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[0]),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[10]),
        .Q(\SYNC[10].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[10].sync_reg [0]),
        .Q(\SYNC[10].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[11]),
        .Q(\SYNC[11].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[11].sync_reg [0]),
        .Q(\SYNC[11].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[12]),
        .Q(\SYNC[12].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[12].sync_reg [0]),
        .Q(\SYNC[12].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[13]),
        .Q(\SYNC[13].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[13].sync_reg [0]),
        .Q(\SYNC[13].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[14]),
        .Q(\SYNC[14].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[14].sync_reg [0]),
        .Q(\SYNC[14].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[15]),
        .Q(\SYNC[15].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[15].sync_reg [0]),
        .Q(\SYNC[15].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[1]),
        .Q(\SYNC[1].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[1].sync_reg [0]),
        .Q(\SYNC[1].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[2]),
        .Q(\SYNC[2].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[2].sync_reg [0]),
        .Q(\SYNC[2].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[3]),
        .Q(\SYNC[3].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[3].sync_reg [0]),
        .Q(\SYNC[3].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[4]),
        .Q(\SYNC[4].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[4].sync_reg [0]),
        .Q(\SYNC[4].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[5]),
        .Q(\SYNC[5].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[5].sync_reg [0]),
        .Q(\SYNC[5].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[6]),
        .Q(\SYNC[6].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[6].sync_reg [0]),
        .Q(\SYNC[6].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[7]),
        .Q(\SYNC[7].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[7].sync_reg [0]),
        .Q(\SYNC[7].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[8]),
        .Q(\SYNC[8].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[8].sync_reg [0]),
        .Q(\SYNC[8].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[0] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[9]),
        .Q(\SYNC[9].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[1] 
       (.C(\SYNC[15].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[9].sync_reg [0]),
        .Q(\SYNC[9].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized1
   (D,
    \SYNC[7].sync_reg_reg[1]_0 ,
    out);
  output [8:0]D;
  input \SYNC[7].sync_reg_reg[1]_0 ;
  input [8:0]out;

  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[1].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[2].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[3].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[4].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[5].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[6].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[7].sync_reg ;
  wire \SYNC[7].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[8].sync_reg ;
  wire [8:0]out;

  assign D[8] = \SYNC[8].sync_reg [1];
  assign D[7] = \SYNC[7].sync_reg [1];
  assign D[6] = \SYNC[6].sync_reg [1];
  assign D[5] = \SYNC[5].sync_reg [1];
  assign D[4] = \SYNC[4].sync_reg [1];
  assign D[3] = \SYNC[3].sync_reg [1];
  assign D[2] = \SYNC[2].sync_reg [1];
  assign D[1] = \SYNC[1].sync_reg [1];
  assign D[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[0]),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[0] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[1]),
        .Q(\SYNC[1].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[1] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[1].sync_reg [0]),
        .Q(\SYNC[1].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[0] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[2]),
        .Q(\SYNC[2].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[1] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[2].sync_reg [0]),
        .Q(\SYNC[2].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[0] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[3]),
        .Q(\SYNC[3].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[1] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[3].sync_reg [0]),
        .Q(\SYNC[3].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[0] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[4]),
        .Q(\SYNC[4].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[1] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[4].sync_reg [0]),
        .Q(\SYNC[4].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[0] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[5]),
        .Q(\SYNC[5].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[1] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[5].sync_reg [0]),
        .Q(\SYNC[5].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[0] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[6]),
        .Q(\SYNC[6].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[1] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[6].sync_reg [0]),
        .Q(\SYNC[6].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[0] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[7]),
        .Q(\SYNC[7].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[1] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[7].sync_reg [0]),
        .Q(\SYNC[7].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[0] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(out[8]),
        .Q(\SYNC[8].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[1] 
       (.C(\SYNC[7].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[8].sync_reg [0]),
        .Q(\SYNC[8].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized2
   (out,
    CLK,
    D);
  output [0:0]out;
  input CLK;
  input [0:0]D;

  wire CLK;
  wire [0:0]D;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;

  assign out[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized3
   (s_do_i,
    CLK,
    out);
  output [8:0]s_do_i;
  input CLK;
  input [8:0]out;

  wire CLK;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[1].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[2].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[3].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[4].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[5].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[6].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[7].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[8].sync_reg ;
  wire [8:0]out;

  assign s_do_i[8] = \SYNC[8].sync_reg [1];
  assign s_do_i[7] = \SYNC[7].sync_reg [1];
  assign s_do_i[6] = \SYNC[6].sync_reg [1];
  assign s_do_i[5] = \SYNC[5].sync_reg [1];
  assign s_do_i[4] = \SYNC[4].sync_reg [1];
  assign s_do_i[3] = \SYNC[3].sync_reg [1];
  assign s_do_i[2] = \SYNC[2].sync_reg [1];
  assign s_do_i[1] = \SYNC[1].sync_reg [1];
  assign s_do_i[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(out[0]),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(out[1]),
        .Q(\SYNC[1].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[1].sync_reg [0]),
        .Q(\SYNC[1].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(out[2]),
        .Q(\SYNC[2].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[2].sync_reg [0]),
        .Q(\SYNC[2].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(out[3]),
        .Q(\SYNC[3].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[3].sync_reg [0]),
        .Q(\SYNC[3].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(out[4]),
        .Q(\SYNC[4].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[4].sync_reg [0]),
        .Q(\SYNC[4].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(out[5]),
        .Q(\SYNC[5].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[5].sync_reg [0]),
        .Q(\SYNC[5].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(out[6]),
        .Q(\SYNC[6].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[6].sync_reg [0]),
        .Q(\SYNC[6].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(out[7]),
        .Q(\SYNC[7].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[7].sync_reg [0]),
        .Q(\SYNC[7].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(out[8]),
        .Q(\SYNC[8].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[8].sync_reg [0]),
        .Q(\SYNC[8].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized4
   (out,
    CLK,
    D);
  output [0:0]out;
  input CLK;
  input [0:0]D;

  wire CLK;
  wire [0:0]D;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;

  assign out[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized4_0
   (out,
    CLK,
    D);
  output [0:0]out;
  input CLK;
  input [0:0]D;

  wire CLK;
  wire [0:0]D;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;

  assign out[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized4_3
   (out,
    \SYNC[0].sync_reg_reg[1]_0 ,
    D);
  output [0:0]out;
  input \SYNC[0].sync_reg_reg[1]_0 ;
  input [0:0]D;

  wire [0:0]D;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  wire \SYNC[0].sync_reg_reg[1]_0 ;

  assign out[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(D),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized4_7
   (out,
    \SYNC[0].sync_reg_reg[0]_0 ,
    D);
  output [0:0]out;
  input \SYNC[0].sync_reg_reg[0]_0 ;
  input [0:0]D;

  wire [0:0]D;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  wire \SYNC[0].sync_reg_reg[0]_0 ;

  assign out[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[0]_0 ),
        .CE(1'b1),
        .D(D),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[0]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized5
   (io_read_data_riuclk,
    CLK,
    \SYNC[31].sync_reg_reg[0]_0 );
  output [31:0]io_read_data_riuclk;
  input CLK;
  input [31:0]\SYNC[31].sync_reg_reg[0]_0 ;

  wire CLK;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[10].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[11].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[12].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[13].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[14].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[15].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[16].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[17].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[18].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[19].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[1].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[20].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[21].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[22].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[23].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[24].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[25].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[26].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[27].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[28].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[29].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[2].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[30].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[31].sync_reg ;
  wire [31:0]\SYNC[31].sync_reg_reg[0]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[3].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[4].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[5].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[6].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[7].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[8].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[9].sync_reg ;

  assign io_read_data_riuclk[31] = \SYNC[31].sync_reg [1];
  assign io_read_data_riuclk[30] = \SYNC[30].sync_reg [1];
  assign io_read_data_riuclk[29] = \SYNC[29].sync_reg [1];
  assign io_read_data_riuclk[28] = \SYNC[28].sync_reg [1];
  assign io_read_data_riuclk[27] = \SYNC[27].sync_reg [1];
  assign io_read_data_riuclk[26] = \SYNC[26].sync_reg [1];
  assign io_read_data_riuclk[25] = \SYNC[25].sync_reg [1];
  assign io_read_data_riuclk[24] = \SYNC[24].sync_reg [1];
  assign io_read_data_riuclk[23] = \SYNC[23].sync_reg [1];
  assign io_read_data_riuclk[22] = \SYNC[22].sync_reg [1];
  assign io_read_data_riuclk[21] = \SYNC[21].sync_reg [1];
  assign io_read_data_riuclk[20] = \SYNC[20].sync_reg [1];
  assign io_read_data_riuclk[19] = \SYNC[19].sync_reg [1];
  assign io_read_data_riuclk[18] = \SYNC[18].sync_reg [1];
  assign io_read_data_riuclk[17] = \SYNC[17].sync_reg [1];
  assign io_read_data_riuclk[16] = \SYNC[16].sync_reg [1];
  assign io_read_data_riuclk[15] = \SYNC[15].sync_reg [1];
  assign io_read_data_riuclk[14] = \SYNC[14].sync_reg [1];
  assign io_read_data_riuclk[13] = \SYNC[13].sync_reg [1];
  assign io_read_data_riuclk[12] = \SYNC[12].sync_reg [1];
  assign io_read_data_riuclk[11] = \SYNC[11].sync_reg [1];
  assign io_read_data_riuclk[10] = \SYNC[10].sync_reg [1];
  assign io_read_data_riuclk[9] = \SYNC[9].sync_reg [1];
  assign io_read_data_riuclk[8] = \SYNC[8].sync_reg [1];
  assign io_read_data_riuclk[7] = \SYNC[7].sync_reg [1];
  assign io_read_data_riuclk[6] = \SYNC[6].sync_reg [1];
  assign io_read_data_riuclk[5] = \SYNC[5].sync_reg [1];
  assign io_read_data_riuclk[4] = \SYNC[4].sync_reg [1];
  assign io_read_data_riuclk[3] = \SYNC[3].sync_reg [1];
  assign io_read_data_riuclk[2] = \SYNC[2].sync_reg [1];
  assign io_read_data_riuclk[1] = \SYNC[1].sync_reg [1];
  assign io_read_data_riuclk[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [0]),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [10]),
        .Q(\SYNC[10].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[10].sync_reg [0]),
        .Q(\SYNC[10].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [11]),
        .Q(\SYNC[11].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[11].sync_reg [0]),
        .Q(\SYNC[11].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [12]),
        .Q(\SYNC[12].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[12].sync_reg [0]),
        .Q(\SYNC[12].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [13]),
        .Q(\SYNC[13].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[13].sync_reg [0]),
        .Q(\SYNC[13].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [14]),
        .Q(\SYNC[14].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[14].sync_reg [0]),
        .Q(\SYNC[14].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [15]),
        .Q(\SYNC[15].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[15].sync_reg [0]),
        .Q(\SYNC[15].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [16]),
        .Q(\SYNC[16].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[16].sync_reg [0]),
        .Q(\SYNC[16].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [17]),
        .Q(\SYNC[17].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[17].sync_reg [0]),
        .Q(\SYNC[17].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [18]),
        .Q(\SYNC[18].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[18].sync_reg [0]),
        .Q(\SYNC[18].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [19]),
        .Q(\SYNC[19].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg [0]),
        .Q(\SYNC[19].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [1]),
        .Q(\SYNC[1].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[1].sync_reg [0]),
        .Q(\SYNC[1].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[20].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [20]),
        .Q(\SYNC[20].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[20].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[20].sync_reg [0]),
        .Q(\SYNC[20].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[21].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [21]),
        .Q(\SYNC[21].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[21].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[21].sync_reg [0]),
        .Q(\SYNC[21].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[22].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [22]),
        .Q(\SYNC[22].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[22].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[22].sync_reg [0]),
        .Q(\SYNC[22].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[23].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [23]),
        .Q(\SYNC[23].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[23].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[23].sync_reg [0]),
        .Q(\SYNC[23].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[24].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [24]),
        .Q(\SYNC[24].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[24].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[24].sync_reg [0]),
        .Q(\SYNC[24].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[25].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [25]),
        .Q(\SYNC[25].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[25].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[25].sync_reg [0]),
        .Q(\SYNC[25].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[26].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [26]),
        .Q(\SYNC[26].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[26].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[26].sync_reg [0]),
        .Q(\SYNC[26].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[27].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [27]),
        .Q(\SYNC[27].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[27].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[27].sync_reg [0]),
        .Q(\SYNC[27].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[28].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [28]),
        .Q(\SYNC[28].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[28].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[28].sync_reg [0]),
        .Q(\SYNC[28].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[29].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [29]),
        .Q(\SYNC[29].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[29].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[29].sync_reg [0]),
        .Q(\SYNC[29].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [2]),
        .Q(\SYNC[2].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[2].sync_reg [0]),
        .Q(\SYNC[2].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[30].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [30]),
        .Q(\SYNC[30].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[30].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[30].sync_reg [0]),
        .Q(\SYNC[30].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[31].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [31]),
        .Q(\SYNC[31].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[31].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg [0]),
        .Q(\SYNC[31].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [3]),
        .Q(\SYNC[3].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[3].sync_reg [0]),
        .Q(\SYNC[3].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [4]),
        .Q(\SYNC[4].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[4].sync_reg [0]),
        .Q(\SYNC[4].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [5]),
        .Q(\SYNC[5].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[5].sync_reg [0]),
        .Q(\SYNC[5].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [6]),
        .Q(\SYNC[6].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[6].sync_reg [0]),
        .Q(\SYNC[6].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [7]),
        .Q(\SYNC[7].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[7].sync_reg [0]),
        .Q(\SYNC[7].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [8]),
        .Q(\SYNC[8].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[8].sync_reg [0]),
        .Q(\SYNC[8].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [9]),
        .Q(\SYNC[9].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[9].sync_reg [0]),
        .Q(\SYNC[9].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized6
   (out,
    CLK,
    D);
  output [0:0]out;
  input CLK;
  input [0:0]D;

  wire CLK;
  wire [0:0]D;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;

  assign out[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(D),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized7
   (\SYNC[19].sync_reg_reg[1]_0 ,
    phy2clb_fixdly_rdy_low_riuclk);
  input \SYNC[19].sync_reg_reg[1]_0 ;
  input [19:0]phy2clb_fixdly_rdy_low_riuclk;

  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[10].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[11].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[12].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[13].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[14].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[15].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[16].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[17].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[18].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[19].sync_reg ;
  wire \SYNC[19].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[1].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[2].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[3].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[4].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[5].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[6].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[7].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[8].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[9].sync_reg ;
  wire [19:0]phy2clb_fixdly_rdy_low_riuclk;

  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[0]),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[10]),
        .Q(\SYNC[10].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[10].sync_reg [0]),
        .Q(\SYNC[10].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[11]),
        .Q(\SYNC[11].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[11].sync_reg [0]),
        .Q(\SYNC[11].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[12]),
        .Q(\SYNC[12].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[12].sync_reg [0]),
        .Q(\SYNC[12].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[13]),
        .Q(\SYNC[13].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[13].sync_reg [0]),
        .Q(\SYNC[13].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[14]),
        .Q(\SYNC[14].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[14].sync_reg [0]),
        .Q(\SYNC[14].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[15]),
        .Q(\SYNC[15].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[15].sync_reg [0]),
        .Q(\SYNC[15].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[16]),
        .Q(\SYNC[16].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[16].sync_reg [0]),
        .Q(\SYNC[16].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[17]),
        .Q(\SYNC[17].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[17].sync_reg [0]),
        .Q(\SYNC[17].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[18]),
        .Q(\SYNC[18].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[18].sync_reg [0]),
        .Q(\SYNC[18].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[19]),
        .Q(\SYNC[19].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg [0]),
        .Q(\SYNC[19].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[1]),
        .Q(\SYNC[1].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[1].sync_reg [0]),
        .Q(\SYNC[1].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[2]),
        .Q(\SYNC[2].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[2].sync_reg [0]),
        .Q(\SYNC[2].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[3]),
        .Q(\SYNC[3].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[3].sync_reg [0]),
        .Q(\SYNC[3].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[4]),
        .Q(\SYNC[4].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[4].sync_reg [0]),
        .Q(\SYNC[4].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[5]),
        .Q(\SYNC[5].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[5].sync_reg [0]),
        .Q(\SYNC[5].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[6]),
        .Q(\SYNC[6].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[6].sync_reg [0]),
        .Q(\SYNC[6].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[7]),
        .Q(\SYNC[7].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[7].sync_reg [0]),
        .Q(\SYNC[7].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[8]),
        .Q(\SYNC[8].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[8].sync_reg [0]),
        .Q(\SYNC[8].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_riuclk[9]),
        .Q(\SYNC[9].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[9].sync_reg [0]),
        .Q(\SYNC[9].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized7_4
   (\SYNC[19].sync_reg_reg[1]_0 ,
    phy2clb_fixdly_rdy_upp_riuclk);
  input \SYNC[19].sync_reg_reg[1]_0 ;
  input [19:0]phy2clb_fixdly_rdy_upp_riuclk;

  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[10].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[11].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[12].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[13].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[14].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[15].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[16].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[17].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[18].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[19].sync_reg ;
  wire \SYNC[19].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[1].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[2].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[3].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[4].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[5].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[6].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[7].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[8].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[9].sync_reg ;
  wire [19:0]phy2clb_fixdly_rdy_upp_riuclk;

  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[0]),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[10]),
        .Q(\SYNC[10].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[10].sync_reg [0]),
        .Q(\SYNC[10].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[11]),
        .Q(\SYNC[11].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[11].sync_reg [0]),
        .Q(\SYNC[11].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[12]),
        .Q(\SYNC[12].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[12].sync_reg [0]),
        .Q(\SYNC[12].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[13]),
        .Q(\SYNC[13].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[13].sync_reg [0]),
        .Q(\SYNC[13].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[14]),
        .Q(\SYNC[14].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[14].sync_reg [0]),
        .Q(\SYNC[14].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[15]),
        .Q(\SYNC[15].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[15].sync_reg [0]),
        .Q(\SYNC[15].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[16]),
        .Q(\SYNC[16].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[16].sync_reg [0]),
        .Q(\SYNC[16].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[17]),
        .Q(\SYNC[17].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[17].sync_reg [0]),
        .Q(\SYNC[17].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[18]),
        .Q(\SYNC[18].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[18].sync_reg [0]),
        .Q(\SYNC[18].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[19]),
        .Q(\SYNC[19].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg [0]),
        .Q(\SYNC[19].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[1]),
        .Q(\SYNC[1].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[1].sync_reg [0]),
        .Q(\SYNC[1].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[2]),
        .Q(\SYNC[2].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[2].sync_reg [0]),
        .Q(\SYNC[2].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[3]),
        .Q(\SYNC[3].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[3].sync_reg [0]),
        .Q(\SYNC[3].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[4]),
        .Q(\SYNC[4].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[4].sync_reg [0]),
        .Q(\SYNC[4].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[5]),
        .Q(\SYNC[5].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[5].sync_reg [0]),
        .Q(\SYNC[5].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[6]),
        .Q(\SYNC[6].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[6].sync_reg [0]),
        .Q(\SYNC[6].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[7]),
        .Q(\SYNC[7].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[7].sync_reg [0]),
        .Q(\SYNC[7].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[8]),
        .Q(\SYNC[8].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[8].sync_reg [0]),
        .Q(\SYNC[8].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_riuclk[9]),
        .Q(\SYNC[9].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[9].sync_reg [0]),
        .Q(\SYNC[9].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized7_5
   (\SYNC[19].sync_reg_reg[1]_0 ,
    phy2clb_phy_rdy_low_riuclk);
  input \SYNC[19].sync_reg_reg[1]_0 ;
  input [19:0]phy2clb_phy_rdy_low_riuclk;

  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[10].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[11].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[12].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[13].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[14].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[15].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[16].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[17].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[18].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[19].sync_reg ;
  wire \SYNC[19].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[1].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[2].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[3].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[4].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[5].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[6].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[7].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[8].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[9].sync_reg ;
  wire [19:0]phy2clb_phy_rdy_low_riuclk;

  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[0]),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[10]),
        .Q(\SYNC[10].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[10].sync_reg [0]),
        .Q(\SYNC[10].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[11]),
        .Q(\SYNC[11].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[11].sync_reg [0]),
        .Q(\SYNC[11].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[12]),
        .Q(\SYNC[12].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[12].sync_reg [0]),
        .Q(\SYNC[12].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[13]),
        .Q(\SYNC[13].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[13].sync_reg [0]),
        .Q(\SYNC[13].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[14]),
        .Q(\SYNC[14].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[14].sync_reg [0]),
        .Q(\SYNC[14].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[15]),
        .Q(\SYNC[15].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[15].sync_reg [0]),
        .Q(\SYNC[15].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[16]),
        .Q(\SYNC[16].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[16].sync_reg [0]),
        .Q(\SYNC[16].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[17]),
        .Q(\SYNC[17].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[17].sync_reg [0]),
        .Q(\SYNC[17].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[18]),
        .Q(\SYNC[18].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[18].sync_reg [0]),
        .Q(\SYNC[18].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[19]),
        .Q(\SYNC[19].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg [0]),
        .Q(\SYNC[19].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[1]),
        .Q(\SYNC[1].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[1].sync_reg [0]),
        .Q(\SYNC[1].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[2]),
        .Q(\SYNC[2].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[2].sync_reg [0]),
        .Q(\SYNC[2].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[3]),
        .Q(\SYNC[3].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[3].sync_reg [0]),
        .Q(\SYNC[3].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[4]),
        .Q(\SYNC[4].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[4].sync_reg [0]),
        .Q(\SYNC[4].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[5]),
        .Q(\SYNC[5].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[5].sync_reg [0]),
        .Q(\SYNC[5].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[6]),
        .Q(\SYNC[6].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[6].sync_reg [0]),
        .Q(\SYNC[6].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[7]),
        .Q(\SYNC[7].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[7].sync_reg [0]),
        .Q(\SYNC[7].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[8]),
        .Q(\SYNC[8].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[8].sync_reg [0]),
        .Q(\SYNC[8].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_riuclk[9]),
        .Q(\SYNC[9].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[9].sync_reg [0]),
        .Q(\SYNC[9].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized7_6
   (\SYNC[19].sync_reg_reg[1]_0 ,
    phy2clb_phy_rdy_upp_riuclk);
  input \SYNC[19].sync_reg_reg[1]_0 ;
  input [19:0]phy2clb_phy_rdy_upp_riuclk;

  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[10].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[11].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[12].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[13].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[14].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[15].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[16].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[17].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[18].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[19].sync_reg ;
  wire \SYNC[19].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[1].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[2].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[3].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[4].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[5].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[6].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[7].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[8].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[9].sync_reg ;
  wire [19:0]phy2clb_phy_rdy_upp_riuclk;

  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[0]),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[10]),
        .Q(\SYNC[10].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[10].sync_reg [0]),
        .Q(\SYNC[10].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[11]),
        .Q(\SYNC[11].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[11].sync_reg [0]),
        .Q(\SYNC[11].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[12]),
        .Q(\SYNC[12].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[12].sync_reg [0]),
        .Q(\SYNC[12].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[13]),
        .Q(\SYNC[13].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[13].sync_reg [0]),
        .Q(\SYNC[13].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[14]),
        .Q(\SYNC[14].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[14].sync_reg [0]),
        .Q(\SYNC[14].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[15]),
        .Q(\SYNC[15].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[15].sync_reg [0]),
        .Q(\SYNC[15].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[16]),
        .Q(\SYNC[16].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[16].sync_reg [0]),
        .Q(\SYNC[16].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[17]),
        .Q(\SYNC[17].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[17].sync_reg [0]),
        .Q(\SYNC[17].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[18]),
        .Q(\SYNC[18].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[18].sync_reg [0]),
        .Q(\SYNC[18].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[19]),
        .Q(\SYNC[19].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg [0]),
        .Q(\SYNC[19].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[1]),
        .Q(\SYNC[1].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[1].sync_reg [0]),
        .Q(\SYNC[1].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[2]),
        .Q(\SYNC[2].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[2].sync_reg [0]),
        .Q(\SYNC[2].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[3]),
        .Q(\SYNC[3].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[3].sync_reg [0]),
        .Q(\SYNC[3].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[4]),
        .Q(\SYNC[4].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[4].sync_reg [0]),
        .Q(\SYNC[4].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[5]),
        .Q(\SYNC[5].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[5].sync_reg [0]),
        .Q(\SYNC[5].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[6]),
        .Q(\SYNC[6].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[6].sync_reg [0]),
        .Q(\SYNC[6].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[7]),
        .Q(\SYNC[7].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[7].sync_reg [0]),
        .Q(\SYNC[7].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[8]),
        .Q(\SYNC[8].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[8].sync_reg [0]),
        .Q(\SYNC[8].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_riuclk[9]),
        .Q(\SYNC[9].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[9].sync_reg [0]),
        .Q(\SYNC[9].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized7_8
   (riu2clb_valid,
    \SYNC[19].sync_reg_reg[1]_0 ,
    \SYNC[19].sync_reg_reg[0]_0 );
  output [19:0]riu2clb_valid;
  input \SYNC[19].sync_reg_reg[1]_0 ;
  input [19:0]\SYNC[19].sync_reg_reg[0]_0 ;

  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[10].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[11].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[12].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[13].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[14].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[15].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[16].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[17].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[18].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[19].sync_reg ;
  wire [19:0]\SYNC[19].sync_reg_reg[0]_0 ;
  wire \SYNC[19].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[1].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[2].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[3].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[4].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[5].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[6].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[7].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[8].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[9].sync_reg ;

  assign riu2clb_valid[19] = \SYNC[19].sync_reg [1];
  assign riu2clb_valid[18] = \SYNC[18].sync_reg [1];
  assign riu2clb_valid[17] = \SYNC[17].sync_reg [1];
  assign riu2clb_valid[16] = \SYNC[16].sync_reg [1];
  assign riu2clb_valid[15] = \SYNC[15].sync_reg [1];
  assign riu2clb_valid[14] = \SYNC[14].sync_reg [1];
  assign riu2clb_valid[13] = \SYNC[13].sync_reg [1];
  assign riu2clb_valid[12] = \SYNC[12].sync_reg [1];
  assign riu2clb_valid[11] = \SYNC[11].sync_reg [1];
  assign riu2clb_valid[10] = \SYNC[10].sync_reg [1];
  assign riu2clb_valid[9] = \SYNC[9].sync_reg [1];
  assign riu2clb_valid[8] = \SYNC[8].sync_reg [1];
  assign riu2clb_valid[7] = \SYNC[7].sync_reg [1];
  assign riu2clb_valid[6] = \SYNC[6].sync_reg [1];
  assign riu2clb_valid[5] = \SYNC[5].sync_reg [1];
  assign riu2clb_valid[4] = \SYNC[4].sync_reg [1];
  assign riu2clb_valid[3] = \SYNC[3].sync_reg [1];
  assign riu2clb_valid[2] = \SYNC[2].sync_reg [1];
  assign riu2clb_valid[1] = \SYNC[1].sync_reg [1];
  assign riu2clb_valid[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [0]),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [10]),
        .Q(\SYNC[10].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[10].sync_reg [0]),
        .Q(\SYNC[10].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [11]),
        .Q(\SYNC[11].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[11].sync_reg [0]),
        .Q(\SYNC[11].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [12]),
        .Q(\SYNC[12].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[12].sync_reg [0]),
        .Q(\SYNC[12].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [13]),
        .Q(\SYNC[13].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[13].sync_reg [0]),
        .Q(\SYNC[13].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [14]),
        .Q(\SYNC[14].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[14].sync_reg [0]),
        .Q(\SYNC[14].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [15]),
        .Q(\SYNC[15].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[15].sync_reg [0]),
        .Q(\SYNC[15].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [16]),
        .Q(\SYNC[16].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[16].sync_reg [0]),
        .Q(\SYNC[16].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [17]),
        .Q(\SYNC[17].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[17].sync_reg [0]),
        .Q(\SYNC[17].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [18]),
        .Q(\SYNC[18].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[18].sync_reg [0]),
        .Q(\SYNC[18].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [19]),
        .Q(\SYNC[19].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg [0]),
        .Q(\SYNC[19].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [1]),
        .Q(\SYNC[1].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[1].sync_reg [0]),
        .Q(\SYNC[1].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [2]),
        .Q(\SYNC[2].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[2].sync_reg [0]),
        .Q(\SYNC[2].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [3]),
        .Q(\SYNC[3].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[3].sync_reg [0]),
        .Q(\SYNC[3].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [4]),
        .Q(\SYNC[4].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[4].sync_reg [0]),
        .Q(\SYNC[4].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [5]),
        .Q(\SYNC[5].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[5].sync_reg [0]),
        .Q(\SYNC[5].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [6]),
        .Q(\SYNC[6].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[6].sync_reg [0]),
        .Q(\SYNC[6].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [7]),
        .Q(\SYNC[7].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[7].sync_reg [0]),
        .Q(\SYNC[7].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [8]),
        .Q(\SYNC[8].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[8].sync_reg [0]),
        .Q(\SYNC[8].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[0] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg_reg[0]_0 [9]),
        .Q(\SYNC[9].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[1] 
       (.C(\SYNC[19].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[9].sync_reg [0]),
        .Q(\SYNC[9].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized8
   (\SYNC[23].sync_reg_reg[1]_0 ,
    clear_gt_data_ready_flag,
    \SYNC[0].sync_reg_reg[1]_0 ,
    \SYNC[9].sync_reg_reg[1]_0 ,
    \SYNC[8].sync_reg_reg[1]_0 ,
    \SYNC[0].sync_reg_reg[1]_1 ,
    \SYNC[17].sync_reg_reg[1]_0 ,
    \SYNC[20].sync_reg_reg[1]_0 ,
    \SYNC[18].sync_reg_reg[1]_0 ,
    \SYNC[19].sync_reg_reg[1]_0 ,
    \SYNC[2].sync_reg_reg[1]_0 ,
    \SYNC[8].sync_reg_reg[1]_1 ,
    \SYNC[1].sync_reg_reg[1]_0 ,
    \SYNC[1].sync_reg_reg[1]_1 ,
    \SYNC[4].sync_reg_reg[1]_0 ,
    \SYNC[4].sync_reg_reg[1]_1 ,
    \SYNC[6].sync_reg_reg[1]_0 ,
    \SYNC[6].sync_reg_reg[1]_1 ,
    \SYNC[6].sync_reg_reg[1]_2 ,
    \SYNC[24].sync_reg_reg[1]_0 ,
    \SYNC[24].sync_reg_reg[1]_1 ,
    rst_r1_reg,
    \SYNC[4].sync_reg_reg[1]_2 ,
    \SYNC[4].sync_reg_reg[1]_3 ,
    \SYNC[17].sync_reg_reg[1]_1 ,
    \SYNC[18].sync_reg_reg[1]_1 ,
    \SYNC[10].sync_reg_reg[1]_0 ,
    \SYNC[20].sync_reg_reg[1]_1 ,
    \SYNC[19].sync_reg_reg[1]_1 ,
    cnt_clr_access,
    lrdimm_cmp_clr,
    a_b_cmd_sel_start0,
    \SYNC[3].sync_reg_reg[1]_0 ,
    \SYNC[3].sync_reg_reg[1]_1 ,
    \SYNC[17].sync_reg_reg[1]_2 ,
    \SYNC[23].sync_reg_reg[1]_1 ,
    io_addr_strobe_reg,
    \SYNC[1].sync_reg_reg[1]_2 ,
    \SYNC[4].sync_reg_reg[1]_4 ,
    \SYNC[21].sync_reg_reg[1]_0 ,
    rst_r1_reg_0,
    \SYNC[21].sync_reg_reg[1]_1 ,
    \cal_timer_reg[31] ,
    \SYNC[12].sync_reg_reg[1]_0 ,
    \SYNC[22].sync_reg_reg[1]_0 ,
    \SYNC[4].sync_reg_reg[1]_5 ,
    \SYNC[23].sync_reg_reg[1]_2 ,
    \SYNC[12].sync_reg_reg[1]_1 ,
    \SYNC[9].sync_reg_reg[1]_1 ,
    \SYNC[18].sync_reg_reg[1]_2 ,
    \SYNC[17].sync_reg_reg[1]_3 ,
    \SYNC[17].sync_reg_reg[1]_4 ,
    \SYNC[9].sync_reg_reg[1]_2 ,
    \SYNC[12].sync_reg_reg[1]_2 ,
    \SYNC[21].sync_reg_reg[1]_2 ,
    \SYNC[18].sync_reg_reg[1]_3 ,
    ena,
    \SYNC[3].sync_reg_reg[1]_2 ,
    \SYNC[20].sync_reg_reg[1]_2 ,
    \SYNC[9].sync_reg_reg[1]_3 ,
    \SYNC[0].sync_reg_reg[1]_2 ,
    \SYNC[21].sync_reg_reg[1]_3 ,
    \SYNC[0].sync_reg_reg[1]_3 ,
    \SYNC[4].sync_reg_reg[1]_6 ,
    cnt_clr_reg,
    \SYNC[0].sync_reg_reg[1]_4 ,
    \SYNC[0].sync_reg_reg[1]_5 ,
    \SYNC[0].sync_reg_reg[1]_6 ,
    io_addr_strobe_reg_0,
    E,
    rst_r1_reg_1,
    \SYNC[8].sync_reg_reg[1]_2 ,
    \SYNC[8].sync_reg_reg[1]_3 ,
    \SYNC[20].sync_reg_reg[1]_3 ,
    \SYNC[20].sync_reg_reg[1]_4 ,
    \SYNC[20].sync_reg_reg[1]_5 ,
    \SYNC[20].sync_reg_reg[1]_6 ,
    \SYNC[8].sync_reg_reg[1]_4 ,
    \SYNC[20].sync_reg_reg[1]_7 ,
    \cal_timer_reg[30] ,
    cal_timer_reg_23_sp_1,
    cal_timer_reg_22_sp_1,
    rd_vref_value0_out,
    \SYNC[1].sync_reg_reg[1]_3 ,
    \SYNC[0].sync_reg_reg[1]_7 ,
    \SYNC[0].sync_reg_reg[1]_8 ,
    io_addr_strobe,
    out,
    gt_data_ready_flag,
    xsdb_wr_en_reg,
    \cal_cs_pos_reg[1] ,
    p_52_in,
    \cal_DQOut_post_reg[31] ,
    io_write_data,
    \addr_dec_to_mb_data_reg[31] ,
    cal_timer_reg,
    \addr_dec_to_mb_data_reg[31]_0 ,
    \addr_dec_to_mb_data[7]_i_5_0 ,
    \addr_dec_to_mb_data[2]_i_4_0 ,
    \addr_dec_to_mb_data_reg[1] ,
    \addr_dec_to_mb_data[1]_i_3_0 ,
    \addr_dec_to_mb_data_reg[19] ,
    \addr_dec_to_mb_data_reg[19]_0 ,
    riu2clb_valid,
    \addr_dec_to_mb_data_reg[18] ,
    \addr_dec_to_mb_data_reg[17] ,
    \addr_dec_to_mb_data_reg[16] ,
    \addr_dec_to_mb_data_reg[16]_0 ,
    \addr_dec_to_mb_data_reg[13] ,
    \addr_dec_to_mb_data_reg[12] ,
    \addr_dec_to_mb_data_reg[12]_0 ,
    \addr_dec_to_mb_data_reg[11] ,
    \addr_dec_to_mb_data_reg[10] ,
    \addr_dec_to_mb_data_reg[9] ,
    \addr_dec_to_mb_data_reg[8] ,
    \addr_dec_to_mb_data_reg[3] ,
    \addr_dec_to_mb_data[5]_i_6_0 ,
    \addr_dec_to_mb_data[5]_i_6_1 ,
    \addr_dec_to_mb_data_reg[2] ,
    douta,
    \addr_dec_to_mb_data[1]_i_2_0 ,
    \addr_dec_to_mb_data_reg[0] ,
    \addr_dec_to_mb_data[5]_i_2_0 ,
    \addr_dec_to_mb_data_reg[5] ,
    \addr_dec_to_mb_data_reg[4] ,
    \addr_dec_to_mb_data_reg[4]_0 ,
    \addr_dec_to_mb_data_reg[6] ,
    \addr_dec_to_mb_data_reg[7] ,
    initDone,
    phy2clb_rd_dq_bits,
    \addr_dec_to_mb_data_reg[5]_0 ,
    \addr_dec_to_mb_data[6]_i_4_0 ,
    \addr_dec_to_mb_data_reg[0]_0 ,
    \addr_dec_to_mb_data[4]_i_3_0 ,
    \addr_dec_to_mb_data[0]_i_6_0 ,
    \addr_dec_to_mb_data[1]_i_5_0 ,
    \addr_dec_to_mb_data[1]_i_5_1 ,
    \addr_dec_to_mb_data[2]_i_6_0 ,
    \addr_dec_to_mb_data[2]_i_6_1 ,
    \addr_dec_to_mb_data_reg[14] ,
    \addr_dec_to_mb_data_reg[14]_0 ,
    \addr_dec_to_mb_data_reg[15] ,
    \addr_dec_to_mb_data_reg[15]_0 ,
    \addr_dec_to_mb_data[31]_i_3_0 ,
    \addr_dec_to_mb_data[31]_i_9_0 ,
    \addr_dec_to_mb_data[30]_i_6_0 ,
    \addr_dec_to_mb_data[11]_i_3_0 ,
    \addr_dec_to_mb_data[3]_i_3_0 ,
    \addr_dec_to_mb_data[30]_i_6_1 ,
    \addr_dec_to_mb_data[0]_i_6_1 ,
    \addr_dec_to_mb_data_reg[0]_1 ,
    \addr_dec_to_mb_data[29]_i_2_0 ,
    \addr_dec_to_mb_data[29]_i_2_1 ,
    \addr_dec_to_mb_data[28]_i_2_0 ,
    \addr_dec_to_mb_data[28]_i_2_1 ,
    \addr_dec_to_mb_data[27]_i_2_0 ,
    \addr_dec_to_mb_data[27]_i_2_1 ,
    \addr_dec_to_mb_data[26]_i_2_0 ,
    \addr_dec_to_mb_data[26]_i_2_1 ,
    \addr_dec_to_mb_data[25]_i_2_0 ,
    \addr_dec_to_mb_data[25]_i_2_1 ,
    \addr_dec_to_mb_data[24]_i_2_0 ,
    \addr_dec_to_mb_data[24]_i_2_1 ,
    \addr_dec_to_mb_data[21]_i_2_0 ,
    \addr_dec_to_mb_data[21]_i_2_1 ,
    \addr_dec_to_mb_data[20]_i_2_0 ,
    \addr_dec_to_mb_data[20]_i_2_1 ,
    \addr_dec_to_mb_data[5]_i_2_1 ,
    \addr_dec_to_mb_data[5]_i_2_2 ,
    \addr_dec_to_mb_data_reg[10]_0 ,
    \addr_dec_to_mb_data_reg[11]_0 ,
    \addr_dec_to_mb_data_reg[12]_1 ,
    \addr_dec_to_mb_data[0]_i_6_2 ,
    \addr_dec_to_mb_data[0]_i_6_3 ,
    \addr_dec_to_mb_data[4]_i_3_1 ,
    \addr_dec_to_mb_data[4]_i_3_2 ,
    \addr_dec_to_mb_data[30]_i_6_2 ,
    \addr_dec_to_mb_data_reg[27] ,
    \addr_dec_to_mb_data_reg[26] ,
    \addr_dec_to_mb_data_reg[20] ,
    \addr_dec_to_mb_data[4]_i_11_0 ,
    \addr_dec_to_mb_data_reg[16]_1 ,
    \addr_dec_to_mb_data_reg[17]_0 ,
    \addr_dec_to_mb_data_reg[18]_0 ,
    \addr_dec_to_mb_data_reg[19]_1 ,
    \addr_dec_to_mb_data[0]_i_21_0 ,
    \addr_dec_to_mb_data[0]_i_21_1 ,
    \addr_dec_to_mb_data[9]_i_4_0 ,
    \addr_dec_to_mb_data_reg[13]_0 ,
    \addr_dec_to_mb_data_reg[20]_0 ,
    \addr_dec_to_mb_data[22]_i_3_0 ,
    \addr_dec_to_mb_data_reg[24] ,
    \addr_dec_to_mb_data_reg[25] ,
    \addr_dec_to_mb_data_reg[26]_0 ,
    \addr_dec_to_mb_data_reg[27]_0 ,
    \addr_dec_to_mb_data[4]_i_3_3 ,
    \addr_dec_to_mb_data[3]_i_10_0 ,
    \addr_dec_to_mb_data[3]_i_10_1 ,
    \addr_dec_to_mb_data[2]_i_6_2 ,
    \addr_dec_to_mb_data[7]_i_15_0 ,
    stop_gate_tracking_ack_reg,
    \addr_dec_to_mb_data[4]_i_10_0 ,
    \addr_dec_to_mb_data[2]_i_11_0 ,
    \addr_dec_to_mb_data[8]_i_4_0 ,
    \addr_dec_to_mb_data[8]_i_4_1 ,
    \addr_dec_to_mb_data[9]_i_3_0 ,
    \addr_dec_to_mb_data[9]_i_3_1 ,
    \addr_dec_to_mb_data[10]_i_4_0 ,
    \addr_dec_to_mb_data[10]_i_4_1 ,
    \addr_dec_to_mb_data[11]_i_4_0 ,
    \addr_dec_to_mb_data[11]_i_4_1 ,
    \addr_dec_to_mb_data[12]_i_4_0 ,
    \addr_dec_to_mb_data[12]_i_4_1 ,
    \addr_dec_to_mb_data[13]_i_2_0 ,
    \addr_dec_to_mb_data[13]_i_2_1 ,
    \addr_dec_to_mb_data[16]_i_2_0 ,
    \addr_dec_to_mb_data[16]_i_2_1 ,
    \addr_dec_to_mb_data[17]_i_2_0 ,
    \addr_dec_to_mb_data[17]_i_2_1 ,
    \addr_dec_to_mb_data[18]_i_2_0 ,
    \addr_dec_to_mb_data[18]_i_2_1 ,
    \addr_dec_to_mb_data[19]_i_2_0 ,
    \addr_dec_to_mb_data[19]_i_2_1 ,
    \addr_dec_to_mb_data[8]_i_8_0 ,
    ub_calDone,
    \addr_dec_to_mb_data[3]_i_13_0 ,
    \addr_dec_to_mb_data[2]_i_4_1 ,
    cplx_status,
    cnt_clr,
    lrdimm_cmp_en,
    cal_oe_dis_low,
    cal_oe_dis_upp,
    \addr_dec_to_mb_data_reg[29] ,
    \addr_dec_to_mb_data_reg[29]_0 ,
    \addr_dec_to_mb_data_reg[28] ,
    \addr_dec_to_mb_data_reg[25]_0 ,
    \addr_dec_to_mb_data_reg[24]_0 ,
    \addr_dec_to_mb_data_reg[21] ,
    \addr_dec_to_mb_data_reg[21]_0 ,
    \addr_dec_to_mb_data_reg[15]_1 ,
    \addr_dec_to_mb_data_reg[30] ,
    \addr_dec_to_mb_data_reg[23] ,
    \addr_dec_to_mb_data_reg[22] ,
    \SYNC[31].sync_reg_reg[1]_0 ,
    \SYNC[31].sync_reg_reg[0]_0 );
  output [20:0]\SYNC[23].sync_reg_reg[1]_0 ;
  output clear_gt_data_ready_flag;
  output [0:0]\SYNC[0].sync_reg_reg[1]_0 ;
  output [0:0]\SYNC[9].sync_reg_reg[1]_0 ;
  output [0:0]\SYNC[8].sync_reg_reg[1]_0 ;
  output [0:0]\SYNC[0].sync_reg_reg[1]_1 ;
  output [0:0]\SYNC[17].sync_reg_reg[1]_0 ;
  output [0:0]\SYNC[20].sync_reg_reg[1]_0 ;
  output [0:0]\SYNC[18].sync_reg_reg[1]_0 ;
  output [0:0]\SYNC[19].sync_reg_reg[1]_0 ;
  output [0:0]\SYNC[2].sync_reg_reg[1]_0 ;
  output [0:0]\SYNC[8].sync_reg_reg[1]_1 ;
  output [0:0]\SYNC[1].sync_reg_reg[1]_0 ;
  output [0:0]\SYNC[1].sync_reg_reg[1]_1 ;
  output \SYNC[4].sync_reg_reg[1]_0 ;
  output \SYNC[4].sync_reg_reg[1]_1 ;
  output \SYNC[6].sync_reg_reg[1]_0 ;
  output \SYNC[6].sync_reg_reg[1]_1 ;
  output \SYNC[6].sync_reg_reg[1]_2 ;
  output \SYNC[24].sync_reg_reg[1]_0 ;
  output \SYNC[24].sync_reg_reg[1]_1 ;
  output rst_r1_reg;
  output \SYNC[4].sync_reg_reg[1]_2 ;
  output \SYNC[4].sync_reg_reg[1]_3 ;
  output \SYNC[17].sync_reg_reg[1]_1 ;
  output [0:0]\SYNC[18].sync_reg_reg[1]_1 ;
  output [0:0]\SYNC[10].sync_reg_reg[1]_0 ;
  output [0:0]\SYNC[20].sync_reg_reg[1]_1 ;
  output [0:0]\SYNC[19].sync_reg_reg[1]_1 ;
  output cnt_clr_access;
  output lrdimm_cmp_clr;
  output a_b_cmd_sel_start0;
  output \SYNC[3].sync_reg_reg[1]_0 ;
  output \SYNC[3].sync_reg_reg[1]_1 ;
  output [0:0]\SYNC[17].sync_reg_reg[1]_2 ;
  output \SYNC[23].sync_reg_reg[1]_1 ;
  output [0:0]io_addr_strobe_reg;
  output [7:0]\SYNC[1].sync_reg_reg[1]_2 ;
  output [0:0]\SYNC[4].sync_reg_reg[1]_4 ;
  output \SYNC[21].sync_reg_reg[1]_0 ;
  output [0:0]rst_r1_reg_0;
  output [0:0]\SYNC[21].sync_reg_reg[1]_1 ;
  output [20:0]\cal_timer_reg[31] ;
  output \SYNC[12].sync_reg_reg[1]_0 ;
  output \SYNC[22].sync_reg_reg[1]_0 ;
  output \SYNC[4].sync_reg_reg[1]_5 ;
  output \SYNC[23].sync_reg_reg[1]_2 ;
  output \SYNC[12].sync_reg_reg[1]_1 ;
  output \SYNC[9].sync_reg_reg[1]_1 ;
  output \SYNC[18].sync_reg_reg[1]_2 ;
  output \SYNC[17].sync_reg_reg[1]_3 ;
  output \SYNC[17].sync_reg_reg[1]_4 ;
  output \SYNC[9].sync_reg_reg[1]_2 ;
  output \SYNC[12].sync_reg_reg[1]_2 ;
  output \SYNC[21].sync_reg_reg[1]_2 ;
  output \SYNC[18].sync_reg_reg[1]_3 ;
  output ena;
  output \SYNC[3].sync_reg_reg[1]_2 ;
  output \SYNC[20].sync_reg_reg[1]_2 ;
  output \SYNC[9].sync_reg_reg[1]_3 ;
  output [0:0]\SYNC[0].sync_reg_reg[1]_2 ;
  output \SYNC[21].sync_reg_reg[1]_3 ;
  output \SYNC[0].sync_reg_reg[1]_3 ;
  output \SYNC[4].sync_reg_reg[1]_6 ;
  output cnt_clr_reg;
  output \SYNC[0].sync_reg_reg[1]_4 ;
  output \SYNC[0].sync_reg_reg[1]_5 ;
  output \SYNC[0].sync_reg_reg[1]_6 ;
  output io_addr_strobe_reg_0;
  output [0:0]E;
  output [0:0]rst_r1_reg_1;
  output \SYNC[8].sync_reg_reg[1]_2 ;
  output \SYNC[8].sync_reg_reg[1]_3 ;
  output \SYNC[20].sync_reg_reg[1]_3 ;
  output \SYNC[20].sync_reg_reg[1]_4 ;
  output \SYNC[20].sync_reg_reg[1]_5 ;
  output \SYNC[20].sync_reg_reg[1]_6 ;
  output \SYNC[8].sync_reg_reg[1]_4 ;
  output \SYNC[20].sync_reg_reg[1]_7 ;
  output \cal_timer_reg[30] ;
  output cal_timer_reg_23_sp_1;
  output cal_timer_reg_22_sp_1;
  output [7:0]rd_vref_value0_out;
  output \SYNC[1].sync_reg_reg[1]_3 ;
  output \SYNC[0].sync_reg_reg[1]_7 ;
  output [10:0]\SYNC[0].sync_reg_reg[1]_8 ;
  input io_addr_strobe;
  input [0:0]out;
  input gt_data_ready_flag;
  input xsdb_wr_en_reg;
  input \cal_cs_pos_reg[1] ;
  input p_52_in;
  input \cal_DQOut_post_reg[31] ;
  input [1:0]io_write_data;
  input \addr_dec_to_mb_data_reg[31] ;
  input [26:0]cal_timer_reg;
  input \addr_dec_to_mb_data_reg[31]_0 ;
  input [6:0]\addr_dec_to_mb_data[7]_i_5_0 ;
  input \addr_dec_to_mb_data[2]_i_4_0 ;
  input \addr_dec_to_mb_data_reg[1] ;
  input \addr_dec_to_mb_data[1]_i_3_0 ;
  input \addr_dec_to_mb_data_reg[19] ;
  input \addr_dec_to_mb_data_reg[19]_0 ;
  input [19:0]riu2clb_valid;
  input \addr_dec_to_mb_data_reg[18] ;
  input \addr_dec_to_mb_data_reg[17] ;
  input [9:0]\addr_dec_to_mb_data_reg[16] ;
  input \addr_dec_to_mb_data_reg[16]_0 ;
  input \addr_dec_to_mb_data_reg[13] ;
  input \addr_dec_to_mb_data_reg[12] ;
  input \addr_dec_to_mb_data_reg[12]_0 ;
  input \addr_dec_to_mb_data_reg[11] ;
  input \addr_dec_to_mb_data_reg[10] ;
  input \addr_dec_to_mb_data_reg[9] ;
  input \addr_dec_to_mb_data_reg[8] ;
  input \addr_dec_to_mb_data_reg[3] ;
  input [4:0]\addr_dec_to_mb_data[5]_i_6_0 ;
  input [4:0]\addr_dec_to_mb_data[5]_i_6_1 ;
  input [0:0]\addr_dec_to_mb_data_reg[2] ;
  input [8:0]douta;
  input \addr_dec_to_mb_data[1]_i_2_0 ;
  input \addr_dec_to_mb_data_reg[0] ;
  input \addr_dec_to_mb_data[5]_i_2_0 ;
  input \addr_dec_to_mb_data_reg[5] ;
  input \addr_dec_to_mb_data_reg[4] ;
  input \addr_dec_to_mb_data_reg[4]_0 ;
  input \addr_dec_to_mb_data_reg[6] ;
  input \addr_dec_to_mb_data_reg[7] ;
  input initDone;
  input [7:0]phy2clb_rd_dq_bits;
  input \addr_dec_to_mb_data_reg[5]_0 ;
  input \addr_dec_to_mb_data[6]_i_4_0 ;
  input \addr_dec_to_mb_data_reg[0]_0 ;
  input \addr_dec_to_mb_data[4]_i_3_0 ;
  input \addr_dec_to_mb_data[0]_i_6_0 ;
  input \addr_dec_to_mb_data[1]_i_5_0 ;
  input \addr_dec_to_mb_data[1]_i_5_1 ;
  input \addr_dec_to_mb_data[2]_i_6_0 ;
  input \addr_dec_to_mb_data[2]_i_6_1 ;
  input \addr_dec_to_mb_data_reg[14] ;
  input \addr_dec_to_mb_data_reg[14]_0 ;
  input \addr_dec_to_mb_data_reg[15] ;
  input \addr_dec_to_mb_data_reg[15]_0 ;
  input [31:0]\addr_dec_to_mb_data[31]_i_3_0 ;
  input [53:0]\addr_dec_to_mb_data[31]_i_9_0 ;
  input [10:0]\addr_dec_to_mb_data[30]_i_6_0 ;
  input [10:0]\addr_dec_to_mb_data[11]_i_3_0 ;
  input \addr_dec_to_mb_data[3]_i_3_0 ;
  input [12:0]\addr_dec_to_mb_data[30]_i_6_1 ;
  input \addr_dec_to_mb_data[0]_i_6_1 ;
  input \addr_dec_to_mb_data_reg[0]_1 ;
  input \addr_dec_to_mb_data[29]_i_2_0 ;
  input \addr_dec_to_mb_data[29]_i_2_1 ;
  input \addr_dec_to_mb_data[28]_i_2_0 ;
  input \addr_dec_to_mb_data[28]_i_2_1 ;
  input \addr_dec_to_mb_data[27]_i_2_0 ;
  input \addr_dec_to_mb_data[27]_i_2_1 ;
  input \addr_dec_to_mb_data[26]_i_2_0 ;
  input \addr_dec_to_mb_data[26]_i_2_1 ;
  input \addr_dec_to_mb_data[25]_i_2_0 ;
  input \addr_dec_to_mb_data[25]_i_2_1 ;
  input \addr_dec_to_mb_data[24]_i_2_0 ;
  input \addr_dec_to_mb_data[24]_i_2_1 ;
  input \addr_dec_to_mb_data[21]_i_2_0 ;
  input \addr_dec_to_mb_data[21]_i_2_1 ;
  input \addr_dec_to_mb_data[20]_i_2_0 ;
  input \addr_dec_to_mb_data[20]_i_2_1 ;
  input \addr_dec_to_mb_data[5]_i_2_1 ;
  input \addr_dec_to_mb_data[5]_i_2_2 ;
  input \addr_dec_to_mb_data_reg[10]_0 ;
  input \addr_dec_to_mb_data_reg[11]_0 ;
  input \addr_dec_to_mb_data_reg[12]_1 ;
  input \addr_dec_to_mb_data[0]_i_6_2 ;
  input \addr_dec_to_mb_data[0]_i_6_3 ;
  input \addr_dec_to_mb_data[4]_i_3_1 ;
  input \addr_dec_to_mb_data[4]_i_3_2 ;
  input [11:0]\addr_dec_to_mb_data[30]_i_6_2 ;
  input \addr_dec_to_mb_data_reg[27] ;
  input \addr_dec_to_mb_data_reg[26] ;
  input \addr_dec_to_mb_data_reg[20] ;
  input \addr_dec_to_mb_data[4]_i_11_0 ;
  input \addr_dec_to_mb_data_reg[16]_1 ;
  input \addr_dec_to_mb_data_reg[17]_0 ;
  input \addr_dec_to_mb_data_reg[18]_0 ;
  input \addr_dec_to_mb_data_reg[19]_1 ;
  input \addr_dec_to_mb_data[0]_i_21_0 ;
  input [0:0]\addr_dec_to_mb_data[0]_i_21_1 ;
  input \addr_dec_to_mb_data[9]_i_4_0 ;
  input \addr_dec_to_mb_data_reg[13]_0 ;
  input \addr_dec_to_mb_data_reg[20]_0 ;
  input \addr_dec_to_mb_data[22]_i_3_0 ;
  input \addr_dec_to_mb_data_reg[24] ;
  input \addr_dec_to_mb_data_reg[25] ;
  input \addr_dec_to_mb_data_reg[26]_0 ;
  input \addr_dec_to_mb_data_reg[27]_0 ;
  input \addr_dec_to_mb_data[4]_i_3_3 ;
  input \addr_dec_to_mb_data[3]_i_10_0 ;
  input \addr_dec_to_mb_data[3]_i_10_1 ;
  input [1:0]\addr_dec_to_mb_data[2]_i_6_2 ;
  input [7:0]\addr_dec_to_mb_data[7]_i_15_0 ;
  input stop_gate_tracking_ack_reg;
  input \addr_dec_to_mb_data[4]_i_10_0 ;
  input \addr_dec_to_mb_data[2]_i_11_0 ;
  input \addr_dec_to_mb_data[8]_i_4_0 ;
  input \addr_dec_to_mb_data[8]_i_4_1 ;
  input \addr_dec_to_mb_data[9]_i_3_0 ;
  input \addr_dec_to_mb_data[9]_i_3_1 ;
  input \addr_dec_to_mb_data[10]_i_4_0 ;
  input \addr_dec_to_mb_data[10]_i_4_1 ;
  input \addr_dec_to_mb_data[11]_i_4_0 ;
  input \addr_dec_to_mb_data[11]_i_4_1 ;
  input \addr_dec_to_mb_data[12]_i_4_0 ;
  input \addr_dec_to_mb_data[12]_i_4_1 ;
  input \addr_dec_to_mb_data[13]_i_2_0 ;
  input \addr_dec_to_mb_data[13]_i_2_1 ;
  input \addr_dec_to_mb_data[16]_i_2_0 ;
  input \addr_dec_to_mb_data[16]_i_2_1 ;
  input \addr_dec_to_mb_data[17]_i_2_0 ;
  input \addr_dec_to_mb_data[17]_i_2_1 ;
  input \addr_dec_to_mb_data[18]_i_2_0 ;
  input \addr_dec_to_mb_data[18]_i_2_1 ;
  input \addr_dec_to_mb_data[19]_i_2_0 ;
  input \addr_dec_to_mb_data[19]_i_2_1 ;
  input \addr_dec_to_mb_data[8]_i_8_0 ;
  input ub_calDone;
  input \addr_dec_to_mb_data[3]_i_13_0 ;
  input \addr_dec_to_mb_data[2]_i_4_1 ;
  input [0:0]cplx_status;
  input cnt_clr;
  input lrdimm_cmp_en;
  input [0:0]cal_oe_dis_low;
  input [0:0]cal_oe_dis_upp;
  input \addr_dec_to_mb_data_reg[29] ;
  input \addr_dec_to_mb_data_reg[29]_0 ;
  input \addr_dec_to_mb_data_reg[28] ;
  input \addr_dec_to_mb_data_reg[25]_0 ;
  input \addr_dec_to_mb_data_reg[24]_0 ;
  input \addr_dec_to_mb_data_reg[21] ;
  input \addr_dec_to_mb_data_reg[21]_0 ;
  input \addr_dec_to_mb_data_reg[15]_1 ;
  input \addr_dec_to_mb_data_reg[30] ;
  input \addr_dec_to_mb_data_reg[23] ;
  input \addr_dec_to_mb_data_reg[22] ;
  input \SYNC[31].sync_reg_reg[1]_0 ;
  input [31:0]\SYNC[31].sync_reg_reg[0]_0 ;

  wire [0:0]E;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  wire [0:0]\SYNC[0].sync_reg_reg[1]_0 ;
  wire [0:0]\SYNC[0].sync_reg_reg[1]_1 ;
  wire [0:0]\SYNC[0].sync_reg_reg[1]_2 ;
  wire \SYNC[0].sync_reg_reg[1]_3 ;
  wire \SYNC[0].sync_reg_reg[1]_4 ;
  wire \SYNC[0].sync_reg_reg[1]_5 ;
  wire \SYNC[0].sync_reg_reg[1]_6 ;
  wire \SYNC[0].sync_reg_reg[1]_7 ;
  wire [10:0]\SYNC[0].sync_reg_reg[1]_8 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[10].sync_reg ;
  wire [0:0]\SYNC[10].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[11].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[12].sync_reg ;
  wire \SYNC[12].sync_reg_reg[1]_0 ;
  wire \SYNC[12].sync_reg_reg[1]_1 ;
  wire \SYNC[12].sync_reg_reg[1]_2 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[13].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[14].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[15].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[16].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[17].sync_reg ;
  wire [0:0]\SYNC[17].sync_reg_reg[1]_0 ;
  wire \SYNC[17].sync_reg_reg[1]_1 ;
  wire [0:0]\SYNC[17].sync_reg_reg[1]_2 ;
  wire \SYNC[17].sync_reg_reg[1]_3 ;
  wire \SYNC[17].sync_reg_reg[1]_4 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[18].sync_reg ;
  wire [0:0]\SYNC[18].sync_reg_reg[1]_0 ;
  wire [0:0]\SYNC[18].sync_reg_reg[1]_1 ;
  wire \SYNC[18].sync_reg_reg[1]_2 ;
  wire \SYNC[18].sync_reg_reg[1]_3 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[19].sync_reg ;
  wire [0:0]\SYNC[19].sync_reg_reg[1]_0 ;
  wire [0:0]\SYNC[19].sync_reg_reg[1]_1 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[1].sync_reg ;
  wire [0:0]\SYNC[1].sync_reg_reg[1]_0 ;
  wire [0:0]\SYNC[1].sync_reg_reg[1]_1 ;
  wire [7:0]\SYNC[1].sync_reg_reg[1]_2 ;
  wire \SYNC[1].sync_reg_reg[1]_3 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[20].sync_reg ;
  wire [0:0]\SYNC[20].sync_reg_reg[1]_0 ;
  wire [0:0]\SYNC[20].sync_reg_reg[1]_1 ;
  wire \SYNC[20].sync_reg_reg[1]_2 ;
  wire \SYNC[20].sync_reg_reg[1]_3 ;
  wire \SYNC[20].sync_reg_reg[1]_4 ;
  wire \SYNC[20].sync_reg_reg[1]_5 ;
  wire \SYNC[20].sync_reg_reg[1]_6 ;
  wire \SYNC[20].sync_reg_reg[1]_7 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[21].sync_reg ;
  wire \SYNC[21].sync_reg_reg[1]_0 ;
  wire [0:0]\SYNC[21].sync_reg_reg[1]_1 ;
  wire \SYNC[21].sync_reg_reg[1]_2 ;
  wire \SYNC[21].sync_reg_reg[1]_3 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[22].sync_reg ;
  wire \SYNC[22].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[23].sync_reg ;
  wire \SYNC[23].sync_reg_reg[1]_1 ;
  wire \SYNC[23].sync_reg_reg[1]_2 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[24].sync_reg ;
  wire \SYNC[24].sync_reg_reg[1]_0 ;
  wire \SYNC[24].sync_reg_reg[1]_1 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[25].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[26].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[27].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[28].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[29].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[2].sync_reg ;
  wire [0:0]\SYNC[2].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[30].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[31].sync_reg ;
  wire [31:0]\SYNC[31].sync_reg_reg[0]_0 ;
  wire \SYNC[31].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[3].sync_reg ;
  wire \SYNC[3].sync_reg_reg[1]_0 ;
  wire \SYNC[3].sync_reg_reg[1]_1 ;
  wire \SYNC[3].sync_reg_reg[1]_2 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[4].sync_reg ;
  wire \SYNC[4].sync_reg_reg[1]_0 ;
  wire \SYNC[4].sync_reg_reg[1]_1 ;
  wire \SYNC[4].sync_reg_reg[1]_2 ;
  wire \SYNC[4].sync_reg_reg[1]_3 ;
  wire [0:0]\SYNC[4].sync_reg_reg[1]_4 ;
  wire \SYNC[4].sync_reg_reg[1]_5 ;
  wire \SYNC[4].sync_reg_reg[1]_6 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[5].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[6].sync_reg ;
  wire \SYNC[6].sync_reg_reg[1]_0 ;
  wire \SYNC[6].sync_reg_reg[1]_1 ;
  wire \SYNC[6].sync_reg_reg[1]_2 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[7].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[8].sync_reg ;
  wire [0:0]\SYNC[8].sync_reg_reg[1]_0 ;
  wire [0:0]\SYNC[8].sync_reg_reg[1]_1 ;
  wire \SYNC[8].sync_reg_reg[1]_2 ;
  wire \SYNC[8].sync_reg_reg[1]_3 ;
  wire \SYNC[8].sync_reg_reg[1]_4 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[9].sync_reg ;
  wire [0:0]\SYNC[9].sync_reg_reg[1]_0 ;
  wire \SYNC[9].sync_reg_reg[1]_1 ;
  wire \SYNC[9].sync_reg_reg[1]_2 ;
  wire \SYNC[9].sync_reg_reg[1]_3 ;
  wire a_b_cmd_sel_start0;
  wire \addr_dec_to_mb_data[0]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_14_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_15_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_16_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_17_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_18_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_19_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_20_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_21_0 ;
  wire [0:0]\addr_dec_to_mb_data[0]_i_21_1 ;
  wire \addr_dec_to_mb_data[0]_i_21_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_22_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_23_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_28_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_29_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_31_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_32_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_34_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_36_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_37_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_38_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_39_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_6_0 ;
  wire \addr_dec_to_mb_data[0]_i_6_1 ;
  wire \addr_dec_to_mb_data[0]_i_6_2 ;
  wire \addr_dec_to_mb_data[0]_i_6_3 ;
  wire \addr_dec_to_mb_data[0]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[0]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[10]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[10]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[10]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[10]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[10]_i_4_0 ;
  wire \addr_dec_to_mb_data[10]_i_4_1 ;
  wire \addr_dec_to_mb_data[10]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[10]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[10]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[10]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[10]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[11]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[11]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[11]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[11]_i_2_n_0 ;
  wire [10:0]\addr_dec_to_mb_data[11]_i_3_0 ;
  wire \addr_dec_to_mb_data[11]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[11]_i_4_0 ;
  wire \addr_dec_to_mb_data[11]_i_4_1 ;
  wire \addr_dec_to_mb_data[11]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[11]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[11]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[11]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[11]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[12]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[12]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[12]_i_4_0 ;
  wire \addr_dec_to_mb_data[12]_i_4_1 ;
  wire \addr_dec_to_mb_data[12]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[12]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[12]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[12]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[13]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[13]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[13]_i_2_0 ;
  wire \addr_dec_to_mb_data[13]_i_2_1 ;
  wire \addr_dec_to_mb_data[13]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[13]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[13]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[13]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[13]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[13]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[13]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[13]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[14]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[14]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[14]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[14]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[15]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[15]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[15]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[15]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[15]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[15]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[16]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[16]_i_2_0 ;
  wire \addr_dec_to_mb_data[16]_i_2_1 ;
  wire \addr_dec_to_mb_data[16]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[16]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[16]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[16]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[16]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[16]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[16]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[17]_i_2_0 ;
  wire \addr_dec_to_mb_data[17]_i_2_1 ;
  wire \addr_dec_to_mb_data[17]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[17]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[17]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[17]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[17]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[17]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[18]_i_2_0 ;
  wire \addr_dec_to_mb_data[18]_i_2_1 ;
  wire \addr_dec_to_mb_data[18]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[18]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[18]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[18]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[18]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[18]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[19]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[19]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[19]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[19]_i_14_n_0 ;
  wire \addr_dec_to_mb_data[19]_i_16_n_0 ;
  wire \addr_dec_to_mb_data[19]_i_2_0 ;
  wire \addr_dec_to_mb_data[19]_i_2_1 ;
  wire \addr_dec_to_mb_data[19]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[19]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[19]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[19]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[19]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[19]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_14_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_15_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_16_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_17_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_18_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_22_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_23_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_24_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_2_0 ;
  wire \addr_dec_to_mb_data[1]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_3_0 ;
  wire \addr_dec_to_mb_data[1]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_5_0 ;
  wire \addr_dec_to_mb_data[1]_i_5_1 ;
  wire \addr_dec_to_mb_data[1]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[1]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[20]_i_2_0 ;
  wire \addr_dec_to_mb_data[20]_i_2_1 ;
  wire \addr_dec_to_mb_data[20]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[20]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[20]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[20]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[20]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[21]_i_2_0 ;
  wire \addr_dec_to_mb_data[21]_i_2_1 ;
  wire \addr_dec_to_mb_data[21]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[21]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[21]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[22]_i_3_0 ;
  wire \addr_dec_to_mb_data[22]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[22]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[22]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[22]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[22]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[23]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[23]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[23]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[23]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[24]_i_2_0 ;
  wire \addr_dec_to_mb_data[24]_i_2_1 ;
  wire \addr_dec_to_mb_data[24]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[24]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[24]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[24]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[25]_i_2_0 ;
  wire \addr_dec_to_mb_data[25]_i_2_1 ;
  wire \addr_dec_to_mb_data[25]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[25]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[25]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[25]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[26]_i_2_0 ;
  wire \addr_dec_to_mb_data[26]_i_2_1 ;
  wire \addr_dec_to_mb_data[26]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[26]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[26]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[26]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[26]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[27]_i_2_0 ;
  wire \addr_dec_to_mb_data[27]_i_2_1 ;
  wire \addr_dec_to_mb_data[27]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[27]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[27]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[27]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[27]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[27]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[28]_i_2_0 ;
  wire \addr_dec_to_mb_data[28]_i_2_1 ;
  wire \addr_dec_to_mb_data[28]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[28]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[28]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[28]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[29]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[29]_i_2_0 ;
  wire \addr_dec_to_mb_data[29]_i_2_1 ;
  wire \addr_dec_to_mb_data[29]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[29]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[29]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[29]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_11_0 ;
  wire \addr_dec_to_mb_data[2]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_14_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_15_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_16_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_17_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_18_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_19_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_20_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_21_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_22_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_23_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_24_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_25_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_26_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_27_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_28_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_29_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_32_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_33_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_34_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_35_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_36_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_4_0 ;
  wire \addr_dec_to_mb_data[2]_i_4_1 ;
  wire \addr_dec_to_mb_data[2]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_6_0 ;
  wire \addr_dec_to_mb_data[2]_i_6_1 ;
  wire [1:0]\addr_dec_to_mb_data[2]_i_6_2 ;
  wire \addr_dec_to_mb_data[2]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[2]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[30]_i_10_n_0 ;
  wire [10:0]\addr_dec_to_mb_data[30]_i_6_0 ;
  wire [12:0]\addr_dec_to_mb_data[30]_i_6_1 ;
  wire [11:0]\addr_dec_to_mb_data[30]_i_6_2 ;
  wire \addr_dec_to_mb_data[30]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[30]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[30]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[31]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[31]_i_12_n_0 ;
  wire [31:0]\addr_dec_to_mb_data[31]_i_3_0 ;
  wire \addr_dec_to_mb_data[31]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[31]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[31]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[31]_i_6_n_0 ;
  wire [53:0]\addr_dec_to_mb_data[31]_i_9_0 ;
  wire \addr_dec_to_mb_data[31]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_10_0 ;
  wire \addr_dec_to_mb_data[3]_i_10_1 ;
  wire \addr_dec_to_mb_data[3]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_13_0 ;
  wire \addr_dec_to_mb_data[3]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_18_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_19_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_20_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_21_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_22_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_23_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_24_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_25_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_28_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_29_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_30_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_31_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_32_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_33_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_36_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_37_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_38_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_39_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_3_0 ;
  wire \addr_dec_to_mb_data[3]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_40_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_41_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[3]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_10_0 ;
  wire \addr_dec_to_mb_data[4]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_11_0 ;
  wire \addr_dec_to_mb_data[4]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_14_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_15_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_16_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_18_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_20_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_21_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_22_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_23_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_24_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_25_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_26_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_28_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_29_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_30_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_31_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_34_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_35_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_38_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_39_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_3_0 ;
  wire \addr_dec_to_mb_data[4]_i_3_1 ;
  wire \addr_dec_to_mb_data[4]_i_3_2 ;
  wire \addr_dec_to_mb_data[4]_i_3_3 ;
  wire \addr_dec_to_mb_data[4]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_40_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_42_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_43_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[4]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_14_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_15_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_16_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_18_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_20_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_21_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_22_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_24_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_25_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_26_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_27_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_28_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_29_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_2_0 ;
  wire \addr_dec_to_mb_data[5]_i_2_1 ;
  wire \addr_dec_to_mb_data[5]_i_2_2 ;
  wire \addr_dec_to_mb_data[5]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_30_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_31_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_32_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_5_n_0 ;
  wire [4:0]\addr_dec_to_mb_data[5]_i_6_0 ;
  wire [4:0]\addr_dec_to_mb_data[5]_i_6_1 ;
  wire \addr_dec_to_mb_data[5]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[5]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_15_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_16_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_17_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_18_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_24_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_4_0 ;
  wire \addr_dec_to_mb_data[6]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[6]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_14_n_0 ;
  wire [7:0]\addr_dec_to_mb_data[7]_i_15_0 ;
  wire \addr_dec_to_mb_data[7]_i_15_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_17_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_18_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_19_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_20_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_21_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_24_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_4_n_0 ;
  wire [6:0]\addr_dec_to_mb_data[7]_i_5_0 ;
  wire \addr_dec_to_mb_data[7]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[7]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_10_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_13_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_15_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_16_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_17_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_19_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_21_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_4_0 ;
  wire \addr_dec_to_mb_data[8]_i_4_1 ;
  wire \addr_dec_to_mb_data[8]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_8_0 ;
  wire \addr_dec_to_mb_data[8]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[8]_i_9_n_0 ;
  wire \addr_dec_to_mb_data[9]_i_11_n_0 ;
  wire \addr_dec_to_mb_data[9]_i_12_n_0 ;
  wire \addr_dec_to_mb_data[9]_i_14_n_0 ;
  wire \addr_dec_to_mb_data[9]_i_2_n_0 ;
  wire \addr_dec_to_mb_data[9]_i_3_0 ;
  wire \addr_dec_to_mb_data[9]_i_3_1 ;
  wire \addr_dec_to_mb_data[9]_i_3_n_0 ;
  wire \addr_dec_to_mb_data[9]_i_4_0 ;
  wire \addr_dec_to_mb_data[9]_i_4_n_0 ;
  wire \addr_dec_to_mb_data[9]_i_5_n_0 ;
  wire \addr_dec_to_mb_data[9]_i_6_n_0 ;
  wire \addr_dec_to_mb_data[9]_i_7_n_0 ;
  wire \addr_dec_to_mb_data[9]_i_8_n_0 ;
  wire \addr_dec_to_mb_data[9]_i_9_n_0 ;
  wire \addr_dec_to_mb_data_reg[0] ;
  wire \addr_dec_to_mb_data_reg[0]_0 ;
  wire \addr_dec_to_mb_data_reg[0]_1 ;
  wire \addr_dec_to_mb_data_reg[10] ;
  wire \addr_dec_to_mb_data_reg[10]_0 ;
  wire \addr_dec_to_mb_data_reg[11] ;
  wire \addr_dec_to_mb_data_reg[11]_0 ;
  wire \addr_dec_to_mb_data_reg[12] ;
  wire \addr_dec_to_mb_data_reg[12]_0 ;
  wire \addr_dec_to_mb_data_reg[12]_1 ;
  wire \addr_dec_to_mb_data_reg[13] ;
  wire \addr_dec_to_mb_data_reg[13]_0 ;
  wire \addr_dec_to_mb_data_reg[14] ;
  wire \addr_dec_to_mb_data_reg[14]_0 ;
  wire \addr_dec_to_mb_data_reg[15] ;
  wire \addr_dec_to_mb_data_reg[15]_0 ;
  wire \addr_dec_to_mb_data_reg[15]_1 ;
  wire [9:0]\addr_dec_to_mb_data_reg[16] ;
  wire \addr_dec_to_mb_data_reg[16]_0 ;
  wire \addr_dec_to_mb_data_reg[16]_1 ;
  wire \addr_dec_to_mb_data_reg[17] ;
  wire \addr_dec_to_mb_data_reg[17]_0 ;
  wire \addr_dec_to_mb_data_reg[18] ;
  wire \addr_dec_to_mb_data_reg[18]_0 ;
  wire \addr_dec_to_mb_data_reg[19] ;
  wire \addr_dec_to_mb_data_reg[19]_0 ;
  wire \addr_dec_to_mb_data_reg[19]_1 ;
  wire \addr_dec_to_mb_data_reg[1] ;
  wire \addr_dec_to_mb_data_reg[20] ;
  wire \addr_dec_to_mb_data_reg[20]_0 ;
  wire \addr_dec_to_mb_data_reg[21] ;
  wire \addr_dec_to_mb_data_reg[21]_0 ;
  wire \addr_dec_to_mb_data_reg[22] ;
  wire \addr_dec_to_mb_data_reg[23] ;
  wire \addr_dec_to_mb_data_reg[24] ;
  wire \addr_dec_to_mb_data_reg[24]_0 ;
  wire \addr_dec_to_mb_data_reg[25] ;
  wire \addr_dec_to_mb_data_reg[25]_0 ;
  wire \addr_dec_to_mb_data_reg[26] ;
  wire \addr_dec_to_mb_data_reg[26]_0 ;
  wire \addr_dec_to_mb_data_reg[27] ;
  wire \addr_dec_to_mb_data_reg[27]_0 ;
  wire \addr_dec_to_mb_data_reg[28] ;
  wire \addr_dec_to_mb_data_reg[29] ;
  wire \addr_dec_to_mb_data_reg[29]_0 ;
  wire [0:0]\addr_dec_to_mb_data_reg[2] ;
  wire \addr_dec_to_mb_data_reg[30] ;
  wire \addr_dec_to_mb_data_reg[31] ;
  wire \addr_dec_to_mb_data_reg[31]_0 ;
  wire \addr_dec_to_mb_data_reg[3] ;
  wire \addr_dec_to_mb_data_reg[4] ;
  wire \addr_dec_to_mb_data_reg[4]_0 ;
  wire \addr_dec_to_mb_data_reg[5] ;
  wire \addr_dec_to_mb_data_reg[5]_0 ;
  wire \addr_dec_to_mb_data_reg[6] ;
  wire \addr_dec_to_mb_data_reg[7] ;
  wire \addr_dec_to_mb_data_reg[8] ;
  wire \addr_dec_to_mb_data_reg[9] ;
  wire calDone_i_2_n_0;
  wire calDone_i_3_n_0;
  wire calDone_i_4_n_0;
  wire calDone_i_5_n_0;
  wire \cal_ADR_A[31]_i_10_n_0 ;
  wire \cal_ADR_A[31]_i_11_n_0 ;
  wire \cal_ADR_A[31]_i_12_n_0 ;
  wire \cal_ADR_A[31]_i_13_n_0 ;
  wire \cal_ADR_A[31]_i_14_n_0 ;
  wire \cal_ADR_A[31]_i_15_n_0 ;
  wire \cal_ADR_A[31]_i_16_n_0 ;
  wire \cal_ADR_A[31]_i_17_n_0 ;
  wire \cal_ADR_A[31]_i_18_n_0 ;
  wire \cal_ADR_A[31]_i_19_n_0 ;
  wire \cal_ADR_A[31]_i_20_n_0 ;
  wire \cal_ADR_A[31]_i_21_n_0 ;
  wire \cal_ADR_A[31]_i_22_n_0 ;
  wire \cal_ADR_A[31]_i_23_n_0 ;
  wire \cal_ADR_A[31]_i_24_n_0 ;
  wire \cal_ADR_A[31]_i_25_n_0 ;
  wire \cal_ADR_A[31]_i_26_n_0 ;
  wire \cal_ADR_A[31]_i_2_n_0 ;
  wire \cal_ADR_A[31]_i_3_n_0 ;
  wire \cal_ADR_A[31]_i_4_n_0 ;
  wire \cal_ADR_A[31]_i_5_n_0 ;
  wire \cal_ADR_A[31]_i_6_n_0 ;
  wire \cal_ADR_A[31]_i_7_n_0 ;
  wire \cal_ADR_A[31]_i_8_n_0 ;
  wire \cal_ADR_A[31]_i_9_n_0 ;
  wire \cal_ADR_B[31]_i_10_n_0 ;
  wire \cal_ADR_B[31]_i_2_n_0 ;
  wire \cal_ADR_B[31]_i_3_n_0 ;
  wire \cal_ADR_B[31]_i_4_n_0 ;
  wire \cal_ADR_B[31]_i_5_n_0 ;
  wire \cal_ADR_B[31]_i_6_n_0 ;
  wire \cal_ADR_B[31]_i_7_n_0 ;
  wire \cal_ADR_B[31]_i_8_n_0 ;
  wire \cal_ADR_B[31]_i_9_n_0 ;
  wire \cal_CS_A[7]_i_10_n_0 ;
  wire \cal_CS_A[7]_i_11_n_0 ;
  wire \cal_CS_A[7]_i_12_n_0 ;
  wire \cal_CS_A[7]_i_13_n_0 ;
  wire \cal_CS_A[7]_i_14_n_0 ;
  wire \cal_CS_A[7]_i_15_n_0 ;
  wire \cal_CS_A[7]_i_16_n_0 ;
  wire \cal_CS_A[7]_i_17_n_0 ;
  wire \cal_CS_A[7]_i_18_n_0 ;
  wire \cal_CS_A[7]_i_19_n_0 ;
  wire \cal_CS_A[7]_i_20_n_0 ;
  wire \cal_CS_A[7]_i_2_n_0 ;
  wire \cal_CS_A[7]_i_3_n_0 ;
  wire \cal_CS_A[7]_i_4_n_0 ;
  wire \cal_CS_A[7]_i_5_n_0 ;
  wire \cal_CS_A[7]_i_6_n_0 ;
  wire \cal_CS_A[7]_i_7_n_0 ;
  wire \cal_CS_A[7]_i_8_n_0 ;
  wire \cal_CS_A[7]_i_9_n_0 ;
  wire \cal_CS_B[7]_i_10_n_0 ;
  wire \cal_CS_B[7]_i_11_n_0 ;
  wire \cal_CS_B[7]_i_12_n_0 ;
  wire \cal_CS_B[7]_i_13_n_0 ;
  wire \cal_CS_B[7]_i_14_n_0 ;
  wire \cal_CS_B[7]_i_15_n_0 ;
  wire \cal_CS_B[7]_i_16_n_0 ;
  wire \cal_CS_B[7]_i_2_n_0 ;
  wire \cal_CS_B[7]_i_3_n_0 ;
  wire \cal_CS_B[7]_i_4_n_0 ;
  wire \cal_CS_B[7]_i_5_n_0 ;
  wire \cal_CS_B[7]_i_6_n_0 ;
  wire \cal_CS_B[7]_i_7_n_0 ;
  wire \cal_CS_B[7]_i_8_n_0 ;
  wire \cal_CS_B[7]_i_9_n_0 ;
  wire \cal_DMOut_n_A[31]_i_2_n_0 ;
  wire \cal_DMOut_n_A[31]_i_3_n_0 ;
  wire \cal_DQOut_A[63]_i_2_n_0 ;
  wire \cal_DQOut_post[63]_i_2_n_0 ;
  wire \cal_DQOut_post_reg[31] ;
  wire \cal_DQOut_pre[63]_i_2_n_0 ;
  wire \cal_DQPat_A[63]_i_2_n_0 ;
  wire \cal_DQPat_A[63]_i_3_n_0 ;
  wire \cal_DQPat_A[63]_i_4_n_0 ;
  wire \cal_DQPat_B[63]_i_2_n_0 ;
  wire \cal_RST_CKE_ODT_PAR[31]_i_2_n_0 ;
  wire \cal_RST_CKE_ODT_PAR[31]_i_3_n_0 ;
  wire \cal_RST_CKE_ODT_PAR[31]_i_4_n_0 ;
  wire \cal_RST_CKE_ODT_PAR[31]_i_5_n_0 ;
  wire \cal_RST_CKE_ODT_PAR[31]_i_6_n_0 ;
  wire \cal_WE_A[7]_i_2_n_0 ;
  wire \cal_WE_A[7]_i_3_n_0 ;
  wire \cal_WE_A[7]_i_4_n_0 ;
  wire \cal_WE_A[7]_i_5_n_0 ;
  wire \cal_WE_B[7]_i_2_n_0 ;
  wire \cal_WE_B[7]_i_3_n_0 ;
  wire \cal_WE_B[7]_i_4_n_0 ;
  wire \cal_WE_B[7]_i_5_n_0 ;
  wire \cal_cmp_en[7]_i_2_n_0 ;
  wire \cal_cmp_en[7]_i_3_n_0 ;
  wire \cal_cmp_en[7]_i_4_n_0 ;
  wire \cal_cmp_en[7]_i_5_n_0 ;
  wire \cal_cs_pos[1]_i_2_n_0 ;
  wire \cal_cs_pos[1]_i_4_n_0 ;
  wire \cal_cs_pos[1]_i_5_n_0 ;
  wire \cal_cs_pos_reg[1] ;
  wire [0:0]cal_oe_dis_low;
  wire \cal_oe_dis_low[7]_i_2_n_0 ;
  wire \cal_oe_dis_low[7]_i_3_n_0 ;
  wire \cal_oe_dis_low[7]_i_4_n_0 ;
  wire [0:0]cal_oe_dis_upp;
  wire \cal_seq[2]_i_2_n_0 ;
  wire \cal_seq[2]_i_3_n_0 ;
  wire \cal_seq[2]_i_4_n_0 ;
  wire \cal_seq[2]_i_5_n_0 ;
  wire \cal_seq_a_a_dly[7]_i_2_n_0 ;
  wire \cal_seq_a_a_dly[7]_i_3_n_0 ;
  wire \cal_seq_a_b_dly[7]_i_2_n_0 ;
  wire \cal_seq_a_b_dly[7]_i_3_n_0 ;
  wire \cal_seq_b_a_dly[7]_i_2_n_0 ;
  wire \cal_seq_b_a_dly[7]_i_3_n_0 ;
  wire \cal_seq_b_a_dly[7]_i_4_n_0 ;
  wire [26:0]cal_timer_reg;
  wire \cal_timer_reg[30] ;
  wire [20:0]\cal_timer_reg[31] ;
  wire cal_timer_reg_22_sn_1;
  wire cal_timer_reg_23_sn_1;
  wire \clb2phy_wrcs0_low[31]_i_10_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_11_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_12_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_13_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_14_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_15_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_2_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_3_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_4_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_5_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_6_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_7_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_8_n_0 ;
  wire \clb2phy_wrcs0_low[31]_i_9_n_0 ;
  wire clear_gt_data_ready_flag;
  wire clear_gt_data_ready_flag_i_2_n_0;
  wire clear_gt_data_ready_flag_i_3_n_0;
  wire clear_gt_data_ready_flag_i_4_n_0;
  wire clear_gt_data_ready_flag_i_5_n_0;
  wire clear_gt_data_ready_flag_i_6_n_0;
  wire clear_gt_data_ready_flag_i_7_n_0;
  wire \cmp_byte[2]_i_2_n_0 ;
  wire cnt_clr;
  wire cnt_clr_access;
  wire cnt_clr_reg;
  wire \cplx_config[0]_i_2_n_0 ;
  wire \cplx_config[0]_i_3_n_0 ;
  wire \cplx_config[0]_i_4_n_0 ;
  wire \cplx_config[0]_i_5_n_0 ;
  wire \cplx_config[16]_i_3_n_0 ;
  wire \cplx_config[16]_i_4_n_0 ;
  wire \cplx_config[16]_i_5_n_0 ;
  wire \cplx_config[16]_i_6_n_0 ;
  wire \cplx_config[16]_i_7_n_0 ;
  wire \cplx_config[16]_i_8_n_0 ;
  wire \cplx_config[16]_i_9_n_0 ;
  wire [0:0]cplx_status;
  wire [8:0]douta;
  wire ena;
  wire gt_data_ready_flag;
  wire initDone;
  wire io_addr_strobe;
  wire [0:0]io_addr_strobe_reg;
  wire io_addr_strobe_reg_0;
  wire [1:0]io_write_data;
  wire \lowCL0[47]_i_3_n_0 ;
  wire \lowCL0[47]_i_5_n_0 ;
  wire lrdimm_cal_mode_i_2_n_0;
  wire lrdimm_cal_mode_i_3_n_0;
  wire lrdimm_cmp_clr;
  wire lrdimm_cmp_clr_i_2_n_0;
  wire lrdimm_cmp_en;
  wire lrdimm_cmp_en_i_2_n_0;
  wire lrdimm_cmp_en_i_3_n_0;
  wire [0:0]out;
  wire p_52_in;
  wire [7:0]phy2clb_rd_dq_bits;
  wire [7:0]rd_vref_value0_out;
  wire \rd_vref_value[53]_i_2_n_0 ;
  wire \rd_vref_value[53]_i_3_n_0 ;
  wire \rd_vref_value[53]_i_4_n_0 ;
  wire [19:0]riu2clb_valid;
  wire rst_r1_reg;
  wire [0:0]rst_r1_reg_0;
  wire [0:0]rst_r1_reg_1;
  wire stop_gate_tracking_ack_i_2_n_0;
  wire stop_gate_tracking_ack_i_3_n_0;
  wire stop_gate_tracking_ack_reg;
  wire \traffic_instr_nxt_instr_r1[5]_i_2_n_0 ;
  wire \traffic_instr_nxt_instr_r1[5]_i_3_n_0 ;
  wire ub_calDone;
  wire \xsdb_wr_data[8]_i_2_n_0 ;
  wire \xsdb_wr_data[8]_i_3_n_0 ;
  wire \xsdb_wr_data[8]_i_4_n_0 ;
  wire \xsdb_wr_data[8]_i_5_n_0 ;
  wire \xsdb_wr_data[8]_i_6_n_0 ;
  wire xsdb_wr_en_reg;

  assign \SYNC[23].sync_reg_reg[1]_0 [20] = \SYNC[23].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [19] = \SYNC[22].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [18] = \SYNC[21].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [17] = \SYNC[20].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [16] = \SYNC[18].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [15] = \SYNC[15].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [14] = \SYNC[14].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [13] = \SYNC[13].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [12] = \SYNC[12].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [11] = \SYNC[11].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [10] = \SYNC[10].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [9] = \SYNC[9].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [8] = \SYNC[8].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [7] = \SYNC[7].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [6] = \SYNC[6].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [5] = \SYNC[5].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [4] = \SYNC[4].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [3] = \SYNC[3].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [2] = \SYNC[2].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [1] = \SYNC[1].sync_reg [1];
  assign \SYNC[23].sync_reg_reg[1]_0 [0] = \SYNC[0].sync_reg [1];
  assign cal_timer_reg_22_sp_1 = cal_timer_reg_22_sn_1;
  assign cal_timer_reg_23_sp_1 = cal_timer_reg_23_sn_1;
  LUT4 #(
    .INIT(16'h1000)) 
    DDR_XSDB_BRAM_i_1
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[20].sync_reg [1]),
        .I3(\SYNC[23].sync_reg [1]),
        .O(ena));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [0]),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [10]),
        .Q(\SYNC[10].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[10].sync_reg [0]),
        .Q(\SYNC[10].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [11]),
        .Q(\SYNC[11].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[11].sync_reg [0]),
        .Q(\SYNC[11].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [12]),
        .Q(\SYNC[12].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[12].sync_reg [0]),
        .Q(\SYNC[12].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [13]),
        .Q(\SYNC[13].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[13].sync_reg [0]),
        .Q(\SYNC[13].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [14]),
        .Q(\SYNC[14].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[14].sync_reg [0]),
        .Q(\SYNC[14].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [15]),
        .Q(\SYNC[15].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[15].sync_reg [0]),
        .Q(\SYNC[15].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [16]),
        .Q(\SYNC[16].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[16].sync_reg [0]),
        .Q(\SYNC[16].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [17]),
        .Q(\SYNC[17].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[17].sync_reg [0]),
        .Q(\SYNC[17].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [18]),
        .Q(\SYNC[18].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[18].sync_reg [0]),
        .Q(\SYNC[18].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [19]),
        .Q(\SYNC[19].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg [0]),
        .Q(\SYNC[19].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [1]),
        .Q(\SYNC[1].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[1].sync_reg [0]),
        .Q(\SYNC[1].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[20].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [20]),
        .Q(\SYNC[20].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[20].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[20].sync_reg [0]),
        .Q(\SYNC[20].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[21].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [21]),
        .Q(\SYNC[21].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[21].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[21].sync_reg [0]),
        .Q(\SYNC[21].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[22].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [22]),
        .Q(\SYNC[22].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[22].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[22].sync_reg [0]),
        .Q(\SYNC[22].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[23].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [23]),
        .Q(\SYNC[23].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[23].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[23].sync_reg [0]),
        .Q(\SYNC[23].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[24].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [24]),
        .Q(\SYNC[24].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[24].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[24].sync_reg [0]),
        .Q(\SYNC[24].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[25].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [25]),
        .Q(\SYNC[25].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[25].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[25].sync_reg [0]),
        .Q(\SYNC[25].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[26].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [26]),
        .Q(\SYNC[26].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[26].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[26].sync_reg [0]),
        .Q(\SYNC[26].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[27].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [27]),
        .Q(\SYNC[27].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[27].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[27].sync_reg [0]),
        .Q(\SYNC[27].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[28].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [28]),
        .Q(\SYNC[28].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[28].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[28].sync_reg [0]),
        .Q(\SYNC[28].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[29].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [29]),
        .Q(\SYNC[29].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[29].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[29].sync_reg [0]),
        .Q(\SYNC[29].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [2]),
        .Q(\SYNC[2].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[2].sync_reg [0]),
        .Q(\SYNC[2].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[30].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [30]),
        .Q(\SYNC[30].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[30].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[30].sync_reg [0]),
        .Q(\SYNC[30].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[31].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [31]),
        .Q(\SYNC[31].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[31].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg [0]),
        .Q(\SYNC[31].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [3]),
        .Q(\SYNC[3].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[3].sync_reg [0]),
        .Q(\SYNC[3].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [4]),
        .Q(\SYNC[4].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[4].sync_reg [0]),
        .Q(\SYNC[4].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [5]),
        .Q(\SYNC[5].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[5].sync_reg [0]),
        .Q(\SYNC[5].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [6]),
        .Q(\SYNC[6].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[6].sync_reg [0]),
        .Q(\SYNC[6].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [7]),
        .Q(\SYNC[7].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[7].sync_reg [0]),
        .Q(\SYNC[7].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [8]),
        .Q(\SYNC[8].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[8].sync_reg [0]),
        .Q(\SYNC[8].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[0] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [9]),
        .Q(\SYNC[9].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[1] 
       (.C(\SYNC[31].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[9].sync_reg [0]),
        .Q(\SYNC[9].sync_reg [1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000AAAAEEFE)) 
    \addr_dec_to_mb_data[0]_i_1 
       (.I0(\addr_dec_to_mb_data[0]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[0]_i_3_n_0 ),
        .I2(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .I3(\addr_dec_to_mb_data[0]_i_4_n_0 ),
        .I4(\addr_dec_to_mb_data[0]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[0]_i_6_n_0 ),
        .O(\cal_timer_reg[31] [0]));
  LUT5 #(
    .INIT(32'h2A280808)) 
    \addr_dec_to_mb_data[0]_i_10 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .O(\addr_dec_to_mb_data[0]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'h00010000)) 
    \addr_dec_to_mb_data[0]_i_13 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[0]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h4000404440004000)) 
    \addr_dec_to_mb_data[0]_i_14 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\SYNC[19].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[0]_i_6_0 ),
        .I3(\SYNC[4].sync_reg [1]),
        .I4(\SYNC[5].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[7]_i_5_0 [0]),
        .O(\addr_dec_to_mb_data[0]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'hBBABBBBB)) 
    \addr_dec_to_mb_data[0]_i_15 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\addr_dec_to_mb_data_reg[0]_1 ),
        .I2(\addr_dec_to_mb_data[0]_i_17_n_0 ),
        .I3(\addr_dec_to_mb_data[0]_i_28_n_0 ),
        .I4(\addr_dec_to_mb_data[11]_i_3_0 [0]),
        .O(\addr_dec_to_mb_data[0]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h47000000FFFFFFFF)) 
    \addr_dec_to_mb_data[0]_i_16 
       (.I0(\addr_dec_to_mb_data[7]_i_15_0 [0]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_3_0 [0]),
        .I3(\addr_dec_to_mb_data[0]_i_29_n_0 ),
        .I4(\addr_dec_to_mb_data[8]_i_15_n_0 ),
        .I5(\SYNC[20].sync_reg [1]),
        .O(\addr_dec_to_mb_data[0]_i_16_n_0 ));
  LUT4 #(
    .INIT(16'h035F)) 
    \addr_dec_to_mb_data[0]_i_17 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\SYNC[12].sync_reg [1]),
        .O(\addr_dec_to_mb_data[0]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF80888000)) 
    \addr_dec_to_mb_data[0]_i_18 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[0]_i_17_n_0 ),
        .I2(\addr_dec_to_mb_data[0]_i_6_1 ),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[0]_i_31_n_0 ),
        .I5(\addr_dec_to_mb_data[0]_i_32_n_0 ),
        .O(\addr_dec_to_mb_data[0]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hB8BB8888B8888888)) 
    \addr_dec_to_mb_data[0]_i_19 
       (.I0(\addr_dec_to_mb_data[0]_i_6_2 ),
        .I1(\SYNC[12].sync_reg_reg[1]_1 ),
        .I2(douta[0]),
        .I3(\SYNC[20].sync_reg [1]),
        .I4(\SYNC[23].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[0]_i_34_n_0 ),
        .O(\addr_dec_to_mb_data[0]_i_19_n_0 ));
  LUT5 #(
    .INIT(32'hAAFFC0FF)) 
    \addr_dec_to_mb_data[0]_i_2 
       (.I0(\addr_dec_to_mb_data[0]_i_7_n_0 ),
        .I1(\addr_dec_to_mb_data[0]_i_8_n_0 ),
        .I2(\addr_dec_to_mb_data_reg[0] ),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[0]_i_10_n_0 ),
        .O(\addr_dec_to_mb_data[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF1DFF0000)) 
    \addr_dec_to_mb_data[0]_i_20 
       (.I0(\addr_dec_to_mb_data[0]_i_6_3 ),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[0]_i_6_1 ),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[0]_i_36_n_0 ),
        .I5(\addr_dec_to_mb_data[0]_i_37_n_0 ),
        .O(\addr_dec_to_mb_data[0]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAFEAE)) 
    \addr_dec_to_mb_data[0]_i_21 
       (.I0(\addr_dec_to_mb_data[0]_i_38_n_0 ),
        .I1(\addr_dec_to_mb_data[7]_i_5_0 [0]),
        .I2(\SYNC[4].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[0]_i_6_0 ),
        .I4(\addr_dec_to_mb_data[0]_i_39_n_0 ),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\addr_dec_to_mb_data[0]_i_21_n_0 ));
  LUT5 #(
    .INIT(32'h55450000)) 
    \addr_dec_to_mb_data[0]_i_22 
       (.I0(\addr_dec_to_mb_data[2]_i_13_n_0 ),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[18].sync_reg [1]),
        .O(\addr_dec_to_mb_data[0]_i_22_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFD5)) 
    \addr_dec_to_mb_data[0]_i_23 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\SYNC[20].sync_reg [1]),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\SYNC[19].sync_reg [1]),
        .O(\addr_dec_to_mb_data[0]_i_23_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \addr_dec_to_mb_data[0]_i_28 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\SYNC[10].sync_reg [1]),
        .O(\addr_dec_to_mb_data[0]_i_28_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \addr_dec_to_mb_data[0]_i_29 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .O(\addr_dec_to_mb_data[0]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF4444F444)) 
    \addr_dec_to_mb_data[0]_i_3 
       (.I0(\addr_dec_to_mb_data_reg[0]_0 ),
        .I1(\SYNC[18].sync_reg_reg[1]_3 ),
        .I2(\addr_dec_to_mb_data_reg[0]_1 ),
        .I3(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .I4(\addr_dec_to_mb_data[0]_i_13_n_0 ),
        .I5(\addr_dec_to_mb_data[0]_i_14_n_0 ),
        .O(\addr_dec_to_mb_data[0]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \addr_dec_to_mb_data[0]_i_31 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(cplx_status),
        .O(\addr_dec_to_mb_data[0]_i_31_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \addr_dec_to_mb_data[0]_i_32 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[11].sync_reg [1]),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .O(\addr_dec_to_mb_data[0]_i_32_n_0 ));
  LUT5 #(
    .INIT(32'h888B8888)) 
    \addr_dec_to_mb_data[0]_i_34 
       (.I0(ub_calDone),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[10].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[11]_i_3_0 [0]),
        .O(\addr_dec_to_mb_data[0]_i_34_n_0 ));
  LUT6 #(
    .INIT(64'hBFFAFFFFBFFFFFFF)) 
    \addr_dec_to_mb_data[0]_i_36 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[4].sync_reg [1]),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\SYNC[10].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[2]_i_6_2 [0]),
        .O(\addr_dec_to_mb_data[0]_i_36_n_0 ));
  LUT6 #(
    .INIT(64'h5555FFF5DDDDDDDD)) 
    \addr_dec_to_mb_data[0]_i_37 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\SYNC[12].sync_reg_reg[1]_1 ),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .I5(\SYNC[9].sync_reg [1]),
        .O(\addr_dec_to_mb_data[0]_i_37_n_0 ));
  LUT6 #(
    .INIT(64'h4444F44444440444)) 
    \addr_dec_to_mb_data[0]_i_38 
       (.I0(\addr_dec_to_mb_data[0]_i_21_0 ),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\cal_CS_A[7]_i_14_n_0 ),
        .I3(\SYNC[17].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[0]_i_21_1 ),
        .O(\addr_dec_to_mb_data[0]_i_38_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAABAFFFFFFFF)) 
    \addr_dec_to_mb_data[0]_i_39 
       (.I0(\addr_dec_to_mb_data[2]_i_13_n_0 ),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[18].sync_reg [1]),
        .I5(\SYNC[19].sync_reg [1]),
        .O(\addr_dec_to_mb_data[0]_i_39_n_0 ));
  LUT6 #(
    .INIT(64'h8AAA88888AAAAAAA)) 
    \addr_dec_to_mb_data[0]_i_4 
       (.I0(\addr_dec_to_mb_data[0]_i_15_n_0 ),
        .I1(\addr_dec_to_mb_data[0]_i_16_n_0 ),
        .I2(douta[0]),
        .I3(\addr_dec_to_mb_data[0]_i_17_n_0 ),
        .I4(\SYNC[23].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[0]_i_18_n_0 ),
        .O(\addr_dec_to_mb_data[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0FA80000)) 
    \addr_dec_to_mb_data[0]_i_5 
       (.I0(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I1(\SYNC[3].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[0]_i_8_n_0 ),
        .O(\addr_dec_to_mb_data[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h004F004F0000004F)) 
    \addr_dec_to_mb_data[0]_i_6 
       (.I0(\addr_dec_to_mb_data[0]_i_19_n_0 ),
        .I1(\addr_dec_to_mb_data[0]_i_20_n_0 ),
        .I2(\addr_dec_to_mb_data[4]_i_25_n_0 ),
        .I3(\addr_dec_to_mb_data[0]_i_21_n_0 ),
        .I4(\addr_dec_to_mb_data[0]_i_22_n_0 ),
        .I5(\addr_dec_to_mb_data_reg[0]_0 ),
        .O(\addr_dec_to_mb_data[0]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \addr_dec_to_mb_data[0]_i_7 
       (.I0(phy2clb_rd_dq_bits[0]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(riu2clb_valid[0]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(cal_timer_reg[0]),
        .O(\addr_dec_to_mb_data[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h05455545FFFFFFFF)) 
    \addr_dec_to_mb_data[0]_i_8 
       (.I0(\addr_dec_to_mb_data[0]_i_23_n_0 ),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[20].sync_reg [1]),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .O(\addr_dec_to_mb_data[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF10000)) 
    \addr_dec_to_mb_data[10]_i_1 
       (.I0(\addr_dec_to_mb_data[10]_i_2_n_0 ),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[10]_i_3_n_0 ),
        .I3(\addr_dec_to_mb_data[10]_i_4_n_0 ),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[10]_i_5_n_0 ),
        .O(\cal_timer_reg[31] [10]));
  LUT4 #(
    .INIT(16'hA808)) 
    \addr_dec_to_mb_data[10]_i_10 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(cal_timer_reg[10]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(riu2clb_valid[10]),
        .O(\addr_dec_to_mb_data[10]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h2220222222222222)) 
    \addr_dec_to_mb_data[10]_i_12 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_3_0 [10]),
        .O(\addr_dec_to_mb_data[10]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h55FD000055FD55FD)) 
    \addr_dec_to_mb_data[10]_i_2 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\addr_dec_to_mb_data[10]_i_6_n_0 ),
        .I2(\addr_dec_to_mb_data[13]_i_9_n_0 ),
        .I3(\addr_dec_to_mb_data[10]_i_7_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[10]_0 ),
        .I5(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .O(\addr_dec_to_mb_data[10]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFB800)) 
    \addr_dec_to_mb_data[10]_i_3 
       (.I0(\addr_dec_to_mb_data[31]_i_9_0 [36]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_9_0 [9]),
        .I3(\SYNC[9].sync_reg_reg[1]_2 ),
        .I4(\addr_dec_to_mb_data[10]_i_9_n_0 ),
        .O(\addr_dec_to_mb_data[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000020002020202)) 
    \addr_dec_to_mb_data[10]_i_4 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_3_0 [10]),
        .I4(\addr_dec_to_mb_data[19]_i_7_n_0 ),
        .I5(\addr_dec_to_mb_data[10]_i_6_n_0 ),
        .O(\addr_dec_to_mb_data[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h20FF202000000000)) 
    \addr_dec_to_mb_data[10]_i_5 
       (.I0(\addr_dec_to_mb_data[31]_i_5_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[10]_i_10_n_0 ),
        .I3(\addr_dec_to_mb_data_reg[10] ),
        .I4(\SYNC[4].sync_reg_reg[1]_5 ),
        .I5(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .O(\addr_dec_to_mb_data[10]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h35FFFFFF)) 
    \addr_dec_to_mb_data[10]_i_6 
       (.I0(\addr_dec_to_mb_data[10]_i_4_0 ),
        .I1(\addr_dec_to_mb_data[10]_i_4_1 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[10]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \addr_dec_to_mb_data[10]_i_7 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[10]_i_12_n_0 ),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .O(\addr_dec_to_mb_data[10]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h4044555540404040)) 
    \addr_dec_to_mb_data[10]_i_9 
       (.I0(\addr_dec_to_mb_data[5]_i_13_n_0 ),
        .I1(\addr_dec_to_mb_data[11]_i_3_0 [9]),
        .I2(\addr_dec_to_mb_data[11]_i_12_n_0 ),
        .I3(\addr_dec_to_mb_data[11]_i_13_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[10]_0 ),
        .I5(\addr_dec_to_mb_data[13]_i_10_n_0 ),
        .O(\addr_dec_to_mb_data[10]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF10000)) 
    \addr_dec_to_mb_data[11]_i_1 
       (.I0(\addr_dec_to_mb_data[11]_i_2_n_0 ),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[11]_i_3_n_0 ),
        .I3(\addr_dec_to_mb_data[11]_i_4_n_0 ),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[11]_i_5_n_0 ),
        .O(\cal_timer_reg[31] [11]));
  LUT6 #(
    .INIT(64'h2220222222222222)) 
    \addr_dec_to_mb_data[11]_i_11 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_3_0 [11]),
        .O(\addr_dec_to_mb_data[11]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0000001500000000)) 
    \addr_dec_to_mb_data[11]_i_12 
       (.I0(\SYNC[12].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\SYNC[10].sync_reg [1]),
        .I5(\SYNC[23].sync_reg [1]),
        .O(\addr_dec_to_mb_data[11]_i_12_n_0 ));
  LUT4 #(
    .INIT(16'hFBBB)) 
    \addr_dec_to_mb_data[11]_i_13 
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\SYNC[22].sync_reg [1]),
        .I3(\SYNC[12].sync_reg [1]),
        .O(\addr_dec_to_mb_data[11]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h55FD000055FD55FD)) 
    \addr_dec_to_mb_data[11]_i_2 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\addr_dec_to_mb_data[11]_i_6_n_0 ),
        .I2(\addr_dec_to_mb_data[13]_i_9_n_0 ),
        .I3(\addr_dec_to_mb_data[11]_i_7_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[11]_0 ),
        .I5(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .O(\addr_dec_to_mb_data[11]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFB800)) 
    \addr_dec_to_mb_data[11]_i_3 
       (.I0(\addr_dec_to_mb_data[31]_i_9_0 [37]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_9_0 [10]),
        .I3(\SYNC[9].sync_reg_reg[1]_2 ),
        .I4(\addr_dec_to_mb_data[11]_i_9_n_0 ),
        .O(\addr_dec_to_mb_data[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000020002020202)) 
    \addr_dec_to_mb_data[11]_i_4 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_3_0 [11]),
        .I4(\addr_dec_to_mb_data[19]_i_7_n_0 ),
        .I5(\addr_dec_to_mb_data[11]_i_6_n_0 ),
        .O(\addr_dec_to_mb_data[11]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF454045404540)) 
    \addr_dec_to_mb_data[11]_i_5 
       (.I0(\addr_dec_to_mb_data[19]_i_16_n_0 ),
        .I1(riu2clb_valid[11]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(cal_timer_reg[11]),
        .I4(\addr_dec_to_mb_data_reg[11] ),
        .I5(\addr_dec_to_mb_data[19]_i_14_n_0 ),
        .O(\addr_dec_to_mb_data[11]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h35FFFFFF)) 
    \addr_dec_to_mb_data[11]_i_6 
       (.I0(\addr_dec_to_mb_data[11]_i_4_0 ),
        .I1(\addr_dec_to_mb_data[11]_i_4_1 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[11]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \addr_dec_to_mb_data[11]_i_7 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[11]_i_11_n_0 ),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .O(\addr_dec_to_mb_data[11]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h4044555540404040)) 
    \addr_dec_to_mb_data[11]_i_9 
       (.I0(\addr_dec_to_mb_data[5]_i_13_n_0 ),
        .I1(\addr_dec_to_mb_data[11]_i_3_0 [10]),
        .I2(\addr_dec_to_mb_data[11]_i_12_n_0 ),
        .I3(\addr_dec_to_mb_data[11]_i_13_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[11]_0 ),
        .I5(\addr_dec_to_mb_data[13]_i_10_n_0 ),
        .O(\addr_dec_to_mb_data[11]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF10000)) 
    \addr_dec_to_mb_data[12]_i_1 
       (.I0(\addr_dec_to_mb_data[12]_i_2_n_0 ),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\addr_dec_to_mb_data_reg[12] ),
        .I3(\addr_dec_to_mb_data[12]_i_4_n_0 ),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[12]_i_5_n_0 ),
        .O(\cal_timer_reg[31] [12]));
  LUT6 #(
    .INIT(64'h2220222222222222)) 
    \addr_dec_to_mb_data[12]_i_10 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_3_0 [12]),
        .O(\addr_dec_to_mb_data[12]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h55FD000055FD55FD)) 
    \addr_dec_to_mb_data[12]_i_2 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\addr_dec_to_mb_data[12]_i_6_n_0 ),
        .I2(\addr_dec_to_mb_data[13]_i_9_n_0 ),
        .I3(\addr_dec_to_mb_data[12]_i_7_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[12]_1 ),
        .I5(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .O(\addr_dec_to_mb_data[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000020002020202)) 
    \addr_dec_to_mb_data[12]_i_4 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_3_0 [12]),
        .I4(\addr_dec_to_mb_data[19]_i_7_n_0 ),
        .I5(\addr_dec_to_mb_data[12]_i_6_n_0 ),
        .O(\addr_dec_to_mb_data[12]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4540FFFF45404540)) 
    \addr_dec_to_mb_data[12]_i_5 
       (.I0(\addr_dec_to_mb_data[19]_i_16_n_0 ),
        .I1(riu2clb_valid[12]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(cal_timer_reg[12]),
        .I4(\addr_dec_to_mb_data_reg[12]_0 ),
        .I5(\addr_dec_to_mb_data[19]_i_14_n_0 ),
        .O(\addr_dec_to_mb_data[12]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h35FFFFFF)) 
    \addr_dec_to_mb_data[12]_i_6 
       (.I0(\addr_dec_to_mb_data[12]_i_4_0 ),
        .I1(\addr_dec_to_mb_data[12]_i_4_1 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[12]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h0100)) 
    \addr_dec_to_mb_data[12]_i_7 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[11].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[12]_i_10_n_0 ),
        .I3(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[12]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF55F70000)) 
    \addr_dec_to_mb_data[13]_i_1 
       (.I0(\addr_dec_to_mb_data[13]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[13]_i_3_n_0 ),
        .I2(\addr_dec_to_mb_data[13]_i_4_n_0 ),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[13]_i_5_n_0 ),
        .O(\cal_timer_reg[31] [13]));
  LUT6 #(
    .INIT(64'h5555404540454045)) 
    \addr_dec_to_mb_data[13]_i_10 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\SYNC[22].sync_reg [1]),
        .I5(\SYNC[12].sync_reg [1]),
        .O(\addr_dec_to_mb_data[13]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h2220222222222222)) 
    \addr_dec_to_mb_data[13]_i_13 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_3_0 [13]),
        .O(\addr_dec_to_mb_data[13]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F777F7F7)) 
    \addr_dec_to_mb_data[13]_i_2 
       (.I0(\SYNC[22].sync_reg_reg[1]_0 ),
        .I1(lrdimm_cmp_en_i_3_n_0),
        .I2(\addr_dec_to_mb_data[13]_i_6_n_0 ),
        .I3(\addr_dec_to_mb_data[19]_i_7_n_0 ),
        .I4(\addr_dec_to_mb_data[31]_i_3_0 [13]),
        .I5(\addr_dec_to_mb_data[13]_i_7_n_0 ),
        .O(\addr_dec_to_mb_data[13]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFF54FFFF)) 
    \addr_dec_to_mb_data[13]_i_3 
       (.I0(\addr_dec_to_mb_data[13]_i_8_n_0 ),
        .I1(\addr_dec_to_mb_data[13]_i_9_n_0 ),
        .I2(\addr_dec_to_mb_data[13]_i_6_n_0 ),
        .I3(\SYNC[23].sync_reg [1]),
        .I4(\SYNC[20].sync_reg [1]),
        .O(\addr_dec_to_mb_data[13]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h0F02)) 
    \addr_dec_to_mb_data[13]_i_4 
       (.I0(\addr_dec_to_mb_data[13]_i_10_n_0 ),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\addr_dec_to_mb_data_reg[13]_0 ),
        .I3(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .O(\addr_dec_to_mb_data[13]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4540FFFF45404540)) 
    \addr_dec_to_mb_data[13]_i_5 
       (.I0(\addr_dec_to_mb_data[19]_i_16_n_0 ),
        .I1(riu2clb_valid[13]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(cal_timer_reg[13]),
        .I4(\addr_dec_to_mb_data_reg[13] ),
        .I5(\addr_dec_to_mb_data[19]_i_14_n_0 ),
        .O(\addr_dec_to_mb_data[13]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h35FFFFFF)) 
    \addr_dec_to_mb_data[13]_i_6 
       (.I0(\addr_dec_to_mb_data[13]_i_2_0 ),
        .I1(\addr_dec_to_mb_data[13]_i_2_1 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[13]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'hA808)) 
    \addr_dec_to_mb_data[13]_i_7 
       (.I0(\SYNC[9].sync_reg_reg[1]_2 ),
        .I1(\addr_dec_to_mb_data[31]_i_9_0 [11]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [38]),
        .O(\addr_dec_to_mb_data[13]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h0100)) 
    \addr_dec_to_mb_data[13]_i_8 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[11].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[13]_i_13_n_0 ),
        .I3(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[13]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'hEAAA)) 
    \addr_dec_to_mb_data[13]_i_9 
       (.I0(\SYNC[12].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\SYNC[6].sync_reg [1]),
        .O(\addr_dec_to_mb_data[13]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0F0FDF0FFF0FD)) 
    \addr_dec_to_mb_data[14]_i_1 
       (.I0(\addr_dec_to_mb_data_reg[14] ),
        .I1(\addr_dec_to_mb_data[14]_i_3_n_0 ),
        .I2(\addr_dec_to_mb_data_reg[14]_0 ),
        .I3(\addr_dec_to_mb_data[15]_i_6_n_0 ),
        .I4(\addr_dec_to_mb_data[31]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[14]_i_5_n_0 ),
        .O(\cal_timer_reg[31] [14]));
  LUT6 #(
    .INIT(64'h8880AAAA88808880)) 
    \addr_dec_to_mb_data[14]_i_3 
       (.I0(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[14]_i_7_n_0 ),
        .I2(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I3(\addr_dec_to_mb_data[19]_i_13_n_0 ),
        .I4(\addr_dec_to_mb_data[14]_i_8_n_0 ),
        .I5(lrdimm_cmp_en_i_3_n_0),
        .O(\addr_dec_to_mb_data[14]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hBBBFFFBF)) 
    \addr_dec_to_mb_data[14]_i_5 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(cal_timer_reg[14]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(riu2clb_valid[14]),
        .O(\addr_dec_to_mb_data[14]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h44F444F4FFFF44F4)) 
    \addr_dec_to_mb_data[14]_i_7 
       (.I0(\SYNC[21].sync_reg_reg[1]_2 ),
        .I1(\addr_dec_to_mb_data[30]_i_6_1 [8]),
        .I2(\addr_dec_to_mb_data[30]_i_6_2 [8]),
        .I3(\SYNC[21].sync_reg_reg[1]_3 ),
        .I4(\addr_dec_to_mb_data[30]_i_6_0 [7]),
        .I5(\SYNC[12].sync_reg_reg[1]_0 ),
        .O(\addr_dec_to_mb_data[14]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'hDFFF)) 
    \addr_dec_to_mb_data[14]_i_8 
       (.I0(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I1(\SYNC[11].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_3_0 [14]),
        .I3(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[14]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAABBBBFFAF)) 
    \addr_dec_to_mb_data[15]_i_1 
       (.I0(\addr_dec_to_mb_data_reg[15] ),
        .I1(\addr_dec_to_mb_data[15]_i_3_n_0 ),
        .I2(\addr_dec_to_mb_data_reg[15]_0 ),
        .I3(\addr_dec_to_mb_data[15]_i_5_n_0 ),
        .I4(\addr_dec_to_mb_data[31]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[15]_i_6_n_0 ),
        .O(\cal_timer_reg[31] [15]));
  LUT4 #(
    .INIT(16'hDFFF)) 
    \addr_dec_to_mb_data[15]_i_10 
       (.I0(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I1(\SYNC[11].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_3_0 [15]),
        .I3(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[15]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h00008808AAAAAAAA)) 
    \addr_dec_to_mb_data[15]_i_11 
       (.I0(\SYNC[22].sync_reg_reg[1]_0 ),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\cal_ADR_A[31]_i_16_n_0 ),
        .I3(\addr_dec_to_mb_data[15]_i_13_n_0 ),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .O(\addr_dec_to_mb_data[15]_i_11_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \addr_dec_to_mb_data[15]_i_13 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[15]_i_13_n_0 ));
  LUT5 #(
    .INIT(32'hBBBFFFBF)) 
    \addr_dec_to_mb_data[15]_i_3 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(cal_timer_reg[15]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(riu2clb_valid[15]),
        .O(\addr_dec_to_mb_data[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h3232FF3200000000)) 
    \addr_dec_to_mb_data[15]_i_5 
       (.I0(\addr_dec_to_mb_data[19]_i_13_n_0 ),
        .I1(\addr_dec_to_mb_data_reg[15]_1 ),
        .I2(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I3(lrdimm_cmp_en_i_3_n_0),
        .I4(\addr_dec_to_mb_data[15]_i_10_n_0 ),
        .I5(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .O(\addr_dec_to_mb_data[15]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \addr_dec_to_mb_data[15]_i_6 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[15]_i_11_n_0 ),
        .O(\addr_dec_to_mb_data[15]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hBBFBBBBBBBBBBBFB)) 
    \addr_dec_to_mb_data[15]_i_7 
       (.I0(\addr_dec_to_mb_data[15]_i_11_n_0 ),
        .I1(\SYNC[9].sync_reg_reg[1]_2 ),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\SYNC[17].sync_reg_reg[1]_4 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF5700)) 
    \addr_dec_to_mb_data[16]_i_1 
       (.I0(\addr_dec_to_mb_data[16]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[16]_i_3_n_0 ),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I4(\addr_dec_to_mb_data[16]_i_4_n_0 ),
        .I5(\addr_dec_to_mb_data[16]_i_5_n_0 ),
        .O(\cal_timer_reg[31] [16]));
  LUT2 #(
    .INIT(4'h2)) 
    \addr_dec_to_mb_data[16]_i_11 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .O(\addr_dec_to_mb_data[16]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h8088AAAAAAAAAAAA)) 
    \addr_dec_to_mb_data[16]_i_2 
       (.I0(\addr_dec_to_mb_data[16]_i_6_n_0 ),
        .I1(\addr_dec_to_mb_data[16]_i_7_n_0 ),
        .I2(\addr_dec_to_mb_data[19]_i_7_n_0 ),
        .I3(\addr_dec_to_mb_data[31]_i_3_0 [16]),
        .I4(\SYNC[22].sync_reg_reg[1]_0 ),
        .I5(lrdimm_cmp_en_i_3_n_0),
        .O(\addr_dec_to_mb_data[16]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0E0E00000E0E000E)) 
    \addr_dec_to_mb_data[16]_i_3 
       (.I0(\addr_dec_to_mb_data[16]_i_7_n_0 ),
        .I1(\addr_dec_to_mb_data[19]_i_10_n_0 ),
        .I2(\addr_dec_to_mb_data[16]_i_8_n_0 ),
        .I3(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[16]_1 ),
        .I5(\addr_dec_to_mb_data[19]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[16]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000A280AAAAA280)) 
    \addr_dec_to_mb_data[16]_i_4 
       (.I0(\addr_dec_to_mb_data[19]_i_14_n_0 ),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data_reg[16] [9]),
        .I3(\addr_dec_to_mb_data_reg[16] [4]),
        .I4(\SYNC[5].sync_reg [1]),
        .I5(\addr_dec_to_mb_data_reg[16]_0 ),
        .O(\addr_dec_to_mb_data[16]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h8880008000000000)) 
    \addr_dec_to_mb_data[16]_i_5 
       (.I0(\addr_dec_to_mb_data[31]_i_5_n_0 ),
        .I1(\addr_dec_to_mb_data[16]_i_11_n_0 ),
        .I2(cal_timer_reg[16]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(riu2clb_valid[16]),
        .I5(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .O(\addr_dec_to_mb_data[16]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h57F7)) 
    \addr_dec_to_mb_data[16]_i_6 
       (.I0(\SYNC[9].sync_reg_reg[1]_2 ),
        .I1(\addr_dec_to_mb_data[31]_i_9_0 [12]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [39]),
        .O(\addr_dec_to_mb_data[16]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h35FFFFFF)) 
    \addr_dec_to_mb_data[16]_i_7 
       (.I0(\addr_dec_to_mb_data[16]_i_2_0 ),
        .I1(\addr_dec_to_mb_data[16]_i_2_1 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[16]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0400000000000000)) 
    \addr_dec_to_mb_data[16]_i_8 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_3_0 [16]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .O(\addr_dec_to_mb_data[16]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFBBBF0000)) 
    \addr_dec_to_mb_data[17]_i_1 
       (.I0(\addr_dec_to_mb_data[17]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[17]_i_3_n_0 ),
        .I2(\addr_dec_to_mb_data[17]_i_4_n_0 ),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[17]_i_5_n_0 ),
        .O(\cal_timer_reg[31] [17]));
  LUT6 #(
    .INIT(64'h0000020002020202)) 
    \addr_dec_to_mb_data[17]_i_2 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_3_0 [17]),
        .I4(\addr_dec_to_mb_data[19]_i_7_n_0 ),
        .I5(\addr_dec_to_mb_data[17]_i_6_n_0 ),
        .O(\addr_dec_to_mb_data[17]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h57F7)) 
    \addr_dec_to_mb_data[17]_i_3 
       (.I0(\SYNC[9].sync_reg_reg[1]_2 ),
        .I1(\addr_dec_to_mb_data[31]_i_9_0 [13]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [40]),
        .O(\addr_dec_to_mb_data[17]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0E0E00000E0E000E)) 
    \addr_dec_to_mb_data[17]_i_4 
       (.I0(\addr_dec_to_mb_data[17]_i_6_n_0 ),
        .I1(\addr_dec_to_mb_data[19]_i_10_n_0 ),
        .I2(\addr_dec_to_mb_data[17]_i_7_n_0 ),
        .I3(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[17]_0 ),
        .I5(\addr_dec_to_mb_data[19]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[17]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4540FFFF45404540)) 
    \addr_dec_to_mb_data[17]_i_5 
       (.I0(\addr_dec_to_mb_data[19]_i_16_n_0 ),
        .I1(riu2clb_valid[17]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(cal_timer_reg[17]),
        .I4(\addr_dec_to_mb_data_reg[17] ),
        .I5(\addr_dec_to_mb_data[19]_i_14_n_0 ),
        .O(\addr_dec_to_mb_data[17]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h35FFFFFF)) 
    \addr_dec_to_mb_data[17]_i_6 
       (.I0(\addr_dec_to_mb_data[17]_i_2_0 ),
        .I1(\addr_dec_to_mb_data[17]_i_2_1 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[17]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0400000000000000)) 
    \addr_dec_to_mb_data[17]_i_7 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_3_0 [17]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .O(\addr_dec_to_mb_data[17]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFBBBF0000)) 
    \addr_dec_to_mb_data[18]_i_1 
       (.I0(\addr_dec_to_mb_data[18]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[18]_i_3_n_0 ),
        .I2(\addr_dec_to_mb_data[18]_i_4_n_0 ),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[18]_i_5_n_0 ),
        .O(\cal_timer_reg[31] [18]));
  LUT6 #(
    .INIT(64'h0000020002020202)) 
    \addr_dec_to_mb_data[18]_i_2 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_3_0 [18]),
        .I4(\addr_dec_to_mb_data[19]_i_7_n_0 ),
        .I5(\addr_dec_to_mb_data[18]_i_6_n_0 ),
        .O(\addr_dec_to_mb_data[18]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h57F7)) 
    \addr_dec_to_mb_data[18]_i_3 
       (.I0(\SYNC[9].sync_reg_reg[1]_2 ),
        .I1(\addr_dec_to_mb_data[31]_i_9_0 [14]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [41]),
        .O(\addr_dec_to_mb_data[18]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0E0E00000E0E000E)) 
    \addr_dec_to_mb_data[18]_i_4 
       (.I0(\addr_dec_to_mb_data[18]_i_6_n_0 ),
        .I1(\addr_dec_to_mb_data[19]_i_10_n_0 ),
        .I2(\addr_dec_to_mb_data[18]_i_7_n_0 ),
        .I3(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[18]_0 ),
        .I5(\addr_dec_to_mb_data[19]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[18]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4F444F4F4F444444)) 
    \addr_dec_to_mb_data[18]_i_5 
       (.I0(\addr_dec_to_mb_data_reg[18] ),
        .I1(\addr_dec_to_mb_data[19]_i_14_n_0 ),
        .I2(\addr_dec_to_mb_data[19]_i_16_n_0 ),
        .I3(riu2clb_valid[18]),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(cal_timer_reg[18]),
        .O(\addr_dec_to_mb_data[18]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h35FFFFFF)) 
    \addr_dec_to_mb_data[18]_i_6 
       (.I0(\addr_dec_to_mb_data[18]_i_2_0 ),
        .I1(\addr_dec_to_mb_data[18]_i_2_1 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[18]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0400000000000000)) 
    \addr_dec_to_mb_data[18]_i_7 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_3_0 [18]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .O(\addr_dec_to_mb_data[18]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFBBBF0000)) 
    \addr_dec_to_mb_data[19]_i_1 
       (.I0(\addr_dec_to_mb_data[19]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data_reg[19] ),
        .I2(\addr_dec_to_mb_data[19]_i_4_n_0 ),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[19]_i_6_n_0 ),
        .O(\cal_timer_reg[31] [19]));
  LUT6 #(
    .INIT(64'hFFFFFF80FFFFFFFF)) 
    \addr_dec_to_mb_data[19]_i_10 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[12].sync_reg [1]),
        .I4(\SYNC[23].sync_reg [1]),
        .I5(\SYNC[20].sync_reg [1]),
        .O(\addr_dec_to_mb_data[19]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0400000000000000)) 
    \addr_dec_to_mb_data[19]_i_11 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_3_0 [19]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .O(\addr_dec_to_mb_data[19]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FBAB)) 
    \addr_dec_to_mb_data[19]_i_13 
       (.I0(\cal_ADR_B[31]_i_8_n_0 ),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\SYNC[10].sync_reg [1]),
        .I5(\SYNC[20].sync_reg [1]),
        .O(\addr_dec_to_mb_data[19]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h222A)) 
    \addr_dec_to_mb_data[19]_i_14 
       (.I0(\SYNC[4].sync_reg_reg[1]_5 ),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[22].sync_reg [1]),
        .I3(\SYNC[21].sync_reg [1]),
        .O(\addr_dec_to_mb_data[19]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hDFDFDFFFFFFFFFFF)) 
    \addr_dec_to_mb_data[19]_i_16 
       (.I0(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\SYNC[3].sync_reg [1]),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\addr_dec_to_mb_data[19]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h0000020002020202)) 
    \addr_dec_to_mb_data[19]_i_2 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_3_0 [19]),
        .I4(\addr_dec_to_mb_data[19]_i_7_n_0 ),
        .I5(\addr_dec_to_mb_data[19]_i_8_n_0 ),
        .O(\addr_dec_to_mb_data[19]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0E0E00000E0E000E)) 
    \addr_dec_to_mb_data[19]_i_4 
       (.I0(\addr_dec_to_mb_data[19]_i_10_n_0 ),
        .I1(\addr_dec_to_mb_data[19]_i_8_n_0 ),
        .I2(\addr_dec_to_mb_data[19]_i_11_n_0 ),
        .I3(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[19]_1 ),
        .I5(\addr_dec_to_mb_data[19]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[19]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hA002AAA0AAAAAAAA)) 
    \addr_dec_to_mb_data[19]_i_5 
       (.I0(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .I1(\SYNC[3].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\SYNC[17].sync_reg [1]),
        .O(\addr_dec_to_mb_data[19]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h8F888F8F8F888888)) 
    \addr_dec_to_mb_data[19]_i_6 
       (.I0(\addr_dec_to_mb_data[19]_i_14_n_0 ),
        .I1(\addr_dec_to_mb_data_reg[19]_0 ),
        .I2(\addr_dec_to_mb_data[19]_i_16_n_0 ),
        .I3(riu2clb_valid[19]),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(cal_timer_reg[19]),
        .O(\addr_dec_to_mb_data[19]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFDFFFF)) 
    \addr_dec_to_mb_data[19]_i_7 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\SYNC[2].sync_reg [1]),
        .O(\addr_dec_to_mb_data[19]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h35FFFFFF)) 
    \addr_dec_to_mb_data[19]_i_8 
       (.I0(\addr_dec_to_mb_data[19]_i_2_0 ),
        .I1(\addr_dec_to_mb_data[19]_i_2_1 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[19]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \addr_dec_to_mb_data[19]_i_9 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\SYNC[22].sync_reg_reg[1]_0 ),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\SYNC[9].sync_reg_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF200)) 
    \addr_dec_to_mb_data[1]_i_1 
       (.I0(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[1]_i_2_n_0 ),
        .I2(\addr_dec_to_mb_data[1]_i_3_n_0 ),
        .I3(\addr_dec_to_mb_data[7]_i_6_n_0 ),
        .I4(\addr_dec_to_mb_data[1]_i_4_n_0 ),
        .I5(\addr_dec_to_mb_data[1]_i_5_n_0 ),
        .O(\cal_timer_reg[31] [1]));
  LUT5 #(
    .INIT(32'h20222000)) 
    \addr_dec_to_mb_data[1]_i_10 
       (.I0(\cal_ADR_B[31]_i_9_n_0 ),
        .I1(\addr_dec_to_mb_data[2]_i_29_n_0 ),
        .I2(\addr_dec_to_mb_data[7]_i_15_0 [1]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[31]_i_3_0 [1]),
        .O(\addr_dec_to_mb_data[1]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h7477FFFFFFFFFFFF)) 
    \addr_dec_to_mb_data[1]_i_12 
       (.I0(\addr_dec_to_mb_data[1]_i_3_0 ),
        .I1(\SYNC[4].sync_reg [1]),
        .I2(\SYNC[5].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[7]_i_5_0 [1]),
        .I4(\addr_dec_to_mb_data[2]_i_32_n_0 ),
        .I5(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .O(\addr_dec_to_mb_data[1]_i_12_n_0 ));
  LUT5 #(
    .INIT(32'h47FF77FF)) 
    \addr_dec_to_mb_data[1]_i_13 
       (.I0(\addr_dec_to_mb_data[5]_i_6_0 [0]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[22].sync_reg [1]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[5]_i_6_1 [0]),
        .O(\addr_dec_to_mb_data[1]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFE200E2)) 
    \addr_dec_to_mb_data[1]_i_14 
       (.I0(cal_timer_reg[1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(phy2clb_rd_dq_bits[1]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(riu2clb_valid[1]),
        .I5(\addr_dec_to_mb_data[7]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[1]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAEFEAAAAA)) 
    \addr_dec_to_mb_data[1]_i_15 
       (.I0(\addr_dec_to_mb_data[1]_i_22_n_0 ),
        .I1(\addr_dec_to_mb_data[1]_i_3_0 ),
        .I2(\SYNC[4].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[7]_i_5_0 [1]),
        .I4(\SYNC[19].sync_reg [1]),
        .I5(\SYNC[18].sync_reg [1]),
        .O(\addr_dec_to_mb_data[1]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF8000)) 
    \addr_dec_to_mb_data[1]_i_16 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[4].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[2]_i_34_n_0 ),
        .I4(\addr_dec_to_mb_data[1]_i_23_n_0 ),
        .O(\addr_dec_to_mb_data[1]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h5557775777777777)) 
    \addr_dec_to_mb_data[1]_i_17 
       (.I0(\addr_dec_to_mb_data[2]_i_7_n_0 ),
        .I1(\addr_dec_to_mb_data[1]_i_24_n_0 ),
        .I2(\addr_dec_to_mb_data[1]_i_5_1 ),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[1]_i_5_0 ),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\addr_dec_to_mb_data[1]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h8888888888B88888)) 
    \addr_dec_to_mb_data[1]_i_18 
       (.I0(\addr_dec_to_mb_data[30]_i_6_1 [0]),
        .I1(\cal_ADR_B[31]_i_8_n_0 ),
        .I2(\addr_dec_to_mb_data[11]_i_3_0 [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[23].sync_reg [1]),
        .I5(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[1]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000005D)) 
    \addr_dec_to_mb_data[1]_i_2 
       (.I0(\addr_dec_to_mb_data[2]_i_7_n_0 ),
        .I1(\addr_dec_to_mb_data[1]_i_6_n_0 ),
        .I2(\addr_dec_to_mb_data[1]_i_7_n_0 ),
        .I3(\addr_dec_to_mb_data[1]_i_8_n_0 ),
        .I4(\addr_dec_to_mb_data[1]_i_9_n_0 ),
        .I5(\addr_dec_to_mb_data[1]_i_10_n_0 ),
        .O(\addr_dec_to_mb_data[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8888800000008000)) 
    \addr_dec_to_mb_data[1]_i_22 
       (.I0(\SYNC[12].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .I2(\addr_dec_to_mb_data[30]_i_6_1 [0]),
        .I3(\SYNC[22].sync_reg [1]),
        .I4(\SYNC[21].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[30]_i_6_2 [0]),
        .O(\addr_dec_to_mb_data[1]_i_22_n_0 ));
  LUT5 #(
    .INIT(32'h80FF8080)) 
    \addr_dec_to_mb_data[1]_i_23 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(douta[1]),
        .I3(\SYNC[9].sync_reg_reg[1]_3 ),
        .I4(\addr_dec_to_mb_data[11]_i_3_0 [1]),
        .O(\addr_dec_to_mb_data[1]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000E200)) 
    \addr_dec_to_mb_data[1]_i_24 
       (.I0(\addr_dec_to_mb_data[31]_i_9_0 [0]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_9_0 [27]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\addr_dec_to_mb_data[1]_i_24_n_0 ));
  LUT4 #(
    .INIT(16'h4FFF)) 
    \addr_dec_to_mb_data[1]_i_3 
       (.I0(\addr_dec_to_mb_data[2]_i_13_n_0 ),
        .I1(\addr_dec_to_mb_data_reg[1] ),
        .I2(\addr_dec_to_mb_data[1]_i_12_n_0 ),
        .I3(\addr_dec_to_mb_data[1]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000008B)) 
    \addr_dec_to_mb_data[1]_i_4 
       (.I0(initDone),
        .I1(\addr_dec_to_mb_data[2]_i_18_n_0 ),
        .I2(\addr_dec_to_mb_data[1]_i_13_n_0 ),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[2]_i_19_n_0 ),
        .I5(\addr_dec_to_mb_data[1]_i_14_n_0 ),
        .O(\addr_dec_to_mb_data[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hA8A8A8A8AAA8AAAA)) 
    \addr_dec_to_mb_data[1]_i_5 
       (.I0(\addr_dec_to_mb_data[2]_i_20_n_0 ),
        .I1(\addr_dec_to_mb_data_reg[1] ),
        .I2(\addr_dec_to_mb_data[1]_i_15_n_0 ),
        .I3(\addr_dec_to_mb_data[1]_i_16_n_0 ),
        .I4(\addr_dec_to_mb_data[1]_i_17_n_0 ),
        .I5(\addr_dec_to_mb_data[2]_i_24_n_0 ),
        .O(\addr_dec_to_mb_data[1]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hBFBBBFFF)) 
    \addr_dec_to_mb_data[1]_i_6 
       (.I0(\addr_dec_to_mb_data[2]_i_25_n_0 ),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[1]_i_5_0 ),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[1]_i_5_1 ),
        .O(\addr_dec_to_mb_data[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004540)) 
    \addr_dec_to_mb_data[1]_i_7 
       (.I0(\addr_dec_to_mb_data[3]_i_24_n_0 ),
        .I1(\addr_dec_to_mb_data[31]_i_9_0 [27]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [0]),
        .I4(\SYNC[21].sync_reg [1]),
        .I5(\SYNC[22].sync_reg [1]),
        .O(\addr_dec_to_mb_data[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFE200E2)) 
    \addr_dec_to_mb_data[1]_i_8 
       (.I0(\addr_dec_to_mb_data[30]_i_6_0 [0]),
        .I1(\SYNC[12].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[30]_i_6_2 [0]),
        .I3(\SYNC[12].sync_reg_reg[1]_2 ),
        .I4(\addr_dec_to_mb_data[1]_i_18_n_0 ),
        .I5(\addr_dec_to_mb_data[5]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hF444444444444444)) 
    \addr_dec_to_mb_data[1]_i_9 
       (.I0(\addr_dec_to_mb_data[1]_i_2_0 ),
        .I1(\addr_dec_to_mb_data[2]_i_28_n_0 ),
        .I2(douta[1]),
        .I3(\SYNC[23].sync_reg_reg[1]_2 ),
        .I4(\addr_dec_to_mb_data[0]_i_17_n_0 ),
        .I5(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .O(\addr_dec_to_mb_data[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFF020000FFFFFFFF)) 
    \addr_dec_to_mb_data[20]_i_1 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[20]_i_2_n_0 ),
        .I3(\addr_dec_to_mb_data[20]_i_3_n_0 ),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[20]_i_4_n_0 ),
        .O(\SYNC[20].sync_reg_reg[1]_7 ));
  LUT6 #(
    .INIT(64'hF7FF0000F7FFF7FF)) 
    \addr_dec_to_mb_data[20]_i_2 
       (.I0(\addr_dec_to_mb_data[31]_i_3_0 [20]),
        .I1(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[20]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[27]_i_6_n_0 ),
        .O(\addr_dec_to_mb_data[20]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000ABAA)) 
    \addr_dec_to_mb_data[20]_i_3 
       (.I0(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[13]_i_10_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[20]_0 ),
        .O(\addr_dec_to_mb_data[20]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hD0DD)) 
    \addr_dec_to_mb_data[20]_i_4 
       (.I0(\SYNC[4].sync_reg_reg[1]_5 ),
        .I1(\addr_dec_to_mb_data_reg[20] ),
        .I2(\SYNC[3].sync_reg_reg[1]_2 ),
        .I3(cal_timer_reg[20]),
        .O(\addr_dec_to_mb_data[20]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hA2AAA2A2A2AAAAAA)) 
    \addr_dec_to_mb_data[20]_i_5 
       (.I0(\addr_dec_to_mb_data[20]_i_8_n_0 ),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\SYNC[12].sync_reg_reg[1]_1 ),
        .I3(\addr_dec_to_mb_data[20]_i_2_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[20]_i_2_1 ),
        .O(\addr_dec_to_mb_data[20]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDFFFFFFFDFF)) 
    \addr_dec_to_mb_data[20]_i_8 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [15]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_9_0 [42]),
        .O(\addr_dec_to_mb_data[20]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFD550000FFFFFFFF)) 
    \addr_dec_to_mb_data[21]_i_1 
       (.I0(\addr_dec_to_mb_data[21]_i_2_n_0 ),
        .I1(\SYNC[20].sync_reg_reg[1]_2 ),
        .I2(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I3(\addr_dec_to_mb_data_reg[21] ),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data_reg[21]_0 ),
        .O(\SYNC[8].sync_reg_reg[1]_4 ));
  LUT6 #(
    .INIT(64'h51555555FFFFFFFF)) 
    \addr_dec_to_mb_data[21]_i_2 
       (.I0(\addr_dec_to_mb_data[21]_i_5_n_0 ),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I4(\addr_dec_to_mb_data[31]_i_3_0 [21]),
        .I5(lrdimm_cmp_en_i_3_n_0),
        .O(\addr_dec_to_mb_data[21]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000A808AAAAAAAA)) 
    \addr_dec_to_mb_data[21]_i_5 
       (.I0(\addr_dec_to_mb_data[27]_i_6_n_0 ),
        .I1(\addr_dec_to_mb_data[21]_i_2_0 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[21]_i_2_1 ),
        .I4(\addr_dec_to_mb_data[5]_i_26_n_0 ),
        .I5(\addr_dec_to_mb_data[21]_i_7_n_0 ),
        .O(\addr_dec_to_mb_data[21]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDFFFFFFFDFF)) 
    \addr_dec_to_mb_data[21]_i_7 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [16]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_9_0 [43]),
        .O(\addr_dec_to_mb_data[21]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF2F22)) 
    \addr_dec_to_mb_data[22]_i_1 
       (.I0(cal_timer_reg[21]),
        .I1(\SYNC[3].sync_reg_reg[1]_2 ),
        .I2(\addr_dec_to_mb_data_reg[22] ),
        .I3(\SYNC[4].sync_reg_reg[1]_5 ),
        .I4(\addr_dec_to_mb_data[22]_i_3_n_0 ),
        .O(cal_timer_reg_22_sn_1));
  LUT6 #(
    .INIT(64'h8A88AAAA8A888A88)) 
    \addr_dec_to_mb_data[22]_i_3 
       (.I0(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I1(\addr_dec_to_mb_data[22]_i_5_n_0 ),
        .I2(\addr_dec_to_mb_data[5]_i_13_n_0 ),
        .I3(\addr_dec_to_mb_data[22]_i_6_n_0 ),
        .I4(\addr_dec_to_mb_data[22]_i_7_n_0 ),
        .I5(lrdimm_cmp_en_i_3_n_0),
        .O(\addr_dec_to_mb_data[22]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h20000000A8888888)) 
    \addr_dec_to_mb_data[22]_i_5 
       (.I0(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[30]_i_6_1 [9]),
        .I4(\SYNC[22].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[22]_i_3_0 ),
        .O(\addr_dec_to_mb_data[22]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00008000AAAA8000)) 
    \addr_dec_to_mb_data[22]_i_6 
       (.I0(\addr_dec_to_mb_data[13]_i_10_n_0 ),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[30]_i_6_1 [9]),
        .I4(\SYNC[21].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[22]_i_3_0 ),
        .O(\addr_dec_to_mb_data[22]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0FFFBBBBFFFF)) 
    \addr_dec_to_mb_data[22]_i_7 
       (.I0(\addr_dec_to_mb_data[22]_i_9_n_0 ),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_3_0 [22]),
        .I3(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I4(\SYNC[11].sync_reg [1]),
        .I5(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[22]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'hABFB)) 
    \addr_dec_to_mb_data[22]_i_9 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[31]_i_9_0 [17]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [44]),
        .O(\addr_dec_to_mb_data[22]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF2F22)) 
    \addr_dec_to_mb_data[23]_i_1 
       (.I0(cal_timer_reg[22]),
        .I1(\SYNC[3].sync_reg_reg[1]_2 ),
        .I2(\addr_dec_to_mb_data_reg[23] ),
        .I3(\SYNC[4].sync_reg_reg[1]_5 ),
        .I4(\addr_dec_to_mb_data[23]_i_3_n_0 ),
        .O(cal_timer_reg_23_sn_1));
  LUT6 #(
    .INIT(64'h8880AAAA88808880)) 
    \addr_dec_to_mb_data[23]_i_3 
       (.I0(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I1(\addr_dec_to_mb_data[23]_i_5_n_0 ),
        .I2(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I3(\SYNC[20].sync_reg_reg[1]_2 ),
        .I4(\addr_dec_to_mb_data[23]_i_6_n_0 ),
        .I5(lrdimm_cmp_en_i_3_n_0),
        .O(\addr_dec_to_mb_data[23]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h44F4FFFF44F444F4)) 
    \addr_dec_to_mb_data[23]_i_5 
       (.I0(\SYNC[21].sync_reg_reg[1]_2 ),
        .I1(\addr_dec_to_mb_data[30]_i_6_1 [10]),
        .I2(\addr_dec_to_mb_data[30]_i_6_2 [9]),
        .I3(\SYNC[21].sync_reg_reg[1]_3 ),
        .I4(\SYNC[12].sync_reg_reg[1]_0 ),
        .I5(\addr_dec_to_mb_data[30]_i_6_0 [8]),
        .O(\addr_dec_to_mb_data[23]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0FFFBBBBFFFF)) 
    \addr_dec_to_mb_data[23]_i_6 
       (.I0(\addr_dec_to_mb_data[23]_i_7_n_0 ),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_3_0 [23]),
        .I3(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I4(\SYNC[11].sync_reg [1]),
        .I5(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[23]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'hABFB)) 
    \addr_dec_to_mb_data[23]_i_7 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[31]_i_9_0 [18]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [45]),
        .O(\addr_dec_to_mb_data[23]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFF020000FFFFFFFF)) 
    \addr_dec_to_mb_data[24]_i_1 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[24]_i_2_n_0 ),
        .I3(\addr_dec_to_mb_data[24]_i_3_n_0 ),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data_reg[24]_0 ),
        .O(\SYNC[20].sync_reg_reg[1]_6 ));
  LUT6 #(
    .INIT(64'hF7FF0000F7FFF7FF)) 
    \addr_dec_to_mb_data[24]_i_2 
       (.I0(\addr_dec_to_mb_data[31]_i_3_0 [24]),
        .I1(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[24]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[27]_i_6_n_0 ),
        .O(\addr_dec_to_mb_data[24]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000ABAA)) 
    \addr_dec_to_mb_data[24]_i_3 
       (.I0(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[13]_i_10_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[24] ),
        .O(\addr_dec_to_mb_data[24]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hA2AAA2A2A2AAAAAA)) 
    \addr_dec_to_mb_data[24]_i_5 
       (.I0(\addr_dec_to_mb_data[24]_i_8_n_0 ),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\SYNC[12].sync_reg_reg[1]_1 ),
        .I3(\addr_dec_to_mb_data[24]_i_2_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[24]_i_2_1 ),
        .O(\addr_dec_to_mb_data[24]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDFFFFFFFDFF)) 
    \addr_dec_to_mb_data[24]_i_8 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [19]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_9_0 [46]),
        .O(\addr_dec_to_mb_data[24]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFF020000FFFFFFFF)) 
    \addr_dec_to_mb_data[25]_i_1 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[25]_i_2_n_0 ),
        .I3(\addr_dec_to_mb_data[25]_i_3_n_0 ),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data_reg[25]_0 ),
        .O(\SYNC[20].sync_reg_reg[1]_5 ));
  LUT6 #(
    .INIT(64'hF7FF0000F7FFF7FF)) 
    \addr_dec_to_mb_data[25]_i_2 
       (.I0(\addr_dec_to_mb_data[31]_i_3_0 [25]),
        .I1(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[25]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[27]_i_6_n_0 ),
        .O(\addr_dec_to_mb_data[25]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000ABAA)) 
    \addr_dec_to_mb_data[25]_i_3 
       (.I0(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[13]_i_10_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[25] ),
        .O(\addr_dec_to_mb_data[25]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hA2AAA2A2A2AAAAAA)) 
    \addr_dec_to_mb_data[25]_i_5 
       (.I0(\addr_dec_to_mb_data[25]_i_8_n_0 ),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\SYNC[12].sync_reg_reg[1]_1 ),
        .I3(\addr_dec_to_mb_data[25]_i_2_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[25]_i_2_1 ),
        .O(\addr_dec_to_mb_data[25]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDFFFFFFFDFF)) 
    \addr_dec_to_mb_data[25]_i_8 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [20]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_9_0 [47]),
        .O(\addr_dec_to_mb_data[25]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFF020000FFFFFFFF)) 
    \addr_dec_to_mb_data[26]_i_1 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[26]_i_2_n_0 ),
        .I3(\addr_dec_to_mb_data[26]_i_3_n_0 ),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[26]_i_4_n_0 ),
        .O(\SYNC[20].sync_reg_reg[1]_4 ));
  LUT6 #(
    .INIT(64'hF7FF0000F7FFF7FF)) 
    \addr_dec_to_mb_data[26]_i_2 
       (.I0(\addr_dec_to_mb_data[31]_i_3_0 [26]),
        .I1(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[26]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[27]_i_6_n_0 ),
        .O(\addr_dec_to_mb_data[26]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000ABAA)) 
    \addr_dec_to_mb_data[26]_i_3 
       (.I0(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[13]_i_10_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[26]_0 ),
        .O(\addr_dec_to_mb_data[26]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hD0DD)) 
    \addr_dec_to_mb_data[26]_i_4 
       (.I0(\SYNC[4].sync_reg_reg[1]_5 ),
        .I1(\addr_dec_to_mb_data_reg[26] ),
        .I2(\SYNC[3].sync_reg_reg[1]_2 ),
        .I3(cal_timer_reg[23]),
        .O(\addr_dec_to_mb_data[26]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hA2AAA2A2A2AAAAAA)) 
    \addr_dec_to_mb_data[26]_i_5 
       (.I0(\addr_dec_to_mb_data[26]_i_8_n_0 ),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\SYNC[12].sync_reg_reg[1]_1 ),
        .I3(\addr_dec_to_mb_data[26]_i_2_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[26]_i_2_1 ),
        .O(\addr_dec_to_mb_data[26]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDFFFFFFFDFF)) 
    \addr_dec_to_mb_data[26]_i_8 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [21]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_9_0 [48]),
        .O(\addr_dec_to_mb_data[26]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFF020000FFFFFFFF)) 
    \addr_dec_to_mb_data[27]_i_1 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[27]_i_2_n_0 ),
        .I3(\addr_dec_to_mb_data[27]_i_3_n_0 ),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[27]_i_4_n_0 ),
        .O(\SYNC[20].sync_reg_reg[1]_3 ));
  LUT6 #(
    .INIT(64'hF7FF0000F7FFF7FF)) 
    \addr_dec_to_mb_data[27]_i_2 
       (.I0(\addr_dec_to_mb_data[31]_i_3_0 [27]),
        .I1(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[27]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[27]_i_6_n_0 ),
        .O(\addr_dec_to_mb_data[27]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000ABAA)) 
    \addr_dec_to_mb_data[27]_i_3 
       (.I0(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[13]_i_10_n_0 ),
        .I4(\addr_dec_to_mb_data_reg[27]_0 ),
        .O(\addr_dec_to_mb_data[27]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hD0DD)) 
    \addr_dec_to_mb_data[27]_i_4 
       (.I0(\SYNC[4].sync_reg_reg[1]_5 ),
        .I1(\addr_dec_to_mb_data_reg[27] ),
        .I2(\SYNC[3].sync_reg_reg[1]_2 ),
        .I3(cal_timer_reg[24]),
        .O(\addr_dec_to_mb_data[27]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hA2AAA2A2A2AAAAAA)) 
    \addr_dec_to_mb_data[27]_i_5 
       (.I0(\addr_dec_to_mb_data[27]_i_9_n_0 ),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\SYNC[12].sync_reg_reg[1]_1 ),
        .I3(\addr_dec_to_mb_data[27]_i_2_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[27]_i_2_1 ),
        .O(\addr_dec_to_mb_data[27]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAA2AAA)) 
    \addr_dec_to_mb_data[27]_i_6 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\SYNC[9].sync_reg [1]),
        .I5(\SYNC[12].sync_reg [1]),
        .O(\addr_dec_to_mb_data[27]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDFFFFFFFDFF)) 
    \addr_dec_to_mb_data[27]_i_9 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [22]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_9_0 [49]),
        .O(\addr_dec_to_mb_data[27]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFD550000FFFFFFFF)) 
    \addr_dec_to_mb_data[28]_i_1 
       (.I0(\addr_dec_to_mb_data[28]_i_2_n_0 ),
        .I1(\SYNC[20].sync_reg_reg[1]_2 ),
        .I2(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I3(\addr_dec_to_mb_data[28]_i_3_n_0 ),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data_reg[28] ),
        .O(\SYNC[8].sync_reg_reg[1]_3 ));
  LUT6 #(
    .INIT(64'h51555555FFFFFFFF)) 
    \addr_dec_to_mb_data[28]_i_2 
       (.I0(\addr_dec_to_mb_data[28]_i_5_n_0 ),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I4(\addr_dec_to_mb_data[31]_i_3_0 [28]),
        .I5(lrdimm_cmp_en_i_3_n_0),
        .O(\addr_dec_to_mb_data[28]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h44F444F4FFFF44F4)) 
    \addr_dec_to_mb_data[28]_i_3 
       (.I0(\SYNC[21].sync_reg_reg[1]_2 ),
        .I1(\addr_dec_to_mb_data[30]_i_6_1 [11]),
        .I2(\addr_dec_to_mb_data[30]_i_6_2 [10]),
        .I3(\SYNC[21].sync_reg_reg[1]_3 ),
        .I4(\addr_dec_to_mb_data[30]_i_6_0 [9]),
        .I5(\SYNC[12].sync_reg_reg[1]_0 ),
        .O(\addr_dec_to_mb_data[28]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000A808AAAAAAAA)) 
    \addr_dec_to_mb_data[28]_i_5 
       (.I0(\addr_dec_to_mb_data[27]_i_6_n_0 ),
        .I1(\addr_dec_to_mb_data[28]_i_2_0 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[28]_i_2_1 ),
        .I4(\addr_dec_to_mb_data[5]_i_26_n_0 ),
        .I5(\addr_dec_to_mb_data[28]_i_7_n_0 ),
        .O(\addr_dec_to_mb_data[28]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDFFFFFFFDFF)) 
    \addr_dec_to_mb_data[28]_i_7 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [23]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_9_0 [50]),
        .O(\addr_dec_to_mb_data[28]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h5F5D0000FFFFFFFF)) 
    \addr_dec_to_mb_data[29]_i_1 
       (.I0(\addr_dec_to_mb_data[29]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I2(\addr_dec_to_mb_data_reg[29] ),
        .I3(\SYNC[20].sync_reg_reg[1]_2 ),
        .I4(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data_reg[29]_0 ),
        .O(\SYNC[8].sync_reg_reg[1]_2 ));
  LUT3 #(
    .INIT(8'hBF)) 
    \addr_dec_to_mb_data[29]_i_10 
       (.I0(\SYNC[12].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .O(\SYNC[12].sync_reg_reg[1]_0 ));
  LUT3 #(
    .INIT(8'hBF)) 
    \addr_dec_to_mb_data[29]_i_11 
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(\SYNC[12].sync_reg [1]),
        .I2(\SYNC[22].sync_reg [1]),
        .O(\SYNC[21].sync_reg_reg[1]_2 ));
  LUT6 #(
    .INIT(64'h000000000000E200)) 
    \addr_dec_to_mb_data[29]_i_13 
       (.I0(\addr_dec_to_mb_data[31]_i_9_0 [24]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_9_0 [51]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\addr_dec_to_mb_data[29]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h51555555FFFFFFFF)) 
    \addr_dec_to_mb_data[29]_i_2 
       (.I0(\addr_dec_to_mb_data[29]_i_7_n_0 ),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I4(\addr_dec_to_mb_data[31]_i_3_0 [29]),
        .I5(lrdimm_cmp_en_i_3_n_0),
        .O(\addr_dec_to_mb_data[29]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h74)) 
    \addr_dec_to_mb_data[29]_i_3 
       (.I0(\addr_dec_to_mb_data[0]_i_13_n_0 ),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .O(\addr_dec_to_mb_data[29]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \addr_dec_to_mb_data[29]_i_5 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[13]_i_10_n_0 ),
        .I2(\SYNC[9].sync_reg [1]),
        .O(\SYNC[20].sync_reg_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA0000A808)) 
    \addr_dec_to_mb_data[29]_i_7 
       (.I0(\addr_dec_to_mb_data[27]_i_6_n_0 ),
        .I1(\addr_dec_to_mb_data[29]_i_2_0 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[29]_i_2_1 ),
        .I4(\addr_dec_to_mb_data[5]_i_26_n_0 ),
        .I5(\addr_dec_to_mb_data[29]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[29]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h0004)) 
    \addr_dec_to_mb_data[29]_i_8 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .O(\addr_dec_to_mb_data[29]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \addr_dec_to_mb_data[29]_i_9 
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(\SYNC[12].sync_reg [1]),
        .O(\SYNC[21].sync_reg_reg[1]_3 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF200)) 
    \addr_dec_to_mb_data[2]_i_1 
       (.I0(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[2]_i_3_n_0 ),
        .I2(\addr_dec_to_mb_data[2]_i_4_n_0 ),
        .I3(\addr_dec_to_mb_data[7]_i_6_n_0 ),
        .I4(\addr_dec_to_mb_data[2]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[2]_i_6_n_0 ),
        .O(\cal_timer_reg[31] [2]));
  LUT6 #(
    .INIT(64'h00000000FFE200E2)) 
    \addr_dec_to_mb_data[2]_i_10 
       (.I0(\addr_dec_to_mb_data[30]_i_6_0 [1]),
        .I1(\SYNC[12].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[30]_i_6_2 [1]),
        .I3(\SYNC[12].sync_reg_reg[1]_2 ),
        .I4(\addr_dec_to_mb_data[2]_i_26_n_0 ),
        .I5(\addr_dec_to_mb_data[5]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h8000FFFF80008000)) 
    \addr_dec_to_mb_data[2]_i_11 
       (.I0(\addr_dec_to_mb_data[0]_i_17_n_0 ),
        .I1(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I2(douta[2]),
        .I3(\SYNC[23].sync_reg_reg[1]_2 ),
        .I4(\addr_dec_to_mb_data[2]_i_27_n_0 ),
        .I5(\addr_dec_to_mb_data[2]_i_28_n_0 ),
        .O(\addr_dec_to_mb_data[2]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'h20222000)) 
    \addr_dec_to_mb_data[2]_i_12 
       (.I0(\cal_ADR_B[31]_i_9_n_0 ),
        .I1(\addr_dec_to_mb_data[2]_i_29_n_0 ),
        .I2(\addr_dec_to_mb_data[7]_i_15_0 [2]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[31]_i_3_0 [2]),
        .O(\addr_dec_to_mb_data[2]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFF08FF08FF080808)) 
    \addr_dec_to_mb_data[2]_i_13 
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(\SYNC[5].sync_reg [1]),
        .I2(\SYNC[4].sync_reg [1]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\SYNC[22].sync_reg [1]),
        .I5(\SYNC[21].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h2222222020202220)) 
    \addr_dec_to_mb_data[2]_i_14 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[2]_i_4_1 ),
        .I2(\SYNC[5].sync_reg [1]),
        .I3(\addr_dec_to_mb_data_reg[16] [0]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data_reg[16] [5]),
        .O(\addr_dec_to_mb_data[2]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'hF8000800)) 
    \addr_dec_to_mb_data[2]_i_15 
       (.I0(\SYNC[22].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[5]_i_6_1 [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[5]_i_6_0 [1]),
        .O(\addr_dec_to_mb_data[2]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hF404000000000000)) 
    \addr_dec_to_mb_data[2]_i_16 
       (.I0(\SYNC[5].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[7]_i_5_0 [2]),
        .I2(\SYNC[4].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[2]_i_4_0 ),
        .I4(\addr_dec_to_mb_data[2]_i_32_n_0 ),
        .I5(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .O(\addr_dec_to_mb_data[2]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFE200E2)) 
    \addr_dec_to_mb_data[2]_i_17 
       (.I0(cal_timer_reg[2]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(phy2clb_rd_dq_bits[2]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(riu2clb_valid[2]),
        .I5(\addr_dec_to_mb_data[7]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[2]_i_17_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \addr_dec_to_mb_data[2]_i_18 
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_18_n_0 ));
  LUT4 #(
    .INIT(16'h00FB)) 
    \addr_dec_to_mb_data[2]_i_19 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[2]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[2]_i_19_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \addr_dec_to_mb_data[2]_i_2 
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00005545)) 
    \addr_dec_to_mb_data[2]_i_20 
       (.I0(\addr_dec_to_mb_data[2]_i_13_n_0 ),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAEFEAAAAA)) 
    \addr_dec_to_mb_data[2]_i_21 
       (.I0(\addr_dec_to_mb_data[2]_i_33_n_0 ),
        .I1(\addr_dec_to_mb_data[2]_i_4_0 ),
        .I2(\SYNC[4].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[7]_i_5_0 [2]),
        .I4(\SYNC[19].sync_reg [1]),
        .I5(\SYNC[18].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF83800000)) 
    \addr_dec_to_mb_data[2]_i_22 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[2]_i_6_2 [1]),
        .I4(\addr_dec_to_mb_data[2]_i_34_n_0 ),
        .I5(\addr_dec_to_mb_data[2]_i_35_n_0 ),
        .O(\addr_dec_to_mb_data[2]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'h5557775777777777)) 
    \addr_dec_to_mb_data[2]_i_23 
       (.I0(\addr_dec_to_mb_data[2]_i_7_n_0 ),
        .I1(\addr_dec_to_mb_data[2]_i_36_n_0 ),
        .I2(\addr_dec_to_mb_data[2]_i_6_1 ),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[2]_i_6_0 ),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAFEAAAA)) 
    \addr_dec_to_mb_data[2]_i_24 
       (.I0(\addr_dec_to_mb_data[3]_i_7_n_0 ),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[23].sync_reg [1]),
        .I4(\SYNC[9].sync_reg [1]),
        .I5(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF44FCFCCC44)) 
    \addr_dec_to_mb_data[2]_i_25 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\SYNC[22].sync_reg [1]),
        .I4(\SYNC[21].sync_reg [1]),
        .I5(\SYNC[12].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'h888B888888888888)) 
    \addr_dec_to_mb_data[2]_i_26 
       (.I0(\addr_dec_to_mb_data[30]_i_6_1 [1]),
        .I1(\cal_ADR_B[31]_i_8_n_0 ),
        .I2(\SYNC[10].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[11]_i_3_0 [2]),
        .I5(\SYNC[23].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'h337733770FFFFFFF)) 
    \addr_dec_to_mb_data[2]_i_27 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[2]_i_11_0 ),
        .I2(\addr_dec_to_mb_data[30]_i_6_1 [1]),
        .I3(\SYNC[12].sync_reg [1]),
        .I4(\SYNC[22].sync_reg [1]),
        .I5(\SYNC[21].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_27_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555555551)) 
    \addr_dec_to_mb_data[2]_i_28 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[10].sync_reg [1]),
        .I5(\SYNC[23].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_28_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDFFFDFFFDFDFD)) 
    \addr_dec_to_mb_data[2]_i_29 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[10].sync_reg [1]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\SYNC[22].sync_reg [1]),
        .I5(\SYNC[21].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000005D)) 
    \addr_dec_to_mb_data[2]_i_3 
       (.I0(\addr_dec_to_mb_data[2]_i_7_n_0 ),
        .I1(\addr_dec_to_mb_data[2]_i_8_n_0 ),
        .I2(\addr_dec_to_mb_data[2]_i_9_n_0 ),
        .I3(\addr_dec_to_mb_data[2]_i_10_n_0 ),
        .I4(\addr_dec_to_mb_data[2]_i_11_n_0 ),
        .I5(\addr_dec_to_mb_data[2]_i_12_n_0 ),
        .O(\addr_dec_to_mb_data[2]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \addr_dec_to_mb_data[2]_i_32 
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_32_n_0 ));
  LUT6 #(
    .INIT(64'h8888800000008000)) 
    \addr_dec_to_mb_data[2]_i_33 
       (.I0(\SYNC[12].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .I2(\addr_dec_to_mb_data[30]_i_6_1 [1]),
        .I3(\SYNC[22].sync_reg [1]),
        .I4(\SYNC[21].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[30]_i_6_2 [1]),
        .O(\addr_dec_to_mb_data[2]_i_33_n_0 ));
  LUT4 #(
    .INIT(16'h0400)) 
    \addr_dec_to_mb_data[2]_i_34 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_34_n_0 ));
  LUT5 #(
    .INIT(32'h80FF8080)) 
    \addr_dec_to_mb_data[2]_i_35 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(douta[2]),
        .I3(\SYNC[9].sync_reg_reg[1]_3 ),
        .I4(\addr_dec_to_mb_data[11]_i_3_0 [2]),
        .O(\addr_dec_to_mb_data[2]_i_35_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000E200)) 
    \addr_dec_to_mb_data[2]_i_36 
       (.I0(\addr_dec_to_mb_data[31]_i_9_0 [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_9_0 [28]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_36_n_0 ));
  LUT4 #(
    .INIT(16'hFFF4)) 
    \addr_dec_to_mb_data[2]_i_4 
       (.I0(\addr_dec_to_mb_data[2]_i_13_n_0 ),
        .I1(\addr_dec_to_mb_data[2]_i_14_n_0 ),
        .I2(\addr_dec_to_mb_data[2]_i_15_n_0 ),
        .I3(\addr_dec_to_mb_data[2]_i_16_n_0 ),
        .O(\addr_dec_to_mb_data[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAEEFA)) 
    \addr_dec_to_mb_data[2]_i_5 
       (.I0(\addr_dec_to_mb_data[2]_i_17_n_0 ),
        .I1(\addr_dec_to_mb_data_reg[2] ),
        .I2(\addr_dec_to_mb_data[2]_i_15_n_0 ),
        .I3(\addr_dec_to_mb_data[2]_i_18_n_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[2]_i_19_n_0 ),
        .O(\addr_dec_to_mb_data[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hA8A8A8A8AAA8AAAA)) 
    \addr_dec_to_mb_data[2]_i_6 
       (.I0(\addr_dec_to_mb_data[2]_i_20_n_0 ),
        .I1(\addr_dec_to_mb_data[2]_i_14_n_0 ),
        .I2(\addr_dec_to_mb_data[2]_i_21_n_0 ),
        .I3(\addr_dec_to_mb_data[2]_i_22_n_0 ),
        .I4(\addr_dec_to_mb_data[2]_i_23_n_0 ),
        .I5(\addr_dec_to_mb_data[2]_i_24_n_0 ),
        .O(\addr_dec_to_mb_data[2]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \addr_dec_to_mb_data[2]_i_7 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hBFBBBFFF)) 
    \addr_dec_to_mb_data[2]_i_8 
       (.I0(\addr_dec_to_mb_data[2]_i_25_n_0 ),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[2]_i_6_0 ),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[2]_i_6_1 ),
        .O(\addr_dec_to_mb_data[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004540)) 
    \addr_dec_to_mb_data[2]_i_9 
       (.I0(\addr_dec_to_mb_data[3]_i_24_n_0 ),
        .I1(\addr_dec_to_mb_data[31]_i_9_0 [28]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [1]),
        .I4(\SYNC[21].sync_reg [1]),
        .I5(\SYNC[22].sync_reg [1]),
        .O(\addr_dec_to_mb_data[2]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \addr_dec_to_mb_data[30]_i_1 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .O(\SYNC[9].sync_reg_reg[1]_1 ));
  LUT4 #(
    .INIT(16'hABFB)) 
    \addr_dec_to_mb_data[30]_i_10 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[31]_i_9_0 [25]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [52]),
        .O(\addr_dec_to_mb_data[30]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFF222)) 
    \addr_dec_to_mb_data[30]_i_2 
       (.I0(cal_timer_reg[25]),
        .I1(\SYNC[3].sync_reg_reg[1]_2 ),
        .I2(\SYNC[4].sync_reg_reg[1]_5 ),
        .I3(\addr_dec_to_mb_data_reg[30] ),
        .I4(\addr_dec_to_mb_data[30]_i_6_n_0 ),
        .O(\cal_timer_reg[30] ));
  LUT5 #(
    .INIT(32'hFDFFFFFF)) 
    \addr_dec_to_mb_data[30]_i_3 
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .O(\SYNC[3].sync_reg_reg[1]_2 ));
  LUT5 #(
    .INIT(32'h0000BF00)) 
    \addr_dec_to_mb_data[30]_i_4 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\SYNC[5].sync_reg [1]),
        .I2(\SYNC[19].sync_reg [1]),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[31]_i_5_n_0 ),
        .O(\SYNC[4].sync_reg_reg[1]_5 ));
  LUT6 #(
    .INIT(64'hA800AAAAA800A800)) 
    \addr_dec_to_mb_data[30]_i_6 
       (.I0(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I1(\SYNC[20].sync_reg_reg[1]_2 ),
        .I2(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I3(\addr_dec_to_mb_data[30]_i_8_n_0 ),
        .I4(\addr_dec_to_mb_data[30]_i_9_n_0 ),
        .I5(lrdimm_cmp_en_i_3_n_0),
        .O(\addr_dec_to_mb_data[30]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h44F444F4FFFF44F4)) 
    \addr_dec_to_mb_data[30]_i_8 
       (.I0(\SYNC[21].sync_reg_reg[1]_2 ),
        .I1(\addr_dec_to_mb_data[30]_i_6_1 [12]),
        .I2(\addr_dec_to_mb_data[30]_i_6_2 [11]),
        .I3(\SYNC[21].sync_reg_reg[1]_3 ),
        .I4(\addr_dec_to_mb_data[30]_i_6_0 [10]),
        .I5(\SYNC[12].sync_reg_reg[1]_0 ),
        .O(\addr_dec_to_mb_data[30]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0FFFBBBBFFFF)) 
    \addr_dec_to_mb_data[30]_i_9 
       (.I0(\addr_dec_to_mb_data[30]_i_10_n_0 ),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_3_0 [30]),
        .I3(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I4(\SYNC[11].sync_reg [1]),
        .I5(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[30]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00E0F0E000E000E0)) 
    \addr_dec_to_mb_data[31]_i_1 
       (.I0(\addr_dec_to_mb_data_reg[31] ),
        .I1(\addr_dec_to_mb_data[31]_i_3_n_0 ),
        .I2(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I3(\addr_dec_to_mb_data[31]_i_5_n_0 ),
        .I4(\addr_dec_to_mb_data[31]_i_6_n_0 ),
        .I5(cal_timer_reg[26]),
        .O(\cal_timer_reg[31] [20]));
  LUT5 #(
    .INIT(32'hEE0EEEEE)) 
    \addr_dec_to_mb_data[31]_i_10 
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\cal_cmp_en[7]_i_5_n_0 ),
        .O(\addr_dec_to_mb_data[31]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'hABFB)) 
    \addr_dec_to_mb_data[31]_i_12 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[31]_i_9_0 [26]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [53]),
        .O(\addr_dec_to_mb_data[31]_i_12_n_0 ));
  LUT4 #(
    .INIT(16'h07FF)) 
    \addr_dec_to_mb_data[31]_i_13 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\SYNC[21].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_3 ));
  LUT6 #(
    .INIT(64'h000F000200000002)) 
    \addr_dec_to_mb_data[31]_i_3 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\addr_dec_to_mb_data[31]_i_9_n_0 ),
        .I2(\SYNC[19].sync_reg [1]),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[31]_i_10_n_0 ),
        .I5(\addr_dec_to_mb_data_reg[31]_0 ),
        .O(\addr_dec_to_mb_data[31]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h1F)) 
    \addr_dec_to_mb_data[31]_i_4 
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .O(\addr_dec_to_mb_data[31]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h088A0882)) 
    \addr_dec_to_mb_data[31]_i_5 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[3].sync_reg [1]),
        .O(\addr_dec_to_mb_data[31]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hEF)) 
    \addr_dec_to_mb_data[31]_i_6 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .O(\addr_dec_to_mb_data[31]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'hAA2A)) 
    \addr_dec_to_mb_data[31]_i_8 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\SYNC[19].sync_reg [1]),
        .I2(\SYNC[5].sync_reg [1]),
        .I3(\SYNC[4].sync_reg [1]),
        .O(\SYNC[18].sync_reg_reg[1]_3 ));
  LUT6 #(
    .INIT(64'hFD0FFDFFFDFFFDFF)) 
    \addr_dec_to_mb_data[31]_i_9 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[31]_i_12_n_0 ),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[31]_i_3_0 [31]),
        .I5(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .O(\addr_dec_to_mb_data[31]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA0000A808)) 
    \addr_dec_to_mb_data[3]_i_10 
       (.I0(\addr_dec_to_mb_data[3]_i_21_n_0 ),
        .I1(\addr_dec_to_mb_data[31]_i_9_0 [2]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [29]),
        .I4(\addr_dec_to_mb_data[3]_i_24_n_0 ),
        .I5(\addr_dec_to_mb_data[0]_i_17_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAFEAE)) 
    \addr_dec_to_mb_data[3]_i_11 
       (.I0(\addr_dec_to_mb_data[3]_i_25_n_0 ),
        .I1(\addr_dec_to_mb_data[3]_i_3_0 ),
        .I2(\SYNC[12].sync_reg_reg[1]_2 ),
        .I3(\addr_dec_to_mb_data[3]_i_28_n_0 ),
        .I4(\addr_dec_to_mb_data[5]_i_13_n_0 ),
        .I5(\addr_dec_to_mb_data[3]_i_29_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7060)) 
    \addr_dec_to_mb_data[3]_i_12 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[2]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAEAEFFAE)) 
    \addr_dec_to_mb_data[3]_i_13 
       (.I0(\addr_dec_to_mb_data[3]_i_30_n_0 ),
        .I1(\addr_dec_to_mb_data[3]_i_31_n_0 ),
        .I2(\addr_dec_to_mb_data[3]_i_32_n_0 ),
        .I3(\addr_dec_to_mb_data[3]_i_4_n_0 ),
        .I4(\addr_dec_to_mb_data[3]_i_12_n_0 ),
        .I5(\addr_dec_to_mb_data[3]_i_33_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_13_n_0 ));
  LUT3 #(
    .INIT(8'h10)) 
    \addr_dec_to_mb_data[3]_i_18 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\SYNC[19].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_18_n_0 ));
  LUT4 #(
    .INIT(16'hC888)) 
    \addr_dec_to_mb_data[3]_i_19 
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[22].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[5]_i_6_1 [2]),
        .O(\addr_dec_to_mb_data[3]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FEFEFEFF)) 
    \addr_dec_to_mb_data[3]_i_2 
       (.I0(\addr_dec_to_mb_data[3]_i_4_n_0 ),
        .I1(\addr_dec_to_mb_data_reg[3] ),
        .I2(\addr_dec_to_mb_data[3]_i_6_n_0 ),
        .I3(\addr_dec_to_mb_data[3]_i_7_n_0 ),
        .I4(\addr_dec_to_mb_data[3]_i_8_n_0 ),
        .I5(\addr_dec_to_mb_data[3]_i_9_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \addr_dec_to_mb_data[3]_i_20 
       (.I0(\addr_dec_to_mb_data[2]_i_34_n_0 ),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\SYNC[4].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAA8080000)) 
    \addr_dec_to_mb_data[3]_i_21 
       (.I0(\addr_dec_to_mb_data[2]_i_7_n_0 ),
        .I1(\addr_dec_to_mb_data[3]_i_10_0 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[3]_i_10_1 ),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[3]_i_36_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_21_n_0 ));
  LUT5 #(
    .INIT(32'h0020C0E0)) 
    \addr_dec_to_mb_data[3]_i_22 
       (.I0(\SYNC[22].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[5]_i_6_1 [2]),
        .I4(\addr_dec_to_mb_data[5]_i_6_0 [2]),
        .O(\addr_dec_to_mb_data[3]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'h0000000005370505)) 
    \addr_dec_to_mb_data[3]_i_23 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[3]_i_37_n_0 ),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[3]_i_38_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_23_n_0 ));
  LUT3 #(
    .INIT(8'hEF)) 
    \addr_dec_to_mb_data[3]_i_24 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'h0000000022200020)) 
    \addr_dec_to_mb_data[3]_i_25 
       (.I0(\cal_ADR_B[31]_i_9_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_3_0 [3]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[7]_i_15_0 [3]),
        .I5(\cal_ADR_B[31]_i_10_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_25_n_0 ));
  LUT3 #(
    .INIT(8'h1F)) 
    \addr_dec_to_mb_data[3]_i_27 
       (.I0(\SYNC[12].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .O(\SYNC[12].sync_reg_reg[1]_2 ));
  LUT6 #(
    .INIT(64'h888B888888888888)) 
    \addr_dec_to_mb_data[3]_i_28 
       (.I0(\addr_dec_to_mb_data[30]_i_6_1 [2]),
        .I1(\cal_ADR_B[31]_i_8_n_0 ),
        .I2(\SYNC[10].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[11]_i_3_0 [3]),
        .I5(\SYNC[23].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_28_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF007500750075)) 
    \addr_dec_to_mb_data[3]_i_29 
       (.I0(\addr_dec_to_mb_data[3]_i_39_n_0 ),
        .I1(\SYNC[21].sync_reg_reg[1]_2 ),
        .I2(\addr_dec_to_mb_data[30]_i_6_1 [2]),
        .I3(\addr_dec_to_mb_data[0]_i_13_n_0 ),
        .I4(\addr_dec_to_mb_data[3]_i_40_n_0 ),
        .I5(\addr_dec_to_mb_data[0]_i_17_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000FFA8)) 
    \addr_dec_to_mb_data[3]_i_3 
       (.I0(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[3]_i_10_n_0 ),
        .I2(\addr_dec_to_mb_data[3]_i_11_n_0 ),
        .I3(\addr_dec_to_mb_data_reg[3] ),
        .I4(\addr_dec_to_mb_data[3]_i_12_n_0 ),
        .I5(\addr_dec_to_mb_data[3]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h4444400000004000)) 
    \addr_dec_to_mb_data[3]_i_30 
       (.I0(\addr_dec_to_mb_data[5]_i_22_n_0 ),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[22].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[5]_i_6_1 [2]),
        .I4(\SYNC[21].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[5]_i_6_0 [2]),
        .O(\addr_dec_to_mb_data[3]_i_30_n_0 ));
  LUT5 #(
    .INIT(32'hBB8B8B8B)) 
    \addr_dec_to_mb_data[3]_i_31 
       (.I0(riu2clb_valid[3]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(cal_timer_reg[3]),
        .O(\addr_dec_to_mb_data[3]_i_31_n_0 ));
  LUT6 #(
    .INIT(64'hBBAAAFAABBAAAAAA)) 
    \addr_dec_to_mb_data[3]_i_32 
       (.I0(\addr_dec_to_mb_data[3]_i_41_n_0 ),
        .I1(\addr_dec_to_mb_data[5]_i_6_0 [2]),
        .I2(\addr_dec_to_mb_data[5]_i_6_1 [2]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\SYNC[21].sync_reg [1]),
        .I5(\SYNC[22].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_32_n_0 ));
  LUT4 #(
    .INIT(16'h4000)) 
    \addr_dec_to_mb_data[3]_i_33 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(phy2clb_rd_dq_bits[3]),
        .I3(\SYNC[17].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_33_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000E200)) 
    \addr_dec_to_mb_data[3]_i_36 
       (.I0(\addr_dec_to_mb_data[31]_i_9_0 [2]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_9_0 [29]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_36_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \addr_dec_to_mb_data[3]_i_37 
       (.I0(\SYNC[22].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .I3(\SYNC[19].sync_reg [1]),
        .I4(\SYNC[9].sync_reg [1]),
        .I5(\SYNC[18].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_37_n_0 ));
  LUT4 #(
    .INIT(16'h8880)) 
    \addr_dec_to_mb_data[3]_i_38 
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[22].sync_reg [1]),
        .I3(\SYNC[21].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_38_n_0 ));
  LUT5 #(
    .INIT(32'h557FFF7F)) 
    \addr_dec_to_mb_data[3]_i_39 
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[30]_i_6_0 [2]),
        .I3(\SYNC[12].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[30]_i_6_2 [2]),
        .O(\addr_dec_to_mb_data[3]_i_39_n_0 ));
  LUT5 #(
    .INIT(32'h0000B800)) 
    \addr_dec_to_mb_data[3]_i_4 
       (.I0(\addr_dec_to_mb_data[3]_i_13_0 ),
        .I1(\SYNC[4].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[7]_i_5_0 [3]),
        .I3(\SYNC[19].sync_reg [1]),
        .I4(\SYNC[18].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \addr_dec_to_mb_data[3]_i_40 
       (.I0(douta[3]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_40_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \addr_dec_to_mb_data[3]_i_41 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[17].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_41_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFB8880000)) 
    \addr_dec_to_mb_data[3]_i_6 
       (.I0(\addr_dec_to_mb_data[30]_i_6_2 [2]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[22].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[30]_i_6_1 [2]),
        .I4(\addr_dec_to_mb_data[3]_i_18_n_0 ),
        .I5(\addr_dec_to_mb_data[3]_i_19_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFE0)) 
    \addr_dec_to_mb_data[3]_i_7 
       (.I0(\SYNC[22].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\SYNC[19].sync_reg [1]),
        .O(\addr_dec_to_mb_data[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000015001515)) 
    \addr_dec_to_mb_data[3]_i_8 
       (.I0(\addr_dec_to_mb_data[3]_i_20_n_0 ),
        .I1(\SYNC[23].sync_reg_reg[1]_2 ),
        .I2(douta[3]),
        .I3(\SYNC[9].sync_reg_reg[1]_3 ),
        .I4(\addr_dec_to_mb_data[11]_i_3_0 [3]),
        .I5(\addr_dec_to_mb_data[3]_i_21_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAAAEA)) 
    \addr_dec_to_mb_data[3]_i_9 
       (.I0(\addr_dec_to_mb_data[3]_i_22_n_0 ),
        .I1(\SYNC[19].sync_reg [1]),
        .I2(\SYNC[5].sync_reg [1]),
        .I3(\SYNC[4].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[3]_i_19_n_0 ),
        .I5(\addr_dec_to_mb_data[3]_i_23_n_0 ),
        .O(\addr_dec_to_mb_data[3]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hBBB8FFFFBBB80000)) 
    \addr_dec_to_mb_data[4]_i_1 
       (.I0(\addr_dec_to_mb_data[4]_i_2_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[4]_i_3_n_0 ),
        .I3(\addr_dec_to_mb_data[4]_i_4_n_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[4]_i_5_n_0 ),
        .O(\cal_timer_reg[31] [4]));
  LUT6 #(
    .INIT(64'hFFFFFFFF44440444)) 
    \addr_dec_to_mb_data[4]_i_10 
       (.I0(\addr_dec_to_mb_data_reg[4]_0 ),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[19].sync_reg [1]),
        .I3(\SYNC[5].sync_reg [1]),
        .I4(\SYNC[4].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[4]_i_31_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hF011F011F0FFF011)) 
    \addr_dec_to_mb_data[4]_i_11 
       (.I0(\addr_dec_to_mb_data[4]_i_3_3 ),
        .I1(\addr_dec_to_mb_data[5]_i_30_n_0 ),
        .I2(\addr_dec_to_mb_data[4]_i_3_0 ),
        .I3(\SYNC[19].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[4]_i_34_n_0 ),
        .I5(\addr_dec_to_mb_data[5]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hEAEEEAAA)) 
    \addr_dec_to_mb_data[4]_i_12 
       (.I0(\addr_dec_to_mb_data[4]_i_30_n_0 ),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[4]_i_3_2 ),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[4]_i_3_1 ),
        .O(\addr_dec_to_mb_data[4]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hDFDFDFDFDFDDDDDD)) 
    \addr_dec_to_mb_data[4]_i_13 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[4]_i_30_n_0 ),
        .I3(\SYNC[6].sync_reg [1]),
        .I4(\SYNC[21].sync_reg [1]),
        .I5(\SYNC[12].sync_reg_reg[1]_1 ),
        .O(\addr_dec_to_mb_data[4]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h88008800880F8800)) 
    \addr_dec_to_mb_data[4]_i_14 
       (.I0(\addr_dec_to_mb_data[0]_i_17_n_0 ),
        .I1(douta[4]),
        .I2(\SYNC[10].sync_reg [1]),
        .I3(\SYNC[23].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF4700FFFFFFFF)) 
    \addr_dec_to_mb_data[4]_i_15 
       (.I0(\addr_dec_to_mb_data[7]_i_15_0 [4]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_3_0 [4]),
        .I3(\addr_dec_to_mb_data[4]_i_35_n_0 ),
        .I4(\SYNC[19].sync_reg [1]),
        .I5(\SYNC[20].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFBBBFFFFFFFF)) 
    \addr_dec_to_mb_data[4]_i_16 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\cal_ADR_A[31]_i_16_n_0 ),
        .I2(\SYNC[19].sync_reg [1]),
        .I3(\SYNC[5].sync_reg [1]),
        .I4(\SYNC[4].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h8808800080008000)) 
    \addr_dec_to_mb_data[4]_i_18 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(riu2clb_valid[4]),
        .I4(cal_timer_reg[4]),
        .I5(\SYNC[3].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBBBBABAAAA)) 
    \addr_dec_to_mb_data[4]_i_2 
       (.I0(\addr_dec_to_mb_data[4]_i_6_n_0 ),
        .I1(\addr_dec_to_mb_data[4]_i_7_n_0 ),
        .I2(\addr_dec_to_mb_data[4]_i_8_n_0 ),
        .I3(\addr_dec_to_mb_data[4]_i_9_n_0 ),
        .I4(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .I5(\addr_dec_to_mb_data[4]_i_10_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h75557555FFFF7555)) 
    \addr_dec_to_mb_data[4]_i_20 
       (.I0(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I1(\SYNC[4].sync_reg [1]),
        .I2(\SYNC[5].sync_reg [1]),
        .I3(\SYNC[19].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\cal_CS_A[7]_i_14_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF4440FFFFFFFF)) 
    \addr_dec_to_mb_data[4]_i_21 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\SYNC[23].sync_reg [1]),
        .I5(\SYNC[20].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_21_n_0 ));
  LUT5 #(
    .INIT(32'hEFFFFFFF)) 
    \addr_dec_to_mb_data[4]_i_22 
       (.I0(\addr_dec_to_mb_data[4]_i_38_n_0 ),
        .I1(\SYNC[11].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\SYNC[4].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFFE200)) 
    \addr_dec_to_mb_data[4]_i_23 
       (.I0(\addr_dec_to_mb_data[4]_i_3_1 ),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[4]_i_3_2 ),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[4]_i_30_n_0 ),
        .I5(\addr_dec_to_mb_data[4]_i_39_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'hFFAACAAA00AACAAA)) 
    \addr_dec_to_mb_data[4]_i_24 
       (.I0(\addr_dec_to_mb_data[4]_i_9_n_0 ),
        .I1(\addr_dec_to_mb_data[30]_i_6_1 [3]),
        .I2(\SYNC[22].sync_reg [1]),
        .I3(\SYNC[12].sync_reg [1]),
        .I4(\SYNC[21].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[30]_i_6_2 [3]),
        .O(\addr_dec_to_mb_data[4]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000005545)) 
    \addr_dec_to_mb_data[4]_i_25 
       (.I0(\addr_dec_to_mb_data[2]_i_13_n_0 ),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[18].sync_reg [1]),
        .I5(\SYNC[19].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF55C00000)) 
    \addr_dec_to_mb_data[4]_i_26 
       (.I0(\addr_dec_to_mb_data_reg[4]_0 ),
        .I1(\addr_dec_to_mb_data[4]_i_3_0 ),
        .I2(\SYNC[19].sync_reg [1]),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[2]_i_19_n_0 ),
        .I5(\addr_dec_to_mb_data[4]_i_40_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'h0000FFFFEEEFFFFF)) 
    \addr_dec_to_mb_data[4]_i_28 
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\SYNC[6].sync_reg [1]),
        .I4(\SYNC[21].sync_reg [1]),
        .I5(\SYNC[9].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_28_n_0 ));
  LUT5 #(
    .INIT(32'h888888C8)) 
    \addr_dec_to_mb_data[4]_i_29 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\SYNC[19].sync_reg [1]),
        .I4(\SYNC[18].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAFFAE)) 
    \addr_dec_to_mb_data[4]_i_3 
       (.I0(\addr_dec_to_mb_data[4]_i_11_n_0 ),
        .I1(\addr_dec_to_mb_data[4]_i_12_n_0 ),
        .I2(\addr_dec_to_mb_data[4]_i_13_n_0 ),
        .I3(\addr_dec_to_mb_data[4]_i_14_n_0 ),
        .I4(\addr_dec_to_mb_data[4]_i_15_n_0 ),
        .I5(\addr_dec_to_mb_data[4]_i_16_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000E200)) 
    \addr_dec_to_mb_data[4]_i_30 
       (.I0(\addr_dec_to_mb_data[31]_i_9_0 [3]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_9_0 [30]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_30_n_0 ));
  LUT6 #(
    .INIT(64'hEEAFEEAAAAAAAAAA)) 
    \addr_dec_to_mb_data[4]_i_31 
       (.I0(\addr_dec_to_mb_data[4]_i_29_n_0 ),
        .I1(\addr_dec_to_mb_data[4]_i_10_0 ),
        .I2(\SYNC[5].sync_reg [1]),
        .I3(\SYNC[4].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[7]_i_5_0 [4]),
        .I5(\addr_dec_to_mb_data[2]_i_32_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_31_n_0 ));
  LUT6 #(
    .INIT(64'hBF80FFFFBF800000)) 
    \addr_dec_to_mb_data[4]_i_34 
       (.I0(\addr_dec_to_mb_data[30]_i_6_1 [3]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[4]_i_42_n_0 ),
        .I4(\SYNC[12].sync_reg_reg[1]_2 ),
        .I5(\addr_dec_to_mb_data[4]_i_11_0 ),
        .O(\addr_dec_to_mb_data[4]_i_34_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \addr_dec_to_mb_data[4]_i_35 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_35_n_0 ));
  LUT4 #(
    .INIT(16'hE0FF)) 
    \addr_dec_to_mb_data[4]_i_38 
       (.I0(\SYNC[22].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_38_n_0 ));
  LUT6 #(
    .INIT(64'hFF1D0000FFFFFFFF)) 
    \addr_dec_to_mb_data[4]_i_39 
       (.I0(\addr_dec_to_mb_data[31]_i_9_0 [3]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_9_0 [30]),
        .I3(\addr_dec_to_mb_data[3]_i_24_n_0 ),
        .I4(\SYNC[12].sync_reg_reg[1]_1 ),
        .I5(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_39_n_0 ));
  LUT6 #(
    .INIT(64'hF8F8F8F8F8FFF8F8)) 
    \addr_dec_to_mb_data[4]_i_4 
       (.I0(\addr_dec_to_mb_data_reg[4] ),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[4]_i_18_n_0 ),
        .I3(\addr_dec_to_mb_data_reg[4]_0 ),
        .I4(\SYNC[18].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[4]_i_20_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0FFEF00E0)) 
    \addr_dec_to_mb_data[4]_i_40 
       (.I0(\addr_dec_to_mb_data_reg[4] ),
        .I1(\SYNC[22].sync_reg_reg[1]_0 ),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[2]_i_18_n_0 ),
        .I4(\SYNC[3].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[4]_i_43_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_40_n_0 ));
  LUT4 #(
    .INIT(16'h1000)) 
    \addr_dec_to_mb_data[4]_i_42 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[11]_i_3_0 [4]),
        .I3(\SYNC[23].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_42_n_0 ));
  LUT4 #(
    .INIT(16'hFFDF)) 
    \addr_dec_to_mb_data[4]_i_43 
       (.I0(stop_gate_tracking_ack_reg),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[2].sync_reg [1]),
        .O(\addr_dec_to_mb_data[4]_i_43_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF510000)) 
    \addr_dec_to_mb_data[4]_i_5 
       (.I0(\addr_dec_to_mb_data[4]_i_21_n_0 ),
        .I1(\addr_dec_to_mb_data[4]_i_22_n_0 ),
        .I2(\addr_dec_to_mb_data[4]_i_23_n_0 ),
        .I3(\addr_dec_to_mb_data[4]_i_24_n_0 ),
        .I4(\addr_dec_to_mb_data[4]_i_25_n_0 ),
        .I5(\addr_dec_to_mb_data[4]_i_26_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBB888B8)) 
    \addr_dec_to_mb_data[4]_i_6 
       (.I0(phy2clb_rd_dq_bits[4]),
        .I1(\addr_dec_to_mb_data[5]_i_22_n_0 ),
        .I2(\addr_dec_to_mb_data[4]_i_11_0 ),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[5]_i_6_0 [3]),
        .I5(\addr_dec_to_mb_data[4]_i_28_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hDFDDDFFFDDDDDDDD)) 
    \addr_dec_to_mb_data[4]_i_7 
       (.I0(\addr_dec_to_mb_data[4]_i_28_n_0 ),
        .I1(\addr_dec_to_mb_data[5]_i_22_n_0 ),
        .I2(\addr_dec_to_mb_data[5]_i_6_1 [3]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[30]_i_6_1 [3]),
        .I5(\addr_dec_to_mb_data[4]_i_29_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h5555555557F7FFFF)) 
    \addr_dec_to_mb_data[4]_i_8 
       (.I0(\addr_dec_to_mb_data[2]_i_7_n_0 ),
        .I1(\addr_dec_to_mb_data[4]_i_3_1 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[4]_i_3_2 ),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[4]_i_30_n_0 ),
        .O(\addr_dec_to_mb_data[4]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hF4444444)) 
    \addr_dec_to_mb_data[4]_i_9 
       (.I0(\SYNC[9].sync_reg_reg[1]_3 ),
        .I1(\addr_dec_to_mb_data[11]_i_3_0 [4]),
        .I2(\SYNC[23].sync_reg [1]),
        .I3(\SYNC[20].sync_reg [1]),
        .I4(douta[4]),
        .O(\addr_dec_to_mb_data[4]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hB888B888B8BBB888)) 
    \addr_dec_to_mb_data[5]_i_1 
       (.I0(\addr_dec_to_mb_data[5]_i_2_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[5]_i_3_n_0 ),
        .I3(\addr_dec_to_mb_data[5]_i_4_n_0 ),
        .I4(\addr_dec_to_mb_data[5]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[5]_i_6_n_0 ),
        .O(\cal_timer_reg[31] [5]));
  LUT6 #(
    .INIT(64'h0000A808AAAAAAAA)) 
    \addr_dec_to_mb_data[5]_i_10 
       (.I0(\addr_dec_to_mb_data[2]_i_7_n_0 ),
        .I1(\addr_dec_to_mb_data[5]_i_2_1 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[5]_i_2_2 ),
        .I4(\addr_dec_to_mb_data[5]_i_26_n_0 ),
        .I5(\addr_dec_to_mb_data[5]_i_27_n_0 ),
        .O(\addr_dec_to_mb_data[5]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'h10000000)) 
    \addr_dec_to_mb_data[5]_i_11 
       (.I0(\SYNC[12].sync_reg [1]),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[21].sync_reg [1]),
        .I4(\SYNC[6].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0000E0FFF0FFF0FF)) 
    \addr_dec_to_mb_data[5]_i_12 
       (.I0(\addr_dec_to_mb_data[5]_i_28_n_0 ),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[5]_i_29_n_0 ),
        .I3(\addr_dec_to_mb_data[13]_i_10_n_0 ),
        .I4(\addr_dec_to_mb_data[11]_i_12_n_0 ),
        .I5(\addr_dec_to_mb_data[11]_i_3_0 [5]),
        .O(\addr_dec_to_mb_data[5]_i_12_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \addr_dec_to_mb_data[5]_i_13 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[9].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAABABBBA)) 
    \addr_dec_to_mb_data[5]_i_14 
       (.I0(\addr_dec_to_mb_data[5]_i_25_n_0 ),
        .I1(\addr_dec_to_mb_data[5]_i_29_n_0 ),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[5]_i_30_n_0 ),
        .I5(\addr_dec_to_mb_data[5]_i_31_n_0 ),
        .O(\addr_dec_to_mb_data[5]_i_14_n_0 ));
  LUT3 #(
    .INIT(8'h08)) 
    \addr_dec_to_mb_data[5]_i_15 
       (.I0(\cal_ADR_B[31]_i_9_n_0 ),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[5]_i_32_n_0 ),
        .O(\addr_dec_to_mb_data[5]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h7F777F7F7F777777)) 
    \addr_dec_to_mb_data[5]_i_16 
       (.I0(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[5].sync_reg [1]),
        .I3(\addr_dec_to_mb_data_reg[16] [6]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data_reg[16] [1]),
        .O(\addr_dec_to_mb_data[5]_i_16_n_0 ));
  LUT5 #(
    .INIT(32'h0008AA08)) 
    \addr_dec_to_mb_data[5]_i_18 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[5]_i_6_1 [4]),
        .I3(\SYNC[21].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[5]_i_6_0 [4]),
        .O(\addr_dec_to_mb_data[5]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h08080808FBFBFB08)) 
    \addr_dec_to_mb_data[5]_i_2 
       (.I0(\addr_dec_to_mb_data[5]_i_7_n_0 ),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[5]_i_8_n_0 ),
        .I3(\addr_dec_to_mb_data[5]_i_9_n_0 ),
        .I4(\addr_dec_to_mb_data[5]_i_10_n_0 ),
        .I5(\addr_dec_to_mb_data[5]_i_6_n_0 ),
        .O(\addr_dec_to_mb_data[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFA8FFA8A8A8FFA8)) 
    \addr_dec_to_mb_data[5]_i_20 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\SYNC[5].sync_reg [1]),
        .I5(\SYNC[4].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h4FFF4FEFFFFFFFFF)) 
    \addr_dec_to_mb_data[5]_i_21 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\cal_seq[2]_i_3_n_0 ),
        .I3(\SYNC[22].sync_reg_reg[1]_0 ),
        .I4(\SYNC[12].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[2]_i_2_n_0 ),
        .O(\addr_dec_to_mb_data[5]_i_21_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \addr_dec_to_mb_data[5]_i_22 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_22_n_0 ));
  LUT5 #(
    .INIT(32'hAA00C000)) 
    \addr_dec_to_mb_data[5]_i_24 
       (.I0(\addr_dec_to_mb_data[30]_i_6_2 [4]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[30]_i_6_1 [4]),
        .I3(\SYNC[12].sync_reg [1]),
        .I4(\SYNC[21].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF88888)) 
    \addr_dec_to_mb_data[5]_i_25 
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(\addr_dec_to_mb_data_reg[5] ),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\SYNC[22].sync_reg [1]),
        .I4(\SYNC[9].sync_reg [1]),
        .I5(\SYNC[18].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_25_n_0 ));
  LUT4 #(
    .INIT(16'hE0FF)) 
    \addr_dec_to_mb_data[5]_i_26 
       (.I0(\SYNC[22].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDFFFFFFFDFF)) 
    \addr_dec_to_mb_data[5]_i_27 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [4]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_9_0 [31]),
        .O(\addr_dec_to_mb_data[5]_i_27_n_0 ));
  LUT3 #(
    .INIT(8'h8F)) 
    \addr_dec_to_mb_data[5]_i_28 
       (.I0(\SYNC[12].sync_reg [1]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_28_n_0 ));
  LUT5 #(
    .INIT(32'h0000DFFF)) 
    \addr_dec_to_mb_data[5]_i_29 
       (.I0(\addr_dec_to_mb_data[30]_i_6_0 [3]),
        .I1(\SYNC[12].sync_reg [1]),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\SYNC[21].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[5]_i_24_n_0 ),
        .O(\addr_dec_to_mb_data[5]_i_29_n_0 ));
  LUT4 #(
    .INIT(16'hE200)) 
    \addr_dec_to_mb_data[5]_i_3 
       (.I0(cal_timer_reg[5]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(riu2clb_valid[5]),
        .I3(\SYNC[0].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \addr_dec_to_mb_data[5]_i_30 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_30_n_0 ));
  LUT6 #(
    .INIT(64'h1555000000000000)) 
    \addr_dec_to_mb_data[5]_i_31 
       (.I0(\SYNC[12].sync_reg_reg[1]_1 ),
        .I1(\SYNC[6].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\SYNC[23].sync_reg_reg[1]_2 ),
        .I5(douta[5]),
        .O(\addr_dec_to_mb_data[5]_i_31_n_0 ));
  LUT5 #(
    .INIT(32'hFF53FFFF)) 
    \addr_dec_to_mb_data[5]_i_32 
       (.I0(\addr_dec_to_mb_data[7]_i_15_0 [5]),
        .I1(\addr_dec_to_mb_data[31]_i_3_0 [5]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_32_n_0 ));
  LUT5 #(
    .INIT(32'hD0009100)) 
    \addr_dec_to_mb_data[5]_i_4 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I3(\SYNC[17].sync_reg [1]),
        .I4(\SYNC[3].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF444F)) 
    \addr_dec_to_mb_data[5]_i_5 
       (.I0(\addr_dec_to_mb_data[5]_i_11_n_0 ),
        .I1(\addr_dec_to_mb_data[5]_i_10_n_0 ),
        .I2(\addr_dec_to_mb_data[5]_i_12_n_0 ),
        .I3(\addr_dec_to_mb_data[5]_i_13_n_0 ),
        .I4(\addr_dec_to_mb_data[5]_i_14_n_0 ),
        .I5(\addr_dec_to_mb_data[5]_i_15_n_0 ),
        .O(\addr_dec_to_mb_data[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hF4F4F4F4F4FFF4F4)) 
    \addr_dec_to_mb_data[5]_i_6 
       (.I0(\addr_dec_to_mb_data[5]_i_16_n_0 ),
        .I1(\addr_dec_to_mb_data_reg[5]_0 ),
        .I2(\addr_dec_to_mb_data[5]_i_18_n_0 ),
        .I3(\addr_dec_to_mb_data_reg[5] ),
        .I4(\SYNC[19].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[5]_i_20_n_0 ),
        .O(\addr_dec_to_mb_data[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFB08080808080808)) 
    \addr_dec_to_mb_data[5]_i_7 
       (.I0(phy2clb_rd_dq_bits[5]),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[30]_i_6_0 [3]),
        .I4(\SYNC[6].sync_reg [1]),
        .I5(\SYNC[21].sync_reg [1]),
        .O(\addr_dec_to_mb_data[5]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA8)) 
    \addr_dec_to_mb_data[5]_i_8 
       (.I0(\addr_dec_to_mb_data[5]_i_21_n_0 ),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[19].sync_reg [1]),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\SYNC[12].sync_reg_reg[1]_0 ),
        .I5(\addr_dec_to_mb_data[5]_i_22_n_0 ),
        .O(\addr_dec_to_mb_data[5]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFCCCCFDDD)) 
    \addr_dec_to_mb_data[5]_i_9 
       (.I0(\addr_dec_to_mb_data[5]_i_2_0 ),
        .I1(\addr_dec_to_mb_data[5]_i_24_n_0 ),
        .I2(douta[5]),
        .I3(\SYNC[23].sync_reg_reg[1]_2 ),
        .I4(\SYNC[12].sync_reg_reg[1]_1 ),
        .I5(\addr_dec_to_mb_data[5]_i_25_n_0 ),
        .O(\addr_dec_to_mb_data[5]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBABAAABAAABAA)) 
    \addr_dec_to_mb_data[6]_i_1 
       (.I0(\addr_dec_to_mb_data[6]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data_reg[6] ),
        .I2(\addr_dec_to_mb_data[7]_i_2_n_0 ),
        .I3(\addr_dec_to_mb_data[6]_i_4_n_0 ),
        .I4(\addr_dec_to_mb_data[6]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[7]_i_6_n_0 ),
        .O(\cal_timer_reg[31] [6]));
  LUT6 #(
    .INIT(64'h5555000100010001)) 
    \addr_dec_to_mb_data[6]_i_10 
       (.I0(\SYNC[12].sync_reg_reg[1]_1 ),
        .I1(\addr_dec_to_mb_data[5]_i_13_n_0 ),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[6]_i_15_n_0 ),
        .I4(douta[6]),
        .I5(\SYNC[23].sync_reg_reg[1]_2 ),
        .O(\addr_dec_to_mb_data[6]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0A08AAA8AAA8AAA8)) 
    \addr_dec_to_mb_data[6]_i_11 
       (.I0(\addr_dec_to_mb_data[6]_i_16_n_0 ),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[6]_i_17_n_0 ),
        .I4(douta[6]),
        .I5(\addr_dec_to_mb_data[0]_i_17_n_0 ),
        .O(\addr_dec_to_mb_data[6]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'h0000FF75)) 
    \addr_dec_to_mb_data[6]_i_12 
       (.I0(\addr_dec_to_mb_data[6]_i_9_n_0 ),
        .I1(\SYNC[12].sync_reg_reg[1]_0 ),
        .I2(\addr_dec_to_mb_data[30]_i_6_0 [4]),
        .I3(\addr_dec_to_mb_data[6]_i_18_n_0 ),
        .I4(\addr_dec_to_mb_data[7]_i_19_n_0 ),
        .O(\addr_dec_to_mb_data[6]_i_12_n_0 ));
  LUT3 #(
    .INIT(8'hDF)) 
    \addr_dec_to_mb_data[6]_i_15 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[11]_i_3_0 [6]),
        .O(\addr_dec_to_mb_data[6]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFABFBFFFFFFFF)) 
    \addr_dec_to_mb_data[6]_i_16 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[31]_i_3_0 [6]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[7]_i_15_0 [6]),
        .I4(\SYNC[10].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[7]_i_24_n_0 ),
        .O(\addr_dec_to_mb_data[6]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hF7F7F7FFFFFFF7FF)) 
    \addr_dec_to_mb_data[6]_i_17 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[11].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [5]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_9_0 [32]),
        .O(\addr_dec_to_mb_data[6]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h0000400000000000)) 
    \addr_dec_to_mb_data[6]_i_18 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[6]_i_24_n_0 ),
        .I2(\addr_dec_to_mb_data[0]_i_17_n_0 ),
        .I3(\addr_dec_to_mb_data[11]_i_3_0 [6]),
        .I4(\SYNC[10].sync_reg [1]),
        .I5(\SYNC[23].sync_reg [1]),
        .O(\addr_dec_to_mb_data[6]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFE200E2)) 
    \addr_dec_to_mb_data[6]_i_2 
       (.I0(cal_timer_reg[6]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(phy2clb_rd_dq_bits[6]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(riu2clb_valid[6]),
        .I5(\addr_dec_to_mb_data[7]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[6]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h40)) 
    \addr_dec_to_mb_data[6]_i_20 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_7 ));
  LUT3 #(
    .INIT(8'h80)) 
    \addr_dec_to_mb_data[6]_i_21 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .O(\SYNC[1].sync_reg_reg[1]_3 ));
  LUT3 #(
    .INIT(8'h01)) 
    \addr_dec_to_mb_data[6]_i_24 
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[20].sync_reg [1]),
        .O(\addr_dec_to_mb_data[6]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBBBBBABBBB)) 
    \addr_dec_to_mb_data[6]_i_4 
       (.I0(\addr_dec_to_mb_data[6]_i_7_n_0 ),
        .I1(\addr_dec_to_mb_data[7]_i_9_n_0 ),
        .I2(\addr_dec_to_mb_data[6]_i_8_n_0 ),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[6]_i_9_n_0 ),
        .I5(\addr_dec_to_mb_data[6]_i_10_n_0 ),
        .O(\addr_dec_to_mb_data[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0F04)) 
    \addr_dec_to_mb_data[6]_i_5 
       (.I0(\addr_dec_to_mb_data[6]_i_11_n_0 ),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[19].sync_reg [1]),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[6]_i_7_n_0 ),
        .I5(\addr_dec_to_mb_data[6]_i_12_n_0 ),
        .O(\addr_dec_to_mb_data[6]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFAAAEAEAAAAAAAA)) 
    \addr_dec_to_mb_data[6]_i_7 
       (.I0(\addr_dec_to_mb_data[5]_i_20_n_0 ),
        .I1(\addr_dec_to_mb_data[7]_i_5_0 [5]),
        .I2(\SYNC[5].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[6]_i_4_0 ),
        .I4(\SYNC[4].sync_reg [1]),
        .I5(\SYNC[19].sync_reg [1]),
        .O(\addr_dec_to_mb_data[6]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFF000000FF00B800)) 
    \addr_dec_to_mb_data[6]_i_8 
       (.I0(\addr_dec_to_mb_data[31]_i_9_0 [32]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_9_0 [5]),
        .I3(lrdimm_cmp_en_i_3_n_0),
        .I4(\addr_dec_to_mb_data[7]_i_17_n_0 ),
        .I5(\addr_dec_to_mb_data[7]_i_18_n_0 ),
        .O(\addr_dec_to_mb_data[6]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'h4F7F7F7F)) 
    \addr_dec_to_mb_data[6]_i_9 
       (.I0(\addr_dec_to_mb_data[30]_i_6_2 [5]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\SYNC[22].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[30]_i_6_1 [5]),
        .O(\addr_dec_to_mb_data[6]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0F0F0FFF4F4F4)) 
    \addr_dec_to_mb_data[7]_i_1 
       (.I0(\addr_dec_to_mb_data[7]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[7]_i_3_n_0 ),
        .I2(\addr_dec_to_mb_data[7]_i_4_n_0 ),
        .I3(\addr_dec_to_mb_data[7]_i_5_n_0 ),
        .I4(\addr_dec_to_mb_data[7]_i_6_n_0 ),
        .I5(\addr_dec_to_mb_data_reg[7] ),
        .O(\cal_timer_reg[31] [7]));
  LUT6 #(
    .INIT(64'hFF000000FF00B800)) 
    \addr_dec_to_mb_data[7]_i_10 
       (.I0(\addr_dec_to_mb_data[31]_i_9_0 [33]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_9_0 [6]),
        .I3(lrdimm_cmp_en_i_3_n_0),
        .I4(\addr_dec_to_mb_data[7]_i_17_n_0 ),
        .I5(\addr_dec_to_mb_data[7]_i_18_n_0 ),
        .O(\addr_dec_to_mb_data[7]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'hB0808080)) 
    \addr_dec_to_mb_data[7]_i_11 
       (.I0(\addr_dec_to_mb_data[30]_i_6_2 [6]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\SYNC[22].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[30]_i_6_1 [6]),
        .O(\addr_dec_to_mb_data[7]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h1F00000000000000)) 
    \addr_dec_to_mb_data[7]_i_12 
       (.I0(\SYNC[22].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\SYNC[23].sync_reg [1]),
        .I4(\SYNC[20].sync_reg [1]),
        .I5(douta[7]),
        .O(\addr_dec_to_mb_data[7]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h89DDFFFFFFFFFFFF)) 
    \addr_dec_to_mb_data[7]_i_13 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[3].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\SYNC[17].sync_reg [1]),
        .O(\addr_dec_to_mb_data[7]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFF0080)) 
    \addr_dec_to_mb_data[7]_i_14 
       (.I0(\addr_dec_to_mb_data[30]_i_6_0 [5]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\SYNC[12].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[7]_i_11_n_0 ),
        .I5(\addr_dec_to_mb_data[7]_i_19_n_0 ),
        .O(\addr_dec_to_mb_data[7]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h0A08AAA8AAA8AAA8)) 
    \addr_dec_to_mb_data[7]_i_15 
       (.I0(\addr_dec_to_mb_data[7]_i_20_n_0 ),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[7]_i_21_n_0 ),
        .I4(douta[7]),
        .I5(\addr_dec_to_mb_data[0]_i_17_n_0 ),
        .O(\addr_dec_to_mb_data[7]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'h00008000)) 
    \addr_dec_to_mb_data[7]_i_17 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[4].sync_reg [1]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[7]_i_17_n_0 ));
  LUT4 #(
    .INIT(16'hEFFF)) 
    \addr_dec_to_mb_data[7]_i_18 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[9].sync_reg [1]),
        .O(\addr_dec_to_mb_data[7]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF000E0000)) 
    \addr_dec_to_mb_data[7]_i_19 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[5]_i_30_n_0 ),
        .I5(\SYNC[19].sync_reg [1]),
        .O(\addr_dec_to_mb_data[7]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAFBAAAA)) 
    \addr_dec_to_mb_data[7]_i_2 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[3].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\SYNC[1].sync_reg [1]),
        .O(\addr_dec_to_mb_data[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFABFBFFFFFFFF)) 
    \addr_dec_to_mb_data[7]_i_20 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[31]_i_3_0 [7]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[7]_i_15_0 [7]),
        .I4(\SYNC[10].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[7]_i_24_n_0 ),
        .O(\addr_dec_to_mb_data[7]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF1DFFFFFF)) 
    \addr_dec_to_mb_data[7]_i_21 
       (.I0(\addr_dec_to_mb_data[31]_i_9_0 [6]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[31]_i_9_0 [33]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\addr_dec_to_mb_data[7]_i_21_n_0 ));
  LUT4 #(
    .INIT(16'hDDD5)) 
    \addr_dec_to_mb_data[7]_i_23 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[22].sync_reg [1]),
        .I3(\SYNC[21].sync_reg [1]),
        .O(\SYNC[18].sync_reg_reg[1]_2 ));
  LUT3 #(
    .INIT(8'h04)) 
    \addr_dec_to_mb_data[7]_i_24 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[7]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBBBBBBBBBA)) 
    \addr_dec_to_mb_data[7]_i_3 
       (.I0(\addr_dec_to_mb_data[7]_i_8_n_0 ),
        .I1(\addr_dec_to_mb_data[7]_i_9_n_0 ),
        .I2(\addr_dec_to_mb_data[7]_i_10_n_0 ),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[7]_i_11_n_0 ),
        .I5(\addr_dec_to_mb_data[7]_i_12_n_0 ),
        .O(\addr_dec_to_mb_data[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFE200E2)) 
    \addr_dec_to_mb_data[7]_i_4 
       (.I0(cal_timer_reg[7]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(phy2clb_rd_dq_bits[7]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(riu2clb_valid[7]),
        .I5(\addr_dec_to_mb_data[7]_i_13_n_0 ),
        .O(\addr_dec_to_mb_data[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFCFCFEFEFCFCFFFE)) 
    \addr_dec_to_mb_data[7]_i_5 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[7]_i_8_n_0 ),
        .I2(\addr_dec_to_mb_data[7]_i_14_n_0 ),
        .I3(\SYNC[20].sync_reg [1]),
        .I4(\SYNC[19].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[7]_i_15_n_0 ),
        .O(\addr_dec_to_mb_data[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAA00222AAAAAAAAA)) 
    \addr_dec_to_mb_data[7]_i_6 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I2(\SYNC[3].sync_reg [1]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\SYNC[17].sync_reg [1]),
        .O(\addr_dec_to_mb_data[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBB3F3B3B3B)) 
    \addr_dec_to_mb_data[7]_i_8 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .I2(\SYNC[5].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[7]_i_5_0 [6]),
        .I4(\SYNC[19].sync_reg [1]),
        .I5(\SYNC[4].sync_reg [1]),
        .O(\addr_dec_to_mb_data[7]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hAABAAAAA)) 
    \addr_dec_to_mb_data[7]_i_9 
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\SYNC[23].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[7]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFD00)) 
    \addr_dec_to_mb_data[8]_i_1 
       (.I0(\addr_dec_to_mb_data[8]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[8]_i_3_n_0 ),
        .I2(\addr_dec_to_mb_data[8]_i_4_n_0 ),
        .I3(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I4(\addr_dec_to_mb_data[8]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[8]_i_6_n_0 ),
        .O(\cal_timer_reg[31] [8]));
  LUT6 #(
    .INIT(64'h4444555500001555)) 
    \addr_dec_to_mb_data[8]_i_10 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\SYNC[6].sync_reg [1]),
        .I4(\SYNC[12].sync_reg_reg[1]_1 ),
        .I5(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[8]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFBBBAFAFA)) 
    \addr_dec_to_mb_data[8]_i_11 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[12].sync_reg_reg[1]_1 ),
        .I3(\addr_dec_to_mb_data[8]_i_19_n_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\SYNC[20].sync_reg [1]),
        .O(\addr_dec_to_mb_data[8]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFF00202000002020)) 
    \addr_dec_to_mb_data[8]_i_12 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[11]_i_3_0 [7]),
        .I3(\addr_dec_to_mb_data[8]_i_16_n_0 ),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\addr_dec_to_mb_data[8]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAAAA0C00AAAA0000)) 
    \addr_dec_to_mb_data[8]_i_13 
       (.I0(douta[8]),
        .I1(\addr_dec_to_mb_data[31]_i_3_0 [8]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\SYNC[23].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .O(\addr_dec_to_mb_data[8]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \addr_dec_to_mb_data[8]_i_15 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .O(\addr_dec_to_mb_data[8]_i_15_n_0 ));
  LUT4 #(
    .INIT(16'h5540)) 
    \addr_dec_to_mb_data[8]_i_16 
       (.I0(\addr_dec_to_mb_data[8]_i_21_n_0 ),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[30]_i_6_1 [7]),
        .I3(\SYNC[21].sync_reg [1]),
        .O(\addr_dec_to_mb_data[8]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h0000A280AAAAA280)) 
    \addr_dec_to_mb_data[8]_i_17 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[12].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[30]_i_6_2 [7]),
        .I3(\addr_dec_to_mb_data[30]_i_6_0 [6]),
        .I4(\SYNC[0].sync_reg_reg[1]_3 ),
        .I5(\addr_dec_to_mb_data[8]_i_8_0 ),
        .O(\addr_dec_to_mb_data[8]_i_17_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \addr_dec_to_mb_data[8]_i_18 
       (.I0(\SYNC[12].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[22].sync_reg [1]),
        .O(\SYNC[12].sync_reg_reg[1]_1 ));
  LUT2 #(
    .INIT(4'h8)) 
    \addr_dec_to_mb_data[8]_i_19 
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .O(\addr_dec_to_mb_data[8]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF1110)) 
    \addr_dec_to_mb_data[8]_i_2 
       (.I0(\addr_dec_to_mb_data[8]_i_7_n_0 ),
        .I1(\addr_dec_to_mb_data[8]_i_8_n_0 ),
        .I2(\addr_dec_to_mb_data[13]_i_9_n_0 ),
        .I3(\addr_dec_to_mb_data[8]_i_9_n_0 ),
        .I4(\addr_dec_to_mb_data[8]_i_10_n_0 ),
        .I5(\SYNC[9].sync_reg [1]),
        .O(\addr_dec_to_mb_data[8]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h07F70F0F)) 
    \addr_dec_to_mb_data[8]_i_21 
       (.I0(\addr_dec_to_mb_data[30]_i_6_0 [6]),
        .I1(\SYNC[6].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[30]_i_6_2 [7]),
        .I4(\SYNC[21].sync_reg [1]),
        .O(\addr_dec_to_mb_data[8]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'hF4FFF44444444444)) 
    \addr_dec_to_mb_data[8]_i_3 
       (.I0(\addr_dec_to_mb_data[8]_i_11_n_0 ),
        .I1(\addr_dec_to_mb_data[8]_i_12_n_0 ),
        .I2(\addr_dec_to_mb_data[31]_i_9_0 [34]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[31]_i_9_0 [7]),
        .I5(\SYNC[9].sync_reg_reg[1]_2 ),
        .O(\addr_dec_to_mb_data[8]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h02000202)) 
    \addr_dec_to_mb_data[8]_i_4 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[8]_i_13_n_0 ),
        .I4(\addr_dec_to_mb_data[8]_i_9_n_0 ),
        .O(\addr_dec_to_mb_data[8]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h0000B800)) 
    \addr_dec_to_mb_data[8]_i_5 
       (.I0(riu2clb_valid[8]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(cal_timer_reg[8]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[9]_i_11_n_0 ),
        .O(\addr_dec_to_mb_data[8]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000A808AAAAA808)) 
    \addr_dec_to_mb_data[8]_i_6 
       (.I0(\addr_dec_to_mb_data[19]_i_14_n_0 ),
        .I1(\addr_dec_to_mb_data_reg[16] [2]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data_reg[16] [7]),
        .I4(\SYNC[5].sync_reg [1]),
        .I5(\addr_dec_to_mb_data_reg[8] ),
        .O(\addr_dec_to_mb_data[8]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \addr_dec_to_mb_data[8]_i_7 
       (.I0(\cal_seq[2]_i_3_n_0 ),
        .I1(\addr_dec_to_mb_data[31]_i_3_0 [8]),
        .I2(\addr_dec_to_mb_data[29]_i_8_n_0 ),
        .I3(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[8]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFDFD00000)) 
    \addr_dec_to_mb_data[8]_i_8 
       (.I0(\addr_dec_to_mb_data[8]_i_15_n_0 ),
        .I1(\cal_ADR_B[31]_i_10_n_0 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[12].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[8]_i_16_n_0 ),
        .I5(\addr_dec_to_mb_data[8]_i_17_n_0 ),
        .O(\addr_dec_to_mb_data[8]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hCFFFDFFFFFFFDFFF)) 
    \addr_dec_to_mb_data[8]_i_9 
       (.I0(\addr_dec_to_mb_data[8]_i_4_0 ),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[8]_i_4_1 ),
        .O(\addr_dec_to_mb_data[8]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFB00)) 
    \addr_dec_to_mb_data[9]_i_1 
       (.I0(\addr_dec_to_mb_data[9]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[9]_i_3_n_0 ),
        .I2(\addr_dec_to_mb_data[9]_i_4_n_0 ),
        .I3(\addr_dec_to_mb_data[19]_i_5_n_0 ),
        .I4(\addr_dec_to_mb_data[9]_i_5_n_0 ),
        .I5(\addr_dec_to_mb_data[9]_i_6_n_0 ),
        .O(\cal_timer_reg[31] [9]));
  LUT6 #(
    .INIT(64'hFFFF1CFFFFFFFFFF)) 
    \addr_dec_to_mb_data[9]_i_11 
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[17].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_4_n_0 ),
        .O(\addr_dec_to_mb_data[9]_i_11_n_0 ));
  LUT3 #(
    .INIT(8'h08)) 
    \addr_dec_to_mb_data[9]_i_12 
       (.I0(\addr_dec_to_mb_data[11]_i_12_n_0 ),
        .I1(\addr_dec_to_mb_data[11]_i_3_0 [8]),
        .I2(\SYNC[20].sync_reg [1]),
        .O(\addr_dec_to_mb_data[9]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h2220222222222222)) 
    \addr_dec_to_mb_data[9]_i_14 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\addr_dec_to_mb_data[31]_i_3_0 [9]),
        .O(\addr_dec_to_mb_data[9]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'hA808)) 
    \addr_dec_to_mb_data[9]_i_2 
       (.I0(\SYNC[9].sync_reg_reg[1]_2 ),
        .I1(\addr_dec_to_mb_data[31]_i_9_0 [8]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data[31]_i_9_0 [35]),
        .O(\addr_dec_to_mb_data[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFD0FF)) 
    \addr_dec_to_mb_data[9]_i_3 
       (.I0(\addr_dec_to_mb_data[31]_i_3_0 [9]),
        .I1(\addr_dec_to_mb_data[19]_i_7_n_0 ),
        .I2(\addr_dec_to_mb_data[9]_i_7_n_0 ),
        .I3(lrdimm_cmp_en_i_3_n_0),
        .I4(\SYNC[22].sync_reg [1]),
        .I5(\SYNC[21].sync_reg [1]),
        .O(\addr_dec_to_mb_data[9]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5454545544444444)) 
    \addr_dec_to_mb_data[9]_i_4 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\addr_dec_to_mb_data[9]_i_8_n_0 ),
        .I2(\addr_dec_to_mb_data[9]_i_9_n_0 ),
        .I3(\addr_dec_to_mb_data[13]_i_9_n_0 ),
        .I4(\addr_dec_to_mb_data[9]_i_7_n_0 ),
        .I5(lrdimm_cmp_en_i_3_n_0),
        .O(\addr_dec_to_mb_data[9]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAA8080000A808)) 
    \addr_dec_to_mb_data[9]_i_5 
       (.I0(\addr_dec_to_mb_data[19]_i_14_n_0 ),
        .I1(\addr_dec_to_mb_data_reg[16] [3]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\addr_dec_to_mb_data_reg[16] [8]),
        .I4(\SYNC[5].sync_reg [1]),
        .I5(\addr_dec_to_mb_data_reg[9] ),
        .O(\addr_dec_to_mb_data[9]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h0000B800)) 
    \addr_dec_to_mb_data[9]_i_6 
       (.I0(riu2clb_valid[9]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(cal_timer_reg[9]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\addr_dec_to_mb_data[9]_i_11_n_0 ),
        .O(\addr_dec_to_mb_data[9]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h35FFFFFF)) 
    \addr_dec_to_mb_data[9]_i_7 
       (.I0(\addr_dec_to_mb_data[9]_i_3_0 ),
        .I1(\addr_dec_to_mb_data[9]_i_3_1 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .O(\addr_dec_to_mb_data[9]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFF40FF40FFFFFFF0)) 
    \addr_dec_to_mb_data[9]_i_8 
       (.I0(\addr_dec_to_mb_data[11]_i_13_n_0 ),
        .I1(\addr_dec_to_mb_data[11]_i_3_0 [8]),
        .I2(\addr_dec_to_mb_data[19]_i_13_n_0 ),
        .I3(\addr_dec_to_mb_data[9]_i_12_n_0 ),
        .I4(\addr_dec_to_mb_data[29]_i_3_n_0 ),
        .I5(\addr_dec_to_mb_data[9]_i_4_0 ),
        .O(\addr_dec_to_mb_data[9]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h0100)) 
    \addr_dec_to_mb_data[9]_i_9 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[11].sync_reg [1]),
        .I2(\addr_dec_to_mb_data[9]_i_14_n_0 ),
        .I3(\SYNC[8].sync_reg [1]),
        .O(\addr_dec_to_mb_data[9]_i_9_n_0 ));
  MUXF7 \addr_dec_to_mb_data_reg[3]_i_1 
       (.I0(\addr_dec_to_mb_data[3]_i_2_n_0 ),
        .I1(\addr_dec_to_mb_data[3]_i_3_n_0 ),
        .O(\cal_timer_reg[31] [3]),
        .S(\SYNC[0].sync_reg [1]));
  LUT6 #(
    .INIT(64'h0000000080000000)) 
    \bisc_bit[3]_i_1 
       (.I0(io_addr_strobe),
        .I1(out),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\SYNC[2].sync_reg [1]),
        .O(io_addr_strobe_reg));
  LUT6 #(
    .INIT(64'h0222222200000000)) 
    calDone_i_1
       (.I0(calDone_i_2_n_0),
        .I1(calDone_i_3_n_0),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(calDone_i_4_n_0),
        .O(\SYNC[17].sync_reg_reg[1]_1 ));
  LUT6 #(
    .INIT(64'h6666626666FF63FF)) 
    calDone_i_2
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[3].sync_reg [1]),
        .I3(\SYNC[17].sync_reg [1]),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(\SYNC[8].sync_reg [1]),
        .O(calDone_i_2_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF77777)) 
    calDone_i_3
       (.I0(out),
        .I1(io_addr_strobe),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(calDone_i_5_n_0),
        .O(calDone_i_3_n_0));
  LUT4 #(
    .INIT(16'hAF8F)) 
    calDone_i_4
       (.I0(\SYNC[5].sync_reg [1]),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\SYNC[18].sync_reg [1]),
        .I3(\SYNC[6].sync_reg [1]),
        .O(calDone_i_4_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFDFFFF)) 
    calDone_i_5
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\SYNC[19].sync_reg [1]),
        .I4(\SYNC[23].sync_reg [1]),
        .I5(\SYNC[20].sync_reg [1]),
        .O(calDone_i_5_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    \cal_ACT_n_A[7]_i_1 
       (.I0(\SYNC[21].sync_reg_reg[1]_1 ),
        .I1(xsdb_wr_en_reg),
        .O(rst_r1_reg_0));
  LUT6 #(
    .INIT(64'h00000000FFFFFFB8)) 
    \cal_ADR_A[31]_i_1 
       (.I0(\cal_ADR_A[31]_i_2_n_0 ),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\cal_ADR_A[31]_i_3_n_0 ),
        .I3(\cal_ADR_A[31]_i_4_n_0 ),
        .I4(\cal_ADR_A[31]_i_5_n_0 ),
        .I5(\cal_ADR_A[31]_i_6_n_0 ),
        .O(\SYNC[20].sync_reg_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h00000000EFEFFFEF)) 
    \cal_ADR_A[31]_i_10 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\cal_ADR_A[31]_i_23_n_0 ),
        .O(\cal_ADR_A[31]_i_10_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \cal_ADR_A[31]_i_11 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\SYNC[6].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EC202020)) 
    \cal_ADR_A[31]_i_12 
       (.I0(\cal_cmp_en[7]_i_2_n_0 ),
        .I1(\SYNC[6].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\cal_ADR_A[31]_i_16_n_0 ),
        .I4(stop_gate_tracking_ack_i_2_n_0),
        .I5(\cal_CS_B[7]_i_14_n_0 ),
        .O(\cal_ADR_A[31]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAABBEBBBEF)) 
    \cal_ADR_A[31]_i_13 
       (.I0(\cal_ADR_A[31]_i_24_n_0 ),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\SYNC[17].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h0000DDD000000000)) 
    \cal_ADR_A[31]_i_14 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hF7F4F7F40000F706)) 
    \cal_ADR_A[31]_i_15 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(\cal_ADR_A[31]_i_25_n_0 ),
        .I5(\SYNC[10].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_15_n_0 ));
  LUT3 #(
    .INIT(8'h1F)) 
    \cal_ADR_A[31]_i_16 
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h0000005700000000)) 
    \cal_ADR_A[31]_i_17 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\SYNC[6].sync_reg [1]),
        .I5(\SYNC[1].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hD900DB00FFFFFFFF)) 
    \cal_ADR_A[31]_i_18 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[17].sync_reg [1]),
        .I4(\SYNC[3].sync_reg [1]),
        .I5(\cal_ADR_A[31]_i_26_n_0 ),
        .O(\cal_ADR_A[31]_i_18_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cal_ADR_A[31]_i_19 
       (.I0(\SYNC[5].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'h88808880BBBF8880)) 
    \cal_ADR_A[31]_i_2 
       (.I0(\cal_ADR_A[31]_i_7_n_0 ),
        .I1(\SYNC[11].sync_reg [1]),
        .I2(\cal_ADR_A[31]_i_8_n_0 ),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\cal_ADR_A[31]_i_9_n_0 ),
        .I5(\cal_ADR_A[31]_i_10_n_0 ),
        .O(\cal_ADR_A[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h020002000300FFF0)) 
    \cal_ADR_A[31]_i_20 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\SYNC[3].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\cal_ADR_B[31]_i_10_n_0 ),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\cal_ADR_A[31]_i_19_n_0 ),
        .O(\cal_ADR_A[31]_i_20_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \cal_ADR_A[31]_i_21 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[3].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAA0020)) 
    \cal_ADR_A[31]_i_22 
       (.I0(\cal_ADR_A[31]_i_23_n_0 ),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\SYNC[6].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'h0F0F9FDFFF0F0F0F)) 
    \cal_ADR_A[31]_i_23 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'h55554444000F0000)) 
    \cal_ADR_A[31]_i_24 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[3].sync_reg [1]),
        .I2(\SYNC[10].sync_reg [1]),
        .I3(\SYNC[17].sync_reg [1]),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_24_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \cal_ADR_A[31]_i_25 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_25_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cal_ADR_A[31]_i_26 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF33003700)) 
    \cal_ADR_A[31]_i_3 
       (.I0(\cplx_config[16]_i_8_n_0 ),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\cal_ADR_A[31]_i_11_n_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\cal_ADR_A[31]_i_12_n_0 ),
        .O(\cal_ADR_A[31]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hA8A8A8A8A8A8A8AA)) 
    \cal_ADR_A[31]_i_4 
       (.I0(\cal_ADR_A[31]_i_11_n_0 ),
        .I1(\cal_ADR_A[31]_i_13_n_0 ),
        .I2(\cal_ADR_A[31]_i_14_n_0 ),
        .I3(\cal_ADR_A[31]_i_15_n_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\SYNC[2].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAAAA0080AAAAAAAA)) 
    \cal_ADR_A[31]_i_5 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(stop_gate_tracking_ack_i_2_n_0),
        .I2(\cal_ADR_A[31]_i_16_n_0 ),
        .I3(\cal_DMOut_n_A[31]_i_2_n_0 ),
        .I4(\cal_ADR_A[31]_i_17_n_0 ),
        .I5(\cal_ADR_A[31]_i_18_n_0 ),
        .O(\cal_ADR_A[31]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFEFFFFFF)) 
    \cal_ADR_A[31]_i_6 
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(\cal_cs_pos_reg[1] ),
        .I2(\cal_DQOut_A[63]_i_2_n_0 ),
        .I3(\SYNC[21].sync_reg [1]),
        .I4(\SYNC[12].sync_reg [1]),
        .I5(\SYNC[9].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000001500000000)) 
    \cal_ADR_A[31]_i_7 
       (.I0(\cal_ADR_A[31]_i_19_n_0 ),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[3].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(stop_gate_tracking_ack_i_2_n_0),
        .O(\cal_ADR_A[31]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \cal_ADR_A[31]_i_8 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h222EFFFF22222222)) 
    \cal_ADR_A[31]_i_9 
       (.I0(\cal_ADR_A[31]_i_20_n_0 ),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\cal_ADR_A[31]_i_21_n_0 ),
        .I3(\SYNC[6].sync_reg [1]),
        .I4(\cal_ADR_A[31]_i_22_n_0 ),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\cal_ADR_A[31]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000000002AA)) 
    \cal_ADR_B[31]_i_1 
       (.I0(\cal_ADR_B[31]_i_2_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\cal_DQPat_A[63]_i_2_n_0 ),
        .I3(\SYNC[6].sync_reg [1]),
        .I4(\cal_ADR_B[31]_i_3_n_0 ),
        .I5(\cal_ADR_B[31]_i_4_n_0 ),
        .O(\SYNC[1].sync_reg_reg[1]_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \cal_ADR_B[31]_i_10 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .O(\cal_ADR_B[31]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEAEAAAEA)) 
    \cal_ADR_B[31]_i_2 
       (.I0(\cal_ADR_B[31]_i_5_n_0 ),
        .I1(\cal_ADR_B[31]_i_6_n_0 ),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\cal_ADR_B[31]_i_7_n_0 ),
        .O(\cal_ADR_B[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFDDDDDDD)) 
    \cal_ADR_B[31]_i_3 
       (.I0(\cal_ADR_B[31]_i_8_n_0 ),
        .I1(\cal_DQOut_post[63]_i_2_n_0 ),
        .I2(lrdimm_cmp_en_i_3_n_0),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\cal_cs_pos_reg[1] ),
        .O(\cal_ADR_B[31]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBBFBBBBBBB)) 
    \cal_ADR_B[31]_i_4 
       (.I0(\cplx_config[0]_i_5_n_0 ),
        .I1(calDone_i_4_n_0),
        .I2(\cal_ADR_B[31]_i_9_n_0 ),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[10].sync_reg [1]),
        .I5(\SYNC[8].sync_reg [1]),
        .O(\cal_ADR_B[31]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0405040404550455)) 
    \cal_ADR_B[31]_i_5 
       (.I0(lrdimm_cmp_clr_i_2_n_0),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\cal_cmp_en[7]_i_5_n_0 ),
        .I4(\cal_CS_A[7]_i_14_n_0 ),
        .I5(\SYNC[17].sync_reg [1]),
        .O(\cal_ADR_B[31]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \cal_ADR_B[31]_i_6 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .O(\cal_ADR_B[31]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAA20AAAAAA2020AA)) 
    \cal_ADR_B[31]_i_7 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[3].sync_reg [1]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\cal_ADR_B[31]_i_10_n_0 ),
        .O(\cal_ADR_B[31]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \cal_ADR_B[31]_i_8 
       (.I0(\SYNC[22].sync_reg [1]),
        .I1(\SYNC[12].sync_reg [1]),
        .O(\cal_ADR_B[31]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \cal_ADR_B[31]_i_9 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .O(\cal_ADR_B[31]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAEA0000)) 
    \cal_CS_A[7]_i_1 
       (.I0(\cal_CS_A[7]_i_2_n_0 ),
        .I1(\cal_CS_A[7]_i_3_n_0 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[6].sync_reg [1]),
        .I4(\SYNC[9].sync_reg [1]),
        .I5(\cal_RST_CKE_ODT_PAR[31]_i_4_n_0 ),
        .O(\SYNC[0].sync_reg_reg[1]_1 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \cal_CS_A[7]_i_10 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[3].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .O(\cal_CS_A[7]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFEEEEEEE)) 
    \cal_CS_A[7]_i_11 
       (.I0(\cal_DQOut_post[63]_i_2_n_0 ),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(lrdimm_cmp_en_i_3_n_0),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\clb2phy_wrcs0_low[31]_i_6_n_0 ),
        .O(\cal_CS_A[7]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0000000F008F008F)) 
    \cal_CS_A[7]_i_12 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\cal_CS_A[7]_i_18_n_0 ),
        .I2(\cal_CS_A[7]_i_19_n_0 ),
        .I3(lrdimm_cmp_en_i_3_n_0),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\cal_CS_B[7]_i_14_n_0 ),
        .O(\cal_CS_A[7]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFCFCAFAFAF0C)) 
    \cal_CS_A[7]_i_13 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(\SYNC[1].sync_reg [1]),
        .O(\cal_CS_A[7]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \cal_CS_A[7]_i_14 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[3].sync_reg [1]),
        .O(\cal_CS_A[7]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h3033222233332222)) 
    \cal_CS_A[7]_i_15 
       (.I0(\SYNC[24].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[20].sync_reg [1]),
        .I5(\cal_CS_A[7]_i_20_n_0 ),
        .O(\cal_CS_A[7]_i_15_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \cal_CS_A[7]_i_16 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .O(\cal_CS_A[7]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h00007F00FFFFFFFF)) 
    \cal_CS_A[7]_i_17 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[10].sync_reg [1]),
        .I3(\SYNC[20].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .I5(\cal_RST_CKE_ODT_PAR[31]_i_3_n_0 ),
        .O(\cal_CS_A[7]_i_17_n_0 ));
  LUT4 #(
    .INIT(16'h0057)) 
    \cal_CS_A[7]_i_18 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[3].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .O(\cal_CS_A[7]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF2FFFFFFF2F2)) 
    \cal_CS_A[7]_i_19 
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[6].sync_reg [1]),
        .I5(\SYNC[18].sync_reg [1]),
        .O(\cal_CS_A[7]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFFFAAAB)) 
    \cal_CS_A[7]_i_2 
       (.I0(\cal_CS_A[7]_i_4_n_0 ),
        .I1(\cal_DMOut_n_A[31]_i_2_n_0 ),
        .I2(\cal_CS_A[7]_i_5_n_0 ),
        .I3(\cal_CS_A[7]_i_6_n_0 ),
        .I4(\cal_CS_A[7]_i_7_n_0 ),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\cal_CS_A[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \cal_CS_A[7]_i_20 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[4].sync_reg [1]),
        .O(\cal_CS_A[7]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h5053505373735053)) 
    \cal_CS_A[7]_i_3 
       (.I0(\cal_CS_A[7]_i_8_n_0 ),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\cal_CS_A[7]_i_9_n_0 ),
        .I4(\cal_CS_A[7]_i_10_n_0 ),
        .I5(\SYNC[1].sync_reg [1]),
        .O(\cal_CS_A[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h02000F0F0C0C0F0F)) 
    \cal_CS_A[7]_i_4 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[11].sync_reg [1]),
        .I2(\cal_CS_A[7]_i_11_n_0 ),
        .I3(\SYNC[4].sync_reg [1]),
        .I4(lrdimm_cmp_en_i_3_n_0),
        .I5(\SYNC[10].sync_reg [1]),
        .O(\cal_CS_A[7]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hBF)) 
    \cal_CS_A[7]_i_5 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[20].sync_reg [1]),
        .O(\cal_CS_A[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hEFFFEFFF00F0FFFF)) 
    \cal_CS_A[7]_i_6 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[4].sync_reg [1]),
        .I4(\cal_ADR_A[31]_i_16_n_0 ),
        .I5(\SYNC[1].sync_reg [1]),
        .O(\cal_CS_A[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAABAAA)) 
    \cal_CS_A[7]_i_7 
       (.I0(\cal_CS_A[7]_i_12_n_0 ),
        .I1(\cal_CS_A[7]_i_13_n_0 ),
        .I2(\SYNC[20].sync_reg [1]),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\SYNC[10].sync_reg [1]),
        .O(\cal_CS_A[7]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFEFEFEFE0EFEFEFE)) 
    \cal_CS_A[7]_i_8 
       (.I0(\cal_CS_A[7]_i_14_n_0 ),
        .I1(\cal_CS_A[7]_i_15_n_0 ),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\cal_CS_A[7]_i_16_n_0 ),
        .I4(\cal_seq_a_a_dly[7]_i_2_n_0 ),
        .I5(\SYNC[17].sync_reg [1]),
        .O(\cal_CS_A[7]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h888A88AA88AA88AA)) 
    \cal_CS_A[7]_i_9 
       (.I0(\cal_CS_A[7]_i_17_n_0 ),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[10].sync_reg [1]),
        .I5(\SYNC[8].sync_reg [1]),
        .O(\cal_CS_A[7]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h0000000055570000)) 
    \cal_CS_B[7]_i_1 
       (.I0(\cal_CS_B[7]_i_2_n_0 ),
        .I1(lrdimm_cal_mode_i_3_n_0),
        .I2(\cal_CS_B[7]_i_3_n_0 ),
        .I3(\cal_CS_B[7]_i_4_n_0 ),
        .I4(\SYNC[9].sync_reg [1]),
        .I5(\cal_CS_B[7]_i_5_n_0 ),
        .O(\SYNC[9].sync_reg_reg[1]_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \cal_CS_B[7]_i_10 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[7].sync_reg [1]),
        .O(\cal_CS_B[7]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEFAF0F00)) 
    \cal_CS_B[7]_i_11 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\cal_CS_A[7]_i_5_n_0 ),
        .O(\cal_CS_B[7]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0F550F110F550011)) 
    \cal_CS_B[7]_i_12 
       (.I0(lrdimm_cal_mode_i_3_n_0),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\cal_ADR_A[31]_i_21_n_0 ),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\SYNC[4].sync_reg [1]),
        .I5(\SYNC[1].sync_reg [1]),
        .O(\cal_CS_B[7]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hF5F5F5F5FFD5D5D5)) 
    \cal_CS_B[7]_i_13 
       (.I0(\cal_CS_B[7]_i_16_n_0 ),
        .I1(\cal_CS_B[7]_i_14_n_0 ),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\SYNC[1].sync_reg [1]),
        .O(\cal_CS_B[7]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cal_CS_B[7]_i_14 
       (.I0(\SYNC[24].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .O(\cal_CS_B[7]_i_14_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \cal_CS_B[7]_i_15 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .O(\cal_CS_B[7]_i_15_n_0 ));
  LUT3 #(
    .INIT(8'h1F)) 
    \cal_CS_B[7]_i_16 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .O(\cal_CS_B[7]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h10115555FFFFFFFF)) 
    \cal_CS_B[7]_i_2 
       (.I0(\cal_CS_B[7]_i_6_n_0 ),
        .I1(\cal_CS_B[7]_i_7_n_0 ),
        .I2(\cal_CS_B[7]_i_8_n_0 ),
        .I3(\cal_CS_B[7]_i_9_n_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(calDone_i_4_n_0),
        .O(\cal_CS_B[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF5FFFDFFFDFF)) 
    \cal_CS_B[7]_i_3 
       (.I0(\cal_CS_B[7]_i_10_n_0 ),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\SYNC[6].sync_reg [1]),
        .O(\cal_CS_B[7]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h4F)) 
    \cal_CS_B[7]_i_4 
       (.I0(\SYNC[5].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[20].sync_reg [1]),
        .O(\cal_CS_B[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFDFFFFFF)) 
    \cal_CS_B[7]_i_5 
       (.I0(\SYNC[22].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(xsdb_wr_en_reg),
        .I3(io_addr_strobe),
        .I4(out),
        .I5(\SYNC[19].sync_reg [1]),
        .O(\cal_CS_B[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h4444444F444F444F)) 
    \cal_CS_B[7]_i_6 
       (.I0(\cal_CS_B[7]_i_11_n_0 ),
        .I1(\cal_CS_B[7]_i_12_n_0 ),
        .I2(\cal_CS_B[7]_i_13_n_0 ),
        .I3(lrdimm_cmp_en_i_3_n_0),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\cal_CS_B[7]_i_14_n_0 ),
        .O(\cal_CS_B[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0203020202030203)) 
    \cal_CS_B[7]_i_7 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\cal_CS_A[7]_i_14_n_0 ),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[20].sync_reg [1]),
        .I4(\cal_CS_B[7]_i_15_n_0 ),
        .I5(\SYNC[24].sync_reg [1]),
        .O(\cal_CS_B[7]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hBBBFBBBFBBBB0000)) 
    \cal_CS_B[7]_i_8 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(\SYNC[6].sync_reg [1]),
        .I5(\SYNC[17].sync_reg [1]),
        .O(\cal_CS_B[7]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cal_CS_B[7]_i_9 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[7].sync_reg [1]),
        .O(\cal_CS_B[7]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000800)) 
    \cal_DMOut_n_A[31]_i_1 
       (.I0(\cal_cmp_en[7]_i_2_n_0 ),
        .I1(p_52_in),
        .I2(\SYNC[4].sync_reg [1]),
        .I3(\SYNC[19].sync_reg [1]),
        .I4(\cal_DMOut_n_A[31]_i_2_n_0 ),
        .I5(\cal_DMOut_n_A[31]_i_3_n_0 ),
        .O(\SYNC[4].sync_reg_reg[1]_4 ));
  LUT3 #(
    .INIT(8'h04)) 
    \cal_DMOut_n_A[31]_i_2 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .O(\cal_DMOut_n_A[31]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h02020200)) 
    \cal_DMOut_n_A[31]_i_3 
       (.I0(\SYNC[24].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\SYNC[20].sync_reg [1]),
        .I3(\SYNC[6].sync_reg [1]),
        .I4(\SYNC[7].sync_reg [1]),
        .O(\cal_DMOut_n_A[31]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \cal_DQOut_A[31]_i_1 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\cal_DQOut_A[63]_i_2_n_0 ),
        .I2(\cal_cmp_en[7]_i_2_n_0 ),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\cal_cs_pos_reg[1] ),
        .O(\SYNC[6].sync_reg_reg[1]_1 ));
  LUT6 #(
    .INIT(64'h0000000000400000)) 
    \cal_DQOut_A[63]_i_1 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\cal_DQOut_A[63]_i_2_n_0 ),
        .I2(\cal_cmp_en[7]_i_2_n_0 ),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\cal_cs_pos_reg[1] ),
        .O(\SYNC[6].sync_reg_reg[1]_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cal_DQOut_A[63]_i_2 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\SYNC[5].sync_reg [1]),
        .O(\cal_DQOut_A[63]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800000000)) 
    \cal_DQOut_post[31]_i_1 
       (.I0(\SYNC[24].sync_reg [1]),
        .I1(\cal_cmp_en[7]_i_2_n_0 ),
        .I2(\cal_DQOut_post_reg[31] ),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\SYNC[6].sync_reg [1]),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\SYNC[24].sync_reg_reg[1]_1 ));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    \cal_DQOut_post[63]_i_1 
       (.I0(\cal_cmp_en[7]_i_2_n_0 ),
        .I1(p_52_in),
        .I2(xsdb_wr_en_reg),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\SYNC[6].sync_reg [1]),
        .I5(\cal_DQOut_post[63]_i_2_n_0 ),
        .O(rst_r1_reg));
  LUT4 #(
    .INIT(16'h1000)) 
    \cal_DQOut_post[63]_i_2 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\SYNC[24].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .O(\cal_DQOut_post[63]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \cal_DQOut_pre[31]_i_1 
       (.I0(\SYNC[24].sync_reg [1]),
        .I1(\cal_cmp_en[7]_i_2_n_0 ),
        .I2(\cal_DQOut_pre[63]_i_2_n_0 ),
        .I3(\cal_cs_pos_reg[1] ),
        .I4(\SYNC[6].sync_reg [1]),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\SYNC[24].sync_reg_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h0800000000000000)) 
    \cal_DQOut_pre[63]_i_1 
       (.I0(\cal_cmp_en[7]_i_2_n_0 ),
        .I1(\cal_DQOut_pre[63]_i_2_n_0 ),
        .I2(\cal_cs_pos_reg[1] ),
        .I3(\SYNC[6].sync_reg [1]),
        .I4(\SYNC[24].sync_reg [1]),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\SYNC[6].sync_reg_reg[1]_2 ));
  LUT2 #(
    .INIT(4'h1)) 
    \cal_DQOut_pre[63]_i_2 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .O(\cal_DQOut_pre[63]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000008A)) 
    \cal_DQPat_A[31]_i_1 
       (.I0(\cal_DQPat_A[63]_i_4_n_0 ),
        .I1(\SYNC[4].sync_reg [1]),
        .I2(\SYNC[19].sync_reg [1]),
        .I3(\cal_DQPat_A[63]_i_2_n_0 ),
        .I4(\cal_DQPat_A[63]_i_3_n_0 ),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\SYNC[4].sync_reg_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h000B000000000000)) 
    \cal_DQPat_A[63]_i_1 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\SYNC[19].sync_reg [1]),
        .I2(\cal_DQPat_A[63]_i_2_n_0 ),
        .I3(\cal_DQPat_A[63]_i_3_n_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\cal_DQPat_A[63]_i_4_n_0 ),
        .O(\SYNC[4].sync_reg_reg[1]_1 ));
  LUT3 #(
    .INIT(8'h10)) 
    \cal_DQPat_A[63]_i_2 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\SYNC[24].sync_reg [1]),
        .O(\cal_DQPat_A[63]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \cal_DQPat_A[63]_i_3 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .O(\cal_DQPat_A[63]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000400000000)) 
    \cal_DQPat_A[63]_i_4 
       (.I0(\xsdb_wr_data[8]_i_4_n_0 ),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\cal_cs_pos_reg[1] ),
        .I4(\SYNC[5].sync_reg [1]),
        .I5(\SYNC[6].sync_reg [1]),
        .O(\cal_DQPat_A[63]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000000B)) 
    \cal_DQPat_B[31]_i_1 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\SYNC[19].sync_reg [1]),
        .I2(\cal_DQPat_A[63]_i_2_n_0 ),
        .I3(\cal_DQPat_A[63]_i_3_n_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\cal_DQPat_B[63]_i_2_n_0 ),
        .O(\SYNC[4].sync_reg_reg[1]_2 ));
  LUT6 #(
    .INIT(64'h00000000000B0000)) 
    \cal_DQPat_B[63]_i_1 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\SYNC[19].sync_reg [1]),
        .I2(\cal_DQPat_A[63]_i_2_n_0 ),
        .I3(\cal_DQPat_A[63]_i_3_n_0 ),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\cal_DQPat_B[63]_i_2_n_0 ),
        .O(\SYNC[4].sync_reg_reg[1]_3 ));
  LUT6 #(
    .INIT(64'hFFFFFFFBFFFFFFFF)) 
    \cal_DQPat_B[63]_i_2 
       (.I0(\xsdb_wr_data[8]_i_4_n_0 ),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\cal_cs_pos_reg[1] ),
        .I4(\SYNC[5].sync_reg [1]),
        .I5(\SYNC[18].sync_reg [1]),
        .O(\cal_DQPat_B[63]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000008A000000)) 
    \cal_RST_CKE_ODT_PAR[31]_i_1 
       (.I0(\cal_RST_CKE_ODT_PAR[31]_i_2_n_0 ),
        .I1(\cal_RST_CKE_ODT_PAR[31]_i_3_n_0 ),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[6].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\cal_RST_CKE_ODT_PAR[31]_i_4_n_0 ),
        .O(\SYNC[17].sync_reg_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hFAFBFEFFFAFBFAFB)) 
    \cal_RST_CKE_ODT_PAR[31]_i_2 
       (.I0(\cal_RST_CKE_ODT_PAR[31]_i_5_n_0 ),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .I3(\SYNC[24].sync_reg [1]),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\SYNC[11].sync_reg [1]),
        .O(\cal_RST_CKE_ODT_PAR[31]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h54)) 
    \cal_RST_CKE_ODT_PAR[31]_i_3 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[3].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .O(\cal_RST_CKE_ODT_PAR[31]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF5DFFFF)) 
    \cal_RST_CKE_ODT_PAR[31]_i_4 
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[5].sync_reg [1]),
        .I3(xsdb_wr_en_reg),
        .I4(p_52_in),
        .I5(\SYNC[19].sync_reg [1]),
        .O(\cal_RST_CKE_ODT_PAR[31]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000D5D5D555)) 
    \cal_RST_CKE_ODT_PAR[31]_i_5 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[4].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\cal_RST_CKE_ODT_PAR[31]_i_6_n_0 ),
        .O(\cal_RST_CKE_ODT_PAR[31]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF6040FFFFFFFF)) 
    \cal_RST_CKE_ODT_PAR[31]_i_6 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .I5(\SYNC[20].sync_reg [1]),
        .O(\cal_RST_CKE_ODT_PAR[31]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h000000000E000000)) 
    \cal_WE_A[7]_i_1 
       (.I0(\cal_WE_A[7]_i_2_n_0 ),
        .I1(\cal_WE_A[7]_i_3_n_0 ),
        .I2(\cal_WE_A[7]_i_4_n_0 ),
        .I3(p_52_in),
        .I4(\SYNC[21].sync_reg [1]),
        .I5(\cal_WE_A[7]_i_5_n_0 ),
        .O(\SYNC[21].sync_reg_reg[1]_1 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF04000700)) 
    \cal_WE_A[7]_i_2 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\SYNC[11].sync_reg [1]),
        .I2(\SYNC[10].sync_reg [1]),
        .I3(\SYNC[20].sync_reg [1]),
        .I4(\SYNC[9].sync_reg [1]),
        .I5(\cal_WE_B[7]_i_4_n_0 ),
        .O(\cal_WE_A[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00B0000000000000)) 
    \cal_WE_A[7]_i_3 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(\SYNC[10].sync_reg [1]),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[20].sync_reg [1]),
        .I5(\SYNC[8].sync_reg [1]),
        .O(\cal_WE_A[7]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \cal_WE_A[7]_i_4 
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .O(\cal_WE_A[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h8FFF8FFFFFFF8FFF)) 
    \cal_WE_A[7]_i_5 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[6].sync_reg [1]),
        .I4(\SYNC[18].sync_reg [1]),
        .I5(\SYNC[5].sync_reg [1]),
        .O(\cal_WE_A[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h000E000E000E0000)) 
    \cal_WE_B[7]_i_1 
       (.I0(\cal_WE_B[7]_i_2_n_0 ),
        .I1(\cal_WE_B[7]_i_3_n_0 ),
        .I2(\cal_WE_A[7]_i_5_n_0 ),
        .I3(\cal_CS_B[7]_i_5_n_0 ),
        .I4(\cal_WE_B[7]_i_4_n_0 ),
        .I5(\cal_WE_B[7]_i_5_n_0 ),
        .O(\SYNC[8].sync_reg_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h3010303030FF3030)) 
    \cal_WE_B[7]_i_2 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(\cal_ADR_B[31]_i_9_n_0 ),
        .O(\cal_WE_B[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000FBFFFFF)) 
    \cal_WE_B[7]_i_3 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(lrdimm_cmp_en_i_3_n_0),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[10].sync_reg [1]),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\cal_WE_B[7]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hCD)) 
    \cal_WE_B[7]_i_4 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\SYNC[24].sync_reg [1]),
        .O(\cal_WE_B[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000FF008D008D00)) 
    \cal_WE_B[7]_i_5 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\SYNC[20].sync_reg [1]),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\SYNC[11].sync_reg [1]),
        .O(\cal_WE_B[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800080008)) 
    \cal_cmp_en[7]_i_1 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\cal_cmp_en[7]_i_2_n_0 ),
        .I2(\cal_cmp_en[7]_i_3_n_0 ),
        .I3(\cal_cmp_en[7]_i_4_n_0 ),
        .I4(\cal_cmp_en[7]_i_5_n_0 ),
        .I5(\SYNC[0].sync_reg_reg[1]_0 ),
        .O(\SYNC[18].sync_reg_reg[1]_1 ));
  LUT5 #(
    .INIT(32'h5D5D7D77)) 
    \cal_cmp_en[7]_i_2 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(\SYNC[2].sync_reg [1]),
        .O(\cal_cmp_en[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000800)) 
    \cal_cmp_en[7]_i_3 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\cal_cmp_en[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFBFFFFF)) 
    \cal_cmp_en[7]_i_4 
       (.I0(\cal_DQPat_A[63]_i_2_n_0 ),
        .I1(p_52_in),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\SYNC[5].sync_reg [1]),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\SYNC[19].sync_reg [1]),
        .O(\cal_cmp_en[7]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h00000008)) 
    \cal_cmp_en[7]_i_5 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .O(\cal_cmp_en[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000020000000)) 
    \cal_cs_pos[1]_i_1 
       (.I0(\cal_cs_pos[1]_i_2_n_0 ),
        .I1(\cal_cs_pos_reg[1] ),
        .I2(\cal_cs_pos[1]_i_4_n_0 ),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\cal_cs_pos[1]_i_5_n_0 ),
        .O(\SYNC[1].sync_reg_reg[1]_1 ));
  LUT5 #(
    .INIT(32'h0000FB33)) 
    \cal_cs_pos[1]_i_2 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .I3(\SYNC[5].sync_reg [1]),
        .I4(\SYNC[23].sync_reg [1]),
        .O(\cal_cs_pos[1]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h08)) 
    \cal_cs_pos[1]_i_4 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .I2(\SYNC[10].sync_reg [1]),
        .O(\cal_cs_pos[1]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hFFEF)) 
    \cal_cs_pos[1]_i_5 
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[20].sync_reg [1]),
        .I3(\SYNC[11].sync_reg [1]),
        .O(\cal_cs_pos[1]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \cal_oe_dis_low[7]_i_1 
       (.I0(io_write_data[0]),
        .I1(\cal_oe_dis_low[7]_i_2_n_0 ),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(cal_oe_dis_low),
        .O(\SYNC[0].sync_reg_reg[1]_5 ));
  LUT6 #(
    .INIT(64'h0223232200000000)) 
    \cal_oe_dis_low[7]_i_2 
       (.I0(calDone_i_2_n_0),
        .I1(\cal_oe_dis_low[7]_i_3_n_0 ),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(calDone_i_4_n_0),
        .O(\cal_oe_dis_low[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFD)) 
    \cal_oe_dis_low[7]_i_3 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\cal_oe_dis_low[7]_i_4_n_0 ),
        .I2(\SYNC[23].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[19].sync_reg [1]),
        .I5(\SYNC[11].sync_reg [1]),
        .O(\cal_oe_dis_low[7]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \cal_oe_dis_low[7]_i_4 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(io_addr_strobe),
        .I2(out),
        .O(\cal_oe_dis_low[7]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \cal_oe_dis_upp[7]_i_1 
       (.I0(io_write_data[0]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(cal_oe_dis_low),
        .I3(\cal_oe_dis_low[7]_i_2_n_0 ),
        .I4(cal_oe_dis_upp),
        .O(\SYNC[0].sync_reg_reg[1]_6 ));
  LUT6 #(
    .INIT(64'h0000000008000000)) 
    \cal_seq[2]_i_1 
       (.I0(\cal_seq[2]_i_2_n_0 ),
        .I1(\cal_seq[2]_i_3_n_0 ),
        .I2(\SYNC[19].sync_reg [1]),
        .I3(p_52_in),
        .I4(\SYNC[20].sync_reg [1]),
        .I5(\cal_seq[2]_i_4_n_0 ),
        .O(\SYNC[19].sync_reg_reg[1]_1 ));
  LUT4 #(
    .INIT(16'hFDD5)) 
    \cal_seq[2]_i_2 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\SYNC[5].sync_reg [1]),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .O(\cal_seq[2]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \cal_seq[2]_i_3 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[11].sync_reg [1]),
        .O(\cal_seq[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFDFFFDFFFD)) 
    \cal_seq[2]_i_4 
       (.I0(\cal_seq[2]_i_5_n_0 ),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\SYNC[3].sync_reg [1]),
        .O(\cal_seq[2]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cal_seq[2]_i_5 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .O(\cal_seq[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800000000)) 
    \cal_seq_a_a_dly[7]_i_1 
       (.I0(\cal_seq_a_b_dly[7]_i_2_n_0 ),
        .I1(\cal_seq_a_a_dly[7]_i_2_n_0 ),
        .I2(\SYNC[19].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\cal_seq_a_a_dly[7]_i_3_n_0 ),
        .I5(\cal_cs_pos[1]_i_2_n_0 ),
        .O(\SYNC[19].sync_reg_reg[1]_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cal_seq_a_a_dly[7]_i_2 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[11].sync_reg [1]),
        .O(\cal_seq_a_a_dly[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFEFFFFFF)) 
    \cal_seq_a_a_dly[7]_i_3 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .O(\cal_seq_a_a_dly[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0800000000000000)) 
    \cal_seq_a_b_dly[7]_i_1 
       (.I0(\cal_seq_a_b_dly[7]_i_2_n_0 ),
        .I1(calDone_i_4_n_0),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\cal_seq_a_b_dly[7]_i_3_n_0 ),
        .O(\SYNC[2].sync_reg_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h0000000003030357)) 
    \cal_seq_a_b_dly[7]_i_2 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[22].sync_reg [1]),
        .I3(\SYNC[12].sync_reg [1]),
        .I4(\SYNC[15].sync_reg [1]),
        .I5(\cal_cs_pos_reg[1] ),
        .O(\cal_seq_a_b_dly[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00000004)) 
    \cal_seq_a_b_dly[7]_i_3 
       (.I0(\cal_seq_b_a_dly[7]_i_2_n_0 ),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .O(\cal_seq_a_b_dly[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \cal_seq_b_a_dly[7]_i_1 
       (.I0(\cal_cs_pos[1]_i_2_n_0 ),
        .I1(\cal_seq_b_a_dly[7]_i_2_n_0 ),
        .I2(\cal_seq_b_a_dly[7]_i_3_n_0 ),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\cal_seq_b_a_dly[7]_i_4_n_0 ),
        .O(\SYNC[8].sync_reg_reg[1]_1 ));
  LUT4 #(
    .INIT(16'hFFEF)) 
    \cal_seq_b_a_dly[7]_i_2 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[19].sync_reg [1]),
        .I2(\SYNC[20].sync_reg [1]),
        .I3(\SYNC[9].sync_reg [1]),
        .O(\cal_seq_b_a_dly[7]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0004)) 
    \cal_seq_b_a_dly[7]_i_3 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .O(\cal_seq_b_a_dly[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDFFFDFFFDDDDD)) 
    \cal_seq_b_a_dly[7]_i_4 
       (.I0(p_52_in),
        .I1(xsdb_wr_en_reg),
        .I2(\SYNC[15].sync_reg [1]),
        .I3(\SYNC[12].sync_reg [1]),
        .I4(\SYNC[22].sync_reg [1]),
        .I5(\SYNC[21].sync_reg [1]),
        .O(\cal_seq_b_a_dly[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h2000000000000000)) 
    \cal_seq_rd_cnt[7]_i_5 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(p_52_in),
        .I3(lrdimm_cmp_en_i_3_n_0),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(\SYNC[2].sync_reg [1]),
        .O(cnt_clr_access));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    \cal_seq_rd_cnt[7]_i_6 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(p_52_in),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(lrdimm_cmp_en_i_3_n_0),
        .O(a_b_cmd_sel_start0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \cal_timer[0]_i_3 
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(out),
        .I3(io_addr_strobe),
        .I4(\SYNC[0].sync_reg [1]),
        .O(\SYNC[3].sync_reg_reg[1]_1 ));
  LUT6 #(
    .INIT(64'h0E00000000000000)) 
    \clb2phy_wrcs0_low[31]_i_1 
       (.I0(\clb2phy_wrcs0_low[31]_i_2_n_0 ),
        .I1(\clb2phy_wrcs0_low[31]_i_3_n_0 ),
        .I2(\clb2phy_wrcs0_low[31]_i_4_n_0 ),
        .I3(\SYNC[21].sync_reg [1]),
        .I4(io_addr_strobe),
        .I5(out),
        .O(\SYNC[21].sync_reg_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hFFE4FFFFFFE4F0E4)) 
    \clb2phy_wrcs0_low[31]_i_10 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[24].sync_reg [1]),
        .I3(\SYNC[6].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\SYNC[3].sync_reg [1]),
        .O(\clb2phy_wrcs0_low[31]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'h44444044)) 
    \clb2phy_wrcs0_low[31]_i_11 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[3].sync_reg [1]),
        .I3(\SYNC[17].sync_reg [1]),
        .I4(\SYNC[2].sync_reg [1]),
        .O(\clb2phy_wrcs0_low[31]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \clb2phy_wrcs0_low[31]_i_12 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .O(\clb2phy_wrcs0_low[31]_i_12_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \clb2phy_wrcs0_low[31]_i_13 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .O(\clb2phy_wrcs0_low[31]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h0020002020000200)) 
    \clb2phy_wrcs0_low[31]_i_14 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(\SYNC[10].sync_reg [1]),
        .O(\clb2phy_wrcs0_low[31]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'h555D5550)) 
    \clb2phy_wrcs0_low[31]_i_15 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[5].sync_reg [1]),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[18].sync_reg [1]),
        .O(\clb2phy_wrcs0_low[31]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h0100FFFF01000100)) 
    \clb2phy_wrcs0_low[31]_i_2 
       (.I0(\clb2phy_wrcs0_low[31]_i_5_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[6].sync_reg [1]),
        .I4(\clb2phy_wrcs0_low[31]_i_6_n_0 ),
        .I5(\clb2phy_wrcs0_low[31]_i_7_n_0 ),
        .O(\clb2phy_wrcs0_low[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h1110111011101111)) 
    \clb2phy_wrcs0_low[31]_i_3 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\clb2phy_wrcs0_low[31]_i_8_n_0 ),
        .I3(\clb2phy_wrcs0_low[31]_i_9_n_0 ),
        .I4(\SYNC[20].sync_reg [1]),
        .I5(\clb2phy_wrcs0_low[31]_i_10_n_0 ),
        .O(\clb2phy_wrcs0_low[31]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFD)) 
    \clb2phy_wrcs0_low[31]_i_4 
       (.I0(\SYNC[15].sync_reg [1]),
        .I1(\cal_DQOut_A[63]_i_2_n_0 ),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\SYNC[12].sync_reg [1]),
        .I4(\SYNC[19].sync_reg [1]),
        .I5(\SYNC[11].sync_reg [1]),
        .O(\clb2phy_wrcs0_low[31]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0300FFFF0704)) 
    \clb2phy_wrcs0_low[31]_i_5 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .I3(\SYNC[24].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\cal_ADR_B[31]_i_10_n_0 ),
        .O(\clb2phy_wrcs0_low[31]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hCE)) 
    \clb2phy_wrcs0_low[31]_i_6 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .I2(\SYNC[7].sync_reg [1]),
        .O(\clb2phy_wrcs0_low[31]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000C0C0AAAAEAFF)) 
    \clb2phy_wrcs0_low[31]_i_7 
       (.I0(\clb2phy_wrcs0_low[31]_i_11_n_0 ),
        .I1(\clb2phy_wrcs0_low[31]_i_12_n_0 ),
        .I2(\clb2phy_wrcs0_low[31]_i_13_n_0 ),
        .I3(\clb2phy_wrcs0_low[31]_i_14_n_0 ),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\cal_DQOut_post[63]_i_2_n_0 ),
        .O(\clb2phy_wrcs0_low[31]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0B0000000BFB0000)) 
    \clb2phy_wrcs0_low[31]_i_8 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[23].sync_reg [1]),
        .I5(\SYNC[3].sync_reg [1]),
        .O(\clb2phy_wrcs0_low[31]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000040447347)) 
    \clb2phy_wrcs0_low[31]_i_9 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\SYNC[3].sync_reg [1]),
        .I5(\clb2phy_wrcs0_low[31]_i_15_n_0 ),
        .O(\clb2phy_wrcs0_low[31]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000F0FB)) 
    clear_gt_data_ready_flag_i_1
       (.I0(clear_gt_data_ready_flag_i_2_n_0),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(clear_gt_data_ready_flag_i_3_n_0),
        .I3(\SYNC[0].sync_reg_reg[1]_0 ),
        .I4(clear_gt_data_ready_flag_i_4_n_0),
        .I5(clear_gt_data_ready_flag_i_5_n_0),
        .O(clear_gt_data_ready_flag));
  LUT3 #(
    .INIT(8'h01)) 
    clear_gt_data_ready_flag_i_2
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .O(clear_gt_data_ready_flag_i_2_n_0));
  LUT3 #(
    .INIT(8'h8F)) 
    clear_gt_data_ready_flag_i_3
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .O(clear_gt_data_ready_flag_i_3_n_0));
  LUT6 #(
    .INIT(64'hFFDFFFFFFFFFFFFF)) 
    clear_gt_data_ready_flag_i_4
       (.I0(clear_gt_data_ready_flag_i_6_n_0),
        .I1(clear_gt_data_ready_flag_i_7_n_0),
        .I2(io_addr_strobe),
        .I3(out),
        .I4(\SYNC[8].sync_reg [1]),
        .I5(gt_data_ready_flag),
        .O(clear_gt_data_ready_flag_i_4_n_0));
  LUT5 #(
    .INIT(32'hFFFEFFFF)) 
    clear_gt_data_ready_flag_i_5
       (.I0(\SYNC[22].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .I3(\SYNC[19].sync_reg [1]),
        .I4(\SYNC[20].sync_reg [1]),
        .O(clear_gt_data_ready_flag_i_5_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    clear_gt_data_ready_flag_i_6
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .O(clear_gt_data_ready_flag_i_6_n_0));
  LUT2 #(
    .INIT(4'h7)) 
    clear_gt_data_ready_flag_i_7
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[11].sync_reg [1]),
        .O(clear_gt_data_ready_flag_i_7_n_0));
  LUT6 #(
    .INIT(64'h0008000800080808)) 
    \cmp_byte[2]_i_1 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\cal_cmp_en[7]_i_2_n_0 ),
        .I2(\cmp_byte[2]_i_2_n_0 ),
        .I3(\cal_DQPat_A[63]_i_2_n_0 ),
        .I4(\SYNC[6].sync_reg [1]),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\SYNC[18].sync_reg_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hFEEEFFFEFEEEFEEE)) 
    \cmp_byte[2]_i_2 
       (.I0(\cal_cs_pos_reg[1] ),
        .I1(\SYNC[5].sync_reg [1]),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[4].sync_reg [1]),
        .I5(\SYNC[19].sync_reg [1]),
        .O(\cmp_byte[2]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    cnt_clr_i_1
       (.I0(cnt_clr),
        .I1(cnt_clr_access),
        .I2(io_write_data[0]),
        .I3(a_b_cmd_sel_start0),
        .O(cnt_clr_reg));
  LUT6 #(
    .INIT(64'h0000000002000000)) 
    \cplx_config[0]_i_1 
       (.I0(\cplx_config[0]_i_2_n_0 ),
        .I1(\cplx_config[0]_i_3_n_0 ),
        .I2(\cplx_config[0]_i_4_n_0 ),
        .I3(\SYNC[20].sync_reg [1]),
        .I4(p_52_in),
        .I5(\cplx_config[0]_i_5_n_0 ),
        .O(\SYNC[20].sync_reg_reg[1]_1 ));
  LUT6 #(
    .INIT(64'hF1F1F1F13535F135)) 
    \cplx_config[0]_i_2 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\SYNC[2].sync_reg [1]),
        .O(\cplx_config[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFDFFFFF)) 
    \cplx_config[0]_i_3 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(io_write_data[0]),
        .I3(\SYNC[22].sync_reg [1]),
        .I4(\SYNC[11].sync_reg [1]),
        .I5(\SYNC[7].sync_reg [1]),
        .O(\cplx_config[0]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h2A)) 
    \cplx_config[0]_i_4 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\SYNC[5].sync_reg [1]),
        .I2(\SYNC[6].sync_reg [1]),
        .O(\cplx_config[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF80)) 
    \cplx_config[0]_i_5 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[9].sync_reg [1]),
        .I4(\SYNC[19].sync_reg [1]),
        .I5(\SYNC[21].sync_reg [1]),
        .O(\cplx_config[0]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \cplx_config[15]_i_1 
       (.I0(\SYNC[17].sync_reg_reg[1]_3 ),
        .I1(io_addr_strobe),
        .I2(out),
        .O(io_addr_strobe_reg_0));
  LUT6 #(
    .INIT(64'h20002000EFCC2000)) 
    \cplx_config[16]_i_2 
       (.I0(\cplx_config[16]_i_3_n_0 ),
        .I1(\cplx_config[16]_i_4_n_0 ),
        .I2(\cplx_config[16]_i_5_n_0 ),
        .I3(\cplx_config[16]_i_6_n_0 ),
        .I4(\cplx_config[16]_i_7_n_0 ),
        .I5(\cplx_config[16]_i_8_n_0 ),
        .O(\SYNC[17].sync_reg_reg[1]_3 ));
  LUT6 #(
    .INIT(64'hB0B000B000B000B0)) 
    \cplx_config[16]_i_3 
       (.I0(\cal_RST_CKE_ODT_PAR[31]_i_3_n_0 ),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\cal_CS_B[7]_i_9_n_0 ),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\SYNC[5].sync_reg [1]),
        .I5(\SYNC[6].sync_reg [1]),
        .O(\cplx_config[16]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0F0F0F0F01000000)) 
    \cplx_config[16]_i_4 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(clear_gt_data_ready_flag_i_5_n_0),
        .I2(\cplx_config[16]_i_9_n_0 ),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(\SYNC[10].sync_reg [1]),
        .O(\cplx_config[16]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFDFFFFFFFFFFF)) 
    \cplx_config[16]_i_5 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\SYNC[5].sync_reg [1]),
        .I4(\SYNC[7].sync_reg [1]),
        .I5(\SYNC[11].sync_reg [1]),
        .O(\cplx_config[16]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000800)) 
    \cplx_config[16]_i_6 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[22].sync_reg_reg[1]_0 ),
        .I2(\SYNC[23].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .I4(\SYNC[9].sync_reg [1]),
        .I5(\SYNC[19].sync_reg [1]),
        .O(\cplx_config[16]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \cplx_config[16]_i_7 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .O(\cplx_config[16]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cplx_config[16]_i_8 
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .O(\cplx_config[16]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'hFEFF)) 
    \cplx_config[16]_i_9 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .O(\cplx_config[16]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \genblk10[0].cal_DMOut_n_A_r[7]_i_1 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \genblk10[4].cal_DMOut_n_A_r[39]_i_1 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_2 ));
  LUT2 #(
    .INIT(4'h1)) 
    io_ready_i_2
       (.I0(\SYNC[22].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .O(\SYNC[22].sync_reg_reg[1]_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    io_ready_i_3
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .O(\SYNC[23].sync_reg_reg[1]_2 ));
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    io_ready_i_4
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[10].sync_reg [1]),
        .I3(\SYNC[23].sync_reg [1]),
        .I4(\SYNC[8].sync_reg [1]),
        .O(\SYNC[9].sync_reg_reg[1]_3 ));
  LUT4 #(
    .INIT(16'h0008)) 
    \lowCL0[11]_i_1 
       (.I0(\lowCL0[47]_i_3_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .O(\SYNC[1].sync_reg_reg[1]_2 [1]));
  LUT4 #(
    .INIT(16'h0200)) 
    \lowCL0[17]_i_1 
       (.I0(\lowCL0[47]_i_3_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[3].sync_reg [1]),
        .I3(\SYNC[2].sync_reg [1]),
        .O(\SYNC[1].sync_reg_reg[1]_2 [2]));
  LUT4 #(
    .INIT(16'h0080)) 
    \lowCL0[23]_i_1 
       (.I0(\lowCL0[47]_i_3_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .O(\SYNC[1].sync_reg_reg[1]_2 [3]));
  LUT4 #(
    .INIT(16'h0008)) 
    \lowCL0[29]_i_1 
       (.I0(\lowCL0[47]_i_3_n_0 ),
        .I1(\SYNC[3].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[2].sync_reg [1]),
        .O(\SYNC[1].sync_reg_reg[1]_2 [4]));
  LUT4 #(
    .INIT(16'h0800)) 
    \lowCL0[35]_i_1 
       (.I0(\lowCL0[47]_i_3_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .O(\SYNC[1].sync_reg_reg[1]_2 [5]));
  LUT4 #(
    .INIT(16'h0080)) 
    \lowCL0[41]_i_1 
       (.I0(\lowCL0[47]_i_3_n_0 ),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[3].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .O(\SYNC[1].sync_reg_reg[1]_2 [6]));
  LUT4 #(
    .INIT(16'h8000)) 
    \lowCL0[47]_i_1 
       (.I0(\lowCL0[47]_i_3_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .O(\SYNC[1].sync_reg_reg[1]_2 [7]));
  LUT5 #(
    .INIT(32'h02000202)) 
    \lowCL0[47]_i_3 
       (.I0(\cplx_config[0]_i_2_n_0 ),
        .I1(\lowCL0[47]_i_5_n_0 ),
        .I2(\cal_DQPat_A[63]_i_3_n_0 ),
        .I3(\SYNC[5].sync_reg [1]),
        .I4(\SYNC[18].sync_reg [1]),
        .O(\lowCL0[47]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFF7FFFFFFFFFFFFF)) 
    \lowCL0[47]_i_5 
       (.I0(lrdimm_cmp_en_i_3_n_0),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[19].sync_reg [1]),
        .I4(out),
        .I5(io_addr_strobe),
        .O(\lowCL0[47]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h0002)) 
    \lowCL0[5]_i_1 
       (.I0(\lowCL0[47]_i_3_n_0 ),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .O(\SYNC[1].sync_reg_reg[1]_2 [0]));
  LUT6 #(
    .INIT(64'h0000000000000200)) 
    lrdimm_cal_mode_i_1
       (.I0(\cal_seq[2]_i_2_n_0 ),
        .I1(\SYNC[23].sync_reg [1]),
        .I2(\SYNC[8].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(lrdimm_cal_mode_i_2_n_0),
        .I5(lrdimm_cal_mode_i_3_n_0),
        .O(\SYNC[23].sync_reg_reg[1]_1 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF7FFF)) 
    lrdimm_cal_mode_i_2
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(out),
        .I3(io_addr_strobe),
        .I4(\SYNC[19].sync_reg [1]),
        .I5(\SYNC[0].sync_reg [1]),
        .O(lrdimm_cal_mode_i_2_n_0));
  LUT4 #(
    .INIT(16'hC4C0)) 
    lrdimm_cal_mode_i_3
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .O(lrdimm_cal_mode_i_3_n_0));
  LUT6 #(
    .INIT(64'h0800000000000000)) 
    lrdimm_cmp_clr_i_1
       (.I0(io_write_data[0]),
        .I1(lrdimm_cmp_clr_i_2_n_0),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(out),
        .I4(io_addr_strobe),
        .I5(\SYNC[0].sync_reg [1]),
        .O(lrdimm_cmp_clr));
  LUT4 #(
    .INIT(16'h4000)) 
    lrdimm_cmp_clr_i_2
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[11].sync_reg [1]),
        .I3(\SYNC[10].sync_reg [1]),
        .O(lrdimm_cmp_clr_i_2_n_0));
  LUT6 #(
    .INIT(64'hBFFFFFFF80000000)) 
    lrdimm_cmp_en_i_1
       (.I0(io_write_data[0]),
        .I1(lrdimm_cmp_en_i_2_n_0),
        .I2(\SYNC[10].sync_reg [1]),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(lrdimm_cmp_en_i_3_n_0),
        .I5(lrdimm_cmp_en),
        .O(\SYNC[0].sync_reg_reg[1]_4 ));
  LUT4 #(
    .INIT(16'h4000)) 
    lrdimm_cmp_en_i_2
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(out),
        .I2(io_addr_strobe),
        .I3(\SYNC[0].sync_reg [1]),
        .O(lrdimm_cmp_en_i_2_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    lrdimm_cmp_en_i_3
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\SYNC[23].sync_reg [1]),
        .O(lrdimm_cmp_en_i_3_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \max_rd_lat[5]_i_1 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(out),
        .I4(io_addr_strobe),
        .I5(\SYNC[0].sync_reg [1]),
        .O(\SYNC[17].sync_reg_reg[1]_2 ));
  LUT6 #(
    .INIT(64'h0000000000A20000)) 
    \rd_vref_value[11]_i_1 
       (.I0(\rd_vref_value[53]_i_2_n_0 ),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[3].sync_reg [1]),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\SYNC[1].sync_reg [1]),
        .O(rd_vref_value0_out[1]));
  LUT4 #(
    .INIT(16'h0400)) 
    \rd_vref_value[18]_i_1 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\rd_vref_value[53]_i_2_n_0 ),
        .O(rd_vref_value0_out[2]));
  LUT5 #(
    .INIT(32'h00400000)) 
    \rd_vref_value[25]_i_1 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[17].sync_reg [1]),
        .I4(\rd_vref_value[53]_i_2_n_0 ),
        .O(rd_vref_value0_out[3]));
  LUT5 #(
    .INIT(32'h00020000)) 
    \rd_vref_value[32]_i_1 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[17].sync_reg [1]),
        .I4(\rd_vref_value[53]_i_2_n_0 ),
        .O(rd_vref_value0_out[4]));
  LUT4 #(
    .INIT(16'h0800)) 
    \rd_vref_value[39]_i_1 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\rd_vref_value[53]_i_2_n_0 ),
        .O(rd_vref_value0_out[5]));
  LUT5 #(
    .INIT(32'h00080000)) 
    \rd_vref_value[46]_i_1 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[17].sync_reg [1]),
        .I4(\rd_vref_value[53]_i_2_n_0 ),
        .O(rd_vref_value0_out[6]));
  LUT6 #(
    .INIT(64'h000000000000040C)) 
    \rd_vref_value[4]_i_1 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\rd_vref_value[53]_i_2_n_0 ),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(\SYNC[1].sync_reg [1]),
        .I5(\SYNC[0].sync_reg [1]),
        .O(rd_vref_value0_out[0]));
  LUT5 #(
    .INIT(32'h00800000)) 
    \rd_vref_value[53]_i_1 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[17].sync_reg [1]),
        .I4(\rd_vref_value[53]_i_2_n_0 ),
        .O(rd_vref_value0_out[7]));
  LUT6 #(
    .INIT(64'h8880888A8000888A)) 
    \rd_vref_value[53]_i_2 
       (.I0(\rd_vref_value[53]_i_3_n_0 ),
        .I1(\rd_vref_value[53]_i_4_n_0 ),
        .I2(\SYNC[6].sync_reg [1]),
        .I3(\SYNC[7].sync_reg [1]),
        .I4(\SYNC[18].sync_reg [1]),
        .I5(\SYNC[5].sync_reg [1]),
        .O(\rd_vref_value[53]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \rd_vref_value[53]_i_3 
       (.I0(p_52_in),
        .I1(\SYNC[4].sync_reg [1]),
        .I2(\SYNC[19].sync_reg [1]),
        .O(\rd_vref_value[53]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hFD)) 
    \rd_vref_value[53]_i_4 
       (.I0(\SYNC[24].sync_reg [1]),
        .I1(\SYNC[20].sync_reg [1]),
        .I2(\SYNC[23].sync_reg [1]),
        .O(\rd_vref_value[53]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFFFFF80000000)) 
    stop_gate_tracking_ack_i_1
       (.I0(io_write_data[1]),
        .I1(stop_gate_tracking_ack_i_2_n_0),
        .I2(p_52_in),
        .I3(stop_gate_tracking_ack_i_3_n_0),
        .I4(\SYNC[17].sync_reg [1]),
        .I5(stop_gate_tracking_ack_reg),
        .O(\SYNC[4].sync_reg_reg[1]_6 ));
  LUT2 #(
    .INIT(4'h1)) 
    stop_gate_tracking_ack_i_2
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .O(stop_gate_tracking_ack_i_2_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    stop_gate_tracking_ack_i_3
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .O(stop_gate_tracking_ack_i_3_n_0));
  LUT6 #(
    .INIT(64'h0000000080000000)) 
    \traffic_instr_nxt_instr_r1[5]_i_1 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\SYNC[9].sync_reg [1]),
        .I2(calDone_i_4_n_0),
        .I3(io_addr_strobe),
        .I4(out),
        .I5(\traffic_instr_nxt_instr_r1[5]_i_2_n_0 ),
        .O(\SYNC[10].sync_reg_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hFDFFFFFFFFFFFFFF)) 
    \traffic_instr_nxt_instr_r1[5]_i_2 
       (.I0(\cal_seq_a_a_dly[7]_i_2_n_0 ),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[19].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\traffic_instr_nxt_instr_r1[5]_i_3_n_0 ),
        .O(\traffic_instr_nxt_instr_r1[5]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \traffic_instr_nxt_instr_r1[5]_i_3 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(\SYNC[8].sync_reg [1]),
        .O(\traffic_instr_nxt_instr_r1[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h01AA981E008E85F5)) 
    \u_ddr_config_rom/dout_o[0]_i_1 
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[5].sync_reg [1]),
        .I4(\SYNC[4].sync_reg [1]),
        .I5(\SYNC[1].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_8 [0]));
  LUT6 #(
    .INIT(64'h0000100000000000)) 
    \u_ddr_config_rom/dout_o[10]_i_1 
       (.I0(\SYNC[5].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\SYNC[3].sync_reg [1]),
        .I5(\SYNC[4].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_8 [9]));
  LUT6 #(
    .INIT(64'h0000000000004100)) 
    \u_ddr_config_rom/dout_o[11]_i_1 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[4].sync_reg [1]),
        .I4(\SYNC[5].sync_reg [1]),
        .I5(\SYNC[3].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_8 [10]));
  LUT6 #(
    .INIT(64'h0000020000080940)) 
    \u_ddr_config_rom/dout_o[1]_i_1 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[5].sync_reg [1]),
        .I2(\SYNC[4].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(\SYNC[3].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_8 [1]));
  LUT6 #(
    .INIT(64'h0004008000017A00)) 
    \u_ddr_config_rom/dout_o[2]_i_1 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[1].sync_reg [1]),
        .I2(\SYNC[5].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(\SYNC[4].sync_reg [1]),
        .I5(\SYNC[2].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_8 [2]));
  LUT6 #(
    .INIT(64'h0001010020000800)) 
    \u_ddr_config_rom/dout_o[3]_i_1 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[3].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[5].sync_reg [1]),
        .I5(\SYNC[4].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_8 [3]));
  LUT6 #(
    .INIT(64'h0000118000010002)) 
    \u_ddr_config_rom/dout_o[4]_i_1 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\SYNC[5].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[4].sync_reg [1]),
        .I4(\SYNC[3].sync_reg [1]),
        .I5(\SYNC[1].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_8 [4]));
  LUT6 #(
    .INIT(64'h0040000000000500)) 
    \u_ddr_config_rom/dout_o[5]_i_1 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[5].sync_reg [1]),
        .I2(\SYNC[3].sync_reg [1]),
        .I3(\SYNC[4].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .I5(\SYNC[1].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_8 [5]));
  LUT5 #(
    .INIT(32'h00000002)) 
    \u_ddr_config_rom/dout_o[6]_i_1 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(\SYNC[0].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_8 [6]));
  LUT5 #(
    .INIT(32'h00000002)) 
    \u_ddr_config_rom/dout_o[8]_i_1 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\SYNC[3].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[5].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_8 [7]));
  LUT6 #(
    .INIT(64'h0000000000002022)) 
    \u_ddr_config_rom/dout_o[9]_i_1 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\SYNC[3].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .I3(\SYNC[1].sync_reg [1]),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(\SYNC[5].sync_reg [1]),
        .O(\SYNC[0].sync_reg_reg[1]_8 [8]));
  LUT6 #(
    .INIT(64'h0000000004000000)) 
    ub_ready_i_1
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[17].sync_reg [1]),
        .I2(\SYNC[2].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(p_52_in),
        .I5(\SYNC[1].sync_reg [1]),
        .O(\SYNC[3].sync_reg_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h1000000000000000)) 
    write_vref_mode_i_1
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[0].sync_reg [1]),
        .I2(out),
        .I3(io_addr_strobe),
        .I4(\SYNC[2].sync_reg [1]),
        .I5(\SYNC[17].sync_reg [1]),
        .O(E));
  LUT6 #(
    .INIT(64'h0000000000000455)) 
    \xsdb_wr_data[8]_i_1 
       (.I0(xsdb_wr_en_reg),
        .I1(\SYNC[22].sync_reg_reg[1]_0 ),
        .I2(\cal_DQPat_A[63]_i_3_n_0 ),
        .I3(\xsdb_wr_data[8]_i_2_n_0 ),
        .I4(\xsdb_wr_data[8]_i_3_n_0 ),
        .I5(\xsdb_wr_data[8]_i_4_n_0 ),
        .O(rst_r1_reg_1));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \xsdb_wr_data[8]_i_2 
       (.I0(\xsdb_wr_data[8]_i_5_n_0 ),
        .I1(\cal_DQPat_A[63]_i_3_n_0 ),
        .I2(\SYNC[15].sync_reg [1]),
        .I3(\SYNC[12].sync_reg [1]),
        .I4(\SYNC[9].sync_reg [1]),
        .I5(\SYNC[11].sync_reg [1]),
        .O(\xsdb_wr_data[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFEFFFFFFFFFF)) 
    \xsdb_wr_data[8]_i_3 
       (.I0(\cal_CS_B[7]_i_4_n_0 ),
        .I1(\cal_DMOut_n_A[31]_i_2_n_0 ),
        .I2(\xsdb_wr_data[8]_i_6_n_0 ),
        .I3(\SYNC[23].sync_reg [1]),
        .I4(\SYNC[19].sync_reg [1]),
        .I5(p_52_in),
        .O(\xsdb_wr_data[8]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hF10E0000)) 
    \xsdb_wr_data[8]_i_4 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\SYNC[3].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .I4(\SYNC[17].sync_reg [1]),
        .O(\xsdb_wr_data[8]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \xsdb_wr_data[8]_i_5 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\SYNC[6].sync_reg [1]),
        .O(\xsdb_wr_data[8]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \xsdb_wr_data[8]_i_6 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\SYNC[21].sync_reg [1]),
        .I2(\SYNC[0].sync_reg [1]),
        .O(\xsdb_wr_data[8]_i_6_n_0 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized8_1
   (io_write_data,
    cnt_clr_reg,
    \SYNC[5].sync_reg_reg[1]_0 ,
    \SYNC[13].sync_reg_reg[1]_0 ,
    \SYNC[21].sync_reg_reg[1]_0 ,
    \SYNC[29].sync_reg_reg[1]_0 ,
    O,
    \SYNC[15].sync_reg_reg[1]_0 ,
    \SYNC[23].sync_reg_reg[1]_0 ,
    \SYNC[31].sync_reg_reg[1]_0 ,
    \SYNC[0].sync_reg_reg[1]_0 ,
    cal_seq_cnt_gt_0_reg,
    cnt_clr,
    a_b_cmd_sel_start0,
    cal_timer_reg_31_sp_1,
    cal_timer_reg,
    \uppCL3_reg[44] ,
    \uppCL0_reg[47] ,
    \uppCL0_reg[33] ,
    \uppCL0_reg[37] ,
    \uppCL0_reg[32] ,
    \uppCL0_reg[36] ,
    \uppCL0_reg[46] ,
    \uppCL1_reg[33] ,
    \uppCL1_reg[37] ,
    \uppCL1_reg[47] ,
    \uppCL1_reg[32] ,
    \uppCL1_reg[36] ,
    \uppCL1_reg[46] ,
    \uppCL2_reg[33] ,
    \uppCL2_reg[37] ,
    \uppCL2_reg[47] ,
    \uppCL2_reg[32] ,
    \uppCL2_reg[36] ,
    \uppCL2_reg[46] ,
    \uppCL3_reg[33] ,
    \uppCL3_reg[37] ,
    \uppCL3_reg[47] ,
    \uppCL3_reg[32] ,
    \uppCL3_reg[36] ,
    \uppCL3_reg[46] ,
    S,
    a_b_cmd_sel_start,
    \SYNC[30].sync_reg_reg[1]_0 ,
    \SYNC[31].sync_reg_reg[0]_0 );
  output [31:0]io_write_data;
  output cnt_clr_reg;
  output [9:0]\SYNC[5].sync_reg_reg[1]_0 ;
  output [9:0]\SYNC[13].sync_reg_reg[1]_0 ;
  output [9:0]\SYNC[21].sync_reg_reg[1]_0 ;
  output [9:0]\SYNC[29].sync_reg_reg[1]_0 ;
  output [7:0]O;
  output [7:0]\SYNC[15].sync_reg_reg[1]_0 ;
  output [7:0]\SYNC[23].sync_reg_reg[1]_0 ;
  output [7:0]\SYNC[31].sync_reg_reg[1]_0 ;
  output \SYNC[0].sync_reg_reg[1]_0 ;
  input cal_seq_cnt_gt_0_reg;
  input cnt_clr;
  input a_b_cmd_sel_start0;
  input cal_timer_reg_31_sp_1;
  input [31:0]cal_timer_reg;
  input [1:0]\uppCL3_reg[44] ;
  input \uppCL0_reg[47] ;
  input \uppCL0_reg[33] ;
  input \uppCL0_reg[37] ;
  input \uppCL0_reg[32] ;
  input \uppCL0_reg[36] ;
  input \uppCL0_reg[46] ;
  input \uppCL1_reg[33] ;
  input \uppCL1_reg[37] ;
  input \uppCL1_reg[47] ;
  input \uppCL1_reg[32] ;
  input \uppCL1_reg[36] ;
  input \uppCL1_reg[46] ;
  input \uppCL2_reg[33] ;
  input \uppCL2_reg[37] ;
  input \uppCL2_reg[47] ;
  input \uppCL2_reg[32] ;
  input \uppCL2_reg[36] ;
  input \uppCL2_reg[46] ;
  input \uppCL3_reg[33] ;
  input \uppCL3_reg[37] ;
  input \uppCL3_reg[47] ;
  input \uppCL3_reg[32] ;
  input \uppCL3_reg[36] ;
  input \uppCL3_reg[46] ;
  input [0:0]S;
  input a_b_cmd_sel_start;
  input \SYNC[30].sync_reg_reg[1]_0 ;
  input [31:0]\SYNC[31].sync_reg_reg[0]_0 ;

  wire [7:0]O;
  wire [0:0]S;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  wire \SYNC[0].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[10].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[11].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[12].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[13].sync_reg ;
  wire [9:0]\SYNC[13].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[14].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[15].sync_reg ;
  wire [7:0]\SYNC[15].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[16].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[17].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[18].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[19].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[1].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[20].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[21].sync_reg ;
  wire [9:0]\SYNC[21].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[22].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[23].sync_reg ;
  wire [7:0]\SYNC[23].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[24].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[25].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[26].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[27].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[28].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[29].sync_reg ;
  wire [9:0]\SYNC[29].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[2].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[30].sync_reg ;
  wire \SYNC[30].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[31].sync_reg ;
  wire [31:0]\SYNC[31].sync_reg_reg[0]_0 ;
  wire [7:0]\SYNC[31].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[3].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[4].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[5].sync_reg ;
  wire [9:0]\SYNC[5].sync_reg_reg[1]_0 ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[6].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[7].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[8].sync_reg ;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[9].sync_reg ;
  wire a_b_cmd_sel_start;
  wire a_b_cmd_sel_start0;
  wire cal_seq_cnt_gt_0_i_12_n_0;
  wire cal_seq_cnt_gt_0_i_13_n_0;
  wire cal_seq_cnt_gt_0_i_2_n_0;
  wire cal_seq_cnt_gt_0_i_3_n_0;
  wire cal_seq_cnt_gt_0_i_5_n_0;
  wire cal_seq_cnt_gt_0_i_6_n_0;
  wire cal_seq_cnt_gt_0_i_7_n_0;
  wire cal_seq_cnt_gt_0_i_8_n_0;
  wire cal_seq_cnt_gt_0_reg;
  wire \cal_timer[0]_i_10_n_0 ;
  wire \cal_timer[0]_i_11_n_0 ;
  wire \cal_timer[0]_i_12_n_0 ;
  wire \cal_timer[0]_i_13_n_0 ;
  wire \cal_timer[0]_i_14_n_0 ;
  wire \cal_timer[0]_i_7_n_0 ;
  wire \cal_timer[0]_i_8_n_0 ;
  wire \cal_timer[0]_i_9_n_0 ;
  wire \cal_timer[16]_i_2_n_0 ;
  wire \cal_timer[16]_i_3_n_0 ;
  wire \cal_timer[16]_i_4_n_0 ;
  wire \cal_timer[16]_i_5_n_0 ;
  wire \cal_timer[16]_i_6_n_0 ;
  wire \cal_timer[16]_i_7_n_0 ;
  wire \cal_timer[16]_i_8_n_0 ;
  wire \cal_timer[16]_i_9_n_0 ;
  wire \cal_timer[24]_i_2_n_0 ;
  wire \cal_timer[24]_i_3_n_0 ;
  wire \cal_timer[24]_i_4_n_0 ;
  wire \cal_timer[24]_i_5_n_0 ;
  wire \cal_timer[24]_i_6_n_0 ;
  wire \cal_timer[24]_i_7_n_0 ;
  wire \cal_timer[24]_i_8_n_0 ;
  wire \cal_timer[24]_i_9_n_0 ;
  wire \cal_timer[8]_i_2_n_0 ;
  wire \cal_timer[8]_i_3_n_0 ;
  wire \cal_timer[8]_i_4_n_0 ;
  wire \cal_timer[8]_i_5_n_0 ;
  wire \cal_timer[8]_i_6_n_0 ;
  wire \cal_timer[8]_i_7_n_0 ;
  wire \cal_timer[8]_i_8_n_0 ;
  wire \cal_timer[8]_i_9_n_0 ;
  wire [31:0]cal_timer_reg;
  wire \cal_timer_reg[0]_i_2_n_0 ;
  wire \cal_timer_reg[0]_i_2_n_1 ;
  wire \cal_timer_reg[0]_i_2_n_2 ;
  wire \cal_timer_reg[0]_i_2_n_3 ;
  wire \cal_timer_reg[0]_i_2_n_4 ;
  wire \cal_timer_reg[0]_i_2_n_5 ;
  wire \cal_timer_reg[0]_i_2_n_6 ;
  wire \cal_timer_reg[0]_i_2_n_7 ;
  wire \cal_timer_reg[16]_i_1_n_0 ;
  wire \cal_timer_reg[16]_i_1_n_1 ;
  wire \cal_timer_reg[16]_i_1_n_2 ;
  wire \cal_timer_reg[16]_i_1_n_3 ;
  wire \cal_timer_reg[16]_i_1_n_4 ;
  wire \cal_timer_reg[16]_i_1_n_5 ;
  wire \cal_timer_reg[16]_i_1_n_6 ;
  wire \cal_timer_reg[16]_i_1_n_7 ;
  wire \cal_timer_reg[24]_i_1_n_1 ;
  wire \cal_timer_reg[24]_i_1_n_2 ;
  wire \cal_timer_reg[24]_i_1_n_3 ;
  wire \cal_timer_reg[24]_i_1_n_4 ;
  wire \cal_timer_reg[24]_i_1_n_5 ;
  wire \cal_timer_reg[24]_i_1_n_6 ;
  wire \cal_timer_reg[24]_i_1_n_7 ;
  wire \cal_timer_reg[8]_i_1_n_0 ;
  wire \cal_timer_reg[8]_i_1_n_1 ;
  wire \cal_timer_reg[8]_i_1_n_2 ;
  wire \cal_timer_reg[8]_i_1_n_3 ;
  wire \cal_timer_reg[8]_i_1_n_4 ;
  wire \cal_timer_reg[8]_i_1_n_5 ;
  wire \cal_timer_reg[8]_i_1_n_6 ;
  wire \cal_timer_reg[8]_i_1_n_7 ;
  wire cal_timer_reg_31_sn_1;
  wire cnt_clr;
  wire cnt_clr_reg;
  wire \uppCL0_reg[32] ;
  wire \uppCL0_reg[33] ;
  wire \uppCL0_reg[36] ;
  wire \uppCL0_reg[37] ;
  wire \uppCL0_reg[46] ;
  wire \uppCL0_reg[47] ;
  wire \uppCL1_reg[32] ;
  wire \uppCL1_reg[33] ;
  wire \uppCL1_reg[36] ;
  wire \uppCL1_reg[37] ;
  wire \uppCL1_reg[46] ;
  wire \uppCL1_reg[47] ;
  wire \uppCL2_reg[32] ;
  wire \uppCL2_reg[33] ;
  wire \uppCL2_reg[36] ;
  wire \uppCL2_reg[37] ;
  wire \uppCL2_reg[46] ;
  wire \uppCL2_reg[47] ;
  wire \uppCL3_reg[32] ;
  wire \uppCL3_reg[33] ;
  wire \uppCL3_reg[36] ;
  wire \uppCL3_reg[37] ;
  wire [1:0]\uppCL3_reg[44] ;
  wire \uppCL3_reg[46] ;
  wire \uppCL3_reg[47] ;
  wire [7:7]\NLW_cal_timer_reg[24]_i_1_CO_UNCONNECTED ;

  assign cal_timer_reg_31_sn_1 = cal_timer_reg_31_sp_1;
  assign io_write_data[31] = \SYNC[31].sync_reg [1];
  assign io_write_data[30] = \SYNC[30].sync_reg [1];
  assign io_write_data[29] = \SYNC[29].sync_reg [1];
  assign io_write_data[28] = \SYNC[28].sync_reg [1];
  assign io_write_data[27] = \SYNC[27].sync_reg [1];
  assign io_write_data[26] = \SYNC[26].sync_reg [1];
  assign io_write_data[25] = \SYNC[25].sync_reg [1];
  assign io_write_data[24] = \SYNC[24].sync_reg [1];
  assign io_write_data[23] = \SYNC[23].sync_reg [1];
  assign io_write_data[22] = \SYNC[22].sync_reg [1];
  assign io_write_data[21] = \SYNC[21].sync_reg [1];
  assign io_write_data[20] = \SYNC[20].sync_reg [1];
  assign io_write_data[19] = \SYNC[19].sync_reg [1];
  assign io_write_data[18] = \SYNC[18].sync_reg [1];
  assign io_write_data[17] = \SYNC[17].sync_reg [1];
  assign io_write_data[16] = \SYNC[16].sync_reg [1];
  assign io_write_data[15] = \SYNC[15].sync_reg [1];
  assign io_write_data[14] = \SYNC[14].sync_reg [1];
  assign io_write_data[13] = \SYNC[13].sync_reg [1];
  assign io_write_data[12] = \SYNC[12].sync_reg [1];
  assign io_write_data[11] = \SYNC[11].sync_reg [1];
  assign io_write_data[10] = \SYNC[10].sync_reg [1];
  assign io_write_data[9] = \SYNC[9].sync_reg [1];
  assign io_write_data[8] = \SYNC[8].sync_reg [1];
  assign io_write_data[7] = \SYNC[7].sync_reg [1];
  assign io_write_data[6] = \SYNC[6].sync_reg [1];
  assign io_write_data[5] = \SYNC[5].sync_reg [1];
  assign io_write_data[4] = \SYNC[4].sync_reg [1];
  assign io_write_data[3] = \SYNC[3].sync_reg [1];
  assign io_write_data[2] = \SYNC[2].sync_reg [1];
  assign io_write_data[1] = \SYNC[1].sync_reg [1];
  assign io_write_data[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [0]),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [10]),
        .Q(\SYNC[10].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[10].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[10].sync_reg [0]),
        .Q(\SYNC[10].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [11]),
        .Q(\SYNC[11].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[11].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[11].sync_reg [0]),
        .Q(\SYNC[11].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [12]),
        .Q(\SYNC[12].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[12].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[12].sync_reg [0]),
        .Q(\SYNC[12].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [13]),
        .Q(\SYNC[13].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[13].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[13].sync_reg [0]),
        .Q(\SYNC[13].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [14]),
        .Q(\SYNC[14].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[14].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[14].sync_reg [0]),
        .Q(\SYNC[14].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [15]),
        .Q(\SYNC[15].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[15].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[15].sync_reg [0]),
        .Q(\SYNC[15].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [16]),
        .Q(\SYNC[16].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[16].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[16].sync_reg [0]),
        .Q(\SYNC[16].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [17]),
        .Q(\SYNC[17].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[17].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[17].sync_reg [0]),
        .Q(\SYNC[17].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [18]),
        .Q(\SYNC[18].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[18].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[18].sync_reg [0]),
        .Q(\SYNC[18].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [19]),
        .Q(\SYNC[19].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[19].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[19].sync_reg [0]),
        .Q(\SYNC[19].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [1]),
        .Q(\SYNC[1].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[1].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[1].sync_reg [0]),
        .Q(\SYNC[1].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[20].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [20]),
        .Q(\SYNC[20].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[20].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[20].sync_reg [0]),
        .Q(\SYNC[20].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[21].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [21]),
        .Q(\SYNC[21].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[21].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[21].sync_reg [0]),
        .Q(\SYNC[21].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[22].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [22]),
        .Q(\SYNC[22].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[22].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[22].sync_reg [0]),
        .Q(\SYNC[22].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[23].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [23]),
        .Q(\SYNC[23].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[23].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[23].sync_reg [0]),
        .Q(\SYNC[23].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[24].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [24]),
        .Q(\SYNC[24].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[24].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[24].sync_reg [0]),
        .Q(\SYNC[24].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[25].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [25]),
        .Q(\SYNC[25].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[25].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[25].sync_reg [0]),
        .Q(\SYNC[25].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[26].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [26]),
        .Q(\SYNC[26].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[26].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[26].sync_reg [0]),
        .Q(\SYNC[26].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[27].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [27]),
        .Q(\SYNC[27].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[27].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[27].sync_reg [0]),
        .Q(\SYNC[27].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[28].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [28]),
        .Q(\SYNC[28].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[28].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[28].sync_reg [0]),
        .Q(\SYNC[28].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[29].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [29]),
        .Q(\SYNC[29].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[29].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[29].sync_reg [0]),
        .Q(\SYNC[29].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [2]),
        .Q(\SYNC[2].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[2].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[2].sync_reg [0]),
        .Q(\SYNC[2].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[30].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [30]),
        .Q(\SYNC[30].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[30].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[30].sync_reg [0]),
        .Q(\SYNC[30].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[31].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [31]),
        .Q(\SYNC[31].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[31].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg [0]),
        .Q(\SYNC[31].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [3]),
        .Q(\SYNC[3].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[3].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[3].sync_reg [0]),
        .Q(\SYNC[3].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [4]),
        .Q(\SYNC[4].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[4].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[4].sync_reg [0]),
        .Q(\SYNC[4].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [5]),
        .Q(\SYNC[5].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[5].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[5].sync_reg [0]),
        .Q(\SYNC[5].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [6]),
        .Q(\SYNC[6].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[6].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[6].sync_reg [0]),
        .Q(\SYNC[6].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [7]),
        .Q(\SYNC[7].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[7].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[7].sync_reg [0]),
        .Q(\SYNC[7].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [8]),
        .Q(\SYNC[8].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[8].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[8].sync_reg [0]),
        .Q(\SYNC[8].sync_reg [1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[0] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[31].sync_reg_reg[0]_0 [9]),
        .Q(\SYNC[9].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[9].sync_reg_reg[1] 
       (.C(\SYNC[30].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[9].sync_reg [0]),
        .Q(\SYNC[9].sync_reg [1]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hB8)) 
    a_b_cmd_sel_start_i_1
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(a_b_cmd_sel_start0),
        .I2(a_b_cmd_sel_start),
        .O(\SYNC[0].sync_reg_reg[1]_0 ));
  LUT5 #(
    .INIT(32'hDDDD000F)) 
    cal_seq_cnt_gt_0_i_1
       (.I0(cal_seq_cnt_gt_0_i_2_n_0),
        .I1(cal_seq_cnt_gt_0_i_3_n_0),
        .I2(cal_seq_cnt_gt_0_reg),
        .I3(cnt_clr),
        .I4(a_b_cmd_sel_start0),
        .O(cnt_clr_reg));
  LUT4 #(
    .INIT(16'hFFFE)) 
    cal_seq_cnt_gt_0_i_12
       (.I0(\SYNC[27].sync_reg [1]),
        .I1(\SYNC[26].sync_reg [1]),
        .I2(\SYNC[25].sync_reg [1]),
        .I3(\SYNC[24].sync_reg [1]),
        .O(cal_seq_cnt_gt_0_i_12_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    cal_seq_cnt_gt_0_i_13
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\SYNC[2].sync_reg [1]),
        .I2(\SYNC[1].sync_reg [1]),
        .I3(\SYNC[0].sync_reg [1]),
        .O(cal_seq_cnt_gt_0_i_13_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    cal_seq_cnt_gt_0_i_2
       (.I0(cal_seq_cnt_gt_0_i_5_n_0),
        .I1(\SYNC[22].sync_reg [1]),
        .I2(\SYNC[21].sync_reg [1]),
        .I3(\SYNC[23].sync_reg [1]),
        .I4(\SYNC[20].sync_reg [1]),
        .I5(cal_seq_cnt_gt_0_i_6_n_0),
        .O(cal_seq_cnt_gt_0_i_2_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    cal_seq_cnt_gt_0_i_3
       (.I0(cal_seq_cnt_gt_0_i_7_n_0),
        .I1(\SYNC[15].sync_reg [1]),
        .I2(\SYNC[12].sync_reg [1]),
        .I3(\SYNC[14].sync_reg [1]),
        .I4(\SYNC[13].sync_reg [1]),
        .I5(cal_seq_cnt_gt_0_i_8_n_0),
        .O(cal_seq_cnt_gt_0_i_3_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    cal_seq_cnt_gt_0_i_5
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(\SYNC[18].sync_reg [1]),
        .I2(\SYNC[17].sync_reg [1]),
        .I3(\SYNC[16].sync_reg [1]),
        .O(cal_seq_cnt_gt_0_i_5_n_0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    cal_seq_cnt_gt_0_i_6
       (.I0(\SYNC[28].sync_reg [1]),
        .I1(\SYNC[31].sync_reg [1]),
        .I2(\SYNC[29].sync_reg [1]),
        .I3(\SYNC[30].sync_reg [1]),
        .I4(cal_seq_cnt_gt_0_i_12_n_0),
        .O(cal_seq_cnt_gt_0_i_6_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    cal_seq_cnt_gt_0_i_7
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\SYNC[10].sync_reg [1]),
        .I2(\SYNC[9].sync_reg [1]),
        .I3(\SYNC[8].sync_reg [1]),
        .O(cal_seq_cnt_gt_0_i_7_n_0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    cal_seq_cnt_gt_0_i_8
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(\SYNC[7].sync_reg [1]),
        .I2(\SYNC[4].sync_reg [1]),
        .I3(\SYNC[5].sync_reg [1]),
        .I4(cal_seq_cnt_gt_0_i_13_n_0),
        .O(cal_seq_cnt_gt_0_i_8_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[0]_i_10 
       (.I0(\SYNC[5].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[5]),
        .O(\cal_timer[0]_i_10_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[0]_i_11 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[4]),
        .O(\cal_timer[0]_i_11_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[0]_i_12 
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[3]),
        .O(\cal_timer[0]_i_12_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[0]_i_13 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[2]),
        .O(\cal_timer[0]_i_13_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[0]_i_14 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[1]),
        .O(\cal_timer[0]_i_14_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[0]_i_7 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[0]),
        .O(\cal_timer[0]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[0]_i_8 
       (.I0(\SYNC[7].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[7]),
        .O(\cal_timer[0]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[0]_i_9 
       (.I0(\SYNC[6].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[6]),
        .O(\cal_timer[0]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[16]_i_2 
       (.I0(\SYNC[23].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[23]),
        .O(\cal_timer[16]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[16]_i_3 
       (.I0(\SYNC[22].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[22]),
        .O(\cal_timer[16]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[16]_i_4 
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[21]),
        .O(\cal_timer[16]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[16]_i_5 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[20]),
        .O(\cal_timer[16]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[16]_i_6 
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[19]),
        .O(\cal_timer[16]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[16]_i_7 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[18]),
        .O(\cal_timer[16]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[16]_i_8 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[17]),
        .O(\cal_timer[16]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[16]_i_9 
       (.I0(\SYNC[16].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[16]),
        .O(\cal_timer[16]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[24]_i_2 
       (.I0(\SYNC[31].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[31]),
        .O(\cal_timer[24]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[24]_i_3 
       (.I0(\SYNC[30].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[30]),
        .O(\cal_timer[24]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[24]_i_4 
       (.I0(\SYNC[29].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[29]),
        .O(\cal_timer[24]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[24]_i_5 
       (.I0(\SYNC[28].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[28]),
        .O(\cal_timer[24]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[24]_i_6 
       (.I0(\SYNC[27].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[27]),
        .O(\cal_timer[24]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[24]_i_7 
       (.I0(\SYNC[26].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[26]),
        .O(\cal_timer[24]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[24]_i_8 
       (.I0(\SYNC[25].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[25]),
        .O(\cal_timer[24]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[24]_i_9 
       (.I0(\SYNC[24].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[24]),
        .O(\cal_timer[24]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[8]_i_2 
       (.I0(\SYNC[15].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[15]),
        .O(\cal_timer[8]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[8]_i_3 
       (.I0(\SYNC[14].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[14]),
        .O(\cal_timer[8]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[8]_i_4 
       (.I0(\SYNC[13].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[13]),
        .O(\cal_timer[8]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[8]_i_5 
       (.I0(\SYNC[12].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[12]),
        .O(\cal_timer[8]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[8]_i_6 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[11]),
        .O(\cal_timer[8]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[8]_i_7 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[10]),
        .O(\cal_timer[8]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[8]_i_8 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[9]),
        .O(\cal_timer[8]_i_8_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cal_timer[8]_i_9 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(cal_timer_reg_31_sn_1),
        .I2(cal_timer_reg[8]),
        .O(\cal_timer[8]_i_9_n_0 ));
  (* ADDER_THRESHOLD = "16" *) 
  CARRY8 \cal_timer_reg[0]_i_2 
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({\cal_timer_reg[0]_i_2_n_0 ,\cal_timer_reg[0]_i_2_n_1 ,\cal_timer_reg[0]_i_2_n_2 ,\cal_timer_reg[0]_i_2_n_3 ,\cal_timer_reg[0]_i_2_n_4 ,\cal_timer_reg[0]_i_2_n_5 ,\cal_timer_reg[0]_i_2_n_6 ,\cal_timer_reg[0]_i_2_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\cal_timer[0]_i_7_n_0 }),
        .O(O),
        .S({\cal_timer[0]_i_8_n_0 ,\cal_timer[0]_i_9_n_0 ,\cal_timer[0]_i_10_n_0 ,\cal_timer[0]_i_11_n_0 ,\cal_timer[0]_i_12_n_0 ,\cal_timer[0]_i_13_n_0 ,\cal_timer[0]_i_14_n_0 ,S}));
  (* ADDER_THRESHOLD = "16" *) 
  CARRY8 \cal_timer_reg[16]_i_1 
       (.CI(\cal_timer_reg[8]_i_1_n_0 ),
        .CI_TOP(1'b0),
        .CO({\cal_timer_reg[16]_i_1_n_0 ,\cal_timer_reg[16]_i_1_n_1 ,\cal_timer_reg[16]_i_1_n_2 ,\cal_timer_reg[16]_i_1_n_3 ,\cal_timer_reg[16]_i_1_n_4 ,\cal_timer_reg[16]_i_1_n_5 ,\cal_timer_reg[16]_i_1_n_6 ,\cal_timer_reg[16]_i_1_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O(\SYNC[23].sync_reg_reg[1]_0 ),
        .S({\cal_timer[16]_i_2_n_0 ,\cal_timer[16]_i_3_n_0 ,\cal_timer[16]_i_4_n_0 ,\cal_timer[16]_i_5_n_0 ,\cal_timer[16]_i_6_n_0 ,\cal_timer[16]_i_7_n_0 ,\cal_timer[16]_i_8_n_0 ,\cal_timer[16]_i_9_n_0 }));
  (* ADDER_THRESHOLD = "16" *) 
  CARRY8 \cal_timer_reg[24]_i_1 
       (.CI(\cal_timer_reg[16]_i_1_n_0 ),
        .CI_TOP(1'b0),
        .CO({\NLW_cal_timer_reg[24]_i_1_CO_UNCONNECTED [7],\cal_timer_reg[24]_i_1_n_1 ,\cal_timer_reg[24]_i_1_n_2 ,\cal_timer_reg[24]_i_1_n_3 ,\cal_timer_reg[24]_i_1_n_4 ,\cal_timer_reg[24]_i_1_n_5 ,\cal_timer_reg[24]_i_1_n_6 ,\cal_timer_reg[24]_i_1_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O(\SYNC[31].sync_reg_reg[1]_0 ),
        .S({\cal_timer[24]_i_2_n_0 ,\cal_timer[24]_i_3_n_0 ,\cal_timer[24]_i_4_n_0 ,\cal_timer[24]_i_5_n_0 ,\cal_timer[24]_i_6_n_0 ,\cal_timer[24]_i_7_n_0 ,\cal_timer[24]_i_8_n_0 ,\cal_timer[24]_i_9_n_0 }));
  (* ADDER_THRESHOLD = "16" *) 
  CARRY8 \cal_timer_reg[8]_i_1 
       (.CI(\cal_timer_reg[0]_i_2_n_0 ),
        .CI_TOP(1'b0),
        .CO({\cal_timer_reg[8]_i_1_n_0 ,\cal_timer_reg[8]_i_1_n_1 ,\cal_timer_reg[8]_i_1_n_2 ,\cal_timer_reg[8]_i_1_n_3 ,\cal_timer_reg[8]_i_1_n_4 ,\cal_timer_reg[8]_i_1_n_5 ,\cal_timer_reg[8]_i_1_n_6 ,\cal_timer_reg[8]_i_1_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O(\SYNC[15].sync_reg_reg[1]_0 ),
        .S({\cal_timer[8]_i_2_n_0 ,\cal_timer[8]_i_3_n_0 ,\cal_timer[8]_i_4_n_0 ,\cal_timer[8]_i_5_n_0 ,\cal_timer[8]_i_6_n_0 ,\cal_timer[8]_i_7_n_0 ,\cal_timer[8]_i_8_n_0 ,\cal_timer[8]_i_9_n_0 }));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL0[32]_i_1 
       (.I0(\SYNC[2].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL0_reg[32] ),
        .O(\SYNC[5].sync_reg_reg[1]_0 [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL0[33]_i_1 
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL0_reg[33] ),
        .O(\SYNC[5].sync_reg_reg[1]_0 [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL0[36]_i_1 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL0_reg[36] ),
        .O(\SYNC[5].sync_reg_reg[1]_0 [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL0[37]_i_1 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL0_reg[37] ),
        .O(\SYNC[5].sync_reg_reg[1]_0 [3]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \uppCL0[42]_i_1 
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL0_reg[36] ),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\uppCL0_reg[32] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[5].sync_reg_reg[1]_0 [4]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \uppCL0[43]_i_1 
       (.I0(\SYNC[1].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL0_reg[37] ),
        .I3(\SYNC[3].sync_reg [1]),
        .I4(\uppCL0_reg[33] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[5].sync_reg_reg[1]_0 [5]));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \uppCL0[44]_i_1 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL0_reg[46] ),
        .I3(\SYNC[2].sync_reg [1]),
        .I4(\uppCL0_reg[32] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[5].sync_reg_reg[1]_0 [6]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \uppCL0[45]_i_1 
       (.I0(\SYNC[3].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL0_reg[33] ),
        .I3(\SYNC[5].sync_reg [1]),
        .I4(\uppCL0_reg[47] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[5].sync_reg_reg[1]_0 [7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL0[46]_i_1 
       (.I0(\SYNC[4].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL0_reg[46] ),
        .O(\SYNC[5].sync_reg_reg[1]_0 [8]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL0[47]_i_1 
       (.I0(\SYNC[5].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL0_reg[47] ),
        .O(\SYNC[5].sync_reg_reg[1]_0 [9]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL1[32]_i_1 
       (.I0(\SYNC[10].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL1_reg[32] ),
        .O(\SYNC[13].sync_reg_reg[1]_0 [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL1[33]_i_1 
       (.I0(\SYNC[11].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL1_reg[33] ),
        .O(\SYNC[13].sync_reg_reg[1]_0 [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL1[36]_i_1 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL1_reg[36] ),
        .O(\SYNC[13].sync_reg_reg[1]_0 [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL1[37]_i_1 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL1_reg[37] ),
        .O(\SYNC[13].sync_reg_reg[1]_0 [3]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \uppCL1[42]_i_1 
       (.I0(\SYNC[8].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL1_reg[36] ),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\uppCL1_reg[32] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[13].sync_reg_reg[1]_0 [4]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \uppCL1[43]_i_1 
       (.I0(\SYNC[9].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL1_reg[37] ),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\uppCL1_reg[33] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[13].sync_reg_reg[1]_0 [5]));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \uppCL1[44]_i_1 
       (.I0(\SYNC[12].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL1_reg[46] ),
        .I3(\SYNC[10].sync_reg [1]),
        .I4(\uppCL1_reg[32] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[13].sync_reg_reg[1]_0 [6]));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \uppCL1[45]_i_1 
       (.I0(\SYNC[13].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL1_reg[47] ),
        .I3(\SYNC[11].sync_reg [1]),
        .I4(\uppCL1_reg[33] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[13].sync_reg_reg[1]_0 [7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL1[46]_i_1 
       (.I0(\SYNC[12].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL1_reg[46] ),
        .O(\SYNC[13].sync_reg_reg[1]_0 [8]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL1[47]_i_1 
       (.I0(\SYNC[13].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL1_reg[47] ),
        .O(\SYNC[13].sync_reg_reg[1]_0 [9]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL2[32]_i_1 
       (.I0(\SYNC[18].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL2_reg[32] ),
        .O(\SYNC[21].sync_reg_reg[1]_0 [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL2[33]_i_1 
       (.I0(\SYNC[19].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL2_reg[33] ),
        .O(\SYNC[21].sync_reg_reg[1]_0 [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL2[36]_i_1 
       (.I0(\SYNC[16].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL2_reg[36] ),
        .O(\SYNC[21].sync_reg_reg[1]_0 [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL2[37]_i_1 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL2_reg[37] ),
        .O(\SYNC[21].sync_reg_reg[1]_0 [3]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \uppCL2[42]_i_1 
       (.I0(\SYNC[16].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL2_reg[36] ),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\uppCL2_reg[32] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[21].sync_reg_reg[1]_0 [4]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \uppCL2[43]_i_1 
       (.I0(\SYNC[17].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL2_reg[37] ),
        .I3(\SYNC[19].sync_reg [1]),
        .I4(\uppCL2_reg[33] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[21].sync_reg_reg[1]_0 [5]));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \uppCL2[44]_i_1 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL2_reg[46] ),
        .I3(\SYNC[18].sync_reg [1]),
        .I4(\uppCL2_reg[32] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[21].sync_reg_reg[1]_0 [6]));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \uppCL2[45]_i_1 
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL2_reg[47] ),
        .I3(\SYNC[19].sync_reg [1]),
        .I4(\uppCL2_reg[33] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[21].sync_reg_reg[1]_0 [7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL2[46]_i_1 
       (.I0(\SYNC[20].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL2_reg[46] ),
        .O(\SYNC[21].sync_reg_reg[1]_0 [8]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL2[47]_i_1 
       (.I0(\SYNC[21].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL2_reg[47] ),
        .O(\SYNC[21].sync_reg_reg[1]_0 [9]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL3[32]_i_1 
       (.I0(\SYNC[26].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL3_reg[32] ),
        .O(\SYNC[29].sync_reg_reg[1]_0 [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL3[33]_i_1 
       (.I0(\SYNC[27].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL3_reg[33] ),
        .O(\SYNC[29].sync_reg_reg[1]_0 [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL3[36]_i_1 
       (.I0(\SYNC[24].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL3_reg[36] ),
        .O(\SYNC[29].sync_reg_reg[1]_0 [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL3[37]_i_1 
       (.I0(\SYNC[25].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL3_reg[37] ),
        .O(\SYNC[29].sync_reg_reg[1]_0 [3]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \uppCL3[42]_i_1 
       (.I0(\SYNC[24].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL3_reg[36] ),
        .I3(\SYNC[26].sync_reg [1]),
        .I4(\uppCL3_reg[32] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[29].sync_reg_reg[1]_0 [4]));
  LUT6 #(
    .INIT(64'hB8B8B8B8FF33CC00)) 
    \uppCL3[43]_i_1 
       (.I0(\SYNC[25].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL3_reg[37] ),
        .I3(\SYNC[27].sync_reg [1]),
        .I4(\uppCL3_reg[33] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[29].sync_reg_reg[1]_0 [5]));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \uppCL3[44]_i_1 
       (.I0(\SYNC[28].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL3_reg[46] ),
        .I3(\SYNC[26].sync_reg [1]),
        .I4(\uppCL3_reg[32] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[29].sync_reg_reg[1]_0 [6]));
  LUT6 #(
    .INIT(64'hFF33CC00B8B8B8B8)) 
    \uppCL3[45]_i_1 
       (.I0(\SYNC[29].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL3_reg[47] ),
        .I3(\SYNC[27].sync_reg [1]),
        .I4(\uppCL3_reg[33] ),
        .I5(\uppCL3_reg[44] [1]),
        .O(\SYNC[29].sync_reg_reg[1]_0 [7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL3[46]_i_1 
       (.I0(\SYNC[28].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL3_reg[46] ),
        .O(\SYNC[29].sync_reg_reg[1]_0 [8]));
  LUT3 #(
    .INIT(8'hB8)) 
    \uppCL3[47]_i_1 
       (.I0(\SYNC[29].sync_reg [1]),
        .I1(\uppCL3_reg[44] [0]),
        .I2(\uppCL3_reg[47] ),
        .O(\SYNC[29].sync_reg_reg[1]_0 [9]));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized9
   (out,
    \SYNC[0].sync_reg_reg[1]_0 ,
    D);
  output [0:0]out;
  input \SYNC[0].sync_reg_reg[1]_0 ;
  input [0:0]D;

  wire [0:0]D;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  wire \SYNC[0].sync_reg_reg[1]_0 ;

  assign out[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(D),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_sync" *) 
module ddr4_0_ddr4_v2_2_17_cal_sync__parameterized9_2
   (out,
    p_52_in,
    io_addr_strobe,
    \SYNC[0].sync_reg_reg[0]_0 ,
    D);
  output [0:0]out;
  output p_52_in;
  input io_addr_strobe;
  input \SYNC[0].sync_reg_reg[0]_0 ;
  input [0:0]D;

  wire [0:0]D;
  (* DONT_TOUCH *) (* RTL_KEEP = "yes" *) (* async_reg = "true" *) wire [1:0]\SYNC[0].sync_reg ;
  wire \SYNC[0].sync_reg_reg[0]_0 ;
  wire io_addr_strobe;
  wire p_52_in;

  assign out[0] = \SYNC[0].sync_reg [1];
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[0]_0 ),
        .CE(1'b1),
        .D(D),
        .Q(\SYNC[0].sync_reg [0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \SYNC[0].sync_reg_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[0]_0 ),
        .CE(1'b1),
        .D(\SYNC[0].sync_reg [0]),
        .Q(\SYNC[0].sync_reg [1]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    cmd_go_ind_i_1
       (.I0(\SYNC[0].sync_reg [1]),
        .I1(io_addr_strobe),
        .O(p_52_in));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_top" *) 
module ddr4_0_ddr4_v2_2_17_cal_top
   (sl_oport_o,
    douta,
    ub_calDone,
    calDone,
    initDone,
    \mcal_clb2phy_fifo_rden_reg[103]_0 ,
    \ch1_mcal_clb2phy_fifo_rden_reg[103]_0 ,
    calDone_gated_reg_0,
    sample_gts,
    io_addr_strobe,
    D,
    cnt_clr,
    cal_oe_dis_upp,
    cal_oe_dis_low,
    oe_0_mux_cal,
    rst_r1_reg_0,
    lrdimm_cmp_en,
    clear_gt_data_ready_flag_reg,
    gt_data_ready_flag,
    io_ready_lvl_reg,
    ub_initDone_reg,
    en_vtc,
    calWrCAS,
    cal_timer_reg,
    stop_gate_tracking_ack_reg,
    a_b_cmd_sel_start,
    rdCAS_reg,
    \cplx_CAS_reg[6] ,
    cal_CS_n,
    pointer_we,
    rd_data_en_phy2mc,
    per_rd_done,
    \wrQ_reg[0][0] ,
    cal_BA,
    p_0_in,
    \wrQ_reg[1][8] ,
    in0,
    \not_strict_mode.status_ram_0.RAM32M0 ,
    \not_strict_mode.bypass_cpy2 ,
    \rdDataAddr_reg[4] ,
    \rdData_reg[5]_0 ,
    match6_13_return,
    ADDRD,
    match4_13_return,
    \rdData_reg[11]_0 ,
    match6_14_return,
    \rdDataAddr_reg[4]_rep__0 ,
    match4_14_return,
    \rdData_reg[17]_0 ,
    match6_15_return,
    \rdDataAddr_reg[4]_rep__1 ,
    match4_15_return,
    \rdData_reg[23]_0 ,
    match6_16_return,
    match4_16_return,
    \rdData_reg[29]_0 ,
    match6_17_return,
    match4_17_return,
    \rdData_reg[35]_0 ,
    match6_18_return,
    match4_18_return,
    \rdData_reg[41]_0 ,
    match6_19_return,
    match4_19_return,
    \rdData_reg[47]_0 ,
    match6_110_return,
    match4_110_return,
    \rdData_reg[53]_0 ,
    match6_111_return,
    match4_111_return,
    \rdData_reg[59]_0 ,
    match6_112_return,
    match4_112_return,
    \rdData_reg[65]_0 ,
    match6_113_return,
    match4_113_return,
    \rdData_reg[71]_0 ,
    match6_114_return,
    match4_114_return,
    \rdData_reg[77]_0 ,
    match6_115_return,
    match4_115_return,
    \rdData_reg[83]_0 ,
    match6_116_return,
    match4_116_return,
    \rdData_reg[89]_0 ,
    match6_117_return,
    match4_117_return,
    \rdData_reg[95]_0 ,
    match6_118_return,
    match4_118_return,
    \rdData_reg[101]_0 ,
    match6_119_return,
    match4_119_return,
    \rdData_reg[107]_0 ,
    match6_120_return,
    match4_120_return,
    \rdData_reg[113]_0 ,
    match6_121_return,
    match4_121_return,
    \rdData_reg[119]_0 ,
    match6_122_return,
    match4_122_return,
    \rdData_reg[125]_0 ,
    match6_123_return,
    match4_123_return,
    \rdData_reg[131]_0 ,
    match6_124_return,
    match4_124_return,
    \rdData_reg[137]_0 ,
    match6_125_return,
    match4_125_return,
    \rdData_reg[143]_0 ,
    match6_126_return,
    match4_126_return,
    \rdData_reg[149]_0 ,
    match6_127_return,
    match4_127_return,
    \rdData_reg[155]_0 ,
    match6_128_return,
    match4_128_return,
    \rdData_reg[161]_0 ,
    match6_129_return,
    match4_129_return,
    \rdData_reg[167]_0 ,
    match6_130_return,
    match4_130_return,
    \rdData_reg[173]_0 ,
    match6_131_return,
    match4_131_return,
    \rdData_reg[179]_0 ,
    match6_132_return,
    match4_132_return,
    \rdData_reg[185]_0 ,
    match6_133_return,
    match4_133_return,
    \rdData_reg[191]_0 ,
    match6_134_return,
    match4_134_return,
    \rdData_reg[197]_0 ,
    match6_135_return,
    match4_135_return,
    \rdData_reg[203]_0 ,
    match6_136_return,
    match4_136_return,
    \rdData_reg[209]_0 ,
    match6_137_return,
    match4_137_return,
    \rdData_reg[215]_0 ,
    match6_138_return,
    match4_138_return,
    \rdData_reg[221]_0 ,
    match6_139_return,
    match4_139_return,
    \rdData_reg[227]_0 ,
    match6_140_return,
    match4_140_return,
    \rdData_reg[233]_0 ,
    match6_141_return,
    match4_141_return,
    \rdData_reg[239]_0 ,
    match6_142_return,
    match4_142_return,
    \rdData_reg[245]_0 ,
    match6_143_return,
    match4_143_return,
    \rdData_reg[251]_0 ,
    match6_144_return,
    match4_144_return,
    \rdData_reg[257]_0 ,
    match6_145_return,
    match4_145_return,
    \rdData_reg[263]_0 ,
    match6_146_return,
    match4_146_return,
    \rdData_reg[269]_0 ,
    match6_147_return,
    match4_147_return,
    \rdData_reg[275]_0 ,
    match6_148_return,
    match4_148_return,
    \rdData_reg[281]_0 ,
    match6_149_return,
    match4_149_return,
    \rdData_reg[287]_0 ,
    match6_150_return,
    match4_150_return,
    \rdData_reg[293]_0 ,
    match6_151_return,
    match4_151_return,
    \rdData_reg[299]_0 ,
    match6_152_return,
    match4_152_return,
    \rdData_reg[305]_0 ,
    match6_153_return,
    match4_153_return,
    \rdData_reg[311]_0 ,
    match6_154_return,
    match4_154_return,
    \rdData_reg[317]_0 ,
    match6_155_return,
    match4_155_return,
    \rdData_reg[323]_0 ,
    match6_156_return,
    match4_156_return,
    \rdData_reg[329]_0 ,
    match6_157_return,
    match4_157_return,
    \rdData_reg[335]_0 ,
    match6_158_return,
    match4_158_return,
    \rdData_reg[341]_0 ,
    match6_159_return,
    match4_159_return,
    \rdData_reg[347]_0 ,
    match6_160_return,
    match4_160_return,
    \rdData_reg[353]_0 ,
    match6_161_return,
    match4_161_return,
    \rdData_reg[359]_0 ,
    match6_162_return,
    match4_162_return,
    \rdData_reg[365]_0 ,
    match6_163_return,
    match4_163_return,
    \rdData_reg[371]_0 ,
    match6_164_return,
    match4_164_return,
    \rdData_reg[377]_0 ,
    match6_165_return,
    match4_165_return,
    \rdData_reg[383]_0 ,
    match6_166_return,
    match4_166_return,
    \rdData_reg[389]_0 ,
    match6_167_return,
    match4_167_return,
    \rdData_reg[395]_0 ,
    match6_168_return,
    match4_168_return,
    \rdData_reg[401]_0 ,
    match6_169_return,
    match4_169_return,
    \rdData_reg[407]_0 ,
    match6_170_return,
    match4_170_return,
    \rdData_reg[413]_0 ,
    match6_171_return,
    match4_171_return,
    \rdData_reg[419]_0 ,
    match6_172_return,
    match4_172_return,
    \rdData_reg[425]_0 ,
    match6_173_return,
    match4_173_return,
    \rdData_reg[431]_0 ,
    match6_174_return,
    match4_174_return,
    \rdData_reg[437]_0 ,
    match6_175_return,
    match4_175_return,
    \rdData_reg[443]_0 ,
    match6_176_return,
    match4_176_return,
    \rdData_reg[449]_0 ,
    match6_177_return,
    match4_177_return,
    \rdData_reg[455]_0 ,
    match6_178_return,
    match4_178_return,
    \rdData_reg[461]_0 ,
    match6_179_return,
    match4_179_return,
    \rdData_reg[467]_0 ,
    match6_180_return,
    match4_180_return,
    \rdData_reg[473]_0 ,
    match6_181_return,
    match4_181_return,
    \rdData_reg[479]_0 ,
    match6_182_return,
    match4_182_return,
    \rdData_reg[485]_0 ,
    match6_183_return,
    match4_183_return,
    \rdData_reg[491]_0 ,
    match6_184_return,
    match4_184_return,
    \rdData_reg[497]_0 ,
    match6_185_return,
    match4_185_return,
    \rdData_reg[503]_0 ,
    match6_186_return,
    match4_186_return,
    \rdData_reg[509]_0 ,
    match6_187_return,
    match4_187_return,
    \rdData_reg[511]_0 ,
    match6_188_return,
    match4_188_return,
    match4_1_return,
    match6_1_return,
    match4_10_return,
    match6_10_return,
    match4_11_return,
    match6_11_return,
    match4_12_return,
    match6_12_return,
    \SYNC[0].sync_reg_reg[1] ,
    \cal_seq_rd_cnt_reg[7] ,
    \cal_seq_cnt_reg[31] ,
    \cal_CS_A_reg[6] ,
    \mcal_DQIn_byte_r1_reg[48] ,
    \cal_CS_A_reg[7] ,
    \SYNC[20].sync_reg_reg[1] ,
    \cal_CS_A_reg[0] ,
    \cplx_error_accum_reg[14] ,
    \cplx_error_accum_reg[63] ,
    \cplx_error_accum_reg[15] ,
    \cplx_error_accum_reg[44] ,
    \cal_ADR_B_reg[12] ,
    \cplx_error_accum_reg[19] ,
    \cal_ADR_A_reg[0] ,
    \cal_RST_CKE_ODT_PAR_reg[30] ,
    cal_timer_reg_29_sp_1,
    cal_timer_reg_28_sp_1,
    cal_timer_reg_25_sp_1,
    cal_timer_reg_24_sp_1,
    cal_timer_reg_21_sp_1,
    \cal_CS_B_reg[5] ,
    \cal_CS_A_reg[5] ,
    \cal_ADR_B_reg[30] ,
    \cal_ADR_A_reg[30] ,
    \SYNC[5].sync_reg_reg[1] ,
    \SYNC[5].sync_reg_reg[1]_0 ,
    \mcal_DQIn_byte_r1_reg[31] ,
    \cal_ADR_A_reg[29] ,
    \cal_ADR_A_reg[27] ,
    \cal_ADR_A_reg[26] ,
    \cal_ADR_B_reg[25] ,
    \cal_ADR_B_reg[24] ,
    \cal_ADR_A_reg[21] ,
    \cal_ADR_A_reg[20] ,
    \cal_ADR_B_reg[19] ,
    \cal_ADR_B_reg[18] ,
    \cal_ADR_B_reg[17] ,
    \cal_RST_CKE_ODT_PAR_reg[16] ,
    \cal_ADR_B_reg[15] ,
    \cal_ADR_B_reg[13] ,
    \cal_ADR_B_reg[11] ,
    \cal_ADR_B_reg[10] ,
    \cal_RST_CKE_ODT_PAR_reg[9] ,
    \cal_ADR_A_reg[1] ,
    \cal_ADR_A_reg[4] ,
    \cal_seq_cnt_reg[13] ,
    mem_reg_bram_0,
    \cal_ADR_B_reg[31] ,
    \SYNC[3].sync_reg_reg[1] ,
    \SYNC[3].sync_reg_reg[1]_0 ,
    \SYNC[3].sync_reg_reg[1]_1 ,
    \SYNC[3].sync_reg_reg[1]_2 ,
    \SYNC[0].sync_reg_reg[1]_0 ,
    \SYNC[3].sync_reg_reg[1]_3 ,
    \SYNC[3].sync_reg_reg[1]_4 ,
    \SYNC[3].sync_reg_reg[1]_5 ,
    \SYNC[3].sync_reg_reg[1]_6 ,
    \SYNC[3].sync_reg_reg[1]_7 ,
    \SYNC[3].sync_reg_reg[1]_8 ,
    \SYNC[3].sync_reg_reg[1]_9 ,
    \SYNC[3].sync_reg_reg[1]_10 ,
    \SYNC[3].sync_reg_reg[1]_11 ,
    \SYNC[3].sync_reg_reg[1]_12 ,
    \SYNC[3].sync_reg_reg[1]_13 ,
    \SYNC[3].sync_reg_reg[1]_14 ,
    \SYNC[3].sync_reg_reg[1]_15 ,
    \SYNC[3].sync_reg_reg[1]_16 ,
    \SYNC[3].sync_reg_reg[1]_17 ,
    \SYNC[3].sync_reg_reg[1]_18 ,
    \SYNC[3].sync_reg_reg[1]_19 ,
    \SYNC[3].sync_reg_reg[1]_20 ,
    \SYNC[3].sync_reg_reg[1]_21 ,
    \SYNC[3].sync_reg_reg[1]_22 ,
    \SYNC[3].sync_reg_reg[1]_23 ,
    \SYNC[3].sync_reg_reg[1]_24 ,
    \SYNC[3].sync_reg_reg[1]_25 ,
    \SYNC[3].sync_reg_reg[1]_26 ,
    \SYNC[3].sync_reg_reg[1]_27 ,
    \SYNC[3].sync_reg_reg[1]_28 ,
    \SYNC[3].sync_reg_reg[1]_29 ,
    \SYNC[3].sync_reg_reg[1]_30 ,
    \SYNC[3].sync_reg_reg[1]_31 ,
    \SYNC[3].sync_reg_reg[1]_32 ,
    \SYNC[3].sync_reg_reg[1]_33 ,
    \SYNC[3].sync_reg_reg[1]_34 ,
    \SYNC[3].sync_reg_reg[1]_35 ,
    \SYNC[3].sync_reg_reg[1]_36 ,
    \SYNC[3].sync_reg_reg[1]_37 ,
    \SYNC[3].sync_reg_reg[1]_38 ,
    \SYNC[3].sync_reg_reg[1]_39 ,
    \SYNC[3].sync_reg_reg[1]_40 ,
    \SYNC[3].sync_reg_reg[1]_41 ,
    \SYNC[3].sync_reg_reg[1]_42 ,
    \SYNC[3].sync_reg_reg[1]_43 ,
    \SYNC[3].sync_reg_reg[1]_44 ,
    \SYNC[3].sync_reg_reg[1]_45 ,
    \SYNC[5].sync_reg_reg[1]_1 ,
    \SYNC[5].sync_reg_reg[1]_2 ,
    \SYNC[5].sync_reg_reg[1]_3 ,
    \SYNC[5].sync_reg_reg[1]_4 ,
    \cal_ADR_A_reg[22] ,
    \SYNC[5].sync_reg_reg[1]_5 ,
    \SYNC[5].sync_reg_reg[1]_6 ,
    \SYNC[5].sync_reg_reg[1]_7 ,
    \SYNC[5].sync_reg_reg[1]_8 ,
    \SYNC[5].sync_reg_reg[1]_9 ,
    \SYNC[5].sync_reg_reg[1]_10 ,
    \SYNC[5].sync_reg_reg[1]_11 ,
    \SYNC[5].sync_reg_reg[1]_12 ,
    \SYNC[5].sync_reg_reg[1]_13 ,
    \genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9] ,
    \genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8] ,
    \SYNC[4].sync_reg_reg[1] ,
    \mcal_DMIn_bit_r1_reg[7] ,
    \SYNC[5].sync_reg_reg[1]_14 ,
    \cal_ADR_A_reg[4]_0 ,
    \cal_CS_A_reg[4] ,
    \SYNC[4].sync_reg_reg[1]_0 ,
    \rd_vref_value_reg[46] ,
    \cal_ADR_A_reg[3] ,
    \SYNC[5].sync_reg_reg[1]_15 ,
    \cal_ADR_A_reg[2] ,
    \SYNC[18].sync_reg_reg[1] ,
    \SYNC[5].sync_reg_reg[1]_16 ,
    gt_data_ready_flag_reg,
    cplx_status,
    \cal_ADR_A_reg[0]_0 ,
    \dout_o_reg[5] ,
    \dout_o_reg[11] ,
    rst_r1_reg_1,
    S,
    \delay_cntr_reg[2] ,
    lrdimm_cal_mode_reg,
    lrdimm_cal_mode_reg_0,
    \SYNC[5].sync_reg_reg[1]_17 ,
    \rd_vref_value_reg[42] ,
    mcal_rd_vref_value,
    \rd_vref_value_reg[43] ,
    \rd_vref_value_reg[44] ,
    \rd_vref_value_reg[45] ,
    \rd_vref_value_reg[48] ,
    mcal_ACT_n,
    mcal_ADR,
    \mcal_BA_dly_reg[0][15]_0 ,
    \mcal_BG_dly_reg[0][7]_0 ,
    \mcal_CKE_dly_reg[0][7]_0 ,
    \mcal_CS_n_dly_reg[0][7]_0 ,
    \mcal_ODT_dly_reg[0][7]_0 ,
    \mcal_PAR_dly_reg[0][7]_0 ,
    \cal_RESET_n_reg[7]_0 ,
    ADDRC,
    ADDRA,
    \wrQ_reg[0][8]_rep__0 ,
    \wrQ_reg[0][8]_rep__1 ,
    \oe_upp_reg[3] ,
    \oe_low_reg[3] ,
    ch0_mcal_clb2phy_rden_upp,
    \io_read_data_reg[31] ,
    bisc_byte,
    underfill_done_nxt,
    \rdDataAddr_reg[4]_0 ,
    \rdDataAddr_reg[4]_1 ,
    \rdDataAddr_reg[4]_2 ,
    ch0_mcal_DQOut,
    ch0_mcal_DMOut_n,
    ch0_mcal_clb2phy_rden_low,
    out,
    \dReg_reg[10] ,
    ena,
    io_address,
    SR,
    mc_BG,
    mc_CKE,
    mc_CS_n,
    mc_ODT,
    io_addr_strobe_lvl_r1_reg_0,
    mcal_DQIn,
    calDone_reg,
    io_write_data,
    lrdimm_cmp_clr,
    lrdimm_cal_mode_reg_1,
    p_52_in,
    clear_gt_data_ready_flag,
    gt_data_ready_flag_nxt,
    ub_ready_reg,
    E,
    \clb2phy_wrcs0_low_reg[31] ,
    O,
    \cal_timer_reg[15] ,
    \cal_timer_reg[23] ,
    \cal_timer_reg[31] ,
    stop_gate_tracking_ack_reg_0,
    cnt_clr_reg,
    a_b_cmd_sel_start_reg,
    lrdimm_cmp_en_reg,
    cal_seq_cnt_gt_0_reg,
    xsdb_wr_en_reg,
    \cal_oe_dis_low_reg[7] ,
    \cal_oe_dis_upp_reg[7] ,
    pllGate,
    \calSt_reg[0] ,
    mc_BA,
    \rams[1].RAM32M0 ,
    winAct,
    calDone_gated_reg_1,
    mcRdCAS,
    mcCasSlot2,
    \mc_ADR7_reg[16]_0 ,
    mc_ADR,
    \mcal_PAR_dly_reg[0][5]_0 ,
    \mcal_PAR_dly_reg[0][3]_0 ,
    \mcal_PAR_dly_reg[0][1]_0 ,
    \mcal_PAR_dly_reg[0][7]_1 ,
    Q,
    \wrQ_reg[0][8] ,
    mcWrCAS,
    \wrQ_reg[1][8]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ,
    DOA,
    \not_strict_mode.app_rd_data_end_reg ,
    DOC,
    DOB,
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ,
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    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ,
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    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ,
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    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ,
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    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ,
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] ,
    \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] ,
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] ,
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] ,
    \cplx_config_reg[16] ,
    \cplx_config_reg[0] ,
    \cplx_config_reg[16]_0 ,
    cnt_clr_access,
    a_b_cmd_sel_start0,
    cal_timer_reg_0_sp_1,
    \addr_dec_to_mb_data[7]_i_7 ,
    io_ready_reg,
    \addr_dec_to_mb_data_reg[15] ,
    \addr_dec_to_mb_data_reg[19] ,
    \addr_dec_to_mb_data_reg[12] ,
    \addr_dec_to_mb_data[0]_i_3 ,
    io_ready_reg_0,
    io_ready_reg_1,
    \addr_dec_to_mb_data_reg[29] ,
    \addr_dec_to_mb_data_reg[29]_0 ,
    \addr_dec_to_mb_data_reg[14] ,
    \addr_dec_to_mb_data_reg[29]_1 ,
    \addr_dec_to_mb_data_reg[29]_2 ,
    \addr_dec_to_mb_data_reg[29]_3 ,
    \addr_dec_to_mb_data[4]_i_11 ,
    \addr_dec_to_mb_data[31]_i_3 ,
    \addr_dec_to_mb_data[6]_i_7 ,
    \addr_dec_to_mb_data[6]_i_7_0 ,
    \dout_o_reg[11]_0 ,
    \mcal_ADR_dly_reg[0][126]_0 ,
    \mcal_BA_dly_reg[0][4]_0 ,
    \mcal_BG_dly_reg[0][4]_0 ,
    \mcal_CS_n_dly_reg[0][6]_0 ,
    \mcal_ODT_dly_reg[0][7]_1 ,
    \cal_mcal_DMIn_n_reg[63]_0 ,
    \wrQ_reg[0][7]_rep ,
    \wrQ_reg[0][7]_rep__0 ,
    \wrQ_reg[0][7]_rep__1 ,
    \wrQ_reg[0][5]_rep ,
    \wrQ_reg[0][5]_rep__0 ,
    \wrQ_reg[0][5]_rep__1 ,
    \wrQ_reg[0][6]_rep ,
    \wrQ_reg[0][6]_rep__0 ,
    \wrQ_reg[0][6]_rep__1 ,
    \wrQ_reg[0][8]_rep ,
    \wrQ_reg[0][8]_rep__0_0 ,
    \wrQ_reg[0][8]_rep__1_0 ,
    \cal_seq_reg[2] ,
    \cal_cmp_en_reg[7] ,
    \cal_DQPat_A_reg[63] ,
    \cal_DQPat_A_reg[31] ,
    \cal_DQPat_B_reg[63] ,
    \cal_DQPat_B_reg[31] ,
    \cmp_byte_reg[2] ,
    \cal_cs_pos_reg[1] ,
    \cplx_config_reg[1] ,
    \cal_seq_a_b_dly_reg[7] ,
    \cal_seq_a_a_dly_reg[7] ,
    \cal_seq_b_a_dly_reg[7] ,
    \cal_RST_CKE_ODT_PAR_reg[31] ,
    \traffic_instr_nxt_instr_r1_reg[5] ,
    \uppCL3_reg[42] ,
    \uppCL0_reg[47] ,
    \uppCL1_reg[47] ,
    \uppCL2_reg[47] ,
    \uppCL3_reg[47] ,
    \cal_CS_A_reg[7]_0 ,
    \cal_CS_B_reg[7] ,
    \cal_ADR_A_reg[31] ,
    \cal_ADR_B_reg[31]_0 ,
    \addr_dec_to_mb_data_reg[31] ,
    \addr_dec_to_mb_data_reg[30] ,
    \addr_dec_to_mb_data_reg[30]_0 ,
    \addr_dec_to_mb_data_reg[29]_4 ,
    \addr_dec_to_mb_data_reg[28] ,
    \addr_dec_to_mb_data_reg[27] ,
    \addr_dec_to_mb_data_reg[26] ,
    \addr_dec_to_mb_data_reg[25] ,
    \addr_dec_to_mb_data_reg[24] ,
    \addr_dec_to_mb_data_reg[23] ,
    \addr_dec_to_mb_data_reg[22] ,
    \addr_dec_to_mb_data_reg[21] ,
    \addr_dec_to_mb_data_reg[20] ,
    \bisc_bit_reg[0] ,
    \cal_DQOut_A_reg[63] ,
    \cal_DQOut_A_reg[31] ,
    \cal_DQOut_pre_reg[63] ,
    \cal_DQOut_pre_reg[31] ,
    \cal_DQOut_post_reg[63] ,
    \cal_DQOut_post_reg[31] ,
    \cal_DMOut_n_A_reg[31] ,
    \genblk10[3].cal_DMOut_n_A_r_reg[24] ,
    \genblk10[6].cal_DMOut_n_A_r_reg[48] ,
    \cal_CAS_A_reg[0] ,
    \cal_RAS_B_reg[0] ,
    \cal_ACT_n_A_reg[7] ,
    \max_rd_lat_reg[5] ,
    rd_vref_value0_out,
    cmdBuf,
    \read_lat_fifo_in_reg[6] );
  output [16:0]sl_oport_o;
  output [8:0]douta;
  output ub_calDone;
  output calDone;
  output initDone;
  output [103:0]\mcal_clb2phy_fifo_rden_reg[103]_0 ;
  output [103:0]\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 ;
  output calDone_gated_reg_0;
  output sample_gts;
  output io_addr_strobe;
  output [511:0]D;
  output cnt_clr;
  output [0:0]cal_oe_dis_upp;
  output [0:0]cal_oe_dis_low;
  output [0:0]oe_0_mux_cal;
  output rst_r1_reg_0;
  output lrdimm_cmp_en;
  output clear_gt_data_ready_flag_reg;
  output gt_data_ready_flag;
  output [0:0]io_ready_lvl_reg;
  output ub_initDone_reg;
  output en_vtc;
  output calWrCAS;
  output [31:0]cal_timer_reg;
  output stop_gate_tracking_ack_reg;
  output a_b_cmd_sel_start;
  output rdCAS_reg;
  output [7:0]\cplx_CAS_reg[6] ;
  output [3:0]cal_CS_n;
  output pointer_we;
  output rd_data_en_phy2mc;
  output per_rd_done;
  output [0:0]\wrQ_reg[0][0] ;
  output [0:0]cal_BA;
  output [0:0]p_0_in;
  output [3:0]\wrQ_reg[1][8] ;
  output [85:0]in0;
  output \not_strict_mode.status_ram_0.RAM32M0 ;
  output \not_strict_mode.bypass_cpy2 ;
  output [4:0]\rdDataAddr_reg[4] ;
  output [5:0]\rdData_reg[5]_0 ;
  output match6_13_return;
  output [1:0]ADDRD;
  output match4_13_return;
  output [5:0]\rdData_reg[11]_0 ;
  output match6_14_return;
  output [1:0]\rdDataAddr_reg[4]_rep__0 ;
  output match4_14_return;
  output [5:0]\rdData_reg[17]_0 ;
  output match6_15_return;
  output [1:0]\rdDataAddr_reg[4]_rep__1 ;
  output match4_15_return;
  output [5:0]\rdData_reg[23]_0 ;
  output match6_16_return;
  output match4_16_return;
  output [5:0]\rdData_reg[29]_0 ;
  output match6_17_return;
  output match4_17_return;
  output [5:0]\rdData_reg[35]_0 ;
  output match6_18_return;
  output match4_18_return;
  output [5:0]\rdData_reg[41]_0 ;
  output match6_19_return;
  output match4_19_return;
  output [5:0]\rdData_reg[47]_0 ;
  output match6_110_return;
  output match4_110_return;
  output [5:0]\rdData_reg[53]_0 ;
  output match6_111_return;
  output match4_111_return;
  output [5:0]\rdData_reg[59]_0 ;
  output match6_112_return;
  output match4_112_return;
  output [5:0]\rdData_reg[65]_0 ;
  output match6_113_return;
  output match4_113_return;
  output [5:0]\rdData_reg[71]_0 ;
  output match6_114_return;
  output match4_114_return;
  output [5:0]\rdData_reg[77]_0 ;
  output match6_115_return;
  output match4_115_return;
  output [5:0]\rdData_reg[83]_0 ;
  output match6_116_return;
  output match4_116_return;
  output [5:0]\rdData_reg[89]_0 ;
  output match6_117_return;
  output match4_117_return;
  output [5:0]\rdData_reg[95]_0 ;
  output match6_118_return;
  output match4_118_return;
  output [5:0]\rdData_reg[101]_0 ;
  output match6_119_return;
  output match4_119_return;
  output [5:0]\rdData_reg[107]_0 ;
  output match6_120_return;
  output match4_120_return;
  output [5:0]\rdData_reg[113]_0 ;
  output match6_121_return;
  output match4_121_return;
  output [5:0]\rdData_reg[119]_0 ;
  output match6_122_return;
  output match4_122_return;
  output [5:0]\rdData_reg[125]_0 ;
  output match6_123_return;
  output match4_123_return;
  output [5:0]\rdData_reg[131]_0 ;
  output match6_124_return;
  output match4_124_return;
  output [5:0]\rdData_reg[137]_0 ;
  output match6_125_return;
  output match4_125_return;
  output [5:0]\rdData_reg[143]_0 ;
  output match6_126_return;
  output match4_126_return;
  output [5:0]\rdData_reg[149]_0 ;
  output match6_127_return;
  output match4_127_return;
  output [5:0]\rdData_reg[155]_0 ;
  output match6_128_return;
  output match4_128_return;
  output [5:0]\rdData_reg[161]_0 ;
  output match6_129_return;
  output match4_129_return;
  output [5:0]\rdData_reg[167]_0 ;
  output match6_130_return;
  output match4_130_return;
  output [5:0]\rdData_reg[173]_0 ;
  output match6_131_return;
  output match4_131_return;
  output [5:0]\rdData_reg[179]_0 ;
  output match6_132_return;
  output match4_132_return;
  output [5:0]\rdData_reg[185]_0 ;
  output match6_133_return;
  output match4_133_return;
  output [5:0]\rdData_reg[191]_0 ;
  output match6_134_return;
  output match4_134_return;
  output [5:0]\rdData_reg[197]_0 ;
  output match6_135_return;
  output match4_135_return;
  output [5:0]\rdData_reg[203]_0 ;
  output match6_136_return;
  output match4_136_return;
  output [5:0]\rdData_reg[209]_0 ;
  output match6_137_return;
  output match4_137_return;
  output [5:0]\rdData_reg[215]_0 ;
  output match6_138_return;
  output match4_138_return;
  output [5:0]\rdData_reg[221]_0 ;
  output match6_139_return;
  output match4_139_return;
  output [5:0]\rdData_reg[227]_0 ;
  output match6_140_return;
  output match4_140_return;
  output [5:0]\rdData_reg[233]_0 ;
  output match6_141_return;
  output match4_141_return;
  output [5:0]\rdData_reg[239]_0 ;
  output match6_142_return;
  output match4_142_return;
  output [5:0]\rdData_reg[245]_0 ;
  output match6_143_return;
  output match4_143_return;
  output [5:0]\rdData_reg[251]_0 ;
  output match6_144_return;
  output match4_144_return;
  output [5:0]\rdData_reg[257]_0 ;
  output match6_145_return;
  output match4_145_return;
  output [5:0]\rdData_reg[263]_0 ;
  output match6_146_return;
  output match4_146_return;
  output [5:0]\rdData_reg[269]_0 ;
  output match6_147_return;
  output match4_147_return;
  output [5:0]\rdData_reg[275]_0 ;
  output match6_148_return;
  output match4_148_return;
  output [5:0]\rdData_reg[281]_0 ;
  output match6_149_return;
  output match4_149_return;
  output [5:0]\rdData_reg[287]_0 ;
  output match6_150_return;
  output match4_150_return;
  output [5:0]\rdData_reg[293]_0 ;
  output match6_151_return;
  output match4_151_return;
  output [5:0]\rdData_reg[299]_0 ;
  output match6_152_return;
  output match4_152_return;
  output [5:0]\rdData_reg[305]_0 ;
  output match6_153_return;
  output match4_153_return;
  output [5:0]\rdData_reg[311]_0 ;
  output match6_154_return;
  output match4_154_return;
  output [5:0]\rdData_reg[317]_0 ;
  output match6_155_return;
  output match4_155_return;
  output [5:0]\rdData_reg[323]_0 ;
  output match6_156_return;
  output match4_156_return;
  output [5:0]\rdData_reg[329]_0 ;
  output match6_157_return;
  output match4_157_return;
  output [5:0]\rdData_reg[335]_0 ;
  output match6_158_return;
  output match4_158_return;
  output [5:0]\rdData_reg[341]_0 ;
  output match6_159_return;
  output match4_159_return;
  output [5:0]\rdData_reg[347]_0 ;
  output match6_160_return;
  output match4_160_return;
  output [5:0]\rdData_reg[353]_0 ;
  output match6_161_return;
  output match4_161_return;
  output [5:0]\rdData_reg[359]_0 ;
  output match6_162_return;
  output match4_162_return;
  output [5:0]\rdData_reg[365]_0 ;
  output match6_163_return;
  output match4_163_return;
  output [5:0]\rdData_reg[371]_0 ;
  output match6_164_return;
  output match4_164_return;
  output [5:0]\rdData_reg[377]_0 ;
  output match6_165_return;
  output match4_165_return;
  output [5:0]\rdData_reg[383]_0 ;
  output match6_166_return;
  output match4_166_return;
  output [5:0]\rdData_reg[389]_0 ;
  output match6_167_return;
  output match4_167_return;
  output [5:0]\rdData_reg[395]_0 ;
  output match6_168_return;
  output match4_168_return;
  output [5:0]\rdData_reg[401]_0 ;
  output match6_169_return;
  output match4_169_return;
  output [5:0]\rdData_reg[407]_0 ;
  output match6_170_return;
  output match4_170_return;
  output [5:0]\rdData_reg[413]_0 ;
  output match6_171_return;
  output match4_171_return;
  output [5:0]\rdData_reg[419]_0 ;
  output match6_172_return;
  output match4_172_return;
  output [5:0]\rdData_reg[425]_0 ;
  output match6_173_return;
  output match4_173_return;
  output [5:0]\rdData_reg[431]_0 ;
  output match6_174_return;
  output match4_174_return;
  output [5:0]\rdData_reg[437]_0 ;
  output match6_175_return;
  output match4_175_return;
  output [5:0]\rdData_reg[443]_0 ;
  output match6_176_return;
  output match4_176_return;
  output [5:0]\rdData_reg[449]_0 ;
  output match6_177_return;
  output match4_177_return;
  output [5:0]\rdData_reg[455]_0 ;
  output match6_178_return;
  output match4_178_return;
  output [5:0]\rdData_reg[461]_0 ;
  output match6_179_return;
  output match4_179_return;
  output [5:0]\rdData_reg[467]_0 ;
  output match6_180_return;
  output match4_180_return;
  output [5:0]\rdData_reg[473]_0 ;
  output match6_181_return;
  output match4_181_return;
  output [5:0]\rdData_reg[479]_0 ;
  output match6_182_return;
  output match4_182_return;
  output [5:0]\rdData_reg[485]_0 ;
  output match6_183_return;
  output match4_183_return;
  output [5:0]\rdData_reg[491]_0 ;
  output match6_184_return;
  output match4_184_return;
  output [5:0]\rdData_reg[497]_0 ;
  output match6_185_return;
  output match4_185_return;
  output [5:0]\rdData_reg[503]_0 ;
  output match6_186_return;
  output match4_186_return;
  output [5:0]\rdData_reg[509]_0 ;
  output match6_187_return;
  output match4_187_return;
  output [1:0]\rdData_reg[511]_0 ;
  output match6_188_return;
  output match4_188_return;
  output match4_1_return;
  output match6_1_return;
  output match4_10_return;
  output match6_10_return;
  output match4_11_return;
  output match6_11_return;
  output match4_12_return;
  output match6_12_return;
  output \SYNC[0].sync_reg_reg[1] ;
  output [7:0]\cal_seq_rd_cnt_reg[7] ;
  output [31:0]\cal_seq_cnt_reg[31] ;
  output \cal_CS_A_reg[6] ;
  output [9:0]\mcal_DQIn_byte_r1_reg[48] ;
  output \cal_CS_A_reg[7] ;
  output \SYNC[20].sync_reg_reg[1] ;
  output \cal_CS_A_reg[0] ;
  output \cplx_error_accum_reg[14] ;
  output [53:0]\cplx_error_accum_reg[63] ;
  output \cplx_error_accum_reg[15] ;
  output \cplx_error_accum_reg[44] ;
  output \cal_ADR_B_reg[12] ;
  output \cplx_error_accum_reg[19] ;
  output \cal_ADR_A_reg[0] ;
  output [10:0]\cal_RST_CKE_ODT_PAR_reg[30] ;
  output cal_timer_reg_29_sp_1;
  output cal_timer_reg_28_sp_1;
  output cal_timer_reg_25_sp_1;
  output cal_timer_reg_24_sp_1;
  output cal_timer_reg_21_sp_1;
  output [4:0]\cal_CS_B_reg[5] ;
  output [4:0]\cal_CS_A_reg[5] ;
  output [12:0]\cal_ADR_B_reg[30] ;
  output [11:0]\cal_ADR_A_reg[30] ;
  output \SYNC[5].sync_reg_reg[1] ;
  output \SYNC[5].sync_reg_reg[1]_0 ;
  output \mcal_DQIn_byte_r1_reg[31] ;
  output \cal_ADR_A_reg[29] ;
  output \cal_ADR_A_reg[27] ;
  output \cal_ADR_A_reg[26] ;
  output \cal_ADR_B_reg[25] ;
  output \cal_ADR_B_reg[24] ;
  output \cal_ADR_A_reg[21] ;
  output \cal_ADR_A_reg[20] ;
  output \cal_ADR_B_reg[19] ;
  output \cal_ADR_B_reg[18] ;
  output \cal_ADR_B_reg[17] ;
  output \cal_RST_CKE_ODT_PAR_reg[16] ;
  output \cal_ADR_B_reg[15] ;
  output \cal_ADR_B_reg[13] ;
  output \cal_ADR_B_reg[11] ;
  output \cal_ADR_B_reg[10] ;
  output \cal_RST_CKE_ODT_PAR_reg[9] ;
  output \cal_ADR_A_reg[1] ;
  output \cal_ADR_A_reg[4] ;
  output \cal_seq_cnt_reg[13] ;
  output mem_reg_bram_0;
  output \cal_ADR_B_reg[31] ;
  output \SYNC[3].sync_reg_reg[1] ;
  output \SYNC[3].sync_reg_reg[1]_0 ;
  output \SYNC[3].sync_reg_reg[1]_1 ;
  output \SYNC[3].sync_reg_reg[1]_2 ;
  output \SYNC[0].sync_reg_reg[1]_0 ;
  output \SYNC[3].sync_reg_reg[1]_3 ;
  output \SYNC[3].sync_reg_reg[1]_4 ;
  output \SYNC[3].sync_reg_reg[1]_5 ;
  output \SYNC[3].sync_reg_reg[1]_6 ;
  output \SYNC[3].sync_reg_reg[1]_7 ;
  output \SYNC[3].sync_reg_reg[1]_8 ;
  output \SYNC[3].sync_reg_reg[1]_9 ;
  output \SYNC[3].sync_reg_reg[1]_10 ;
  output \SYNC[3].sync_reg_reg[1]_11 ;
  output \SYNC[3].sync_reg_reg[1]_12 ;
  output \SYNC[3].sync_reg_reg[1]_13 ;
  output \SYNC[3].sync_reg_reg[1]_14 ;
  output \SYNC[3].sync_reg_reg[1]_15 ;
  output \SYNC[3].sync_reg_reg[1]_16 ;
  output \SYNC[3].sync_reg_reg[1]_17 ;
  output \SYNC[3].sync_reg_reg[1]_18 ;
  output \SYNC[3].sync_reg_reg[1]_19 ;
  output \SYNC[3].sync_reg_reg[1]_20 ;
  output \SYNC[3].sync_reg_reg[1]_21 ;
  output \SYNC[3].sync_reg_reg[1]_22 ;
  output \SYNC[3].sync_reg_reg[1]_23 ;
  output \SYNC[3].sync_reg_reg[1]_24 ;
  output \SYNC[3].sync_reg_reg[1]_25 ;
  output \SYNC[3].sync_reg_reg[1]_26 ;
  output \SYNC[3].sync_reg_reg[1]_27 ;
  output \SYNC[3].sync_reg_reg[1]_28 ;
  output \SYNC[3].sync_reg_reg[1]_29 ;
  output \SYNC[3].sync_reg_reg[1]_30 ;
  output \SYNC[3].sync_reg_reg[1]_31 ;
  output \SYNC[3].sync_reg_reg[1]_32 ;
  output \SYNC[3].sync_reg_reg[1]_33 ;
  output \SYNC[3].sync_reg_reg[1]_34 ;
  output \SYNC[3].sync_reg_reg[1]_35 ;
  output \SYNC[3].sync_reg_reg[1]_36 ;
  output \SYNC[3].sync_reg_reg[1]_37 ;
  output \SYNC[3].sync_reg_reg[1]_38 ;
  output \SYNC[3].sync_reg_reg[1]_39 ;
  output \SYNC[3].sync_reg_reg[1]_40 ;
  output \SYNC[3].sync_reg_reg[1]_41 ;
  output \SYNC[3].sync_reg_reg[1]_42 ;
  output \SYNC[3].sync_reg_reg[1]_43 ;
  output \SYNC[3].sync_reg_reg[1]_44 ;
  output \SYNC[3].sync_reg_reg[1]_45 ;
  output \SYNC[5].sync_reg_reg[1]_1 ;
  output \SYNC[5].sync_reg_reg[1]_2 ;
  output \SYNC[5].sync_reg_reg[1]_3 ;
  output \SYNC[5].sync_reg_reg[1]_4 ;
  output \cal_ADR_A_reg[22] ;
  output \SYNC[5].sync_reg_reg[1]_5 ;
  output \SYNC[5].sync_reg_reg[1]_6 ;
  output \SYNC[5].sync_reg_reg[1]_7 ;
  output \SYNC[5].sync_reg_reg[1]_8 ;
  output \SYNC[5].sync_reg_reg[1]_9 ;
  output \SYNC[5].sync_reg_reg[1]_10 ;
  output \SYNC[5].sync_reg_reg[1]_11 ;
  output \SYNC[5].sync_reg_reg[1]_12 ;
  output \SYNC[5].sync_reg_reg[1]_13 ;
  output \genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9] ;
  output \genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8] ;
  output \SYNC[4].sync_reg_reg[1] ;
  output [6:0]\mcal_DMIn_bit_r1_reg[7] ;
  output \SYNC[5].sync_reg_reg[1]_14 ;
  output \cal_ADR_A_reg[4]_0 ;
  output \cal_CS_A_reg[4] ;
  output \SYNC[4].sync_reg_reg[1]_0 ;
  output \rd_vref_value_reg[46] ;
  output \cal_ADR_A_reg[3] ;
  output \SYNC[5].sync_reg_reg[1]_15 ;
  output \cal_ADR_A_reg[2] ;
  output \SYNC[18].sync_reg_reg[1] ;
  output \SYNC[5].sync_reg_reg[1]_16 ;
  output gt_data_ready_flag_reg;
  output [0:0]cplx_status;
  output \cal_ADR_A_reg[0]_0 ;
  output \dout_o_reg[5] ;
  output [10:0]\dout_o_reg[11] ;
  output rst_r1_reg_1;
  output [0:0]S;
  output [1:0]\delay_cntr_reg[2] ;
  output lrdimm_cal_mode_reg;
  output lrdimm_cal_mode_reg_0;
  output \SYNC[5].sync_reg_reg[1]_17 ;
  output \rd_vref_value_reg[42] ;
  output [55:0]mcal_rd_vref_value;
  output \rd_vref_value_reg[43] ;
  output \rd_vref_value_reg[44] ;
  output \rd_vref_value_reg[45] ;
  output \rd_vref_value_reg[48] ;
  output [7:0]mcal_ACT_n;
  output [88:0]mcal_ADR;
  output [9:0]\mcal_BA_dly_reg[0][15]_0 ;
  output [4:0]\mcal_BG_dly_reg[0][7]_0 ;
  output [2:0]\mcal_CKE_dly_reg[0][7]_0 ;
  output [7:0]\mcal_CS_n_dly_reg[0][7]_0 ;
  output [4:0]\mcal_ODT_dly_reg[0][7]_0 ;
  output [7:0]\mcal_PAR_dly_reg[0][7]_0 ;
  output [7:0]\cal_RESET_n_reg[7]_0 ;
  output [3:0]ADDRC;
  output [3:0]ADDRA;
  output [3:0]\wrQ_reg[0][8]_rep__0 ;
  output [3:0]\wrQ_reg[0][8]_rep__1 ;
  output [3:0]\oe_upp_reg[3] ;
  output [3:0]\oe_low_reg[3] ;
  output [31:0]ch0_mcal_clb2phy_rden_upp;
  output [31:0]\io_read_data_reg[31] ;
  output [8:0]bisc_byte;
  output underfill_done_nxt;
  output \rdDataAddr_reg[4]_0 ;
  output \rdDataAddr_reg[4]_1 ;
  output \rdDataAddr_reg[4]_2 ;
  output [511:0]ch0_mcal_DQOut;
  output [63:0]ch0_mcal_DMOut_n;
  output [31:0]ch0_mcal_clb2phy_rden_low;
  input [36:0]out;
  input \dReg_reg[10] ;
  input ena;
  input [20:0]io_address;
  input [0:0]SR;
  input [2:0]mc_BG;
  input [1:0]mc_CKE;
  input [0:0]mc_CS_n;
  input [1:0]mc_ODT;
  input [0:0]io_addr_strobe_lvl_r1_reg_0;
  input [511:0]mcal_DQIn;
  input calDone_reg;
  input [31:0]io_write_data;
  input lrdimm_cmp_clr;
  input lrdimm_cal_mode_reg_1;
  input p_52_in;
  input clear_gt_data_ready_flag;
  input gt_data_ready_flag_nxt;
  input ub_ready_reg;
  input [0:0]E;
  input \clb2phy_wrcs0_low_reg[31] ;
  input [7:0]O;
  input [7:0]\cal_timer_reg[15] ;
  input [7:0]\cal_timer_reg[23] ;
  input [7:0]\cal_timer_reg[31] ;
  input stop_gate_tracking_ack_reg_0;
  input cnt_clr_reg;
  input a_b_cmd_sel_start_reg;
  input lrdimm_cmp_en_reg;
  input cal_seq_cnt_gt_0_reg;
  input [0:0]xsdb_wr_en_reg;
  input \cal_oe_dis_low_reg[7] ;
  input \cal_oe_dis_upp_reg[7] ;
  input pllGate;
  input \calSt_reg[0] ;
  input [6:0]mc_BA;
  input [0:0]\rams[1].RAM32M0 ;
  input winAct;
  input [0:0]calDone_gated_reg_1;
  input mcRdCAS;
  input mcCasSlot2;
  input [4:0]\mc_ADR7_reg[16]_0 ;
  input [35:0]mc_ADR;
  input \mcal_PAR_dly_reg[0][5]_0 ;
  input \mcal_PAR_dly_reg[0][3]_0 ;
  input \mcal_PAR_dly_reg[0][1]_0 ;
  input \mcal_PAR_dly_reg[0][7]_1 ;
  input [575:0]Q;
  input [3:0]\wrQ_reg[0][8] ;
  input mcWrCAS;
  input [4:0]\wrQ_reg[1][8]_0 ;
  input [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ;
  input [0:0]DOA;
  input [4:0]\not_strict_mode.app_rd_data_end_reg ;
  input [1:0]DOC;
  input [1:0]DOB;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ;
  input [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ;
  input [4:0]\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] ;
  input [4:0]\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] ;
  input [4:0]\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] ;
  input [4:0]\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] ;
  input [0:0]\cplx_config_reg[16] ;
  input [0:0]\cplx_config_reg[0] ;
  input \cplx_config_reg[16]_0 ;
  input cnt_clr_access;
  input a_b_cmd_sel_start0;
  input cal_timer_reg_0_sp_1;
  input \addr_dec_to_mb_data[7]_i_7 ;
  input io_ready_reg;
  input \addr_dec_to_mb_data_reg[15] ;
  input \addr_dec_to_mb_data_reg[19] ;
  input \addr_dec_to_mb_data_reg[12] ;
  input \addr_dec_to_mb_data[0]_i_3 ;
  input io_ready_reg_0;
  input io_ready_reg_1;
  input \addr_dec_to_mb_data_reg[29] ;
  input \addr_dec_to_mb_data_reg[29]_0 ;
  input \addr_dec_to_mb_data_reg[14] ;
  input \addr_dec_to_mb_data_reg[29]_1 ;
  input \addr_dec_to_mb_data_reg[29]_2 ;
  input \addr_dec_to_mb_data_reg[29]_3 ;
  input \addr_dec_to_mb_data[4]_i_11 ;
  input \addr_dec_to_mb_data[31]_i_3 ;
  input \addr_dec_to_mb_data[6]_i_7 ;
  input \addr_dec_to_mb_data[6]_i_7_0 ;
  input [10:0]\dout_o_reg[11]_0 ;
  input [7:0]\mcal_ADR_dly_reg[0][126]_0 ;
  input [0:0]\mcal_BA_dly_reg[0][4]_0 ;
  input [0:0]\mcal_BG_dly_reg[0][4]_0 ;
  input [3:0]\mcal_CS_n_dly_reg[0][6]_0 ;
  input [1:0]\mcal_ODT_dly_reg[0][7]_1 ;
  input [63:0]\cal_mcal_DMIn_n_reg[63]_0 ;
  input \wrQ_reg[0][7]_rep ;
  input \wrQ_reg[0][7]_rep__0 ;
  input \wrQ_reg[0][7]_rep__1 ;
  input \wrQ_reg[0][5]_rep ;
  input \wrQ_reg[0][5]_rep__0 ;
  input \wrQ_reg[0][5]_rep__1 ;
  input \wrQ_reg[0][6]_rep ;
  input \wrQ_reg[0][6]_rep__0 ;
  input \wrQ_reg[0][6]_rep__1 ;
  input \wrQ_reg[0][8]_rep ;
  input \wrQ_reg[0][8]_rep__0_0 ;
  input \wrQ_reg[0][8]_rep__1_0 ;
  input [0:0]\cal_seq_reg[2] ;
  input [0:0]\cal_cmp_en_reg[7] ;
  input \cal_DQPat_A_reg[63] ;
  input \cal_DQPat_A_reg[31] ;
  input \cal_DQPat_B_reg[63] ;
  input \cal_DQPat_B_reg[31] ;
  input [0:0]\cmp_byte_reg[2] ;
  input [0:0]\cal_cs_pos_reg[1] ;
  input \cplx_config_reg[1] ;
  input [0:0]\cal_seq_a_b_dly_reg[7] ;
  input [0:0]\cal_seq_a_a_dly_reg[7] ;
  input [0:0]\cal_seq_b_a_dly_reg[7] ;
  input [0:0]\cal_RST_CKE_ODT_PAR_reg[31] ;
  input [0:0]\traffic_instr_nxt_instr_r1_reg[5] ;
  input [7:0]\uppCL3_reg[42] ;
  input [9:0]\uppCL0_reg[47] ;
  input [9:0]\uppCL1_reg[47] ;
  input [9:0]\uppCL2_reg[47] ;
  input [9:0]\uppCL3_reg[47] ;
  input [0:0]\cal_CS_A_reg[7]_0 ;
  input [0:0]\cal_CS_B_reg[7] ;
  input [0:0]\cal_ADR_A_reg[31] ;
  input [0:0]\cal_ADR_B_reg[31]_0 ;
  input [20:0]\addr_dec_to_mb_data_reg[31] ;
  input \addr_dec_to_mb_data_reg[30] ;
  input \addr_dec_to_mb_data_reg[30]_0 ;
  input \addr_dec_to_mb_data_reg[29]_4 ;
  input \addr_dec_to_mb_data_reg[28] ;
  input \addr_dec_to_mb_data_reg[27] ;
  input \addr_dec_to_mb_data_reg[26] ;
  input \addr_dec_to_mb_data_reg[25] ;
  input \addr_dec_to_mb_data_reg[24] ;
  input \addr_dec_to_mb_data_reg[23] ;
  input \addr_dec_to_mb_data_reg[22] ;
  input \addr_dec_to_mb_data_reg[21] ;
  input \addr_dec_to_mb_data_reg[20] ;
  input [0:0]\bisc_bit_reg[0] ;
  input \cal_DQOut_A_reg[63] ;
  input \cal_DQOut_A_reg[31] ;
  input \cal_DQOut_pre_reg[63] ;
  input \cal_DQOut_pre_reg[31] ;
  input \cal_DQOut_post_reg[63] ;
  input \cal_DQOut_post_reg[31] ;
  input [0:0]\cal_DMOut_n_A_reg[31] ;
  input [0:0]\genblk10[3].cal_DMOut_n_A_r_reg[24] ;
  input [0:0]\genblk10[6].cal_DMOut_n_A_r_reg[48] ;
  input [0:0]\cal_CAS_A_reg[0] ;
  input [0:0]\cal_RAS_B_reg[0] ;
  input [0:0]\cal_ACT_n_A_reg[7] ;
  input [0:0]\max_rd_lat_reg[5] ;
  input [7:0]rd_vref_value0_out;
  input [19:0]cmdBuf;
  input [6:0]\read_lat_fifo_in_reg[6] ;

  wire [3:0]ADDRA;
  wire [3:0]ADDRC;
  wire [1:0]ADDRD;
  wire [511:0]D;
  wire [63:0]DMOut;
  wire [0:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire [511:0]DQOut;
  wire [0:0]E;
  wire [7:0]O;
  wire [575:0]Q;
  wire [0:0]S;
  wire [0:0]SR;
  wire \SYNC[0].sync_reg_reg[1] ;
  wire \SYNC[0].sync_reg_reg[1]_0 ;
  wire \SYNC[18].sync_reg_reg[1] ;
  wire \SYNC[20].sync_reg_reg[1] ;
  wire \SYNC[3].sync_reg_reg[1] ;
  wire \SYNC[3].sync_reg_reg[1]_0 ;
  wire \SYNC[3].sync_reg_reg[1]_1 ;
  wire \SYNC[3].sync_reg_reg[1]_10 ;
  wire \SYNC[3].sync_reg_reg[1]_11 ;
  wire \SYNC[3].sync_reg_reg[1]_12 ;
  wire \SYNC[3].sync_reg_reg[1]_13 ;
  wire \SYNC[3].sync_reg_reg[1]_14 ;
  wire \SYNC[3].sync_reg_reg[1]_15 ;
  wire \SYNC[3].sync_reg_reg[1]_16 ;
  wire \SYNC[3].sync_reg_reg[1]_17 ;
  wire \SYNC[3].sync_reg_reg[1]_18 ;
  wire \SYNC[3].sync_reg_reg[1]_19 ;
  wire \SYNC[3].sync_reg_reg[1]_2 ;
  wire \SYNC[3].sync_reg_reg[1]_20 ;
  wire \SYNC[3].sync_reg_reg[1]_21 ;
  wire \SYNC[3].sync_reg_reg[1]_22 ;
  wire \SYNC[3].sync_reg_reg[1]_23 ;
  wire \SYNC[3].sync_reg_reg[1]_24 ;
  wire \SYNC[3].sync_reg_reg[1]_25 ;
  wire \SYNC[3].sync_reg_reg[1]_26 ;
  wire \SYNC[3].sync_reg_reg[1]_27 ;
  wire \SYNC[3].sync_reg_reg[1]_28 ;
  wire \SYNC[3].sync_reg_reg[1]_29 ;
  wire \SYNC[3].sync_reg_reg[1]_3 ;
  wire \SYNC[3].sync_reg_reg[1]_30 ;
  wire \SYNC[3].sync_reg_reg[1]_31 ;
  wire \SYNC[3].sync_reg_reg[1]_32 ;
  wire \SYNC[3].sync_reg_reg[1]_33 ;
  wire \SYNC[3].sync_reg_reg[1]_34 ;
  wire \SYNC[3].sync_reg_reg[1]_35 ;
  wire \SYNC[3].sync_reg_reg[1]_36 ;
  wire \SYNC[3].sync_reg_reg[1]_37 ;
  wire \SYNC[3].sync_reg_reg[1]_38 ;
  wire \SYNC[3].sync_reg_reg[1]_39 ;
  wire \SYNC[3].sync_reg_reg[1]_4 ;
  wire \SYNC[3].sync_reg_reg[1]_40 ;
  wire \SYNC[3].sync_reg_reg[1]_41 ;
  wire \SYNC[3].sync_reg_reg[1]_42 ;
  wire \SYNC[3].sync_reg_reg[1]_43 ;
  wire \SYNC[3].sync_reg_reg[1]_44 ;
  wire \SYNC[3].sync_reg_reg[1]_45 ;
  wire \SYNC[3].sync_reg_reg[1]_5 ;
  wire \SYNC[3].sync_reg_reg[1]_6 ;
  wire \SYNC[3].sync_reg_reg[1]_7 ;
  wire \SYNC[3].sync_reg_reg[1]_8 ;
  wire \SYNC[3].sync_reg_reg[1]_9 ;
  wire \SYNC[4].sync_reg_reg[1] ;
  wire \SYNC[4].sync_reg_reg[1]_0 ;
  wire \SYNC[5].sync_reg_reg[1] ;
  wire \SYNC[5].sync_reg_reg[1]_0 ;
  wire \SYNC[5].sync_reg_reg[1]_1 ;
  wire \SYNC[5].sync_reg_reg[1]_10 ;
  wire \SYNC[5].sync_reg_reg[1]_11 ;
  wire \SYNC[5].sync_reg_reg[1]_12 ;
  wire \SYNC[5].sync_reg_reg[1]_13 ;
  wire \SYNC[5].sync_reg_reg[1]_14 ;
  wire \SYNC[5].sync_reg_reg[1]_15 ;
  wire \SYNC[5].sync_reg_reg[1]_16 ;
  wire \SYNC[5].sync_reg_reg[1]_17 ;
  wire \SYNC[5].sync_reg_reg[1]_2 ;
  wire \SYNC[5].sync_reg_reg[1]_3 ;
  wire \SYNC[5].sync_reg_reg[1]_4 ;
  wire \SYNC[5].sync_reg_reg[1]_5 ;
  wire \SYNC[5].sync_reg_reg[1]_6 ;
  wire \SYNC[5].sync_reg_reg[1]_7 ;
  wire \SYNC[5].sync_reg_reg[1]_8 ;
  wire \SYNC[5].sync_reg_reg[1]_9 ;
  wire a_b_cmd_sel_start;
  wire a_b_cmd_sel_start0;
  wire a_b_cmd_sel_start_reg;
  wire \addr_dec_to_mb_data[0]_i_3 ;
  wire \addr_dec_to_mb_data[31]_i_3 ;
  wire \addr_dec_to_mb_data[4]_i_11 ;
  wire \addr_dec_to_mb_data[6]_i_7 ;
  wire \addr_dec_to_mb_data[6]_i_7_0 ;
  wire \addr_dec_to_mb_data[7]_i_7 ;
  wire \addr_dec_to_mb_data_reg[12] ;
  wire \addr_dec_to_mb_data_reg[14] ;
  wire \addr_dec_to_mb_data_reg[15] ;
  wire \addr_dec_to_mb_data_reg[19] ;
  wire \addr_dec_to_mb_data_reg[20] ;
  wire \addr_dec_to_mb_data_reg[21] ;
  wire \addr_dec_to_mb_data_reg[22] ;
  wire \addr_dec_to_mb_data_reg[23] ;
  wire \addr_dec_to_mb_data_reg[24] ;
  wire \addr_dec_to_mb_data_reg[25] ;
  wire \addr_dec_to_mb_data_reg[26] ;
  wire \addr_dec_to_mb_data_reg[27] ;
  wire \addr_dec_to_mb_data_reg[28] ;
  wire \addr_dec_to_mb_data_reg[29] ;
  wire \addr_dec_to_mb_data_reg[29]_0 ;
  wire \addr_dec_to_mb_data_reg[29]_1 ;
  wire \addr_dec_to_mb_data_reg[29]_2 ;
  wire \addr_dec_to_mb_data_reg[29]_3 ;
  wire \addr_dec_to_mb_data_reg[29]_4 ;
  wire \addr_dec_to_mb_data_reg[30] ;
  wire \addr_dec_to_mb_data_reg[30]_0 ;
  wire [20:0]\addr_dec_to_mb_data_reg[31] ;
  wire [0:0]\bisc_bit_reg[0] ;
  wire [8:0]bisc_byte;
  wire calDone;
  wire calDone_gated_reg_0;
  wire [0:0]calDone_gated_reg_1;
  wire calDone_i;
  wire calDone_reg;
  wire calRdCAS;
  wire \calSt_reg[0] ;
  wire calWrCAS;
  wire [7:0]cal_ACT_n;
  wire [0:0]\cal_ACT_n_A_reg[7] ;
  wire \cal_ADR_A_reg[0] ;
  wire \cal_ADR_A_reg[0]_0 ;
  wire \cal_ADR_A_reg[1] ;
  wire \cal_ADR_A_reg[20] ;
  wire \cal_ADR_A_reg[21] ;
  wire \cal_ADR_A_reg[22] ;
  wire \cal_ADR_A_reg[26] ;
  wire \cal_ADR_A_reg[27] ;
  wire \cal_ADR_A_reg[29] ;
  wire \cal_ADR_A_reg[2] ;
  wire [11:0]\cal_ADR_A_reg[30] ;
  wire [0:0]\cal_ADR_A_reg[31] ;
  wire \cal_ADR_A_reg[3] ;
  wire \cal_ADR_A_reg[4] ;
  wire \cal_ADR_A_reg[4]_0 ;
  wire \cal_ADR_B_reg[10] ;
  wire \cal_ADR_B_reg[11] ;
  wire \cal_ADR_B_reg[12] ;
  wire \cal_ADR_B_reg[13] ;
  wire \cal_ADR_B_reg[15] ;
  wire \cal_ADR_B_reg[17] ;
  wire \cal_ADR_B_reg[18] ;
  wire \cal_ADR_B_reg[19] ;
  wire \cal_ADR_B_reg[24] ;
  wire \cal_ADR_B_reg[25] ;
  wire [12:0]\cal_ADR_B_reg[30] ;
  wire \cal_ADR_B_reg[31] ;
  wire [0:0]\cal_ADR_B_reg[31]_0 ;
  wire [0:0]cal_BA;
  wire [0:0]\cal_CAS_A_reg[0] ;
  wire \cal_CS_A_reg[0] ;
  wire \cal_CS_A_reg[4] ;
  wire [4:0]\cal_CS_A_reg[5] ;
  wire \cal_CS_A_reg[6] ;
  wire \cal_CS_A_reg[7] ;
  wire [0:0]\cal_CS_A_reg[7]_0 ;
  wire [4:0]\cal_CS_B_reg[5] ;
  wire [0:0]\cal_CS_B_reg[7] ;
  wire [3:0]cal_CS_n;
  wire [0:0]\cal_DMOut_n_A_reg[31] ;
  wire \cal_DQOut_A_reg[31] ;
  wire \cal_DQOut_A_reg[63] ;
  wire \cal_DQOut_post_reg[31] ;
  wire \cal_DQOut_post_reg[63] ;
  wire \cal_DQOut_pre_reg[31] ;
  wire \cal_DQOut_pre_reg[63] ;
  wire \cal_DQPat_A_reg[31] ;
  wire \cal_DQPat_A_reg[63] ;
  wire \cal_DQPat_B_reg[31] ;
  wire \cal_DQPat_B_reg[63] ;
  wire [0:0]\cal_RAS_B_reg[0] ;
  wire [7:0]cal_RESET_n_int;
  wire [7:0]\cal_RESET_n_reg[7]_0 ;
  wire \cal_RST_CKE_ODT_PAR_reg[16] ;
  wire [10:0]\cal_RST_CKE_ODT_PAR_reg[30] ;
  wire [0:0]\cal_RST_CKE_ODT_PAR_reg[31] ;
  wire \cal_RST_CKE_ODT_PAR_reg[9] ;
  wire [103:103]cal_clb2phy_fifo_rden;
  wire cal_clear_fifo_rden;
  wire [0:0]\cal_cmp_en_reg[7] ;
  wire [0:0]\cal_cs_pos_reg[1] ;
  wire [63:0]cal_mcal_DMIn_n;
  wire [63:0]\cal_mcal_DMIn_n_reg[63]_0 ;
  wire [0:0]cal_oe_dis_low;
  wire \cal_oe_dis_low_reg[7] ;
  wire [0:0]cal_oe_dis_upp;
  wire \cal_oe_dis_upp_reg[7] ;
  wire [0:0]\cal_seq_a_a_dly_reg[7] ;
  wire [0:0]\cal_seq_a_b_dly_reg[7] ;
  wire [0:0]\cal_seq_b_a_dly_reg[7] ;
  wire cal_seq_cnt_gt_0_reg;
  wire \cal_seq_cnt_reg[13] ;
  wire [31:0]\cal_seq_cnt_reg[31] ;
  wire [7:0]\cal_seq_rd_cnt_reg[7] ;
  wire [0:0]\cal_seq_reg[2] ;
  wire [31:0]cal_timer_reg;
  wire [7:0]\cal_timer_reg[15] ;
  wire [7:0]\cal_timer_reg[23] ;
  wire [7:0]\cal_timer_reg[31] ;
  wire cal_timer_reg_0_sn_1;
  wire cal_timer_reg_21_sn_1;
  wire cal_timer_reg_24_sn_1;
  wire cal_timer_reg_25_sn_1;
  wire cal_timer_reg_28_sn_1;
  wire cal_timer_reg_29_sn_1;
  wire [63:0]ch0_mcal_DMOut_n;
  wire [511:0]ch0_mcal_DQOut;
  wire [31:0]ch0_mcal_clb2phy_rden_low;
  wire [31:0]ch0_mcal_clb2phy_rden_upp;
  (* RTL_KEEP = "true" *) wire [103:0]\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 ;
  wire \clb2phy_wrcs0_low_reg[31] ;
  wire clear_gt_data_ready_flag;
  wire clear_gt_data_ready_flag_reg;
  wire [19:0]cmdBuf;
  wire [0:0]\cmp_byte_reg[2] ;
  wire cnt_clr;
  wire cnt_clr_access;
  wire cnt_clr_reg;
  wire [7:0]\cplx_CAS_reg[6] ;
  wire [0:0]\cplx_config_reg[0] ;
  wire [0:0]\cplx_config_reg[16] ;
  wire \cplx_config_reg[16]_0 ;
  wire \cplx_config_reg[1] ;
  wire \cplx_error_accum_reg[14] ;
  wire \cplx_error_accum_reg[15] ;
  wire \cplx_error_accum_reg[19] ;
  wire \cplx_error_accum_reg[44] ;
  wire [53:0]\cplx_error_accum_reg[63] ;
  wire [0:0]cplx_status;
  wire \dReg_reg[10] ;
  wire [1:0]\delay_cntr_reg[2] ;
  wire [10:0]\dout_o_reg[11] ;
  wire [10:0]\dout_o_reg[11]_0 ;
  wire \dout_o_reg[5] ;
  wire [8:0]douta;
  wire en_vtc;
  wire ena;
  wire [0:0]\genblk10[3].cal_DMOut_n_A_r_reg[24] ;
  wire [0:0]\genblk10[6].cal_DMOut_n_A_r_reg[48] ;
  wire \genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8] ;
  wire \genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9] ;
  wire gt_data_ready_flag;
  wire gt_data_ready_flag_nxt;
  wire gt_data_ready_flag_reg;
  wire [85:0]in0;
  wire initDone;
  wire io_addr_strobe;
  wire io_addr_strobe0;
  wire io_addr_strobe_lvl_r1;
  wire [0:0]io_addr_strobe_lvl_r1_reg_0;
  wire io_addr_strobe_lvl_r2;
  wire [20:0]io_address;
  wire [31:0]\io_read_data_reg[31] ;
  wire [0:0]io_ready_lvl_reg;
  wire io_ready_reg;
  wire io_ready_reg_0;
  wire io_ready_reg_1;
  wire [31:0]io_write_data;
  wire lrdimm_cal_mode_reg;
  wire lrdimm_cal_mode_reg_0;
  wire lrdimm_cal_mode_reg_1;
  wire lrdimm_cmp_clr;
  wire lrdimm_cmp_en;
  wire lrdimm_cmp_en_reg;
  wire match4_10_return;
  wire match4_110_return;
  wire match4_111_return;
  wire match4_112_return;
  wire match4_113_return;
  wire match4_114_return;
  wire match4_115_return;
  wire match4_116_return;
  wire match4_117_return;
  wire match4_118_return;
  wire match4_119_return;
  wire match4_11_return;
  wire match4_120_return;
  wire match4_121_return;
  wire match4_122_return;
  wire match4_123_return;
  wire match4_124_return;
  wire match4_125_return;
  wire match4_126_return;
  wire match4_127_return;
  wire match4_128_return;
  wire match4_129_return;
  wire match4_12_return;
  wire match4_130_return;
  wire match4_131_return;
  wire match4_132_return;
  wire match4_133_return;
  wire match4_134_return;
  wire match4_135_return;
  wire match4_136_return;
  wire match4_137_return;
  wire match4_138_return;
  wire match4_139_return;
  wire match4_13_return;
  wire match4_140_return;
  wire match4_141_return;
  wire match4_142_return;
  wire match4_143_return;
  wire match4_144_return;
  wire match4_145_return;
  wire match4_146_return;
  wire match4_147_return;
  wire match4_148_return;
  wire match4_149_return;
  wire match4_14_return;
  wire match4_150_return;
  wire match4_151_return;
  wire match4_152_return;
  wire match4_153_return;
  wire match4_154_return;
  wire match4_155_return;
  wire match4_156_return;
  wire match4_157_return;
  wire match4_158_return;
  wire match4_159_return;
  wire match4_15_return;
  wire match4_160_return;
  wire match4_161_return;
  wire match4_162_return;
  wire match4_163_return;
  wire match4_164_return;
  wire match4_165_return;
  wire match4_166_return;
  wire match4_167_return;
  wire match4_168_return;
  wire match4_169_return;
  wire match4_16_return;
  wire match4_170_return;
  wire match4_171_return;
  wire match4_172_return;
  wire match4_173_return;
  wire match4_174_return;
  wire match4_175_return;
  wire match4_176_return;
  wire match4_177_return;
  wire match4_178_return;
  wire match4_179_return;
  wire match4_17_return;
  wire match4_180_return;
  wire match4_181_return;
  wire match4_182_return;
  wire match4_183_return;
  wire match4_184_return;
  wire match4_185_return;
  wire match4_186_return;
  wire match4_187_return;
  wire match4_188_return;
  wire match4_18_return;
  wire match4_19_return;
  wire match4_1_return;
  wire match6_10_return;
  wire match6_110_return;
  wire match6_111_return;
  wire match6_112_return;
  wire match6_113_return;
  wire match6_114_return;
  wire match6_115_return;
  wire match6_116_return;
  wire match6_117_return;
  wire match6_118_return;
  wire match6_119_return;
  wire match6_11_return;
  wire match6_120_return;
  wire match6_121_return;
  wire match6_122_return;
  wire match6_123_return;
  wire match6_124_return;
  wire match6_125_return;
  wire match6_126_return;
  wire match6_127_return;
  wire match6_128_return;
  wire match6_129_return;
  wire match6_12_return;
  wire match6_130_return;
  wire match6_131_return;
  wire match6_132_return;
  wire match6_133_return;
  wire match6_134_return;
  wire match6_135_return;
  wire match6_136_return;
  wire match6_137_return;
  wire match6_138_return;
  wire match6_139_return;
  wire match6_13_return;
  wire match6_140_return;
  wire match6_141_return;
  wire match6_142_return;
  wire match6_143_return;
  wire match6_144_return;
  wire match6_145_return;
  wire match6_146_return;
  wire match6_147_return;
  wire match6_148_return;
  wire match6_149_return;
  wire match6_14_return;
  wire match6_150_return;
  wire match6_151_return;
  wire match6_152_return;
  wire match6_153_return;
  wire match6_154_return;
  wire match6_155_return;
  wire match6_156_return;
  wire match6_157_return;
  wire match6_158_return;
  wire match6_159_return;
  wire match6_15_return;
  wire match6_160_return;
  wire match6_161_return;
  wire match6_162_return;
  wire match6_163_return;
  wire match6_164_return;
  wire match6_165_return;
  wire match6_166_return;
  wire match6_167_return;
  wire match6_168_return;
  wire match6_169_return;
  wire match6_16_return;
  wire match6_170_return;
  wire match6_171_return;
  wire match6_172_return;
  wire match6_173_return;
  wire match6_174_return;
  wire match6_175_return;
  wire match6_176_return;
  wire match6_177_return;
  wire match6_178_return;
  wire match6_179_return;
  wire match6_17_return;
  wire match6_180_return;
  wire match6_181_return;
  wire match6_182_return;
  wire match6_183_return;
  wire match6_184_return;
  wire match6_185_return;
  wire match6_186_return;
  wire match6_187_return;
  wire match6_188_return;
  wire match6_18_return;
  wire match6_19_return;
  wire match6_1_return;
  wire [0:0]\max_rd_lat_reg[5] ;
  wire mcCasSlot2;
  wire mcRdCAS;
  wire mcWrCAS;
  wire [35:0]mc_ADR;
  wire [16:10]mc_ADR7;
  wire [4:0]\mc_ADR7_reg[16]_0 ;
  wire [6:0]mc_BA;
  wire [2:0]mc_BG;
  wire [1:0]mc_CKE;
  wire mc_CKE7;
  wire [0:0]mc_CS_n;
  wire mc_CS_n7;
  wire [1:0]mc_ODT;
  wire mc_ODT7;
  wire [103:103]mc_clb2phy_fifo_rden_nxt;
  wire [1:1]mcalCasSlot;
  wire [1:0]mcalRank;
  wire mcalRdCAS;
  wire [7:0]mcal_ACT_n;
  wire [88:0]mcal_ADR;
  wire [7:0]\mcal_ADR_dly_reg[0][126]_0 ;
  wire [9:0]\mcal_BA_dly_reg[0][15]_0 ;
  wire [0:0]\mcal_BA_dly_reg[0][4]_0 ;
  wire [0:0]\mcal_BG_dly_reg[0][4]_0 ;
  wire [4:0]\mcal_BG_dly_reg[0][7]_0 ;
  wire [2:0]\mcal_CKE_dly_reg[0][7]_0 ;
  wire [3:0]\mcal_CS_n_dly_reg[0][6]_0 ;
  wire [7:0]\mcal_CS_n_dly_reg[0][7]_0 ;
  wire [6:0]\mcal_DMIn_bit_r1_reg[7] ;
  wire [511:0]mcal_DQIn;
  wire \mcal_DQIn_byte_r1_reg[31] ;
  wire [9:0]\mcal_DQIn_byte_r1_reg[48] ;
  wire [4:0]\mcal_ODT_dly_reg[0][7]_0 ;
  wire [1:0]\mcal_ODT_dly_reg[0][7]_1 ;
  wire \mcal_PAR_dly[0][0]_i_4_n_0 ;
  wire \mcal_PAR_dly_reg[0][1]_0 ;
  wire \mcal_PAR_dly_reg[0][3]_0 ;
  wire \mcal_PAR_dly_reg[0][5]_0 ;
  wire [7:0]\mcal_PAR_dly_reg[0][7]_0 ;
  wire \mcal_PAR_dly_reg[0][7]_1 ;
  (* RTL_KEEP = "true" *) wire [103:0]\mcal_clb2phy_fifo_rden_reg[103]_0 ;
  wire [55:0]mcal_rd_vref_value;
  wire mem_reg_bram_0;
  wire [4:0]\not_strict_mode.app_rd_data_end_reg ;
  wire \not_strict_mode.bypass_cpy2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ;
  wire [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ;
  wire \not_strict_mode.status_ram_0.RAM32M0 ;
  wire [4:0]\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] ;
  wire [4:0]\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] ;
  wire [4:0]\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] ;
  wire [4:0]\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] ;
  wire [0:0]oe_0_mux_cal;
  wire [3:0]\oe_low_reg[3] ;
  wire [3:0]\oe_upp_reg[3] ;
  wire [36:0]out;
  wire [0:0]p_0_in;
  wire [4:3]p_0_in__0;
  wire [0:0]p_1_in;
  wire [8:0]p_1_in__0;
  wire p_52_in;
  wire per_rd_done;
  wire phy_rden_and;
  wire [7:3]phy_rden_and_stg_gt;
  wire \phy_rden_and_stg_reg[2]_srl3_n_0 ;
  wire phy_rden_or;
  wire [7:3]phy_rden_or_stg_gt;
  wire \phy_rden_or_stg_reg[2]_srl3_n_0 ;
  wire pllGate;
  wire pointer_we;
  wire [0:0]\rams[1].RAM32M0 ;
  wire rdCAS_reg;
  wire [4:0]\rdDataAddr_reg[4] ;
  wire \rdDataAddr_reg[4]_0 ;
  wire \rdDataAddr_reg[4]_1 ;
  wire \rdDataAddr_reg[4]_2 ;
  wire [1:0]\rdDataAddr_reg[4]_rep__0 ;
  wire [1:0]\rdDataAddr_reg[4]_rep__1 ;
  wire rdDataEn_pi;
  wire [5:0]\rdData_reg[101]_0 ;
  wire [5:0]\rdData_reg[107]_0 ;
  wire [5:0]\rdData_reg[113]_0 ;
  wire [5:0]\rdData_reg[119]_0 ;
  wire [5:0]\rdData_reg[11]_0 ;
  wire [5:0]\rdData_reg[125]_0 ;
  wire [5:0]\rdData_reg[131]_0 ;
  wire [5:0]\rdData_reg[137]_0 ;
  wire [5:0]\rdData_reg[143]_0 ;
  wire [5:0]\rdData_reg[149]_0 ;
  wire [5:0]\rdData_reg[155]_0 ;
  wire [5:0]\rdData_reg[161]_0 ;
  wire [5:0]\rdData_reg[167]_0 ;
  wire [5:0]\rdData_reg[173]_0 ;
  wire [5:0]\rdData_reg[179]_0 ;
  wire [5:0]\rdData_reg[17]_0 ;
  wire [5:0]\rdData_reg[185]_0 ;
  wire [5:0]\rdData_reg[191]_0 ;
  wire [5:0]\rdData_reg[197]_0 ;
  wire [5:0]\rdData_reg[203]_0 ;
  wire [5:0]\rdData_reg[209]_0 ;
  wire [5:0]\rdData_reg[215]_0 ;
  wire [5:0]\rdData_reg[221]_0 ;
  wire [5:0]\rdData_reg[227]_0 ;
  wire [5:0]\rdData_reg[233]_0 ;
  wire [5:0]\rdData_reg[239]_0 ;
  wire [5:0]\rdData_reg[23]_0 ;
  wire [5:0]\rdData_reg[245]_0 ;
  wire [5:0]\rdData_reg[251]_0 ;
  wire [5:0]\rdData_reg[257]_0 ;
  wire [5:0]\rdData_reg[263]_0 ;
  wire [5:0]\rdData_reg[269]_0 ;
  wire [5:0]\rdData_reg[275]_0 ;
  wire [5:0]\rdData_reg[281]_0 ;
  wire [5:0]\rdData_reg[287]_0 ;
  wire [5:0]\rdData_reg[293]_0 ;
  wire [5:0]\rdData_reg[299]_0 ;
  wire [5:0]\rdData_reg[29]_0 ;
  wire [5:0]\rdData_reg[305]_0 ;
  wire [5:0]\rdData_reg[311]_0 ;
  wire [5:0]\rdData_reg[317]_0 ;
  wire [5:0]\rdData_reg[323]_0 ;
  wire [5:0]\rdData_reg[329]_0 ;
  wire [5:0]\rdData_reg[335]_0 ;
  wire [5:0]\rdData_reg[341]_0 ;
  wire [5:0]\rdData_reg[347]_0 ;
  wire [5:0]\rdData_reg[353]_0 ;
  wire [5:0]\rdData_reg[359]_0 ;
  wire [5:0]\rdData_reg[35]_0 ;
  wire [5:0]\rdData_reg[365]_0 ;
  wire [5:0]\rdData_reg[371]_0 ;
  wire [5:0]\rdData_reg[377]_0 ;
  wire [5:0]\rdData_reg[383]_0 ;
  wire [5:0]\rdData_reg[389]_0 ;
  wire [5:0]\rdData_reg[395]_0 ;
  wire [5:0]\rdData_reg[401]_0 ;
  wire [5:0]\rdData_reg[407]_0 ;
  wire [5:0]\rdData_reg[413]_0 ;
  wire [5:0]\rdData_reg[419]_0 ;
  wire [5:0]\rdData_reg[41]_0 ;
  wire [5:0]\rdData_reg[425]_0 ;
  wire [5:0]\rdData_reg[431]_0 ;
  wire [5:0]\rdData_reg[437]_0 ;
  wire [5:0]\rdData_reg[443]_0 ;
  wire [5:0]\rdData_reg[449]_0 ;
  wire [5:0]\rdData_reg[455]_0 ;
  wire [5:0]\rdData_reg[461]_0 ;
  wire [5:0]\rdData_reg[467]_0 ;
  wire [5:0]\rdData_reg[473]_0 ;
  wire [5:0]\rdData_reg[479]_0 ;
  wire [5:0]\rdData_reg[47]_0 ;
  wire [5:0]\rdData_reg[485]_0 ;
  wire [5:0]\rdData_reg[491]_0 ;
  wire [5:0]\rdData_reg[497]_0 ;
  wire [5:0]\rdData_reg[503]_0 ;
  wire [5:0]\rdData_reg[509]_0 ;
  wire [1:0]\rdData_reg[511]_0 ;
  wire [5:0]\rdData_reg[53]_0 ;
  wire [5:0]\rdData_reg[59]_0 ;
  wire [5:0]\rdData_reg[5]_0 ;
  wire [5:0]\rdData_reg[65]_0 ;
  wire [5:0]\rdData_reg[71]_0 ;
  wire [5:0]\rdData_reg[77]_0 ;
  wire [5:0]\rdData_reg[83]_0 ;
  wire [5:0]\rdData_reg[89]_0 ;
  wire [5:0]\rdData_reg[95]_0 ;
  wire [3:2]\rdEn[0].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[0].u_ddr_mc_rd_en_low/rs2mask ;
  wire [12:2]\rdEn[0].u_ddr_mc_rd_en_low/rs2mask0 ;
  wire [3:2]\rdEn[0].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[0].u_ddr_mc_rd_en_upp/rs2mask ;
  wire [12:2]\rdEn[0].u_ddr_mc_rd_en_upp/rs2mask0 ;
  wire [3:2]\rdEn[1].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[1].u_ddr_mc_rd_en_low/rs2mask ;
  wire [12:2]\rdEn[1].u_ddr_mc_rd_en_low/rs2mask0 ;
  wire [3:2]\rdEn[1].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[1].u_ddr_mc_rd_en_upp/rs2mask ;
  wire [12:2]\rdEn[1].u_ddr_mc_rd_en_upp/rs2mask0__0 ;
  wire [18:17]\rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[1]_71 ;
  wire [18:17]\rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[3]_73 ;
  wire [18:17]\rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[5]_75 ;
  wire [18:17]\rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[7]_77 ;
  wire [3:2]\rdEn[2].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[2].u_ddr_mc_rd_en_low/rs2mask ;
  wire [12:2]\rdEn[2].u_ddr_mc_rd_en_low/rs2mask0 ;
  wire [3:2]\rdEn[2].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[2].u_ddr_mc_rd_en_upp/rs2mask ;
  wire [12:2]\rdEn[2].u_ddr_mc_rd_en_upp/rs2mask0 ;
  wire [3:2]\rdEn[3].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[3].u_ddr_mc_rd_en_low/rs2mask ;
  wire [12:2]\rdEn[3].u_ddr_mc_rd_en_low/rs2mask0 ;
  wire [3:2]\rdEn[3].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[3].u_ddr_mc_rd_en_upp/rs2mask ;
  wire [12:2]\rdEn[3].u_ddr_mc_rd_en_upp/rs2mask0 ;
  wire [3:2]\rdEn[4].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[4].u_ddr_mc_rd_en_low/rs2mask ;
  wire [12:2]\rdEn[4].u_ddr_mc_rd_en_low/rs2mask0 ;
  wire [3:2]\rdEn[4].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[4].u_ddr_mc_rd_en_upp/rs2mask ;
  wire [12:2]\rdEn[4].u_ddr_mc_rd_en_upp/rs2mask0 ;
  wire [3:2]\rdEn[5].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[5].u_ddr_mc_rd_en_low/rs2mask ;
  wire [12:2]\rdEn[5].u_ddr_mc_rd_en_low/rs2mask0 ;
  wire [3:2]\rdEn[5].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[5].u_ddr_mc_rd_en_upp/rs2mask ;
  wire [12:2]\rdEn[5].u_ddr_mc_rd_en_upp/rs2mask0 ;
  wire [3:2]\rdEn[6].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[6].u_ddr_mc_rd_en_low/rs2mask ;
  wire [12:2]\rdEn[6].u_ddr_mc_rd_en_low/rs2mask0 ;
  wire [3:2]\rdEn[6].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[6].u_ddr_mc_rd_en_upp/rs2mask ;
  wire [12:2]\rdEn[6].u_ddr_mc_rd_en_upp/rs2mask0 ;
  wire [3:2]\rdEn[7].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[7].u_ddr_mc_rd_en_low/rs2mask ;
  wire [12:2]\rdEn[7].u_ddr_mc_rd_en_low/rs2mask0 ;
  wire [3:2]\rdEn[7].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ;
  wire [9:2]\rdEn[7].u_ddr_mc_rd_en_upp/rs2mask ;
  wire [12:2]\rdEn[7].u_ddr_mc_rd_en_upp/rs2mask0__0 ;
  wire [18:17]\rdEn[7].u_ddr_mc_rd_en_upp/rsMask_reg[1]_79 ;
  wire [18:17]\rdEn[7].u_ddr_mc_rd_en_upp/rsMask_reg[3]_81 ;
  wire [18:17]\rdEn[7].u_ddr_mc_rd_en_upp/rsMask_reg[5]_83 ;
  wire [18:17]\rdEn[7].u_ddr_mc_rd_en_upp/rsMask_reg[7]_85 ;
  wire rd_data_en_phy2mc;
  wire [7:0]rd_vref_value0_out;
  wire \rd_vref_value_reg[42] ;
  wire \rd_vref_value_reg[43] ;
  wire \rd_vref_value_reg[44] ;
  wire \rd_vref_value_reg[45] ;
  wire \rd_vref_value_reg[46] ;
  wire \rd_vref_value_reg[48] ;
  wire [6:0]\read_lat_fifo_in_reg[6] ;
  (* RTL_KEEP = "true" *) wire rst_r1;
  wire rst_r1_reg_0;
  wire rst_r1_reg_1;
  wire sample_gts;
  wire sample_gts0;
  wire sample_gts_i_2_n_0;
  wire [16:0]sl_oport_o;
  wire stop_gate_tracking_ack_reg;
  wire stop_gate_tracking_ack_reg_0;
  wire [0:0]\traffic_instr_nxt_instr_r1_reg[5] ;
  wire [0:0]\u_ddr_cal_addr_decode/dqin_valid_shift_nxt ;
  wire u_ddr_cal_n_100;
  wire u_ddr_cal_n_1000;
  wire u_ddr_cal_n_1001;
  wire u_ddr_cal_n_1002;
  wire u_ddr_cal_n_1003;
  wire u_ddr_cal_n_1004;
  wire u_ddr_cal_n_1005;
  wire u_ddr_cal_n_1006;
  wire u_ddr_cal_n_1007;
  wire u_ddr_cal_n_1008;
  wire u_ddr_cal_n_1009;
  wire u_ddr_cal_n_101;
  wire u_ddr_cal_n_1010;
  wire u_ddr_cal_n_1011;
  wire u_ddr_cal_n_1012;
  wire u_ddr_cal_n_1013;
  wire u_ddr_cal_n_1014;
  wire u_ddr_cal_n_1015;
  wire u_ddr_cal_n_1016;
  wire u_ddr_cal_n_1017;
  wire u_ddr_cal_n_1018;
  wire u_ddr_cal_n_1019;
  wire u_ddr_cal_n_102;
  wire u_ddr_cal_n_1020;
  wire u_ddr_cal_n_1021;
  wire u_ddr_cal_n_1022;
  wire u_ddr_cal_n_1023;
  wire u_ddr_cal_n_1024;
  wire u_ddr_cal_n_1025;
  wire u_ddr_cal_n_1026;
  wire u_ddr_cal_n_1027;
  wire u_ddr_cal_n_1028;
  wire u_ddr_cal_n_1029;
  wire u_ddr_cal_n_103;
  wire u_ddr_cal_n_1030;
  wire u_ddr_cal_n_1031;
  wire u_ddr_cal_n_1032;
  wire u_ddr_cal_n_1033;
  wire u_ddr_cal_n_1034;
  wire u_ddr_cal_n_1035;
  wire u_ddr_cal_n_1036;
  wire u_ddr_cal_n_1037;
  wire u_ddr_cal_n_1038;
  wire u_ddr_cal_n_1039;
  wire u_ddr_cal_n_104;
  wire u_ddr_cal_n_1040;
  wire u_ddr_cal_n_1041;
  wire u_ddr_cal_n_1042;
  wire u_ddr_cal_n_1043;
  wire u_ddr_cal_n_1044;
  wire u_ddr_cal_n_1045;
  wire u_ddr_cal_n_1046;
  wire u_ddr_cal_n_1047;
  wire u_ddr_cal_n_1048;
  wire u_ddr_cal_n_1049;
  wire u_ddr_cal_n_105;
  wire u_ddr_cal_n_1050;
  wire u_ddr_cal_n_1051;
  wire u_ddr_cal_n_1052;
  wire u_ddr_cal_n_1053;
  wire u_ddr_cal_n_1054;
  wire u_ddr_cal_n_1055;
  wire u_ddr_cal_n_1056;
  wire u_ddr_cal_n_1057;
  wire u_ddr_cal_n_1058;
  wire u_ddr_cal_n_1059;
  wire u_ddr_cal_n_106;
  wire u_ddr_cal_n_1060;
  wire u_ddr_cal_n_1061;
  wire u_ddr_cal_n_1062;
  wire u_ddr_cal_n_1063;
  wire u_ddr_cal_n_1064;
  wire u_ddr_cal_n_1065;
  wire u_ddr_cal_n_1066;
  wire u_ddr_cal_n_1067;
  wire u_ddr_cal_n_1068;
  wire u_ddr_cal_n_1069;
  wire u_ddr_cal_n_107;
  wire u_ddr_cal_n_1070;
  wire u_ddr_cal_n_1071;
  wire u_ddr_cal_n_1072;
  wire u_ddr_cal_n_1073;
  wire u_ddr_cal_n_1074;
  wire u_ddr_cal_n_1075;
  wire u_ddr_cal_n_1076;
  wire u_ddr_cal_n_1077;
  wire u_ddr_cal_n_1078;
  wire u_ddr_cal_n_1079;
  wire u_ddr_cal_n_108;
  wire u_ddr_cal_n_1080;
  wire u_ddr_cal_n_1081;
  wire u_ddr_cal_n_1082;
  wire u_ddr_cal_n_109;
  wire u_ddr_cal_n_110;
  wire u_ddr_cal_n_111;
  wire u_ddr_cal_n_112;
  wire u_ddr_cal_n_113;
  wire u_ddr_cal_n_114;
  wire u_ddr_cal_n_117;
  wire u_ddr_cal_n_118;
  wire u_ddr_cal_n_119;
  wire u_ddr_cal_n_120;
  wire u_ddr_cal_n_126;
  wire u_ddr_cal_n_127;
  wire u_ddr_cal_n_128;
  wire u_ddr_cal_n_129;
  wire u_ddr_cal_n_130;
  wire u_ddr_cal_n_131;
  wire u_ddr_cal_n_132;
  wire u_ddr_cal_n_133;
  wire u_ddr_cal_n_134;
  wire u_ddr_cal_n_135;
  wire u_ddr_cal_n_136;
  wire u_ddr_cal_n_137;
  wire u_ddr_cal_n_1374;
  wire u_ddr_cal_n_1375;
  wire u_ddr_cal_n_1376;
  wire u_ddr_cal_n_1377;
  wire u_ddr_cal_n_1378;
  wire u_ddr_cal_n_1379;
  wire u_ddr_cal_n_138;
  wire u_ddr_cal_n_1380;
  wire u_ddr_cal_n_1383;
  wire u_ddr_cal_n_1384;
  wire u_ddr_cal_n_1385;
  wire u_ddr_cal_n_1386;
  wire u_ddr_cal_n_1387;
  wire u_ddr_cal_n_1388;
  wire u_ddr_cal_n_1389;
  wire u_ddr_cal_n_139;
  wire u_ddr_cal_n_1390;
  wire u_ddr_cal_n_1391;
  wire u_ddr_cal_n_1392;
  wire u_ddr_cal_n_1393;
  wire u_ddr_cal_n_1394;
  wire u_ddr_cal_n_1395;
  wire u_ddr_cal_n_1396;
  wire u_ddr_cal_n_1397;
  wire u_ddr_cal_n_1398;
  wire u_ddr_cal_n_1399;
  wire u_ddr_cal_n_140;
  wire u_ddr_cal_n_1400;
  wire u_ddr_cal_n_1401;
  wire u_ddr_cal_n_1402;
  wire u_ddr_cal_n_1403;
  wire u_ddr_cal_n_1404;
  wire u_ddr_cal_n_1405;
  wire u_ddr_cal_n_1406;
  wire u_ddr_cal_n_1407;
  wire u_ddr_cal_n_1408;
  wire u_ddr_cal_n_1409;
  wire u_ddr_cal_n_141;
  wire u_ddr_cal_n_1410;
  wire u_ddr_cal_n_1411;
  wire u_ddr_cal_n_1412;
  wire u_ddr_cal_n_1413;
  wire u_ddr_cal_n_1414;
  wire u_ddr_cal_n_1415;
  wire u_ddr_cal_n_1416;
  wire u_ddr_cal_n_1417;
  wire u_ddr_cal_n_1418;
  wire u_ddr_cal_n_1419;
  wire u_ddr_cal_n_142;
  wire u_ddr_cal_n_1420;
  wire u_ddr_cal_n_1421;
  wire u_ddr_cal_n_1422;
  wire u_ddr_cal_n_1423;
  wire u_ddr_cal_n_1424;
  wire u_ddr_cal_n_1425;
  wire u_ddr_cal_n_1426;
  wire u_ddr_cal_n_1427;
  wire u_ddr_cal_n_1428;
  wire u_ddr_cal_n_1429;
  wire u_ddr_cal_n_143;
  wire u_ddr_cal_n_1430;
  wire u_ddr_cal_n_1431;
  wire u_ddr_cal_n_1432;
  wire u_ddr_cal_n_1433;
  wire u_ddr_cal_n_1434;
  wire u_ddr_cal_n_1437;
  wire u_ddr_cal_n_1438;
  wire u_ddr_cal_n_1439;
  wire u_ddr_cal_n_144;
  wire u_ddr_cal_n_1440;
  wire u_ddr_cal_n_1441;
  wire u_ddr_cal_n_1442;
  wire u_ddr_cal_n_1443;
  wire u_ddr_cal_n_1444;
  wire u_ddr_cal_n_1445;
  wire u_ddr_cal_n_1446;
  wire u_ddr_cal_n_1447;
  wire u_ddr_cal_n_1448;
  wire u_ddr_cal_n_1449;
  wire u_ddr_cal_n_145;
  wire u_ddr_cal_n_1450;
  wire u_ddr_cal_n_1451;
  wire u_ddr_cal_n_1452;
  wire u_ddr_cal_n_1453;
  wire u_ddr_cal_n_1454;
  wire u_ddr_cal_n_1455;
  wire u_ddr_cal_n_1456;
  wire u_ddr_cal_n_1457;
  wire u_ddr_cal_n_1458;
  wire u_ddr_cal_n_1459;
  wire u_ddr_cal_n_146;
  wire u_ddr_cal_n_1460;
  wire u_ddr_cal_n_1461;
  wire u_ddr_cal_n_1462;
  wire u_ddr_cal_n_1463;
  wire u_ddr_cal_n_1464;
  wire u_ddr_cal_n_1465;
  wire u_ddr_cal_n_1466;
  wire u_ddr_cal_n_1467;
  wire u_ddr_cal_n_1468;
  wire u_ddr_cal_n_1469;
  wire u_ddr_cal_n_147;
  wire u_ddr_cal_n_1470;
  wire u_ddr_cal_n_1471;
  wire u_ddr_cal_n_1472;
  wire u_ddr_cal_n_1473;
  wire u_ddr_cal_n_1474;
  wire u_ddr_cal_n_1475;
  wire u_ddr_cal_n_1476;
  wire u_ddr_cal_n_1477;
  wire u_ddr_cal_n_1478;
  wire u_ddr_cal_n_1479;
  wire u_ddr_cal_n_148;
  wire u_ddr_cal_n_1480;
  wire u_ddr_cal_n_1481;
  wire u_ddr_cal_n_1482;
  wire u_ddr_cal_n_1483;
  wire u_ddr_cal_n_1484;
  wire u_ddr_cal_n_1485;
  wire u_ddr_cal_n_1486;
  wire u_ddr_cal_n_1487;
  wire u_ddr_cal_n_1488;
  wire u_ddr_cal_n_149;
  wire u_ddr_cal_n_1491;
  wire u_ddr_cal_n_1492;
  wire u_ddr_cal_n_1493;
  wire u_ddr_cal_n_1494;
  wire u_ddr_cal_n_1495;
  wire u_ddr_cal_n_1496;
  wire u_ddr_cal_n_1497;
  wire u_ddr_cal_n_1498;
  wire u_ddr_cal_n_1499;
  wire u_ddr_cal_n_150;
  wire u_ddr_cal_n_1500;
  wire u_ddr_cal_n_1501;
  wire u_ddr_cal_n_1502;
  wire u_ddr_cal_n_1503;
  wire u_ddr_cal_n_1504;
  wire u_ddr_cal_n_1505;
  wire u_ddr_cal_n_1506;
  wire u_ddr_cal_n_1507;
  wire u_ddr_cal_n_1508;
  wire u_ddr_cal_n_1509;
  wire u_ddr_cal_n_151;
  wire u_ddr_cal_n_1510;
  wire u_ddr_cal_n_1511;
  wire u_ddr_cal_n_1512;
  wire u_ddr_cal_n_1513;
  wire u_ddr_cal_n_1514;
  wire u_ddr_cal_n_1515;
  wire u_ddr_cal_n_1516;
  wire u_ddr_cal_n_1517;
  wire u_ddr_cal_n_1518;
  wire u_ddr_cal_n_1519;
  wire u_ddr_cal_n_152;
  wire u_ddr_cal_n_1520;
  wire u_ddr_cal_n_1521;
  wire u_ddr_cal_n_1522;
  wire u_ddr_cal_n_1523;
  wire u_ddr_cal_n_1524;
  wire u_ddr_cal_n_1525;
  wire u_ddr_cal_n_1526;
  wire u_ddr_cal_n_1527;
  wire u_ddr_cal_n_1528;
  wire u_ddr_cal_n_1529;
  wire u_ddr_cal_n_153;
  wire u_ddr_cal_n_1530;
  wire u_ddr_cal_n_1531;
  wire u_ddr_cal_n_1532;
  wire u_ddr_cal_n_1533;
  wire u_ddr_cal_n_1534;
  wire u_ddr_cal_n_1535;
  wire u_ddr_cal_n_1536;
  wire u_ddr_cal_n_1537;
  wire u_ddr_cal_n_1538;
  wire u_ddr_cal_n_1539;
  wire u_ddr_cal_n_154;
  wire u_ddr_cal_n_1540;
  wire u_ddr_cal_n_1541;
  wire u_ddr_cal_n_1542;
  wire u_ddr_cal_n_1545;
  wire u_ddr_cal_n_1546;
  wire u_ddr_cal_n_1547;
  wire u_ddr_cal_n_1548;
  wire u_ddr_cal_n_1549;
  wire u_ddr_cal_n_155;
  wire u_ddr_cal_n_1550;
  wire u_ddr_cal_n_1551;
  wire u_ddr_cal_n_1552;
  wire u_ddr_cal_n_1553;
  wire u_ddr_cal_n_1554;
  wire u_ddr_cal_n_1555;
  wire u_ddr_cal_n_1556;
  wire u_ddr_cal_n_1557;
  wire u_ddr_cal_n_1558;
  wire u_ddr_cal_n_1559;
  wire u_ddr_cal_n_156;
  wire u_ddr_cal_n_1560;
  wire u_ddr_cal_n_1561;
  wire u_ddr_cal_n_1562;
  wire u_ddr_cal_n_1563;
  wire u_ddr_cal_n_1564;
  wire u_ddr_cal_n_1565;
  wire u_ddr_cal_n_1566;
  wire u_ddr_cal_n_1567;
  wire u_ddr_cal_n_1568;
  wire u_ddr_cal_n_1569;
  wire u_ddr_cal_n_157;
  wire u_ddr_cal_n_1570;
  wire u_ddr_cal_n_1571;
  wire u_ddr_cal_n_1572;
  wire u_ddr_cal_n_1573;
  wire u_ddr_cal_n_1574;
  wire u_ddr_cal_n_1575;
  wire u_ddr_cal_n_1576;
  wire u_ddr_cal_n_1577;
  wire u_ddr_cal_n_1578;
  wire u_ddr_cal_n_1579;
  wire u_ddr_cal_n_158;
  wire u_ddr_cal_n_1580;
  wire u_ddr_cal_n_1581;
  wire u_ddr_cal_n_1582;
  wire u_ddr_cal_n_1583;
  wire u_ddr_cal_n_1584;
  wire u_ddr_cal_n_1585;
  wire u_ddr_cal_n_1586;
  wire u_ddr_cal_n_1587;
  wire u_ddr_cal_n_1588;
  wire u_ddr_cal_n_1589;
  wire u_ddr_cal_n_159;
  wire u_ddr_cal_n_1590;
  wire u_ddr_cal_n_1591;
  wire u_ddr_cal_n_1592;
  wire u_ddr_cal_n_1593;
  wire u_ddr_cal_n_1594;
  wire u_ddr_cal_n_1595;
  wire u_ddr_cal_n_1596;
  wire u_ddr_cal_n_1599;
  wire u_ddr_cal_n_160;
  wire u_ddr_cal_n_1600;
  wire u_ddr_cal_n_1601;
  wire u_ddr_cal_n_1602;
  wire u_ddr_cal_n_1603;
  wire u_ddr_cal_n_1604;
  wire u_ddr_cal_n_1605;
  wire u_ddr_cal_n_1606;
  wire u_ddr_cal_n_1607;
  wire u_ddr_cal_n_1608;
  wire u_ddr_cal_n_1609;
  wire u_ddr_cal_n_161;
  wire u_ddr_cal_n_1610;
  wire u_ddr_cal_n_1611;
  wire u_ddr_cal_n_1612;
  wire u_ddr_cal_n_1613;
  wire u_ddr_cal_n_1614;
  wire u_ddr_cal_n_1615;
  wire u_ddr_cal_n_1616;
  wire u_ddr_cal_n_1617;
  wire u_ddr_cal_n_1618;
  wire u_ddr_cal_n_1619;
  wire u_ddr_cal_n_162;
  wire u_ddr_cal_n_1620;
  wire u_ddr_cal_n_1621;
  wire u_ddr_cal_n_1622;
  wire u_ddr_cal_n_1623;
  wire u_ddr_cal_n_1624;
  wire u_ddr_cal_n_1625;
  wire u_ddr_cal_n_1626;
  wire u_ddr_cal_n_1627;
  wire u_ddr_cal_n_1628;
  wire u_ddr_cal_n_1629;
  wire u_ddr_cal_n_163;
  wire u_ddr_cal_n_1630;
  wire u_ddr_cal_n_1631;
  wire u_ddr_cal_n_1632;
  wire u_ddr_cal_n_1633;
  wire u_ddr_cal_n_1634;
  wire u_ddr_cal_n_1635;
  wire u_ddr_cal_n_1636;
  wire u_ddr_cal_n_1637;
  wire u_ddr_cal_n_1638;
  wire u_ddr_cal_n_1639;
  wire u_ddr_cal_n_164;
  wire u_ddr_cal_n_1640;
  wire u_ddr_cal_n_1641;
  wire u_ddr_cal_n_1642;
  wire u_ddr_cal_n_1643;
  wire u_ddr_cal_n_1644;
  wire u_ddr_cal_n_1645;
  wire u_ddr_cal_n_1646;
  wire u_ddr_cal_n_1647;
  wire u_ddr_cal_n_1648;
  wire u_ddr_cal_n_1649;
  wire u_ddr_cal_n_165;
  wire u_ddr_cal_n_1650;
  wire u_ddr_cal_n_1653;
  wire u_ddr_cal_n_1654;
  wire u_ddr_cal_n_1655;
  wire u_ddr_cal_n_1656;
  wire u_ddr_cal_n_1657;
  wire u_ddr_cal_n_1658;
  wire u_ddr_cal_n_1659;
  wire u_ddr_cal_n_166;
  wire u_ddr_cal_n_1660;
  wire u_ddr_cal_n_1661;
  wire u_ddr_cal_n_1662;
  wire u_ddr_cal_n_1663;
  wire u_ddr_cal_n_1664;
  wire u_ddr_cal_n_1665;
  wire u_ddr_cal_n_1666;
  wire u_ddr_cal_n_1667;
  wire u_ddr_cal_n_1668;
  wire u_ddr_cal_n_1669;
  wire u_ddr_cal_n_167;
  wire u_ddr_cal_n_1670;
  wire u_ddr_cal_n_1671;
  wire u_ddr_cal_n_1672;
  wire u_ddr_cal_n_1673;
  wire u_ddr_cal_n_1674;
  wire u_ddr_cal_n_1675;
  wire u_ddr_cal_n_1676;
  wire u_ddr_cal_n_1677;
  wire u_ddr_cal_n_1678;
  wire u_ddr_cal_n_1679;
  wire u_ddr_cal_n_168;
  wire u_ddr_cal_n_1680;
  wire u_ddr_cal_n_1681;
  wire u_ddr_cal_n_1682;
  wire u_ddr_cal_n_1683;
  wire u_ddr_cal_n_1684;
  wire u_ddr_cal_n_1685;
  wire u_ddr_cal_n_1686;
  wire u_ddr_cal_n_1687;
  wire u_ddr_cal_n_1688;
  wire u_ddr_cal_n_1689;
  wire u_ddr_cal_n_169;
  wire u_ddr_cal_n_1690;
  wire u_ddr_cal_n_1691;
  wire u_ddr_cal_n_1692;
  wire u_ddr_cal_n_1693;
  wire u_ddr_cal_n_1694;
  wire u_ddr_cal_n_1695;
  wire u_ddr_cal_n_1696;
  wire u_ddr_cal_n_1697;
  wire u_ddr_cal_n_1698;
  wire u_ddr_cal_n_1699;
  wire u_ddr_cal_n_170;
  wire u_ddr_cal_n_1700;
  wire u_ddr_cal_n_1701;
  wire u_ddr_cal_n_1702;
  wire u_ddr_cal_n_1703;
  wire u_ddr_cal_n_1704;
  wire u_ddr_cal_n_1707;
  wire u_ddr_cal_n_1708;
  wire u_ddr_cal_n_1709;
  wire u_ddr_cal_n_171;
  wire u_ddr_cal_n_1710;
  wire u_ddr_cal_n_1711;
  wire u_ddr_cal_n_1712;
  wire u_ddr_cal_n_1713;
  wire u_ddr_cal_n_1714;
  wire u_ddr_cal_n_1715;
  wire u_ddr_cal_n_1716;
  wire u_ddr_cal_n_1717;
  wire u_ddr_cal_n_1718;
  wire u_ddr_cal_n_1719;
  wire u_ddr_cal_n_172;
  wire u_ddr_cal_n_1720;
  wire u_ddr_cal_n_1721;
  wire u_ddr_cal_n_1722;
  wire u_ddr_cal_n_1723;
  wire u_ddr_cal_n_1724;
  wire u_ddr_cal_n_1725;
  wire u_ddr_cal_n_1726;
  wire u_ddr_cal_n_1727;
  wire u_ddr_cal_n_1728;
  wire u_ddr_cal_n_1729;
  wire u_ddr_cal_n_173;
  wire u_ddr_cal_n_1730;
  wire u_ddr_cal_n_1731;
  wire u_ddr_cal_n_1732;
  wire u_ddr_cal_n_1733;
  wire u_ddr_cal_n_1734;
  wire u_ddr_cal_n_1735;
  wire u_ddr_cal_n_1736;
  wire u_ddr_cal_n_1737;
  wire u_ddr_cal_n_1738;
  wire u_ddr_cal_n_1739;
  wire u_ddr_cal_n_174;
  wire u_ddr_cal_n_1740;
  wire u_ddr_cal_n_1741;
  wire u_ddr_cal_n_1742;
  wire u_ddr_cal_n_1743;
  wire u_ddr_cal_n_1744;
  wire u_ddr_cal_n_1745;
  wire u_ddr_cal_n_1746;
  wire u_ddr_cal_n_1747;
  wire u_ddr_cal_n_1748;
  wire u_ddr_cal_n_1749;
  wire u_ddr_cal_n_175;
  wire u_ddr_cal_n_1750;
  wire u_ddr_cal_n_1751;
  wire u_ddr_cal_n_1752;
  wire u_ddr_cal_n_1753;
  wire u_ddr_cal_n_1754;
  wire u_ddr_cal_n_1755;
  wire u_ddr_cal_n_1756;
  wire u_ddr_cal_n_1757;
  wire u_ddr_cal_n_1758;
  wire u_ddr_cal_n_176;
  wire u_ddr_cal_n_1761;
  wire u_ddr_cal_n_1762;
  wire u_ddr_cal_n_1763;
  wire u_ddr_cal_n_1764;
  wire u_ddr_cal_n_1765;
  wire u_ddr_cal_n_1766;
  wire u_ddr_cal_n_1767;
  wire u_ddr_cal_n_1768;
  wire u_ddr_cal_n_1769;
  wire u_ddr_cal_n_177;
  wire u_ddr_cal_n_1770;
  wire u_ddr_cal_n_1771;
  wire u_ddr_cal_n_1772;
  wire u_ddr_cal_n_1773;
  wire u_ddr_cal_n_1774;
  wire u_ddr_cal_n_1775;
  wire u_ddr_cal_n_1776;
  wire u_ddr_cal_n_1777;
  wire u_ddr_cal_n_1778;
  wire u_ddr_cal_n_1779;
  wire u_ddr_cal_n_178;
  wire u_ddr_cal_n_1780;
  wire u_ddr_cal_n_1781;
  wire u_ddr_cal_n_1782;
  wire u_ddr_cal_n_1783;
  wire u_ddr_cal_n_1784;
  wire u_ddr_cal_n_1785;
  wire u_ddr_cal_n_1786;
  wire u_ddr_cal_n_1787;
  wire u_ddr_cal_n_1788;
  wire u_ddr_cal_n_1789;
  wire u_ddr_cal_n_179;
  wire u_ddr_cal_n_1790;
  wire u_ddr_cal_n_1791;
  wire u_ddr_cal_n_1792;
  wire u_ddr_cal_n_1793;
  wire u_ddr_cal_n_1794;
  wire u_ddr_cal_n_1795;
  wire u_ddr_cal_n_1796;
  wire u_ddr_cal_n_1797;
  wire u_ddr_cal_n_1798;
  wire u_ddr_cal_n_1799;
  wire u_ddr_cal_n_180;
  wire u_ddr_cal_n_1800;
  wire u_ddr_cal_n_1801;
  wire u_ddr_cal_n_1802;
  wire u_ddr_cal_n_1803;
  wire u_ddr_cal_n_1804;
  wire u_ddr_cal_n_1805;
  wire u_ddr_cal_n_1806;
  wire u_ddr_cal_n_1807;
  wire u_ddr_cal_n_1808;
  wire u_ddr_cal_n_1809;
  wire u_ddr_cal_n_181;
  wire u_ddr_cal_n_1810;
  wire u_ddr_cal_n_1811;
  wire u_ddr_cal_n_1812;
  wire u_ddr_cal_n_1813;
  wire u_ddr_cal_n_1814;
  wire u_ddr_cal_n_1815;
  wire u_ddr_cal_n_1816;
  wire u_ddr_cal_n_1817;
  wire u_ddr_cal_n_1818;
  wire u_ddr_cal_n_1819;
  wire u_ddr_cal_n_182;
  wire u_ddr_cal_n_1820;
  wire u_ddr_cal_n_1821;
  wire u_ddr_cal_n_1822;
  wire u_ddr_cal_n_1823;
  wire u_ddr_cal_n_1824;
  wire u_ddr_cal_n_1825;
  wire u_ddr_cal_n_1826;
  wire u_ddr_cal_n_1827;
  wire u_ddr_cal_n_1828;
  wire u_ddr_cal_n_1829;
  wire u_ddr_cal_n_183;
  wire u_ddr_cal_n_1830;
  wire u_ddr_cal_n_1831;
  wire u_ddr_cal_n_1832;
  wire u_ddr_cal_n_1833;
  wire u_ddr_cal_n_1834;
  wire u_ddr_cal_n_1835;
  wire u_ddr_cal_n_1836;
  wire u_ddr_cal_n_1837;
  wire u_ddr_cal_n_1838;
  wire u_ddr_cal_n_1839;
  wire u_ddr_cal_n_184;
  wire u_ddr_cal_n_1840;
  wire u_ddr_cal_n_1841;
  wire u_ddr_cal_n_1842;
  wire u_ddr_cal_n_1847;
  wire u_ddr_cal_n_1848;
  wire u_ddr_cal_n_1849;
  wire u_ddr_cal_n_185;
  wire u_ddr_cal_n_1850;
  wire u_ddr_cal_n_1851;
  wire u_ddr_cal_n_1852;
  wire u_ddr_cal_n_1853;
  wire u_ddr_cal_n_1854;
  wire u_ddr_cal_n_1855;
  wire u_ddr_cal_n_1856;
  wire u_ddr_cal_n_1857;
  wire u_ddr_cal_n_1858;
  wire u_ddr_cal_n_1859;
  wire u_ddr_cal_n_186;
  wire u_ddr_cal_n_1860;
  wire u_ddr_cal_n_1861;
  wire u_ddr_cal_n_1862;
  wire u_ddr_cal_n_1863;
  wire u_ddr_cal_n_1864;
  wire u_ddr_cal_n_1865;
  wire u_ddr_cal_n_1866;
  wire u_ddr_cal_n_1867;
  wire u_ddr_cal_n_1868;
  wire u_ddr_cal_n_1869;
  wire u_ddr_cal_n_187;
  wire u_ddr_cal_n_1870;
  wire u_ddr_cal_n_1871;
  wire u_ddr_cal_n_1872;
  wire u_ddr_cal_n_1873;
  wire u_ddr_cal_n_1874;
  wire u_ddr_cal_n_1875;
  wire u_ddr_cal_n_1876;
  wire u_ddr_cal_n_1877;
  wire u_ddr_cal_n_1878;
  wire u_ddr_cal_n_1879;
  wire u_ddr_cal_n_188;
  wire u_ddr_cal_n_1880;
  wire u_ddr_cal_n_1881;
  wire u_ddr_cal_n_1882;
  wire u_ddr_cal_n_1883;
  wire u_ddr_cal_n_1884;
  wire u_ddr_cal_n_1885;
  wire u_ddr_cal_n_1886;
  wire u_ddr_cal_n_189;
  wire u_ddr_cal_n_1891;
  wire u_ddr_cal_n_1892;
  wire u_ddr_cal_n_1893;
  wire u_ddr_cal_n_1894;
  wire u_ddr_cal_n_1895;
  wire u_ddr_cal_n_1896;
  wire u_ddr_cal_n_1897;
  wire u_ddr_cal_n_1898;
  wire u_ddr_cal_n_1899;
  wire u_ddr_cal_n_190;
  wire u_ddr_cal_n_1900;
  wire u_ddr_cal_n_1901;
  wire u_ddr_cal_n_1902;
  wire u_ddr_cal_n_1903;
  wire u_ddr_cal_n_1904;
  wire u_ddr_cal_n_1905;
  wire u_ddr_cal_n_1906;
  wire u_ddr_cal_n_1907;
  wire u_ddr_cal_n_1908;
  wire u_ddr_cal_n_1909;
  wire u_ddr_cal_n_191;
  wire u_ddr_cal_n_1910;
  wire u_ddr_cal_n_1911;
  wire u_ddr_cal_n_1912;
  wire u_ddr_cal_n_1913;
  wire u_ddr_cal_n_1914;
  wire u_ddr_cal_n_1915;
  wire u_ddr_cal_n_1916;
  wire u_ddr_cal_n_1917;
  wire u_ddr_cal_n_1918;
  wire u_ddr_cal_n_1919;
  wire u_ddr_cal_n_192;
  wire u_ddr_cal_n_1920;
  wire u_ddr_cal_n_1921;
  wire u_ddr_cal_n_1922;
  wire u_ddr_cal_n_1923;
  wire u_ddr_cal_n_1924;
  wire u_ddr_cal_n_1925;
  wire u_ddr_cal_n_193;
  wire u_ddr_cal_n_194;
  wire u_ddr_cal_n_195;
  wire u_ddr_cal_n_196;
  wire u_ddr_cal_n_197;
  wire u_ddr_cal_n_198;
  wire u_ddr_cal_n_199;
  wire u_ddr_cal_n_1995;
  wire u_ddr_cal_n_1996;
  wire u_ddr_cal_n_1997;
  wire u_ddr_cal_n_1998;
  wire u_ddr_cal_n_1999;
  wire u_ddr_cal_n_200;
  wire u_ddr_cal_n_2000;
  wire u_ddr_cal_n_2001;
  wire u_ddr_cal_n_2002;
  wire u_ddr_cal_n_2003;
  wire u_ddr_cal_n_2004;
  wire u_ddr_cal_n_2005;
  wire u_ddr_cal_n_2006;
  wire u_ddr_cal_n_2007;
  wire u_ddr_cal_n_2008;
  wire u_ddr_cal_n_2009;
  wire u_ddr_cal_n_201;
  wire u_ddr_cal_n_2010;
  wire u_ddr_cal_n_2011;
  wire u_ddr_cal_n_2012;
  wire u_ddr_cal_n_2013;
  wire u_ddr_cal_n_2014;
  wire u_ddr_cal_n_2015;
  wire u_ddr_cal_n_2016;
  wire u_ddr_cal_n_2017;
  wire u_ddr_cal_n_2018;
  wire u_ddr_cal_n_2019;
  wire u_ddr_cal_n_202;
  wire u_ddr_cal_n_2020;
  wire u_ddr_cal_n_2021;
  wire u_ddr_cal_n_2022;
  wire u_ddr_cal_n_2023;
  wire u_ddr_cal_n_2024;
  wire u_ddr_cal_n_2025;
  wire u_ddr_cal_n_2026;
  wire u_ddr_cal_n_2027;
  wire u_ddr_cal_n_2028;
  wire u_ddr_cal_n_2029;
  wire u_ddr_cal_n_2030;
  wire u_ddr_cal_n_2031;
  wire u_ddr_cal_n_2032;
  wire u_ddr_cal_n_2033;
  wire u_ddr_cal_n_2034;
  wire u_ddr_cal_n_2035;
  wire u_ddr_cal_n_2036;
  wire u_ddr_cal_n_2037;
  wire u_ddr_cal_n_2038;
  wire u_ddr_cal_n_2039;
  wire u_ddr_cal_n_204;
  wire u_ddr_cal_n_2040;
  wire u_ddr_cal_n_2041;
  wire u_ddr_cal_n_2042;
  wire u_ddr_cal_n_2043;
  wire u_ddr_cal_n_2044;
  wire u_ddr_cal_n_2045;
  wire u_ddr_cal_n_2046;
  wire u_ddr_cal_n_2047;
  wire u_ddr_cal_n_2048;
  wire u_ddr_cal_n_2049;
  wire u_ddr_cal_n_205;
  wire u_ddr_cal_n_2050;
  wire u_ddr_cal_n_2051;
  wire u_ddr_cal_n_2052;
  wire u_ddr_cal_n_206;
  wire u_ddr_cal_n_2063;
  wire u_ddr_cal_n_2064;
  wire u_ddr_cal_n_2065;
  wire u_ddr_cal_n_2066;
  wire u_ddr_cal_n_2067;
  wire u_ddr_cal_n_2068;
  wire u_ddr_cal_n_2069;
  wire u_ddr_cal_n_207;
  wire u_ddr_cal_n_2070;
  wire u_ddr_cal_n_2071;
  wire u_ddr_cal_n_2072;
  wire u_ddr_cal_n_2073;
  wire u_ddr_cal_n_2074;
  wire u_ddr_cal_n_2075;
  wire u_ddr_cal_n_2076;
  wire u_ddr_cal_n_2077;
  wire u_ddr_cal_n_2078;
  wire u_ddr_cal_n_2079;
  wire u_ddr_cal_n_2080;
  wire u_ddr_cal_n_2081;
  wire u_ddr_cal_n_2082;
  wire u_ddr_cal_n_2083;
  wire u_ddr_cal_n_2084;
  wire u_ddr_cal_n_2085;
  wire u_ddr_cal_n_2086;
  wire u_ddr_cal_n_2087;
  wire u_ddr_cal_n_2088;
  wire u_ddr_cal_n_2089;
  wire u_ddr_cal_n_209;
  wire u_ddr_cal_n_2090;
  wire u_ddr_cal_n_2091;
  wire u_ddr_cal_n_2092;
  wire u_ddr_cal_n_2093;
  wire u_ddr_cal_n_2094;
  wire u_ddr_cal_n_2095;
  wire u_ddr_cal_n_2096;
  wire u_ddr_cal_n_2097;
  wire u_ddr_cal_n_2098;
  wire u_ddr_cal_n_2099;
  wire u_ddr_cal_n_210;
  wire u_ddr_cal_n_2100;
  wire u_ddr_cal_n_2101;
  wire u_ddr_cal_n_2102;
  wire u_ddr_cal_n_2103;
  wire u_ddr_cal_n_2104;
  wire u_ddr_cal_n_2105;
  wire u_ddr_cal_n_2106;
  wire u_ddr_cal_n_2107;
  wire u_ddr_cal_n_2108;
  wire u_ddr_cal_n_2109;
  wire u_ddr_cal_n_211;
  wire u_ddr_cal_n_2110;
  wire u_ddr_cal_n_2111;
  wire u_ddr_cal_n_2112;
  wire u_ddr_cal_n_2113;
  wire u_ddr_cal_n_2114;
  wire u_ddr_cal_n_2115;
  wire u_ddr_cal_n_2116;
  wire u_ddr_cal_n_2117;
  wire u_ddr_cal_n_2118;
  wire u_ddr_cal_n_2119;
  wire u_ddr_cal_n_212;
  wire u_ddr_cal_n_2120;
  wire u_ddr_cal_n_213;
  wire u_ddr_cal_n_2131;
  wire u_ddr_cal_n_2132;
  wire u_ddr_cal_n_2133;
  wire u_ddr_cal_n_2134;
  wire u_ddr_cal_n_2135;
  wire u_ddr_cal_n_2136;
  wire u_ddr_cal_n_2137;
  wire u_ddr_cal_n_2138;
  wire u_ddr_cal_n_2139;
  wire u_ddr_cal_n_214;
  wire u_ddr_cal_n_2140;
  wire u_ddr_cal_n_2141;
  wire u_ddr_cal_n_2142;
  wire u_ddr_cal_n_2143;
  wire u_ddr_cal_n_2144;
  wire u_ddr_cal_n_2145;
  wire u_ddr_cal_n_2146;
  wire u_ddr_cal_n_2147;
  wire u_ddr_cal_n_2148;
  wire u_ddr_cal_n_2149;
  wire u_ddr_cal_n_215;
  wire u_ddr_cal_n_2150;
  wire u_ddr_cal_n_2151;
  wire u_ddr_cal_n_2152;
  wire u_ddr_cal_n_2153;
  wire u_ddr_cal_n_2154;
  wire u_ddr_cal_n_2155;
  wire u_ddr_cal_n_2156;
  wire u_ddr_cal_n_2157;
  wire u_ddr_cal_n_2158;
  wire u_ddr_cal_n_2159;
  wire u_ddr_cal_n_216;
  wire u_ddr_cal_n_2160;
  wire u_ddr_cal_n_2161;
  wire u_ddr_cal_n_2162;
  wire u_ddr_cal_n_2163;
  wire u_ddr_cal_n_2164;
  wire u_ddr_cal_n_2165;
  wire u_ddr_cal_n_2166;
  wire u_ddr_cal_n_2167;
  wire u_ddr_cal_n_2168;
  wire u_ddr_cal_n_2169;
  wire u_ddr_cal_n_2170;
  wire u_ddr_cal_n_2171;
  wire u_ddr_cal_n_2172;
  wire u_ddr_cal_n_2173;
  wire u_ddr_cal_n_2174;
  wire u_ddr_cal_n_2175;
  wire u_ddr_cal_n_2176;
  wire u_ddr_cal_n_2177;
  wire u_ddr_cal_n_2178;
  wire u_ddr_cal_n_2179;
  wire u_ddr_cal_n_2180;
  wire u_ddr_cal_n_2181;
  wire u_ddr_cal_n_2182;
  wire u_ddr_cal_n_2183;
  wire u_ddr_cal_n_2184;
  wire u_ddr_cal_n_2185;
  wire u_ddr_cal_n_2186;
  wire u_ddr_cal_n_2187;
  wire u_ddr_cal_n_2188;
  wire u_ddr_cal_n_2199;
  wire u_ddr_cal_n_2200;
  wire u_ddr_cal_n_2201;
  wire u_ddr_cal_n_2202;
  wire u_ddr_cal_n_2203;
  wire u_ddr_cal_n_2204;
  wire u_ddr_cal_n_2205;
  wire u_ddr_cal_n_2206;
  wire u_ddr_cal_n_2207;
  wire u_ddr_cal_n_2208;
  wire u_ddr_cal_n_2209;
  wire u_ddr_cal_n_2210;
  wire u_ddr_cal_n_2211;
  wire u_ddr_cal_n_2212;
  wire u_ddr_cal_n_2213;
  wire u_ddr_cal_n_2214;
  wire u_ddr_cal_n_2215;
  wire u_ddr_cal_n_2216;
  wire u_ddr_cal_n_2217;
  wire u_ddr_cal_n_2218;
  wire u_ddr_cal_n_2219;
  wire u_ddr_cal_n_2220;
  wire u_ddr_cal_n_2221;
  wire u_ddr_cal_n_2222;
  wire u_ddr_cal_n_2223;
  wire u_ddr_cal_n_2224;
  wire u_ddr_cal_n_2225;
  wire u_ddr_cal_n_2226;
  wire u_ddr_cal_n_2227;
  wire u_ddr_cal_n_2228;
  wire u_ddr_cal_n_2229;
  wire u_ddr_cal_n_2230;
  wire u_ddr_cal_n_2231;
  wire u_ddr_cal_n_2232;
  wire u_ddr_cal_n_2233;
  wire u_ddr_cal_n_2234;
  wire u_ddr_cal_n_2235;
  wire u_ddr_cal_n_2236;
  wire u_ddr_cal_n_2237;
  wire u_ddr_cal_n_2238;
  wire u_ddr_cal_n_2239;
  wire u_ddr_cal_n_2240;
  wire u_ddr_cal_n_2241;
  wire u_ddr_cal_n_2242;
  wire u_ddr_cal_n_2243;
  wire u_ddr_cal_n_2244;
  wire u_ddr_cal_n_2245;
  wire u_ddr_cal_n_2246;
  wire u_ddr_cal_n_2247;
  wire u_ddr_cal_n_2248;
  wire u_ddr_cal_n_2249;
  wire u_ddr_cal_n_2250;
  wire u_ddr_cal_n_2251;
  wire u_ddr_cal_n_2252;
  wire u_ddr_cal_n_2253;
  wire u_ddr_cal_n_2254;
  wire u_ddr_cal_n_2255;
  wire u_ddr_cal_n_2256;
  wire u_ddr_cal_n_2267;
  wire u_ddr_cal_n_2268;
  wire u_ddr_cal_n_2269;
  wire u_ddr_cal_n_2270;
  wire u_ddr_cal_n_2271;
  wire u_ddr_cal_n_2272;
  wire u_ddr_cal_n_2273;
  wire u_ddr_cal_n_2274;
  wire u_ddr_cal_n_2275;
  wire u_ddr_cal_n_2276;
  wire u_ddr_cal_n_2277;
  wire u_ddr_cal_n_2278;
  wire u_ddr_cal_n_2279;
  wire u_ddr_cal_n_2280;
  wire u_ddr_cal_n_2281;
  wire u_ddr_cal_n_2282;
  wire u_ddr_cal_n_2283;
  wire u_ddr_cal_n_2284;
  wire u_ddr_cal_n_2285;
  wire u_ddr_cal_n_2286;
  wire u_ddr_cal_n_2287;
  wire u_ddr_cal_n_2288;
  wire u_ddr_cal_n_2289;
  wire u_ddr_cal_n_2290;
  wire u_ddr_cal_n_2291;
  wire u_ddr_cal_n_2292;
  wire u_ddr_cal_n_2293;
  wire u_ddr_cal_n_2294;
  wire u_ddr_cal_n_2295;
  wire u_ddr_cal_n_2296;
  wire u_ddr_cal_n_2297;
  wire u_ddr_cal_n_2298;
  wire u_ddr_cal_n_2299;
  wire u_ddr_cal_n_2300;
  wire u_ddr_cal_n_2301;
  wire u_ddr_cal_n_2302;
  wire u_ddr_cal_n_2303;
  wire u_ddr_cal_n_2304;
  wire u_ddr_cal_n_2305;
  wire u_ddr_cal_n_2306;
  wire u_ddr_cal_n_2307;
  wire u_ddr_cal_n_2308;
  wire u_ddr_cal_n_2309;
  wire u_ddr_cal_n_2310;
  wire u_ddr_cal_n_2311;
  wire u_ddr_cal_n_2312;
  wire u_ddr_cal_n_2313;
  wire u_ddr_cal_n_2314;
  wire u_ddr_cal_n_2315;
  wire u_ddr_cal_n_2316;
  wire u_ddr_cal_n_2317;
  wire u_ddr_cal_n_2318;
  wire u_ddr_cal_n_2319;
  wire u_ddr_cal_n_2320;
  wire u_ddr_cal_n_2321;
  wire u_ddr_cal_n_2322;
  wire u_ddr_cal_n_2323;
  wire u_ddr_cal_n_2324;
  wire u_ddr_cal_n_2335;
  wire u_ddr_cal_n_2336;
  wire u_ddr_cal_n_2337;
  wire u_ddr_cal_n_2338;
  wire u_ddr_cal_n_2339;
  wire u_ddr_cal_n_2340;
  wire u_ddr_cal_n_2341;
  wire u_ddr_cal_n_2342;
  wire u_ddr_cal_n_2343;
  wire u_ddr_cal_n_2344;
  wire u_ddr_cal_n_2345;
  wire u_ddr_cal_n_2346;
  wire u_ddr_cal_n_2347;
  wire u_ddr_cal_n_2348;
  wire u_ddr_cal_n_2349;
  wire u_ddr_cal_n_2350;
  wire u_ddr_cal_n_2351;
  wire u_ddr_cal_n_2352;
  wire u_ddr_cal_n_2353;
  wire u_ddr_cal_n_2354;
  wire u_ddr_cal_n_2355;
  wire u_ddr_cal_n_2356;
  wire u_ddr_cal_n_2357;
  wire u_ddr_cal_n_2358;
  wire u_ddr_cal_n_2359;
  wire u_ddr_cal_n_2360;
  wire u_ddr_cal_n_2361;
  wire u_ddr_cal_n_2362;
  wire u_ddr_cal_n_2363;
  wire u_ddr_cal_n_2364;
  wire u_ddr_cal_n_2365;
  wire u_ddr_cal_n_2366;
  wire u_ddr_cal_n_2367;
  wire u_ddr_cal_n_2368;
  wire u_ddr_cal_n_2369;
  wire u_ddr_cal_n_2370;
  wire u_ddr_cal_n_2371;
  wire u_ddr_cal_n_2372;
  wire u_ddr_cal_n_2373;
  wire u_ddr_cal_n_2374;
  wire u_ddr_cal_n_2375;
  wire u_ddr_cal_n_2376;
  wire u_ddr_cal_n_2377;
  wire u_ddr_cal_n_2378;
  wire u_ddr_cal_n_2379;
  wire u_ddr_cal_n_2380;
  wire u_ddr_cal_n_2381;
  wire u_ddr_cal_n_2382;
  wire u_ddr_cal_n_2383;
  wire u_ddr_cal_n_2384;
  wire u_ddr_cal_n_2385;
  wire u_ddr_cal_n_2386;
  wire u_ddr_cal_n_2387;
  wire u_ddr_cal_n_2388;
  wire u_ddr_cal_n_2389;
  wire u_ddr_cal_n_2390;
  wire u_ddr_cal_n_2391;
  wire u_ddr_cal_n_2392;
  wire u_ddr_cal_n_2403;
  wire u_ddr_cal_n_2404;
  wire u_ddr_cal_n_2405;
  wire u_ddr_cal_n_2406;
  wire u_ddr_cal_n_2407;
  wire u_ddr_cal_n_2408;
  wire u_ddr_cal_n_2409;
  wire u_ddr_cal_n_2410;
  wire u_ddr_cal_n_2411;
  wire u_ddr_cal_n_2412;
  wire u_ddr_cal_n_2413;
  wire u_ddr_cal_n_2414;
  wire u_ddr_cal_n_2415;
  wire u_ddr_cal_n_2416;
  wire u_ddr_cal_n_2417;
  wire u_ddr_cal_n_2418;
  wire u_ddr_cal_n_2419;
  wire u_ddr_cal_n_2420;
  wire u_ddr_cal_n_2421;
  wire u_ddr_cal_n_2422;
  wire u_ddr_cal_n_2423;
  wire u_ddr_cal_n_2424;
  wire u_ddr_cal_n_2425;
  wire u_ddr_cal_n_2426;
  wire u_ddr_cal_n_2427;
  wire u_ddr_cal_n_2428;
  wire u_ddr_cal_n_2429;
  wire u_ddr_cal_n_2430;
  wire u_ddr_cal_n_2431;
  wire u_ddr_cal_n_2432;
  wire u_ddr_cal_n_2433;
  wire u_ddr_cal_n_2434;
  wire u_ddr_cal_n_2435;
  wire u_ddr_cal_n_2436;
  wire u_ddr_cal_n_2437;
  wire u_ddr_cal_n_2438;
  wire u_ddr_cal_n_2439;
  wire u_ddr_cal_n_2440;
  wire u_ddr_cal_n_2441;
  wire u_ddr_cal_n_2442;
  wire u_ddr_cal_n_2443;
  wire u_ddr_cal_n_2444;
  wire u_ddr_cal_n_2445;
  wire u_ddr_cal_n_2446;
  wire u_ddr_cal_n_2447;
  wire u_ddr_cal_n_2448;
  wire u_ddr_cal_n_2449;
  wire u_ddr_cal_n_2450;
  wire u_ddr_cal_n_2451;
  wire u_ddr_cal_n_2452;
  wire u_ddr_cal_n_2453;
  wire u_ddr_cal_n_2454;
  wire u_ddr_cal_n_2455;
  wire u_ddr_cal_n_2456;
  wire u_ddr_cal_n_2457;
  wire u_ddr_cal_n_2458;
  wire u_ddr_cal_n_2459;
  wire u_ddr_cal_n_2460;
  wire u_ddr_cal_n_2471;
  wire u_ddr_cal_n_2472;
  wire u_ddr_cal_n_2473;
  wire u_ddr_cal_n_2474;
  wire u_ddr_cal_n_2475;
  wire u_ddr_cal_n_2476;
  wire u_ddr_cal_n_2477;
  wire u_ddr_cal_n_2478;
  wire u_ddr_cal_n_2479;
  wire u_ddr_cal_n_2480;
  wire u_ddr_cal_n_2481;
  wire u_ddr_cal_n_2482;
  wire u_ddr_cal_n_2483;
  wire u_ddr_cal_n_2484;
  wire u_ddr_cal_n_2485;
  wire u_ddr_cal_n_2486;
  wire u_ddr_cal_n_2487;
  wire u_ddr_cal_n_2488;
  wire u_ddr_cal_n_2489;
  wire u_ddr_cal_n_2490;
  wire u_ddr_cal_n_2491;
  wire u_ddr_cal_n_2492;
  wire u_ddr_cal_n_2493;
  wire u_ddr_cal_n_2494;
  wire u_ddr_cal_n_2495;
  wire u_ddr_cal_n_2496;
  wire u_ddr_cal_n_2497;
  wire u_ddr_cal_n_2498;
  wire u_ddr_cal_n_2499;
  wire u_ddr_cal_n_2500;
  wire u_ddr_cal_n_2501;
  wire u_ddr_cal_n_2502;
  wire u_ddr_cal_n_2503;
  wire u_ddr_cal_n_2504;
  wire u_ddr_cal_n_2505;
  wire u_ddr_cal_n_2506;
  wire u_ddr_cal_n_2507;
  wire u_ddr_cal_n_2508;
  wire u_ddr_cal_n_2509;
  wire u_ddr_cal_n_2510;
  wire u_ddr_cal_n_2511;
  wire u_ddr_cal_n_2512;
  wire u_ddr_cal_n_2513;
  wire u_ddr_cal_n_2514;
  wire u_ddr_cal_n_2515;
  wire u_ddr_cal_n_2516;
  wire u_ddr_cal_n_2517;
  wire u_ddr_cal_n_2518;
  wire u_ddr_cal_n_2519;
  wire u_ddr_cal_n_2520;
  wire u_ddr_cal_n_2521;
  wire u_ddr_cal_n_2522;
  wire u_ddr_cal_n_2523;
  wire u_ddr_cal_n_2524;
  wire u_ddr_cal_n_2525;
  wire u_ddr_cal_n_2526;
  wire u_ddr_cal_n_2527;
  wire u_ddr_cal_n_2528;
  wire u_ddr_cal_n_2539;
  wire u_ddr_cal_n_2540;
  wire u_ddr_cal_n_2541;
  wire u_ddr_cal_n_2542;
  wire u_ddr_cal_n_2543;
  wire u_ddr_cal_n_2544;
  wire u_ddr_cal_n_2545;
  wire u_ddr_cal_n_2546;
  wire u_ddr_cal_n_2547;
  wire u_ddr_cal_n_2548;
  wire u_ddr_cal_n_2549;
  wire u_ddr_cal_n_2550;
  wire u_ddr_cal_n_2551;
  wire u_ddr_cal_n_2552;
  wire u_ddr_cal_n_2553;
  wire u_ddr_cal_n_2554;
  wire u_ddr_cal_n_2555;
  wire u_ddr_cal_n_2556;
  wire u_ddr_cal_n_2557;
  wire u_ddr_cal_n_2558;
  wire u_ddr_cal_n_2559;
  wire u_ddr_cal_n_2560;
  wire u_ddr_cal_n_2561;
  wire u_ddr_cal_n_2562;
  wire u_ddr_cal_n_2563;
  wire u_ddr_cal_n_2564;
  wire u_ddr_cal_n_2565;
  wire u_ddr_cal_n_2566;
  wire u_ddr_cal_n_2567;
  wire u_ddr_cal_n_2568;
  wire u_ddr_cal_n_2569;
  wire u_ddr_cal_n_2570;
  wire u_ddr_cal_n_2571;
  wire u_ddr_cal_n_2572;
  wire u_ddr_cal_n_2573;
  wire u_ddr_cal_n_2574;
  wire u_ddr_cal_n_2575;
  wire u_ddr_cal_n_2576;
  wire u_ddr_cal_n_2577;
  wire u_ddr_cal_n_2578;
  wire u_ddr_cal_n_2579;
  wire u_ddr_cal_n_2580;
  wire u_ddr_cal_n_2581;
  wire u_ddr_cal_n_2582;
  wire u_ddr_cal_n_2583;
  wire u_ddr_cal_n_2584;
  wire u_ddr_cal_n_2585;
  wire u_ddr_cal_n_2586;
  wire u_ddr_cal_n_2587;
  wire u_ddr_cal_n_2588;
  wire u_ddr_cal_n_2589;
  wire u_ddr_cal_n_2590;
  wire u_ddr_cal_n_2591;
  wire u_ddr_cal_n_2592;
  wire u_ddr_cal_n_2593;
  wire u_ddr_cal_n_2594;
  wire u_ddr_cal_n_2595;
  wire u_ddr_cal_n_2596;
  wire u_ddr_cal_n_2607;
  wire u_ddr_cal_n_2608;
  wire u_ddr_cal_n_2609;
  wire u_ddr_cal_n_2610;
  wire u_ddr_cal_n_2611;
  wire u_ddr_cal_n_2612;
  wire u_ddr_cal_n_2613;
  wire u_ddr_cal_n_2614;
  wire u_ddr_cal_n_2615;
  wire u_ddr_cal_n_2616;
  wire u_ddr_cal_n_2617;
  wire u_ddr_cal_n_2618;
  wire u_ddr_cal_n_2619;
  wire u_ddr_cal_n_2620;
  wire u_ddr_cal_n_2621;
  wire u_ddr_cal_n_2622;
  wire u_ddr_cal_n_2623;
  wire u_ddr_cal_n_2624;
  wire u_ddr_cal_n_2625;
  wire u_ddr_cal_n_2626;
  wire u_ddr_cal_n_2627;
  wire u_ddr_cal_n_2628;
  wire u_ddr_cal_n_2629;
  wire u_ddr_cal_n_2630;
  wire u_ddr_cal_n_2631;
  wire u_ddr_cal_n_2632;
  wire u_ddr_cal_n_2633;
  wire u_ddr_cal_n_2634;
  wire u_ddr_cal_n_2635;
  wire u_ddr_cal_n_2636;
  wire u_ddr_cal_n_2637;
  wire u_ddr_cal_n_2638;
  wire u_ddr_cal_n_2639;
  wire u_ddr_cal_n_2640;
  wire u_ddr_cal_n_2641;
  wire u_ddr_cal_n_2642;
  wire u_ddr_cal_n_2643;
  wire u_ddr_cal_n_2644;
  wire u_ddr_cal_n_2645;
  wire u_ddr_cal_n_2646;
  wire u_ddr_cal_n_2647;
  wire u_ddr_cal_n_2648;
  wire u_ddr_cal_n_2649;
  wire u_ddr_cal_n_2650;
  wire u_ddr_cal_n_2651;
  wire u_ddr_cal_n_2652;
  wire u_ddr_cal_n_2653;
  wire u_ddr_cal_n_2654;
  wire u_ddr_cal_n_2655;
  wire u_ddr_cal_n_2656;
  wire u_ddr_cal_n_2657;
  wire u_ddr_cal_n_2658;
  wire u_ddr_cal_n_2659;
  wire u_ddr_cal_n_2660;
  wire u_ddr_cal_n_2661;
  wire u_ddr_cal_n_2662;
  wire u_ddr_cal_n_2663;
  wire u_ddr_cal_n_2664;
  wire u_ddr_cal_n_2675;
  wire u_ddr_cal_n_2676;
  wire u_ddr_cal_n_2677;
  wire u_ddr_cal_n_2678;
  wire u_ddr_cal_n_2679;
  wire u_ddr_cal_n_2680;
  wire u_ddr_cal_n_2681;
  wire u_ddr_cal_n_2682;
  wire u_ddr_cal_n_2683;
  wire u_ddr_cal_n_2684;
  wire u_ddr_cal_n_2685;
  wire u_ddr_cal_n_2686;
  wire u_ddr_cal_n_2687;
  wire u_ddr_cal_n_2688;
  wire u_ddr_cal_n_2689;
  wire u_ddr_cal_n_2690;
  wire u_ddr_cal_n_2691;
  wire u_ddr_cal_n_2692;
  wire u_ddr_cal_n_2693;
  wire u_ddr_cal_n_2694;
  wire u_ddr_cal_n_2695;
  wire u_ddr_cal_n_2696;
  wire u_ddr_cal_n_2697;
  wire u_ddr_cal_n_2698;
  wire u_ddr_cal_n_2699;
  wire u_ddr_cal_n_2700;
  wire u_ddr_cal_n_2701;
  wire u_ddr_cal_n_2702;
  wire u_ddr_cal_n_2703;
  wire u_ddr_cal_n_2704;
  wire u_ddr_cal_n_2705;
  wire u_ddr_cal_n_2706;
  wire u_ddr_cal_n_2707;
  wire u_ddr_cal_n_2708;
  wire u_ddr_cal_n_2709;
  wire u_ddr_cal_n_2710;
  wire u_ddr_cal_n_2711;
  wire u_ddr_cal_n_2712;
  wire u_ddr_cal_n_2713;
  wire u_ddr_cal_n_2714;
  wire u_ddr_cal_n_2715;
  wire u_ddr_cal_n_2716;
  wire u_ddr_cal_n_2717;
  wire u_ddr_cal_n_2718;
  wire u_ddr_cal_n_2719;
  wire u_ddr_cal_n_2720;
  wire u_ddr_cal_n_2721;
  wire u_ddr_cal_n_2722;
  wire u_ddr_cal_n_2723;
  wire u_ddr_cal_n_2724;
  wire u_ddr_cal_n_2725;
  wire u_ddr_cal_n_2726;
  wire u_ddr_cal_n_2727;
  wire u_ddr_cal_n_2728;
  wire u_ddr_cal_n_2729;
  wire u_ddr_cal_n_2730;
  wire u_ddr_cal_n_2731;
  wire u_ddr_cal_n_2732;
  wire u_ddr_cal_n_2743;
  wire u_ddr_cal_n_2744;
  wire u_ddr_cal_n_2745;
  wire u_ddr_cal_n_2746;
  wire u_ddr_cal_n_2747;
  wire u_ddr_cal_n_2748;
  wire u_ddr_cal_n_2749;
  wire u_ddr_cal_n_2750;
  wire u_ddr_cal_n_2751;
  wire u_ddr_cal_n_2752;
  wire u_ddr_cal_n_2753;
  wire u_ddr_cal_n_2754;
  wire u_ddr_cal_n_2755;
  wire u_ddr_cal_n_2756;
  wire u_ddr_cal_n_2757;
  wire u_ddr_cal_n_2758;
  wire u_ddr_cal_n_2759;
  wire u_ddr_cal_n_2760;
  wire u_ddr_cal_n_2761;
  wire u_ddr_cal_n_2762;
  wire u_ddr_cal_n_2763;
  wire u_ddr_cal_n_2764;
  wire u_ddr_cal_n_2765;
  wire u_ddr_cal_n_2766;
  wire u_ddr_cal_n_2767;
  wire u_ddr_cal_n_2768;
  wire u_ddr_cal_n_2769;
  wire u_ddr_cal_n_2770;
  wire u_ddr_cal_n_2771;
  wire u_ddr_cal_n_2772;
  wire u_ddr_cal_n_2773;
  wire u_ddr_cal_n_2774;
  wire u_ddr_cal_n_2775;
  wire u_ddr_cal_n_2776;
  wire u_ddr_cal_n_2777;
  wire u_ddr_cal_n_2778;
  wire u_ddr_cal_n_2779;
  wire u_ddr_cal_n_2780;
  wire u_ddr_cal_n_2781;
  wire u_ddr_cal_n_2782;
  wire u_ddr_cal_n_2783;
  wire u_ddr_cal_n_2784;
  wire u_ddr_cal_n_2785;
  wire u_ddr_cal_n_2786;
  wire u_ddr_cal_n_2787;
  wire u_ddr_cal_n_2788;
  wire u_ddr_cal_n_2789;
  wire u_ddr_cal_n_2790;
  wire u_ddr_cal_n_2791;
  wire u_ddr_cal_n_2792;
  wire u_ddr_cal_n_2793;
  wire u_ddr_cal_n_2794;
  wire u_ddr_cal_n_2795;
  wire u_ddr_cal_n_2796;
  wire u_ddr_cal_n_2797;
  wire u_ddr_cal_n_2798;
  wire u_ddr_cal_n_2799;
  wire u_ddr_cal_n_2800;
  wire u_ddr_cal_n_2811;
  wire u_ddr_cal_n_2812;
  wire u_ddr_cal_n_2813;
  wire u_ddr_cal_n_2814;
  wire u_ddr_cal_n_2815;
  wire u_ddr_cal_n_2816;
  wire u_ddr_cal_n_2817;
  wire u_ddr_cal_n_2818;
  wire u_ddr_cal_n_2819;
  wire u_ddr_cal_n_2820;
  wire u_ddr_cal_n_2821;
  wire u_ddr_cal_n_2822;
  wire u_ddr_cal_n_2823;
  wire u_ddr_cal_n_2824;
  wire u_ddr_cal_n_2825;
  wire u_ddr_cal_n_2826;
  wire u_ddr_cal_n_2827;
  wire u_ddr_cal_n_2828;
  wire u_ddr_cal_n_2829;
  wire u_ddr_cal_n_2830;
  wire u_ddr_cal_n_2831;
  wire u_ddr_cal_n_2832;
  wire u_ddr_cal_n_2833;
  wire u_ddr_cal_n_2834;
  wire u_ddr_cal_n_2835;
  wire u_ddr_cal_n_2836;
  wire u_ddr_cal_n_2837;
  wire u_ddr_cal_n_2838;
  wire u_ddr_cal_n_2839;
  wire u_ddr_cal_n_2840;
  wire u_ddr_cal_n_2841;
  wire u_ddr_cal_n_2842;
  wire u_ddr_cal_n_2843;
  wire u_ddr_cal_n_2844;
  wire u_ddr_cal_n_2845;
  wire u_ddr_cal_n_2846;
  wire u_ddr_cal_n_2847;
  wire u_ddr_cal_n_2848;
  wire u_ddr_cal_n_2849;
  wire u_ddr_cal_n_2850;
  wire u_ddr_cal_n_2851;
  wire u_ddr_cal_n_2852;
  wire u_ddr_cal_n_2853;
  wire u_ddr_cal_n_2854;
  wire u_ddr_cal_n_2855;
  wire u_ddr_cal_n_2856;
  wire u_ddr_cal_n_2857;
  wire u_ddr_cal_n_2858;
  wire u_ddr_cal_n_2859;
  wire u_ddr_cal_n_2860;
  wire u_ddr_cal_n_2861;
  wire u_ddr_cal_n_2862;
  wire u_ddr_cal_n_2863;
  wire u_ddr_cal_n_2864;
  wire u_ddr_cal_n_2865;
  wire u_ddr_cal_n_2866;
  wire u_ddr_cal_n_2867;
  wire u_ddr_cal_n_2868;
  wire u_ddr_cal_n_2879;
  wire u_ddr_cal_n_2880;
  wire u_ddr_cal_n_2881;
  wire u_ddr_cal_n_2882;
  wire u_ddr_cal_n_2883;
  wire u_ddr_cal_n_2884;
  wire u_ddr_cal_n_2885;
  wire u_ddr_cal_n_2886;
  wire u_ddr_cal_n_2887;
  wire u_ddr_cal_n_2888;
  wire u_ddr_cal_n_2889;
  wire u_ddr_cal_n_2890;
  wire u_ddr_cal_n_2891;
  wire u_ddr_cal_n_2892;
  wire u_ddr_cal_n_2893;
  wire u_ddr_cal_n_2894;
  wire u_ddr_cal_n_2895;
  wire u_ddr_cal_n_2896;
  wire u_ddr_cal_n_2897;
  wire u_ddr_cal_n_2898;
  wire u_ddr_cal_n_2899;
  wire u_ddr_cal_n_2900;
  wire u_ddr_cal_n_2901;
  wire u_ddr_cal_n_2902;
  wire u_ddr_cal_n_2903;
  wire u_ddr_cal_n_2904;
  wire u_ddr_cal_n_2905;
  wire u_ddr_cal_n_2906;
  wire u_ddr_cal_n_2907;
  wire u_ddr_cal_n_2908;
  wire u_ddr_cal_n_2909;
  wire u_ddr_cal_n_2910;
  wire u_ddr_cal_n_2911;
  wire u_ddr_cal_n_2912;
  wire u_ddr_cal_n_2913;
  wire u_ddr_cal_n_2914;
  wire u_ddr_cal_n_2915;
  wire u_ddr_cal_n_2916;
  wire u_ddr_cal_n_2917;
  wire u_ddr_cal_n_2918;
  wire u_ddr_cal_n_2919;
  wire u_ddr_cal_n_2920;
  wire u_ddr_cal_n_2921;
  wire u_ddr_cal_n_2922;
  wire u_ddr_cal_n_2923;
  wire u_ddr_cal_n_2924;
  wire u_ddr_cal_n_2925;
  wire u_ddr_cal_n_2926;
  wire u_ddr_cal_n_2927;
  wire u_ddr_cal_n_2928;
  wire u_ddr_cal_n_2929;
  wire u_ddr_cal_n_2930;
  wire u_ddr_cal_n_2931;
  wire u_ddr_cal_n_2932;
  wire u_ddr_cal_n_2933;
  wire u_ddr_cal_n_2934;
  wire u_ddr_cal_n_2935;
  wire u_ddr_cal_n_2936;
  wire u_ddr_cal_n_2943;
  wire u_ddr_cal_n_2944;
  wire u_ddr_cal_n_2945;
  wire u_ddr_cal_n_2946;
  wire u_ddr_cal_n_2947;
  wire u_ddr_cal_n_2948;
  wire u_ddr_cal_n_2949;
  wire u_ddr_cal_n_2950;
  wire u_ddr_cal_n_2951;
  wire u_ddr_cal_n_2952;
  wire u_ddr_cal_n_2953;
  wire u_ddr_cal_n_2954;
  wire u_ddr_cal_n_2955;
  wire u_ddr_cal_n_2956;
  wire u_ddr_cal_n_2957;
  wire u_ddr_cal_n_2963;
  wire u_ddr_cal_n_2964;
  wire u_ddr_cal_n_2965;
  wire u_ddr_cal_n_2966;
  wire u_ddr_cal_n_2967;
  wire u_ddr_cal_n_2968;
  wire u_ddr_cal_n_2969;
  wire u_ddr_cal_n_2970;
  wire u_ddr_cal_n_2971;
  wire u_ddr_cal_n_2972;
  wire u_ddr_cal_n_2973;
  wire u_ddr_cal_n_2974;
  wire u_ddr_cal_n_2975;
  wire u_ddr_cal_n_2976;
  wire u_ddr_cal_n_2977;
  wire u_ddr_cal_n_793;
  wire u_ddr_cal_n_794;
  wire u_ddr_cal_n_795;
  wire u_ddr_cal_n_796;
  wire u_ddr_cal_n_797;
  wire u_ddr_cal_n_798;
  wire u_ddr_cal_n_799;
  wire u_ddr_cal_n_800;
  wire u_ddr_cal_n_802;
  wire u_ddr_cal_n_803;
  wire u_ddr_cal_n_810;
  wire u_ddr_cal_n_811;
  wire u_ddr_cal_n_812;
  wire u_ddr_cal_n_819;
  wire u_ddr_cal_n_820;
  wire u_ddr_cal_n_821;
  wire u_ddr_cal_n_828;
  wire u_ddr_cal_n_829;
  wire u_ddr_cal_n_830;
  wire u_ddr_cal_n_837;
  wire u_ddr_cal_n_838;
  wire u_ddr_cal_n_839;
  wire u_ddr_cal_n_840;
  wire u_ddr_cal_n_841;
  wire u_ddr_cal_n_842;
  wire u_ddr_cal_n_843;
  wire u_ddr_cal_n_844;
  wire u_ddr_cal_n_845;
  wire u_ddr_cal_n_846;
  wire u_ddr_cal_n_847;
  wire u_ddr_cal_n_848;
  wire u_ddr_cal_n_849;
  wire u_ddr_cal_n_850;
  wire u_ddr_cal_n_851;
  wire u_ddr_cal_n_852;
  wire u_ddr_cal_n_853;
  wire u_ddr_cal_n_854;
  wire u_ddr_cal_n_855;
  wire u_ddr_cal_n_856;
  wire u_ddr_cal_n_857;
  wire u_ddr_cal_n_858;
  wire u_ddr_cal_n_859;
  wire u_ddr_cal_n_86;
  wire u_ddr_cal_n_860;
  wire u_ddr_cal_n_861;
  wire u_ddr_cal_n_862;
  wire u_ddr_cal_n_863;
  wire u_ddr_cal_n_864;
  wire u_ddr_cal_n_865;
  wire u_ddr_cal_n_866;
  wire u_ddr_cal_n_867;
  wire u_ddr_cal_n_868;
  wire u_ddr_cal_n_869;
  wire u_ddr_cal_n_87;
  wire u_ddr_cal_n_870;
  wire u_ddr_cal_n_871;
  wire u_ddr_cal_n_872;
  wire u_ddr_cal_n_873;
  wire u_ddr_cal_n_874;
  wire u_ddr_cal_n_875;
  wire u_ddr_cal_n_876;
  wire u_ddr_cal_n_877;
  wire u_ddr_cal_n_878;
  wire u_ddr_cal_n_879;
  wire u_ddr_cal_n_88;
  wire u_ddr_cal_n_880;
  wire u_ddr_cal_n_881;
  wire u_ddr_cal_n_882;
  wire u_ddr_cal_n_883;
  wire u_ddr_cal_n_884;
  wire u_ddr_cal_n_885;
  wire u_ddr_cal_n_886;
  wire u_ddr_cal_n_887;
  wire u_ddr_cal_n_888;
  wire u_ddr_cal_n_889;
  wire u_ddr_cal_n_89;
  wire u_ddr_cal_n_890;
  wire u_ddr_cal_n_891;
  wire u_ddr_cal_n_892;
  wire u_ddr_cal_n_893;
  wire u_ddr_cal_n_894;
  wire u_ddr_cal_n_895;
  wire u_ddr_cal_n_896;
  wire u_ddr_cal_n_897;
  wire u_ddr_cal_n_898;
  wire u_ddr_cal_n_899;
  wire u_ddr_cal_n_900;
  wire u_ddr_cal_n_901;
  wire u_ddr_cal_n_902;
  wire u_ddr_cal_n_903;
  wire u_ddr_cal_n_904;
  wire u_ddr_cal_n_905;
  wire u_ddr_cal_n_906;
  wire u_ddr_cal_n_907;
  wire u_ddr_cal_n_908;
  wire u_ddr_cal_n_909;
  wire u_ddr_cal_n_910;
  wire u_ddr_cal_n_911;
  wire u_ddr_cal_n_912;
  wire u_ddr_cal_n_913;
  wire u_ddr_cal_n_914;
  wire u_ddr_cal_n_915;
  wire u_ddr_cal_n_916;
  wire u_ddr_cal_n_917;
  wire u_ddr_cal_n_918;
  wire u_ddr_cal_n_919;
  wire u_ddr_cal_n_920;
  wire u_ddr_cal_n_921;
  wire u_ddr_cal_n_922;
  wire u_ddr_cal_n_923;
  wire u_ddr_cal_n_924;
  wire u_ddr_cal_n_925;
  wire u_ddr_cal_n_926;
  wire u_ddr_cal_n_927;
  wire u_ddr_cal_n_928;
  wire u_ddr_cal_n_929;
  wire u_ddr_cal_n_930;
  wire u_ddr_cal_n_931;
  wire u_ddr_cal_n_932;
  wire u_ddr_cal_n_933;
  wire u_ddr_cal_n_934;
  wire u_ddr_cal_n_935;
  wire u_ddr_cal_n_936;
  wire u_ddr_cal_n_937;
  wire u_ddr_cal_n_938;
  wire u_ddr_cal_n_939;
  wire u_ddr_cal_n_940;
  wire u_ddr_cal_n_941;
  wire u_ddr_cal_n_942;
  wire u_ddr_cal_n_943;
  wire u_ddr_cal_n_944;
  wire u_ddr_cal_n_945;
  wire u_ddr_cal_n_946;
  wire u_ddr_cal_n_947;
  wire u_ddr_cal_n_948;
  wire u_ddr_cal_n_949;
  wire u_ddr_cal_n_950;
  wire u_ddr_cal_n_951;
  wire u_ddr_cal_n_952;
  wire u_ddr_cal_n_953;
  wire u_ddr_cal_n_954;
  wire u_ddr_cal_n_955;
  wire u_ddr_cal_n_956;
  wire u_ddr_cal_n_957;
  wire u_ddr_cal_n_958;
  wire u_ddr_cal_n_959;
  wire u_ddr_cal_n_960;
  wire u_ddr_cal_n_961;
  wire u_ddr_cal_n_962;
  wire u_ddr_cal_n_963;
  wire u_ddr_cal_n_964;
  wire u_ddr_cal_n_965;
  wire u_ddr_cal_n_966;
  wire u_ddr_cal_n_967;
  wire u_ddr_cal_n_968;
  wire u_ddr_cal_n_969;
  wire u_ddr_cal_n_970;
  wire u_ddr_cal_n_971;
  wire u_ddr_cal_n_972;
  wire u_ddr_cal_n_973;
  wire u_ddr_cal_n_974;
  wire u_ddr_cal_n_975;
  wire u_ddr_cal_n_976;
  wire u_ddr_cal_n_977;
  wire u_ddr_cal_n_978;
  wire u_ddr_cal_n_979;
  wire u_ddr_cal_n_980;
  wire u_ddr_cal_n_981;
  wire u_ddr_cal_n_982;
  wire u_ddr_cal_n_983;
  wire u_ddr_cal_n_984;
  wire u_ddr_cal_n_985;
  wire u_ddr_cal_n_986;
  wire u_ddr_cal_n_987;
  wire u_ddr_cal_n_988;
  wire u_ddr_cal_n_989;
  wire u_ddr_cal_n_990;
  wire u_ddr_cal_n_991;
  wire u_ddr_cal_n_992;
  wire u_ddr_cal_n_993;
  wire u_ddr_cal_n_994;
  wire u_ddr_cal_n_995;
  wire u_ddr_cal_n_996;
  wire u_ddr_cal_n_997;
  wire u_ddr_cal_n_998;
  wire u_ddr_cal_n_999;
  wire u_ddr_mc_pi_n_10;
  wire u_ddr_mc_pi_n_11;
  wire u_ddr_mc_pi_n_12;
  wire u_ddr_mc_pi_n_13;
  wire u_ddr_mc_pi_n_14;
  wire u_ddr_mc_pi_n_15;
  wire u_ddr_mc_pi_n_1526;
  wire u_ddr_mc_pi_n_16;
  wire u_ddr_mc_pi_n_3;
  wire u_ddr_mc_pi_n_8;
  wire u_ddr_mc_pi_n_829;
  wire u_ddr_mc_pi_n_830;
  wire u_ddr_mc_pi_n_831;
  wire u_ddr_mc_pi_n_832;
  wire u_ddr_mc_pi_n_833;
  wire u_ddr_mc_pi_n_834;
  wire u_ddr_mc_pi_n_835;
  wire u_ddr_mc_pi_n_836;
  wire u_ddr_mc_pi_n_837;
  wire u_ddr_mc_pi_n_838;
  wire u_ddr_mc_pi_n_839;
  wire u_ddr_mc_pi_n_840;
  wire u_ddr_mc_pi_n_841;
  wire u_ddr_mc_pi_n_842;
  wire u_ddr_mc_pi_n_843;
  wire u_ddr_mc_pi_n_844;
  wire u_ddr_mc_pi_n_845;
  wire u_ddr_mc_pi_n_846;
  wire u_ddr_mc_pi_n_847;
  wire u_ddr_mc_pi_n_848;
  wire u_ddr_mc_pi_n_849;
  wire u_ddr_mc_pi_n_850;
  wire u_ddr_mc_pi_n_851;
  wire u_ddr_mc_pi_n_852;
  wire u_ddr_mc_pi_n_853;
  wire u_ddr_mc_pi_n_854;
  wire u_ddr_mc_pi_n_855;
  wire u_ddr_mc_pi_n_856;
  wire u_ddr_mc_pi_n_865;
  wire u_ddr_mc_pi_n_9;
  wire \u_ddr_mc_read/read_lat_shift_cal_dq_valid_nxt ;
  wire [31:1]\u_ddr_mc_read/read_lat_shift_nxt ;
  wire [9:8]\u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/dReg0_out ;
  wire [9:8]\u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/dReg0_out ;
  wire [9:8]\u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/dReg0_out ;
  wire [9:8]\u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/dReg0_out ;
  wire [9:8]\u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/dReg0_out ;
  wire [9:8]\u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/dReg0_out ;
  wire [9:8]\u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/dReg0_out ;
  wire [9:8]\u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/dReg0_out ;
  wire [2:1]\u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/wosp ;
  wire \u_ddr_mc_write/wrDataVal ;
  wire [0:0]\u_ddr_mc_write/wrQ_nxt[1]_13 ;
  wire ub_calDone;
  wire ub_initDone_reg;
  wire ub_ready_reg;
  wire underfill_done_nxt;
  wire [45:7]uppCL0;
  wire [9:0]\uppCL0_reg[47] ;
  wire [45:7]uppCL1;
  wire [9:0]\uppCL1_reg[47] ;
  wire [45:7]uppCL2;
  wire [9:0]\uppCL2_reg[47] ;
  wire [45:7]uppCL3;
  wire [7:0]\uppCL3_reg[42] ;
  wire [9:0]\uppCL3_reg[47] ;
  wire winAct;
  wire wrDataEn_pi;
  wire [0:0]\wrQ_reg[0][0] ;
  wire \wrQ_reg[0][5]_rep ;
  wire \wrQ_reg[0][5]_rep__0 ;
  wire \wrQ_reg[0][5]_rep__1 ;
  wire \wrQ_reg[0][6]_rep ;
  wire \wrQ_reg[0][6]_rep__0 ;
  wire \wrQ_reg[0][6]_rep__1 ;
  wire \wrQ_reg[0][7]_rep ;
  wire \wrQ_reg[0][7]_rep__0 ;
  wire \wrQ_reg[0][7]_rep__1 ;
  wire [3:0]\wrQ_reg[0][8] ;
  wire \wrQ_reg[0][8]_rep ;
  wire [3:0]\wrQ_reg[0][8]_rep__0 ;
  wire \wrQ_reg[0][8]_rep__0_0 ;
  wire [3:0]\wrQ_reg[0][8]_rep__1 ;
  wire \wrQ_reg[0][8]_rep__1_0 ;
  wire [3:0]\wrQ_reg[1][8] ;
  wire [4:0]\wrQ_reg[1][8]_0 ;
  wire [0:0]xsdb_wr_en_reg;

  assign cal_timer_reg_0_sn_1 = cal_timer_reg_0_sp_1;
  assign cal_timer_reg_21_sp_1 = cal_timer_reg_21_sn_1;
  assign cal_timer_reg_24_sp_1 = cal_timer_reg_24_sn_1;
  assign cal_timer_reg_25_sp_1 = cal_timer_reg_25_sn_1;
  assign cal_timer_reg_28_sp_1 = cal_timer_reg_28_sn_1;
  assign cal_timer_reg_29_sp_1 = cal_timer_reg_29_sn_1;
  FDRE calDone_gated_reg
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(calDone_i),
        .Q(calDone_gated_reg_0),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RESET_n_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_RESET_n_int[0]),
        .Q(\cal_RESET_n_reg[7]_0 [0]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RESET_n_reg[1] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_RESET_n_int[1]),
        .Q(\cal_RESET_n_reg[7]_0 [1]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RESET_n_reg[2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_RESET_n_int[2]),
        .Q(\cal_RESET_n_reg[7]_0 [2]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RESET_n_reg[3] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_RESET_n_int[3]),
        .Q(\cal_RESET_n_reg[7]_0 [3]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RESET_n_reg[4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_RESET_n_int[4]),
        .Q(\cal_RESET_n_reg[7]_0 [4]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RESET_n_reg[5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_RESET_n_int[5]),
        .Q(\cal_RESET_n_reg[7]_0 [5]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RESET_n_reg[6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_RESET_n_int[6]),
        .Q(\cal_RESET_n_reg[7]_0 [6]),
        .R(rst_r1));
  FDRE #(
    .INIT(1'b0)) 
    \cal_RESET_n_reg[7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_RESET_n_int[7]),
        .Q(\cal_RESET_n_reg[7]_0 [7]),
        .R(rst_r1));
  FDRE \cal_mcal_DMIn_n_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [0]),
        .Q(cal_mcal_DMIn_n[0]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[10] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [10]),
        .Q(cal_mcal_DMIn_n[10]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[11] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [11]),
        .Q(cal_mcal_DMIn_n[11]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[12] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [12]),
        .Q(cal_mcal_DMIn_n[12]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[13] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [13]),
        .Q(cal_mcal_DMIn_n[13]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[14] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [14]),
        .Q(cal_mcal_DMIn_n[14]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[15] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [15]),
        .Q(cal_mcal_DMIn_n[15]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[16] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [16]),
        .Q(cal_mcal_DMIn_n[16]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[17] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [17]),
        .Q(cal_mcal_DMIn_n[17]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[18] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [18]),
        .Q(cal_mcal_DMIn_n[18]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[19] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [19]),
        .Q(cal_mcal_DMIn_n[19]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[1] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [1]),
        .Q(cal_mcal_DMIn_n[1]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[20] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [20]),
        .Q(cal_mcal_DMIn_n[20]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[21] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [21]),
        .Q(cal_mcal_DMIn_n[21]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[22] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [22]),
        .Q(cal_mcal_DMIn_n[22]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[23] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [23]),
        .Q(cal_mcal_DMIn_n[23]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[24] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [24]),
        .Q(cal_mcal_DMIn_n[24]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[25] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [25]),
        .Q(cal_mcal_DMIn_n[25]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[26] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [26]),
        .Q(cal_mcal_DMIn_n[26]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[27] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [27]),
        .Q(cal_mcal_DMIn_n[27]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[28] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [28]),
        .Q(cal_mcal_DMIn_n[28]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[29] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [29]),
        .Q(cal_mcal_DMIn_n[29]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [2]),
        .Q(cal_mcal_DMIn_n[2]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[30] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [30]),
        .Q(cal_mcal_DMIn_n[30]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[31] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [31]),
        .Q(cal_mcal_DMIn_n[31]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[32] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [32]),
        .Q(cal_mcal_DMIn_n[32]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[33] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [33]),
        .Q(cal_mcal_DMIn_n[33]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[34] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [34]),
        .Q(cal_mcal_DMIn_n[34]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[35] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [35]),
        .Q(cal_mcal_DMIn_n[35]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[36] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [36]),
        .Q(cal_mcal_DMIn_n[36]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[37] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [37]),
        .Q(cal_mcal_DMIn_n[37]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[38] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [38]),
        .Q(cal_mcal_DMIn_n[38]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[39] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [39]),
        .Q(cal_mcal_DMIn_n[39]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[3] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [3]),
        .Q(cal_mcal_DMIn_n[3]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[40] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [40]),
        .Q(cal_mcal_DMIn_n[40]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[41] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [41]),
        .Q(cal_mcal_DMIn_n[41]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[42] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [42]),
        .Q(cal_mcal_DMIn_n[42]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[43] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [43]),
        .Q(cal_mcal_DMIn_n[43]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[44] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [44]),
        .Q(cal_mcal_DMIn_n[44]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[45] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [45]),
        .Q(cal_mcal_DMIn_n[45]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[46] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [46]),
        .Q(cal_mcal_DMIn_n[46]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[47] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [47]),
        .Q(cal_mcal_DMIn_n[47]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[48] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [48]),
        .Q(cal_mcal_DMIn_n[48]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[49] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [49]),
        .Q(cal_mcal_DMIn_n[49]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [4]),
        .Q(cal_mcal_DMIn_n[4]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[50] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [50]),
        .Q(cal_mcal_DMIn_n[50]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[51] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [51]),
        .Q(cal_mcal_DMIn_n[51]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[52] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [52]),
        .Q(cal_mcal_DMIn_n[52]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[53] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [53]),
        .Q(cal_mcal_DMIn_n[53]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[54] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [54]),
        .Q(cal_mcal_DMIn_n[54]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[55] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [55]),
        .Q(cal_mcal_DMIn_n[55]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[56] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [56]),
        .Q(cal_mcal_DMIn_n[56]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[57] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [57]),
        .Q(cal_mcal_DMIn_n[57]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[58] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [58]),
        .Q(cal_mcal_DMIn_n[58]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[59] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [59]),
        .Q(cal_mcal_DMIn_n[59]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [5]),
        .Q(cal_mcal_DMIn_n[5]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[60] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [60]),
        .Q(cal_mcal_DMIn_n[60]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[61] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [61]),
        .Q(cal_mcal_DMIn_n[61]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[62] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [62]),
        .Q(cal_mcal_DMIn_n[62]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[63] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [63]),
        .Q(cal_mcal_DMIn_n[63]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [6]),
        .Q(cal_mcal_DMIn_n[6]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [7]),
        .Q(cal_mcal_DMIn_n[7]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[8] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [8]),
        .Q(cal_mcal_DMIn_n[8]),
        .R(1'b0));
  FDRE \cal_mcal_DMIn_n_reg[9] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\cal_mcal_DMIn_n_reg[63]_0 [9]),
        .Q(cal_mcal_DMIn_n[9]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [0]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[100] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [100]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[101] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [101]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[102] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [102]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[103] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [103]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[10] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [10]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[11] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [11]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[12] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [12]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[13] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [13]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[14] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [14]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[15] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [15]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[16] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [16]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[17] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [17]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[18] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [18]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[19] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [19]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[1] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [1]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[20] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [20]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[21] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [21]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[22] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [22]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[23] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [23]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[24] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [24]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[25] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [25]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[26] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [26]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[27] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [27]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[28] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [28]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[29] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [29]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [2]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[30] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [30]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[31] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [31]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[32] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [32]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[33] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [33]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[34] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [34]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[35] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [35]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[36] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [36]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[37] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [37]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[38] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [38]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[39] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [39]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[3] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [3]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[40] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [40]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[41] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [41]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[42] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [42]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[43] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [43]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[44] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [44]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[45] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [45]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[46] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [46]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[47] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [47]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[48] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [48]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[49] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [49]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [4]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[50] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [50]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[51] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [51]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[52] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [52]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[53] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [53]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[54] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [54]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[55] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [55]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[56] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [56]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[57] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [57]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[58] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [58]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[59] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [59]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [5]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[60] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [60]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[61] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [61]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[62] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [62]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[63] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [63]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[64] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [64]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[65] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [65]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[66] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [66]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[67] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [67]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[68] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [68]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[69] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [69]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [6]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[70] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [70]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[71] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [71]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[72] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [72]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[73] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [73]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[74] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [74]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[75] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [75]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[76] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [76]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[77] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [77]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[78] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [78]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[79] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [79]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [7]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[80] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [80]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[81] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [81]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[82] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [82]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[83] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [83]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[84] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [84]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[85] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [85]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[86] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [86]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[87] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [87]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[88] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [88]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[89] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [89]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[8] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [8]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[90] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [90]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[91] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [91]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[92] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [92]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[93] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [93]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[94] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [94]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[95] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [95]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[96] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [96]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[97] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [97]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[98] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [98]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[99] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [99]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \ch1_mcal_clb2phy_fifo_rden_reg[9] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_clb2phy_fifo_rden),
        .Q(\ch1_mcal_clb2phy_fifo_rden_reg[103]_0 [9]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h6)) 
    io_addr_strobe_i_1
       (.I0(io_addr_strobe_lvl_r2),
        .I1(io_addr_strobe_lvl_r1),
        .O(io_addr_strobe0));
  FDRE io_addr_strobe_lvl_r1_reg
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(io_addr_strobe_lvl_r1_reg_0),
        .Q(io_addr_strobe_lvl_r1),
        .R(1'b0));
  FDRE io_addr_strobe_lvl_r2_reg
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(io_addr_strobe_lvl_r1),
        .Q(io_addr_strobe_lvl_r2),
        .R(1'b0));
  FDRE io_addr_strobe_reg
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(io_addr_strobe0),
        .Q(io_addr_strobe),
        .R(1'b0));
  FDRE \mc_ADR7_reg[10] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mc_ADR7_reg[16]_0 [0]),
        .Q(mc_ADR7[10]),
        .R(1'b0));
  FDRE \mc_ADR7_reg[13] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mc_ADR7_reg[16]_0 [1]),
        .Q(mc_ADR7[13]),
        .R(1'b0));
  FDRE \mc_ADR7_reg[14] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mc_ADR7_reg[16]_0 [2]),
        .Q(mc_ADR7[14]),
        .R(1'b0));
  FDRE \mc_ADR7_reg[15] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mc_ADR7_reg[16]_0 [3]),
        .Q(mc_ADR7[15]),
        .R(1'b0));
  FDRE \mc_ADR7_reg[16] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mc_ADR7_reg[16]_0 [4]),
        .Q(mc_ADR7[16]),
        .R(1'b0));
  FDRE \mc_BA7_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_BA[2]),
        .Q(p_1_in__0[0]),
        .R(1'b0));
  FDRE \mc_BA7_reg[1] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_BA[6]),
        .Q(p_1_in__0[8]),
        .R(1'b0));
  FDRE \mc_BG7_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_BG[2]),
        .Q(p_1_in),
        .R(1'b0));
  FDRE \mc_CKE7_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_CKE[1]),
        .Q(mc_CKE7),
        .R(1'b0));
  FDRE \mc_CS_n7_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_CS_n),
        .Q(mc_CS_n7),
        .R(1'b0));
  FDRE \mc_ODT7_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_ODT[1]),
        .Q(mc_ODT7),
        .R(1'b0));
  FDSE \mcal_ACT_n_dly_reg[0][0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_ACT_n[0]),
        .Q(mcal_ACT_n[0]),
        .S(calDone));
  FDSE \mcal_ACT_n_dly_reg[0][1] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_ACT_n[1]),
        .Q(mcal_ACT_n[1]),
        .S(calDone));
  FDSE \mcal_ACT_n_dly_reg[0][2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_ACT_n[2]),
        .Q(mcal_ACT_n[2]),
        .S(calDone));
  FDRE \mcal_ACT_n_dly_reg[0][3] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(mcal_ACT_n[3]),
        .R(1'b0));
  FDRE \mcal_ACT_n_dly_reg[0][4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(p_0_in__0[4]),
        .Q(mcal_ACT_n[4]),
        .R(1'b0));
  FDSE \mcal_ACT_n_dly_reg[0][5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_ACT_n[5]),
        .Q(mcal_ACT_n[5]),
        .S(calDone));
  FDSE \mcal_ACT_n_dly_reg[0][6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_ACT_n[6]),
        .Q(mcal_ACT_n[6]),
        .S(calDone));
  FDSE \mcal_ACT_n_dly_reg[0][7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_ACT_n[7]),
        .Q(mcal_ACT_n[7]),
        .S(calDone));
  FDRE \mcal_ADR_dly_reg[0][0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_202),
        .Q(mcal_ADR[0]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][100] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_144),
        .Q(mcal_ADR[58]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][102] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_143),
        .Q(mcal_ADR[59]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][103] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_142),
        .Q(mcal_ADR[60]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][104] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_141),
        .Q(mcal_ADR[61]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][108] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_140),
        .Q(mcal_ADR[62]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][110] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_139),
        .Q(mcal_ADR[63]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][111] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_138),
        .Q(mcal_ADR[64]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][112] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_137),
        .Q(mcal_ADR[65]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][113] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_ADR_dly_reg[0][126]_0 [0]),
        .Q(mcal_ADR[66]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][114] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_ADR_dly_reg[0][126]_0 [1]),
        .Q(mcal_ADR[67]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][115] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_136),
        .Q(mcal_ADR[68]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][116] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_135),
        .Q(mcal_ADR[69]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][117] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_ADR_dly_reg[0][126]_0 [2]),
        .Q(mcal_ADR[70]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][118] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_ADR_dly_reg[0][126]_0 [3]),
        .Q(mcal_ADR[71]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][119] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_134),
        .Q(mcal_ADR[72]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][120] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_133),
        .Q(mcal_ADR[73]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][121] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_ADR_dly_reg[0][126]_0 [4]),
        .Q(mcal_ADR[74]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][122] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_ADR_dly_reg[0][126]_0 [5]),
        .Q(mcal_ADR[75]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][123] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_132),
        .Q(mcal_ADR[76]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][124] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_131),
        .Q(mcal_ADR[77]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][125] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_ADR_dly_reg[0][126]_0 [6]),
        .Q(mcal_ADR[78]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][126] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_ADR_dly_reg[0][126]_0 [7]),
        .Q(mcal_ADR[79]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][127] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_130),
        .Q(mcal_ADR[80]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][128] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_129),
        .Q(mcal_ADR[81]),
        .R(1'b0));
  FDSE \mcal_ADR_dly_reg[0][129] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_86),
        .Q(mcal_ADR[82]),
        .S(calDone));
  FDRE \mcal_ADR_dly_reg[0][12] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_196),
        .Q(mcal_ADR[6]),
        .R(1'b0));
  FDSE \mcal_ADR_dly_reg[0][130] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_87),
        .Q(mcal_ADR[83]),
        .S(calDone));
  FDRE \mcal_ADR_dly_reg[0][131] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_128),
        .Q(mcal_ADR[84]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][132] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_127),
        .Q(mcal_ADR[85]),
        .R(1'b0));
  FDSE \mcal_ADR_dly_reg[0][133] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_88),
        .Q(mcal_ADR[86]),
        .S(calDone));
  FDSE \mcal_ADR_dly_reg[0][134] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_89),
        .Q(mcal_ADR[87]),
        .S(calDone));
  FDRE \mcal_ADR_dly_reg[0][135] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_126),
        .Q(mcal_ADR[88]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][14] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_195),
        .Q(mcal_ADR[7]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][15] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_194),
        .Q(mcal_ADR[8]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][16] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_193),
        .Q(mcal_ADR[9]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][20] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_192),
        .Q(mcal_ADR[10]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][22] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_191),
        .Q(mcal_ADR[11]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][23] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_190),
        .Q(mcal_ADR[12]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][24] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_189),
        .Q(mcal_ADR[13]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][26] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_188),
        .Q(mcal_ADR[14]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][28] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_187),
        .Q(mcal_ADR[15]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_201),
        .Q(mcal_ADR[1]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][30] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_186),
        .Q(mcal_ADR[16]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][31] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_185),
        .Q(mcal_ADR[17]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][32] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_184),
        .Q(mcal_ADR[18]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][34] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_183),
        .Q(mcal_ADR[19]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][36] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_182),
        .Q(mcal_ADR[20]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][38] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_181),
        .Q(mcal_ADR[21]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][39] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_180),
        .Q(mcal_ADR[22]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][40] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_179),
        .Q(mcal_ADR[23]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][42] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_178),
        .Q(mcal_ADR[24]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][44] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_177),
        .Q(mcal_ADR[25]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][46] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_176),
        .Q(mcal_ADR[26]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][47] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_175),
        .Q(mcal_ADR[27]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][48] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_174),
        .Q(mcal_ADR[28]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_200),
        .Q(mcal_ADR[2]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][50] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_173),
        .Q(mcal_ADR[29]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][52] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_172),
        .Q(mcal_ADR[30]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][54] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_171),
        .Q(mcal_ADR[31]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][55] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_170),
        .Q(mcal_ADR[32]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][56] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_169),
        .Q(mcal_ADR[33]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][58] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_168),
        .Q(mcal_ADR[34]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][60] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_167),
        .Q(mcal_ADR[35]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][62] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_166),
        .Q(mcal_ADR[36]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][63] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_165),
        .Q(mcal_ADR[37]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][64] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_164),
        .Q(mcal_ADR[38]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][66] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_163),
        .Q(mcal_ADR[39]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][68] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_162),
        .Q(mcal_ADR[40]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_199),
        .Q(mcal_ADR[3]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][70] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_161),
        .Q(mcal_ADR[41]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][71] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_160),
        .Q(mcal_ADR[42]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][72] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_159),
        .Q(mcal_ADR[43]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][74] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_158),
        .Q(mcal_ADR[44]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][76] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_157),
        .Q(mcal_ADR[45]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][78] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_156),
        .Q(mcal_ADR[46]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][79] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_155),
        .Q(mcal_ADR[47]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_198),
        .Q(mcal_ADR[4]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][80] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_154),
        .Q(mcal_ADR[48]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][82] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_153),
        .Q(mcal_ADR[49]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][84] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_152),
        .Q(mcal_ADR[50]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][86] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_151),
        .Q(mcal_ADR[51]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][87] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_150),
        .Q(mcal_ADR[52]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][88] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_149),
        .Q(mcal_ADR[53]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][8] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_197),
        .Q(mcal_ADR[5]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][92] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_148),
        .Q(mcal_ADR[54]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][94] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_147),
        .Q(mcal_ADR[55]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][95] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_146),
        .Q(mcal_ADR[56]),
        .R(1'b0));
  FDRE \mcal_ADR_dly_reg[0][96] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_145),
        .Q(mcal_ADR[57]),
        .R(1'b0));
  FDRE \mcal_BA_dly_reg[0][0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_108),
        .Q(\mcal_BA_dly_reg[0][15]_0 [0]),
        .R(1'b0));
  FDRE \mcal_BA_dly_reg[0][10] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_103),
        .Q(\mcal_BA_dly_reg[0][15]_0 [6]),
        .R(1'b0));
  FDRE \mcal_BA_dly_reg[0][12] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_102),
        .Q(\mcal_BA_dly_reg[0][15]_0 [7]),
        .R(1'b0));
  FDRE \mcal_BA_dly_reg[0][14] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_101),
        .Q(\mcal_BA_dly_reg[0][15]_0 [8]),
        .R(1'b0));
  FDRE \mcal_BA_dly_reg[0][15] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_100),
        .Q(\mcal_BA_dly_reg[0][15]_0 [9]),
        .R(1'b0));
  FDRE \mcal_BA_dly_reg[0][2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_107),
        .Q(\mcal_BA_dly_reg[0][15]_0 [1]),
        .R(1'b0));
  FDRE \mcal_BA_dly_reg[0][4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_BA_dly_reg[0][4]_0 ),
        .Q(\mcal_BA_dly_reg[0][15]_0 [2]),
        .R(1'b0));
  FDRE \mcal_BA_dly_reg[0][6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_106),
        .Q(\mcal_BA_dly_reg[0][15]_0 [3]),
        .R(1'b0));
  FDRE \mcal_BA_dly_reg[0][7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_105),
        .Q(\mcal_BA_dly_reg[0][15]_0 [4]),
        .R(1'b0));
  FDRE \mcal_BA_dly_reg[0][8] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_104),
        .Q(\mcal_BA_dly_reg[0][15]_0 [5]),
        .R(1'b0));
  FDRE \mcal_BG_dly_reg[0][0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_207),
        .Q(\mcal_BG_dly_reg[0][7]_0 [0]),
        .R(1'b0));
  FDRE \mcal_BG_dly_reg[0][2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_206),
        .Q(\mcal_BG_dly_reg[0][7]_0 [1]),
        .R(1'b0));
  FDRE \mcal_BG_dly_reg[0][4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_BG_dly_reg[0][4]_0 ),
        .Q(\mcal_BG_dly_reg[0][7]_0 [2]),
        .R(1'b0));
  FDRE \mcal_BG_dly_reg[0][6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_205),
        .Q(\mcal_BG_dly_reg[0][7]_0 [3]),
        .R(1'b0));
  FDRE \mcal_BG_dly_reg[0][7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_204),
        .Q(\mcal_BG_dly_reg[0][7]_0 [4]),
        .R(1'b0));
  FDRE \mcal_CKE_dly_reg[0][0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_111),
        .Q(\mcal_CKE_dly_reg[0][7]_0 [0]),
        .R(1'b0));
  FDRE \mcal_CKE_dly_reg[0][6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_110),
        .Q(\mcal_CKE_dly_reg[0][7]_0 [1]),
        .R(1'b0));
  FDRE \mcal_CKE_dly_reg[0][7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_109),
        .Q(\mcal_CKE_dly_reg[0][7]_0 [2]),
        .R(1'b0));
  FDRE \mcal_CS_n_dly_reg[0][0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_120),
        .Q(\mcal_CS_n_dly_reg[0][7]_0 [0]),
        .R(1'b0));
  FDRE \mcal_CS_n_dly_reg[0][1] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_CS_n_dly_reg[0][6]_0 [0]),
        .Q(\mcal_CS_n_dly_reg[0][7]_0 [1]),
        .R(1'b0));
  FDRE \mcal_CS_n_dly_reg[0][2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_CS_n_dly_reg[0][6]_0 [1]),
        .Q(\mcal_CS_n_dly_reg[0][7]_0 [2]),
        .R(1'b0));
  FDRE \mcal_CS_n_dly_reg[0][3] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_119),
        .Q(\mcal_CS_n_dly_reg[0][7]_0 [3]),
        .R(1'b0));
  FDRE \mcal_CS_n_dly_reg[0][4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_118),
        .Q(\mcal_CS_n_dly_reg[0][7]_0 [4]),
        .R(1'b0));
  FDRE \mcal_CS_n_dly_reg[0][5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_CS_n_dly_reg[0][6]_0 [2]),
        .Q(\mcal_CS_n_dly_reg[0][7]_0 [5]),
        .R(1'b0));
  FDRE \mcal_CS_n_dly_reg[0][6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_CS_n_dly_reg[0][6]_0 [3]),
        .Q(\mcal_CS_n_dly_reg[0][7]_0 [6]),
        .R(1'b0));
  FDRE \mcal_CS_n_dly_reg[0][7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_117),
        .Q(\mcal_CS_n_dly_reg[0][7]_0 [7]),
        .R(1'b0));
  FDRE \mcal_ODT_dly_reg[0][0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_114),
        .Q(\mcal_ODT_dly_reg[0][7]_0 [0]),
        .R(1'b0));
  FDRE \mcal_ODT_dly_reg[0][2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_113),
        .Q(\mcal_ODT_dly_reg[0][7]_0 [1]),
        .R(1'b0));
  FDRE \mcal_ODT_dly_reg[0][4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_112),
        .Q(\mcal_ODT_dly_reg[0][7]_0 [2]),
        .R(1'b0));
  FDRE \mcal_ODT_dly_reg[0][6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_ODT_dly_reg[0][7]_1 [0]),
        .Q(\mcal_ODT_dly_reg[0][7]_0 [3]),
        .R(1'b0));
  FDRE \mcal_ODT_dly_reg[0][7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\mcal_ODT_dly_reg[0][7]_1 [1]),
        .Q(\mcal_ODT_dly_reg[0][7]_0 [4]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h9669699669969669)) 
    \mcal_PAR_dly[0][0]_i_4 
       (.I0(p_1_in__0[8]),
        .I1(mc_ADR7[16]),
        .I2(mc_ADR7[14]),
        .I3(mc_ADR7[15]),
        .I4(mc_ADR7[13]),
        .I5(mc_ADR7[10]),
        .O(\mcal_PAR_dly[0][0]_i_4_n_0 ));
  FDRE \mcal_PAR_dly_reg[0][0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_216),
        .Q(\mcal_PAR_dly_reg[0][7]_0 [0]),
        .R(1'b0));
  FDRE \mcal_PAR_dly_reg[0][1] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_215),
        .Q(\mcal_PAR_dly_reg[0][7]_0 [1]),
        .R(1'b0));
  FDRE \mcal_PAR_dly_reg[0][2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_214),
        .Q(\mcal_PAR_dly_reg[0][7]_0 [2]),
        .R(1'b0));
  FDRE \mcal_PAR_dly_reg[0][3] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_213),
        .Q(\mcal_PAR_dly_reg[0][7]_0 [3]),
        .R(1'b0));
  FDRE \mcal_PAR_dly_reg[0][4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_212),
        .Q(\mcal_PAR_dly_reg[0][7]_0 [4]),
        .R(1'b0));
  FDRE \mcal_PAR_dly_reg[0][5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_211),
        .Q(\mcal_PAR_dly_reg[0][7]_0 [5]),
        .R(1'b0));
  FDRE \mcal_PAR_dly_reg[0][6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_210),
        .Q(\mcal_PAR_dly_reg[0][7]_0 [6]),
        .R(1'b0));
  FDRE \mcal_PAR_dly_reg[0][7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(u_ddr_cal_n_209),
        .Q(\mcal_PAR_dly_reg[0][7]_0 [7]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [0]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[100] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [100]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[101] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [101]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[102] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [102]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[103] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [103]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[10] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [10]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[11] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [11]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[12] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [12]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[13] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [13]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[14] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [14]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[15] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [15]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[16] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [16]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[17] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [17]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[18] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [18]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[19] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [19]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[1] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [1]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[20] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [20]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[21] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [21]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[22] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [22]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[23] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [23]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[24] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [24]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[25] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [25]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[26] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [26]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[27] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [27]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[28] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [28]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[29] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [29]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [2]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[30] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [30]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[31] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [31]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[32] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [32]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[33] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [33]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[34] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [34]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[35] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [35]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[36] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [36]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[37] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [37]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[38] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [38]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[39] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [39]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[3] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [3]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[40] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [40]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[41] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [41]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[42] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [42]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[43] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [43]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[44] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [44]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[45] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [45]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[46] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [46]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[47] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [47]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[48] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [48]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[49] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [49]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [4]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[50] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [50]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[51] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [51]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[52] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [52]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[53] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [53]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[54] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [54]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[55] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [55]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[56] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [56]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[57] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [57]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[58] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [58]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[59] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [59]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [5]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[60] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [60]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[61] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [61]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[62] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [62]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[63] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [63]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[64] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [64]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[65] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [65]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[66] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [66]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[67] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [67]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[68] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [68]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[69] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [69]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [6]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[70] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [70]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[71] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [71]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[72] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [72]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[73] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [73]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[74] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [74]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[75] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [75]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[76] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [76]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[77] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [77]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[78] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [78]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[79] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [79]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [7]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[80] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [80]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[81] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [81]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[82] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [82]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[83] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [83]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[84] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [84]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[85] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [85]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[86] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [86]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[87] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [87]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[88] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [88]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[89] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [89]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[8] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [8]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[90] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [90]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[91] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [91]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[92] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [92]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[93] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [93]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[94] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [94]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[95] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [95]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[96] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [96]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[97] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [97]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[98] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [98]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[99] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [99]),
        .S(cal_clb2phy_fifo_rden));
  (* KEEP = "yes" *) 
  FDSE \mcal_clb2phy_fifo_rden_reg[9] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mc_clb2phy_fifo_rden_nxt),
        .Q(\mcal_clb2phy_fifo_rden_reg[103]_0 [9]),
        .S(cal_clb2phy_fifo_rden));
  SRL16E \phy_rden_and_stg_reg[2]_srl3 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\dReg_reg[10] ),
        .D(phy_rden_and),
        .Q(\phy_rden_and_stg_reg[2]_srl3_n_0 ));
  FDRE \phy_rden_and_stg_reg[3] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\phy_rden_and_stg_reg[2]_srl3_n_0 ),
        .Q(phy_rden_and_stg_gt[3]),
        .R(1'b0));
  FDRE \phy_rden_and_stg_reg[4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(phy_rden_and_stg_gt[3]),
        .Q(phy_rden_and_stg_gt[4]),
        .R(1'b0));
  FDRE \phy_rden_and_stg_reg[5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(phy_rden_and_stg_gt[4]),
        .Q(phy_rden_and_stg_gt[5]),
        .R(1'b0));
  FDRE \phy_rden_and_stg_reg[6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(phy_rden_and_stg_gt[5]),
        .Q(phy_rden_and_stg_gt[6]),
        .R(1'b0));
  FDRE \phy_rden_and_stg_reg[7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(phy_rden_and_stg_gt[6]),
        .Q(phy_rden_and_stg_gt[7]),
        .R(1'b0));
  SRL16E \phy_rden_or_stg_reg[2]_srl3 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\dReg_reg[10] ),
        .D(phy_rden_or),
        .Q(\phy_rden_or_stg_reg[2]_srl3_n_0 ));
  FDRE \phy_rden_or_stg_reg[3] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\phy_rden_or_stg_reg[2]_srl3_n_0 ),
        .Q(phy_rden_or_stg_gt[3]),
        .R(1'b0));
  FDRE \phy_rden_or_stg_reg[4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(phy_rden_or_stg_gt[3]),
        .Q(phy_rden_or_stg_gt[4]),
        .R(1'b0));
  FDRE \phy_rden_or_stg_reg[5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(phy_rden_or_stg_gt[4]),
        .Q(phy_rden_or_stg_gt[5]),
        .R(1'b0));
  FDRE \phy_rden_or_stg_reg[6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(phy_rden_or_stg_gt[5]),
        .Q(phy_rden_or_stg_gt[6]),
        .R(1'b0));
  FDRE \phy_rden_or_stg_reg[7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(phy_rden_or_stg_gt[6]),
        .Q(phy_rden_or_stg_gt[7]),
        .R(1'b0));
  FDRE \rdData_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[0]),
        .Q(D[0]),
        .R(1'b0));
  FDRE \rdData_reg[100] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[100]),
        .Q(D[100]),
        .R(1'b0));
  FDRE \rdData_reg[101] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[108]),
        .Q(D[108]),
        .R(1'b0));
  FDRE \rdData_reg[102] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[116]),
        .Q(D[116]),
        .R(1'b0));
  FDRE \rdData_reg[103] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[124]),
        .Q(D[124]),
        .R(1'b0));
  FDRE \rdData_reg[104] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[69]),
        .Q(D[69]),
        .R(1'b0));
  FDRE \rdData_reg[105] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[77]),
        .Q(D[77]),
        .R(1'b0));
  FDRE \rdData_reg[106] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[85]),
        .Q(D[85]),
        .R(1'b0));
  FDRE \rdData_reg[107] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[93]),
        .Q(D[93]),
        .R(1'b0));
  FDRE \rdData_reg[108] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[101]),
        .Q(D[101]),
        .R(1'b0));
  FDRE \rdData_reg[109] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[109]),
        .Q(D[109]),
        .R(1'b0));
  FDRE \rdData_reg[10] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[17]),
        .Q(D[17]),
        .R(1'b0));
  FDRE \rdData_reg[110] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[117]),
        .Q(D[117]),
        .R(1'b0));
  FDRE \rdData_reg[111] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[125]),
        .Q(D[125]),
        .R(1'b0));
  FDRE \rdData_reg[112] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[70]),
        .Q(D[70]),
        .R(1'b0));
  FDRE \rdData_reg[113] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[78]),
        .Q(D[78]),
        .R(1'b0));
  FDRE \rdData_reg[114] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[86]),
        .Q(D[86]),
        .R(1'b0));
  FDRE \rdData_reg[115] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[94]),
        .Q(D[94]),
        .R(1'b0));
  FDRE \rdData_reg[116] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[102]),
        .Q(D[102]),
        .R(1'b0));
  FDRE \rdData_reg[117] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[110]),
        .Q(D[110]),
        .R(1'b0));
  FDRE \rdData_reg[118] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[118]),
        .Q(D[118]),
        .R(1'b0));
  FDRE \rdData_reg[119] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[126]),
        .Q(D[126]),
        .R(1'b0));
  FDRE \rdData_reg[11] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[25]),
        .Q(D[25]),
        .R(1'b0));
  FDRE \rdData_reg[120] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[71]),
        .Q(D[71]),
        .R(1'b0));
  FDRE \rdData_reg[121] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[79]),
        .Q(D[79]),
        .R(1'b0));
  FDRE \rdData_reg[122] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[87]),
        .Q(D[87]),
        .R(1'b0));
  FDRE \rdData_reg[123] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[95]),
        .Q(D[95]),
        .R(1'b0));
  FDRE \rdData_reg[124] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[103]),
        .Q(D[103]),
        .R(1'b0));
  FDRE \rdData_reg[125] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[111]),
        .Q(D[111]),
        .R(1'b0));
  FDRE \rdData_reg[126] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[119]),
        .Q(D[119]),
        .R(1'b0));
  FDRE \rdData_reg[127] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[127]),
        .Q(D[127]),
        .R(1'b0));
  FDRE \rdData_reg[128] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[128]),
        .Q(D[128]),
        .R(1'b0));
  FDRE \rdData_reg[129] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[136]),
        .Q(D[136]),
        .R(1'b0));
  FDRE \rdData_reg[12] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[33]),
        .Q(D[33]),
        .R(1'b0));
  FDRE \rdData_reg[130] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[144]),
        .Q(D[144]),
        .R(1'b0));
  FDRE \rdData_reg[131] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[152]),
        .Q(D[152]),
        .R(1'b0));
  FDRE \rdData_reg[132] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[160]),
        .Q(D[160]),
        .R(1'b0));
  FDRE \rdData_reg[133] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[168]),
        .Q(D[168]),
        .R(1'b0));
  FDRE \rdData_reg[134] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[176]),
        .Q(D[176]),
        .R(1'b0));
  FDRE \rdData_reg[135] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[184]),
        .Q(D[184]),
        .R(1'b0));
  FDRE \rdData_reg[136] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[129]),
        .Q(D[129]),
        .R(1'b0));
  FDRE \rdData_reg[137] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[137]),
        .Q(D[137]),
        .R(1'b0));
  FDRE \rdData_reg[138] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[145]),
        .Q(D[145]),
        .R(1'b0));
  FDRE \rdData_reg[139] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[153]),
        .Q(D[153]),
        .R(1'b0));
  FDRE \rdData_reg[13] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[41]),
        .Q(D[41]),
        .R(1'b0));
  FDRE \rdData_reg[140] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[161]),
        .Q(D[161]),
        .R(1'b0));
  FDRE \rdData_reg[141] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[169]),
        .Q(D[169]),
        .R(1'b0));
  FDRE \rdData_reg[142] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[177]),
        .Q(D[177]),
        .R(1'b0));
  FDRE \rdData_reg[143] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[185]),
        .Q(D[185]),
        .R(1'b0));
  FDRE \rdData_reg[144] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[130]),
        .Q(D[130]),
        .R(1'b0));
  FDRE \rdData_reg[145] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[138]),
        .Q(D[138]),
        .R(1'b0));
  FDRE \rdData_reg[146] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[146]),
        .Q(D[146]),
        .R(1'b0));
  FDRE \rdData_reg[147] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[154]),
        .Q(D[154]),
        .R(1'b0));
  FDRE \rdData_reg[148] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[162]),
        .Q(D[162]),
        .R(1'b0));
  FDRE \rdData_reg[149] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[170]),
        .Q(D[170]),
        .R(1'b0));
  FDRE \rdData_reg[14] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[49]),
        .Q(D[49]),
        .R(1'b0));
  FDRE \rdData_reg[150] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[178]),
        .Q(D[178]),
        .R(1'b0));
  FDRE \rdData_reg[151] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[186]),
        .Q(D[186]),
        .R(1'b0));
  FDRE \rdData_reg[152] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[131]),
        .Q(D[131]),
        .R(1'b0));
  FDRE \rdData_reg[153] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[139]),
        .Q(D[139]),
        .R(1'b0));
  FDRE \rdData_reg[154] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[147]),
        .Q(D[147]),
        .R(1'b0));
  FDRE \rdData_reg[155] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[155]),
        .Q(D[155]),
        .R(1'b0));
  FDRE \rdData_reg[156] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[163]),
        .Q(D[163]),
        .R(1'b0));
  FDRE \rdData_reg[157] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[171]),
        .Q(D[171]),
        .R(1'b0));
  FDRE \rdData_reg[158] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[179]),
        .Q(D[179]),
        .R(1'b0));
  FDRE \rdData_reg[159] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[187]),
        .Q(D[187]),
        .R(1'b0));
  FDRE \rdData_reg[15] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[57]),
        .Q(D[57]),
        .R(1'b0));
  FDRE \rdData_reg[160] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[132]),
        .Q(D[132]),
        .R(1'b0));
  FDRE \rdData_reg[161] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[140]),
        .Q(D[140]),
        .R(1'b0));
  FDRE \rdData_reg[162] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[148]),
        .Q(D[148]),
        .R(1'b0));
  FDRE \rdData_reg[163] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[156]),
        .Q(D[156]),
        .R(1'b0));
  FDRE \rdData_reg[164] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[164]),
        .Q(D[164]),
        .R(1'b0));
  FDRE \rdData_reg[165] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[172]),
        .Q(D[172]),
        .R(1'b0));
  FDRE \rdData_reg[166] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[180]),
        .Q(D[180]),
        .R(1'b0));
  FDRE \rdData_reg[167] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[188]),
        .Q(D[188]),
        .R(1'b0));
  FDRE \rdData_reg[168] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[133]),
        .Q(D[133]),
        .R(1'b0));
  FDRE \rdData_reg[169] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[141]),
        .Q(D[141]),
        .R(1'b0));
  FDRE \rdData_reg[16] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[2]),
        .Q(D[2]),
        .R(1'b0));
  FDRE \rdData_reg[170] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[149]),
        .Q(D[149]),
        .R(1'b0));
  FDRE \rdData_reg[171] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[157]),
        .Q(D[157]),
        .R(1'b0));
  FDRE \rdData_reg[172] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[165]),
        .Q(D[165]),
        .R(1'b0));
  FDRE \rdData_reg[173] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[173]),
        .Q(D[173]),
        .R(1'b0));
  FDRE \rdData_reg[174] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[181]),
        .Q(D[181]),
        .R(1'b0));
  FDRE \rdData_reg[175] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[189]),
        .Q(D[189]),
        .R(1'b0));
  FDRE \rdData_reg[176] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[134]),
        .Q(D[134]),
        .R(1'b0));
  FDRE \rdData_reg[177] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[142]),
        .Q(D[142]),
        .R(1'b0));
  FDRE \rdData_reg[178] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[150]),
        .Q(D[150]),
        .R(1'b0));
  FDRE \rdData_reg[179] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[158]),
        .Q(D[158]),
        .R(1'b0));
  FDRE \rdData_reg[17] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[10]),
        .Q(D[10]),
        .R(1'b0));
  FDRE \rdData_reg[180] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[166]),
        .Q(D[166]),
        .R(1'b0));
  FDRE \rdData_reg[181] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[174]),
        .Q(D[174]),
        .R(1'b0));
  FDRE \rdData_reg[182] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[182]),
        .Q(D[182]),
        .R(1'b0));
  FDRE \rdData_reg[183] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[190]),
        .Q(D[190]),
        .R(1'b0));
  FDRE \rdData_reg[184] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[135]),
        .Q(D[135]),
        .R(1'b0));
  FDRE \rdData_reg[185] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[143]),
        .Q(D[143]),
        .R(1'b0));
  FDRE \rdData_reg[186] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[151]),
        .Q(D[151]),
        .R(1'b0));
  FDRE \rdData_reg[187] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[159]),
        .Q(D[159]),
        .R(1'b0));
  FDRE \rdData_reg[188] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[167]),
        .Q(D[167]),
        .R(1'b0));
  FDRE \rdData_reg[189] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[175]),
        .Q(D[175]),
        .R(1'b0));
  FDRE \rdData_reg[18] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[18]),
        .Q(D[18]),
        .R(1'b0));
  FDRE \rdData_reg[190] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[183]),
        .Q(D[183]),
        .R(1'b0));
  FDRE \rdData_reg[191] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[191]),
        .Q(D[191]),
        .R(1'b0));
  FDRE \rdData_reg[192] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[192]),
        .Q(D[192]),
        .R(1'b0));
  FDRE \rdData_reg[193] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[200]),
        .Q(D[200]),
        .R(1'b0));
  FDRE \rdData_reg[194] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[208]),
        .Q(D[208]),
        .R(1'b0));
  FDRE \rdData_reg[195] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[216]),
        .Q(D[216]),
        .R(1'b0));
  FDRE \rdData_reg[196] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[224]),
        .Q(D[224]),
        .R(1'b0));
  FDRE \rdData_reg[197] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[232]),
        .Q(D[232]),
        .R(1'b0));
  FDRE \rdData_reg[198] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[240]),
        .Q(D[240]),
        .R(1'b0));
  FDRE \rdData_reg[199] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[248]),
        .Q(D[248]),
        .R(1'b0));
  FDRE \rdData_reg[19] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[26]),
        .Q(D[26]),
        .R(1'b0));
  FDRE \rdData_reg[1] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[8]),
        .Q(D[8]),
        .R(1'b0));
  FDRE \rdData_reg[200] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[193]),
        .Q(D[193]),
        .R(1'b0));
  FDRE \rdData_reg[201] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[201]),
        .Q(D[201]),
        .R(1'b0));
  FDRE \rdData_reg[202] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[209]),
        .Q(D[209]),
        .R(1'b0));
  FDRE \rdData_reg[203] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[217]),
        .Q(D[217]),
        .R(1'b0));
  FDRE \rdData_reg[204] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[225]),
        .Q(D[225]),
        .R(1'b0));
  FDRE \rdData_reg[205] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[233]),
        .Q(D[233]),
        .R(1'b0));
  FDRE \rdData_reg[206] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[241]),
        .Q(D[241]),
        .R(1'b0));
  FDRE \rdData_reg[207] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[249]),
        .Q(D[249]),
        .R(1'b0));
  FDRE \rdData_reg[208] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[194]),
        .Q(D[194]),
        .R(1'b0));
  FDRE \rdData_reg[209] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[202]),
        .Q(D[202]),
        .R(1'b0));
  FDRE \rdData_reg[20] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[34]),
        .Q(D[34]),
        .R(1'b0));
  FDRE \rdData_reg[210] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[210]),
        .Q(D[210]),
        .R(1'b0));
  FDRE \rdData_reg[211] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[218]),
        .Q(D[218]),
        .R(1'b0));
  FDRE \rdData_reg[212] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[226]),
        .Q(D[226]),
        .R(1'b0));
  FDRE \rdData_reg[213] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[234]),
        .Q(D[234]),
        .R(1'b0));
  FDRE \rdData_reg[214] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[242]),
        .Q(D[242]),
        .R(1'b0));
  FDRE \rdData_reg[215] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[250]),
        .Q(D[250]),
        .R(1'b0));
  FDRE \rdData_reg[216] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[195]),
        .Q(D[195]),
        .R(1'b0));
  FDRE \rdData_reg[217] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[203]),
        .Q(D[203]),
        .R(1'b0));
  FDRE \rdData_reg[218] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[211]),
        .Q(D[211]),
        .R(1'b0));
  FDRE \rdData_reg[219] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[219]),
        .Q(D[219]),
        .R(1'b0));
  FDRE \rdData_reg[21] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[42]),
        .Q(D[42]),
        .R(1'b0));
  FDRE \rdData_reg[220] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[227]),
        .Q(D[227]),
        .R(1'b0));
  FDRE \rdData_reg[221] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[235]),
        .Q(D[235]),
        .R(1'b0));
  FDRE \rdData_reg[222] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[243]),
        .Q(D[243]),
        .R(1'b0));
  FDRE \rdData_reg[223] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[251]),
        .Q(D[251]),
        .R(1'b0));
  FDRE \rdData_reg[224] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[196]),
        .Q(D[196]),
        .R(1'b0));
  FDRE \rdData_reg[225] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[204]),
        .Q(D[204]),
        .R(1'b0));
  FDRE \rdData_reg[226] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[212]),
        .Q(D[212]),
        .R(1'b0));
  FDRE \rdData_reg[227] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[220]),
        .Q(D[220]),
        .R(1'b0));
  FDRE \rdData_reg[228] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[228]),
        .Q(D[228]),
        .R(1'b0));
  FDRE \rdData_reg[229] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[236]),
        .Q(D[236]),
        .R(1'b0));
  FDRE \rdData_reg[22] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[50]),
        .Q(D[50]),
        .R(1'b0));
  FDRE \rdData_reg[230] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[244]),
        .Q(D[244]),
        .R(1'b0));
  FDRE \rdData_reg[231] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[252]),
        .Q(D[252]),
        .R(1'b0));
  FDRE \rdData_reg[232] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[197]),
        .Q(D[197]),
        .R(1'b0));
  FDRE \rdData_reg[233] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[205]),
        .Q(D[205]),
        .R(1'b0));
  FDRE \rdData_reg[234] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[213]),
        .Q(D[213]),
        .R(1'b0));
  FDRE \rdData_reg[235] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[221]),
        .Q(D[221]),
        .R(1'b0));
  FDRE \rdData_reg[236] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[229]),
        .Q(D[229]),
        .R(1'b0));
  FDRE \rdData_reg[237] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[237]),
        .Q(D[237]),
        .R(1'b0));
  FDRE \rdData_reg[238] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[245]),
        .Q(D[245]),
        .R(1'b0));
  FDRE \rdData_reg[239] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[253]),
        .Q(D[253]),
        .R(1'b0));
  FDRE \rdData_reg[23] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[58]),
        .Q(D[58]),
        .R(1'b0));
  FDRE \rdData_reg[240] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[198]),
        .Q(D[198]),
        .R(1'b0));
  FDRE \rdData_reg[241] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[206]),
        .Q(D[206]),
        .R(1'b0));
  FDRE \rdData_reg[242] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[214]),
        .Q(D[214]),
        .R(1'b0));
  FDRE \rdData_reg[243] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[222]),
        .Q(D[222]),
        .R(1'b0));
  FDRE \rdData_reg[244] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[230]),
        .Q(D[230]),
        .R(1'b0));
  FDRE \rdData_reg[245] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[238]),
        .Q(D[238]),
        .R(1'b0));
  FDRE \rdData_reg[246] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[246]),
        .Q(D[246]),
        .R(1'b0));
  FDRE \rdData_reg[247] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[254]),
        .Q(D[254]),
        .R(1'b0));
  FDRE \rdData_reg[248] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[199]),
        .Q(D[199]),
        .R(1'b0));
  FDRE \rdData_reg[249] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[207]),
        .Q(D[207]),
        .R(1'b0));
  FDRE \rdData_reg[24] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[3]),
        .Q(D[3]),
        .R(1'b0));
  FDRE \rdData_reg[250] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[215]),
        .Q(D[215]),
        .R(1'b0));
  FDRE \rdData_reg[251] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[223]),
        .Q(D[223]),
        .R(1'b0));
  FDRE \rdData_reg[252] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[231]),
        .Q(D[231]),
        .R(1'b0));
  FDRE \rdData_reg[253] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[239]),
        .Q(D[239]),
        .R(1'b0));
  FDRE \rdData_reg[254] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[247]),
        .Q(D[247]),
        .R(1'b0));
  FDRE \rdData_reg[255] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[255]),
        .Q(D[255]),
        .R(1'b0));
  FDRE \rdData_reg[256] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[256]),
        .Q(D[256]),
        .R(1'b0));
  FDRE \rdData_reg[257] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[264]),
        .Q(D[264]),
        .R(1'b0));
  FDRE \rdData_reg[258] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[272]),
        .Q(D[272]),
        .R(1'b0));
  FDRE \rdData_reg[259] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[280]),
        .Q(D[280]),
        .R(1'b0));
  FDRE \rdData_reg[25] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[11]),
        .Q(D[11]),
        .R(1'b0));
  FDRE \rdData_reg[260] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[288]),
        .Q(D[288]),
        .R(1'b0));
  FDRE \rdData_reg[261] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[296]),
        .Q(D[296]),
        .R(1'b0));
  FDRE \rdData_reg[262] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[304]),
        .Q(D[304]),
        .R(1'b0));
  FDRE \rdData_reg[263] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[312]),
        .Q(D[312]),
        .R(1'b0));
  FDRE \rdData_reg[264] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[257]),
        .Q(D[257]),
        .R(1'b0));
  FDRE \rdData_reg[265] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[265]),
        .Q(D[265]),
        .R(1'b0));
  FDRE \rdData_reg[266] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[273]),
        .Q(D[273]),
        .R(1'b0));
  FDRE \rdData_reg[267] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[281]),
        .Q(D[281]),
        .R(1'b0));
  FDRE \rdData_reg[268] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[289]),
        .Q(D[289]),
        .R(1'b0));
  FDRE \rdData_reg[269] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[297]),
        .Q(D[297]),
        .R(1'b0));
  FDRE \rdData_reg[26] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[19]),
        .Q(D[19]),
        .R(1'b0));
  FDRE \rdData_reg[270] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[305]),
        .Q(D[305]),
        .R(1'b0));
  FDRE \rdData_reg[271] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[313]),
        .Q(D[313]),
        .R(1'b0));
  FDRE \rdData_reg[272] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[258]),
        .Q(D[258]),
        .R(1'b0));
  FDRE \rdData_reg[273] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[266]),
        .Q(D[266]),
        .R(1'b0));
  FDRE \rdData_reg[274] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[274]),
        .Q(D[274]),
        .R(1'b0));
  FDRE \rdData_reg[275] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[282]),
        .Q(D[282]),
        .R(1'b0));
  FDRE \rdData_reg[276] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[290]),
        .Q(D[290]),
        .R(1'b0));
  FDRE \rdData_reg[277] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[298]),
        .Q(D[298]),
        .R(1'b0));
  FDRE \rdData_reg[278] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[306]),
        .Q(D[306]),
        .R(1'b0));
  FDRE \rdData_reg[279] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[314]),
        .Q(D[314]),
        .R(1'b0));
  FDRE \rdData_reg[27] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[27]),
        .Q(D[27]),
        .R(1'b0));
  FDRE \rdData_reg[280] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[259]),
        .Q(D[259]),
        .R(1'b0));
  FDRE \rdData_reg[281] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[267]),
        .Q(D[267]),
        .R(1'b0));
  FDRE \rdData_reg[282] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[275]),
        .Q(D[275]),
        .R(1'b0));
  FDRE \rdData_reg[283] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[283]),
        .Q(D[283]),
        .R(1'b0));
  FDRE \rdData_reg[284] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[291]),
        .Q(D[291]),
        .R(1'b0));
  FDRE \rdData_reg[285] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[299]),
        .Q(D[299]),
        .R(1'b0));
  FDRE \rdData_reg[286] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[307]),
        .Q(D[307]),
        .R(1'b0));
  FDRE \rdData_reg[287] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[315]),
        .Q(D[315]),
        .R(1'b0));
  FDRE \rdData_reg[288] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[260]),
        .Q(D[260]),
        .R(1'b0));
  FDRE \rdData_reg[289] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[268]),
        .Q(D[268]),
        .R(1'b0));
  FDRE \rdData_reg[28] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[35]),
        .Q(D[35]),
        .R(1'b0));
  FDRE \rdData_reg[290] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[276]),
        .Q(D[276]),
        .R(1'b0));
  FDRE \rdData_reg[291] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[284]),
        .Q(D[284]),
        .R(1'b0));
  FDRE \rdData_reg[292] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[292]),
        .Q(D[292]),
        .R(1'b0));
  FDRE \rdData_reg[293] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[300]),
        .Q(D[300]),
        .R(1'b0));
  FDRE \rdData_reg[294] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[308]),
        .Q(D[308]),
        .R(1'b0));
  FDRE \rdData_reg[295] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[316]),
        .Q(D[316]),
        .R(1'b0));
  FDRE \rdData_reg[296] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[261]),
        .Q(D[261]),
        .R(1'b0));
  FDRE \rdData_reg[297] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[269]),
        .Q(D[269]),
        .R(1'b0));
  FDRE \rdData_reg[298] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[277]),
        .Q(D[277]),
        .R(1'b0));
  FDRE \rdData_reg[299] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[285]),
        .Q(D[285]),
        .R(1'b0));
  FDRE \rdData_reg[29] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[43]),
        .Q(D[43]),
        .R(1'b0));
  FDRE \rdData_reg[2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[16]),
        .Q(D[16]),
        .R(1'b0));
  FDRE \rdData_reg[300] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[293]),
        .Q(D[293]),
        .R(1'b0));
  FDRE \rdData_reg[301] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[301]),
        .Q(D[301]),
        .R(1'b0));
  FDRE \rdData_reg[302] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[309]),
        .Q(D[309]),
        .R(1'b0));
  FDRE \rdData_reg[303] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[317]),
        .Q(D[317]),
        .R(1'b0));
  FDRE \rdData_reg[304] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[262]),
        .Q(D[262]),
        .R(1'b0));
  FDRE \rdData_reg[305] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[270]),
        .Q(D[270]),
        .R(1'b0));
  FDRE \rdData_reg[306] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[278]),
        .Q(D[278]),
        .R(1'b0));
  FDRE \rdData_reg[307] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[286]),
        .Q(D[286]),
        .R(1'b0));
  FDRE \rdData_reg[308] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[294]),
        .Q(D[294]),
        .R(1'b0));
  FDRE \rdData_reg[309] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[302]),
        .Q(D[302]),
        .R(1'b0));
  FDRE \rdData_reg[30] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[51]),
        .Q(D[51]),
        .R(1'b0));
  FDRE \rdData_reg[310] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[310]),
        .Q(D[310]),
        .R(1'b0));
  FDRE \rdData_reg[311] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[318]),
        .Q(D[318]),
        .R(1'b0));
  FDRE \rdData_reg[312] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[263]),
        .Q(D[263]),
        .R(1'b0));
  FDRE \rdData_reg[313] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[271]),
        .Q(D[271]),
        .R(1'b0));
  FDRE \rdData_reg[314] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[279]),
        .Q(D[279]),
        .R(1'b0));
  FDRE \rdData_reg[315] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[287]),
        .Q(D[287]),
        .R(1'b0));
  FDRE \rdData_reg[316] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[295]),
        .Q(D[295]),
        .R(1'b0));
  FDRE \rdData_reg[317] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[303]),
        .Q(D[303]),
        .R(1'b0));
  FDRE \rdData_reg[318] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[311]),
        .Q(D[311]),
        .R(1'b0));
  FDRE \rdData_reg[319] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[319]),
        .Q(D[319]),
        .R(1'b0));
  FDRE \rdData_reg[31] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[59]),
        .Q(D[59]),
        .R(1'b0));
  FDRE \rdData_reg[320] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[320]),
        .Q(D[320]),
        .R(1'b0));
  FDRE \rdData_reg[321] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[328]),
        .Q(D[328]),
        .R(1'b0));
  FDRE \rdData_reg[322] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[336]),
        .Q(D[336]),
        .R(1'b0));
  FDRE \rdData_reg[323] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[344]),
        .Q(D[344]),
        .R(1'b0));
  FDRE \rdData_reg[324] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[352]),
        .Q(D[352]),
        .R(1'b0));
  FDRE \rdData_reg[325] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[360]),
        .Q(D[360]),
        .R(1'b0));
  FDRE \rdData_reg[326] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[368]),
        .Q(D[368]),
        .R(1'b0));
  FDRE \rdData_reg[327] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[376]),
        .Q(D[376]),
        .R(1'b0));
  FDRE \rdData_reg[328] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[321]),
        .Q(D[321]),
        .R(1'b0));
  FDRE \rdData_reg[329] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[329]),
        .Q(D[329]),
        .R(1'b0));
  FDRE \rdData_reg[32] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[4]),
        .Q(D[4]),
        .R(1'b0));
  FDRE \rdData_reg[330] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[337]),
        .Q(D[337]),
        .R(1'b0));
  FDRE \rdData_reg[331] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[345]),
        .Q(D[345]),
        .R(1'b0));
  FDRE \rdData_reg[332] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[353]),
        .Q(D[353]),
        .R(1'b0));
  FDRE \rdData_reg[333] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[361]),
        .Q(D[361]),
        .R(1'b0));
  FDRE \rdData_reg[334] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[369]),
        .Q(D[369]),
        .R(1'b0));
  FDRE \rdData_reg[335] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[377]),
        .Q(D[377]),
        .R(1'b0));
  FDRE \rdData_reg[336] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[322]),
        .Q(D[322]),
        .R(1'b0));
  FDRE \rdData_reg[337] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[330]),
        .Q(D[330]),
        .R(1'b0));
  FDRE \rdData_reg[338] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[338]),
        .Q(D[338]),
        .R(1'b0));
  FDRE \rdData_reg[339] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[346]),
        .Q(D[346]),
        .R(1'b0));
  FDRE \rdData_reg[33] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[12]),
        .Q(D[12]),
        .R(1'b0));
  FDRE \rdData_reg[340] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[354]),
        .Q(D[354]),
        .R(1'b0));
  FDRE \rdData_reg[341] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[362]),
        .Q(D[362]),
        .R(1'b0));
  FDRE \rdData_reg[342] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[370]),
        .Q(D[370]),
        .R(1'b0));
  FDRE \rdData_reg[343] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[378]),
        .Q(D[378]),
        .R(1'b0));
  FDRE \rdData_reg[344] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[323]),
        .Q(D[323]),
        .R(1'b0));
  FDRE \rdData_reg[345] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[331]),
        .Q(D[331]),
        .R(1'b0));
  FDRE \rdData_reg[346] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[339]),
        .Q(D[339]),
        .R(1'b0));
  FDRE \rdData_reg[347] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[347]),
        .Q(D[347]),
        .R(1'b0));
  FDRE \rdData_reg[348] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[355]),
        .Q(D[355]),
        .R(1'b0));
  FDRE \rdData_reg[349] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[363]),
        .Q(D[363]),
        .R(1'b0));
  FDRE \rdData_reg[34] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[20]),
        .Q(D[20]),
        .R(1'b0));
  FDRE \rdData_reg[350] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[371]),
        .Q(D[371]),
        .R(1'b0));
  FDRE \rdData_reg[351] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[379]),
        .Q(D[379]),
        .R(1'b0));
  FDRE \rdData_reg[352] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[324]),
        .Q(D[324]),
        .R(1'b0));
  FDRE \rdData_reg[353] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[332]),
        .Q(D[332]),
        .R(1'b0));
  FDRE \rdData_reg[354] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[340]),
        .Q(D[340]),
        .R(1'b0));
  FDRE \rdData_reg[355] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[348]),
        .Q(D[348]),
        .R(1'b0));
  FDRE \rdData_reg[356] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[356]),
        .Q(D[356]),
        .R(1'b0));
  FDRE \rdData_reg[357] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[364]),
        .Q(D[364]),
        .R(1'b0));
  FDRE \rdData_reg[358] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[372]),
        .Q(D[372]),
        .R(1'b0));
  FDRE \rdData_reg[359] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[380]),
        .Q(D[380]),
        .R(1'b0));
  FDRE \rdData_reg[35] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[28]),
        .Q(D[28]),
        .R(1'b0));
  FDRE \rdData_reg[360] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[325]),
        .Q(D[325]),
        .R(1'b0));
  FDRE \rdData_reg[361] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[333]),
        .Q(D[333]),
        .R(1'b0));
  FDRE \rdData_reg[362] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[341]),
        .Q(D[341]),
        .R(1'b0));
  FDRE \rdData_reg[363] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[349]),
        .Q(D[349]),
        .R(1'b0));
  FDRE \rdData_reg[364] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[357]),
        .Q(D[357]),
        .R(1'b0));
  FDRE \rdData_reg[365] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[365]),
        .Q(D[365]),
        .R(1'b0));
  FDRE \rdData_reg[366] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[373]),
        .Q(D[373]),
        .R(1'b0));
  FDRE \rdData_reg[367] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[381]),
        .Q(D[381]),
        .R(1'b0));
  FDRE \rdData_reg[368] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[326]),
        .Q(D[326]),
        .R(1'b0));
  FDRE \rdData_reg[369] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[334]),
        .Q(D[334]),
        .R(1'b0));
  FDRE \rdData_reg[36] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[36]),
        .Q(D[36]),
        .R(1'b0));
  FDRE \rdData_reg[370] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[342]),
        .Q(D[342]),
        .R(1'b0));
  FDRE \rdData_reg[371] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[350]),
        .Q(D[350]),
        .R(1'b0));
  FDRE \rdData_reg[372] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[358]),
        .Q(D[358]),
        .R(1'b0));
  FDRE \rdData_reg[373] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[366]),
        .Q(D[366]),
        .R(1'b0));
  FDRE \rdData_reg[374] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[374]),
        .Q(D[374]),
        .R(1'b0));
  FDRE \rdData_reg[375] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[382]),
        .Q(D[382]),
        .R(1'b0));
  FDRE \rdData_reg[376] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[327]),
        .Q(D[327]),
        .R(1'b0));
  FDRE \rdData_reg[377] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[335]),
        .Q(D[335]),
        .R(1'b0));
  FDRE \rdData_reg[378] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[343]),
        .Q(D[343]),
        .R(1'b0));
  FDRE \rdData_reg[379] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[351]),
        .Q(D[351]),
        .R(1'b0));
  FDRE \rdData_reg[37] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[44]),
        .Q(D[44]),
        .R(1'b0));
  FDRE \rdData_reg[380] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[359]),
        .Q(D[359]),
        .R(1'b0));
  FDRE \rdData_reg[381] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[367]),
        .Q(D[367]),
        .R(1'b0));
  FDRE \rdData_reg[382] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[375]),
        .Q(D[375]),
        .R(1'b0));
  FDRE \rdData_reg[383] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[383]),
        .Q(D[383]),
        .R(1'b0));
  FDRE \rdData_reg[384] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[384]),
        .Q(D[384]),
        .R(1'b0));
  FDRE \rdData_reg[385] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[392]),
        .Q(D[392]),
        .R(1'b0));
  FDRE \rdData_reg[386] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[400]),
        .Q(D[400]),
        .R(1'b0));
  FDRE \rdData_reg[387] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[408]),
        .Q(D[408]),
        .R(1'b0));
  FDRE \rdData_reg[388] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[416]),
        .Q(D[416]),
        .R(1'b0));
  FDRE \rdData_reg[389] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[424]),
        .Q(D[424]),
        .R(1'b0));
  FDRE \rdData_reg[38] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[52]),
        .Q(D[52]),
        .R(1'b0));
  FDRE \rdData_reg[390] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[432]),
        .Q(D[432]),
        .R(1'b0));
  FDRE \rdData_reg[391] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[440]),
        .Q(D[440]),
        .R(1'b0));
  FDRE \rdData_reg[392] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[385]),
        .Q(D[385]),
        .R(1'b0));
  FDRE \rdData_reg[393] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[393]),
        .Q(D[393]),
        .R(1'b0));
  FDRE \rdData_reg[394] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[401]),
        .Q(D[401]),
        .R(1'b0));
  FDRE \rdData_reg[395] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[409]),
        .Q(D[409]),
        .R(1'b0));
  FDRE \rdData_reg[396] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[417]),
        .Q(D[417]),
        .R(1'b0));
  FDRE \rdData_reg[397] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[425]),
        .Q(D[425]),
        .R(1'b0));
  FDRE \rdData_reg[398] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[433]),
        .Q(D[433]),
        .R(1'b0));
  FDRE \rdData_reg[399] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[441]),
        .Q(D[441]),
        .R(1'b0));
  FDRE \rdData_reg[39] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[60]),
        .Q(D[60]),
        .R(1'b0));
  FDRE \rdData_reg[3] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[24]),
        .Q(D[24]),
        .R(1'b0));
  FDRE \rdData_reg[400] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[386]),
        .Q(D[386]),
        .R(1'b0));
  FDRE \rdData_reg[401] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[394]),
        .Q(D[394]),
        .R(1'b0));
  FDRE \rdData_reg[402] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[402]),
        .Q(D[402]),
        .R(1'b0));
  FDRE \rdData_reg[403] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[410]),
        .Q(D[410]),
        .R(1'b0));
  FDRE \rdData_reg[404] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[418]),
        .Q(D[418]),
        .R(1'b0));
  FDRE \rdData_reg[405] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[426]),
        .Q(D[426]),
        .R(1'b0));
  FDRE \rdData_reg[406] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[434]),
        .Q(D[434]),
        .R(1'b0));
  FDRE \rdData_reg[407] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[442]),
        .Q(D[442]),
        .R(1'b0));
  FDRE \rdData_reg[408] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[387]),
        .Q(D[387]),
        .R(1'b0));
  FDRE \rdData_reg[409] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[395]),
        .Q(D[395]),
        .R(1'b0));
  FDRE \rdData_reg[40] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[5]),
        .Q(D[5]),
        .R(1'b0));
  FDRE \rdData_reg[410] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[403]),
        .Q(D[403]),
        .R(1'b0));
  FDRE \rdData_reg[411] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[411]),
        .Q(D[411]),
        .R(1'b0));
  FDRE \rdData_reg[412] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[419]),
        .Q(D[419]),
        .R(1'b0));
  FDRE \rdData_reg[413] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[427]),
        .Q(D[427]),
        .R(1'b0));
  FDRE \rdData_reg[414] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[435]),
        .Q(D[435]),
        .R(1'b0));
  FDRE \rdData_reg[415] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[443]),
        .Q(D[443]),
        .R(1'b0));
  FDRE \rdData_reg[416] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[388]),
        .Q(D[388]),
        .R(1'b0));
  FDRE \rdData_reg[417] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[396]),
        .Q(D[396]),
        .R(1'b0));
  FDRE \rdData_reg[418] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[404]),
        .Q(D[404]),
        .R(1'b0));
  FDRE \rdData_reg[419] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[412]),
        .Q(D[412]),
        .R(1'b0));
  FDRE \rdData_reg[41] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[13]),
        .Q(D[13]),
        .R(1'b0));
  FDRE \rdData_reg[420] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[420]),
        .Q(D[420]),
        .R(1'b0));
  FDRE \rdData_reg[421] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[428]),
        .Q(D[428]),
        .R(1'b0));
  FDRE \rdData_reg[422] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[436]),
        .Q(D[436]),
        .R(1'b0));
  FDRE \rdData_reg[423] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[444]),
        .Q(D[444]),
        .R(1'b0));
  FDRE \rdData_reg[424] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[389]),
        .Q(D[389]),
        .R(1'b0));
  FDRE \rdData_reg[425] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[397]),
        .Q(D[397]),
        .R(1'b0));
  FDRE \rdData_reg[426] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[405]),
        .Q(D[405]),
        .R(1'b0));
  FDRE \rdData_reg[427] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[413]),
        .Q(D[413]),
        .R(1'b0));
  FDRE \rdData_reg[428] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[421]),
        .Q(D[421]),
        .R(1'b0));
  FDRE \rdData_reg[429] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[429]),
        .Q(D[429]),
        .R(1'b0));
  FDRE \rdData_reg[42] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[21]),
        .Q(D[21]),
        .R(1'b0));
  FDRE \rdData_reg[430] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[437]),
        .Q(D[437]),
        .R(1'b0));
  FDRE \rdData_reg[431] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[445]),
        .Q(D[445]),
        .R(1'b0));
  FDRE \rdData_reg[432] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[390]),
        .Q(D[390]),
        .R(1'b0));
  FDRE \rdData_reg[433] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[398]),
        .Q(D[398]),
        .R(1'b0));
  FDRE \rdData_reg[434] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[406]),
        .Q(D[406]),
        .R(1'b0));
  FDRE \rdData_reg[435] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[414]),
        .Q(D[414]),
        .R(1'b0));
  FDRE \rdData_reg[436] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[422]),
        .Q(D[422]),
        .R(1'b0));
  FDRE \rdData_reg[437] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[430]),
        .Q(D[430]),
        .R(1'b0));
  FDRE \rdData_reg[438] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[438]),
        .Q(D[438]),
        .R(1'b0));
  FDRE \rdData_reg[439] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[446]),
        .Q(D[446]),
        .R(1'b0));
  FDRE \rdData_reg[43] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[29]),
        .Q(D[29]),
        .R(1'b0));
  FDRE \rdData_reg[440] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[391]),
        .Q(D[391]),
        .R(1'b0));
  FDRE \rdData_reg[441] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[399]),
        .Q(D[399]),
        .R(1'b0));
  FDRE \rdData_reg[442] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[407]),
        .Q(D[407]),
        .R(1'b0));
  FDRE \rdData_reg[443] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[415]),
        .Q(D[415]),
        .R(1'b0));
  FDRE \rdData_reg[444] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[423]),
        .Q(D[423]),
        .R(1'b0));
  FDRE \rdData_reg[445] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[431]),
        .Q(D[431]),
        .R(1'b0));
  FDRE \rdData_reg[446] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[439]),
        .Q(D[439]),
        .R(1'b0));
  FDRE \rdData_reg[447] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[447]),
        .Q(D[447]),
        .R(1'b0));
  FDRE \rdData_reg[448] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[448]),
        .Q(D[448]),
        .R(1'b0));
  FDRE \rdData_reg[449] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[456]),
        .Q(D[456]),
        .R(1'b0));
  FDRE \rdData_reg[44] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[37]),
        .Q(D[37]),
        .R(1'b0));
  FDRE \rdData_reg[450] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[464]),
        .Q(D[464]),
        .R(1'b0));
  FDRE \rdData_reg[451] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[472]),
        .Q(D[472]),
        .R(1'b0));
  FDRE \rdData_reg[452] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[480]),
        .Q(D[480]),
        .R(1'b0));
  FDRE \rdData_reg[453] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[488]),
        .Q(D[488]),
        .R(1'b0));
  FDRE \rdData_reg[454] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[496]),
        .Q(D[496]),
        .R(1'b0));
  FDRE \rdData_reg[455] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[504]),
        .Q(D[504]),
        .R(1'b0));
  FDRE \rdData_reg[456] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[449]),
        .Q(D[449]),
        .R(1'b0));
  FDRE \rdData_reg[457] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[457]),
        .Q(D[457]),
        .R(1'b0));
  FDRE \rdData_reg[458] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[465]),
        .Q(D[465]),
        .R(1'b0));
  FDRE \rdData_reg[459] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[473]),
        .Q(D[473]),
        .R(1'b0));
  FDRE \rdData_reg[45] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[45]),
        .Q(D[45]),
        .R(1'b0));
  FDRE \rdData_reg[460] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[481]),
        .Q(D[481]),
        .R(1'b0));
  FDRE \rdData_reg[461] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[489]),
        .Q(D[489]),
        .R(1'b0));
  FDRE \rdData_reg[462] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[497]),
        .Q(D[497]),
        .R(1'b0));
  FDRE \rdData_reg[463] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[505]),
        .Q(D[505]),
        .R(1'b0));
  FDRE \rdData_reg[464] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[450]),
        .Q(D[450]),
        .R(1'b0));
  FDRE \rdData_reg[465] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[458]),
        .Q(D[458]),
        .R(1'b0));
  FDRE \rdData_reg[466] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[466]),
        .Q(D[466]),
        .R(1'b0));
  FDRE \rdData_reg[467] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[474]),
        .Q(D[474]),
        .R(1'b0));
  FDRE \rdData_reg[468] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[482]),
        .Q(D[482]),
        .R(1'b0));
  FDRE \rdData_reg[469] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[490]),
        .Q(D[490]),
        .R(1'b0));
  FDRE \rdData_reg[46] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[53]),
        .Q(D[53]),
        .R(1'b0));
  FDRE \rdData_reg[470] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[498]),
        .Q(D[498]),
        .R(1'b0));
  FDRE \rdData_reg[471] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[506]),
        .Q(D[506]),
        .R(1'b0));
  FDRE \rdData_reg[472] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[451]),
        .Q(D[451]),
        .R(1'b0));
  FDRE \rdData_reg[473] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[459]),
        .Q(D[459]),
        .R(1'b0));
  FDRE \rdData_reg[474] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[467]),
        .Q(D[467]),
        .R(1'b0));
  FDRE \rdData_reg[475] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[475]),
        .Q(D[475]),
        .R(1'b0));
  FDRE \rdData_reg[476] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[483]),
        .Q(D[483]),
        .R(1'b0));
  FDRE \rdData_reg[477] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[491]),
        .Q(D[491]),
        .R(1'b0));
  FDRE \rdData_reg[478] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[499]),
        .Q(D[499]),
        .R(1'b0));
  FDRE \rdData_reg[479] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[507]),
        .Q(D[507]),
        .R(1'b0));
  FDRE \rdData_reg[47] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[61]),
        .Q(D[61]),
        .R(1'b0));
  FDRE \rdData_reg[480] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[452]),
        .Q(D[452]),
        .R(1'b0));
  FDRE \rdData_reg[481] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[460]),
        .Q(D[460]),
        .R(1'b0));
  FDRE \rdData_reg[482] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[468]),
        .Q(D[468]),
        .R(1'b0));
  FDRE \rdData_reg[483] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[476]),
        .Q(D[476]),
        .R(1'b0));
  FDRE \rdData_reg[484] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[484]),
        .Q(D[484]),
        .R(1'b0));
  FDRE \rdData_reg[485] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[492]),
        .Q(D[492]),
        .R(1'b0));
  FDRE \rdData_reg[486] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[500]),
        .Q(D[500]),
        .R(1'b0));
  FDRE \rdData_reg[487] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[508]),
        .Q(D[508]),
        .R(1'b0));
  FDRE \rdData_reg[488] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[453]),
        .Q(D[453]),
        .R(1'b0));
  FDRE \rdData_reg[489] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[461]),
        .Q(D[461]),
        .R(1'b0));
  FDRE \rdData_reg[48] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[6]),
        .Q(D[6]),
        .R(1'b0));
  FDRE \rdData_reg[490] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[469]),
        .Q(D[469]),
        .R(1'b0));
  FDRE \rdData_reg[491] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[477]),
        .Q(D[477]),
        .R(1'b0));
  FDRE \rdData_reg[492] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[485]),
        .Q(D[485]),
        .R(1'b0));
  FDRE \rdData_reg[493] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[493]),
        .Q(D[493]),
        .R(1'b0));
  FDRE \rdData_reg[494] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[501]),
        .Q(D[501]),
        .R(1'b0));
  FDRE \rdData_reg[495] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[509]),
        .Q(D[509]),
        .R(1'b0));
  FDRE \rdData_reg[496] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[454]),
        .Q(D[454]),
        .R(1'b0));
  FDRE \rdData_reg[497] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[462]),
        .Q(D[462]),
        .R(1'b0));
  FDRE \rdData_reg[498] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[470]),
        .Q(D[470]),
        .R(1'b0));
  FDRE \rdData_reg[499] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[478]),
        .Q(D[478]),
        .R(1'b0));
  FDRE \rdData_reg[49] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[14]),
        .Q(D[14]),
        .R(1'b0));
  FDRE \rdData_reg[4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[32]),
        .Q(D[32]),
        .R(1'b0));
  FDRE \rdData_reg[500] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[486]),
        .Q(D[486]),
        .R(1'b0));
  FDRE \rdData_reg[501] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[494]),
        .Q(D[494]),
        .R(1'b0));
  FDRE \rdData_reg[502] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[502]),
        .Q(D[502]),
        .R(1'b0));
  FDRE \rdData_reg[503] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[510]),
        .Q(D[510]),
        .R(1'b0));
  FDRE \rdData_reg[504] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[455]),
        .Q(D[455]),
        .R(1'b0));
  FDRE \rdData_reg[505] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[463]),
        .Q(D[463]),
        .R(1'b0));
  FDRE \rdData_reg[506] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[471]),
        .Q(D[471]),
        .R(1'b0));
  FDRE \rdData_reg[507] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[479]),
        .Q(D[479]),
        .R(1'b0));
  FDRE \rdData_reg[508] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[487]),
        .Q(D[487]),
        .R(1'b0));
  FDRE \rdData_reg[509] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[495]),
        .Q(D[495]),
        .R(1'b0));
  FDRE \rdData_reg[50] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[22]),
        .Q(D[22]),
        .R(1'b0));
  FDRE \rdData_reg[510] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[503]),
        .Q(D[503]),
        .R(1'b0));
  FDRE \rdData_reg[511] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[511]),
        .Q(D[511]),
        .R(1'b0));
  FDRE \rdData_reg[51] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[30]),
        .Q(D[30]),
        .R(1'b0));
  FDRE \rdData_reg[52] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[38]),
        .Q(D[38]),
        .R(1'b0));
  FDRE \rdData_reg[53] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[46]),
        .Q(D[46]),
        .R(1'b0));
  FDRE \rdData_reg[54] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[54]),
        .Q(D[54]),
        .R(1'b0));
  FDRE \rdData_reg[55] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[62]),
        .Q(D[62]),
        .R(1'b0));
  FDRE \rdData_reg[56] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[7]),
        .Q(D[7]),
        .R(1'b0));
  FDRE \rdData_reg[57] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[15]),
        .Q(D[15]),
        .R(1'b0));
  FDRE \rdData_reg[58] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[23]),
        .Q(D[23]),
        .R(1'b0));
  FDRE \rdData_reg[59] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[31]),
        .Q(D[31]),
        .R(1'b0));
  FDRE \rdData_reg[5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[40]),
        .Q(D[40]),
        .R(1'b0));
  FDRE \rdData_reg[60] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[39]),
        .Q(D[39]),
        .R(1'b0));
  FDRE \rdData_reg[61] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[47]),
        .Q(D[47]),
        .R(1'b0));
  FDRE \rdData_reg[62] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[55]),
        .Q(D[55]),
        .R(1'b0));
  FDRE \rdData_reg[63] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[63]),
        .Q(D[63]),
        .R(1'b0));
  FDRE \rdData_reg[64] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[64]),
        .Q(D[64]),
        .R(1'b0));
  FDRE \rdData_reg[65] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[72]),
        .Q(D[72]),
        .R(1'b0));
  FDRE \rdData_reg[66] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[80]),
        .Q(D[80]),
        .R(1'b0));
  FDRE \rdData_reg[67] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[88]),
        .Q(D[88]),
        .R(1'b0));
  FDRE \rdData_reg[68] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[96]),
        .Q(D[96]),
        .R(1'b0));
  FDRE \rdData_reg[69] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[104]),
        .Q(D[104]),
        .R(1'b0));
  FDRE \rdData_reg[6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[48]),
        .Q(D[48]),
        .R(1'b0));
  FDRE \rdData_reg[70] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[112]),
        .Q(D[112]),
        .R(1'b0));
  FDRE \rdData_reg[71] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[120]),
        .Q(D[120]),
        .R(1'b0));
  FDRE \rdData_reg[72] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[65]),
        .Q(D[65]),
        .R(1'b0));
  FDRE \rdData_reg[73] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[73]),
        .Q(D[73]),
        .R(1'b0));
  FDRE \rdData_reg[74] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[81]),
        .Q(D[81]),
        .R(1'b0));
  FDRE \rdData_reg[75] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[89]),
        .Q(D[89]),
        .R(1'b0));
  FDRE \rdData_reg[76] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[97]),
        .Q(D[97]),
        .R(1'b0));
  FDRE \rdData_reg[77] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[105]),
        .Q(D[105]),
        .R(1'b0));
  FDRE \rdData_reg[78] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[113]),
        .Q(D[113]),
        .R(1'b0));
  FDRE \rdData_reg[79] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[121]),
        .Q(D[121]),
        .R(1'b0));
  FDRE \rdData_reg[7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[56]),
        .Q(D[56]),
        .R(1'b0));
  FDRE \rdData_reg[80] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[66]),
        .Q(D[66]),
        .R(1'b0));
  FDRE \rdData_reg[81] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[74]),
        .Q(D[74]),
        .R(1'b0));
  FDRE \rdData_reg[82] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[82]),
        .Q(D[82]),
        .R(1'b0));
  FDRE \rdData_reg[83] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[90]),
        .Q(D[90]),
        .R(1'b0));
  FDRE \rdData_reg[84] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[98]),
        .Q(D[98]),
        .R(1'b0));
  FDRE \rdData_reg[85] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[106]),
        .Q(D[106]),
        .R(1'b0));
  FDRE \rdData_reg[86] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[114]),
        .Q(D[114]),
        .R(1'b0));
  FDRE \rdData_reg[87] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[122]),
        .Q(D[122]),
        .R(1'b0));
  FDRE \rdData_reg[88] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[67]),
        .Q(D[67]),
        .R(1'b0));
  FDRE \rdData_reg[89] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[75]),
        .Q(D[75]),
        .R(1'b0));
  FDRE \rdData_reg[8] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[1]),
        .Q(D[1]),
        .R(1'b0));
  FDRE \rdData_reg[90] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[83]),
        .Q(D[83]),
        .R(1'b0));
  FDRE \rdData_reg[91] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[91]),
        .Q(D[91]),
        .R(1'b0));
  FDRE \rdData_reg[92] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[99]),
        .Q(D[99]),
        .R(1'b0));
  FDRE \rdData_reg[93] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[107]),
        .Q(D[107]),
        .R(1'b0));
  FDRE \rdData_reg[94] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[115]),
        .Q(D[115]),
        .R(1'b0));
  FDRE \rdData_reg[95] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[123]),
        .Q(D[123]),
        .R(1'b0));
  FDRE \rdData_reg[96] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[68]),
        .Q(D[68]),
        .R(1'b0));
  FDRE \rdData_reg[97] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[76]),
        .Q(D[76]),
        .R(1'b0));
  FDRE \rdData_reg[98] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[84]),
        .Q(D[84]),
        .R(1'b0));
  FDRE \rdData_reg[99] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[92]),
        .Q(D[92]),
        .R(1'b0));
  FDRE \rdData_reg[9] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(mcal_DQIn[9]),
        .Q(D[9]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE rst_r1_reg
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(SR),
        .Q(rst_r1),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h80000000FFFFFFFF)) 
    sample_gts_i_1
       (.I0(phy_rden_and_stg_gt[5]),
        .I1(phy_rden_and_stg_gt[4]),
        .I2(phy_rden_and_stg_gt[7]),
        .I3(phy_rden_and_stg_gt[6]),
        .I4(phy_rden_and_stg_gt[3]),
        .I5(sample_gts_i_2_n_0),
        .O(sample_gts0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    sample_gts_i_2
       (.I0(phy_rden_or_stg_gt[3]),
        .I1(phy_rden_or_stg_gt[6]),
        .I2(phy_rden_or_stg_gt[7]),
        .I3(phy_rden_or_stg_gt[4]),
        .I4(phy_rden_or_stg_gt[5]),
        .O(sample_gts_i_2_n_0));
  FDRE sample_gts_reg
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(sample_gts0),
        .Q(sample_gts),
        .R(1'b0));
  ddr4_0_ddr4_v2_2_17_cal u_ddr_cal
       (.D(cal_clb2phy_fifo_rden),
        .DMOut(DMOut),
        .DQOut(DQOut),
        .E(E),
        .O(O),
        .Q({p_1_in__0[8],p_1_in__0[0]}),
        .S(S),
        .SR(SR),
        .\SYNC[0].sync_reg_reg[1] (\SYNC[0].sync_reg_reg[1] ),
        .\SYNC[0].sync_reg_reg[1]_0 (\SYNC[0].sync_reg_reg[1]_0 ),
        .\SYNC[0].sync_reg_reg[1]_1 (\dReg_reg[10] ),
        .\SYNC[18].sync_reg_reg[1] (\SYNC[18].sync_reg_reg[1] ),
        .\SYNC[20].sync_reg_reg[1] (\SYNC[20].sync_reg_reg[1] ),
        .\SYNC[3].sync_reg_reg[1] (\SYNC[3].sync_reg_reg[1] ),
        .\SYNC[3].sync_reg_reg[1]_0 (\SYNC[3].sync_reg_reg[1]_0 ),
        .\SYNC[3].sync_reg_reg[1]_1 (\SYNC[3].sync_reg_reg[1]_1 ),
        .\SYNC[3].sync_reg_reg[1]_10 (\SYNC[3].sync_reg_reg[1]_10 ),
        .\SYNC[3].sync_reg_reg[1]_11 (\SYNC[3].sync_reg_reg[1]_11 ),
        .\SYNC[3].sync_reg_reg[1]_12 (\SYNC[3].sync_reg_reg[1]_12 ),
        .\SYNC[3].sync_reg_reg[1]_13 (\SYNC[3].sync_reg_reg[1]_13 ),
        .\SYNC[3].sync_reg_reg[1]_14 (\SYNC[3].sync_reg_reg[1]_14 ),
        .\SYNC[3].sync_reg_reg[1]_15 (\SYNC[3].sync_reg_reg[1]_15 ),
        .\SYNC[3].sync_reg_reg[1]_16 (\SYNC[3].sync_reg_reg[1]_16 ),
        .\SYNC[3].sync_reg_reg[1]_17 (\SYNC[3].sync_reg_reg[1]_17 ),
        .\SYNC[3].sync_reg_reg[1]_18 (\SYNC[3].sync_reg_reg[1]_18 ),
        .\SYNC[3].sync_reg_reg[1]_19 (\SYNC[3].sync_reg_reg[1]_19 ),
        .\SYNC[3].sync_reg_reg[1]_2 (\SYNC[3].sync_reg_reg[1]_2 ),
        .\SYNC[3].sync_reg_reg[1]_20 (\SYNC[3].sync_reg_reg[1]_20 ),
        .\SYNC[3].sync_reg_reg[1]_21 (\SYNC[3].sync_reg_reg[1]_21 ),
        .\SYNC[3].sync_reg_reg[1]_22 (\SYNC[3].sync_reg_reg[1]_22 ),
        .\SYNC[3].sync_reg_reg[1]_23 (\SYNC[3].sync_reg_reg[1]_23 ),
        .\SYNC[3].sync_reg_reg[1]_24 (\SYNC[3].sync_reg_reg[1]_24 ),
        .\SYNC[3].sync_reg_reg[1]_25 (\SYNC[3].sync_reg_reg[1]_25 ),
        .\SYNC[3].sync_reg_reg[1]_26 (\SYNC[3].sync_reg_reg[1]_26 ),
        .\SYNC[3].sync_reg_reg[1]_27 (\SYNC[3].sync_reg_reg[1]_27 ),
        .\SYNC[3].sync_reg_reg[1]_28 (\SYNC[3].sync_reg_reg[1]_28 ),
        .\SYNC[3].sync_reg_reg[1]_29 (\SYNC[3].sync_reg_reg[1]_29 ),
        .\SYNC[3].sync_reg_reg[1]_3 (\SYNC[3].sync_reg_reg[1]_3 ),
        .\SYNC[3].sync_reg_reg[1]_30 (\SYNC[3].sync_reg_reg[1]_30 ),
        .\SYNC[3].sync_reg_reg[1]_31 (\SYNC[3].sync_reg_reg[1]_31 ),
        .\SYNC[3].sync_reg_reg[1]_32 (\SYNC[3].sync_reg_reg[1]_32 ),
        .\SYNC[3].sync_reg_reg[1]_33 (\SYNC[3].sync_reg_reg[1]_33 ),
        .\SYNC[3].sync_reg_reg[1]_34 (\SYNC[3].sync_reg_reg[1]_34 ),
        .\SYNC[3].sync_reg_reg[1]_35 (\SYNC[3].sync_reg_reg[1]_35 ),
        .\SYNC[3].sync_reg_reg[1]_36 (\SYNC[3].sync_reg_reg[1]_36 ),
        .\SYNC[3].sync_reg_reg[1]_37 (\SYNC[3].sync_reg_reg[1]_37 ),
        .\SYNC[3].sync_reg_reg[1]_38 (\SYNC[3].sync_reg_reg[1]_38 ),
        .\SYNC[3].sync_reg_reg[1]_39 (\SYNC[3].sync_reg_reg[1]_39 ),
        .\SYNC[3].sync_reg_reg[1]_4 (\SYNC[3].sync_reg_reg[1]_4 ),
        .\SYNC[3].sync_reg_reg[1]_40 (\SYNC[3].sync_reg_reg[1]_40 ),
        .\SYNC[3].sync_reg_reg[1]_41 (\SYNC[3].sync_reg_reg[1]_41 ),
        .\SYNC[3].sync_reg_reg[1]_42 (\SYNC[3].sync_reg_reg[1]_42 ),
        .\SYNC[3].sync_reg_reg[1]_43 (\SYNC[3].sync_reg_reg[1]_43 ),
        .\SYNC[3].sync_reg_reg[1]_44 (\SYNC[3].sync_reg_reg[1]_44 ),
        .\SYNC[3].sync_reg_reg[1]_45 (\SYNC[3].sync_reg_reg[1]_45 ),
        .\SYNC[3].sync_reg_reg[1]_5 (\SYNC[3].sync_reg_reg[1]_5 ),
        .\SYNC[3].sync_reg_reg[1]_6 (\SYNC[3].sync_reg_reg[1]_6 ),
        .\SYNC[3].sync_reg_reg[1]_7 (\SYNC[3].sync_reg_reg[1]_7 ),
        .\SYNC[3].sync_reg_reg[1]_8 (\SYNC[3].sync_reg_reg[1]_8 ),
        .\SYNC[3].sync_reg_reg[1]_9 (\SYNC[3].sync_reg_reg[1]_9 ),
        .\SYNC[4].sync_reg_reg[1] (\SYNC[4].sync_reg_reg[1] ),
        .\SYNC[4].sync_reg_reg[1]_0 (\SYNC[4].sync_reg_reg[1]_0 ),
        .\SYNC[5].sync_reg_reg[1] (\SYNC[5].sync_reg_reg[1] ),
        .\SYNC[5].sync_reg_reg[1]_0 (\SYNC[5].sync_reg_reg[1]_0 ),
        .\SYNC[5].sync_reg_reg[1]_1 (\SYNC[5].sync_reg_reg[1]_1 ),
        .\SYNC[5].sync_reg_reg[1]_10 (\SYNC[5].sync_reg_reg[1]_10 ),
        .\SYNC[5].sync_reg_reg[1]_11 (\SYNC[5].sync_reg_reg[1]_11 ),
        .\SYNC[5].sync_reg_reg[1]_12 (\SYNC[5].sync_reg_reg[1]_12 ),
        .\SYNC[5].sync_reg_reg[1]_13 (\SYNC[5].sync_reg_reg[1]_13 ),
        .\SYNC[5].sync_reg_reg[1]_14 (\SYNC[5].sync_reg_reg[1]_14 ),
        .\SYNC[5].sync_reg_reg[1]_15 (\SYNC[5].sync_reg_reg[1]_15 ),
        .\SYNC[5].sync_reg_reg[1]_16 (\SYNC[5].sync_reg_reg[1]_16 ),
        .\SYNC[5].sync_reg_reg[1]_17 (\SYNC[5].sync_reg_reg[1]_17 ),
        .\SYNC[5].sync_reg_reg[1]_2 (\SYNC[5].sync_reg_reg[1]_2 ),
        .\SYNC[5].sync_reg_reg[1]_3 (\SYNC[5].sync_reg_reg[1]_3 ),
        .\SYNC[5].sync_reg_reg[1]_4 (\SYNC[5].sync_reg_reg[1]_4 ),
        .\SYNC[5].sync_reg_reg[1]_5 (\SYNC[5].sync_reg_reg[1]_5 ),
        .\SYNC[5].sync_reg_reg[1]_6 (\SYNC[5].sync_reg_reg[1]_6 ),
        .\SYNC[5].sync_reg_reg[1]_7 (\SYNC[5].sync_reg_reg[1]_7 ),
        .\SYNC[5].sync_reg_reg[1]_8 (\SYNC[5].sync_reg_reg[1]_8 ),
        .\SYNC[5].sync_reg_reg[1]_9 (\SYNC[5].sync_reg_reg[1]_9 ),
        .a_b_cmd_sel_start0(a_b_cmd_sel_start0),
        .a_b_cmd_sel_start_reg(a_b_cmd_sel_start),
        .a_b_cmd_sel_start_reg_0(a_b_cmd_sel_start_reg),
        .\addr_dec_to_mb_data[0]_i_3 (\addr_dec_to_mb_data[0]_i_3 ),
        .\addr_dec_to_mb_data[31]_i_3 (\addr_dec_to_mb_data[31]_i_3 ),
        .\addr_dec_to_mb_data[4]_i_11 (\addr_dec_to_mb_data[4]_i_11 ),
        .\addr_dec_to_mb_data[6]_i_7 (\addr_dec_to_mb_data[6]_i_7 ),
        .\addr_dec_to_mb_data[6]_i_7_0 (\addr_dec_to_mb_data[6]_i_7_0 ),
        .\addr_dec_to_mb_data[7]_i_7 (\addr_dec_to_mb_data[7]_i_7 ),
        .\addr_dec_to_mb_data_reg[12] (\addr_dec_to_mb_data_reg[12] ),
        .\addr_dec_to_mb_data_reg[14] (\addr_dec_to_mb_data_reg[14] ),
        .\addr_dec_to_mb_data_reg[15] (\addr_dec_to_mb_data_reg[15] ),
        .\addr_dec_to_mb_data_reg[19] (\addr_dec_to_mb_data_reg[19] ),
        .\addr_dec_to_mb_data_reg[20] (\addr_dec_to_mb_data_reg[20] ),
        .\addr_dec_to_mb_data_reg[21] (\addr_dec_to_mb_data_reg[21] ),
        .\addr_dec_to_mb_data_reg[22] (\addr_dec_to_mb_data_reg[22] ),
        .\addr_dec_to_mb_data_reg[23] (\addr_dec_to_mb_data_reg[23] ),
        .\addr_dec_to_mb_data_reg[24] (\addr_dec_to_mb_data_reg[24] ),
        .\addr_dec_to_mb_data_reg[25] (\addr_dec_to_mb_data_reg[25] ),
        .\addr_dec_to_mb_data_reg[26] (\addr_dec_to_mb_data_reg[26] ),
        .\addr_dec_to_mb_data_reg[27] (\addr_dec_to_mb_data_reg[27] ),
        .\addr_dec_to_mb_data_reg[28] (\addr_dec_to_mb_data_reg[28] ),
        .\addr_dec_to_mb_data_reg[29] (\addr_dec_to_mb_data_reg[29] ),
        .\addr_dec_to_mb_data_reg[29]_0 (\addr_dec_to_mb_data_reg[29]_0 ),
        .\addr_dec_to_mb_data_reg[29]_1 (\addr_dec_to_mb_data_reg[29]_1 ),
        .\addr_dec_to_mb_data_reg[29]_2 (\addr_dec_to_mb_data_reg[29]_2 ),
        .\addr_dec_to_mb_data_reg[29]_3 (\addr_dec_to_mb_data_reg[29]_3 ),
        .\addr_dec_to_mb_data_reg[29]_4 (\addr_dec_to_mb_data_reg[29]_4 ),
        .\addr_dec_to_mb_data_reg[30] (\addr_dec_to_mb_data_reg[30] ),
        .\addr_dec_to_mb_data_reg[30]_0 (\addr_dec_to_mb_data_reg[30]_0 ),
        .\addr_dec_to_mb_data_reg[31] (\addr_dec_to_mb_data_reg[31] ),
        .\bisc_bit_reg[0] (\bisc_bit_reg[0] ),
        .bisc_byte(bisc_byte),
        .\blk1.(null)[0].diff (\rdEn[6].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_1 (\rdEn[3].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_11 (\rdEn[5].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_13 (\rdEn[5].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_15 (\rdEn[4].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_17 (\rdEn[6].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_19 (\rdEn[3].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_21 (\rdEn[2].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_23 (\rdEn[1].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_25 (\rdEn[0].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_27 (\rdEn[1].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_28 (\rdEn[7].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_3 (\rdEn[2].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_5 (\rdEn[4].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_7 (\rdEn[7].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_9 (\rdEn[0].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .calDone_gated_reg(calDone_gated_reg_1),
        .calDone_i(calDone_i),
        .calDone_reg_0(ub_calDone),
        .calDone_reg_1(calDone),
        .calDone_reg_10(u_ddr_cal_n_798),
        .calDone_reg_11(u_ddr_cal_n_799),
        .calDone_reg_12(u_ddr_cal_n_800),
        .calDone_reg_13(u_ddr_cal_n_802),
        .calDone_reg_14(calDone_reg),
        .calDone_reg_2({u_ddr_cal_n_126,u_ddr_cal_n_127,u_ddr_cal_n_128,u_ddr_cal_n_129,u_ddr_cal_n_130,u_ddr_cal_n_131,u_ddr_cal_n_132,u_ddr_cal_n_133,u_ddr_cal_n_134,u_ddr_cal_n_135,u_ddr_cal_n_136,u_ddr_cal_n_137,u_ddr_cal_n_138,u_ddr_cal_n_139,u_ddr_cal_n_140,u_ddr_cal_n_141,u_ddr_cal_n_142,u_ddr_cal_n_143,u_ddr_cal_n_144,u_ddr_cal_n_145,u_ddr_cal_n_146,u_ddr_cal_n_147,u_ddr_cal_n_148,u_ddr_cal_n_149,u_ddr_cal_n_150,u_ddr_cal_n_151,u_ddr_cal_n_152,u_ddr_cal_n_153,u_ddr_cal_n_154,u_ddr_cal_n_155,u_ddr_cal_n_156,u_ddr_cal_n_157,u_ddr_cal_n_158,u_ddr_cal_n_159,u_ddr_cal_n_160,u_ddr_cal_n_161,u_ddr_cal_n_162,u_ddr_cal_n_163,u_ddr_cal_n_164,u_ddr_cal_n_165,u_ddr_cal_n_166,u_ddr_cal_n_167,u_ddr_cal_n_168,u_ddr_cal_n_169,u_ddr_cal_n_170,u_ddr_cal_n_171,u_ddr_cal_n_172,u_ddr_cal_n_173,u_ddr_cal_n_174,u_ddr_cal_n_175,u_ddr_cal_n_176,u_ddr_cal_n_177,u_ddr_cal_n_178,u_ddr_cal_n_179,u_ddr_cal_n_180,u_ddr_cal_n_181,u_ddr_cal_n_182,u_ddr_cal_n_183,u_ddr_cal_n_184,u_ddr_cal_n_185,u_ddr_cal_n_186,u_ddr_cal_n_187,u_ddr_cal_n_188,u_ddr_cal_n_189,u_ddr_cal_n_190,u_ddr_cal_n_191,u_ddr_cal_n_192,u_ddr_cal_n_193,u_ddr_cal_n_194,u_ddr_cal_n_195,u_ddr_cal_n_196,u_ddr_cal_n_197,u_ddr_cal_n_198,u_ddr_cal_n_199,u_ddr_cal_n_200,u_ddr_cal_n_201,u_ddr_cal_n_202}),
        .calDone_reg_3({u_ddr_cal_n_204,u_ddr_cal_n_205,u_ddr_cal_n_206,u_ddr_cal_n_207}),
        .calDone_reg_4({u_ddr_cal_n_209,u_ddr_cal_n_210,u_ddr_cal_n_211,u_ddr_cal_n_212,u_ddr_cal_n_213,u_ddr_cal_n_214,u_ddr_cal_n_215,u_ddr_cal_n_216}),
        .calDone_reg_5(u_ddr_cal_n_793),
        .calDone_reg_6(u_ddr_cal_n_794),
        .calDone_reg_7(u_ddr_cal_n_795),
        .calDone_reg_8(u_ddr_cal_n_796),
        .calDone_reg_9(u_ddr_cal_n_797),
        .calRdCAS(calRdCAS),
        .\calSt_reg[0]_0 (\calSt_reg[0] ),
        .\cal_ACT_n_A_reg[7] (\cal_ACT_n_A_reg[7] ),
        .\cal_ACT_n_pre_reg[7] ({cal_ACT_n[7:5],cal_ACT_n[2:0]}),
        .\cal_ADR_A_reg[0] (\cal_ADR_A_reg[0] ),
        .\cal_ADR_A_reg[0]_0 (\cal_ADR_A_reg[0]_0 ),
        .\cal_ADR_A_reg[1] (\cal_ADR_A_reg[1] ),
        .\cal_ADR_A_reg[20] (\cal_ADR_A_reg[20] ),
        .\cal_ADR_A_reg[21] (\cal_ADR_A_reg[21] ),
        .\cal_ADR_A_reg[22] (\cal_ADR_A_reg[22] ),
        .\cal_ADR_A_reg[26] (\cal_ADR_A_reg[26] ),
        .\cal_ADR_A_reg[27] (\cal_ADR_A_reg[27] ),
        .\cal_ADR_A_reg[29] (\cal_ADR_A_reg[29] ),
        .\cal_ADR_A_reg[2] (\cal_ADR_A_reg[2] ),
        .\cal_ADR_A_reg[30] (\cal_ADR_A_reg[30] ),
        .\cal_ADR_A_reg[31] (\cal_ADR_A_reg[31] ),
        .\cal_ADR_A_reg[3] (\cal_ADR_A_reg[3] ),
        .\cal_ADR_A_reg[4] (\cal_ADR_A_reg[4] ),
        .\cal_ADR_A_reg[4]_0 (\cal_ADR_A_reg[4]_0 ),
        .\cal_ADR_B_reg[10] (\cal_ADR_B_reg[10] ),
        .\cal_ADR_B_reg[11] (\cal_ADR_B_reg[11] ),
        .\cal_ADR_B_reg[12] (\cal_ADR_B_reg[12] ),
        .\cal_ADR_B_reg[13] (\cal_ADR_B_reg[13] ),
        .\cal_ADR_B_reg[15] (\cal_ADR_B_reg[15] ),
        .\cal_ADR_B_reg[17] (\cal_ADR_B_reg[17] ),
        .\cal_ADR_B_reg[18] (\cal_ADR_B_reg[18] ),
        .\cal_ADR_B_reg[19] (\cal_ADR_B_reg[19] ),
        .\cal_ADR_B_reg[24] (\cal_ADR_B_reg[24] ),
        .\cal_ADR_B_reg[25] (\cal_ADR_B_reg[25] ),
        .\cal_ADR_B_reg[30] (\cal_ADR_B_reg[30] ),
        .\cal_ADR_B_reg[31] (\cal_ADR_B_reg[31] ),
        .\cal_ADR_B_reg[31]_0 (\cal_ADR_B_reg[31]_0 ),
        .\cal_CAS_A_reg[0] (\cal_CAS_A_reg[0] ),
        .\cal_CS_A_reg[0] (\cal_CS_A_reg[0] ),
        .\cal_CS_A_reg[4] (\cal_CS_A_reg[4] ),
        .\cal_CS_A_reg[5] (\cal_CS_A_reg[5] ),
        .\cal_CS_A_reg[6] (\cal_CS_A_reg[6] ),
        .\cal_CS_A_reg[7] (\cal_CS_A_reg[7] ),
        .\cal_CS_A_reg[7]_0 (\cal_CS_A_reg[7]_0 ),
        .\cal_CS_B_reg[5] (\cal_CS_B_reg[5] ),
        .\cal_CS_B_reg[7] (\cal_CS_B_reg[7] ),
        .cal_CS_n(cal_CS_n),
        .\cal_DMOut_n_A_reg[31] (\cal_DMOut_n_A_reg[31] ),
        .\cal_DQOut_A_reg[31] (\cal_DQOut_A_reg[31] ),
        .\cal_DQOut_A_reg[63] (\cal_DQOut_A_reg[63] ),
        .\cal_DQOut_post_reg[31] (\cal_DQOut_post_reg[31] ),
        .\cal_DQOut_post_reg[63] (\cal_DQOut_post_reg[63] ),
        .\cal_DQOut_pre_reg[31] (\cal_DQOut_pre_reg[31] ),
        .\cal_DQOut_pre_reg[63] (\cal_DQOut_pre_reg[63] ),
        .\cal_DQPat_A_reg[31] (\cal_DQPat_A_reg[31] ),
        .\cal_DQPat_A_reg[63] (\cal_DQPat_A_reg[63] ),
        .\cal_DQPat_B_reg[31] (\cal_DQPat_B_reg[31] ),
        .\cal_DQPat_B_reg[63] (\cal_DQPat_B_reg[63] ),
        .\cal_RAS_B_reg[0] (\cal_RAS_B_reg[0] ),
        .\cal_RAS_pre_reg[1] (u_ddr_cal_n_86),
        .\cal_RAS_pre_reg[2] (u_ddr_cal_n_87),
        .\cal_RST_CKE_ODT_PAR_reg[16] ({u_ddr_cal_n_109,u_ddr_cal_n_110,u_ddr_cal_n_111}),
        .\cal_RST_CKE_ODT_PAR_reg[16]_0 (\cal_RST_CKE_ODT_PAR_reg[16] ),
        .\cal_RST_CKE_ODT_PAR_reg[30] (\cal_RST_CKE_ODT_PAR_reg[30] ),
        .\cal_RST_CKE_ODT_PAR_reg[31] (\cal_RST_CKE_ODT_PAR_reg[31] ),
        .\cal_RST_CKE_ODT_PAR_reg[7] (cal_RESET_n_int),
        .\cal_RST_CKE_ODT_PAR_reg[9] (\cal_RST_CKE_ODT_PAR_reg[9] ),
        .cal_clear_fifo_rden(cal_clear_fifo_rden),
        .\cal_cmp_en_reg[7] (\cal_cmp_en_reg[7] ),
        .\cal_cs_pos_reg[1] (\cal_cs_pos_reg[1] ),
        .cal_oe_dis_low(cal_oe_dis_low),
        .\cal_oe_dis_low_reg[7] (\cal_oe_dis_low_reg[7] ),
        .cal_oe_dis_upp(cal_oe_dis_upp),
        .\cal_oe_dis_upp_reg[7] (\cal_oe_dis_upp_reg[7] ),
        .\cal_seq_a_a_dly_reg[7] (\cal_seq_a_a_dly_reg[7] ),
        .\cal_seq_a_b_dly_reg[7] (\cal_seq_a_b_dly_reg[7] ),
        .\cal_seq_b_a_dly_reg[7] (\cal_seq_b_a_dly_reg[7] ),
        .cal_seq_cnt_gt_0_reg(cal_seq_cnt_gt_0_reg),
        .\cal_seq_cnt_reg[13] (\cal_seq_cnt_reg[13] ),
        .\cal_seq_cnt_reg[31] (\cal_seq_cnt_reg[31] ),
        .\cal_seq_rd_cnt_reg[7] (\cal_seq_rd_cnt_reg[7] ),
        .\cal_seq_reg[2] (\cal_seq_reg[2] ),
        .cal_timer_reg(cal_timer_reg),
        .\cal_timer_reg[15] (\cal_timer_reg[15] ),
        .\cal_timer_reg[23] (\cal_timer_reg[23] ),
        .\cal_timer_reg[31] (\cal_timer_reg[31] ),
        .cal_timer_reg_0_sp_1(cal_timer_reg_0_sn_1),
        .cal_timer_reg_21_sp_1(cal_timer_reg_21_sn_1),
        .cal_timer_reg_24_sp_1(cal_timer_reg_24_sn_1),
        .cal_timer_reg_25_sp_1(cal_timer_reg_25_sn_1),
        .cal_timer_reg_28_sp_1(cal_timer_reg_28_sn_1),
        .cal_timer_reg_29_sp_1(cal_timer_reg_29_sn_1),
        .\clb2phy_wrcs0_low_reg[31] (\clb2phy_wrcs0_low_reg[31] ),
        .clear_gt_data_ready_flag(clear_gt_data_ready_flag),
        .clear_gt_data_ready_flag_reg(clear_gt_data_ready_flag_reg),
        .\cmp_byte_reg[2] (\cmp_byte_reg[2] ),
        .cnt_clr_access(cnt_clr_access),
        .cnt_clr_reg(cnt_clr),
        .cnt_clr_reg_0(cnt_clr_reg),
        .\cplx_CAS_reg[6] (\cplx_CAS_reg[6] ),
        .\cplx_RAS_reg[6] (u_ddr_cal_n_88),
        .\cplx_RAS_reg[6]_0 (u_ddr_cal_n_89),
        .cplx_cal_reg({u_ddr_cal_n_117,u_ddr_cal_n_118,u_ddr_cal_n_119,u_ddr_cal_n_120}),
        .\cplx_config_reg[0] (\cplx_config_reg[0] ),
        .\cplx_config_reg[16] (\cplx_config_reg[16] ),
        .\cplx_config_reg[16]_0 (\cplx_config_reg[16]_0 ),
        .\cplx_config_reg[1] (\cplx_config_reg[1] ),
        .\cplx_error_accum_reg[14] (\cplx_error_accum_reg[14] ),
        .\cplx_error_accum_reg[15] (\cplx_error_accum_reg[15] ),
        .\cplx_error_accum_reg[19] (\cplx_error_accum_reg[19] ),
        .\cplx_error_accum_reg[44] (\cplx_error_accum_reg[44] ),
        .\cplx_error_accum_reg[63] (\cplx_error_accum_reg[63] ),
        .cplx_status(cplx_status),
        .\dReg_reg[10] (u_ddr_mc_pi_n_12),
        .\dReg_reg[11] (u_ddr_mc_pi_n_10),
        .\dReg_reg[11]_0 (u_ddr_mc_pi_n_13),
        .\dReg_reg[11]_1 (u_ddr_mc_pi_n_14),
        .\dReg_reg[15] (Q),
        .\dReg_reg[8] (u_ddr_mc_pi_n_15),
        .\dReg_reg[8]_0 (u_ddr_mc_pi_n_16),
        .\dReg_reg[9] (u_ddr_mc_pi_n_8),
        .\dReg_reg[9]_0 (u_ddr_mc_pi_n_11),
        .\dReg_reg[9]_1 (u_ddr_mc_pi_n_9),
        .\delay_cntr_reg[2] (\delay_cntr_reg[2] ),
        .\dout_o_reg[11] (\dout_o_reg[11] ),
        .\dout_o_reg[11]_0 (\dout_o_reg[11]_0 ),
        .\dout_o_reg[5] (\dout_o_reg[5] ),
        .douta(douta),
        .\dqin_valid_shift_reg[0] (\u_ddr_cal_addr_decode/dqin_valid_shift_nxt ),
        .en_vtc(en_vtc),
        .ena(ena),
        .\genblk10[3].cal_DMOut_n_A_r_reg[24] (\genblk10[3].cal_DMOut_n_A_r_reg[24] ),
        .\genblk10[6].cal_DMOut_n_A_r_reg[48] (\genblk10[6].cal_DMOut_n_A_r_reg[48] ),
        .\genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8] (\genblk6[8].mcal_DQ0In_lrdimm_or_r_reg[8] ),
        .\genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9] (\genblk6[9].mcal_DQ0In_lrdimm_or_r_reg[9] ),
        .gt_data_ready_flag(gt_data_ready_flag),
        .gt_data_ready_flag_nxt(gt_data_ready_flag_nxt),
        .gt_data_ready_flag_reg(gt_data_ready_flag_reg),
        .in0({u_ddr_cal_n_1374,u_ddr_cal_n_1375}),
        .initDone(initDone),
        .\init_cal_BA_reg[15]_0 ({u_ddr_cal_n_100,u_ddr_cal_n_101,u_ddr_cal_n_102,u_ddr_cal_n_103,u_ddr_cal_n_104,u_ddr_cal_n_105,u_ddr_cal_n_106,u_ddr_cal_n_107,u_ddr_cal_n_108}),
        .\init_cal_BA_reg[7]_0 (cal_BA),
        .\init_cal_BG_reg[7]_0 (p_0_in),
        .io_addr_strobe_r1_reg(io_addr_strobe),
        .io_address(io_address),
        .\io_read_data_reg[31] (\io_read_data_reg[31] ),
        .io_ready_lvl_reg(io_ready_lvl_reg),
        .io_ready_reg(io_ready_reg),
        .io_ready_reg_0(io_ready_reg_0),
        .io_ready_reg_1(io_ready_reg_1),
        .io_write_data(io_write_data),
        .\lowCL0_reg[0]_0 (u_ddr_cal_n_1057),
        .\lowCL0_reg[12]_0 (u_ddr_cal_n_1033),
        .\lowCL0_reg[13]_0 (u_ddr_cal_n_2744),
        .\lowCL0_reg[13]_1 (u_ddr_cal_n_2746),
        .\lowCL0_reg[13]_2 (u_ddr_cal_n_2749),
        .\lowCL0_reg[14]_0 (u_ddr_cal_n_1031),
        .\lowCL0_reg[14]_1 (u_ddr_cal_n_1032),
        .\lowCL0_reg[14]_2 (u_ddr_cal_n_1074),
        .\lowCL0_reg[14]_3 ({\rdEn[2].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[2].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\lowCL0_reg[14]_4 (u_ddr_cal_n_2743),
        .\lowCL0_reg[14]_5 (u_ddr_cal_n_2745),
        .\lowCL0_reg[14]_6 (u_ddr_cal_n_2747),
        .\lowCL0_reg[15]_0 (u_ddr_cal_n_2748),
        .\lowCL0_reg[18]_0 (u_ddr_cal_n_1021),
        .\lowCL0_reg[19]_0 (u_ddr_cal_n_2676),
        .\lowCL0_reg[19]_1 (u_ddr_cal_n_2678),
        .\lowCL0_reg[19]_2 (u_ddr_cal_n_2681),
        .\lowCL0_reg[1]_0 (u_ddr_cal_n_2880),
        .\lowCL0_reg[1]_1 (u_ddr_cal_n_2882),
        .\lowCL0_reg[1]_2 (u_ddr_cal_n_2885),
        .\lowCL0_reg[20]_0 (u_ddr_cal_n_1019),
        .\lowCL0_reg[20]_1 (u_ddr_cal_n_1020),
        .\lowCL0_reg[20]_2 (u_ddr_cal_n_1070),
        .\lowCL0_reg[20]_3 ({\rdEn[3].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[3].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\lowCL0_reg[20]_4 (u_ddr_cal_n_2675),
        .\lowCL0_reg[20]_5 (u_ddr_cal_n_2677),
        .\lowCL0_reg[20]_6 (u_ddr_cal_n_2679),
        .\lowCL0_reg[21]_0 (u_ddr_cal_n_2680),
        .\lowCL0_reg[24]_0 (u_ddr_cal_n_985),
        .\lowCL0_reg[25]_0 (u_ddr_cal_n_2540),
        .\lowCL0_reg[25]_1 (u_ddr_cal_n_2542),
        .\lowCL0_reg[25]_2 (u_ddr_cal_n_2545),
        .\lowCL0_reg[26]_0 (u_ddr_cal_n_983),
        .\lowCL0_reg[26]_1 (u_ddr_cal_n_984),
        .\lowCL0_reg[26]_2 (u_ddr_cal_n_1018),
        .\lowCL0_reg[26]_3 ({\rdEn[4].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[4].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\lowCL0_reg[26]_4 (u_ddr_cal_n_2539),
        .\lowCL0_reg[26]_5 (u_ddr_cal_n_2541),
        .\lowCL0_reg[26]_6 (u_ddr_cal_n_2543),
        .\lowCL0_reg[27]_0 (u_ddr_cal_n_2544),
        .\lowCL0_reg[2]_0 (u_ddr_cal_n_1055),
        .\lowCL0_reg[2]_1 (u_ddr_cal_n_1056),
        .\lowCL0_reg[2]_2 (u_ddr_cal_n_1082),
        .\lowCL0_reg[2]_3 ({\rdEn[0].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[0].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\lowCL0_reg[2]_4 (u_ddr_cal_n_2879),
        .\lowCL0_reg[2]_5 (u_ddr_cal_n_2881),
        .\lowCL0_reg[2]_6 (u_ddr_cal_n_2883),
        .\lowCL0_reg[30]_0 (u_ddr_cal_n_973),
        .\lowCL0_reg[31]_0 (u_ddr_cal_n_2472),
        .\lowCL0_reg[31]_1 (u_ddr_cal_n_2474),
        .\lowCL0_reg[31]_2 (u_ddr_cal_n_2477),
        .\lowCL0_reg[32]_0 (u_ddr_cal_n_971),
        .\lowCL0_reg[32]_1 (u_ddr_cal_n_972),
        .\lowCL0_reg[32]_2 (u_ddr_cal_n_1014),
        .\lowCL0_reg[32]_3 ({\rdEn[5].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[5].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\lowCL0_reg[32]_4 (u_ddr_cal_n_2471),
        .\lowCL0_reg[32]_5 (u_ddr_cal_n_2473),
        .\lowCL0_reg[32]_6 (u_ddr_cal_n_2475),
        .\lowCL0_reg[33]_0 (u_ddr_cal_n_2476),
        .\lowCL0_reg[36]_0 (u_ddr_cal_n_997),
        .\lowCL0_reg[37]_0 (u_ddr_cal_n_2608),
        .\lowCL0_reg[37]_1 (u_ddr_cal_n_2610),
        .\lowCL0_reg[37]_2 (u_ddr_cal_n_2613),
        .\lowCL0_reg[38]_0 (u_ddr_cal_n_995),
        .\lowCL0_reg[38]_1 (u_ddr_cal_n_996),
        .\lowCL0_reg[38]_2 (u_ddr_cal_n_1010),
        .\lowCL0_reg[38]_3 ({\rdEn[6].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[6].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\lowCL0_reg[38]_4 (u_ddr_cal_n_2607),
        .\lowCL0_reg[38]_5 (u_ddr_cal_n_2609),
        .\lowCL0_reg[38]_6 (u_ddr_cal_n_2611),
        .\lowCL0_reg[39]_0 (u_ddr_cal_n_2612),
        .\lowCL0_reg[3]_0 (u_ddr_cal_n_2884),
        .\lowCL0_reg[42]_0 (u_ddr_cal_n_925),
        .\lowCL0_reg[43]_0 (u_ddr_cal_n_2268),
        .\lowCL0_reg[43]_1 (u_ddr_cal_n_2270),
        .\lowCL0_reg[43]_2 (u_ddr_cal_n_2273),
        .\lowCL0_reg[44]_0 (u_ddr_cal_n_923),
        .\lowCL0_reg[44]_1 (u_ddr_cal_n_924),
        .\lowCL0_reg[44]_2 (u_ddr_cal_n_962),
        .\lowCL0_reg[44]_3 ({\rdEn[7].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[7].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\lowCL0_reg[44]_4 (u_ddr_cal_n_2267),
        .\lowCL0_reg[44]_5 (u_ddr_cal_n_2269),
        .\lowCL0_reg[44]_6 (u_ddr_cal_n_2271),
        .\lowCL0_reg[45]_0 (u_ddr_cal_n_2272),
        .\lowCL0_reg[6]_0 (u_ddr_cal_n_1045),
        .\lowCL0_reg[7]_0 (u_ddr_cal_n_2812),
        .\lowCL0_reg[7]_1 (u_ddr_cal_n_2814),
        .\lowCL0_reg[7]_2 (u_ddr_cal_n_2817),
        .\lowCL0_reg[8]_0 (u_ddr_cal_n_1043),
        .\lowCL0_reg[8]_1 (u_ddr_cal_n_1044),
        .\lowCL0_reg[8]_2 (u_ddr_cal_n_1078),
        .\lowCL0_reg[8]_3 ({\rdEn[1].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[1].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\lowCL0_reg[8]_4 (u_ddr_cal_n_2811),
        .\lowCL0_reg[8]_5 (u_ddr_cal_n_2813),
        .\lowCL0_reg[8]_6 (u_ddr_cal_n_2815),
        .\lowCL0_reg[9]_0 (u_ddr_cal_n_2816),
        .\lowCL1_reg[0]_0 (u_ddr_cal_n_1060),
        .\lowCL1_reg[12]_0 (u_ddr_cal_n_1036),
        .\lowCL1_reg[13]_0 (u_ddr_cal_n_2750),
        .\lowCL1_reg[13]_1 (u_ddr_cal_n_2751),
        .\lowCL1_reg[13]_2 (u_ddr_cal_n_2755),
        .\lowCL1_reg[13]_3 (u_ddr_cal_n_2757),
        .\lowCL1_reg[13]_4 (u_ddr_cal_n_2759),
        .\lowCL1_reg[13]_5 (u_ddr_cal_n_2761),
        .\lowCL1_reg[13]_6 (u_ddr_cal_n_2762),
        .\lowCL1_reg[13]_7 (u_ddr_cal_n_2764),
        .\lowCL1_reg[13]_8 (u_ddr_cal_n_2765),
        .\lowCL1_reg[14]_0 (u_ddr_cal_n_1034),
        .\lowCL1_reg[14]_1 (u_ddr_cal_n_1035),
        .\lowCL1_reg[14]_2 (u_ddr_cal_n_1073),
        .\lowCL1_reg[14]_3 ({u_ddr_cal_n_2752,u_ddr_cal_n_2753,u_ddr_cal_n_2754}),
        .\lowCL1_reg[14]_4 (u_ddr_cal_n_2756),
        .\lowCL1_reg[14]_5 (u_ddr_cal_n_2758),
        .\lowCL1_reg[14]_6 (u_ddr_cal_n_2760),
        .\lowCL1_reg[14]_7 (u_ddr_cal_n_2766),
        .\lowCL1_reg[15]_0 (u_ddr_cal_n_2763),
        .\lowCL1_reg[18]_0 (u_ddr_cal_n_1024),
        .\lowCL1_reg[19]_0 (u_ddr_cal_n_2682),
        .\lowCL1_reg[19]_1 (u_ddr_cal_n_2683),
        .\lowCL1_reg[19]_2 (u_ddr_cal_n_2687),
        .\lowCL1_reg[19]_3 (u_ddr_cal_n_2689),
        .\lowCL1_reg[19]_4 (u_ddr_cal_n_2691),
        .\lowCL1_reg[19]_5 (u_ddr_cal_n_2693),
        .\lowCL1_reg[19]_6 (u_ddr_cal_n_2694),
        .\lowCL1_reg[19]_7 (u_ddr_cal_n_2696),
        .\lowCL1_reg[19]_8 (u_ddr_cal_n_2697),
        .\lowCL1_reg[1]_0 (u_ddr_cal_n_2886),
        .\lowCL1_reg[1]_1 (u_ddr_cal_n_2887),
        .\lowCL1_reg[1]_2 (u_ddr_cal_n_2891),
        .\lowCL1_reg[1]_3 (u_ddr_cal_n_2893),
        .\lowCL1_reg[1]_4 (u_ddr_cal_n_2895),
        .\lowCL1_reg[1]_5 (u_ddr_cal_n_2897),
        .\lowCL1_reg[1]_6 (u_ddr_cal_n_2898),
        .\lowCL1_reg[1]_7 (u_ddr_cal_n_2900),
        .\lowCL1_reg[1]_8 (u_ddr_cal_n_2901),
        .\lowCL1_reg[20]_0 (u_ddr_cal_n_1022),
        .\lowCL1_reg[20]_1 (u_ddr_cal_n_1023),
        .\lowCL1_reg[20]_2 (u_ddr_cal_n_1069),
        .\lowCL1_reg[20]_3 ({u_ddr_cal_n_2684,u_ddr_cal_n_2685,u_ddr_cal_n_2686}),
        .\lowCL1_reg[20]_4 (u_ddr_cal_n_2688),
        .\lowCL1_reg[20]_5 (u_ddr_cal_n_2690),
        .\lowCL1_reg[20]_6 (u_ddr_cal_n_2692),
        .\lowCL1_reg[20]_7 (u_ddr_cal_n_2698),
        .\lowCL1_reg[21]_0 (u_ddr_cal_n_2695),
        .\lowCL1_reg[24]_0 (u_ddr_cal_n_988),
        .\lowCL1_reg[25]_0 (u_ddr_cal_n_2546),
        .\lowCL1_reg[25]_1 (u_ddr_cal_n_2547),
        .\lowCL1_reg[25]_2 (u_ddr_cal_n_2551),
        .\lowCL1_reg[25]_3 (u_ddr_cal_n_2553),
        .\lowCL1_reg[25]_4 (u_ddr_cal_n_2555),
        .\lowCL1_reg[25]_5 (u_ddr_cal_n_2557),
        .\lowCL1_reg[25]_6 (u_ddr_cal_n_2558),
        .\lowCL1_reg[25]_7 (u_ddr_cal_n_2560),
        .\lowCL1_reg[25]_8 (u_ddr_cal_n_2561),
        .\lowCL1_reg[26]_0 (u_ddr_cal_n_986),
        .\lowCL1_reg[26]_1 (u_ddr_cal_n_987),
        .\lowCL1_reg[26]_2 (u_ddr_cal_n_1017),
        .\lowCL1_reg[26]_3 ({u_ddr_cal_n_2548,u_ddr_cal_n_2549,u_ddr_cal_n_2550}),
        .\lowCL1_reg[26]_4 (u_ddr_cal_n_2552),
        .\lowCL1_reg[26]_5 (u_ddr_cal_n_2554),
        .\lowCL1_reg[26]_6 (u_ddr_cal_n_2556),
        .\lowCL1_reg[26]_7 (u_ddr_cal_n_2562),
        .\lowCL1_reg[27]_0 (u_ddr_cal_n_2559),
        .\lowCL1_reg[2]_0 (u_ddr_cal_n_1058),
        .\lowCL1_reg[2]_1 (u_ddr_cal_n_1059),
        .\lowCL1_reg[2]_2 (u_ddr_cal_n_1081),
        .\lowCL1_reg[2]_3 ({u_ddr_cal_n_2888,u_ddr_cal_n_2889,u_ddr_cal_n_2890}),
        .\lowCL1_reg[2]_4 (u_ddr_cal_n_2892),
        .\lowCL1_reg[2]_5 (u_ddr_cal_n_2894),
        .\lowCL1_reg[2]_6 (u_ddr_cal_n_2896),
        .\lowCL1_reg[2]_7 (u_ddr_cal_n_2902),
        .\lowCL1_reg[30]_0 (u_ddr_cal_n_976),
        .\lowCL1_reg[31]_0 (u_ddr_cal_n_2478),
        .\lowCL1_reg[31]_1 (u_ddr_cal_n_2479),
        .\lowCL1_reg[31]_2 (u_ddr_cal_n_2483),
        .\lowCL1_reg[31]_3 (u_ddr_cal_n_2485),
        .\lowCL1_reg[31]_4 (u_ddr_cal_n_2487),
        .\lowCL1_reg[31]_5 (u_ddr_cal_n_2489),
        .\lowCL1_reg[31]_6 (u_ddr_cal_n_2490),
        .\lowCL1_reg[31]_7 (u_ddr_cal_n_2492),
        .\lowCL1_reg[31]_8 (u_ddr_cal_n_2493),
        .\lowCL1_reg[32]_0 (u_ddr_cal_n_974),
        .\lowCL1_reg[32]_1 (u_ddr_cal_n_975),
        .\lowCL1_reg[32]_2 (u_ddr_cal_n_1013),
        .\lowCL1_reg[32]_3 ({u_ddr_cal_n_2480,u_ddr_cal_n_2481,u_ddr_cal_n_2482}),
        .\lowCL1_reg[32]_4 (u_ddr_cal_n_2484),
        .\lowCL1_reg[32]_5 (u_ddr_cal_n_2486),
        .\lowCL1_reg[32]_6 (u_ddr_cal_n_2488),
        .\lowCL1_reg[32]_7 (u_ddr_cal_n_2494),
        .\lowCL1_reg[33]_0 (u_ddr_cal_n_2491),
        .\lowCL1_reg[36]_0 (u_ddr_cal_n_1000),
        .\lowCL1_reg[37]_0 (u_ddr_cal_n_2614),
        .\lowCL1_reg[37]_1 (u_ddr_cal_n_2615),
        .\lowCL1_reg[37]_2 (u_ddr_cal_n_2619),
        .\lowCL1_reg[37]_3 (u_ddr_cal_n_2621),
        .\lowCL1_reg[37]_4 (u_ddr_cal_n_2623),
        .\lowCL1_reg[37]_5 (u_ddr_cal_n_2625),
        .\lowCL1_reg[37]_6 (u_ddr_cal_n_2626),
        .\lowCL1_reg[37]_7 (u_ddr_cal_n_2628),
        .\lowCL1_reg[37]_8 (u_ddr_cal_n_2629),
        .\lowCL1_reg[38]_0 (u_ddr_cal_n_998),
        .\lowCL1_reg[38]_1 (u_ddr_cal_n_999),
        .\lowCL1_reg[38]_2 (u_ddr_cal_n_1009),
        .\lowCL1_reg[38]_3 ({u_ddr_cal_n_2616,u_ddr_cal_n_2617,u_ddr_cal_n_2618}),
        .\lowCL1_reg[38]_4 (u_ddr_cal_n_2620),
        .\lowCL1_reg[38]_5 (u_ddr_cal_n_2622),
        .\lowCL1_reg[38]_6 (u_ddr_cal_n_2624),
        .\lowCL1_reg[38]_7 (u_ddr_cal_n_2630),
        .\lowCL1_reg[39]_0 (u_ddr_cal_n_2627),
        .\lowCL1_reg[3]_0 (u_ddr_cal_n_2899),
        .\lowCL1_reg[42]_0 (u_ddr_cal_n_928),
        .\lowCL1_reg[43]_0 (u_ddr_cal_n_2274),
        .\lowCL1_reg[43]_1 (u_ddr_cal_n_2275),
        .\lowCL1_reg[43]_2 (u_ddr_cal_n_2279),
        .\lowCL1_reg[43]_3 (u_ddr_cal_n_2281),
        .\lowCL1_reg[43]_4 (u_ddr_cal_n_2283),
        .\lowCL1_reg[43]_5 (u_ddr_cal_n_2285),
        .\lowCL1_reg[43]_6 (u_ddr_cal_n_2286),
        .\lowCL1_reg[43]_7 (u_ddr_cal_n_2288),
        .\lowCL1_reg[43]_8 (u_ddr_cal_n_2289),
        .\lowCL1_reg[44]_0 (u_ddr_cal_n_926),
        .\lowCL1_reg[44]_1 (u_ddr_cal_n_927),
        .\lowCL1_reg[44]_2 (u_ddr_cal_n_961),
        .\lowCL1_reg[44]_3 ({u_ddr_cal_n_2276,u_ddr_cal_n_2277,u_ddr_cal_n_2278}),
        .\lowCL1_reg[44]_4 (u_ddr_cal_n_2280),
        .\lowCL1_reg[44]_5 (u_ddr_cal_n_2282),
        .\lowCL1_reg[44]_6 (u_ddr_cal_n_2284),
        .\lowCL1_reg[44]_7 (u_ddr_cal_n_2290),
        .\lowCL1_reg[45]_0 (u_ddr_cal_n_2287),
        .\lowCL1_reg[6]_0 (u_ddr_cal_n_1048),
        .\lowCL1_reg[7]_0 (u_ddr_cal_n_2818),
        .\lowCL1_reg[7]_1 (u_ddr_cal_n_2819),
        .\lowCL1_reg[7]_2 (u_ddr_cal_n_2823),
        .\lowCL1_reg[7]_3 (u_ddr_cal_n_2825),
        .\lowCL1_reg[7]_4 (u_ddr_cal_n_2827),
        .\lowCL1_reg[7]_5 (u_ddr_cal_n_2829),
        .\lowCL1_reg[7]_6 (u_ddr_cal_n_2830),
        .\lowCL1_reg[7]_7 (u_ddr_cal_n_2832),
        .\lowCL1_reg[7]_8 (u_ddr_cal_n_2833),
        .\lowCL1_reg[8]_0 (u_ddr_cal_n_1046),
        .\lowCL1_reg[8]_1 (u_ddr_cal_n_1047),
        .\lowCL1_reg[8]_2 (u_ddr_cal_n_1077),
        .\lowCL1_reg[8]_3 ({u_ddr_cal_n_2820,u_ddr_cal_n_2821,u_ddr_cal_n_2822}),
        .\lowCL1_reg[8]_4 (u_ddr_cal_n_2824),
        .\lowCL1_reg[8]_5 (u_ddr_cal_n_2826),
        .\lowCL1_reg[8]_6 (u_ddr_cal_n_2828),
        .\lowCL1_reg[8]_7 (u_ddr_cal_n_2834),
        .\lowCL1_reg[9]_0 (u_ddr_cal_n_2831),
        .\lowCL2_reg[0]_0 (u_ddr_cal_n_1063),
        .\lowCL2_reg[12]_0 (u_ddr_cal_n_1039),
        .\lowCL2_reg[13]_0 (u_ddr_cal_n_2767),
        .\lowCL2_reg[13]_1 (u_ddr_cal_n_2768),
        .\lowCL2_reg[13]_2 (u_ddr_cal_n_2772),
        .\lowCL2_reg[13]_3 (u_ddr_cal_n_2774),
        .\lowCL2_reg[13]_4 (u_ddr_cal_n_2776),
        .\lowCL2_reg[13]_5 (u_ddr_cal_n_2778),
        .\lowCL2_reg[13]_6 (u_ddr_cal_n_2779),
        .\lowCL2_reg[13]_7 (u_ddr_cal_n_2781),
        .\lowCL2_reg[13]_8 (u_ddr_cal_n_2782),
        .\lowCL2_reg[14]_0 (u_ddr_cal_n_1037),
        .\lowCL2_reg[14]_1 (u_ddr_cal_n_1038),
        .\lowCL2_reg[14]_2 (u_ddr_cal_n_1072),
        .\lowCL2_reg[14]_3 ({u_ddr_cal_n_2769,u_ddr_cal_n_2770,u_ddr_cal_n_2771}),
        .\lowCL2_reg[14]_4 (u_ddr_cal_n_2773),
        .\lowCL2_reg[14]_5 (u_ddr_cal_n_2775),
        .\lowCL2_reg[14]_6 (u_ddr_cal_n_2777),
        .\lowCL2_reg[14]_7 (u_ddr_cal_n_2783),
        .\lowCL2_reg[15]_0 (u_ddr_cal_n_2780),
        .\lowCL2_reg[18]_0 (u_ddr_cal_n_1027),
        .\lowCL2_reg[19]_0 (u_ddr_cal_n_2699),
        .\lowCL2_reg[19]_1 (u_ddr_cal_n_2700),
        .\lowCL2_reg[19]_2 (u_ddr_cal_n_2704),
        .\lowCL2_reg[19]_3 (u_ddr_cal_n_2706),
        .\lowCL2_reg[19]_4 (u_ddr_cal_n_2708),
        .\lowCL2_reg[19]_5 (u_ddr_cal_n_2710),
        .\lowCL2_reg[19]_6 (u_ddr_cal_n_2711),
        .\lowCL2_reg[19]_7 (u_ddr_cal_n_2713),
        .\lowCL2_reg[19]_8 (u_ddr_cal_n_2714),
        .\lowCL2_reg[1]_0 (u_ddr_cal_n_2903),
        .\lowCL2_reg[1]_1 (u_ddr_cal_n_2904),
        .\lowCL2_reg[1]_2 (u_ddr_cal_n_2908),
        .\lowCL2_reg[1]_3 (u_ddr_cal_n_2910),
        .\lowCL2_reg[1]_4 (u_ddr_cal_n_2912),
        .\lowCL2_reg[1]_5 (u_ddr_cal_n_2914),
        .\lowCL2_reg[1]_6 (u_ddr_cal_n_2915),
        .\lowCL2_reg[1]_7 (u_ddr_cal_n_2917),
        .\lowCL2_reg[1]_8 (u_ddr_cal_n_2918),
        .\lowCL2_reg[20]_0 (u_ddr_cal_n_1025),
        .\lowCL2_reg[20]_1 (u_ddr_cal_n_1026),
        .\lowCL2_reg[20]_2 (u_ddr_cal_n_1068),
        .\lowCL2_reg[20]_3 ({u_ddr_cal_n_2701,u_ddr_cal_n_2702,u_ddr_cal_n_2703}),
        .\lowCL2_reg[20]_4 (u_ddr_cal_n_2705),
        .\lowCL2_reg[20]_5 (u_ddr_cal_n_2707),
        .\lowCL2_reg[20]_6 (u_ddr_cal_n_2709),
        .\lowCL2_reg[20]_7 (u_ddr_cal_n_2715),
        .\lowCL2_reg[21]_0 (u_ddr_cal_n_2712),
        .\lowCL2_reg[24]_0 (u_ddr_cal_n_991),
        .\lowCL2_reg[25]_0 (u_ddr_cal_n_2563),
        .\lowCL2_reg[25]_1 (u_ddr_cal_n_2564),
        .\lowCL2_reg[25]_2 (u_ddr_cal_n_2568),
        .\lowCL2_reg[25]_3 (u_ddr_cal_n_2570),
        .\lowCL2_reg[25]_4 (u_ddr_cal_n_2572),
        .\lowCL2_reg[25]_5 (u_ddr_cal_n_2574),
        .\lowCL2_reg[25]_6 (u_ddr_cal_n_2575),
        .\lowCL2_reg[25]_7 (u_ddr_cal_n_2577),
        .\lowCL2_reg[25]_8 (u_ddr_cal_n_2578),
        .\lowCL2_reg[26]_0 (u_ddr_cal_n_989),
        .\lowCL2_reg[26]_1 (u_ddr_cal_n_990),
        .\lowCL2_reg[26]_2 (u_ddr_cal_n_1016),
        .\lowCL2_reg[26]_3 ({u_ddr_cal_n_2565,u_ddr_cal_n_2566,u_ddr_cal_n_2567}),
        .\lowCL2_reg[26]_4 (u_ddr_cal_n_2569),
        .\lowCL2_reg[26]_5 (u_ddr_cal_n_2571),
        .\lowCL2_reg[26]_6 (u_ddr_cal_n_2573),
        .\lowCL2_reg[26]_7 (u_ddr_cal_n_2579),
        .\lowCL2_reg[27]_0 (u_ddr_cal_n_2576),
        .\lowCL2_reg[2]_0 (u_ddr_cal_n_1061),
        .\lowCL2_reg[2]_1 (u_ddr_cal_n_1062),
        .\lowCL2_reg[2]_2 (u_ddr_cal_n_1080),
        .\lowCL2_reg[2]_3 ({u_ddr_cal_n_2905,u_ddr_cal_n_2906,u_ddr_cal_n_2907}),
        .\lowCL2_reg[2]_4 (u_ddr_cal_n_2909),
        .\lowCL2_reg[2]_5 (u_ddr_cal_n_2911),
        .\lowCL2_reg[2]_6 (u_ddr_cal_n_2913),
        .\lowCL2_reg[2]_7 (u_ddr_cal_n_2919),
        .\lowCL2_reg[30]_0 (u_ddr_cal_n_979),
        .\lowCL2_reg[31]_0 (u_ddr_cal_n_2495),
        .\lowCL2_reg[31]_1 (u_ddr_cal_n_2496),
        .\lowCL2_reg[31]_2 (u_ddr_cal_n_2500),
        .\lowCL2_reg[31]_3 (u_ddr_cal_n_2502),
        .\lowCL2_reg[31]_4 (u_ddr_cal_n_2504),
        .\lowCL2_reg[31]_5 (u_ddr_cal_n_2506),
        .\lowCL2_reg[31]_6 (u_ddr_cal_n_2507),
        .\lowCL2_reg[31]_7 (u_ddr_cal_n_2509),
        .\lowCL2_reg[31]_8 (u_ddr_cal_n_2510),
        .\lowCL2_reg[32]_0 (u_ddr_cal_n_977),
        .\lowCL2_reg[32]_1 (u_ddr_cal_n_978),
        .\lowCL2_reg[32]_2 (u_ddr_cal_n_1012),
        .\lowCL2_reg[32]_3 ({u_ddr_cal_n_2497,u_ddr_cal_n_2498,u_ddr_cal_n_2499}),
        .\lowCL2_reg[32]_4 (u_ddr_cal_n_2501),
        .\lowCL2_reg[32]_5 (u_ddr_cal_n_2503),
        .\lowCL2_reg[32]_6 (u_ddr_cal_n_2505),
        .\lowCL2_reg[32]_7 (u_ddr_cal_n_2511),
        .\lowCL2_reg[33]_0 (u_ddr_cal_n_2508),
        .\lowCL2_reg[36]_0 (u_ddr_cal_n_1003),
        .\lowCL2_reg[37]_0 (u_ddr_cal_n_2631),
        .\lowCL2_reg[37]_1 (u_ddr_cal_n_2632),
        .\lowCL2_reg[37]_2 (u_ddr_cal_n_2636),
        .\lowCL2_reg[37]_3 (u_ddr_cal_n_2638),
        .\lowCL2_reg[37]_4 (u_ddr_cal_n_2640),
        .\lowCL2_reg[37]_5 (u_ddr_cal_n_2642),
        .\lowCL2_reg[37]_6 (u_ddr_cal_n_2643),
        .\lowCL2_reg[37]_7 (u_ddr_cal_n_2645),
        .\lowCL2_reg[37]_8 (u_ddr_cal_n_2646),
        .\lowCL2_reg[38]_0 (u_ddr_cal_n_1001),
        .\lowCL2_reg[38]_1 (u_ddr_cal_n_1002),
        .\lowCL2_reg[38]_2 (u_ddr_cal_n_1008),
        .\lowCL2_reg[38]_3 ({u_ddr_cal_n_2633,u_ddr_cal_n_2634,u_ddr_cal_n_2635}),
        .\lowCL2_reg[38]_4 (u_ddr_cal_n_2637),
        .\lowCL2_reg[38]_5 (u_ddr_cal_n_2639),
        .\lowCL2_reg[38]_6 (u_ddr_cal_n_2641),
        .\lowCL2_reg[38]_7 (u_ddr_cal_n_2647),
        .\lowCL2_reg[39]_0 (u_ddr_cal_n_2644),
        .\lowCL2_reg[3]_0 (u_ddr_cal_n_2916),
        .\lowCL2_reg[42]_0 (u_ddr_cal_n_931),
        .\lowCL2_reg[43]_0 (u_ddr_cal_n_2291),
        .\lowCL2_reg[43]_1 (u_ddr_cal_n_2292),
        .\lowCL2_reg[43]_2 (u_ddr_cal_n_2296),
        .\lowCL2_reg[43]_3 (u_ddr_cal_n_2298),
        .\lowCL2_reg[43]_4 (u_ddr_cal_n_2300),
        .\lowCL2_reg[43]_5 (u_ddr_cal_n_2302),
        .\lowCL2_reg[43]_6 (u_ddr_cal_n_2303),
        .\lowCL2_reg[43]_7 (u_ddr_cal_n_2305),
        .\lowCL2_reg[43]_8 (u_ddr_cal_n_2306),
        .\lowCL2_reg[44]_0 (u_ddr_cal_n_929),
        .\lowCL2_reg[44]_1 (u_ddr_cal_n_930),
        .\lowCL2_reg[44]_2 (u_ddr_cal_n_960),
        .\lowCL2_reg[44]_3 ({u_ddr_cal_n_2293,u_ddr_cal_n_2294,u_ddr_cal_n_2295}),
        .\lowCL2_reg[44]_4 (u_ddr_cal_n_2297),
        .\lowCL2_reg[44]_5 (u_ddr_cal_n_2299),
        .\lowCL2_reg[44]_6 (u_ddr_cal_n_2301),
        .\lowCL2_reg[44]_7 (u_ddr_cal_n_2307),
        .\lowCL2_reg[45]_0 (u_ddr_cal_n_2304),
        .\lowCL2_reg[6]_0 (u_ddr_cal_n_1051),
        .\lowCL2_reg[7]_0 (u_ddr_cal_n_2835),
        .\lowCL2_reg[7]_1 (u_ddr_cal_n_2836),
        .\lowCL2_reg[7]_2 (u_ddr_cal_n_2840),
        .\lowCL2_reg[7]_3 (u_ddr_cal_n_2842),
        .\lowCL2_reg[7]_4 (u_ddr_cal_n_2844),
        .\lowCL2_reg[7]_5 (u_ddr_cal_n_2846),
        .\lowCL2_reg[7]_6 (u_ddr_cal_n_2847),
        .\lowCL2_reg[7]_7 (u_ddr_cal_n_2849),
        .\lowCL2_reg[7]_8 (u_ddr_cal_n_2850),
        .\lowCL2_reg[8]_0 (u_ddr_cal_n_1049),
        .\lowCL2_reg[8]_1 (u_ddr_cal_n_1050),
        .\lowCL2_reg[8]_2 (u_ddr_cal_n_1076),
        .\lowCL2_reg[8]_3 ({u_ddr_cal_n_2837,u_ddr_cal_n_2838,u_ddr_cal_n_2839}),
        .\lowCL2_reg[8]_4 (u_ddr_cal_n_2841),
        .\lowCL2_reg[8]_5 (u_ddr_cal_n_2843),
        .\lowCL2_reg[8]_6 (u_ddr_cal_n_2845),
        .\lowCL2_reg[8]_7 (u_ddr_cal_n_2851),
        .\lowCL2_reg[9]_0 (u_ddr_cal_n_2848),
        .\lowCL3_reg[0]_0 (u_ddr_cal_n_1066),
        .\lowCL3_reg[12]_0 (u_ddr_cal_n_1042),
        .\lowCL3_reg[13]_0 (u_ddr_cal_n_2784),
        .\lowCL3_reg[13]_1 (u_ddr_cal_n_2785),
        .\lowCL3_reg[13]_2 (u_ddr_cal_n_2789),
        .\lowCL3_reg[13]_3 (u_ddr_cal_n_2791),
        .\lowCL3_reg[13]_4 (u_ddr_cal_n_2793),
        .\lowCL3_reg[13]_5 (u_ddr_cal_n_2795),
        .\lowCL3_reg[13]_6 (u_ddr_cal_n_2796),
        .\lowCL3_reg[13]_7 (u_ddr_cal_n_2798),
        .\lowCL3_reg[13]_8 (u_ddr_cal_n_2799),
        .\lowCL3_reg[14]_0 (u_ddr_cal_n_1040),
        .\lowCL3_reg[14]_1 (u_ddr_cal_n_1041),
        .\lowCL3_reg[14]_2 (u_ddr_cal_n_1071),
        .\lowCL3_reg[14]_3 ({u_ddr_cal_n_2786,u_ddr_cal_n_2787,u_ddr_cal_n_2788}),
        .\lowCL3_reg[14]_4 (u_ddr_cal_n_2790),
        .\lowCL3_reg[14]_5 (u_ddr_cal_n_2792),
        .\lowCL3_reg[14]_6 (u_ddr_cal_n_2794),
        .\lowCL3_reg[14]_7 (u_ddr_cal_n_2800),
        .\lowCL3_reg[15]_0 (u_ddr_cal_n_2797),
        .\lowCL3_reg[18]_0 (u_ddr_cal_n_1030),
        .\lowCL3_reg[19]_0 (u_ddr_cal_n_2716),
        .\lowCL3_reg[19]_1 (u_ddr_cal_n_2717),
        .\lowCL3_reg[19]_2 (u_ddr_cal_n_2721),
        .\lowCL3_reg[19]_3 (u_ddr_cal_n_2723),
        .\lowCL3_reg[19]_4 (u_ddr_cal_n_2725),
        .\lowCL3_reg[19]_5 (u_ddr_cal_n_2727),
        .\lowCL3_reg[19]_6 (u_ddr_cal_n_2728),
        .\lowCL3_reg[19]_7 (u_ddr_cal_n_2730),
        .\lowCL3_reg[19]_8 (u_ddr_cal_n_2731),
        .\lowCL3_reg[1]_0 (u_ddr_cal_n_2920),
        .\lowCL3_reg[1]_1 (u_ddr_cal_n_2921),
        .\lowCL3_reg[1]_2 (u_ddr_cal_n_2925),
        .\lowCL3_reg[1]_3 (u_ddr_cal_n_2927),
        .\lowCL3_reg[1]_4 (u_ddr_cal_n_2929),
        .\lowCL3_reg[1]_5 (u_ddr_cal_n_2931),
        .\lowCL3_reg[1]_6 (u_ddr_cal_n_2932),
        .\lowCL3_reg[1]_7 (u_ddr_cal_n_2934),
        .\lowCL3_reg[1]_8 (u_ddr_cal_n_2935),
        .\lowCL3_reg[20]_0 (u_ddr_cal_n_1028),
        .\lowCL3_reg[20]_1 (u_ddr_cal_n_1029),
        .\lowCL3_reg[20]_2 (u_ddr_cal_n_1067),
        .\lowCL3_reg[20]_3 ({u_ddr_cal_n_2718,u_ddr_cal_n_2719,u_ddr_cal_n_2720}),
        .\lowCL3_reg[20]_4 (u_ddr_cal_n_2722),
        .\lowCL3_reg[20]_5 (u_ddr_cal_n_2724),
        .\lowCL3_reg[20]_6 (u_ddr_cal_n_2726),
        .\lowCL3_reg[20]_7 (u_ddr_cal_n_2732),
        .\lowCL3_reg[21]_0 (u_ddr_cal_n_2729),
        .\lowCL3_reg[24]_0 (u_ddr_cal_n_994),
        .\lowCL3_reg[25]_0 (u_ddr_cal_n_2580),
        .\lowCL3_reg[25]_1 (u_ddr_cal_n_2581),
        .\lowCL3_reg[25]_2 (u_ddr_cal_n_2585),
        .\lowCL3_reg[25]_3 (u_ddr_cal_n_2587),
        .\lowCL3_reg[25]_4 (u_ddr_cal_n_2589),
        .\lowCL3_reg[25]_5 (u_ddr_cal_n_2591),
        .\lowCL3_reg[25]_6 (u_ddr_cal_n_2592),
        .\lowCL3_reg[25]_7 (u_ddr_cal_n_2594),
        .\lowCL3_reg[25]_8 (u_ddr_cal_n_2595),
        .\lowCL3_reg[26]_0 (u_ddr_cal_n_992),
        .\lowCL3_reg[26]_1 (u_ddr_cal_n_993),
        .\lowCL3_reg[26]_2 (u_ddr_cal_n_1015),
        .\lowCL3_reg[26]_3 ({u_ddr_cal_n_2582,u_ddr_cal_n_2583,u_ddr_cal_n_2584}),
        .\lowCL3_reg[26]_4 (u_ddr_cal_n_2586),
        .\lowCL3_reg[26]_5 (u_ddr_cal_n_2588),
        .\lowCL3_reg[26]_6 (u_ddr_cal_n_2590),
        .\lowCL3_reg[26]_7 (u_ddr_cal_n_2596),
        .\lowCL3_reg[27]_0 (u_ddr_cal_n_2593),
        .\lowCL3_reg[2]_0 (u_ddr_cal_n_1064),
        .\lowCL3_reg[2]_1 (u_ddr_cal_n_1065),
        .\lowCL3_reg[2]_2 (u_ddr_cal_n_1079),
        .\lowCL3_reg[2]_3 ({u_ddr_cal_n_2922,u_ddr_cal_n_2923,u_ddr_cal_n_2924}),
        .\lowCL3_reg[2]_4 (u_ddr_cal_n_2926),
        .\lowCL3_reg[2]_5 (u_ddr_cal_n_2928),
        .\lowCL3_reg[2]_6 (u_ddr_cal_n_2930),
        .\lowCL3_reg[2]_7 (u_ddr_cal_n_2936),
        .\lowCL3_reg[30]_0 (u_ddr_cal_n_982),
        .\lowCL3_reg[31]_0 (u_ddr_cal_n_2512),
        .\lowCL3_reg[31]_1 (u_ddr_cal_n_2513),
        .\lowCL3_reg[31]_2 (u_ddr_cal_n_2517),
        .\lowCL3_reg[31]_3 (u_ddr_cal_n_2519),
        .\lowCL3_reg[31]_4 (u_ddr_cal_n_2521),
        .\lowCL3_reg[31]_5 (u_ddr_cal_n_2523),
        .\lowCL3_reg[31]_6 (u_ddr_cal_n_2524),
        .\lowCL3_reg[31]_7 (u_ddr_cal_n_2526),
        .\lowCL3_reg[31]_8 (u_ddr_cal_n_2527),
        .\lowCL3_reg[32]_0 (u_ddr_cal_n_980),
        .\lowCL3_reg[32]_1 (u_ddr_cal_n_981),
        .\lowCL3_reg[32]_2 (u_ddr_cal_n_1011),
        .\lowCL3_reg[32]_3 ({u_ddr_cal_n_2514,u_ddr_cal_n_2515,u_ddr_cal_n_2516}),
        .\lowCL3_reg[32]_4 (u_ddr_cal_n_2518),
        .\lowCL3_reg[32]_5 (u_ddr_cal_n_2520),
        .\lowCL3_reg[32]_6 (u_ddr_cal_n_2522),
        .\lowCL3_reg[32]_7 (u_ddr_cal_n_2528),
        .\lowCL3_reg[33]_0 (u_ddr_cal_n_2525),
        .\lowCL3_reg[36]_0 (u_ddr_cal_n_1006),
        .\lowCL3_reg[37]_0 (u_ddr_cal_n_2648),
        .\lowCL3_reg[37]_1 (u_ddr_cal_n_2649),
        .\lowCL3_reg[37]_2 (u_ddr_cal_n_2653),
        .\lowCL3_reg[37]_3 (u_ddr_cal_n_2655),
        .\lowCL3_reg[37]_4 (u_ddr_cal_n_2657),
        .\lowCL3_reg[37]_5 (u_ddr_cal_n_2659),
        .\lowCL3_reg[37]_6 (u_ddr_cal_n_2660),
        .\lowCL3_reg[37]_7 (u_ddr_cal_n_2662),
        .\lowCL3_reg[37]_8 (u_ddr_cal_n_2663),
        .\lowCL3_reg[38]_0 (u_ddr_cal_n_1004),
        .\lowCL3_reg[38]_1 (u_ddr_cal_n_1005),
        .\lowCL3_reg[38]_2 (u_ddr_cal_n_1007),
        .\lowCL3_reg[38]_3 ({u_ddr_cal_n_2650,u_ddr_cal_n_2651,u_ddr_cal_n_2652}),
        .\lowCL3_reg[38]_4 (u_ddr_cal_n_2654),
        .\lowCL3_reg[38]_5 (u_ddr_cal_n_2656),
        .\lowCL3_reg[38]_6 (u_ddr_cal_n_2658),
        .\lowCL3_reg[38]_7 (u_ddr_cal_n_2664),
        .\lowCL3_reg[39]_0 (u_ddr_cal_n_2661),
        .\lowCL3_reg[3]_0 (u_ddr_cal_n_2933),
        .\lowCL3_reg[42]_0 (u_ddr_cal_n_934),
        .\lowCL3_reg[43]_0 (u_ddr_cal_n_2308),
        .\lowCL3_reg[43]_1 (u_ddr_cal_n_2309),
        .\lowCL3_reg[43]_2 (u_ddr_cal_n_2313),
        .\lowCL3_reg[43]_3 (u_ddr_cal_n_2315),
        .\lowCL3_reg[43]_4 (u_ddr_cal_n_2317),
        .\lowCL3_reg[43]_5 (u_ddr_cal_n_2319),
        .\lowCL3_reg[43]_6 (u_ddr_cal_n_2320),
        .\lowCL3_reg[43]_7 (u_ddr_cal_n_2322),
        .\lowCL3_reg[43]_8 (u_ddr_cal_n_2323),
        .\lowCL3_reg[44]_0 (u_ddr_cal_n_932),
        .\lowCL3_reg[44]_1 (u_ddr_cal_n_933),
        .\lowCL3_reg[44]_2 (u_ddr_cal_n_959),
        .\lowCL3_reg[44]_3 ({u_ddr_cal_n_2310,u_ddr_cal_n_2311,u_ddr_cal_n_2312}),
        .\lowCL3_reg[44]_4 (u_ddr_cal_n_2314),
        .\lowCL3_reg[44]_5 (u_ddr_cal_n_2316),
        .\lowCL3_reg[44]_6 (u_ddr_cal_n_2318),
        .\lowCL3_reg[44]_7 (u_ddr_cal_n_2324),
        .\lowCL3_reg[45]_0 (u_ddr_cal_n_2321),
        .\lowCL3_reg[6]_0 (u_ddr_cal_n_1054),
        .\lowCL3_reg[7]_0 (u_ddr_cal_n_2852),
        .\lowCL3_reg[7]_1 (u_ddr_cal_n_2853),
        .\lowCL3_reg[7]_2 (u_ddr_cal_n_2857),
        .\lowCL3_reg[7]_3 (u_ddr_cal_n_2859),
        .\lowCL3_reg[7]_4 (u_ddr_cal_n_2861),
        .\lowCL3_reg[7]_5 (u_ddr_cal_n_2863),
        .\lowCL3_reg[7]_6 (u_ddr_cal_n_2864),
        .\lowCL3_reg[7]_7 (u_ddr_cal_n_2866),
        .\lowCL3_reg[7]_8 (u_ddr_cal_n_2867),
        .\lowCL3_reg[8]_0 (u_ddr_cal_n_1052),
        .\lowCL3_reg[8]_1 (u_ddr_cal_n_1053),
        .\lowCL3_reg[8]_2 (u_ddr_cal_n_1075),
        .\lowCL3_reg[8]_3 ({u_ddr_cal_n_2854,u_ddr_cal_n_2855,u_ddr_cal_n_2856}),
        .\lowCL3_reg[8]_4 (u_ddr_cal_n_2858),
        .\lowCL3_reg[8]_5 (u_ddr_cal_n_2860),
        .\lowCL3_reg[8]_6 (u_ddr_cal_n_2862),
        .\lowCL3_reg[8]_7 (u_ddr_cal_n_2868),
        .\lowCL3_reg[9]_0 (u_ddr_cal_n_2865),
        .lrdimm_cal_mode_reg(lrdimm_cal_mode_reg),
        .lrdimm_cal_mode_reg_0(lrdimm_cal_mode_reg_0),
        .lrdimm_cal_mode_reg_1(lrdimm_cal_mode_reg_1),
        .lrdimm_cmp_clr(lrdimm_cmp_clr),
        .lrdimm_cmp_en_reg(lrdimm_cmp_en),
        .lrdimm_cmp_en_reg_0(lrdimm_cmp_en_reg),
        .\max_rd_lat_reg[5]_0 (\max_rd_lat_reg[5] ),
        .mcCasSlot2(mcCasSlot2),
        .mcRdCAS(mcRdCAS),
        .mcWrCAS(mcWrCAS),
        .mc_ADR(mc_ADR),
        .mc_BA(mc_BA),
        .mc_BG(mc_BG),
        .mc_CKE(mc_CKE),
        .mc_CKE7(mc_CKE7),
        .mc_CS_n(mc_CS_n),
        .mc_CS_n7(mc_CS_n7),
        .mc_ODT(mc_ODT[0]),
        .mc_ODT7(mc_ODT7),
        .\mc_clb2phy_fifo_rden_nxt[103]_i_3_0 ({u_ddr_mc_pi_n_1526,\u_ddr_mc_read/read_lat_shift_nxt }),
        .mcalCasSlot(mcalCasSlot),
        .mcalRank(mcalRank),
        .mcalRdCAS(mcalRdCAS),
        .\mcal_ADR_dly_reg[0][128] ({mc_ADR7[16:13],mc_ADR7[10]}),
        .\mcal_ADR_dly_reg[0][135] (\mc_ADR7_reg[16]_0 ),
        .\mcal_DMIn_bit_r1_reg[7] (\mcal_DMIn_bit_r1_reg[7] ),
        .\mcal_DMIn_n_r_reg[63] (cal_mcal_DMIn_n),
        .\mcal_DQIn_byte_r1_reg[31] (\mcal_DQIn_byte_r1_reg[31] ),
        .\mcal_DQIn_byte_r1_reg[48] (\mcal_DQIn_byte_r1_reg[48] ),
        .\mcal_DQIn_r_reg[511] (D),
        .\mcal_PAR_dly_reg[0][0] (\mcal_PAR_dly[0][0]_i_4_n_0 ),
        .\mcal_PAR_dly_reg[0][1] (\mcal_PAR_dly_reg[0][1]_0 ),
        .\mcal_PAR_dly_reg[0][3] (\mcal_PAR_dly_reg[0][3]_0 ),
        .\mcal_PAR_dly_reg[0][5] (\mcal_PAR_dly_reg[0][5]_0 ),
        .\mcal_PAR_dly_reg[0][7] (\mcal_PAR_dly_reg[0][7]_1 ),
        .mcal_rd_vref_value(mcal_rd_vref_value),
        .mem_reg_bram_0(mem_reg_bram_0),
        .out(out),
        .p_1_in(p_1_in),
        .p_52_in(p_52_in),
        .pllGate(pllGate),
        .rdCAS_reg(rdCAS_reg),
        .rdDataEn_pi(rdDataEn_pi),
        .\rdEn_reg[28] (u_ddr_mc_pi_n_830),
        .\rdEn_reg[28]_0 (u_ddr_mc_pi_n_832),
        .\rdEn_reg[28]_1 (u_ddr_mc_pi_n_834),
        .\rdEn_reg[28]_10 (u_ddr_mc_pi_n_852),
        .\rdEn_reg[28]_11 (u_ddr_mc_pi_n_854),
        .\rdEn_reg[28]_12 (u_ddr_mc_pi_n_856),
        .\rdEn_reg[28]_2 (u_ddr_mc_pi_n_836),
        .\rdEn_reg[28]_3 (u_ddr_mc_pi_n_838),
        .\rdEn_reg[28]_4 (u_ddr_mc_pi_n_840),
        .\rdEn_reg[28]_5 (u_ddr_mc_pi_n_842),
        .\rdEn_reg[28]_6 (u_ddr_mc_pi_n_844),
        .\rdEn_reg[28]_7 (u_ddr_mc_pi_n_846),
        .\rdEn_reg[28]_8 (u_ddr_mc_pi_n_848),
        .\rdEn_reg[28]_9 (u_ddr_mc_pi_n_850),
        .\rdEn_reg[29] (u_ddr_mc_pi_n_3),
        .\rdEn_reg[29]_0 (u_ddr_mc_pi_n_829),
        .\rdEn_reg[29]_1 (u_ddr_mc_pi_n_831),
        .\rdEn_reg[29]_10 (u_ddr_mc_pi_n_849),
        .\rdEn_reg[29]_11 (u_ddr_mc_pi_n_851),
        .\rdEn_reg[29]_12 (u_ddr_mc_pi_n_853),
        .\rdEn_reg[29]_13 (u_ddr_mc_pi_n_855),
        .\rdEn_reg[29]_2 (u_ddr_mc_pi_n_833),
        .\rdEn_reg[29]_3 (u_ddr_mc_pi_n_835),
        .\rdEn_reg[29]_4 (u_ddr_mc_pi_n_837),
        .\rdEn_reg[29]_5 (u_ddr_mc_pi_n_839),
        .\rdEn_reg[29]_6 (u_ddr_mc_pi_n_841),
        .\rdEn_reg[29]_7 (u_ddr_mc_pi_n_843),
        .\rdEn_reg[29]_8 (u_ddr_mc_pi_n_845),
        .\rdEn_reg[29]_9 (u_ddr_mc_pi_n_847),
        .rd_vref_value0_out(rd_vref_value0_out),
        .\rd_vref_value_reg[42] (\rd_vref_value_reg[42] ),
        .\rd_vref_value_reg[43] (\rd_vref_value_reg[43] ),
        .\rd_vref_value_reg[44] (\rd_vref_value_reg[44] ),
        .\rd_vref_value_reg[45] (\rd_vref_value_reg[45] ),
        .\rd_vref_value_reg[46] (\rd_vref_value_reg[46] ),
        .\rd_vref_value_reg[48] (\rd_vref_value_reg[48] ),
        .read_lat_shift_cal_dq_valid_nxt(\u_ddr_mc_read/read_lat_shift_cal_dq_valid_nxt ),
        .rs2mask0({\rdEn[6].u_ddr_mc_rd_en_upp/rs2mask0 [12:10],\rdEn[6].u_ddr_mc_rd_en_upp/rs2mask0 [3:2]}),
        .rs2mask0_10({\rdEn[0].u_ddr_mc_rd_en_upp/rs2mask0 [12:10],\rdEn[0].u_ddr_mc_rd_en_upp/rs2mask0 [3:2]}),
        .rs2mask0_12({\rdEn[5].u_ddr_mc_rd_en_upp/rs2mask0 [12:10],\rdEn[5].u_ddr_mc_rd_en_upp/rs2mask0 [3:2]}),
        .rs2mask0_14({\rdEn[5].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[5].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_16({\rdEn[4].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[4].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_18({\rdEn[6].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[6].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_2({\rdEn[3].u_ddr_mc_rd_en_upp/rs2mask0 [12:10],\rdEn[3].u_ddr_mc_rd_en_upp/rs2mask0 [3:2]}),
        .rs2mask0_20({\rdEn[3].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[3].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_22({\rdEn[2].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[2].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_24({\rdEn[1].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[1].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_26({\rdEn[0].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[0].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_4({\rdEn[2].u_ddr_mc_rd_en_upp/rs2mask0 [12:10],\rdEn[2].u_ddr_mc_rd_en_upp/rs2mask0 [3:2]}),
        .rs2mask0_6({\rdEn[4].u_ddr_mc_rd_en_upp/rs2mask0 [12:10],\rdEn[4].u_ddr_mc_rd_en_upp/rs2mask0 [3:2]}),
        .rs2mask0_8({\rdEn[7].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[7].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0__0({\rdEn[1].u_ddr_mc_rd_en_upp/rs2mask0__0 [12],\rdEn[1].u_ddr_mc_rd_en_upp/rs2mask0__0 [10],\rdEn[1].u_ddr_mc_rd_en_upp/rs2mask0__0 [3:2]}),
        .rs2mask0__0_0({\rdEn[7].u_ddr_mc_rd_en_upp/rs2mask0__0 [12],\rdEn[7].u_ddr_mc_rd_en_upp/rs2mask0__0 [10],\rdEn[7].u_ddr_mc_rd_en_upp/rs2mask0__0 [3:2]}),
        .\rsMask_reg[1]_71 (\rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[1]_71 ),
        .\rsMask_reg[1]_79 (\rdEn[7].u_ddr_mc_rd_en_upp/rsMask_reg[1]_79 ),
        .\rsMask_reg[3]_73 (\rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[3]_73 ),
        .\rsMask_reg[3]_81 (\rdEn[7].u_ddr_mc_rd_en_upp/rsMask_reg[3]_81 ),
        .\rsMask_reg[5]_75 (\rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[5]_75 ),
        .\rsMask_reg[5]_83 (\rdEn[7].u_ddr_mc_rd_en_upp/rsMask_reg[5]_83 ),
        .\rsMask_reg[7][18] ({u_ddr_cal_n_1376,u_ddr_cal_n_1377}),
        .\rsMask_reg[7]_77 (\rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[7]_77 ),
        .\rsMask_reg[7]_85 (\rdEn[7].u_ddr_mc_rd_en_upp/rsMask_reg[7]_85 ),
        .rst_r1_reg_0(rst_r1_reg_0),
        .rst_r1_reg_1(rst_r1_reg_1),
        .rst_r1_reg_10({u_ddr_cal_n_1826,u_ddr_cal_n_1827}),
        .rst_r1_reg_11({u_ddr_cal_n_1828,u_ddr_cal_n_1829}),
        .rst_r1_reg_12({u_ddr_cal_n_1830,u_ddr_cal_n_1831}),
        .rst_r1_reg_13({u_ddr_cal_n_1832,u_ddr_cal_n_1833}),
        .rst_r1_reg_14({u_ddr_cal_n_1834,u_ddr_cal_n_1835}),
        .rst_r1_reg_15({u_ddr_cal_n_1836,u_ddr_cal_n_1837}),
        .rst_r1_reg_2({u_ddr_cal_n_1378,u_ddr_cal_n_1379}),
        .rst_r1_reg_3({u_ddr_cal_n_1812,u_ddr_cal_n_1813}),
        .rst_r1_reg_4({u_ddr_cal_n_1814,u_ddr_cal_n_1815}),
        .rst_r1_reg_5({u_ddr_cal_n_1816,u_ddr_cal_n_1817}),
        .rst_r1_reg_6({u_ddr_cal_n_1818,u_ddr_cal_n_1819}),
        .rst_r1_reg_7({u_ddr_cal_n_1820,u_ddr_cal_n_1821}),
        .rst_r1_reg_8({u_ddr_cal_n_1822,u_ddr_cal_n_1823}),
        .rst_r1_reg_9({u_ddr_cal_n_1824,u_ddr_cal_n_1825}),
        .sl_oport_o(sl_oport_o),
        .stop_gate_tracking_ack_reg(stop_gate_tracking_ack_reg),
        .stop_gate_tracking_ack_reg_0(stop_gate_tracking_ack_reg_0),
        .\traffic_instr_nxt_instr_r1_reg[5] (\traffic_instr_nxt_instr_r1_reg[5] ),
        .ub_initDone_reg(ub_initDone_reg),
        .ub_ready_reg({u_ddr_cal_n_112,u_ddr_cal_n_113,u_ddr_cal_n_114}),
        .ub_ready_reg_0(ub_ready_reg),
        .\uppCL0_reg[0]_0 (u_ddr_cal_n_937),
        .\uppCL0_reg[12]_0 (u_ddr_cal_n_853),
        .\uppCL0_reg[13]_0 (u_ddr_cal_n_2132),
        .\uppCL0_reg[13]_1 (u_ddr_cal_n_2134),
        .\uppCL0_reg[13]_2 (u_ddr_cal_n_2137),
        .\uppCL0_reg[14]_0 (u_ddr_cal_n_851),
        .\uppCL0_reg[14]_1 (u_ddr_cal_n_852),
        .\uppCL0_reg[14]_2 (u_ddr_cal_n_890),
        .\uppCL0_reg[14]_3 ({\rdEn[2].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[2].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\uppCL0_reg[14]_4 (u_ddr_cal_n_2131),
        .\uppCL0_reg[14]_5 (u_ddr_cal_n_2133),
        .\uppCL0_reg[14]_6 (u_ddr_cal_n_2135),
        .\uppCL0_reg[15]_0 (u_ddr_cal_n_2136),
        .\uppCL0_reg[18]_0 (u_ddr_cal_n_841),
        .\uppCL0_reg[19]_0 (u_ddr_cal_n_2064),
        .\uppCL0_reg[19]_1 (u_ddr_cal_n_2066),
        .\uppCL0_reg[19]_2 (u_ddr_cal_n_2069),
        .\uppCL0_reg[1]_0 (u_ddr_cal_n_2336),
        .\uppCL0_reg[1]_1 (u_ddr_cal_n_2338),
        .\uppCL0_reg[1]_2 (u_ddr_cal_n_2341),
        .\uppCL0_reg[20]_0 (u_ddr_cal_n_839),
        .\uppCL0_reg[20]_1 (u_ddr_cal_n_840),
        .\uppCL0_reg[20]_2 (u_ddr_cal_n_886),
        .\uppCL0_reg[20]_3 ({\rdEn[3].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[3].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\uppCL0_reg[20]_4 (u_ddr_cal_n_2063),
        .\uppCL0_reg[20]_5 (u_ddr_cal_n_2065),
        .\uppCL0_reg[20]_6 (u_ddr_cal_n_2067),
        .\uppCL0_reg[21]_0 (u_ddr_cal_n_2068),
        .\uppCL0_reg[24]_0 (u_ddr_cal_n_865),
        .\uppCL0_reg[25]_0 (u_ddr_cal_n_2200),
        .\uppCL0_reg[25]_1 (u_ddr_cal_n_2202),
        .\uppCL0_reg[25]_2 (u_ddr_cal_n_2205),
        .\uppCL0_reg[26]_0 (u_ddr_cal_n_863),
        .\uppCL0_reg[26]_1 (u_ddr_cal_n_864),
        .\uppCL0_reg[26]_2 (u_ddr_cal_n_882),
        .\uppCL0_reg[26]_3 ({\rdEn[4].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[4].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\uppCL0_reg[26]_4 (u_ddr_cal_n_2199),
        .\uppCL0_reg[26]_5 (u_ddr_cal_n_2201),
        .\uppCL0_reg[26]_6 (u_ddr_cal_n_2203),
        .\uppCL0_reg[27]_0 (u_ddr_cal_n_2204),
        .\uppCL0_reg[2]_0 (u_ddr_cal_n_935),
        .\uppCL0_reg[2]_1 (u_ddr_cal_n_936),
        .\uppCL0_reg[2]_2 (u_ddr_cal_n_970),
        .\uppCL0_reg[2]_3 ({\rdEn[0].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[0].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\uppCL0_reg[2]_4 (u_ddr_cal_n_2335),
        .\uppCL0_reg[2]_5 (u_ddr_cal_n_2337),
        .\uppCL0_reg[2]_6 (u_ddr_cal_n_2339),
        .\uppCL0_reg[30]_0 (u_ddr_cal_n_949),
        .\uppCL0_reg[31]_0 (u_ddr_cal_n_2404),
        .\uppCL0_reg[31]_1 (u_ddr_cal_n_2406),
        .\uppCL0_reg[31]_2 (u_ddr_cal_n_2409),
        .\uppCL0_reg[32]_0 (u_ddr_cal_n_947),
        .\uppCL0_reg[32]_1 (u_ddr_cal_n_948),
        .\uppCL0_reg[32]_2 (u_ddr_cal_n_966),
        .\uppCL0_reg[32]_3 ({\rdEn[5].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[5].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\uppCL0_reg[32]_4 (u_ddr_cal_n_2403),
        .\uppCL0_reg[32]_5 (u_ddr_cal_n_2405),
        .\uppCL0_reg[32]_6 (u_ddr_cal_n_2407),
        .\uppCL0_reg[33]_0 (u_ddr_cal_n_2408),
        .\uppCL0_reg[36]_0 (u_ddr_cal_n_811),
        .\uppCL0_reg[37]_0 (u_ddr_cal_n_1996),
        .\uppCL0_reg[37]_1 (u_ddr_cal_n_1998),
        .\uppCL0_reg[37]_2 (u_ddr_cal_n_2001),
        .\uppCL0_reg[38]_0 (u_ddr_cal_n_803),
        .\uppCL0_reg[38]_1 (u_ddr_cal_n_810),
        .\uppCL0_reg[38]_2 (u_ddr_cal_n_878),
        .\uppCL0_reg[38]_3 ({\rdEn[6].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[6].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\uppCL0_reg[38]_4 (u_ddr_cal_n_1995),
        .\uppCL0_reg[38]_5 (u_ddr_cal_n_1997),
        .\uppCL0_reg[38]_6 (u_ddr_cal_n_1999),
        .\uppCL0_reg[39]_0 (u_ddr_cal_n_2000),
        .\uppCL0_reg[3]_0 (u_ddr_cal_n_2340),
        .\uppCL0_reg[42]_0 (u_ddr_cal_n_905),
        .\uppCL0_reg[43]_0 (u_ddr_cal_n_1883),
        .\uppCL0_reg[43]_1 (u_ddr_cal_n_1885),
        .\uppCL0_reg[43]_2 (u_ddr_cal_n_1892),
        .\uppCL0_reg[44]_0 (u_ddr_cal_n_903),
        .\uppCL0_reg[44]_1 (u_ddr_cal_n_904),
        .\uppCL0_reg[44]_2 (u_ddr_cal_n_916),
        .\uppCL0_reg[44]_3 (u_ddr_cal_n_1882),
        .\uppCL0_reg[44]_4 (u_ddr_cal_n_1884),
        .\uppCL0_reg[44]_5 (u_ddr_cal_n_1886),
        .\uppCL0_reg[44]_6 ({\rdEn[7].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[7].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\uppCL0_reg[45]_0 ({uppCL0[45:43],uppCL0[9:7]}),
        .\uppCL0_reg[45]_1 (u_ddr_cal_n_1891),
        .\uppCL0_reg[47] (\uppCL0_reg[47] ),
        .\uppCL0_reg[6]_0 (u_ddr_cal_n_893),
        .\uppCL0_reg[7]_0 (u_ddr_cal_n_1839),
        .\uppCL0_reg[7]_1 (u_ddr_cal_n_1841),
        .\uppCL0_reg[7]_2 (u_ddr_cal_n_1848),
        .\uppCL0_reg[8]_0 (u_ddr_cal_n_891),
        .\uppCL0_reg[8]_1 (u_ddr_cal_n_892),
        .\uppCL0_reg[8]_2 (u_ddr_cal_n_920),
        .\uppCL0_reg[8]_3 (u_ddr_cal_n_1838),
        .\uppCL0_reg[8]_4 (u_ddr_cal_n_1840),
        .\uppCL0_reg[8]_5 (u_ddr_cal_n_1842),
        .\uppCL0_reg[8]_6 ({\rdEn[1].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[1].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\uppCL0_reg[9]_0 (u_ddr_cal_n_1847),
        .\uppCL1_reg[0]_0 (u_ddr_cal_n_940),
        .\uppCL1_reg[12]_0 (u_ddr_cal_n_856),
        .\uppCL1_reg[13]_0 (u_ddr_cal_n_2138),
        .\uppCL1_reg[13]_1 (u_ddr_cal_n_2139),
        .\uppCL1_reg[13]_2 (u_ddr_cal_n_2143),
        .\uppCL1_reg[13]_3 (u_ddr_cal_n_2145),
        .\uppCL1_reg[13]_4 (u_ddr_cal_n_2147),
        .\uppCL1_reg[13]_5 (u_ddr_cal_n_2149),
        .\uppCL1_reg[13]_6 (u_ddr_cal_n_2150),
        .\uppCL1_reg[13]_7 (u_ddr_cal_n_2152),
        .\uppCL1_reg[13]_8 (u_ddr_cal_n_2153),
        .\uppCL1_reg[14]_0 (u_ddr_cal_n_854),
        .\uppCL1_reg[14]_1 (u_ddr_cal_n_855),
        .\uppCL1_reg[14]_2 (u_ddr_cal_n_889),
        .\uppCL1_reg[14]_3 ({u_ddr_cal_n_2140,u_ddr_cal_n_2141,u_ddr_cal_n_2142}),
        .\uppCL1_reg[14]_4 (u_ddr_cal_n_2144),
        .\uppCL1_reg[14]_5 (u_ddr_cal_n_2146),
        .\uppCL1_reg[14]_6 (u_ddr_cal_n_2148),
        .\uppCL1_reg[14]_7 (u_ddr_cal_n_2154),
        .\uppCL1_reg[15]_0 (u_ddr_cal_n_2151),
        .\uppCL1_reg[18]_0 (u_ddr_cal_n_844),
        .\uppCL1_reg[19]_0 (u_ddr_cal_n_2070),
        .\uppCL1_reg[19]_1 (u_ddr_cal_n_2071),
        .\uppCL1_reg[19]_2 (u_ddr_cal_n_2075),
        .\uppCL1_reg[19]_3 (u_ddr_cal_n_2077),
        .\uppCL1_reg[19]_4 (u_ddr_cal_n_2079),
        .\uppCL1_reg[19]_5 (u_ddr_cal_n_2081),
        .\uppCL1_reg[19]_6 (u_ddr_cal_n_2082),
        .\uppCL1_reg[19]_7 (u_ddr_cal_n_2084),
        .\uppCL1_reg[19]_8 (u_ddr_cal_n_2085),
        .\uppCL1_reg[1]_0 (u_ddr_cal_n_2342),
        .\uppCL1_reg[1]_1 (u_ddr_cal_n_2343),
        .\uppCL1_reg[1]_2 (u_ddr_cal_n_2347),
        .\uppCL1_reg[1]_3 (u_ddr_cal_n_2349),
        .\uppCL1_reg[1]_4 (u_ddr_cal_n_2351),
        .\uppCL1_reg[1]_5 (u_ddr_cal_n_2353),
        .\uppCL1_reg[1]_6 (u_ddr_cal_n_2354),
        .\uppCL1_reg[1]_7 (u_ddr_cal_n_2356),
        .\uppCL1_reg[1]_8 (u_ddr_cal_n_2357),
        .\uppCL1_reg[20]_0 (u_ddr_cal_n_842),
        .\uppCL1_reg[20]_1 (u_ddr_cal_n_843),
        .\uppCL1_reg[20]_2 (u_ddr_cal_n_885),
        .\uppCL1_reg[20]_3 ({u_ddr_cal_n_2072,u_ddr_cal_n_2073,u_ddr_cal_n_2074}),
        .\uppCL1_reg[20]_4 (u_ddr_cal_n_2076),
        .\uppCL1_reg[20]_5 (u_ddr_cal_n_2078),
        .\uppCL1_reg[20]_6 (u_ddr_cal_n_2080),
        .\uppCL1_reg[20]_7 (u_ddr_cal_n_2086),
        .\uppCL1_reg[21]_0 (u_ddr_cal_n_2083),
        .\uppCL1_reg[24]_0 (u_ddr_cal_n_868),
        .\uppCL1_reg[25]_0 (u_ddr_cal_n_2206),
        .\uppCL1_reg[25]_1 (u_ddr_cal_n_2207),
        .\uppCL1_reg[25]_2 (u_ddr_cal_n_2211),
        .\uppCL1_reg[25]_3 (u_ddr_cal_n_2213),
        .\uppCL1_reg[25]_4 (u_ddr_cal_n_2215),
        .\uppCL1_reg[25]_5 (u_ddr_cal_n_2217),
        .\uppCL1_reg[25]_6 (u_ddr_cal_n_2218),
        .\uppCL1_reg[25]_7 (u_ddr_cal_n_2220),
        .\uppCL1_reg[25]_8 (u_ddr_cal_n_2221),
        .\uppCL1_reg[26]_0 (u_ddr_cal_n_866),
        .\uppCL1_reg[26]_1 (u_ddr_cal_n_867),
        .\uppCL1_reg[26]_2 (u_ddr_cal_n_881),
        .\uppCL1_reg[26]_3 ({u_ddr_cal_n_2208,u_ddr_cal_n_2209,u_ddr_cal_n_2210}),
        .\uppCL1_reg[26]_4 (u_ddr_cal_n_2212),
        .\uppCL1_reg[26]_5 (u_ddr_cal_n_2214),
        .\uppCL1_reg[26]_6 (u_ddr_cal_n_2216),
        .\uppCL1_reg[26]_7 (u_ddr_cal_n_2222),
        .\uppCL1_reg[27]_0 (u_ddr_cal_n_2219),
        .\uppCL1_reg[2]_0 (u_ddr_cal_n_938),
        .\uppCL1_reg[2]_1 (u_ddr_cal_n_939),
        .\uppCL1_reg[2]_2 (u_ddr_cal_n_969),
        .\uppCL1_reg[2]_3 ({u_ddr_cal_n_2344,u_ddr_cal_n_2345,u_ddr_cal_n_2346}),
        .\uppCL1_reg[2]_4 (u_ddr_cal_n_2348),
        .\uppCL1_reg[2]_5 (u_ddr_cal_n_2350),
        .\uppCL1_reg[2]_6 (u_ddr_cal_n_2352),
        .\uppCL1_reg[2]_7 (u_ddr_cal_n_2358),
        .\uppCL1_reg[30]_0 (u_ddr_cal_n_952),
        .\uppCL1_reg[31]_0 (u_ddr_cal_n_2410),
        .\uppCL1_reg[31]_1 (u_ddr_cal_n_2411),
        .\uppCL1_reg[31]_2 (u_ddr_cal_n_2415),
        .\uppCL1_reg[31]_3 (u_ddr_cal_n_2417),
        .\uppCL1_reg[31]_4 (u_ddr_cal_n_2419),
        .\uppCL1_reg[31]_5 (u_ddr_cal_n_2421),
        .\uppCL1_reg[31]_6 (u_ddr_cal_n_2422),
        .\uppCL1_reg[31]_7 (u_ddr_cal_n_2424),
        .\uppCL1_reg[31]_8 (u_ddr_cal_n_2425),
        .\uppCL1_reg[32]_0 (u_ddr_cal_n_950),
        .\uppCL1_reg[32]_1 (u_ddr_cal_n_951),
        .\uppCL1_reg[32]_2 (u_ddr_cal_n_965),
        .\uppCL1_reg[32]_3 ({u_ddr_cal_n_2412,u_ddr_cal_n_2413,u_ddr_cal_n_2414}),
        .\uppCL1_reg[32]_4 (u_ddr_cal_n_2416),
        .\uppCL1_reg[32]_5 (u_ddr_cal_n_2418),
        .\uppCL1_reg[32]_6 (u_ddr_cal_n_2420),
        .\uppCL1_reg[32]_7 (u_ddr_cal_n_2426),
        .\uppCL1_reg[33]_0 (u_ddr_cal_n_2423),
        .\uppCL1_reg[36]_0 (u_ddr_cal_n_820),
        .\uppCL1_reg[37]_0 (u_ddr_cal_n_2002),
        .\uppCL1_reg[37]_1 (u_ddr_cal_n_2003),
        .\uppCL1_reg[37]_2 (u_ddr_cal_n_2007),
        .\uppCL1_reg[37]_3 (u_ddr_cal_n_2009),
        .\uppCL1_reg[37]_4 (u_ddr_cal_n_2011),
        .\uppCL1_reg[37]_5 (u_ddr_cal_n_2013),
        .\uppCL1_reg[37]_6 (u_ddr_cal_n_2014),
        .\uppCL1_reg[37]_7 (u_ddr_cal_n_2016),
        .\uppCL1_reg[37]_8 (u_ddr_cal_n_2017),
        .\uppCL1_reg[38]_0 (u_ddr_cal_n_812),
        .\uppCL1_reg[38]_1 (u_ddr_cal_n_819),
        .\uppCL1_reg[38]_2 (u_ddr_cal_n_877),
        .\uppCL1_reg[38]_3 ({u_ddr_cal_n_2004,u_ddr_cal_n_2005,u_ddr_cal_n_2006}),
        .\uppCL1_reg[38]_4 (u_ddr_cal_n_2008),
        .\uppCL1_reg[38]_5 (u_ddr_cal_n_2010),
        .\uppCL1_reg[38]_6 (u_ddr_cal_n_2012),
        .\uppCL1_reg[38]_7 (u_ddr_cal_n_2018),
        .\uppCL1_reg[39]_0 (u_ddr_cal_n_2015),
        .\uppCL1_reg[3]_0 (u_ddr_cal_n_2355),
        .\uppCL1_reg[42]_0 (u_ddr_cal_n_908),
        .\uppCL1_reg[43]_0 (u_ddr_cal_n_1894),
        .\uppCL1_reg[43]_1 (u_ddr_cal_n_1896),
        .\uppCL1_reg[43]_2 (u_ddr_cal_n_1898),
        .\uppCL1_reg[43]_3 (u_ddr_cal_n_1899),
        .\uppCL1_reg[43]_4 (u_ddr_cal_n_1901),
        .\uppCL1_reg[43]_5 (u_ddr_cal_n_1902),
        .\uppCL1_reg[43]_6 (u_ddr_cal_n_2963),
        .\uppCL1_reg[43]_7 (u_ddr_cal_n_2964),
        .\uppCL1_reg[44]_0 (u_ddr_cal_n_906),
        .\uppCL1_reg[44]_1 (u_ddr_cal_n_907),
        .\uppCL1_reg[44]_2 (u_ddr_cal_n_915),
        .\uppCL1_reg[44]_3 (u_ddr_cal_n_1893),
        .\uppCL1_reg[44]_4 (u_ddr_cal_n_1895),
        .\uppCL1_reg[44]_5 (u_ddr_cal_n_1897),
        .\uppCL1_reg[44]_6 (u_ddr_cal_n_1903),
        .\uppCL1_reg[44]_7 ({u_ddr_cal_n_2965,u_ddr_cal_n_2966,u_ddr_cal_n_2967}),
        .\uppCL1_reg[45]_0 ({uppCL1[45:43],uppCL1[9:7]}),
        .\uppCL1_reg[45]_1 (u_ddr_cal_n_1900),
        .\uppCL1_reg[47] (\uppCL1_reg[47] ),
        .\uppCL1_reg[6]_0 (u_ddr_cal_n_896),
        .\uppCL1_reg[7]_0 (u_ddr_cal_n_1850),
        .\uppCL1_reg[7]_1 (u_ddr_cal_n_1852),
        .\uppCL1_reg[7]_2 (u_ddr_cal_n_1854),
        .\uppCL1_reg[7]_3 (u_ddr_cal_n_1855),
        .\uppCL1_reg[7]_4 (u_ddr_cal_n_1857),
        .\uppCL1_reg[7]_5 (u_ddr_cal_n_1858),
        .\uppCL1_reg[7]_6 (u_ddr_cal_n_2943),
        .\uppCL1_reg[7]_7 (u_ddr_cal_n_2944),
        .\uppCL1_reg[8]_0 (u_ddr_cal_n_894),
        .\uppCL1_reg[8]_1 (u_ddr_cal_n_895),
        .\uppCL1_reg[8]_2 (u_ddr_cal_n_919),
        .\uppCL1_reg[8]_3 (u_ddr_cal_n_1849),
        .\uppCL1_reg[8]_4 (u_ddr_cal_n_1851),
        .\uppCL1_reg[8]_5 (u_ddr_cal_n_1853),
        .\uppCL1_reg[8]_6 (u_ddr_cal_n_1859),
        .\uppCL1_reg[8]_7 ({u_ddr_cal_n_2945,u_ddr_cal_n_2946,u_ddr_cal_n_2947}),
        .\uppCL1_reg[9]_0 (u_ddr_cal_n_1856),
        .\uppCL2_reg[0]_0 (u_ddr_cal_n_943),
        .\uppCL2_reg[12]_0 (u_ddr_cal_n_859),
        .\uppCL2_reg[13]_0 (u_ddr_cal_n_2155),
        .\uppCL2_reg[13]_1 (u_ddr_cal_n_2156),
        .\uppCL2_reg[13]_2 (u_ddr_cal_n_2160),
        .\uppCL2_reg[13]_3 (u_ddr_cal_n_2162),
        .\uppCL2_reg[13]_4 (u_ddr_cal_n_2164),
        .\uppCL2_reg[13]_5 (u_ddr_cal_n_2166),
        .\uppCL2_reg[13]_6 (u_ddr_cal_n_2167),
        .\uppCL2_reg[13]_7 (u_ddr_cal_n_2169),
        .\uppCL2_reg[13]_8 (u_ddr_cal_n_2170),
        .\uppCL2_reg[14]_0 (u_ddr_cal_n_857),
        .\uppCL2_reg[14]_1 (u_ddr_cal_n_858),
        .\uppCL2_reg[14]_2 (u_ddr_cal_n_888),
        .\uppCL2_reg[14]_3 ({u_ddr_cal_n_2157,u_ddr_cal_n_2158,u_ddr_cal_n_2159}),
        .\uppCL2_reg[14]_4 (u_ddr_cal_n_2161),
        .\uppCL2_reg[14]_5 (u_ddr_cal_n_2163),
        .\uppCL2_reg[14]_6 (u_ddr_cal_n_2165),
        .\uppCL2_reg[14]_7 (u_ddr_cal_n_2171),
        .\uppCL2_reg[15]_0 (u_ddr_cal_n_2168),
        .\uppCL2_reg[18]_0 (u_ddr_cal_n_847),
        .\uppCL2_reg[19]_0 (u_ddr_cal_n_2087),
        .\uppCL2_reg[19]_1 (u_ddr_cal_n_2088),
        .\uppCL2_reg[19]_2 (u_ddr_cal_n_2092),
        .\uppCL2_reg[19]_3 (u_ddr_cal_n_2094),
        .\uppCL2_reg[19]_4 (u_ddr_cal_n_2096),
        .\uppCL2_reg[19]_5 (u_ddr_cal_n_2098),
        .\uppCL2_reg[19]_6 (u_ddr_cal_n_2099),
        .\uppCL2_reg[19]_7 (u_ddr_cal_n_2101),
        .\uppCL2_reg[19]_8 (u_ddr_cal_n_2102),
        .\uppCL2_reg[1]_0 (u_ddr_cal_n_2359),
        .\uppCL2_reg[1]_1 (u_ddr_cal_n_2360),
        .\uppCL2_reg[1]_2 (u_ddr_cal_n_2364),
        .\uppCL2_reg[1]_3 (u_ddr_cal_n_2366),
        .\uppCL2_reg[1]_4 (u_ddr_cal_n_2368),
        .\uppCL2_reg[1]_5 (u_ddr_cal_n_2370),
        .\uppCL2_reg[1]_6 (u_ddr_cal_n_2371),
        .\uppCL2_reg[1]_7 (u_ddr_cal_n_2373),
        .\uppCL2_reg[1]_8 (u_ddr_cal_n_2374),
        .\uppCL2_reg[20]_0 (u_ddr_cal_n_845),
        .\uppCL2_reg[20]_1 (u_ddr_cal_n_846),
        .\uppCL2_reg[20]_2 (u_ddr_cal_n_884),
        .\uppCL2_reg[20]_3 ({u_ddr_cal_n_2089,u_ddr_cal_n_2090,u_ddr_cal_n_2091}),
        .\uppCL2_reg[20]_4 (u_ddr_cal_n_2093),
        .\uppCL2_reg[20]_5 (u_ddr_cal_n_2095),
        .\uppCL2_reg[20]_6 (u_ddr_cal_n_2097),
        .\uppCL2_reg[20]_7 (u_ddr_cal_n_2103),
        .\uppCL2_reg[21]_0 (u_ddr_cal_n_2100),
        .\uppCL2_reg[24]_0 (u_ddr_cal_n_871),
        .\uppCL2_reg[25]_0 (u_ddr_cal_n_2223),
        .\uppCL2_reg[25]_1 (u_ddr_cal_n_2224),
        .\uppCL2_reg[25]_2 (u_ddr_cal_n_2228),
        .\uppCL2_reg[25]_3 (u_ddr_cal_n_2230),
        .\uppCL2_reg[25]_4 (u_ddr_cal_n_2232),
        .\uppCL2_reg[25]_5 (u_ddr_cal_n_2234),
        .\uppCL2_reg[25]_6 (u_ddr_cal_n_2235),
        .\uppCL2_reg[25]_7 (u_ddr_cal_n_2237),
        .\uppCL2_reg[25]_8 (u_ddr_cal_n_2238),
        .\uppCL2_reg[26]_0 (u_ddr_cal_n_869),
        .\uppCL2_reg[26]_1 (u_ddr_cal_n_870),
        .\uppCL2_reg[26]_2 (u_ddr_cal_n_880),
        .\uppCL2_reg[26]_3 ({u_ddr_cal_n_2225,u_ddr_cal_n_2226,u_ddr_cal_n_2227}),
        .\uppCL2_reg[26]_4 (u_ddr_cal_n_2229),
        .\uppCL2_reg[26]_5 (u_ddr_cal_n_2231),
        .\uppCL2_reg[26]_6 (u_ddr_cal_n_2233),
        .\uppCL2_reg[26]_7 (u_ddr_cal_n_2239),
        .\uppCL2_reg[27]_0 (u_ddr_cal_n_2236),
        .\uppCL2_reg[2]_0 (u_ddr_cal_n_941),
        .\uppCL2_reg[2]_1 (u_ddr_cal_n_942),
        .\uppCL2_reg[2]_2 (u_ddr_cal_n_968),
        .\uppCL2_reg[2]_3 ({u_ddr_cal_n_2361,u_ddr_cal_n_2362,u_ddr_cal_n_2363}),
        .\uppCL2_reg[2]_4 (u_ddr_cal_n_2365),
        .\uppCL2_reg[2]_5 (u_ddr_cal_n_2367),
        .\uppCL2_reg[2]_6 (u_ddr_cal_n_2369),
        .\uppCL2_reg[2]_7 (u_ddr_cal_n_2375),
        .\uppCL2_reg[30]_0 (u_ddr_cal_n_955),
        .\uppCL2_reg[31]_0 (u_ddr_cal_n_2427),
        .\uppCL2_reg[31]_1 (u_ddr_cal_n_2428),
        .\uppCL2_reg[31]_2 (u_ddr_cal_n_2432),
        .\uppCL2_reg[31]_3 (u_ddr_cal_n_2434),
        .\uppCL2_reg[31]_4 (u_ddr_cal_n_2436),
        .\uppCL2_reg[31]_5 (u_ddr_cal_n_2438),
        .\uppCL2_reg[31]_6 (u_ddr_cal_n_2439),
        .\uppCL2_reg[31]_7 (u_ddr_cal_n_2441),
        .\uppCL2_reg[31]_8 (u_ddr_cal_n_2442),
        .\uppCL2_reg[32]_0 (u_ddr_cal_n_953),
        .\uppCL2_reg[32]_1 (u_ddr_cal_n_954),
        .\uppCL2_reg[32]_2 (u_ddr_cal_n_964),
        .\uppCL2_reg[32]_3 ({u_ddr_cal_n_2429,u_ddr_cal_n_2430,u_ddr_cal_n_2431}),
        .\uppCL2_reg[32]_4 (u_ddr_cal_n_2433),
        .\uppCL2_reg[32]_5 (u_ddr_cal_n_2435),
        .\uppCL2_reg[32]_6 (u_ddr_cal_n_2437),
        .\uppCL2_reg[32]_7 (u_ddr_cal_n_2443),
        .\uppCL2_reg[33]_0 (u_ddr_cal_n_2440),
        .\uppCL2_reg[36]_0 (u_ddr_cal_n_829),
        .\uppCL2_reg[37]_0 (u_ddr_cal_n_2019),
        .\uppCL2_reg[37]_1 (u_ddr_cal_n_2020),
        .\uppCL2_reg[37]_2 (u_ddr_cal_n_2024),
        .\uppCL2_reg[37]_3 (u_ddr_cal_n_2026),
        .\uppCL2_reg[37]_4 (u_ddr_cal_n_2028),
        .\uppCL2_reg[37]_5 (u_ddr_cal_n_2030),
        .\uppCL2_reg[37]_6 (u_ddr_cal_n_2031),
        .\uppCL2_reg[37]_7 (u_ddr_cal_n_2033),
        .\uppCL2_reg[37]_8 (u_ddr_cal_n_2034),
        .\uppCL2_reg[38]_0 (u_ddr_cal_n_821),
        .\uppCL2_reg[38]_1 (u_ddr_cal_n_828),
        .\uppCL2_reg[38]_2 (u_ddr_cal_n_876),
        .\uppCL2_reg[38]_3 ({u_ddr_cal_n_2021,u_ddr_cal_n_2022,u_ddr_cal_n_2023}),
        .\uppCL2_reg[38]_4 (u_ddr_cal_n_2025),
        .\uppCL2_reg[38]_5 (u_ddr_cal_n_2027),
        .\uppCL2_reg[38]_6 (u_ddr_cal_n_2029),
        .\uppCL2_reg[38]_7 (u_ddr_cal_n_2035),
        .\uppCL2_reg[39]_0 (u_ddr_cal_n_2032),
        .\uppCL2_reg[3]_0 (u_ddr_cal_n_2372),
        .\uppCL2_reg[42]_0 (u_ddr_cal_n_911),
        .\uppCL2_reg[43]_0 (u_ddr_cal_n_1905),
        .\uppCL2_reg[43]_1 (u_ddr_cal_n_1907),
        .\uppCL2_reg[43]_2 (u_ddr_cal_n_1909),
        .\uppCL2_reg[43]_3 (u_ddr_cal_n_1910),
        .\uppCL2_reg[43]_4 (u_ddr_cal_n_1912),
        .\uppCL2_reg[43]_5 (u_ddr_cal_n_1913),
        .\uppCL2_reg[43]_6 (u_ddr_cal_n_2968),
        .\uppCL2_reg[43]_7 (u_ddr_cal_n_2969),
        .\uppCL2_reg[44]_0 (u_ddr_cal_n_909),
        .\uppCL2_reg[44]_1 (u_ddr_cal_n_910),
        .\uppCL2_reg[44]_2 (u_ddr_cal_n_918),
        .\uppCL2_reg[44]_3 (u_ddr_cal_n_1904),
        .\uppCL2_reg[44]_4 (u_ddr_cal_n_1906),
        .\uppCL2_reg[44]_5 (u_ddr_cal_n_1908),
        .\uppCL2_reg[44]_6 (u_ddr_cal_n_1914),
        .\uppCL2_reg[44]_7 ({u_ddr_cal_n_2970,u_ddr_cal_n_2971,u_ddr_cal_n_2972}),
        .\uppCL2_reg[45]_0 ({uppCL2[45:43],uppCL2[9:7]}),
        .\uppCL2_reg[45]_1 (u_ddr_cal_n_1911),
        .\uppCL2_reg[47] (\uppCL2_reg[47] ),
        .\uppCL2_reg[6]_0 (u_ddr_cal_n_899),
        .\uppCL2_reg[7]_0 (u_ddr_cal_n_1861),
        .\uppCL2_reg[7]_1 (u_ddr_cal_n_1863),
        .\uppCL2_reg[7]_2 (u_ddr_cal_n_1865),
        .\uppCL2_reg[7]_3 (u_ddr_cal_n_1866),
        .\uppCL2_reg[7]_4 (u_ddr_cal_n_1868),
        .\uppCL2_reg[7]_5 (u_ddr_cal_n_1869),
        .\uppCL2_reg[7]_6 (u_ddr_cal_n_2948),
        .\uppCL2_reg[7]_7 (u_ddr_cal_n_2949),
        .\uppCL2_reg[8]_0 (u_ddr_cal_n_897),
        .\uppCL2_reg[8]_1 (u_ddr_cal_n_898),
        .\uppCL2_reg[8]_2 (u_ddr_cal_n_922),
        .\uppCL2_reg[8]_3 (u_ddr_cal_n_1860),
        .\uppCL2_reg[8]_4 (u_ddr_cal_n_1862),
        .\uppCL2_reg[8]_5 (u_ddr_cal_n_1864),
        .\uppCL2_reg[8]_6 (u_ddr_cal_n_1870),
        .\uppCL2_reg[8]_7 ({u_ddr_cal_n_2950,u_ddr_cal_n_2951,u_ddr_cal_n_2952}),
        .\uppCL2_reg[9]_0 (u_ddr_cal_n_1867),
        .\uppCL3_reg[0]_0 (u_ddr_cal_n_946),
        .\uppCL3_reg[12]_0 (u_ddr_cal_n_862),
        .\uppCL3_reg[13]_0 (u_ddr_cal_n_2172),
        .\uppCL3_reg[13]_1 (u_ddr_cal_n_2173),
        .\uppCL3_reg[13]_2 (u_ddr_cal_n_2177),
        .\uppCL3_reg[13]_3 (u_ddr_cal_n_2179),
        .\uppCL3_reg[13]_4 (u_ddr_cal_n_2181),
        .\uppCL3_reg[13]_5 (u_ddr_cal_n_2183),
        .\uppCL3_reg[13]_6 (u_ddr_cal_n_2184),
        .\uppCL3_reg[13]_7 (u_ddr_cal_n_2186),
        .\uppCL3_reg[13]_8 (u_ddr_cal_n_2187),
        .\uppCL3_reg[14]_0 (u_ddr_cal_n_860),
        .\uppCL3_reg[14]_1 (u_ddr_cal_n_861),
        .\uppCL3_reg[14]_2 (u_ddr_cal_n_887),
        .\uppCL3_reg[14]_3 ({u_ddr_cal_n_2174,u_ddr_cal_n_2175,u_ddr_cal_n_2176}),
        .\uppCL3_reg[14]_4 (u_ddr_cal_n_2178),
        .\uppCL3_reg[14]_5 (u_ddr_cal_n_2180),
        .\uppCL3_reg[14]_6 (u_ddr_cal_n_2182),
        .\uppCL3_reg[14]_7 (u_ddr_cal_n_2188),
        .\uppCL3_reg[15]_0 (u_ddr_cal_n_2185),
        .\uppCL3_reg[18]_0 (u_ddr_cal_n_850),
        .\uppCL3_reg[19]_0 (u_ddr_cal_n_2104),
        .\uppCL3_reg[19]_1 (u_ddr_cal_n_2105),
        .\uppCL3_reg[19]_2 (u_ddr_cal_n_2109),
        .\uppCL3_reg[19]_3 (u_ddr_cal_n_2111),
        .\uppCL3_reg[19]_4 (u_ddr_cal_n_2113),
        .\uppCL3_reg[19]_5 (u_ddr_cal_n_2115),
        .\uppCL3_reg[19]_6 (u_ddr_cal_n_2116),
        .\uppCL3_reg[19]_7 (u_ddr_cal_n_2118),
        .\uppCL3_reg[19]_8 (u_ddr_cal_n_2119),
        .\uppCL3_reg[1]_0 (u_ddr_cal_n_2376),
        .\uppCL3_reg[1]_1 (u_ddr_cal_n_2377),
        .\uppCL3_reg[1]_2 (u_ddr_cal_n_2381),
        .\uppCL3_reg[1]_3 (u_ddr_cal_n_2383),
        .\uppCL3_reg[1]_4 (u_ddr_cal_n_2385),
        .\uppCL3_reg[1]_5 (u_ddr_cal_n_2387),
        .\uppCL3_reg[1]_6 (u_ddr_cal_n_2388),
        .\uppCL3_reg[1]_7 (u_ddr_cal_n_2390),
        .\uppCL3_reg[1]_8 (u_ddr_cal_n_2391),
        .\uppCL3_reg[20]_0 (u_ddr_cal_n_848),
        .\uppCL3_reg[20]_1 (u_ddr_cal_n_849),
        .\uppCL3_reg[20]_2 (u_ddr_cal_n_883),
        .\uppCL3_reg[20]_3 ({u_ddr_cal_n_2106,u_ddr_cal_n_2107,u_ddr_cal_n_2108}),
        .\uppCL3_reg[20]_4 (u_ddr_cal_n_2110),
        .\uppCL3_reg[20]_5 (u_ddr_cal_n_2112),
        .\uppCL3_reg[20]_6 (u_ddr_cal_n_2114),
        .\uppCL3_reg[20]_7 (u_ddr_cal_n_2120),
        .\uppCL3_reg[21]_0 (u_ddr_cal_n_2117),
        .\uppCL3_reg[24]_0 (u_ddr_cal_n_874),
        .\uppCL3_reg[25]_0 (u_ddr_cal_n_2240),
        .\uppCL3_reg[25]_1 (u_ddr_cal_n_2241),
        .\uppCL3_reg[25]_2 (u_ddr_cal_n_2245),
        .\uppCL3_reg[25]_3 (u_ddr_cal_n_2247),
        .\uppCL3_reg[25]_4 (u_ddr_cal_n_2249),
        .\uppCL3_reg[25]_5 (u_ddr_cal_n_2251),
        .\uppCL3_reg[25]_6 (u_ddr_cal_n_2252),
        .\uppCL3_reg[25]_7 (u_ddr_cal_n_2254),
        .\uppCL3_reg[25]_8 (u_ddr_cal_n_2255),
        .\uppCL3_reg[26]_0 (u_ddr_cal_n_872),
        .\uppCL3_reg[26]_1 (u_ddr_cal_n_873),
        .\uppCL3_reg[26]_2 (u_ddr_cal_n_879),
        .\uppCL3_reg[26]_3 ({u_ddr_cal_n_2242,u_ddr_cal_n_2243,u_ddr_cal_n_2244}),
        .\uppCL3_reg[26]_4 (u_ddr_cal_n_2246),
        .\uppCL3_reg[26]_5 (u_ddr_cal_n_2248),
        .\uppCL3_reg[26]_6 (u_ddr_cal_n_2250),
        .\uppCL3_reg[26]_7 (u_ddr_cal_n_2256),
        .\uppCL3_reg[27]_0 (u_ddr_cal_n_2253),
        .\uppCL3_reg[2]_0 (u_ddr_cal_n_944),
        .\uppCL3_reg[2]_1 (u_ddr_cal_n_945),
        .\uppCL3_reg[2]_2 (u_ddr_cal_n_967),
        .\uppCL3_reg[2]_3 ({u_ddr_cal_n_2378,u_ddr_cal_n_2379,u_ddr_cal_n_2380}),
        .\uppCL3_reg[2]_4 (u_ddr_cal_n_2382),
        .\uppCL3_reg[2]_5 (u_ddr_cal_n_2384),
        .\uppCL3_reg[2]_6 (u_ddr_cal_n_2386),
        .\uppCL3_reg[2]_7 (u_ddr_cal_n_2392),
        .\uppCL3_reg[30]_0 (u_ddr_cal_n_958),
        .\uppCL3_reg[31]_0 (u_ddr_cal_n_2444),
        .\uppCL3_reg[31]_1 (u_ddr_cal_n_2445),
        .\uppCL3_reg[31]_2 (u_ddr_cal_n_2449),
        .\uppCL3_reg[31]_3 (u_ddr_cal_n_2451),
        .\uppCL3_reg[31]_4 (u_ddr_cal_n_2453),
        .\uppCL3_reg[31]_5 (u_ddr_cal_n_2455),
        .\uppCL3_reg[31]_6 (u_ddr_cal_n_2456),
        .\uppCL3_reg[31]_7 (u_ddr_cal_n_2458),
        .\uppCL3_reg[31]_8 (u_ddr_cal_n_2459),
        .\uppCL3_reg[32]_0 (u_ddr_cal_n_956),
        .\uppCL3_reg[32]_1 (u_ddr_cal_n_957),
        .\uppCL3_reg[32]_2 (u_ddr_cal_n_963),
        .\uppCL3_reg[32]_3 ({u_ddr_cal_n_2446,u_ddr_cal_n_2447,u_ddr_cal_n_2448}),
        .\uppCL3_reg[32]_4 (u_ddr_cal_n_2450),
        .\uppCL3_reg[32]_5 (u_ddr_cal_n_2452),
        .\uppCL3_reg[32]_6 (u_ddr_cal_n_2454),
        .\uppCL3_reg[32]_7 (u_ddr_cal_n_2460),
        .\uppCL3_reg[33]_0 (u_ddr_cal_n_2457),
        .\uppCL3_reg[36]_0 (u_ddr_cal_n_838),
        .\uppCL3_reg[37]_0 (u_ddr_cal_n_2036),
        .\uppCL3_reg[37]_1 (u_ddr_cal_n_2037),
        .\uppCL3_reg[37]_2 (u_ddr_cal_n_2041),
        .\uppCL3_reg[37]_3 (u_ddr_cal_n_2043),
        .\uppCL3_reg[37]_4 (u_ddr_cal_n_2045),
        .\uppCL3_reg[37]_5 (u_ddr_cal_n_2047),
        .\uppCL3_reg[37]_6 (u_ddr_cal_n_2048),
        .\uppCL3_reg[37]_7 (u_ddr_cal_n_2050),
        .\uppCL3_reg[37]_8 (u_ddr_cal_n_2051),
        .\uppCL3_reg[38]_0 (u_ddr_cal_n_830),
        .\uppCL3_reg[38]_1 (u_ddr_cal_n_837),
        .\uppCL3_reg[38]_2 (u_ddr_cal_n_875),
        .\uppCL3_reg[38]_3 ({u_ddr_cal_n_2038,u_ddr_cal_n_2039,u_ddr_cal_n_2040}),
        .\uppCL3_reg[38]_4 (u_ddr_cal_n_2042),
        .\uppCL3_reg[38]_5 (u_ddr_cal_n_2044),
        .\uppCL3_reg[38]_6 (u_ddr_cal_n_2046),
        .\uppCL3_reg[38]_7 (u_ddr_cal_n_2052),
        .\uppCL3_reg[39]_0 (u_ddr_cal_n_2049),
        .\uppCL3_reg[3]_0 (u_ddr_cal_n_2389),
        .\uppCL3_reg[42]_0 (u_ddr_cal_n_914),
        .\uppCL3_reg[42]_1 (\uppCL3_reg[42] ),
        .\uppCL3_reg[43]_0 (u_ddr_cal_n_1916),
        .\uppCL3_reg[43]_1 (u_ddr_cal_n_1918),
        .\uppCL3_reg[43]_2 (u_ddr_cal_n_1920),
        .\uppCL3_reg[43]_3 (u_ddr_cal_n_1921),
        .\uppCL3_reg[43]_4 (u_ddr_cal_n_1923),
        .\uppCL3_reg[43]_5 (u_ddr_cal_n_1924),
        .\uppCL3_reg[43]_6 (u_ddr_cal_n_2973),
        .\uppCL3_reg[43]_7 (u_ddr_cal_n_2974),
        .\uppCL3_reg[44]_0 (u_ddr_cal_n_912),
        .\uppCL3_reg[44]_1 (u_ddr_cal_n_913),
        .\uppCL3_reg[44]_2 (u_ddr_cal_n_917),
        .\uppCL3_reg[44]_3 (u_ddr_cal_n_1915),
        .\uppCL3_reg[44]_4 (u_ddr_cal_n_1917),
        .\uppCL3_reg[44]_5 (u_ddr_cal_n_1919),
        .\uppCL3_reg[44]_6 (u_ddr_cal_n_1925),
        .\uppCL3_reg[44]_7 ({u_ddr_cal_n_2975,u_ddr_cal_n_2976,u_ddr_cal_n_2977}),
        .\uppCL3_reg[45]_0 ({uppCL3[45:43],uppCL3[9:7]}),
        .\uppCL3_reg[45]_1 (u_ddr_cal_n_1922),
        .\uppCL3_reg[47] (\uppCL3_reg[47] ),
        .\uppCL3_reg[6]_0 (u_ddr_cal_n_902),
        .\uppCL3_reg[7]_0 (u_ddr_cal_n_1872),
        .\uppCL3_reg[7]_1 (u_ddr_cal_n_1874),
        .\uppCL3_reg[7]_2 (u_ddr_cal_n_1876),
        .\uppCL3_reg[7]_3 (u_ddr_cal_n_1877),
        .\uppCL3_reg[7]_4 (u_ddr_cal_n_1879),
        .\uppCL3_reg[7]_5 (u_ddr_cal_n_1880),
        .\uppCL3_reg[7]_6 (u_ddr_cal_n_2953),
        .\uppCL3_reg[7]_7 (u_ddr_cal_n_2954),
        .\uppCL3_reg[8]_0 (u_ddr_cal_n_900),
        .\uppCL3_reg[8]_1 (u_ddr_cal_n_901),
        .\uppCL3_reg[8]_2 (u_ddr_cal_n_921),
        .\uppCL3_reg[8]_3 (u_ddr_cal_n_1871),
        .\uppCL3_reg[8]_4 (u_ddr_cal_n_1873),
        .\uppCL3_reg[8]_5 (u_ddr_cal_n_1875),
        .\uppCL3_reg[8]_6 (u_ddr_cal_n_1881),
        .\uppCL3_reg[8]_7 ({u_ddr_cal_n_2955,u_ddr_cal_n_2956,u_ddr_cal_n_2957}),
        .\uppCL3_reg[9]_0 (u_ddr_cal_n_1878),
        .winAct(winAct),
        .winAct_reg(p_0_in__0),
        .wosp(\u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/wosp ),
        .\wosp_reg[1] (u_ddr_cal_n_1380),
        .\wosp_reg[1]_0 (u_ddr_cal_n_1384),
        .\wosp_reg[1]_1 (u_ddr_cal_n_1418),
        .\wosp_reg[1]_10 (u_ddr_cal_n_1427),
        .\wosp_reg[1]_100 (u_ddr_cal_n_1697),
        .\wosp_reg[1]_101 (u_ddr_cal_n_1698),
        .\wosp_reg[1]_102 (u_ddr_cal_n_1699),
        .\wosp_reg[1]_103 (u_ddr_cal_n_1700),
        .\wosp_reg[1]_104 (u_ddr_cal_n_1701),
        .\wosp_reg[1]_105 (u_ddr_cal_n_1702),
        .\wosp_reg[1]_106 (u_ddr_cal_n_1703),
        .\wosp_reg[1]_107 (u_ddr_cal_n_1704),
        .\wosp_reg[1]_108 (u_ddr_cal_n_1708),
        .\wosp_reg[1]_109 (u_ddr_cal_n_1742),
        .\wosp_reg[1]_11 (u_ddr_cal_n_1428),
        .\wosp_reg[1]_110 (u_ddr_cal_n_1743),
        .\wosp_reg[1]_111 (u_ddr_cal_n_1744),
        .\wosp_reg[1]_112 (u_ddr_cal_n_1745),
        .\wosp_reg[1]_113 (u_ddr_cal_n_1746),
        .\wosp_reg[1]_114 (u_ddr_cal_n_1747),
        .\wosp_reg[1]_115 (u_ddr_cal_n_1748),
        .\wosp_reg[1]_116 (u_ddr_cal_n_1749),
        .\wosp_reg[1]_117 (u_ddr_cal_n_1750),
        .\wosp_reg[1]_118 (u_ddr_cal_n_1751),
        .\wosp_reg[1]_119 (u_ddr_cal_n_1752),
        .\wosp_reg[1]_12 (u_ddr_cal_n_1429),
        .\wosp_reg[1]_120 (u_ddr_cal_n_1753),
        .\wosp_reg[1]_121 (u_ddr_cal_n_1754),
        .\wosp_reg[1]_122 (u_ddr_cal_n_1755),
        .\wosp_reg[1]_123 (u_ddr_cal_n_1756),
        .\wosp_reg[1]_124 (u_ddr_cal_n_1757),
        .\wosp_reg[1]_125 (u_ddr_cal_n_1758),
        .\wosp_reg[1]_126 (u_ddr_cal_n_1762),
        .\wosp_reg[1]_127 (u_ddr_cal_n_1796),
        .\wosp_reg[1]_128 (u_ddr_cal_n_1797),
        .\wosp_reg[1]_129 (u_ddr_cal_n_1798),
        .\wosp_reg[1]_13 (u_ddr_cal_n_1430),
        .\wosp_reg[1]_130 (u_ddr_cal_n_1799),
        .\wosp_reg[1]_131 (u_ddr_cal_n_1800),
        .\wosp_reg[1]_132 (u_ddr_cal_n_1801),
        .\wosp_reg[1]_133 (u_ddr_cal_n_1802),
        .\wosp_reg[1]_134 (u_ddr_cal_n_1803),
        .\wosp_reg[1]_135 (u_ddr_cal_n_1804),
        .\wosp_reg[1]_136 (u_ddr_cal_n_1805),
        .\wosp_reg[1]_137 (u_ddr_cal_n_1806),
        .\wosp_reg[1]_138 (u_ddr_cal_n_1807),
        .\wosp_reg[1]_139 (u_ddr_cal_n_1808),
        .\wosp_reg[1]_14 (u_ddr_cal_n_1431),
        .\wosp_reg[1]_140 (u_ddr_cal_n_1809),
        .\wosp_reg[1]_141 (u_ddr_cal_n_1810),
        .\wosp_reg[1]_142 (u_ddr_cal_n_1811),
        .\wosp_reg[1]_15 (u_ddr_cal_n_1432),
        .\wosp_reg[1]_16 (u_ddr_cal_n_1433),
        .\wosp_reg[1]_17 (u_ddr_cal_n_1434),
        .\wosp_reg[1]_18 (u_ddr_cal_n_1438),
        .\wosp_reg[1]_19 (u_ddr_cal_n_1472),
        .\wosp_reg[1]_2 (u_ddr_cal_n_1419),
        .\wosp_reg[1]_20 (u_ddr_cal_n_1473),
        .\wosp_reg[1]_21 (u_ddr_cal_n_1474),
        .\wosp_reg[1]_22 (u_ddr_cal_n_1475),
        .\wosp_reg[1]_23 (u_ddr_cal_n_1476),
        .\wosp_reg[1]_24 (u_ddr_cal_n_1477),
        .\wosp_reg[1]_25 (u_ddr_cal_n_1478),
        .\wosp_reg[1]_26 (u_ddr_cal_n_1479),
        .\wosp_reg[1]_27 (u_ddr_cal_n_1480),
        .\wosp_reg[1]_28 (u_ddr_cal_n_1481),
        .\wosp_reg[1]_29 (u_ddr_cal_n_1482),
        .\wosp_reg[1]_3 (u_ddr_cal_n_1420),
        .\wosp_reg[1]_30 (u_ddr_cal_n_1483),
        .\wosp_reg[1]_31 (u_ddr_cal_n_1484),
        .\wosp_reg[1]_32 (u_ddr_cal_n_1485),
        .\wosp_reg[1]_33 (u_ddr_cal_n_1486),
        .\wosp_reg[1]_34 (u_ddr_cal_n_1487),
        .\wosp_reg[1]_35 (u_ddr_cal_n_1488),
        .\wosp_reg[1]_36 (u_ddr_cal_n_1492),
        .\wosp_reg[1]_37 (u_ddr_cal_n_1526),
        .\wosp_reg[1]_38 (u_ddr_cal_n_1527),
        .\wosp_reg[1]_39 (u_ddr_cal_n_1528),
        .\wosp_reg[1]_4 (u_ddr_cal_n_1421),
        .\wosp_reg[1]_40 (u_ddr_cal_n_1529),
        .\wosp_reg[1]_41 (u_ddr_cal_n_1530),
        .\wosp_reg[1]_42 (u_ddr_cal_n_1531),
        .\wosp_reg[1]_43 (u_ddr_cal_n_1532),
        .\wosp_reg[1]_44 (u_ddr_cal_n_1533),
        .\wosp_reg[1]_45 (u_ddr_cal_n_1534),
        .\wosp_reg[1]_46 (u_ddr_cal_n_1535),
        .\wosp_reg[1]_47 (u_ddr_cal_n_1536),
        .\wosp_reg[1]_48 (u_ddr_cal_n_1537),
        .\wosp_reg[1]_49 (u_ddr_cal_n_1538),
        .\wosp_reg[1]_5 (u_ddr_cal_n_1422),
        .\wosp_reg[1]_50 (u_ddr_cal_n_1539),
        .\wosp_reg[1]_51 (u_ddr_cal_n_1540),
        .\wosp_reg[1]_52 (u_ddr_cal_n_1541),
        .\wosp_reg[1]_53 (u_ddr_cal_n_1542),
        .\wosp_reg[1]_54 (u_ddr_cal_n_1546),
        .\wosp_reg[1]_55 (u_ddr_cal_n_1580),
        .\wosp_reg[1]_56 (u_ddr_cal_n_1581),
        .\wosp_reg[1]_57 (u_ddr_cal_n_1582),
        .\wosp_reg[1]_58 (u_ddr_cal_n_1583),
        .\wosp_reg[1]_59 (u_ddr_cal_n_1584),
        .\wosp_reg[1]_6 (u_ddr_cal_n_1423),
        .\wosp_reg[1]_60 (u_ddr_cal_n_1585),
        .\wosp_reg[1]_61 (u_ddr_cal_n_1586),
        .\wosp_reg[1]_62 (u_ddr_cal_n_1587),
        .\wosp_reg[1]_63 (u_ddr_cal_n_1588),
        .\wosp_reg[1]_64 (u_ddr_cal_n_1589),
        .\wosp_reg[1]_65 (u_ddr_cal_n_1590),
        .\wosp_reg[1]_66 (u_ddr_cal_n_1591),
        .\wosp_reg[1]_67 (u_ddr_cal_n_1592),
        .\wosp_reg[1]_68 (u_ddr_cal_n_1593),
        .\wosp_reg[1]_69 (u_ddr_cal_n_1594),
        .\wosp_reg[1]_7 (u_ddr_cal_n_1424),
        .\wosp_reg[1]_70 (u_ddr_cal_n_1595),
        .\wosp_reg[1]_71 (u_ddr_cal_n_1596),
        .\wosp_reg[1]_72 (u_ddr_cal_n_1600),
        .\wosp_reg[1]_73 (u_ddr_cal_n_1634),
        .\wosp_reg[1]_74 (u_ddr_cal_n_1635),
        .\wosp_reg[1]_75 (u_ddr_cal_n_1636),
        .\wosp_reg[1]_76 (u_ddr_cal_n_1637),
        .\wosp_reg[1]_77 (u_ddr_cal_n_1638),
        .\wosp_reg[1]_78 (u_ddr_cal_n_1639),
        .\wosp_reg[1]_79 (u_ddr_cal_n_1640),
        .\wosp_reg[1]_8 (u_ddr_cal_n_1425),
        .\wosp_reg[1]_80 (u_ddr_cal_n_1641),
        .\wosp_reg[1]_81 (u_ddr_cal_n_1642),
        .\wosp_reg[1]_82 (u_ddr_cal_n_1643),
        .\wosp_reg[1]_83 (u_ddr_cal_n_1644),
        .\wosp_reg[1]_84 (u_ddr_cal_n_1645),
        .\wosp_reg[1]_85 (u_ddr_cal_n_1646),
        .\wosp_reg[1]_86 (u_ddr_cal_n_1647),
        .\wosp_reg[1]_87 (u_ddr_cal_n_1648),
        .\wosp_reg[1]_88 (u_ddr_cal_n_1649),
        .\wosp_reg[1]_89 (u_ddr_cal_n_1650),
        .\wosp_reg[1]_9 (u_ddr_cal_n_1426),
        .\wosp_reg[1]_90 (u_ddr_cal_n_1654),
        .\wosp_reg[1]_91 (u_ddr_cal_n_1688),
        .\wosp_reg[1]_92 (u_ddr_cal_n_1689),
        .\wosp_reg[1]_93 (u_ddr_cal_n_1690),
        .\wosp_reg[1]_94 (u_ddr_cal_n_1691),
        .\wosp_reg[1]_95 (u_ddr_cal_n_1692),
        .\wosp_reg[1]_96 (u_ddr_cal_n_1693),
        .\wosp_reg[1]_97 (u_ddr_cal_n_1694),
        .\wosp_reg[1]_98 (u_ddr_cal_n_1695),
        .\wosp_reg[1]_99 (u_ddr_cal_n_1696),
        .\wosp_reg[2] (\u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/dReg0_out ),
        .\wosp_reg[2]_0 (u_ddr_cal_n_1761),
        .\wosp_reg[2]_rep (\u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/dReg0_out ),
        .\wosp_reg[2]_rep_0 (u_ddr_cal_n_1383),
        .\wosp_reg[2]_rep_1 (\u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/dReg0_out ),
        .\wosp_reg[2]_rep_2 (u_ddr_cal_n_1437),
        .\wosp_reg[2]_rep_3 (\u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/dReg0_out ),
        .\wosp_reg[2]_rep_4 (u_ddr_cal_n_1491),
        .\wosp_reg[2]_rep__0 (\u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/dReg0_out ),
        .\wosp_reg[2]_rep__0_0 (u_ddr_cal_n_1545),
        .\wosp_reg[2]_rep__0_1 (\u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/dReg0_out ),
        .\wosp_reg[2]_rep__0_2 (u_ddr_cal_n_1599),
        .\wosp_reg[2]_rep__0_3 (\u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/dReg0_out ),
        .\wosp_reg[2]_rep__0_4 (u_ddr_cal_n_1653),
        .\wosp_reg[2]_rep__1 ({u_ddr_cal_n_1386,u_ddr_cal_n_1387}),
        .\wosp_reg[2]_rep__1_0 (u_ddr_cal_n_1388),
        .\wosp_reg[2]_rep__1_1 (u_ddr_cal_n_1389),
        .\wosp_reg[2]_rep__1_10 (u_ddr_cal_n_1401),
        .\wosp_reg[2]_rep__1_11 (u_ddr_cal_n_1404),
        .\wosp_reg[2]_rep__1_12 (\u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/dReg0_out ),
        .\wosp_reg[2]_rep__1_13 (u_ddr_cal_n_1707),
        .\wosp_reg[2]_rep__1_2 ({u_ddr_cal_n_1390,u_ddr_cal_n_1391}),
        .\wosp_reg[2]_rep__1_3 (u_ddr_cal_n_1392),
        .\wosp_reg[2]_rep__1_4 (u_ddr_cal_n_1393),
        .\wosp_reg[2]_rep__1_5 ({u_ddr_cal_n_1394,u_ddr_cal_n_1395}),
        .\wosp_reg[2]_rep__1_6 (u_ddr_cal_n_1396),
        .\wosp_reg[2]_rep__1_7 (u_ddr_cal_n_1397),
        .\wosp_reg[2]_rep__1_8 ({u_ddr_cal_n_1398,u_ddr_cal_n_1399}),
        .\wosp_reg[2]_rep__1_9 (u_ddr_cal_n_1400),
        .\wosp_reg[2]_rep__2 (u_ddr_cal_n_1385),
        .\wosp_reg[2]_rep__2_0 ({u_ddr_cal_n_1402,u_ddr_cal_n_1403}),
        .\wosp_reg[2]_rep__2_1 (u_ddr_cal_n_1405),
        .\wosp_reg[2]_rep__2_10 (u_ddr_cal_n_1417),
        .\wosp_reg[2]_rep__2_11 ({u_ddr_cal_n_1440,u_ddr_cal_n_1441}),
        .\wosp_reg[2]_rep__2_12 (u_ddr_cal_n_1442),
        .\wosp_reg[2]_rep__2_13 (u_ddr_cal_n_1443),
        .\wosp_reg[2]_rep__2_14 ({u_ddr_cal_n_1444,u_ddr_cal_n_1445}),
        .\wosp_reg[2]_rep__2_15 (u_ddr_cal_n_1446),
        .\wosp_reg[2]_rep__2_16 (u_ddr_cal_n_1447),
        .\wosp_reg[2]_rep__2_17 ({u_ddr_cal_n_1448,u_ddr_cal_n_1449}),
        .\wosp_reg[2]_rep__2_18 (u_ddr_cal_n_1450),
        .\wosp_reg[2]_rep__2_19 (u_ddr_cal_n_1451),
        .\wosp_reg[2]_rep__2_2 ({u_ddr_cal_n_1406,u_ddr_cal_n_1407}),
        .\wosp_reg[2]_rep__2_20 ({u_ddr_cal_n_1452,u_ddr_cal_n_1453}),
        .\wosp_reg[2]_rep__2_21 (u_ddr_cal_n_1454),
        .\wosp_reg[2]_rep__2_22 (u_ddr_cal_n_1455),
        .\wosp_reg[2]_rep__2_23 ({u_ddr_cal_n_1456,u_ddr_cal_n_1457}),
        .\wosp_reg[2]_rep__2_24 (u_ddr_cal_n_1458),
        .\wosp_reg[2]_rep__2_25 (u_ddr_cal_n_1459),
        .\wosp_reg[2]_rep__2_26 ({u_ddr_cal_n_1460,u_ddr_cal_n_1461}),
        .\wosp_reg[2]_rep__2_27 (u_ddr_cal_n_1462),
        .\wosp_reg[2]_rep__2_28 (u_ddr_cal_n_1463),
        .\wosp_reg[2]_rep__2_29 ({u_ddr_cal_n_1464,u_ddr_cal_n_1465}),
        .\wosp_reg[2]_rep__2_3 (u_ddr_cal_n_1408),
        .\wosp_reg[2]_rep__2_30 (u_ddr_cal_n_1466),
        .\wosp_reg[2]_rep__2_31 (u_ddr_cal_n_1467),
        .\wosp_reg[2]_rep__2_32 ({u_ddr_cal_n_1468,u_ddr_cal_n_1469}),
        .\wosp_reg[2]_rep__2_33 (u_ddr_cal_n_1470),
        .\wosp_reg[2]_rep__2_34 (u_ddr_cal_n_1471),
        .\wosp_reg[2]_rep__2_4 (u_ddr_cal_n_1409),
        .\wosp_reg[2]_rep__2_5 ({u_ddr_cal_n_1410,u_ddr_cal_n_1411}),
        .\wosp_reg[2]_rep__2_6 (u_ddr_cal_n_1412),
        .\wosp_reg[2]_rep__2_7 (u_ddr_cal_n_1413),
        .\wosp_reg[2]_rep__2_8 ({u_ddr_cal_n_1414,u_ddr_cal_n_1415}),
        .\wosp_reg[2]_rep__2_9 (u_ddr_cal_n_1416),
        .\wosp_reg[2]_rep__3 (u_ddr_cal_n_1439),
        .\wosp_reg[2]_rep__3_0 (u_ddr_cal_n_1493),
        .\wosp_reg[2]_rep__3_1 ({u_ddr_cal_n_1494,u_ddr_cal_n_1495}),
        .\wosp_reg[2]_rep__3_10 ({u_ddr_cal_n_1506,u_ddr_cal_n_1507}),
        .\wosp_reg[2]_rep__3_11 (u_ddr_cal_n_1508),
        .\wosp_reg[2]_rep__3_12 (u_ddr_cal_n_1509),
        .\wosp_reg[2]_rep__3_13 ({u_ddr_cal_n_1510,u_ddr_cal_n_1511}),
        .\wosp_reg[2]_rep__3_14 (u_ddr_cal_n_1512),
        .\wosp_reg[2]_rep__3_15 (u_ddr_cal_n_1513),
        .\wosp_reg[2]_rep__3_16 ({u_ddr_cal_n_1514,u_ddr_cal_n_1515}),
        .\wosp_reg[2]_rep__3_17 (u_ddr_cal_n_1516),
        .\wosp_reg[2]_rep__3_18 (u_ddr_cal_n_1517),
        .\wosp_reg[2]_rep__3_19 ({u_ddr_cal_n_1518,u_ddr_cal_n_1519}),
        .\wosp_reg[2]_rep__3_2 (u_ddr_cal_n_1496),
        .\wosp_reg[2]_rep__3_20 (u_ddr_cal_n_1520),
        .\wosp_reg[2]_rep__3_21 (u_ddr_cal_n_1521),
        .\wosp_reg[2]_rep__3_22 ({u_ddr_cal_n_1522,u_ddr_cal_n_1523}),
        .\wosp_reg[2]_rep__3_23 (u_ddr_cal_n_1524),
        .\wosp_reg[2]_rep__3_24 (u_ddr_cal_n_1525),
        .\wosp_reg[2]_rep__3_25 ({u_ddr_cal_n_1548,u_ddr_cal_n_1549}),
        .\wosp_reg[2]_rep__3_26 (u_ddr_cal_n_1550),
        .\wosp_reg[2]_rep__3_27 (u_ddr_cal_n_1551),
        .\wosp_reg[2]_rep__3_28 ({u_ddr_cal_n_1552,u_ddr_cal_n_1553}),
        .\wosp_reg[2]_rep__3_29 (u_ddr_cal_n_1554),
        .\wosp_reg[2]_rep__3_3 (u_ddr_cal_n_1497),
        .\wosp_reg[2]_rep__3_30 (u_ddr_cal_n_1555),
        .\wosp_reg[2]_rep__3_31 ({u_ddr_cal_n_1556,u_ddr_cal_n_1557}),
        .\wosp_reg[2]_rep__3_32 (u_ddr_cal_n_1558),
        .\wosp_reg[2]_rep__3_33 (u_ddr_cal_n_1559),
        .\wosp_reg[2]_rep__3_4 ({u_ddr_cal_n_1498,u_ddr_cal_n_1499}),
        .\wosp_reg[2]_rep__3_5 (u_ddr_cal_n_1500),
        .\wosp_reg[2]_rep__3_6 (u_ddr_cal_n_1501),
        .\wosp_reg[2]_rep__3_7 ({u_ddr_cal_n_1502,u_ddr_cal_n_1503}),
        .\wosp_reg[2]_rep__3_8 (u_ddr_cal_n_1504),
        .\wosp_reg[2]_rep__3_9 (u_ddr_cal_n_1505),
        .\wosp_reg[2]_rep__4 (u_ddr_cal_n_1547),
        .\wosp_reg[2]_rep__4_0 ({u_ddr_cal_n_1560,u_ddr_cal_n_1561}),
        .\wosp_reg[2]_rep__4_1 (u_ddr_cal_n_1562),
        .\wosp_reg[2]_rep__4_10 (u_ddr_cal_n_1574),
        .\wosp_reg[2]_rep__4_11 (u_ddr_cal_n_1575),
        .\wosp_reg[2]_rep__4_12 ({u_ddr_cal_n_1576,u_ddr_cal_n_1577}),
        .\wosp_reg[2]_rep__4_13 (u_ddr_cal_n_1578),
        .\wosp_reg[2]_rep__4_14 (u_ddr_cal_n_1579),
        .\wosp_reg[2]_rep__4_15 ({u_ddr_cal_n_1602,u_ddr_cal_n_1603}),
        .\wosp_reg[2]_rep__4_16 (u_ddr_cal_n_1604),
        .\wosp_reg[2]_rep__4_17 (u_ddr_cal_n_1605),
        .\wosp_reg[2]_rep__4_18 ({u_ddr_cal_n_1606,u_ddr_cal_n_1607}),
        .\wosp_reg[2]_rep__4_19 (u_ddr_cal_n_1608),
        .\wosp_reg[2]_rep__4_2 (u_ddr_cal_n_1563),
        .\wosp_reg[2]_rep__4_20 (u_ddr_cal_n_1609),
        .\wosp_reg[2]_rep__4_21 ({u_ddr_cal_n_1610,u_ddr_cal_n_1611}),
        .\wosp_reg[2]_rep__4_22 (u_ddr_cal_n_1612),
        .\wosp_reg[2]_rep__4_23 (u_ddr_cal_n_1613),
        .\wosp_reg[2]_rep__4_24 ({u_ddr_cal_n_1614,u_ddr_cal_n_1615}),
        .\wosp_reg[2]_rep__4_25 (u_ddr_cal_n_1616),
        .\wosp_reg[2]_rep__4_26 (u_ddr_cal_n_1617),
        .\wosp_reg[2]_rep__4_27 ({u_ddr_cal_n_1618,u_ddr_cal_n_1619}),
        .\wosp_reg[2]_rep__4_28 (u_ddr_cal_n_1620),
        .\wosp_reg[2]_rep__4_29 (u_ddr_cal_n_1621),
        .\wosp_reg[2]_rep__4_3 ({u_ddr_cal_n_1564,u_ddr_cal_n_1565}),
        .\wosp_reg[2]_rep__4_30 ({u_ddr_cal_n_1622,u_ddr_cal_n_1623}),
        .\wosp_reg[2]_rep__4_31 (u_ddr_cal_n_1624),
        .\wosp_reg[2]_rep__4_32 (u_ddr_cal_n_1625),
        .\wosp_reg[2]_rep__4_33 (u_ddr_cal_n_1628),
        .\wosp_reg[2]_rep__4_4 (u_ddr_cal_n_1566),
        .\wosp_reg[2]_rep__4_5 (u_ddr_cal_n_1567),
        .\wosp_reg[2]_rep__4_6 ({u_ddr_cal_n_1568,u_ddr_cal_n_1569}),
        .\wosp_reg[2]_rep__4_7 (u_ddr_cal_n_1570),
        .\wosp_reg[2]_rep__4_8 (u_ddr_cal_n_1571),
        .\wosp_reg[2]_rep__4_9 ({u_ddr_cal_n_1572,u_ddr_cal_n_1573}),
        .\wosp_reg[2]_rep__5 (u_ddr_cal_n_1601),
        .\wosp_reg[2]_rep__5_0 ({u_ddr_cal_n_1626,u_ddr_cal_n_1627}),
        .\wosp_reg[2]_rep__5_1 (u_ddr_cal_n_1629),
        .\wosp_reg[2]_rep__5_10 (u_ddr_cal_n_1662),
        .\wosp_reg[2]_rep__5_11 (u_ddr_cal_n_1663),
        .\wosp_reg[2]_rep__5_12 ({u_ddr_cal_n_1664,u_ddr_cal_n_1665}),
        .\wosp_reg[2]_rep__5_13 (u_ddr_cal_n_1666),
        .\wosp_reg[2]_rep__5_14 (u_ddr_cal_n_1667),
        .\wosp_reg[2]_rep__5_15 ({u_ddr_cal_n_1668,u_ddr_cal_n_1669}),
        .\wosp_reg[2]_rep__5_16 (u_ddr_cal_n_1670),
        .\wosp_reg[2]_rep__5_17 (u_ddr_cal_n_1671),
        .\wosp_reg[2]_rep__5_18 ({u_ddr_cal_n_1672,u_ddr_cal_n_1673}),
        .\wosp_reg[2]_rep__5_19 (u_ddr_cal_n_1674),
        .\wosp_reg[2]_rep__5_2 ({u_ddr_cal_n_1630,u_ddr_cal_n_1631}),
        .\wosp_reg[2]_rep__5_20 (u_ddr_cal_n_1675),
        .\wosp_reg[2]_rep__5_21 ({u_ddr_cal_n_1676,u_ddr_cal_n_1677}),
        .\wosp_reg[2]_rep__5_22 (u_ddr_cal_n_1678),
        .\wosp_reg[2]_rep__5_23 (u_ddr_cal_n_1679),
        .\wosp_reg[2]_rep__5_24 ({u_ddr_cal_n_1680,u_ddr_cal_n_1681}),
        .\wosp_reg[2]_rep__5_25 (u_ddr_cal_n_1682),
        .\wosp_reg[2]_rep__5_26 (u_ddr_cal_n_1683),
        .\wosp_reg[2]_rep__5_27 ({u_ddr_cal_n_1684,u_ddr_cal_n_1685}),
        .\wosp_reg[2]_rep__5_28 (u_ddr_cal_n_1686),
        .\wosp_reg[2]_rep__5_29 (u_ddr_cal_n_1687),
        .\wosp_reg[2]_rep__5_3 (u_ddr_cal_n_1632),
        .\wosp_reg[2]_rep__5_30 ({u_ddr_cal_n_1710,u_ddr_cal_n_1711}),
        .\wosp_reg[2]_rep__5_31 (u_ddr_cal_n_1712),
        .\wosp_reg[2]_rep__5_32 (u_ddr_cal_n_1713),
        .\wosp_reg[2]_rep__5_33 (u_ddr_cal_n_1716),
        .\wosp_reg[2]_rep__5_4 (u_ddr_cal_n_1633),
        .\wosp_reg[2]_rep__5_5 (u_ddr_cal_n_1655),
        .\wosp_reg[2]_rep__5_6 ({u_ddr_cal_n_1656,u_ddr_cal_n_1657}),
        .\wosp_reg[2]_rep__5_7 (u_ddr_cal_n_1658),
        .\wosp_reg[2]_rep__5_8 (u_ddr_cal_n_1659),
        .\wosp_reg[2]_rep__5_9 ({u_ddr_cal_n_1660,u_ddr_cal_n_1661}),
        .\wosp_reg[2]_rep__6 (u_ddr_cal_n_1709),
        .\wosp_reg[2]_rep__6_0 ({u_ddr_cal_n_1714,u_ddr_cal_n_1715}),
        .\wosp_reg[2]_rep__6_1 (u_ddr_cal_n_1717),
        .\wosp_reg[2]_rep__6_10 (u_ddr_cal_n_1729),
        .\wosp_reg[2]_rep__6_11 ({u_ddr_cal_n_1730,u_ddr_cal_n_1731}),
        .\wosp_reg[2]_rep__6_12 (u_ddr_cal_n_1732),
        .\wosp_reg[2]_rep__6_13 (u_ddr_cal_n_1733),
        .\wosp_reg[2]_rep__6_14 ({u_ddr_cal_n_1734,u_ddr_cal_n_1735}),
        .\wosp_reg[2]_rep__6_15 (u_ddr_cal_n_1736),
        .\wosp_reg[2]_rep__6_16 (u_ddr_cal_n_1737),
        .\wosp_reg[2]_rep__6_17 ({u_ddr_cal_n_1738,u_ddr_cal_n_1739}),
        .\wosp_reg[2]_rep__6_18 (u_ddr_cal_n_1740),
        .\wosp_reg[2]_rep__6_19 (u_ddr_cal_n_1741),
        .\wosp_reg[2]_rep__6_2 ({u_ddr_cal_n_1718,u_ddr_cal_n_1719}),
        .\wosp_reg[2]_rep__6_20 (u_ddr_cal_n_1763),
        .\wosp_reg[2]_rep__6_21 (u_ddr_cal_n_1767),
        .\wosp_reg[2]_rep__6_22 ({u_ddr_cal_n_1768,u_ddr_cal_n_1769}),
        .\wosp_reg[2]_rep__6_23 (u_ddr_cal_n_1770),
        .\wosp_reg[2]_rep__6_24 (u_ddr_cal_n_1771),
        .\wosp_reg[2]_rep__6_25 ({u_ddr_cal_n_1772,u_ddr_cal_n_1773}),
        .\wosp_reg[2]_rep__6_26 (u_ddr_cal_n_1774),
        .\wosp_reg[2]_rep__6_27 (u_ddr_cal_n_1775),
        .\wosp_reg[2]_rep__6_28 ({u_ddr_cal_n_1776,u_ddr_cal_n_1777}),
        .\wosp_reg[2]_rep__6_29 (u_ddr_cal_n_1778),
        .\wosp_reg[2]_rep__6_3 (u_ddr_cal_n_1720),
        .\wosp_reg[2]_rep__6_30 (u_ddr_cal_n_1779),
        .\wosp_reg[2]_rep__6_31 ({u_ddr_cal_n_1780,u_ddr_cal_n_1781}),
        .\wosp_reg[2]_rep__6_32 (u_ddr_cal_n_1782),
        .\wosp_reg[2]_rep__6_33 (u_ddr_cal_n_1783),
        .\wosp_reg[2]_rep__6_34 ({u_ddr_cal_n_1784,u_ddr_cal_n_1785}),
        .\wosp_reg[2]_rep__6_35 (u_ddr_cal_n_1786),
        .\wosp_reg[2]_rep__6_36 (u_ddr_cal_n_1787),
        .\wosp_reg[2]_rep__6_37 ({u_ddr_cal_n_1788,u_ddr_cal_n_1789}),
        .\wosp_reg[2]_rep__6_38 (u_ddr_cal_n_1790),
        .\wosp_reg[2]_rep__6_39 (u_ddr_cal_n_1791),
        .\wosp_reg[2]_rep__6_4 (u_ddr_cal_n_1721),
        .\wosp_reg[2]_rep__6_40 ({u_ddr_cal_n_1792,u_ddr_cal_n_1793}),
        .\wosp_reg[2]_rep__6_41 (u_ddr_cal_n_1794),
        .\wosp_reg[2]_rep__6_42 (u_ddr_cal_n_1795),
        .\wosp_reg[2]_rep__6_5 ({u_ddr_cal_n_1722,u_ddr_cal_n_1723}),
        .\wosp_reg[2]_rep__6_6 (u_ddr_cal_n_1724),
        .\wosp_reg[2]_rep__6_7 (u_ddr_cal_n_1725),
        .\wosp_reg[2]_rep__6_8 ({u_ddr_cal_n_1726,u_ddr_cal_n_1727}),
        .\wosp_reg[2]_rep__6_9 (u_ddr_cal_n_1728),
        .\wosp_reg[2]_rep__7 ({u_ddr_cal_n_1764,u_ddr_cal_n_1765}),
        .\wosp_reg[2]_rep__7_0 (u_ddr_cal_n_1766),
        .wrCAS_reg(calWrCAS),
        .wrDataEn_pi(wrDataEn_pi),
        .wrDataVal(\u_ddr_mc_write/wrDataVal ),
        .\wrQ_nxt[1]_13 (\u_ddr_mc_write/wrQ_nxt[1]_13 ),
        .\wrQ_reg[1][0] (oe_0_mux_cal),
        .wren_reg(u_ddr_mc_pi_n_865),
        .xsdb_wr_en_reg(xsdb_wr_en_reg));
  ddr4_0_ddr4_v2_2_17_cal_pi u_ddr_mc_pi
       (.ADDRA(ADDRA),
        .ADDRC(ADDRC),
        .D(D),
        .DMOut(DMOut),
        .DOA(DOA),
        .DOB(DOB),
        .DOC(DOC),
        .DQOut(DQOut),
        .Q(\rdDataAddr_reg[4] ),
        .SR(SR),
        .\blk1.(null)[0].diff (\rdEn[1].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_0 (\rdEn[7].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_1 (\rdEn[6].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_11 (\rdEn[0].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_13 (\rdEn[5].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_15 (\rdEn[5].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_17 (\rdEn[4].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_19 (\rdEn[6].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_21 (\rdEn[3].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_23 (\rdEn[2].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_25 (\rdEn[1].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_27 (\rdEn[0].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_3 (\rdEn[3].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_5 (\rdEn[2].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_7 (\rdEn[4].u_ddr_mc_rd_en_upp/blk1.(null)[0].diff ),
        .\blk1.(null)[0].diff_9 (\rdEn[7].u_ddr_mc_rd_en_low/blk1.(null)[0].diff ),
        .calDone_reg(rd_data_en_phy2mc),
        .calRdCAS(calRdCAS),
        .cal_clear_fifo_rden(cal_clear_fifo_rden),
        .cal_oe_dis_low(cal_oe_dis_low),
        .cal_oe_dis_upp(cal_oe_dis_upp),
        .ch0_mcal_DMOut_n(ch0_mcal_DMOut_n),
        .ch0_mcal_DQOut(ch0_mcal_DQOut),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .cmdBuf(cmdBuf),
        .cnt_clr(cnt_clr),
        .\dReg_reg[10] (\dReg_reg[10] ),
        .\dReg_reg[10]_0 (u_ddr_cal_n_1384),
        .\dReg_reg[10]_1 (u_ddr_cal_n_1419),
        .\dReg_reg[10]_10 (u_ddr_cal_n_1473),
        .\dReg_reg[10]_11 (u_ddr_cal_n_1475),
        .\dReg_reg[10]_12 (u_ddr_cal_n_1477),
        .\dReg_reg[10]_13 (u_ddr_cal_n_1479),
        .\dReg_reg[10]_14 (u_ddr_cal_n_1481),
        .\dReg_reg[10]_15 (u_ddr_cal_n_1483),
        .\dReg_reg[10]_16 (u_ddr_cal_n_1485),
        .\dReg_reg[10]_17 (u_ddr_cal_n_1487),
        .\dReg_reg[10]_18 (u_ddr_cal_n_1492),
        .\dReg_reg[10]_19 (u_ddr_cal_n_1527),
        .\dReg_reg[10]_2 (u_ddr_cal_n_1421),
        .\dReg_reg[10]_20 (u_ddr_cal_n_1529),
        .\dReg_reg[10]_21 (u_ddr_cal_n_1531),
        .\dReg_reg[10]_22 (u_ddr_cal_n_1533),
        .\dReg_reg[10]_23 (u_ddr_cal_n_1535),
        .\dReg_reg[10]_24 (u_ddr_cal_n_1537),
        .\dReg_reg[10]_25 (u_ddr_cal_n_1539),
        .\dReg_reg[10]_26 (u_ddr_cal_n_1541),
        .\dReg_reg[10]_27 (u_ddr_cal_n_1546),
        .\dReg_reg[10]_28 (u_ddr_cal_n_1581),
        .\dReg_reg[10]_29 (u_ddr_cal_n_1583),
        .\dReg_reg[10]_3 (u_ddr_cal_n_1423),
        .\dReg_reg[10]_30 (u_ddr_cal_n_1585),
        .\dReg_reg[10]_31 (u_ddr_cal_n_1587),
        .\dReg_reg[10]_32 (u_ddr_cal_n_1589),
        .\dReg_reg[10]_33 (u_ddr_cal_n_1591),
        .\dReg_reg[10]_34 (u_ddr_cal_n_1593),
        .\dReg_reg[10]_35 (u_ddr_cal_n_1595),
        .\dReg_reg[10]_36 (u_ddr_cal_n_1600),
        .\dReg_reg[10]_37 (u_ddr_cal_n_1635),
        .\dReg_reg[10]_38 (u_ddr_cal_n_1637),
        .\dReg_reg[10]_39 (u_ddr_cal_n_1639),
        .\dReg_reg[10]_4 (u_ddr_cal_n_1425),
        .\dReg_reg[10]_40 (u_ddr_cal_n_1641),
        .\dReg_reg[10]_41 (u_ddr_cal_n_1643),
        .\dReg_reg[10]_42 (u_ddr_cal_n_1645),
        .\dReg_reg[10]_43 (u_ddr_cal_n_1647),
        .\dReg_reg[10]_44 (u_ddr_cal_n_1649),
        .\dReg_reg[10]_45 (u_ddr_cal_n_1654),
        .\dReg_reg[10]_46 (u_ddr_cal_n_1689),
        .\dReg_reg[10]_47 (u_ddr_cal_n_1691),
        .\dReg_reg[10]_48 (u_ddr_cal_n_1693),
        .\dReg_reg[10]_49 (u_ddr_cal_n_1695),
        .\dReg_reg[10]_5 (u_ddr_cal_n_1427),
        .\dReg_reg[10]_50 (u_ddr_cal_n_1697),
        .\dReg_reg[10]_51 (u_ddr_cal_n_1699),
        .\dReg_reg[10]_52 (u_ddr_cal_n_1701),
        .\dReg_reg[10]_53 (u_ddr_cal_n_1703),
        .\dReg_reg[10]_54 (u_ddr_cal_n_1708),
        .\dReg_reg[10]_55 (u_ddr_cal_n_1743),
        .\dReg_reg[10]_56 (u_ddr_cal_n_1745),
        .\dReg_reg[10]_57 (u_ddr_cal_n_1747),
        .\dReg_reg[10]_58 (u_ddr_cal_n_1749),
        .\dReg_reg[10]_59 (u_ddr_cal_n_1751),
        .\dReg_reg[10]_6 (u_ddr_cal_n_1429),
        .\dReg_reg[10]_60 (u_ddr_cal_n_1753),
        .\dReg_reg[10]_61 (u_ddr_cal_n_1755),
        .\dReg_reg[10]_62 (u_ddr_cal_n_1757),
        .\dReg_reg[10]_63 (u_ddr_cal_n_1762),
        .\dReg_reg[10]_64 (u_ddr_cal_n_1797),
        .\dReg_reg[10]_65 (u_ddr_cal_n_1799),
        .\dReg_reg[10]_66 (u_ddr_cal_n_1801),
        .\dReg_reg[10]_67 (u_ddr_cal_n_1803),
        .\dReg_reg[10]_68 (u_ddr_cal_n_1805),
        .\dReg_reg[10]_69 (u_ddr_cal_n_1807),
        .\dReg_reg[10]_7 (u_ddr_cal_n_1431),
        .\dReg_reg[10]_70 (u_ddr_cal_n_1809),
        .\dReg_reg[10]_71 (u_ddr_cal_n_1811),
        .\dReg_reg[10]_8 (u_ddr_cal_n_1433),
        .\dReg_reg[10]_9 (u_ddr_cal_n_1438),
        .\dReg_reg[11] (u_ddr_cal_n_1380),
        .\dReg_reg[11]_0 (u_ddr_cal_n_1418),
        .\dReg_reg[11]_1 (u_ddr_cal_n_1420),
        .\dReg_reg[11]_10 (u_ddr_cal_n_1474),
        .\dReg_reg[11]_11 (u_ddr_cal_n_1476),
        .\dReg_reg[11]_12 (u_ddr_cal_n_1478),
        .\dReg_reg[11]_13 (u_ddr_cal_n_1480),
        .\dReg_reg[11]_14 (u_ddr_cal_n_1482),
        .\dReg_reg[11]_15 (u_ddr_cal_n_1484),
        .\dReg_reg[11]_16 (u_ddr_cal_n_1486),
        .\dReg_reg[11]_17 (u_ddr_cal_n_1488),
        .\dReg_reg[11]_18 (u_ddr_cal_n_1526),
        .\dReg_reg[11]_19 (u_ddr_cal_n_1528),
        .\dReg_reg[11]_2 (u_ddr_cal_n_1422),
        .\dReg_reg[11]_20 (u_ddr_cal_n_1530),
        .\dReg_reg[11]_21 (u_ddr_cal_n_1532),
        .\dReg_reg[11]_22 (u_ddr_cal_n_1534),
        .\dReg_reg[11]_23 (u_ddr_cal_n_1536),
        .\dReg_reg[11]_24 (u_ddr_cal_n_1538),
        .\dReg_reg[11]_25 (u_ddr_cal_n_1540),
        .\dReg_reg[11]_26 (u_ddr_cal_n_1542),
        .\dReg_reg[11]_27 (u_ddr_cal_n_1580),
        .\dReg_reg[11]_28 (u_ddr_cal_n_1582),
        .\dReg_reg[11]_29 (u_ddr_cal_n_1584),
        .\dReg_reg[11]_3 (u_ddr_cal_n_1424),
        .\dReg_reg[11]_30 (u_ddr_cal_n_1586),
        .\dReg_reg[11]_31 (u_ddr_cal_n_1588),
        .\dReg_reg[11]_32 (u_ddr_cal_n_1590),
        .\dReg_reg[11]_33 (u_ddr_cal_n_1592),
        .\dReg_reg[11]_34 (u_ddr_cal_n_1594),
        .\dReg_reg[11]_35 (u_ddr_cal_n_1596),
        .\dReg_reg[11]_36 (u_ddr_cal_n_1634),
        .\dReg_reg[11]_37 (u_ddr_cal_n_1636),
        .\dReg_reg[11]_38 (u_ddr_cal_n_1638),
        .\dReg_reg[11]_39 (u_ddr_cal_n_1640),
        .\dReg_reg[11]_4 (u_ddr_cal_n_1426),
        .\dReg_reg[11]_40 (u_ddr_cal_n_1642),
        .\dReg_reg[11]_41 (u_ddr_cal_n_1644),
        .\dReg_reg[11]_42 (u_ddr_cal_n_1646),
        .\dReg_reg[11]_43 (u_ddr_cal_n_1648),
        .\dReg_reg[11]_44 (u_ddr_cal_n_1650),
        .\dReg_reg[11]_45 (u_ddr_cal_n_1688),
        .\dReg_reg[11]_46 (u_ddr_cal_n_1690),
        .\dReg_reg[11]_47 (u_ddr_cal_n_1692),
        .\dReg_reg[11]_48 (u_ddr_cal_n_1694),
        .\dReg_reg[11]_49 (u_ddr_cal_n_1696),
        .\dReg_reg[11]_5 (u_ddr_cal_n_1428),
        .\dReg_reg[11]_50 (u_ddr_cal_n_1698),
        .\dReg_reg[11]_51 (u_ddr_cal_n_1700),
        .\dReg_reg[11]_52 (u_ddr_cal_n_1702),
        .\dReg_reg[11]_53 (u_ddr_cal_n_1704),
        .\dReg_reg[11]_54 (u_ddr_cal_n_1742),
        .\dReg_reg[11]_55 (u_ddr_cal_n_1744),
        .\dReg_reg[11]_56 (u_ddr_cal_n_1746),
        .\dReg_reg[11]_57 (u_ddr_cal_n_1748),
        .\dReg_reg[11]_58 (u_ddr_cal_n_1750),
        .\dReg_reg[11]_59 (u_ddr_cal_n_1752),
        .\dReg_reg[11]_6 (u_ddr_cal_n_1430),
        .\dReg_reg[11]_60 (u_ddr_cal_n_1754),
        .\dReg_reg[11]_61 (u_ddr_cal_n_1756),
        .\dReg_reg[11]_62 (u_ddr_cal_n_1758),
        .\dReg_reg[11]_63 (u_ddr_cal_n_1796),
        .\dReg_reg[11]_64 (u_ddr_cal_n_1798),
        .\dReg_reg[11]_65 (u_ddr_cal_n_1800),
        .\dReg_reg[11]_66 (u_ddr_cal_n_1802),
        .\dReg_reg[11]_67 (u_ddr_cal_n_1804),
        .\dReg_reg[11]_68 (u_ddr_cal_n_1806),
        .\dReg_reg[11]_69 (u_ddr_cal_n_1808),
        .\dReg_reg[11]_7 (u_ddr_cal_n_1432),
        .\dReg_reg[11]_70 (u_ddr_cal_n_1810),
        .\dReg_reg[11]_8 (u_ddr_cal_n_1434),
        .\dReg_reg[11]_9 (u_ddr_cal_n_1472),
        .\dReg_reg[6] (u_ddr_cal_n_1385),
        .\dReg_reg[6]_0 (u_ddr_cal_n_1416),
        .\dReg_reg[6]_1 (u_ddr_cal_n_1412),
        .\dReg_reg[6]_10 (u_ddr_cal_n_1466),
        .\dReg_reg[6]_11 (u_ddr_cal_n_1462),
        .\dReg_reg[6]_12 (u_ddr_cal_n_1458),
        .\dReg_reg[6]_13 (u_ddr_cal_n_1454),
        .\dReg_reg[6]_14 (u_ddr_cal_n_1450),
        .\dReg_reg[6]_15 (u_ddr_cal_n_1446),
        .\dReg_reg[6]_16 (u_ddr_cal_n_1442),
        .\dReg_reg[6]_17 (u_ddr_cal_n_1493),
        .\dReg_reg[6]_18 (u_ddr_cal_n_1524),
        .\dReg_reg[6]_19 (u_ddr_cal_n_1520),
        .\dReg_reg[6]_2 (u_ddr_cal_n_1408),
        .\dReg_reg[6]_20 (u_ddr_cal_n_1516),
        .\dReg_reg[6]_21 (u_ddr_cal_n_1512),
        .\dReg_reg[6]_22 (u_ddr_cal_n_1508),
        .\dReg_reg[6]_23 (u_ddr_cal_n_1504),
        .\dReg_reg[6]_24 (u_ddr_cal_n_1500),
        .\dReg_reg[6]_25 (u_ddr_cal_n_1496),
        .\dReg_reg[6]_26 (u_ddr_cal_n_1547),
        .\dReg_reg[6]_27 (u_ddr_cal_n_1578),
        .\dReg_reg[6]_28 (u_ddr_cal_n_1574),
        .\dReg_reg[6]_29 (u_ddr_cal_n_1570),
        .\dReg_reg[6]_3 (u_ddr_cal_n_1404),
        .\dReg_reg[6]_30 (u_ddr_cal_n_1566),
        .\dReg_reg[6]_31 (u_ddr_cal_n_1562),
        .\dReg_reg[6]_32 (u_ddr_cal_n_1558),
        .\dReg_reg[6]_33 (u_ddr_cal_n_1554),
        .\dReg_reg[6]_34 (u_ddr_cal_n_1550),
        .\dReg_reg[6]_35 (u_ddr_cal_n_1601),
        .\dReg_reg[6]_36 (u_ddr_cal_n_1632),
        .\dReg_reg[6]_37 (u_ddr_cal_n_1628),
        .\dReg_reg[6]_38 (u_ddr_cal_n_1624),
        .\dReg_reg[6]_39 (u_ddr_cal_n_1620),
        .\dReg_reg[6]_4 (u_ddr_cal_n_1400),
        .\dReg_reg[6]_40 (u_ddr_cal_n_1616),
        .\dReg_reg[6]_41 (u_ddr_cal_n_1612),
        .\dReg_reg[6]_42 (u_ddr_cal_n_1608),
        .\dReg_reg[6]_43 (u_ddr_cal_n_1604),
        .\dReg_reg[6]_44 (u_ddr_cal_n_1655),
        .\dReg_reg[6]_45 (u_ddr_cal_n_1686),
        .\dReg_reg[6]_46 (u_ddr_cal_n_1682),
        .\dReg_reg[6]_47 (u_ddr_cal_n_1678),
        .\dReg_reg[6]_48 (u_ddr_cal_n_1674),
        .\dReg_reg[6]_49 (u_ddr_cal_n_1670),
        .\dReg_reg[6]_5 (u_ddr_cal_n_1396),
        .\dReg_reg[6]_50 (u_ddr_cal_n_1666),
        .\dReg_reg[6]_51 (u_ddr_cal_n_1662),
        .\dReg_reg[6]_52 (u_ddr_cal_n_1658),
        .\dReg_reg[6]_53 (u_ddr_cal_n_1709),
        .\dReg_reg[6]_54 (u_ddr_cal_n_1740),
        .\dReg_reg[6]_55 (u_ddr_cal_n_1736),
        .\dReg_reg[6]_56 (u_ddr_cal_n_1732),
        .\dReg_reg[6]_57 (u_ddr_cal_n_1728),
        .\dReg_reg[6]_58 (u_ddr_cal_n_1724),
        .\dReg_reg[6]_59 (u_ddr_cal_n_1720),
        .\dReg_reg[6]_6 (u_ddr_cal_n_1392),
        .\dReg_reg[6]_60 (u_ddr_cal_n_1716),
        .\dReg_reg[6]_61 (u_ddr_cal_n_1712),
        .\dReg_reg[6]_62 (u_ddr_cal_n_1763),
        .\dReg_reg[6]_63 (u_ddr_cal_n_1794),
        .\dReg_reg[6]_64 (u_ddr_cal_n_1790),
        .\dReg_reg[6]_65 (u_ddr_cal_n_1786),
        .\dReg_reg[6]_66 (u_ddr_cal_n_1782),
        .\dReg_reg[6]_67 (u_ddr_cal_n_1778),
        .\dReg_reg[6]_68 (u_ddr_cal_n_1774),
        .\dReg_reg[6]_69 (u_ddr_cal_n_1770),
        .\dReg_reg[6]_7 (u_ddr_cal_n_1388),
        .\dReg_reg[6]_70 (u_ddr_cal_n_1766),
        .\dReg_reg[6]_8 (u_ddr_cal_n_1439),
        .\dReg_reg[6]_9 (u_ddr_cal_n_1470),
        .\dReg_reg[7] (u_ddr_cal_n_1383),
        .\dReg_reg[7]_0 (u_ddr_cal_n_1417),
        .\dReg_reg[7]_1 (u_ddr_cal_n_1413),
        .\dReg_reg[7]_10 (u_ddr_cal_n_1467),
        .\dReg_reg[7]_11 (u_ddr_cal_n_1463),
        .\dReg_reg[7]_12 (u_ddr_cal_n_1459),
        .\dReg_reg[7]_13 (u_ddr_cal_n_1455),
        .\dReg_reg[7]_14 (u_ddr_cal_n_1451),
        .\dReg_reg[7]_15 (u_ddr_cal_n_1447),
        .\dReg_reg[7]_16 (u_ddr_cal_n_1443),
        .\dReg_reg[7]_17 (u_ddr_cal_n_1491),
        .\dReg_reg[7]_18 (u_ddr_cal_n_1525),
        .\dReg_reg[7]_19 (u_ddr_cal_n_1521),
        .\dReg_reg[7]_2 (u_ddr_cal_n_1409),
        .\dReg_reg[7]_20 (u_ddr_cal_n_1517),
        .\dReg_reg[7]_21 (u_ddr_cal_n_1513),
        .\dReg_reg[7]_22 (u_ddr_cal_n_1509),
        .\dReg_reg[7]_23 (u_ddr_cal_n_1505),
        .\dReg_reg[7]_24 (u_ddr_cal_n_1501),
        .\dReg_reg[7]_25 (u_ddr_cal_n_1497),
        .\dReg_reg[7]_26 (u_ddr_cal_n_1545),
        .\dReg_reg[7]_27 (u_ddr_cal_n_1579),
        .\dReg_reg[7]_28 (u_ddr_cal_n_1575),
        .\dReg_reg[7]_29 (u_ddr_cal_n_1571),
        .\dReg_reg[7]_3 (u_ddr_cal_n_1405),
        .\dReg_reg[7]_30 (u_ddr_cal_n_1567),
        .\dReg_reg[7]_31 (u_ddr_cal_n_1563),
        .\dReg_reg[7]_32 (u_ddr_cal_n_1559),
        .\dReg_reg[7]_33 (u_ddr_cal_n_1555),
        .\dReg_reg[7]_34 (u_ddr_cal_n_1551),
        .\dReg_reg[7]_35 (u_ddr_cal_n_1599),
        .\dReg_reg[7]_36 (u_ddr_cal_n_1633),
        .\dReg_reg[7]_37 (u_ddr_cal_n_1629),
        .\dReg_reg[7]_38 (u_ddr_cal_n_1625),
        .\dReg_reg[7]_39 (u_ddr_cal_n_1621),
        .\dReg_reg[7]_4 (u_ddr_cal_n_1401),
        .\dReg_reg[7]_40 (u_ddr_cal_n_1617),
        .\dReg_reg[7]_41 (u_ddr_cal_n_1613),
        .\dReg_reg[7]_42 (u_ddr_cal_n_1609),
        .\dReg_reg[7]_43 (u_ddr_cal_n_1605),
        .\dReg_reg[7]_44 (u_ddr_cal_n_1653),
        .\dReg_reg[7]_45 (u_ddr_cal_n_1687),
        .\dReg_reg[7]_46 (u_ddr_cal_n_1683),
        .\dReg_reg[7]_47 (u_ddr_cal_n_1679),
        .\dReg_reg[7]_48 (u_ddr_cal_n_1675),
        .\dReg_reg[7]_49 (u_ddr_cal_n_1671),
        .\dReg_reg[7]_5 (u_ddr_cal_n_1397),
        .\dReg_reg[7]_50 (u_ddr_cal_n_1667),
        .\dReg_reg[7]_51 (u_ddr_cal_n_1663),
        .\dReg_reg[7]_52 (u_ddr_cal_n_1659),
        .\dReg_reg[7]_53 (u_ddr_cal_n_1707),
        .\dReg_reg[7]_54 (u_ddr_cal_n_1741),
        .\dReg_reg[7]_55 (u_ddr_cal_n_1737),
        .\dReg_reg[7]_56 (u_ddr_cal_n_1733),
        .\dReg_reg[7]_57 (u_ddr_cal_n_1729),
        .\dReg_reg[7]_58 (u_ddr_cal_n_1725),
        .\dReg_reg[7]_59 (u_ddr_cal_n_1721),
        .\dReg_reg[7]_6 (u_ddr_cal_n_1393),
        .\dReg_reg[7]_60 (u_ddr_cal_n_1717),
        .\dReg_reg[7]_61 (u_ddr_cal_n_1713),
        .\dReg_reg[7]_62 (u_ddr_cal_n_1761),
        .\dReg_reg[7]_63 (u_ddr_cal_n_1795),
        .\dReg_reg[7]_64 (u_ddr_cal_n_1791),
        .\dReg_reg[7]_65 (u_ddr_cal_n_1787),
        .\dReg_reg[7]_66 (u_ddr_cal_n_1783),
        .\dReg_reg[7]_67 (u_ddr_cal_n_1779),
        .\dReg_reg[7]_68 (u_ddr_cal_n_1775),
        .\dReg_reg[7]_69 (u_ddr_cal_n_1771),
        .\dReg_reg[7]_7 (u_ddr_cal_n_1389),
        .\dReg_reg[7]_70 (u_ddr_cal_n_1767),
        .\dReg_reg[7]_8 (u_ddr_cal_n_1437),
        .\dReg_reg[7]_9 (u_ddr_cal_n_1471),
        .\dReg_reg[9] (\u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/dReg0_out ),
        .\dReg_reg[9]_0 (\u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/dReg0_out ),
        .\dReg_reg[9]_1 (\u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/dReg0_out ),
        .\dReg_reg[9]_10 ({u_ddr_cal_n_1402,u_ddr_cal_n_1403}),
        .\dReg_reg[9]_11 ({u_ddr_cal_n_1398,u_ddr_cal_n_1399}),
        .\dReg_reg[9]_12 ({u_ddr_cal_n_1394,u_ddr_cal_n_1395}),
        .\dReg_reg[9]_13 ({u_ddr_cal_n_1390,u_ddr_cal_n_1391}),
        .\dReg_reg[9]_14 ({u_ddr_cal_n_1386,u_ddr_cal_n_1387}),
        .\dReg_reg[9]_15 ({u_ddr_cal_n_1468,u_ddr_cal_n_1469}),
        .\dReg_reg[9]_16 ({u_ddr_cal_n_1464,u_ddr_cal_n_1465}),
        .\dReg_reg[9]_17 ({u_ddr_cal_n_1460,u_ddr_cal_n_1461}),
        .\dReg_reg[9]_18 ({u_ddr_cal_n_1456,u_ddr_cal_n_1457}),
        .\dReg_reg[9]_19 ({u_ddr_cal_n_1452,u_ddr_cal_n_1453}),
        .\dReg_reg[9]_2 (\u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/dReg0_out ),
        .\dReg_reg[9]_20 ({u_ddr_cal_n_1448,u_ddr_cal_n_1449}),
        .\dReg_reg[9]_21 ({u_ddr_cal_n_1444,u_ddr_cal_n_1445}),
        .\dReg_reg[9]_22 ({u_ddr_cal_n_1440,u_ddr_cal_n_1441}),
        .\dReg_reg[9]_23 ({u_ddr_cal_n_1522,u_ddr_cal_n_1523}),
        .\dReg_reg[9]_24 ({u_ddr_cal_n_1518,u_ddr_cal_n_1519}),
        .\dReg_reg[9]_25 ({u_ddr_cal_n_1514,u_ddr_cal_n_1515}),
        .\dReg_reg[9]_26 ({u_ddr_cal_n_1510,u_ddr_cal_n_1511}),
        .\dReg_reg[9]_27 ({u_ddr_cal_n_1506,u_ddr_cal_n_1507}),
        .\dReg_reg[9]_28 ({u_ddr_cal_n_1502,u_ddr_cal_n_1503}),
        .\dReg_reg[9]_29 ({u_ddr_cal_n_1498,u_ddr_cal_n_1499}),
        .\dReg_reg[9]_3 (\u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/dReg0_out ),
        .\dReg_reg[9]_30 ({u_ddr_cal_n_1494,u_ddr_cal_n_1495}),
        .\dReg_reg[9]_31 ({u_ddr_cal_n_1576,u_ddr_cal_n_1577}),
        .\dReg_reg[9]_32 ({u_ddr_cal_n_1572,u_ddr_cal_n_1573}),
        .\dReg_reg[9]_33 ({u_ddr_cal_n_1568,u_ddr_cal_n_1569}),
        .\dReg_reg[9]_34 ({u_ddr_cal_n_1564,u_ddr_cal_n_1565}),
        .\dReg_reg[9]_35 ({u_ddr_cal_n_1560,u_ddr_cal_n_1561}),
        .\dReg_reg[9]_36 ({u_ddr_cal_n_1556,u_ddr_cal_n_1557}),
        .\dReg_reg[9]_37 ({u_ddr_cal_n_1552,u_ddr_cal_n_1553}),
        .\dReg_reg[9]_38 ({u_ddr_cal_n_1548,u_ddr_cal_n_1549}),
        .\dReg_reg[9]_39 ({u_ddr_cal_n_1630,u_ddr_cal_n_1631}),
        .\dReg_reg[9]_4 (\u_ddr_mc_write/genByte[5].u_ddr_mc_wr_byte/dReg0_out ),
        .\dReg_reg[9]_40 ({u_ddr_cal_n_1626,u_ddr_cal_n_1627}),
        .\dReg_reg[9]_41 ({u_ddr_cal_n_1622,u_ddr_cal_n_1623}),
        .\dReg_reg[9]_42 ({u_ddr_cal_n_1618,u_ddr_cal_n_1619}),
        .\dReg_reg[9]_43 ({u_ddr_cal_n_1614,u_ddr_cal_n_1615}),
        .\dReg_reg[9]_44 ({u_ddr_cal_n_1610,u_ddr_cal_n_1611}),
        .\dReg_reg[9]_45 ({u_ddr_cal_n_1606,u_ddr_cal_n_1607}),
        .\dReg_reg[9]_46 ({u_ddr_cal_n_1602,u_ddr_cal_n_1603}),
        .\dReg_reg[9]_47 ({u_ddr_cal_n_1684,u_ddr_cal_n_1685}),
        .\dReg_reg[9]_48 ({u_ddr_cal_n_1680,u_ddr_cal_n_1681}),
        .\dReg_reg[9]_49 ({u_ddr_cal_n_1676,u_ddr_cal_n_1677}),
        .\dReg_reg[9]_5 (\u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/dReg0_out ),
        .\dReg_reg[9]_50 ({u_ddr_cal_n_1672,u_ddr_cal_n_1673}),
        .\dReg_reg[9]_51 ({u_ddr_cal_n_1668,u_ddr_cal_n_1669}),
        .\dReg_reg[9]_52 ({u_ddr_cal_n_1664,u_ddr_cal_n_1665}),
        .\dReg_reg[9]_53 ({u_ddr_cal_n_1660,u_ddr_cal_n_1661}),
        .\dReg_reg[9]_54 ({u_ddr_cal_n_1656,u_ddr_cal_n_1657}),
        .\dReg_reg[9]_55 ({u_ddr_cal_n_1738,u_ddr_cal_n_1739}),
        .\dReg_reg[9]_56 ({u_ddr_cal_n_1734,u_ddr_cal_n_1735}),
        .\dReg_reg[9]_57 ({u_ddr_cal_n_1730,u_ddr_cal_n_1731}),
        .\dReg_reg[9]_58 ({u_ddr_cal_n_1726,u_ddr_cal_n_1727}),
        .\dReg_reg[9]_59 ({u_ddr_cal_n_1722,u_ddr_cal_n_1723}),
        .\dReg_reg[9]_6 (\u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/dReg0_out ),
        .\dReg_reg[9]_60 ({u_ddr_cal_n_1718,u_ddr_cal_n_1719}),
        .\dReg_reg[9]_61 ({u_ddr_cal_n_1714,u_ddr_cal_n_1715}),
        .\dReg_reg[9]_62 ({u_ddr_cal_n_1710,u_ddr_cal_n_1711}),
        .\dReg_reg[9]_63 ({u_ddr_cal_n_1792,u_ddr_cal_n_1793}),
        .\dReg_reg[9]_64 ({u_ddr_cal_n_1788,u_ddr_cal_n_1789}),
        .\dReg_reg[9]_65 ({u_ddr_cal_n_1784,u_ddr_cal_n_1785}),
        .\dReg_reg[9]_66 ({u_ddr_cal_n_1780,u_ddr_cal_n_1781}),
        .\dReg_reg[9]_67 ({u_ddr_cal_n_1776,u_ddr_cal_n_1777}),
        .\dReg_reg[9]_68 ({u_ddr_cal_n_1772,u_ddr_cal_n_1773}),
        .\dReg_reg[9]_69 ({u_ddr_cal_n_1768,u_ddr_cal_n_1769}),
        .\dReg_reg[9]_7 ({u_ddr_cal_n_1414,u_ddr_cal_n_1415}),
        .\dReg_reg[9]_70 ({u_ddr_cal_n_1764,u_ddr_cal_n_1765}),
        .\dReg_reg[9]_8 ({u_ddr_cal_n_1410,u_ddr_cal_n_1411}),
        .\dReg_reg[9]_9 ({u_ddr_cal_n_1406,u_ddr_cal_n_1407}),
        .in0({u_ddr_cal_n_1374,u_ddr_cal_n_1375}),
        .match4_10_return(match4_10_return),
        .match4_110_return(match4_110_return),
        .match4_111_return(match4_111_return),
        .match4_112_return(match4_112_return),
        .match4_113_return(match4_113_return),
        .match4_114_return(match4_114_return),
        .match4_115_return(match4_115_return),
        .match4_116_return(match4_116_return),
        .match4_117_return(match4_117_return),
        .match4_118_return(match4_118_return),
        .match4_119_return(match4_119_return),
        .match4_11_return(match4_11_return),
        .match4_120_return(match4_120_return),
        .match4_121_return(match4_121_return),
        .match4_122_return(match4_122_return),
        .match4_123_return(match4_123_return),
        .match4_124_return(match4_124_return),
        .match4_125_return(match4_125_return),
        .match4_126_return(match4_126_return),
        .match4_127_return(match4_127_return),
        .match4_128_return(match4_128_return),
        .match4_129_return(match4_129_return),
        .match4_12_return(match4_12_return),
        .match4_130_return(match4_130_return),
        .match4_131_return(match4_131_return),
        .match4_132_return(match4_132_return),
        .match4_133_return(match4_133_return),
        .match4_134_return(match4_134_return),
        .match4_135_return(match4_135_return),
        .match4_136_return(match4_136_return),
        .match4_137_return(match4_137_return),
        .match4_138_return(match4_138_return),
        .match4_139_return(match4_139_return),
        .match4_13_return(match4_13_return),
        .match4_140_return(match4_140_return),
        .match4_141_return(match4_141_return),
        .match4_142_return(match4_142_return),
        .match4_143_return(match4_143_return),
        .match4_144_return(match4_144_return),
        .match4_145_return(match4_145_return),
        .match4_146_return(match4_146_return),
        .match4_147_return(match4_147_return),
        .match4_148_return(match4_148_return),
        .match4_149_return(match4_149_return),
        .match4_14_return(match4_14_return),
        .match4_150_return(match4_150_return),
        .match4_151_return(match4_151_return),
        .match4_152_return(match4_152_return),
        .match4_153_return(match4_153_return),
        .match4_154_return(match4_154_return),
        .match4_155_return(match4_155_return),
        .match4_156_return(match4_156_return),
        .match4_157_return(match4_157_return),
        .match4_158_return(match4_158_return),
        .match4_159_return(match4_159_return),
        .match4_15_return(match4_15_return),
        .match4_160_return(match4_160_return),
        .match4_161_return(match4_161_return),
        .match4_162_return(match4_162_return),
        .match4_163_return(match4_163_return),
        .match4_164_return(match4_164_return),
        .match4_165_return(match4_165_return),
        .match4_166_return(match4_166_return),
        .match4_167_return(match4_167_return),
        .match4_168_return(match4_168_return),
        .match4_169_return(match4_169_return),
        .match4_16_return(match4_16_return),
        .match4_170_return(match4_170_return),
        .match4_171_return(match4_171_return),
        .match4_172_return(match4_172_return),
        .match4_173_return(match4_173_return),
        .match4_174_return(match4_174_return),
        .match4_175_return(match4_175_return),
        .match4_176_return(match4_176_return),
        .match4_177_return(match4_177_return),
        .match4_178_return(match4_178_return),
        .match4_179_return(match4_179_return),
        .match4_17_return(match4_17_return),
        .match4_180_return(match4_180_return),
        .match4_181_return(match4_181_return),
        .match4_182_return(match4_182_return),
        .match4_183_return(match4_183_return),
        .match4_184_return(match4_184_return),
        .match4_185_return(match4_185_return),
        .match4_186_return(match4_186_return),
        .match4_187_return(match4_187_return),
        .match4_188_return(match4_188_return),
        .match4_18_return(match4_18_return),
        .match4_19_return(match4_19_return),
        .match4_1_return(match4_1_return),
        .match6_10_return(match6_10_return),
        .match6_110_return(match6_110_return),
        .match6_111_return(match6_111_return),
        .match6_112_return(match6_112_return),
        .match6_113_return(match6_113_return),
        .match6_114_return(match6_114_return),
        .match6_115_return(match6_115_return),
        .match6_116_return(match6_116_return),
        .match6_117_return(match6_117_return),
        .match6_118_return(match6_118_return),
        .match6_119_return(match6_119_return),
        .match6_11_return(match6_11_return),
        .match6_120_return(match6_120_return),
        .match6_121_return(match6_121_return),
        .match6_122_return(match6_122_return),
        .match6_123_return(match6_123_return),
        .match6_124_return(match6_124_return),
        .match6_125_return(match6_125_return),
        .match6_126_return(match6_126_return),
        .match6_127_return(match6_127_return),
        .match6_128_return(match6_128_return),
        .match6_129_return(match6_129_return),
        .match6_12_return(match6_12_return),
        .match6_130_return(match6_130_return),
        .match6_131_return(match6_131_return),
        .match6_132_return(match6_132_return),
        .match6_133_return(match6_133_return),
        .match6_134_return(match6_134_return),
        .match6_135_return(match6_135_return),
        .match6_136_return(match6_136_return),
        .match6_137_return(match6_137_return),
        .match6_138_return(match6_138_return),
        .match6_139_return(match6_139_return),
        .match6_13_return(match6_13_return),
        .match6_140_return(match6_140_return),
        .match6_141_return(match6_141_return),
        .match6_142_return(match6_142_return),
        .match6_143_return(match6_143_return),
        .match6_144_return(match6_144_return),
        .match6_145_return(match6_145_return),
        .match6_146_return(match6_146_return),
        .match6_147_return(match6_147_return),
        .match6_148_return(match6_148_return),
        .match6_149_return(match6_149_return),
        .match6_14_return(match6_14_return),
        .match6_150_return(match6_150_return),
        .match6_151_return(match6_151_return),
        .match6_152_return(match6_152_return),
        .match6_153_return(match6_153_return),
        .match6_154_return(match6_154_return),
        .match6_155_return(match6_155_return),
        .match6_156_return(match6_156_return),
        .match6_157_return(match6_157_return),
        .match6_158_return(match6_158_return),
        .match6_159_return(match6_159_return),
        .match6_15_return(match6_15_return),
        .match6_160_return(match6_160_return),
        .match6_161_return(match6_161_return),
        .match6_162_return(match6_162_return),
        .match6_163_return(match6_163_return),
        .match6_164_return(match6_164_return),
        .match6_165_return(match6_165_return),
        .match6_166_return(match6_166_return),
        .match6_167_return(match6_167_return),
        .match6_168_return(match6_168_return),
        .match6_169_return(match6_169_return),
        .match6_16_return(match6_16_return),
        .match6_170_return(match6_170_return),
        .match6_171_return(match6_171_return),
        .match6_172_return(match6_172_return),
        .match6_173_return(match6_173_return),
        .match6_174_return(match6_174_return),
        .match6_175_return(match6_175_return),
        .match6_176_return(match6_176_return),
        .match6_177_return(match6_177_return),
        .match6_178_return(match6_178_return),
        .match6_179_return(match6_179_return),
        .match6_17_return(match6_17_return),
        .match6_180_return(match6_180_return),
        .match6_181_return(match6_181_return),
        .match6_182_return(match6_182_return),
        .match6_183_return(match6_183_return),
        .match6_184_return(match6_184_return),
        .match6_185_return(match6_185_return),
        .match6_186_return(match6_186_return),
        .match6_187_return(match6_187_return),
        .match6_188_return(match6_188_return),
        .match6_18_return(match6_18_return),
        .match6_19_return(match6_19_return),
        .match6_1_return(match6_1_return),
        .mcCasSlot2(mcCasSlot2),
        .mcRdCAS(mcRdCAS),
        .mcWrCAS(mcWrCAS),
        .mc_clb2phy_fifo_rden_nxt(mc_clb2phy_fifo_rden_nxt),
        .mcalCasSlot(mcalCasSlot),
        .mcalRank(mcalRank),
        .mcalRdCAS(mcalRdCAS),
        .\not_strict_mode.app_rd_data_end_reg (\not_strict_mode.app_rd_data_end_reg ),
        .\not_strict_mode.bypass_cpy2 (\not_strict_mode.bypass_cpy2 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] (\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] (\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] (\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] (\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] (\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] (\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] (\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] (\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] (\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] (\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] (\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] (\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] (\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] (\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] (\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] (\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] (\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] (\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] (\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] (\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] (\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] (\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] (\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] (\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] (\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] (\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] (\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] (\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] (\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] (\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] (\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] (\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] (\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] (\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] (\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] (\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] (\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] (\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] (\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] (\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] (\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] (\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] (\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] (\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] (\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] (\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] (\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] (\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] (\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] (\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] (\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] (\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] (\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] (\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] (\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] (\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] (\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] (\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] (\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] (\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] (\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] (\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] (\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] (\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] (\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] (\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] (\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] (\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] (\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] (\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] (\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] (\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] (\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] (\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] (\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] (\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] (\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] (\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] (\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] (\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] (\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] (\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] (\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] (\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] (\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] (\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] (\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] (\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] (\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] (\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] (\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] (\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] (\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] (\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] (\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] (\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] (\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] (\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] (\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] (\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] (\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] (\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] (\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] (\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] (\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] (\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] (\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] (\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] (\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] (\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] (\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] (\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] (\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] (\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] (\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] (\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] (\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] (\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] (\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] (\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] (\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] (\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] (\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] (\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] (\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] (\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] (\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] (\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] (\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] (\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] (\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] (\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] (\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] (\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] (\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] (\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] (\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] (\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] (\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] (\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] (\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] (\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] (\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] (\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] (\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] (\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] (\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] (\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] (\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] (\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] (\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] (\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] (\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] (\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] (\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] (\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] (\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] (\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] (\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] (\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] (\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] (\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] (\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] (\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] (\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] (\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] (\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] (\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] (\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] (\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] (\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] (\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] (\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] (\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] (\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] (\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] (\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] (\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] (\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] (\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] (\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] (\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] (\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] (\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] (\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] (\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] (\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] (\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] (\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] (\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] (\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] (\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] (\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] (\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] (\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] (\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] (\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] (\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] (\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] (\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] (\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] (\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] (\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] (\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] (\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] (\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] (\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] (\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] (\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] (\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] (\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] (\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] (\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] (\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] (\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] (\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] (\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] (\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] (\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] (\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] (\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] (\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] (\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] (\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] (\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] (\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] (\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] (\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] (\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] (\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] (\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] (\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] (\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] (\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] (\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] (\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] (\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] (\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] (\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] (\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] (\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] (\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] (\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] (\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] (\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] (\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] (\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 (\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] (\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] (in0),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] (\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] (\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] (\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] (\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] (\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] (\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ),
        .\not_strict_mode.status_ram_0.RAM32M0 (\not_strict_mode.status_ram_0.RAM32M0 ),
        .\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] (\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] ),
        .\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] (\not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] ),
        .\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] (\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] ),
        .\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] (\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] ),
        .\oe_0_mux_cal_reg[0] (oe_0_mux_cal),
        .\oe_0_mux_cal_reg[0]_0 (u_ddr_cal_n_802),
        .\oe_low_reg[3] (\oe_low_reg[3] ),
        .\oe_low_reg[5] (calDone),
        .\oe_upp_reg[3] (\oe_upp_reg[3] ),
        .out(u_ddr_mc_pi_n_3),
        .per_rd_done(per_rd_done),
        .phy_rden_and(phy_rden_and),
        .phy_rden_or(phy_rden_or),
        .pointer_we(pointer_we),
        .pop_read_lat_fifo_reg(\u_ddr_cal_addr_decode/dqin_valid_shift_nxt ),
        .\rams[1].RAM32M0 (\rams[1].RAM32M0 ),
        .\rdDataAddr_reg[3]_rep (ADDRD[0]),
        .\rdDataAddr_reg[3]_rep__0 (\rdDataAddr_reg[4]_rep__0 [0]),
        .\rdDataAddr_reg[3]_rep__1 (\rdDataAddr_reg[4]_rep__1 [0]),
        .\rdDataAddr_reg[4] (\rdDataAddr_reg[4]_0 ),
        .\rdDataAddr_reg[4]_0 (\rdDataAddr_reg[4]_1 ),
        .\rdDataAddr_reg[4]_1 (\rdDataAddr_reg[4]_2 ),
        .\rdDataAddr_reg[4]_rep (ADDRD[1]),
        .\rdDataAddr_reg[4]_rep__0 (\rdDataAddr_reg[4]_rep__0 [1]),
        .\rdDataAddr_reg[4]_rep__1 (\rdDataAddr_reg[4]_rep__1 [1]),
        .rdDataEn_pi(rdDataEn_pi),
        .\rdData_reg[101] (\rdData_reg[101]_0 ),
        .\rdData_reg[107] (\rdData_reg[107]_0 ),
        .\rdData_reg[113] (\rdData_reg[113]_0 ),
        .\rdData_reg[119] (\rdData_reg[119]_0 ),
        .\rdData_reg[11] (\rdData_reg[11]_0 ),
        .\rdData_reg[125] (\rdData_reg[125]_0 ),
        .\rdData_reg[131] (\rdData_reg[131]_0 ),
        .\rdData_reg[137] (\rdData_reg[137]_0 ),
        .\rdData_reg[143] (\rdData_reg[143]_0 ),
        .\rdData_reg[149] (\rdData_reg[149]_0 ),
        .\rdData_reg[155] (\rdData_reg[155]_0 ),
        .\rdData_reg[161] (\rdData_reg[161]_0 ),
        .\rdData_reg[167] (\rdData_reg[167]_0 ),
        .\rdData_reg[173] (\rdData_reg[173]_0 ),
        .\rdData_reg[179] (\rdData_reg[179]_0 ),
        .\rdData_reg[17] (\rdData_reg[17]_0 ),
        .\rdData_reg[185] (\rdData_reg[185]_0 ),
        .\rdData_reg[191] (\rdData_reg[191]_0 ),
        .\rdData_reg[197] (\rdData_reg[197]_0 ),
        .\rdData_reg[203] (\rdData_reg[203]_0 ),
        .\rdData_reg[209] (\rdData_reg[209]_0 ),
        .\rdData_reg[215] (\rdData_reg[215]_0 ),
        .\rdData_reg[221] (\rdData_reg[221]_0 ),
        .\rdData_reg[227] (\rdData_reg[227]_0 ),
        .\rdData_reg[233] (\rdData_reg[233]_0 ),
        .\rdData_reg[239] (\rdData_reg[239]_0 ),
        .\rdData_reg[23] (\rdData_reg[23]_0 ),
        .\rdData_reg[245] (\rdData_reg[245]_0 ),
        .\rdData_reg[251] (\rdData_reg[251]_0 ),
        .\rdData_reg[257] (\rdData_reg[257]_0 ),
        .\rdData_reg[263] (\rdData_reg[263]_0 ),
        .\rdData_reg[269] (\rdData_reg[269]_0 ),
        .\rdData_reg[275] (\rdData_reg[275]_0 ),
        .\rdData_reg[281] (\rdData_reg[281]_0 ),
        .\rdData_reg[287] (\rdData_reg[287]_0 ),
        .\rdData_reg[293] (\rdData_reg[293]_0 ),
        .\rdData_reg[299] (\rdData_reg[299]_0 ),
        .\rdData_reg[29] (\rdData_reg[29]_0 ),
        .\rdData_reg[305] (\rdData_reg[305]_0 ),
        .\rdData_reg[311] (\rdData_reg[311]_0 ),
        .\rdData_reg[317] (\rdData_reg[317]_0 ),
        .\rdData_reg[323] (\rdData_reg[323]_0 ),
        .\rdData_reg[329] (\rdData_reg[329]_0 ),
        .\rdData_reg[335] (\rdData_reg[335]_0 ),
        .\rdData_reg[341] (\rdData_reg[341]_0 ),
        .\rdData_reg[347] (\rdData_reg[347]_0 ),
        .\rdData_reg[353] (\rdData_reg[353]_0 ),
        .\rdData_reg[359] (\rdData_reg[359]_0 ),
        .\rdData_reg[35] (\rdData_reg[35]_0 ),
        .\rdData_reg[365] (\rdData_reg[365]_0 ),
        .\rdData_reg[371] (\rdData_reg[371]_0 ),
        .\rdData_reg[377] (\rdData_reg[377]_0 ),
        .\rdData_reg[383] (\rdData_reg[383]_0 ),
        .\rdData_reg[389] (\rdData_reg[389]_0 ),
        .\rdData_reg[395] (\rdData_reg[395]_0 ),
        .\rdData_reg[401] (\rdData_reg[401]_0 ),
        .\rdData_reg[407] (\rdData_reg[407]_0 ),
        .\rdData_reg[413] (\rdData_reg[413]_0 ),
        .\rdData_reg[419] (\rdData_reg[419]_0 ),
        .\rdData_reg[41] (\rdData_reg[41]_0 ),
        .\rdData_reg[425] (\rdData_reg[425]_0 ),
        .\rdData_reg[431] (\rdData_reg[431]_0 ),
        .\rdData_reg[437] (\rdData_reg[437]_0 ),
        .\rdData_reg[443] (\rdData_reg[443]_0 ),
        .\rdData_reg[449] (\rdData_reg[449]_0 ),
        .\rdData_reg[455] (\rdData_reg[455]_0 ),
        .\rdData_reg[461] (\rdData_reg[461]_0 ),
        .\rdData_reg[467] (\rdData_reg[467]_0 ),
        .\rdData_reg[473] (\rdData_reg[473]_0 ),
        .\rdData_reg[479] (\rdData_reg[479]_0 ),
        .\rdData_reg[47] (\rdData_reg[47]_0 ),
        .\rdData_reg[485] (\rdData_reg[485]_0 ),
        .\rdData_reg[491] (\rdData_reg[491]_0 ),
        .\rdData_reg[497] (\rdData_reg[497]_0 ),
        .\rdData_reg[503] (\rdData_reg[503]_0 ),
        .\rdData_reg[509] (\rdData_reg[509]_0 ),
        .\rdData_reg[511] (\rdData_reg[511]_0 ),
        .\rdData_reg[53] (\rdData_reg[53]_0 ),
        .\rdData_reg[59] (\rdData_reg[59]_0 ),
        .\rdData_reg[5] (\rdData_reg[5]_0 ),
        .\rdData_reg[65] (\rdData_reg[65]_0 ),
        .\rdData_reg[71] (\rdData_reg[71]_0 ),
        .\rdData_reg[77] (\rdData_reg[77]_0 ),
        .\rdData_reg[83] (\rdData_reg[83]_0 ),
        .\rdData_reg[89] (\rdData_reg[89]_0 ),
        .\rdData_reg[95] (\rdData_reg[95]_0 ),
        .\rdEn_reg[12] (u_ddr_cal_n_793),
        .\rdEn_reg[12]_0 (u_ddr_cal_n_797),
        .\rdEn_reg[12]_1 (u_ddr_cal_n_795),
        .\rdEn_reg[12]_2 (u_ddr_cal_n_796),
        .\rdEn_reg[12]_3 (u_ddr_cal_n_794),
        .\rdEn_reg[13] (u_ddr_cal_n_799),
        .\rdEn_reg[14] (u_ddr_cal_n_800),
        .\rdEn_reg[14]_0 (u_ddr_cal_n_798),
        .\rdEn_reg[29] ({u_ddr_cal_n_1376,u_ddr_cal_n_1377}),
        .\rdEn_reg[29]_0 ({u_ddr_cal_n_1378,u_ddr_cal_n_1379}),
        .\rdEn_reg[29]_1 ({u_ddr_cal_n_1812,u_ddr_cal_n_1813}),
        .\rdEn_reg[29]_10 ({u_ddr_cal_n_1830,u_ddr_cal_n_1831}),
        .\rdEn_reg[29]_11 ({u_ddr_cal_n_1832,u_ddr_cal_n_1833}),
        .\rdEn_reg[29]_12 ({u_ddr_cal_n_1834,u_ddr_cal_n_1835}),
        .\rdEn_reg[29]_13 ({u_ddr_cal_n_1836,u_ddr_cal_n_1837}),
        .\rdEn_reg[29]_2 ({u_ddr_cal_n_1814,u_ddr_cal_n_1815}),
        .\rdEn_reg[29]_3 ({u_ddr_cal_n_1816,u_ddr_cal_n_1817}),
        .\rdEn_reg[29]_4 ({u_ddr_cal_n_1818,u_ddr_cal_n_1819}),
        .\rdEn_reg[29]_5 ({u_ddr_cal_n_1820,u_ddr_cal_n_1821}),
        .\rdEn_reg[29]_6 ({u_ddr_cal_n_1822,u_ddr_cal_n_1823}),
        .\rdEn_reg[29]_7 ({u_ddr_cal_n_1824,u_ddr_cal_n_1825}),
        .\rdEn_reg[29]_8 ({u_ddr_cal_n_1826,u_ddr_cal_n_1827}),
        .\rdEn_reg[29]_9 ({u_ddr_cal_n_1828,u_ddr_cal_n_1829}),
        .\read_lat_fifo_in_reg[6] (\read_lat_fifo_in_reg[6] ),
        .read_lat_shift_cal_dq_valid_nxt(\u_ddr_mc_read/read_lat_shift_cal_dq_valid_nxt ),
        .\read_lat_shift_reg[31] ({u_ddr_mc_pi_n_1526,\u_ddr_mc_read/read_lat_shift_nxt }),
        .rs2mask0({\rdEn[6].u_ddr_mc_rd_en_upp/rs2mask0 [12:10],\rdEn[6].u_ddr_mc_rd_en_upp/rs2mask0 [3:2]}),
        .rs2mask0_10({\rdEn[0].u_ddr_mc_rd_en_upp/rs2mask0 [12:10],\rdEn[0].u_ddr_mc_rd_en_upp/rs2mask0 [3:2]}),
        .rs2mask0_12({\rdEn[5].u_ddr_mc_rd_en_upp/rs2mask0 [12:10],\rdEn[5].u_ddr_mc_rd_en_upp/rs2mask0 [3:2]}),
        .rs2mask0_14({\rdEn[5].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[5].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_16({\rdEn[4].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[4].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_18({\rdEn[6].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[6].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_2({\rdEn[3].u_ddr_mc_rd_en_upp/rs2mask0 [12:10],\rdEn[3].u_ddr_mc_rd_en_upp/rs2mask0 [3:2]}),
        .rs2mask0_20({\rdEn[3].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[3].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_22({\rdEn[2].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[2].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_24({\rdEn[1].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[1].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_26({\rdEn[0].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[0].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .rs2mask0_4({\rdEn[2].u_ddr_mc_rd_en_upp/rs2mask0 [12:10],\rdEn[2].u_ddr_mc_rd_en_upp/rs2mask0 [3:2]}),
        .rs2mask0_6({\rdEn[4].u_ddr_mc_rd_en_upp/rs2mask0 [12:10],\rdEn[4].u_ddr_mc_rd_en_upp/rs2mask0 [3:2]}),
        .rs2mask0_8({\rdEn[7].u_ddr_mc_rd_en_low/rs2mask0 [12:10],\rdEn[7].u_ddr_mc_rd_en_low/rs2mask0 [3:2]}),
        .\rsMask_reg[0][11] (u_ddr_cal_n_892),
        .\rsMask_reg[0][11]_0 (u_ddr_cal_n_904),
        .\rsMask_reg[0][11]_1 (u_ddr_cal_n_810),
        .\rsMask_reg[0][11]_10 (u_ddr_cal_n_996),
        .\rsMask_reg[0][11]_11 (u_ddr_cal_n_1020),
        .\rsMask_reg[0][11]_12 (u_ddr_cal_n_1032),
        .\rsMask_reg[0][11]_13 (u_ddr_cal_n_1044),
        .\rsMask_reg[0][11]_14 (u_ddr_cal_n_1056),
        .\rsMask_reg[0][11]_2 (u_ddr_cal_n_840),
        .\rsMask_reg[0][11]_3 (u_ddr_cal_n_852),
        .\rsMask_reg[0][11]_4 (u_ddr_cal_n_864),
        .\rsMask_reg[0][11]_5 (u_ddr_cal_n_924),
        .\rsMask_reg[0][11]_6 (u_ddr_cal_n_936),
        .\rsMask_reg[0][11]_7 (u_ddr_cal_n_948),
        .\rsMask_reg[0][11]_8 (u_ddr_cal_n_972),
        .\rsMask_reg[0][11]_9 (u_ddr_cal_n_984),
        .\rsMask_reg[0][9] ({\rdEn[1].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[1].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_0 ({\rdEn[7].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[7].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_1 ({\rdEn[6].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[6].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_10 ({\rdEn[6].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[6].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_11 ({\rdEn[3].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[3].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_12 ({\rdEn[2].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[2].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_13 ({\rdEn[1].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[1].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_14 ({\rdEn[0].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[0].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_2 ({\rdEn[3].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[3].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_3 ({\rdEn[2].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[2].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_4 ({\rdEn[4].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[4].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_5 ({\rdEn[7].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[7].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_6 ({\rdEn[0].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[0].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_7 ({\rdEn[5].u_ddr_mc_rd_en_upp/rs2mask [9],\rdEn[5].u_ddr_mc_rd_en_upp/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_8 ({\rdEn[5].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[5].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\rsMask_reg[0][9]_9 ({\rdEn[4].u_ddr_mc_rd_en_low/rs2mask [9],\rdEn[4].u_ddr_mc_rd_en_low/rs2mask [3:2]}),
        .\rsMask_reg[1][11] ({uppCL0[45:43],uppCL0[9:7]}),
        .\rsMask_reg[1][12] ({\rdEn[1].u_ddr_mc_rd_en_upp/rs2mask0__0 [12],\rdEn[1].u_ddr_mc_rd_en_upp/rs2mask0__0 [10],\rdEn[1].u_ddr_mc_rd_en_upp/rs2mask0__0 [3:2]}),
        .\rsMask_reg[1][12]_0 ({\rdEn[7].u_ddr_mc_rd_en_upp/rs2mask0__0 [12],\rdEn[7].u_ddr_mc_rd_en_upp/rs2mask0__0 [10],\rdEn[7].u_ddr_mc_rd_en_upp/rs2mask0__0 [3:2]}),
        .\rsMask_reg[1][15] (u_ddr_cal_n_920),
        .\rsMask_reg[1][15]_0 (u_ddr_cal_n_916),
        .\rsMask_reg[1][15]_1 (u_ddr_cal_n_878),
        .\rsMask_reg[1][15]_10 (u_ddr_cal_n_1010),
        .\rsMask_reg[1][15]_11 (u_ddr_cal_n_1070),
        .\rsMask_reg[1][15]_12 (u_ddr_cal_n_1074),
        .\rsMask_reg[1][15]_13 (u_ddr_cal_n_1078),
        .\rsMask_reg[1][15]_14 (u_ddr_cal_n_1082),
        .\rsMask_reg[1][15]_2 (u_ddr_cal_n_886),
        .\rsMask_reg[1][15]_3 (u_ddr_cal_n_890),
        .\rsMask_reg[1][15]_4 (u_ddr_cal_n_882),
        .\rsMask_reg[1][15]_5 (u_ddr_cal_n_962),
        .\rsMask_reg[1][15]_6 (u_ddr_cal_n_970),
        .\rsMask_reg[1][15]_7 (u_ddr_cal_n_966),
        .\rsMask_reg[1][15]_8 (u_ddr_cal_n_1014),
        .\rsMask_reg[1][15]_9 (u_ddr_cal_n_1018),
        .\rsMask_reg[1][16] (u_ddr_cal_n_1839),
        .\rsMask_reg[1][16]_0 (u_ddr_cal_n_1883),
        .\rsMask_reg[1][16]_1 (u_ddr_cal_n_1996),
        .\rsMask_reg[1][16]_10 (u_ddr_cal_n_2608),
        .\rsMask_reg[1][16]_11 (u_ddr_cal_n_2676),
        .\rsMask_reg[1][16]_12 (u_ddr_cal_n_2744),
        .\rsMask_reg[1][16]_13 (u_ddr_cal_n_2812),
        .\rsMask_reg[1][16]_14 (u_ddr_cal_n_2880),
        .\rsMask_reg[1][16]_2 (u_ddr_cal_n_2064),
        .\rsMask_reg[1][16]_3 (u_ddr_cal_n_2132),
        .\rsMask_reg[1][16]_4 (u_ddr_cal_n_2200),
        .\rsMask_reg[1][16]_5 (u_ddr_cal_n_2268),
        .\rsMask_reg[1][16]_6 (u_ddr_cal_n_2336),
        .\rsMask_reg[1][16]_7 (u_ddr_cal_n_2404),
        .\rsMask_reg[1][16]_8 (u_ddr_cal_n_2472),
        .\rsMask_reg[1][16]_9 (u_ddr_cal_n_2540),
        .\rsMask_reg[1][17] (u_ddr_cal_n_1840),
        .\rsMask_reg[1][17]_0 (u_ddr_cal_n_1884),
        .\rsMask_reg[1][17]_1 (u_ddr_cal_n_1997),
        .\rsMask_reg[1][17]_10 (u_ddr_cal_n_2609),
        .\rsMask_reg[1][17]_11 (u_ddr_cal_n_2677),
        .\rsMask_reg[1][17]_12 (u_ddr_cal_n_2745),
        .\rsMask_reg[1][17]_13 (u_ddr_cal_n_2813),
        .\rsMask_reg[1][17]_14 (u_ddr_cal_n_2881),
        .\rsMask_reg[1][17]_2 (u_ddr_cal_n_2065),
        .\rsMask_reg[1][17]_3 (u_ddr_cal_n_2133),
        .\rsMask_reg[1][17]_4 (u_ddr_cal_n_2201),
        .\rsMask_reg[1][17]_5 (u_ddr_cal_n_2269),
        .\rsMask_reg[1][17]_6 (u_ddr_cal_n_2337),
        .\rsMask_reg[1][17]_7 (u_ddr_cal_n_2405),
        .\rsMask_reg[1][17]_8 (u_ddr_cal_n_2473),
        .\rsMask_reg[1][17]_9 (u_ddr_cal_n_2541),
        .\rsMask_reg[1][18] (\rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[1]_71 ),
        .\rsMask_reg[1][18]_0 (\rdEn[7].u_ddr_mc_rd_en_upp/rsMask_reg[1]_79 ),
        .\rsMask_reg[1][18]_1 (u_ddr_cal_n_1847),
        .\rsMask_reg[1][18]_10 (u_ddr_cal_n_2131),
        .\rsMask_reg[1][18]_11 (u_ddr_cal_n_2204),
        .\rsMask_reg[1][18]_12 (u_ddr_cal_n_2199),
        .\rsMask_reg[1][18]_13 (u_ddr_cal_n_2272),
        .\rsMask_reg[1][18]_14 (u_ddr_cal_n_2267),
        .\rsMask_reg[1][18]_15 (u_ddr_cal_n_2340),
        .\rsMask_reg[1][18]_16 (u_ddr_cal_n_2335),
        .\rsMask_reg[1][18]_17 (u_ddr_cal_n_2408),
        .\rsMask_reg[1][18]_18 (u_ddr_cal_n_2403),
        .\rsMask_reg[1][18]_19 (u_ddr_cal_n_2476),
        .\rsMask_reg[1][18]_2 (u_ddr_cal_n_1838),
        .\rsMask_reg[1][18]_20 (u_ddr_cal_n_2471),
        .\rsMask_reg[1][18]_21 (u_ddr_cal_n_2544),
        .\rsMask_reg[1][18]_22 (u_ddr_cal_n_2539),
        .\rsMask_reg[1][18]_23 (u_ddr_cal_n_2612),
        .\rsMask_reg[1][18]_24 (u_ddr_cal_n_2607),
        .\rsMask_reg[1][18]_25 (u_ddr_cal_n_2680),
        .\rsMask_reg[1][18]_26 (u_ddr_cal_n_2675),
        .\rsMask_reg[1][18]_27 (u_ddr_cal_n_2748),
        .\rsMask_reg[1][18]_28 (u_ddr_cal_n_2743),
        .\rsMask_reg[1][18]_29 (u_ddr_cal_n_2816),
        .\rsMask_reg[1][18]_3 (u_ddr_cal_n_1891),
        .\rsMask_reg[1][18]_30 (u_ddr_cal_n_2811),
        .\rsMask_reg[1][18]_31 (u_ddr_cal_n_2884),
        .\rsMask_reg[1][18]_32 (u_ddr_cal_n_2879),
        .\rsMask_reg[1][18]_4 (u_ddr_cal_n_1882),
        .\rsMask_reg[1][18]_5 (u_ddr_cal_n_2000),
        .\rsMask_reg[1][18]_6 (u_ddr_cal_n_1995),
        .\rsMask_reg[1][18]_7 (u_ddr_cal_n_2068),
        .\rsMask_reg[1][18]_8 (u_ddr_cal_n_2063),
        .\rsMask_reg[1][18]_9 (u_ddr_cal_n_2136),
        .\rsMask_reg[1][1] (u_ddr_cal_n_891),
        .\rsMask_reg[1][1]_0 (u_ddr_cal_n_903),
        .\rsMask_reg[1][1]_1 (u_ddr_cal_n_803),
        .\rsMask_reg[1][1]_10 (u_ddr_cal_n_995),
        .\rsMask_reg[1][1]_11 (u_ddr_cal_n_1019),
        .\rsMask_reg[1][1]_12 (u_ddr_cal_n_1031),
        .\rsMask_reg[1][1]_13 (u_ddr_cal_n_1043),
        .\rsMask_reg[1][1]_14 (u_ddr_cal_n_1055),
        .\rsMask_reg[1][1]_2 (u_ddr_cal_n_839),
        .\rsMask_reg[1][1]_3 (u_ddr_cal_n_851),
        .\rsMask_reg[1][1]_4 (u_ddr_cal_n_863),
        .\rsMask_reg[1][1]_5 (u_ddr_cal_n_923),
        .\rsMask_reg[1][1]_6 (u_ddr_cal_n_935),
        .\rsMask_reg[1][1]_7 (u_ddr_cal_n_947),
        .\rsMask_reg[1][1]_8 (u_ddr_cal_n_971),
        .\rsMask_reg[1][1]_9 (u_ddr_cal_n_983),
        .\rsMask_reg[1][4] (u_ddr_cal_n_893),
        .\rsMask_reg[1][4]_0 (u_ddr_cal_n_905),
        .\rsMask_reg[1][4]_1 (u_ddr_cal_n_811),
        .\rsMask_reg[1][4]_10 (u_ddr_cal_n_997),
        .\rsMask_reg[1][4]_11 (u_ddr_cal_n_1021),
        .\rsMask_reg[1][4]_12 (u_ddr_cal_n_1033),
        .\rsMask_reg[1][4]_13 (u_ddr_cal_n_1045),
        .\rsMask_reg[1][4]_14 (u_ddr_cal_n_1057),
        .\rsMask_reg[1][4]_2 (u_ddr_cal_n_841),
        .\rsMask_reg[1][4]_3 (u_ddr_cal_n_853),
        .\rsMask_reg[1][4]_4 (u_ddr_cal_n_865),
        .\rsMask_reg[1][4]_5 (u_ddr_cal_n_925),
        .\rsMask_reg[1][4]_6 (u_ddr_cal_n_937),
        .\rsMask_reg[1][4]_7 (u_ddr_cal_n_949),
        .\rsMask_reg[1][4]_8 (u_ddr_cal_n_973),
        .\rsMask_reg[1][4]_9 (u_ddr_cal_n_985),
        .\rsMask_reg[1][5] (u_ddr_cal_n_1842),
        .\rsMask_reg[1][5]_0 (u_ddr_cal_n_1886),
        .\rsMask_reg[1][5]_1 (u_ddr_cal_n_1999),
        .\rsMask_reg[1][5]_10 (u_ddr_cal_n_2611),
        .\rsMask_reg[1][5]_11 (u_ddr_cal_n_2679),
        .\rsMask_reg[1][5]_12 (u_ddr_cal_n_2747),
        .\rsMask_reg[1][5]_13 (u_ddr_cal_n_2815),
        .\rsMask_reg[1][5]_14 (u_ddr_cal_n_2883),
        .\rsMask_reg[1][5]_2 (u_ddr_cal_n_2067),
        .\rsMask_reg[1][5]_3 (u_ddr_cal_n_2135),
        .\rsMask_reg[1][5]_4 (u_ddr_cal_n_2203),
        .\rsMask_reg[1][5]_5 (u_ddr_cal_n_2271),
        .\rsMask_reg[1][5]_6 (u_ddr_cal_n_2339),
        .\rsMask_reg[1][5]_7 (u_ddr_cal_n_2407),
        .\rsMask_reg[1][5]_8 (u_ddr_cal_n_2475),
        .\rsMask_reg[1][5]_9 (u_ddr_cal_n_2543),
        .\rsMask_reg[1][6] (u_ddr_cal_n_1841),
        .\rsMask_reg[1][6]_0 (u_ddr_cal_n_1885),
        .\rsMask_reg[1][6]_1 (u_ddr_cal_n_1998),
        .\rsMask_reg[1][6]_10 (u_ddr_cal_n_2610),
        .\rsMask_reg[1][6]_11 (u_ddr_cal_n_2678),
        .\rsMask_reg[1][6]_12 (u_ddr_cal_n_2746),
        .\rsMask_reg[1][6]_13 (u_ddr_cal_n_2814),
        .\rsMask_reg[1][6]_14 (u_ddr_cal_n_2882),
        .\rsMask_reg[1][6]_2 (u_ddr_cal_n_2066),
        .\rsMask_reg[1][6]_3 (u_ddr_cal_n_2134),
        .\rsMask_reg[1][6]_4 (u_ddr_cal_n_2202),
        .\rsMask_reg[1][6]_5 (u_ddr_cal_n_2270),
        .\rsMask_reg[1][6]_6 (u_ddr_cal_n_2338),
        .\rsMask_reg[1][6]_7 (u_ddr_cal_n_2406),
        .\rsMask_reg[1][6]_8 (u_ddr_cal_n_2474),
        .\rsMask_reg[1][6]_9 (u_ddr_cal_n_2542),
        .\rsMask_reg[1][8] (u_ddr_cal_n_1848),
        .\rsMask_reg[1][8]_0 (u_ddr_cal_n_1892),
        .\rsMask_reg[1][8]_1 (u_ddr_cal_n_2001),
        .\rsMask_reg[1][8]_10 (u_ddr_cal_n_2613),
        .\rsMask_reg[1][8]_11 (u_ddr_cal_n_2681),
        .\rsMask_reg[1][8]_12 (u_ddr_cal_n_2749),
        .\rsMask_reg[1][8]_13 (u_ddr_cal_n_2817),
        .\rsMask_reg[1][8]_14 (u_ddr_cal_n_2885),
        .\rsMask_reg[1][8]_2 (u_ddr_cal_n_2069),
        .\rsMask_reg[1][8]_3 (u_ddr_cal_n_2137),
        .\rsMask_reg[1][8]_4 (u_ddr_cal_n_2205),
        .\rsMask_reg[1][8]_5 (u_ddr_cal_n_2273),
        .\rsMask_reg[1][8]_6 (u_ddr_cal_n_2341),
        .\rsMask_reg[1][8]_7 (u_ddr_cal_n_2409),
        .\rsMask_reg[1][8]_8 (u_ddr_cal_n_2477),
        .\rsMask_reg[1][8]_9 (u_ddr_cal_n_2545),
        .\rsMask_reg[2][11] (u_ddr_cal_n_895),
        .\rsMask_reg[2][11]_0 (u_ddr_cal_n_907),
        .\rsMask_reg[2][11]_1 (u_ddr_cal_n_819),
        .\rsMask_reg[2][11]_10 (u_ddr_cal_n_999),
        .\rsMask_reg[2][11]_11 (u_ddr_cal_n_1023),
        .\rsMask_reg[2][11]_12 (u_ddr_cal_n_1035),
        .\rsMask_reg[2][11]_13 (u_ddr_cal_n_1047),
        .\rsMask_reg[2][11]_14 (u_ddr_cal_n_1059),
        .\rsMask_reg[2][11]_2 (u_ddr_cal_n_843),
        .\rsMask_reg[2][11]_3 (u_ddr_cal_n_855),
        .\rsMask_reg[2][11]_4 (u_ddr_cal_n_867),
        .\rsMask_reg[2][11]_5 (u_ddr_cal_n_927),
        .\rsMask_reg[2][11]_6 (u_ddr_cal_n_939),
        .\rsMask_reg[2][11]_7 (u_ddr_cal_n_951),
        .\rsMask_reg[2][11]_8 (u_ddr_cal_n_975),
        .\rsMask_reg[2][11]_9 (u_ddr_cal_n_987),
        .\rsMask_reg[2][9] ({u_ddr_cal_n_2945,u_ddr_cal_n_2946,u_ddr_cal_n_2947}),
        .\rsMask_reg[2][9]_0 ({u_ddr_cal_n_2965,u_ddr_cal_n_2966,u_ddr_cal_n_2967}),
        .\rsMask_reg[2][9]_1 ({u_ddr_cal_n_2004,u_ddr_cal_n_2005,u_ddr_cal_n_2006}),
        .\rsMask_reg[2][9]_10 ({u_ddr_cal_n_2616,u_ddr_cal_n_2617,u_ddr_cal_n_2618}),
        .\rsMask_reg[2][9]_11 ({u_ddr_cal_n_2684,u_ddr_cal_n_2685,u_ddr_cal_n_2686}),
        .\rsMask_reg[2][9]_12 ({u_ddr_cal_n_2752,u_ddr_cal_n_2753,u_ddr_cal_n_2754}),
        .\rsMask_reg[2][9]_13 ({u_ddr_cal_n_2820,u_ddr_cal_n_2821,u_ddr_cal_n_2822}),
        .\rsMask_reg[2][9]_14 ({u_ddr_cal_n_2888,u_ddr_cal_n_2889,u_ddr_cal_n_2890}),
        .\rsMask_reg[2][9]_2 ({u_ddr_cal_n_2072,u_ddr_cal_n_2073,u_ddr_cal_n_2074}),
        .\rsMask_reg[2][9]_3 ({u_ddr_cal_n_2140,u_ddr_cal_n_2141,u_ddr_cal_n_2142}),
        .\rsMask_reg[2][9]_4 ({u_ddr_cal_n_2208,u_ddr_cal_n_2209,u_ddr_cal_n_2210}),
        .\rsMask_reg[2][9]_5 ({u_ddr_cal_n_2276,u_ddr_cal_n_2277,u_ddr_cal_n_2278}),
        .\rsMask_reg[2][9]_6 ({u_ddr_cal_n_2344,u_ddr_cal_n_2345,u_ddr_cal_n_2346}),
        .\rsMask_reg[2][9]_7 ({u_ddr_cal_n_2412,u_ddr_cal_n_2413,u_ddr_cal_n_2414}),
        .\rsMask_reg[2][9]_8 ({u_ddr_cal_n_2480,u_ddr_cal_n_2481,u_ddr_cal_n_2482}),
        .\rsMask_reg[2][9]_9 ({u_ddr_cal_n_2548,u_ddr_cal_n_2549,u_ddr_cal_n_2550}),
        .\rsMask_reg[3][10] (u_ddr_cal_n_1855),
        .\rsMask_reg[3][10]_0 (u_ddr_cal_n_1899),
        .\rsMask_reg[3][10]_1 (u_ddr_cal_n_2014),
        .\rsMask_reg[3][10]_10 (u_ddr_cal_n_2626),
        .\rsMask_reg[3][10]_11 (u_ddr_cal_n_2694),
        .\rsMask_reg[3][10]_12 (u_ddr_cal_n_2762),
        .\rsMask_reg[3][10]_13 (u_ddr_cal_n_2830),
        .\rsMask_reg[3][10]_14 (u_ddr_cal_n_2898),
        .\rsMask_reg[3][10]_2 (u_ddr_cal_n_2082),
        .\rsMask_reg[3][10]_3 (u_ddr_cal_n_2150),
        .\rsMask_reg[3][10]_4 (u_ddr_cal_n_2218),
        .\rsMask_reg[3][10]_5 (u_ddr_cal_n_2286),
        .\rsMask_reg[3][10]_6 (u_ddr_cal_n_2354),
        .\rsMask_reg[3][10]_7 (u_ddr_cal_n_2422),
        .\rsMask_reg[3][10]_8 (u_ddr_cal_n_2490),
        .\rsMask_reg[3][10]_9 (u_ddr_cal_n_2558),
        .\rsMask_reg[3][11] ({uppCL1[45:43],uppCL1[9:7]}),
        .\rsMask_reg[3][11]_0 (u_ddr_cal_n_2007),
        .\rsMask_reg[3][11]_1 (u_ddr_cal_n_2075),
        .\rsMask_reg[3][11]_10 (u_ddr_cal_n_2687),
        .\rsMask_reg[3][11]_11 (u_ddr_cal_n_2755),
        .\rsMask_reg[3][11]_12 (u_ddr_cal_n_2823),
        .\rsMask_reg[3][11]_13 (u_ddr_cal_n_2891),
        .\rsMask_reg[3][11]_2 (u_ddr_cal_n_2143),
        .\rsMask_reg[3][11]_3 (u_ddr_cal_n_2211),
        .\rsMask_reg[3][11]_4 (u_ddr_cal_n_2279),
        .\rsMask_reg[3][11]_5 (u_ddr_cal_n_2347),
        .\rsMask_reg[3][11]_6 (u_ddr_cal_n_2415),
        .\rsMask_reg[3][11]_7 (u_ddr_cal_n_2483),
        .\rsMask_reg[3][11]_8 (u_ddr_cal_n_2551),
        .\rsMask_reg[3][11]_9 (u_ddr_cal_n_2619),
        .\rsMask_reg[3][12] (u_ddr_cal_n_1854),
        .\rsMask_reg[3][12]_0 (u_ddr_cal_n_1898),
        .\rsMask_reg[3][12]_1 (u_ddr_cal_n_2013),
        .\rsMask_reg[3][12]_10 (u_ddr_cal_n_2625),
        .\rsMask_reg[3][12]_11 (u_ddr_cal_n_2693),
        .\rsMask_reg[3][12]_12 (u_ddr_cal_n_2761),
        .\rsMask_reg[3][12]_13 (u_ddr_cal_n_2829),
        .\rsMask_reg[3][12]_14 (u_ddr_cal_n_2897),
        .\rsMask_reg[3][12]_2 (u_ddr_cal_n_2081),
        .\rsMask_reg[3][12]_3 (u_ddr_cal_n_2149),
        .\rsMask_reg[3][12]_4 (u_ddr_cal_n_2217),
        .\rsMask_reg[3][12]_5 (u_ddr_cal_n_2285),
        .\rsMask_reg[3][12]_6 (u_ddr_cal_n_2353),
        .\rsMask_reg[3][12]_7 (u_ddr_cal_n_2421),
        .\rsMask_reg[3][12]_8 (u_ddr_cal_n_2489),
        .\rsMask_reg[3][12]_9 (u_ddr_cal_n_2557),
        .\rsMask_reg[3][15] (u_ddr_cal_n_919),
        .\rsMask_reg[3][15]_0 (u_ddr_cal_n_915),
        .\rsMask_reg[3][15]_1 (u_ddr_cal_n_877),
        .\rsMask_reg[3][15]_10 (u_ddr_cal_n_1009),
        .\rsMask_reg[3][15]_11 (u_ddr_cal_n_1069),
        .\rsMask_reg[3][15]_12 (u_ddr_cal_n_1073),
        .\rsMask_reg[3][15]_13 (u_ddr_cal_n_1077),
        .\rsMask_reg[3][15]_14 (u_ddr_cal_n_1081),
        .\rsMask_reg[3][15]_2 (u_ddr_cal_n_885),
        .\rsMask_reg[3][15]_3 (u_ddr_cal_n_889),
        .\rsMask_reg[3][15]_4 (u_ddr_cal_n_881),
        .\rsMask_reg[3][15]_5 (u_ddr_cal_n_961),
        .\rsMask_reg[3][15]_6 (u_ddr_cal_n_969),
        .\rsMask_reg[3][15]_7 (u_ddr_cal_n_965),
        .\rsMask_reg[3][15]_8 (u_ddr_cal_n_1013),
        .\rsMask_reg[3][15]_9 (u_ddr_cal_n_1017),
        .\rsMask_reg[3][16] (u_ddr_cal_n_1850),
        .\rsMask_reg[3][16]_0 (u_ddr_cal_n_1894),
        .\rsMask_reg[3][16]_1 (u_ddr_cal_n_2009),
        .\rsMask_reg[3][16]_10 (u_ddr_cal_n_2621),
        .\rsMask_reg[3][16]_11 (u_ddr_cal_n_2689),
        .\rsMask_reg[3][16]_12 (u_ddr_cal_n_2757),
        .\rsMask_reg[3][16]_13 (u_ddr_cal_n_2825),
        .\rsMask_reg[3][16]_14 (u_ddr_cal_n_2893),
        .\rsMask_reg[3][16]_2 (u_ddr_cal_n_2077),
        .\rsMask_reg[3][16]_3 (u_ddr_cal_n_2145),
        .\rsMask_reg[3][16]_4 (u_ddr_cal_n_2213),
        .\rsMask_reg[3][16]_5 (u_ddr_cal_n_2281),
        .\rsMask_reg[3][16]_6 (u_ddr_cal_n_2349),
        .\rsMask_reg[3][16]_7 (u_ddr_cal_n_2417),
        .\rsMask_reg[3][16]_8 (u_ddr_cal_n_2485),
        .\rsMask_reg[3][16]_9 (u_ddr_cal_n_2553),
        .\rsMask_reg[3][17] (u_ddr_cal_n_1851),
        .\rsMask_reg[3][17]_0 (u_ddr_cal_n_1895),
        .\rsMask_reg[3][17]_1 (u_ddr_cal_n_2010),
        .\rsMask_reg[3][17]_10 (u_ddr_cal_n_2622),
        .\rsMask_reg[3][17]_11 (u_ddr_cal_n_2690),
        .\rsMask_reg[3][17]_12 (u_ddr_cal_n_2758),
        .\rsMask_reg[3][17]_13 (u_ddr_cal_n_2826),
        .\rsMask_reg[3][17]_14 (u_ddr_cal_n_2894),
        .\rsMask_reg[3][17]_2 (u_ddr_cal_n_2078),
        .\rsMask_reg[3][17]_3 (u_ddr_cal_n_2146),
        .\rsMask_reg[3][17]_4 (u_ddr_cal_n_2214),
        .\rsMask_reg[3][17]_5 (u_ddr_cal_n_2282),
        .\rsMask_reg[3][17]_6 (u_ddr_cal_n_2350),
        .\rsMask_reg[3][17]_7 (u_ddr_cal_n_2418),
        .\rsMask_reg[3][17]_8 (u_ddr_cal_n_2486),
        .\rsMask_reg[3][17]_9 (u_ddr_cal_n_2554),
        .\rsMask_reg[3][18] (\rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[3]_73 ),
        .\rsMask_reg[3][18]_0 (\rdEn[7].u_ddr_mc_rd_en_upp/rsMask_reg[3]_81 ),
        .\rsMask_reg[3][18]_1 (u_ddr_cal_n_1856),
        .\rsMask_reg[3][18]_10 (u_ddr_cal_n_2144),
        .\rsMask_reg[3][18]_11 (u_ddr_cal_n_2219),
        .\rsMask_reg[3][18]_12 (u_ddr_cal_n_2212),
        .\rsMask_reg[3][18]_13 (u_ddr_cal_n_2287),
        .\rsMask_reg[3][18]_14 (u_ddr_cal_n_2280),
        .\rsMask_reg[3][18]_15 (u_ddr_cal_n_2355),
        .\rsMask_reg[3][18]_16 (u_ddr_cal_n_2348),
        .\rsMask_reg[3][18]_17 (u_ddr_cal_n_2423),
        .\rsMask_reg[3][18]_18 (u_ddr_cal_n_2416),
        .\rsMask_reg[3][18]_19 (u_ddr_cal_n_2491),
        .\rsMask_reg[3][18]_2 (u_ddr_cal_n_1849),
        .\rsMask_reg[3][18]_20 (u_ddr_cal_n_2484),
        .\rsMask_reg[3][18]_21 (u_ddr_cal_n_2559),
        .\rsMask_reg[3][18]_22 (u_ddr_cal_n_2552),
        .\rsMask_reg[3][18]_23 (u_ddr_cal_n_2627),
        .\rsMask_reg[3][18]_24 (u_ddr_cal_n_2620),
        .\rsMask_reg[3][18]_25 (u_ddr_cal_n_2695),
        .\rsMask_reg[3][18]_26 (u_ddr_cal_n_2688),
        .\rsMask_reg[3][18]_27 (u_ddr_cal_n_2763),
        .\rsMask_reg[3][18]_28 (u_ddr_cal_n_2756),
        .\rsMask_reg[3][18]_29 (u_ddr_cal_n_2831),
        .\rsMask_reg[3][18]_3 (u_ddr_cal_n_1900),
        .\rsMask_reg[3][18]_30 (u_ddr_cal_n_2824),
        .\rsMask_reg[3][18]_31 (u_ddr_cal_n_2899),
        .\rsMask_reg[3][18]_32 (u_ddr_cal_n_2892),
        .\rsMask_reg[3][18]_4 (u_ddr_cal_n_1893),
        .\rsMask_reg[3][18]_5 (u_ddr_cal_n_2015),
        .\rsMask_reg[3][18]_6 (u_ddr_cal_n_2008),
        .\rsMask_reg[3][18]_7 (u_ddr_cal_n_2083),
        .\rsMask_reg[3][18]_8 (u_ddr_cal_n_2076),
        .\rsMask_reg[3][18]_9 (u_ddr_cal_n_2151),
        .\rsMask_reg[3][1] (u_ddr_cal_n_894),
        .\rsMask_reg[3][1]_0 (u_ddr_cal_n_906),
        .\rsMask_reg[3][1]_1 (u_ddr_cal_n_812),
        .\rsMask_reg[3][1]_10 (u_ddr_cal_n_998),
        .\rsMask_reg[3][1]_11 (u_ddr_cal_n_1022),
        .\rsMask_reg[3][1]_12 (u_ddr_cal_n_1034),
        .\rsMask_reg[3][1]_13 (u_ddr_cal_n_1046),
        .\rsMask_reg[3][1]_14 (u_ddr_cal_n_1058),
        .\rsMask_reg[3][1]_2 (u_ddr_cal_n_842),
        .\rsMask_reg[3][1]_3 (u_ddr_cal_n_854),
        .\rsMask_reg[3][1]_4 (u_ddr_cal_n_866),
        .\rsMask_reg[3][1]_5 (u_ddr_cal_n_926),
        .\rsMask_reg[3][1]_6 (u_ddr_cal_n_938),
        .\rsMask_reg[3][1]_7 (u_ddr_cal_n_950),
        .\rsMask_reg[3][1]_8 (u_ddr_cal_n_974),
        .\rsMask_reg[3][1]_9 (u_ddr_cal_n_986),
        .\rsMask_reg[3][2] (u_ddr_cal_n_1858),
        .\rsMask_reg[3][2]_0 (u_ddr_cal_n_1902),
        .\rsMask_reg[3][2]_1 (u_ddr_cal_n_2017),
        .\rsMask_reg[3][2]_10 (u_ddr_cal_n_2629),
        .\rsMask_reg[3][2]_11 (u_ddr_cal_n_2697),
        .\rsMask_reg[3][2]_12 (u_ddr_cal_n_2765),
        .\rsMask_reg[3][2]_13 (u_ddr_cal_n_2833),
        .\rsMask_reg[3][2]_14 (u_ddr_cal_n_2901),
        .\rsMask_reg[3][2]_2 (u_ddr_cal_n_2085),
        .\rsMask_reg[3][2]_3 (u_ddr_cal_n_2153),
        .\rsMask_reg[3][2]_4 (u_ddr_cal_n_2221),
        .\rsMask_reg[3][2]_5 (u_ddr_cal_n_2289),
        .\rsMask_reg[3][2]_6 (u_ddr_cal_n_2357),
        .\rsMask_reg[3][2]_7 (u_ddr_cal_n_2425),
        .\rsMask_reg[3][2]_8 (u_ddr_cal_n_2493),
        .\rsMask_reg[3][2]_9 (u_ddr_cal_n_2561),
        .\rsMask_reg[3][3] (u_ddr_cal_n_1859),
        .\rsMask_reg[3][3]_0 (u_ddr_cal_n_1903),
        .\rsMask_reg[3][3]_1 (u_ddr_cal_n_2018),
        .\rsMask_reg[3][3]_10 (u_ddr_cal_n_2630),
        .\rsMask_reg[3][3]_11 (u_ddr_cal_n_2698),
        .\rsMask_reg[3][3]_12 (u_ddr_cal_n_2766),
        .\rsMask_reg[3][3]_13 (u_ddr_cal_n_2834),
        .\rsMask_reg[3][3]_14 (u_ddr_cal_n_2902),
        .\rsMask_reg[3][3]_2 (u_ddr_cal_n_2086),
        .\rsMask_reg[3][3]_3 (u_ddr_cal_n_2154),
        .\rsMask_reg[3][3]_4 (u_ddr_cal_n_2222),
        .\rsMask_reg[3][3]_5 (u_ddr_cal_n_2290),
        .\rsMask_reg[3][3]_6 (u_ddr_cal_n_2358),
        .\rsMask_reg[3][3]_7 (u_ddr_cal_n_2426),
        .\rsMask_reg[3][3]_8 (u_ddr_cal_n_2494),
        .\rsMask_reg[3][3]_9 (u_ddr_cal_n_2562),
        .\rsMask_reg[3][4] (u_ddr_cal_n_896),
        .\rsMask_reg[3][4]_0 (u_ddr_cal_n_908),
        .\rsMask_reg[3][4]_1 (u_ddr_cal_n_820),
        .\rsMask_reg[3][4]_10 (u_ddr_cal_n_1000),
        .\rsMask_reg[3][4]_11 (u_ddr_cal_n_1024),
        .\rsMask_reg[3][4]_12 (u_ddr_cal_n_1036),
        .\rsMask_reg[3][4]_13 (u_ddr_cal_n_1048),
        .\rsMask_reg[3][4]_14 (u_ddr_cal_n_1060),
        .\rsMask_reg[3][4]_2 (u_ddr_cal_n_844),
        .\rsMask_reg[3][4]_3 (u_ddr_cal_n_856),
        .\rsMask_reg[3][4]_4 (u_ddr_cal_n_868),
        .\rsMask_reg[3][4]_5 (u_ddr_cal_n_928),
        .\rsMask_reg[3][4]_6 (u_ddr_cal_n_940),
        .\rsMask_reg[3][4]_7 (u_ddr_cal_n_952),
        .\rsMask_reg[3][4]_8 (u_ddr_cal_n_976),
        .\rsMask_reg[3][4]_9 (u_ddr_cal_n_988),
        .\rsMask_reg[3][5] (u_ddr_cal_n_1853),
        .\rsMask_reg[3][5]_0 (u_ddr_cal_n_1897),
        .\rsMask_reg[3][5]_1 (u_ddr_cal_n_2012),
        .\rsMask_reg[3][5]_10 (u_ddr_cal_n_2624),
        .\rsMask_reg[3][5]_11 (u_ddr_cal_n_2692),
        .\rsMask_reg[3][5]_12 (u_ddr_cal_n_2760),
        .\rsMask_reg[3][5]_13 (u_ddr_cal_n_2828),
        .\rsMask_reg[3][5]_14 (u_ddr_cal_n_2896),
        .\rsMask_reg[3][5]_2 (u_ddr_cal_n_2080),
        .\rsMask_reg[3][5]_3 (u_ddr_cal_n_2148),
        .\rsMask_reg[3][5]_4 (u_ddr_cal_n_2216),
        .\rsMask_reg[3][5]_5 (u_ddr_cal_n_2284),
        .\rsMask_reg[3][5]_6 (u_ddr_cal_n_2352),
        .\rsMask_reg[3][5]_7 (u_ddr_cal_n_2420),
        .\rsMask_reg[3][5]_8 (u_ddr_cal_n_2488),
        .\rsMask_reg[3][5]_9 (u_ddr_cal_n_2556),
        .\rsMask_reg[3][6] (u_ddr_cal_n_1852),
        .\rsMask_reg[3][6]_0 (u_ddr_cal_n_1896),
        .\rsMask_reg[3][6]_1 (u_ddr_cal_n_2011),
        .\rsMask_reg[3][6]_10 (u_ddr_cal_n_2623),
        .\rsMask_reg[3][6]_11 (u_ddr_cal_n_2691),
        .\rsMask_reg[3][6]_12 (u_ddr_cal_n_2759),
        .\rsMask_reg[3][6]_13 (u_ddr_cal_n_2827),
        .\rsMask_reg[3][6]_14 (u_ddr_cal_n_2895),
        .\rsMask_reg[3][6]_2 (u_ddr_cal_n_2079),
        .\rsMask_reg[3][6]_3 (u_ddr_cal_n_2147),
        .\rsMask_reg[3][6]_4 (u_ddr_cal_n_2215),
        .\rsMask_reg[3][6]_5 (u_ddr_cal_n_2283),
        .\rsMask_reg[3][6]_6 (u_ddr_cal_n_2351),
        .\rsMask_reg[3][6]_7 (u_ddr_cal_n_2419),
        .\rsMask_reg[3][6]_8 (u_ddr_cal_n_2487),
        .\rsMask_reg[3][6]_9 (u_ddr_cal_n_2555),
        .\rsMask_reg[3][8] (u_ddr_cal_n_1857),
        .\rsMask_reg[3][8]_0 (u_ddr_cal_n_1901),
        .\rsMask_reg[3][8]_1 (u_ddr_cal_n_2016),
        .\rsMask_reg[3][8]_10 (u_ddr_cal_n_2628),
        .\rsMask_reg[3][8]_11 (u_ddr_cal_n_2696),
        .\rsMask_reg[3][8]_12 (u_ddr_cal_n_2764),
        .\rsMask_reg[3][8]_13 (u_ddr_cal_n_2832),
        .\rsMask_reg[3][8]_14 (u_ddr_cal_n_2900),
        .\rsMask_reg[3][8]_2 (u_ddr_cal_n_2084),
        .\rsMask_reg[3][8]_3 (u_ddr_cal_n_2152),
        .\rsMask_reg[3][8]_4 (u_ddr_cal_n_2220),
        .\rsMask_reg[3][8]_5 (u_ddr_cal_n_2288),
        .\rsMask_reg[3][8]_6 (u_ddr_cal_n_2356),
        .\rsMask_reg[3][8]_7 (u_ddr_cal_n_2424),
        .\rsMask_reg[3][8]_8 (u_ddr_cal_n_2492),
        .\rsMask_reg[3][8]_9 (u_ddr_cal_n_2560),
        .\rsMask_reg[3][9] (u_ddr_cal_n_2944),
        .\rsMask_reg[3][9]_0 (u_ddr_cal_n_2943),
        .\rsMask_reg[3][9]_1 (u_ddr_cal_n_2964),
        .\rsMask_reg[3][9]_10 (u_ddr_cal_n_2206),
        .\rsMask_reg[3][9]_11 (u_ddr_cal_n_2275),
        .\rsMask_reg[3][9]_12 (u_ddr_cal_n_2274),
        .\rsMask_reg[3][9]_13 (u_ddr_cal_n_2343),
        .\rsMask_reg[3][9]_14 (u_ddr_cal_n_2342),
        .\rsMask_reg[3][9]_15 (u_ddr_cal_n_2411),
        .\rsMask_reg[3][9]_16 (u_ddr_cal_n_2410),
        .\rsMask_reg[3][9]_17 (u_ddr_cal_n_2479),
        .\rsMask_reg[3][9]_18 (u_ddr_cal_n_2478),
        .\rsMask_reg[3][9]_19 (u_ddr_cal_n_2547),
        .\rsMask_reg[3][9]_2 (u_ddr_cal_n_2963),
        .\rsMask_reg[3][9]_20 (u_ddr_cal_n_2546),
        .\rsMask_reg[3][9]_21 (u_ddr_cal_n_2615),
        .\rsMask_reg[3][9]_22 (u_ddr_cal_n_2614),
        .\rsMask_reg[3][9]_23 (u_ddr_cal_n_2683),
        .\rsMask_reg[3][9]_24 (u_ddr_cal_n_2682),
        .\rsMask_reg[3][9]_25 (u_ddr_cal_n_2751),
        .\rsMask_reg[3][9]_26 (u_ddr_cal_n_2750),
        .\rsMask_reg[3][9]_27 (u_ddr_cal_n_2819),
        .\rsMask_reg[3][9]_28 (u_ddr_cal_n_2818),
        .\rsMask_reg[3][9]_29 (u_ddr_cal_n_2887),
        .\rsMask_reg[3][9]_3 (u_ddr_cal_n_2003),
        .\rsMask_reg[3][9]_30 (u_ddr_cal_n_2886),
        .\rsMask_reg[3][9]_4 (u_ddr_cal_n_2002),
        .\rsMask_reg[3][9]_5 (u_ddr_cal_n_2071),
        .\rsMask_reg[3][9]_6 (u_ddr_cal_n_2070),
        .\rsMask_reg[3][9]_7 (u_ddr_cal_n_2139),
        .\rsMask_reg[3][9]_8 (u_ddr_cal_n_2138),
        .\rsMask_reg[3][9]_9 (u_ddr_cal_n_2207),
        .\rsMask_reg[4][11] (u_ddr_cal_n_898),
        .\rsMask_reg[4][11]_0 (u_ddr_cal_n_910),
        .\rsMask_reg[4][11]_1 (u_ddr_cal_n_828),
        .\rsMask_reg[4][11]_10 (u_ddr_cal_n_1002),
        .\rsMask_reg[4][11]_11 (u_ddr_cal_n_1026),
        .\rsMask_reg[4][11]_12 (u_ddr_cal_n_1038),
        .\rsMask_reg[4][11]_13 (u_ddr_cal_n_1050),
        .\rsMask_reg[4][11]_14 (u_ddr_cal_n_1062),
        .\rsMask_reg[4][11]_2 (u_ddr_cal_n_846),
        .\rsMask_reg[4][11]_3 (u_ddr_cal_n_858),
        .\rsMask_reg[4][11]_4 (u_ddr_cal_n_870),
        .\rsMask_reg[4][11]_5 (u_ddr_cal_n_930),
        .\rsMask_reg[4][11]_6 (u_ddr_cal_n_942),
        .\rsMask_reg[4][11]_7 (u_ddr_cal_n_954),
        .\rsMask_reg[4][11]_8 (u_ddr_cal_n_978),
        .\rsMask_reg[4][11]_9 (u_ddr_cal_n_990),
        .\rsMask_reg[4][9] ({u_ddr_cal_n_2950,u_ddr_cal_n_2951,u_ddr_cal_n_2952}),
        .\rsMask_reg[4][9]_0 ({u_ddr_cal_n_2970,u_ddr_cal_n_2971,u_ddr_cal_n_2972}),
        .\rsMask_reg[4][9]_1 ({u_ddr_cal_n_2021,u_ddr_cal_n_2022,u_ddr_cal_n_2023}),
        .\rsMask_reg[4][9]_10 ({u_ddr_cal_n_2633,u_ddr_cal_n_2634,u_ddr_cal_n_2635}),
        .\rsMask_reg[4][9]_11 ({u_ddr_cal_n_2701,u_ddr_cal_n_2702,u_ddr_cal_n_2703}),
        .\rsMask_reg[4][9]_12 ({u_ddr_cal_n_2769,u_ddr_cal_n_2770,u_ddr_cal_n_2771}),
        .\rsMask_reg[4][9]_13 ({u_ddr_cal_n_2837,u_ddr_cal_n_2838,u_ddr_cal_n_2839}),
        .\rsMask_reg[4][9]_14 ({u_ddr_cal_n_2905,u_ddr_cal_n_2906,u_ddr_cal_n_2907}),
        .\rsMask_reg[4][9]_2 ({u_ddr_cal_n_2089,u_ddr_cal_n_2090,u_ddr_cal_n_2091}),
        .\rsMask_reg[4][9]_3 ({u_ddr_cal_n_2157,u_ddr_cal_n_2158,u_ddr_cal_n_2159}),
        .\rsMask_reg[4][9]_4 ({u_ddr_cal_n_2225,u_ddr_cal_n_2226,u_ddr_cal_n_2227}),
        .\rsMask_reg[4][9]_5 ({u_ddr_cal_n_2293,u_ddr_cal_n_2294,u_ddr_cal_n_2295}),
        .\rsMask_reg[4][9]_6 ({u_ddr_cal_n_2361,u_ddr_cal_n_2362,u_ddr_cal_n_2363}),
        .\rsMask_reg[4][9]_7 ({u_ddr_cal_n_2429,u_ddr_cal_n_2430,u_ddr_cal_n_2431}),
        .\rsMask_reg[4][9]_8 ({u_ddr_cal_n_2497,u_ddr_cal_n_2498,u_ddr_cal_n_2499}),
        .\rsMask_reg[4][9]_9 ({u_ddr_cal_n_2565,u_ddr_cal_n_2566,u_ddr_cal_n_2567}),
        .\rsMask_reg[5][10] (u_ddr_cal_n_1866),
        .\rsMask_reg[5][10]_0 (u_ddr_cal_n_1910),
        .\rsMask_reg[5][10]_1 (u_ddr_cal_n_2031),
        .\rsMask_reg[5][10]_10 (u_ddr_cal_n_2643),
        .\rsMask_reg[5][10]_11 (u_ddr_cal_n_2711),
        .\rsMask_reg[5][10]_12 (u_ddr_cal_n_2779),
        .\rsMask_reg[5][10]_13 (u_ddr_cal_n_2847),
        .\rsMask_reg[5][10]_14 (u_ddr_cal_n_2915),
        .\rsMask_reg[5][10]_2 (u_ddr_cal_n_2099),
        .\rsMask_reg[5][10]_3 (u_ddr_cal_n_2167),
        .\rsMask_reg[5][10]_4 (u_ddr_cal_n_2235),
        .\rsMask_reg[5][10]_5 (u_ddr_cal_n_2303),
        .\rsMask_reg[5][10]_6 (u_ddr_cal_n_2371),
        .\rsMask_reg[5][10]_7 (u_ddr_cal_n_2439),
        .\rsMask_reg[5][10]_8 (u_ddr_cal_n_2507),
        .\rsMask_reg[5][10]_9 (u_ddr_cal_n_2575),
        .\rsMask_reg[5][11] ({uppCL2[45:43],uppCL2[9:7]}),
        .\rsMask_reg[5][11]_0 (u_ddr_cal_n_2024),
        .\rsMask_reg[5][11]_1 (u_ddr_cal_n_2092),
        .\rsMask_reg[5][11]_10 (u_ddr_cal_n_2704),
        .\rsMask_reg[5][11]_11 (u_ddr_cal_n_2772),
        .\rsMask_reg[5][11]_12 (u_ddr_cal_n_2840),
        .\rsMask_reg[5][11]_13 (u_ddr_cal_n_2908),
        .\rsMask_reg[5][11]_2 (u_ddr_cal_n_2160),
        .\rsMask_reg[5][11]_3 (u_ddr_cal_n_2228),
        .\rsMask_reg[5][11]_4 (u_ddr_cal_n_2296),
        .\rsMask_reg[5][11]_5 (u_ddr_cal_n_2364),
        .\rsMask_reg[5][11]_6 (u_ddr_cal_n_2432),
        .\rsMask_reg[5][11]_7 (u_ddr_cal_n_2500),
        .\rsMask_reg[5][11]_8 (u_ddr_cal_n_2568),
        .\rsMask_reg[5][11]_9 (u_ddr_cal_n_2636),
        .\rsMask_reg[5][12] (u_ddr_cal_n_1865),
        .\rsMask_reg[5][12]_0 (u_ddr_cal_n_1909),
        .\rsMask_reg[5][12]_1 (u_ddr_cal_n_2030),
        .\rsMask_reg[5][12]_10 (u_ddr_cal_n_2642),
        .\rsMask_reg[5][12]_11 (u_ddr_cal_n_2710),
        .\rsMask_reg[5][12]_12 (u_ddr_cal_n_2778),
        .\rsMask_reg[5][12]_13 (u_ddr_cal_n_2846),
        .\rsMask_reg[5][12]_14 (u_ddr_cal_n_2914),
        .\rsMask_reg[5][12]_2 (u_ddr_cal_n_2098),
        .\rsMask_reg[5][12]_3 (u_ddr_cal_n_2166),
        .\rsMask_reg[5][12]_4 (u_ddr_cal_n_2234),
        .\rsMask_reg[5][12]_5 (u_ddr_cal_n_2302),
        .\rsMask_reg[5][12]_6 (u_ddr_cal_n_2370),
        .\rsMask_reg[5][12]_7 (u_ddr_cal_n_2438),
        .\rsMask_reg[5][12]_8 (u_ddr_cal_n_2506),
        .\rsMask_reg[5][12]_9 (u_ddr_cal_n_2574),
        .\rsMask_reg[5][15] (u_ddr_cal_n_922),
        .\rsMask_reg[5][15]_0 (u_ddr_cal_n_918),
        .\rsMask_reg[5][15]_1 (u_ddr_cal_n_876),
        .\rsMask_reg[5][15]_10 (u_ddr_cal_n_1008),
        .\rsMask_reg[5][15]_11 (u_ddr_cal_n_1068),
        .\rsMask_reg[5][15]_12 (u_ddr_cal_n_1072),
        .\rsMask_reg[5][15]_13 (u_ddr_cal_n_1076),
        .\rsMask_reg[5][15]_14 (u_ddr_cal_n_1080),
        .\rsMask_reg[5][15]_2 (u_ddr_cal_n_884),
        .\rsMask_reg[5][15]_3 (u_ddr_cal_n_888),
        .\rsMask_reg[5][15]_4 (u_ddr_cal_n_880),
        .\rsMask_reg[5][15]_5 (u_ddr_cal_n_960),
        .\rsMask_reg[5][15]_6 (u_ddr_cal_n_968),
        .\rsMask_reg[5][15]_7 (u_ddr_cal_n_964),
        .\rsMask_reg[5][15]_8 (u_ddr_cal_n_1012),
        .\rsMask_reg[5][15]_9 (u_ddr_cal_n_1016),
        .\rsMask_reg[5][16] (u_ddr_cal_n_1861),
        .\rsMask_reg[5][16]_0 (u_ddr_cal_n_1905),
        .\rsMask_reg[5][16]_1 (u_ddr_cal_n_2026),
        .\rsMask_reg[5][16]_10 (u_ddr_cal_n_2638),
        .\rsMask_reg[5][16]_11 (u_ddr_cal_n_2706),
        .\rsMask_reg[5][16]_12 (u_ddr_cal_n_2774),
        .\rsMask_reg[5][16]_13 (u_ddr_cal_n_2842),
        .\rsMask_reg[5][16]_14 (u_ddr_cal_n_2910),
        .\rsMask_reg[5][16]_2 (u_ddr_cal_n_2094),
        .\rsMask_reg[5][16]_3 (u_ddr_cal_n_2162),
        .\rsMask_reg[5][16]_4 (u_ddr_cal_n_2230),
        .\rsMask_reg[5][16]_5 (u_ddr_cal_n_2298),
        .\rsMask_reg[5][16]_6 (u_ddr_cal_n_2366),
        .\rsMask_reg[5][16]_7 (u_ddr_cal_n_2434),
        .\rsMask_reg[5][16]_8 (u_ddr_cal_n_2502),
        .\rsMask_reg[5][16]_9 (u_ddr_cal_n_2570),
        .\rsMask_reg[5][17] (u_ddr_cal_n_1862),
        .\rsMask_reg[5][17]_0 (u_ddr_cal_n_1906),
        .\rsMask_reg[5][17]_1 (u_ddr_cal_n_2027),
        .\rsMask_reg[5][17]_10 (u_ddr_cal_n_2639),
        .\rsMask_reg[5][17]_11 (u_ddr_cal_n_2707),
        .\rsMask_reg[5][17]_12 (u_ddr_cal_n_2775),
        .\rsMask_reg[5][17]_13 (u_ddr_cal_n_2843),
        .\rsMask_reg[5][17]_14 (u_ddr_cal_n_2911),
        .\rsMask_reg[5][17]_2 (u_ddr_cal_n_2095),
        .\rsMask_reg[5][17]_3 (u_ddr_cal_n_2163),
        .\rsMask_reg[5][17]_4 (u_ddr_cal_n_2231),
        .\rsMask_reg[5][17]_5 (u_ddr_cal_n_2299),
        .\rsMask_reg[5][17]_6 (u_ddr_cal_n_2367),
        .\rsMask_reg[5][17]_7 (u_ddr_cal_n_2435),
        .\rsMask_reg[5][17]_8 (u_ddr_cal_n_2503),
        .\rsMask_reg[5][17]_9 (u_ddr_cal_n_2571),
        .\rsMask_reg[5][18] (\rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[5]_75 ),
        .\rsMask_reg[5][18]_0 (\rdEn[7].u_ddr_mc_rd_en_upp/rsMask_reg[5]_83 ),
        .\rsMask_reg[5][18]_1 (u_ddr_cal_n_1867),
        .\rsMask_reg[5][18]_10 (u_ddr_cal_n_2161),
        .\rsMask_reg[5][18]_11 (u_ddr_cal_n_2236),
        .\rsMask_reg[5][18]_12 (u_ddr_cal_n_2229),
        .\rsMask_reg[5][18]_13 (u_ddr_cal_n_2304),
        .\rsMask_reg[5][18]_14 (u_ddr_cal_n_2297),
        .\rsMask_reg[5][18]_15 (u_ddr_cal_n_2372),
        .\rsMask_reg[5][18]_16 (u_ddr_cal_n_2365),
        .\rsMask_reg[5][18]_17 (u_ddr_cal_n_2440),
        .\rsMask_reg[5][18]_18 (u_ddr_cal_n_2433),
        .\rsMask_reg[5][18]_19 (u_ddr_cal_n_2508),
        .\rsMask_reg[5][18]_2 (u_ddr_cal_n_1860),
        .\rsMask_reg[5][18]_20 (u_ddr_cal_n_2501),
        .\rsMask_reg[5][18]_21 (u_ddr_cal_n_2576),
        .\rsMask_reg[5][18]_22 (u_ddr_cal_n_2569),
        .\rsMask_reg[5][18]_23 (u_ddr_cal_n_2644),
        .\rsMask_reg[5][18]_24 (u_ddr_cal_n_2637),
        .\rsMask_reg[5][18]_25 (u_ddr_cal_n_2712),
        .\rsMask_reg[5][18]_26 (u_ddr_cal_n_2705),
        .\rsMask_reg[5][18]_27 (u_ddr_cal_n_2780),
        .\rsMask_reg[5][18]_28 (u_ddr_cal_n_2773),
        .\rsMask_reg[5][18]_29 (u_ddr_cal_n_2848),
        .\rsMask_reg[5][18]_3 (u_ddr_cal_n_1911),
        .\rsMask_reg[5][18]_30 (u_ddr_cal_n_2841),
        .\rsMask_reg[5][18]_31 (u_ddr_cal_n_2916),
        .\rsMask_reg[5][18]_32 (u_ddr_cal_n_2909),
        .\rsMask_reg[5][18]_4 (u_ddr_cal_n_1904),
        .\rsMask_reg[5][18]_5 (u_ddr_cal_n_2032),
        .\rsMask_reg[5][18]_6 (u_ddr_cal_n_2025),
        .\rsMask_reg[5][18]_7 (u_ddr_cal_n_2100),
        .\rsMask_reg[5][18]_8 (u_ddr_cal_n_2093),
        .\rsMask_reg[5][18]_9 (u_ddr_cal_n_2168),
        .\rsMask_reg[5][1] (u_ddr_cal_n_897),
        .\rsMask_reg[5][1]_0 (u_ddr_cal_n_909),
        .\rsMask_reg[5][1]_1 (u_ddr_cal_n_821),
        .\rsMask_reg[5][1]_10 (u_ddr_cal_n_1001),
        .\rsMask_reg[5][1]_11 (u_ddr_cal_n_1025),
        .\rsMask_reg[5][1]_12 (u_ddr_cal_n_1037),
        .\rsMask_reg[5][1]_13 (u_ddr_cal_n_1049),
        .\rsMask_reg[5][1]_14 (u_ddr_cal_n_1061),
        .\rsMask_reg[5][1]_2 (u_ddr_cal_n_845),
        .\rsMask_reg[5][1]_3 (u_ddr_cal_n_857),
        .\rsMask_reg[5][1]_4 (u_ddr_cal_n_869),
        .\rsMask_reg[5][1]_5 (u_ddr_cal_n_929),
        .\rsMask_reg[5][1]_6 (u_ddr_cal_n_941),
        .\rsMask_reg[5][1]_7 (u_ddr_cal_n_953),
        .\rsMask_reg[5][1]_8 (u_ddr_cal_n_977),
        .\rsMask_reg[5][1]_9 (u_ddr_cal_n_989),
        .\rsMask_reg[5][2] (u_ddr_cal_n_1869),
        .\rsMask_reg[5][2]_0 (u_ddr_cal_n_1913),
        .\rsMask_reg[5][2]_1 (u_ddr_cal_n_2034),
        .\rsMask_reg[5][2]_10 (u_ddr_cal_n_2646),
        .\rsMask_reg[5][2]_11 (u_ddr_cal_n_2714),
        .\rsMask_reg[5][2]_12 (u_ddr_cal_n_2782),
        .\rsMask_reg[5][2]_13 (u_ddr_cal_n_2850),
        .\rsMask_reg[5][2]_14 (u_ddr_cal_n_2918),
        .\rsMask_reg[5][2]_2 (u_ddr_cal_n_2102),
        .\rsMask_reg[5][2]_3 (u_ddr_cal_n_2170),
        .\rsMask_reg[5][2]_4 (u_ddr_cal_n_2238),
        .\rsMask_reg[5][2]_5 (u_ddr_cal_n_2306),
        .\rsMask_reg[5][2]_6 (u_ddr_cal_n_2374),
        .\rsMask_reg[5][2]_7 (u_ddr_cal_n_2442),
        .\rsMask_reg[5][2]_8 (u_ddr_cal_n_2510),
        .\rsMask_reg[5][2]_9 (u_ddr_cal_n_2578),
        .\rsMask_reg[5][3] (u_ddr_cal_n_1870),
        .\rsMask_reg[5][3]_0 (u_ddr_cal_n_1914),
        .\rsMask_reg[5][3]_1 (u_ddr_cal_n_2035),
        .\rsMask_reg[5][3]_10 (u_ddr_cal_n_2647),
        .\rsMask_reg[5][3]_11 (u_ddr_cal_n_2715),
        .\rsMask_reg[5][3]_12 (u_ddr_cal_n_2783),
        .\rsMask_reg[5][3]_13 (u_ddr_cal_n_2851),
        .\rsMask_reg[5][3]_14 (u_ddr_cal_n_2919),
        .\rsMask_reg[5][3]_2 (u_ddr_cal_n_2103),
        .\rsMask_reg[5][3]_3 (u_ddr_cal_n_2171),
        .\rsMask_reg[5][3]_4 (u_ddr_cal_n_2239),
        .\rsMask_reg[5][3]_5 (u_ddr_cal_n_2307),
        .\rsMask_reg[5][3]_6 (u_ddr_cal_n_2375),
        .\rsMask_reg[5][3]_7 (u_ddr_cal_n_2443),
        .\rsMask_reg[5][3]_8 (u_ddr_cal_n_2511),
        .\rsMask_reg[5][3]_9 (u_ddr_cal_n_2579),
        .\rsMask_reg[5][4] (u_ddr_cal_n_899),
        .\rsMask_reg[5][4]_0 (u_ddr_cal_n_911),
        .\rsMask_reg[5][4]_1 (u_ddr_cal_n_829),
        .\rsMask_reg[5][4]_10 (u_ddr_cal_n_1003),
        .\rsMask_reg[5][4]_11 (u_ddr_cal_n_1027),
        .\rsMask_reg[5][4]_12 (u_ddr_cal_n_1039),
        .\rsMask_reg[5][4]_13 (u_ddr_cal_n_1051),
        .\rsMask_reg[5][4]_14 (u_ddr_cal_n_1063),
        .\rsMask_reg[5][4]_2 (u_ddr_cal_n_847),
        .\rsMask_reg[5][4]_3 (u_ddr_cal_n_859),
        .\rsMask_reg[5][4]_4 (u_ddr_cal_n_871),
        .\rsMask_reg[5][4]_5 (u_ddr_cal_n_931),
        .\rsMask_reg[5][4]_6 (u_ddr_cal_n_943),
        .\rsMask_reg[5][4]_7 (u_ddr_cal_n_955),
        .\rsMask_reg[5][4]_8 (u_ddr_cal_n_979),
        .\rsMask_reg[5][4]_9 (u_ddr_cal_n_991),
        .\rsMask_reg[5][5] (u_ddr_cal_n_1864),
        .\rsMask_reg[5][5]_0 (u_ddr_cal_n_1908),
        .\rsMask_reg[5][5]_1 (u_ddr_cal_n_2029),
        .\rsMask_reg[5][5]_10 (u_ddr_cal_n_2641),
        .\rsMask_reg[5][5]_11 (u_ddr_cal_n_2709),
        .\rsMask_reg[5][5]_12 (u_ddr_cal_n_2777),
        .\rsMask_reg[5][5]_13 (u_ddr_cal_n_2845),
        .\rsMask_reg[5][5]_14 (u_ddr_cal_n_2913),
        .\rsMask_reg[5][5]_2 (u_ddr_cal_n_2097),
        .\rsMask_reg[5][5]_3 (u_ddr_cal_n_2165),
        .\rsMask_reg[5][5]_4 (u_ddr_cal_n_2233),
        .\rsMask_reg[5][5]_5 (u_ddr_cal_n_2301),
        .\rsMask_reg[5][5]_6 (u_ddr_cal_n_2369),
        .\rsMask_reg[5][5]_7 (u_ddr_cal_n_2437),
        .\rsMask_reg[5][5]_8 (u_ddr_cal_n_2505),
        .\rsMask_reg[5][5]_9 (u_ddr_cal_n_2573),
        .\rsMask_reg[5][6] (u_ddr_cal_n_1863),
        .\rsMask_reg[5][6]_0 (u_ddr_cal_n_1907),
        .\rsMask_reg[5][6]_1 (u_ddr_cal_n_2028),
        .\rsMask_reg[5][6]_10 (u_ddr_cal_n_2640),
        .\rsMask_reg[5][6]_11 (u_ddr_cal_n_2708),
        .\rsMask_reg[5][6]_12 (u_ddr_cal_n_2776),
        .\rsMask_reg[5][6]_13 (u_ddr_cal_n_2844),
        .\rsMask_reg[5][6]_14 (u_ddr_cal_n_2912),
        .\rsMask_reg[5][6]_2 (u_ddr_cal_n_2096),
        .\rsMask_reg[5][6]_3 (u_ddr_cal_n_2164),
        .\rsMask_reg[5][6]_4 (u_ddr_cal_n_2232),
        .\rsMask_reg[5][6]_5 (u_ddr_cal_n_2300),
        .\rsMask_reg[5][6]_6 (u_ddr_cal_n_2368),
        .\rsMask_reg[5][6]_7 (u_ddr_cal_n_2436),
        .\rsMask_reg[5][6]_8 (u_ddr_cal_n_2504),
        .\rsMask_reg[5][6]_9 (u_ddr_cal_n_2572),
        .\rsMask_reg[5][8] (u_ddr_cal_n_1868),
        .\rsMask_reg[5][8]_0 (u_ddr_cal_n_1912),
        .\rsMask_reg[5][8]_1 (u_ddr_cal_n_2033),
        .\rsMask_reg[5][8]_10 (u_ddr_cal_n_2645),
        .\rsMask_reg[5][8]_11 (u_ddr_cal_n_2713),
        .\rsMask_reg[5][8]_12 (u_ddr_cal_n_2781),
        .\rsMask_reg[5][8]_13 (u_ddr_cal_n_2849),
        .\rsMask_reg[5][8]_14 (u_ddr_cal_n_2917),
        .\rsMask_reg[5][8]_2 (u_ddr_cal_n_2101),
        .\rsMask_reg[5][8]_3 (u_ddr_cal_n_2169),
        .\rsMask_reg[5][8]_4 (u_ddr_cal_n_2237),
        .\rsMask_reg[5][8]_5 (u_ddr_cal_n_2305),
        .\rsMask_reg[5][8]_6 (u_ddr_cal_n_2373),
        .\rsMask_reg[5][8]_7 (u_ddr_cal_n_2441),
        .\rsMask_reg[5][8]_8 (u_ddr_cal_n_2509),
        .\rsMask_reg[5][8]_9 (u_ddr_cal_n_2577),
        .\rsMask_reg[5][9] (u_ddr_cal_n_2949),
        .\rsMask_reg[5][9]_0 (u_ddr_cal_n_2948),
        .\rsMask_reg[5][9]_1 (u_ddr_cal_n_2969),
        .\rsMask_reg[5][9]_10 (u_ddr_cal_n_2223),
        .\rsMask_reg[5][9]_11 (u_ddr_cal_n_2292),
        .\rsMask_reg[5][9]_12 (u_ddr_cal_n_2291),
        .\rsMask_reg[5][9]_13 (u_ddr_cal_n_2360),
        .\rsMask_reg[5][9]_14 (u_ddr_cal_n_2359),
        .\rsMask_reg[5][9]_15 (u_ddr_cal_n_2428),
        .\rsMask_reg[5][9]_16 (u_ddr_cal_n_2427),
        .\rsMask_reg[5][9]_17 (u_ddr_cal_n_2496),
        .\rsMask_reg[5][9]_18 (u_ddr_cal_n_2495),
        .\rsMask_reg[5][9]_19 (u_ddr_cal_n_2564),
        .\rsMask_reg[5][9]_2 (u_ddr_cal_n_2968),
        .\rsMask_reg[5][9]_20 (u_ddr_cal_n_2563),
        .\rsMask_reg[5][9]_21 (u_ddr_cal_n_2632),
        .\rsMask_reg[5][9]_22 (u_ddr_cal_n_2631),
        .\rsMask_reg[5][9]_23 (u_ddr_cal_n_2700),
        .\rsMask_reg[5][9]_24 (u_ddr_cal_n_2699),
        .\rsMask_reg[5][9]_25 (u_ddr_cal_n_2768),
        .\rsMask_reg[5][9]_26 (u_ddr_cal_n_2767),
        .\rsMask_reg[5][9]_27 (u_ddr_cal_n_2836),
        .\rsMask_reg[5][9]_28 (u_ddr_cal_n_2835),
        .\rsMask_reg[5][9]_29 (u_ddr_cal_n_2904),
        .\rsMask_reg[5][9]_3 (u_ddr_cal_n_2020),
        .\rsMask_reg[5][9]_30 (u_ddr_cal_n_2903),
        .\rsMask_reg[5][9]_4 (u_ddr_cal_n_2019),
        .\rsMask_reg[5][9]_5 (u_ddr_cal_n_2088),
        .\rsMask_reg[5][9]_6 (u_ddr_cal_n_2087),
        .\rsMask_reg[5][9]_7 (u_ddr_cal_n_2156),
        .\rsMask_reg[5][9]_8 (u_ddr_cal_n_2155),
        .\rsMask_reg[5][9]_9 (u_ddr_cal_n_2224),
        .\rsMask_reg[6][11] (u_ddr_cal_n_901),
        .\rsMask_reg[6][11]_0 (u_ddr_cal_n_913),
        .\rsMask_reg[6][11]_1 (u_ddr_cal_n_837),
        .\rsMask_reg[6][11]_10 (u_ddr_cal_n_1005),
        .\rsMask_reg[6][11]_11 (u_ddr_cal_n_1029),
        .\rsMask_reg[6][11]_12 (u_ddr_cal_n_1041),
        .\rsMask_reg[6][11]_13 (u_ddr_cal_n_1053),
        .\rsMask_reg[6][11]_14 (u_ddr_cal_n_1065),
        .\rsMask_reg[6][11]_2 (u_ddr_cal_n_849),
        .\rsMask_reg[6][11]_3 (u_ddr_cal_n_861),
        .\rsMask_reg[6][11]_4 (u_ddr_cal_n_873),
        .\rsMask_reg[6][11]_5 (u_ddr_cal_n_933),
        .\rsMask_reg[6][11]_6 (u_ddr_cal_n_945),
        .\rsMask_reg[6][11]_7 (u_ddr_cal_n_957),
        .\rsMask_reg[6][11]_8 (u_ddr_cal_n_981),
        .\rsMask_reg[6][11]_9 (u_ddr_cal_n_993),
        .\rsMask_reg[6][9] ({u_ddr_cal_n_2955,u_ddr_cal_n_2956,u_ddr_cal_n_2957}),
        .\rsMask_reg[6][9]_0 ({u_ddr_cal_n_2975,u_ddr_cal_n_2976,u_ddr_cal_n_2977}),
        .\rsMask_reg[6][9]_1 ({u_ddr_cal_n_2038,u_ddr_cal_n_2039,u_ddr_cal_n_2040}),
        .\rsMask_reg[6][9]_10 ({u_ddr_cal_n_2650,u_ddr_cal_n_2651,u_ddr_cal_n_2652}),
        .\rsMask_reg[6][9]_11 ({u_ddr_cal_n_2718,u_ddr_cal_n_2719,u_ddr_cal_n_2720}),
        .\rsMask_reg[6][9]_12 ({u_ddr_cal_n_2786,u_ddr_cal_n_2787,u_ddr_cal_n_2788}),
        .\rsMask_reg[6][9]_13 ({u_ddr_cal_n_2854,u_ddr_cal_n_2855,u_ddr_cal_n_2856}),
        .\rsMask_reg[6][9]_14 ({u_ddr_cal_n_2922,u_ddr_cal_n_2923,u_ddr_cal_n_2924}),
        .\rsMask_reg[6][9]_2 ({u_ddr_cal_n_2106,u_ddr_cal_n_2107,u_ddr_cal_n_2108}),
        .\rsMask_reg[6][9]_3 ({u_ddr_cal_n_2174,u_ddr_cal_n_2175,u_ddr_cal_n_2176}),
        .\rsMask_reg[6][9]_4 ({u_ddr_cal_n_2242,u_ddr_cal_n_2243,u_ddr_cal_n_2244}),
        .\rsMask_reg[6][9]_5 ({u_ddr_cal_n_2310,u_ddr_cal_n_2311,u_ddr_cal_n_2312}),
        .\rsMask_reg[6][9]_6 ({u_ddr_cal_n_2378,u_ddr_cal_n_2379,u_ddr_cal_n_2380}),
        .\rsMask_reg[6][9]_7 ({u_ddr_cal_n_2446,u_ddr_cal_n_2447,u_ddr_cal_n_2448}),
        .\rsMask_reg[6][9]_8 ({u_ddr_cal_n_2514,u_ddr_cal_n_2515,u_ddr_cal_n_2516}),
        .\rsMask_reg[6][9]_9 ({u_ddr_cal_n_2582,u_ddr_cal_n_2583,u_ddr_cal_n_2584}),
        .\rsMask_reg[7][10] (u_ddr_cal_n_1877),
        .\rsMask_reg[7][10]_0 (u_ddr_cal_n_1921),
        .\rsMask_reg[7][10]_1 (u_ddr_cal_n_2048),
        .\rsMask_reg[7][10]_10 (u_ddr_cal_n_2660),
        .\rsMask_reg[7][10]_11 (u_ddr_cal_n_2728),
        .\rsMask_reg[7][10]_12 (u_ddr_cal_n_2796),
        .\rsMask_reg[7][10]_13 (u_ddr_cal_n_2864),
        .\rsMask_reg[7][10]_14 (u_ddr_cal_n_2932),
        .\rsMask_reg[7][10]_2 (u_ddr_cal_n_2116),
        .\rsMask_reg[7][10]_3 (u_ddr_cal_n_2184),
        .\rsMask_reg[7][10]_4 (u_ddr_cal_n_2252),
        .\rsMask_reg[7][10]_5 (u_ddr_cal_n_2320),
        .\rsMask_reg[7][10]_6 (u_ddr_cal_n_2388),
        .\rsMask_reg[7][10]_7 (u_ddr_cal_n_2456),
        .\rsMask_reg[7][10]_8 (u_ddr_cal_n_2524),
        .\rsMask_reg[7][10]_9 (u_ddr_cal_n_2592),
        .\rsMask_reg[7][11] ({uppCL3[45:43],uppCL3[9:7]}),
        .\rsMask_reg[7][11]_0 (u_ddr_cal_n_2041),
        .\rsMask_reg[7][11]_1 (u_ddr_cal_n_2109),
        .\rsMask_reg[7][11]_10 (u_ddr_cal_n_2721),
        .\rsMask_reg[7][11]_11 (u_ddr_cal_n_2789),
        .\rsMask_reg[7][11]_12 (u_ddr_cal_n_2857),
        .\rsMask_reg[7][11]_13 (u_ddr_cal_n_2925),
        .\rsMask_reg[7][11]_2 (u_ddr_cal_n_2177),
        .\rsMask_reg[7][11]_3 (u_ddr_cal_n_2245),
        .\rsMask_reg[7][11]_4 (u_ddr_cal_n_2313),
        .\rsMask_reg[7][11]_5 (u_ddr_cal_n_2381),
        .\rsMask_reg[7][11]_6 (u_ddr_cal_n_2449),
        .\rsMask_reg[7][11]_7 (u_ddr_cal_n_2517),
        .\rsMask_reg[7][11]_8 (u_ddr_cal_n_2585),
        .\rsMask_reg[7][11]_9 (u_ddr_cal_n_2653),
        .\rsMask_reg[7][12] (u_ddr_cal_n_1876),
        .\rsMask_reg[7][12]_0 (u_ddr_cal_n_1920),
        .\rsMask_reg[7][12]_1 (u_ddr_cal_n_2047),
        .\rsMask_reg[7][12]_10 (u_ddr_cal_n_2659),
        .\rsMask_reg[7][12]_11 (u_ddr_cal_n_2727),
        .\rsMask_reg[7][12]_12 (u_ddr_cal_n_2795),
        .\rsMask_reg[7][12]_13 (u_ddr_cal_n_2863),
        .\rsMask_reg[7][12]_14 (u_ddr_cal_n_2931),
        .\rsMask_reg[7][12]_2 (u_ddr_cal_n_2115),
        .\rsMask_reg[7][12]_3 (u_ddr_cal_n_2183),
        .\rsMask_reg[7][12]_4 (u_ddr_cal_n_2251),
        .\rsMask_reg[7][12]_5 (u_ddr_cal_n_2319),
        .\rsMask_reg[7][12]_6 (u_ddr_cal_n_2387),
        .\rsMask_reg[7][12]_7 (u_ddr_cal_n_2455),
        .\rsMask_reg[7][12]_8 (u_ddr_cal_n_2523),
        .\rsMask_reg[7][12]_9 (u_ddr_cal_n_2591),
        .\rsMask_reg[7][15] (u_ddr_cal_n_921),
        .\rsMask_reg[7][15]_0 (u_ddr_cal_n_917),
        .\rsMask_reg[7][15]_1 (u_ddr_cal_n_875),
        .\rsMask_reg[7][15]_10 (u_ddr_cal_n_1007),
        .\rsMask_reg[7][15]_11 (u_ddr_cal_n_1067),
        .\rsMask_reg[7][15]_12 (u_ddr_cal_n_1071),
        .\rsMask_reg[7][15]_13 (u_ddr_cal_n_1075),
        .\rsMask_reg[7][15]_14 (u_ddr_cal_n_1079),
        .\rsMask_reg[7][15]_2 (u_ddr_cal_n_883),
        .\rsMask_reg[7][15]_3 (u_ddr_cal_n_887),
        .\rsMask_reg[7][15]_4 (u_ddr_cal_n_879),
        .\rsMask_reg[7][15]_5 (u_ddr_cal_n_959),
        .\rsMask_reg[7][15]_6 (u_ddr_cal_n_967),
        .\rsMask_reg[7][15]_7 (u_ddr_cal_n_963),
        .\rsMask_reg[7][15]_8 (u_ddr_cal_n_1011),
        .\rsMask_reg[7][15]_9 (u_ddr_cal_n_1015),
        .\rsMask_reg[7][16] (u_ddr_cal_n_1872),
        .\rsMask_reg[7][16]_0 (u_ddr_cal_n_1916),
        .\rsMask_reg[7][16]_1 (u_ddr_cal_n_2043),
        .\rsMask_reg[7][16]_10 (u_ddr_cal_n_2655),
        .\rsMask_reg[7][16]_11 (u_ddr_cal_n_2723),
        .\rsMask_reg[7][16]_12 (u_ddr_cal_n_2791),
        .\rsMask_reg[7][16]_13 (u_ddr_cal_n_2859),
        .\rsMask_reg[7][16]_14 (u_ddr_cal_n_2927),
        .\rsMask_reg[7][16]_2 (u_ddr_cal_n_2111),
        .\rsMask_reg[7][16]_3 (u_ddr_cal_n_2179),
        .\rsMask_reg[7][16]_4 (u_ddr_cal_n_2247),
        .\rsMask_reg[7][16]_5 (u_ddr_cal_n_2315),
        .\rsMask_reg[7][16]_6 (u_ddr_cal_n_2383),
        .\rsMask_reg[7][16]_7 (u_ddr_cal_n_2451),
        .\rsMask_reg[7][16]_8 (u_ddr_cal_n_2519),
        .\rsMask_reg[7][16]_9 (u_ddr_cal_n_2587),
        .\rsMask_reg[7][17] (u_ddr_mc_pi_n_830),
        .\rsMask_reg[7][17]_0 (u_ddr_mc_pi_n_832),
        .\rsMask_reg[7][17]_1 (u_ddr_mc_pi_n_834),
        .\rsMask_reg[7][17]_10 (u_ddr_mc_pi_n_852),
        .\rsMask_reg[7][17]_11 (u_ddr_mc_pi_n_854),
        .\rsMask_reg[7][17]_12 (u_ddr_mc_pi_n_856),
        .\rsMask_reg[7][17]_13 (u_ddr_cal_n_1873),
        .\rsMask_reg[7][17]_14 (u_ddr_cal_n_1917),
        .\rsMask_reg[7][17]_15 (u_ddr_cal_n_2044),
        .\rsMask_reg[7][17]_16 (u_ddr_cal_n_2112),
        .\rsMask_reg[7][17]_17 (u_ddr_cal_n_2180),
        .\rsMask_reg[7][17]_18 (u_ddr_cal_n_2248),
        .\rsMask_reg[7][17]_19 (u_ddr_cal_n_2316),
        .\rsMask_reg[7][17]_2 (u_ddr_mc_pi_n_836),
        .\rsMask_reg[7][17]_20 (u_ddr_cal_n_2384),
        .\rsMask_reg[7][17]_21 (u_ddr_cal_n_2452),
        .\rsMask_reg[7][17]_22 (u_ddr_cal_n_2520),
        .\rsMask_reg[7][17]_23 (u_ddr_cal_n_2588),
        .\rsMask_reg[7][17]_24 (u_ddr_cal_n_2656),
        .\rsMask_reg[7][17]_25 (u_ddr_cal_n_2724),
        .\rsMask_reg[7][17]_26 (u_ddr_cal_n_2792),
        .\rsMask_reg[7][17]_27 (u_ddr_cal_n_2860),
        .\rsMask_reg[7][17]_28 (u_ddr_cal_n_2928),
        .\rsMask_reg[7][17]_3 (u_ddr_mc_pi_n_838),
        .\rsMask_reg[7][17]_4 (u_ddr_mc_pi_n_840),
        .\rsMask_reg[7][17]_5 (u_ddr_mc_pi_n_842),
        .\rsMask_reg[7][17]_6 (u_ddr_mc_pi_n_844),
        .\rsMask_reg[7][17]_7 (u_ddr_mc_pi_n_846),
        .\rsMask_reg[7][17]_8 (u_ddr_mc_pi_n_848),
        .\rsMask_reg[7][17]_9 (u_ddr_mc_pi_n_850),
        .\rsMask_reg[7][18] (\rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[7]_77 ),
        .\rsMask_reg[7][18]_0 (\rdEn[7].u_ddr_mc_rd_en_upp/rsMask_reg[7]_85 ),
        .\rsMask_reg[7][18]_1 (u_ddr_mc_pi_n_829),
        .\rsMask_reg[7][18]_10 (u_ddr_mc_pi_n_847),
        .\rsMask_reg[7][18]_11 (u_ddr_mc_pi_n_849),
        .\rsMask_reg[7][18]_12 (u_ddr_mc_pi_n_851),
        .\rsMask_reg[7][18]_13 (u_ddr_mc_pi_n_853),
        .\rsMask_reg[7][18]_14 (u_ddr_mc_pi_n_855),
        .\rsMask_reg[7][18]_15 (u_ddr_cal_n_1878),
        .\rsMask_reg[7][18]_16 (u_ddr_cal_n_1871),
        .\rsMask_reg[7][18]_17 (u_ddr_cal_n_1922),
        .\rsMask_reg[7][18]_18 (u_ddr_cal_n_1915),
        .\rsMask_reg[7][18]_19 (u_ddr_cal_n_2049),
        .\rsMask_reg[7][18]_2 (u_ddr_mc_pi_n_831),
        .\rsMask_reg[7][18]_20 (u_ddr_cal_n_2042),
        .\rsMask_reg[7][18]_21 (u_ddr_cal_n_2117),
        .\rsMask_reg[7][18]_22 (u_ddr_cal_n_2110),
        .\rsMask_reg[7][18]_23 (u_ddr_cal_n_2185),
        .\rsMask_reg[7][18]_24 (u_ddr_cal_n_2178),
        .\rsMask_reg[7][18]_25 (u_ddr_cal_n_2253),
        .\rsMask_reg[7][18]_26 (u_ddr_cal_n_2246),
        .\rsMask_reg[7][18]_27 (u_ddr_cal_n_2321),
        .\rsMask_reg[7][18]_28 (u_ddr_cal_n_2314),
        .\rsMask_reg[7][18]_29 (u_ddr_cal_n_2389),
        .\rsMask_reg[7][18]_3 (u_ddr_mc_pi_n_833),
        .\rsMask_reg[7][18]_30 (u_ddr_cal_n_2382),
        .\rsMask_reg[7][18]_31 (u_ddr_cal_n_2457),
        .\rsMask_reg[7][18]_32 (u_ddr_cal_n_2450),
        .\rsMask_reg[7][18]_33 (u_ddr_cal_n_2525),
        .\rsMask_reg[7][18]_34 (u_ddr_cal_n_2518),
        .\rsMask_reg[7][18]_35 (u_ddr_cal_n_2593),
        .\rsMask_reg[7][18]_36 (u_ddr_cal_n_2586),
        .\rsMask_reg[7][18]_37 (u_ddr_cal_n_2661),
        .\rsMask_reg[7][18]_38 (u_ddr_cal_n_2654),
        .\rsMask_reg[7][18]_39 (u_ddr_cal_n_2729),
        .\rsMask_reg[7][18]_4 (u_ddr_mc_pi_n_835),
        .\rsMask_reg[7][18]_40 (u_ddr_cal_n_2722),
        .\rsMask_reg[7][18]_41 (u_ddr_cal_n_2797),
        .\rsMask_reg[7][18]_42 (u_ddr_cal_n_2790),
        .\rsMask_reg[7][18]_43 (u_ddr_cal_n_2865),
        .\rsMask_reg[7][18]_44 (u_ddr_cal_n_2858),
        .\rsMask_reg[7][18]_45 (u_ddr_cal_n_2933),
        .\rsMask_reg[7][18]_46 (u_ddr_cal_n_2926),
        .\rsMask_reg[7][18]_5 (u_ddr_mc_pi_n_837),
        .\rsMask_reg[7][18]_6 (u_ddr_mc_pi_n_839),
        .\rsMask_reg[7][18]_7 (u_ddr_mc_pi_n_841),
        .\rsMask_reg[7][18]_8 (u_ddr_mc_pi_n_843),
        .\rsMask_reg[7][18]_9 (u_ddr_mc_pi_n_845),
        .\rsMask_reg[7][1] (u_ddr_cal_n_900),
        .\rsMask_reg[7][1]_0 (u_ddr_cal_n_912),
        .\rsMask_reg[7][1]_1 (u_ddr_cal_n_830),
        .\rsMask_reg[7][1]_10 (u_ddr_cal_n_1004),
        .\rsMask_reg[7][1]_11 (u_ddr_cal_n_1028),
        .\rsMask_reg[7][1]_12 (u_ddr_cal_n_1040),
        .\rsMask_reg[7][1]_13 (u_ddr_cal_n_1052),
        .\rsMask_reg[7][1]_14 (u_ddr_cal_n_1064),
        .\rsMask_reg[7][1]_2 (u_ddr_cal_n_848),
        .\rsMask_reg[7][1]_3 (u_ddr_cal_n_860),
        .\rsMask_reg[7][1]_4 (u_ddr_cal_n_872),
        .\rsMask_reg[7][1]_5 (u_ddr_cal_n_932),
        .\rsMask_reg[7][1]_6 (u_ddr_cal_n_944),
        .\rsMask_reg[7][1]_7 (u_ddr_cal_n_956),
        .\rsMask_reg[7][1]_8 (u_ddr_cal_n_980),
        .\rsMask_reg[7][1]_9 (u_ddr_cal_n_992),
        .\rsMask_reg[7][2] (u_ddr_cal_n_1880),
        .\rsMask_reg[7][2]_0 (u_ddr_cal_n_1924),
        .\rsMask_reg[7][2]_1 (u_ddr_cal_n_2051),
        .\rsMask_reg[7][2]_10 (u_ddr_cal_n_2663),
        .\rsMask_reg[7][2]_11 (u_ddr_cal_n_2731),
        .\rsMask_reg[7][2]_12 (u_ddr_cal_n_2799),
        .\rsMask_reg[7][2]_13 (u_ddr_cal_n_2867),
        .\rsMask_reg[7][2]_14 (u_ddr_cal_n_2935),
        .\rsMask_reg[7][2]_2 (u_ddr_cal_n_2119),
        .\rsMask_reg[7][2]_3 (u_ddr_cal_n_2187),
        .\rsMask_reg[7][2]_4 (u_ddr_cal_n_2255),
        .\rsMask_reg[7][2]_5 (u_ddr_cal_n_2323),
        .\rsMask_reg[7][2]_6 (u_ddr_cal_n_2391),
        .\rsMask_reg[7][2]_7 (u_ddr_cal_n_2459),
        .\rsMask_reg[7][2]_8 (u_ddr_cal_n_2527),
        .\rsMask_reg[7][2]_9 (u_ddr_cal_n_2595),
        .\rsMask_reg[7][3] (u_ddr_cal_n_1881),
        .\rsMask_reg[7][3]_0 (u_ddr_cal_n_1925),
        .\rsMask_reg[7][3]_1 (u_ddr_cal_n_2052),
        .\rsMask_reg[7][3]_10 (u_ddr_cal_n_2664),
        .\rsMask_reg[7][3]_11 (u_ddr_cal_n_2732),
        .\rsMask_reg[7][3]_12 (u_ddr_cal_n_2800),
        .\rsMask_reg[7][3]_13 (u_ddr_cal_n_2868),
        .\rsMask_reg[7][3]_14 (u_ddr_cal_n_2936),
        .\rsMask_reg[7][3]_2 (u_ddr_cal_n_2120),
        .\rsMask_reg[7][3]_3 (u_ddr_cal_n_2188),
        .\rsMask_reg[7][3]_4 (u_ddr_cal_n_2256),
        .\rsMask_reg[7][3]_5 (u_ddr_cal_n_2324),
        .\rsMask_reg[7][3]_6 (u_ddr_cal_n_2392),
        .\rsMask_reg[7][3]_7 (u_ddr_cal_n_2460),
        .\rsMask_reg[7][3]_8 (u_ddr_cal_n_2528),
        .\rsMask_reg[7][3]_9 (u_ddr_cal_n_2596),
        .\rsMask_reg[7][4] (u_ddr_cal_n_902),
        .\rsMask_reg[7][4]_0 (u_ddr_cal_n_914),
        .\rsMask_reg[7][4]_1 (u_ddr_cal_n_838),
        .\rsMask_reg[7][4]_10 (u_ddr_cal_n_1006),
        .\rsMask_reg[7][4]_11 (u_ddr_cal_n_1030),
        .\rsMask_reg[7][4]_12 (u_ddr_cal_n_1042),
        .\rsMask_reg[7][4]_13 (u_ddr_cal_n_1054),
        .\rsMask_reg[7][4]_14 (u_ddr_cal_n_1066),
        .\rsMask_reg[7][4]_2 (u_ddr_cal_n_850),
        .\rsMask_reg[7][4]_3 (u_ddr_cal_n_862),
        .\rsMask_reg[7][4]_4 (u_ddr_cal_n_874),
        .\rsMask_reg[7][4]_5 (u_ddr_cal_n_934),
        .\rsMask_reg[7][4]_6 (u_ddr_cal_n_946),
        .\rsMask_reg[7][4]_7 (u_ddr_cal_n_958),
        .\rsMask_reg[7][4]_8 (u_ddr_cal_n_982),
        .\rsMask_reg[7][4]_9 (u_ddr_cal_n_994),
        .\rsMask_reg[7][5] (u_ddr_cal_n_1875),
        .\rsMask_reg[7][5]_0 (u_ddr_cal_n_1919),
        .\rsMask_reg[7][5]_1 (u_ddr_cal_n_2046),
        .\rsMask_reg[7][5]_10 (u_ddr_cal_n_2658),
        .\rsMask_reg[7][5]_11 (u_ddr_cal_n_2726),
        .\rsMask_reg[7][5]_12 (u_ddr_cal_n_2794),
        .\rsMask_reg[7][5]_13 (u_ddr_cal_n_2862),
        .\rsMask_reg[7][5]_14 (u_ddr_cal_n_2930),
        .\rsMask_reg[7][5]_2 (u_ddr_cal_n_2114),
        .\rsMask_reg[7][5]_3 (u_ddr_cal_n_2182),
        .\rsMask_reg[7][5]_4 (u_ddr_cal_n_2250),
        .\rsMask_reg[7][5]_5 (u_ddr_cal_n_2318),
        .\rsMask_reg[7][5]_6 (u_ddr_cal_n_2386),
        .\rsMask_reg[7][5]_7 (u_ddr_cal_n_2454),
        .\rsMask_reg[7][5]_8 (u_ddr_cal_n_2522),
        .\rsMask_reg[7][5]_9 (u_ddr_cal_n_2590),
        .\rsMask_reg[7][6] (u_ddr_cal_n_1874),
        .\rsMask_reg[7][6]_0 (u_ddr_cal_n_1918),
        .\rsMask_reg[7][6]_1 (u_ddr_cal_n_2045),
        .\rsMask_reg[7][6]_10 (u_ddr_cal_n_2657),
        .\rsMask_reg[7][6]_11 (u_ddr_cal_n_2725),
        .\rsMask_reg[7][6]_12 (u_ddr_cal_n_2793),
        .\rsMask_reg[7][6]_13 (u_ddr_cal_n_2861),
        .\rsMask_reg[7][6]_14 (u_ddr_cal_n_2929),
        .\rsMask_reg[7][6]_2 (u_ddr_cal_n_2113),
        .\rsMask_reg[7][6]_3 (u_ddr_cal_n_2181),
        .\rsMask_reg[7][6]_4 (u_ddr_cal_n_2249),
        .\rsMask_reg[7][6]_5 (u_ddr_cal_n_2317),
        .\rsMask_reg[7][6]_6 (u_ddr_cal_n_2385),
        .\rsMask_reg[7][6]_7 (u_ddr_cal_n_2453),
        .\rsMask_reg[7][6]_8 (u_ddr_cal_n_2521),
        .\rsMask_reg[7][6]_9 (u_ddr_cal_n_2589),
        .\rsMask_reg[7][8] (u_ddr_cal_n_1879),
        .\rsMask_reg[7][8]_0 (u_ddr_cal_n_1923),
        .\rsMask_reg[7][8]_1 (u_ddr_cal_n_2050),
        .\rsMask_reg[7][8]_10 (u_ddr_cal_n_2662),
        .\rsMask_reg[7][8]_11 (u_ddr_cal_n_2730),
        .\rsMask_reg[7][8]_12 (u_ddr_cal_n_2798),
        .\rsMask_reg[7][8]_13 (u_ddr_cal_n_2866),
        .\rsMask_reg[7][8]_14 (u_ddr_cal_n_2934),
        .\rsMask_reg[7][8]_2 (u_ddr_cal_n_2118),
        .\rsMask_reg[7][8]_3 (u_ddr_cal_n_2186),
        .\rsMask_reg[7][8]_4 (u_ddr_cal_n_2254),
        .\rsMask_reg[7][8]_5 (u_ddr_cal_n_2322),
        .\rsMask_reg[7][8]_6 (u_ddr_cal_n_2390),
        .\rsMask_reg[7][8]_7 (u_ddr_cal_n_2458),
        .\rsMask_reg[7][8]_8 (u_ddr_cal_n_2526),
        .\rsMask_reg[7][8]_9 (u_ddr_cal_n_2594),
        .\rsMask_reg[7][9] (u_ddr_cal_n_2954),
        .\rsMask_reg[7][9]_0 (u_ddr_cal_n_2953),
        .\rsMask_reg[7][9]_1 (u_ddr_cal_n_2974),
        .\rsMask_reg[7][9]_10 (u_ddr_cal_n_2240),
        .\rsMask_reg[7][9]_11 (u_ddr_cal_n_2309),
        .\rsMask_reg[7][9]_12 (u_ddr_cal_n_2308),
        .\rsMask_reg[7][9]_13 (u_ddr_cal_n_2377),
        .\rsMask_reg[7][9]_14 (u_ddr_cal_n_2376),
        .\rsMask_reg[7][9]_15 (u_ddr_cal_n_2445),
        .\rsMask_reg[7][9]_16 (u_ddr_cal_n_2444),
        .\rsMask_reg[7][9]_17 (u_ddr_cal_n_2513),
        .\rsMask_reg[7][9]_18 (u_ddr_cal_n_2512),
        .\rsMask_reg[7][9]_19 (u_ddr_cal_n_2581),
        .\rsMask_reg[7][9]_2 (u_ddr_cal_n_2973),
        .\rsMask_reg[7][9]_20 (u_ddr_cal_n_2580),
        .\rsMask_reg[7][9]_21 (u_ddr_cal_n_2649),
        .\rsMask_reg[7][9]_22 (u_ddr_cal_n_2648),
        .\rsMask_reg[7][9]_23 (u_ddr_cal_n_2717),
        .\rsMask_reg[7][9]_24 (u_ddr_cal_n_2716),
        .\rsMask_reg[7][9]_25 (u_ddr_cal_n_2785),
        .\rsMask_reg[7][9]_26 (u_ddr_cal_n_2784),
        .\rsMask_reg[7][9]_27 (u_ddr_cal_n_2853),
        .\rsMask_reg[7][9]_28 (u_ddr_cal_n_2852),
        .\rsMask_reg[7][9]_29 (u_ddr_cal_n_2921),
        .\rsMask_reg[7][9]_3 (u_ddr_cal_n_2037),
        .\rsMask_reg[7][9]_30 (u_ddr_cal_n_2920),
        .\rsMask_reg[7][9]_4 (u_ddr_cal_n_2036),
        .\rsMask_reg[7][9]_5 (u_ddr_cal_n_2105),
        .\rsMask_reg[7][9]_6 (u_ddr_cal_n_2104),
        .\rsMask_reg[7][9]_7 (u_ddr_cal_n_2173),
        .\rsMask_reg[7][9]_8 (u_ddr_cal_n_2172),
        .\rsMask_reg[7][9]_9 (u_ddr_cal_n_2241),
        .underfill_done_nxt(underfill_done_nxt),
        .wosp(\u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/wosp ),
        .\wosp_reg[2]_rep (u_ddr_mc_pi_n_8),
        .\wosp_reg[2]_rep__0 (u_ddr_mc_pi_n_9),
        .\wosp_reg[2]_rep__1 (u_ddr_mc_pi_n_10),
        .\wosp_reg[2]_rep__2 (u_ddr_mc_pi_n_11),
        .\wosp_reg[2]_rep__3 (u_ddr_mc_pi_n_12),
        .\wosp_reg[2]_rep__4 (u_ddr_mc_pi_n_13),
        .\wosp_reg[2]_rep__5 (u_ddr_mc_pi_n_14),
        .\wosp_reg[2]_rep__6 (u_ddr_mc_pi_n_15),
        .\wosp_reg[2]_rep__7 (u_ddr_mc_pi_n_16),
        .wrDataEn_pi(wrDataEn_pi),
        .wrDataVal(\u_ddr_mc_write/wrDataVal ),
        .\wrQ_nxt[1]_13 (\u_ddr_mc_write/wrQ_nxt[1]_13 ),
        .\wrQ_reg[0][0] (\wrQ_reg[0][0] ),
        .\wrQ_reg[0][0]_rep (u_ddr_mc_pi_n_865),
        .\wrQ_reg[0][2] (calWrCAS),
        .\wrQ_reg[0][5]_rep (\wrQ_reg[0][5]_rep ),
        .\wrQ_reg[0][5]_rep__0 (\wrQ_reg[0][5]_rep__0 ),
        .\wrQ_reg[0][5]_rep__1 (\wrQ_reg[0][5]_rep__1 ),
        .\wrQ_reg[0][6]_rep (\wrQ_reg[0][6]_rep ),
        .\wrQ_reg[0][6]_rep__0 (\wrQ_reg[0][6]_rep__0 ),
        .\wrQ_reg[0][6]_rep__1 (\wrQ_reg[0][6]_rep__1 ),
        .\wrQ_reg[0][7]_rep (\wrQ_reg[0][7]_rep ),
        .\wrQ_reg[0][7]_rep__0 (\wrQ_reg[0][7]_rep__0 ),
        .\wrQ_reg[0][7]_rep__1 (\wrQ_reg[0][7]_rep__1 ),
        .\wrQ_reg[0][8] (\wrQ_reg[0][8] ),
        .\wrQ_reg[0][8]_rep (\wrQ_reg[0][8]_rep ),
        .\wrQ_reg[0][8]_rep__0 (\wrQ_reg[0][8]_rep__0 ),
        .\wrQ_reg[0][8]_rep__0_0 (\wrQ_reg[0][8]_rep__0_0 ),
        .\wrQ_reg[0][8]_rep__1 (\wrQ_reg[0][8]_rep__1 ),
        .\wrQ_reg[0][8]_rep__1_0 (\wrQ_reg[0][8]_rep__1_0 ),
        .\wrQ_reg[1][8] (\wrQ_reg[1][8] ),
        .\wrQ_reg[1][8]_0 (\wrQ_reg[1][8]_0 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit
   (\wosp_reg[1]_0 ,
    \wosp_reg[2]_0 ,
    \wosp_reg[2]_rep_0 ,
    \wosp_reg[2]_rep__0_0 ,
    \wosp_reg[2]_rep__1_0 ,
    \wosp_reg[2]_rep__2_0 ,
    \wosp_reg[2]_rep__3_0 ,
    \wosp_reg[2]_rep__4_0 ,
    \wosp_reg[2]_rep__5_0 ,
    \wosp_reg[2]_rep__6_0 ,
    \wosp_reg[2]_rep__7_0 ,
    wrDataVal_reg,
    D,
    \wosp_reg[1]_1 ,
    \wosp_reg[1]_2 ,
    \wosp_reg[1]_3 ,
    \wosp_reg[1]_4 ,
    \wosp_reg[1]_5 ,
    \wosp_reg[1]_6 ,
    \wosp_reg[1]_7 ,
    \wosp_reg[1]_8 ,
    \wosp_reg[1]_9 ,
    \wosp_reg[1]_10 ,
    \wosp_reg[1]_11 ,
    \wosp_reg[1]_12 ,
    \wosp_reg[1]_13 ,
    \wosp_reg[1]_14 ,
    \wosp_reg[1]_15 ,
    \wosp_reg[1]_16 ,
    \wosp_reg[1]_17 ,
    \wosp_reg[1]_18 ,
    \wosp_reg[1]_19 ,
    \wosp_reg[1]_20 ,
    \wosp_reg[1]_21 ,
    \wosp_reg[1]_22 ,
    \wosp_reg[1]_23 ,
    \wosp_reg[1]_24 ,
    \wosp_reg[1]_25 ,
    \wosp_reg[1]_26 ,
    \wosp_reg[1]_27 ,
    \wosp_reg[1]_28 ,
    \wosp_reg[1]_29 ,
    \wosp_reg[1]_30 ,
    \wosp_reg[1]_31 ,
    \wosp_reg[1]_32 ,
    \wosp_reg[1]_33 ,
    \wosp_reg[1]_34 ,
    \wosp_reg[1]_35 ,
    \wosp_reg[1]_36 ,
    \wosp_reg[1]_37 ,
    \wosp_reg[1]_38 ,
    \wosp_reg[1]_39 ,
    \wosp_reg[1]_40 ,
    \wosp_reg[1]_41 ,
    \wosp_reg[1]_42 ,
    \wosp_reg[1]_43 ,
    \wosp_reg[1]_44 ,
    \wosp_reg[1]_45 ,
    \wosp_reg[1]_46 ,
    \wosp_reg[1]_47 ,
    \wosp_reg[1]_48 ,
    \wosp_reg[1]_49 ,
    \wosp_reg[1]_50 ,
    \wosp_reg[1]_51 ,
    \wosp_reg[1]_52 ,
    \wosp_reg[1]_53 ,
    \wosp_reg[1]_54 ,
    \wosp_reg[1]_55 ,
    \wosp_reg[1]_56 ,
    \wosp_reg[1]_57 ,
    \wosp_reg[1]_58 ,
    \wosp_reg[1]_59 ,
    \wosp_reg[1]_60 ,
    \wosp_reg[1]_61 ,
    \wosp_reg[1]_62 ,
    \wosp_reg[1]_63 ,
    \wosp_reg[1]_64 ,
    \wosp_reg[1]_65 ,
    \wosp_reg[1]_66 ,
    \wosp_reg[1]_67 ,
    \wosp_reg[1]_68 ,
    \wosp_reg[1]_69 ,
    \wosp_reg[1]_70 ,
    ch0_mcal_DQOut,
    \wosp_reg[1]_71 ,
    \wosp_reg[2]_rep__7_1 ,
    sel,
    \dReg_reg[6]_0 ,
    DQOut,
    DMOut,
    \dReg_reg[7]_0 ,
    dReg,
    \dReg_reg[6]_1 ,
    dReg__0,
    dReg__1,
    dReg__2,
    dReg__3,
    dReg__4,
    dReg__5,
    dReg__6,
    dReg__7,
    \dReg_reg[7]_1 ,
    \dReg_reg[6]_2 ,
    \dReg_reg[7]_2 ,
    \dReg_reg[6]_3 ,
    \dReg_reg[7]_3 ,
    \dReg_reg[6]_4 ,
    \dReg_reg[7]_4 ,
    \dReg_reg[6]_5 ,
    \dReg_reg[7]_5 ,
    \dReg_reg[6]_6 ,
    \dReg_reg[7]_6 ,
    \dReg_reg[6]_7 ,
    \dReg_reg[7]_7 ,
    \dReg_reg[6]_8 ,
    \dReg_reg[7]_8 ,
    \dReg_reg[6]_9 ,
    \dReg_reg[7]_9 ,
    dReg_0,
    \dReg_reg[6]_10 ,
    dReg__0_1,
    dReg__1_2,
    dReg__2_3,
    dReg__3_4,
    dReg__4_5,
    dReg__5_6,
    dReg__6_7,
    dReg__7_8,
    \dReg_reg[7]_10 ,
    \dReg_reg[6]_11 ,
    \dReg_reg[7]_11 ,
    \dReg_reg[6]_12 ,
    \dReg_reg[7]_12 ,
    \dReg_reg[6]_13 ,
    \dReg_reg[7]_13 ,
    \dReg_reg[6]_14 ,
    \dReg_reg[7]_14 ,
    \dReg_reg[6]_15 ,
    \dReg_reg[7]_15 ,
    \dReg_reg[6]_16 ,
    \dReg_reg[7]_16 ,
    \dReg_reg[6]_17 ,
    \dReg_reg[7]_17 ,
    \dReg_reg[6]_18 ,
    \dReg_reg[7]_18 ,
    dReg_9,
    \dReg_reg[6]_19 ,
    dReg__0_10,
    dReg__1_11,
    dReg__2_12,
    dReg__3_13,
    dReg__4_14,
    dReg__5_15,
    dReg__6_16,
    dReg__7_17,
    \dReg_reg[7]_19 ,
    \dReg_reg[6]_20 ,
    \dReg_reg[7]_20 ,
    \dReg_reg[6]_21 ,
    \dReg_reg[7]_21 ,
    \dReg_reg[6]_22 ,
    \dReg_reg[7]_22 ,
    \dReg_reg[6]_23 ,
    \dReg_reg[7]_23 ,
    \dReg_reg[6]_24 ,
    \dReg_reg[7]_24 ,
    \dReg_reg[6]_25 ,
    \dReg_reg[7]_25 ,
    \dReg_reg[6]_26 ,
    \dReg_reg[7]_26 ,
    \dReg_reg[6]_27 ,
    \dReg_reg[7]_27 ,
    dReg_18,
    \dReg_reg[6]_28 ,
    dReg__0_19,
    dReg__1_20,
    dReg__2_21,
    dReg__3_22,
    dReg__4_23,
    dReg__5_24,
    dReg__6_25,
    dReg__7_26,
    \dReg_reg[7]_28 ,
    \dReg_reg[6]_29 ,
    \dReg_reg[7]_29 ,
    \dReg_reg[6]_30 ,
    \dReg_reg[7]_30 ,
    \dReg_reg[6]_31 ,
    \dReg_reg[7]_31 ,
    \dReg_reg[6]_32 ,
    \dReg_reg[7]_32 ,
    \dReg_reg[6]_33 ,
    \dReg_reg[7]_33 ,
    \dReg_reg[6]_34 ,
    \dReg_reg[7]_34 ,
    \dReg_reg[6]_35 ,
    \dReg_reg[7]_35 ,
    \dReg_reg[6]_36 ,
    \dReg_reg[7]_36 ,
    dReg_27,
    \dReg_reg[6]_37 ,
    dReg__0_28,
    dReg__1_29,
    dReg__2_30,
    dReg__3_31,
    dReg__4_32,
    dReg__5_33,
    dReg__6_34,
    dReg__7_35,
    \dReg_reg[7]_37 ,
    \dReg_reg[6]_38 ,
    \dReg_reg[7]_38 ,
    \dReg_reg[6]_39 ,
    \dReg_reg[7]_39 ,
    \dReg_reg[6]_40 ,
    \dReg_reg[7]_40 ,
    \dReg_reg[6]_41 ,
    \dReg_reg[7]_41 ,
    \dReg_reg[6]_42 ,
    \dReg_reg[7]_42 ,
    \dReg_reg[6]_43 ,
    \dReg_reg[7]_43 ,
    \dReg_reg[6]_44 ,
    \dReg_reg[7]_44 ,
    \dReg_reg[6]_45 ,
    \dReg_reg[7]_45 ,
    dReg_36,
    \dReg_reg[6]_46 ,
    dReg__0_37,
    dReg__1_38,
    dReg__2_39,
    dReg__3_40,
    dReg__4_41,
    dReg__5_42,
    dReg__6_43,
    dReg__7_44,
    \dReg_reg[7]_46 ,
    \dReg_reg[6]_47 ,
    \dReg_reg[7]_47 ,
    \dReg_reg[6]_48 ,
    \dReg_reg[7]_48 ,
    \dReg_reg[6]_49 ,
    \dReg_reg[7]_49 ,
    \dReg_reg[6]_50 ,
    \dReg_reg[7]_50 ,
    \dReg_reg[6]_51 ,
    \dReg_reg[7]_51 ,
    \dReg_reg[6]_52 ,
    \dReg_reg[7]_52 ,
    \dReg_reg[6]_53 ,
    \dReg_reg[7]_53 ,
    \dReg_reg[6]_54 ,
    \dReg_reg[7]_54 ,
    dReg_45,
    \dReg_reg[6]_55 ,
    dReg__0_46,
    dReg__1_47,
    dReg__2_48,
    dReg__3_49,
    dReg__4_50,
    dReg__5_51,
    dReg__6_52,
    dReg__7_53,
    \dReg_reg[7]_55 ,
    \dReg_reg[6]_56 ,
    \dReg_reg[7]_56 ,
    \dReg_reg[6]_57 ,
    \dReg_reg[7]_57 ,
    \dReg_reg[6]_58 ,
    \dReg_reg[7]_58 ,
    \dReg_reg[6]_59 ,
    \dReg_reg[7]_59 ,
    \dReg_reg[6]_60 ,
    \dReg_reg[7]_60 ,
    \dReg_reg[6]_61 ,
    \dReg_reg[7]_61 ,
    \dReg_reg[6]_62 ,
    \dReg_reg[7]_62 ,
    \dReg_reg[6]_63 ,
    \dReg_reg[7]_63 ,
    \dReg_reg[6]_64 ,
    dReg__0_2,
    dReg__1_3,
    dReg__2_4,
    dReg__3_5,
    dReg__4_6,
    dReg__5_7,
    dReg__6_8,
    dReg__7_9,
    \dReg_reg[7]_64 ,
    \dReg_reg[6]_65 ,
    \dReg_reg[7]_65 ,
    \dReg_reg[6]_66 ,
    \dReg_reg[7]_66 ,
    \dReg_reg[6]_67 ,
    \dReg_reg[7]_67 ,
    \dReg_reg[6]_68 ,
    \dReg_reg[7]_68 ,
    \dReg_reg[6]_69 ,
    \dReg_reg[7]_69 ,
    \dReg_reg[6]_70 ,
    \dReg_reg[7]_70 ,
    \dReg_reg[6]_71 ,
    \dReg_reg[7]_71 ,
    \dReg_reg[6]_72 ,
    \dReg_reg[9]_0 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_0 );
  output \wosp_reg[1]_0 ;
  output \wosp_reg[2]_0 ;
  output \wosp_reg[2]_rep_0 ;
  output \wosp_reg[2]_rep__0_0 ;
  output \wosp_reg[2]_rep__1_0 ;
  output \wosp_reg[2]_rep__2_0 ;
  output \wosp_reg[2]_rep__3_0 ;
  output \wosp_reg[2]_rep__4_0 ;
  output \wosp_reg[2]_rep__5_0 ;
  output \wosp_reg[2]_rep__6_0 ;
  output \wosp_reg[2]_rep__7_0 ;
  output wrDataVal_reg;
  output [8:0]D;
  output [7:0]\wosp_reg[1]_1 ;
  output [7:0]\wosp_reg[1]_2 ;
  output [7:0]\wosp_reg[1]_3 ;
  output [7:0]\wosp_reg[1]_4 ;
  output [7:0]\wosp_reg[1]_5 ;
  output [7:0]\wosp_reg[1]_6 ;
  output [7:0]\wosp_reg[1]_7 ;
  output [7:0]\wosp_reg[1]_8 ;
  output [8:0]\wosp_reg[1]_9 ;
  output [7:0]\wosp_reg[1]_10 ;
  output [7:0]\wosp_reg[1]_11 ;
  output [7:0]\wosp_reg[1]_12 ;
  output [7:0]\wosp_reg[1]_13 ;
  output [7:0]\wosp_reg[1]_14 ;
  output [7:0]\wosp_reg[1]_15 ;
  output [7:0]\wosp_reg[1]_16 ;
  output [7:0]\wosp_reg[1]_17 ;
  output [8:0]\wosp_reg[1]_18 ;
  output [7:0]\wosp_reg[1]_19 ;
  output [7:0]\wosp_reg[1]_20 ;
  output [7:0]\wosp_reg[1]_21 ;
  output [7:0]\wosp_reg[1]_22 ;
  output [7:0]\wosp_reg[1]_23 ;
  output [7:0]\wosp_reg[1]_24 ;
  output [7:0]\wosp_reg[1]_25 ;
  output [7:0]\wosp_reg[1]_26 ;
  output [8:0]\wosp_reg[1]_27 ;
  output [7:0]\wosp_reg[1]_28 ;
  output [7:0]\wosp_reg[1]_29 ;
  output [7:0]\wosp_reg[1]_30 ;
  output [7:0]\wosp_reg[1]_31 ;
  output [7:0]\wosp_reg[1]_32 ;
  output [7:0]\wosp_reg[1]_33 ;
  output [7:0]\wosp_reg[1]_34 ;
  output [7:0]\wosp_reg[1]_35 ;
  output [8:0]\wosp_reg[1]_36 ;
  output [7:0]\wosp_reg[1]_37 ;
  output [7:0]\wosp_reg[1]_38 ;
  output [7:0]\wosp_reg[1]_39 ;
  output [7:0]\wosp_reg[1]_40 ;
  output [7:0]\wosp_reg[1]_41 ;
  output [7:0]\wosp_reg[1]_42 ;
  output [7:0]\wosp_reg[1]_43 ;
  output [7:0]\wosp_reg[1]_44 ;
  output [8:0]\wosp_reg[1]_45 ;
  output [7:0]\wosp_reg[1]_46 ;
  output [7:0]\wosp_reg[1]_47 ;
  output [7:0]\wosp_reg[1]_48 ;
  output [7:0]\wosp_reg[1]_49 ;
  output [7:0]\wosp_reg[1]_50 ;
  output [7:0]\wosp_reg[1]_51 ;
  output [7:0]\wosp_reg[1]_52 ;
  output [7:0]\wosp_reg[1]_53 ;
  output [8:0]\wosp_reg[1]_54 ;
  output [7:0]\wosp_reg[1]_55 ;
  output [7:0]\wosp_reg[1]_56 ;
  output [7:0]\wosp_reg[1]_57 ;
  output [7:0]\wosp_reg[1]_58 ;
  output [7:0]\wosp_reg[1]_59 ;
  output [7:0]\wosp_reg[1]_60 ;
  output [7:0]\wosp_reg[1]_61 ;
  output [7:0]\wosp_reg[1]_62 ;
  output [7:0]\wosp_reg[1]_63 ;
  output [7:0]\wosp_reg[1]_64 ;
  output [7:0]\wosp_reg[1]_65 ;
  output [7:0]\wosp_reg[1]_66 ;
  output [7:0]\wosp_reg[1]_67 ;
  output [7:0]\wosp_reg[1]_68 ;
  output [7:0]\wosp_reg[1]_69 ;
  output [7:0]\wosp_reg[1]_70 ;
  output [7:0]ch0_mcal_DQOut;
  input \wosp_reg[1]_71 ;
  input \wosp_reg[2]_rep__7_1 ;
  input [0:0]sel;
  input \dReg_reg[6]_0 ;
  input [511:0]DQOut;
  input [63:0]DMOut;
  input \dReg_reg[7]_0 ;
  input [5:0]dReg;
  input \dReg_reg[6]_1 ;
  input [5:0]dReg__0;
  input [5:0]dReg__1;
  input [5:0]dReg__2;
  input [5:0]dReg__3;
  input [5:0]dReg__4;
  input [5:0]dReg__5;
  input [5:0]dReg__6;
  input [5:0]dReg__7;
  input \dReg_reg[7]_1 ;
  input \dReg_reg[6]_2 ;
  input \dReg_reg[7]_2 ;
  input \dReg_reg[6]_3 ;
  input \dReg_reg[7]_3 ;
  input \dReg_reg[6]_4 ;
  input \dReg_reg[7]_4 ;
  input \dReg_reg[6]_5 ;
  input \dReg_reg[7]_5 ;
  input \dReg_reg[6]_6 ;
  input \dReg_reg[7]_6 ;
  input \dReg_reg[6]_7 ;
  input \dReg_reg[7]_7 ;
  input \dReg_reg[6]_8 ;
  input \dReg_reg[7]_8 ;
  input \dReg_reg[6]_9 ;
  input \dReg_reg[7]_9 ;
  input [5:0]dReg_0;
  input \dReg_reg[6]_10 ;
  input [5:0]dReg__0_1;
  input [5:0]dReg__1_2;
  input [5:0]dReg__2_3;
  input [5:0]dReg__3_4;
  input [5:0]dReg__4_5;
  input [5:0]dReg__5_6;
  input [5:0]dReg__6_7;
  input [5:0]dReg__7_8;
  input \dReg_reg[7]_10 ;
  input \dReg_reg[6]_11 ;
  input \dReg_reg[7]_11 ;
  input \dReg_reg[6]_12 ;
  input \dReg_reg[7]_12 ;
  input \dReg_reg[6]_13 ;
  input \dReg_reg[7]_13 ;
  input \dReg_reg[6]_14 ;
  input \dReg_reg[7]_14 ;
  input \dReg_reg[6]_15 ;
  input \dReg_reg[7]_15 ;
  input \dReg_reg[6]_16 ;
  input \dReg_reg[7]_16 ;
  input \dReg_reg[6]_17 ;
  input \dReg_reg[7]_17 ;
  input \dReg_reg[6]_18 ;
  input \dReg_reg[7]_18 ;
  input [5:0]dReg_9;
  input \dReg_reg[6]_19 ;
  input [5:0]dReg__0_10;
  input [5:0]dReg__1_11;
  input [5:0]dReg__2_12;
  input [5:0]dReg__3_13;
  input [5:0]dReg__4_14;
  input [5:0]dReg__5_15;
  input [5:0]dReg__6_16;
  input [5:0]dReg__7_17;
  input \dReg_reg[7]_19 ;
  input \dReg_reg[6]_20 ;
  input \dReg_reg[7]_20 ;
  input \dReg_reg[6]_21 ;
  input \dReg_reg[7]_21 ;
  input \dReg_reg[6]_22 ;
  input \dReg_reg[7]_22 ;
  input \dReg_reg[6]_23 ;
  input \dReg_reg[7]_23 ;
  input \dReg_reg[6]_24 ;
  input \dReg_reg[7]_24 ;
  input \dReg_reg[6]_25 ;
  input \dReg_reg[7]_25 ;
  input \dReg_reg[6]_26 ;
  input \dReg_reg[7]_26 ;
  input \dReg_reg[6]_27 ;
  input \dReg_reg[7]_27 ;
  input [5:0]dReg_18;
  input \dReg_reg[6]_28 ;
  input [5:0]dReg__0_19;
  input [5:0]dReg__1_20;
  input [5:0]dReg__2_21;
  input [5:0]dReg__3_22;
  input [5:0]dReg__4_23;
  input [5:0]dReg__5_24;
  input [5:0]dReg__6_25;
  input [5:0]dReg__7_26;
  input \dReg_reg[7]_28 ;
  input \dReg_reg[6]_29 ;
  input \dReg_reg[7]_29 ;
  input \dReg_reg[6]_30 ;
  input \dReg_reg[7]_30 ;
  input \dReg_reg[6]_31 ;
  input \dReg_reg[7]_31 ;
  input \dReg_reg[6]_32 ;
  input \dReg_reg[7]_32 ;
  input \dReg_reg[6]_33 ;
  input \dReg_reg[7]_33 ;
  input \dReg_reg[6]_34 ;
  input \dReg_reg[7]_34 ;
  input \dReg_reg[6]_35 ;
  input \dReg_reg[7]_35 ;
  input \dReg_reg[6]_36 ;
  input \dReg_reg[7]_36 ;
  input [5:0]dReg_27;
  input \dReg_reg[6]_37 ;
  input [5:0]dReg__0_28;
  input [5:0]dReg__1_29;
  input [5:0]dReg__2_30;
  input [5:0]dReg__3_31;
  input [5:0]dReg__4_32;
  input [5:0]dReg__5_33;
  input [5:0]dReg__6_34;
  input [5:0]dReg__7_35;
  input \dReg_reg[7]_37 ;
  input \dReg_reg[6]_38 ;
  input \dReg_reg[7]_38 ;
  input \dReg_reg[6]_39 ;
  input \dReg_reg[7]_39 ;
  input \dReg_reg[6]_40 ;
  input \dReg_reg[7]_40 ;
  input \dReg_reg[6]_41 ;
  input \dReg_reg[7]_41 ;
  input \dReg_reg[6]_42 ;
  input \dReg_reg[7]_42 ;
  input \dReg_reg[6]_43 ;
  input \dReg_reg[7]_43 ;
  input \dReg_reg[6]_44 ;
  input \dReg_reg[7]_44 ;
  input \dReg_reg[6]_45 ;
  input \dReg_reg[7]_45 ;
  input [5:0]dReg_36;
  input \dReg_reg[6]_46 ;
  input [5:0]dReg__0_37;
  input [5:0]dReg__1_38;
  input [5:0]dReg__2_39;
  input [5:0]dReg__3_40;
  input [5:0]dReg__4_41;
  input [5:0]dReg__5_42;
  input [5:0]dReg__6_43;
  input [5:0]dReg__7_44;
  input \dReg_reg[7]_46 ;
  input \dReg_reg[6]_47 ;
  input \dReg_reg[7]_47 ;
  input \dReg_reg[6]_48 ;
  input \dReg_reg[7]_48 ;
  input \dReg_reg[6]_49 ;
  input \dReg_reg[7]_49 ;
  input \dReg_reg[6]_50 ;
  input \dReg_reg[7]_50 ;
  input \dReg_reg[6]_51 ;
  input \dReg_reg[7]_51 ;
  input \dReg_reg[6]_52 ;
  input \dReg_reg[7]_52 ;
  input \dReg_reg[6]_53 ;
  input \dReg_reg[7]_53 ;
  input \dReg_reg[6]_54 ;
  input \dReg_reg[7]_54 ;
  input [5:0]dReg_45;
  input \dReg_reg[6]_55 ;
  input [5:0]dReg__0_46;
  input [5:0]dReg__1_47;
  input [5:0]dReg__2_48;
  input [5:0]dReg__3_49;
  input [5:0]dReg__4_50;
  input [5:0]dReg__5_51;
  input [5:0]dReg__6_52;
  input [5:0]dReg__7_53;
  input \dReg_reg[7]_55 ;
  input \dReg_reg[6]_56 ;
  input \dReg_reg[7]_56 ;
  input \dReg_reg[6]_57 ;
  input \dReg_reg[7]_57 ;
  input \dReg_reg[6]_58 ;
  input \dReg_reg[7]_58 ;
  input \dReg_reg[6]_59 ;
  input \dReg_reg[7]_59 ;
  input \dReg_reg[6]_60 ;
  input \dReg_reg[7]_60 ;
  input \dReg_reg[6]_61 ;
  input \dReg_reg[7]_61 ;
  input \dReg_reg[6]_62 ;
  input \dReg_reg[7]_62 ;
  input \dReg_reg[6]_63 ;
  input \dReg_reg[7]_63 ;
  input \dReg_reg[6]_64 ;
  input [5:0]dReg__0_2;
  input [5:0]dReg__1_3;
  input [5:0]dReg__2_4;
  input [5:0]dReg__3_5;
  input [5:0]dReg__4_6;
  input [5:0]dReg__5_7;
  input [5:0]dReg__6_8;
  input [5:0]dReg__7_9;
  input \dReg_reg[7]_64 ;
  input \dReg_reg[6]_65 ;
  input \dReg_reg[7]_65 ;
  input \dReg_reg[6]_66 ;
  input \dReg_reg[7]_66 ;
  input \dReg_reg[6]_67 ;
  input \dReg_reg[7]_67 ;
  input \dReg_reg[6]_68 ;
  input \dReg_reg[7]_68 ;
  input \dReg_reg[6]_69 ;
  input \dReg_reg[7]_69 ;
  input \dReg_reg[6]_70 ;
  input \dReg_reg[7]_70 ;
  input \dReg_reg[6]_71 ;
  input \dReg_reg[7]_71 ;
  input \dReg_reg[6]_72 ;
  input [1:0]\dReg_reg[9]_0 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_0 ;

  wire [8:0]D;
  wire [63:0]DMOut;
  wire [511:0]DQOut;
  wire [7:0]ch0_mcal_DQOut;
  wire [5:0]dReg;
  wire [15:2]dReg0_out;
  wire [5:0]dReg_0;
  wire [15:8]dReg_1;
  wire [5:0]dReg_18;
  wire [5:0]dReg_27;
  wire [5:0]dReg_36;
  wire [5:0]dReg_45;
  wire [5:0]dReg_9;
  wire [5:0]dReg__0;
  wire [5:0]dReg__0_1;
  wire [5:0]dReg__0_10;
  wire [5:0]dReg__0_19;
  wire [5:0]dReg__0_2;
  wire [5:0]dReg__0_28;
  wire [5:0]dReg__0_37;
  wire [5:0]dReg__0_46;
  wire [5:0]dReg__1;
  wire [5:0]dReg__1_11;
  wire [5:0]dReg__1_2;
  wire [5:0]dReg__1_20;
  wire [5:0]dReg__1_29;
  wire [5:0]dReg__1_3;
  wire [5:0]dReg__1_38;
  wire [5:0]dReg__1_47;
  wire [5:0]dReg__2;
  wire [5:0]dReg__2_12;
  wire [5:0]dReg__2_21;
  wire [5:0]dReg__2_3;
  wire [5:0]dReg__2_30;
  wire [5:0]dReg__2_39;
  wire [5:0]dReg__2_4;
  wire [5:0]dReg__2_48;
  wire [5:0]dReg__3;
  wire [5:0]dReg__3_13;
  wire [5:0]dReg__3_22;
  wire [5:0]dReg__3_31;
  wire [5:0]dReg__3_4;
  wire [5:0]dReg__3_40;
  wire [5:0]dReg__3_49;
  wire [5:0]dReg__3_5;
  wire [5:0]dReg__4;
  wire [5:0]dReg__4_14;
  wire [5:0]dReg__4_23;
  wire [5:0]dReg__4_32;
  wire [5:0]dReg__4_41;
  wire [5:0]dReg__4_5;
  wire [5:0]dReg__4_50;
  wire [5:0]dReg__4_6;
  wire [5:0]dReg__5;
  wire [5:0]dReg__5_15;
  wire [5:0]dReg__5_24;
  wire [5:0]dReg__5_33;
  wire [5:0]dReg__5_42;
  wire [5:0]dReg__5_51;
  wire [5:0]dReg__5_6;
  wire [5:0]dReg__5_7;
  wire [5:0]dReg__6;
  wire [5:0]dReg__6_16;
  wire [5:0]dReg__6_25;
  wire [5:0]dReg__6_34;
  wire [5:0]dReg__6_43;
  wire [5:0]dReg__6_52;
  wire [5:0]dReg__6_7;
  wire [5:0]dReg__6_8;
  wire [5:0]dReg__7;
  wire [5:0]dReg__7_17;
  wire [5:0]dReg__7_26;
  wire [5:0]dReg__7_35;
  wire [5:0]dReg__7_44;
  wire [5:0]dReg__7_53;
  wire [5:0]dReg__7_8;
  wire [5:0]dReg__7_9;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire \dReg_reg[6]_0 ;
  wire \dReg_reg[6]_1 ;
  wire \dReg_reg[6]_10 ;
  wire \dReg_reg[6]_11 ;
  wire \dReg_reg[6]_12 ;
  wire \dReg_reg[6]_13 ;
  wire \dReg_reg[6]_14 ;
  wire \dReg_reg[6]_15 ;
  wire \dReg_reg[6]_16 ;
  wire \dReg_reg[6]_17 ;
  wire \dReg_reg[6]_18 ;
  wire \dReg_reg[6]_19 ;
  wire \dReg_reg[6]_2 ;
  wire \dReg_reg[6]_20 ;
  wire \dReg_reg[6]_21 ;
  wire \dReg_reg[6]_22 ;
  wire \dReg_reg[6]_23 ;
  wire \dReg_reg[6]_24 ;
  wire \dReg_reg[6]_25 ;
  wire \dReg_reg[6]_26 ;
  wire \dReg_reg[6]_27 ;
  wire \dReg_reg[6]_28 ;
  wire \dReg_reg[6]_29 ;
  wire \dReg_reg[6]_3 ;
  wire \dReg_reg[6]_30 ;
  wire \dReg_reg[6]_31 ;
  wire \dReg_reg[6]_32 ;
  wire \dReg_reg[6]_33 ;
  wire \dReg_reg[6]_34 ;
  wire \dReg_reg[6]_35 ;
  wire \dReg_reg[6]_36 ;
  wire \dReg_reg[6]_37 ;
  wire \dReg_reg[6]_38 ;
  wire \dReg_reg[6]_39 ;
  wire \dReg_reg[6]_4 ;
  wire \dReg_reg[6]_40 ;
  wire \dReg_reg[6]_41 ;
  wire \dReg_reg[6]_42 ;
  wire \dReg_reg[6]_43 ;
  wire \dReg_reg[6]_44 ;
  wire \dReg_reg[6]_45 ;
  wire \dReg_reg[6]_46 ;
  wire \dReg_reg[6]_47 ;
  wire \dReg_reg[6]_48 ;
  wire \dReg_reg[6]_49 ;
  wire \dReg_reg[6]_5 ;
  wire \dReg_reg[6]_50 ;
  wire \dReg_reg[6]_51 ;
  wire \dReg_reg[6]_52 ;
  wire \dReg_reg[6]_53 ;
  wire \dReg_reg[6]_54 ;
  wire \dReg_reg[6]_55 ;
  wire \dReg_reg[6]_56 ;
  wire \dReg_reg[6]_57 ;
  wire \dReg_reg[6]_58 ;
  wire \dReg_reg[6]_59 ;
  wire \dReg_reg[6]_6 ;
  wire \dReg_reg[6]_60 ;
  wire \dReg_reg[6]_61 ;
  wire \dReg_reg[6]_62 ;
  wire \dReg_reg[6]_63 ;
  wire \dReg_reg[6]_64 ;
  wire \dReg_reg[6]_65 ;
  wire \dReg_reg[6]_66 ;
  wire \dReg_reg[6]_67 ;
  wire \dReg_reg[6]_68 ;
  wire \dReg_reg[6]_69 ;
  wire \dReg_reg[6]_7 ;
  wire \dReg_reg[6]_70 ;
  wire \dReg_reg[6]_71 ;
  wire \dReg_reg[6]_72 ;
  wire \dReg_reg[6]_8 ;
  wire \dReg_reg[6]_9 ;
  wire \dReg_reg[7]_0 ;
  wire \dReg_reg[7]_1 ;
  wire \dReg_reg[7]_10 ;
  wire \dReg_reg[7]_11 ;
  wire \dReg_reg[7]_12 ;
  wire \dReg_reg[7]_13 ;
  wire \dReg_reg[7]_14 ;
  wire \dReg_reg[7]_15 ;
  wire \dReg_reg[7]_16 ;
  wire \dReg_reg[7]_17 ;
  wire \dReg_reg[7]_18 ;
  wire \dReg_reg[7]_19 ;
  wire \dReg_reg[7]_2 ;
  wire \dReg_reg[7]_20 ;
  wire \dReg_reg[7]_21 ;
  wire \dReg_reg[7]_22 ;
  wire \dReg_reg[7]_23 ;
  wire \dReg_reg[7]_24 ;
  wire \dReg_reg[7]_25 ;
  wire \dReg_reg[7]_26 ;
  wire \dReg_reg[7]_27 ;
  wire \dReg_reg[7]_28 ;
  wire \dReg_reg[7]_29 ;
  wire \dReg_reg[7]_3 ;
  wire \dReg_reg[7]_30 ;
  wire \dReg_reg[7]_31 ;
  wire \dReg_reg[7]_32 ;
  wire \dReg_reg[7]_33 ;
  wire \dReg_reg[7]_34 ;
  wire \dReg_reg[7]_35 ;
  wire \dReg_reg[7]_36 ;
  wire \dReg_reg[7]_37 ;
  wire \dReg_reg[7]_38 ;
  wire \dReg_reg[7]_39 ;
  wire \dReg_reg[7]_4 ;
  wire \dReg_reg[7]_40 ;
  wire \dReg_reg[7]_41 ;
  wire \dReg_reg[7]_42 ;
  wire \dReg_reg[7]_43 ;
  wire \dReg_reg[7]_44 ;
  wire \dReg_reg[7]_45 ;
  wire \dReg_reg[7]_46 ;
  wire \dReg_reg[7]_47 ;
  wire \dReg_reg[7]_48 ;
  wire \dReg_reg[7]_49 ;
  wire \dReg_reg[7]_5 ;
  wire \dReg_reg[7]_50 ;
  wire \dReg_reg[7]_51 ;
  wire \dReg_reg[7]_52 ;
  wire \dReg_reg[7]_53 ;
  wire \dReg_reg[7]_54 ;
  wire \dReg_reg[7]_55 ;
  wire \dReg_reg[7]_56 ;
  wire \dReg_reg[7]_57 ;
  wire \dReg_reg[7]_58 ;
  wire \dReg_reg[7]_59 ;
  wire \dReg_reg[7]_6 ;
  wire \dReg_reg[7]_60 ;
  wire \dReg_reg[7]_61 ;
  wire \dReg_reg[7]_62 ;
  wire \dReg_reg[7]_63 ;
  wire \dReg_reg[7]_64 ;
  wire \dReg_reg[7]_65 ;
  wire \dReg_reg[7]_66 ;
  wire \dReg_reg[7]_67 ;
  wire \dReg_reg[7]_68 ;
  wire \dReg_reg[7]_69 ;
  wire \dReg_reg[7]_7 ;
  wire \dReg_reg[7]_70 ;
  wire \dReg_reg[7]_71 ;
  wire \dReg_reg[7]_8 ;
  wire \dReg_reg[7]_9 ;
  wire [1:0]\dReg_reg[9]_0 ;
  wire [0:0]sel;
  wire \wosp_reg[1]_0 ;
  wire [7:0]\wosp_reg[1]_1 ;
  wire [7:0]\wosp_reg[1]_10 ;
  wire [7:0]\wosp_reg[1]_11 ;
  wire [7:0]\wosp_reg[1]_12 ;
  wire [7:0]\wosp_reg[1]_13 ;
  wire [7:0]\wosp_reg[1]_14 ;
  wire [7:0]\wosp_reg[1]_15 ;
  wire [7:0]\wosp_reg[1]_16 ;
  wire [7:0]\wosp_reg[1]_17 ;
  wire [8:0]\wosp_reg[1]_18 ;
  wire [7:0]\wosp_reg[1]_19 ;
  wire [7:0]\wosp_reg[1]_2 ;
  wire [7:0]\wosp_reg[1]_20 ;
  wire [7:0]\wosp_reg[1]_21 ;
  wire [7:0]\wosp_reg[1]_22 ;
  wire [7:0]\wosp_reg[1]_23 ;
  wire [7:0]\wosp_reg[1]_24 ;
  wire [7:0]\wosp_reg[1]_25 ;
  wire [7:0]\wosp_reg[1]_26 ;
  wire [8:0]\wosp_reg[1]_27 ;
  wire [7:0]\wosp_reg[1]_28 ;
  wire [7:0]\wosp_reg[1]_29 ;
  wire [7:0]\wosp_reg[1]_3 ;
  wire [7:0]\wosp_reg[1]_30 ;
  wire [7:0]\wosp_reg[1]_31 ;
  wire [7:0]\wosp_reg[1]_32 ;
  wire [7:0]\wosp_reg[1]_33 ;
  wire [7:0]\wosp_reg[1]_34 ;
  wire [7:0]\wosp_reg[1]_35 ;
  wire [8:0]\wosp_reg[1]_36 ;
  wire [7:0]\wosp_reg[1]_37 ;
  wire [7:0]\wosp_reg[1]_38 ;
  wire [7:0]\wosp_reg[1]_39 ;
  wire [7:0]\wosp_reg[1]_4 ;
  wire [7:0]\wosp_reg[1]_40 ;
  wire [7:0]\wosp_reg[1]_41 ;
  wire [7:0]\wosp_reg[1]_42 ;
  wire [7:0]\wosp_reg[1]_43 ;
  wire [7:0]\wosp_reg[1]_44 ;
  wire [8:0]\wosp_reg[1]_45 ;
  wire [7:0]\wosp_reg[1]_46 ;
  wire [7:0]\wosp_reg[1]_47 ;
  wire [7:0]\wosp_reg[1]_48 ;
  wire [7:0]\wosp_reg[1]_49 ;
  wire [7:0]\wosp_reg[1]_5 ;
  wire [7:0]\wosp_reg[1]_50 ;
  wire [7:0]\wosp_reg[1]_51 ;
  wire [7:0]\wosp_reg[1]_52 ;
  wire [7:0]\wosp_reg[1]_53 ;
  wire [8:0]\wosp_reg[1]_54 ;
  wire [7:0]\wosp_reg[1]_55 ;
  wire [7:0]\wosp_reg[1]_56 ;
  wire [7:0]\wosp_reg[1]_57 ;
  wire [7:0]\wosp_reg[1]_58 ;
  wire [7:0]\wosp_reg[1]_59 ;
  wire [7:0]\wosp_reg[1]_6 ;
  wire [7:0]\wosp_reg[1]_60 ;
  wire [7:0]\wosp_reg[1]_61 ;
  wire [7:0]\wosp_reg[1]_62 ;
  wire [7:0]\wosp_reg[1]_63 ;
  wire [7:0]\wosp_reg[1]_64 ;
  wire [7:0]\wosp_reg[1]_65 ;
  wire [7:0]\wosp_reg[1]_66 ;
  wire [7:0]\wosp_reg[1]_67 ;
  wire [7:0]\wosp_reg[1]_68 ;
  wire [7:0]\wosp_reg[1]_69 ;
  wire [7:0]\wosp_reg[1]_7 ;
  wire [7:0]\wosp_reg[1]_70 ;
  wire \wosp_reg[1]_71 ;
  wire [7:0]\wosp_reg[1]_8 ;
  wire [8:0]\wosp_reg[1]_9 ;
  wire \wosp_reg[2]_0 ;
  wire \wosp_reg[2]_rep_0 ;
  wire \wosp_reg[2]_rep__0_0 ;
  wire \wosp_reg[2]_rep__1_0 ;
  wire \wosp_reg[2]_rep__2_0 ;
  wire \wosp_reg[2]_rep__3_0 ;
  wire \wosp_reg[2]_rep__4_0 ;
  wire \wosp_reg[2]_rep__5_0 ;
  wire \wosp_reg[2]_rep__6_0 ;
  wire \wosp_reg[2]_rep__7_0 ;
  wire \wosp_reg[2]_rep__7_1 ;
  wire wrDataVal_reg;

  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1 
       (.I0(DMOut[6]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[4]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_1 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__0 
       (.I0(DQOut[62]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[60]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_2 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__1 
       (.I0(DQOut[52]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[54]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_3 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__10 
       (.I0(DQOut[116]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[118]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_12 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__11 
       (.I0(DQOut[110]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[108]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_13 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__12 
       (.I0(DQOut[100]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[102]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_14 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__13 
       (.I0(DQOut[94]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[92]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_15 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__14 
       (.I0(DQOut[86]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[84]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_16 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__15 
       (.I0(DQOut[78]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[76]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_17 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__16 
       (.I0(DQOut[68]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[70]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_9 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__17 
       (.I0(DMOut[22]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[20]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_19 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__18 
       (.I0(DQOut[190]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[188]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_20 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__19 
       (.I0(DQOut[180]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[182]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_21 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__2 
       (.I0(DQOut[46]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[44]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_4 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__20 
       (.I0(DQOut[174]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[172]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_22 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__21 
       (.I0(DQOut[164]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[166]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_23 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__22 
       (.I0(DQOut[158]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[156]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_24 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__23 
       (.I0(DQOut[150]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[148]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_25 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__24 
       (.I0(DQOut[142]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[140]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_26 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__25 
       (.I0(DQOut[132]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[134]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_18 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__26 
       (.I0(DMOut[30]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[28]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_28 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__27 
       (.I0(DQOut[254]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[252]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_29 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__28 
       (.I0(DQOut[244]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[246]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_30 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__29 
       (.I0(DQOut[238]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[236]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_31 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__3 
       (.I0(DQOut[36]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[38]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_5 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__30 
       (.I0(DQOut[228]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[230]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_32 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__31 
       (.I0(DQOut[222]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[220]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_33 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__32 
       (.I0(DQOut[214]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[212]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_34 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__33 
       (.I0(DQOut[206]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[204]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_35 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__34 
       (.I0(DQOut[196]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[198]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_27 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__35 
       (.I0(DMOut[38]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[36]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_37 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__36 
       (.I0(DQOut[318]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[316]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_38 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__37 
       (.I0(DQOut[308]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[310]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_39 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__38 
       (.I0(DQOut[302]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[300]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_40 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__39 
       (.I0(DQOut[292]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[294]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_41 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__4 
       (.I0(DQOut[30]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[28]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_6 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__40 
       (.I0(DQOut[286]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[284]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_42 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__41 
       (.I0(DQOut[278]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[276]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_43 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__42 
       (.I0(DQOut[270]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[268]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_44 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__43 
       (.I0(DQOut[260]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[262]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_36 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__44 
       (.I0(DMOut[46]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[44]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_46 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__45 
       (.I0(DQOut[382]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[380]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_47 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__46 
       (.I0(DQOut[372]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[374]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_48 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__47 
       (.I0(DQOut[366]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[364]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_49 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__48 
       (.I0(DQOut[356]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[358]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_50 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__49 
       (.I0(DQOut[350]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[348]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_51 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__5 
       (.I0(DQOut[22]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[20]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_7 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__50 
       (.I0(DQOut[342]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[340]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_52 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__51 
       (.I0(DQOut[334]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[332]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_53 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__52 
       (.I0(DQOut[324]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[326]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_45 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__53 
       (.I0(DMOut[54]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[52]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_55 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__54 
       (.I0(DQOut[446]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[444]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_56 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__55 
       (.I0(DQOut[436]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[438]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_57 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__56 
       (.I0(DQOut[430]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[428]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_58 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__57 
       (.I0(DQOut[420]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[422]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_59 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__58 
       (.I0(DQOut[414]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[412]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_60 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__59 
       (.I0(DQOut[406]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[404]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_61 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__6 
       (.I0(DQOut[14]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[12]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_8 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__60 
       (.I0(DQOut[398]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[396]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_62 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__61 
       (.I0(DQOut[388]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[390]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_54 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__62 
       (.I0(DMOut[62]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[60]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_63 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__63 
       (.I0(DQOut[510]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[508]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_64 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__64 
       (.I0(DQOut[500]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[502]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_65 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__65 
       (.I0(DQOut[494]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[492]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_66 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__66 
       (.I0(DQOut[484]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[486]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_67 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__67 
       (.I0(DQOut[478]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[476]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_68 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__68 
       (.I0(DQOut[470]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[468]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_69 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__69 
       (.I0(DQOut[462]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[460]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_70 [6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__7 
       (.I0(DQOut[4]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[6]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(D[6]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[12]_i_1__70 
       (.I0(DQOut[452]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[454]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(dReg0_out[12]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__8 
       (.I0(DMOut[14]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[12]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_10 [6]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[12]_i_1__9 
       (.I0(DQOut[126]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[124]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_11 [6]));
  (* SOFT_HLUTNM = "soft_lutpair2481" *) 
  LUT5 #(
    .INIT(32'h80C08000)) 
    \dReg[13]_i_1 
       (.I0(DQOut[5]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[7]),
        .O(D[7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__0 
       (.I0(DMOut[5]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[7]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_1 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__1 
       (.I0(DQOut[63]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[61]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_2 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__10 
       (.I0(DQOut[127]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[125]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_11 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__11 
       (.I0(DQOut[119]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[117]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_12 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__12 
       (.I0(DQOut[111]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[109]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_13 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__13 
       (.I0(DQOut[101]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[103]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_14 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__14 
       (.I0(DQOut[95]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[93]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_15 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__15 
       (.I0(DQOut[87]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[85]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_16 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__16 
       (.I0(DQOut[79]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[77]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_17 [7]));
  LUT5 #(
    .INIT(32'h80C08000)) 
    \dReg[13]_i_1__17 
       (.I0(DQOut[133]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[135]),
        .O(\wosp_reg[1]_18 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__18 
       (.I0(DMOut[21]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[23]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_19 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__19 
       (.I0(DQOut[191]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[189]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_20 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__2 
       (.I0(DQOut[55]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[53]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_3 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__20 
       (.I0(DQOut[183]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[181]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_21 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__21 
       (.I0(DQOut[175]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[173]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_22 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__22 
       (.I0(DQOut[165]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[167]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_23 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__23 
       (.I0(DQOut[159]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[157]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_24 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__24 
       (.I0(DQOut[151]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[149]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_25 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__25 
       (.I0(DQOut[143]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[141]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_26 [7]));
  (* SOFT_HLUTNM = "soft_lutpair2483" *) 
  LUT5 #(
    .INIT(32'h80C08000)) 
    \dReg[13]_i_1__26 
       (.I0(DQOut[197]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[199]),
        .O(\wosp_reg[1]_27 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__27 
       (.I0(DMOut[29]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[31]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_28 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__28 
       (.I0(DQOut[255]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[253]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_29 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__29 
       (.I0(DQOut[247]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[245]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_30 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__3 
       (.I0(DQOut[47]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[45]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_4 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__30 
       (.I0(DQOut[239]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[237]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_31 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__31 
       (.I0(DQOut[229]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[231]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_32 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__32 
       (.I0(DQOut[223]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[221]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_33 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__33 
       (.I0(DQOut[215]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[213]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_34 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__34 
       (.I0(DQOut[207]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[205]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_35 [7]));
  (* SOFT_HLUTNM = "soft_lutpair2484" *) 
  LUT5 #(
    .INIT(32'h80C08000)) 
    \dReg[13]_i_1__35 
       (.I0(DQOut[261]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[263]),
        .O(\wosp_reg[1]_36 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__36 
       (.I0(DMOut[37]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[39]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_37 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__37 
       (.I0(DQOut[319]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[317]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_38 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__38 
       (.I0(DQOut[311]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[309]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_39 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__39 
       (.I0(DQOut[303]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[301]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_40 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__4 
       (.I0(DQOut[37]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[39]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_5 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__40 
       (.I0(DQOut[293]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[295]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_41 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__41 
       (.I0(DQOut[287]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[285]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_42 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__42 
       (.I0(DQOut[279]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[277]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_43 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__43 
       (.I0(DQOut[271]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[269]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_44 [7]));
  LUT5 #(
    .INIT(32'h80C08000)) 
    \dReg[13]_i_1__44 
       (.I0(DQOut[325]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[327]),
        .O(\wosp_reg[1]_45 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__45 
       (.I0(DMOut[45]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[47]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_46 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__46 
       (.I0(DQOut[383]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[381]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_47 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__47 
       (.I0(DQOut[375]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[373]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_48 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__48 
       (.I0(DQOut[367]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[365]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_49 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__49 
       (.I0(DQOut[357]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[359]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_50 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__5 
       (.I0(DQOut[31]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[29]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_6 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__50 
       (.I0(DQOut[351]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[349]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_51 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__51 
       (.I0(DQOut[343]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[341]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_52 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__52 
       (.I0(DQOut[335]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[333]),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_53 [7]));
  (* SOFT_HLUTNM = "soft_lutpair2485" *) 
  LUT5 #(
    .INIT(32'h80C08000)) 
    \dReg[13]_i_1__53 
       (.I0(DQOut[389]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[391]),
        .O(\wosp_reg[1]_54 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__54 
       (.I0(DMOut[53]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[55]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_55 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__55 
       (.I0(DQOut[447]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[445]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_56 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__56 
       (.I0(DQOut[439]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[437]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_57 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__57 
       (.I0(DQOut[431]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[429]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_58 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__58 
       (.I0(DQOut[421]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[423]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_59 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__59 
       (.I0(DQOut[415]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[413]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_60 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__6 
       (.I0(DQOut[23]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[21]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_7 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__60 
       (.I0(DQOut[407]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[405]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_61 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__61 
       (.I0(DQOut[399]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[397]),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_62 [7]));
  (* SOFT_HLUTNM = "soft_lutpair2486" *) 
  LUT5 #(
    .INIT(32'h80C08000)) 
    \dReg[13]_i_1__62 
       (.I0(DQOut[453]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[455]),
        .O(dReg0_out[13]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__63 
       (.I0(DMOut[61]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[63]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_63 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__64 
       (.I0(DQOut[511]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[509]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_64 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__65 
       (.I0(DQOut[503]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[501]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_65 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__66 
       (.I0(DQOut[495]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[493]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_66 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__67 
       (.I0(DQOut[485]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[487]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_67 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__68 
       (.I0(DQOut[479]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[477]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_68 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__69 
       (.I0(DQOut[471]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[469]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_69 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__7 
       (.I0(DQOut[15]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[13]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_8 [7]));
  LUT5 #(
    .INIT(32'hE2000000)) 
    \dReg[13]_i_1__70 
       (.I0(DQOut[463]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[461]),
        .I3(\wosp_reg[2]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_70 [7]));
  (* SOFT_HLUTNM = "soft_lutpair2482" *) 
  LUT5 #(
    .INIT(32'h80C08000)) 
    \dReg[13]_i_1__8 
       (.I0(DQOut[69]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[71]),
        .O(\wosp_reg[1]_9 [7]));
  LUT5 #(
    .INIT(32'hB8000000)) 
    \dReg[13]_i_1__9 
       (.I0(DMOut[13]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DMOut[15]),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_10 [7]));
  LUT3 #(
    .INIT(8'h7F)) 
    \dReg[14]_i_1 
       (.I0(\dReg_reg[6]_0 ),
        .I1(\wosp_reg[2]_rep__1_0 ),
        .I2(\wosp_reg[1]_0 ),
        .O(wrDataVal_reg));
  (* SOFT_HLUTNM = "soft_lutpair2481" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \dReg[15]_i_1 
       (.I0(\wosp_reg[1]_0 ),
        .I1(DQOut[7]),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(\dReg_reg[6]_0 ),
        .O(D[8]));
  (* SOFT_HLUTNM = "soft_lutpair2482" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \dReg[15]_i_1__0 
       (.I0(\wosp_reg[1]_0 ),
        .I1(DQOut[71]),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_9 [8]));
  LUT4 #(
    .INIT(16'h8000)) 
    \dReg[15]_i_1__1 
       (.I0(\wosp_reg[1]_0 ),
        .I1(DQOut[135]),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_18 [8]));
  (* SOFT_HLUTNM = "soft_lutpair2483" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \dReg[15]_i_1__2 
       (.I0(\wosp_reg[1]_0 ),
        .I1(DQOut[199]),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_27 [8]));
  (* SOFT_HLUTNM = "soft_lutpair2484" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \dReg[15]_i_1__3 
       (.I0(\wosp_reg[1]_0 ),
        .I1(DQOut[263]),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_36 [8]));
  LUT4 #(
    .INIT(16'h8000)) 
    \dReg[15]_i_1__4 
       (.I0(\wosp_reg[1]_0 ),
        .I1(DQOut[327]),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_45 [8]));
  (* SOFT_HLUTNM = "soft_lutpair2485" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \dReg[15]_i_1__5 
       (.I0(\wosp_reg[1]_0 ),
        .I1(DQOut[391]),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_54 [8]));
  (* SOFT_HLUTNM = "soft_lutpair2486" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \dReg[15]_i_1__6 
       (.I0(\wosp_reg[1]_0 ),
        .I1(DQOut[455]),
        .I2(\wosp_reg[2]_0 ),
        .I3(\dReg_reg[6]_0 ),
        .O(dReg0_out[15]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1 
       (.I0(DQOut[0]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(dReg[0]),
        .O(D[0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__0 
       (.I0(DQOut[8]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__0[0]),
        .O(\wosp_reg[1]_8 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__1 
       (.I0(DQOut[16]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__1[0]),
        .O(\wosp_reg[1]_7 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__10 
       (.I0(DQOut[80]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__1_2[0]),
        .O(\wosp_reg[1]_16 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__11 
       (.I0(DQOut[88]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__2_3[0]),
        .O(\wosp_reg[1]_15 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__12 
       (.I0(DQOut[96]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__3_4[0]),
        .O(\wosp_reg[1]_14 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__13 
       (.I0(DQOut[104]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__4_5[0]),
        .O(\wosp_reg[1]_13 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__14 
       (.I0(DQOut[112]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__5_6[0]),
        .O(\wosp_reg[1]_12 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__15 
       (.I0(DQOut[120]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__6_7[0]),
        .O(\wosp_reg[1]_11 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__16 
       (.I0(DMOut[8]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__7_8[0]),
        .O(\wosp_reg[1]_10 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__17 
       (.I0(DQOut[128]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(dReg_9[0]),
        .O(\wosp_reg[1]_18 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__18 
       (.I0(DQOut[136]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__0_10[0]),
        .O(\wosp_reg[1]_26 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__19 
       (.I0(DQOut[144]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__1_11[0]),
        .O(\wosp_reg[1]_25 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__2 
       (.I0(DQOut[24]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__2[0]),
        .O(\wosp_reg[1]_6 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__20 
       (.I0(DQOut[152]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__2_12[0]),
        .O(\wosp_reg[1]_24 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__21 
       (.I0(DQOut[160]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__3_13[0]),
        .O(\wosp_reg[1]_23 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__22 
       (.I0(DQOut[168]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__4_14[0]),
        .O(\wosp_reg[1]_22 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__23 
       (.I0(DQOut[176]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__5_15[0]),
        .O(\wosp_reg[1]_21 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__24 
       (.I0(DQOut[184]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__6_16[0]),
        .O(\wosp_reg[1]_20 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__25 
       (.I0(DMOut[16]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__7_17[0]),
        .O(\wosp_reg[1]_19 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__26 
       (.I0(DQOut[192]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(dReg_18[0]),
        .O(\wosp_reg[1]_27 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__27 
       (.I0(DQOut[200]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__0_19[0]),
        .O(\wosp_reg[1]_35 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__28 
       (.I0(DQOut[208]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__1_20[0]),
        .O(\wosp_reg[1]_34 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__29 
       (.I0(DQOut[216]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__2_21[0]),
        .O(\wosp_reg[1]_33 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__3 
       (.I0(DQOut[32]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__3[0]),
        .O(\wosp_reg[1]_5 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__30 
       (.I0(DQOut[224]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__3_22[0]),
        .O(\wosp_reg[1]_32 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__31 
       (.I0(DQOut[232]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__4_23[0]),
        .O(\wosp_reg[1]_31 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__32 
       (.I0(DQOut[240]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__5_24[0]),
        .O(\wosp_reg[1]_30 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__33 
       (.I0(DQOut[248]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__6_25[0]),
        .O(\wosp_reg[1]_29 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__34 
       (.I0(DMOut[24]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__7_26[0]),
        .O(\wosp_reg[1]_28 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__35 
       (.I0(DQOut[256]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(dReg_27[0]),
        .O(\wosp_reg[1]_36 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__36 
       (.I0(DQOut[264]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__0_28[0]),
        .O(\wosp_reg[1]_44 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__37 
       (.I0(DQOut[272]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__1_29[0]),
        .O(\wosp_reg[1]_43 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__38 
       (.I0(DQOut[280]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__2_30[0]),
        .O(\wosp_reg[1]_42 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__39 
       (.I0(DQOut[288]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__3_31[0]),
        .O(\wosp_reg[1]_41 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__4 
       (.I0(DQOut[40]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(dReg__4[0]),
        .O(\wosp_reg[1]_4 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__40 
       (.I0(DQOut[296]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__4_32[0]),
        .O(\wosp_reg[1]_40 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__41 
       (.I0(DQOut[304]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__5_33[0]),
        .O(\wosp_reg[1]_39 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__42 
       (.I0(DQOut[312]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__6_34[0]),
        .O(\wosp_reg[1]_38 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__43 
       (.I0(DMOut[32]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__7_35[0]),
        .O(\wosp_reg[1]_37 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__44 
       (.I0(DQOut[320]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(dReg_36[0]),
        .O(\wosp_reg[1]_45 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__45 
       (.I0(DQOut[328]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__0_37[0]),
        .O(\wosp_reg[1]_53 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__46 
       (.I0(DQOut[336]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__1_38[0]),
        .O(\wosp_reg[1]_52 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__47 
       (.I0(DQOut[344]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__2_39[0]),
        .O(\wosp_reg[1]_51 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__48 
       (.I0(DQOut[352]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__3_40[0]),
        .O(\wosp_reg[1]_50 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__49 
       (.I0(DQOut[360]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__4_41[0]),
        .O(\wosp_reg[1]_49 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__5 
       (.I0(DQOut[48]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(dReg__5[0]),
        .O(\wosp_reg[1]_3 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__50 
       (.I0(DQOut[368]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__5_42[0]),
        .O(\wosp_reg[1]_48 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__51 
       (.I0(DQOut[376]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__6_43[0]),
        .O(\wosp_reg[1]_47 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__52 
       (.I0(DMOut[40]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__7_44[0]),
        .O(\wosp_reg[1]_46 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__53 
       (.I0(DQOut[384]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(dReg_45[0]),
        .O(\wosp_reg[1]_54 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__54 
       (.I0(DQOut[392]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__0_46[0]),
        .O(\wosp_reg[1]_62 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__55 
       (.I0(DQOut[400]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__1_47[0]),
        .O(\wosp_reg[1]_61 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__56 
       (.I0(DQOut[408]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__2_48[0]),
        .O(\wosp_reg[1]_60 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__57 
       (.I0(DQOut[416]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__3_49[0]),
        .O(\wosp_reg[1]_59 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__58 
       (.I0(DQOut[424]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__4_50[0]),
        .O(\wosp_reg[1]_58 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__59 
       (.I0(DQOut[432]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__5_51[0]),
        .O(\wosp_reg[1]_57 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__6 
       (.I0(DQOut[56]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(dReg__6[0]),
        .O(\wosp_reg[1]_2 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__60 
       (.I0(DQOut[440]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__6_52[0]),
        .O(\wosp_reg[1]_56 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__61 
       (.I0(DMOut[48]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__7_53[0]),
        .O(\wosp_reg[1]_55 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__62 
       (.I0(DQOut[448]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg_1[10]),
        .O(dReg0_out[2]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__63 
       (.I0(DQOut[456]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__0_2[0]),
        .O(\wosp_reg[1]_70 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__64 
       (.I0(DQOut[464]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__1_3[0]),
        .O(\wosp_reg[1]_69 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__65 
       (.I0(DQOut[472]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__2_4[0]),
        .O(\wosp_reg[1]_68 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__66 
       (.I0(DQOut[480]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__3_5[0]),
        .O(\wosp_reg[1]_67 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__67 
       (.I0(DQOut[488]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__4_6[0]),
        .O(\wosp_reg[1]_66 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__68 
       (.I0(DQOut[496]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__5_7[0]),
        .O(\wosp_reg[1]_65 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__69 
       (.I0(DQOut[504]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__6_8[0]),
        .O(\wosp_reg[1]_64 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__7 
       (.I0(DMOut[0]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(dReg__7[0]),
        .O(\wosp_reg[1]_1 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__70 
       (.I0(DMOut[56]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__7_9[0]),
        .O(\wosp_reg[1]_63 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__8 
       (.I0(DQOut[64]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(dReg_0[0]),
        .O(\wosp_reg[1]_9 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[2]_i_1__9 
       (.I0(DQOut[72]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__0_1[0]),
        .O(\wosp_reg[1]_17 [0]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1 
       (.I0(DQOut[1]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(dReg[1]),
        .O(D[1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__0 
       (.I0(DQOut[9]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__0[1]),
        .O(\wosp_reg[1]_8 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__1 
       (.I0(DQOut[17]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__1[1]),
        .O(\wosp_reg[1]_7 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__10 
       (.I0(DQOut[81]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__1_2[1]),
        .O(\wosp_reg[1]_16 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__11 
       (.I0(DQOut[89]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__2_3[1]),
        .O(\wosp_reg[1]_15 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__12 
       (.I0(DQOut[97]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__3_4[1]),
        .O(\wosp_reg[1]_14 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__13 
       (.I0(DQOut[105]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__4_5[1]),
        .O(\wosp_reg[1]_13 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__14 
       (.I0(DQOut[113]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__5_6[1]),
        .O(\wosp_reg[1]_12 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__15 
       (.I0(DQOut[121]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__6_7[1]),
        .O(\wosp_reg[1]_11 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__16 
       (.I0(DMOut[9]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__7_8[1]),
        .O(\wosp_reg[1]_10 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__17 
       (.I0(DQOut[129]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(dReg_9[1]),
        .O(\wosp_reg[1]_18 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__18 
       (.I0(DQOut[137]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__0_10[1]),
        .O(\wosp_reg[1]_26 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__19 
       (.I0(DQOut[145]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__1_11[1]),
        .O(\wosp_reg[1]_25 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__2 
       (.I0(DQOut[25]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__2[1]),
        .O(\wosp_reg[1]_6 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__20 
       (.I0(DQOut[153]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__2_12[1]),
        .O(\wosp_reg[1]_24 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__21 
       (.I0(DQOut[161]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__3_13[1]),
        .O(\wosp_reg[1]_23 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__22 
       (.I0(DQOut[169]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__4_14[1]),
        .O(\wosp_reg[1]_22 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__23 
       (.I0(DQOut[177]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__5_15[1]),
        .O(\wosp_reg[1]_21 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__24 
       (.I0(DQOut[185]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__6_16[1]),
        .O(\wosp_reg[1]_20 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__25 
       (.I0(DMOut[17]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__7_17[1]),
        .O(\wosp_reg[1]_19 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__26 
       (.I0(DQOut[193]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(dReg_18[1]),
        .O(\wosp_reg[1]_27 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__27 
       (.I0(DQOut[201]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__0_19[1]),
        .O(\wosp_reg[1]_35 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__28 
       (.I0(DQOut[209]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__1_20[1]),
        .O(\wosp_reg[1]_34 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__29 
       (.I0(DQOut[217]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__2_21[1]),
        .O(\wosp_reg[1]_33 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__3 
       (.I0(DQOut[33]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__2_0 ),
        .I4(dReg__3[1]),
        .O(\wosp_reg[1]_5 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__30 
       (.I0(DQOut[225]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__3_22[1]),
        .O(\wosp_reg[1]_32 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__31 
       (.I0(DQOut[233]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__4_23[1]),
        .O(\wosp_reg[1]_31 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__32 
       (.I0(DQOut[241]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__5_24[1]),
        .O(\wosp_reg[1]_30 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__33 
       (.I0(DQOut[249]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__6_25[1]),
        .O(\wosp_reg[1]_29 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__34 
       (.I0(DMOut[25]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__7_26[1]),
        .O(\wosp_reg[1]_28 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__35 
       (.I0(DQOut[257]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(dReg_27[1]),
        .O(\wosp_reg[1]_36 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__36 
       (.I0(DQOut[265]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__0_28[1]),
        .O(\wosp_reg[1]_44 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__37 
       (.I0(DQOut[273]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__1_29[1]),
        .O(\wosp_reg[1]_43 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__38 
       (.I0(DQOut[281]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__2_30[1]),
        .O(\wosp_reg[1]_42 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__39 
       (.I0(DQOut[289]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__3_31[1]),
        .O(\wosp_reg[1]_41 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__4 
       (.I0(DQOut[41]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(dReg__4[1]),
        .O(\wosp_reg[1]_4 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__40 
       (.I0(DQOut[297]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__4_32[1]),
        .O(\wosp_reg[1]_40 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__41 
       (.I0(DQOut[305]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__5_33[1]),
        .O(\wosp_reg[1]_39 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__42 
       (.I0(DQOut[313]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__6_34[1]),
        .O(\wosp_reg[1]_38 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__43 
       (.I0(DMOut[33]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__4_0 ),
        .I4(dReg__7_35[1]),
        .O(\wosp_reg[1]_37 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__44 
       (.I0(DQOut[321]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__0_0 ),
        .I4(dReg_36[1]),
        .O(\wosp_reg[1]_45 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__45 
       (.I0(DQOut[329]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__0_37[1]),
        .O(\wosp_reg[1]_53 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__46 
       (.I0(DQOut[337]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__1_38[1]),
        .O(\wosp_reg[1]_52 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__47 
       (.I0(DQOut[345]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__2_39[1]),
        .O(\wosp_reg[1]_51 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__48 
       (.I0(DQOut[353]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__3_40[1]),
        .O(\wosp_reg[1]_50 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__49 
       (.I0(DQOut[361]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__4_41[1]),
        .O(\wosp_reg[1]_49 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__5 
       (.I0(DQOut[49]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(dReg__5[1]),
        .O(\wosp_reg[1]_3 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__50 
       (.I0(DQOut[369]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__5_42[1]),
        .O(\wosp_reg[1]_48 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__51 
       (.I0(DQOut[377]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__6_43[1]),
        .O(\wosp_reg[1]_47 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__52 
       (.I0(DMOut[41]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__7_44[1]),
        .O(\wosp_reg[1]_46 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__53 
       (.I0(DQOut[385]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(dReg_45[1]),
        .O(\wosp_reg[1]_54 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__54 
       (.I0(DQOut[393]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__0_46[1]),
        .O(\wosp_reg[1]_62 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__55 
       (.I0(DQOut[401]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__1_47[1]),
        .O(\wosp_reg[1]_61 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__56 
       (.I0(DQOut[409]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__2_48[1]),
        .O(\wosp_reg[1]_60 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__57 
       (.I0(DQOut[417]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__3_49[1]),
        .O(\wosp_reg[1]_59 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__58 
       (.I0(DQOut[425]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__4_50[1]),
        .O(\wosp_reg[1]_58 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__59 
       (.I0(DQOut[433]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__5_51[1]),
        .O(\wosp_reg[1]_57 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__6 
       (.I0(DQOut[57]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(dReg__6[1]),
        .O(\wosp_reg[1]_2 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__60 
       (.I0(DQOut[441]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__6_0 ),
        .I4(dReg__6_52[1]),
        .O(\wosp_reg[1]_56 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__61 
       (.I0(DMOut[49]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__5_0 ),
        .I4(dReg__7_53[1]),
        .O(\wosp_reg[1]_55 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__62 
       (.I0(DQOut[449]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg_1[11]),
        .O(dReg0_out[3]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__63 
       (.I0(DQOut[457]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__0_2[1]),
        .O(\wosp_reg[1]_70 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__64 
       (.I0(DQOut[465]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__1_3[1]),
        .O(\wosp_reg[1]_69 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__65 
       (.I0(DQOut[473]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__2_4[1]),
        .O(\wosp_reg[1]_68 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__66 
       (.I0(DQOut[481]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__3_5[1]),
        .O(\wosp_reg[1]_67 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__67 
       (.I0(DQOut[489]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__4_6[1]),
        .O(\wosp_reg[1]_66 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__68 
       (.I0(DQOut[497]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__5_7[1]),
        .O(\wosp_reg[1]_65 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__69 
       (.I0(DQOut[505]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__6_8[1]),
        .O(\wosp_reg[1]_64 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__7 
       (.I0(DMOut[1]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__1_0 ),
        .I4(dReg__7[1]),
        .O(\wosp_reg[1]_1 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__70 
       (.I0(DMOut[57]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_0 ),
        .I4(dReg__7_9[1]),
        .O(\wosp_reg[1]_63 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__8 
       (.I0(DQOut[65]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep_0 ),
        .I4(dReg_0[1]),
        .O(\wosp_reg[1]_9 [1]));
  LUT5 #(
    .INIT(32'hFFEF0020)) 
    \dReg[3]_i_1__9 
       (.I0(DQOut[73]),
        .I1(\wosp_reg[1]_0 ),
        .I2(\dReg_reg[6]_0 ),
        .I3(\wosp_reg[2]_rep__3_0 ),
        .I4(dReg__0_1[1]),
        .O(\wosp_reg[1]_17 [1]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1 
       (.I0(dReg__7[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DMOut[0]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[2]),
        .O(\wosp_reg[1]_1 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__0 
       (.I0(dReg__6[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[56]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[58]),
        .O(\wosp_reg[1]_2 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__1 
       (.I0(dReg__5[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[48]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[50]),
        .O(\wosp_reg[1]_3 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__10 
       (.I0(dReg__5_6[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[112]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[114]),
        .O(\wosp_reg[1]_12 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__11 
       (.I0(dReg__4_5[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[104]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[106]),
        .O(\wosp_reg[1]_13 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__12 
       (.I0(dReg__3_4[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[96]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[98]),
        .O(\wosp_reg[1]_14 [2]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[4]_i_1__13 
       (.I0(DQOut[88]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[90]),
        .I3(dReg__2_3[2]),
        .I4(\wosp_reg[2]_rep_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_15 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__14 
       (.I0(dReg__1_2[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[80]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[82]),
        .O(\wosp_reg[1]_16 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__15 
       (.I0(dReg__0_1[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[72]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[74]),
        .O(\wosp_reg[1]_17 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__16 
       (.I0(dReg_0[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[64]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[66]),
        .O(\wosp_reg[1]_9 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__17 
       (.I0(dReg__7_17[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DMOut[16]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[18]),
        .O(\wosp_reg[1]_19 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__18 
       (.I0(dReg__6_16[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[184]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[186]),
        .O(\wosp_reg[1]_20 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__19 
       (.I0(dReg__5_15[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[176]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[178]),
        .O(\wosp_reg[1]_21 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__2 
       (.I0(dReg__4[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[40]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[42]),
        .O(\wosp_reg[1]_4 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__20 
       (.I0(dReg__4_14[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[168]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[170]),
        .O(\wosp_reg[1]_22 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__21 
       (.I0(dReg__3_13[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[160]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[162]),
        .O(\wosp_reg[1]_23 [2]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[4]_i_1__22 
       (.I0(DQOut[152]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[154]),
        .I3(dReg__2_12[2]),
        .I4(\wosp_reg[2]_rep_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_24 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__23 
       (.I0(dReg__1_11[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[144]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[146]),
        .O(\wosp_reg[1]_25 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__24 
       (.I0(dReg__0_10[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[136]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[138]),
        .O(\wosp_reg[1]_26 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__25 
       (.I0(dReg_9[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[128]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[130]),
        .O(\wosp_reg[1]_18 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__26 
       (.I0(dReg__7_26[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DMOut[24]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[26]),
        .O(\wosp_reg[1]_28 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__27 
       (.I0(dReg__6_25[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[248]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[250]),
        .O(\wosp_reg[1]_29 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__28 
       (.I0(dReg__5_24[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[240]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[242]),
        .O(\wosp_reg[1]_30 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__29 
       (.I0(dReg__4_23[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[232]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[234]),
        .O(\wosp_reg[1]_31 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__3 
       (.I0(dReg__3[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[32]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[34]),
        .O(\wosp_reg[1]_5 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__30 
       (.I0(dReg__3_22[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[224]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[226]),
        .O(\wosp_reg[1]_32 [2]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[4]_i_1__31 
       (.I0(DQOut[216]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[218]),
        .I3(dReg__2_21[2]),
        .I4(\wosp_reg[2]_rep__0_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_33 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__32 
       (.I0(dReg__1_20[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[208]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[210]),
        .O(\wosp_reg[1]_34 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__33 
       (.I0(dReg__0_19[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[200]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[202]),
        .O(\wosp_reg[1]_35 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__34 
       (.I0(dReg_18[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[192]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[194]),
        .O(\wosp_reg[1]_27 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__35 
       (.I0(dReg__7_35[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DMOut[32]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[34]),
        .O(\wosp_reg[1]_37 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__36 
       (.I0(dReg__6_34[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[312]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[314]),
        .O(\wosp_reg[1]_38 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__37 
       (.I0(dReg__5_33[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[304]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[306]),
        .O(\wosp_reg[1]_39 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__38 
       (.I0(dReg__4_32[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[296]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[298]),
        .O(\wosp_reg[1]_40 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__39 
       (.I0(dReg__3_31[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[288]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[290]),
        .O(\wosp_reg[1]_41 [2]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[4]_i_1__4 
       (.I0(DQOut[24]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[26]),
        .I3(dReg__2[2]),
        .I4(\wosp_reg[2]_rep_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_6 [2]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[4]_i_1__40 
       (.I0(DQOut[280]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[282]),
        .I3(dReg__2_30[2]),
        .I4(\wosp_reg[2]_rep__0_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_42 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__41 
       (.I0(dReg__1_29[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[272]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[274]),
        .O(\wosp_reg[1]_43 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__42 
       (.I0(dReg__0_28[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[264]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[266]),
        .O(\wosp_reg[1]_44 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__43 
       (.I0(dReg_27[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[256]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[258]),
        .O(\wosp_reg[1]_36 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__44 
       (.I0(dReg__7_44[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DMOut[40]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[42]),
        .O(\wosp_reg[1]_46 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__45 
       (.I0(dReg__6_43[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[376]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[378]),
        .O(\wosp_reg[1]_47 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__46 
       (.I0(dReg__5_42[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[368]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[370]),
        .O(\wosp_reg[1]_48 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__47 
       (.I0(dReg__4_41[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[360]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[362]),
        .O(\wosp_reg[1]_49 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__48 
       (.I0(dReg__3_40[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[352]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[354]),
        .O(\wosp_reg[1]_50 [2]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[4]_i_1__49 
       (.I0(DQOut[344]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[346]),
        .I3(dReg__2_39[2]),
        .I4(\wosp_reg[2]_rep__1_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_51 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__5 
       (.I0(dReg__1[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[16]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[18]),
        .O(\wosp_reg[1]_7 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__50 
       (.I0(dReg__1_38[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[336]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[338]),
        .O(\wosp_reg[1]_52 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__51 
       (.I0(dReg__0_37[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[328]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[330]),
        .O(\wosp_reg[1]_53 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__52 
       (.I0(dReg_36[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[320]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[322]),
        .O(\wosp_reg[1]_45 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__53 
       (.I0(dReg__7_53[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DMOut[48]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[50]),
        .O(\wosp_reg[1]_55 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__54 
       (.I0(dReg__6_52[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[440]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[442]),
        .O(\wosp_reg[1]_56 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__55 
       (.I0(dReg__5_51[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[432]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[434]),
        .O(\wosp_reg[1]_57 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__56 
       (.I0(dReg__4_50[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[424]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[426]),
        .O(\wosp_reg[1]_58 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__57 
       (.I0(dReg__3_49[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[416]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[418]),
        .O(\wosp_reg[1]_59 [2]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[4]_i_1__58 
       (.I0(DQOut[408]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[410]),
        .I3(dReg__2_48[2]),
        .I4(\wosp_reg[2]_rep__1_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_60 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__59 
       (.I0(dReg__1_47[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[400]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[402]),
        .O(\wosp_reg[1]_61 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__6 
       (.I0(dReg__0[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[8]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[10]),
        .O(\wosp_reg[1]_8 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__60 
       (.I0(dReg__0_46[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[392]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[394]),
        .O(\wosp_reg[1]_62 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__61 
       (.I0(dReg_45[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[384]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[386]),
        .O(\wosp_reg[1]_54 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__62 
       (.I0(dReg__7_9[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DMOut[56]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[58]),
        .O(\wosp_reg[1]_63 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__63 
       (.I0(dReg__6_8[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DQOut[504]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[506]),
        .O(\wosp_reg[1]_64 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__64 
       (.I0(dReg__5_7[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DQOut[496]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[498]),
        .O(\wosp_reg[1]_65 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__65 
       (.I0(dReg__4_6[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DQOut[488]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[490]),
        .O(\wosp_reg[1]_66 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__66 
       (.I0(dReg__3_5[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DQOut[480]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[482]),
        .O(\wosp_reg[1]_67 [2]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[4]_i_1__67 
       (.I0(DQOut[472]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[474]),
        .I3(dReg__2_4[2]),
        .I4(\wosp_reg[2]_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_68 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__68 
       (.I0(dReg__1_3[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DQOut[464]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[466]),
        .O(\wosp_reg[1]_69 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__69 
       (.I0(dReg__0_2[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DQOut[456]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[458]),
        .O(\wosp_reg[1]_70 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__7 
       (.I0(dReg[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[0]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[2]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__70 
       (.I0(dReg_1[12]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DQOut[448]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[450]),
        .O(dReg0_out[4]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__8 
       (.I0(dReg__7_8[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DMOut[8]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[10]),
        .O(\wosp_reg[1]_10 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[4]_i_1__9 
       (.I0(dReg__6_7[2]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[120]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[122]),
        .O(\wosp_reg[1]_11 [2]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1 
       (.I0(dReg[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[1]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[3]),
        .O(D[3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__0 
       (.I0(dReg__7[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DMOut[1]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[3]),
        .O(\wosp_reg[1]_1 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__1 
       (.I0(dReg__6[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[57]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[59]),
        .O(\wosp_reg[1]_2 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__10 
       (.I0(dReg__6_7[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[121]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[123]),
        .O(\wosp_reg[1]_11 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__11 
       (.I0(dReg__5_6[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[113]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[115]),
        .O(\wosp_reg[1]_12 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__12 
       (.I0(DQOut[105]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[107]),
        .I3(dReg__4_5[3]),
        .I4(\wosp_reg[2]_rep_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_13 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__13 
       (.I0(DQOut[97]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[99]),
        .I3(dReg__3_4[3]),
        .I4(\wosp_reg[2]_rep_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_14 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__14 
       (.I0(dReg__2_3[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[89]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[91]),
        .O(\wosp_reg[1]_15 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__15 
       (.I0(DQOut[81]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[83]),
        .I3(dReg__1_2[3]),
        .I4(\wosp_reg[2]_rep_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_16 [3]));
  LUT6 #(
    .INIT(64'hAEAEAEA2A2AEA2A2)) 
    \dReg[5]_i_1__16 
       (.I0(dReg__0_1[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[75]),
        .I5(DQOut[73]),
        .O(\wosp_reg[1]_17 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__17 
       (.I0(dReg_9[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[129]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[131]),
        .O(\wosp_reg[1]_18 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__18 
       (.I0(dReg__7_17[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DMOut[17]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[19]),
        .O(\wosp_reg[1]_19 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__19 
       (.I0(dReg__6_16[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[185]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[187]),
        .O(\wosp_reg[1]_20 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__2 
       (.I0(dReg__5[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[49]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[51]),
        .O(\wosp_reg[1]_3 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__20 
       (.I0(dReg__5_15[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[177]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[179]),
        .O(\wosp_reg[1]_21 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__21 
       (.I0(DQOut[169]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[171]),
        .I3(dReg__4_14[3]),
        .I4(\wosp_reg[2]_rep_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_22 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__22 
       (.I0(DQOut[161]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[163]),
        .I3(dReg__3_13[3]),
        .I4(\wosp_reg[2]_rep_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_23 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__23 
       (.I0(dReg__2_12[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[153]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[155]),
        .O(\wosp_reg[1]_24 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__24 
       (.I0(DQOut[145]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[147]),
        .I3(dReg__1_11[3]),
        .I4(\wosp_reg[2]_rep_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_25 [3]));
  LUT6 #(
    .INIT(64'hAEAEAEA2A2AEA2A2)) 
    \dReg[5]_i_1__25 
       (.I0(dReg__0_10[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[139]),
        .I5(DQOut[137]),
        .O(\wosp_reg[1]_26 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__26 
       (.I0(dReg_18[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[193]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[195]),
        .O(\wosp_reg[1]_27 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__27 
       (.I0(dReg__7_26[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DMOut[25]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[27]),
        .O(\wosp_reg[1]_28 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__28 
       (.I0(dReg__6_25[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[249]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[251]),
        .O(\wosp_reg[1]_29 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__29 
       (.I0(dReg__5_24[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[241]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[243]),
        .O(\wosp_reg[1]_30 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__3 
       (.I0(DQOut[41]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[43]),
        .I3(dReg__4[3]),
        .I4(\wosp_reg[2]_rep_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_4 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__30 
       (.I0(DQOut[233]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[235]),
        .I3(dReg__4_23[3]),
        .I4(\wosp_reg[2]_rep__0_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_31 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__31 
       (.I0(DQOut[225]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[227]),
        .I3(dReg__3_22[3]),
        .I4(\wosp_reg[2]_rep__0_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_32 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__32 
       (.I0(dReg__2_21[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[217]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[219]),
        .O(\wosp_reg[1]_33 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__33 
       (.I0(DQOut[209]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[211]),
        .I3(dReg__1_20[3]),
        .I4(\wosp_reg[2]_rep__0_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_34 [3]));
  LUT6 #(
    .INIT(64'hAEAEAEA2A2AEA2A2)) 
    \dReg[5]_i_1__34 
       (.I0(dReg__0_19[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[203]),
        .I5(DQOut[201]),
        .O(\wosp_reg[1]_35 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__35 
       (.I0(dReg_27[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[257]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[259]),
        .O(\wosp_reg[1]_36 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__36 
       (.I0(dReg__7_35[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DMOut[33]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[35]),
        .O(\wosp_reg[1]_37 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__37 
       (.I0(dReg__6_34[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[313]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[315]),
        .O(\wosp_reg[1]_38 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__38 
       (.I0(dReg__5_33[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[305]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[307]),
        .O(\wosp_reg[1]_39 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__39 
       (.I0(DQOut[297]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[299]),
        .I3(dReg__4_32[3]),
        .I4(\wosp_reg[2]_rep__0_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_40 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__4 
       (.I0(DQOut[33]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[35]),
        .I3(dReg__3[3]),
        .I4(\wosp_reg[2]_rep_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_5 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__40 
       (.I0(DQOut[289]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[291]),
        .I3(dReg__3_31[3]),
        .I4(\wosp_reg[2]_rep__0_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_41 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__41 
       (.I0(dReg__2_30[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(DQOut[281]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[283]),
        .O(\wosp_reg[1]_42 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__42 
       (.I0(DQOut[273]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[275]),
        .I3(dReg__1_29[3]),
        .I4(\wosp_reg[2]_rep__0_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_43 [3]));
  LUT6 #(
    .INIT(64'hAEAEAEA2A2AEA2A2)) 
    \dReg[5]_i_1__43 
       (.I0(dReg__0_28[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[267]),
        .I5(DQOut[265]),
        .O(\wosp_reg[1]_44 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__44 
       (.I0(dReg_36[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[321]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[323]),
        .O(\wosp_reg[1]_45 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__45 
       (.I0(dReg__7_44[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DMOut[41]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[43]),
        .O(\wosp_reg[1]_46 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__46 
       (.I0(dReg__6_43[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[377]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[379]),
        .O(\wosp_reg[1]_47 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__47 
       (.I0(dReg__5_42[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[369]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[371]),
        .O(\wosp_reg[1]_48 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__48 
       (.I0(DQOut[361]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[363]),
        .I3(dReg__4_41[3]),
        .I4(\wosp_reg[2]_rep__1_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_49 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__49 
       (.I0(DQOut[353]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[355]),
        .I3(dReg__3_40[3]),
        .I4(\wosp_reg[2]_rep__1_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_50 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__5 
       (.I0(dReg__2[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[25]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[27]),
        .O(\wosp_reg[1]_6 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__50 
       (.I0(dReg__2_39[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[345]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[347]),
        .O(\wosp_reg[1]_51 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__51 
       (.I0(DQOut[337]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[339]),
        .I3(dReg__1_38[3]),
        .I4(\wosp_reg[2]_rep__1_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_52 [3]));
  LUT6 #(
    .INIT(64'hAEAEAEA2A2AEA2A2)) 
    \dReg[5]_i_1__52 
       (.I0(dReg__0_37[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__0_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[331]),
        .I5(DQOut[329]),
        .O(\wosp_reg[1]_53 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__53 
       (.I0(dReg_45[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[385]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[387]),
        .O(\wosp_reg[1]_54 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__54 
       (.I0(dReg__7_53[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DMOut[49]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[51]),
        .O(\wosp_reg[1]_55 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__55 
       (.I0(dReg__6_52[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[441]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[443]),
        .O(\wosp_reg[1]_56 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__56 
       (.I0(dReg__5_51[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[433]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[435]),
        .O(\wosp_reg[1]_57 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__57 
       (.I0(DQOut[425]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[427]),
        .I3(dReg__4_50[3]),
        .I4(\wosp_reg[2]_rep__1_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_58 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__58 
       (.I0(DQOut[417]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[419]),
        .I3(dReg__3_49[3]),
        .I4(\wosp_reg[2]_rep__1_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_59 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__59 
       (.I0(dReg__2_48[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(DQOut[409]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[411]),
        .O(\wosp_reg[1]_60 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__6 
       (.I0(DQOut[17]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[19]),
        .I3(dReg__1[3]),
        .I4(\wosp_reg[2]_rep_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_7 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__60 
       (.I0(DQOut[401]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[403]),
        .I3(dReg__1_47[3]),
        .I4(\wosp_reg[2]_rep__1_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_61 [3]));
  LUT6 #(
    .INIT(64'hAEAEAEA2A2AEA2A2)) 
    \dReg[5]_i_1__61 
       (.I0(dReg__0_46[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep__1_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[395]),
        .I5(DQOut[393]),
        .O(\wosp_reg[1]_62 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__62 
       (.I0(dReg_1[13]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DQOut[449]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[451]),
        .O(dReg0_out[5]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__63 
       (.I0(dReg__7_9[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DMOut[57]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[59]),
        .O(\wosp_reg[1]_63 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__64 
       (.I0(dReg__6_8[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DQOut[505]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[507]),
        .O(\wosp_reg[1]_64 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__65 
       (.I0(dReg__5_7[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DQOut[497]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[499]),
        .O(\wosp_reg[1]_65 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__66 
       (.I0(DQOut[489]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[491]),
        .I3(dReg__4_6[3]),
        .I4(\wosp_reg[2]_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_66 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__67 
       (.I0(DQOut[481]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[483]),
        .I3(dReg__3_5[3]),
        .I4(\wosp_reg[2]_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_67 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__68 
       (.I0(dReg__2_4[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(DQOut[473]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[475]),
        .O(\wosp_reg[1]_68 [3]));
  LUT6 #(
    .INIT(64'hFF00B8B8FF00FF00)) 
    \dReg[5]_i_1__69 
       (.I0(DQOut[465]),
        .I1(\wosp_reg[1]_0 ),
        .I2(DQOut[467]),
        .I3(dReg__1_3[3]),
        .I4(\wosp_reg[2]_0 ),
        .I5(\dReg_reg[6]_0 ),
        .O(\wosp_reg[1]_69 [3]));
  LUT6 #(
    .INIT(64'hAEAEAEA2A2AEA2A2)) 
    \dReg[5]_i_1__7 
       (.I0(dReg__0[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[11]),
        .I5(DQOut[9]),
        .O(\wosp_reg[1]_8 [3]));
  LUT6 #(
    .INIT(64'hAEAEAEA2A2AEA2A2)) 
    \dReg[5]_i_1__70 
       (.I0(dReg__0_2[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_0 ),
        .I3(\wosp_reg[1]_0 ),
        .I4(DQOut[459]),
        .I5(DQOut[457]),
        .O(\wosp_reg[1]_70 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__8 
       (.I0(dReg_0[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DQOut[65]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DQOut[67]),
        .O(\wosp_reg[1]_9 [3]));
  LUT6 #(
    .INIT(64'hAEA2AEAEAEA2A2A2)) 
    \dReg[5]_i_1__9 
       (.I0(dReg__7_8[3]),
        .I1(\dReg_reg[6]_0 ),
        .I2(\wosp_reg[2]_rep_0 ),
        .I3(DMOut[9]),
        .I4(\wosp_reg[1]_0 ),
        .I5(DMOut[11]),
        .O(\wosp_reg[1]_10 [3]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[2]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_1 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg[4]),
        .O(D[4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__0 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[10]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_2 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0[4]),
        .O(\wosp_reg[1]_8 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__1 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[18]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_3 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1[4]),
        .O(\wosp_reg[1]_7 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__10 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[82]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_12 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_2[4]),
        .O(\wosp_reg[1]_16 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__11 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[90]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_13 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_3[4]),
        .O(\wosp_reg[1]_15 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__12 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[98]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_14 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_4[4]),
        .O(\wosp_reg[1]_14 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__13 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[106]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_15 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_5[4]),
        .O(\wosp_reg[1]_13 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__14 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[114]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_16 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_6[4]),
        .O(\wosp_reg[1]_12 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__15 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[122]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_17 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_7[4]),
        .O(\wosp_reg[1]_11 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__16 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DMOut[10]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_18 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_8[4]),
        .O(\wosp_reg[1]_10 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__17 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[130]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_19 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_9[4]),
        .O(\wosp_reg[1]_18 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__18 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[138]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_20 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_10[4]),
        .O(\wosp_reg[1]_26 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__19 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[146]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_21 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_11[4]),
        .O(\wosp_reg[1]_25 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__2 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[26]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_4 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2[4]),
        .O(\wosp_reg[1]_6 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__20 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[154]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_22 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_12[4]),
        .O(\wosp_reg[1]_24 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__21 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[162]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_23 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_13[4]),
        .O(\wosp_reg[1]_23 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__22 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[170]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_24 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_14[4]),
        .O(\wosp_reg[1]_22 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__23 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[178]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_25 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_15[4]),
        .O(\wosp_reg[1]_21 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__24 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[186]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_26 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_16[4]),
        .O(\wosp_reg[1]_20 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__25 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DMOut[18]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_27 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_17[4]),
        .O(\wosp_reg[1]_19 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__26 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[194]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_28 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_18[4]),
        .O(\wosp_reg[1]_27 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__27 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[202]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_29 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_19[4]),
        .O(\wosp_reg[1]_35 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__28 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[210]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_30 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_20[4]),
        .O(\wosp_reg[1]_34 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__29 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[218]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_31 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_21[4]),
        .O(\wosp_reg[1]_33 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__3 
       (.I0(\wosp_reg[2]_rep__1_0 ),
        .I1(DQOut[34]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_5 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3[4]),
        .O(\wosp_reg[1]_5 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__30 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[226]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_32 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_22[4]),
        .O(\wosp_reg[1]_32 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__31 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[234]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_33 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_23[4]),
        .O(\wosp_reg[1]_31 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__32 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[242]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_34 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_24[4]),
        .O(\wosp_reg[1]_30 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__33 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[250]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_35 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_25[4]),
        .O(\wosp_reg[1]_29 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__34 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DMOut[26]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_36 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_26[4]),
        .O(\wosp_reg[1]_28 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__35 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[258]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_37 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_27[4]),
        .O(\wosp_reg[1]_36 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__36 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[266]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_38 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_28[4]),
        .O(\wosp_reg[1]_44 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__37 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[274]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_39 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_29[4]),
        .O(\wosp_reg[1]_43 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__38 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[282]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_40 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_30[4]),
        .O(\wosp_reg[1]_42 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__39 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[290]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_41 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_31[4]),
        .O(\wosp_reg[1]_41 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__4 
       (.I0(\wosp_reg[2]_rep__1_0 ),
        .I1(DQOut[42]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_6 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4[4]),
        .O(\wosp_reg[1]_4 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__40 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[298]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_42 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_32[4]),
        .O(\wosp_reg[1]_40 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__41 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[306]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_43 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_33[4]),
        .O(\wosp_reg[1]_39 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__42 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[314]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_44 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_34[4]),
        .O(\wosp_reg[1]_38 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__43 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DMOut[34]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_45 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_35[4]),
        .O(\wosp_reg[1]_37 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__44 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[322]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_46 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_36[4]),
        .O(\wosp_reg[1]_45 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__45 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[330]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_47 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_37[4]),
        .O(\wosp_reg[1]_53 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__46 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[338]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_48 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_38[4]),
        .O(\wosp_reg[1]_52 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__47 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[346]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_49 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_39[4]),
        .O(\wosp_reg[1]_51 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__48 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[354]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_50 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_40[4]),
        .O(\wosp_reg[1]_50 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__49 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[362]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_51 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_41[4]),
        .O(\wosp_reg[1]_49 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__5 
       (.I0(\wosp_reg[2]_rep__1_0 ),
        .I1(DQOut[50]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_7 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5[4]),
        .O(\wosp_reg[1]_3 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__50 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[370]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_52 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_42[4]),
        .O(\wosp_reg[1]_48 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__51 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[378]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_53 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_43[4]),
        .O(\wosp_reg[1]_47 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__52 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DMOut[42]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_54 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_44[4]),
        .O(\wosp_reg[1]_46 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__53 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[386]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_55 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_45[4]),
        .O(\wosp_reg[1]_54 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__54 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[394]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_56 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_46[4]),
        .O(\wosp_reg[1]_62 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__55 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[402]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_57 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_47[4]),
        .O(\wosp_reg[1]_61 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__56 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[410]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_58 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_48[4]),
        .O(\wosp_reg[1]_60 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__57 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[418]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_59 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_49[4]),
        .O(\wosp_reg[1]_59 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__58 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[426]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_60 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_50[4]),
        .O(\wosp_reg[1]_58 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__59 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[434]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_61 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_51[4]),
        .O(\wosp_reg[1]_57 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__6 
       (.I0(\wosp_reg[2]_rep__1_0 ),
        .I1(DQOut[58]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_8 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6[4]),
        .O(\wosp_reg[1]_2 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__60 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[442]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_62 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_52[4]),
        .O(\wosp_reg[1]_56 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__61 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DMOut[50]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_63 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_53[4]),
        .O(\wosp_reg[1]_55 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__62 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[450]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_64 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_1[14]),
        .O(dReg0_out[6]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__63 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[458]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_65 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_2[4]),
        .O(\wosp_reg[1]_70 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__64 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[466]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_66 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_3[4]),
        .O(\wosp_reg[1]_69 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__65 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[474]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_67 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_4[4]),
        .O(\wosp_reg[1]_68 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__66 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[482]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_68 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_5[4]),
        .O(\wosp_reg[1]_67 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__67 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[490]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_69 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_6[4]),
        .O(\wosp_reg[1]_66 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__68 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[498]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_70 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_7[4]),
        .O(\wosp_reg[1]_65 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__69 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[506]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_71 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_8[4]),
        .O(\wosp_reg[1]_64 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__7 
       (.I0(\wosp_reg[2]_rep__1_0 ),
        .I1(DMOut[2]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_9 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7[4]),
        .O(\wosp_reg[1]_1 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__70 
       (.I0(\wosp_reg[2]_rep__7_0 ),
        .I1(DMOut[58]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_72 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_9[4]),
        .O(\wosp_reg[1]_63 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__8 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[66]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_10 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_0[4]),
        .O(\wosp_reg[1]_9 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[6]_i_1__9 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[74]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[6]_11 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_1[4]),
        .O(\wosp_reg[1]_17 [4]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1 
       (.I0(\wosp_reg[2]_rep_0 ),
        .I1(DQOut[3]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_0 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg[5]),
        .O(D[5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__0 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[11]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_1 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0[5]),
        .O(\wosp_reg[1]_8 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__1 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[19]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_2 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1[5]),
        .O(\wosp_reg[1]_7 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__10 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[83]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_11 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_2[5]),
        .O(\wosp_reg[1]_16 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__11 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[91]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_12 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_3[5]),
        .O(\wosp_reg[1]_15 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__12 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[99]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_13 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_4[5]),
        .O(\wosp_reg[1]_14 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__13 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[107]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_14 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_5[5]),
        .O(\wosp_reg[1]_13 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__14 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[115]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_15 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_6[5]),
        .O(\wosp_reg[1]_12 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__15 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[123]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_16 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_7[5]),
        .O(\wosp_reg[1]_11 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__16 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DMOut[11]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_17 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_8[5]),
        .O(\wosp_reg[1]_10 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__17 
       (.I0(\wosp_reg[2]_rep_0 ),
        .I1(DQOut[131]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_18 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_9[5]),
        .O(\wosp_reg[1]_18 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__18 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[139]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_19 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_10[5]),
        .O(\wosp_reg[1]_26 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__19 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[147]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_20 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_11[5]),
        .O(\wosp_reg[1]_25 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__2 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[27]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_3 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2[5]),
        .O(\wosp_reg[1]_6 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__20 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[155]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_21 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_12[5]),
        .O(\wosp_reg[1]_24 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__21 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[163]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_22 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_13[5]),
        .O(\wosp_reg[1]_23 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__22 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[171]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_23 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_14[5]),
        .O(\wosp_reg[1]_22 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__23 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[179]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_24 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_15[5]),
        .O(\wosp_reg[1]_21 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__24 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[187]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_25 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_16[5]),
        .O(\wosp_reg[1]_20 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__25 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DMOut[19]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_26 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_17[5]),
        .O(\wosp_reg[1]_19 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__26 
       (.I0(\wosp_reg[2]_rep__0_0 ),
        .I1(DQOut[195]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_27 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_18[5]),
        .O(\wosp_reg[1]_27 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__27 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[203]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_28 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_19[5]),
        .O(\wosp_reg[1]_35 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__28 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[211]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_29 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_20[5]),
        .O(\wosp_reg[1]_34 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__29 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[219]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_30 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_21[5]),
        .O(\wosp_reg[1]_33 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__3 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[35]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_4 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3[5]),
        .O(\wosp_reg[1]_5 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__30 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[227]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_31 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_22[5]),
        .O(\wosp_reg[1]_32 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__31 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[235]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_32 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_23[5]),
        .O(\wosp_reg[1]_31 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__32 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[243]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_33 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_24[5]),
        .O(\wosp_reg[1]_30 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__33 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DQOut[251]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_34 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_25[5]),
        .O(\wosp_reg[1]_29 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__34 
       (.I0(\wosp_reg[2]_rep__3_0 ),
        .I1(DMOut[27]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_35 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_26[5]),
        .O(\wosp_reg[1]_28 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__35 
       (.I0(\wosp_reg[2]_rep__0_0 ),
        .I1(DQOut[259]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_36 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_27[5]),
        .O(\wosp_reg[1]_36 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__36 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[267]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_37 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_28[5]),
        .O(\wosp_reg[1]_44 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__37 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[275]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_38 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_29[5]),
        .O(\wosp_reg[1]_43 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__38 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[283]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_39 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_30[5]),
        .O(\wosp_reg[1]_42 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__39 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[291]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_40 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_31[5]),
        .O(\wosp_reg[1]_41 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__4 
       (.I0(\wosp_reg[2]_rep__1_0 ),
        .I1(DQOut[43]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_5 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4[5]),
        .O(\wosp_reg[1]_4 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__40 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[299]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_41 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_32[5]),
        .O(\wosp_reg[1]_40 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__41 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[307]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_42 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_33[5]),
        .O(\wosp_reg[1]_39 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__42 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DQOut[315]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_43 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_34[5]),
        .O(\wosp_reg[1]_38 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__43 
       (.I0(\wosp_reg[2]_rep__4_0 ),
        .I1(DMOut[35]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_44 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_35[5]),
        .O(\wosp_reg[1]_37 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__44 
       (.I0(\wosp_reg[2]_rep__0_0 ),
        .I1(DQOut[323]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_45 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_36[5]),
        .O(\wosp_reg[1]_45 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__45 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[331]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_46 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_37[5]),
        .O(\wosp_reg[1]_53 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__46 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[339]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_47 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_38[5]),
        .O(\wosp_reg[1]_52 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__47 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[347]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_48 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_39[5]),
        .O(\wosp_reg[1]_51 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__48 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[355]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_49 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_40[5]),
        .O(\wosp_reg[1]_50 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__49 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[363]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_50 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_41[5]),
        .O(\wosp_reg[1]_49 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__5 
       (.I0(\wosp_reg[2]_rep__1_0 ),
        .I1(DQOut[51]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_6 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5[5]),
        .O(\wosp_reg[1]_3 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__50 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[371]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_51 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_42[5]),
        .O(\wosp_reg[1]_48 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__51 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DQOut[379]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_52 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_43[5]),
        .O(\wosp_reg[1]_47 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__52 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DMOut[43]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_53 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_44[5]),
        .O(\wosp_reg[1]_46 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__53 
       (.I0(\wosp_reg[2]_rep__1_0 ),
        .I1(DQOut[387]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_54 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_45[5]),
        .O(\wosp_reg[1]_54 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__54 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[395]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_55 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_46[5]),
        .O(\wosp_reg[1]_62 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__55 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[403]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_56 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_47[5]),
        .O(\wosp_reg[1]_61 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__56 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[411]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_57 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_48[5]),
        .O(\wosp_reg[1]_60 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__57 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[419]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_58 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_49[5]),
        .O(\wosp_reg[1]_59 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__58 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[427]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_59 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_50[5]),
        .O(\wosp_reg[1]_58 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__59 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[435]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_60 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_51[5]),
        .O(\wosp_reg[1]_57 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__6 
       (.I0(\wosp_reg[2]_rep__1_0 ),
        .I1(DQOut[59]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_7 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6[5]),
        .O(\wosp_reg[1]_2 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__60 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[443]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_61 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_52[5]),
        .O(\wosp_reg[1]_56 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__61 
       (.I0(\wosp_reg[2]_rep__5_0 ),
        .I1(DMOut[51]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_62 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_53[5]),
        .O(\wosp_reg[1]_55 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__62 
       (.I0(\wosp_reg[2]_0 ),
        .I1(DQOut[451]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_63 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_1[15]),
        .O(dReg0_out[7]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__63 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[459]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_64 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_2[5]),
        .O(\wosp_reg[1]_70 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__64 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[467]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_65 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__1_3[5]),
        .O(\wosp_reg[1]_69 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__65 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[475]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_66 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__2_4[5]),
        .O(\wosp_reg[1]_68 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__66 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[483]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_67 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__3_5[5]),
        .O(\wosp_reg[1]_67 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__67 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[491]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_68 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__4_6[5]),
        .O(\wosp_reg[1]_66 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__68 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[499]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_69 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__5_7[5]),
        .O(\wosp_reg[1]_65 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__69 
       (.I0(\wosp_reg[2]_rep__6_0 ),
        .I1(DQOut[507]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_70 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__6_8[5]),
        .O(\wosp_reg[1]_64 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__7 
       (.I0(\wosp_reg[2]_rep__1_0 ),
        .I1(DMOut[3]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_8 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7[5]),
        .O(\wosp_reg[1]_1 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__70 
       (.I0(\wosp_reg[2]_rep__7_0 ),
        .I1(DMOut[59]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_71 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__7_9[5]),
        .O(\wosp_reg[1]_63 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__8 
       (.I0(\wosp_reg[2]_rep_0 ),
        .I1(DQOut[67]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_9 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg_0[5]),
        .O(\wosp_reg[1]_9 [5]));
  LUT6 #(
    .INIT(64'hEFE0FFFF4F400000)) 
    \dReg[7]_i_1__9 
       (.I0(\wosp_reg[2]_rep__2_0 ),
        .I1(DQOut[75]),
        .I2(\wosp_reg[1]_0 ),
        .I3(\dReg_reg[7]_10 ),
        .I4(\dReg_reg[6]_0 ),
        .I5(dReg__0_1[5]),
        .O(\wosp_reg[1]_17 [5]));
  FDRE \dReg_reg[0] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(dReg_1[8]),
        .Q(ch0_mcal_DQOut[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_0 ),
        .Q(dReg_1[10]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(dReg_1[11]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(dReg0_out[12]),
        .Q(dReg_1[12]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(dReg0_out[13]),
        .Q(dReg_1[13]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(DQOut[454]),
        .Q(dReg_1[14]),
        .R(wrDataVal_reg));
  FDRE \dReg_reg[15] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(dReg0_out[15]),
        .Q(dReg_1[15]),
        .R(1'b0));
  FDRE \dReg_reg[1] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(dReg_1[9]),
        .Q(ch0_mcal_DQOut[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(dReg0_out[2]),
        .Q(ch0_mcal_DQOut[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(dReg0_out[3]),
        .Q(ch0_mcal_DQOut[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(dReg0_out[4]),
        .Q(ch0_mcal_DQOut[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(dReg0_out[5]),
        .Q(ch0_mcal_DQOut[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(dReg0_out[6]),
        .Q(ch0_mcal_DQOut[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(dReg0_out[7]),
        .Q(ch0_mcal_DQOut[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(\dReg_reg[9]_0 [0]),
        .Q(dReg_1[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(\dReg_reg[9]_0 [1]),
        .Q(dReg_1[9]),
        .R(1'b0));
  FDRE \wosp_reg[1] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(\wosp_reg[1]_71 ),
        .Q(\wosp_reg[1]_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "wosp_reg[2]" *) 
  FDRE \wosp_reg[2] 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(sel),
        .Q(\wosp_reg[2]_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "wosp_reg[2]" *) 
  FDRE \wosp_reg[2]_rep 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(sel),
        .Q(\wosp_reg[2]_rep_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "wosp_reg[2]" *) 
  FDRE \wosp_reg[2]_rep__0 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(sel),
        .Q(\wosp_reg[2]_rep__0_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "wosp_reg[2]" *) 
  FDRE \wosp_reg[2]_rep__1 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(sel),
        .Q(\wosp_reg[2]_rep__1_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "wosp_reg[2]" *) 
  FDRE \wosp_reg[2]_rep__2 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(sel),
        .Q(\wosp_reg[2]_rep__2_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "wosp_reg[2]" *) 
  FDRE \wosp_reg[2]_rep__3 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(sel),
        .Q(\wosp_reg[2]_rep__3_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "wosp_reg[2]" *) 
  FDRE \wosp_reg[2]_rep__4 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(sel),
        .Q(\wosp_reg[2]_rep__4_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "wosp_reg[2]" *) 
  FDRE \wosp_reg[2]_rep__5 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(sel),
        .Q(\wosp_reg[2]_rep__5_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "wosp_reg[2]" *) 
  FDRE \wosp_reg[2]_rep__6 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(sel),
        .Q(\wosp_reg[2]_rep__6_0 ),
        .R(1'b0));
  (* ORIG_CELL_NAME = "wosp_reg[2]" *) 
  FDRE \wosp_reg[2]_rep__7 
       (.C(\wosp_reg[2]_rep__7_1 ),
        .CE(1'b1),
        .D(sel),
        .Q(\wosp_reg[2]_rep__7_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_100
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[10]_1 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_2 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[10]_1 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_2 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__3;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[11]_0 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_2 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_0 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__3[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__3[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_101
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[10]_1 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_2 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[10]_1 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_2 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__4;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[11]_0 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_2 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_0 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__4[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__4[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_102
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[10]_1 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_2 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[10]_1 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_2 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__5;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[11]_0 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_2 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_0 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__5[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__5[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_103
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[10]_1 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_2 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[10]_1 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_2 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__6;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[11]_0 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_2 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_0 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__6[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__6[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_104
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DMOut,
    \dReg_reg[10]_1 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_2 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DMOut;
  input \dReg_reg[10]_1 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_2 ;

  wire [1:0]DMOut;
  wire [9:8]dReg__7;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[11]_0 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_2 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_0 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__7[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__7[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_34
   (Q,
    \dReg_reg[15]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[15]_1 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]Q;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[15]_1 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [9:0]D;
  wire [1:0]DQOut;
  wire [9:0]Q;
  wire [9:8]dReg__0_2;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire \dReg_reg[15]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0_2[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0_2[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg__0_2[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg__0_2[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_35
   (Q,
    \dReg_reg[15]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[15]_1 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]Q;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[15]_1 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [9:0]D;
  wire [1:0]DQOut;
  wire [9:0]Q;
  wire [9:8]dReg__1_3;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire \dReg_reg[15]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1_3[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1_3[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg__1_3[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg__1_3[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_36
   (Q,
    \dReg_reg[15]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[15]_1 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]Q;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[15]_1 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [9:0]D;
  wire [1:0]DQOut;
  wire [9:0]Q;
  wire [9:8]dReg__2_4;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire \dReg_reg[15]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2_4[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2_4[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg__2_4[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg__2_4[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_37
   (Q,
    \dReg_reg[15]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[15]_1 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]Q;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[15]_1 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [9:0]D;
  wire [1:0]DQOut;
  wire [9:0]Q;
  wire [9:8]dReg__3_5;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire \dReg_reg[15]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3_5[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3_5[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg__3_5[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg__3_5[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_38
   (Q,
    \dReg_reg[15]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[15]_1 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]Q;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[15]_1 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [9:0]D;
  wire [1:0]DQOut;
  wire [9:0]Q;
  wire [9:8]dReg__4_6;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire \dReg_reg[15]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4_6[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4_6[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg__4_6[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg__4_6[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_39
   (Q,
    \dReg_reg[15]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[15]_1 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]Q;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[15]_1 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [9:0]D;
  wire [1:0]DQOut;
  wire [9:0]Q;
  wire [9:8]dReg__5_7;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire \dReg_reg[15]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5_7[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5_7[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg__5_7[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg__5_7[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_40
   (Q,
    \dReg_reg[15]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[15]_1 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]Q;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[15]_1 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [9:0]D;
  wire [1:0]DQOut;
  wire [9:0]Q;
  wire [9:8]dReg__6_8;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire \dReg_reg[15]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6_8[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6_8[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg__6_8[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg__6_8[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_41
   (Q,
    \dReg_reg[15]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[15]_1 ,
    DMOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]Q;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[15]_1 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [9:0]D;
  wire [1:0]DMOut;
  wire [9:0]Q;
  wire [9:8]dReg__7_9;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire \dReg_reg[15]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7_9[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[15]_1 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7_9[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg__7_9[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg__7_9[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_42
   (Q,
    \dReg_reg[14]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_1 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [10:0]Q;
  output [2:0]\dReg_reg[14]_0 ;
  input [10:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_1 ;
  input [0:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [10:0]D;
  wire [0:0]DQOut;
  wire [10:0]Q;
  wire [9:8]dReg;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [2:0]\dReg_reg[14]_0 ;
  wire \dReg_reg[14]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[14]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[14]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut),
        .Q(\dReg_reg[14]_0 [2]),
        .R(\dReg_reg[14]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_43
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__0;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__0[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__0[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_44
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__1;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__1[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__1[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_45
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__2;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__2[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__2[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_46
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__3;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__3[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__3[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_47
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__4;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__4[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__4[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_48
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__5;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__5[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__5[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_49
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__6;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__6[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__6[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_50
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DMOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DMOut;
  wire [9:8]dReg__7;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__7[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__7[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_51
   (Q,
    \dReg_reg[14]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_1 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [10:0]Q;
  output [2:0]\dReg_reg[14]_0 ;
  input [10:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_1 ;
  input [0:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [10:0]D;
  wire [0:0]DQOut;
  wire [10:0]Q;
  wire [9:8]dReg;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [2:0]\dReg_reg[14]_0 ;
  wire \dReg_reg[14]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[14]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[14]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut),
        .Q(\dReg_reg[14]_0 [2]),
        .R(\dReg_reg[14]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_52
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__0;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__0[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__0[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_53
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__1;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__1[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__1[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_54
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__2;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__2[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__2[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_55
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__3;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__3[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__3[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_56
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__4;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__4[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__4[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_57
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__5;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__5[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__5[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_58
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__6;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__6[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__6[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_59
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DMOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DMOut;
  wire [9:8]dReg__7;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__7[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__7[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_60
   (Q,
    \dReg_reg[14]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_1 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [10:0]Q;
  output [2:0]\dReg_reg[14]_0 ;
  input [10:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_1 ;
  input [0:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [10:0]D;
  wire [0:0]DQOut;
  wire [10:0]Q;
  wire [9:8]dReg;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [2:0]\dReg_reg[14]_0 ;
  wire \dReg_reg[14]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[14]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[14]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut),
        .Q(\dReg_reg[14]_0 [2]),
        .R(\dReg_reg[14]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_61
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__0;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__0[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__0[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_62
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__1;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__1[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__1[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_63
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__2;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__2[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__2[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_64
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__3;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__3[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__3[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_65
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__4;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__4[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__4[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_66
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__5;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__5[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__5[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_67
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__6;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__6[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__6[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_68
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DMOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DMOut;
  wire [9:8]dReg__7;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__7[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__7[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_69
   (Q,
    \dReg_reg[14]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_1 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [10:0]Q;
  output [2:0]\dReg_reg[14]_0 ;
  input [10:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_1 ;
  input [0:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [10:0]D;
  wire [0:0]DQOut;
  wire [10:0]Q;
  wire [9:8]dReg;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [2:0]\dReg_reg[14]_0 ;
  wire \dReg_reg[14]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[14]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[14]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut),
        .Q(\dReg_reg[14]_0 [2]),
        .R(\dReg_reg[14]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_70
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__0;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__0[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__0[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_71
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__1;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__1[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__1[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_72
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__2;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__2[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__2[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_73
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__3;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__3[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__3[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_74
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__4;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__4[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__4[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_75
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__5;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__5[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__5[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_76
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__6;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__6[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__6[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_77
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DMOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DMOut;
  wire [9:8]dReg__7;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__7[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__7[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_78
   (Q,
    \dReg_reg[14]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_1 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [10:0]Q;
  output [2:0]\dReg_reg[14]_0 ;
  input [10:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_1 ;
  input [0:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [10:0]D;
  wire [0:0]DQOut;
  wire [10:0]Q;
  wire [9:8]dReg;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [2:0]\dReg_reg[14]_0 ;
  wire \dReg_reg[14]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[14]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[14]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut),
        .Q(\dReg_reg[14]_0 [2]),
        .R(\dReg_reg[14]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_79
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__0;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__0[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__0[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_80
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__1;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__1[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__1[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_81
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__2;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__2[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__2[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_82
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__3;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__3[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__3[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_83
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__4;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__4[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__4[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_84
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__5;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__5[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__5[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_85
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__6;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__6[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__6[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_86
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DMOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DMOut;
  wire [9:8]dReg__7;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__7[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__7[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_87
   (wrDataVal_reg,
    Q,
    \dReg_reg[14]_0 ,
    \dReg_reg[11]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_1 ,
    DQOut,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output wrDataVal_reg;
  output [10:0]Q;
  output [2:0]\dReg_reg[14]_0 ;
  input \dReg_reg[11]_0 ;
  input [10:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_1 ;
  input [0:0]DQOut;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [10:0]D;
  wire [0:0]DQOut;
  wire [10:0]Q;
  wire [9:8]dReg;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [2:0]\dReg_reg[14]_0 ;
  wire \dReg_reg[14]_1 ;
  wire wrDataVal_reg;

  LUT1 #(
    .INIT(2'h1)) 
    \dReg[11]_i_1 
       (.I0(\dReg_reg[11]_0 ),
        .O(wrDataVal_reg));
  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[14]_0 [0]),
        .R(wrDataVal_reg));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[14]_0 [1]),
        .R(wrDataVal_reg));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut),
        .Q(\dReg_reg[14]_0 [2]),
        .R(\dReg_reg[14]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_88
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__0;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__0[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__0[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_89
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__1;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__1[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__1[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_90
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__2;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__2[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__2[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_91
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__3;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__3[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__3[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__3[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_92
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__4;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__4[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__4[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__4[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_93
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__5;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__5[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__5[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__5[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_94
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__6;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__6[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__6[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__6[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_95
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DMOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;

  wire [1:0]DMOut;
  wire [9:8]dReg__7;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_1 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_1 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[11]_0 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DMOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__7[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__7[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__7[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_96
   (Q,
    \dReg_reg[14]_0 ,
    D,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_1 ,
    DQOut,
    \dReg_reg[10]_1 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_2 );
  output [10:0]Q;
  output [2:0]\dReg_reg[14]_0 ;
  input [10:0]D;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_1 ;
  input [0:0]DQOut;
  input \dReg_reg[10]_1 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_2 ;

  wire [10:0]D;
  wire [0:0]DQOut;
  wire [10:0]Q;
  wire [9:8]dReg;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[11]_0 ;
  wire [2:0]\dReg_reg[14]_0 ;
  wire \dReg_reg[14]_1 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[8]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_2 ),
        .Q(\dReg_reg[14]_0 [0]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_0 ),
        .Q(\dReg_reg[14]_0 [1]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut),
        .Q(\dReg_reg[14]_0 [2]),
        .R(\dReg_reg[14]_1 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg[9]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(dReg[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(dReg[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_97
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[10]_1 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_2 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[10]_1 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_2 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__0;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[11]_0 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_2 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_0 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__0[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__0[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__0[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_98
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[10]_1 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_2 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[10]_1 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_2 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__1;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[11]_0 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_2 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_0 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__1[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__1[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__1[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_bit" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_bit_99
   (\dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[10]_1 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_2 );
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  input [9:0]\dReg_reg[13]_1 ;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[14]_0 ;
  input [1:0]DQOut;
  input \dReg_reg[10]_1 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_2 ;

  wire [1:0]DQOut;
  wire [9:8]dReg__2;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[11]_0 ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15]_0 ;

  FDRE \dReg_reg[0] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[8]),
        .Q(\dReg_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \dReg_reg[10] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[10]_2 ),
        .Q(\dReg_reg[15]_0 [0]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[11] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[11]_0 ),
        .Q(\dReg_reg[15]_0 [1]),
        .R(\dReg_reg[10]_1 ));
  FDRE \dReg_reg[12] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [8]),
        .Q(\dReg_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \dReg_reg[13] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [9]),
        .Q(\dReg_reg[13]_0 [9]),
        .R(1'b0));
  FDRE \dReg_reg[14] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[0]),
        .Q(\dReg_reg[15]_0 [2]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[15] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(DQOut[1]),
        .Q(\dReg_reg[15]_0 [3]),
        .R(\dReg_reg[14]_0 ));
  FDRE \dReg_reg[1] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(dReg__2[9]),
        .Q(\dReg_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \dReg_reg[2] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [0]),
        .Q(\dReg_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \dReg_reg[3] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [1]),
        .Q(\dReg_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \dReg_reg[4] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [2]),
        .Q(\dReg_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \dReg_reg[5] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [3]),
        .Q(\dReg_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \dReg_reg[6] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [4]),
        .Q(\dReg_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \dReg_reg[7] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [5]),
        .Q(\dReg_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \dReg_reg[8] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [6]),
        .Q(dReg__2[8]),
        .R(1'b0));
  FDRE \dReg_reg[9] 
       (.C(\dReg_reg[10]_0 ),
        .CE(1'b1),
        .D(\dReg_reg[13]_1 [7]),
        .Q(dReg__2[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_byte" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_byte
   (Q,
    \dReg_reg[14] ,
    \dReg_reg[13] ,
    \dReg_reg[15] ,
    \dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[15]_1 ,
    \dReg_reg[13]_2 ,
    \dReg_reg[15]_2 ,
    \dReg_reg[13]_3 ,
    \dReg_reg[15]_3 ,
    \dReg_reg[13]_4 ,
    \dReg_reg[15]_4 ,
    \dReg_reg[13]_5 ,
    \dReg_reg[15]_5 ,
    \dReg_reg[13]_6 ,
    \dReg_reg[15]_6 ,
    D,
    \dReg_reg[10] ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[10]_0 ,
    \dReg_reg[11] ,
    \dReg_reg[10]_1 ,
    \dReg_reg[13]_7 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_2 ,
    \dReg_reg[13]_8 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_3 ,
    \dReg_reg[13]_9 ,
    \dReg_reg[11]_2 ,
    \dReg_reg[10]_4 ,
    \dReg_reg[13]_10 ,
    \dReg_reg[11]_3 ,
    \dReg_reg[10]_5 ,
    \dReg_reg[13]_11 ,
    \dReg_reg[11]_4 ,
    \dReg_reg[10]_6 ,
    \dReg_reg[13]_12 ,
    \dReg_reg[11]_5 ,
    \dReg_reg[10]_7 ,
    \dReg_reg[13]_13 ,
    \dReg_reg[11]_6 ,
    \dReg_reg[10]_8 ,
    \dReg_reg[13]_14 ,
    DMOut,
    \dReg_reg[11]_7 ,
    \dReg_reg[10]_9 );
  output [10:0]Q;
  output [2:0]\dReg_reg[14] ;
  output [9:0]\dReg_reg[13] ;
  output [3:0]\dReg_reg[15] ;
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  output [9:0]\dReg_reg[13]_1 ;
  output [3:0]\dReg_reg[15]_1 ;
  output [9:0]\dReg_reg[13]_2 ;
  output [3:0]\dReg_reg[15]_2 ;
  output [9:0]\dReg_reg[13]_3 ;
  output [3:0]\dReg_reg[15]_3 ;
  output [9:0]\dReg_reg[13]_4 ;
  output [3:0]\dReg_reg[15]_4 ;
  output [9:0]\dReg_reg[13]_5 ;
  output [3:0]\dReg_reg[15]_5 ;
  output [9:0]\dReg_reg[13]_6 ;
  output [3:0]\dReg_reg[15]_6 ;
  input [10:0]D;
  input \dReg_reg[10] ;
  input \dReg_reg[14]_0 ;
  input [14:0]DQOut;
  input \dReg_reg[10]_0 ;
  input \dReg_reg[11] ;
  input \dReg_reg[10]_1 ;
  input [9:0]\dReg_reg[13]_7 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_2 ;
  input [9:0]\dReg_reg[13]_8 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_3 ;
  input [9:0]\dReg_reg[13]_9 ;
  input \dReg_reg[11]_2 ;
  input \dReg_reg[10]_4 ;
  input [9:0]\dReg_reg[13]_10 ;
  input \dReg_reg[11]_3 ;
  input \dReg_reg[10]_5 ;
  input [9:0]\dReg_reg[13]_11 ;
  input \dReg_reg[11]_4 ;
  input \dReg_reg[10]_6 ;
  input [9:0]\dReg_reg[13]_12 ;
  input \dReg_reg[11]_5 ;
  input \dReg_reg[10]_7 ;
  input [9:0]\dReg_reg[13]_13 ;
  input \dReg_reg[11]_6 ;
  input \dReg_reg[10]_8 ;
  input [9:0]\dReg_reg[13]_14 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_7 ;
  input \dReg_reg[10]_9 ;

  wire [10:0]D;
  wire [1:0]DMOut;
  wire [14:0]DQOut;
  wire [10:0]Q;
  wire \dReg_reg[10] ;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[10]_3 ;
  wire \dReg_reg[10]_4 ;
  wire \dReg_reg[10]_5 ;
  wire \dReg_reg[10]_6 ;
  wire \dReg_reg[10]_7 ;
  wire \dReg_reg[10]_8 ;
  wire \dReg_reg[10]_9 ;
  wire \dReg_reg[11] ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire \dReg_reg[11]_2 ;
  wire \dReg_reg[11]_3 ;
  wire \dReg_reg[11]_4 ;
  wire \dReg_reg[11]_5 ;
  wire \dReg_reg[11]_6 ;
  wire \dReg_reg[11]_7 ;
  wire [9:0]\dReg_reg[13] ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire [9:0]\dReg_reg[13]_10 ;
  wire [9:0]\dReg_reg[13]_11 ;
  wire [9:0]\dReg_reg[13]_12 ;
  wire [9:0]\dReg_reg[13]_13 ;
  wire [9:0]\dReg_reg[13]_14 ;
  wire [9:0]\dReg_reg[13]_2 ;
  wire [9:0]\dReg_reg[13]_3 ;
  wire [9:0]\dReg_reg[13]_4 ;
  wire [9:0]\dReg_reg[13]_5 ;
  wire [9:0]\dReg_reg[13]_6 ;
  wire [9:0]\dReg_reg[13]_7 ;
  wire [9:0]\dReg_reg[13]_8 ;
  wire [9:0]\dReg_reg[13]_9 ;
  wire [2:0]\dReg_reg[14] ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15] ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire [3:0]\dReg_reg[15]_1 ;
  wire [3:0]\dReg_reg[15]_2 ;
  wire [3:0]\dReg_reg[15]_3 ;
  wire [3:0]\dReg_reg[15]_4 ;
  wire [3:0]\dReg_reg[15]_5 ;
  wire [3:0]\dReg_reg[15]_6 ;

  ddr4_0_ddr4_v2_2_17_cal_wr_bit_96 \genBit[0].u_ddr_mc_wr_bit 
       (.D(D),
        .DQOut(DQOut[0]),
        .Q(Q),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_1 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[14]_0 (\dReg_reg[14] ),
        .\dReg_reg[14]_1 (\dReg_reg[14]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_97 \genBit[1].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[2:1]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_2 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_0 ),
        .\dReg_reg[13]_0 (\dReg_reg[13] ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_7 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15] ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_98 \genBit[2].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[4:3]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_3 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_1 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_0 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_8 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_99 \genBit[3].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[6:5]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_4 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_2 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_1 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_9 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_1 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_100 \genBit[4].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[8:7]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_5 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_3 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_2 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_10 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_2 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_101 \genBit[5].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[10:9]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_6 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_4 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_3 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_11 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_3 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_102 \genBit[6].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[12:11]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_7 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_5 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_4 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_12 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_4 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_103 \genBit[7].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[14:13]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_8 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_6 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_5 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_13 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_5 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_104 u_ddr_mc_wr_dm
       (.DMOut(DMOut),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_9 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_7 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_6 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_14 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_6 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_byte" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_byte_27
   (wrDataVal_reg,
    Q,
    \dReg_reg[14] ,
    \dReg_reg[13] ,
    \dReg_reg[15] ,
    \dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[15]_1 ,
    \dReg_reg[13]_2 ,
    \dReg_reg[15]_2 ,
    \dReg_reg[13]_3 ,
    \dReg_reg[15]_3 ,
    \dReg_reg[13]_4 ,
    \dReg_reg[15]_4 ,
    \dReg_reg[13]_5 ,
    \dReg_reg[15]_5 ,
    \dReg_reg[13]_6 ,
    \dReg_reg[15]_6 ,
    \dReg_reg[11] ,
    D,
    \dReg_reg[10] ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[13]_7 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 ,
    \dReg_reg[13]_8 ,
    \dReg_reg[11]_2 ,
    \dReg_reg[10]_2 ,
    \dReg_reg[13]_9 ,
    \dReg_reg[11]_3 ,
    \dReg_reg[10]_3 ,
    \dReg_reg[13]_10 ,
    \dReg_reg[11]_4 ,
    \dReg_reg[10]_4 ,
    \dReg_reg[13]_11 ,
    \dReg_reg[11]_5 ,
    \dReg_reg[10]_5 ,
    \dReg_reg[13]_12 ,
    \dReg_reg[11]_6 ,
    \dReg_reg[10]_6 ,
    \dReg_reg[13]_13 ,
    \dReg_reg[11]_7 ,
    \dReg_reg[10]_7 ,
    \dReg_reg[13]_14 ,
    DMOut,
    \dReg_reg[11]_8 ,
    \dReg_reg[10]_8 );
  output wrDataVal_reg;
  output [10:0]Q;
  output [2:0]\dReg_reg[14] ;
  output [9:0]\dReg_reg[13] ;
  output [3:0]\dReg_reg[15] ;
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  output [9:0]\dReg_reg[13]_1 ;
  output [3:0]\dReg_reg[15]_1 ;
  output [9:0]\dReg_reg[13]_2 ;
  output [3:0]\dReg_reg[15]_2 ;
  output [9:0]\dReg_reg[13]_3 ;
  output [3:0]\dReg_reg[15]_3 ;
  output [9:0]\dReg_reg[13]_4 ;
  output [3:0]\dReg_reg[15]_4 ;
  output [9:0]\dReg_reg[13]_5 ;
  output [3:0]\dReg_reg[15]_5 ;
  output [9:0]\dReg_reg[13]_6 ;
  output [3:0]\dReg_reg[15]_6 ;
  input \dReg_reg[11] ;
  input [10:0]D;
  input \dReg_reg[10] ;
  input \dReg_reg[14]_0 ;
  input [14:0]DQOut;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_0 ;
  input [9:0]\dReg_reg[13]_7 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;
  input [9:0]\dReg_reg[13]_8 ;
  input \dReg_reg[11]_2 ;
  input \dReg_reg[10]_2 ;
  input [9:0]\dReg_reg[13]_9 ;
  input \dReg_reg[11]_3 ;
  input \dReg_reg[10]_3 ;
  input [9:0]\dReg_reg[13]_10 ;
  input \dReg_reg[11]_4 ;
  input \dReg_reg[10]_4 ;
  input [9:0]\dReg_reg[13]_11 ;
  input \dReg_reg[11]_5 ;
  input \dReg_reg[10]_5 ;
  input [9:0]\dReg_reg[13]_12 ;
  input \dReg_reg[11]_6 ;
  input \dReg_reg[10]_6 ;
  input [9:0]\dReg_reg[13]_13 ;
  input \dReg_reg[11]_7 ;
  input \dReg_reg[10]_7 ;
  input [9:0]\dReg_reg[13]_14 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_8 ;
  input \dReg_reg[10]_8 ;

  wire [10:0]D;
  wire [1:0]DMOut;
  wire [14:0]DQOut;
  wire [10:0]Q;
  wire \dReg_reg[10] ;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[10]_3 ;
  wire \dReg_reg[10]_4 ;
  wire \dReg_reg[10]_5 ;
  wire \dReg_reg[10]_6 ;
  wire \dReg_reg[10]_7 ;
  wire \dReg_reg[10]_8 ;
  wire \dReg_reg[11] ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire \dReg_reg[11]_2 ;
  wire \dReg_reg[11]_3 ;
  wire \dReg_reg[11]_4 ;
  wire \dReg_reg[11]_5 ;
  wire \dReg_reg[11]_6 ;
  wire \dReg_reg[11]_7 ;
  wire \dReg_reg[11]_8 ;
  wire [9:0]\dReg_reg[13] ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire [9:0]\dReg_reg[13]_10 ;
  wire [9:0]\dReg_reg[13]_11 ;
  wire [9:0]\dReg_reg[13]_12 ;
  wire [9:0]\dReg_reg[13]_13 ;
  wire [9:0]\dReg_reg[13]_14 ;
  wire [9:0]\dReg_reg[13]_2 ;
  wire [9:0]\dReg_reg[13]_3 ;
  wire [9:0]\dReg_reg[13]_4 ;
  wire [9:0]\dReg_reg[13]_5 ;
  wire [9:0]\dReg_reg[13]_6 ;
  wire [9:0]\dReg_reg[13]_7 ;
  wire [9:0]\dReg_reg[13]_8 ;
  wire [9:0]\dReg_reg[13]_9 ;
  wire [2:0]\dReg_reg[14] ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15] ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire [3:0]\dReg_reg[15]_1 ;
  wire [3:0]\dReg_reg[15]_2 ;
  wire [3:0]\dReg_reg[15]_3 ;
  wire [3:0]\dReg_reg[15]_4 ;
  wire [3:0]\dReg_reg[15]_5 ;
  wire [3:0]\dReg_reg[15]_6 ;
  wire wrDataVal_reg;

  ddr4_0_ddr4_v2_2_17_cal_wr_bit_87 \genBit[0].u_ddr_mc_wr_bit 
       (.D(D),
        .DQOut(DQOut[0]),
        .Q(Q),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_0 ),
        .\dReg_reg[14]_0 (\dReg_reg[14] ),
        .\dReg_reg[14]_1 (\dReg_reg[14]_0 ),
        .wrDataVal_reg(wrDataVal_reg));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_88 \genBit[1].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[2:1]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_1 ),
        .\dReg_reg[11]_0 (wrDataVal_reg),
        .\dReg_reg[11]_1 (\dReg_reg[11]_1 ),
        .\dReg_reg[13]_0 (\dReg_reg[13] ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_7 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15] ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_89 \genBit[2].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[4:3]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_2 ),
        .\dReg_reg[11]_0 (wrDataVal_reg),
        .\dReg_reg[11]_1 (\dReg_reg[11]_2 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_0 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_8 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_90 \genBit[3].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[6:5]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_3 ),
        .\dReg_reg[11]_0 (wrDataVal_reg),
        .\dReg_reg[11]_1 (\dReg_reg[11]_3 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_1 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_9 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_1 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_91 \genBit[4].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[8:7]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_4 ),
        .\dReg_reg[11]_0 (wrDataVal_reg),
        .\dReg_reg[11]_1 (\dReg_reg[11]_4 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_2 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_10 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_2 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_92 \genBit[5].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[10:9]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_5 ),
        .\dReg_reg[11]_0 (wrDataVal_reg),
        .\dReg_reg[11]_1 (\dReg_reg[11]_5 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_3 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_11 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_3 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_93 \genBit[6].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[12:11]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_6 ),
        .\dReg_reg[11]_0 (wrDataVal_reg),
        .\dReg_reg[11]_1 (\dReg_reg[11]_6 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_4 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_12 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_4 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_94 \genBit[7].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[14:13]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_7 ),
        .\dReg_reg[11]_0 (wrDataVal_reg),
        .\dReg_reg[11]_1 (\dReg_reg[11]_7 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_5 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_13 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_5 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_95 u_ddr_mc_wr_dm
       (.DMOut(DMOut),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_8 ),
        .\dReg_reg[11]_0 (wrDataVal_reg),
        .\dReg_reg[11]_1 (\dReg_reg[11]_8 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_6 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_14 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_6 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_byte" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_byte_28
   (Q,
    \dReg_reg[14] ,
    \dReg_reg[13] ,
    \dReg_reg[15] ,
    \dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[15]_1 ,
    \dReg_reg[13]_2 ,
    \dReg_reg[15]_2 ,
    \dReg_reg[13]_3 ,
    \dReg_reg[15]_3 ,
    \dReg_reg[13]_4 ,
    \dReg_reg[15]_4 ,
    \dReg_reg[13]_5 ,
    \dReg_reg[15]_5 ,
    \dReg_reg[13]_6 ,
    \dReg_reg[15]_6 ,
    D,
    \dReg_reg[10] ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11] ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[13]_7 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 ,
    \dReg_reg[13]_8 ,
    \dReg_reg[11]_2 ,
    \dReg_reg[10]_2 ,
    \dReg_reg[13]_9 ,
    \dReg_reg[11]_3 ,
    \dReg_reg[10]_3 ,
    \dReg_reg[13]_10 ,
    \dReg_reg[11]_4 ,
    \dReg_reg[10]_4 ,
    \dReg_reg[13]_11 ,
    \dReg_reg[11]_5 ,
    \dReg_reg[10]_5 ,
    \dReg_reg[13]_12 ,
    \dReg_reg[11]_6 ,
    \dReg_reg[10]_6 ,
    \dReg_reg[13]_13 ,
    \dReg_reg[11]_7 ,
    \dReg_reg[10]_7 ,
    \dReg_reg[13]_14 ,
    DMOut,
    \dReg_reg[11]_8 ,
    \dReg_reg[10]_8 );
  output [10:0]Q;
  output [2:0]\dReg_reg[14] ;
  output [9:0]\dReg_reg[13] ;
  output [3:0]\dReg_reg[15] ;
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  output [9:0]\dReg_reg[13]_1 ;
  output [3:0]\dReg_reg[15]_1 ;
  output [9:0]\dReg_reg[13]_2 ;
  output [3:0]\dReg_reg[15]_2 ;
  output [9:0]\dReg_reg[13]_3 ;
  output [3:0]\dReg_reg[15]_3 ;
  output [9:0]\dReg_reg[13]_4 ;
  output [3:0]\dReg_reg[15]_4 ;
  output [9:0]\dReg_reg[13]_5 ;
  output [3:0]\dReg_reg[15]_5 ;
  output [9:0]\dReg_reg[13]_6 ;
  output [3:0]\dReg_reg[15]_6 ;
  input [10:0]D;
  input \dReg_reg[10] ;
  input \dReg_reg[14]_0 ;
  input [14:0]DQOut;
  input \dReg_reg[11] ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_0 ;
  input [9:0]\dReg_reg[13]_7 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;
  input [9:0]\dReg_reg[13]_8 ;
  input \dReg_reg[11]_2 ;
  input \dReg_reg[10]_2 ;
  input [9:0]\dReg_reg[13]_9 ;
  input \dReg_reg[11]_3 ;
  input \dReg_reg[10]_3 ;
  input [9:0]\dReg_reg[13]_10 ;
  input \dReg_reg[11]_4 ;
  input \dReg_reg[10]_4 ;
  input [9:0]\dReg_reg[13]_11 ;
  input \dReg_reg[11]_5 ;
  input \dReg_reg[10]_5 ;
  input [9:0]\dReg_reg[13]_12 ;
  input \dReg_reg[11]_6 ;
  input \dReg_reg[10]_6 ;
  input [9:0]\dReg_reg[13]_13 ;
  input \dReg_reg[11]_7 ;
  input \dReg_reg[10]_7 ;
  input [9:0]\dReg_reg[13]_14 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_8 ;
  input \dReg_reg[10]_8 ;

  wire [10:0]D;
  wire [1:0]DMOut;
  wire [14:0]DQOut;
  wire [10:0]Q;
  wire \dReg_reg[10] ;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[10]_3 ;
  wire \dReg_reg[10]_4 ;
  wire \dReg_reg[10]_5 ;
  wire \dReg_reg[10]_6 ;
  wire \dReg_reg[10]_7 ;
  wire \dReg_reg[10]_8 ;
  wire \dReg_reg[11] ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire \dReg_reg[11]_2 ;
  wire \dReg_reg[11]_3 ;
  wire \dReg_reg[11]_4 ;
  wire \dReg_reg[11]_5 ;
  wire \dReg_reg[11]_6 ;
  wire \dReg_reg[11]_7 ;
  wire \dReg_reg[11]_8 ;
  wire [9:0]\dReg_reg[13] ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire [9:0]\dReg_reg[13]_10 ;
  wire [9:0]\dReg_reg[13]_11 ;
  wire [9:0]\dReg_reg[13]_12 ;
  wire [9:0]\dReg_reg[13]_13 ;
  wire [9:0]\dReg_reg[13]_14 ;
  wire [9:0]\dReg_reg[13]_2 ;
  wire [9:0]\dReg_reg[13]_3 ;
  wire [9:0]\dReg_reg[13]_4 ;
  wire [9:0]\dReg_reg[13]_5 ;
  wire [9:0]\dReg_reg[13]_6 ;
  wire [9:0]\dReg_reg[13]_7 ;
  wire [9:0]\dReg_reg[13]_8 ;
  wire [9:0]\dReg_reg[13]_9 ;
  wire [2:0]\dReg_reg[14] ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15] ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire [3:0]\dReg_reg[15]_1 ;
  wire [3:0]\dReg_reg[15]_2 ;
  wire [3:0]\dReg_reg[15]_3 ;
  wire [3:0]\dReg_reg[15]_4 ;
  wire [3:0]\dReg_reg[15]_5 ;
  wire [3:0]\dReg_reg[15]_6 ;

  ddr4_0_ddr4_v2_2_17_cal_wr_bit_78 \genBit[0].u_ddr_mc_wr_bit 
       (.D(D),
        .DQOut(DQOut[0]),
        .Q(Q),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_0 ),
        .\dReg_reg[14]_0 (\dReg_reg[14] ),
        .\dReg_reg[14]_1 (\dReg_reg[14]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_79 \genBit[1].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[2:1]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_1 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_1 ),
        .\dReg_reg[13]_0 (\dReg_reg[13] ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_7 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15] ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_80 \genBit[2].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[4:3]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_2 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_2 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_0 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_8 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_81 \genBit[3].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[6:5]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_3 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_3 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_1 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_9 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_1 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_82 \genBit[4].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[8:7]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_4 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_4 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_2 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_10 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_2 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_83 \genBit[5].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[10:9]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_5 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_5 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_3 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_11 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_3 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_84 \genBit[6].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[12:11]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_6 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_6 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_4 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_12 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_4 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_85 \genBit[7].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[14:13]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_7 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_7 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_5 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_13 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_5 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_86 u_ddr_mc_wr_dm
       (.DMOut(DMOut),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_8 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_8 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_6 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_14 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_6 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_byte" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_byte_29
   (Q,
    \dReg_reg[14] ,
    \dReg_reg[13] ,
    \dReg_reg[15] ,
    \dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[15]_1 ,
    \dReg_reg[13]_2 ,
    \dReg_reg[15]_2 ,
    \dReg_reg[13]_3 ,
    \dReg_reg[15]_3 ,
    \dReg_reg[13]_4 ,
    \dReg_reg[15]_4 ,
    \dReg_reg[13]_5 ,
    \dReg_reg[15]_5 ,
    \dReg_reg[13]_6 ,
    \dReg_reg[15]_6 ,
    D,
    \dReg_reg[10] ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11] ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[13]_7 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 ,
    \dReg_reg[13]_8 ,
    \dReg_reg[11]_2 ,
    \dReg_reg[10]_2 ,
    \dReg_reg[13]_9 ,
    \dReg_reg[11]_3 ,
    \dReg_reg[10]_3 ,
    \dReg_reg[13]_10 ,
    \dReg_reg[11]_4 ,
    \dReg_reg[10]_4 ,
    \dReg_reg[13]_11 ,
    \dReg_reg[11]_5 ,
    \dReg_reg[10]_5 ,
    \dReg_reg[13]_12 ,
    \dReg_reg[11]_6 ,
    \dReg_reg[10]_6 ,
    \dReg_reg[13]_13 ,
    \dReg_reg[11]_7 ,
    \dReg_reg[10]_7 ,
    \dReg_reg[13]_14 ,
    DMOut,
    \dReg_reg[11]_8 ,
    \dReg_reg[10]_8 );
  output [10:0]Q;
  output [2:0]\dReg_reg[14] ;
  output [9:0]\dReg_reg[13] ;
  output [3:0]\dReg_reg[15] ;
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  output [9:0]\dReg_reg[13]_1 ;
  output [3:0]\dReg_reg[15]_1 ;
  output [9:0]\dReg_reg[13]_2 ;
  output [3:0]\dReg_reg[15]_2 ;
  output [9:0]\dReg_reg[13]_3 ;
  output [3:0]\dReg_reg[15]_3 ;
  output [9:0]\dReg_reg[13]_4 ;
  output [3:0]\dReg_reg[15]_4 ;
  output [9:0]\dReg_reg[13]_5 ;
  output [3:0]\dReg_reg[15]_5 ;
  output [9:0]\dReg_reg[13]_6 ;
  output [3:0]\dReg_reg[15]_6 ;
  input [10:0]D;
  input \dReg_reg[10] ;
  input \dReg_reg[14]_0 ;
  input [14:0]DQOut;
  input \dReg_reg[11] ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_0 ;
  input [9:0]\dReg_reg[13]_7 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;
  input [9:0]\dReg_reg[13]_8 ;
  input \dReg_reg[11]_2 ;
  input \dReg_reg[10]_2 ;
  input [9:0]\dReg_reg[13]_9 ;
  input \dReg_reg[11]_3 ;
  input \dReg_reg[10]_3 ;
  input [9:0]\dReg_reg[13]_10 ;
  input \dReg_reg[11]_4 ;
  input \dReg_reg[10]_4 ;
  input [9:0]\dReg_reg[13]_11 ;
  input \dReg_reg[11]_5 ;
  input \dReg_reg[10]_5 ;
  input [9:0]\dReg_reg[13]_12 ;
  input \dReg_reg[11]_6 ;
  input \dReg_reg[10]_6 ;
  input [9:0]\dReg_reg[13]_13 ;
  input \dReg_reg[11]_7 ;
  input \dReg_reg[10]_7 ;
  input [9:0]\dReg_reg[13]_14 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_8 ;
  input \dReg_reg[10]_8 ;

  wire [10:0]D;
  wire [1:0]DMOut;
  wire [14:0]DQOut;
  wire [10:0]Q;
  wire \dReg_reg[10] ;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[10]_3 ;
  wire \dReg_reg[10]_4 ;
  wire \dReg_reg[10]_5 ;
  wire \dReg_reg[10]_6 ;
  wire \dReg_reg[10]_7 ;
  wire \dReg_reg[10]_8 ;
  wire \dReg_reg[11] ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire \dReg_reg[11]_2 ;
  wire \dReg_reg[11]_3 ;
  wire \dReg_reg[11]_4 ;
  wire \dReg_reg[11]_5 ;
  wire \dReg_reg[11]_6 ;
  wire \dReg_reg[11]_7 ;
  wire \dReg_reg[11]_8 ;
  wire [9:0]\dReg_reg[13] ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire [9:0]\dReg_reg[13]_10 ;
  wire [9:0]\dReg_reg[13]_11 ;
  wire [9:0]\dReg_reg[13]_12 ;
  wire [9:0]\dReg_reg[13]_13 ;
  wire [9:0]\dReg_reg[13]_14 ;
  wire [9:0]\dReg_reg[13]_2 ;
  wire [9:0]\dReg_reg[13]_3 ;
  wire [9:0]\dReg_reg[13]_4 ;
  wire [9:0]\dReg_reg[13]_5 ;
  wire [9:0]\dReg_reg[13]_6 ;
  wire [9:0]\dReg_reg[13]_7 ;
  wire [9:0]\dReg_reg[13]_8 ;
  wire [9:0]\dReg_reg[13]_9 ;
  wire [2:0]\dReg_reg[14] ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15] ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire [3:0]\dReg_reg[15]_1 ;
  wire [3:0]\dReg_reg[15]_2 ;
  wire [3:0]\dReg_reg[15]_3 ;
  wire [3:0]\dReg_reg[15]_4 ;
  wire [3:0]\dReg_reg[15]_5 ;
  wire [3:0]\dReg_reg[15]_6 ;

  ddr4_0_ddr4_v2_2_17_cal_wr_bit_69 \genBit[0].u_ddr_mc_wr_bit 
       (.D(D),
        .DQOut(DQOut[0]),
        .Q(Q),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_0 ),
        .\dReg_reg[14]_0 (\dReg_reg[14] ),
        .\dReg_reg[14]_1 (\dReg_reg[14]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_70 \genBit[1].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[2:1]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_1 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_1 ),
        .\dReg_reg[13]_0 (\dReg_reg[13] ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_7 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15] ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_71 \genBit[2].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[4:3]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_2 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_2 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_0 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_8 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_72 \genBit[3].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[6:5]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_3 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_3 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_1 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_9 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_1 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_73 \genBit[4].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[8:7]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_4 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_4 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_2 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_10 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_2 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_74 \genBit[5].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[10:9]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_5 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_5 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_3 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_11 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_3 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_75 \genBit[6].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[12:11]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_6 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_6 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_4 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_12 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_4 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_76 \genBit[7].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[14:13]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_7 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_7 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_5 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_13 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_5 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_77 u_ddr_mc_wr_dm
       (.DMOut(DMOut),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_8 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_8 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_6 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_14 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_6 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_byte" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_byte_30
   (Q,
    \dReg_reg[14] ,
    \dReg_reg[13] ,
    \dReg_reg[15] ,
    \dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[15]_1 ,
    \dReg_reg[13]_2 ,
    \dReg_reg[15]_2 ,
    \dReg_reg[13]_3 ,
    \dReg_reg[15]_3 ,
    \dReg_reg[13]_4 ,
    \dReg_reg[15]_4 ,
    \dReg_reg[13]_5 ,
    \dReg_reg[15]_5 ,
    \dReg_reg[13]_6 ,
    \dReg_reg[15]_6 ,
    D,
    \dReg_reg[10] ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11] ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[13]_7 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 ,
    \dReg_reg[13]_8 ,
    \dReg_reg[11]_2 ,
    \dReg_reg[10]_2 ,
    \dReg_reg[13]_9 ,
    \dReg_reg[11]_3 ,
    \dReg_reg[10]_3 ,
    \dReg_reg[13]_10 ,
    \dReg_reg[11]_4 ,
    \dReg_reg[10]_4 ,
    \dReg_reg[13]_11 ,
    \dReg_reg[11]_5 ,
    \dReg_reg[10]_5 ,
    \dReg_reg[13]_12 ,
    \dReg_reg[11]_6 ,
    \dReg_reg[10]_6 ,
    \dReg_reg[13]_13 ,
    \dReg_reg[11]_7 ,
    \dReg_reg[10]_7 ,
    \dReg_reg[13]_14 ,
    DMOut,
    \dReg_reg[11]_8 ,
    \dReg_reg[10]_8 );
  output [10:0]Q;
  output [2:0]\dReg_reg[14] ;
  output [9:0]\dReg_reg[13] ;
  output [3:0]\dReg_reg[15] ;
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  output [9:0]\dReg_reg[13]_1 ;
  output [3:0]\dReg_reg[15]_1 ;
  output [9:0]\dReg_reg[13]_2 ;
  output [3:0]\dReg_reg[15]_2 ;
  output [9:0]\dReg_reg[13]_3 ;
  output [3:0]\dReg_reg[15]_3 ;
  output [9:0]\dReg_reg[13]_4 ;
  output [3:0]\dReg_reg[15]_4 ;
  output [9:0]\dReg_reg[13]_5 ;
  output [3:0]\dReg_reg[15]_5 ;
  output [9:0]\dReg_reg[13]_6 ;
  output [3:0]\dReg_reg[15]_6 ;
  input [10:0]D;
  input \dReg_reg[10] ;
  input \dReg_reg[14]_0 ;
  input [14:0]DQOut;
  input \dReg_reg[11] ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_0 ;
  input [9:0]\dReg_reg[13]_7 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;
  input [9:0]\dReg_reg[13]_8 ;
  input \dReg_reg[11]_2 ;
  input \dReg_reg[10]_2 ;
  input [9:0]\dReg_reg[13]_9 ;
  input \dReg_reg[11]_3 ;
  input \dReg_reg[10]_3 ;
  input [9:0]\dReg_reg[13]_10 ;
  input \dReg_reg[11]_4 ;
  input \dReg_reg[10]_4 ;
  input [9:0]\dReg_reg[13]_11 ;
  input \dReg_reg[11]_5 ;
  input \dReg_reg[10]_5 ;
  input [9:0]\dReg_reg[13]_12 ;
  input \dReg_reg[11]_6 ;
  input \dReg_reg[10]_6 ;
  input [9:0]\dReg_reg[13]_13 ;
  input \dReg_reg[11]_7 ;
  input \dReg_reg[10]_7 ;
  input [9:0]\dReg_reg[13]_14 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_8 ;
  input \dReg_reg[10]_8 ;

  wire [10:0]D;
  wire [1:0]DMOut;
  wire [14:0]DQOut;
  wire [10:0]Q;
  wire \dReg_reg[10] ;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[10]_3 ;
  wire \dReg_reg[10]_4 ;
  wire \dReg_reg[10]_5 ;
  wire \dReg_reg[10]_6 ;
  wire \dReg_reg[10]_7 ;
  wire \dReg_reg[10]_8 ;
  wire \dReg_reg[11] ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire \dReg_reg[11]_2 ;
  wire \dReg_reg[11]_3 ;
  wire \dReg_reg[11]_4 ;
  wire \dReg_reg[11]_5 ;
  wire \dReg_reg[11]_6 ;
  wire \dReg_reg[11]_7 ;
  wire \dReg_reg[11]_8 ;
  wire [9:0]\dReg_reg[13] ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire [9:0]\dReg_reg[13]_10 ;
  wire [9:0]\dReg_reg[13]_11 ;
  wire [9:0]\dReg_reg[13]_12 ;
  wire [9:0]\dReg_reg[13]_13 ;
  wire [9:0]\dReg_reg[13]_14 ;
  wire [9:0]\dReg_reg[13]_2 ;
  wire [9:0]\dReg_reg[13]_3 ;
  wire [9:0]\dReg_reg[13]_4 ;
  wire [9:0]\dReg_reg[13]_5 ;
  wire [9:0]\dReg_reg[13]_6 ;
  wire [9:0]\dReg_reg[13]_7 ;
  wire [9:0]\dReg_reg[13]_8 ;
  wire [9:0]\dReg_reg[13]_9 ;
  wire [2:0]\dReg_reg[14] ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15] ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire [3:0]\dReg_reg[15]_1 ;
  wire [3:0]\dReg_reg[15]_2 ;
  wire [3:0]\dReg_reg[15]_3 ;
  wire [3:0]\dReg_reg[15]_4 ;
  wire [3:0]\dReg_reg[15]_5 ;
  wire [3:0]\dReg_reg[15]_6 ;

  ddr4_0_ddr4_v2_2_17_cal_wr_bit_60 \genBit[0].u_ddr_mc_wr_bit 
       (.D(D),
        .DQOut(DQOut[0]),
        .Q(Q),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_0 ),
        .\dReg_reg[14]_0 (\dReg_reg[14] ),
        .\dReg_reg[14]_1 (\dReg_reg[14]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_61 \genBit[1].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[2:1]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_1 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_1 ),
        .\dReg_reg[13]_0 (\dReg_reg[13] ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_7 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15] ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_62 \genBit[2].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[4:3]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_2 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_2 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_0 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_8 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_63 \genBit[3].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[6:5]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_3 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_3 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_1 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_9 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_1 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_64 \genBit[4].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[8:7]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_4 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_4 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_2 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_10 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_2 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_65 \genBit[5].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[10:9]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_5 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_5 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_3 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_11 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_3 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_66 \genBit[6].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[12:11]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_6 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_6 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_4 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_12 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_4 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_67 \genBit[7].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[14:13]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_7 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_7 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_5 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_13 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_5 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_68 u_ddr_mc_wr_dm
       (.DMOut(DMOut),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_8 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_8 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_6 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_14 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_6 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_byte" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_byte_31
   (Q,
    \dReg_reg[14] ,
    \dReg_reg[13] ,
    \dReg_reg[15] ,
    \dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[15]_1 ,
    \dReg_reg[13]_2 ,
    \dReg_reg[15]_2 ,
    \dReg_reg[13]_3 ,
    \dReg_reg[15]_3 ,
    \dReg_reg[13]_4 ,
    \dReg_reg[15]_4 ,
    \dReg_reg[13]_5 ,
    \dReg_reg[15]_5 ,
    \dReg_reg[13]_6 ,
    \dReg_reg[15]_6 ,
    D,
    \dReg_reg[10] ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11] ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[13]_7 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 ,
    \dReg_reg[13]_8 ,
    \dReg_reg[11]_2 ,
    \dReg_reg[10]_2 ,
    \dReg_reg[13]_9 ,
    \dReg_reg[11]_3 ,
    \dReg_reg[10]_3 ,
    \dReg_reg[13]_10 ,
    \dReg_reg[11]_4 ,
    \dReg_reg[10]_4 ,
    \dReg_reg[13]_11 ,
    \dReg_reg[11]_5 ,
    \dReg_reg[10]_5 ,
    \dReg_reg[13]_12 ,
    \dReg_reg[11]_6 ,
    \dReg_reg[10]_6 ,
    \dReg_reg[13]_13 ,
    \dReg_reg[11]_7 ,
    \dReg_reg[10]_7 ,
    \dReg_reg[13]_14 ,
    DMOut,
    \dReg_reg[11]_8 ,
    \dReg_reg[10]_8 );
  output [10:0]Q;
  output [2:0]\dReg_reg[14] ;
  output [9:0]\dReg_reg[13] ;
  output [3:0]\dReg_reg[15] ;
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  output [9:0]\dReg_reg[13]_1 ;
  output [3:0]\dReg_reg[15]_1 ;
  output [9:0]\dReg_reg[13]_2 ;
  output [3:0]\dReg_reg[15]_2 ;
  output [9:0]\dReg_reg[13]_3 ;
  output [3:0]\dReg_reg[15]_3 ;
  output [9:0]\dReg_reg[13]_4 ;
  output [3:0]\dReg_reg[15]_4 ;
  output [9:0]\dReg_reg[13]_5 ;
  output [3:0]\dReg_reg[15]_5 ;
  output [9:0]\dReg_reg[13]_6 ;
  output [3:0]\dReg_reg[15]_6 ;
  input [10:0]D;
  input \dReg_reg[10] ;
  input \dReg_reg[14]_0 ;
  input [14:0]DQOut;
  input \dReg_reg[11] ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_0 ;
  input [9:0]\dReg_reg[13]_7 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;
  input [9:0]\dReg_reg[13]_8 ;
  input \dReg_reg[11]_2 ;
  input \dReg_reg[10]_2 ;
  input [9:0]\dReg_reg[13]_9 ;
  input \dReg_reg[11]_3 ;
  input \dReg_reg[10]_3 ;
  input [9:0]\dReg_reg[13]_10 ;
  input \dReg_reg[11]_4 ;
  input \dReg_reg[10]_4 ;
  input [9:0]\dReg_reg[13]_11 ;
  input \dReg_reg[11]_5 ;
  input \dReg_reg[10]_5 ;
  input [9:0]\dReg_reg[13]_12 ;
  input \dReg_reg[11]_6 ;
  input \dReg_reg[10]_6 ;
  input [9:0]\dReg_reg[13]_13 ;
  input \dReg_reg[11]_7 ;
  input \dReg_reg[10]_7 ;
  input [9:0]\dReg_reg[13]_14 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_8 ;
  input \dReg_reg[10]_8 ;

  wire [10:0]D;
  wire [1:0]DMOut;
  wire [14:0]DQOut;
  wire [10:0]Q;
  wire \dReg_reg[10] ;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[10]_3 ;
  wire \dReg_reg[10]_4 ;
  wire \dReg_reg[10]_5 ;
  wire \dReg_reg[10]_6 ;
  wire \dReg_reg[10]_7 ;
  wire \dReg_reg[10]_8 ;
  wire \dReg_reg[11] ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire \dReg_reg[11]_2 ;
  wire \dReg_reg[11]_3 ;
  wire \dReg_reg[11]_4 ;
  wire \dReg_reg[11]_5 ;
  wire \dReg_reg[11]_6 ;
  wire \dReg_reg[11]_7 ;
  wire \dReg_reg[11]_8 ;
  wire [9:0]\dReg_reg[13] ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire [9:0]\dReg_reg[13]_10 ;
  wire [9:0]\dReg_reg[13]_11 ;
  wire [9:0]\dReg_reg[13]_12 ;
  wire [9:0]\dReg_reg[13]_13 ;
  wire [9:0]\dReg_reg[13]_14 ;
  wire [9:0]\dReg_reg[13]_2 ;
  wire [9:0]\dReg_reg[13]_3 ;
  wire [9:0]\dReg_reg[13]_4 ;
  wire [9:0]\dReg_reg[13]_5 ;
  wire [9:0]\dReg_reg[13]_6 ;
  wire [9:0]\dReg_reg[13]_7 ;
  wire [9:0]\dReg_reg[13]_8 ;
  wire [9:0]\dReg_reg[13]_9 ;
  wire [2:0]\dReg_reg[14] ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15] ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire [3:0]\dReg_reg[15]_1 ;
  wire [3:0]\dReg_reg[15]_2 ;
  wire [3:0]\dReg_reg[15]_3 ;
  wire [3:0]\dReg_reg[15]_4 ;
  wire [3:0]\dReg_reg[15]_5 ;
  wire [3:0]\dReg_reg[15]_6 ;

  ddr4_0_ddr4_v2_2_17_cal_wr_bit_51 \genBit[0].u_ddr_mc_wr_bit 
       (.D(D),
        .DQOut(DQOut[0]),
        .Q(Q),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_0 ),
        .\dReg_reg[14]_0 (\dReg_reg[14] ),
        .\dReg_reg[14]_1 (\dReg_reg[14]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_52 \genBit[1].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[2:1]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_1 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_1 ),
        .\dReg_reg[13]_0 (\dReg_reg[13] ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_7 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15] ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_53 \genBit[2].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[4:3]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_2 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_2 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_0 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_8 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_54 \genBit[3].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[6:5]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_3 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_3 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_1 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_9 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_1 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_55 \genBit[4].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[8:7]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_4 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_4 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_2 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_10 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_2 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_56 \genBit[5].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[10:9]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_5 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_5 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_3 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_11 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_3 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_57 \genBit[6].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[12:11]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_6 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_6 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_4 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_12 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_4 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_58 \genBit[7].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[14:13]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_7 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_7 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_5 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_13 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_5 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_59 u_ddr_mc_wr_dm
       (.DMOut(DMOut),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_8 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_8 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_6 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_14 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_6 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_byte" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_byte_32
   (Q,
    \dReg_reg[14] ,
    \dReg_reg[13] ,
    \dReg_reg[15] ,
    \dReg_reg[13]_0 ,
    \dReg_reg[15]_0 ,
    \dReg_reg[13]_1 ,
    \dReg_reg[15]_1 ,
    \dReg_reg[13]_2 ,
    \dReg_reg[15]_2 ,
    \dReg_reg[13]_3 ,
    \dReg_reg[15]_3 ,
    \dReg_reg[13]_4 ,
    \dReg_reg[15]_4 ,
    \dReg_reg[13]_5 ,
    \dReg_reg[15]_5 ,
    \dReg_reg[13]_6 ,
    \dReg_reg[15]_6 ,
    D,
    \dReg_reg[10] ,
    \dReg_reg[14]_0 ,
    DQOut,
    \dReg_reg[11] ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[13]_7 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 ,
    \dReg_reg[13]_8 ,
    \dReg_reg[11]_2 ,
    \dReg_reg[10]_2 ,
    \dReg_reg[13]_9 ,
    \dReg_reg[11]_3 ,
    \dReg_reg[10]_3 ,
    \dReg_reg[13]_10 ,
    \dReg_reg[11]_4 ,
    \dReg_reg[10]_4 ,
    \dReg_reg[13]_11 ,
    \dReg_reg[11]_5 ,
    \dReg_reg[10]_5 ,
    \dReg_reg[13]_12 ,
    \dReg_reg[11]_6 ,
    \dReg_reg[10]_6 ,
    \dReg_reg[13]_13 ,
    \dReg_reg[11]_7 ,
    \dReg_reg[10]_7 ,
    \dReg_reg[13]_14 ,
    DMOut,
    \dReg_reg[11]_8 ,
    \dReg_reg[10]_8 );
  output [10:0]Q;
  output [2:0]\dReg_reg[14] ;
  output [9:0]\dReg_reg[13] ;
  output [3:0]\dReg_reg[15] ;
  output [9:0]\dReg_reg[13]_0 ;
  output [3:0]\dReg_reg[15]_0 ;
  output [9:0]\dReg_reg[13]_1 ;
  output [3:0]\dReg_reg[15]_1 ;
  output [9:0]\dReg_reg[13]_2 ;
  output [3:0]\dReg_reg[15]_2 ;
  output [9:0]\dReg_reg[13]_3 ;
  output [3:0]\dReg_reg[15]_3 ;
  output [9:0]\dReg_reg[13]_4 ;
  output [3:0]\dReg_reg[15]_4 ;
  output [9:0]\dReg_reg[13]_5 ;
  output [3:0]\dReg_reg[15]_5 ;
  output [9:0]\dReg_reg[13]_6 ;
  output [3:0]\dReg_reg[15]_6 ;
  input [10:0]D;
  input \dReg_reg[10] ;
  input \dReg_reg[14]_0 ;
  input [14:0]DQOut;
  input \dReg_reg[11] ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_0 ;
  input [9:0]\dReg_reg[13]_7 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;
  input [9:0]\dReg_reg[13]_8 ;
  input \dReg_reg[11]_2 ;
  input \dReg_reg[10]_2 ;
  input [9:0]\dReg_reg[13]_9 ;
  input \dReg_reg[11]_3 ;
  input \dReg_reg[10]_3 ;
  input [9:0]\dReg_reg[13]_10 ;
  input \dReg_reg[11]_4 ;
  input \dReg_reg[10]_4 ;
  input [9:0]\dReg_reg[13]_11 ;
  input \dReg_reg[11]_5 ;
  input \dReg_reg[10]_5 ;
  input [9:0]\dReg_reg[13]_12 ;
  input \dReg_reg[11]_6 ;
  input \dReg_reg[10]_6 ;
  input [9:0]\dReg_reg[13]_13 ;
  input \dReg_reg[11]_7 ;
  input \dReg_reg[10]_7 ;
  input [9:0]\dReg_reg[13]_14 ;
  input [1:0]DMOut;
  input \dReg_reg[11]_8 ;
  input \dReg_reg[10]_8 ;

  wire [10:0]D;
  wire [1:0]DMOut;
  wire [14:0]DQOut;
  wire [10:0]Q;
  wire \dReg_reg[10] ;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[10]_3 ;
  wire \dReg_reg[10]_4 ;
  wire \dReg_reg[10]_5 ;
  wire \dReg_reg[10]_6 ;
  wire \dReg_reg[10]_7 ;
  wire \dReg_reg[10]_8 ;
  wire \dReg_reg[11] ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire \dReg_reg[11]_2 ;
  wire \dReg_reg[11]_3 ;
  wire \dReg_reg[11]_4 ;
  wire \dReg_reg[11]_5 ;
  wire \dReg_reg[11]_6 ;
  wire \dReg_reg[11]_7 ;
  wire \dReg_reg[11]_8 ;
  wire [9:0]\dReg_reg[13] ;
  wire [9:0]\dReg_reg[13]_0 ;
  wire [9:0]\dReg_reg[13]_1 ;
  wire [9:0]\dReg_reg[13]_10 ;
  wire [9:0]\dReg_reg[13]_11 ;
  wire [9:0]\dReg_reg[13]_12 ;
  wire [9:0]\dReg_reg[13]_13 ;
  wire [9:0]\dReg_reg[13]_14 ;
  wire [9:0]\dReg_reg[13]_2 ;
  wire [9:0]\dReg_reg[13]_3 ;
  wire [9:0]\dReg_reg[13]_4 ;
  wire [9:0]\dReg_reg[13]_5 ;
  wire [9:0]\dReg_reg[13]_6 ;
  wire [9:0]\dReg_reg[13]_7 ;
  wire [9:0]\dReg_reg[13]_8 ;
  wire [9:0]\dReg_reg[13]_9 ;
  wire [2:0]\dReg_reg[14] ;
  wire \dReg_reg[14]_0 ;
  wire [3:0]\dReg_reg[15] ;
  wire [3:0]\dReg_reg[15]_0 ;
  wire [3:0]\dReg_reg[15]_1 ;
  wire [3:0]\dReg_reg[15]_2 ;
  wire [3:0]\dReg_reg[15]_3 ;
  wire [3:0]\dReg_reg[15]_4 ;
  wire [3:0]\dReg_reg[15]_5 ;
  wire [3:0]\dReg_reg[15]_6 ;

  ddr4_0_ddr4_v2_2_17_cal_wr_bit_42 \genBit[0].u_ddr_mc_wr_bit 
       (.D(D),
        .DQOut(DQOut[0]),
        .Q(Q),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_0 ),
        .\dReg_reg[14]_0 (\dReg_reg[14] ),
        .\dReg_reg[14]_1 (\dReg_reg[14]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_43 \genBit[1].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[2:1]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_1 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_1 ),
        .\dReg_reg[13]_0 (\dReg_reg[13] ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_7 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15] ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_44 \genBit[2].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[4:3]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_2 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_2 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_0 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_8 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_45 \genBit[3].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[6:5]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_3 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_3 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_1 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_9 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_1 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_46 \genBit[4].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[8:7]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_4 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_4 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_2 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_10 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_2 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_47 \genBit[5].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[10:9]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_5 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_5 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_3 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_11 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_3 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_48 \genBit[6].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[12:11]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_6 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_6 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_4 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_12 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_4 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_49 \genBit[7].u_ddr_mc_wr_bit 
       (.DQOut(DQOut[14:13]),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_7 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_7 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_5 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_13 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_5 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_50 u_ddr_mc_wr_dm
       (.DMOut(DMOut),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_8 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_8 ),
        .\dReg_reg[13]_0 (\dReg_reg[13]_6 ),
        .\dReg_reg[13]_1 (\dReg_reg[13]_14 ),
        .\dReg_reg[14]_0 (\dReg_reg[14]_0 ),
        .\dReg_reg[15]_0 (\dReg_reg[15]_6 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_wr_byte" *) 
module ddr4_0_ddr4_v2_2_17_cal_wr_byte_33
   (\wosp_reg[1] ,
    \wosp_reg[2] ,
    \wosp_reg[2]_rep ,
    \wosp_reg[2]_rep__0 ,
    \wosp_reg[2]_rep__1 ,
    \wosp_reg[2]_rep__2 ,
    \wosp_reg[2]_rep__3 ,
    \wosp_reg[2]_rep__4 ,
    \wosp_reg[2]_rep__5 ,
    \wosp_reg[2]_rep__6 ,
    \wosp_reg[2]_rep__7 ,
    wrDataVal_reg,
    D,
    \wosp_reg[1]_0 ,
    \wosp_reg[1]_1 ,
    \wosp_reg[1]_2 ,
    \wosp_reg[1]_3 ,
    \wosp_reg[1]_4 ,
    \wosp_reg[1]_5 ,
    \wosp_reg[1]_6 ,
    \wosp_reg[1]_7 ,
    \wosp_reg[1]_8 ,
    \wosp_reg[1]_9 ,
    \wosp_reg[1]_10 ,
    \wosp_reg[1]_11 ,
    \wosp_reg[1]_12 ,
    \wosp_reg[1]_13 ,
    \wosp_reg[1]_14 ,
    \wosp_reg[1]_15 ,
    \wosp_reg[1]_16 ,
    \wosp_reg[1]_17 ,
    \wosp_reg[1]_18 ,
    \wosp_reg[1]_19 ,
    \wosp_reg[1]_20 ,
    \wosp_reg[1]_21 ,
    \wosp_reg[1]_22 ,
    \wosp_reg[1]_23 ,
    \wosp_reg[1]_24 ,
    \wosp_reg[1]_25 ,
    \wosp_reg[1]_26 ,
    \wosp_reg[1]_27 ,
    \wosp_reg[1]_28 ,
    \wosp_reg[1]_29 ,
    \wosp_reg[1]_30 ,
    \wosp_reg[1]_31 ,
    \wosp_reg[1]_32 ,
    \wosp_reg[1]_33 ,
    \wosp_reg[1]_34 ,
    \wosp_reg[1]_35 ,
    \wosp_reg[1]_36 ,
    \wosp_reg[1]_37 ,
    \wosp_reg[1]_38 ,
    \wosp_reg[1]_39 ,
    \wosp_reg[1]_40 ,
    \wosp_reg[1]_41 ,
    \wosp_reg[1]_42 ,
    \wosp_reg[1]_43 ,
    \wosp_reg[1]_44 ,
    \wosp_reg[1]_45 ,
    \wosp_reg[1]_46 ,
    \wosp_reg[1]_47 ,
    \wosp_reg[1]_48 ,
    \wosp_reg[1]_49 ,
    \wosp_reg[1]_50 ,
    \wosp_reg[1]_51 ,
    \wosp_reg[1]_52 ,
    \wosp_reg[1]_53 ,
    \wosp_reg[1]_54 ,
    \wosp_reg[1]_55 ,
    \wosp_reg[1]_56 ,
    \wosp_reg[1]_57 ,
    \wosp_reg[1]_58 ,
    \wosp_reg[1]_59 ,
    \wosp_reg[1]_60 ,
    \wosp_reg[1]_61 ,
    ch0_mcal_DQOut,
    ch0_mcal_DMOut_n,
    \wosp_reg[1]_62 ,
    \dReg_reg[10] ,
    sel,
    \dReg_reg[6] ,
    DQOut,
    DMOut,
    \dReg_reg[7] ,
    dReg,
    \dReg_reg[6]_0 ,
    dReg__0,
    dReg__1,
    dReg__2,
    dReg__3,
    dReg__4,
    dReg__5,
    dReg__6,
    dReg__7,
    \dReg_reg[7]_0 ,
    \dReg_reg[6]_1 ,
    \dReg_reg[7]_1 ,
    \dReg_reg[6]_2 ,
    \dReg_reg[7]_2 ,
    \dReg_reg[6]_3 ,
    \dReg_reg[7]_3 ,
    \dReg_reg[6]_4 ,
    \dReg_reg[7]_4 ,
    \dReg_reg[6]_5 ,
    \dReg_reg[7]_5 ,
    \dReg_reg[6]_6 ,
    \dReg_reg[7]_6 ,
    \dReg_reg[6]_7 ,
    \dReg_reg[7]_7 ,
    \dReg_reg[6]_8 ,
    \dReg_reg[7]_8 ,
    dReg_0,
    \dReg_reg[6]_9 ,
    dReg__0_1,
    dReg__1_2,
    dReg__2_3,
    dReg__3_4,
    dReg__4_5,
    dReg__5_6,
    dReg__6_7,
    dReg__7_8,
    \dReg_reg[7]_9 ,
    \dReg_reg[6]_10 ,
    \dReg_reg[7]_10 ,
    \dReg_reg[6]_11 ,
    \dReg_reg[7]_11 ,
    \dReg_reg[6]_12 ,
    \dReg_reg[7]_12 ,
    \dReg_reg[6]_13 ,
    \dReg_reg[7]_13 ,
    \dReg_reg[6]_14 ,
    \dReg_reg[7]_14 ,
    \dReg_reg[6]_15 ,
    \dReg_reg[7]_15 ,
    \dReg_reg[6]_16 ,
    \dReg_reg[7]_16 ,
    \dReg_reg[6]_17 ,
    \dReg_reg[7]_17 ,
    dReg_9,
    \dReg_reg[6]_18 ,
    dReg__0_10,
    dReg__1_11,
    dReg__2_12,
    dReg__3_13,
    dReg__4_14,
    dReg__5_15,
    dReg__6_16,
    dReg__7_17,
    \dReg_reg[7]_18 ,
    \dReg_reg[6]_19 ,
    \dReg_reg[7]_19 ,
    \dReg_reg[6]_20 ,
    \dReg_reg[7]_20 ,
    \dReg_reg[6]_21 ,
    \dReg_reg[7]_21 ,
    \dReg_reg[6]_22 ,
    \dReg_reg[7]_22 ,
    \dReg_reg[6]_23 ,
    \dReg_reg[7]_23 ,
    \dReg_reg[6]_24 ,
    \dReg_reg[7]_24 ,
    \dReg_reg[6]_25 ,
    \dReg_reg[7]_25 ,
    \dReg_reg[6]_26 ,
    \dReg_reg[7]_26 ,
    dReg_18,
    \dReg_reg[6]_27 ,
    dReg__0_19,
    dReg__1_20,
    dReg__2_21,
    dReg__3_22,
    dReg__4_23,
    dReg__5_24,
    dReg__6_25,
    dReg__7_26,
    \dReg_reg[7]_27 ,
    \dReg_reg[6]_28 ,
    \dReg_reg[7]_28 ,
    \dReg_reg[6]_29 ,
    \dReg_reg[7]_29 ,
    \dReg_reg[6]_30 ,
    \dReg_reg[7]_30 ,
    \dReg_reg[6]_31 ,
    \dReg_reg[7]_31 ,
    \dReg_reg[6]_32 ,
    \dReg_reg[7]_32 ,
    \dReg_reg[6]_33 ,
    \dReg_reg[7]_33 ,
    \dReg_reg[6]_34 ,
    \dReg_reg[7]_34 ,
    \dReg_reg[6]_35 ,
    \dReg_reg[7]_35 ,
    dReg_27,
    \dReg_reg[6]_36 ,
    dReg__0_28,
    dReg__1_29,
    dReg__2_30,
    dReg__3_31,
    dReg__4_32,
    dReg__5_33,
    dReg__6_34,
    dReg__7_35,
    \dReg_reg[7]_36 ,
    \dReg_reg[6]_37 ,
    \dReg_reg[7]_37 ,
    \dReg_reg[6]_38 ,
    \dReg_reg[7]_38 ,
    \dReg_reg[6]_39 ,
    \dReg_reg[7]_39 ,
    \dReg_reg[6]_40 ,
    \dReg_reg[7]_40 ,
    \dReg_reg[6]_41 ,
    \dReg_reg[7]_41 ,
    \dReg_reg[6]_42 ,
    \dReg_reg[7]_42 ,
    \dReg_reg[6]_43 ,
    \dReg_reg[7]_43 ,
    \dReg_reg[6]_44 ,
    \dReg_reg[7]_44 ,
    dReg_36,
    \dReg_reg[6]_45 ,
    dReg__0_37,
    dReg__1_38,
    dReg__2_39,
    dReg__3_40,
    dReg__4_41,
    dReg__5_42,
    dReg__6_43,
    dReg__7_44,
    \dReg_reg[7]_45 ,
    \dReg_reg[6]_46 ,
    \dReg_reg[7]_46 ,
    \dReg_reg[6]_47 ,
    \dReg_reg[7]_47 ,
    \dReg_reg[6]_48 ,
    \dReg_reg[7]_48 ,
    \dReg_reg[6]_49 ,
    \dReg_reg[7]_49 ,
    \dReg_reg[6]_50 ,
    \dReg_reg[7]_50 ,
    \dReg_reg[6]_51 ,
    \dReg_reg[7]_51 ,
    \dReg_reg[6]_52 ,
    \dReg_reg[7]_52 ,
    \dReg_reg[6]_53 ,
    \dReg_reg[7]_53 ,
    dReg_45,
    \dReg_reg[6]_54 ,
    dReg__0_46,
    dReg__1_47,
    dReg__2_48,
    dReg__3_49,
    dReg__4_50,
    dReg__5_51,
    dReg__6_52,
    dReg__7_53,
    \dReg_reg[7]_54 ,
    \dReg_reg[6]_55 ,
    \dReg_reg[7]_55 ,
    \dReg_reg[6]_56 ,
    \dReg_reg[7]_56 ,
    \dReg_reg[6]_57 ,
    \dReg_reg[7]_57 ,
    \dReg_reg[6]_58 ,
    \dReg_reg[7]_58 ,
    \dReg_reg[6]_59 ,
    \dReg_reg[7]_59 ,
    \dReg_reg[6]_60 ,
    \dReg_reg[7]_60 ,
    \dReg_reg[6]_61 ,
    \dReg_reg[7]_61 ,
    \dReg_reg[6]_62 ,
    \dReg_reg[7]_62 ,
    \dReg_reg[6]_63 ,
    \dReg_reg[7]_63 ,
    \dReg_reg[6]_64 ,
    \dReg_reg[7]_64 ,
    \dReg_reg[6]_65 ,
    \dReg_reg[7]_65 ,
    \dReg_reg[6]_66 ,
    \dReg_reg[7]_66 ,
    \dReg_reg[6]_67 ,
    \dReg_reg[7]_67 ,
    \dReg_reg[6]_68 ,
    \dReg_reg[7]_68 ,
    \dReg_reg[6]_69 ,
    \dReg_reg[7]_69 ,
    \dReg_reg[6]_70 ,
    \dReg_reg[7]_70 ,
    \dReg_reg[6]_71 ,
    \dReg_reg[9] ,
    \dReg_reg[11] ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_0 ,
    \dReg_reg[9]_0 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_1 ,
    \dReg_reg[9]_1 ,
    \dReg_reg[11]_2 ,
    \dReg_reg[10]_2 ,
    \dReg_reg[9]_2 ,
    \dReg_reg[11]_3 ,
    \dReg_reg[10]_3 ,
    \dReg_reg[9]_3 ,
    \dReg_reg[11]_4 ,
    \dReg_reg[10]_4 ,
    \dReg_reg[9]_4 ,
    \dReg_reg[11]_5 ,
    \dReg_reg[10]_5 ,
    \dReg_reg[9]_5 ,
    \dReg_reg[11]_6 ,
    \dReg_reg[10]_6 ,
    \dReg_reg[9]_6 ,
    \dReg_reg[11]_7 ,
    \dReg_reg[10]_7 ,
    \dReg_reg[9]_7 ,
    \dReg_reg[11]_8 ,
    \dReg_reg[10]_8 );
  output \wosp_reg[1] ;
  output \wosp_reg[2] ;
  output \wosp_reg[2]_rep ;
  output \wosp_reg[2]_rep__0 ;
  output \wosp_reg[2]_rep__1 ;
  output \wosp_reg[2]_rep__2 ;
  output \wosp_reg[2]_rep__3 ;
  output \wosp_reg[2]_rep__4 ;
  output \wosp_reg[2]_rep__5 ;
  output \wosp_reg[2]_rep__6 ;
  output \wosp_reg[2]_rep__7 ;
  output wrDataVal_reg;
  output [8:0]D;
  output [7:0]\wosp_reg[1]_0 ;
  output [7:0]\wosp_reg[1]_1 ;
  output [7:0]\wosp_reg[1]_2 ;
  output [7:0]\wosp_reg[1]_3 ;
  output [7:0]\wosp_reg[1]_4 ;
  output [7:0]\wosp_reg[1]_5 ;
  output [7:0]\wosp_reg[1]_6 ;
  output [7:0]\wosp_reg[1]_7 ;
  output [8:0]\wosp_reg[1]_8 ;
  output [7:0]\wosp_reg[1]_9 ;
  output [7:0]\wosp_reg[1]_10 ;
  output [7:0]\wosp_reg[1]_11 ;
  output [7:0]\wosp_reg[1]_12 ;
  output [7:0]\wosp_reg[1]_13 ;
  output [7:0]\wosp_reg[1]_14 ;
  output [7:0]\wosp_reg[1]_15 ;
  output [7:0]\wosp_reg[1]_16 ;
  output [8:0]\wosp_reg[1]_17 ;
  output [7:0]\wosp_reg[1]_18 ;
  output [7:0]\wosp_reg[1]_19 ;
  output [7:0]\wosp_reg[1]_20 ;
  output [7:0]\wosp_reg[1]_21 ;
  output [7:0]\wosp_reg[1]_22 ;
  output [7:0]\wosp_reg[1]_23 ;
  output [7:0]\wosp_reg[1]_24 ;
  output [7:0]\wosp_reg[1]_25 ;
  output [8:0]\wosp_reg[1]_26 ;
  output [7:0]\wosp_reg[1]_27 ;
  output [7:0]\wosp_reg[1]_28 ;
  output [7:0]\wosp_reg[1]_29 ;
  output [7:0]\wosp_reg[1]_30 ;
  output [7:0]\wosp_reg[1]_31 ;
  output [7:0]\wosp_reg[1]_32 ;
  output [7:0]\wosp_reg[1]_33 ;
  output [7:0]\wosp_reg[1]_34 ;
  output [8:0]\wosp_reg[1]_35 ;
  output [7:0]\wosp_reg[1]_36 ;
  output [7:0]\wosp_reg[1]_37 ;
  output [7:0]\wosp_reg[1]_38 ;
  output [7:0]\wosp_reg[1]_39 ;
  output [7:0]\wosp_reg[1]_40 ;
  output [7:0]\wosp_reg[1]_41 ;
  output [7:0]\wosp_reg[1]_42 ;
  output [7:0]\wosp_reg[1]_43 ;
  output [8:0]\wosp_reg[1]_44 ;
  output [7:0]\wosp_reg[1]_45 ;
  output [7:0]\wosp_reg[1]_46 ;
  output [7:0]\wosp_reg[1]_47 ;
  output [7:0]\wosp_reg[1]_48 ;
  output [7:0]\wosp_reg[1]_49 ;
  output [7:0]\wosp_reg[1]_50 ;
  output [7:0]\wosp_reg[1]_51 ;
  output [7:0]\wosp_reg[1]_52 ;
  output [8:0]\wosp_reg[1]_53 ;
  output [7:0]\wosp_reg[1]_54 ;
  output [7:0]\wosp_reg[1]_55 ;
  output [7:0]\wosp_reg[1]_56 ;
  output [7:0]\wosp_reg[1]_57 ;
  output [7:0]\wosp_reg[1]_58 ;
  output [7:0]\wosp_reg[1]_59 ;
  output [7:0]\wosp_reg[1]_60 ;
  output [7:0]\wosp_reg[1]_61 ;
  output [63:0]ch0_mcal_DQOut;
  output [7:0]ch0_mcal_DMOut_n;
  input \wosp_reg[1]_62 ;
  input \dReg_reg[10] ;
  input [0:0]sel;
  input \dReg_reg[6] ;
  input [511:0]DQOut;
  input [63:0]DMOut;
  input \dReg_reg[7] ;
  input [5:0]dReg;
  input \dReg_reg[6]_0 ;
  input [5:0]dReg__0;
  input [5:0]dReg__1;
  input [5:0]dReg__2;
  input [5:0]dReg__3;
  input [5:0]dReg__4;
  input [5:0]dReg__5;
  input [5:0]dReg__6;
  input [5:0]dReg__7;
  input \dReg_reg[7]_0 ;
  input \dReg_reg[6]_1 ;
  input \dReg_reg[7]_1 ;
  input \dReg_reg[6]_2 ;
  input \dReg_reg[7]_2 ;
  input \dReg_reg[6]_3 ;
  input \dReg_reg[7]_3 ;
  input \dReg_reg[6]_4 ;
  input \dReg_reg[7]_4 ;
  input \dReg_reg[6]_5 ;
  input \dReg_reg[7]_5 ;
  input \dReg_reg[6]_6 ;
  input \dReg_reg[7]_6 ;
  input \dReg_reg[6]_7 ;
  input \dReg_reg[7]_7 ;
  input \dReg_reg[6]_8 ;
  input \dReg_reg[7]_8 ;
  input [5:0]dReg_0;
  input \dReg_reg[6]_9 ;
  input [5:0]dReg__0_1;
  input [5:0]dReg__1_2;
  input [5:0]dReg__2_3;
  input [5:0]dReg__3_4;
  input [5:0]dReg__4_5;
  input [5:0]dReg__5_6;
  input [5:0]dReg__6_7;
  input [5:0]dReg__7_8;
  input \dReg_reg[7]_9 ;
  input \dReg_reg[6]_10 ;
  input \dReg_reg[7]_10 ;
  input \dReg_reg[6]_11 ;
  input \dReg_reg[7]_11 ;
  input \dReg_reg[6]_12 ;
  input \dReg_reg[7]_12 ;
  input \dReg_reg[6]_13 ;
  input \dReg_reg[7]_13 ;
  input \dReg_reg[6]_14 ;
  input \dReg_reg[7]_14 ;
  input \dReg_reg[6]_15 ;
  input \dReg_reg[7]_15 ;
  input \dReg_reg[6]_16 ;
  input \dReg_reg[7]_16 ;
  input \dReg_reg[6]_17 ;
  input \dReg_reg[7]_17 ;
  input [5:0]dReg_9;
  input \dReg_reg[6]_18 ;
  input [5:0]dReg__0_10;
  input [5:0]dReg__1_11;
  input [5:0]dReg__2_12;
  input [5:0]dReg__3_13;
  input [5:0]dReg__4_14;
  input [5:0]dReg__5_15;
  input [5:0]dReg__6_16;
  input [5:0]dReg__7_17;
  input \dReg_reg[7]_18 ;
  input \dReg_reg[6]_19 ;
  input \dReg_reg[7]_19 ;
  input \dReg_reg[6]_20 ;
  input \dReg_reg[7]_20 ;
  input \dReg_reg[6]_21 ;
  input \dReg_reg[7]_21 ;
  input \dReg_reg[6]_22 ;
  input \dReg_reg[7]_22 ;
  input \dReg_reg[6]_23 ;
  input \dReg_reg[7]_23 ;
  input \dReg_reg[6]_24 ;
  input \dReg_reg[7]_24 ;
  input \dReg_reg[6]_25 ;
  input \dReg_reg[7]_25 ;
  input \dReg_reg[6]_26 ;
  input \dReg_reg[7]_26 ;
  input [5:0]dReg_18;
  input \dReg_reg[6]_27 ;
  input [5:0]dReg__0_19;
  input [5:0]dReg__1_20;
  input [5:0]dReg__2_21;
  input [5:0]dReg__3_22;
  input [5:0]dReg__4_23;
  input [5:0]dReg__5_24;
  input [5:0]dReg__6_25;
  input [5:0]dReg__7_26;
  input \dReg_reg[7]_27 ;
  input \dReg_reg[6]_28 ;
  input \dReg_reg[7]_28 ;
  input \dReg_reg[6]_29 ;
  input \dReg_reg[7]_29 ;
  input \dReg_reg[6]_30 ;
  input \dReg_reg[7]_30 ;
  input \dReg_reg[6]_31 ;
  input \dReg_reg[7]_31 ;
  input \dReg_reg[6]_32 ;
  input \dReg_reg[7]_32 ;
  input \dReg_reg[6]_33 ;
  input \dReg_reg[7]_33 ;
  input \dReg_reg[6]_34 ;
  input \dReg_reg[7]_34 ;
  input \dReg_reg[6]_35 ;
  input \dReg_reg[7]_35 ;
  input [5:0]dReg_27;
  input \dReg_reg[6]_36 ;
  input [5:0]dReg__0_28;
  input [5:0]dReg__1_29;
  input [5:0]dReg__2_30;
  input [5:0]dReg__3_31;
  input [5:0]dReg__4_32;
  input [5:0]dReg__5_33;
  input [5:0]dReg__6_34;
  input [5:0]dReg__7_35;
  input \dReg_reg[7]_36 ;
  input \dReg_reg[6]_37 ;
  input \dReg_reg[7]_37 ;
  input \dReg_reg[6]_38 ;
  input \dReg_reg[7]_38 ;
  input \dReg_reg[6]_39 ;
  input \dReg_reg[7]_39 ;
  input \dReg_reg[6]_40 ;
  input \dReg_reg[7]_40 ;
  input \dReg_reg[6]_41 ;
  input \dReg_reg[7]_41 ;
  input \dReg_reg[6]_42 ;
  input \dReg_reg[7]_42 ;
  input \dReg_reg[6]_43 ;
  input \dReg_reg[7]_43 ;
  input \dReg_reg[6]_44 ;
  input \dReg_reg[7]_44 ;
  input [5:0]dReg_36;
  input \dReg_reg[6]_45 ;
  input [5:0]dReg__0_37;
  input [5:0]dReg__1_38;
  input [5:0]dReg__2_39;
  input [5:0]dReg__3_40;
  input [5:0]dReg__4_41;
  input [5:0]dReg__5_42;
  input [5:0]dReg__6_43;
  input [5:0]dReg__7_44;
  input \dReg_reg[7]_45 ;
  input \dReg_reg[6]_46 ;
  input \dReg_reg[7]_46 ;
  input \dReg_reg[6]_47 ;
  input \dReg_reg[7]_47 ;
  input \dReg_reg[6]_48 ;
  input \dReg_reg[7]_48 ;
  input \dReg_reg[6]_49 ;
  input \dReg_reg[7]_49 ;
  input \dReg_reg[6]_50 ;
  input \dReg_reg[7]_50 ;
  input \dReg_reg[6]_51 ;
  input \dReg_reg[7]_51 ;
  input \dReg_reg[6]_52 ;
  input \dReg_reg[7]_52 ;
  input \dReg_reg[6]_53 ;
  input \dReg_reg[7]_53 ;
  input [5:0]dReg_45;
  input \dReg_reg[6]_54 ;
  input [5:0]dReg__0_46;
  input [5:0]dReg__1_47;
  input [5:0]dReg__2_48;
  input [5:0]dReg__3_49;
  input [5:0]dReg__4_50;
  input [5:0]dReg__5_51;
  input [5:0]dReg__6_52;
  input [5:0]dReg__7_53;
  input \dReg_reg[7]_54 ;
  input \dReg_reg[6]_55 ;
  input \dReg_reg[7]_55 ;
  input \dReg_reg[6]_56 ;
  input \dReg_reg[7]_56 ;
  input \dReg_reg[6]_57 ;
  input \dReg_reg[7]_57 ;
  input \dReg_reg[6]_58 ;
  input \dReg_reg[7]_58 ;
  input \dReg_reg[6]_59 ;
  input \dReg_reg[7]_59 ;
  input \dReg_reg[6]_60 ;
  input \dReg_reg[7]_60 ;
  input \dReg_reg[6]_61 ;
  input \dReg_reg[7]_61 ;
  input \dReg_reg[6]_62 ;
  input \dReg_reg[7]_62 ;
  input \dReg_reg[6]_63 ;
  input \dReg_reg[7]_63 ;
  input \dReg_reg[6]_64 ;
  input \dReg_reg[7]_64 ;
  input \dReg_reg[6]_65 ;
  input \dReg_reg[7]_65 ;
  input \dReg_reg[6]_66 ;
  input \dReg_reg[7]_66 ;
  input \dReg_reg[6]_67 ;
  input \dReg_reg[7]_67 ;
  input \dReg_reg[6]_68 ;
  input \dReg_reg[7]_68 ;
  input \dReg_reg[6]_69 ;
  input \dReg_reg[7]_69 ;
  input \dReg_reg[6]_70 ;
  input \dReg_reg[7]_70 ;
  input \dReg_reg[6]_71 ;
  input [1:0]\dReg_reg[9] ;
  input \dReg_reg[11] ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_0 ;
  input [1:0]\dReg_reg[9]_0 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_1 ;
  input [1:0]\dReg_reg[9]_1 ;
  input \dReg_reg[11]_2 ;
  input \dReg_reg[10]_2 ;
  input [1:0]\dReg_reg[9]_2 ;
  input \dReg_reg[11]_3 ;
  input \dReg_reg[10]_3 ;
  input [1:0]\dReg_reg[9]_3 ;
  input \dReg_reg[11]_4 ;
  input \dReg_reg[10]_4 ;
  input [1:0]\dReg_reg[9]_4 ;
  input \dReg_reg[11]_5 ;
  input \dReg_reg[10]_5 ;
  input [1:0]\dReg_reg[9]_5 ;
  input \dReg_reg[11]_6 ;
  input \dReg_reg[10]_6 ;
  input [1:0]\dReg_reg[9]_6 ;
  input \dReg_reg[11]_7 ;
  input \dReg_reg[10]_7 ;
  input [1:0]\dReg_reg[9]_7 ;
  input \dReg_reg[11]_8 ;
  input \dReg_reg[10]_8 ;

  wire [8:0]D;
  wire [63:0]DMOut;
  wire [511:0]DQOut;
  wire [7:0]ch0_mcal_DMOut_n;
  wire [63:0]ch0_mcal_DQOut;
  wire [5:0]dReg;
  wire [5:0]dReg_0;
  wire [5:0]dReg_18;
  wire [5:0]dReg_27;
  wire [5:0]dReg_36;
  wire [5:0]dReg_45;
  wire [5:0]dReg_9;
  wire [5:0]dReg__0;
  wire [5:0]dReg__0_1;
  wire [5:0]dReg__0_10;
  wire [5:0]dReg__0_19;
  wire [15:10]dReg__0_2;
  wire [5:0]dReg__0_28;
  wire [5:0]dReg__0_37;
  wire [5:0]dReg__0_46;
  wire [5:0]dReg__1;
  wire [5:0]dReg__1_11;
  wire [5:0]dReg__1_2;
  wire [5:0]dReg__1_20;
  wire [5:0]dReg__1_29;
  wire [15:10]dReg__1_3;
  wire [5:0]dReg__1_38;
  wire [5:0]dReg__1_47;
  wire [5:0]dReg__2;
  wire [5:0]dReg__2_12;
  wire [5:0]dReg__2_21;
  wire [5:0]dReg__2_3;
  wire [5:0]dReg__2_30;
  wire [5:0]dReg__2_39;
  wire [15:10]dReg__2_4;
  wire [5:0]dReg__2_48;
  wire [5:0]dReg__3;
  wire [5:0]dReg__3_13;
  wire [5:0]dReg__3_22;
  wire [5:0]dReg__3_31;
  wire [5:0]dReg__3_4;
  wire [5:0]dReg__3_40;
  wire [5:0]dReg__3_49;
  wire [15:10]dReg__3_5;
  wire [5:0]dReg__4;
  wire [5:0]dReg__4_14;
  wire [5:0]dReg__4_23;
  wire [5:0]dReg__4_32;
  wire [5:0]dReg__4_41;
  wire [5:0]dReg__4_5;
  wire [5:0]dReg__4_50;
  wire [15:10]dReg__4_6;
  wire [5:0]dReg__5;
  wire [5:0]dReg__5_15;
  wire [5:0]dReg__5_24;
  wire [5:0]dReg__5_33;
  wire [5:0]dReg__5_42;
  wire [5:0]dReg__5_51;
  wire [5:0]dReg__5_6;
  wire [15:10]dReg__5_7;
  wire [5:0]dReg__6;
  wire [5:0]dReg__6_16;
  wire [5:0]dReg__6_25;
  wire [5:0]dReg__6_34;
  wire [5:0]dReg__6_43;
  wire [5:0]dReg__6_52;
  wire [5:0]dReg__6_7;
  wire [15:10]dReg__6_8;
  wire [5:0]dReg__7;
  wire [5:0]dReg__7_17;
  wire [5:0]dReg__7_26;
  wire [5:0]dReg__7_35;
  wire [5:0]dReg__7_44;
  wire [5:0]dReg__7_53;
  wire [5:0]dReg__7_8;
  wire [15:10]dReg__7_9;
  wire \dReg_reg[10] ;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[10]_3 ;
  wire \dReg_reg[10]_4 ;
  wire \dReg_reg[10]_5 ;
  wire \dReg_reg[10]_6 ;
  wire \dReg_reg[10]_7 ;
  wire \dReg_reg[10]_8 ;
  wire \dReg_reg[11] ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire \dReg_reg[11]_2 ;
  wire \dReg_reg[11]_3 ;
  wire \dReg_reg[11]_4 ;
  wire \dReg_reg[11]_5 ;
  wire \dReg_reg[11]_6 ;
  wire \dReg_reg[11]_7 ;
  wire \dReg_reg[11]_8 ;
  wire \dReg_reg[6] ;
  wire \dReg_reg[6]_0 ;
  wire \dReg_reg[6]_1 ;
  wire \dReg_reg[6]_10 ;
  wire \dReg_reg[6]_11 ;
  wire \dReg_reg[6]_12 ;
  wire \dReg_reg[6]_13 ;
  wire \dReg_reg[6]_14 ;
  wire \dReg_reg[6]_15 ;
  wire \dReg_reg[6]_16 ;
  wire \dReg_reg[6]_17 ;
  wire \dReg_reg[6]_18 ;
  wire \dReg_reg[6]_19 ;
  wire \dReg_reg[6]_2 ;
  wire \dReg_reg[6]_20 ;
  wire \dReg_reg[6]_21 ;
  wire \dReg_reg[6]_22 ;
  wire \dReg_reg[6]_23 ;
  wire \dReg_reg[6]_24 ;
  wire \dReg_reg[6]_25 ;
  wire \dReg_reg[6]_26 ;
  wire \dReg_reg[6]_27 ;
  wire \dReg_reg[6]_28 ;
  wire \dReg_reg[6]_29 ;
  wire \dReg_reg[6]_3 ;
  wire \dReg_reg[6]_30 ;
  wire \dReg_reg[6]_31 ;
  wire \dReg_reg[6]_32 ;
  wire \dReg_reg[6]_33 ;
  wire \dReg_reg[6]_34 ;
  wire \dReg_reg[6]_35 ;
  wire \dReg_reg[6]_36 ;
  wire \dReg_reg[6]_37 ;
  wire \dReg_reg[6]_38 ;
  wire \dReg_reg[6]_39 ;
  wire \dReg_reg[6]_4 ;
  wire \dReg_reg[6]_40 ;
  wire \dReg_reg[6]_41 ;
  wire \dReg_reg[6]_42 ;
  wire \dReg_reg[6]_43 ;
  wire \dReg_reg[6]_44 ;
  wire \dReg_reg[6]_45 ;
  wire \dReg_reg[6]_46 ;
  wire \dReg_reg[6]_47 ;
  wire \dReg_reg[6]_48 ;
  wire \dReg_reg[6]_49 ;
  wire \dReg_reg[6]_5 ;
  wire \dReg_reg[6]_50 ;
  wire \dReg_reg[6]_51 ;
  wire \dReg_reg[6]_52 ;
  wire \dReg_reg[6]_53 ;
  wire \dReg_reg[6]_54 ;
  wire \dReg_reg[6]_55 ;
  wire \dReg_reg[6]_56 ;
  wire \dReg_reg[6]_57 ;
  wire \dReg_reg[6]_58 ;
  wire \dReg_reg[6]_59 ;
  wire \dReg_reg[6]_6 ;
  wire \dReg_reg[6]_60 ;
  wire \dReg_reg[6]_61 ;
  wire \dReg_reg[6]_62 ;
  wire \dReg_reg[6]_63 ;
  wire \dReg_reg[6]_64 ;
  wire \dReg_reg[6]_65 ;
  wire \dReg_reg[6]_66 ;
  wire \dReg_reg[6]_67 ;
  wire \dReg_reg[6]_68 ;
  wire \dReg_reg[6]_69 ;
  wire \dReg_reg[6]_7 ;
  wire \dReg_reg[6]_70 ;
  wire \dReg_reg[6]_71 ;
  wire \dReg_reg[6]_8 ;
  wire \dReg_reg[6]_9 ;
  wire \dReg_reg[7] ;
  wire \dReg_reg[7]_0 ;
  wire \dReg_reg[7]_1 ;
  wire \dReg_reg[7]_10 ;
  wire \dReg_reg[7]_11 ;
  wire \dReg_reg[7]_12 ;
  wire \dReg_reg[7]_13 ;
  wire \dReg_reg[7]_14 ;
  wire \dReg_reg[7]_15 ;
  wire \dReg_reg[7]_16 ;
  wire \dReg_reg[7]_17 ;
  wire \dReg_reg[7]_18 ;
  wire \dReg_reg[7]_19 ;
  wire \dReg_reg[7]_2 ;
  wire \dReg_reg[7]_20 ;
  wire \dReg_reg[7]_21 ;
  wire \dReg_reg[7]_22 ;
  wire \dReg_reg[7]_23 ;
  wire \dReg_reg[7]_24 ;
  wire \dReg_reg[7]_25 ;
  wire \dReg_reg[7]_26 ;
  wire \dReg_reg[7]_27 ;
  wire \dReg_reg[7]_28 ;
  wire \dReg_reg[7]_29 ;
  wire \dReg_reg[7]_3 ;
  wire \dReg_reg[7]_30 ;
  wire \dReg_reg[7]_31 ;
  wire \dReg_reg[7]_32 ;
  wire \dReg_reg[7]_33 ;
  wire \dReg_reg[7]_34 ;
  wire \dReg_reg[7]_35 ;
  wire \dReg_reg[7]_36 ;
  wire \dReg_reg[7]_37 ;
  wire \dReg_reg[7]_38 ;
  wire \dReg_reg[7]_39 ;
  wire \dReg_reg[7]_4 ;
  wire \dReg_reg[7]_40 ;
  wire \dReg_reg[7]_41 ;
  wire \dReg_reg[7]_42 ;
  wire \dReg_reg[7]_43 ;
  wire \dReg_reg[7]_44 ;
  wire \dReg_reg[7]_45 ;
  wire \dReg_reg[7]_46 ;
  wire \dReg_reg[7]_47 ;
  wire \dReg_reg[7]_48 ;
  wire \dReg_reg[7]_49 ;
  wire \dReg_reg[7]_5 ;
  wire \dReg_reg[7]_50 ;
  wire \dReg_reg[7]_51 ;
  wire \dReg_reg[7]_52 ;
  wire \dReg_reg[7]_53 ;
  wire \dReg_reg[7]_54 ;
  wire \dReg_reg[7]_55 ;
  wire \dReg_reg[7]_56 ;
  wire \dReg_reg[7]_57 ;
  wire \dReg_reg[7]_58 ;
  wire \dReg_reg[7]_59 ;
  wire \dReg_reg[7]_6 ;
  wire \dReg_reg[7]_60 ;
  wire \dReg_reg[7]_61 ;
  wire \dReg_reg[7]_62 ;
  wire \dReg_reg[7]_63 ;
  wire \dReg_reg[7]_64 ;
  wire \dReg_reg[7]_65 ;
  wire \dReg_reg[7]_66 ;
  wire \dReg_reg[7]_67 ;
  wire \dReg_reg[7]_68 ;
  wire \dReg_reg[7]_69 ;
  wire \dReg_reg[7]_7 ;
  wire \dReg_reg[7]_70 ;
  wire \dReg_reg[7]_8 ;
  wire \dReg_reg[7]_9 ;
  wire [1:0]\dReg_reg[9] ;
  wire [1:0]\dReg_reg[9]_0 ;
  wire [1:0]\dReg_reg[9]_1 ;
  wire [1:0]\dReg_reg[9]_2 ;
  wire [1:0]\dReg_reg[9]_3 ;
  wire [1:0]\dReg_reg[9]_4 ;
  wire [1:0]\dReg_reg[9]_5 ;
  wire [1:0]\dReg_reg[9]_6 ;
  wire [1:0]\dReg_reg[9]_7 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_523 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_524 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_525 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_526 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_527 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_528 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_529 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_530 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_531 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_532 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_533 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_534 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_535 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_536 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_537 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_538 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_539 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_540 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_541 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_542 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_543 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_544 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_545 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_546 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_547 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_548 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_549 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_550 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_551 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_552 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_553 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_554 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_555 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_556 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_557 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_558 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_559 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_560 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_561 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_562 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_563 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_564 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_565 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_566 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_567 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_568 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_569 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_570 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_571 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_572 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_573 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_574 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_575 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_576 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_577 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_578 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_579 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_580 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_581 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_582 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_583 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_584 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_585 ;
  wire \genBit[0].u_ddr_mc_wr_bit_n_586 ;
  wire [0:0]sel;
  wire \wosp_reg[1] ;
  wire [7:0]\wosp_reg[1]_0 ;
  wire [7:0]\wosp_reg[1]_1 ;
  wire [7:0]\wosp_reg[1]_10 ;
  wire [7:0]\wosp_reg[1]_11 ;
  wire [7:0]\wosp_reg[1]_12 ;
  wire [7:0]\wosp_reg[1]_13 ;
  wire [7:0]\wosp_reg[1]_14 ;
  wire [7:0]\wosp_reg[1]_15 ;
  wire [7:0]\wosp_reg[1]_16 ;
  wire [8:0]\wosp_reg[1]_17 ;
  wire [7:0]\wosp_reg[1]_18 ;
  wire [7:0]\wosp_reg[1]_19 ;
  wire [7:0]\wosp_reg[1]_2 ;
  wire [7:0]\wosp_reg[1]_20 ;
  wire [7:0]\wosp_reg[1]_21 ;
  wire [7:0]\wosp_reg[1]_22 ;
  wire [7:0]\wosp_reg[1]_23 ;
  wire [7:0]\wosp_reg[1]_24 ;
  wire [7:0]\wosp_reg[1]_25 ;
  wire [8:0]\wosp_reg[1]_26 ;
  wire [7:0]\wosp_reg[1]_27 ;
  wire [7:0]\wosp_reg[1]_28 ;
  wire [7:0]\wosp_reg[1]_29 ;
  wire [7:0]\wosp_reg[1]_3 ;
  wire [7:0]\wosp_reg[1]_30 ;
  wire [7:0]\wosp_reg[1]_31 ;
  wire [7:0]\wosp_reg[1]_32 ;
  wire [7:0]\wosp_reg[1]_33 ;
  wire [7:0]\wosp_reg[1]_34 ;
  wire [8:0]\wosp_reg[1]_35 ;
  wire [7:0]\wosp_reg[1]_36 ;
  wire [7:0]\wosp_reg[1]_37 ;
  wire [7:0]\wosp_reg[1]_38 ;
  wire [7:0]\wosp_reg[1]_39 ;
  wire [7:0]\wosp_reg[1]_4 ;
  wire [7:0]\wosp_reg[1]_40 ;
  wire [7:0]\wosp_reg[1]_41 ;
  wire [7:0]\wosp_reg[1]_42 ;
  wire [7:0]\wosp_reg[1]_43 ;
  wire [8:0]\wosp_reg[1]_44 ;
  wire [7:0]\wosp_reg[1]_45 ;
  wire [7:0]\wosp_reg[1]_46 ;
  wire [7:0]\wosp_reg[1]_47 ;
  wire [7:0]\wosp_reg[1]_48 ;
  wire [7:0]\wosp_reg[1]_49 ;
  wire [7:0]\wosp_reg[1]_5 ;
  wire [7:0]\wosp_reg[1]_50 ;
  wire [7:0]\wosp_reg[1]_51 ;
  wire [7:0]\wosp_reg[1]_52 ;
  wire [8:0]\wosp_reg[1]_53 ;
  wire [7:0]\wosp_reg[1]_54 ;
  wire [7:0]\wosp_reg[1]_55 ;
  wire [7:0]\wosp_reg[1]_56 ;
  wire [7:0]\wosp_reg[1]_57 ;
  wire [7:0]\wosp_reg[1]_58 ;
  wire [7:0]\wosp_reg[1]_59 ;
  wire [7:0]\wosp_reg[1]_6 ;
  wire [7:0]\wosp_reg[1]_60 ;
  wire [7:0]\wosp_reg[1]_61 ;
  wire \wosp_reg[1]_62 ;
  wire [7:0]\wosp_reg[1]_7 ;
  wire [8:0]\wosp_reg[1]_8 ;
  wire [7:0]\wosp_reg[1]_9 ;
  wire \wosp_reg[2] ;
  wire \wosp_reg[2]_rep ;
  wire \wosp_reg[2]_rep__0 ;
  wire \wosp_reg[2]_rep__1 ;
  wire \wosp_reg[2]_rep__2 ;
  wire \wosp_reg[2]_rep__3 ;
  wire \wosp_reg[2]_rep__4 ;
  wire \wosp_reg[2]_rep__5 ;
  wire \wosp_reg[2]_rep__6 ;
  wire \wosp_reg[2]_rep__7 ;
  wire wrDataVal_reg;

  ddr4_0_ddr4_v2_2_17_cal_wr_bit \genBit[0].u_ddr_mc_wr_bit 
       (.D(D),
        .DMOut(DMOut),
        .DQOut(DQOut),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[7:0]),
        .dReg(dReg),
        .dReg_0(dReg_0),
        .dReg_18(dReg_18),
        .dReg_27(dReg_27),
        .dReg_36(dReg_36),
        .dReg_45(dReg_45),
        .dReg_9(dReg_9),
        .dReg__0(dReg__0),
        .dReg__0_1(dReg__0_1),
        .dReg__0_10(dReg__0_10),
        .dReg__0_19(dReg__0_19),
        .dReg__0_2(dReg__0_2),
        .dReg__0_28(dReg__0_28),
        .dReg__0_37(dReg__0_37),
        .dReg__0_46(dReg__0_46),
        .dReg__1(dReg__1),
        .dReg__1_11(dReg__1_11),
        .dReg__1_2(dReg__1_2),
        .dReg__1_20(dReg__1_20),
        .dReg__1_29(dReg__1_29),
        .dReg__1_3(dReg__1_3),
        .dReg__1_38(dReg__1_38),
        .dReg__1_47(dReg__1_47),
        .dReg__2(dReg__2),
        .dReg__2_12(dReg__2_12),
        .dReg__2_21(dReg__2_21),
        .dReg__2_3(dReg__2_3),
        .dReg__2_30(dReg__2_30),
        .dReg__2_39(dReg__2_39),
        .dReg__2_4(dReg__2_4),
        .dReg__2_48(dReg__2_48),
        .dReg__3(dReg__3),
        .dReg__3_13(dReg__3_13),
        .dReg__3_22(dReg__3_22),
        .dReg__3_31(dReg__3_31),
        .dReg__3_4(dReg__3_4),
        .dReg__3_40(dReg__3_40),
        .dReg__3_49(dReg__3_49),
        .dReg__3_5(dReg__3_5),
        .dReg__4(dReg__4),
        .dReg__4_14(dReg__4_14),
        .dReg__4_23(dReg__4_23),
        .dReg__4_32(dReg__4_32),
        .dReg__4_41(dReg__4_41),
        .dReg__4_5(dReg__4_5),
        .dReg__4_50(dReg__4_50),
        .dReg__4_6(dReg__4_6),
        .dReg__5(dReg__5),
        .dReg__5_15(dReg__5_15),
        .dReg__5_24(dReg__5_24),
        .dReg__5_33(dReg__5_33),
        .dReg__5_42(dReg__5_42),
        .dReg__5_51(dReg__5_51),
        .dReg__5_6(dReg__5_6),
        .dReg__5_7(dReg__5_7),
        .dReg__6(dReg__6),
        .dReg__6_16(dReg__6_16),
        .dReg__6_25(dReg__6_25),
        .dReg__6_34(dReg__6_34),
        .dReg__6_43(dReg__6_43),
        .dReg__6_52(dReg__6_52),
        .dReg__6_7(dReg__6_7),
        .dReg__6_8(dReg__6_8),
        .dReg__7(dReg__7),
        .dReg__7_17(dReg__7_17),
        .dReg__7_26(dReg__7_26),
        .dReg__7_35(dReg__7_35),
        .dReg__7_44(dReg__7_44),
        .dReg__7_53(dReg__7_53),
        .dReg__7_8(dReg__7_8),
        .dReg__7_9(dReg__7_9),
        .\dReg_reg[10]_0 (\dReg_reg[10]_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_0 ),
        .\dReg_reg[6]_0 (\dReg_reg[6] ),
        .\dReg_reg[6]_1 (\dReg_reg[6]_0 ),
        .\dReg_reg[6]_10 (\dReg_reg[6]_9 ),
        .\dReg_reg[6]_11 (\dReg_reg[6]_10 ),
        .\dReg_reg[6]_12 (\dReg_reg[6]_11 ),
        .\dReg_reg[6]_13 (\dReg_reg[6]_12 ),
        .\dReg_reg[6]_14 (\dReg_reg[6]_13 ),
        .\dReg_reg[6]_15 (\dReg_reg[6]_14 ),
        .\dReg_reg[6]_16 (\dReg_reg[6]_15 ),
        .\dReg_reg[6]_17 (\dReg_reg[6]_16 ),
        .\dReg_reg[6]_18 (\dReg_reg[6]_17 ),
        .\dReg_reg[6]_19 (\dReg_reg[6]_18 ),
        .\dReg_reg[6]_2 (\dReg_reg[6]_1 ),
        .\dReg_reg[6]_20 (\dReg_reg[6]_19 ),
        .\dReg_reg[6]_21 (\dReg_reg[6]_20 ),
        .\dReg_reg[6]_22 (\dReg_reg[6]_21 ),
        .\dReg_reg[6]_23 (\dReg_reg[6]_22 ),
        .\dReg_reg[6]_24 (\dReg_reg[6]_23 ),
        .\dReg_reg[6]_25 (\dReg_reg[6]_24 ),
        .\dReg_reg[6]_26 (\dReg_reg[6]_25 ),
        .\dReg_reg[6]_27 (\dReg_reg[6]_26 ),
        .\dReg_reg[6]_28 (\dReg_reg[6]_27 ),
        .\dReg_reg[6]_29 (\dReg_reg[6]_28 ),
        .\dReg_reg[6]_3 (\dReg_reg[6]_2 ),
        .\dReg_reg[6]_30 (\dReg_reg[6]_29 ),
        .\dReg_reg[6]_31 (\dReg_reg[6]_30 ),
        .\dReg_reg[6]_32 (\dReg_reg[6]_31 ),
        .\dReg_reg[6]_33 (\dReg_reg[6]_32 ),
        .\dReg_reg[6]_34 (\dReg_reg[6]_33 ),
        .\dReg_reg[6]_35 (\dReg_reg[6]_34 ),
        .\dReg_reg[6]_36 (\dReg_reg[6]_35 ),
        .\dReg_reg[6]_37 (\dReg_reg[6]_36 ),
        .\dReg_reg[6]_38 (\dReg_reg[6]_37 ),
        .\dReg_reg[6]_39 (\dReg_reg[6]_38 ),
        .\dReg_reg[6]_4 (\dReg_reg[6]_3 ),
        .\dReg_reg[6]_40 (\dReg_reg[6]_39 ),
        .\dReg_reg[6]_41 (\dReg_reg[6]_40 ),
        .\dReg_reg[6]_42 (\dReg_reg[6]_41 ),
        .\dReg_reg[6]_43 (\dReg_reg[6]_42 ),
        .\dReg_reg[6]_44 (\dReg_reg[6]_43 ),
        .\dReg_reg[6]_45 (\dReg_reg[6]_44 ),
        .\dReg_reg[6]_46 (\dReg_reg[6]_45 ),
        .\dReg_reg[6]_47 (\dReg_reg[6]_46 ),
        .\dReg_reg[6]_48 (\dReg_reg[6]_47 ),
        .\dReg_reg[6]_49 (\dReg_reg[6]_48 ),
        .\dReg_reg[6]_5 (\dReg_reg[6]_4 ),
        .\dReg_reg[6]_50 (\dReg_reg[6]_49 ),
        .\dReg_reg[6]_51 (\dReg_reg[6]_50 ),
        .\dReg_reg[6]_52 (\dReg_reg[6]_51 ),
        .\dReg_reg[6]_53 (\dReg_reg[6]_52 ),
        .\dReg_reg[6]_54 (\dReg_reg[6]_53 ),
        .\dReg_reg[6]_55 (\dReg_reg[6]_54 ),
        .\dReg_reg[6]_56 (\dReg_reg[6]_55 ),
        .\dReg_reg[6]_57 (\dReg_reg[6]_56 ),
        .\dReg_reg[6]_58 (\dReg_reg[6]_57 ),
        .\dReg_reg[6]_59 (\dReg_reg[6]_58 ),
        .\dReg_reg[6]_6 (\dReg_reg[6]_5 ),
        .\dReg_reg[6]_60 (\dReg_reg[6]_59 ),
        .\dReg_reg[6]_61 (\dReg_reg[6]_60 ),
        .\dReg_reg[6]_62 (\dReg_reg[6]_61 ),
        .\dReg_reg[6]_63 (\dReg_reg[6]_62 ),
        .\dReg_reg[6]_64 (\dReg_reg[6]_63 ),
        .\dReg_reg[6]_65 (\dReg_reg[6]_64 ),
        .\dReg_reg[6]_66 (\dReg_reg[6]_65 ),
        .\dReg_reg[6]_67 (\dReg_reg[6]_66 ),
        .\dReg_reg[6]_68 (\dReg_reg[6]_67 ),
        .\dReg_reg[6]_69 (\dReg_reg[6]_68 ),
        .\dReg_reg[6]_7 (\dReg_reg[6]_6 ),
        .\dReg_reg[6]_70 (\dReg_reg[6]_69 ),
        .\dReg_reg[6]_71 (\dReg_reg[6]_70 ),
        .\dReg_reg[6]_72 (\dReg_reg[6]_71 ),
        .\dReg_reg[6]_8 (\dReg_reg[6]_7 ),
        .\dReg_reg[6]_9 (\dReg_reg[6]_8 ),
        .\dReg_reg[7]_0 (\dReg_reg[7] ),
        .\dReg_reg[7]_1 (\dReg_reg[7]_0 ),
        .\dReg_reg[7]_10 (\dReg_reg[7]_9 ),
        .\dReg_reg[7]_11 (\dReg_reg[7]_10 ),
        .\dReg_reg[7]_12 (\dReg_reg[7]_11 ),
        .\dReg_reg[7]_13 (\dReg_reg[7]_12 ),
        .\dReg_reg[7]_14 (\dReg_reg[7]_13 ),
        .\dReg_reg[7]_15 (\dReg_reg[7]_14 ),
        .\dReg_reg[7]_16 (\dReg_reg[7]_15 ),
        .\dReg_reg[7]_17 (\dReg_reg[7]_16 ),
        .\dReg_reg[7]_18 (\dReg_reg[7]_17 ),
        .\dReg_reg[7]_19 (\dReg_reg[7]_18 ),
        .\dReg_reg[7]_2 (\dReg_reg[7]_1 ),
        .\dReg_reg[7]_20 (\dReg_reg[7]_19 ),
        .\dReg_reg[7]_21 (\dReg_reg[7]_20 ),
        .\dReg_reg[7]_22 (\dReg_reg[7]_21 ),
        .\dReg_reg[7]_23 (\dReg_reg[7]_22 ),
        .\dReg_reg[7]_24 (\dReg_reg[7]_23 ),
        .\dReg_reg[7]_25 (\dReg_reg[7]_24 ),
        .\dReg_reg[7]_26 (\dReg_reg[7]_25 ),
        .\dReg_reg[7]_27 (\dReg_reg[7]_26 ),
        .\dReg_reg[7]_28 (\dReg_reg[7]_27 ),
        .\dReg_reg[7]_29 (\dReg_reg[7]_28 ),
        .\dReg_reg[7]_3 (\dReg_reg[7]_2 ),
        .\dReg_reg[7]_30 (\dReg_reg[7]_29 ),
        .\dReg_reg[7]_31 (\dReg_reg[7]_30 ),
        .\dReg_reg[7]_32 (\dReg_reg[7]_31 ),
        .\dReg_reg[7]_33 (\dReg_reg[7]_32 ),
        .\dReg_reg[7]_34 (\dReg_reg[7]_33 ),
        .\dReg_reg[7]_35 (\dReg_reg[7]_34 ),
        .\dReg_reg[7]_36 (\dReg_reg[7]_35 ),
        .\dReg_reg[7]_37 (\dReg_reg[7]_36 ),
        .\dReg_reg[7]_38 (\dReg_reg[7]_37 ),
        .\dReg_reg[7]_39 (\dReg_reg[7]_38 ),
        .\dReg_reg[7]_4 (\dReg_reg[7]_3 ),
        .\dReg_reg[7]_40 (\dReg_reg[7]_39 ),
        .\dReg_reg[7]_41 (\dReg_reg[7]_40 ),
        .\dReg_reg[7]_42 (\dReg_reg[7]_41 ),
        .\dReg_reg[7]_43 (\dReg_reg[7]_42 ),
        .\dReg_reg[7]_44 (\dReg_reg[7]_43 ),
        .\dReg_reg[7]_45 (\dReg_reg[7]_44 ),
        .\dReg_reg[7]_46 (\dReg_reg[7]_45 ),
        .\dReg_reg[7]_47 (\dReg_reg[7]_46 ),
        .\dReg_reg[7]_48 (\dReg_reg[7]_47 ),
        .\dReg_reg[7]_49 (\dReg_reg[7]_48 ),
        .\dReg_reg[7]_5 (\dReg_reg[7]_4 ),
        .\dReg_reg[7]_50 (\dReg_reg[7]_49 ),
        .\dReg_reg[7]_51 (\dReg_reg[7]_50 ),
        .\dReg_reg[7]_52 (\dReg_reg[7]_51 ),
        .\dReg_reg[7]_53 (\dReg_reg[7]_52 ),
        .\dReg_reg[7]_54 (\dReg_reg[7]_53 ),
        .\dReg_reg[7]_55 (\dReg_reg[7]_54 ),
        .\dReg_reg[7]_56 (\dReg_reg[7]_55 ),
        .\dReg_reg[7]_57 (\dReg_reg[7]_56 ),
        .\dReg_reg[7]_58 (\dReg_reg[7]_57 ),
        .\dReg_reg[7]_59 (\dReg_reg[7]_58 ),
        .\dReg_reg[7]_6 (\dReg_reg[7]_5 ),
        .\dReg_reg[7]_60 (\dReg_reg[7]_59 ),
        .\dReg_reg[7]_61 (\dReg_reg[7]_60 ),
        .\dReg_reg[7]_62 (\dReg_reg[7]_61 ),
        .\dReg_reg[7]_63 (\dReg_reg[7]_62 ),
        .\dReg_reg[7]_64 (\dReg_reg[7]_63 ),
        .\dReg_reg[7]_65 (\dReg_reg[7]_64 ),
        .\dReg_reg[7]_66 (\dReg_reg[7]_65 ),
        .\dReg_reg[7]_67 (\dReg_reg[7]_66 ),
        .\dReg_reg[7]_68 (\dReg_reg[7]_67 ),
        .\dReg_reg[7]_69 (\dReg_reg[7]_68 ),
        .\dReg_reg[7]_7 (\dReg_reg[7]_6 ),
        .\dReg_reg[7]_70 (\dReg_reg[7]_69 ),
        .\dReg_reg[7]_71 (\dReg_reg[7]_70 ),
        .\dReg_reg[7]_8 (\dReg_reg[7]_7 ),
        .\dReg_reg[7]_9 (\dReg_reg[7]_8 ),
        .\dReg_reg[9]_0 (\dReg_reg[9] ),
        .sel(sel),
        .\wosp_reg[1]_0 (\wosp_reg[1] ),
        .\wosp_reg[1]_1 (\wosp_reg[1]_0 ),
        .\wosp_reg[1]_10 (\wosp_reg[1]_9 ),
        .\wosp_reg[1]_11 (\wosp_reg[1]_10 ),
        .\wosp_reg[1]_12 (\wosp_reg[1]_11 ),
        .\wosp_reg[1]_13 (\wosp_reg[1]_12 ),
        .\wosp_reg[1]_14 (\wosp_reg[1]_13 ),
        .\wosp_reg[1]_15 (\wosp_reg[1]_14 ),
        .\wosp_reg[1]_16 (\wosp_reg[1]_15 ),
        .\wosp_reg[1]_17 (\wosp_reg[1]_16 ),
        .\wosp_reg[1]_18 (\wosp_reg[1]_17 ),
        .\wosp_reg[1]_19 (\wosp_reg[1]_18 ),
        .\wosp_reg[1]_2 (\wosp_reg[1]_1 ),
        .\wosp_reg[1]_20 (\wosp_reg[1]_19 ),
        .\wosp_reg[1]_21 (\wosp_reg[1]_20 ),
        .\wosp_reg[1]_22 (\wosp_reg[1]_21 ),
        .\wosp_reg[1]_23 (\wosp_reg[1]_22 ),
        .\wosp_reg[1]_24 (\wosp_reg[1]_23 ),
        .\wosp_reg[1]_25 (\wosp_reg[1]_24 ),
        .\wosp_reg[1]_26 (\wosp_reg[1]_25 ),
        .\wosp_reg[1]_27 (\wosp_reg[1]_26 ),
        .\wosp_reg[1]_28 (\wosp_reg[1]_27 ),
        .\wosp_reg[1]_29 (\wosp_reg[1]_28 ),
        .\wosp_reg[1]_3 (\wosp_reg[1]_2 ),
        .\wosp_reg[1]_30 (\wosp_reg[1]_29 ),
        .\wosp_reg[1]_31 (\wosp_reg[1]_30 ),
        .\wosp_reg[1]_32 (\wosp_reg[1]_31 ),
        .\wosp_reg[1]_33 (\wosp_reg[1]_32 ),
        .\wosp_reg[1]_34 (\wosp_reg[1]_33 ),
        .\wosp_reg[1]_35 (\wosp_reg[1]_34 ),
        .\wosp_reg[1]_36 (\wosp_reg[1]_35 ),
        .\wosp_reg[1]_37 (\wosp_reg[1]_36 ),
        .\wosp_reg[1]_38 (\wosp_reg[1]_37 ),
        .\wosp_reg[1]_39 (\wosp_reg[1]_38 ),
        .\wosp_reg[1]_4 (\wosp_reg[1]_3 ),
        .\wosp_reg[1]_40 (\wosp_reg[1]_39 ),
        .\wosp_reg[1]_41 (\wosp_reg[1]_40 ),
        .\wosp_reg[1]_42 (\wosp_reg[1]_41 ),
        .\wosp_reg[1]_43 (\wosp_reg[1]_42 ),
        .\wosp_reg[1]_44 (\wosp_reg[1]_43 ),
        .\wosp_reg[1]_45 (\wosp_reg[1]_44 ),
        .\wosp_reg[1]_46 (\wosp_reg[1]_45 ),
        .\wosp_reg[1]_47 (\wosp_reg[1]_46 ),
        .\wosp_reg[1]_48 (\wosp_reg[1]_47 ),
        .\wosp_reg[1]_49 (\wosp_reg[1]_48 ),
        .\wosp_reg[1]_5 (\wosp_reg[1]_4 ),
        .\wosp_reg[1]_50 (\wosp_reg[1]_49 ),
        .\wosp_reg[1]_51 (\wosp_reg[1]_50 ),
        .\wosp_reg[1]_52 (\wosp_reg[1]_51 ),
        .\wosp_reg[1]_53 (\wosp_reg[1]_52 ),
        .\wosp_reg[1]_54 (\wosp_reg[1]_53 ),
        .\wosp_reg[1]_55 (\wosp_reg[1]_54 ),
        .\wosp_reg[1]_56 (\wosp_reg[1]_55 ),
        .\wosp_reg[1]_57 (\wosp_reg[1]_56 ),
        .\wosp_reg[1]_58 (\wosp_reg[1]_57 ),
        .\wosp_reg[1]_59 (\wosp_reg[1]_58 ),
        .\wosp_reg[1]_6 (\wosp_reg[1]_5 ),
        .\wosp_reg[1]_60 (\wosp_reg[1]_59 ),
        .\wosp_reg[1]_61 (\wosp_reg[1]_60 ),
        .\wosp_reg[1]_62 (\wosp_reg[1]_61 ),
        .\wosp_reg[1]_63 ({\genBit[0].u_ddr_mc_wr_bit_n_523 ,\genBit[0].u_ddr_mc_wr_bit_n_524 ,\genBit[0].u_ddr_mc_wr_bit_n_525 ,\genBit[0].u_ddr_mc_wr_bit_n_526 ,\genBit[0].u_ddr_mc_wr_bit_n_527 ,\genBit[0].u_ddr_mc_wr_bit_n_528 ,\genBit[0].u_ddr_mc_wr_bit_n_529 ,\genBit[0].u_ddr_mc_wr_bit_n_530 }),
        .\wosp_reg[1]_64 ({\genBit[0].u_ddr_mc_wr_bit_n_531 ,\genBit[0].u_ddr_mc_wr_bit_n_532 ,\genBit[0].u_ddr_mc_wr_bit_n_533 ,\genBit[0].u_ddr_mc_wr_bit_n_534 ,\genBit[0].u_ddr_mc_wr_bit_n_535 ,\genBit[0].u_ddr_mc_wr_bit_n_536 ,\genBit[0].u_ddr_mc_wr_bit_n_537 ,\genBit[0].u_ddr_mc_wr_bit_n_538 }),
        .\wosp_reg[1]_65 ({\genBit[0].u_ddr_mc_wr_bit_n_539 ,\genBit[0].u_ddr_mc_wr_bit_n_540 ,\genBit[0].u_ddr_mc_wr_bit_n_541 ,\genBit[0].u_ddr_mc_wr_bit_n_542 ,\genBit[0].u_ddr_mc_wr_bit_n_543 ,\genBit[0].u_ddr_mc_wr_bit_n_544 ,\genBit[0].u_ddr_mc_wr_bit_n_545 ,\genBit[0].u_ddr_mc_wr_bit_n_546 }),
        .\wosp_reg[1]_66 ({\genBit[0].u_ddr_mc_wr_bit_n_547 ,\genBit[0].u_ddr_mc_wr_bit_n_548 ,\genBit[0].u_ddr_mc_wr_bit_n_549 ,\genBit[0].u_ddr_mc_wr_bit_n_550 ,\genBit[0].u_ddr_mc_wr_bit_n_551 ,\genBit[0].u_ddr_mc_wr_bit_n_552 ,\genBit[0].u_ddr_mc_wr_bit_n_553 ,\genBit[0].u_ddr_mc_wr_bit_n_554 }),
        .\wosp_reg[1]_67 ({\genBit[0].u_ddr_mc_wr_bit_n_555 ,\genBit[0].u_ddr_mc_wr_bit_n_556 ,\genBit[0].u_ddr_mc_wr_bit_n_557 ,\genBit[0].u_ddr_mc_wr_bit_n_558 ,\genBit[0].u_ddr_mc_wr_bit_n_559 ,\genBit[0].u_ddr_mc_wr_bit_n_560 ,\genBit[0].u_ddr_mc_wr_bit_n_561 ,\genBit[0].u_ddr_mc_wr_bit_n_562 }),
        .\wosp_reg[1]_68 ({\genBit[0].u_ddr_mc_wr_bit_n_563 ,\genBit[0].u_ddr_mc_wr_bit_n_564 ,\genBit[0].u_ddr_mc_wr_bit_n_565 ,\genBit[0].u_ddr_mc_wr_bit_n_566 ,\genBit[0].u_ddr_mc_wr_bit_n_567 ,\genBit[0].u_ddr_mc_wr_bit_n_568 ,\genBit[0].u_ddr_mc_wr_bit_n_569 ,\genBit[0].u_ddr_mc_wr_bit_n_570 }),
        .\wosp_reg[1]_69 ({\genBit[0].u_ddr_mc_wr_bit_n_571 ,\genBit[0].u_ddr_mc_wr_bit_n_572 ,\genBit[0].u_ddr_mc_wr_bit_n_573 ,\genBit[0].u_ddr_mc_wr_bit_n_574 ,\genBit[0].u_ddr_mc_wr_bit_n_575 ,\genBit[0].u_ddr_mc_wr_bit_n_576 ,\genBit[0].u_ddr_mc_wr_bit_n_577 ,\genBit[0].u_ddr_mc_wr_bit_n_578 }),
        .\wosp_reg[1]_7 (\wosp_reg[1]_6 ),
        .\wosp_reg[1]_70 ({\genBit[0].u_ddr_mc_wr_bit_n_579 ,\genBit[0].u_ddr_mc_wr_bit_n_580 ,\genBit[0].u_ddr_mc_wr_bit_n_581 ,\genBit[0].u_ddr_mc_wr_bit_n_582 ,\genBit[0].u_ddr_mc_wr_bit_n_583 ,\genBit[0].u_ddr_mc_wr_bit_n_584 ,\genBit[0].u_ddr_mc_wr_bit_n_585 ,\genBit[0].u_ddr_mc_wr_bit_n_586 }),
        .\wosp_reg[1]_71 (\wosp_reg[1]_62 ),
        .\wosp_reg[1]_8 (\wosp_reg[1]_7 ),
        .\wosp_reg[1]_9 (\wosp_reg[1]_8 ),
        .\wosp_reg[2]_0 (\wosp_reg[2] ),
        .\wosp_reg[2]_rep_0 (\wosp_reg[2]_rep ),
        .\wosp_reg[2]_rep__0_0 (\wosp_reg[2]_rep__0 ),
        .\wosp_reg[2]_rep__1_0 (\wosp_reg[2]_rep__1 ),
        .\wosp_reg[2]_rep__2_0 (\wosp_reg[2]_rep__2 ),
        .\wosp_reg[2]_rep__3_0 (\wosp_reg[2]_rep__3 ),
        .\wosp_reg[2]_rep__4_0 (\wosp_reg[2]_rep__4 ),
        .\wosp_reg[2]_rep__5_0 (\wosp_reg[2]_rep__5 ),
        .\wosp_reg[2]_rep__6_0 (\wosp_reg[2]_rep__6 ),
        .\wosp_reg[2]_rep__7_0 (\wosp_reg[2]_rep__7 ),
        .\wosp_reg[2]_rep__7_1 (\dReg_reg[10] ),
        .wrDataVal_reg(wrDataVal_reg));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_34 \genBit[1].u_ddr_mc_wr_bit 
       (.D({\genBit[0].u_ddr_mc_wr_bit_n_579 ,\genBit[0].u_ddr_mc_wr_bit_n_580 ,\dReg_reg[9]_0 ,\genBit[0].u_ddr_mc_wr_bit_n_581 ,\genBit[0].u_ddr_mc_wr_bit_n_582 ,\genBit[0].u_ddr_mc_wr_bit_n_583 ,\genBit[0].u_ddr_mc_wr_bit_n_584 ,\genBit[0].u_ddr_mc_wr_bit_n_585 ,\genBit[0].u_ddr_mc_wr_bit_n_586 }),
        .DQOut(DQOut[463:462]),
        .Q({dReg__0_2[13:12],ch0_mcal_DQOut[15:8]}),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_1 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_1 ),
        .\dReg_reg[15]_0 ({dReg__0_2[15:14],dReg__0_2[11:10]}),
        .\dReg_reg[15]_1 (wrDataVal_reg));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_35 \genBit[2].u_ddr_mc_wr_bit 
       (.D({\genBit[0].u_ddr_mc_wr_bit_n_571 ,\genBit[0].u_ddr_mc_wr_bit_n_572 ,\dReg_reg[9]_1 ,\genBit[0].u_ddr_mc_wr_bit_n_573 ,\genBit[0].u_ddr_mc_wr_bit_n_574 ,\genBit[0].u_ddr_mc_wr_bit_n_575 ,\genBit[0].u_ddr_mc_wr_bit_n_576 ,\genBit[0].u_ddr_mc_wr_bit_n_577 ,\genBit[0].u_ddr_mc_wr_bit_n_578 }),
        .DQOut(DQOut[471:470]),
        .Q({dReg__1_3[13:12],ch0_mcal_DQOut[23:16]}),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_2 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_2 ),
        .\dReg_reg[15]_0 ({dReg__1_3[15:14],dReg__1_3[11:10]}),
        .\dReg_reg[15]_1 (wrDataVal_reg));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_36 \genBit[3].u_ddr_mc_wr_bit 
       (.D({\genBit[0].u_ddr_mc_wr_bit_n_563 ,\genBit[0].u_ddr_mc_wr_bit_n_564 ,\dReg_reg[9]_2 ,\genBit[0].u_ddr_mc_wr_bit_n_565 ,\genBit[0].u_ddr_mc_wr_bit_n_566 ,\genBit[0].u_ddr_mc_wr_bit_n_567 ,\genBit[0].u_ddr_mc_wr_bit_n_568 ,\genBit[0].u_ddr_mc_wr_bit_n_569 ,\genBit[0].u_ddr_mc_wr_bit_n_570 }),
        .DQOut(DQOut[479:478]),
        .Q({dReg__2_4[13:12],ch0_mcal_DQOut[31:24]}),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_3 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_3 ),
        .\dReg_reg[15]_0 ({dReg__2_4[15:14],dReg__2_4[11:10]}),
        .\dReg_reg[15]_1 (wrDataVal_reg));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_37 \genBit[4].u_ddr_mc_wr_bit 
       (.D({\genBit[0].u_ddr_mc_wr_bit_n_555 ,\genBit[0].u_ddr_mc_wr_bit_n_556 ,\dReg_reg[9]_3 ,\genBit[0].u_ddr_mc_wr_bit_n_557 ,\genBit[0].u_ddr_mc_wr_bit_n_558 ,\genBit[0].u_ddr_mc_wr_bit_n_559 ,\genBit[0].u_ddr_mc_wr_bit_n_560 ,\genBit[0].u_ddr_mc_wr_bit_n_561 ,\genBit[0].u_ddr_mc_wr_bit_n_562 }),
        .DQOut(DQOut[487:486]),
        .Q({dReg__3_5[13:12],ch0_mcal_DQOut[39:32]}),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_4 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_4 ),
        .\dReg_reg[15]_0 ({dReg__3_5[15:14],dReg__3_5[11:10]}),
        .\dReg_reg[15]_1 (wrDataVal_reg));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_38 \genBit[5].u_ddr_mc_wr_bit 
       (.D({\genBit[0].u_ddr_mc_wr_bit_n_547 ,\genBit[0].u_ddr_mc_wr_bit_n_548 ,\dReg_reg[9]_4 ,\genBit[0].u_ddr_mc_wr_bit_n_549 ,\genBit[0].u_ddr_mc_wr_bit_n_550 ,\genBit[0].u_ddr_mc_wr_bit_n_551 ,\genBit[0].u_ddr_mc_wr_bit_n_552 ,\genBit[0].u_ddr_mc_wr_bit_n_553 ,\genBit[0].u_ddr_mc_wr_bit_n_554 }),
        .DQOut(DQOut[495:494]),
        .Q({dReg__4_6[13:12],ch0_mcal_DQOut[47:40]}),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_5 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_5 ),
        .\dReg_reg[15]_0 ({dReg__4_6[15:14],dReg__4_6[11:10]}),
        .\dReg_reg[15]_1 (wrDataVal_reg));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_39 \genBit[6].u_ddr_mc_wr_bit 
       (.D({\genBit[0].u_ddr_mc_wr_bit_n_539 ,\genBit[0].u_ddr_mc_wr_bit_n_540 ,\dReg_reg[9]_5 ,\genBit[0].u_ddr_mc_wr_bit_n_541 ,\genBit[0].u_ddr_mc_wr_bit_n_542 ,\genBit[0].u_ddr_mc_wr_bit_n_543 ,\genBit[0].u_ddr_mc_wr_bit_n_544 ,\genBit[0].u_ddr_mc_wr_bit_n_545 ,\genBit[0].u_ddr_mc_wr_bit_n_546 }),
        .DQOut(DQOut[503:502]),
        .Q({dReg__5_7[13:12],ch0_mcal_DQOut[55:48]}),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_6 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_6 ),
        .\dReg_reg[15]_0 ({dReg__5_7[15:14],dReg__5_7[11:10]}),
        .\dReg_reg[15]_1 (wrDataVal_reg));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_40 \genBit[7].u_ddr_mc_wr_bit 
       (.D({\genBit[0].u_ddr_mc_wr_bit_n_531 ,\genBit[0].u_ddr_mc_wr_bit_n_532 ,\dReg_reg[9]_6 ,\genBit[0].u_ddr_mc_wr_bit_n_533 ,\genBit[0].u_ddr_mc_wr_bit_n_534 ,\genBit[0].u_ddr_mc_wr_bit_n_535 ,\genBit[0].u_ddr_mc_wr_bit_n_536 ,\genBit[0].u_ddr_mc_wr_bit_n_537 ,\genBit[0].u_ddr_mc_wr_bit_n_538 }),
        .DQOut(DQOut[511:510]),
        .Q({dReg__6_8[13:12],ch0_mcal_DQOut[63:56]}),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_7 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_7 ),
        .\dReg_reg[15]_0 ({dReg__6_8[15:14],dReg__6_8[11:10]}),
        .\dReg_reg[15]_1 (wrDataVal_reg));
  ddr4_0_ddr4_v2_2_17_cal_wr_bit_41 u_ddr_mc_wr_dm
       (.D({\genBit[0].u_ddr_mc_wr_bit_n_523 ,\genBit[0].u_ddr_mc_wr_bit_n_524 ,\dReg_reg[9]_7 ,\genBit[0].u_ddr_mc_wr_bit_n_525 ,\genBit[0].u_ddr_mc_wr_bit_n_526 ,\genBit[0].u_ddr_mc_wr_bit_n_527 ,\genBit[0].u_ddr_mc_wr_bit_n_528 ,\genBit[0].u_ddr_mc_wr_bit_n_529 ,\genBit[0].u_ddr_mc_wr_bit_n_530 }),
        .DMOut(DMOut[63:62]),
        .Q({dReg__7_9[13:12],ch0_mcal_DMOut_n}),
        .\dReg_reg[10]_0 (\dReg_reg[10] ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_8 ),
        .\dReg_reg[11]_0 (\dReg_reg[11] ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_8 ),
        .\dReg_reg[15]_0 ({dReg__7_9[15:14],dReg__7_9[11:10]}),
        .\dReg_reg[15]_1 (wrDataVal_reg));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_write" *) 
module ddr4_0_ddr4_v2_2_17_cal_write
   (wrDataVal_reg_0,
    \wrQ_reg[0][0]_0 ,
    \wosp_reg[1] ,
    \wosp_reg[2] ,
    \oe_0_mux_cal_reg[0]_0 ,
    \wosp_reg[2]_rep ,
    \wosp_reg[2]_rep__0 ,
    \wosp_reg[2]_rep__1 ,
    \wosp_reg[2]_rep__2 ,
    \wosp_reg[2]_rep__3 ,
    \wosp_reg[2]_rep__4 ,
    \wosp_reg[2]_rep__5 ,
    \wosp_reg[2]_rep__6 ,
    \wosp_reg[2]_rep__7 ,
    pointer_we,
    \wrQ_reg[0][0]_1 ,
    \wrQ_reg[1][8]_0 ,
    ADDRC,
    \wrQ_reg[0][0]_rep_0 ,
    ADDRA,
    \wrQ_reg[0][8]_rep__0_0 ,
    \wrQ_reg[0][8]_rep__1_0 ,
    \oe_upp_reg[3]_0 ,
    \oe_low_reg[3]_0 ,
    ch0_mcal_DQOut,
    ch0_mcal_DMOut_n,
    cal_oe_dis_upp,
    \dReg_reg[10] ,
    cal_oe_dis_low,
    out,
    \oe_0_mux_cal_reg[0]_1 ,
    \oe_low_reg[5]_0 ,
    \rams[1].RAM32M0 ,
    mcWrCAS,
    mcCasSlot2,
    \wrQ_reg[0][2]_0 ,
    DQOut,
    DMOut,
    \dReg_reg[7] ,
    \dReg_reg[6] ,
    \dReg_reg[7]_0 ,
    \dReg_reg[6]_0 ,
    \dReg_reg[7]_1 ,
    \dReg_reg[6]_1 ,
    \dReg_reg[7]_2 ,
    \dReg_reg[6]_2 ,
    \dReg_reg[7]_3 ,
    \dReg_reg[6]_3 ,
    \dReg_reg[7]_4 ,
    \dReg_reg[6]_4 ,
    \dReg_reg[7]_5 ,
    \dReg_reg[6]_5 ,
    \dReg_reg[7]_6 ,
    \dReg_reg[6]_6 ,
    \dReg_reg[7]_7 ,
    \dReg_reg[6]_7 ,
    \dReg_reg[7]_8 ,
    \dReg_reg[6]_8 ,
    \dReg_reg[7]_9 ,
    \dReg_reg[6]_9 ,
    \dReg_reg[7]_10 ,
    \dReg_reg[6]_10 ,
    \dReg_reg[7]_11 ,
    \dReg_reg[6]_11 ,
    \dReg_reg[7]_12 ,
    \dReg_reg[6]_12 ,
    \dReg_reg[7]_13 ,
    \dReg_reg[6]_13 ,
    \dReg_reg[7]_14 ,
    \dReg_reg[6]_14 ,
    \dReg_reg[7]_15 ,
    \dReg_reg[6]_15 ,
    \dReg_reg[7]_16 ,
    \dReg_reg[6]_16 ,
    \dReg_reg[7]_17 ,
    \dReg_reg[6]_17 ,
    \dReg_reg[7]_18 ,
    \dReg_reg[6]_18 ,
    \dReg_reg[7]_19 ,
    \dReg_reg[6]_19 ,
    \dReg_reg[7]_20 ,
    \dReg_reg[6]_20 ,
    \dReg_reg[7]_21 ,
    \dReg_reg[6]_21 ,
    \dReg_reg[7]_22 ,
    \dReg_reg[6]_22 ,
    \dReg_reg[7]_23 ,
    \dReg_reg[6]_23 ,
    \dReg_reg[7]_24 ,
    \dReg_reg[6]_24 ,
    \dReg_reg[7]_25 ,
    \dReg_reg[6]_25 ,
    \dReg_reg[7]_26 ,
    \dReg_reg[6]_26 ,
    \dReg_reg[7]_27 ,
    \dReg_reg[6]_27 ,
    \dReg_reg[7]_28 ,
    \dReg_reg[6]_28 ,
    \dReg_reg[7]_29 ,
    \dReg_reg[6]_29 ,
    \dReg_reg[7]_30 ,
    \dReg_reg[6]_30 ,
    \dReg_reg[7]_31 ,
    \dReg_reg[6]_31 ,
    \dReg_reg[7]_32 ,
    \dReg_reg[6]_32 ,
    \dReg_reg[7]_33 ,
    \dReg_reg[6]_33 ,
    \dReg_reg[7]_34 ,
    \dReg_reg[6]_34 ,
    \dReg_reg[7]_35 ,
    \dReg_reg[6]_35 ,
    \dReg_reg[7]_36 ,
    \dReg_reg[6]_36 ,
    \dReg_reg[7]_37 ,
    \dReg_reg[6]_37 ,
    \dReg_reg[7]_38 ,
    \dReg_reg[6]_38 ,
    \dReg_reg[7]_39 ,
    \dReg_reg[6]_39 ,
    \dReg_reg[7]_40 ,
    \dReg_reg[6]_40 ,
    \dReg_reg[7]_41 ,
    \dReg_reg[6]_41 ,
    \dReg_reg[7]_42 ,
    \dReg_reg[6]_42 ,
    \dReg_reg[7]_43 ,
    \dReg_reg[6]_43 ,
    \dReg_reg[7]_44 ,
    \dReg_reg[6]_44 ,
    \dReg_reg[7]_45 ,
    \dReg_reg[6]_45 ,
    \dReg_reg[7]_46 ,
    \dReg_reg[6]_46 ,
    \dReg_reg[7]_47 ,
    \dReg_reg[6]_47 ,
    \dReg_reg[7]_48 ,
    \dReg_reg[6]_48 ,
    \dReg_reg[7]_49 ,
    \dReg_reg[6]_49 ,
    \dReg_reg[7]_50 ,
    \dReg_reg[6]_50 ,
    \dReg_reg[7]_51 ,
    \dReg_reg[6]_51 ,
    \dReg_reg[7]_52 ,
    \dReg_reg[6]_52 ,
    \dReg_reg[7]_53 ,
    \dReg_reg[6]_53 ,
    \dReg_reg[7]_54 ,
    \dReg_reg[6]_54 ,
    \dReg_reg[7]_55 ,
    \dReg_reg[6]_55 ,
    \dReg_reg[7]_56 ,
    \dReg_reg[6]_56 ,
    \dReg_reg[7]_57 ,
    \dReg_reg[6]_57 ,
    \dReg_reg[7]_58 ,
    \dReg_reg[6]_58 ,
    \dReg_reg[7]_59 ,
    \dReg_reg[6]_59 ,
    \dReg_reg[7]_60 ,
    \dReg_reg[6]_60 ,
    \dReg_reg[7]_61 ,
    \dReg_reg[6]_61 ,
    \dReg_reg[7]_62 ,
    \dReg_reg[6]_62 ,
    \dReg_reg[7]_63 ,
    \dReg_reg[6]_63 ,
    \dReg_reg[7]_64 ,
    \dReg_reg[6]_64 ,
    \dReg_reg[7]_65 ,
    \dReg_reg[6]_65 ,
    \dReg_reg[7]_66 ,
    \dReg_reg[6]_66 ,
    \dReg_reg[7]_67 ,
    \dReg_reg[6]_67 ,
    \dReg_reg[7]_68 ,
    \dReg_reg[6]_68 ,
    \dReg_reg[7]_69 ,
    \dReg_reg[6]_69 ,
    \dReg_reg[7]_70 ,
    \dReg_reg[6]_70 ,
    \wrQ_reg[1][8]_1 ,
    \wrQ_nxt[1]_13 ,
    \wrQ_reg[0][8]_0 ,
    \wrQ_reg[0][7]_rep_0 ,
    \wrQ_reg[0][7]_rep__0_0 ,
    \wrQ_reg[0][7]_rep__1_0 ,
    \wrQ_reg[0][5]_rep_0 ,
    \wrQ_reg[0][5]_rep__0_0 ,
    \wrQ_reg[0][5]_rep__1_0 ,
    \wrQ_reg[0][6]_rep_0 ,
    \wrQ_reg[0][6]_rep__0_0 ,
    \wrQ_reg[0][6]_rep__1_0 ,
    \wrQ_reg[0][8]_rep_0 ,
    \wrQ_reg[0][8]_rep__0_1 ,
    \wrQ_reg[0][8]_rep__1_1 ,
    \dReg_reg[9] ,
    \dReg_reg[11] ,
    \dReg_reg[10]_0 ,
    \dReg_reg[9]_0 ,
    \dReg_reg[11]_0 ,
    \dReg_reg[10]_1 ,
    \dReg_reg[9]_1 ,
    \dReg_reg[11]_1 ,
    \dReg_reg[10]_2 ,
    \dReg_reg[9]_2 ,
    \dReg_reg[11]_2 ,
    \dReg_reg[10]_3 ,
    \dReg_reg[9]_3 ,
    \dReg_reg[11]_3 ,
    \dReg_reg[10]_4 ,
    \dReg_reg[9]_4 ,
    \dReg_reg[11]_4 ,
    \dReg_reg[10]_5 ,
    \dReg_reg[9]_5 ,
    \dReg_reg[11]_5 ,
    \dReg_reg[10]_6 ,
    \dReg_reg[9]_6 ,
    \dReg_reg[11]_6 ,
    \dReg_reg[10]_7 ,
    \dReg_reg[9]_7 ,
    \dReg_reg[11]_7 ,
    \dReg_reg[10]_8 ,
    \dReg_reg[9]_8 ,
    \dReg_reg[11]_8 ,
    \dReg_reg[10]_9 ,
    \dReg_reg[9]_9 ,
    \dReg_reg[11]_9 ,
    \dReg_reg[10]_10 ,
    \dReg_reg[9]_10 ,
    \dReg_reg[11]_10 ,
    \dReg_reg[10]_11 ,
    \dReg_reg[9]_11 ,
    \dReg_reg[11]_11 ,
    \dReg_reg[10]_12 ,
    \dReg_reg[9]_12 ,
    \dReg_reg[11]_12 ,
    \dReg_reg[10]_13 ,
    \dReg_reg[9]_13 ,
    \dReg_reg[11]_13 ,
    \dReg_reg[10]_14 ,
    \dReg_reg[9]_14 ,
    \dReg_reg[11]_14 ,
    \dReg_reg[10]_15 ,
    \dReg_reg[9]_15 ,
    \dReg_reg[11]_15 ,
    \dReg_reg[10]_16 ,
    \dReg_reg[9]_16 ,
    \dReg_reg[11]_16 ,
    \dReg_reg[10]_17 ,
    \dReg_reg[9]_17 ,
    \dReg_reg[11]_17 ,
    \dReg_reg[10]_18 ,
    \dReg_reg[9]_18 ,
    \dReg_reg[11]_18 ,
    \dReg_reg[10]_19 ,
    \dReg_reg[9]_19 ,
    \dReg_reg[11]_19 ,
    \dReg_reg[10]_20 ,
    \dReg_reg[9]_20 ,
    \dReg_reg[11]_20 ,
    \dReg_reg[10]_21 ,
    \dReg_reg[9]_21 ,
    \dReg_reg[11]_21 ,
    \dReg_reg[10]_22 ,
    \dReg_reg[9]_22 ,
    \dReg_reg[11]_22 ,
    \dReg_reg[10]_23 ,
    \dReg_reg[9]_23 ,
    \dReg_reg[11]_23 ,
    \dReg_reg[10]_24 ,
    \dReg_reg[9]_24 ,
    \dReg_reg[11]_24 ,
    \dReg_reg[10]_25 ,
    \dReg_reg[9]_25 ,
    \dReg_reg[11]_25 ,
    \dReg_reg[10]_26 ,
    \dReg_reg[9]_26 ,
    \dReg_reg[11]_26 ,
    \dReg_reg[10]_27 ,
    \dReg_reg[9]_27 ,
    \dReg_reg[11]_27 ,
    \dReg_reg[10]_28 ,
    \dReg_reg[9]_28 ,
    \dReg_reg[11]_28 ,
    \dReg_reg[10]_29 ,
    \dReg_reg[9]_29 ,
    \dReg_reg[11]_29 ,
    \dReg_reg[10]_30 ,
    \dReg_reg[9]_30 ,
    \dReg_reg[11]_30 ,
    \dReg_reg[10]_31 ,
    \dReg_reg[9]_31 ,
    \dReg_reg[11]_31 ,
    \dReg_reg[10]_32 ,
    \dReg_reg[9]_32 ,
    \dReg_reg[11]_32 ,
    \dReg_reg[10]_33 ,
    \dReg_reg[9]_33 ,
    \dReg_reg[11]_33 ,
    \dReg_reg[10]_34 ,
    \dReg_reg[9]_34 ,
    \dReg_reg[11]_34 ,
    \dReg_reg[10]_35 ,
    \dReg_reg[9]_35 ,
    \dReg_reg[11]_35 ,
    \dReg_reg[10]_36 ,
    \dReg_reg[9]_36 ,
    \dReg_reg[11]_36 ,
    \dReg_reg[10]_37 ,
    \dReg_reg[9]_37 ,
    \dReg_reg[11]_37 ,
    \dReg_reg[10]_38 ,
    \dReg_reg[9]_38 ,
    \dReg_reg[11]_38 ,
    \dReg_reg[10]_39 ,
    \dReg_reg[9]_39 ,
    \dReg_reg[11]_39 ,
    \dReg_reg[10]_40 ,
    \dReg_reg[9]_40 ,
    \dReg_reg[11]_40 ,
    \dReg_reg[10]_41 ,
    \dReg_reg[9]_41 ,
    \dReg_reg[11]_41 ,
    \dReg_reg[10]_42 ,
    \dReg_reg[9]_42 ,
    \dReg_reg[11]_42 ,
    \dReg_reg[10]_43 ,
    \dReg_reg[9]_43 ,
    \dReg_reg[11]_43 ,
    \dReg_reg[10]_44 ,
    \dReg_reg[9]_44 ,
    \dReg_reg[11]_44 ,
    \dReg_reg[10]_45 ,
    \dReg_reg[9]_45 ,
    \dReg_reg[11]_45 ,
    \dReg_reg[10]_46 ,
    \dReg_reg[9]_46 ,
    \dReg_reg[11]_46 ,
    \dReg_reg[10]_47 ,
    \dReg_reg[9]_47 ,
    \dReg_reg[11]_47 ,
    \dReg_reg[10]_48 ,
    \dReg_reg[9]_48 ,
    \dReg_reg[11]_48 ,
    \dReg_reg[10]_49 ,
    \dReg_reg[9]_49 ,
    \dReg_reg[11]_49 ,
    \dReg_reg[10]_50 ,
    \dReg_reg[9]_50 ,
    \dReg_reg[11]_50 ,
    \dReg_reg[10]_51 ,
    \dReg_reg[9]_51 ,
    \dReg_reg[11]_51 ,
    \dReg_reg[10]_52 ,
    \dReg_reg[9]_52 ,
    \dReg_reg[11]_52 ,
    \dReg_reg[10]_53 ,
    \dReg_reg[9]_53 ,
    \dReg_reg[11]_53 ,
    \dReg_reg[10]_54 ,
    \dReg_reg[9]_54 ,
    \dReg_reg[11]_54 ,
    \dReg_reg[10]_55 ,
    \dReg_reg[9]_55 ,
    \dReg_reg[11]_55 ,
    \dReg_reg[10]_56 ,
    \dReg_reg[9]_56 ,
    \dReg_reg[11]_56 ,
    \dReg_reg[10]_57 ,
    \dReg_reg[9]_57 ,
    \dReg_reg[11]_57 ,
    \dReg_reg[10]_58 ,
    \dReg_reg[9]_58 ,
    \dReg_reg[11]_58 ,
    \dReg_reg[10]_59 ,
    \dReg_reg[9]_59 ,
    \dReg_reg[11]_59 ,
    \dReg_reg[10]_60 ,
    \dReg_reg[9]_60 ,
    \dReg_reg[11]_60 ,
    \dReg_reg[10]_61 ,
    \dReg_reg[9]_61 ,
    \dReg_reg[11]_61 ,
    \dReg_reg[10]_62 ,
    \dReg_reg[9]_62 ,
    \dReg_reg[11]_62 ,
    \dReg_reg[10]_63 ,
    \dReg_reg[9]_63 ,
    \dReg_reg[11]_63 ,
    \dReg_reg[10]_64 ,
    \dReg_reg[9]_64 ,
    \dReg_reg[11]_64 ,
    \dReg_reg[10]_65 ,
    \dReg_reg[9]_65 ,
    \dReg_reg[11]_65 ,
    \dReg_reg[10]_66 ,
    \dReg_reg[9]_66 ,
    \dReg_reg[11]_66 ,
    \dReg_reg[10]_67 ,
    \dReg_reg[9]_67 ,
    \dReg_reg[11]_67 ,
    \dReg_reg[10]_68 ,
    \dReg_reg[9]_68 ,
    \dReg_reg[11]_68 ,
    \dReg_reg[10]_69 ,
    \dReg_reg[9]_69 ,
    \dReg_reg[11]_69 ,
    \dReg_reg[10]_70 ,
    \dReg_reg[9]_70 ,
    \dReg_reg[11]_70 ,
    \dReg_reg[10]_71 );
  output wrDataVal_reg_0;
  output \wrQ_reg[0][0]_0 ;
  output \wosp_reg[1] ;
  output \wosp_reg[2] ;
  output \oe_0_mux_cal_reg[0]_0 ;
  output \wosp_reg[2]_rep ;
  output \wosp_reg[2]_rep__0 ;
  output \wosp_reg[2]_rep__1 ;
  output \wosp_reg[2]_rep__2 ;
  output \wosp_reg[2]_rep__3 ;
  output \wosp_reg[2]_rep__4 ;
  output \wosp_reg[2]_rep__5 ;
  output \wosp_reg[2]_rep__6 ;
  output \wosp_reg[2]_rep__7 ;
  output pointer_we;
  output [0:0]\wrQ_reg[0][0]_1 ;
  output [3:0]\wrQ_reg[1][8]_0 ;
  output [3:0]ADDRC;
  output \wrQ_reg[0][0]_rep_0 ;
  output [3:0]ADDRA;
  output [3:0]\wrQ_reg[0][8]_rep__0_0 ;
  output [3:0]\wrQ_reg[0][8]_rep__1_0 ;
  output [3:0]\oe_upp_reg[3]_0 ;
  output [3:0]\oe_low_reg[3]_0 ;
  output [511:0]ch0_mcal_DQOut;
  output [63:0]ch0_mcal_DMOut_n;
  input [0:0]cal_oe_dis_upp;
  input \dReg_reg[10] ;
  input [0:0]cal_oe_dis_low;
  input out;
  input \oe_0_mux_cal_reg[0]_1 ;
  input \oe_low_reg[5]_0 ;
  input [0:0]\rams[1].RAM32M0 ;
  input mcWrCAS;
  input mcCasSlot2;
  input \wrQ_reg[0][2]_0 ;
  input [511:0]DQOut;
  input [63:0]DMOut;
  input \dReg_reg[7] ;
  input \dReg_reg[6] ;
  input \dReg_reg[7]_0 ;
  input \dReg_reg[6]_0 ;
  input \dReg_reg[7]_1 ;
  input \dReg_reg[6]_1 ;
  input \dReg_reg[7]_2 ;
  input \dReg_reg[6]_2 ;
  input \dReg_reg[7]_3 ;
  input \dReg_reg[6]_3 ;
  input \dReg_reg[7]_4 ;
  input \dReg_reg[6]_4 ;
  input \dReg_reg[7]_5 ;
  input \dReg_reg[6]_5 ;
  input \dReg_reg[7]_6 ;
  input \dReg_reg[6]_6 ;
  input \dReg_reg[7]_7 ;
  input \dReg_reg[6]_7 ;
  input \dReg_reg[7]_8 ;
  input \dReg_reg[6]_8 ;
  input \dReg_reg[7]_9 ;
  input \dReg_reg[6]_9 ;
  input \dReg_reg[7]_10 ;
  input \dReg_reg[6]_10 ;
  input \dReg_reg[7]_11 ;
  input \dReg_reg[6]_11 ;
  input \dReg_reg[7]_12 ;
  input \dReg_reg[6]_12 ;
  input \dReg_reg[7]_13 ;
  input \dReg_reg[6]_13 ;
  input \dReg_reg[7]_14 ;
  input \dReg_reg[6]_14 ;
  input \dReg_reg[7]_15 ;
  input \dReg_reg[6]_15 ;
  input \dReg_reg[7]_16 ;
  input \dReg_reg[6]_16 ;
  input \dReg_reg[7]_17 ;
  input \dReg_reg[6]_17 ;
  input \dReg_reg[7]_18 ;
  input \dReg_reg[6]_18 ;
  input \dReg_reg[7]_19 ;
  input \dReg_reg[6]_19 ;
  input \dReg_reg[7]_20 ;
  input \dReg_reg[6]_20 ;
  input \dReg_reg[7]_21 ;
  input \dReg_reg[6]_21 ;
  input \dReg_reg[7]_22 ;
  input \dReg_reg[6]_22 ;
  input \dReg_reg[7]_23 ;
  input \dReg_reg[6]_23 ;
  input \dReg_reg[7]_24 ;
  input \dReg_reg[6]_24 ;
  input \dReg_reg[7]_25 ;
  input \dReg_reg[6]_25 ;
  input \dReg_reg[7]_26 ;
  input \dReg_reg[6]_26 ;
  input \dReg_reg[7]_27 ;
  input \dReg_reg[6]_27 ;
  input \dReg_reg[7]_28 ;
  input \dReg_reg[6]_28 ;
  input \dReg_reg[7]_29 ;
  input \dReg_reg[6]_29 ;
  input \dReg_reg[7]_30 ;
  input \dReg_reg[6]_30 ;
  input \dReg_reg[7]_31 ;
  input \dReg_reg[6]_31 ;
  input \dReg_reg[7]_32 ;
  input \dReg_reg[6]_32 ;
  input \dReg_reg[7]_33 ;
  input \dReg_reg[6]_33 ;
  input \dReg_reg[7]_34 ;
  input \dReg_reg[6]_34 ;
  input \dReg_reg[7]_35 ;
  input \dReg_reg[6]_35 ;
  input \dReg_reg[7]_36 ;
  input \dReg_reg[6]_36 ;
  input \dReg_reg[7]_37 ;
  input \dReg_reg[6]_37 ;
  input \dReg_reg[7]_38 ;
  input \dReg_reg[6]_38 ;
  input \dReg_reg[7]_39 ;
  input \dReg_reg[6]_39 ;
  input \dReg_reg[7]_40 ;
  input \dReg_reg[6]_40 ;
  input \dReg_reg[7]_41 ;
  input \dReg_reg[6]_41 ;
  input \dReg_reg[7]_42 ;
  input \dReg_reg[6]_42 ;
  input \dReg_reg[7]_43 ;
  input \dReg_reg[6]_43 ;
  input \dReg_reg[7]_44 ;
  input \dReg_reg[6]_44 ;
  input \dReg_reg[7]_45 ;
  input \dReg_reg[6]_45 ;
  input \dReg_reg[7]_46 ;
  input \dReg_reg[6]_46 ;
  input \dReg_reg[7]_47 ;
  input \dReg_reg[6]_47 ;
  input \dReg_reg[7]_48 ;
  input \dReg_reg[6]_48 ;
  input \dReg_reg[7]_49 ;
  input \dReg_reg[6]_49 ;
  input \dReg_reg[7]_50 ;
  input \dReg_reg[6]_50 ;
  input \dReg_reg[7]_51 ;
  input \dReg_reg[6]_51 ;
  input \dReg_reg[7]_52 ;
  input \dReg_reg[6]_52 ;
  input \dReg_reg[7]_53 ;
  input \dReg_reg[6]_53 ;
  input \dReg_reg[7]_54 ;
  input \dReg_reg[6]_54 ;
  input \dReg_reg[7]_55 ;
  input \dReg_reg[6]_55 ;
  input \dReg_reg[7]_56 ;
  input \dReg_reg[6]_56 ;
  input \dReg_reg[7]_57 ;
  input \dReg_reg[6]_57 ;
  input \dReg_reg[7]_58 ;
  input \dReg_reg[6]_58 ;
  input \dReg_reg[7]_59 ;
  input \dReg_reg[6]_59 ;
  input \dReg_reg[7]_60 ;
  input \dReg_reg[6]_60 ;
  input \dReg_reg[7]_61 ;
  input \dReg_reg[6]_61 ;
  input \dReg_reg[7]_62 ;
  input \dReg_reg[6]_62 ;
  input \dReg_reg[7]_63 ;
  input \dReg_reg[6]_63 ;
  input \dReg_reg[7]_64 ;
  input \dReg_reg[6]_64 ;
  input \dReg_reg[7]_65 ;
  input \dReg_reg[6]_65 ;
  input \dReg_reg[7]_66 ;
  input \dReg_reg[6]_66 ;
  input \dReg_reg[7]_67 ;
  input \dReg_reg[6]_67 ;
  input \dReg_reg[7]_68 ;
  input \dReg_reg[6]_68 ;
  input \dReg_reg[7]_69 ;
  input \dReg_reg[6]_69 ;
  input \dReg_reg[7]_70 ;
  input \dReg_reg[6]_70 ;
  input [4:0]\wrQ_reg[1][8]_1 ;
  input [0:0]\wrQ_nxt[1]_13 ;
  input [3:0]\wrQ_reg[0][8]_0 ;
  input \wrQ_reg[0][7]_rep_0 ;
  input \wrQ_reg[0][7]_rep__0_0 ;
  input \wrQ_reg[0][7]_rep__1_0 ;
  input \wrQ_reg[0][5]_rep_0 ;
  input \wrQ_reg[0][5]_rep__0_0 ;
  input \wrQ_reg[0][5]_rep__1_0 ;
  input \wrQ_reg[0][6]_rep_0 ;
  input \wrQ_reg[0][6]_rep__0_0 ;
  input \wrQ_reg[0][6]_rep__1_0 ;
  input \wrQ_reg[0][8]_rep_0 ;
  input \wrQ_reg[0][8]_rep__0_1 ;
  input \wrQ_reg[0][8]_rep__1_1 ;
  input [1:0]\dReg_reg[9] ;
  input \dReg_reg[11] ;
  input \dReg_reg[10]_0 ;
  input [1:0]\dReg_reg[9]_0 ;
  input \dReg_reg[11]_0 ;
  input \dReg_reg[10]_1 ;
  input [1:0]\dReg_reg[9]_1 ;
  input \dReg_reg[11]_1 ;
  input \dReg_reg[10]_2 ;
  input [1:0]\dReg_reg[9]_2 ;
  input \dReg_reg[11]_2 ;
  input \dReg_reg[10]_3 ;
  input [1:0]\dReg_reg[9]_3 ;
  input \dReg_reg[11]_3 ;
  input \dReg_reg[10]_4 ;
  input [1:0]\dReg_reg[9]_4 ;
  input \dReg_reg[11]_4 ;
  input \dReg_reg[10]_5 ;
  input [1:0]\dReg_reg[9]_5 ;
  input \dReg_reg[11]_5 ;
  input \dReg_reg[10]_6 ;
  input [1:0]\dReg_reg[9]_6 ;
  input \dReg_reg[11]_6 ;
  input \dReg_reg[10]_7 ;
  input [1:0]\dReg_reg[9]_7 ;
  input \dReg_reg[11]_7 ;
  input \dReg_reg[10]_8 ;
  input [1:0]\dReg_reg[9]_8 ;
  input \dReg_reg[11]_8 ;
  input \dReg_reg[10]_9 ;
  input [1:0]\dReg_reg[9]_9 ;
  input \dReg_reg[11]_9 ;
  input \dReg_reg[10]_10 ;
  input [1:0]\dReg_reg[9]_10 ;
  input \dReg_reg[11]_10 ;
  input \dReg_reg[10]_11 ;
  input [1:0]\dReg_reg[9]_11 ;
  input \dReg_reg[11]_11 ;
  input \dReg_reg[10]_12 ;
  input [1:0]\dReg_reg[9]_12 ;
  input \dReg_reg[11]_12 ;
  input \dReg_reg[10]_13 ;
  input [1:0]\dReg_reg[9]_13 ;
  input \dReg_reg[11]_13 ;
  input \dReg_reg[10]_14 ;
  input [1:0]\dReg_reg[9]_14 ;
  input \dReg_reg[11]_14 ;
  input \dReg_reg[10]_15 ;
  input [1:0]\dReg_reg[9]_15 ;
  input \dReg_reg[11]_15 ;
  input \dReg_reg[10]_16 ;
  input [1:0]\dReg_reg[9]_16 ;
  input \dReg_reg[11]_16 ;
  input \dReg_reg[10]_17 ;
  input [1:0]\dReg_reg[9]_17 ;
  input \dReg_reg[11]_17 ;
  input \dReg_reg[10]_18 ;
  input [1:0]\dReg_reg[9]_18 ;
  input \dReg_reg[11]_18 ;
  input \dReg_reg[10]_19 ;
  input [1:0]\dReg_reg[9]_19 ;
  input \dReg_reg[11]_19 ;
  input \dReg_reg[10]_20 ;
  input [1:0]\dReg_reg[9]_20 ;
  input \dReg_reg[11]_20 ;
  input \dReg_reg[10]_21 ;
  input [1:0]\dReg_reg[9]_21 ;
  input \dReg_reg[11]_21 ;
  input \dReg_reg[10]_22 ;
  input [1:0]\dReg_reg[9]_22 ;
  input \dReg_reg[11]_22 ;
  input \dReg_reg[10]_23 ;
  input [1:0]\dReg_reg[9]_23 ;
  input \dReg_reg[11]_23 ;
  input \dReg_reg[10]_24 ;
  input [1:0]\dReg_reg[9]_24 ;
  input \dReg_reg[11]_24 ;
  input \dReg_reg[10]_25 ;
  input [1:0]\dReg_reg[9]_25 ;
  input \dReg_reg[11]_25 ;
  input \dReg_reg[10]_26 ;
  input [1:0]\dReg_reg[9]_26 ;
  input \dReg_reg[11]_26 ;
  input \dReg_reg[10]_27 ;
  input [1:0]\dReg_reg[9]_27 ;
  input \dReg_reg[11]_27 ;
  input \dReg_reg[10]_28 ;
  input [1:0]\dReg_reg[9]_28 ;
  input \dReg_reg[11]_28 ;
  input \dReg_reg[10]_29 ;
  input [1:0]\dReg_reg[9]_29 ;
  input \dReg_reg[11]_29 ;
  input \dReg_reg[10]_30 ;
  input [1:0]\dReg_reg[9]_30 ;
  input \dReg_reg[11]_30 ;
  input \dReg_reg[10]_31 ;
  input [1:0]\dReg_reg[9]_31 ;
  input \dReg_reg[11]_31 ;
  input \dReg_reg[10]_32 ;
  input [1:0]\dReg_reg[9]_32 ;
  input \dReg_reg[11]_32 ;
  input \dReg_reg[10]_33 ;
  input [1:0]\dReg_reg[9]_33 ;
  input \dReg_reg[11]_33 ;
  input \dReg_reg[10]_34 ;
  input [1:0]\dReg_reg[9]_34 ;
  input \dReg_reg[11]_34 ;
  input \dReg_reg[10]_35 ;
  input [1:0]\dReg_reg[9]_35 ;
  input \dReg_reg[11]_35 ;
  input \dReg_reg[10]_36 ;
  input [1:0]\dReg_reg[9]_36 ;
  input \dReg_reg[11]_36 ;
  input \dReg_reg[10]_37 ;
  input [1:0]\dReg_reg[9]_37 ;
  input \dReg_reg[11]_37 ;
  input \dReg_reg[10]_38 ;
  input [1:0]\dReg_reg[9]_38 ;
  input \dReg_reg[11]_38 ;
  input \dReg_reg[10]_39 ;
  input [1:0]\dReg_reg[9]_39 ;
  input \dReg_reg[11]_39 ;
  input \dReg_reg[10]_40 ;
  input [1:0]\dReg_reg[9]_40 ;
  input \dReg_reg[11]_40 ;
  input \dReg_reg[10]_41 ;
  input [1:0]\dReg_reg[9]_41 ;
  input \dReg_reg[11]_41 ;
  input \dReg_reg[10]_42 ;
  input [1:0]\dReg_reg[9]_42 ;
  input \dReg_reg[11]_42 ;
  input \dReg_reg[10]_43 ;
  input [1:0]\dReg_reg[9]_43 ;
  input \dReg_reg[11]_43 ;
  input \dReg_reg[10]_44 ;
  input [1:0]\dReg_reg[9]_44 ;
  input \dReg_reg[11]_44 ;
  input \dReg_reg[10]_45 ;
  input [1:0]\dReg_reg[9]_45 ;
  input \dReg_reg[11]_45 ;
  input \dReg_reg[10]_46 ;
  input [1:0]\dReg_reg[9]_46 ;
  input \dReg_reg[11]_46 ;
  input \dReg_reg[10]_47 ;
  input [1:0]\dReg_reg[9]_47 ;
  input \dReg_reg[11]_47 ;
  input \dReg_reg[10]_48 ;
  input [1:0]\dReg_reg[9]_48 ;
  input \dReg_reg[11]_48 ;
  input \dReg_reg[10]_49 ;
  input [1:0]\dReg_reg[9]_49 ;
  input \dReg_reg[11]_49 ;
  input \dReg_reg[10]_50 ;
  input [1:0]\dReg_reg[9]_50 ;
  input \dReg_reg[11]_50 ;
  input \dReg_reg[10]_51 ;
  input [1:0]\dReg_reg[9]_51 ;
  input \dReg_reg[11]_51 ;
  input \dReg_reg[10]_52 ;
  input [1:0]\dReg_reg[9]_52 ;
  input \dReg_reg[11]_52 ;
  input \dReg_reg[10]_53 ;
  input [1:0]\dReg_reg[9]_53 ;
  input \dReg_reg[11]_53 ;
  input \dReg_reg[10]_54 ;
  input [1:0]\dReg_reg[9]_54 ;
  input \dReg_reg[11]_54 ;
  input \dReg_reg[10]_55 ;
  input [1:0]\dReg_reg[9]_55 ;
  input \dReg_reg[11]_55 ;
  input \dReg_reg[10]_56 ;
  input [1:0]\dReg_reg[9]_56 ;
  input \dReg_reg[11]_56 ;
  input \dReg_reg[10]_57 ;
  input [1:0]\dReg_reg[9]_57 ;
  input \dReg_reg[11]_57 ;
  input \dReg_reg[10]_58 ;
  input [1:0]\dReg_reg[9]_58 ;
  input \dReg_reg[11]_58 ;
  input \dReg_reg[10]_59 ;
  input [1:0]\dReg_reg[9]_59 ;
  input \dReg_reg[11]_59 ;
  input \dReg_reg[10]_60 ;
  input [1:0]\dReg_reg[9]_60 ;
  input \dReg_reg[11]_60 ;
  input \dReg_reg[10]_61 ;
  input [1:0]\dReg_reg[9]_61 ;
  input \dReg_reg[11]_61 ;
  input \dReg_reg[10]_62 ;
  input [1:0]\dReg_reg[9]_62 ;
  input \dReg_reg[11]_62 ;
  input \dReg_reg[10]_63 ;
  input [1:0]\dReg_reg[9]_63 ;
  input \dReg_reg[11]_63 ;
  input \dReg_reg[10]_64 ;
  input [1:0]\dReg_reg[9]_64 ;
  input \dReg_reg[11]_64 ;
  input \dReg_reg[10]_65 ;
  input [1:0]\dReg_reg[9]_65 ;
  input \dReg_reg[11]_65 ;
  input \dReg_reg[10]_66 ;
  input [1:0]\dReg_reg[9]_66 ;
  input \dReg_reg[11]_66 ;
  input \dReg_reg[10]_67 ;
  input [1:0]\dReg_reg[9]_67 ;
  input \dReg_reg[11]_67 ;
  input \dReg_reg[10]_68 ;
  input [1:0]\dReg_reg[9]_68 ;
  input \dReg_reg[11]_68 ;
  input \dReg_reg[10]_69 ;
  input [1:0]\dReg_reg[9]_69 ;
  input \dReg_reg[11]_69 ;
  input \dReg_reg[10]_70 ;
  input [1:0]\dReg_reg[9]_70 ;
  input \dReg_reg[11]_70 ;
  input \dReg_reg[10]_71 ;

  wire [3:0]ADDRA;
  wire [3:0]ADDRC;
  wire [63:0]DMOut;
  wire [511:0]DQOut;
  wire [0:0]cal_oe_dis_low;
  wire cal_oe_dis_low_dly;
  wire [0:0]cal_oe_dis_upp;
  wire cal_oe_dis_upp_dly;
  wire [63:0]ch0_mcal_DMOut_n;
  wire [511:0]ch0_mcal_DQOut;
  wire [15:10]dReg;
  wire [15:2]dReg0_out;
  wire [15:2]dReg0_out_54;
  wire [15:2]dReg0_out_55;
  wire [15:2]dReg0_out_56;
  wire [15:2]dReg0_out_57;
  wire [15:2]dReg0_out_58;
  wire [15:2]dReg0_out_59;
  wire [15:10]dReg_17;
  wire [15:10]dReg_26;
  wire [15:10]dReg_35;
  wire [15:10]dReg_44;
  wire [15:10]dReg_53;
  wire [15:10]dReg_8;
  wire [15:10]dReg__0;
  wire [15:10]dReg__0_16;
  wire [15:10]dReg__0_25;
  wire [15:10]dReg__0_34;
  wire [15:10]dReg__0_43;
  wire [15:10]dReg__0_52;
  wire [15:10]dReg__0_7;
  wire [15:10]dReg__1;
  wire [15:10]dReg__1_15;
  wire [15:10]dReg__1_24;
  wire [15:10]dReg__1_33;
  wire [15:10]dReg__1_42;
  wire [15:10]dReg__1_51;
  wire [15:10]dReg__1_6;
  wire [15:10]dReg__2;
  wire [15:10]dReg__2_14;
  wire [15:10]dReg__2_23;
  wire [15:10]dReg__2_32;
  wire [15:10]dReg__2_41;
  wire [15:10]dReg__2_5;
  wire [15:10]dReg__2_50;
  wire [15:10]dReg__3;
  wire [15:10]dReg__3_13;
  wire [15:10]dReg__3_22;
  wire [15:10]dReg__3_31;
  wire [15:10]dReg__3_4;
  wire [15:10]dReg__3_40;
  wire [15:10]dReg__3_49;
  wire [15:10]dReg__4;
  wire [15:10]dReg__4_12;
  wire [15:10]dReg__4_21;
  wire [15:10]dReg__4_3;
  wire [15:10]dReg__4_30;
  wire [15:10]dReg__4_39;
  wire [15:10]dReg__4_48;
  wire [15:10]dReg__5;
  wire [15:10]dReg__5_11;
  wire [15:10]dReg__5_2;
  wire [15:10]dReg__5_20;
  wire [15:10]dReg__5_29;
  wire [15:10]dReg__5_38;
  wire [15:10]dReg__5_47;
  wire [15:10]dReg__6;
  wire [15:10]dReg__6_1;
  wire [15:10]dReg__6_10;
  wire [15:10]dReg__6_19;
  wire [15:10]dReg__6_28;
  wire [15:10]dReg__6_37;
  wire [15:10]dReg__6_46;
  wire [15:10]dReg__7;
  wire [15:10]dReg__7_0;
  wire [15:10]dReg__7_18;
  wire [15:10]dReg__7_27;
  wire [15:10]dReg__7_36;
  wire [15:10]dReg__7_45;
  wire [15:10]dReg__7_9;
  wire \dReg_reg[10] ;
  wire \dReg_reg[10]_0 ;
  wire \dReg_reg[10]_1 ;
  wire \dReg_reg[10]_10 ;
  wire \dReg_reg[10]_11 ;
  wire \dReg_reg[10]_12 ;
  wire \dReg_reg[10]_13 ;
  wire \dReg_reg[10]_14 ;
  wire \dReg_reg[10]_15 ;
  wire \dReg_reg[10]_16 ;
  wire \dReg_reg[10]_17 ;
  wire \dReg_reg[10]_18 ;
  wire \dReg_reg[10]_19 ;
  wire \dReg_reg[10]_2 ;
  wire \dReg_reg[10]_20 ;
  wire \dReg_reg[10]_21 ;
  wire \dReg_reg[10]_22 ;
  wire \dReg_reg[10]_23 ;
  wire \dReg_reg[10]_24 ;
  wire \dReg_reg[10]_25 ;
  wire \dReg_reg[10]_26 ;
  wire \dReg_reg[10]_27 ;
  wire \dReg_reg[10]_28 ;
  wire \dReg_reg[10]_29 ;
  wire \dReg_reg[10]_3 ;
  wire \dReg_reg[10]_30 ;
  wire \dReg_reg[10]_31 ;
  wire \dReg_reg[10]_32 ;
  wire \dReg_reg[10]_33 ;
  wire \dReg_reg[10]_34 ;
  wire \dReg_reg[10]_35 ;
  wire \dReg_reg[10]_36 ;
  wire \dReg_reg[10]_37 ;
  wire \dReg_reg[10]_38 ;
  wire \dReg_reg[10]_39 ;
  wire \dReg_reg[10]_4 ;
  wire \dReg_reg[10]_40 ;
  wire \dReg_reg[10]_41 ;
  wire \dReg_reg[10]_42 ;
  wire \dReg_reg[10]_43 ;
  wire \dReg_reg[10]_44 ;
  wire \dReg_reg[10]_45 ;
  wire \dReg_reg[10]_46 ;
  wire \dReg_reg[10]_47 ;
  wire \dReg_reg[10]_48 ;
  wire \dReg_reg[10]_49 ;
  wire \dReg_reg[10]_5 ;
  wire \dReg_reg[10]_50 ;
  wire \dReg_reg[10]_51 ;
  wire \dReg_reg[10]_52 ;
  wire \dReg_reg[10]_53 ;
  wire \dReg_reg[10]_54 ;
  wire \dReg_reg[10]_55 ;
  wire \dReg_reg[10]_56 ;
  wire \dReg_reg[10]_57 ;
  wire \dReg_reg[10]_58 ;
  wire \dReg_reg[10]_59 ;
  wire \dReg_reg[10]_6 ;
  wire \dReg_reg[10]_60 ;
  wire \dReg_reg[10]_61 ;
  wire \dReg_reg[10]_62 ;
  wire \dReg_reg[10]_63 ;
  wire \dReg_reg[10]_64 ;
  wire \dReg_reg[10]_65 ;
  wire \dReg_reg[10]_66 ;
  wire \dReg_reg[10]_67 ;
  wire \dReg_reg[10]_68 ;
  wire \dReg_reg[10]_69 ;
  wire \dReg_reg[10]_7 ;
  wire \dReg_reg[10]_70 ;
  wire \dReg_reg[10]_71 ;
  wire \dReg_reg[10]_8 ;
  wire \dReg_reg[10]_9 ;
  wire \dReg_reg[11] ;
  wire \dReg_reg[11]_0 ;
  wire \dReg_reg[11]_1 ;
  wire \dReg_reg[11]_10 ;
  wire \dReg_reg[11]_11 ;
  wire \dReg_reg[11]_12 ;
  wire \dReg_reg[11]_13 ;
  wire \dReg_reg[11]_14 ;
  wire \dReg_reg[11]_15 ;
  wire \dReg_reg[11]_16 ;
  wire \dReg_reg[11]_17 ;
  wire \dReg_reg[11]_18 ;
  wire \dReg_reg[11]_19 ;
  wire \dReg_reg[11]_2 ;
  wire \dReg_reg[11]_20 ;
  wire \dReg_reg[11]_21 ;
  wire \dReg_reg[11]_22 ;
  wire \dReg_reg[11]_23 ;
  wire \dReg_reg[11]_24 ;
  wire \dReg_reg[11]_25 ;
  wire \dReg_reg[11]_26 ;
  wire \dReg_reg[11]_27 ;
  wire \dReg_reg[11]_28 ;
  wire \dReg_reg[11]_29 ;
  wire \dReg_reg[11]_3 ;
  wire \dReg_reg[11]_30 ;
  wire \dReg_reg[11]_31 ;
  wire \dReg_reg[11]_32 ;
  wire \dReg_reg[11]_33 ;
  wire \dReg_reg[11]_34 ;
  wire \dReg_reg[11]_35 ;
  wire \dReg_reg[11]_36 ;
  wire \dReg_reg[11]_37 ;
  wire \dReg_reg[11]_38 ;
  wire \dReg_reg[11]_39 ;
  wire \dReg_reg[11]_4 ;
  wire \dReg_reg[11]_40 ;
  wire \dReg_reg[11]_41 ;
  wire \dReg_reg[11]_42 ;
  wire \dReg_reg[11]_43 ;
  wire \dReg_reg[11]_44 ;
  wire \dReg_reg[11]_45 ;
  wire \dReg_reg[11]_46 ;
  wire \dReg_reg[11]_47 ;
  wire \dReg_reg[11]_48 ;
  wire \dReg_reg[11]_49 ;
  wire \dReg_reg[11]_5 ;
  wire \dReg_reg[11]_50 ;
  wire \dReg_reg[11]_51 ;
  wire \dReg_reg[11]_52 ;
  wire \dReg_reg[11]_53 ;
  wire \dReg_reg[11]_54 ;
  wire \dReg_reg[11]_55 ;
  wire \dReg_reg[11]_56 ;
  wire \dReg_reg[11]_57 ;
  wire \dReg_reg[11]_58 ;
  wire \dReg_reg[11]_59 ;
  wire \dReg_reg[11]_6 ;
  wire \dReg_reg[11]_60 ;
  wire \dReg_reg[11]_61 ;
  wire \dReg_reg[11]_62 ;
  wire \dReg_reg[11]_63 ;
  wire \dReg_reg[11]_64 ;
  wire \dReg_reg[11]_65 ;
  wire \dReg_reg[11]_66 ;
  wire \dReg_reg[11]_67 ;
  wire \dReg_reg[11]_68 ;
  wire \dReg_reg[11]_69 ;
  wire \dReg_reg[11]_7 ;
  wire \dReg_reg[11]_70 ;
  wire \dReg_reg[11]_8 ;
  wire \dReg_reg[11]_9 ;
  wire \dReg_reg[6] ;
  wire \dReg_reg[6]_0 ;
  wire \dReg_reg[6]_1 ;
  wire \dReg_reg[6]_10 ;
  wire \dReg_reg[6]_11 ;
  wire \dReg_reg[6]_12 ;
  wire \dReg_reg[6]_13 ;
  wire \dReg_reg[6]_14 ;
  wire \dReg_reg[6]_15 ;
  wire \dReg_reg[6]_16 ;
  wire \dReg_reg[6]_17 ;
  wire \dReg_reg[6]_18 ;
  wire \dReg_reg[6]_19 ;
  wire \dReg_reg[6]_2 ;
  wire \dReg_reg[6]_20 ;
  wire \dReg_reg[6]_21 ;
  wire \dReg_reg[6]_22 ;
  wire \dReg_reg[6]_23 ;
  wire \dReg_reg[6]_24 ;
  wire \dReg_reg[6]_25 ;
  wire \dReg_reg[6]_26 ;
  wire \dReg_reg[6]_27 ;
  wire \dReg_reg[6]_28 ;
  wire \dReg_reg[6]_29 ;
  wire \dReg_reg[6]_3 ;
  wire \dReg_reg[6]_30 ;
  wire \dReg_reg[6]_31 ;
  wire \dReg_reg[6]_32 ;
  wire \dReg_reg[6]_33 ;
  wire \dReg_reg[6]_34 ;
  wire \dReg_reg[6]_35 ;
  wire \dReg_reg[6]_36 ;
  wire \dReg_reg[6]_37 ;
  wire \dReg_reg[6]_38 ;
  wire \dReg_reg[6]_39 ;
  wire \dReg_reg[6]_4 ;
  wire \dReg_reg[6]_40 ;
  wire \dReg_reg[6]_41 ;
  wire \dReg_reg[6]_42 ;
  wire \dReg_reg[6]_43 ;
  wire \dReg_reg[6]_44 ;
  wire \dReg_reg[6]_45 ;
  wire \dReg_reg[6]_46 ;
  wire \dReg_reg[6]_47 ;
  wire \dReg_reg[6]_48 ;
  wire \dReg_reg[6]_49 ;
  wire \dReg_reg[6]_5 ;
  wire \dReg_reg[6]_50 ;
  wire \dReg_reg[6]_51 ;
  wire \dReg_reg[6]_52 ;
  wire \dReg_reg[6]_53 ;
  wire \dReg_reg[6]_54 ;
  wire \dReg_reg[6]_55 ;
  wire \dReg_reg[6]_56 ;
  wire \dReg_reg[6]_57 ;
  wire \dReg_reg[6]_58 ;
  wire \dReg_reg[6]_59 ;
  wire \dReg_reg[6]_6 ;
  wire \dReg_reg[6]_60 ;
  wire \dReg_reg[6]_61 ;
  wire \dReg_reg[6]_62 ;
  wire \dReg_reg[6]_63 ;
  wire \dReg_reg[6]_64 ;
  wire \dReg_reg[6]_65 ;
  wire \dReg_reg[6]_66 ;
  wire \dReg_reg[6]_67 ;
  wire \dReg_reg[6]_68 ;
  wire \dReg_reg[6]_69 ;
  wire \dReg_reg[6]_7 ;
  wire \dReg_reg[6]_70 ;
  wire \dReg_reg[6]_8 ;
  wire \dReg_reg[6]_9 ;
  wire \dReg_reg[7] ;
  wire \dReg_reg[7]_0 ;
  wire \dReg_reg[7]_1 ;
  wire \dReg_reg[7]_10 ;
  wire \dReg_reg[7]_11 ;
  wire \dReg_reg[7]_12 ;
  wire \dReg_reg[7]_13 ;
  wire \dReg_reg[7]_14 ;
  wire \dReg_reg[7]_15 ;
  wire \dReg_reg[7]_16 ;
  wire \dReg_reg[7]_17 ;
  wire \dReg_reg[7]_18 ;
  wire \dReg_reg[7]_19 ;
  wire \dReg_reg[7]_2 ;
  wire \dReg_reg[7]_20 ;
  wire \dReg_reg[7]_21 ;
  wire \dReg_reg[7]_22 ;
  wire \dReg_reg[7]_23 ;
  wire \dReg_reg[7]_24 ;
  wire \dReg_reg[7]_25 ;
  wire \dReg_reg[7]_26 ;
  wire \dReg_reg[7]_27 ;
  wire \dReg_reg[7]_28 ;
  wire \dReg_reg[7]_29 ;
  wire \dReg_reg[7]_3 ;
  wire \dReg_reg[7]_30 ;
  wire \dReg_reg[7]_31 ;
  wire \dReg_reg[7]_32 ;
  wire \dReg_reg[7]_33 ;
  wire \dReg_reg[7]_34 ;
  wire \dReg_reg[7]_35 ;
  wire \dReg_reg[7]_36 ;
  wire \dReg_reg[7]_37 ;
  wire \dReg_reg[7]_38 ;
  wire \dReg_reg[7]_39 ;
  wire \dReg_reg[7]_4 ;
  wire \dReg_reg[7]_40 ;
  wire \dReg_reg[7]_41 ;
  wire \dReg_reg[7]_42 ;
  wire \dReg_reg[7]_43 ;
  wire \dReg_reg[7]_44 ;
  wire \dReg_reg[7]_45 ;
  wire \dReg_reg[7]_46 ;
  wire \dReg_reg[7]_47 ;
  wire \dReg_reg[7]_48 ;
  wire \dReg_reg[7]_49 ;
  wire \dReg_reg[7]_5 ;
  wire \dReg_reg[7]_50 ;
  wire \dReg_reg[7]_51 ;
  wire \dReg_reg[7]_52 ;
  wire \dReg_reg[7]_53 ;
  wire \dReg_reg[7]_54 ;
  wire \dReg_reg[7]_55 ;
  wire \dReg_reg[7]_56 ;
  wire \dReg_reg[7]_57 ;
  wire \dReg_reg[7]_58 ;
  wire \dReg_reg[7]_59 ;
  wire \dReg_reg[7]_6 ;
  wire \dReg_reg[7]_60 ;
  wire \dReg_reg[7]_61 ;
  wire \dReg_reg[7]_62 ;
  wire \dReg_reg[7]_63 ;
  wire \dReg_reg[7]_64 ;
  wire \dReg_reg[7]_65 ;
  wire \dReg_reg[7]_66 ;
  wire \dReg_reg[7]_67 ;
  wire \dReg_reg[7]_68 ;
  wire \dReg_reg[7]_69 ;
  wire \dReg_reg[7]_7 ;
  wire \dReg_reg[7]_70 ;
  wire \dReg_reg[7]_8 ;
  wire \dReg_reg[7]_9 ;
  wire [1:0]\dReg_reg[9] ;
  wire [1:0]\dReg_reg[9]_0 ;
  wire [1:0]\dReg_reg[9]_1 ;
  wire [1:0]\dReg_reg[9]_10 ;
  wire [1:0]\dReg_reg[9]_11 ;
  wire [1:0]\dReg_reg[9]_12 ;
  wire [1:0]\dReg_reg[9]_13 ;
  wire [1:0]\dReg_reg[9]_14 ;
  wire [1:0]\dReg_reg[9]_15 ;
  wire [1:0]\dReg_reg[9]_16 ;
  wire [1:0]\dReg_reg[9]_17 ;
  wire [1:0]\dReg_reg[9]_18 ;
  wire [1:0]\dReg_reg[9]_19 ;
  wire [1:0]\dReg_reg[9]_2 ;
  wire [1:0]\dReg_reg[9]_20 ;
  wire [1:0]\dReg_reg[9]_21 ;
  wire [1:0]\dReg_reg[9]_22 ;
  wire [1:0]\dReg_reg[9]_23 ;
  wire [1:0]\dReg_reg[9]_24 ;
  wire [1:0]\dReg_reg[9]_25 ;
  wire [1:0]\dReg_reg[9]_26 ;
  wire [1:0]\dReg_reg[9]_27 ;
  wire [1:0]\dReg_reg[9]_28 ;
  wire [1:0]\dReg_reg[9]_29 ;
  wire [1:0]\dReg_reg[9]_3 ;
  wire [1:0]\dReg_reg[9]_30 ;
  wire [1:0]\dReg_reg[9]_31 ;
  wire [1:0]\dReg_reg[9]_32 ;
  wire [1:0]\dReg_reg[9]_33 ;
  wire [1:0]\dReg_reg[9]_34 ;
  wire [1:0]\dReg_reg[9]_35 ;
  wire [1:0]\dReg_reg[9]_36 ;
  wire [1:0]\dReg_reg[9]_37 ;
  wire [1:0]\dReg_reg[9]_38 ;
  wire [1:0]\dReg_reg[9]_39 ;
  wire [1:0]\dReg_reg[9]_4 ;
  wire [1:0]\dReg_reg[9]_40 ;
  wire [1:0]\dReg_reg[9]_41 ;
  wire [1:0]\dReg_reg[9]_42 ;
  wire [1:0]\dReg_reg[9]_43 ;
  wire [1:0]\dReg_reg[9]_44 ;
  wire [1:0]\dReg_reg[9]_45 ;
  wire [1:0]\dReg_reg[9]_46 ;
  wire [1:0]\dReg_reg[9]_47 ;
  wire [1:0]\dReg_reg[9]_48 ;
  wire [1:0]\dReg_reg[9]_49 ;
  wire [1:0]\dReg_reg[9]_5 ;
  wire [1:0]\dReg_reg[9]_50 ;
  wire [1:0]\dReg_reg[9]_51 ;
  wire [1:0]\dReg_reg[9]_52 ;
  wire [1:0]\dReg_reg[9]_53 ;
  wire [1:0]\dReg_reg[9]_54 ;
  wire [1:0]\dReg_reg[9]_55 ;
  wire [1:0]\dReg_reg[9]_56 ;
  wire [1:0]\dReg_reg[9]_57 ;
  wire [1:0]\dReg_reg[9]_58 ;
  wire [1:0]\dReg_reg[9]_59 ;
  wire [1:0]\dReg_reg[9]_6 ;
  wire [1:0]\dReg_reg[9]_60 ;
  wire [1:0]\dReg_reg[9]_61 ;
  wire [1:0]\dReg_reg[9]_62 ;
  wire [1:0]\dReg_reg[9]_63 ;
  wire [1:0]\dReg_reg[9]_64 ;
  wire [1:0]\dReg_reg[9]_65 ;
  wire [1:0]\dReg_reg[9]_66 ;
  wire [1:0]\dReg_reg[9]_67 ;
  wire [1:0]\dReg_reg[9]_68 ;
  wire [1:0]\dReg_reg[9]_69 ;
  wire [1:0]\dReg_reg[9]_7 ;
  wire [1:0]\dReg_reg[9]_70 ;
  wire [1:0]\dReg_reg[9]_8 ;
  wire [1:0]\dReg_reg[9]_9 ;
  wire \genByte[1].u_ddr_mc_wr_byte_n_0 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_100 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_101 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_102 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_103 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_104 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_105 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_106 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_107 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_108 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_109 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_11 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_110 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_111 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_112 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_113 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_114 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_115 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_116 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_117 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_118 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_119 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_120 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_121 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_122 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_123 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_124 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_125 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_126 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_127 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_128 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_129 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_130 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_131 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_132 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_133 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_134 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_135 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_136 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_137 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_138 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_139 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_140 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_141 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_142 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_143 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_144 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_145 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_146 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_147 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_148 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_149 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_150 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_151 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_152 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_153 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_154 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_155 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_156 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_157 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_167 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_168 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_169 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_170 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_171 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_172 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_173 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_174 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_175 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_176 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_177 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_178 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_179 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_180 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_181 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_182 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_183 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_184 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_185 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_186 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_187 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_188 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_189 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_190 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_191 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_192 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_193 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_194 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_195 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_196 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_197 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_198 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_199 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_200 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_201 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_202 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_203 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_204 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_205 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_206 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_207 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_208 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_209 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_21 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_210 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_211 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_212 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_213 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_214 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_215 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_216 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_217 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_218 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_219 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_22 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_220 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_221 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_222 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_223 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_224 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_225 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_226 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_227 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_228 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_229 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_23 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_230 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_24 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_240 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_241 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_242 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_243 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_244 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_245 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_246 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_247 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_248 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_249 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_25 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_250 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_251 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_252 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_253 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_254 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_255 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_256 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_257 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_258 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_259 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_26 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_260 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_261 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_262 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_263 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_264 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_265 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_266 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_267 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_268 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_269 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_27 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_270 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_271 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_272 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_273 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_274 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_275 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_276 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_277 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_278 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_279 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_28 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_280 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_281 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_282 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_283 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_284 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_285 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_286 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_287 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_288 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_289 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_29 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_290 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_291 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_292 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_293 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_294 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_295 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_296 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_297 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_298 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_299 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_30 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_300 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_301 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_302 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_303 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_31 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_313 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_314 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_315 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_316 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_317 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_318 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_319 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_32 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_320 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_321 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_322 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_323 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_324 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_325 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_326 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_327 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_328 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_329 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_33 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_330 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_331 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_332 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_333 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_334 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_335 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_336 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_337 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_338 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_339 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_34 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_340 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_341 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_342 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_343 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_344 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_345 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_346 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_347 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_348 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_349 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_35 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_350 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_351 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_352 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_353 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_354 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_355 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_356 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_357 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_358 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_359 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_36 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_360 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_361 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_362 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_363 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_364 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_365 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_366 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_367 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_368 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_369 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_37 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_370 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_371 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_372 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_373 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_374 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_375 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_376 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_38 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_386 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_387 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_388 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_389 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_39 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_390 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_391 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_392 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_393 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_394 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_395 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_396 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_397 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_398 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_399 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_40 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_400 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_401 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_402 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_403 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_404 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_405 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_406 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_407 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_408 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_409 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_41 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_410 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_411 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_412 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_413 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_414 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_415 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_416 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_417 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_418 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_419 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_42 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_420 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_421 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_422 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_423 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_424 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_425 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_426 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_427 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_428 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_429 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_43 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_430 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_431 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_432 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_433 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_434 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_435 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_436 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_437 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_438 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_439 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_44 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_440 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_441 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_442 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_443 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_444 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_445 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_446 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_447 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_448 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_449 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_45 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_459 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_46 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_460 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_461 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_462 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_463 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_464 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_465 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_466 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_467 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_468 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_469 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_47 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_470 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_471 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_472 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_473 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_474 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_475 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_476 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_477 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_478 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_479 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_48 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_480 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_481 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_482 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_483 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_484 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_485 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_486 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_487 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_488 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_489 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_49 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_490 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_491 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_492 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_493 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_494 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_495 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_496 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_497 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_498 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_499 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_50 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_500 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_501 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_502 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_503 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_504 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_505 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_506 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_507 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_508 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_509 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_51 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_510 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_511 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_512 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_513 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_514 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_515 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_516 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_517 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_518 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_519 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_52 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_520 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_521 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_522 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_53 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_54 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_55 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_56 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_57 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_58 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_59 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_60 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_61 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_62 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_63 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_64 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_65 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_66 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_67 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_68 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_69 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_70 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_71 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_72 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_73 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_74 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_75 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_76 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_77 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_78 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_79 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_80 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_81 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_82 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_83 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_84 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_94 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_95 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_96 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_97 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_98 ;
  wire \genByte[7].u_ddr_mc_wr_byte_n_99 ;
  wire mcCasSlot2;
  wire mcWrCAS;
  wire \oe_0_mux_cal_reg[0]_0 ;
  wire \oe_0_mux_cal_reg[0]_1 ;
  wire [7:4]oe_low;
  wire \oe_low[0]_i_1_n_0 ;
  wire \oe_low[1]_i_1_n_0 ;
  wire \oe_low[2]_i_1_n_0 ;
  wire \oe_low[3]_i_1_n_0 ;
  wire \oe_low[4]_i_1_n_0 ;
  wire \oe_low[5]_i_1_n_0 ;
  wire \oe_low[6]_i_1_n_0 ;
  wire \oe_low[7]_i_1_n_0 ;
  wire [3:0]\oe_low_reg[3]_0 ;
  wire \oe_low_reg[5]_0 ;
  wire [7:4]oe_upp;
  wire \oe_upp[0]_i_1_n_0 ;
  wire \oe_upp[1]_i_1_n_0 ;
  wire \oe_upp[2]_i_1_n_0 ;
  wire \oe_upp[3]_i_1_n_0 ;
  wire \oe_upp[4]_i_1_n_0 ;
  wire \oe_upp[5]_i_1_n_0 ;
  wire \oe_upp[6]_i_1_n_0 ;
  wire \oe_upp[7]_i_1_n_0 ;
  wire [3:0]\oe_upp_reg[3]_0 ;
  wire out;
  wire pointer_we;
  wire [0:0]\rams[1].RAM32M0 ;
  wire [1:1]sel;
  wire \wosp_reg[1] ;
  wire \wosp_reg[2] ;
  wire \wosp_reg[2]_rep ;
  wire \wosp_reg[2]_rep__0 ;
  wire \wosp_reg[2]_rep__1 ;
  wire \wosp_reg[2]_rep__2 ;
  wire \wosp_reg[2]_rep__3 ;
  wire \wosp_reg[2]_rep__4 ;
  wire \wosp_reg[2]_rep__5 ;
  wire \wosp_reg[2]_rep__6 ;
  wire \wosp_reg[2]_rep__7 ;
  wire wrDataVal_reg_0;
  wire \wrQ[0][0]_rep_i_1_n_0 ;
  wire [2:0]\wrQ_nxt[0]_12 ;
  wire [0:0]\wrQ_nxt[1]_13 ;
  wire \wrQ_reg[0][0]_0 ;
  wire [0:0]\wrQ_reg[0][0]_1 ;
  wire \wrQ_reg[0][0]_rep_0 ;
  wire \wrQ_reg[0][2]_0 ;
  wire \wrQ_reg[0][5]_rep_0 ;
  wire \wrQ_reg[0][5]_rep__0_0 ;
  wire \wrQ_reg[0][5]_rep__1_0 ;
  wire \wrQ_reg[0][6]_rep_0 ;
  wire \wrQ_reg[0][6]_rep__0_0 ;
  wire \wrQ_reg[0][6]_rep__1_0 ;
  wire \wrQ_reg[0][7]_rep_0 ;
  wire \wrQ_reg[0][7]_rep__0_0 ;
  wire \wrQ_reg[0][7]_rep__1_0 ;
  wire [3:0]\wrQ_reg[0][8]_0 ;
  wire \wrQ_reg[0][8]_rep_0 ;
  wire [3:0]\wrQ_reg[0][8]_rep__0_0 ;
  wire \wrQ_reg[0][8]_rep__0_1 ;
  wire [3:0]\wrQ_reg[0][8]_rep__1_0 ;
  wire \wrQ_reg[0][8]_rep__1_1 ;
  wire [3:0]\wrQ_reg[1][8]_0 ;
  wire [4:0]\wrQ_reg[1][8]_1 ;
  wire [2:0]\wrQ_reg[1]_11 ;

  FDRE cal_oe_dis_low_dly_reg
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_oe_dis_low),
        .Q(cal_oe_dis_low_dly),
        .R(1'b0));
  FDRE cal_oe_dis_upp_dly_reg
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(cal_oe_dis_upp),
        .Q(cal_oe_dis_upp_dly),
        .R(1'b0));
  ddr4_0_ddr4_v2_2_17_cal_wr_byte \genByte[0].u_ddr_mc_wr_byte 
       (.D({dReg0_out_59[15],dReg0_out_59[13:12],\dReg_reg[9] ,dReg0_out_59[7:2]}),
        .DMOut(DMOut[7:6]),
        .DQOut({DQOut[63:62],DQOut[55:54],DQOut[47:46],DQOut[39:38],DQOut[31:30],DQOut[23:22],DQOut[15:14],DQOut[6]}),
        .Q({dReg[15],dReg[13:12],ch0_mcal_DQOut[7:0]}),
        .\dReg_reg[10] (\dReg_reg[10] ),
        .\dReg_reg[10]_0 (\genByte[1].u_ddr_mc_wr_byte_n_0 ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_0 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_1 ),
        .\dReg_reg[10]_3 (\dReg_reg[10]_2 ),
        .\dReg_reg[10]_4 (\dReg_reg[10]_3 ),
        .\dReg_reg[10]_5 (\dReg_reg[10]_4 ),
        .\dReg_reg[10]_6 (\dReg_reg[10]_5 ),
        .\dReg_reg[10]_7 (\dReg_reg[10]_6 ),
        .\dReg_reg[10]_8 (\dReg_reg[10]_7 ),
        .\dReg_reg[10]_9 (\dReg_reg[10]_8 ),
        .\dReg_reg[11] (\dReg_reg[11] ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_0 ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_1 ),
        .\dReg_reg[11]_2 (\dReg_reg[11]_2 ),
        .\dReg_reg[11]_3 (\dReg_reg[11]_3 ),
        .\dReg_reg[11]_4 (\dReg_reg[11]_4 ),
        .\dReg_reg[11]_5 (\dReg_reg[11]_5 ),
        .\dReg_reg[11]_6 (\dReg_reg[11]_6 ),
        .\dReg_reg[11]_7 (\dReg_reg[11]_7 ),
        .\dReg_reg[13] ({dReg__0[13:12],ch0_mcal_DQOut[15:8]}),
        .\dReg_reg[13]_0 ({dReg__1[13:12],ch0_mcal_DQOut[23:16]}),
        .\dReg_reg[13]_1 ({dReg__2[13:12],ch0_mcal_DQOut[31:24]}),
        .\dReg_reg[13]_10 ({\genByte[7].u_ddr_mc_wr_byte_n_53 ,\genByte[7].u_ddr_mc_wr_byte_n_54 ,\dReg_reg[9]_3 ,\genByte[7].u_ddr_mc_wr_byte_n_55 ,\genByte[7].u_ddr_mc_wr_byte_n_56 ,\genByte[7].u_ddr_mc_wr_byte_n_57 ,\genByte[7].u_ddr_mc_wr_byte_n_58 ,\genByte[7].u_ddr_mc_wr_byte_n_59 ,\genByte[7].u_ddr_mc_wr_byte_n_60 }),
        .\dReg_reg[13]_11 ({\genByte[7].u_ddr_mc_wr_byte_n_45 ,\genByte[7].u_ddr_mc_wr_byte_n_46 ,\dReg_reg[9]_4 ,\genByte[7].u_ddr_mc_wr_byte_n_47 ,\genByte[7].u_ddr_mc_wr_byte_n_48 ,\genByte[7].u_ddr_mc_wr_byte_n_49 ,\genByte[7].u_ddr_mc_wr_byte_n_50 ,\genByte[7].u_ddr_mc_wr_byte_n_51 ,\genByte[7].u_ddr_mc_wr_byte_n_52 }),
        .\dReg_reg[13]_12 ({\genByte[7].u_ddr_mc_wr_byte_n_37 ,\genByte[7].u_ddr_mc_wr_byte_n_38 ,\dReg_reg[9]_5 ,\genByte[7].u_ddr_mc_wr_byte_n_39 ,\genByte[7].u_ddr_mc_wr_byte_n_40 ,\genByte[7].u_ddr_mc_wr_byte_n_41 ,\genByte[7].u_ddr_mc_wr_byte_n_42 ,\genByte[7].u_ddr_mc_wr_byte_n_43 ,\genByte[7].u_ddr_mc_wr_byte_n_44 }),
        .\dReg_reg[13]_13 ({\genByte[7].u_ddr_mc_wr_byte_n_29 ,\genByte[7].u_ddr_mc_wr_byte_n_30 ,\dReg_reg[9]_6 ,\genByte[7].u_ddr_mc_wr_byte_n_31 ,\genByte[7].u_ddr_mc_wr_byte_n_32 ,\genByte[7].u_ddr_mc_wr_byte_n_33 ,\genByte[7].u_ddr_mc_wr_byte_n_34 ,\genByte[7].u_ddr_mc_wr_byte_n_35 ,\genByte[7].u_ddr_mc_wr_byte_n_36 }),
        .\dReg_reg[13]_14 ({\genByte[7].u_ddr_mc_wr_byte_n_21 ,\genByte[7].u_ddr_mc_wr_byte_n_22 ,\dReg_reg[9]_7 ,\genByte[7].u_ddr_mc_wr_byte_n_23 ,\genByte[7].u_ddr_mc_wr_byte_n_24 ,\genByte[7].u_ddr_mc_wr_byte_n_25 ,\genByte[7].u_ddr_mc_wr_byte_n_26 ,\genByte[7].u_ddr_mc_wr_byte_n_27 ,\genByte[7].u_ddr_mc_wr_byte_n_28 }),
        .\dReg_reg[13]_2 ({dReg__3[13:12],ch0_mcal_DQOut[39:32]}),
        .\dReg_reg[13]_3 ({dReg__4[13:12],ch0_mcal_DQOut[47:40]}),
        .\dReg_reg[13]_4 ({dReg__5[13:12],ch0_mcal_DQOut[55:48]}),
        .\dReg_reg[13]_5 ({dReg__6[13:12],ch0_mcal_DQOut[63:56]}),
        .\dReg_reg[13]_6 ({dReg__7[13:12],ch0_mcal_DMOut_n[7:0]}),
        .\dReg_reg[13]_7 ({\genByte[7].u_ddr_mc_wr_byte_n_77 ,\genByte[7].u_ddr_mc_wr_byte_n_78 ,\dReg_reg[9]_0 ,\genByte[7].u_ddr_mc_wr_byte_n_79 ,\genByte[7].u_ddr_mc_wr_byte_n_80 ,\genByte[7].u_ddr_mc_wr_byte_n_81 ,\genByte[7].u_ddr_mc_wr_byte_n_82 ,\genByte[7].u_ddr_mc_wr_byte_n_83 ,\genByte[7].u_ddr_mc_wr_byte_n_84 }),
        .\dReg_reg[13]_8 ({\genByte[7].u_ddr_mc_wr_byte_n_69 ,\genByte[7].u_ddr_mc_wr_byte_n_70 ,\dReg_reg[9]_1 ,\genByte[7].u_ddr_mc_wr_byte_n_71 ,\genByte[7].u_ddr_mc_wr_byte_n_72 ,\genByte[7].u_ddr_mc_wr_byte_n_73 ,\genByte[7].u_ddr_mc_wr_byte_n_74 ,\genByte[7].u_ddr_mc_wr_byte_n_75 ,\genByte[7].u_ddr_mc_wr_byte_n_76 }),
        .\dReg_reg[13]_9 ({\genByte[7].u_ddr_mc_wr_byte_n_61 ,\genByte[7].u_ddr_mc_wr_byte_n_62 ,\dReg_reg[9]_2 ,\genByte[7].u_ddr_mc_wr_byte_n_63 ,\genByte[7].u_ddr_mc_wr_byte_n_64 ,\genByte[7].u_ddr_mc_wr_byte_n_65 ,\genByte[7].u_ddr_mc_wr_byte_n_66 ,\genByte[7].u_ddr_mc_wr_byte_n_67 ,\genByte[7].u_ddr_mc_wr_byte_n_68 }),
        .\dReg_reg[14] ({dReg[14],dReg[11:10]}),
        .\dReg_reg[14]_0 (\genByte[7].u_ddr_mc_wr_byte_n_11 ),
        .\dReg_reg[15] ({dReg__0[15:14],dReg__0[11:10]}),
        .\dReg_reg[15]_0 ({dReg__1[15:14],dReg__1[11:10]}),
        .\dReg_reg[15]_1 ({dReg__2[15:14],dReg__2[11:10]}),
        .\dReg_reg[15]_2 ({dReg__3[15:14],dReg__3[11:10]}),
        .\dReg_reg[15]_3 ({dReg__4[15:14],dReg__4[11:10]}),
        .\dReg_reg[15]_4 ({dReg__5[15:14],dReg__5[11:10]}),
        .\dReg_reg[15]_5 ({dReg__6[15:14],dReg__6[11:10]}),
        .\dReg_reg[15]_6 ({dReg__7[15:14],dReg__7[11:10]}));
  ddr4_0_ddr4_v2_2_17_cal_wr_byte_27 \genByte[1].u_ddr_mc_wr_byte 
       (.D({dReg0_out_58[15],dReg0_out_58[13:12],\dReg_reg[9]_8 ,dReg0_out_58[7:2]}),
        .DMOut(DMOut[15:14]),
        .DQOut({DQOut[127:126],DQOut[119:118],DQOut[111:110],DQOut[103:102],DQOut[95:94],DQOut[87:86],DQOut[79:78],DQOut[70]}),
        .Q({dReg_8[15],dReg_8[13:12],ch0_mcal_DQOut[71:64]}),
        .\dReg_reg[10] (\dReg_reg[10] ),
        .\dReg_reg[10]_0 (\dReg_reg[10]_9 ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_10 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_11 ),
        .\dReg_reg[10]_3 (\dReg_reg[10]_12 ),
        .\dReg_reg[10]_4 (\dReg_reg[10]_13 ),
        .\dReg_reg[10]_5 (\dReg_reg[10]_14 ),
        .\dReg_reg[10]_6 (\dReg_reg[10]_15 ),
        .\dReg_reg[10]_7 (\dReg_reg[10]_16 ),
        .\dReg_reg[10]_8 (\dReg_reg[10]_17 ),
        .\dReg_reg[11] (wrDataVal_reg_0),
        .\dReg_reg[11]_0 (\dReg_reg[11]_8 ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_9 ),
        .\dReg_reg[11]_2 (\dReg_reg[11]_10 ),
        .\dReg_reg[11]_3 (\dReg_reg[11]_11 ),
        .\dReg_reg[11]_4 (\dReg_reg[11]_12 ),
        .\dReg_reg[11]_5 (\dReg_reg[11]_13 ),
        .\dReg_reg[11]_6 (\dReg_reg[11]_14 ),
        .\dReg_reg[11]_7 (\dReg_reg[11]_15 ),
        .\dReg_reg[11]_8 (\dReg_reg[11]_16 ),
        .\dReg_reg[13] ({dReg__0_7[13:12],ch0_mcal_DQOut[79:72]}),
        .\dReg_reg[13]_0 ({dReg__1_6[13:12],ch0_mcal_DQOut[87:80]}),
        .\dReg_reg[13]_1 ({dReg__2_5[13:12],ch0_mcal_DQOut[95:88]}),
        .\dReg_reg[13]_10 ({\genByte[7].u_ddr_mc_wr_byte_n_126 ,\genByte[7].u_ddr_mc_wr_byte_n_127 ,\dReg_reg[9]_12 ,\genByte[7].u_ddr_mc_wr_byte_n_128 ,\genByte[7].u_ddr_mc_wr_byte_n_129 ,\genByte[7].u_ddr_mc_wr_byte_n_130 ,\genByte[7].u_ddr_mc_wr_byte_n_131 ,\genByte[7].u_ddr_mc_wr_byte_n_132 ,\genByte[7].u_ddr_mc_wr_byte_n_133 }),
        .\dReg_reg[13]_11 ({\genByte[7].u_ddr_mc_wr_byte_n_118 ,\genByte[7].u_ddr_mc_wr_byte_n_119 ,\dReg_reg[9]_13 ,\genByte[7].u_ddr_mc_wr_byte_n_120 ,\genByte[7].u_ddr_mc_wr_byte_n_121 ,\genByte[7].u_ddr_mc_wr_byte_n_122 ,\genByte[7].u_ddr_mc_wr_byte_n_123 ,\genByte[7].u_ddr_mc_wr_byte_n_124 ,\genByte[7].u_ddr_mc_wr_byte_n_125 }),
        .\dReg_reg[13]_12 ({\genByte[7].u_ddr_mc_wr_byte_n_110 ,\genByte[7].u_ddr_mc_wr_byte_n_111 ,\dReg_reg[9]_14 ,\genByte[7].u_ddr_mc_wr_byte_n_112 ,\genByte[7].u_ddr_mc_wr_byte_n_113 ,\genByte[7].u_ddr_mc_wr_byte_n_114 ,\genByte[7].u_ddr_mc_wr_byte_n_115 ,\genByte[7].u_ddr_mc_wr_byte_n_116 ,\genByte[7].u_ddr_mc_wr_byte_n_117 }),
        .\dReg_reg[13]_13 ({\genByte[7].u_ddr_mc_wr_byte_n_102 ,\genByte[7].u_ddr_mc_wr_byte_n_103 ,\dReg_reg[9]_15 ,\genByte[7].u_ddr_mc_wr_byte_n_104 ,\genByte[7].u_ddr_mc_wr_byte_n_105 ,\genByte[7].u_ddr_mc_wr_byte_n_106 ,\genByte[7].u_ddr_mc_wr_byte_n_107 ,\genByte[7].u_ddr_mc_wr_byte_n_108 ,\genByte[7].u_ddr_mc_wr_byte_n_109 }),
        .\dReg_reg[13]_14 ({\genByte[7].u_ddr_mc_wr_byte_n_94 ,\genByte[7].u_ddr_mc_wr_byte_n_95 ,\dReg_reg[9]_16 ,\genByte[7].u_ddr_mc_wr_byte_n_96 ,\genByte[7].u_ddr_mc_wr_byte_n_97 ,\genByte[7].u_ddr_mc_wr_byte_n_98 ,\genByte[7].u_ddr_mc_wr_byte_n_99 ,\genByte[7].u_ddr_mc_wr_byte_n_100 ,\genByte[7].u_ddr_mc_wr_byte_n_101 }),
        .\dReg_reg[13]_2 ({dReg__3_4[13:12],ch0_mcal_DQOut[103:96]}),
        .\dReg_reg[13]_3 ({dReg__4_3[13:12],ch0_mcal_DQOut[111:104]}),
        .\dReg_reg[13]_4 ({dReg__5_2[13:12],ch0_mcal_DQOut[119:112]}),
        .\dReg_reg[13]_5 ({dReg__6_1[13:12],ch0_mcal_DQOut[127:120]}),
        .\dReg_reg[13]_6 ({dReg__7_0[13:12],ch0_mcal_DMOut_n[15:8]}),
        .\dReg_reg[13]_7 ({\genByte[7].u_ddr_mc_wr_byte_n_150 ,\genByte[7].u_ddr_mc_wr_byte_n_151 ,\dReg_reg[9]_9 ,\genByte[7].u_ddr_mc_wr_byte_n_152 ,\genByte[7].u_ddr_mc_wr_byte_n_153 ,\genByte[7].u_ddr_mc_wr_byte_n_154 ,\genByte[7].u_ddr_mc_wr_byte_n_155 ,\genByte[7].u_ddr_mc_wr_byte_n_156 ,\genByte[7].u_ddr_mc_wr_byte_n_157 }),
        .\dReg_reg[13]_8 ({\genByte[7].u_ddr_mc_wr_byte_n_142 ,\genByte[7].u_ddr_mc_wr_byte_n_143 ,\dReg_reg[9]_10 ,\genByte[7].u_ddr_mc_wr_byte_n_144 ,\genByte[7].u_ddr_mc_wr_byte_n_145 ,\genByte[7].u_ddr_mc_wr_byte_n_146 ,\genByte[7].u_ddr_mc_wr_byte_n_147 ,\genByte[7].u_ddr_mc_wr_byte_n_148 ,\genByte[7].u_ddr_mc_wr_byte_n_149 }),
        .\dReg_reg[13]_9 ({\genByte[7].u_ddr_mc_wr_byte_n_134 ,\genByte[7].u_ddr_mc_wr_byte_n_135 ,\dReg_reg[9]_11 ,\genByte[7].u_ddr_mc_wr_byte_n_136 ,\genByte[7].u_ddr_mc_wr_byte_n_137 ,\genByte[7].u_ddr_mc_wr_byte_n_138 ,\genByte[7].u_ddr_mc_wr_byte_n_139 ,\genByte[7].u_ddr_mc_wr_byte_n_140 ,\genByte[7].u_ddr_mc_wr_byte_n_141 }),
        .\dReg_reg[14] ({dReg_8[14],dReg_8[11:10]}),
        .\dReg_reg[14]_0 (\genByte[7].u_ddr_mc_wr_byte_n_11 ),
        .\dReg_reg[15] ({dReg__0_7[15:14],dReg__0_7[11:10]}),
        .\dReg_reg[15]_0 ({dReg__1_6[15:14],dReg__1_6[11:10]}),
        .\dReg_reg[15]_1 ({dReg__2_5[15:14],dReg__2_5[11:10]}),
        .\dReg_reg[15]_2 ({dReg__3_4[15:14],dReg__3_4[11:10]}),
        .\dReg_reg[15]_3 ({dReg__4_3[15:14],dReg__4_3[11:10]}),
        .\dReg_reg[15]_4 ({dReg__5_2[15:14],dReg__5_2[11:10]}),
        .\dReg_reg[15]_5 ({dReg__6_1[15:14],dReg__6_1[11:10]}),
        .\dReg_reg[15]_6 ({dReg__7_0[15:14],dReg__7_0[11:10]}),
        .wrDataVal_reg(\genByte[1].u_ddr_mc_wr_byte_n_0 ));
  ddr4_0_ddr4_v2_2_17_cal_wr_byte_28 \genByte[2].u_ddr_mc_wr_byte 
       (.D({dReg0_out_57[15],dReg0_out_57[13:12],\dReg_reg[9]_17 ,dReg0_out_57[7:2]}),
        .DMOut(DMOut[23:22]),
        .DQOut({DQOut[191:190],DQOut[183:182],DQOut[175:174],DQOut[167:166],DQOut[159:158],DQOut[151:150],DQOut[143:142],DQOut[134]}),
        .Q({dReg_17[15],dReg_17[13:12],ch0_mcal_DQOut[135:128]}),
        .\dReg_reg[10] (\dReg_reg[10] ),
        .\dReg_reg[10]_0 (\dReg_reg[10]_18 ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_19 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_20 ),
        .\dReg_reg[10]_3 (\dReg_reg[10]_21 ),
        .\dReg_reg[10]_4 (\dReg_reg[10]_22 ),
        .\dReg_reg[10]_5 (\dReg_reg[10]_23 ),
        .\dReg_reg[10]_6 (\dReg_reg[10]_24 ),
        .\dReg_reg[10]_7 (\dReg_reg[10]_25 ),
        .\dReg_reg[10]_8 (\dReg_reg[10]_26 ),
        .\dReg_reg[11] (\genByte[1].u_ddr_mc_wr_byte_n_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_17 ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_18 ),
        .\dReg_reg[11]_2 (\dReg_reg[11]_19 ),
        .\dReg_reg[11]_3 (\dReg_reg[11]_20 ),
        .\dReg_reg[11]_4 (\dReg_reg[11]_21 ),
        .\dReg_reg[11]_5 (\dReg_reg[11]_22 ),
        .\dReg_reg[11]_6 (\dReg_reg[11]_23 ),
        .\dReg_reg[11]_7 (\dReg_reg[11]_24 ),
        .\dReg_reg[11]_8 (\dReg_reg[11]_25 ),
        .\dReg_reg[13] ({dReg__0_16[13:12],ch0_mcal_DQOut[143:136]}),
        .\dReg_reg[13]_0 ({dReg__1_15[13:12],ch0_mcal_DQOut[151:144]}),
        .\dReg_reg[13]_1 ({dReg__2_14[13:12],ch0_mcal_DQOut[159:152]}),
        .\dReg_reg[13]_10 ({\genByte[7].u_ddr_mc_wr_byte_n_199 ,\genByte[7].u_ddr_mc_wr_byte_n_200 ,\dReg_reg[9]_21 ,\genByte[7].u_ddr_mc_wr_byte_n_201 ,\genByte[7].u_ddr_mc_wr_byte_n_202 ,\genByte[7].u_ddr_mc_wr_byte_n_203 ,\genByte[7].u_ddr_mc_wr_byte_n_204 ,\genByte[7].u_ddr_mc_wr_byte_n_205 ,\genByte[7].u_ddr_mc_wr_byte_n_206 }),
        .\dReg_reg[13]_11 ({\genByte[7].u_ddr_mc_wr_byte_n_191 ,\genByte[7].u_ddr_mc_wr_byte_n_192 ,\dReg_reg[9]_22 ,\genByte[7].u_ddr_mc_wr_byte_n_193 ,\genByte[7].u_ddr_mc_wr_byte_n_194 ,\genByte[7].u_ddr_mc_wr_byte_n_195 ,\genByte[7].u_ddr_mc_wr_byte_n_196 ,\genByte[7].u_ddr_mc_wr_byte_n_197 ,\genByte[7].u_ddr_mc_wr_byte_n_198 }),
        .\dReg_reg[13]_12 ({\genByte[7].u_ddr_mc_wr_byte_n_183 ,\genByte[7].u_ddr_mc_wr_byte_n_184 ,\dReg_reg[9]_23 ,\genByte[7].u_ddr_mc_wr_byte_n_185 ,\genByte[7].u_ddr_mc_wr_byte_n_186 ,\genByte[7].u_ddr_mc_wr_byte_n_187 ,\genByte[7].u_ddr_mc_wr_byte_n_188 ,\genByte[7].u_ddr_mc_wr_byte_n_189 ,\genByte[7].u_ddr_mc_wr_byte_n_190 }),
        .\dReg_reg[13]_13 ({\genByte[7].u_ddr_mc_wr_byte_n_175 ,\genByte[7].u_ddr_mc_wr_byte_n_176 ,\dReg_reg[9]_24 ,\genByte[7].u_ddr_mc_wr_byte_n_177 ,\genByte[7].u_ddr_mc_wr_byte_n_178 ,\genByte[7].u_ddr_mc_wr_byte_n_179 ,\genByte[7].u_ddr_mc_wr_byte_n_180 ,\genByte[7].u_ddr_mc_wr_byte_n_181 ,\genByte[7].u_ddr_mc_wr_byte_n_182 }),
        .\dReg_reg[13]_14 ({\genByte[7].u_ddr_mc_wr_byte_n_167 ,\genByte[7].u_ddr_mc_wr_byte_n_168 ,\dReg_reg[9]_25 ,\genByte[7].u_ddr_mc_wr_byte_n_169 ,\genByte[7].u_ddr_mc_wr_byte_n_170 ,\genByte[7].u_ddr_mc_wr_byte_n_171 ,\genByte[7].u_ddr_mc_wr_byte_n_172 ,\genByte[7].u_ddr_mc_wr_byte_n_173 ,\genByte[7].u_ddr_mc_wr_byte_n_174 }),
        .\dReg_reg[13]_2 ({dReg__3_13[13:12],ch0_mcal_DQOut[167:160]}),
        .\dReg_reg[13]_3 ({dReg__4_12[13:12],ch0_mcal_DQOut[175:168]}),
        .\dReg_reg[13]_4 ({dReg__5_11[13:12],ch0_mcal_DQOut[183:176]}),
        .\dReg_reg[13]_5 ({dReg__6_10[13:12],ch0_mcal_DQOut[191:184]}),
        .\dReg_reg[13]_6 ({dReg__7_9[13:12],ch0_mcal_DMOut_n[23:16]}),
        .\dReg_reg[13]_7 ({\genByte[7].u_ddr_mc_wr_byte_n_223 ,\genByte[7].u_ddr_mc_wr_byte_n_224 ,\dReg_reg[9]_18 ,\genByte[7].u_ddr_mc_wr_byte_n_225 ,\genByte[7].u_ddr_mc_wr_byte_n_226 ,\genByte[7].u_ddr_mc_wr_byte_n_227 ,\genByte[7].u_ddr_mc_wr_byte_n_228 ,\genByte[7].u_ddr_mc_wr_byte_n_229 ,\genByte[7].u_ddr_mc_wr_byte_n_230 }),
        .\dReg_reg[13]_8 ({\genByte[7].u_ddr_mc_wr_byte_n_215 ,\genByte[7].u_ddr_mc_wr_byte_n_216 ,\dReg_reg[9]_19 ,\genByte[7].u_ddr_mc_wr_byte_n_217 ,\genByte[7].u_ddr_mc_wr_byte_n_218 ,\genByte[7].u_ddr_mc_wr_byte_n_219 ,\genByte[7].u_ddr_mc_wr_byte_n_220 ,\genByte[7].u_ddr_mc_wr_byte_n_221 ,\genByte[7].u_ddr_mc_wr_byte_n_222 }),
        .\dReg_reg[13]_9 ({\genByte[7].u_ddr_mc_wr_byte_n_207 ,\genByte[7].u_ddr_mc_wr_byte_n_208 ,\dReg_reg[9]_20 ,\genByte[7].u_ddr_mc_wr_byte_n_209 ,\genByte[7].u_ddr_mc_wr_byte_n_210 ,\genByte[7].u_ddr_mc_wr_byte_n_211 ,\genByte[7].u_ddr_mc_wr_byte_n_212 ,\genByte[7].u_ddr_mc_wr_byte_n_213 ,\genByte[7].u_ddr_mc_wr_byte_n_214 }),
        .\dReg_reg[14] ({dReg_17[14],dReg_17[11:10]}),
        .\dReg_reg[14]_0 (\genByte[7].u_ddr_mc_wr_byte_n_11 ),
        .\dReg_reg[15] ({dReg__0_16[15:14],dReg__0_16[11:10]}),
        .\dReg_reg[15]_0 ({dReg__1_15[15:14],dReg__1_15[11:10]}),
        .\dReg_reg[15]_1 ({dReg__2_14[15:14],dReg__2_14[11:10]}),
        .\dReg_reg[15]_2 ({dReg__3_13[15:14],dReg__3_13[11:10]}),
        .\dReg_reg[15]_3 ({dReg__4_12[15:14],dReg__4_12[11:10]}),
        .\dReg_reg[15]_4 ({dReg__5_11[15:14],dReg__5_11[11:10]}),
        .\dReg_reg[15]_5 ({dReg__6_10[15:14],dReg__6_10[11:10]}),
        .\dReg_reg[15]_6 ({dReg__7_9[15:14],dReg__7_9[11:10]}));
  ddr4_0_ddr4_v2_2_17_cal_wr_byte_29 \genByte[3].u_ddr_mc_wr_byte 
       (.D({dReg0_out_56[15],dReg0_out_56[13:12],\dReg_reg[9]_26 ,dReg0_out_56[7:2]}),
        .DMOut(DMOut[31:30]),
        .DQOut({DQOut[255:254],DQOut[247:246],DQOut[239:238],DQOut[231:230],DQOut[223:222],DQOut[215:214],DQOut[207:206],DQOut[198]}),
        .Q({dReg_26[15],dReg_26[13:12],ch0_mcal_DQOut[199:192]}),
        .\dReg_reg[10] (\dReg_reg[10] ),
        .\dReg_reg[10]_0 (\dReg_reg[10]_27 ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_28 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_29 ),
        .\dReg_reg[10]_3 (\dReg_reg[10]_30 ),
        .\dReg_reg[10]_4 (\dReg_reg[10]_31 ),
        .\dReg_reg[10]_5 (\dReg_reg[10]_32 ),
        .\dReg_reg[10]_6 (\dReg_reg[10]_33 ),
        .\dReg_reg[10]_7 (\dReg_reg[10]_34 ),
        .\dReg_reg[10]_8 (\dReg_reg[10]_35 ),
        .\dReg_reg[11] (\genByte[1].u_ddr_mc_wr_byte_n_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_26 ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_27 ),
        .\dReg_reg[11]_2 (\dReg_reg[11]_28 ),
        .\dReg_reg[11]_3 (\dReg_reg[11]_29 ),
        .\dReg_reg[11]_4 (\dReg_reg[11]_30 ),
        .\dReg_reg[11]_5 (\dReg_reg[11]_31 ),
        .\dReg_reg[11]_6 (\dReg_reg[11]_32 ),
        .\dReg_reg[11]_7 (\dReg_reg[11]_33 ),
        .\dReg_reg[11]_8 (\dReg_reg[11]_34 ),
        .\dReg_reg[13] ({dReg__0_25[13:12],ch0_mcal_DQOut[207:200]}),
        .\dReg_reg[13]_0 ({dReg__1_24[13:12],ch0_mcal_DQOut[215:208]}),
        .\dReg_reg[13]_1 ({dReg__2_23[13:12],ch0_mcal_DQOut[223:216]}),
        .\dReg_reg[13]_10 ({\genByte[7].u_ddr_mc_wr_byte_n_272 ,\genByte[7].u_ddr_mc_wr_byte_n_273 ,\dReg_reg[9]_30 ,\genByte[7].u_ddr_mc_wr_byte_n_274 ,\genByte[7].u_ddr_mc_wr_byte_n_275 ,\genByte[7].u_ddr_mc_wr_byte_n_276 ,\genByte[7].u_ddr_mc_wr_byte_n_277 ,\genByte[7].u_ddr_mc_wr_byte_n_278 ,\genByte[7].u_ddr_mc_wr_byte_n_279 }),
        .\dReg_reg[13]_11 ({\genByte[7].u_ddr_mc_wr_byte_n_264 ,\genByte[7].u_ddr_mc_wr_byte_n_265 ,\dReg_reg[9]_31 ,\genByte[7].u_ddr_mc_wr_byte_n_266 ,\genByte[7].u_ddr_mc_wr_byte_n_267 ,\genByte[7].u_ddr_mc_wr_byte_n_268 ,\genByte[7].u_ddr_mc_wr_byte_n_269 ,\genByte[7].u_ddr_mc_wr_byte_n_270 ,\genByte[7].u_ddr_mc_wr_byte_n_271 }),
        .\dReg_reg[13]_12 ({\genByte[7].u_ddr_mc_wr_byte_n_256 ,\genByte[7].u_ddr_mc_wr_byte_n_257 ,\dReg_reg[9]_32 ,\genByte[7].u_ddr_mc_wr_byte_n_258 ,\genByte[7].u_ddr_mc_wr_byte_n_259 ,\genByte[7].u_ddr_mc_wr_byte_n_260 ,\genByte[7].u_ddr_mc_wr_byte_n_261 ,\genByte[7].u_ddr_mc_wr_byte_n_262 ,\genByte[7].u_ddr_mc_wr_byte_n_263 }),
        .\dReg_reg[13]_13 ({\genByte[7].u_ddr_mc_wr_byte_n_248 ,\genByte[7].u_ddr_mc_wr_byte_n_249 ,\dReg_reg[9]_33 ,\genByte[7].u_ddr_mc_wr_byte_n_250 ,\genByte[7].u_ddr_mc_wr_byte_n_251 ,\genByte[7].u_ddr_mc_wr_byte_n_252 ,\genByte[7].u_ddr_mc_wr_byte_n_253 ,\genByte[7].u_ddr_mc_wr_byte_n_254 ,\genByte[7].u_ddr_mc_wr_byte_n_255 }),
        .\dReg_reg[13]_14 ({\genByte[7].u_ddr_mc_wr_byte_n_240 ,\genByte[7].u_ddr_mc_wr_byte_n_241 ,\dReg_reg[9]_34 ,\genByte[7].u_ddr_mc_wr_byte_n_242 ,\genByte[7].u_ddr_mc_wr_byte_n_243 ,\genByte[7].u_ddr_mc_wr_byte_n_244 ,\genByte[7].u_ddr_mc_wr_byte_n_245 ,\genByte[7].u_ddr_mc_wr_byte_n_246 ,\genByte[7].u_ddr_mc_wr_byte_n_247 }),
        .\dReg_reg[13]_2 ({dReg__3_22[13:12],ch0_mcal_DQOut[231:224]}),
        .\dReg_reg[13]_3 ({dReg__4_21[13:12],ch0_mcal_DQOut[239:232]}),
        .\dReg_reg[13]_4 ({dReg__5_20[13:12],ch0_mcal_DQOut[247:240]}),
        .\dReg_reg[13]_5 ({dReg__6_19[13:12],ch0_mcal_DQOut[255:248]}),
        .\dReg_reg[13]_6 ({dReg__7_18[13:12],ch0_mcal_DMOut_n[31:24]}),
        .\dReg_reg[13]_7 ({\genByte[7].u_ddr_mc_wr_byte_n_296 ,\genByte[7].u_ddr_mc_wr_byte_n_297 ,\dReg_reg[9]_27 ,\genByte[7].u_ddr_mc_wr_byte_n_298 ,\genByte[7].u_ddr_mc_wr_byte_n_299 ,\genByte[7].u_ddr_mc_wr_byte_n_300 ,\genByte[7].u_ddr_mc_wr_byte_n_301 ,\genByte[7].u_ddr_mc_wr_byte_n_302 ,\genByte[7].u_ddr_mc_wr_byte_n_303 }),
        .\dReg_reg[13]_8 ({\genByte[7].u_ddr_mc_wr_byte_n_288 ,\genByte[7].u_ddr_mc_wr_byte_n_289 ,\dReg_reg[9]_28 ,\genByte[7].u_ddr_mc_wr_byte_n_290 ,\genByte[7].u_ddr_mc_wr_byte_n_291 ,\genByte[7].u_ddr_mc_wr_byte_n_292 ,\genByte[7].u_ddr_mc_wr_byte_n_293 ,\genByte[7].u_ddr_mc_wr_byte_n_294 ,\genByte[7].u_ddr_mc_wr_byte_n_295 }),
        .\dReg_reg[13]_9 ({\genByte[7].u_ddr_mc_wr_byte_n_280 ,\genByte[7].u_ddr_mc_wr_byte_n_281 ,\dReg_reg[9]_29 ,\genByte[7].u_ddr_mc_wr_byte_n_282 ,\genByte[7].u_ddr_mc_wr_byte_n_283 ,\genByte[7].u_ddr_mc_wr_byte_n_284 ,\genByte[7].u_ddr_mc_wr_byte_n_285 ,\genByte[7].u_ddr_mc_wr_byte_n_286 ,\genByte[7].u_ddr_mc_wr_byte_n_287 }),
        .\dReg_reg[14] ({dReg_26[14],dReg_26[11:10]}),
        .\dReg_reg[14]_0 (\genByte[7].u_ddr_mc_wr_byte_n_11 ),
        .\dReg_reg[15] ({dReg__0_25[15:14],dReg__0_25[11:10]}),
        .\dReg_reg[15]_0 ({dReg__1_24[15:14],dReg__1_24[11:10]}),
        .\dReg_reg[15]_1 ({dReg__2_23[15:14],dReg__2_23[11:10]}),
        .\dReg_reg[15]_2 ({dReg__3_22[15:14],dReg__3_22[11:10]}),
        .\dReg_reg[15]_3 ({dReg__4_21[15:14],dReg__4_21[11:10]}),
        .\dReg_reg[15]_4 ({dReg__5_20[15:14],dReg__5_20[11:10]}),
        .\dReg_reg[15]_5 ({dReg__6_19[15:14],dReg__6_19[11:10]}),
        .\dReg_reg[15]_6 ({dReg__7_18[15:14],dReg__7_18[11:10]}));
  ddr4_0_ddr4_v2_2_17_cal_wr_byte_30 \genByte[4].u_ddr_mc_wr_byte 
       (.D({dReg0_out_55[15],dReg0_out_55[13:12],\dReg_reg[9]_35 ,dReg0_out_55[7:2]}),
        .DMOut(DMOut[39:38]),
        .DQOut({DQOut[319:318],DQOut[311:310],DQOut[303:302],DQOut[295:294],DQOut[287:286],DQOut[279:278],DQOut[271:270],DQOut[262]}),
        .Q({dReg_35[15],dReg_35[13:12],ch0_mcal_DQOut[263:256]}),
        .\dReg_reg[10] (\dReg_reg[10] ),
        .\dReg_reg[10]_0 (\dReg_reg[10]_36 ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_37 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_38 ),
        .\dReg_reg[10]_3 (\dReg_reg[10]_39 ),
        .\dReg_reg[10]_4 (\dReg_reg[10]_40 ),
        .\dReg_reg[10]_5 (\dReg_reg[10]_41 ),
        .\dReg_reg[10]_6 (\dReg_reg[10]_42 ),
        .\dReg_reg[10]_7 (\dReg_reg[10]_43 ),
        .\dReg_reg[10]_8 (\dReg_reg[10]_44 ),
        .\dReg_reg[11] (\genByte[1].u_ddr_mc_wr_byte_n_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_35 ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_36 ),
        .\dReg_reg[11]_2 (\dReg_reg[11]_37 ),
        .\dReg_reg[11]_3 (\dReg_reg[11]_38 ),
        .\dReg_reg[11]_4 (\dReg_reg[11]_39 ),
        .\dReg_reg[11]_5 (\dReg_reg[11]_40 ),
        .\dReg_reg[11]_6 (\dReg_reg[11]_41 ),
        .\dReg_reg[11]_7 (\dReg_reg[11]_42 ),
        .\dReg_reg[11]_8 (\dReg_reg[11]_43 ),
        .\dReg_reg[13] ({dReg__0_34[13:12],ch0_mcal_DQOut[271:264]}),
        .\dReg_reg[13]_0 ({dReg__1_33[13:12],ch0_mcal_DQOut[279:272]}),
        .\dReg_reg[13]_1 ({dReg__2_32[13:12],ch0_mcal_DQOut[287:280]}),
        .\dReg_reg[13]_10 ({\genByte[7].u_ddr_mc_wr_byte_n_345 ,\genByte[7].u_ddr_mc_wr_byte_n_346 ,\dReg_reg[9]_39 ,\genByte[7].u_ddr_mc_wr_byte_n_347 ,\genByte[7].u_ddr_mc_wr_byte_n_348 ,\genByte[7].u_ddr_mc_wr_byte_n_349 ,\genByte[7].u_ddr_mc_wr_byte_n_350 ,\genByte[7].u_ddr_mc_wr_byte_n_351 ,\genByte[7].u_ddr_mc_wr_byte_n_352 }),
        .\dReg_reg[13]_11 ({\genByte[7].u_ddr_mc_wr_byte_n_337 ,\genByte[7].u_ddr_mc_wr_byte_n_338 ,\dReg_reg[9]_40 ,\genByte[7].u_ddr_mc_wr_byte_n_339 ,\genByte[7].u_ddr_mc_wr_byte_n_340 ,\genByte[7].u_ddr_mc_wr_byte_n_341 ,\genByte[7].u_ddr_mc_wr_byte_n_342 ,\genByte[7].u_ddr_mc_wr_byte_n_343 ,\genByte[7].u_ddr_mc_wr_byte_n_344 }),
        .\dReg_reg[13]_12 ({\genByte[7].u_ddr_mc_wr_byte_n_329 ,\genByte[7].u_ddr_mc_wr_byte_n_330 ,\dReg_reg[9]_41 ,\genByte[7].u_ddr_mc_wr_byte_n_331 ,\genByte[7].u_ddr_mc_wr_byte_n_332 ,\genByte[7].u_ddr_mc_wr_byte_n_333 ,\genByte[7].u_ddr_mc_wr_byte_n_334 ,\genByte[7].u_ddr_mc_wr_byte_n_335 ,\genByte[7].u_ddr_mc_wr_byte_n_336 }),
        .\dReg_reg[13]_13 ({\genByte[7].u_ddr_mc_wr_byte_n_321 ,\genByte[7].u_ddr_mc_wr_byte_n_322 ,\dReg_reg[9]_42 ,\genByte[7].u_ddr_mc_wr_byte_n_323 ,\genByte[7].u_ddr_mc_wr_byte_n_324 ,\genByte[7].u_ddr_mc_wr_byte_n_325 ,\genByte[7].u_ddr_mc_wr_byte_n_326 ,\genByte[7].u_ddr_mc_wr_byte_n_327 ,\genByte[7].u_ddr_mc_wr_byte_n_328 }),
        .\dReg_reg[13]_14 ({\genByte[7].u_ddr_mc_wr_byte_n_313 ,\genByte[7].u_ddr_mc_wr_byte_n_314 ,\dReg_reg[9]_43 ,\genByte[7].u_ddr_mc_wr_byte_n_315 ,\genByte[7].u_ddr_mc_wr_byte_n_316 ,\genByte[7].u_ddr_mc_wr_byte_n_317 ,\genByte[7].u_ddr_mc_wr_byte_n_318 ,\genByte[7].u_ddr_mc_wr_byte_n_319 ,\genByte[7].u_ddr_mc_wr_byte_n_320 }),
        .\dReg_reg[13]_2 ({dReg__3_31[13:12],ch0_mcal_DQOut[295:288]}),
        .\dReg_reg[13]_3 ({dReg__4_30[13:12],ch0_mcal_DQOut[303:296]}),
        .\dReg_reg[13]_4 ({dReg__5_29[13:12],ch0_mcal_DQOut[311:304]}),
        .\dReg_reg[13]_5 ({dReg__6_28[13:12],ch0_mcal_DQOut[319:312]}),
        .\dReg_reg[13]_6 ({dReg__7_27[13:12],ch0_mcal_DMOut_n[39:32]}),
        .\dReg_reg[13]_7 ({\genByte[7].u_ddr_mc_wr_byte_n_369 ,\genByte[7].u_ddr_mc_wr_byte_n_370 ,\dReg_reg[9]_36 ,\genByte[7].u_ddr_mc_wr_byte_n_371 ,\genByte[7].u_ddr_mc_wr_byte_n_372 ,\genByte[7].u_ddr_mc_wr_byte_n_373 ,\genByte[7].u_ddr_mc_wr_byte_n_374 ,\genByte[7].u_ddr_mc_wr_byte_n_375 ,\genByte[7].u_ddr_mc_wr_byte_n_376 }),
        .\dReg_reg[13]_8 ({\genByte[7].u_ddr_mc_wr_byte_n_361 ,\genByte[7].u_ddr_mc_wr_byte_n_362 ,\dReg_reg[9]_37 ,\genByte[7].u_ddr_mc_wr_byte_n_363 ,\genByte[7].u_ddr_mc_wr_byte_n_364 ,\genByte[7].u_ddr_mc_wr_byte_n_365 ,\genByte[7].u_ddr_mc_wr_byte_n_366 ,\genByte[7].u_ddr_mc_wr_byte_n_367 ,\genByte[7].u_ddr_mc_wr_byte_n_368 }),
        .\dReg_reg[13]_9 ({\genByte[7].u_ddr_mc_wr_byte_n_353 ,\genByte[7].u_ddr_mc_wr_byte_n_354 ,\dReg_reg[9]_38 ,\genByte[7].u_ddr_mc_wr_byte_n_355 ,\genByte[7].u_ddr_mc_wr_byte_n_356 ,\genByte[7].u_ddr_mc_wr_byte_n_357 ,\genByte[7].u_ddr_mc_wr_byte_n_358 ,\genByte[7].u_ddr_mc_wr_byte_n_359 ,\genByte[7].u_ddr_mc_wr_byte_n_360 }),
        .\dReg_reg[14] ({dReg_35[14],dReg_35[11:10]}),
        .\dReg_reg[14]_0 (\genByte[7].u_ddr_mc_wr_byte_n_11 ),
        .\dReg_reg[15] ({dReg__0_34[15:14],dReg__0_34[11:10]}),
        .\dReg_reg[15]_0 ({dReg__1_33[15:14],dReg__1_33[11:10]}),
        .\dReg_reg[15]_1 ({dReg__2_32[15:14],dReg__2_32[11:10]}),
        .\dReg_reg[15]_2 ({dReg__3_31[15:14],dReg__3_31[11:10]}),
        .\dReg_reg[15]_3 ({dReg__4_30[15:14],dReg__4_30[11:10]}),
        .\dReg_reg[15]_4 ({dReg__5_29[15:14],dReg__5_29[11:10]}),
        .\dReg_reg[15]_5 ({dReg__6_28[15:14],dReg__6_28[11:10]}),
        .\dReg_reg[15]_6 ({dReg__7_27[15:14],dReg__7_27[11:10]}));
  ddr4_0_ddr4_v2_2_17_cal_wr_byte_31 \genByte[5].u_ddr_mc_wr_byte 
       (.D({dReg0_out_54[15],dReg0_out_54[13:12],\dReg_reg[9]_44 ,dReg0_out_54[7:2]}),
        .DMOut(DMOut[47:46]),
        .DQOut({DQOut[383:382],DQOut[375:374],DQOut[367:366],DQOut[359:358],DQOut[351:350],DQOut[343:342],DQOut[335:334],DQOut[326]}),
        .Q({dReg_44[15],dReg_44[13:12],ch0_mcal_DQOut[327:320]}),
        .\dReg_reg[10] (\dReg_reg[10] ),
        .\dReg_reg[10]_0 (\dReg_reg[10]_45 ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_46 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_47 ),
        .\dReg_reg[10]_3 (\dReg_reg[10]_48 ),
        .\dReg_reg[10]_4 (\dReg_reg[10]_49 ),
        .\dReg_reg[10]_5 (\dReg_reg[10]_50 ),
        .\dReg_reg[10]_6 (\dReg_reg[10]_51 ),
        .\dReg_reg[10]_7 (\dReg_reg[10]_52 ),
        .\dReg_reg[10]_8 (\dReg_reg[10]_53 ),
        .\dReg_reg[11] (\genByte[1].u_ddr_mc_wr_byte_n_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_44 ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_45 ),
        .\dReg_reg[11]_2 (\dReg_reg[11]_46 ),
        .\dReg_reg[11]_3 (\dReg_reg[11]_47 ),
        .\dReg_reg[11]_4 (\dReg_reg[11]_48 ),
        .\dReg_reg[11]_5 (\dReg_reg[11]_49 ),
        .\dReg_reg[11]_6 (\dReg_reg[11]_50 ),
        .\dReg_reg[11]_7 (\dReg_reg[11]_51 ),
        .\dReg_reg[11]_8 (\dReg_reg[11]_52 ),
        .\dReg_reg[13] ({dReg__0_43[13:12],ch0_mcal_DQOut[335:328]}),
        .\dReg_reg[13]_0 ({dReg__1_42[13:12],ch0_mcal_DQOut[343:336]}),
        .\dReg_reg[13]_1 ({dReg__2_41[13:12],ch0_mcal_DQOut[351:344]}),
        .\dReg_reg[13]_10 ({\genByte[7].u_ddr_mc_wr_byte_n_418 ,\genByte[7].u_ddr_mc_wr_byte_n_419 ,\dReg_reg[9]_48 ,\genByte[7].u_ddr_mc_wr_byte_n_420 ,\genByte[7].u_ddr_mc_wr_byte_n_421 ,\genByte[7].u_ddr_mc_wr_byte_n_422 ,\genByte[7].u_ddr_mc_wr_byte_n_423 ,\genByte[7].u_ddr_mc_wr_byte_n_424 ,\genByte[7].u_ddr_mc_wr_byte_n_425 }),
        .\dReg_reg[13]_11 ({\genByte[7].u_ddr_mc_wr_byte_n_410 ,\genByte[7].u_ddr_mc_wr_byte_n_411 ,\dReg_reg[9]_49 ,\genByte[7].u_ddr_mc_wr_byte_n_412 ,\genByte[7].u_ddr_mc_wr_byte_n_413 ,\genByte[7].u_ddr_mc_wr_byte_n_414 ,\genByte[7].u_ddr_mc_wr_byte_n_415 ,\genByte[7].u_ddr_mc_wr_byte_n_416 ,\genByte[7].u_ddr_mc_wr_byte_n_417 }),
        .\dReg_reg[13]_12 ({\genByte[7].u_ddr_mc_wr_byte_n_402 ,\genByte[7].u_ddr_mc_wr_byte_n_403 ,\dReg_reg[9]_50 ,\genByte[7].u_ddr_mc_wr_byte_n_404 ,\genByte[7].u_ddr_mc_wr_byte_n_405 ,\genByte[7].u_ddr_mc_wr_byte_n_406 ,\genByte[7].u_ddr_mc_wr_byte_n_407 ,\genByte[7].u_ddr_mc_wr_byte_n_408 ,\genByte[7].u_ddr_mc_wr_byte_n_409 }),
        .\dReg_reg[13]_13 ({\genByte[7].u_ddr_mc_wr_byte_n_394 ,\genByte[7].u_ddr_mc_wr_byte_n_395 ,\dReg_reg[9]_51 ,\genByte[7].u_ddr_mc_wr_byte_n_396 ,\genByte[7].u_ddr_mc_wr_byte_n_397 ,\genByte[7].u_ddr_mc_wr_byte_n_398 ,\genByte[7].u_ddr_mc_wr_byte_n_399 ,\genByte[7].u_ddr_mc_wr_byte_n_400 ,\genByte[7].u_ddr_mc_wr_byte_n_401 }),
        .\dReg_reg[13]_14 ({\genByte[7].u_ddr_mc_wr_byte_n_386 ,\genByte[7].u_ddr_mc_wr_byte_n_387 ,\dReg_reg[9]_52 ,\genByte[7].u_ddr_mc_wr_byte_n_388 ,\genByte[7].u_ddr_mc_wr_byte_n_389 ,\genByte[7].u_ddr_mc_wr_byte_n_390 ,\genByte[7].u_ddr_mc_wr_byte_n_391 ,\genByte[7].u_ddr_mc_wr_byte_n_392 ,\genByte[7].u_ddr_mc_wr_byte_n_393 }),
        .\dReg_reg[13]_2 ({dReg__3_40[13:12],ch0_mcal_DQOut[359:352]}),
        .\dReg_reg[13]_3 ({dReg__4_39[13:12],ch0_mcal_DQOut[367:360]}),
        .\dReg_reg[13]_4 ({dReg__5_38[13:12],ch0_mcal_DQOut[375:368]}),
        .\dReg_reg[13]_5 ({dReg__6_37[13:12],ch0_mcal_DQOut[383:376]}),
        .\dReg_reg[13]_6 ({dReg__7_36[13:12],ch0_mcal_DMOut_n[47:40]}),
        .\dReg_reg[13]_7 ({\genByte[7].u_ddr_mc_wr_byte_n_442 ,\genByte[7].u_ddr_mc_wr_byte_n_443 ,\dReg_reg[9]_45 ,\genByte[7].u_ddr_mc_wr_byte_n_444 ,\genByte[7].u_ddr_mc_wr_byte_n_445 ,\genByte[7].u_ddr_mc_wr_byte_n_446 ,\genByte[7].u_ddr_mc_wr_byte_n_447 ,\genByte[7].u_ddr_mc_wr_byte_n_448 ,\genByte[7].u_ddr_mc_wr_byte_n_449 }),
        .\dReg_reg[13]_8 ({\genByte[7].u_ddr_mc_wr_byte_n_434 ,\genByte[7].u_ddr_mc_wr_byte_n_435 ,\dReg_reg[9]_46 ,\genByte[7].u_ddr_mc_wr_byte_n_436 ,\genByte[7].u_ddr_mc_wr_byte_n_437 ,\genByte[7].u_ddr_mc_wr_byte_n_438 ,\genByte[7].u_ddr_mc_wr_byte_n_439 ,\genByte[7].u_ddr_mc_wr_byte_n_440 ,\genByte[7].u_ddr_mc_wr_byte_n_441 }),
        .\dReg_reg[13]_9 ({\genByte[7].u_ddr_mc_wr_byte_n_426 ,\genByte[7].u_ddr_mc_wr_byte_n_427 ,\dReg_reg[9]_47 ,\genByte[7].u_ddr_mc_wr_byte_n_428 ,\genByte[7].u_ddr_mc_wr_byte_n_429 ,\genByte[7].u_ddr_mc_wr_byte_n_430 ,\genByte[7].u_ddr_mc_wr_byte_n_431 ,\genByte[7].u_ddr_mc_wr_byte_n_432 ,\genByte[7].u_ddr_mc_wr_byte_n_433 }),
        .\dReg_reg[14] ({dReg_44[14],dReg_44[11:10]}),
        .\dReg_reg[14]_0 (\genByte[7].u_ddr_mc_wr_byte_n_11 ),
        .\dReg_reg[15] ({dReg__0_43[15:14],dReg__0_43[11:10]}),
        .\dReg_reg[15]_0 ({dReg__1_42[15:14],dReg__1_42[11:10]}),
        .\dReg_reg[15]_1 ({dReg__2_41[15:14],dReg__2_41[11:10]}),
        .\dReg_reg[15]_2 ({dReg__3_40[15:14],dReg__3_40[11:10]}),
        .\dReg_reg[15]_3 ({dReg__4_39[15:14],dReg__4_39[11:10]}),
        .\dReg_reg[15]_4 ({dReg__5_38[15:14],dReg__5_38[11:10]}),
        .\dReg_reg[15]_5 ({dReg__6_37[15:14],dReg__6_37[11:10]}),
        .\dReg_reg[15]_6 ({dReg__7_36[15:14],dReg__7_36[11:10]}));
  ddr4_0_ddr4_v2_2_17_cal_wr_byte_32 \genByte[6].u_ddr_mc_wr_byte 
       (.D({dReg0_out[15],dReg0_out[13:12],\dReg_reg[9]_53 ,dReg0_out[7:2]}),
        .DMOut(DMOut[55:54]),
        .DQOut({DQOut[447:446],DQOut[439:438],DQOut[431:430],DQOut[423:422],DQOut[415:414],DQOut[407:406],DQOut[399:398],DQOut[390]}),
        .Q({dReg_53[15],dReg_53[13:12],ch0_mcal_DQOut[391:384]}),
        .\dReg_reg[10] (\dReg_reg[10] ),
        .\dReg_reg[10]_0 (\dReg_reg[10]_54 ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_55 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_56 ),
        .\dReg_reg[10]_3 (\dReg_reg[10]_57 ),
        .\dReg_reg[10]_4 (\dReg_reg[10]_58 ),
        .\dReg_reg[10]_5 (\dReg_reg[10]_59 ),
        .\dReg_reg[10]_6 (\dReg_reg[10]_60 ),
        .\dReg_reg[10]_7 (\dReg_reg[10]_61 ),
        .\dReg_reg[10]_8 (\dReg_reg[10]_62 ),
        .\dReg_reg[11] (\genByte[1].u_ddr_mc_wr_byte_n_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_53 ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_54 ),
        .\dReg_reg[11]_2 (\dReg_reg[11]_55 ),
        .\dReg_reg[11]_3 (\dReg_reg[11]_56 ),
        .\dReg_reg[11]_4 (\dReg_reg[11]_57 ),
        .\dReg_reg[11]_5 (\dReg_reg[11]_58 ),
        .\dReg_reg[11]_6 (\dReg_reg[11]_59 ),
        .\dReg_reg[11]_7 (\dReg_reg[11]_60 ),
        .\dReg_reg[11]_8 (\dReg_reg[11]_61 ),
        .\dReg_reg[13] ({dReg__0_52[13:12],ch0_mcal_DQOut[399:392]}),
        .\dReg_reg[13]_0 ({dReg__1_51[13:12],ch0_mcal_DQOut[407:400]}),
        .\dReg_reg[13]_1 ({dReg__2_50[13:12],ch0_mcal_DQOut[415:408]}),
        .\dReg_reg[13]_10 ({\genByte[7].u_ddr_mc_wr_byte_n_491 ,\genByte[7].u_ddr_mc_wr_byte_n_492 ,\dReg_reg[9]_57 ,\genByte[7].u_ddr_mc_wr_byte_n_493 ,\genByte[7].u_ddr_mc_wr_byte_n_494 ,\genByte[7].u_ddr_mc_wr_byte_n_495 ,\genByte[7].u_ddr_mc_wr_byte_n_496 ,\genByte[7].u_ddr_mc_wr_byte_n_497 ,\genByte[7].u_ddr_mc_wr_byte_n_498 }),
        .\dReg_reg[13]_11 ({\genByte[7].u_ddr_mc_wr_byte_n_483 ,\genByte[7].u_ddr_mc_wr_byte_n_484 ,\dReg_reg[9]_58 ,\genByte[7].u_ddr_mc_wr_byte_n_485 ,\genByte[7].u_ddr_mc_wr_byte_n_486 ,\genByte[7].u_ddr_mc_wr_byte_n_487 ,\genByte[7].u_ddr_mc_wr_byte_n_488 ,\genByte[7].u_ddr_mc_wr_byte_n_489 ,\genByte[7].u_ddr_mc_wr_byte_n_490 }),
        .\dReg_reg[13]_12 ({\genByte[7].u_ddr_mc_wr_byte_n_475 ,\genByte[7].u_ddr_mc_wr_byte_n_476 ,\dReg_reg[9]_59 ,\genByte[7].u_ddr_mc_wr_byte_n_477 ,\genByte[7].u_ddr_mc_wr_byte_n_478 ,\genByte[7].u_ddr_mc_wr_byte_n_479 ,\genByte[7].u_ddr_mc_wr_byte_n_480 ,\genByte[7].u_ddr_mc_wr_byte_n_481 ,\genByte[7].u_ddr_mc_wr_byte_n_482 }),
        .\dReg_reg[13]_13 ({\genByte[7].u_ddr_mc_wr_byte_n_467 ,\genByte[7].u_ddr_mc_wr_byte_n_468 ,\dReg_reg[9]_60 ,\genByte[7].u_ddr_mc_wr_byte_n_469 ,\genByte[7].u_ddr_mc_wr_byte_n_470 ,\genByte[7].u_ddr_mc_wr_byte_n_471 ,\genByte[7].u_ddr_mc_wr_byte_n_472 ,\genByte[7].u_ddr_mc_wr_byte_n_473 ,\genByte[7].u_ddr_mc_wr_byte_n_474 }),
        .\dReg_reg[13]_14 ({\genByte[7].u_ddr_mc_wr_byte_n_459 ,\genByte[7].u_ddr_mc_wr_byte_n_460 ,\dReg_reg[9]_61 ,\genByte[7].u_ddr_mc_wr_byte_n_461 ,\genByte[7].u_ddr_mc_wr_byte_n_462 ,\genByte[7].u_ddr_mc_wr_byte_n_463 ,\genByte[7].u_ddr_mc_wr_byte_n_464 ,\genByte[7].u_ddr_mc_wr_byte_n_465 ,\genByte[7].u_ddr_mc_wr_byte_n_466 }),
        .\dReg_reg[13]_2 ({dReg__3_49[13:12],ch0_mcal_DQOut[423:416]}),
        .\dReg_reg[13]_3 ({dReg__4_48[13:12],ch0_mcal_DQOut[431:424]}),
        .\dReg_reg[13]_4 ({dReg__5_47[13:12],ch0_mcal_DQOut[439:432]}),
        .\dReg_reg[13]_5 ({dReg__6_46[13:12],ch0_mcal_DQOut[447:440]}),
        .\dReg_reg[13]_6 ({dReg__7_45[13:12],ch0_mcal_DMOut_n[55:48]}),
        .\dReg_reg[13]_7 ({\genByte[7].u_ddr_mc_wr_byte_n_515 ,\genByte[7].u_ddr_mc_wr_byte_n_516 ,\dReg_reg[9]_54 ,\genByte[7].u_ddr_mc_wr_byte_n_517 ,\genByte[7].u_ddr_mc_wr_byte_n_518 ,\genByte[7].u_ddr_mc_wr_byte_n_519 ,\genByte[7].u_ddr_mc_wr_byte_n_520 ,\genByte[7].u_ddr_mc_wr_byte_n_521 ,\genByte[7].u_ddr_mc_wr_byte_n_522 }),
        .\dReg_reg[13]_8 ({\genByte[7].u_ddr_mc_wr_byte_n_507 ,\genByte[7].u_ddr_mc_wr_byte_n_508 ,\dReg_reg[9]_55 ,\genByte[7].u_ddr_mc_wr_byte_n_509 ,\genByte[7].u_ddr_mc_wr_byte_n_510 ,\genByte[7].u_ddr_mc_wr_byte_n_511 ,\genByte[7].u_ddr_mc_wr_byte_n_512 ,\genByte[7].u_ddr_mc_wr_byte_n_513 ,\genByte[7].u_ddr_mc_wr_byte_n_514 }),
        .\dReg_reg[13]_9 ({\genByte[7].u_ddr_mc_wr_byte_n_499 ,\genByte[7].u_ddr_mc_wr_byte_n_500 ,\dReg_reg[9]_56 ,\genByte[7].u_ddr_mc_wr_byte_n_501 ,\genByte[7].u_ddr_mc_wr_byte_n_502 ,\genByte[7].u_ddr_mc_wr_byte_n_503 ,\genByte[7].u_ddr_mc_wr_byte_n_504 ,\genByte[7].u_ddr_mc_wr_byte_n_505 ,\genByte[7].u_ddr_mc_wr_byte_n_506 }),
        .\dReg_reg[14] ({dReg_53[14],dReg_53[11:10]}),
        .\dReg_reg[14]_0 (\genByte[7].u_ddr_mc_wr_byte_n_11 ),
        .\dReg_reg[15] ({dReg__0_52[15:14],dReg__0_52[11:10]}),
        .\dReg_reg[15]_0 ({dReg__1_51[15:14],dReg__1_51[11:10]}),
        .\dReg_reg[15]_1 ({dReg__2_50[15:14],dReg__2_50[11:10]}),
        .\dReg_reg[15]_2 ({dReg__3_49[15:14],dReg__3_49[11:10]}),
        .\dReg_reg[15]_3 ({dReg__4_48[15:14],dReg__4_48[11:10]}),
        .\dReg_reg[15]_4 ({dReg__5_47[15:14],dReg__5_47[11:10]}),
        .\dReg_reg[15]_5 ({dReg__6_46[15:14],dReg__6_46[11:10]}),
        .\dReg_reg[15]_6 ({dReg__7_45[15:14],dReg__7_45[11:10]}));
  ddr4_0_ddr4_v2_2_17_cal_wr_byte_33 \genByte[7].u_ddr_mc_wr_byte 
       (.D({dReg0_out_59[15],dReg0_out_59[13:12],dReg0_out_59[7:2]}),
        .DMOut(DMOut),
        .DQOut(DQOut),
        .ch0_mcal_DMOut_n(ch0_mcal_DMOut_n[63:56]),
        .ch0_mcal_DQOut(ch0_mcal_DQOut[511:448]),
        .dReg(dReg),
        .dReg_0(dReg_8),
        .dReg_18(dReg_26),
        .dReg_27(dReg_35),
        .dReg_36(dReg_44),
        .dReg_45(dReg_53),
        .dReg_9(dReg_17),
        .dReg__0(dReg__0),
        .dReg__0_1(dReg__0_7),
        .dReg__0_10(dReg__0_16),
        .dReg__0_19(dReg__0_25),
        .dReg__0_28(dReg__0_34),
        .dReg__0_37(dReg__0_43),
        .dReg__0_46(dReg__0_52),
        .dReg__1(dReg__1),
        .dReg__1_11(dReg__1_15),
        .dReg__1_2(dReg__1_6),
        .dReg__1_20(dReg__1_24),
        .dReg__1_29(dReg__1_33),
        .dReg__1_38(dReg__1_42),
        .dReg__1_47(dReg__1_51),
        .dReg__2(dReg__2),
        .dReg__2_12(dReg__2_14),
        .dReg__2_21(dReg__2_23),
        .dReg__2_3(dReg__2_5),
        .dReg__2_30(dReg__2_32),
        .dReg__2_39(dReg__2_41),
        .dReg__2_48(dReg__2_50),
        .dReg__3(dReg__3),
        .dReg__3_13(dReg__3_13),
        .dReg__3_22(dReg__3_22),
        .dReg__3_31(dReg__3_31),
        .dReg__3_4(dReg__3_4),
        .dReg__3_40(dReg__3_40),
        .dReg__3_49(dReg__3_49),
        .dReg__4(dReg__4),
        .dReg__4_14(dReg__4_12),
        .dReg__4_23(dReg__4_21),
        .dReg__4_32(dReg__4_30),
        .dReg__4_41(dReg__4_39),
        .dReg__4_5(dReg__4_3),
        .dReg__4_50(dReg__4_48),
        .dReg__5(dReg__5),
        .dReg__5_15(dReg__5_11),
        .dReg__5_24(dReg__5_20),
        .dReg__5_33(dReg__5_29),
        .dReg__5_42(dReg__5_38),
        .dReg__5_51(dReg__5_47),
        .dReg__5_6(dReg__5_2),
        .dReg__6(dReg__6),
        .dReg__6_16(dReg__6_10),
        .dReg__6_25(dReg__6_19),
        .dReg__6_34(dReg__6_28),
        .dReg__6_43(dReg__6_37),
        .dReg__6_52(dReg__6_46),
        .dReg__6_7(dReg__6_1),
        .dReg__7(dReg__7),
        .dReg__7_17(dReg__7_9),
        .dReg__7_26(dReg__7_18),
        .dReg__7_35(dReg__7_27),
        .dReg__7_44(dReg__7_36),
        .dReg__7_53(dReg__7_45),
        .dReg__7_8(dReg__7_0),
        .\dReg_reg[10] (\dReg_reg[10] ),
        .\dReg_reg[10]_0 (\dReg_reg[10]_63 ),
        .\dReg_reg[10]_1 (\dReg_reg[10]_64 ),
        .\dReg_reg[10]_2 (\dReg_reg[10]_65 ),
        .\dReg_reg[10]_3 (\dReg_reg[10]_66 ),
        .\dReg_reg[10]_4 (\dReg_reg[10]_67 ),
        .\dReg_reg[10]_5 (\dReg_reg[10]_68 ),
        .\dReg_reg[10]_6 (\dReg_reg[10]_69 ),
        .\dReg_reg[10]_7 (\dReg_reg[10]_70 ),
        .\dReg_reg[10]_8 (\dReg_reg[10]_71 ),
        .\dReg_reg[11] (\genByte[1].u_ddr_mc_wr_byte_n_0 ),
        .\dReg_reg[11]_0 (\dReg_reg[11]_62 ),
        .\dReg_reg[11]_1 (\dReg_reg[11]_63 ),
        .\dReg_reg[11]_2 (\dReg_reg[11]_64 ),
        .\dReg_reg[11]_3 (\dReg_reg[11]_65 ),
        .\dReg_reg[11]_4 (\dReg_reg[11]_66 ),
        .\dReg_reg[11]_5 (\dReg_reg[11]_67 ),
        .\dReg_reg[11]_6 (\dReg_reg[11]_68 ),
        .\dReg_reg[11]_7 (\dReg_reg[11]_69 ),
        .\dReg_reg[11]_8 (\dReg_reg[11]_70 ),
        .\dReg_reg[6] (wrDataVal_reg_0),
        .\dReg_reg[6]_0 (\dReg_reg[6] ),
        .\dReg_reg[6]_1 (\dReg_reg[6]_0 ),
        .\dReg_reg[6]_10 (\dReg_reg[6]_9 ),
        .\dReg_reg[6]_11 (\dReg_reg[6]_10 ),
        .\dReg_reg[6]_12 (\dReg_reg[6]_11 ),
        .\dReg_reg[6]_13 (\dReg_reg[6]_12 ),
        .\dReg_reg[6]_14 (\dReg_reg[6]_13 ),
        .\dReg_reg[6]_15 (\dReg_reg[6]_14 ),
        .\dReg_reg[6]_16 (\dReg_reg[6]_15 ),
        .\dReg_reg[6]_17 (\dReg_reg[6]_16 ),
        .\dReg_reg[6]_18 (\dReg_reg[6]_17 ),
        .\dReg_reg[6]_19 (\dReg_reg[6]_18 ),
        .\dReg_reg[6]_2 (\dReg_reg[6]_1 ),
        .\dReg_reg[6]_20 (\dReg_reg[6]_19 ),
        .\dReg_reg[6]_21 (\dReg_reg[6]_20 ),
        .\dReg_reg[6]_22 (\dReg_reg[6]_21 ),
        .\dReg_reg[6]_23 (\dReg_reg[6]_22 ),
        .\dReg_reg[6]_24 (\dReg_reg[6]_23 ),
        .\dReg_reg[6]_25 (\dReg_reg[6]_24 ),
        .\dReg_reg[6]_26 (\dReg_reg[6]_25 ),
        .\dReg_reg[6]_27 (\dReg_reg[6]_26 ),
        .\dReg_reg[6]_28 (\dReg_reg[6]_27 ),
        .\dReg_reg[6]_29 (\dReg_reg[6]_28 ),
        .\dReg_reg[6]_3 (\dReg_reg[6]_2 ),
        .\dReg_reg[6]_30 (\dReg_reg[6]_29 ),
        .\dReg_reg[6]_31 (\dReg_reg[6]_30 ),
        .\dReg_reg[6]_32 (\dReg_reg[6]_31 ),
        .\dReg_reg[6]_33 (\dReg_reg[6]_32 ),
        .\dReg_reg[6]_34 (\dReg_reg[6]_33 ),
        .\dReg_reg[6]_35 (\dReg_reg[6]_34 ),
        .\dReg_reg[6]_36 (\dReg_reg[6]_35 ),
        .\dReg_reg[6]_37 (\dReg_reg[6]_36 ),
        .\dReg_reg[6]_38 (\dReg_reg[6]_37 ),
        .\dReg_reg[6]_39 (\dReg_reg[6]_38 ),
        .\dReg_reg[6]_4 (\dReg_reg[6]_3 ),
        .\dReg_reg[6]_40 (\dReg_reg[6]_39 ),
        .\dReg_reg[6]_41 (\dReg_reg[6]_40 ),
        .\dReg_reg[6]_42 (\dReg_reg[6]_41 ),
        .\dReg_reg[6]_43 (\dReg_reg[6]_42 ),
        .\dReg_reg[6]_44 (\dReg_reg[6]_43 ),
        .\dReg_reg[6]_45 (\dReg_reg[6]_44 ),
        .\dReg_reg[6]_46 (\dReg_reg[6]_45 ),
        .\dReg_reg[6]_47 (\dReg_reg[6]_46 ),
        .\dReg_reg[6]_48 (\dReg_reg[6]_47 ),
        .\dReg_reg[6]_49 (\dReg_reg[6]_48 ),
        .\dReg_reg[6]_5 (\dReg_reg[6]_4 ),
        .\dReg_reg[6]_50 (\dReg_reg[6]_49 ),
        .\dReg_reg[6]_51 (\dReg_reg[6]_50 ),
        .\dReg_reg[6]_52 (\dReg_reg[6]_51 ),
        .\dReg_reg[6]_53 (\dReg_reg[6]_52 ),
        .\dReg_reg[6]_54 (\dReg_reg[6]_53 ),
        .\dReg_reg[6]_55 (\dReg_reg[6]_54 ),
        .\dReg_reg[6]_56 (\dReg_reg[6]_55 ),
        .\dReg_reg[6]_57 (\dReg_reg[6]_56 ),
        .\dReg_reg[6]_58 (\dReg_reg[6]_57 ),
        .\dReg_reg[6]_59 (\dReg_reg[6]_58 ),
        .\dReg_reg[6]_6 (\dReg_reg[6]_5 ),
        .\dReg_reg[6]_60 (\dReg_reg[6]_59 ),
        .\dReg_reg[6]_61 (\dReg_reg[6]_60 ),
        .\dReg_reg[6]_62 (\dReg_reg[6]_61 ),
        .\dReg_reg[6]_63 (\dReg_reg[6]_62 ),
        .\dReg_reg[6]_64 (\dReg_reg[6]_63 ),
        .\dReg_reg[6]_65 (\dReg_reg[6]_64 ),
        .\dReg_reg[6]_66 (\dReg_reg[6]_65 ),
        .\dReg_reg[6]_67 (\dReg_reg[6]_66 ),
        .\dReg_reg[6]_68 (\dReg_reg[6]_67 ),
        .\dReg_reg[6]_69 (\dReg_reg[6]_68 ),
        .\dReg_reg[6]_7 (\dReg_reg[6]_6 ),
        .\dReg_reg[6]_70 (\dReg_reg[6]_69 ),
        .\dReg_reg[6]_71 (\dReg_reg[6]_70 ),
        .\dReg_reg[6]_8 (\dReg_reg[6]_7 ),
        .\dReg_reg[6]_9 (\dReg_reg[6]_8 ),
        .\dReg_reg[7] (\dReg_reg[7] ),
        .\dReg_reg[7]_0 (\dReg_reg[7]_0 ),
        .\dReg_reg[7]_1 (\dReg_reg[7]_1 ),
        .\dReg_reg[7]_10 (\dReg_reg[7]_10 ),
        .\dReg_reg[7]_11 (\dReg_reg[7]_11 ),
        .\dReg_reg[7]_12 (\dReg_reg[7]_12 ),
        .\dReg_reg[7]_13 (\dReg_reg[7]_13 ),
        .\dReg_reg[7]_14 (\dReg_reg[7]_14 ),
        .\dReg_reg[7]_15 (\dReg_reg[7]_15 ),
        .\dReg_reg[7]_16 (\dReg_reg[7]_16 ),
        .\dReg_reg[7]_17 (\dReg_reg[7]_17 ),
        .\dReg_reg[7]_18 (\dReg_reg[7]_18 ),
        .\dReg_reg[7]_19 (\dReg_reg[7]_19 ),
        .\dReg_reg[7]_2 (\dReg_reg[7]_2 ),
        .\dReg_reg[7]_20 (\dReg_reg[7]_20 ),
        .\dReg_reg[7]_21 (\dReg_reg[7]_21 ),
        .\dReg_reg[7]_22 (\dReg_reg[7]_22 ),
        .\dReg_reg[7]_23 (\dReg_reg[7]_23 ),
        .\dReg_reg[7]_24 (\dReg_reg[7]_24 ),
        .\dReg_reg[7]_25 (\dReg_reg[7]_25 ),
        .\dReg_reg[7]_26 (\dReg_reg[7]_26 ),
        .\dReg_reg[7]_27 (\dReg_reg[7]_27 ),
        .\dReg_reg[7]_28 (\dReg_reg[7]_28 ),
        .\dReg_reg[7]_29 (\dReg_reg[7]_29 ),
        .\dReg_reg[7]_3 (\dReg_reg[7]_3 ),
        .\dReg_reg[7]_30 (\dReg_reg[7]_30 ),
        .\dReg_reg[7]_31 (\dReg_reg[7]_31 ),
        .\dReg_reg[7]_32 (\dReg_reg[7]_32 ),
        .\dReg_reg[7]_33 (\dReg_reg[7]_33 ),
        .\dReg_reg[7]_34 (\dReg_reg[7]_34 ),
        .\dReg_reg[7]_35 (\dReg_reg[7]_35 ),
        .\dReg_reg[7]_36 (\dReg_reg[7]_36 ),
        .\dReg_reg[7]_37 (\dReg_reg[7]_37 ),
        .\dReg_reg[7]_38 (\dReg_reg[7]_38 ),
        .\dReg_reg[7]_39 (\dReg_reg[7]_39 ),
        .\dReg_reg[7]_4 (\dReg_reg[7]_4 ),
        .\dReg_reg[7]_40 (\dReg_reg[7]_40 ),
        .\dReg_reg[7]_41 (\dReg_reg[7]_41 ),
        .\dReg_reg[7]_42 (\dReg_reg[7]_42 ),
        .\dReg_reg[7]_43 (\dReg_reg[7]_43 ),
        .\dReg_reg[7]_44 (\dReg_reg[7]_44 ),
        .\dReg_reg[7]_45 (\dReg_reg[7]_45 ),
        .\dReg_reg[7]_46 (\dReg_reg[7]_46 ),
        .\dReg_reg[7]_47 (\dReg_reg[7]_47 ),
        .\dReg_reg[7]_48 (\dReg_reg[7]_48 ),
        .\dReg_reg[7]_49 (\dReg_reg[7]_49 ),
        .\dReg_reg[7]_5 (\dReg_reg[7]_5 ),
        .\dReg_reg[7]_50 (\dReg_reg[7]_50 ),
        .\dReg_reg[7]_51 (\dReg_reg[7]_51 ),
        .\dReg_reg[7]_52 (\dReg_reg[7]_52 ),
        .\dReg_reg[7]_53 (\dReg_reg[7]_53 ),
        .\dReg_reg[7]_54 (\dReg_reg[7]_54 ),
        .\dReg_reg[7]_55 (\dReg_reg[7]_55 ),
        .\dReg_reg[7]_56 (\dReg_reg[7]_56 ),
        .\dReg_reg[7]_57 (\dReg_reg[7]_57 ),
        .\dReg_reg[7]_58 (\dReg_reg[7]_58 ),
        .\dReg_reg[7]_59 (\dReg_reg[7]_59 ),
        .\dReg_reg[7]_6 (\dReg_reg[7]_6 ),
        .\dReg_reg[7]_60 (\dReg_reg[7]_60 ),
        .\dReg_reg[7]_61 (\dReg_reg[7]_61 ),
        .\dReg_reg[7]_62 (\dReg_reg[7]_62 ),
        .\dReg_reg[7]_63 (\dReg_reg[7]_63 ),
        .\dReg_reg[7]_64 (\dReg_reg[7]_64 ),
        .\dReg_reg[7]_65 (\dReg_reg[7]_65 ),
        .\dReg_reg[7]_66 (\dReg_reg[7]_66 ),
        .\dReg_reg[7]_67 (\dReg_reg[7]_67 ),
        .\dReg_reg[7]_68 (\dReg_reg[7]_68 ),
        .\dReg_reg[7]_69 (\dReg_reg[7]_69 ),
        .\dReg_reg[7]_7 (\dReg_reg[7]_7 ),
        .\dReg_reg[7]_70 (\dReg_reg[7]_70 ),
        .\dReg_reg[7]_8 (\dReg_reg[7]_8 ),
        .\dReg_reg[7]_9 (\dReg_reg[7]_9 ),
        .\dReg_reg[9] (\dReg_reg[9]_62 ),
        .\dReg_reg[9]_0 (\dReg_reg[9]_63 ),
        .\dReg_reg[9]_1 (\dReg_reg[9]_64 ),
        .\dReg_reg[9]_2 (\dReg_reg[9]_65 ),
        .\dReg_reg[9]_3 (\dReg_reg[9]_66 ),
        .\dReg_reg[9]_4 (\dReg_reg[9]_67 ),
        .\dReg_reg[9]_5 (\dReg_reg[9]_68 ),
        .\dReg_reg[9]_6 (\dReg_reg[9]_69 ),
        .\dReg_reg[9]_7 (\dReg_reg[9]_70 ),
        .sel(sel),
        .\wosp_reg[1] (\wosp_reg[1] ),
        .\wosp_reg[1]_0 ({\genByte[7].u_ddr_mc_wr_byte_n_21 ,\genByte[7].u_ddr_mc_wr_byte_n_22 ,\genByte[7].u_ddr_mc_wr_byte_n_23 ,\genByte[7].u_ddr_mc_wr_byte_n_24 ,\genByte[7].u_ddr_mc_wr_byte_n_25 ,\genByte[7].u_ddr_mc_wr_byte_n_26 ,\genByte[7].u_ddr_mc_wr_byte_n_27 ,\genByte[7].u_ddr_mc_wr_byte_n_28 }),
        .\wosp_reg[1]_1 ({\genByte[7].u_ddr_mc_wr_byte_n_29 ,\genByte[7].u_ddr_mc_wr_byte_n_30 ,\genByte[7].u_ddr_mc_wr_byte_n_31 ,\genByte[7].u_ddr_mc_wr_byte_n_32 ,\genByte[7].u_ddr_mc_wr_byte_n_33 ,\genByte[7].u_ddr_mc_wr_byte_n_34 ,\genByte[7].u_ddr_mc_wr_byte_n_35 ,\genByte[7].u_ddr_mc_wr_byte_n_36 }),
        .\wosp_reg[1]_10 ({\genByte[7].u_ddr_mc_wr_byte_n_102 ,\genByte[7].u_ddr_mc_wr_byte_n_103 ,\genByte[7].u_ddr_mc_wr_byte_n_104 ,\genByte[7].u_ddr_mc_wr_byte_n_105 ,\genByte[7].u_ddr_mc_wr_byte_n_106 ,\genByte[7].u_ddr_mc_wr_byte_n_107 ,\genByte[7].u_ddr_mc_wr_byte_n_108 ,\genByte[7].u_ddr_mc_wr_byte_n_109 }),
        .\wosp_reg[1]_11 ({\genByte[7].u_ddr_mc_wr_byte_n_110 ,\genByte[7].u_ddr_mc_wr_byte_n_111 ,\genByte[7].u_ddr_mc_wr_byte_n_112 ,\genByte[7].u_ddr_mc_wr_byte_n_113 ,\genByte[7].u_ddr_mc_wr_byte_n_114 ,\genByte[7].u_ddr_mc_wr_byte_n_115 ,\genByte[7].u_ddr_mc_wr_byte_n_116 ,\genByte[7].u_ddr_mc_wr_byte_n_117 }),
        .\wosp_reg[1]_12 ({\genByte[7].u_ddr_mc_wr_byte_n_118 ,\genByte[7].u_ddr_mc_wr_byte_n_119 ,\genByte[7].u_ddr_mc_wr_byte_n_120 ,\genByte[7].u_ddr_mc_wr_byte_n_121 ,\genByte[7].u_ddr_mc_wr_byte_n_122 ,\genByte[7].u_ddr_mc_wr_byte_n_123 ,\genByte[7].u_ddr_mc_wr_byte_n_124 ,\genByte[7].u_ddr_mc_wr_byte_n_125 }),
        .\wosp_reg[1]_13 ({\genByte[7].u_ddr_mc_wr_byte_n_126 ,\genByte[7].u_ddr_mc_wr_byte_n_127 ,\genByte[7].u_ddr_mc_wr_byte_n_128 ,\genByte[7].u_ddr_mc_wr_byte_n_129 ,\genByte[7].u_ddr_mc_wr_byte_n_130 ,\genByte[7].u_ddr_mc_wr_byte_n_131 ,\genByte[7].u_ddr_mc_wr_byte_n_132 ,\genByte[7].u_ddr_mc_wr_byte_n_133 }),
        .\wosp_reg[1]_14 ({\genByte[7].u_ddr_mc_wr_byte_n_134 ,\genByte[7].u_ddr_mc_wr_byte_n_135 ,\genByte[7].u_ddr_mc_wr_byte_n_136 ,\genByte[7].u_ddr_mc_wr_byte_n_137 ,\genByte[7].u_ddr_mc_wr_byte_n_138 ,\genByte[7].u_ddr_mc_wr_byte_n_139 ,\genByte[7].u_ddr_mc_wr_byte_n_140 ,\genByte[7].u_ddr_mc_wr_byte_n_141 }),
        .\wosp_reg[1]_15 ({\genByte[7].u_ddr_mc_wr_byte_n_142 ,\genByte[7].u_ddr_mc_wr_byte_n_143 ,\genByte[7].u_ddr_mc_wr_byte_n_144 ,\genByte[7].u_ddr_mc_wr_byte_n_145 ,\genByte[7].u_ddr_mc_wr_byte_n_146 ,\genByte[7].u_ddr_mc_wr_byte_n_147 ,\genByte[7].u_ddr_mc_wr_byte_n_148 ,\genByte[7].u_ddr_mc_wr_byte_n_149 }),
        .\wosp_reg[1]_16 ({\genByte[7].u_ddr_mc_wr_byte_n_150 ,\genByte[7].u_ddr_mc_wr_byte_n_151 ,\genByte[7].u_ddr_mc_wr_byte_n_152 ,\genByte[7].u_ddr_mc_wr_byte_n_153 ,\genByte[7].u_ddr_mc_wr_byte_n_154 ,\genByte[7].u_ddr_mc_wr_byte_n_155 ,\genByte[7].u_ddr_mc_wr_byte_n_156 ,\genByte[7].u_ddr_mc_wr_byte_n_157 }),
        .\wosp_reg[1]_17 ({dReg0_out_57[15],dReg0_out_57[13:12],dReg0_out_57[7:2]}),
        .\wosp_reg[1]_18 ({\genByte[7].u_ddr_mc_wr_byte_n_167 ,\genByte[7].u_ddr_mc_wr_byte_n_168 ,\genByte[7].u_ddr_mc_wr_byte_n_169 ,\genByte[7].u_ddr_mc_wr_byte_n_170 ,\genByte[7].u_ddr_mc_wr_byte_n_171 ,\genByte[7].u_ddr_mc_wr_byte_n_172 ,\genByte[7].u_ddr_mc_wr_byte_n_173 ,\genByte[7].u_ddr_mc_wr_byte_n_174 }),
        .\wosp_reg[1]_19 ({\genByte[7].u_ddr_mc_wr_byte_n_175 ,\genByte[7].u_ddr_mc_wr_byte_n_176 ,\genByte[7].u_ddr_mc_wr_byte_n_177 ,\genByte[7].u_ddr_mc_wr_byte_n_178 ,\genByte[7].u_ddr_mc_wr_byte_n_179 ,\genByte[7].u_ddr_mc_wr_byte_n_180 ,\genByte[7].u_ddr_mc_wr_byte_n_181 ,\genByte[7].u_ddr_mc_wr_byte_n_182 }),
        .\wosp_reg[1]_2 ({\genByte[7].u_ddr_mc_wr_byte_n_37 ,\genByte[7].u_ddr_mc_wr_byte_n_38 ,\genByte[7].u_ddr_mc_wr_byte_n_39 ,\genByte[7].u_ddr_mc_wr_byte_n_40 ,\genByte[7].u_ddr_mc_wr_byte_n_41 ,\genByte[7].u_ddr_mc_wr_byte_n_42 ,\genByte[7].u_ddr_mc_wr_byte_n_43 ,\genByte[7].u_ddr_mc_wr_byte_n_44 }),
        .\wosp_reg[1]_20 ({\genByte[7].u_ddr_mc_wr_byte_n_183 ,\genByte[7].u_ddr_mc_wr_byte_n_184 ,\genByte[7].u_ddr_mc_wr_byte_n_185 ,\genByte[7].u_ddr_mc_wr_byte_n_186 ,\genByte[7].u_ddr_mc_wr_byte_n_187 ,\genByte[7].u_ddr_mc_wr_byte_n_188 ,\genByte[7].u_ddr_mc_wr_byte_n_189 ,\genByte[7].u_ddr_mc_wr_byte_n_190 }),
        .\wosp_reg[1]_21 ({\genByte[7].u_ddr_mc_wr_byte_n_191 ,\genByte[7].u_ddr_mc_wr_byte_n_192 ,\genByte[7].u_ddr_mc_wr_byte_n_193 ,\genByte[7].u_ddr_mc_wr_byte_n_194 ,\genByte[7].u_ddr_mc_wr_byte_n_195 ,\genByte[7].u_ddr_mc_wr_byte_n_196 ,\genByte[7].u_ddr_mc_wr_byte_n_197 ,\genByte[7].u_ddr_mc_wr_byte_n_198 }),
        .\wosp_reg[1]_22 ({\genByte[7].u_ddr_mc_wr_byte_n_199 ,\genByte[7].u_ddr_mc_wr_byte_n_200 ,\genByte[7].u_ddr_mc_wr_byte_n_201 ,\genByte[7].u_ddr_mc_wr_byte_n_202 ,\genByte[7].u_ddr_mc_wr_byte_n_203 ,\genByte[7].u_ddr_mc_wr_byte_n_204 ,\genByte[7].u_ddr_mc_wr_byte_n_205 ,\genByte[7].u_ddr_mc_wr_byte_n_206 }),
        .\wosp_reg[1]_23 ({\genByte[7].u_ddr_mc_wr_byte_n_207 ,\genByte[7].u_ddr_mc_wr_byte_n_208 ,\genByte[7].u_ddr_mc_wr_byte_n_209 ,\genByte[7].u_ddr_mc_wr_byte_n_210 ,\genByte[7].u_ddr_mc_wr_byte_n_211 ,\genByte[7].u_ddr_mc_wr_byte_n_212 ,\genByte[7].u_ddr_mc_wr_byte_n_213 ,\genByte[7].u_ddr_mc_wr_byte_n_214 }),
        .\wosp_reg[1]_24 ({\genByte[7].u_ddr_mc_wr_byte_n_215 ,\genByte[7].u_ddr_mc_wr_byte_n_216 ,\genByte[7].u_ddr_mc_wr_byte_n_217 ,\genByte[7].u_ddr_mc_wr_byte_n_218 ,\genByte[7].u_ddr_mc_wr_byte_n_219 ,\genByte[7].u_ddr_mc_wr_byte_n_220 ,\genByte[7].u_ddr_mc_wr_byte_n_221 ,\genByte[7].u_ddr_mc_wr_byte_n_222 }),
        .\wosp_reg[1]_25 ({\genByte[7].u_ddr_mc_wr_byte_n_223 ,\genByte[7].u_ddr_mc_wr_byte_n_224 ,\genByte[7].u_ddr_mc_wr_byte_n_225 ,\genByte[7].u_ddr_mc_wr_byte_n_226 ,\genByte[7].u_ddr_mc_wr_byte_n_227 ,\genByte[7].u_ddr_mc_wr_byte_n_228 ,\genByte[7].u_ddr_mc_wr_byte_n_229 ,\genByte[7].u_ddr_mc_wr_byte_n_230 }),
        .\wosp_reg[1]_26 ({dReg0_out_56[15],dReg0_out_56[13:12],dReg0_out_56[7:2]}),
        .\wosp_reg[1]_27 ({\genByte[7].u_ddr_mc_wr_byte_n_240 ,\genByte[7].u_ddr_mc_wr_byte_n_241 ,\genByte[7].u_ddr_mc_wr_byte_n_242 ,\genByte[7].u_ddr_mc_wr_byte_n_243 ,\genByte[7].u_ddr_mc_wr_byte_n_244 ,\genByte[7].u_ddr_mc_wr_byte_n_245 ,\genByte[7].u_ddr_mc_wr_byte_n_246 ,\genByte[7].u_ddr_mc_wr_byte_n_247 }),
        .\wosp_reg[1]_28 ({\genByte[7].u_ddr_mc_wr_byte_n_248 ,\genByte[7].u_ddr_mc_wr_byte_n_249 ,\genByte[7].u_ddr_mc_wr_byte_n_250 ,\genByte[7].u_ddr_mc_wr_byte_n_251 ,\genByte[7].u_ddr_mc_wr_byte_n_252 ,\genByte[7].u_ddr_mc_wr_byte_n_253 ,\genByte[7].u_ddr_mc_wr_byte_n_254 ,\genByte[7].u_ddr_mc_wr_byte_n_255 }),
        .\wosp_reg[1]_29 ({\genByte[7].u_ddr_mc_wr_byte_n_256 ,\genByte[7].u_ddr_mc_wr_byte_n_257 ,\genByte[7].u_ddr_mc_wr_byte_n_258 ,\genByte[7].u_ddr_mc_wr_byte_n_259 ,\genByte[7].u_ddr_mc_wr_byte_n_260 ,\genByte[7].u_ddr_mc_wr_byte_n_261 ,\genByte[7].u_ddr_mc_wr_byte_n_262 ,\genByte[7].u_ddr_mc_wr_byte_n_263 }),
        .\wosp_reg[1]_3 ({\genByte[7].u_ddr_mc_wr_byte_n_45 ,\genByte[7].u_ddr_mc_wr_byte_n_46 ,\genByte[7].u_ddr_mc_wr_byte_n_47 ,\genByte[7].u_ddr_mc_wr_byte_n_48 ,\genByte[7].u_ddr_mc_wr_byte_n_49 ,\genByte[7].u_ddr_mc_wr_byte_n_50 ,\genByte[7].u_ddr_mc_wr_byte_n_51 ,\genByte[7].u_ddr_mc_wr_byte_n_52 }),
        .\wosp_reg[1]_30 ({\genByte[7].u_ddr_mc_wr_byte_n_264 ,\genByte[7].u_ddr_mc_wr_byte_n_265 ,\genByte[7].u_ddr_mc_wr_byte_n_266 ,\genByte[7].u_ddr_mc_wr_byte_n_267 ,\genByte[7].u_ddr_mc_wr_byte_n_268 ,\genByte[7].u_ddr_mc_wr_byte_n_269 ,\genByte[7].u_ddr_mc_wr_byte_n_270 ,\genByte[7].u_ddr_mc_wr_byte_n_271 }),
        .\wosp_reg[1]_31 ({\genByte[7].u_ddr_mc_wr_byte_n_272 ,\genByte[7].u_ddr_mc_wr_byte_n_273 ,\genByte[7].u_ddr_mc_wr_byte_n_274 ,\genByte[7].u_ddr_mc_wr_byte_n_275 ,\genByte[7].u_ddr_mc_wr_byte_n_276 ,\genByte[7].u_ddr_mc_wr_byte_n_277 ,\genByte[7].u_ddr_mc_wr_byte_n_278 ,\genByte[7].u_ddr_mc_wr_byte_n_279 }),
        .\wosp_reg[1]_32 ({\genByte[7].u_ddr_mc_wr_byte_n_280 ,\genByte[7].u_ddr_mc_wr_byte_n_281 ,\genByte[7].u_ddr_mc_wr_byte_n_282 ,\genByte[7].u_ddr_mc_wr_byte_n_283 ,\genByte[7].u_ddr_mc_wr_byte_n_284 ,\genByte[7].u_ddr_mc_wr_byte_n_285 ,\genByte[7].u_ddr_mc_wr_byte_n_286 ,\genByte[7].u_ddr_mc_wr_byte_n_287 }),
        .\wosp_reg[1]_33 ({\genByte[7].u_ddr_mc_wr_byte_n_288 ,\genByte[7].u_ddr_mc_wr_byte_n_289 ,\genByte[7].u_ddr_mc_wr_byte_n_290 ,\genByte[7].u_ddr_mc_wr_byte_n_291 ,\genByte[7].u_ddr_mc_wr_byte_n_292 ,\genByte[7].u_ddr_mc_wr_byte_n_293 ,\genByte[7].u_ddr_mc_wr_byte_n_294 ,\genByte[7].u_ddr_mc_wr_byte_n_295 }),
        .\wosp_reg[1]_34 ({\genByte[7].u_ddr_mc_wr_byte_n_296 ,\genByte[7].u_ddr_mc_wr_byte_n_297 ,\genByte[7].u_ddr_mc_wr_byte_n_298 ,\genByte[7].u_ddr_mc_wr_byte_n_299 ,\genByte[7].u_ddr_mc_wr_byte_n_300 ,\genByte[7].u_ddr_mc_wr_byte_n_301 ,\genByte[7].u_ddr_mc_wr_byte_n_302 ,\genByte[7].u_ddr_mc_wr_byte_n_303 }),
        .\wosp_reg[1]_35 ({dReg0_out_55[15],dReg0_out_55[13:12],dReg0_out_55[7:2]}),
        .\wosp_reg[1]_36 ({\genByte[7].u_ddr_mc_wr_byte_n_313 ,\genByte[7].u_ddr_mc_wr_byte_n_314 ,\genByte[7].u_ddr_mc_wr_byte_n_315 ,\genByte[7].u_ddr_mc_wr_byte_n_316 ,\genByte[7].u_ddr_mc_wr_byte_n_317 ,\genByte[7].u_ddr_mc_wr_byte_n_318 ,\genByte[7].u_ddr_mc_wr_byte_n_319 ,\genByte[7].u_ddr_mc_wr_byte_n_320 }),
        .\wosp_reg[1]_37 ({\genByte[7].u_ddr_mc_wr_byte_n_321 ,\genByte[7].u_ddr_mc_wr_byte_n_322 ,\genByte[7].u_ddr_mc_wr_byte_n_323 ,\genByte[7].u_ddr_mc_wr_byte_n_324 ,\genByte[7].u_ddr_mc_wr_byte_n_325 ,\genByte[7].u_ddr_mc_wr_byte_n_326 ,\genByte[7].u_ddr_mc_wr_byte_n_327 ,\genByte[7].u_ddr_mc_wr_byte_n_328 }),
        .\wosp_reg[1]_38 ({\genByte[7].u_ddr_mc_wr_byte_n_329 ,\genByte[7].u_ddr_mc_wr_byte_n_330 ,\genByte[7].u_ddr_mc_wr_byte_n_331 ,\genByte[7].u_ddr_mc_wr_byte_n_332 ,\genByte[7].u_ddr_mc_wr_byte_n_333 ,\genByte[7].u_ddr_mc_wr_byte_n_334 ,\genByte[7].u_ddr_mc_wr_byte_n_335 ,\genByte[7].u_ddr_mc_wr_byte_n_336 }),
        .\wosp_reg[1]_39 ({\genByte[7].u_ddr_mc_wr_byte_n_337 ,\genByte[7].u_ddr_mc_wr_byte_n_338 ,\genByte[7].u_ddr_mc_wr_byte_n_339 ,\genByte[7].u_ddr_mc_wr_byte_n_340 ,\genByte[7].u_ddr_mc_wr_byte_n_341 ,\genByte[7].u_ddr_mc_wr_byte_n_342 ,\genByte[7].u_ddr_mc_wr_byte_n_343 ,\genByte[7].u_ddr_mc_wr_byte_n_344 }),
        .\wosp_reg[1]_4 ({\genByte[7].u_ddr_mc_wr_byte_n_53 ,\genByte[7].u_ddr_mc_wr_byte_n_54 ,\genByte[7].u_ddr_mc_wr_byte_n_55 ,\genByte[7].u_ddr_mc_wr_byte_n_56 ,\genByte[7].u_ddr_mc_wr_byte_n_57 ,\genByte[7].u_ddr_mc_wr_byte_n_58 ,\genByte[7].u_ddr_mc_wr_byte_n_59 ,\genByte[7].u_ddr_mc_wr_byte_n_60 }),
        .\wosp_reg[1]_40 ({\genByte[7].u_ddr_mc_wr_byte_n_345 ,\genByte[7].u_ddr_mc_wr_byte_n_346 ,\genByte[7].u_ddr_mc_wr_byte_n_347 ,\genByte[7].u_ddr_mc_wr_byte_n_348 ,\genByte[7].u_ddr_mc_wr_byte_n_349 ,\genByte[7].u_ddr_mc_wr_byte_n_350 ,\genByte[7].u_ddr_mc_wr_byte_n_351 ,\genByte[7].u_ddr_mc_wr_byte_n_352 }),
        .\wosp_reg[1]_41 ({\genByte[7].u_ddr_mc_wr_byte_n_353 ,\genByte[7].u_ddr_mc_wr_byte_n_354 ,\genByte[7].u_ddr_mc_wr_byte_n_355 ,\genByte[7].u_ddr_mc_wr_byte_n_356 ,\genByte[7].u_ddr_mc_wr_byte_n_357 ,\genByte[7].u_ddr_mc_wr_byte_n_358 ,\genByte[7].u_ddr_mc_wr_byte_n_359 ,\genByte[7].u_ddr_mc_wr_byte_n_360 }),
        .\wosp_reg[1]_42 ({\genByte[7].u_ddr_mc_wr_byte_n_361 ,\genByte[7].u_ddr_mc_wr_byte_n_362 ,\genByte[7].u_ddr_mc_wr_byte_n_363 ,\genByte[7].u_ddr_mc_wr_byte_n_364 ,\genByte[7].u_ddr_mc_wr_byte_n_365 ,\genByte[7].u_ddr_mc_wr_byte_n_366 ,\genByte[7].u_ddr_mc_wr_byte_n_367 ,\genByte[7].u_ddr_mc_wr_byte_n_368 }),
        .\wosp_reg[1]_43 ({\genByte[7].u_ddr_mc_wr_byte_n_369 ,\genByte[7].u_ddr_mc_wr_byte_n_370 ,\genByte[7].u_ddr_mc_wr_byte_n_371 ,\genByte[7].u_ddr_mc_wr_byte_n_372 ,\genByte[7].u_ddr_mc_wr_byte_n_373 ,\genByte[7].u_ddr_mc_wr_byte_n_374 ,\genByte[7].u_ddr_mc_wr_byte_n_375 ,\genByte[7].u_ddr_mc_wr_byte_n_376 }),
        .\wosp_reg[1]_44 ({dReg0_out_54[15],dReg0_out_54[13:12],dReg0_out_54[7:2]}),
        .\wosp_reg[1]_45 ({\genByte[7].u_ddr_mc_wr_byte_n_386 ,\genByte[7].u_ddr_mc_wr_byte_n_387 ,\genByte[7].u_ddr_mc_wr_byte_n_388 ,\genByte[7].u_ddr_mc_wr_byte_n_389 ,\genByte[7].u_ddr_mc_wr_byte_n_390 ,\genByte[7].u_ddr_mc_wr_byte_n_391 ,\genByte[7].u_ddr_mc_wr_byte_n_392 ,\genByte[7].u_ddr_mc_wr_byte_n_393 }),
        .\wosp_reg[1]_46 ({\genByte[7].u_ddr_mc_wr_byte_n_394 ,\genByte[7].u_ddr_mc_wr_byte_n_395 ,\genByte[7].u_ddr_mc_wr_byte_n_396 ,\genByte[7].u_ddr_mc_wr_byte_n_397 ,\genByte[7].u_ddr_mc_wr_byte_n_398 ,\genByte[7].u_ddr_mc_wr_byte_n_399 ,\genByte[7].u_ddr_mc_wr_byte_n_400 ,\genByte[7].u_ddr_mc_wr_byte_n_401 }),
        .\wosp_reg[1]_47 ({\genByte[7].u_ddr_mc_wr_byte_n_402 ,\genByte[7].u_ddr_mc_wr_byte_n_403 ,\genByte[7].u_ddr_mc_wr_byte_n_404 ,\genByte[7].u_ddr_mc_wr_byte_n_405 ,\genByte[7].u_ddr_mc_wr_byte_n_406 ,\genByte[7].u_ddr_mc_wr_byte_n_407 ,\genByte[7].u_ddr_mc_wr_byte_n_408 ,\genByte[7].u_ddr_mc_wr_byte_n_409 }),
        .\wosp_reg[1]_48 ({\genByte[7].u_ddr_mc_wr_byte_n_410 ,\genByte[7].u_ddr_mc_wr_byte_n_411 ,\genByte[7].u_ddr_mc_wr_byte_n_412 ,\genByte[7].u_ddr_mc_wr_byte_n_413 ,\genByte[7].u_ddr_mc_wr_byte_n_414 ,\genByte[7].u_ddr_mc_wr_byte_n_415 ,\genByte[7].u_ddr_mc_wr_byte_n_416 ,\genByte[7].u_ddr_mc_wr_byte_n_417 }),
        .\wosp_reg[1]_49 ({\genByte[7].u_ddr_mc_wr_byte_n_418 ,\genByte[7].u_ddr_mc_wr_byte_n_419 ,\genByte[7].u_ddr_mc_wr_byte_n_420 ,\genByte[7].u_ddr_mc_wr_byte_n_421 ,\genByte[7].u_ddr_mc_wr_byte_n_422 ,\genByte[7].u_ddr_mc_wr_byte_n_423 ,\genByte[7].u_ddr_mc_wr_byte_n_424 ,\genByte[7].u_ddr_mc_wr_byte_n_425 }),
        .\wosp_reg[1]_5 ({\genByte[7].u_ddr_mc_wr_byte_n_61 ,\genByte[7].u_ddr_mc_wr_byte_n_62 ,\genByte[7].u_ddr_mc_wr_byte_n_63 ,\genByte[7].u_ddr_mc_wr_byte_n_64 ,\genByte[7].u_ddr_mc_wr_byte_n_65 ,\genByte[7].u_ddr_mc_wr_byte_n_66 ,\genByte[7].u_ddr_mc_wr_byte_n_67 ,\genByte[7].u_ddr_mc_wr_byte_n_68 }),
        .\wosp_reg[1]_50 ({\genByte[7].u_ddr_mc_wr_byte_n_426 ,\genByte[7].u_ddr_mc_wr_byte_n_427 ,\genByte[7].u_ddr_mc_wr_byte_n_428 ,\genByte[7].u_ddr_mc_wr_byte_n_429 ,\genByte[7].u_ddr_mc_wr_byte_n_430 ,\genByte[7].u_ddr_mc_wr_byte_n_431 ,\genByte[7].u_ddr_mc_wr_byte_n_432 ,\genByte[7].u_ddr_mc_wr_byte_n_433 }),
        .\wosp_reg[1]_51 ({\genByte[7].u_ddr_mc_wr_byte_n_434 ,\genByte[7].u_ddr_mc_wr_byte_n_435 ,\genByte[7].u_ddr_mc_wr_byte_n_436 ,\genByte[7].u_ddr_mc_wr_byte_n_437 ,\genByte[7].u_ddr_mc_wr_byte_n_438 ,\genByte[7].u_ddr_mc_wr_byte_n_439 ,\genByte[7].u_ddr_mc_wr_byte_n_440 ,\genByte[7].u_ddr_mc_wr_byte_n_441 }),
        .\wosp_reg[1]_52 ({\genByte[7].u_ddr_mc_wr_byte_n_442 ,\genByte[7].u_ddr_mc_wr_byte_n_443 ,\genByte[7].u_ddr_mc_wr_byte_n_444 ,\genByte[7].u_ddr_mc_wr_byte_n_445 ,\genByte[7].u_ddr_mc_wr_byte_n_446 ,\genByte[7].u_ddr_mc_wr_byte_n_447 ,\genByte[7].u_ddr_mc_wr_byte_n_448 ,\genByte[7].u_ddr_mc_wr_byte_n_449 }),
        .\wosp_reg[1]_53 ({dReg0_out[15],dReg0_out[13:12],dReg0_out[7:2]}),
        .\wosp_reg[1]_54 ({\genByte[7].u_ddr_mc_wr_byte_n_459 ,\genByte[7].u_ddr_mc_wr_byte_n_460 ,\genByte[7].u_ddr_mc_wr_byte_n_461 ,\genByte[7].u_ddr_mc_wr_byte_n_462 ,\genByte[7].u_ddr_mc_wr_byte_n_463 ,\genByte[7].u_ddr_mc_wr_byte_n_464 ,\genByte[7].u_ddr_mc_wr_byte_n_465 ,\genByte[7].u_ddr_mc_wr_byte_n_466 }),
        .\wosp_reg[1]_55 ({\genByte[7].u_ddr_mc_wr_byte_n_467 ,\genByte[7].u_ddr_mc_wr_byte_n_468 ,\genByte[7].u_ddr_mc_wr_byte_n_469 ,\genByte[7].u_ddr_mc_wr_byte_n_470 ,\genByte[7].u_ddr_mc_wr_byte_n_471 ,\genByte[7].u_ddr_mc_wr_byte_n_472 ,\genByte[7].u_ddr_mc_wr_byte_n_473 ,\genByte[7].u_ddr_mc_wr_byte_n_474 }),
        .\wosp_reg[1]_56 ({\genByte[7].u_ddr_mc_wr_byte_n_475 ,\genByte[7].u_ddr_mc_wr_byte_n_476 ,\genByte[7].u_ddr_mc_wr_byte_n_477 ,\genByte[7].u_ddr_mc_wr_byte_n_478 ,\genByte[7].u_ddr_mc_wr_byte_n_479 ,\genByte[7].u_ddr_mc_wr_byte_n_480 ,\genByte[7].u_ddr_mc_wr_byte_n_481 ,\genByte[7].u_ddr_mc_wr_byte_n_482 }),
        .\wosp_reg[1]_57 ({\genByte[7].u_ddr_mc_wr_byte_n_483 ,\genByte[7].u_ddr_mc_wr_byte_n_484 ,\genByte[7].u_ddr_mc_wr_byte_n_485 ,\genByte[7].u_ddr_mc_wr_byte_n_486 ,\genByte[7].u_ddr_mc_wr_byte_n_487 ,\genByte[7].u_ddr_mc_wr_byte_n_488 ,\genByte[7].u_ddr_mc_wr_byte_n_489 ,\genByte[7].u_ddr_mc_wr_byte_n_490 }),
        .\wosp_reg[1]_58 ({\genByte[7].u_ddr_mc_wr_byte_n_491 ,\genByte[7].u_ddr_mc_wr_byte_n_492 ,\genByte[7].u_ddr_mc_wr_byte_n_493 ,\genByte[7].u_ddr_mc_wr_byte_n_494 ,\genByte[7].u_ddr_mc_wr_byte_n_495 ,\genByte[7].u_ddr_mc_wr_byte_n_496 ,\genByte[7].u_ddr_mc_wr_byte_n_497 ,\genByte[7].u_ddr_mc_wr_byte_n_498 }),
        .\wosp_reg[1]_59 ({\genByte[7].u_ddr_mc_wr_byte_n_499 ,\genByte[7].u_ddr_mc_wr_byte_n_500 ,\genByte[7].u_ddr_mc_wr_byte_n_501 ,\genByte[7].u_ddr_mc_wr_byte_n_502 ,\genByte[7].u_ddr_mc_wr_byte_n_503 ,\genByte[7].u_ddr_mc_wr_byte_n_504 ,\genByte[7].u_ddr_mc_wr_byte_n_505 ,\genByte[7].u_ddr_mc_wr_byte_n_506 }),
        .\wosp_reg[1]_6 ({\genByte[7].u_ddr_mc_wr_byte_n_69 ,\genByte[7].u_ddr_mc_wr_byte_n_70 ,\genByte[7].u_ddr_mc_wr_byte_n_71 ,\genByte[7].u_ddr_mc_wr_byte_n_72 ,\genByte[7].u_ddr_mc_wr_byte_n_73 ,\genByte[7].u_ddr_mc_wr_byte_n_74 ,\genByte[7].u_ddr_mc_wr_byte_n_75 ,\genByte[7].u_ddr_mc_wr_byte_n_76 }),
        .\wosp_reg[1]_60 ({\genByte[7].u_ddr_mc_wr_byte_n_507 ,\genByte[7].u_ddr_mc_wr_byte_n_508 ,\genByte[7].u_ddr_mc_wr_byte_n_509 ,\genByte[7].u_ddr_mc_wr_byte_n_510 ,\genByte[7].u_ddr_mc_wr_byte_n_511 ,\genByte[7].u_ddr_mc_wr_byte_n_512 ,\genByte[7].u_ddr_mc_wr_byte_n_513 ,\genByte[7].u_ddr_mc_wr_byte_n_514 }),
        .\wosp_reg[1]_61 ({\genByte[7].u_ddr_mc_wr_byte_n_515 ,\genByte[7].u_ddr_mc_wr_byte_n_516 ,\genByte[7].u_ddr_mc_wr_byte_n_517 ,\genByte[7].u_ddr_mc_wr_byte_n_518 ,\genByte[7].u_ddr_mc_wr_byte_n_519 ,\genByte[7].u_ddr_mc_wr_byte_n_520 ,\genByte[7].u_ddr_mc_wr_byte_n_521 ,\genByte[7].u_ddr_mc_wr_byte_n_522 }),
        .\wosp_reg[1]_62 (\wrQ_reg[0][0]_0 ),
        .\wosp_reg[1]_7 ({\genByte[7].u_ddr_mc_wr_byte_n_77 ,\genByte[7].u_ddr_mc_wr_byte_n_78 ,\genByte[7].u_ddr_mc_wr_byte_n_79 ,\genByte[7].u_ddr_mc_wr_byte_n_80 ,\genByte[7].u_ddr_mc_wr_byte_n_81 ,\genByte[7].u_ddr_mc_wr_byte_n_82 ,\genByte[7].u_ddr_mc_wr_byte_n_83 ,\genByte[7].u_ddr_mc_wr_byte_n_84 }),
        .\wosp_reg[1]_8 ({dReg0_out_58[15],dReg0_out_58[13:12],dReg0_out_58[7:2]}),
        .\wosp_reg[1]_9 ({\genByte[7].u_ddr_mc_wr_byte_n_94 ,\genByte[7].u_ddr_mc_wr_byte_n_95 ,\genByte[7].u_ddr_mc_wr_byte_n_96 ,\genByte[7].u_ddr_mc_wr_byte_n_97 ,\genByte[7].u_ddr_mc_wr_byte_n_98 ,\genByte[7].u_ddr_mc_wr_byte_n_99 ,\genByte[7].u_ddr_mc_wr_byte_n_100 ,\genByte[7].u_ddr_mc_wr_byte_n_101 }),
        .\wosp_reg[2] (\wosp_reg[2] ),
        .\wosp_reg[2]_rep (\wosp_reg[2]_rep ),
        .\wosp_reg[2]_rep__0 (\wosp_reg[2]_rep__0 ),
        .\wosp_reg[2]_rep__1 (\wosp_reg[2]_rep__1 ),
        .\wosp_reg[2]_rep__2 (\wosp_reg[2]_rep__2 ),
        .\wosp_reg[2]_rep__3 (\wosp_reg[2]_rep__3 ),
        .\wosp_reg[2]_rep__4 (\wosp_reg[2]_rep__4 ),
        .\wosp_reg[2]_rep__5 (\wosp_reg[2]_rep__5 ),
        .\wosp_reg[2]_rep__6 (\wosp_reg[2]_rep__6 ),
        .\wosp_reg[2]_rep__7 (\wosp_reg[2]_rep__7 ),
        .wrDataVal_reg(\genByte[7].u_ddr_mc_wr_byte_n_11 ));
  FDRE \oe_0_mux_cal_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_0_mux_cal_reg[0]_1 ),
        .Q(\oe_0_mux_cal_reg[0]_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2494" *) 
  LUT3 #(
    .INIT(8'h8C)) 
    \oe_low[0]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(oe_low[4]),
        .I2(cal_oe_dis_low_dly),
        .O(\oe_low[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2490" *) 
  LUT5 #(
    .INIT(32'h88A8CCFC)) 
    \oe_low[1]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(oe_low[5]),
        .I2(\wrQ_reg[0][0]_0 ),
        .I3(sel),
        .I4(cal_oe_dis_low_dly),
        .O(\oe_low[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2487" *) 
  LUT5 #(
    .INIT(32'h88A8CCFC)) 
    \oe_low[2]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(oe_low[6]),
        .I2(\wrQ_reg[0][0]_0 ),
        .I3(sel),
        .I4(cal_oe_dis_low_dly),
        .O(\oe_low[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2492" *) 
  LUT4 #(
    .INIT(16'hA8FC)) 
    \oe_low[3]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(oe_low[7]),
        .I2(\wrQ_reg[0][0]_0 ),
        .I3(cal_oe_dis_low_dly),
        .O(\oe_low[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2492" *) 
  LUT3 #(
    .INIT(8'h8C)) 
    \oe_low[4]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(\wrQ_reg[0][0]_0 ),
        .I2(cal_oe_dis_low_dly),
        .O(\oe_low[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2494" *) 
  LUT3 #(
    .INIT(8'h8C)) 
    \oe_low[5]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(\wrQ_reg[0][0]_0 ),
        .I2(cal_oe_dis_low_dly),
        .O(\oe_low[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2490" *) 
  LUT4 #(
    .INIT(16'h80C0)) 
    \oe_low[6]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(\wrQ_reg[0][0]_0 ),
        .I2(sel),
        .I3(cal_oe_dis_low_dly),
        .O(\oe_low[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2487" *) 
  LUT4 #(
    .INIT(16'h80C0)) 
    \oe_low[7]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(sel),
        .I2(\wrQ_reg[0][0]_0 ),
        .I3(cal_oe_dis_low_dly),
        .O(\oe_low[7]_i_1_n_0 ));
  FDRE \oe_low_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_low[0]_i_1_n_0 ),
        .Q(\oe_low_reg[3]_0 [0]),
        .R(out));
  FDRE \oe_low_reg[1] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_low[1]_i_1_n_0 ),
        .Q(\oe_low_reg[3]_0 [1]),
        .R(out));
  FDRE \oe_low_reg[2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_low[2]_i_1_n_0 ),
        .Q(\oe_low_reg[3]_0 [2]),
        .R(out));
  FDRE \oe_low_reg[3] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_low[3]_i_1_n_0 ),
        .Q(\oe_low_reg[3]_0 [3]),
        .R(out));
  FDRE \oe_low_reg[4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_low[4]_i_1_n_0 ),
        .Q(oe_low[4]),
        .R(out));
  FDRE \oe_low_reg[5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_low[5]_i_1_n_0 ),
        .Q(oe_low[5]),
        .R(out));
  FDRE \oe_low_reg[6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_low[6]_i_1_n_0 ),
        .Q(oe_low[6]),
        .R(out));
  FDRE \oe_low_reg[7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_low[7]_i_1_n_0 ),
        .Q(oe_low[7]),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2493" *) 
  LUT3 #(
    .INIT(8'h8C)) 
    \oe_upp[0]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(oe_upp[4]),
        .I2(cal_oe_dis_upp_dly),
        .O(\oe_upp[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2489" *) 
  LUT5 #(
    .INIT(32'h88A8CCFC)) 
    \oe_upp[1]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(oe_upp[5]),
        .I2(\wrQ_reg[0][0]_0 ),
        .I3(sel),
        .I4(cal_oe_dis_upp_dly),
        .O(\oe_upp[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2488" *) 
  LUT5 #(
    .INIT(32'h88A8CCFC)) 
    \oe_upp[2]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(oe_upp[6]),
        .I2(\wrQ_reg[0][0]_0 ),
        .I3(sel),
        .I4(cal_oe_dis_upp_dly),
        .O(\oe_upp[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2491" *) 
  LUT4 #(
    .INIT(16'hA8FC)) 
    \oe_upp[3]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(oe_upp[7]),
        .I2(\wrQ_reg[0][0]_0 ),
        .I3(cal_oe_dis_upp_dly),
        .O(\oe_upp[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2491" *) 
  LUT3 #(
    .INIT(8'h8C)) 
    \oe_upp[4]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(\wrQ_reg[0][0]_0 ),
        .I2(cal_oe_dis_upp_dly),
        .O(\oe_upp[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2493" *) 
  LUT3 #(
    .INIT(8'h8C)) 
    \oe_upp[5]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(\wrQ_reg[0][0]_0 ),
        .I2(cal_oe_dis_upp_dly),
        .O(\oe_upp[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2489" *) 
  LUT4 #(
    .INIT(16'h80C0)) 
    \oe_upp[6]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(\wrQ_reg[0][0]_0 ),
        .I2(sel),
        .I3(cal_oe_dis_upp_dly),
        .O(\oe_upp[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2488" *) 
  LUT4 #(
    .INIT(16'h80C0)) 
    \oe_upp[7]_i_1 
       (.I0(\oe_low_reg[5]_0 ),
        .I1(sel),
        .I2(\wrQ_reg[0][0]_0 ),
        .I3(cal_oe_dis_upp_dly),
        .O(\oe_upp[7]_i_1_n_0 ));
  FDRE \oe_upp_reg[0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_upp[0]_i_1_n_0 ),
        .Q(\oe_upp_reg[3]_0 [0]),
        .R(out));
  FDRE \oe_upp_reg[1] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_upp[1]_i_1_n_0 ),
        .Q(\oe_upp_reg[3]_0 [1]),
        .R(out));
  FDRE \oe_upp_reg[2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_upp[2]_i_1_n_0 ),
        .Q(\oe_upp_reg[3]_0 [2]),
        .R(out));
  FDRE \oe_upp_reg[3] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_upp[3]_i_1_n_0 ),
        .Q(\oe_upp_reg[3]_0 [3]),
        .R(out));
  FDRE \oe_upp_reg[4] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_upp[4]_i_1_n_0 ),
        .Q(oe_upp[4]),
        .R(out));
  FDRE \oe_upp_reg[5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_upp[5]_i_1_n_0 ),
        .Q(oe_upp[5]),
        .R(out));
  FDRE \oe_upp_reg[6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_upp[6]_i_1_n_0 ),
        .Q(oe_upp[6]),
        .R(out));
  FDRE \oe_upp_reg[7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\oe_upp[7]_i_1_n_0 ),
        .Q(oe_upp[7]),
        .R(out));
  LUT3 #(
    .INIT(8'h8F)) 
    \rams[0].RAM32M0_i_1 
       (.I0(\wrQ_reg[0][0]_0 ),
        .I1(\oe_low_reg[5]_0 ),
        .I2(\rams[1].RAM32M0 ),
        .O(pointer_we));
  LUT2 #(
    .INIT(4'h8)) 
    \rd_data_indx_r[3]_i_1 
       (.I0(\wrQ_reg[0][0]_0 ),
        .I1(\oe_low_reg[5]_0 ),
        .O(\wrQ_reg[0][0]_1 ));
  FDRE wrDataVal_reg
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][0]_0 ),
        .Q(wrDataVal_reg_0),
        .R(out));
  LUT6 #(
    .INIT(64'hFFFFFFFF02020302)) 
    \wrQ[0][0]_i_1 
       (.I0(mcWrCAS),
        .I1(\oe_0_mux_cal_reg[0]_0 ),
        .I2(mcCasSlot2),
        .I3(\wrQ_reg[0][2]_0 ),
        .I4(\oe_low_reg[5]_0 ),
        .I5(\wrQ_reg[1]_11 [0]),
        .O(\wrQ_nxt[0]_12 [0]));
  LUT6 #(
    .INIT(64'hFFFFFFFF02020302)) 
    \wrQ[0][0]_rep_i_1 
       (.I0(mcWrCAS),
        .I1(\oe_0_mux_cal_reg[0]_0 ),
        .I2(mcCasSlot2),
        .I3(\wrQ_reg[0][2]_0 ),
        .I4(\oe_low_reg[5]_0 ),
        .I5(\wrQ_reg[1]_11 [0]),
        .O(\wrQ[0][0]_rep_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFEFF02020202)) 
    \wrQ[0][2]_i_1 
       (.I0(mcWrCAS),
        .I1(\oe_0_mux_cal_reg[0]_0 ),
        .I2(mcCasSlot2),
        .I3(\wrQ_reg[0][2]_0 ),
        .I4(\oe_low_reg[5]_0 ),
        .I5(\wrQ_reg[1]_11 [2]),
        .O(\wrQ_nxt[0]_12 [2]));
  (* ORIG_CELL_NAME = "wrQ_reg[0][0]" *) 
  FDRE \wrQ_reg[0][0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_nxt[0]_12 [0]),
        .Q(\wrQ_reg[0][0]_0 ),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][0]" *) 
  FDRE \wrQ_reg[0][0]_rep 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ[0][0]_rep_i_1_n_0 ),
        .Q(\wrQ_reg[0][0]_rep_0 ),
        .R(out));
  FDRE \wrQ_reg[0][2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_nxt[0]_12 [2]),
        .Q(sel),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][5]" *) 
  FDRE \wrQ_reg[0][5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][8]_0 [0]),
        .Q(ADDRC[0]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][5]" *) 
  FDRE \wrQ_reg[0][5]_rep 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][5]_rep_0 ),
        .Q(ADDRA[0]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][5]" *) 
  FDRE \wrQ_reg[0][5]_rep__0 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][5]_rep__0_0 ),
        .Q(\wrQ_reg[0][8]_rep__0_0 [0]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][5]" *) 
  FDRE \wrQ_reg[0][5]_rep__1 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][5]_rep__1_0 ),
        .Q(\wrQ_reg[0][8]_rep__1_0 [0]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][6]" *) 
  FDRE \wrQ_reg[0][6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][8]_0 [1]),
        .Q(ADDRC[1]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][6]" *) 
  FDRE \wrQ_reg[0][6]_rep 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][6]_rep_0 ),
        .Q(ADDRA[1]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][6]" *) 
  FDRE \wrQ_reg[0][6]_rep__0 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][6]_rep__0_0 ),
        .Q(\wrQ_reg[0][8]_rep__0_0 [1]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][6]" *) 
  FDRE \wrQ_reg[0][6]_rep__1 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][6]_rep__1_0 ),
        .Q(\wrQ_reg[0][8]_rep__1_0 [1]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][7]" *) 
  FDRE \wrQ_reg[0][7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][8]_0 [2]),
        .Q(ADDRC[2]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][7]" *) 
  FDRE \wrQ_reg[0][7]_rep 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][7]_rep_0 ),
        .Q(ADDRA[2]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][7]" *) 
  FDRE \wrQ_reg[0][7]_rep__0 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][7]_rep__0_0 ),
        .Q(\wrQ_reg[0][8]_rep__0_0 [2]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][7]" *) 
  FDRE \wrQ_reg[0][7]_rep__1 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][7]_rep__1_0 ),
        .Q(\wrQ_reg[0][8]_rep__1_0 [2]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][8]" *) 
  FDRE \wrQ_reg[0][8] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][8]_0 [3]),
        .Q(ADDRC[3]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][8]" *) 
  FDRE \wrQ_reg[0][8]_rep 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][8]_rep_0 ),
        .Q(ADDRA[3]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][8]" *) 
  FDRE \wrQ_reg[0][8]_rep__0 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][8]_rep__0_1 ),
        .Q(\wrQ_reg[0][8]_rep__0_0 [3]),
        .R(out));
  (* ORIG_CELL_NAME = "wrQ_reg[0][8]" *) 
  FDRE \wrQ_reg[0][8]_rep__1 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[0][8]_rep__1_1 ),
        .Q(\wrQ_reg[0][8]_rep__1_0 [3]),
        .R(out));
  FDRE \wrQ_reg[1][0] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_nxt[1]_13 ),
        .Q(\wrQ_reg[1]_11 [0]),
        .R(out));
  FDRE \wrQ_reg[1][2] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[1][8]_1 [0]),
        .Q(\wrQ_reg[1]_11 [2]),
        .R(out));
  FDRE \wrQ_reg[1][5] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[1][8]_1 [1]),
        .Q(\wrQ_reg[1][8]_0 [0]),
        .R(out));
  FDRE \wrQ_reg[1][6] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[1][8]_1 [2]),
        .Q(\wrQ_reg[1][8]_0 [1]),
        .R(out));
  FDRE \wrQ_reg[1][7] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[1][8]_1 [3]),
        .Q(\wrQ_reg[1][8]_0 [2]),
        .R(out));
  FDRE \wrQ_reg[1][8] 
       (.C(\dReg_reg[10] ),
        .CE(1'b1),
        .D(\wrQ_reg[1][8]_1 [4]),
        .Q(\wrQ_reg[1][8]_0 [3]),
        .R(out));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_xsdb_arbiter" *) 
module ddr4_0_ddr4_v2_2_17_cal_xsdb_arbiter
   (s_do_i,
    s_drdy_i,
    bramB_en,
    web,
    enb,
    Q,
    \bram_di_reg[8]_0 ,
    CLK,
    \SYNC[0].sync_reg_reg[1] ,
    SS,
    E,
    s_dwe_o,
    t1,
    D,
    \slave_addr_r_reg[15]_0 ,
    \slave_di_r_reg[8]_0 ,
    s_den_o);
  output [8:0]s_do_i;
  output s_drdy_i;
  output bramB_en;
  output web;
  output enb;
  output [15:0]Q;
  output [8:0]\bram_di_reg[8]_0 ;
  input CLK;
  input \SYNC[0].sync_reg_reg[1] ;
  input [0:0]SS;
  input [0:0]E;
  input s_dwe_o;
  input t1;
  input [8:0]D;
  input [15:0]\slave_addr_r_reg[15]_0 ;
  input [8:0]\slave_di_r_reg[8]_0 ;
  input s_den_o;

  wire CLK;
  wire [8:0]D;
  wire [0:0]E;
  wire [15:0]Q;
  wire [0:0]SS;
  wire \SYNC[0].sync_reg_reg[1] ;
  wire bramB_en;
  wire [8:0]\bram_di_reg[8]_0 ;
  wire enb;
  wire s_den_o;
  wire [8:0]s_do_i;
  wire s_drdy_i;
  wire s_dwe_o;
  wire [15:0]slave_addr_fclk;
  (* DONT_TOUCH *) wire [15:0]slave_addr_r;
  wire [15:0]\slave_addr_r_reg[15]_0 ;
  wire slave_cmd_en;
  wire slave_cmd_en_r;
  wire [8:0]slave_di_fclk;
  (* DONT_TOUCH *) wire [8:0]slave_di_r;
  wire [8:0]\slave_di_r_reg[8]_0 ;
  (* DONT_TOUCH *) wire [8:0]slave_do_fclk;
  wire slave_en_fclk;
  wire slave_en_fclk_i_1_n_0;
  (* DONT_TOUCH *) wire slave_en_lvl;
  wire slave_en_lvl_fclk;
  wire slave_en_lvl_fclk_r1;
  wire slave_en_lvl_fclk_r2;
  wire slave_en_lvl_i_2_n_0;
  wire slave_rdy0;
  (* DONT_TOUCH *) wire slave_rdy_cptd_sclk;
  wire slave_rdy_fclk_r;
  (* DONT_TOUCH *) wire slave_rdy_lvl_fclk;
  wire slave_rdy_lvl_sclk;
  wire slave_rdy_lvl_sclk_r1;
  wire slave_rdy_lvl_sclk_r2;
  wire slave_we_fclk;
  (* DONT_TOUCH *) wire slave_we_r;
  wire slave_we_r_reg0;
  wire t1;
  wire u_slave_rdy_cptd_sync_n_0;
  wire web;

  LUT2 #(
    .INIT(4'hE)) 
    DDR_XSDB_BRAM_i_2
       (.I0(bramB_en),
        .I1(t1),
        .O(enb));
  FDRE \bram_addr_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[0]),
        .Q(Q[0]),
        .R(SS));
  FDRE \bram_addr_reg[10] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[10]),
        .Q(Q[10]),
        .R(SS));
  FDRE \bram_addr_reg[11] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[11]),
        .Q(Q[11]),
        .R(SS));
  FDRE \bram_addr_reg[12] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[12]),
        .Q(Q[12]),
        .R(SS));
  FDRE \bram_addr_reg[13] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[13]),
        .Q(Q[13]),
        .R(SS));
  FDRE \bram_addr_reg[14] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[14]),
        .Q(Q[14]),
        .R(SS));
  FDRE \bram_addr_reg[15] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[15]),
        .Q(Q[15]),
        .R(SS));
  FDRE \bram_addr_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[1]),
        .Q(Q[1]),
        .R(SS));
  FDRE \bram_addr_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[2]),
        .Q(Q[2]),
        .R(SS));
  FDRE \bram_addr_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[3]),
        .Q(Q[3]),
        .R(SS));
  FDRE \bram_addr_reg[4] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[4]),
        .Q(Q[4]),
        .R(SS));
  FDRE \bram_addr_reg[5] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[5]),
        .Q(Q[5]),
        .R(SS));
  FDRE \bram_addr_reg[6] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[6]),
        .Q(Q[6]),
        .R(SS));
  FDRE \bram_addr_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[7]),
        .Q(Q[7]),
        .R(SS));
  FDRE \bram_addr_reg[8] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[8]),
        .Q(Q[8]),
        .R(SS));
  FDRE \bram_addr_reg[9] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_addr_fclk[9]),
        .Q(Q[9]),
        .R(SS));
  FDRE \bram_di_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_di_fclk[0]),
        .Q(\bram_di_reg[8]_0 [0]),
        .R(SS));
  FDRE \bram_di_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_di_fclk[1]),
        .Q(\bram_di_reg[8]_0 [1]),
        .R(SS));
  FDRE \bram_di_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_di_fclk[2]),
        .Q(\bram_di_reg[8]_0 [2]),
        .R(SS));
  FDRE \bram_di_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_di_fclk[3]),
        .Q(\bram_di_reg[8]_0 [3]),
        .R(SS));
  FDRE \bram_di_reg[4] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_di_fclk[4]),
        .Q(\bram_di_reg[8]_0 [4]),
        .R(SS));
  FDRE \bram_di_reg[5] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_di_fclk[5]),
        .Q(\bram_di_reg[8]_0 [5]),
        .R(SS));
  FDRE \bram_di_reg[6] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_di_fclk[6]),
        .Q(\bram_di_reg[8]_0 [6]),
        .R(SS));
  FDRE \bram_di_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_di_fclk[7]),
        .Q(\bram_di_reg[8]_0 [7]),
        .R(SS));
  FDRE \bram_di_reg[8] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_di_fclk[8]),
        .Q(\bram_di_reg[8]_0 [8]),
        .R(SS));
  FDRE bram_en_reg
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(1'b1),
        .D(slave_en_fclk),
        .Q(bramB_en),
        .R(SS));
  FDRE bram_we_reg
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(slave_en_fclk),
        .D(slave_we_fclk),
        .Q(web),
        .R(SS));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [0]),
        .Q(slave_addr_r[0]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[10] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [10]),
        .Q(slave_addr_r[10]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[11] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [11]),
        .Q(slave_addr_r[11]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[12] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [12]),
        .Q(slave_addr_r[12]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[13] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [13]),
        .Q(slave_addr_r[13]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[14] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [14]),
        .Q(slave_addr_r[14]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[15] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [15]),
        .Q(slave_addr_r[15]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [1]),
        .Q(slave_addr_r[1]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [2]),
        .Q(slave_addr_r[2]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [3]),
        .Q(slave_addr_r[3]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [4]),
        .Q(slave_addr_r[4]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [5]),
        .Q(slave_addr_r[5]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [6]),
        .Q(slave_addr_r[6]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [7]),
        .Q(slave_addr_r[7]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [8]),
        .Q(slave_addr_r[8]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_addr_r_reg[9] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_addr_r_reg[15]_0 [9]),
        .Q(slave_addr_r[9]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    slave_cmd_en_r_i_1
       (.I0(s_den_o),
        .I1(s_dwe_o),
        .O(slave_cmd_en));
  FDRE slave_cmd_en_r_reg
       (.C(CLK),
        .CE(1'b1),
        .D(slave_cmd_en),
        .Q(slave_cmd_en_r),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_di_r_reg[0] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_di_r_reg[8]_0 [0]),
        .Q(slave_di_r[0]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_di_r_reg[1] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_di_r_reg[8]_0 [1]),
        .Q(slave_di_r[1]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_di_r_reg[2] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_di_r_reg[8]_0 [2]),
        .Q(slave_di_r[2]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_di_r_reg[3] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_di_r_reg[8]_0 [3]),
        .Q(slave_di_r[3]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_di_r_reg[4] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_di_r_reg[8]_0 [4]),
        .Q(slave_di_r[4]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_di_r_reg[5] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_di_r_reg[8]_0 [5]),
        .Q(slave_di_r[5]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_di_r_reg[6] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_di_r_reg[8]_0 [6]),
        .Q(slave_di_r[6]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_di_r_reg[7] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_di_r_reg[8]_0 [7]),
        .Q(slave_di_r[7]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_di_r_reg[8] 
       (.C(CLK),
        .CE(1'b1),
        .D(\slave_di_r_reg[8]_0 [8]),
        .Q(slave_di_r[8]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_do_fclk_reg[0] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(E),
        .D(D[0]),
        .Q(slave_do_fclk[0]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_do_fclk_reg[1] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(E),
        .D(D[1]),
        .Q(slave_do_fclk[1]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_do_fclk_reg[2] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(E),
        .D(D[2]),
        .Q(slave_do_fclk[2]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_do_fclk_reg[3] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(E),
        .D(D[3]),
        .Q(slave_do_fclk[3]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_do_fclk_reg[4] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(E),
        .D(D[4]),
        .Q(slave_do_fclk[4]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_do_fclk_reg[5] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(E),
        .D(D[5]),
        .Q(slave_do_fclk[5]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_do_fclk_reg[6] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(E),
        .D(D[6]),
        .Q(slave_do_fclk[6]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_do_fclk_reg[7] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(E),
        .D(D[7]),
        .Q(slave_do_fclk[7]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \slave_do_fclk_reg[8] 
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(E),
        .D(D[8]),
        .Q(slave_do_fclk[8]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h6)) 
    slave_en_fclk_i_1
       (.I0(slave_en_lvl_fclk_r1),
        .I1(slave_en_lvl_fclk_r2),
        .O(slave_en_fclk_i_1_n_0));
  FDRE slave_en_fclk_reg
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(1'b1),
        .D(slave_en_fclk_i_1_n_0),
        .Q(slave_en_fclk),
        .R(1'b0));
  FDRE slave_en_lvl_fclk_r1_reg
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(1'b1),
        .D(slave_en_lvl_fclk),
        .Q(slave_en_lvl_fclk_r1),
        .R(1'b0));
  FDRE slave_en_lvl_fclk_r2_reg
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(1'b1),
        .D(slave_en_lvl_fclk_r1),
        .Q(slave_en_lvl_fclk_r2),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h0E)) 
    slave_en_lvl_i_1
       (.I0(s_dwe_o),
        .I1(s_den_o),
        .I2(slave_cmd_en_r),
        .O(slave_we_r_reg0));
  LUT1 #(
    .INIT(2'h1)) 
    slave_en_lvl_i_2
       (.I0(slave_en_lvl),
        .O(slave_en_lvl_i_2_n_0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    slave_en_lvl_reg
       (.C(CLK),
        .CE(slave_we_r_reg0),
        .D(slave_en_lvl_i_2_n_0),
        .Q(slave_en_lvl),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE slave_rdy_cptd_sclk_reg
       (.C(CLK),
        .CE(1'b1),
        .D(slave_rdy0),
        .Q(slave_rdy_cptd_sclk),
        .R(1'b0));
  FDRE slave_rdy_fclk_r_reg
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(1'b1),
        .D(E),
        .Q(slave_rdy_fclk_r),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    slave_rdy_i_1
       (.I0(slave_rdy_lvl_sclk_r1),
        .I1(slave_rdy_lvl_sclk_r2),
        .O(slave_rdy0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE slave_rdy_lvl_fclk_reg
       (.C(\SYNC[0].sync_reg_reg[1] ),
        .CE(1'b1),
        .D(u_slave_rdy_cptd_sync_n_0),
        .Q(slave_rdy_lvl_fclk),
        .R(SS));
  FDRE slave_rdy_lvl_sclk_r1_reg
       (.C(CLK),
        .CE(1'b1),
        .D(slave_rdy_lvl_sclk),
        .Q(slave_rdy_lvl_sclk_r1),
        .R(1'b0));
  FDRE slave_rdy_lvl_sclk_r2_reg
       (.C(CLK),
        .CE(1'b1),
        .D(slave_rdy_lvl_sclk_r1),
        .Q(slave_rdy_lvl_sclk_r2),
        .R(1'b0));
  FDRE slave_rdy_reg
       (.C(CLK),
        .CE(1'b1),
        .D(slave_rdy0),
        .Q(s_drdy_i),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE slave_we_r_reg
       (.C(CLK),
        .CE(slave_we_r_reg0),
        .D(s_dwe_o),
        .Q(slave_we_r),
        .R(1'b0));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized0 u_slave_addr_sync
       (.D(slave_addr_fclk),
        .\SYNC[15].sync_reg_reg[1]_0 (\SYNC[0].sync_reg_reg[1] ),
        .out(slave_addr_r));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized1 u_slave_di_sync
       (.D(slave_di_fclk),
        .\SYNC[7].sync_reg_reg[1]_0 (\SYNC[0].sync_reg_reg[1] ),
        .out(slave_di_r));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized3 u_slave_do_sync
       (.CLK(CLK),
        .out(slave_do_fclk),
        .s_do_i(s_do_i));
  ddr4_0_ddr4_v2_2_17_cal_sync u_slave_en_sync
       (.D(slave_en_lvl),
        .\SYNC[0].sync_reg_reg[0]_0 (\SYNC[0].sync_reg_reg[1] ),
        .out(slave_en_lvl_fclk));
  ddr4_0_ddr4_v2_2_17_cal_sync_105 u_slave_rdy_cptd_sync
       (.D(slave_rdy_lvl_fclk),
        .E(E),
        .\SYNC[0].sync_reg_reg[0]_0 (slave_rdy_cptd_sclk),
        .\SYNC[0].sync_reg_reg[1]_0 (\SYNC[0].sync_reg_reg[1] ),
        .slave_rdy_fclk_r(slave_rdy_fclk_r),
        .slave_rdy_fclk_r_reg(u_slave_rdy_cptd_sync_n_0));
  ddr4_0_ddr4_v2_2_17_cal_sync__parameterized2 u_slave_rdy_sync
       (.CLK(CLK),
        .D(slave_rdy_lvl_fclk),
        .out(slave_rdy_lvl_sclk));
  ddr4_0_ddr4_v2_2_17_cal_sync_106 u_slave_we_sync
       (.D(slave_we_r),
        .\SYNC[0].sync_reg_reg[1]_0 (\SYNC[0].sync_reg_reg[1] ),
        .out(slave_we_fclk));
endmodule

(* ABITS = "17" *) (* ADDR_WIDTH = "16" *) (* BABITS = "2" *) 
(* BGBITS = "1" *) (* BISC_EN = "1" *) (* BITS_PER_BYTE = "8" *) 
(* CA_MIRROR = "0" *) (* CKEBITS = "1" *) (* CLKFBOUT_MULT_MMCM = "17" *) 
(* CLKFBOUT_MULT_PLL = "4" *) (* CLKOUT0_DIVIDE_MMCM = "4" *) (* CLKOUT0_DIVIDE_PLL = "1" *) 
(* COMPLEX_LOOP_CNT = "4" *) (* CSBITS = "1" *) (* DATA_WIDTH = "9" *) 
(* DBYTES = "8" *) (* DDR4_REG_RC03 = "13'b0000000110000" *) (* DDR4_REG_RC04 = "13'b0000001000000" *) 
(* DDR4_REG_RC05 = "13'b0000001010000" *) (* DEBUG_MESSAGES = "1'b0" *) (* DIVCLK_DIVIDE_MMCM = "1" *) 
(* DIVCLK_DIVIDE_PLL = "1" *) (* DM_DBI_SETTING = "3'b001" *) (* DQBITS = "64" *) 
(* DQS_GATE = "1" *) (* DQS_SAMPLE_CNT = "20" *) (* DQS_TRACKING = "1" *) 
(* DRAM_WIDTH = "16" *) (* EXTRA_CMD_DELAY = "0" *) (* INIT = "2304'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010001000000001000000100000000001000000001000000001101000001000000000000000100000010100000000010000000000000000000000000000000000001000000000000000000000011000000000001100000001000000101101100100100111001001010000001000000000110000000000000000000000000000000000000001000000000000000001000000000000000000000000000000100001000000000000000000000000000000000001000101001000000100000000100000000100000010100000000001010100000001001001001001000001001001000110010000010000000001000001001001011010001000000001000000000000000111000000000000000000000000000000000000000000000000000000000000001000000001000000001000001000000010000000001000000000001000000010000000010000000000000000000000010010" *) 
(* INIT_BRAM0 = "2304'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010001000000001000000100000000001000000001000000001101000001000000000000000100000010100000000010000000000000000000000000000000000001000000000000000000000011000000000001100000001000000101101100100100111001001010000001000000000110000000000000000000000000000000000000001000000000000000001000000000000000000000000000000100001000000000000000000000000000000000001000101001000000100000000100000000100000010100000000001010100000001001001001001000001001001000110010000010000000001000001001001011010001000000001000000000000000111000000000000000000000000000000000000000000000000000000000000001000000001000000001000001000000010000000001000000000001000000010000000010000000000000000000000010010" *) (* IODELAY_QTR_CK_TAP_CNT = "41" *) (* MEM = "DDR4" *) 
(* MEMORY_CONFIGURATION = "1" *) (* MEMORY_TYPE = "2" *) (* MEMORY_VOLTAGE = "1" *) 
(* MEM_CODE = "0" *) (* MR0 = "13'b0101101100100" *) (* MR0_0 = "9'b101100100" *) 
(* MR0_1 = "9'b000000101" *) (* MR1 = "13'b0001100000001" *) (* MR1_0 = "9'b100000001" *) 
(* MR1_1 = "9'b000000001" *) (* MR2 = "13'b0000000011000" *) (* MR2_0 = "9'b000011000" *) 
(* MR2_1 = "9'b000000000" *) (* MR3 = "13'b0001000000000" *) (* MR3_0 = "9'b000000000" *) 
(* MR3_1 = "9'b000000001" *) (* MR4 = "13'b0000000000000" *) (* MR4_0 = "9'b000000000" *) 
(* MR4_1 = "9'b000000000" *) (* MR5 = "13'b0010000000000" *) (* MR5_0 = "9'b000000000" *) 
(* MR5_1 = "9'b000000010" *) (* MR6 = "13'b0100000010100" *) (* MR6_0 = "9'b000010100" *) 
(* MR6_1 = "9'b000000100" *) (* NIBBLE = "16" *) (* NUM_BRAMS = "1" *) 
(* ODTBITS = "1" *) (* ODTRD = "16'b0000000000000000" *) (* ODTWR = "16'b0000000000100001" *) 
(* ORIG_REF_NAME = "ddr4_v2_2_17_cal_xsdb_bram" *) (* PIPELINE_REG = "1" *) (* RANKS = "1" *) 
(* RDLVL = "1" *) (* RDLVL_COMPLEX = "1" *) (* RDLVL_DBI = "0" *) 
(* RDLVL_SAMPLE_CNT = "4" *) (* RD_VREF = "0" *) (* RD_VREF_PATTERN = "2" *) 
(* REG_CTRL_ON = "0" *) (* RTL_VERSION = "7" *) (* SIZE = "36864" *) 
(* SLOT0_CONFIG = "8'b00000001" *) (* SLOT0_FUNC_CS = "8'b00000001" *) (* SLOT0_ODD_CS = "8'b00000000" *) 
(* SLOT1_CONFIG = "8'b00000000" *) (* SLOT1_FUNC_CS = "8'b00000000" *) (* SLOT1_ODD_CS = "8'b00000000" *) 
(* SLOTS = "0" *) (* SPREAD_SHEET_VERSION = "16'b0000000000000010" *) (* START_ADDRESS = "18" *) 
(* S_HEIGHT = "1" *) (* USE_CS_PORT = "1" *) (* WRITE_LAT = "1" *) 
(* WRLVL = "1" *) (* WRLVL_SAMPLE_CNT = "4" *) (* WR_DQS_COMPLEX = "1" *) 
(* WR_DQS_DM_DBI = "1" *) (* WR_DQS_DQ = "1" *) (* WR_VREF = "0" *) 
(* WR_VREF_PATTERN = "2" *) (* bram_map = "yes" *) (* ddr4_reg_rc3x = "13'b0001100111001" *) 
(* mem0_init_0 = "9'b000010010" *) (* mem0_init_1 = "9'b000000000" *) (* mem0_init_10 = "9'b000000001" *) 
(* mem0_init_100 = "9'b000000000" *) (* mem0_init_101 = "9'b000000000" *) (* mem0_init_102 = "9'b000000000" *) 
(* mem0_init_103 = "9'b000000000" *) (* mem0_init_104 = "9'b000000000" *) (* mem0_init_105 = "9'b000000000" *) 
(* mem0_init_106 = "9'b000000000" *) (* mem0_init_107 = "9'b000000000" *) (* mem0_init_108 = "9'b000000000" *) 
(* mem0_init_109 = "9'b000000000" *) (* mem0_init_11 = "9'b000000001" *) (* mem0_init_110 = "9'b000000000" *) 
(* mem0_init_111 = "9'b000000000" *) (* mem0_init_112 = "9'b000000000" *) (* mem0_init_113 = "9'b000000000" *) 
(* mem0_init_114 = "9'b000000000" *) (* mem0_init_115 = "9'b000000000" *) (* mem0_init_116 = "9'b000000000" *) 
(* mem0_init_117 = "9'b000000000" *) (* mem0_init_118 = "9'b000000000" *) (* mem0_init_119 = "9'b000000000" *) 
(* mem0_init_12 = "0" *) (* mem0_init_120 = "9'b000000000" *) (* mem0_init_121 = "9'b000000000" *) 
(* mem0_init_122 = "9'b000000000" *) (* mem0_init_123 = "9'b000000000" *) (* mem0_init_124 = "9'b000000000" *) 
(* mem0_init_125 = "9'b000000000" *) (* mem0_init_126 = "9'b000000000" *) (* mem0_init_127 = "9'b000000000" *) 
(* mem0_init_128 = "9'b000000000" *) (* mem0_init_129 = "9'b000000000" *) (* mem0_init_13 = "9'b000000000" *) 
(* mem0_init_130 = "9'b000000000" *) (* mem0_init_131 = "9'b000000000" *) (* mem0_init_132 = "9'b000000000" *) 
(* mem0_init_133 = "9'b000000000" *) (* mem0_init_134 = "9'b000000000" *) (* mem0_init_135 = "9'b000000000" *) 
(* mem0_init_136 = "9'b000000000" *) (* mem0_init_137 = "9'b000000000" *) (* mem0_init_138 = "9'b000000000" *) 
(* mem0_init_139 = "9'b000000000" *) (* mem0_init_14 = "9'b000000000" *) (* mem0_init_140 = "9'b000000000" *) 
(* mem0_init_141 = "9'b000000000" *) (* mem0_init_142 = "9'b000000000" *) (* mem0_init_143 = "9'b000000000" *) 
(* mem0_init_144 = "9'b000000000" *) (* mem0_init_145 = "9'b000000000" *) (* mem0_init_146 = "9'b000000000" *) 
(* mem0_init_147 = "9'b000000000" *) (* mem0_init_148 = "9'b000000000" *) (* mem0_init_149 = "9'b000000000" *) 
(* mem0_init_15 = "9'b000000000" *) (* mem0_init_150 = "9'b000000000" *) (* mem0_init_151 = "9'b000000000" *) 
(* mem0_init_152 = "9'b000000000" *) (* mem0_init_153 = "9'b000000000" *) (* mem0_init_154 = "9'b000000000" *) 
(* mem0_init_155 = "9'b000000000" *) (* mem0_init_156 = "9'b000000000" *) (* mem0_init_157 = "9'b000000000" *) 
(* mem0_init_158 = "9'b000000000" *) (* mem0_init_159 = "9'b000000000" *) (* mem0_init_16 = "9'b000000000" *) 
(* mem0_init_160 = "9'b000000000" *) (* mem0_init_161 = "9'b000000000" *) (* mem0_init_162 = "9'b000000000" *) 
(* mem0_init_163 = "9'b000000000" *) (* mem0_init_164 = "9'b000000000" *) (* mem0_init_165 = "9'b000000000" *) 
(* mem0_init_166 = "9'b000000000" *) (* mem0_init_167 = "9'b000000000" *) (* mem0_init_168 = "9'b000000000" *) 
(* mem0_init_169 = "9'b000000000" *) (* mem0_init_17 = "9'b000000000" *) (* mem0_init_170 = "9'b000000000" *) 
(* mem0_init_171 = "9'b000000000" *) (* mem0_init_172 = "9'b000000000" *) (* mem0_init_173 = "9'b000000000" *) 
(* mem0_init_174 = "9'b000000000" *) (* mem0_init_175 = "9'b000000000" *) (* mem0_init_176 = "9'b000000000" *) 
(* mem0_init_177 = "9'b000000000" *) (* mem0_init_178 = "9'b000000000" *) (* mem0_init_179 = "9'b000000000" *) 
(* mem0_init_18 = "9'b000000111" *) (* mem0_init_180 = "9'b000000000" *) (* mem0_init_181 = "9'b000000000" *) 
(* mem0_init_182 = "9'b000000000" *) (* mem0_init_183 = "9'b000000000" *) (* mem0_init_184 = "9'b000000000" *) 
(* mem0_init_185 = "9'b000000000" *) (* mem0_init_186 = "9'b000000000" *) (* mem0_init_187 = "9'b000000000" *) 
(* mem0_init_188 = "9'b000000000" *) (* mem0_init_189 = "9'b000000000" *) (* mem0_init_19 = "9'b000000000" *) 
(* mem0_init_190 = "9'b000000000" *) (* mem0_init_191 = "9'b000000000" *) (* mem0_init_192 = "9'b000000000" *) 
(* mem0_init_193 = "9'b000000000" *) (* mem0_init_194 = "9'b000000000" *) (* mem0_init_195 = "9'b000000000" *) 
(* mem0_init_196 = "9'b000000000" *) (* mem0_init_197 = "9'b000000000" *) (* mem0_init_198 = "9'b000000000" *) 
(* mem0_init_199 = "9'b000000000" *) (* mem0_init_2 = "9'b000000000" *) (* mem0_init_20 = "9'b000000001" *) 
(* mem0_init_200 = "9'b000000000" *) (* mem0_init_201 = "9'b000000000" *) (* mem0_init_202 = "9'b000000000" *) 
(* mem0_init_203 = "9'b000000000" *) (* mem0_init_204 = "9'b000000000" *) (* mem0_init_205 = "9'b000000000" *) 
(* mem0_init_206 = "9'b000000000" *) (* mem0_init_207 = "9'b000000000" *) (* mem0_init_208 = "9'b000000000" *) 
(* mem0_init_209 = "9'b000000000" *) (* mem0_init_21 = "9'b011010001" *) (* mem0_init_210 = "9'b000000000" *) 
(* mem0_init_211 = "9'b000000000" *) (* mem0_init_212 = "9'b000000000" *) (* mem0_init_213 = "9'b000000000" *) 
(* mem0_init_214 = "9'b000000000" *) (* mem0_init_215 = "9'b000000000" *) (* mem0_init_216 = "9'b000000000" *) 
(* mem0_init_217 = "9'b000000000" *) (* mem0_init_218 = "9'b000000000" *) (* mem0_init_219 = "9'b000000000" *) 
(* mem0_init_22 = "9'b001001001" *) (* mem0_init_220 = "9'b000000000" *) (* mem0_init_221 = "9'b000000000" *) 
(* mem0_init_222 = "9'b000000000" *) (* mem0_init_223 = "9'b000000000" *) (* mem0_init_224 = "9'b000000000" *) 
(* mem0_init_225 = "9'b000000000" *) (* mem0_init_226 = "9'b000000000" *) (* mem0_init_227 = "9'b000000000" *) 
(* mem0_init_228 = "9'b000000000" *) (* mem0_init_229 = "9'b000000000" *) (* mem0_init_23 = "9'b000001000" *) 
(* mem0_init_230 = "9'b000000000" *) (* mem0_init_231 = "9'b000000000" *) (* mem0_init_232 = "9'b000000000" *) 
(* mem0_init_233 = "9'b000000000" *) (* mem0_init_234 = "9'b000000000" *) (* mem0_init_235 = "9'b000000000" *) 
(* mem0_init_236 = "9'b000000000" *) (* mem0_init_237 = "9'b000000000" *) (* mem0_init_238 = "9'b000000000" *) 
(* mem0_init_239 = "9'b000000000" *) (* mem0_init_24 = "9'b000010000" *) (* mem0_init_240 = "9'b000000000" *) 
(* mem0_init_241 = "9'b000000000" *) (* mem0_init_242 = "9'b000000000" *) (* mem0_init_243 = "9'b000000000" *) 
(* mem0_init_244 = "9'b000000000" *) (* mem0_init_245 = "9'b000000000" *) (* mem0_init_246 = "9'b000000000" *) 
(* mem0_init_247 = "9'b000000000" *) (* mem0_init_248 = "9'b000000000" *) (* mem0_init_249 = "9'b000000000" *) 
(* mem0_init_25 = "9'b000110010" *) (* mem0_init_250 = "9'b000000000" *) (* mem0_init_251 = "9'b000000000" *) 
(* mem0_init_252 = "9'b000000000" *) (* mem0_init_253 = "9'b000000000" *) (* mem0_init_254 = "9'b000000000" *) 
(* mem0_init_255 = "9'b000000000" *) (* mem0_init_26 = "9'b001001001" *) (* mem0_init_27 = "9'b001001000" *) 
(* mem0_init_28 = "9'b001001001" *) (* mem0_init_29 = "9'b010100000" *) (* mem0_init_3 = "9'b000000010" *) 
(* mem0_init_30 = "9'b000000001" *) (* mem0_init_31 = "9'b000010100" *) (* mem0_init_32 = "9'b000000100" *) 
(* mem0_init_33 = "9'b000000100" *) (* mem0_init_34 = "9'b000000100" *) (* mem0_init_35 = "9'b000101001" *) 
(* mem0_init_36 = "9'b000000001" *) (* mem0_init_37 = "9'b000000000" *) (* mem0_init_38 = "9'b000000000" *) 
(* mem0_init_39 = "9'b000000000" *) (* mem0_init_4 = "9'b000000010" *) (* mem0_init_40 = "9'b000100001" *) 
(* mem0_init_41 = "9'b000000000" *) (* mem0_init_42 = "9'b000000000" *) (* mem0_init_43 = "9'b000000000" *) 
(* mem0_init_44 = "9'b000000001" *) (* mem0_init_45 = "9'b000000000" *) (* mem0_init_46 = "9'b000000001" *) 
(* mem0_init_47 = "9'b000000000" *) (* mem0_init_48 = "9'b000000000" *) (* mem0_init_49 = "9'b000000000" *) 
(* mem0_init_5 = "1" *) (* mem0_init_50 = "9'b000110000" *) (* mem0_init_51 = "9'b001000000" *) 
(* mem0_init_52 = "9'b001010000" *) (* mem0_init_53 = "9'b100111001" *) (* mem0_init_54 = "9'b101100100" *) 
(* mem0_init_55 = "9'b000000101" *) (* mem0_init_56 = "9'b100000001" *) (* mem0_init_57 = "9'b000000001" *) 
(* mem0_init_58 = "9'b000011000" *) (* mem0_init_59 = "9'b000000000" *) (* mem0_init_6 = "9'b000001000" *) 
(* mem0_init_60 = "9'b000000000" *) (* mem0_init_61 = "9'b000000001" *) (* mem0_init_62 = "9'b000000000" *) 
(* mem0_init_63 = "9'b000000000" *) (* mem0_init_64 = "9'b000000000" *) (* mem0_init_65 = "9'b000000010" *) 
(* mem0_init_66 = "9'b000010100" *) (* mem0_init_67 = "9'b000000100" *) (* mem0_init_68 = "9'b000000000" *) 
(* mem0_init_69 = "9'b101000001" *) (* mem0_init_7 = "9'b000010000" *) (* mem0_init_70 = "9'b000000001" *) 
(* mem0_init_71 = "9'b000000001" *) (* mem0_init_72 = "9'b000000001" *) (* mem0_init_73 = "9'b000000100" *) 
(* mem0_init_74 = "9'b000000001" *) (* mem0_init_75 = "9'b000010001" *) (* mem0_init_76 = "9'b000000001" *) 
(* mem0_init_77 = "9'b000000000" *) (* mem0_init_78 = "9'b000000000" *) (* mem0_init_79 = "9'b000000000" *) 
(* mem0_init_8 = "9'b000001000" *) (* mem0_init_80 = "9'b000000000" *) (* mem0_init_81 = "9'b000000000" *) 
(* mem0_init_82 = "9'b000000000" *) (* mem0_init_83 = "9'b000000000" *) (* mem0_init_84 = "9'b000000000" *) 
(* mem0_init_85 = "9'b000000000" *) (* mem0_init_86 = "9'b000000000" *) (* mem0_init_87 = "9'b000000000" *) 
(* mem0_init_88 = "9'b000000000" *) (* mem0_init_89 = "9'b000000000" *) (* mem0_init_9 = "9'b000000001" *) 
(* mem0_init_90 = "9'b000000000" *) (* mem0_init_91 = "9'b000000000" *) (* mem0_init_92 = "9'b000000000" *) 
(* mem0_init_93 = "9'b000000000" *) (* mem0_init_94 = "9'b000000000" *) (* mem0_init_95 = "9'b000000000" *) 
(* mem0_init_96 = "9'b000000000" *) (* mem0_init_97 = "9'b000000000" *) (* mem0_init_98 = "9'b000000000" *) 
(* mem0_init_99 = "9'b000000000" *) (* nCK_PER_CLK = "4" *) (* tCK = "833" *) 
module ddr4_0_ddr4_v2_2_17_cal_xsdb_bram
   (clka,
    clkb,
    ena,
    enb,
    addra,
    addrb,
    dina,
    dinb,
    douta,
    doutb,
    wea,
    web,
    rsta,
    rstb);
  input clka;
  input clkb;
  input ena;
  input enb;
  input [15:0]addra;
  input [15:0]addrb;
  input [8:0]dina;
  input [8:0]dinb;
  output [8:0]douta;
  output [8:0]doutb;
  input wea;
  input web;
  input rsta;
  input rstb;

  wire [15:0]addra;
  wire [15:0]addrb;
  wire clka;
  wire [8:0]dina;
  wire [8:0]dinb;
  wire [8:0]douta;
  wire [8:0]doutb;
  wire ena;
  wire enb;
  wire wea;
  wire web;

  ddr4_0_ddr4_v2_2_17_cfg_mem_mod mem_inst
       (.addra(addra[11:0]),
        .addrb(addrb[11:0]),
        .clka(clka),
        .dina(dina),
        .dinb(dinb),
        .douta(douta),
        .doutb(doutb),
        .ena(ena),
        .enb(enb),
        .wea(wea),
        .web(web));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_cfg_mem_mod" *) 
module ddr4_0_ddr4_v2_2_17_cfg_mem_mod
   (doutb,
    douta,
    clka,
    enb,
    ena,
    addrb,
    addra,
    dinb,
    dina,
    web,
    wea);
  output [8:0]doutb;
  output [8:0]douta;
  input clka;
  input enb;
  input ena;
  input [11:0]addrb;
  input [11:0]addra;
  input [8:0]dinb;
  input [8:0]dina;
  input web;
  input wea;

  wire [11:0]addra;
  wire [11:0]addrb;
  wire clka;
  wire [8:0]dina;
  wire [8:0]dinb;
  wire [8:0]douta;
  wire [8:0]doutb;
  wire ena;
  wire enb;
  wire wea;
  wire web;

  ddr4_0_ddr4_v2_2_17_bram_tdp \gen_mem[0].inst 
       (.addra(addra),
        .addrb(addrb),
        .clka(clka),
        .dina(dina),
        .dinb(dinb),
        .douta(douta),
        .doutb(doutb),
        .ena(ena),
        .enb(enb),
        .wea(wea),
        .web(web));
endmodule

(* C_BUILD_REVISION = "0" *) (* C_CORE_INFO1 = "0" *) (* C_CORE_INFO2 = "0" *) 
(* C_CORE_MAJOR_VER = "3" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "16'b0000000000001000" *) 
(* C_CSE_DRV_VER = "16'b0000000000000010" *) (* C_MAJOR_VERSION = "2017" *) (* C_MINOR_VERSION = "1" *) 
(* C_NEXT_SLAVE = "16'b0000000000000000" *) (* C_PIPE_IFACE = "1" *) (* C_USE_TEST_REG = "1" *) 
(* C_XDEVICEFAMILY = "kintexu" *) (* C_XSDB_SLAVE_TYPE = "16'b0000000010000010" *) (* ORIG_REF_NAME = "ddr4_v2_2_17_chipscope_xsdb_slave" *) 
(* dont_touch = "true" *) 
module ddr4_0_ddr4_v2_2_17_chipscope_xsdb_slave
   (s_rst_o,
    s_dclk_o,
    s_den_o,
    s_dwe_o,
    s_daddr_o,
    s_di_o,
    sl_oport_o,
    s_do_i,
    sl_iport_i,
    s_drdy_i);
  output s_rst_o;
  output s_dclk_o;
  output s_den_o;
  output s_dwe_o;
  output [16:0]s_daddr_o;
  output [15:0]s_di_o;
  output [16:0]sl_oport_o;
  input [15:0]s_do_i;
  input [36:0]sl_iport_i;
  input s_drdy_i;

  wire \G_1PIPE_IFACE.s_den_r0 ;
  wire \G_1PIPE_IFACE.s_den_r_i_2_n_0 ;
  wire \G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ;
  wire [15:0]p_0_in;
  wire [15:0]reg_do;
  wire \reg_do[0]_i_2_n_0 ;
  wire \reg_do[0]_i_3_n_0 ;
  wire \reg_do[0]_i_4_n_0 ;
  wire \reg_do[10]_i_2_n_0 ;
  wire \reg_do[10]_i_3_n_0 ;
  wire \reg_do[10]_i_4_n_0 ;
  wire \reg_do[10]_i_5_n_0 ;
  wire \reg_do[11]_i_2_n_0 ;
  wire \reg_do[11]_i_3_n_0 ;
  wire \reg_do[12]_i_2_n_0 ;
  wire \reg_do[12]_i_3_n_0 ;
  wire \reg_do[13]_i_2_n_0 ;
  wire \reg_do[13]_i_3_n_0 ;
  wire \reg_do[14]_i_2_n_0 ;
  wire \reg_do[14]_i_3_n_0 ;
  wire \reg_do[15]_i_2_n_0 ;
  wire \reg_do[15]_i_3_n_0 ;
  wire \reg_do[15]_i_4_n_0 ;
  wire \reg_do[15]_i_5_n_0 ;
  wire \reg_do[15]_i_6_n_0 ;
  wire \reg_do[1]_i_2_n_0 ;
  wire \reg_do[1]_i_3_n_0 ;
  wire \reg_do[1]_i_4_n_0 ;
  wire \reg_do[2]_i_2_n_0 ;
  wire \reg_do[2]_i_3_n_0 ;
  wire \reg_do[3]_i_2_n_0 ;
  wire \reg_do[3]_i_3_n_0 ;
  wire \reg_do[3]_i_4_n_0 ;
  wire \reg_do[4]_i_2_n_0 ;
  wire \reg_do[4]_i_3_n_0 ;
  wire \reg_do[5]_i_2_n_0 ;
  wire \reg_do[5]_i_3_n_0 ;
  wire \reg_do[5]_i_4_n_0 ;
  wire \reg_do[6]_i_2_n_0 ;
  wire \reg_do[6]_i_3_n_0 ;
  wire \reg_do[6]_i_4_n_0 ;
  wire \reg_do[7]_i_2_n_0 ;
  wire \reg_do[7]_i_3_n_0 ;
  wire \reg_do[7]_i_4_n_0 ;
  wire \reg_do[7]_i_5_n_0 ;
  wire \reg_do[7]_i_6_n_0 ;
  wire \reg_do[8]_i_2_n_0 ;
  wire \reg_do[8]_i_3_n_0 ;
  wire \reg_do[8]_i_4_n_0 ;
  wire \reg_do[9]_i_2_n_0 ;
  wire \reg_do[9]_i_3_n_0 ;
  wire \reg_do[9]_i_4_n_0 ;
  wire \reg_do[9]_i_5_n_0 ;
  wire \reg_do_reg_n_0_[0] ;
  wire \reg_do_reg_n_0_[10] ;
  wire \reg_do_reg_n_0_[11] ;
  wire \reg_do_reg_n_0_[12] ;
  wire \reg_do_reg_n_0_[13] ;
  wire \reg_do_reg_n_0_[14] ;
  wire \reg_do_reg_n_0_[15] ;
  wire \reg_do_reg_n_0_[1] ;
  wire \reg_do_reg_n_0_[2] ;
  wire \reg_do_reg_n_0_[3] ;
  wire \reg_do_reg_n_0_[4] ;
  wire \reg_do_reg_n_0_[5] ;
  wire \reg_do_reg_n_0_[6] ;
  wire \reg_do_reg_n_0_[7] ;
  wire \reg_do_reg_n_0_[8] ;
  wire \reg_do_reg_n_0_[9] ;
  wire reg_drdy;
  wire reg_drdy0;
  wire [15:0]reg_test;
  wire reg_test0;
  wire [16:0]s_daddr_o;
  wire s_den_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_i;
  wire s_drdy_i;
  wire s_dwe_o;
  wire [36:0]sl_iport_i;
  wire [16:0]sl_oport_o;
  (* DONT_TOUCH *) (* UUID = "1" *) wire [127:0]uuid_stamp;

  assign s_dclk_o = sl_iport_i[1];
  assign s_rst_o = sl_iport_i[0];
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[4]),
        .Q(s_daddr_o[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[14]),
        .Q(s_daddr_o[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[15]),
        .Q(s_daddr_o[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[16]),
        .Q(s_daddr_o[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[17]),
        .Q(s_daddr_o[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[18]),
        .Q(s_daddr_o[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[19]),
        .Q(s_daddr_o[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[16] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[20]),
        .Q(s_daddr_o[16]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[5]),
        .Q(s_daddr_o[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[6]),
        .Q(s_daddr_o[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[7]),
        .Q(s_daddr_o[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[8]),
        .Q(s_daddr_o[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[9]),
        .Q(s_daddr_o[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[10]),
        .Q(s_daddr_o[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[11]),
        .Q(s_daddr_o[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[12]),
        .Q(s_daddr_o[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_daddr_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[13]),
        .Q(s_daddr_o[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT5 #(
    .INIT(32'h7FFF0000)) 
    \G_1PIPE_IFACE.s_den_r_i_1 
       (.I0(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ),
        .I1(sl_iport_i[12]),
        .I2(sl_iport_i[13]),
        .I3(sl_iport_i[14]),
        .I4(sl_iport_i[2]),
        .O(\G_1PIPE_IFACE.s_den_r0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \G_1PIPE_IFACE.s_den_r_i_2 
       (.I0(sl_iport_i[15]),
        .I1(sl_iport_i[16]),
        .I2(sl_iport_i[17]),
        .I3(sl_iport_i[18]),
        .I4(sl_iport_i[20]),
        .I5(sl_iport_i[19]),
        .O(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_den_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\G_1PIPE_IFACE.s_den_r0 ),
        .Q(s_den_o),
        .R(sl_iport_i[0]));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[21]),
        .Q(s_di_o[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[31]),
        .Q(s_di_o[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[32]),
        .Q(s_di_o[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[33]),
        .Q(s_di_o[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[34]),
        .Q(s_di_o[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[35]),
        .Q(s_di_o[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[36]),
        .Q(s_di_o[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[22]),
        .Q(s_di_o[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[23]),
        .Q(s_di_o[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[24]),
        .Q(s_di_o[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[25]),
        .Q(s_di_o[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[26]),
        .Q(s_di_o[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[27]),
        .Q(s_di_o[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[28]),
        .Q(s_di_o[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[29]),
        .Q(s_di_o[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_di_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[30]),
        .Q(s_di_o[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[0]_i_1 
       (.I0(\reg_do_reg_n_0_[0] ),
        .I1(s_do_i[0]),
        .I2(reg_drdy),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[10]_i_1 
       (.I0(\reg_do_reg_n_0_[10] ),
        .I1(s_do_i[10]),
        .I2(reg_drdy),
        .O(p_0_in[10]));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[11]_i_1 
       (.I0(\reg_do_reg_n_0_[11] ),
        .I1(s_do_i[11]),
        .I2(reg_drdy),
        .O(p_0_in[11]));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[12]_i_1 
       (.I0(\reg_do_reg_n_0_[12] ),
        .I1(s_do_i[12]),
        .I2(reg_drdy),
        .O(p_0_in[12]));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[13]_i_1 
       (.I0(\reg_do_reg_n_0_[13] ),
        .I1(s_do_i[13]),
        .I2(reg_drdy),
        .O(p_0_in[13]));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[14]_i_1 
       (.I0(\reg_do_reg_n_0_[14] ),
        .I1(s_do_i[14]),
        .I2(reg_drdy),
        .O(p_0_in[14]));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[15]_i_1 
       (.I0(\reg_do_reg_n_0_[15] ),
        .I1(s_do_i[15]),
        .I2(reg_drdy),
        .O(p_0_in[15]));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[1]_i_1 
       (.I0(\reg_do_reg_n_0_[1] ),
        .I1(s_do_i[1]),
        .I2(reg_drdy),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[2]_i_1 
       (.I0(\reg_do_reg_n_0_[2] ),
        .I1(s_do_i[2]),
        .I2(reg_drdy),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[3]_i_1 
       (.I0(\reg_do_reg_n_0_[3] ),
        .I1(s_do_i[3]),
        .I2(reg_drdy),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[4]_i_1 
       (.I0(\reg_do_reg_n_0_[4] ),
        .I1(s_do_i[4]),
        .I2(reg_drdy),
        .O(p_0_in[4]));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[5]_i_1 
       (.I0(\reg_do_reg_n_0_[5] ),
        .I1(s_do_i[5]),
        .I2(reg_drdy),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[6]_i_1 
       (.I0(\reg_do_reg_n_0_[6] ),
        .I1(s_do_i[6]),
        .I2(reg_drdy),
        .O(p_0_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[7]_i_1 
       (.I0(\reg_do_reg_n_0_[7] ),
        .I1(s_do_i[7]),
        .I2(reg_drdy),
        .O(p_0_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[8]_i_1 
       (.I0(\reg_do_reg_n_0_[8] ),
        .I1(s_do_i[8]),
        .I2(reg_drdy),
        .O(p_0_in[8]));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \G_1PIPE_IFACE.s_do_r[9]_i_1 
       (.I0(\reg_do_reg_n_0_[9] ),
        .I1(s_do_i[9]),
        .I2(reg_drdy),
        .O(p_0_in[9]));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(sl_oport_o[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[10]),
        .Q(sl_oport_o[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[11]),
        .Q(sl_oport_o[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[12]),
        .Q(sl_oport_o[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[13]),
        .Q(sl_oport_o[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[14]),
        .Q(sl_oport_o[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[15]),
        .Q(sl_oport_o[16]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(sl_oport_o[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(sl_oport_o[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(sl_oport_o[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(sl_oport_o[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[5]),
        .Q(sl_oport_o[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[6]),
        .Q(sl_oport_o[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[7]),
        .Q(sl_oport_o[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[8]),
        .Q(sl_oport_o[9]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_do_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(p_0_in[9]),
        .Q(sl_oport_o[10]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \G_1PIPE_IFACE.s_drdy_r_i_1 
       (.I0(s_drdy_i),
        .I1(reg_drdy),
        .O(\G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_drdy_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\G_1PIPE_IFACE.s_drdy_r_i_1_n_0 ),
        .Q(sl_oport_o[0]),
        .R(sl_iport_i[0]));
  FDRE #(
    .INIT(1'b0)) 
    \G_1PIPE_IFACE.s_dwe_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[3]),
        .Q(s_dwe_o),
        .R(sl_iport_i[0]));
  LUT5 #(
    .INIT(32'hBFBBAAAA)) 
    \reg_do[0]_i_1 
       (.I0(\reg_do[0]_i_2_n_0 ),
        .I1(sl_iport_i[5]),
        .I2(sl_iport_i[4]),
        .I3(reg_test[0]),
        .I4(\reg_do[10]_i_2_n_0 ),
        .O(reg_do[0]));
  LUT6 #(
    .INIT(64'h00000000AAAA33A3)) 
    \reg_do[0]_i_2 
       (.I0(\reg_do[0]_i_3_n_0 ),
        .I1(\reg_do[0]_i_4_n_0 ),
        .I2(sl_iport_i[6]),
        .I3(sl_iport_i[7]),
        .I4(sl_iport_i[8]),
        .I5(\reg_do[15]_i_4_n_0 ),
        .O(\reg_do[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[0]_i_3 
       (.I0(uuid_stamp[112]),
        .I1(uuid_stamp[96]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[80]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[64]),
        .O(\reg_do[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \reg_do[0]_i_4 
       (.I0(uuid_stamp[48]),
        .I1(uuid_stamp[32]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[16]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[0]),
        .O(\reg_do[0]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6200)) 
    \reg_do[10]_i_1 
       (.I0(sl_iport_i[4]),
        .I1(sl_iport_i[5]),
        .I2(reg_test[10]),
        .I3(\reg_do[10]_i_2_n_0 ),
        .I4(\reg_do[10]_i_3_n_0 ),
        .O(reg_do[10]));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    \reg_do[10]_i_2 
       (.I0(sl_iport_i[11]),
        .I1(sl_iport_i[10]),
        .I2(sl_iport_i[9]),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[7]),
        .I5(sl_iport_i[8]),
        .O(\reg_do[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000003333AA3A)) 
    \reg_do[10]_i_3 
       (.I0(\reg_do[10]_i_4_n_0 ),
        .I1(\reg_do[10]_i_5_n_0 ),
        .I2(sl_iport_i[6]),
        .I3(sl_iport_i[7]),
        .I4(sl_iport_i[8]),
        .I5(\reg_do[15]_i_4_n_0 ),
        .O(\reg_do[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[10]_i_4 
       (.I0(uuid_stamp[58]),
        .I1(uuid_stamp[42]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[26]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[10]),
        .O(\reg_do[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h05F5030305F5F3F3)) 
    \reg_do[10]_i_5 
       (.I0(uuid_stamp[90]),
        .I1(uuid_stamp[74]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[122]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[106]),
        .O(\reg_do[10]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h4540FFFF45404540)) 
    \reg_do[11]_i_1 
       (.I0(\reg_do[15]_i_4_n_0 ),
        .I1(\reg_do[11]_i_2_n_0 ),
        .I2(\reg_do[15]_i_2_n_0 ),
        .I3(\reg_do[11]_i_3_n_0 ),
        .I4(\reg_do[15]_i_6_n_0 ),
        .I5(reg_test[11]),
        .O(reg_do[11]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[11]_i_2 
       (.I0(uuid_stamp[59]),
        .I1(uuid_stamp[43]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[27]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[11]),
        .O(\reg_do[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[11]_i_3 
       (.I0(uuid_stamp[123]),
        .I1(uuid_stamp[107]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[91]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[75]),
        .O(\reg_do[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5404FFFF54045404)) 
    \reg_do[12]_i_1 
       (.I0(\reg_do[15]_i_4_n_0 ),
        .I1(\reg_do[12]_i_2_n_0 ),
        .I2(\reg_do[15]_i_2_n_0 ),
        .I3(\reg_do[12]_i_3_n_0 ),
        .I4(\reg_do[15]_i_6_n_0 ),
        .I5(reg_test[12]),
        .O(reg_do[12]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[12]_i_2 
       (.I0(uuid_stamp[124]),
        .I1(uuid_stamp[108]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[92]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[76]),
        .O(\reg_do[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[12]_i_3 
       (.I0(uuid_stamp[60]),
        .I1(uuid_stamp[44]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[28]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[12]),
        .O(\reg_do[12]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h4540FFFF45404540)) 
    \reg_do[13]_i_1 
       (.I0(\reg_do[15]_i_4_n_0 ),
        .I1(\reg_do[13]_i_2_n_0 ),
        .I2(\reg_do[15]_i_2_n_0 ),
        .I3(\reg_do[13]_i_3_n_0 ),
        .I4(\reg_do[15]_i_6_n_0 ),
        .I5(reg_test[13]),
        .O(reg_do[13]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[13]_i_2 
       (.I0(uuid_stamp[61]),
        .I1(uuid_stamp[45]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[29]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[13]),
        .O(\reg_do[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[13]_i_3 
       (.I0(uuid_stamp[125]),
        .I1(uuid_stamp[109]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[93]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[77]),
        .O(\reg_do[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h4540FFFF45404540)) 
    \reg_do[14]_i_1 
       (.I0(\reg_do[15]_i_4_n_0 ),
        .I1(\reg_do[14]_i_2_n_0 ),
        .I2(\reg_do[15]_i_2_n_0 ),
        .I3(\reg_do[14]_i_3_n_0 ),
        .I4(\reg_do[15]_i_6_n_0 ),
        .I5(reg_test[14]),
        .O(reg_do[14]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[14]_i_2 
       (.I0(uuid_stamp[62]),
        .I1(uuid_stamp[46]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[30]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[14]),
        .O(\reg_do[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[14]_i_3 
       (.I0(uuid_stamp[126]),
        .I1(uuid_stamp[110]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[94]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[78]),
        .O(\reg_do[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0B01FFFF0B010B01)) 
    \reg_do[15]_i_1 
       (.I0(\reg_do[15]_i_2_n_0 ),
        .I1(\reg_do[15]_i_3_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[15]_i_5_n_0 ),
        .I4(\reg_do[15]_i_6_n_0 ),
        .I5(reg_test[15]),
        .O(reg_do[15]));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \reg_do[15]_i_2 
       (.I0(sl_iport_i[8]),
        .I1(sl_iport_i[7]),
        .I2(sl_iport_i[6]),
        .O(\reg_do[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \reg_do[15]_i_3 
       (.I0(uuid_stamp[127]),
        .I1(uuid_stamp[111]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[95]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[79]),
        .O(\reg_do[15]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \reg_do[15]_i_4 
       (.I0(sl_iport_i[7]),
        .I1(sl_iport_i[8]),
        .I2(sl_iport_i[9]),
        .I3(sl_iport_i[11]),
        .I4(sl_iport_i[10]),
        .O(\reg_do[15]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[15]_i_5 
       (.I0(uuid_stamp[63]),
        .I1(uuid_stamp[47]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[31]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[15]),
        .O(\reg_do[15]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFDDDFDFDFFFFFFFF)) 
    \reg_do[15]_i_6 
       (.I0(sl_iport_i[5]),
        .I1(sl_iport_i[4]),
        .I2(sl_iport_i[8]),
        .I3(sl_iport_i[7]),
        .I4(sl_iport_i[6]),
        .I5(\reg_do[9]_i_3_n_0 ),
        .O(\reg_do[15]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h20AA20AA28AA20AA)) 
    \reg_do[1]_i_1 
       (.I0(\reg_do[1]_i_2_n_0 ),
        .I1(sl_iport_i[5]),
        .I2(\reg_do[7]_i_3_n_0 ),
        .I3(\reg_do[9]_i_3_n_0 ),
        .I4(reg_test[1]),
        .I5(sl_iport_i[4]),
        .O(reg_do[1]));
  LUT6 #(
    .INIT(64'hABABABAAAAAAABAA)) 
    \reg_do[1]_i_2 
       (.I0(\reg_do[7]_i_4_n_0 ),
        .I1(sl_iport_i[8]),
        .I2(sl_iport_i[7]),
        .I3(\reg_do[1]_i_3_n_0 ),
        .I4(sl_iport_i[6]),
        .I5(\reg_do[1]_i_4_n_0 ),
        .O(\reg_do[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[1]_i_3 
       (.I0(uuid_stamp[49]),
        .I1(uuid_stamp[33]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[17]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[1]),
        .O(\reg_do[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[1]_i_4 
       (.I0(uuid_stamp[113]),
        .I1(uuid_stamp[97]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[81]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[65]),
        .O(\reg_do[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4540FFFF45404540)) 
    \reg_do[2]_i_1 
       (.I0(\reg_do[15]_i_4_n_0 ),
        .I1(\reg_do[2]_i_2_n_0 ),
        .I2(\reg_do[15]_i_2_n_0 ),
        .I3(\reg_do[2]_i_3_n_0 ),
        .I4(\reg_do[15]_i_6_n_0 ),
        .I5(reg_test[2]),
        .O(reg_do[2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[2]_i_2 
       (.I0(uuid_stamp[50]),
        .I1(uuid_stamp[34]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[18]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[2]),
        .O(\reg_do[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[2]_i_3 
       (.I0(uuid_stamp[114]),
        .I1(uuid_stamp[98]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[82]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[66]),
        .O(\reg_do[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h4540FFFF45404540)) 
    \reg_do[3]_i_1 
       (.I0(\reg_do[15]_i_4_n_0 ),
        .I1(\reg_do[3]_i_2_n_0 ),
        .I2(\reg_do[15]_i_2_n_0 ),
        .I3(\reg_do[3]_i_3_n_0 ),
        .I4(\reg_do[3]_i_4_n_0 ),
        .I5(\reg_do[9]_i_3_n_0 ),
        .O(reg_do[3]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[3]_i_2 
       (.I0(uuid_stamp[51]),
        .I1(uuid_stamp[35]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[19]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[3]),
        .O(\reg_do[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[3]_i_3 
       (.I0(uuid_stamp[115]),
        .I1(uuid_stamp[99]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[83]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[67]),
        .O(\reg_do[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hDDDDDDDDDFFFDFDF)) 
    \reg_do[3]_i_4 
       (.I0(sl_iport_i[5]),
        .I1(sl_iport_i[4]),
        .I2(sl_iport_i[8]),
        .I3(sl_iport_i[7]),
        .I4(sl_iport_i[6]),
        .I5(reg_test[3]),
        .O(\reg_do[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4540FFFF45404540)) 
    \reg_do[4]_i_1 
       (.I0(\reg_do[15]_i_4_n_0 ),
        .I1(\reg_do[4]_i_2_n_0 ),
        .I2(\reg_do[15]_i_2_n_0 ),
        .I3(\reg_do[4]_i_3_n_0 ),
        .I4(\reg_do[15]_i_6_n_0 ),
        .I5(reg_test[4]),
        .O(reg_do[4]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[4]_i_2 
       (.I0(uuid_stamp[52]),
        .I1(uuid_stamp[36]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[20]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[4]),
        .O(\reg_do[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[4]_i_3 
       (.I0(uuid_stamp[116]),
        .I1(uuid_stamp[100]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[84]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[68]),
        .O(\reg_do[4]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6200)) 
    \reg_do[5]_i_1 
       (.I0(sl_iport_i[4]),
        .I1(sl_iport_i[5]),
        .I2(reg_test[5]),
        .I3(\reg_do[10]_i_2_n_0 ),
        .I4(\reg_do[5]_i_2_n_0 ),
        .O(reg_do[5]));
  LUT6 #(
    .INIT(64'h00000000AAFBAA08)) 
    \reg_do[5]_i_2 
       (.I0(\reg_do[5]_i_3_n_0 ),
        .I1(sl_iport_i[6]),
        .I2(sl_iport_i[7]),
        .I3(sl_iport_i[8]),
        .I4(\reg_do[5]_i_4_n_0 ),
        .I5(\reg_do[15]_i_4_n_0 ),
        .O(\reg_do[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[5]_i_3 
       (.I0(uuid_stamp[117]),
        .I1(uuid_stamp[101]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[85]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[69]),
        .O(\reg_do[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[5]_i_4 
       (.I0(uuid_stamp[53]),
        .I1(uuid_stamp[37]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[21]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[5]),
        .O(\reg_do[5]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6200)) 
    \reg_do[6]_i_1 
       (.I0(sl_iport_i[4]),
        .I1(sl_iport_i[5]),
        .I2(reg_test[6]),
        .I3(\reg_do[10]_i_2_n_0 ),
        .I4(\reg_do[6]_i_2_n_0 ),
        .O(reg_do[6]));
  LUT6 #(
    .INIT(64'h00000000AAFBAA08)) 
    \reg_do[6]_i_2 
       (.I0(\reg_do[6]_i_3_n_0 ),
        .I1(sl_iport_i[6]),
        .I2(sl_iport_i[7]),
        .I3(sl_iport_i[8]),
        .I4(\reg_do[6]_i_4_n_0 ),
        .I5(\reg_do[15]_i_4_n_0 ),
        .O(\reg_do[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[6]_i_3 
       (.I0(uuid_stamp[118]),
        .I1(uuid_stamp[102]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[86]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[70]),
        .O(\reg_do[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[6]_i_4 
       (.I0(uuid_stamp[54]),
        .I1(uuid_stamp[38]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[22]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[6]),
        .O(\reg_do[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0228AAAA0220AAAA)) 
    \reg_do[7]_i_1 
       (.I0(\reg_do[7]_i_2_n_0 ),
        .I1(sl_iport_i[5]),
        .I2(sl_iport_i[4]),
        .I3(\reg_do[7]_i_3_n_0 ),
        .I4(\reg_do[9]_i_3_n_0 ),
        .I5(reg_test[7]),
        .O(reg_do[7]));
  LUT6 #(
    .INIT(64'hABABABAAAAAAABAA)) 
    \reg_do[7]_i_2 
       (.I0(\reg_do[7]_i_4_n_0 ),
        .I1(sl_iport_i[8]),
        .I2(sl_iport_i[7]),
        .I3(\reg_do[7]_i_5_n_0 ),
        .I4(sl_iport_i[6]),
        .I5(\reg_do[7]_i_6_n_0 ),
        .O(\reg_do[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \reg_do[7]_i_3 
       (.I0(sl_iport_i[8]),
        .I1(sl_iport_i[7]),
        .I2(sl_iport_i[6]),
        .O(\reg_do[7]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \reg_do[7]_i_4 
       (.I0(sl_iport_i[10]),
        .I1(sl_iport_i[11]),
        .I2(sl_iport_i[9]),
        .I3(sl_iport_i[8]),
        .O(\reg_do[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[7]_i_5 
       (.I0(uuid_stamp[55]),
        .I1(uuid_stamp[39]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[23]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[7]),
        .O(\reg_do[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[7]_i_6 
       (.I0(uuid_stamp[119]),
        .I1(uuid_stamp[103]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[87]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[71]),
        .O(\reg_do[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h4F444F4F4F444444)) 
    \reg_do[8]_i_1 
       (.I0(\reg_do[8]_i_2_n_0 ),
        .I1(\reg_do[9]_i_3_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[8]_i_3_n_0 ),
        .I4(\reg_do[15]_i_2_n_0 ),
        .I5(\reg_do[8]_i_4_n_0 ),
        .O(reg_do[8]));
  LUT6 #(
    .INIT(64'h758A8A8A758AFF8A)) 
    \reg_do[8]_i_2 
       (.I0(sl_iport_i[8]),
        .I1(sl_iport_i[7]),
        .I2(sl_iport_i[6]),
        .I3(sl_iport_i[5]),
        .I4(sl_iport_i[4]),
        .I5(reg_test[8]),
        .O(\reg_do[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[8]_i_3 
       (.I0(uuid_stamp[56]),
        .I1(uuid_stamp[40]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[24]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[8]),
        .O(\reg_do[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[8]_i_4 
       (.I0(uuid_stamp[120]),
        .I1(uuid_stamp[104]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[88]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[72]),
        .O(\reg_do[8]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4F444F4F4F444444)) 
    \reg_do[9]_i_1 
       (.I0(\reg_do[9]_i_2_n_0 ),
        .I1(\reg_do[9]_i_3_n_0 ),
        .I2(\reg_do[15]_i_4_n_0 ),
        .I3(\reg_do[9]_i_4_n_0 ),
        .I4(\reg_do[15]_i_2_n_0 ),
        .I5(\reg_do[9]_i_5_n_0 ),
        .O(reg_do[9]));
  LUT6 #(
    .INIT(64'h758A8AFF75FF8AFF)) 
    \reg_do[9]_i_2 
       (.I0(sl_iport_i[8]),
        .I1(sl_iport_i[7]),
        .I2(sl_iport_i[6]),
        .I3(sl_iport_i[4]),
        .I4(sl_iport_i[5]),
        .I5(reg_test[9]),
        .O(\reg_do[9]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \reg_do[9]_i_3 
       (.I0(sl_iport_i[9]),
        .I1(sl_iport_i[10]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[8]),
        .I4(sl_iport_i[7]),
        .O(\reg_do[9]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[9]_i_4 
       (.I0(uuid_stamp[57]),
        .I1(uuid_stamp[41]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[25]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[9]),
        .O(\reg_do[9]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \reg_do[9]_i_5 
       (.I0(uuid_stamp[121]),
        .I1(uuid_stamp[105]),
        .I2(sl_iport_i[5]),
        .I3(uuid_stamp[89]),
        .I4(sl_iport_i[4]),
        .I5(uuid_stamp[73]),
        .O(\reg_do[9]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[0]),
        .Q(\reg_do_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[10]),
        .Q(\reg_do_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[11]),
        .Q(\reg_do_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[12]),
        .Q(\reg_do_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[13]),
        .Q(\reg_do_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[14]),
        .Q(\reg_do_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[15]),
        .Q(\reg_do_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[1]),
        .Q(\reg_do_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[2]),
        .Q(\reg_do_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[3]),
        .Q(\reg_do_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[4]),
        .Q(\reg_do_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[5]),
        .Q(\reg_do_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[6]),
        .Q(\reg_do_reg_n_0_[6] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[7]),
        .Q(\reg_do_reg_n_0_[7] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[8]),
        .Q(\reg_do_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_do_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[9]),
        .Q(\reg_do_reg_n_0_[9] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    reg_drdy_i_1
       (.I0(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ),
        .I1(sl_iport_i[12]),
        .I2(sl_iport_i[13]),
        .I3(sl_iport_i[14]),
        .I4(sl_iport_i[2]),
        .O(reg_drdy0));
  FDRE #(
    .INIT(1'b0)) 
    reg_drdy_reg
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_drdy0),
        .Q(reg_drdy),
        .R(sl_iport_i[0]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \reg_test[15]_i_1 
       (.I0(\G_1PIPE_IFACE.s_den_r_i_2_n_0 ),
        .I1(sl_iport_i[12]),
        .I2(sl_iport_i[13]),
        .I3(sl_iport_i[14]),
        .I4(sl_iport_i[3]),
        .I5(sl_iport_i[2]),
        .O(reg_test0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[21]),
        .Q(reg_test[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[31]),
        .Q(reg_test[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[32]),
        .Q(reg_test[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[33]),
        .Q(reg_test[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[34]),
        .Q(reg_test[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[35]),
        .Q(reg_test[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[36]),
        .Q(reg_test[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[22]),
        .Q(reg_test[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[23]),
        .Q(reg_test[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[24]),
        .Q(reg_test[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[25]),
        .Q(reg_test[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[26]),
        .Q(reg_test[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[27]),
        .Q(reg_test[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[28]),
        .Q(reg_test[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[29]),
        .Q(reg_test[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \reg_test_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[30]),
        .Q(reg_test[9]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[0]),
        .Q(uuid_stamp[0]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[100] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[100]),
        .Q(uuid_stamp[100]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[101] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[101]),
        .Q(uuid_stamp[101]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[102] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[102]),
        .Q(uuid_stamp[102]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[103] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[103]),
        .Q(uuid_stamp[103]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[104] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[104]),
        .Q(uuid_stamp[104]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[105] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[105]),
        .Q(uuid_stamp[105]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[106] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[106]),
        .Q(uuid_stamp[106]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[107] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[107]),
        .Q(uuid_stamp[107]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[108] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[108]),
        .Q(uuid_stamp[108]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[109] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[109]),
        .Q(uuid_stamp[109]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[10]),
        .Q(uuid_stamp[10]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[110] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[110]),
        .Q(uuid_stamp[110]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[111] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[111]),
        .Q(uuid_stamp[111]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[112] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[112]),
        .Q(uuid_stamp[112]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[113] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[113]),
        .Q(uuid_stamp[113]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[114] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[114]),
        .Q(uuid_stamp[114]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[115] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[115]),
        .Q(uuid_stamp[115]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[116] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[116]),
        .Q(uuid_stamp[116]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[117] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[117]),
        .Q(uuid_stamp[117]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[118] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[118]),
        .Q(uuid_stamp[118]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[119] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[119]),
        .Q(uuid_stamp[119]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[11]),
        .Q(uuid_stamp[11]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[120] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[120]),
        .Q(uuid_stamp[120]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[121] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[121]),
        .Q(uuid_stamp[121]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[122] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[122]),
        .Q(uuid_stamp[122]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[123] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[123]),
        .Q(uuid_stamp[123]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[124] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[124]),
        .Q(uuid_stamp[124]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[125] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[125]),
        .Q(uuid_stamp[125]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[126] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[126]),
        .Q(uuid_stamp[126]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[127] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[127]),
        .Q(uuid_stamp[127]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[12]),
        .Q(uuid_stamp[12]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[13]),
        .Q(uuid_stamp[13]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[14]),
        .Q(uuid_stamp[14]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[15]),
        .Q(uuid_stamp[15]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[16] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[16]),
        .Q(uuid_stamp[16]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[17] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[17]),
        .Q(uuid_stamp[17]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[18] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[18]),
        .Q(uuid_stamp[18]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[19] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[19]),
        .Q(uuid_stamp[19]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[1]),
        .Q(uuid_stamp[1]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[20] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[20]),
        .Q(uuid_stamp[20]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[21] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[21]),
        .Q(uuid_stamp[21]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[22] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[22]),
        .Q(uuid_stamp[22]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[23] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[23]),
        .Q(uuid_stamp[23]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[24] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[24]),
        .Q(uuid_stamp[24]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[25] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[25]),
        .Q(uuid_stamp[25]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[26] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[26]),
        .Q(uuid_stamp[26]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[27] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[27]),
        .Q(uuid_stamp[27]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[28] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[28]),
        .Q(uuid_stamp[28]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[29] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[29]),
        .Q(uuid_stamp[29]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[2]),
        .Q(uuid_stamp[2]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[30] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[30]),
        .Q(uuid_stamp[30]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[31] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[31]),
        .Q(uuid_stamp[31]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[32] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[32]),
        .Q(uuid_stamp[32]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[33] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[33]),
        .Q(uuid_stamp[33]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[34] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[34]),
        .Q(uuid_stamp[34]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[35] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[35]),
        .Q(uuid_stamp[35]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[36] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[36]),
        .Q(uuid_stamp[36]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[37] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[37]),
        .Q(uuid_stamp[37]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[38] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[38]),
        .Q(uuid_stamp[38]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[39] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[39]),
        .Q(uuid_stamp[39]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[3]),
        .Q(uuid_stamp[3]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[40] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[40]),
        .Q(uuid_stamp[40]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[41] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[41]),
        .Q(uuid_stamp[41]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[42] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[42]),
        .Q(uuid_stamp[42]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[43] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[43]),
        .Q(uuid_stamp[43]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[44] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[44]),
        .Q(uuid_stamp[44]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[45] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[45]),
        .Q(uuid_stamp[45]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[46] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[46]),
        .Q(uuid_stamp[46]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[47] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[47]),
        .Q(uuid_stamp[47]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[48] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[48]),
        .Q(uuid_stamp[48]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[49] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[49]),
        .Q(uuid_stamp[49]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[4]),
        .Q(uuid_stamp[4]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[50] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[50]),
        .Q(uuid_stamp[50]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[51] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[51]),
        .Q(uuid_stamp[51]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[52] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[52]),
        .Q(uuid_stamp[52]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[53] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[53]),
        .Q(uuid_stamp[53]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[54] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[54]),
        .Q(uuid_stamp[54]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[55] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[55]),
        .Q(uuid_stamp[55]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[56] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[56]),
        .Q(uuid_stamp[56]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[57] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[57]),
        .Q(uuid_stamp[57]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[58] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[58]),
        .Q(uuid_stamp[58]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[59] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[59]),
        .Q(uuid_stamp[59]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[5]),
        .Q(uuid_stamp[5]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[60] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[60]),
        .Q(uuid_stamp[60]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[61] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[61]),
        .Q(uuid_stamp[61]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[62] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[62]),
        .Q(uuid_stamp[62]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[63] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[63]),
        .Q(uuid_stamp[63]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[64] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[64]),
        .Q(uuid_stamp[64]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[65] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[65]),
        .Q(uuid_stamp[65]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[66] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[66]),
        .Q(uuid_stamp[66]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[67] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[67]),
        .Q(uuid_stamp[67]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[68] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[68]),
        .Q(uuid_stamp[68]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[69] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[69]),
        .Q(uuid_stamp[69]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[6]),
        .Q(uuid_stamp[6]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[70] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[70]),
        .Q(uuid_stamp[70]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[71] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[71]),
        .Q(uuid_stamp[71]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[72] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[72]),
        .Q(uuid_stamp[72]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[73] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[73]),
        .Q(uuid_stamp[73]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[74] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[74]),
        .Q(uuid_stamp[74]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[75] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[75]),
        .Q(uuid_stamp[75]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[76] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[76]),
        .Q(uuid_stamp[76]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[77] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[77]),
        .Q(uuid_stamp[77]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[78] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[78]),
        .Q(uuid_stamp[78]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[79] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[79]),
        .Q(uuid_stamp[79]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[7]),
        .Q(uuid_stamp[7]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[80] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[80]),
        .Q(uuid_stamp[80]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[81] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[81]),
        .Q(uuid_stamp[81]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[82] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[82]),
        .Q(uuid_stamp[82]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[83] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[83]),
        .Q(uuid_stamp[83]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[84] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[84]),
        .Q(uuid_stamp[84]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[85] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[85]),
        .Q(uuid_stamp[85]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[86] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[86]),
        .Q(uuid_stamp[86]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[87] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[87]),
        .Q(uuid_stamp[87]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[88] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[88]),
        .Q(uuid_stamp[88]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[89] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[89]),
        .Q(uuid_stamp[89]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[8]),
        .Q(uuid_stamp[8]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[90] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[90]),
        .Q(uuid_stamp[90]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[91] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[91]),
        .Q(uuid_stamp[91]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[92] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[92]),
        .Q(uuid_stamp[92]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[93] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[93]),
        .Q(uuid_stamp[93]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[94] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[94]),
        .Q(uuid_stamp[94]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[95] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[95]),
        .Q(uuid_stamp[95]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[96] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[96]),
        .Q(uuid_stamp[96]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[97] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[97]),
        .Q(uuid_stamp[97]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[98] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[98]),
        .Q(uuid_stamp[98]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[99] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[99]),
        .Q(uuid_stamp[99]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  (* UUID = "1" *) 
  FDRE \uuid_stamp_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(uuid_stamp[9]),
        .Q(uuid_stamp[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_infrastructure" *) 
module ddr4_0_ddr4_v2_2_17_infrastructure
   (mmcm_lock,
    addn_ui_clkout1,
    addn_ui_clkout2,
    addn_ui_clkout3,
    addn_ui_clkout4,
    dbg_clk,
    u_bufg_divClk_0,
    c0_riu_clk,
    SR,
    riu_clk_rst,
    Reset,
    pllGate,
    pllgate_reg_0,
    mmcm_clk_in,
    sys_clk_in,
    sys_rst,
    ub_initDone,
    pll_lock);
  output mmcm_lock;
  output addn_ui_clkout1;
  output addn_ui_clkout2;
  output addn_ui_clkout3;
  output addn_ui_clkout4;
  output dbg_clk;
  output u_bufg_divClk_0;
  output c0_riu_clk;
  output [0:0]SR;
  output riu_clk_rst;
  output Reset;
  output pllGate;
  output pllgate_reg_0;
  input mmcm_clk_in;
  input sys_clk_in;
  input sys_rst;
  input ub_initDone;
  input pll_lock;

  wire Reset;
  wire [0:0]SR;
  wire addn_ui_clkout1;
  wire addn_ui_clkout2;
  wire addn_ui_clkout3;
  wire addn_ui_clkout4;
  wire c0_riu_clk;
  wire [6:0]counter_div_rst0;
  wire \counter_div_rst[3]_i_1_n_0 ;
  wire \counter_div_rst[3]_i_2_n_0 ;
  wire \counter_div_rst[4]_i_1_n_0 ;
  wire \counter_div_rst[4]_i_2_n_0 ;
  wire \counter_div_rst[6]_i_1_n_0 ;
  wire \counter_div_rst[6]_i_3_n_0 ;
  wire \counter_div_rst_reg_n_0_[0] ;
  wire \counter_div_rst_reg_n_0_[1] ;
  wire \counter_div_rst_reg_n_0_[2] ;
  wire \counter_div_rst_reg_n_0_[3] ;
  wire \counter_div_rst_reg_n_0_[4] ;
  wire \counter_div_rst_reg_n_0_[5] ;
  wire \counter_div_rst_reg_n_0_[6] ;
  wire [6:0]counter_input_rst;
  wire [6:0]counter_input_rst0;
  wire \counter_input_rst[1]_i_1_n_0 ;
  wire \counter_input_rst[4]_i_1_n_0 ;
  wire \counter_input_rst[5]_i_1_n_0 ;
  wire \counter_input_rst[6]_i_1_n_0 ;
  wire \counter_input_rst[6]_i_3_n_0 ;
  wire [6:0]counter_mb_rst0;
  wire \counter_mb_rst[3]_i_1_n_0 ;
  wire \counter_mb_rst[3]_i_2_n_0 ;
  wire \counter_mb_rst[4]_i_1_n_0 ;
  wire \counter_mb_rst[4]_i_2_n_0 ;
  wire \counter_mb_rst[6]_i_1_n_0 ;
  wire \counter_mb_rst[6]_i_3_n_0 ;
  wire \counter_mb_rst_reg_n_0_[0] ;
  wire \counter_mb_rst_reg_n_0_[1] ;
  wire \counter_mb_rst_reg_n_0_[2] ;
  wire \counter_mb_rst_reg_n_0_[3] ;
  wire \counter_mb_rst_reg_n_0_[4] ;
  wire \counter_mb_rst_reg_n_0_[5] ;
  wire \counter_mb_rst_reg_n_0_[6] ;
  wire [6:0]counter_riu_rst0;
  wire \counter_riu_rst[2]_i_1_n_0 ;
  wire \counter_riu_rst[3]_i_1_n_0 ;
  wire \counter_riu_rst[3]_i_2_n_0 ;
  wire \counter_riu_rst[6]_i_1_n_0 ;
  wire \counter_riu_rst[6]_i_3_n_0 ;
  wire \counter_riu_rst_reg_n_0_[0] ;
  wire \counter_riu_rst_reg_n_0_[1] ;
  wire \counter_riu_rst_reg_n_0_[2] ;
  wire \counter_riu_rst_reg_n_0_[3] ;
  wire \counter_riu_rst_reg_n_0_[4] ;
  wire \counter_riu_rst_reg_n_0_[5] ;
  wire \counter_riu_rst_reg_n_0_[6] ;
  wire dbg_clk;
  (* RTL_KEEP = "true" *) wire input_rst_design;
  wire input_rst_design_i_1_n_0;
  wire input_rst_mmcm;
  wire input_rst_mmcm_i_1_n_0;
  wire input_rst_mmcm_i_2_n_0;
  wire mmcm_clk_in;
  wire mmcm_clkout0;
  wire mmcm_clkout1;
  wire mmcm_clkout2;
  wire mmcm_clkout3;
  wire mmcm_clkout4;
  wire mmcm_clkout5;
  wire mmcm_clkout6;
  wire mmcm_lock;
  wire [4:0]p_0_in;
  wire pllGate;
  wire [4:0]pll_gate_cnt_reg;
  wire pll_lock;
  wire pllgate_i_1_n_0;
  wire pllgate_i_2_n_0;
  wire pllgate_reg_0;
  wire riu_clk_rst;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire rst_async_mb;
  wire rst_async_mb_reg0;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire rst_async_riu_div;
  wire rst_async_riu_div_reg0;
  wire rst_div_logic;
  wire rst_div_logic_i_1_n_0;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire [2:0]rst_div_logic_r;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire [1:0]rst_div_sync_r;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire [1:0]rst_input_async;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire [3:0]rst_input_sync_r;
  wire rst_mb_logic;
  wire rst_mb_logic_i_1_n_0;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire [2:0]rst_mb_logic_r;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire [1:0]rst_mb_sync_r;
  wire rst_riu_logic;
  wire rst_riu_logic_i_1_n_0;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire [2:0]rst_riu_logic_r;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire [1:0]rst_riu_sync_r;
  wire sel;
  wire sys_clk_in;
  wire sys_clk_in_bufg;
  wire sys_rst;
  wire u_bufg_divClk_0;
  wire ub_initDone;
  wire \NLW_gen_mmcme3.u_mmcme_adv_inst_CDDCDONE_UNCONNECTED ;
  wire \NLW_gen_mmcme3.u_mmcme_adv_inst_CLKFBOUT_UNCONNECTED ;
  wire \NLW_gen_mmcme3.u_mmcme_adv_inst_CLKFBOUTB_UNCONNECTED ;
  wire \NLW_gen_mmcme3.u_mmcme_adv_inst_CLKFBSTOPPED_UNCONNECTED ;
  wire \NLW_gen_mmcme3.u_mmcme_adv_inst_CLKINSTOPPED_UNCONNECTED ;
  wire \NLW_gen_mmcme3.u_mmcme_adv_inst_CLKOUT0B_UNCONNECTED ;
  wire \NLW_gen_mmcme3.u_mmcme_adv_inst_CLKOUT1B_UNCONNECTED ;
  wire \NLW_gen_mmcme3.u_mmcme_adv_inst_CLKOUT2B_UNCONNECTED ;
  wire \NLW_gen_mmcme3.u_mmcme_adv_inst_CLKOUT3B_UNCONNECTED ;
  wire \NLW_gen_mmcme3.u_mmcme_adv_inst_DRDY_UNCONNECTED ;
  wire \NLW_gen_mmcme3.u_mmcme_adv_inst_PSDONE_UNCONNECTED ;
  wire [15:0]\NLW_gen_mmcme3.u_mmcme_adv_inst_DO_UNCONNECTED ;

  LUT2 #(
    .INIT(4'h8)) 
    \calSt[3]_i_3 
       (.I0(pllGate),
        .I1(ub_initDone),
        .O(pllgate_reg_0));
  LUT1 #(
    .INIT(2'h1)) 
    \counter_div_rst[0]_i_1 
       (.I0(\counter_div_rst_reg_n_0_[0] ),
        .O(counter_div_rst0[0]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \counter_div_rst[1]_i_1 
       (.I0(\counter_div_rst_reg_n_0_[1] ),
        .I1(\counter_div_rst_reg_n_0_[0] ),
        .O(counter_div_rst0[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \counter_div_rst[2]_i_1 
       (.I0(\counter_div_rst_reg_n_0_[2] ),
        .I1(\counter_div_rst_reg_n_0_[0] ),
        .I2(\counter_div_rst_reg_n_0_[1] ),
        .O(counter_div_rst0[2]));
  LUT5 #(
    .INIT(32'hF00FF00E)) 
    \counter_div_rst[3]_i_1 
       (.I0(\counter_div_rst_reg_n_0_[6] ),
        .I1(\counter_div_rst_reg_n_0_[4] ),
        .I2(\counter_div_rst[3]_i_2_n_0 ),
        .I3(\counter_div_rst_reg_n_0_[3] ),
        .I4(\counter_div_rst_reg_n_0_[5] ),
        .O(\counter_div_rst[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \counter_div_rst[3]_i_2 
       (.I0(\counter_div_rst_reg_n_0_[1] ),
        .I1(\counter_div_rst_reg_n_0_[0] ),
        .I2(\counter_div_rst_reg_n_0_[2] ),
        .O(\counter_div_rst[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hC3C2)) 
    \counter_div_rst[4]_i_1 
       (.I0(\counter_div_rst_reg_n_0_[6] ),
        .I1(\counter_div_rst_reg_n_0_[4] ),
        .I2(\counter_div_rst[4]_i_2_n_0 ),
        .I3(\counter_div_rst_reg_n_0_[5] ),
        .O(\counter_div_rst[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \counter_div_rst[4]_i_2 
       (.I0(\counter_div_rst_reg_n_0_[2] ),
        .I1(\counter_div_rst_reg_n_0_[0] ),
        .I2(\counter_div_rst_reg_n_0_[1] ),
        .I3(\counter_div_rst_reg_n_0_[3] ),
        .O(\counter_div_rst[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \counter_div_rst[5]_i_1 
       (.I0(\counter_div_rst_reg_n_0_[5] ),
        .I1(\counter_div_rst_reg_n_0_[3] ),
        .I2(\counter_div_rst_reg_n_0_[1] ),
        .I3(\counter_div_rst_reg_n_0_[0] ),
        .I4(\counter_div_rst_reg_n_0_[2] ),
        .I5(\counter_div_rst_reg_n_0_[4] ),
        .O(counter_div_rst0[5]));
  LUT3 #(
    .INIT(8'hAB)) 
    \counter_div_rst[6]_i_1 
       (.I0(rst_div_sync_r[1]),
        .I1(\counter_div_rst_reg_n_0_[6] ),
        .I2(\counter_div_rst[6]_i_3_n_0 ),
        .O(\counter_div_rst[6]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \counter_div_rst[6]_i_2 
       (.I0(\counter_div_rst_reg_n_0_[6] ),
        .I1(\counter_div_rst[6]_i_3_n_0 ),
        .O(counter_div_rst0[6]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \counter_div_rst[6]_i_3 
       (.I0(\counter_div_rst_reg_n_0_[4] ),
        .I1(\counter_div_rst_reg_n_0_[2] ),
        .I2(\counter_div_rst_reg_n_0_[0] ),
        .I3(\counter_div_rst_reg_n_0_[1] ),
        .I4(\counter_div_rst_reg_n_0_[3] ),
        .I5(\counter_div_rst_reg_n_0_[5] ),
        .O(\counter_div_rst[6]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_div_rst_reg[0] 
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(counter_div_rst0[0]),
        .Q(\counter_div_rst_reg_n_0_[0] ),
        .R(\counter_div_rst[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_div_rst_reg[1] 
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(counter_div_rst0[1]),
        .Q(\counter_div_rst_reg_n_0_[1] ),
        .R(\counter_div_rst[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_div_rst_reg[2] 
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(counter_div_rst0[2]),
        .Q(\counter_div_rst_reg_n_0_[2] ),
        .R(\counter_div_rst[6]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \counter_div_rst_reg[3] 
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(\counter_div_rst[3]_i_1_n_0 ),
        .Q(\counter_div_rst_reg_n_0_[3] ),
        .S(rst_div_sync_r[1]));
  FDSE #(
    .INIT(1'b1)) 
    \counter_div_rst_reg[4] 
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(\counter_div_rst[4]_i_1_n_0 ),
        .Q(\counter_div_rst_reg_n_0_[4] ),
        .S(rst_div_sync_r[1]));
  FDRE #(
    .INIT(1'b0)) 
    \counter_div_rst_reg[5] 
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(counter_div_rst0[5]),
        .Q(\counter_div_rst_reg_n_0_[5] ),
        .R(\counter_div_rst[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_div_rst_reg[6] 
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(counter_div_rst0[6]),
        .Q(\counter_div_rst_reg_n_0_[6] ),
        .R(\counter_div_rst[6]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \counter_input_rst[0]_i_1 
       (.I0(counter_input_rst[0]),
        .O(counter_input_rst0[0]));
  LUT6 #(
    .INIT(64'h9999999999999990)) 
    \counter_input_rst[1]_i_1 
       (.I0(counter_input_rst[0]),
        .I1(counter_input_rst[1]),
        .I2(\counter_input_rst[6]_i_3_n_0 ),
        .I3(counter_input_rst[5]),
        .I4(counter_input_rst[4]),
        .I5(counter_input_rst[6]),
        .O(\counter_input_rst[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \counter_input_rst[2]_i_1 
       (.I0(counter_input_rst[0]),
        .I1(counter_input_rst[1]),
        .I2(counter_input_rst[2]),
        .O(counter_input_rst0[2]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \counter_input_rst[3]_i_1 
       (.I0(counter_input_rst[1]),
        .I1(counter_input_rst[2]),
        .I2(counter_input_rst[0]),
        .I3(counter_input_rst[3]),
        .O(counter_input_rst0[3]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT4 #(
    .INIT(16'hA5A4)) 
    \counter_input_rst[4]_i_1 
       (.I0(\counter_input_rst[6]_i_3_n_0 ),
        .I1(counter_input_rst[5]),
        .I2(counter_input_rst[4]),
        .I3(counter_input_rst[6]),
        .O(\counter_input_rst[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT4 #(
    .INIT(16'hC9C8)) 
    \counter_input_rst[5]_i_1 
       (.I0(\counter_input_rst[6]_i_3_n_0 ),
        .I1(counter_input_rst[5]),
        .I2(counter_input_rst[4]),
        .I3(counter_input_rst[6]),
        .O(\counter_input_rst[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAAAB)) 
    \counter_input_rst[6]_i_1 
       (.I0(rst_input_sync_r[3]),
        .I1(\counter_input_rst[6]_i_3_n_0 ),
        .I2(counter_input_rst[5]),
        .I3(counter_input_rst[4]),
        .I4(counter_input_rst[6]),
        .O(\counter_input_rst[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \counter_input_rst[6]_i_2 
       (.I0(\counter_input_rst[6]_i_3_n_0 ),
        .I1(counter_input_rst[5]),
        .I2(counter_input_rst[4]),
        .I3(counter_input_rst[6]),
        .O(counter_input_rst0[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \counter_input_rst[6]_i_3 
       (.I0(counter_input_rst[3]),
        .I1(counter_input_rst[0]),
        .I2(counter_input_rst[2]),
        .I3(counter_input_rst[1]),
        .O(\counter_input_rst[6]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_input_rst_reg[0] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(counter_input_rst0[0]),
        .Q(counter_input_rst[0]),
        .R(\counter_input_rst[6]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \counter_input_rst_reg[1] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(\counter_input_rst[1]_i_1_n_0 ),
        .Q(counter_input_rst[1]),
        .S(rst_input_sync_r[3]));
  FDRE #(
    .INIT(1'b0)) 
    \counter_input_rst_reg[2] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(counter_input_rst0[2]),
        .Q(counter_input_rst[2]),
        .R(\counter_input_rst[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_input_rst_reg[3] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(counter_input_rst0[3]),
        .Q(counter_input_rst[3]),
        .R(\counter_input_rst[6]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \counter_input_rst_reg[4] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(\counter_input_rst[4]_i_1_n_0 ),
        .Q(counter_input_rst[4]),
        .S(rst_input_sync_r[3]));
  FDSE #(
    .INIT(1'b1)) 
    \counter_input_rst_reg[5] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(\counter_input_rst[5]_i_1_n_0 ),
        .Q(counter_input_rst[5]),
        .S(rst_input_sync_r[3]));
  FDRE #(
    .INIT(1'b0)) 
    \counter_input_rst_reg[6] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(counter_input_rst0[6]),
        .Q(counter_input_rst[6]),
        .R(\counter_input_rst[6]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \counter_mb_rst[0]_i_1 
       (.I0(\counter_mb_rst_reg_n_0_[0] ),
        .O(counter_mb_rst0[0]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \counter_mb_rst[1]_i_1 
       (.I0(\counter_mb_rst_reg_n_0_[1] ),
        .I1(\counter_mb_rst_reg_n_0_[0] ),
        .O(counter_mb_rst0[1]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \counter_mb_rst[2]_i_1 
       (.I0(\counter_mb_rst_reg_n_0_[2] ),
        .I1(\counter_mb_rst_reg_n_0_[0] ),
        .I2(\counter_mb_rst_reg_n_0_[1] ),
        .O(counter_mb_rst0[2]));
  LUT5 #(
    .INIT(32'hF00FF00E)) 
    \counter_mb_rst[3]_i_1 
       (.I0(\counter_mb_rst_reg_n_0_[6] ),
        .I1(\counter_mb_rst_reg_n_0_[4] ),
        .I2(\counter_mb_rst[3]_i_2_n_0 ),
        .I3(\counter_mb_rst_reg_n_0_[3] ),
        .I4(\counter_mb_rst_reg_n_0_[5] ),
        .O(\counter_mb_rst[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \counter_mb_rst[3]_i_2 
       (.I0(\counter_mb_rst_reg_n_0_[1] ),
        .I1(\counter_mb_rst_reg_n_0_[0] ),
        .I2(\counter_mb_rst_reg_n_0_[2] ),
        .O(\counter_mb_rst[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hC3C2)) 
    \counter_mb_rst[4]_i_1 
       (.I0(\counter_mb_rst_reg_n_0_[6] ),
        .I1(\counter_mb_rst_reg_n_0_[4] ),
        .I2(\counter_mb_rst[4]_i_2_n_0 ),
        .I3(\counter_mb_rst_reg_n_0_[5] ),
        .O(\counter_mb_rst[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \counter_mb_rst[4]_i_2 
       (.I0(\counter_mb_rst_reg_n_0_[2] ),
        .I1(\counter_mb_rst_reg_n_0_[0] ),
        .I2(\counter_mb_rst_reg_n_0_[1] ),
        .I3(\counter_mb_rst_reg_n_0_[3] ),
        .O(\counter_mb_rst[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \counter_mb_rst[5]_i_1 
       (.I0(\counter_mb_rst_reg_n_0_[5] ),
        .I1(\counter_mb_rst_reg_n_0_[3] ),
        .I2(\counter_mb_rst_reg_n_0_[1] ),
        .I3(\counter_mb_rst_reg_n_0_[0] ),
        .I4(\counter_mb_rst_reg_n_0_[2] ),
        .I5(\counter_mb_rst_reg_n_0_[4] ),
        .O(counter_mb_rst0[5]));
  LUT3 #(
    .INIT(8'hAB)) 
    \counter_mb_rst[6]_i_1 
       (.I0(rst_mb_sync_r[1]),
        .I1(\counter_mb_rst_reg_n_0_[6] ),
        .I2(\counter_mb_rst[6]_i_3_n_0 ),
        .O(\counter_mb_rst[6]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \counter_mb_rst[6]_i_2 
       (.I0(\counter_mb_rst_reg_n_0_[6] ),
        .I1(\counter_mb_rst[6]_i_3_n_0 ),
        .O(counter_mb_rst0[6]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \counter_mb_rst[6]_i_3 
       (.I0(\counter_mb_rst_reg_n_0_[4] ),
        .I1(\counter_mb_rst_reg_n_0_[2] ),
        .I2(\counter_mb_rst_reg_n_0_[0] ),
        .I3(\counter_mb_rst_reg_n_0_[1] ),
        .I4(\counter_mb_rst_reg_n_0_[3] ),
        .I5(\counter_mb_rst_reg_n_0_[5] ),
        .O(\counter_mb_rst[6]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_mb_rst_reg[0] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(counter_mb_rst0[0]),
        .Q(\counter_mb_rst_reg_n_0_[0] ),
        .R(\counter_mb_rst[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_mb_rst_reg[1] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(counter_mb_rst0[1]),
        .Q(\counter_mb_rst_reg_n_0_[1] ),
        .R(\counter_mb_rst[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_mb_rst_reg[2] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(counter_mb_rst0[2]),
        .Q(\counter_mb_rst_reg_n_0_[2] ),
        .R(\counter_mb_rst[6]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \counter_mb_rst_reg[3] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(\counter_mb_rst[3]_i_1_n_0 ),
        .Q(\counter_mb_rst_reg_n_0_[3] ),
        .S(rst_mb_sync_r[1]));
  FDSE #(
    .INIT(1'b1)) 
    \counter_mb_rst_reg[4] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(\counter_mb_rst[4]_i_1_n_0 ),
        .Q(\counter_mb_rst_reg_n_0_[4] ),
        .S(rst_mb_sync_r[1]));
  FDRE #(
    .INIT(1'b0)) 
    \counter_mb_rst_reg[5] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(counter_mb_rst0[5]),
        .Q(\counter_mb_rst_reg_n_0_[5] ),
        .R(\counter_mb_rst[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_mb_rst_reg[6] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(counter_mb_rst0[6]),
        .Q(\counter_mb_rst_reg_n_0_[6] ),
        .R(\counter_mb_rst[6]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \counter_riu_rst[0]_i_1 
       (.I0(\counter_riu_rst_reg_n_0_[0] ),
        .O(counter_riu_rst0[0]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \counter_riu_rst[1]_i_1 
       (.I0(\counter_riu_rst_reg_n_0_[1] ),
        .I1(\counter_riu_rst_reg_n_0_[0] ),
        .O(counter_riu_rst0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'hE1E1E100)) 
    \counter_riu_rst[2]_i_1 
       (.I0(\counter_riu_rst_reg_n_0_[1] ),
        .I1(\counter_riu_rst_reg_n_0_[0] ),
        .I2(\counter_riu_rst_reg_n_0_[2] ),
        .I3(\counter_riu_rst_reg_n_0_[6] ),
        .I4(\counter_riu_rst[6]_i_3_n_0 ),
        .O(\counter_riu_rst[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF00FF00E)) 
    \counter_riu_rst[3]_i_1 
       (.I0(\counter_riu_rst_reg_n_0_[6] ),
        .I1(\counter_riu_rst_reg_n_0_[4] ),
        .I2(\counter_riu_rst[3]_i_2_n_0 ),
        .I3(\counter_riu_rst_reg_n_0_[3] ),
        .I4(\counter_riu_rst_reg_n_0_[5] ),
        .O(\counter_riu_rst[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \counter_riu_rst[3]_i_2 
       (.I0(\counter_riu_rst_reg_n_0_[1] ),
        .I1(\counter_riu_rst_reg_n_0_[0] ),
        .I2(\counter_riu_rst_reg_n_0_[2] ),
        .O(\counter_riu_rst[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \counter_riu_rst[4]_i_1 
       (.I0(\counter_riu_rst_reg_n_0_[4] ),
        .I1(\counter_riu_rst_reg_n_0_[2] ),
        .I2(\counter_riu_rst_reg_n_0_[0] ),
        .I3(\counter_riu_rst_reg_n_0_[1] ),
        .I4(\counter_riu_rst_reg_n_0_[3] ),
        .O(counter_riu_rst0[4]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \counter_riu_rst[5]_i_1 
       (.I0(\counter_riu_rst_reg_n_0_[5] ),
        .I1(\counter_riu_rst_reg_n_0_[3] ),
        .I2(\counter_riu_rst_reg_n_0_[1] ),
        .I3(\counter_riu_rst_reg_n_0_[0] ),
        .I4(\counter_riu_rst_reg_n_0_[2] ),
        .I5(\counter_riu_rst_reg_n_0_[4] ),
        .O(counter_riu_rst0[5]));
  LUT3 #(
    .INIT(8'hAB)) 
    \counter_riu_rst[6]_i_1 
       (.I0(rst_riu_sync_r[1]),
        .I1(\counter_riu_rst_reg_n_0_[6] ),
        .I2(\counter_riu_rst[6]_i_3_n_0 ),
        .O(\counter_riu_rst[6]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \counter_riu_rst[6]_i_2 
       (.I0(\counter_riu_rst_reg_n_0_[6] ),
        .I1(\counter_riu_rst[6]_i_3_n_0 ),
        .O(counter_riu_rst0[6]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \counter_riu_rst[6]_i_3 
       (.I0(\counter_riu_rst_reg_n_0_[4] ),
        .I1(\counter_riu_rst_reg_n_0_[2] ),
        .I2(\counter_riu_rst_reg_n_0_[0] ),
        .I3(\counter_riu_rst_reg_n_0_[1] ),
        .I4(\counter_riu_rst_reg_n_0_[3] ),
        .I5(\counter_riu_rst_reg_n_0_[5] ),
        .O(\counter_riu_rst[6]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_riu_rst_reg[0] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(counter_riu_rst0[0]),
        .Q(\counter_riu_rst_reg_n_0_[0] ),
        .R(\counter_riu_rst[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_riu_rst_reg[1] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(counter_riu_rst0[1]),
        .Q(\counter_riu_rst_reg_n_0_[1] ),
        .R(\counter_riu_rst[6]_i_1_n_0 ));
  FDSE #(
    .INIT(1'b1)) 
    \counter_riu_rst_reg[2] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(\counter_riu_rst[2]_i_1_n_0 ),
        .Q(\counter_riu_rst_reg_n_0_[2] ),
        .S(rst_riu_sync_r[1]));
  FDSE #(
    .INIT(1'b1)) 
    \counter_riu_rst_reg[3] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(\counter_riu_rst[3]_i_1_n_0 ),
        .Q(\counter_riu_rst_reg_n_0_[3] ),
        .S(rst_riu_sync_r[1]));
  FDRE #(
    .INIT(1'b0)) 
    \counter_riu_rst_reg[4] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(counter_riu_rst0[4]),
        .Q(\counter_riu_rst_reg_n_0_[4] ),
        .R(\counter_riu_rst[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_riu_rst_reg[5] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(counter_riu_rst0[5]),
        .Q(\counter_riu_rst_reg_n_0_[5] ),
        .R(\counter_riu_rst[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \counter_riu_rst_reg[6] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(counter_riu_rst0[6]),
        .Q(\counter_riu_rst_reg_n_0_[6] ),
        .R(\counter_riu_rst[6]_i_1_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  MMCME3_ADV #(
    .BANDWIDTH("OPTIMIZED"),
    .CLKFBOUT_MULT_F(17.000000),
    .CLKFBOUT_PHASE(0.000000),
    .CLKFBOUT_USE_FINE_PS("FALSE"),
    .CLKIN1_PERIOD(14.161000),
    .CLKIN2_PERIOD(0.000000),
    .CLKOUT0_DIVIDE_F(4.000000),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT0_USE_FINE_PS("FALSE"),
    .CLKOUT1_DIVIDE(4),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUT1_USE_FINE_PS("FALSE"),
    .CLKOUT2_DIVIDE(4),
    .CLKOUT2_DUTY_CYCLE(0.500000),
    .CLKOUT2_PHASE(0.000000),
    .CLKOUT2_USE_FINE_PS("FALSE"),
    .CLKOUT3_DIVIDE(4),
    .CLKOUT3_DUTY_CYCLE(0.500000),
    .CLKOUT3_PHASE(0.000000),
    .CLKOUT3_USE_FINE_PS("FALSE"),
    .CLKOUT4_CASCADE("FALSE"),
    .CLKOUT4_DIVIDE(4),
    .CLKOUT4_DUTY_CYCLE(0.500000),
    .CLKOUT4_PHASE(0.000000),
    .CLKOUT4_USE_FINE_PS("FALSE"),
    .CLKOUT5_DIVIDE(16),
    .CLKOUT5_DUTY_CYCLE(0.500000),
    .CLKOUT5_PHASE(0.000000),
    .CLKOUT5_USE_FINE_PS("FALSE"),
    .CLKOUT6_DIVIDE(8),
    .CLKOUT6_DUTY_CYCLE(0.500000),
    .CLKOUT6_PHASE(0.000000),
    .CLKOUT6_USE_FINE_PS("FALSE"),
    .COMPENSATION("INTERNAL"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKFBIN_INVERTED(1'b0),
    .IS_CLKIN1_INVERTED(1'b0),
    .IS_CLKIN2_INVERTED(1'b0),
    .IS_CLKINSEL_INVERTED(1'b0),
    .IS_PSEN_INVERTED(1'b0),
    .IS_PSINCDEC_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .REF_JITTER1(0.010000),
    .REF_JITTER2(0.010000),
    .SS_EN("FALSE"),
    .SS_MODE("CENTER_HIGH"),
    .SS_MOD_PERIOD(10000),
    .STARTUP_WAIT("FALSE")) 
    \gen_mmcme3.u_mmcme_adv_inst 
       (.CDDCDONE(\NLW_gen_mmcme3.u_mmcme_adv_inst_CDDCDONE_UNCONNECTED ),
        .CDDCREQ(1'b0),
        .CLKFBIN(1'b0),
        .CLKFBOUT(\NLW_gen_mmcme3.u_mmcme_adv_inst_CLKFBOUT_UNCONNECTED ),
        .CLKFBOUTB(\NLW_gen_mmcme3.u_mmcme_adv_inst_CLKFBOUTB_UNCONNECTED ),
        .CLKFBSTOPPED(\NLW_gen_mmcme3.u_mmcme_adv_inst_CLKFBSTOPPED_UNCONNECTED ),
        .CLKIN1(mmcm_clk_in),
        .CLKIN2(1'b0),
        .CLKINSEL(1'b1),
        .CLKINSTOPPED(\NLW_gen_mmcme3.u_mmcme_adv_inst_CLKINSTOPPED_UNCONNECTED ),
        .CLKOUT0(mmcm_clkout0),
        .CLKOUT0B(\NLW_gen_mmcme3.u_mmcme_adv_inst_CLKOUT0B_UNCONNECTED ),
        .CLKOUT1(mmcm_clkout1),
        .CLKOUT1B(\NLW_gen_mmcme3.u_mmcme_adv_inst_CLKOUT1B_UNCONNECTED ),
        .CLKOUT2(mmcm_clkout2),
        .CLKOUT2B(\NLW_gen_mmcme3.u_mmcme_adv_inst_CLKOUT2B_UNCONNECTED ),
        .CLKOUT3(mmcm_clkout3),
        .CLKOUT3B(\NLW_gen_mmcme3.u_mmcme_adv_inst_CLKOUT3B_UNCONNECTED ),
        .CLKOUT4(mmcm_clkout4),
        .CLKOUT5(mmcm_clkout5),
        .CLKOUT6(mmcm_clkout6),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(\NLW_gen_mmcme3.u_mmcme_adv_inst_DO_UNCONNECTED [15:0]),
        .DRDY(\NLW_gen_mmcme3.u_mmcme_adv_inst_DRDY_UNCONNECTED ),
        .DWE(1'b0),
        .LOCKED(mmcm_lock),
        .PSCLK(1'b0),
        .PSDONE(\NLW_gen_mmcme3.u_mmcme_adv_inst_PSDONE_UNCONNECTED ),
        .PSEN(1'b0),
        .PSINCDEC(1'b0),
        .PWRDWN(1'b0),
        .RST(input_rst_mmcm));
  LUT4 #(
    .INIT(16'hFFFE)) 
    input_rst_design_i_1
       (.I0(counter_input_rst[6]),
        .I1(counter_input_rst[4]),
        .I2(counter_input_rst[5]),
        .I3(\counter_input_rst[6]_i_3_n_0 ),
        .O(input_rst_design_i_1_n_0));
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    input_rst_design_reg
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(input_rst_design_i_1_n_0),
        .Q(input_rst_design),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT5 #(
    .INIT(32'h000700FE)) 
    input_rst_mmcm_i_1
       (.I0(counter_input_rst[0]),
        .I1(counter_input_rst[1]),
        .I2(counter_input_rst[2]),
        .I3(input_rst_mmcm_i_2_n_0),
        .I4(counter_input_rst[3]),
        .O(input_rst_mmcm_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    input_rst_mmcm_i_2
       (.I0(counter_input_rst[5]),
        .I1(counter_input_rst[4]),
        .I2(counter_input_rst[6]),
        .O(input_rst_mmcm_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    input_rst_mmcm_reg
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(input_rst_mmcm_i_1_n_0),
        .Q(input_rst_mmcm),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h1F)) 
    pll_gate_cnt0
       (.I0(pll_gate_cnt_reg[2]),
        .I1(pll_gate_cnt_reg[3]),
        .I2(pll_gate_cnt_reg[4]),
        .O(sel));
  LUT1 #(
    .INIT(2'h1)) 
    \pll_gate_cnt[0]_i_1 
       (.I0(pll_gate_cnt_reg[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \pll_gate_cnt[1]_i_1 
       (.I0(pll_gate_cnt_reg[0]),
        .I1(pll_gate_cnt_reg[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \pll_gate_cnt[2]_i_1 
       (.I0(pll_gate_cnt_reg[0]),
        .I1(pll_gate_cnt_reg[1]),
        .I2(pll_gate_cnt_reg[2]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \pll_gate_cnt[3]_i_1 
       (.I0(pll_gate_cnt_reg[1]),
        .I1(pll_gate_cnt_reg[0]),
        .I2(pll_gate_cnt_reg[2]),
        .I3(pll_gate_cnt_reg[3]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \pll_gate_cnt[4]_i_1 
       (.I0(pll_gate_cnt_reg[2]),
        .I1(pll_gate_cnt_reg[0]),
        .I2(pll_gate_cnt_reg[1]),
        .I3(pll_gate_cnt_reg[3]),
        .I4(pll_gate_cnt_reg[4]),
        .O(p_0_in[4]));
  FDRE \pll_gate_cnt_reg[0] 
       (.C(u_bufg_divClk_0),
        .CE(sel),
        .D(p_0_in[0]),
        .Q(pll_gate_cnt_reg[0]),
        .R(SR));
  FDRE \pll_gate_cnt_reg[1] 
       (.C(u_bufg_divClk_0),
        .CE(sel),
        .D(p_0_in[1]),
        .Q(pll_gate_cnt_reg[1]),
        .R(SR));
  FDRE \pll_gate_cnt_reg[2] 
       (.C(u_bufg_divClk_0),
        .CE(sel),
        .D(p_0_in[2]),
        .Q(pll_gate_cnt_reg[2]),
        .R(SR));
  FDRE \pll_gate_cnt_reg[3] 
       (.C(u_bufg_divClk_0),
        .CE(sel),
        .D(p_0_in[3]),
        .Q(pll_gate_cnt_reg[3]),
        .R(SR));
  FDRE \pll_gate_cnt_reg[4] 
       (.C(u_bufg_divClk_0),
        .CE(sel),
        .D(p_0_in[4]),
        .Q(pll_gate_cnt_reg[4]),
        .R(SR));
  LUT2 #(
    .INIT(4'h2)) 
    pllgate_i_1
       (.I0(pllgate_i_2_n_0),
        .I1(SR),
        .O(pllgate_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00100000)) 
    pllgate_i_2
       (.I0(pll_gate_cnt_reg[1]),
        .I1(pll_gate_cnt_reg[3]),
        .I2(pll_gate_cnt_reg[4]),
        .I3(pll_gate_cnt_reg[0]),
        .I4(pll_gate_cnt_reg[2]),
        .I5(pllGate),
        .O(pllgate_i_2_n_0));
  FDRE pllgate_reg
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(pllgate_i_1_n_0),
        .Q(pllGate),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hB)) 
    rst_async_mb_i_1
       (.I0(input_rst_design),
        .I1(mmcm_lock),
        .O(rst_async_mb_reg0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    rst_async_mb_reg
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(rst_async_mb_reg0),
        .Q(rst_async_mb),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hDF)) 
    rst_async_riu_div_i_1
       (.I0(mmcm_lock),
        .I1(input_rst_design),
        .I2(pll_lock),
        .O(rst_async_riu_div_reg0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    rst_async_riu_div_reg
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(rst_async_riu_div_reg0),
        .Q(rst_async_riu_div),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    rst_div_logic_i_1
       (.I0(\counter_div_rst[6]_i_3_n_0 ),
        .I1(\counter_div_rst_reg_n_0_[6] ),
        .O(rst_div_logic_i_1_n_0));
  FDRE #(
    .INIT(1'b1)) 
    rst_div_logic_r1_reg
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(rst_div_logic_r[2]),
        .Q(SR),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \rst_div_logic_r_reg[0] 
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(rst_div_logic),
        .Q(rst_div_logic_r[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \rst_div_logic_r_reg[1] 
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(rst_div_logic_r[0]),
        .Q(rst_div_logic_r[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \rst_div_logic_r_reg[2] 
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(rst_div_logic_r[1]),
        .Q(rst_div_logic_r[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    rst_div_logic_reg
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(rst_div_logic_i_1_n_0),
        .Q(rst_div_logic),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rst_div_sync_r_reg[0] 
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(rst_async_riu_div),
        .Q(rst_div_sync_r[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rst_div_sync_r_reg[1] 
       (.C(u_bufg_divClk_0),
        .CE(1'b1),
        .D(rst_div_sync_r[0]),
        .Q(rst_div_sync_r[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  FDPE #(
    .INIT(1'b0)) 
    \rst_input_async_reg[0] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(1'b0),
        .PRE(sys_rst),
        .Q(rst_input_async[0]));
  (* ASYNC_REG *) 
  FDPE #(
    .INIT(1'b0)) 
    \rst_input_async_reg[1] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(rst_input_async[0]),
        .PRE(sys_rst),
        .Q(rst_input_async[1]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rst_input_sync_r_reg[0] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(rst_input_async[1]),
        .Q(rst_input_sync_r[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rst_input_sync_r_reg[1] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(rst_input_sync_r[0]),
        .Q(rst_input_sync_r[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rst_input_sync_r_reg[2] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(rst_input_sync_r[1]),
        .Q(rst_input_sync_r[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rst_input_sync_r_reg[3] 
       (.C(sys_clk_in_bufg),
        .CE(1'b1),
        .D(rst_input_sync_r[2]),
        .Q(rst_input_sync_r[3]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    rst_mb_logic_i_1
       (.I0(\counter_mb_rst[6]_i_3_n_0 ),
        .I1(\counter_mb_rst_reg_n_0_[6] ),
        .O(rst_mb_logic_i_1_n_0));
  FDRE #(
    .INIT(1'b1)) 
    rst_mb_logic_r1_reg
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_mb_logic_r[2]),
        .Q(Reset),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \rst_mb_logic_r_reg[0] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_mb_logic),
        .Q(rst_mb_logic_r[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \rst_mb_logic_r_reg[1] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_mb_logic_r[0]),
        .Q(rst_mb_logic_r[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \rst_mb_logic_r_reg[2] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_mb_logic_r[1]),
        .Q(rst_mb_logic_r[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    rst_mb_logic_reg
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_mb_logic_i_1_n_0),
        .Q(rst_mb_logic),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rst_mb_sync_r_reg[0] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_async_mb),
        .Q(rst_mb_sync_r[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rst_mb_sync_r_reg[1] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_mb_sync_r[0]),
        .Q(rst_mb_sync_r[1]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    rst_riu_logic_i_1
       (.I0(\counter_riu_rst[6]_i_3_n_0 ),
        .I1(\counter_riu_rst_reg_n_0_[6] ),
        .O(rst_riu_logic_i_1_n_0));
  FDRE #(
    .INIT(1'b1)) 
    rst_riu_logic_r1_reg
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_riu_logic_r[2]),
        .Q(riu_clk_rst),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \rst_riu_logic_r_reg[0] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_riu_logic),
        .Q(rst_riu_logic_r[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \rst_riu_logic_r_reg[1] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_riu_logic_r[0]),
        .Q(rst_riu_logic_r[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b1)) 
    \rst_riu_logic_r_reg[2] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_riu_logic_r[1]),
        .Q(rst_riu_logic_r[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b1)) 
    rst_riu_logic_reg
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_riu_logic_i_1_n_0),
        .Q(rst_riu_logic),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rst_riu_sync_r_reg[0] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_async_riu_div),
        .Q(rst_riu_sync_r[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rst_riu_sync_r_reg[1] 
       (.C(c0_riu_clk),
        .CE(1'b1),
        .D(rst_riu_sync_r[0]),
        .Q(rst_riu_sync_r[1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "BUFG" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  BUFGCE #(
    .CE_TYPE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE")) 
    u_bufg_addn_ui_clk_1
       (.CE(1'b1),
        .I(mmcm_clkout1),
        .O(addn_ui_clkout1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "BUFG" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  BUFGCE #(
    .CE_TYPE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE")) 
    u_bufg_addn_ui_clk_2
       (.CE(1'b1),
        .I(mmcm_clkout2),
        .O(addn_ui_clkout2));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "BUFG" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  BUFGCE #(
    .CE_TYPE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE")) 
    u_bufg_addn_ui_clk_3
       (.CE(1'b1),
        .I(mmcm_clkout3),
        .O(addn_ui_clkout3));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "BUFG" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  BUFGCE #(
    .CE_TYPE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE")) 
    u_bufg_addn_ui_clk_4
       (.CE(1'b1),
        .I(mmcm_clkout4),
        .O(addn_ui_clkout4));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "BUFG" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  BUFGCE #(
    .CE_TYPE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE")) 
    u_bufg_dbg_clk
       (.CE(1'b1),
        .I(mmcm_clkout5),
        .O(dbg_clk));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "BUFG" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  BUFGCE #(
    .CE_TYPE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE")) 
    u_bufg_divClk
       (.CE(1'b1),
        .I(mmcm_clkout0),
        .O(u_bufg_divClk_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "BUFG" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  BUFGCE #(
    .CE_TYPE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE")) 
    u_bufg_inst
       (.CE(1'b1),
        .I(sys_clk_in),
        .O(sys_clk_in_bufg));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "BUFG" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  BUFGCE #(
    .CE_TYPE("ASYNC"),
    .SIM_DEVICE("ULTRASCALE")) 
    u_bufg_riuClk
       (.CE(1'b1),
        .I(mmcm_clkout6),
        .O(c0_riu_clk));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc" *) 
module ddr4_0_ddr4_v2_2_17_mc
   (periodic_read_or_ref_block_reg,
    accept_reg,
    accept_reg_0,
    accept_reg_1,
    winAct,
    mc_ADR,
    mcCasSlot2,
    mc_BG,
    mc_BA,
    mcRdCAS,
    winAct_reg,
    winRead_reg,
    gt_data_ready_flag_nxt,
    \winPort_reg[0] ,
    winRead_reg_0,
    winRead_reg_1,
    calDone_reg,
    um_sreIss_reg,
    calDone_reg_0,
    calDone_reg_1,
    calDone_reg_2,
    calDone_reg_3,
    mcWrCAS,
    wrCAS_reg,
    cmdInjTxn_reg,
    wrCAS_reg_0,
    wrCAS_reg_1,
    wrCAS_reg_2,
    wrCAS_reg_3,
    wrCAS_reg_4,
    wrCAS_reg_5,
    wrCAS_reg_6,
    wrCAS_reg_7,
    wrCAS_reg_8,
    wrCAS_reg_9,
    wrCAS_reg_10,
    wrCAS_reg_11,
    accept_ns,
    \txn_fifo_wptr_reg[0] ,
    \buf_fifo_reg[2][0] ,
    \buf_fifo_reg[2][1] ,
    \buf_fifo_reg[2][2] ,
    \buf_fifo_reg[2][3] ,
    \buf_fifo_reg[0][4] ,
    \buf_fifo_reg[0][0] ,
    \buf_fifo_reg[0][1] ,
    \buf_fifo_reg[2][2]_0 ,
    \buf_fifo_reg[0][3] ,
    \buf_fifo_reg[2][4] ,
    \buf_fifo_reg[0][0]_0 ,
    \buf_fifo_reg[0][1]_0 ,
    \buf_fifo_reg[0][2] ,
    \buf_fifo_reg[2][3]_0 ,
    \buf_fifo_reg[0][4]_0 ,
    cmdBuf,
    mc_CKE,
    mc_CS_n,
    mc_ODT,
    um_sreIss_reg_0,
    SR,
    underfill_done_nxt,
    accept_reg_2,
    underfill_done_reg,
    underfill_done_reg_0,
    underfill_done_reg_1,
    periodic_config_gap_enable_reg,
    useAdr,
    calDone,
    p_0_in,
    \mcal_ODT_dly_reg[0][7] ,
    gt_data_ready_flag,
    gt_data_ready_flag_reg,
    cal_BA,
    \mcal_ADR_dly_reg[0][126] ,
    cal_CS_n,
    oe_0_mux_cal,
    calWrCAS,
    \wrQ_reg[0][8]_rep__1 ,
    cmd,
    row_mc_phy,
    col,
    group,
    bank,
    \buf_fifo_reg[1][0] ,
    \buf_fifo_reg[1][1] ,
    \buf_fifo_reg[1][2] ,
    \buf_fifo_reg[1][3] ,
    \buf_fifo_reg[1][4] ,
    \buf_fifo_reg[1][0]_0 ,
    \buf_fifo_reg[1][1]_0 ,
    \buf_fifo_reg[1][2]_0 ,
    \buf_fifo_reg[1][3]_0 ,
    \buf_fifo_reg[1][4]_0 ,
    \buf_fifo_reg[1][0]_1 ,
    \buf_fifo_reg[1][1]_1 ,
    \buf_fifo_reg[1][2]_1 ,
    \buf_fifo_reg[1][3]_1 ,
    \buf_fifo_reg[1][4]_1 ,
    dBufAdr,
    accept_reg_3,
    per_rd_done);
  output periodic_read_or_ref_block_reg;
  output accept_reg;
  output accept_reg_0;
  output accept_reg_1;
  output winAct;
  output [37:0]mc_ADR;
  output mcCasSlot2;
  output [2:0]mc_BG;
  output [6:0]mc_BA;
  output mcRdCAS;
  output [0:0]winAct_reg;
  output [1:0]winRead_reg;
  output gt_data_ready_flag_nxt;
  output [0:0]\winPort_reg[0] ;
  output [7:0]winRead_reg_0;
  output [3:0]winRead_reg_1;
  output calDone_reg;
  output [2:0]um_sreIss_reg;
  output calDone_reg_0;
  output calDone_reg_1;
  output calDone_reg_2;
  output [4:0]calDone_reg_3;
  output mcWrCAS;
  output [3:0]wrCAS_reg;
  output [6:0]cmdInjTxn_reg;
  output wrCAS_reg_0;
  output wrCAS_reg_1;
  output wrCAS_reg_2;
  output wrCAS_reg_3;
  output wrCAS_reg_4;
  output wrCAS_reg_5;
  output wrCAS_reg_6;
  output wrCAS_reg_7;
  output wrCAS_reg_8;
  output wrCAS_reg_9;
  output wrCAS_reg_10;
  output wrCAS_reg_11;
  output accept_ns;
  output \txn_fifo_wptr_reg[0] ;
  output \buf_fifo_reg[2][0] ;
  output \buf_fifo_reg[2][1] ;
  output \buf_fifo_reg[2][2] ;
  output \buf_fifo_reg[2][3] ;
  output \buf_fifo_reg[0][4] ;
  output \buf_fifo_reg[0][0] ;
  output \buf_fifo_reg[0][1] ;
  output \buf_fifo_reg[2][2]_0 ;
  output \buf_fifo_reg[0][3] ;
  output \buf_fifo_reg[2][4] ;
  output \buf_fifo_reg[0][0]_0 ;
  output \buf_fifo_reg[0][1]_0 ;
  output \buf_fifo_reg[0][2] ;
  output \buf_fifo_reg[2][3]_0 ;
  output \buf_fifo_reg[0][4]_0 ;
  output [19:0]cmdBuf;
  output [1:0]mc_CKE;
  output [0:0]mc_CS_n;
  output [1:0]mc_ODT;
  input um_sreIss_reg_0;
  input [0:0]SR;
  input underfill_done_nxt;
  input [0:0]accept_reg_2;
  input underfill_done_reg;
  input underfill_done_reg_0;
  input underfill_done_reg_1;
  input periodic_config_gap_enable_reg;
  input useAdr;
  input calDone;
  input [0:0]p_0_in;
  input \mcal_ODT_dly_reg[0][7] ;
  input gt_data_ready_flag;
  input gt_data_ready_flag_reg;
  input [0:0]cal_BA;
  input [7:0]\mcal_ADR_dly_reg[0][126] ;
  input [3:0]cal_CS_n;
  input [0:0]oe_0_mux_cal;
  input calWrCAS;
  input [3:0]\wrQ_reg[0][8]_rep__1 ;
  input [2:0]cmd;
  input [16:0]row_mc_phy;
  input [6:0]col;
  input [0:0]group;
  input [1:0]bank;
  input \buf_fifo_reg[1][0] ;
  input \buf_fifo_reg[1][1] ;
  input \buf_fifo_reg[1][2] ;
  input \buf_fifo_reg[1][3] ;
  input \buf_fifo_reg[1][4] ;
  input \buf_fifo_reg[1][0]_0 ;
  input \buf_fifo_reg[1][1]_0 ;
  input \buf_fifo_reg[1][2]_0 ;
  input \buf_fifo_reg[1][3]_0 ;
  input \buf_fifo_reg[1][4]_0 ;
  input \buf_fifo_reg[1][0]_1 ;
  input \buf_fifo_reg[1][1]_1 ;
  input \buf_fifo_reg[1][2]_1 ;
  input \buf_fifo_reg[1][3]_1 ;
  input \buf_fifo_reg[1][4]_1 ;
  input [4:0]dBufAdr;
  input accept_reg_3;
  input per_rd_done;

  wire [0:0]SR;
  wire accept_ns;
  wire accept_reg;
  wire accept_reg_0;
  wire accept_reg_1;
  wire [0:0]accept_reg_2;
  wire accept_reg_3;
  wire [3:3]actReq;
  wire actReqR;
  wire [1:0]bank;
  wire \bgr[0].u_ddr_mc_group_n_29 ;
  wire \bgr[0].u_ddr_mc_group_n_35 ;
  wire \bgr[1].u_ddr_mc_group_n_38 ;
  wire \bgr[1].u_ddr_mc_group_n_4 ;
  wire \bgr[1].u_ddr_mc_group_n_5 ;
  wire \bgr[1].u_ddr_mc_group_n_6 ;
  wire \bgr[1].u_ddr_mc_group_n_7 ;
  wire \bgr[1].u_ddr_mc_group_n_8 ;
  wire \bgr[2].u_ddr_mc_group_n_3 ;
  wire \bgr[2].u_ddr_mc_group_n_32 ;
  wire \bgr[2].u_ddr_mc_group_n_4 ;
  wire \bgr[2].u_ddr_mc_group_n_5 ;
  wire \bgr[2].u_ddr_mc_group_n_6 ;
  wire \bgr[2].u_ddr_mc_group_n_7 ;
  wire \bgr[3].u_ddr_mc_group_n_3 ;
  wire \bgr[3].u_ddr_mc_group_n_42 ;
  wire \bgr[3].u_ddr_mc_group_n_5 ;
  wire \bgr[3].u_ddr_mc_group_n_6 ;
  wire \bgr[3].u_ddr_mc_group_n_7 ;
  wire \bgr[3].u_ddr_mc_group_n_8 ;
  wire block_reads;
  wire block_writes;
  wire \buf_fifo_reg[0][0] ;
  wire \buf_fifo_reg[0][0]_0 ;
  wire \buf_fifo_reg[0][1] ;
  wire \buf_fifo_reg[0][1]_0 ;
  wire \buf_fifo_reg[0][2] ;
  wire \buf_fifo_reg[0][3] ;
  wire \buf_fifo_reg[0][4] ;
  wire \buf_fifo_reg[0][4]_0 ;
  wire \buf_fifo_reg[1][0] ;
  wire \buf_fifo_reg[1][0]_0 ;
  wire \buf_fifo_reg[1][0]_1 ;
  wire \buf_fifo_reg[1][1] ;
  wire \buf_fifo_reg[1][1]_0 ;
  wire \buf_fifo_reg[1][1]_1 ;
  wire \buf_fifo_reg[1][2] ;
  wire \buf_fifo_reg[1][2]_0 ;
  wire \buf_fifo_reg[1][2]_1 ;
  wire \buf_fifo_reg[1][3] ;
  wire \buf_fifo_reg[1][3]_0 ;
  wire \buf_fifo_reg[1][3]_1 ;
  wire \buf_fifo_reg[1][4] ;
  wire \buf_fifo_reg[1][4]_0 ;
  wire \buf_fifo_reg[1][4]_1 ;
  wire \buf_fifo_reg[2][0] ;
  wire \buf_fifo_reg[2][1] ;
  wire \buf_fifo_reg[2][2] ;
  wire \buf_fifo_reg[2][2]_0 ;
  wire \buf_fifo_reg[2][3] ;
  wire \buf_fifo_reg[2][3]_0 ;
  wire \buf_fifo_reg[2][4] ;
  wire calDone;
  wire calDone_reg;
  wire calDone_reg_0;
  wire calDone_reg_1;
  wire calDone_reg_2;
  wire [4:0]calDone_reg_3;
  wire calWrCAS;
  wire [0:0]cal_BA;
  wire [3:0]cal_CS_n;
  wire clrReq1;
  wire clrReq13_out;
  wire clrReq15_out;
  wire clrReq17_out;
  wire [2:0]cmd;
  wire [3:0]cmdAP;
  wire [7:0]cmdBank;
  wire [7:0]cmdBankP;
  wire [19:0]cmdBuf;
  wire [39:3]cmdCol;
  wire [6:0]cmdGroup;
  wire [6:0]cmdGroupP;
  wire [0:0]cmdInjTxn;
  wire [6:0]cmdInjTxn_reg;
  wire [67:0]cmdRow;
  wire [7:0]cmd_bank_cas;
  wire [6:0]cmd_group_cas;
  wire [6:0]col;
  wire [4:0]dBufAdr;
  wire d_prevGroup;
  wire [2:0]grAccept_ns;
  wire [0:0]group;
  wire gt_data_ready_flag;
  wire gt_data_ready_flag_nxt;
  wire gt_data_ready_flag_reg;
  wire int_refReq_i_1_n_0;
  wire int_sreCkeDis;
  wire \int_sreCkeDis[0]_i_1_n_0 ;
  wire interval_counter_reset;
  wire mcCasSlot2;
  wire mcRdCAS;
  wire mcWrCAS;
  wire [37:0]mc_ADR;
  wire [6:0]mc_BA;
  wire [2:0]mc_BG;
  wire [1:0]mc_CKE;
  wire [0:0]mc_CS_n;
  wire [1:0]mc_ODT;
  wire [7:0]\mcal_ADR_dly_reg[0][126] ;
  wire \mcal_ODT_dly_reg[0][7] ;
  wire [0:0]oe_0_mux_cal;
  wire [4:4]\outstanding_act_slr_reg[0]_244 ;
  wire [0:0]p_0_in;
  wire p_0_in0_in;
  wire p_0_in1_in;
  wire p_0_in5_in;
  wire p_0_in9_in;
  wire [1:0]p_0_in__10;
  wire [1:0]p_0_in__14;
  wire [1:0]p_0_in__26;
  wire [1:0]p_0_in__30;
  wire [1:0]p_0_in__42;
  wire [1:0]p_0_in__46;
  wire [1:0]p_0_in__58;
  wire [1:0]p_0_in__62;
  wire per_block_ref;
  wire per_cas_block_req;
  wire per_rd_accept_0;
  wire per_rd_done;
  wire per_rd_req;
  wire periodic_config_gap_enable_reg;
  wire periodic_read_or_ref_block_reg;
  wire preIss;
  wire preReqR;
  wire prevCmdAP;
  wire prevGroup;
  wire \prevGroup[0]_i_1_n_0 ;
  wire rdReqR;
  wire [3:0]refOK;
  wire refReq;
  wire ref_req_dly4;
  wire [16:0]row_mc_phy;
  (* RTL_KEEP = "true" *) wire rst_r1;
  wire [2:2]rtw;
  wire rtw_okr;
  wire [1:0]\timerWTP_reg[0][0][0][0]_234 ;
  wire [1:0]\timerWTP_reg[0][0][0][1]_232 ;
  wire [1:0]\timerWTP_reg[0][0][0][2]_230 ;
  wire [1:0]\timerWTP_reg[0][0][0][3]_228 ;
  wire [1:0]\timerWTP_reg[0][0][1][0]_233 ;
  wire [1:0]\timerWTP_reg[0][0][1][1]_231 ;
  wire [1:0]\timerWTP_reg[0][0][1][2]_229 ;
  wire [1:0]\timerWTP_reg[0][0][1][3]_227 ;
  wire tranSentC;
  wire \txn_fifo_wptr_reg[0] ;
  wire [0:0]\u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_fabric ;
  wire u_ddr_mc_arb_a_n_1;
  wire u_ddr_mc_arb_a_n_10;
  wire u_ddr_mc_arb_a_n_11;
  wire u_ddr_mc_arb_a_n_12;
  wire u_ddr_mc_arb_a_n_13;
  wire u_ddr_mc_arb_a_n_14;
  wire u_ddr_mc_arb_a_n_36;
  wire u_ddr_mc_arb_a_n_37;
  wire u_ddr_mc_arb_a_n_38;
  wire u_ddr_mc_arb_a_n_39;
  wire u_ddr_mc_arb_a_n_40;
  wire u_ddr_mc_arb_a_n_41;
  wire u_ddr_mc_arb_a_n_42;
  wire u_ddr_mc_arb_a_n_43;
  wire u_ddr_mc_arb_a_n_6;
  wire u_ddr_mc_arb_a_n_7;
  wire u_ddr_mc_arb_a_n_8;
  wire u_ddr_mc_arb_a_n_9;
  wire u_ddr_mc_arb_c_n_10;
  wire u_ddr_mc_arb_c_n_11;
  wire u_ddr_mc_arb_c_n_12;
  wire u_ddr_mc_arb_c_n_13;
  wire u_ddr_mc_arb_c_n_14;
  wire u_ddr_mc_arb_c_n_15;
  wire u_ddr_mc_arb_c_n_3;
  wire u_ddr_mc_arb_c_n_69;
  wire u_ddr_mc_arb_c_n_72;
  wire u_ddr_mc_arb_c_n_8;
  wire u_ddr_mc_arb_c_n_9;
  wire u_ddr_mc_arb_mux_p_n_9;
  wire u_ddr_mc_cmd_mux_a_n_0;
  wire u_ddr_mc_cmd_mux_a_n_10;
  wire u_ddr_mc_cmd_mux_a_n_11;
  wire u_ddr_mc_cmd_mux_a_n_12;
  wire u_ddr_mc_cmd_mux_a_n_13;
  wire u_ddr_mc_cmd_mux_a_n_14;
  wire u_ddr_mc_cmd_mux_a_n_15;
  wire u_ddr_mc_cmd_mux_a_n_16;
  wire u_ddr_mc_cmd_mux_a_n_17;
  wire u_ddr_mc_cmd_mux_a_n_18;
  wire u_ddr_mc_cmd_mux_a_n_19;
  wire u_ddr_mc_cmd_mux_a_n_3;
  wire u_ddr_mc_cmd_mux_a_n_4;
  wire u_ddr_mc_cmd_mux_a_n_5;
  wire u_ddr_mc_cmd_mux_a_n_6;
  wire u_ddr_mc_cmd_mux_a_n_7;
  wire u_ddr_mc_cmd_mux_a_n_8;
  wire u_ddr_mc_cmd_mux_a_n_9;
  wire u_ddr_mc_cmd_mux_c_n_0;
  wire u_ddr_mc_cmd_mux_c_n_1;
  wire u_ddr_mc_cmd_mux_c_n_10;
  wire u_ddr_mc_cmd_mux_c_n_11;
  wire u_ddr_mc_cmd_mux_c_n_12;
  wire u_ddr_mc_cmd_mux_c_n_13;
  wire u_ddr_mc_cmd_mux_c_n_14;
  wire u_ddr_mc_cmd_mux_c_n_15;
  wire u_ddr_mc_cmd_mux_c_n_16;
  wire u_ddr_mc_ctl_n_21;
  wire u_ddr_mc_ctl_n_22;
  wire u_ddr_mc_ctl_n_27;
  wire u_ddr_mc_ctl_n_3;
  wire [20:20]\u_ddr_mc_odt/odt_shift_nxt[0]_189 ;
  wire [2:0]\u_ddr_mc_odt/p_0_in ;
  wire u_ddr_mc_rd_wr_n_5;
  wire u_ddr_mc_ref_n_14;
  wire u_ddr_mc_ref_n_15;
  wire u_ddr_mc_ref_n_16;
  wire u_ddr_mc_ref_n_17;
  wire u_ddr_mc_ref_n_18;
  wire u_ddr_mc_ref_n_5;
  wire u_ddr_mc_ref_n_6;
  wire u_ddr_mc_ref_n_7;
  wire u_ddr_mc_ref_n_8;
  wire u_ddr_mc_ref_n_9;
  wire um_sreCkeDis;
  wire \um_sreCkeDis[0]_i_1_n_0 ;
  wire [2:0]um_sreIss_reg;
  wire um_sreIss_reg_0;
  wire underfill_done_nxt;
  wire underfill_done_reg;
  wire underfill_done_reg_0;
  wire underfill_done_reg_1;
  wire useAdr;
  wire [4:4]user_fsm;
  wire winAP;
  wire winAct;
  wire [0:0]winAct_reg;
  wire [1:1]winBankA;
  wire [0:0]winGroupA;
  wire [0:0]winGroupC;
  wire [3:0]winPortA;
  wire [3:0]winPortC;
  wire [0:0]\winPort_reg[0] ;
  wire winRead;
  wire [1:0]winRead_reg;
  wire [7:0]winRead_reg_0;
  wire [3:0]winRead_reg_1;
  wire winWrite;
  wire [0:0]win_group_cas;
  wire [3:0]wrCAS_reg;
  wire wrCAS_reg_0;
  wire wrCAS_reg_1;
  wire wrCAS_reg_10;
  wire wrCAS_reg_11;
  wire wrCAS_reg_2;
  wire wrCAS_reg_3;
  wire wrCAS_reg_4;
  wire wrCAS_reg_5;
  wire wrCAS_reg_6;
  wire wrCAS_reg_7;
  wire wrCAS_reg_8;
  wire wrCAS_reg_9;
  wire [3:0]\wrQ_reg[0][8]_rep__1 ;
  wire wrReqR;
  wire wtr_oklr;
  wire wtr_oksr;
  wire [0:0]wtrl;

  ddr4_0_ddr4_v2_2_17_mc_group \bgr[0].u_ddr_mc_group 
       (.\FSM_sequential_grSt_reg[0]_0 (p_0_in0_in),
        .Q({cmdRow[16:0],cmdGroup[0],cmdBank[1:0]}),
        .SR(SR),
        .actReqR(actReqR),
        .actReqR_reg_0(winPortA[0]),
        .bank(bank),
        .\cas_fifo_rptr_reg[0]_0 (winPortC[0]),
        .clrReq13_out(clrReq13_out),
        .cmd(cmd),
        .cmdAP(cmdAP[0]),
        .\cmdBankP_reg[1]_0 (cmdBankP[1:0]),
        .cmdBuf(cmdBuf[4:0]),
        .\cmdCol_reg[9]_0 (cmdCol[9:3]),
        .cmdGroupP(cmdGroupP[0]),
        .cmdInjTxn(cmdInjTxn),
        .cmdRmw_reg_0(\bgr[0].u_ddr_mc_group_n_29 ),
        .\cmd_bank_cas_reg[1]_0 (cmd_bank_cas[1:0]),
        .cmd_group_cas(cmd_group_cas[0]),
        .col(col),
        .dBufAdr(dBufAdr),
        .grAccept_ns(grAccept_ns[0]),
        .group(group),
        .per_rd_accept_0(per_rd_accept_0),
        .per_rd_accept_reg_0(um_sreIss_reg_0),
        .per_rd_req(per_rd_req),
        .preReqR(preReqR),
        .rdReqR(rdReqR),
        .refOK(refOK[0]),
        .refReq(refReq),
        .ref_req_dly4(ref_req_dly4),
        .ref_req_dly4_reg_0(\bgr[0].u_ddr_mc_group_n_35 ),
        .ref_req_dly4_reg_1(periodic_read_or_ref_block_reg),
        .row_mc_phy(row_mc_phy),
        .tranSentC(tranSentC),
        .\txn_fifo_wptr_reg[0]_0 (periodic_config_gap_enable_reg),
        .underfill_done_nxt(underfill_done_nxt),
        .useAdr(useAdr),
        .wrReqR(wrReqR));
  ddr4_0_ddr4_v2_2_17_mc_group_9 \bgr[1].u_ddr_mc_group 
       (.Q({cmdRow[33:17],cmdGroup[2],cmdBank[3:2]}),
        .SR(SR),
        .accept_reg_0(accept_reg),
        .accept_reg_1(accept_reg_3),
        .actReqR_reg_0(\bgr[1].u_ddr_mc_group_n_5 ),
        .actReqR_reg_1(winPortA[1]),
        .bank(bank),
        .\buf_fifo_reg[0][4]_0 (\buf_fifo_reg[0][4] ),
        .\buf_fifo_reg[1][0]_0 (\buf_fifo_reg[1][0]_1 ),
        .\buf_fifo_reg[1][1]_0 (\buf_fifo_reg[1][1]_1 ),
        .\buf_fifo_reg[1][2]_0 (\buf_fifo_reg[1][2]_1 ),
        .\buf_fifo_reg[1][3]_0 (\buf_fifo_reg[1][3]_1 ),
        .\buf_fifo_reg[1][4]_0 (\buf_fifo_reg[1][4]_1 ),
        .\buf_fifo_reg[2][0]_0 (\buf_fifo_reg[2][0] ),
        .\buf_fifo_reg[2][1]_0 (\buf_fifo_reg[2][1] ),
        .\buf_fifo_reg[2][2]_0 (\buf_fifo_reg[2][2] ),
        .\buf_fifo_reg[2][3]_0 (\buf_fifo_reg[2][3] ),
        .\cas_fifo_rptr_reg[0]_0 (winPortC[1]),
        .clrReq15_out(clrReq15_out),
        .cmd(cmd),
        .cmdAP(cmdAP[1]),
        .\cmdBankP_reg[1]_0 (cmdBankP[3:2]),
        .cmdBuf(cmdBuf[9:5]),
        .\cmdCol_reg[9]_0 (cmdCol[19:13]),
        .cmdGroupP(cmdGroupP[2]),
        .\cmdGroupP_reg[0]_0 (um_sreIss_reg_0),
        .cmdRmw_reg_0(\bgr[1].u_ddr_mc_group_n_8 ),
        .\cmd_bank_cas_reg[1]_0 (cmd_bank_cas[3:2]),
        .cmd_group_cas(cmd_group_cas[2]),
        .col(col),
        .grAccept_ns(grAccept_ns[1]),
        .group(group),
        .preReqR_reg_0(\bgr[1].u_ddr_mc_group_n_6 ),
        .preReqR_reg_1(p_0_in1_in),
        .rdReqR_reg_0(\bgr[1].u_ddr_mc_group_n_7 ),
        .refOK(refOK[1]),
        .refOK_reg_0(\bgr[1].u_ddr_mc_group_n_38 ),
        .refReq(refReq),
        .ref_req_dly4(ref_req_dly4),
        .row_mc_phy(row_mc_phy),
        .tranSentC(tranSentC),
        .\txn_fifo_wptr_reg[0]_0 (periodic_config_gap_enable_reg),
        .\um_wait_cntr[2]_i_3 ({refOK[3:2],refOK[0]}),
        .underfill_done_reg_0(underfill_done_reg),
        .useAdr(useAdr),
        .wrReqR_reg_0(\bgr[1].u_ddr_mc_group_n_4 ));
  ddr4_0_ddr4_v2_2_17_mc_group_10 \bgr[2].u_ddr_mc_group 
       (.\FSM_sequential_grSt_reg[0]_0 (winPortA[2]),
        .\FSM_sequential_grSt_reg[0]_1 (\bgr[0].u_ddr_mc_group_n_35 ),
        .Q({cmdRow[50:34],cmdGroup[4],cmdBank[5:4]}),
        .SR(SR),
        .accept_reg_0(accept_reg_0),
        .actReqR_reg_0(\bgr[2].u_ddr_mc_group_n_4 ),
        .bank(bank),
        .\buf_fifo_reg[0][0]_0 (\buf_fifo_reg[0][0] ),
        .\buf_fifo_reg[0][1]_0 (\buf_fifo_reg[0][1] ),
        .\buf_fifo_reg[0][3]_0 (\buf_fifo_reg[0][3] ),
        .\buf_fifo_reg[1][0]_0 (\buf_fifo_reg[1][0]_0 ),
        .\buf_fifo_reg[1][1]_0 (\buf_fifo_reg[1][1]_0 ),
        .\buf_fifo_reg[1][2]_0 (\buf_fifo_reg[1][2]_0 ),
        .\buf_fifo_reg[1][3]_0 (\buf_fifo_reg[1][3]_0 ),
        .\buf_fifo_reg[1][4]_0 (\buf_fifo_reg[1][4]_0 ),
        .\buf_fifo_reg[2][2]_0 (\buf_fifo_reg[2][2]_0 ),
        .\buf_fifo_reg[2][4]_0 (\buf_fifo_reg[2][4] ),
        .calDone_gated_reg(\bgr[2].u_ddr_mc_group_n_32 ),
        .\cas_fifo_rptr_reg[0]_0 (winPortC[2]),
        .clrReq17_out(clrReq17_out),
        .cmd(cmd),
        .cmdAP(cmdAP[2]),
        .\cmdBankP_reg[1]_0 (cmdBankP[5:4]),
        .cmdBuf(cmdBuf[14:10]),
        .\cmdCol_reg[9]_0 (cmdCol[29:23]),
        .cmdGroupP(cmdGroupP[4]),
        .cmdRmw_reg_0(\bgr[2].u_ddr_mc_group_n_7 ),
        .\cmd_bank_cas_reg[1]_0 (cmd_bank_cas[5:4]),
        .cmd_group_cas(cmd_group_cas[4]),
        .col(col),
        .grAccept_ns(grAccept_ns[2]),
        .group(group),
        .preReqR_reg_0(\bgr[2].u_ddr_mc_group_n_5 ),
        .preReqR_reg_1(p_0_in5_in),
        .rdReqR_reg_0(\bgr[2].u_ddr_mc_group_n_6 ),
        .refOK_reg_0(refOK[2]),
        .refReq(refReq),
        .ref_req_dly4(ref_req_dly4),
        .row_mc_phy(row_mc_phy),
        .rst_r1_reg_0(um_sreIss_reg_0),
        .tranSentC(tranSentC),
        .\txn_fifo_wptr_reg[0]_0 (periodic_config_gap_enable_reg),
        .underfill_done_reg_0(underfill_done_reg_0),
        .useAdr(useAdr),
        .wrReqR_reg_0(\bgr[2].u_ddr_mc_group_n_3 ));
  ddr4_0_ddr4_v2_2_17_mc_group_11 \bgr[3].u_ddr_mc_group 
       (.\FSM_sequential_grSt_reg[0]_0 (winPortA[3]),
        .\FSM_sequential_grSt_reg[0]_1 (\bgr[0].u_ddr_mc_group_n_35 ),
        .Q({cmdRow[67:51],cmdGroup[6],cmdBank[7:6]}),
        .SR(SR),
        .accept_ns(accept_ns),
        .accept_reg_0(accept_reg_1),
        .accept_reg_1(accept_reg_2),
        .accept_reg_2(\bgr[2].u_ddr_mc_group_n_32 ),
        .actReq(actReq),
        .actReqR_reg_0(\bgr[3].u_ddr_mc_group_n_5 ),
        .app_rdy_r_reg(grAccept_ns[1:0]),
        .bank(bank),
        .\buf_fifo_reg[0][0]_0 (\buf_fifo_reg[0][0]_0 ),
        .\buf_fifo_reg[0][1]_0 (\buf_fifo_reg[0][1]_0 ),
        .\buf_fifo_reg[0][2]_0 (\buf_fifo_reg[0][2] ),
        .\buf_fifo_reg[0][4]_0 (\buf_fifo_reg[0][4]_0 ),
        .\buf_fifo_reg[1][0]_0 (\buf_fifo_reg[1][0] ),
        .\buf_fifo_reg[1][1]_0 (\buf_fifo_reg[1][1] ),
        .\buf_fifo_reg[1][2]_0 (\buf_fifo_reg[1][2] ),
        .\buf_fifo_reg[1][3]_0 (\buf_fifo_reg[1][3] ),
        .\buf_fifo_reg[1][4]_0 (\buf_fifo_reg[1][4] ),
        .\buf_fifo_reg[2][3]_0 (\buf_fifo_reg[2][3]_0 ),
        .\cas_fifo_rptr_reg[0]_0 (winPortC[3]),
        .clrReq1(clrReq1),
        .cmd(cmd),
        .cmdAP(cmdAP[3]),
        .\cmdBankP_reg[1]_0 (cmdBankP[7:6]),
        .cmdBuf(cmdBuf[19:15]),
        .\cmdCol_reg[9]_0 (cmdCol[39:33]),
        .cmdGroupP(cmdGroupP[6]),
        .\cmdGroupP_reg[0]_0 (um_sreIss_reg_0),
        .cmdRmw_reg_0(\bgr[3].u_ddr_mc_group_n_8 ),
        .\cmd_bank_cas_reg[1]_0 (cmd_bank_cas[7:6]),
        .cmd_group_cas(cmd_group_cas[6]),
        .col(col),
        .grAccept_ns(grAccept_ns[2]),
        .group(group),
        .per_block_ref(per_block_ref),
        .periodic_read_or_ref_block_reg_0(periodic_read_or_ref_block_reg),
        .preReqR_reg_0(\bgr[3].u_ddr_mc_group_n_6 ),
        .preReqR_reg_1(p_0_in9_in),
        .rdReqR_reg_0(\bgr[3].u_ddr_mc_group_n_7 ),
        .refOK(refOK[2:0]),
        .refOK_reg_0(refOK[3]),
        .refOK_reg_1(\bgr[3].u_ddr_mc_group_n_42 ),
        .refReq(refReq),
        .ref_req_dly4(ref_req_dly4),
        .row_mc_phy(row_mc_phy),
        .tranSentC(tranSentC),
        .\txn_fifo_wptr_reg[0]_0 (\txn_fifo_wptr_reg[0] ),
        .\txn_fifo_wptr_reg[0]_1 (periodic_config_gap_enable_reg),
        .underfill_done_reg_0(underfill_done_reg_1),
        .useAdr(useAdr),
        .wrReqR_reg_0(\bgr[3].u_ddr_mc_group_n_3 ));
  LUT6 #(
    .INIT(64'hCFFFFF3F00000020)) 
    int_refReq_i_1
       (.I0(u_ddr_mc_ref_n_16),
        .I1(u_ddr_mc_ref_n_6),
        .I2(u_ddr_mc_ref_n_7),
        .I3(u_ddr_mc_ref_n_8),
        .I4(u_ddr_mc_ref_n_5),
        .I5(refReq),
        .O(int_refReq_i_1_n_0));
  LUT6 #(
    .INIT(64'hF7F7FFF704040000)) 
    \int_sreCkeDis[0]_i_1 
       (.I0(u_ddr_mc_ref_n_7),
        .I1(u_ddr_mc_ref_n_5),
        .I2(u_ddr_mc_ref_n_6),
        .I3(periodic_config_gap_enable_reg),
        .I4(u_ddr_mc_ref_n_8),
        .I5(int_sreCkeDis),
        .O(\int_sreCkeDis[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hEB28)) 
    \prevGroup[0]_i_1 
       (.I0(win_group_cas),
        .I1(winWrite),
        .I2(winRead),
        .I3(prevGroup),
        .O(\prevGroup[0]_i_1_n_0 ));
  (* KEEP = "yes" *) 
  FDRE rst_r1_reg
       (.C(um_sreIss_reg_0),
        .CE(1'b1),
        .D(SR),
        .Q(rst_r1),
        .R(1'b0));
  ddr4_0_ddr4_v2_2_17_mc_act_timer u_ddr_mc_act_timer
       (.D(u_ddr_mc_arb_a_n_6),
        .Q(\outstanding_act_slr_reg[0]_244 ),
        .\act_shift_slr_reg[0][7] (um_sreIss_reg_0),
        .out(rst_r1),
        .\outstanding_act_slr_reg[0][0] (u_ddr_mc_arb_a_n_1));
  ddr4_0_ddr4_v2_2_17_mc_arb_a u_ddr_mc_arb_a
       (.D(u_ddr_mc_arb_a_n_6),
        .Q(winPortA),
        .SR(u_ddr_mc_arb_a_n_36),
        .actReq(actReq),
        .actReqR(actReqR),
        .actReqR_reg(u_ddr_mc_arb_a_n_1),
        .calDone(calDone),
        .calDone_reg(calDone_reg_1),
        .cal_BA(cal_BA),
        .mc_ADR({mc_ADR[37:35],mc_ADR[32:30],mc_ADR[27],mc_ADR[24],mc_ADR[21],mc_ADR[18],mc_ADR[15],mc_ADR[12],mc_ADR[9],mc_ADR[6],mc_ADR[4:3],mc_ADR[1]}),
        .mc_BA(mc_BA[4]),
        .\mcal_ADR_dly_reg[0][100] (u_ddr_mc_cmd_mux_a_n_15),
        .\mcal_ADR_dly_reg[0][108] (u_ddr_mc_cmd_mux_a_n_16),
        .\mcal_ADR_dly_reg[0][116] (u_ddr_mc_cmd_mux_a_n_17),
        .\mcal_ADR_dly_reg[0][124] (u_ddr_mc_cmd_mux_a_n_18),
        .\mcal_ADR_dly_reg[0][12] (u_ddr_mc_cmd_mux_a_n_4),
        .\mcal_ADR_dly_reg[0][132] ({cmdRow[16:0],cmdBank[0]}),
        .\mcal_ADR_dly_reg[0][132]_0 (u_ddr_mc_cmd_mux_a_n_19),
        .\mcal_ADR_dly_reg[0][20] (u_ddr_mc_cmd_mux_a_n_5),
        .\mcal_ADR_dly_reg[0][28] (u_ddr_mc_cmd_mux_a_n_6),
        .\mcal_ADR_dly_reg[0][36] (u_ddr_mc_cmd_mux_a_n_7),
        .\mcal_ADR_dly_reg[0][44] (u_ddr_mc_cmd_mux_a_n_8),
        .\mcal_ADR_dly_reg[0][4] (u_ddr_mc_cmd_mux_a_n_3),
        .\mcal_ADR_dly_reg[0][4]_0 (mc_ADR[33]),
        .\mcal_ADR_dly_reg[0][52] (u_ddr_mc_cmd_mux_a_n_9),
        .\mcal_ADR_dly_reg[0][60] (u_ddr_mc_cmd_mux_a_n_10),
        .\mcal_ADR_dly_reg[0][68] (u_ddr_mc_cmd_mux_a_n_11),
        .\mcal_ADR_dly_reg[0][76] (u_ddr_mc_cmd_mux_a_n_12),
        .\mcal_ADR_dly_reg[0][84] (u_ddr_mc_cmd_mux_a_n_13),
        .\mcal_ADR_dly_reg[0][92] (u_ddr_mc_cmd_mux_a_n_14),
        .\mcal_BA_dly_reg[0][4] (u_ddr_mc_cmd_mux_a_n_0),
        .out(rst_r1),
        .p_0_in(p_0_in),
        .rst_r1_reg(u_ddr_mc_arb_a_n_37),
        .rst_r1_reg_0(u_ddr_mc_arb_a_n_38),
        .rst_r1_reg_1(u_ddr_mc_arb_a_n_39),
        .rst_r1_reg_2(u_ddr_mc_arb_a_n_40),
        .rst_r1_reg_3(u_ddr_mc_arb_a_n_41),
        .rst_r1_reg_4(u_ddr_mc_arb_a_n_42),
        .rst_r1_reg_5(u_ddr_mc_arb_a_n_43),
        .winAct_reg_0(winAct),
        .winAct_reg_1(winAct_reg),
        .winAct_reg_2(\bgr[1].u_ddr_mc_group_n_5 ),
        .winBankA(winBankA),
        .winGroupA(winGroupA),
        .\winPort_reg[0]_0 (u_ddr_mc_arb_a_n_7),
        .\winPort_reg[0]_1 (u_ddr_mc_arb_a_n_8),
        .\winPort_reg[0]_2 (u_ddr_mc_arb_a_n_9),
        .\winPort_reg[0]_3 (u_ddr_mc_arb_a_n_10),
        .\winPort_reg[0]_4 (u_ddr_mc_arb_a_n_11),
        .\winPort_reg[0]_5 (u_ddr_mc_arb_a_n_12),
        .\winPort_reg[0]_6 (u_ddr_mc_arb_a_n_13),
        .\winPort_reg[0]_7 (u_ddr_mc_arb_a_n_14),
        .\winPort_reg[0]_8 (\winPort_reg[0] ),
        .\winPort_reg[1]_0 (\bgr[2].u_ddr_mc_group_n_4 ),
        .\winPort_reg[2]_0 (\outstanding_act_slr_reg[0]_244 ),
        .\winPort_reg[3]_0 (um_sreIss_reg_0),
        .\winPort_reg[3]_1 (\bgr[3].u_ddr_mc_group_n_5 ));
  ddr4_0_ddr4_v2_2_17_mc_arb_c u_ddr_mc_arb_c
       (.D(u_ddr_mc_arb_c_n_3),
        .Q(winPortC),
        .SR(rtw),
        .block_reads(block_reads),
        .block_writes(block_writes),
        .calDone(calDone),
        .calDone_reg(calDone_reg_0),
        .calDone_reg_0(calDone_reg_2),
        .calDone_reg_1(calDone_reg_3),
        .calWrCAS(calWrCAS),
        .clrReq1(clrReq1),
        .clrReq13_out(clrReq13_out),
        .clrReq15_out(clrReq15_out),
        .clrReq17_out(clrReq17_out),
        .cmdInjTxn(cmdInjTxn),
        .cmd_bank_cas(cmd_bank_cas),
        .\cmd_bank_cas_reg[0] (u_ddr_mc_arb_c_n_8),
        .\cmd_bank_cas_reg[0]_0 (u_ddr_mc_arb_c_n_9),
        .\cmd_bank_cas_reg[0]_1 (u_ddr_mc_arb_c_n_10),
        .\cmd_bank_cas_reg[0]_2 (u_ddr_mc_arb_c_n_11),
        .\cmd_bank_cas_reg[0]_3 (u_ddr_mc_arb_c_n_12),
        .\cmd_bank_cas_reg[0]_4 (u_ddr_mc_arb_c_n_13),
        .\cmd_bank_cas_reg[0]_5 (u_ddr_mc_arb_c_n_14),
        .\cmd_bank_cas_reg[0]_6 (u_ddr_mc_arb_c_n_15),
        .cmd_group_cas({cmd_group_cas[6],cmd_group_cas[4],cmd_group_cas[2],cmd_group_cas[0]}),
        .d_prevGroup(d_prevGroup),
        .interval_counter_reset(interval_counter_reset),
        .mc_ADR({mc_ADR[25],mc_ADR[23:22],mc_ADR[20:19],mc_ADR[17:16],mc_ADR[14:13],mc_ADR[11:10],mc_ADR[8:7],mc_ADR[5],mc_ADR[2],mc_ADR[0]}),
        .mc_BA({mc_BA[5],mc_BA[3],mc_BA[1:0]}),
        .mc_BG(mc_BG[1:0]),
        .mc_ODT(mc_ODT[1]),
        .\mcal_ADR_dly_reg[0][26] (u_ddr_mc_cmd_mux_c_n_16),
        .\mcal_ADR_dly_reg[0][34] (u_ddr_mc_cmd_mux_c_n_15),
        .\mcal_ADR_dly_reg[0][42] (u_ddr_mc_cmd_mux_c_n_14),
        .\mcal_ADR_dly_reg[0][50] (u_ddr_mc_cmd_mux_c_n_13),
        .\mcal_ADR_dly_reg[0][58] (u_ddr_mc_cmd_mux_c_n_12),
        .\mcal_ADR_dly_reg[0][66] (u_ddr_mc_cmd_mux_c_n_11),
        .\mcal_ADR_dly_reg[0][74] (cmdCol[9:3]),
        .\mcal_ADR_dly_reg[0][74]_0 (u_ddr_mc_cmd_mux_c_n_10),
        .\mcal_ADR_dly_reg[0][74]_1 (mc_ADR[33]),
        .\mcal_ODT_dly_reg[0][6] ({\u_ddr_mc_odt/p_0_in [2],\u_ddr_mc_odt/p_0_in [0]}),
        .\mcal_ODT_dly_reg[0][7] (\mcal_ODT_dly_reg[0][7] ),
        .\mcal_PAR_dly[0][6]_i_2_0 ({mc_ADR[28],mc_ADR[26]}),
        .\mcal_PAR_dly_reg[0][1] (u_ddr_mc_ctl_n_21),
        .\mcal_PAR_dly_reg[0][5] (u_ddr_mc_ctl_n_22),
        .oe_0_mux_cal(oe_0_mux_cal),
        .oe_fabric(\u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_fabric ),
        .out(rst_r1),
        .per_cas_block_req(per_cas_block_req),
        .\prevGr_reg[0] (u_ddr_mc_rd_wr_n_5),
        .rdReqR(rdReqR),
        .rtw_okr(rtw_okr),
        .\timerWTP_reg[0][0][0][0][1] (\timerWTP_reg[0][0][0][0]_234 ),
        .\timerWTP_reg[0][0][0][1][1] (\timerWTP_reg[0][0][0][1]_232 ),
        .\timerWTP_reg[0][0][0][2][1] (\timerWTP_reg[0][0][0][2]_230 ),
        .\timerWTP_reg[0][0][0][3][1] (u_ddr_mc_cmd_mux_c_n_1),
        .\timerWTP_reg[0][0][0][3][1]_0 (u_ddr_mc_cmd_mux_c_n_0),
        .\timerWTP_reg[0][0][0][3][1]_1 (\timerWTP_reg[0][0][0][3]_228 ),
        .\timerWTP_reg[0][0][1][0][1] (\timerWTP_reg[0][0][1][0]_233 ),
        .\timerWTP_reg[0][0][1][1][1] (\timerWTP_reg[0][0][1][1]_231 ),
        .\timerWTP_reg[0][0][1][2][1] (\timerWTP_reg[0][0][1][2]_229 ),
        .\timerWTP_reg[0][0][1][3][1] (\timerWTP_reg[0][0][1][3]_227 ),
        .tranSentC(tranSentC),
        .winGroupC(winGroupC),
        .\winPort[3]_i_5__0_0 (\bgr[2].u_ddr_mc_group_n_6 ),
        .\winPort[3]_i_6__0_0 (\bgr[3].u_ddr_mc_group_n_7 ),
        .winRead(winRead),
        .winRead_i_4_0(\bgr[1].u_ddr_mc_group_n_7 ),
        .winRead_reg_0(winRead_reg),
        .winRead_reg_1(u_ddr_mc_arb_c_n_72),
        .winRead_reg_2(\u_ddr_mc_odt/odt_shift_nxt[0]_189 ),
        .winWrite(winWrite),
        .winWrite_i_5_0(\bgr[1].u_ddr_mc_group_n_4 ),
        .winWrite_reg_0(mcWrCAS),
        .winWrite_reg_1(u_ddr_mc_arb_c_n_69),
        .winWrite_reg_10(\bgr[2].u_ddr_mc_group_n_3 ),
        .winWrite_reg_11(\bgr[3].u_ddr_mc_group_n_3 ),
        .winWrite_reg_2(p_0_in__14),
        .winWrite_reg_3(p_0_in__10),
        .winWrite_reg_4(p_0_in__30),
        .winWrite_reg_5(p_0_in__26),
        .winWrite_reg_6(p_0_in__46),
        .winWrite_reg_7(p_0_in__42),
        .winWrite_reg_8(p_0_in__62),
        .winWrite_reg_9(p_0_in__58),
        .\win_bank_cas_reg[1]_0 (um_sreIss_reg_0),
        .win_group_cas(win_group_cas),
        .wrCAS_reg(wrCAS_reg),
        .wrCAS_reg_0(wrCAS_reg_0),
        .wrCAS_reg_1(wrCAS_reg_1),
        .wrCAS_reg_10(wrCAS_reg_10),
        .wrCAS_reg_11(wrCAS_reg_11),
        .wrCAS_reg_2(wrCAS_reg_2),
        .wrCAS_reg_3(wrCAS_reg_3),
        .wrCAS_reg_4(wrCAS_reg_4),
        .wrCAS_reg_5(wrCAS_reg_5),
        .wrCAS_reg_6(wrCAS_reg_6),
        .wrCAS_reg_7(wrCAS_reg_7),
        .wrCAS_reg_8(wrCAS_reg_8),
        .wrCAS_reg_9(wrCAS_reg_9),
        .\wrQ_reg[0][5]_rep__1 (cmdInjTxn_reg[0]),
        .\wrQ_reg[0][6]_rep__1 (cmdInjTxn_reg[1]),
        .\wrQ_reg[0][7]_rep__1 (cmdInjTxn_reg[2]),
        .\wrQ_reg[0][8]_rep__1 (\wrQ_reg[0][8]_rep__1 ),
        .\wrQ_reg[0][8]_rep__1_0 (cmdInjTxn_reg[3]),
        .\wrQ_reg[1][2] (mcCasSlot2),
        .wrReqR(wrReqR),
        .wrReqR_reg(u_ddr_mc_ctl_n_27),
        .wtr_oklr(wtr_oklr),
        .wtr_oksr(wtr_oksr));
  ddr4_0_ddr4_v2_2_17_mc_arb_mux_p u_ddr_mc_arb_mux_p
       (.D(p_0_in__14),
        .Q(\timerWTP_reg[0][0][0][3]_228 ),
        .SR(u_ddr_mc_arb_a_n_37),
        .calDone(calDone),
        .calDone_reg(calDone_reg),
        .cmdBankP(cmdBankP),
        .cmdGroupP({cmdGroupP[6],cmdGroupP[4],cmdGroupP[2],cmdGroupP[0]}),
        .d_prevGroup(d_prevGroup),
        .mc_ADR(mc_ADR[34]),
        .\mc_ADR7_reg[13] (mc_ADR[33]),
        .mc_BA({mc_BA[6],mc_BA[2]}),
        .mc_BG(mc_BG[2]),
        .\mcal_PAR_dly_reg[0][7] (u_ddr_mc_ref_n_9),
        .out(rst_r1),
        .preIss(preIss),
        .preReqR(preReqR),
        .\timerRAS_reg[0][0][0][0][0]_0 (u_ddr_mc_arb_a_n_42),
        .\timerRAS_reg[0][0][0][0][3]_0 (u_ddr_mc_arb_a_n_8),
        .\timerRAS_reg[0][0][0][1][0]_0 (u_ddr_mc_arb_a_n_40),
        .\timerRAS_reg[0][0][0][1][3]_0 (u_ddr_mc_arb_a_n_10),
        .\timerRAS_reg[0][0][0][2][0]_0 (u_ddr_mc_arb_a_n_38),
        .\timerRAS_reg[0][0][0][2][3]_0 (u_ddr_mc_arb_a_n_12),
        .\timerRAS_reg[0][0][0][3][0]_0 (u_ddr_mc_arb_a_n_36),
        .\timerRAS_reg[0][0][0][3][3]_0 (u_ddr_mc_arb_a_n_14),
        .\timerRAS_reg[0][0][1][0][0]_0 (u_ddr_mc_arb_a_n_43),
        .\timerRAS_reg[0][0][1][0][3]_0 (u_ddr_mc_arb_a_n_7),
        .\timerRAS_reg[0][0][1][1][0]_0 (u_ddr_mc_arb_a_n_41),
        .\timerRAS_reg[0][0][1][1][3]_0 (u_ddr_mc_arb_a_n_9),
        .\timerRAS_reg[0][0][1][2][0]_0 (u_ddr_mc_arb_a_n_39),
        .\timerRAS_reg[0][0][1][2][3]_0 (u_ddr_mc_arb_a_n_11),
        .\timerRAS_reg[0][0][1][3][3]_0 (u_ddr_mc_arb_a_n_13),
        .\timerWTP_reg[0][0][0][0][1]_0 (\timerWTP_reg[0][0][0][0]_234 ),
        .\timerWTP_reg[0][0][0][0][1]_1 (p_0_in__62),
        .\timerWTP_reg[0][0][0][0][2]_0 (u_ddr_mc_arb_c_n_14),
        .\timerWTP_reg[0][0][0][1][1]_0 (\timerWTP_reg[0][0][0][1]_232 ),
        .\timerWTP_reg[0][0][0][1][1]_1 (p_0_in__46),
        .\timerWTP_reg[0][0][0][1][2]_0 (u_ddr_mc_arb_c_n_12),
        .\timerWTP_reg[0][0][0][2][1]_0 (\timerWTP_reg[0][0][0][2]_230 ),
        .\timerWTP_reg[0][0][0][2][1]_1 (p_0_in__30),
        .\timerWTP_reg[0][0][0][2][2]_0 (u_ddr_mc_arb_c_n_10),
        .\timerWTP_reg[0][0][0][3][2]_0 (u_ddr_mc_arb_c_n_8),
        .\timerWTP_reg[0][0][1][0][1]_0 (\timerWTP_reg[0][0][1][0]_233 ),
        .\timerWTP_reg[0][0][1][0][1]_1 (p_0_in__58),
        .\timerWTP_reg[0][0][1][0][2]_0 (u_ddr_mc_arb_c_n_15),
        .\timerWTP_reg[0][0][1][1][1]_0 (\timerWTP_reg[0][0][1][1]_231 ),
        .\timerWTP_reg[0][0][1][1][1]_1 (p_0_in__42),
        .\timerWTP_reg[0][0][1][1][2]_0 (u_ddr_mc_arb_c_n_13),
        .\timerWTP_reg[0][0][1][2][1]_0 (\timerWTP_reg[0][0][1][2]_229 ),
        .\timerWTP_reg[0][0][1][2][1]_1 (p_0_in__26),
        .\timerWTP_reg[0][0][1][2][2]_0 (u_ddr_mc_arb_c_n_11),
        .\timerWTP_reg[0][0][1][3][1]_0 (\timerWTP_reg[0][0][1][3]_227 ),
        .\timerWTP_reg[0][0][1][3][1]_1 (p_0_in__10),
        .\timerWTP_reg[0][0][1][3][2]_0 (u_ddr_mc_arb_c_n_9),
        .winPort({p_0_in9_in,p_0_in5_in,p_0_in1_in,p_0_in0_in}),
        .\winPort_reg[0] (\bgr[3].u_ddr_mc_group_n_6 ),
        .\winPort_reg[0]_0 (\bgr[2].u_ddr_mc_group_n_5 ),
        .\winPort_reg[0]_1 (\bgr[1].u_ddr_mc_group_n_6 ),
        .\winPort_reg[1] (u_ddr_mc_arb_mux_p_n_9),
        .\winPort_reg[3] (um_sreIss_reg_0),
        .winWrite(winWrite));
  ddr4_0_ddr4_v2_2_17_mc_cmd_mux_ap u_ddr_mc_cmd_mux_a
       (.Q({cmdRow[33:17],cmdGroup[2],cmdBank[3:2]}),
        .\mcal_ADR_dly[0][132]_i_2 ({cmdRow[67:51],cmdGroup[6],cmdBank[7:6]}),
        .\mcal_ADR_dly[0][132]_i_2_0 ({cmdRow[50:34],cmdGroup[4],cmdBank[5:4]}),
        .\mcal_BA_dly_reg[0][4] (winPortA),
        .\mcal_BG_dly_reg[0][4] ({cmdGroup[0],cmdBank[1]}),
        .\txn_fifo_output_reg[0] (u_ddr_mc_cmd_mux_a_n_0),
        .\txn_fifo_output_reg[24] (u_ddr_mc_cmd_mux_a_n_3),
        .\txn_fifo_output_reg[25] (u_ddr_mc_cmd_mux_a_n_4),
        .\txn_fifo_output_reg[26] (u_ddr_mc_cmd_mux_a_n_5),
        .\txn_fifo_output_reg[27] (u_ddr_mc_cmd_mux_a_n_6),
        .\txn_fifo_output_reg[28] (u_ddr_mc_cmd_mux_a_n_7),
        .\txn_fifo_output_reg[29] (u_ddr_mc_cmd_mux_a_n_8),
        .\txn_fifo_output_reg[30] (u_ddr_mc_cmd_mux_a_n_9),
        .\txn_fifo_output_reg[31] (u_ddr_mc_cmd_mux_a_n_10),
        .\txn_fifo_output_reg[32] (u_ddr_mc_cmd_mux_a_n_11),
        .\txn_fifo_output_reg[33] (u_ddr_mc_cmd_mux_a_n_12),
        .\txn_fifo_output_reg[34] (u_ddr_mc_cmd_mux_a_n_13),
        .\txn_fifo_output_reg[35] (u_ddr_mc_cmd_mux_a_n_14),
        .\txn_fifo_output_reg[36] (u_ddr_mc_cmd_mux_a_n_15),
        .\txn_fifo_output_reg[37] (u_ddr_mc_cmd_mux_a_n_16),
        .\txn_fifo_output_reg[38] (u_ddr_mc_cmd_mux_a_n_17),
        .\txn_fifo_output_reg[39] (u_ddr_mc_cmd_mux_a_n_18),
        .\txn_fifo_output_reg[40] (u_ddr_mc_cmd_mux_a_n_19),
        .winBankA(winBankA),
        .winGroupA(winGroupA));
  ddr4_0_ddr4_v2_2_17_mc_cmd_mux_c u_ddr_mc_cmd_mux_c
       (.Q(winPortC),
        .cmdAP(cmdAP),
        .cmdBuf(cmdBuf),
        .cmdCol({cmdCol[39:33],cmdCol[29:23],cmdCol[19:13]}),
        .\cmdCol_reg[3] (u_ddr_mc_cmd_mux_c_n_16),
        .\cmdCol_reg[4] (u_ddr_mc_cmd_mux_c_n_15),
        .\cmdCol_reg[5] (u_ddr_mc_cmd_mux_c_n_14),
        .\cmdCol_reg[6] (u_ddr_mc_cmd_mux_c_n_13),
        .\cmdCol_reg[7] (u_ddr_mc_cmd_mux_c_n_12),
        .\cmdCol_reg[8] (u_ddr_mc_cmd_mux_c_n_11),
        .\cmdCol_reg[9] (u_ddr_mc_cmd_mux_c_n_10),
        .cmdInjTxn(cmdInjTxn),
        .cmdInjTxn_reg(cmdInjTxn_reg),
        .cmd_bank_cas(cmd_bank_cas[7:2]),
        .\cmd_bank_cas_reg[0] (u_ddr_mc_cmd_mux_c_n_1),
        .\cmd_bank_cas_reg[1] (u_ddr_mc_cmd_mux_c_n_0),
        .cmd_group_cas({cmd_group_cas[6],cmd_group_cas[4],cmd_group_cas[2],cmd_group_cas[0]}),
        .\read_lat_fifo_in_reg[5] (\bgr[0].u_ddr_mc_group_n_29 ),
        .\read_lat_fifo_in_reg[5]_0 (\bgr[1].u_ddr_mc_group_n_8 ),
        .\read_lat_fifo_in_reg[5]_1 (\bgr[3].u_ddr_mc_group_n_8 ),
        .\read_lat_fifo_in_reg[5]_2 (\bgr[2].u_ddr_mc_group_n_7 ),
        .winAP(winAP),
        .winGroupC(winGroupC));
  ddr4_0_ddr4_v2_2_17_mc_ctl u_ddr_mc_ctl
       (.D(u_ddr_mc_ctl_n_3),
        .Q(wtrl),
        .calDone(calDone),
        .cal_CS_n(cal_CS_n),
        .mcRdCAS(mcRdCAS),
        .mc_ADR({mc_ADR[33],mc_ADR[28],mc_ADR[26]}),
        .mc_ODT(mc_ODT[0]),
        .\mcal_ADR_dly_reg[0][126] (\mcal_ADR_dly_reg[0][126] ),
        .\odt_shift_reg[0][18] ({\u_ddr_mc_odt/p_0_in [2],\u_ddr_mc_odt/p_0_in [0]}),
        .\odt_shift_reg[0][20] (um_sreIss_reg_0),
        .\odt_shift_reg[0][20]_0 (\u_ddr_mc_odt/odt_shift_nxt[0]_189 ),
        .oe_0_mux_cal(oe_0_mux_cal),
        .oe_fabric(\u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_fabric ),
        .out(rst_r1),
        .per_cas_block_req(per_cas_block_req),
        .prevCAS_reg_0(mcCasSlot2),
        .prevCAS_reg_1(u_ddr_mc_ctl_n_27),
        .prevCmdAP(prevCmdAP),
        .prevGroup(prevGroup),
        .\prevGroup_reg[0]_0 (\prevGroup[0]_i_1_n_0 ),
        .prevSlot2_reg_0(u_ddr_mc_arb_c_n_72),
        .tranSentC(tranSentC),
        .winAP(winAP),
        .winRead(winRead),
        .winRead_reg(winRead_reg_0),
        .winRead_reg_0(winRead_reg_1),
        .winRead_reg_1(u_ddr_mc_ctl_n_21),
        .winRead_reg_2(u_ddr_mc_ctl_n_22),
        .winWrite(winWrite),
        .win_group_cas(win_group_cas));
  ddr4_0_ddr4_v2_2_17_mc_periodic u_ddr_mc_periodic
       (.D(u_ddr_mc_arb_c_n_3),
        .Q(winPortC[0]),
        .cmdInjTxn(cmdInjTxn),
        .gt_data_ready_flag(gt_data_ready_flag),
        .gt_data_ready_flag_nxt(gt_data_ready_flag_nxt),
        .gt_data_ready_flag_reg(gt_data_ready_flag_reg),
        .interval_counter_reset(interval_counter_reset),
        .out(rst_r1),
        .per_block_ref(per_block_ref),
        .per_cas_block_req(per_cas_block_req),
        .per_cas_block_req_reg_0(um_sreIss_reg_0),
        .per_rd_accept_0(per_rd_accept_0),
        .per_rd_done(per_rd_done),
        .per_rd_req(per_rd_req),
        .periodic_config_gap_enable_reg_0(periodic_config_gap_enable_reg),
        .refReq(refReq),
        .tranSentC(tranSentC),
        .winRead(winRead));
  ddr4_0_ddr4_v2_2_17_mc_rd_wr u_ddr_mc_rd_wr
       (.D(u_ddr_mc_ctl_n_3),
        .Q(wtrl),
        .SR(rtw),
        .block_reads(block_reads),
        .block_writes(block_writes),
        .out(rst_r1),
        .\prevGr_reg[0] (u_ddr_mc_rd_wr_n_5),
        .\prevGr_reg[0]_0 (u_ddr_mc_arb_c_n_69),
        .rdReqR(rdReqR),
        .\read_req_ff_reg[1]_0 (\bgr[1].u_ddr_mc_group_n_7 ),
        .\read_req_ff_reg[2]_0 (\bgr[2].u_ddr_mc_group_n_6 ),
        .\read_req_ff_reg[3]_0 (winPortC),
        .\read_req_ff_reg[3]_1 (\bgr[3].u_ddr_mc_group_n_7 ),
        .rtw_okr(rtw_okr),
        .tranSentC(tranSentC),
        .winRead(winRead),
        .winWrite(winWrite),
        .wrReqR(wrReqR),
        .\write_req_ff_reg[1]_0 (\bgr[1].u_ddr_mc_group_n_4 ),
        .\write_req_ff_reg[2]_0 (\bgr[2].u_ddr_mc_group_n_3 ),
        .\write_req_ff_reg[3]_0 (\bgr[3].u_ddr_mc_group_n_3 ),
        .wtr_oklr(wtr_oklr),
        .wtr_oklr_reg(um_sreIss_reg_0),
        .wtr_oksr(wtr_oksr));
  ddr4_0_ddr4_v2_2_17_mc_ref u_ddr_mc_ref
       (.Q(user_fsm),
        .d_prevGroup(d_prevGroup),
        .int_refReq_reg_0(int_refReq_i_1_n_0),
        .int_sreCkeDis(int_sreCkeDis),
        .\int_sreCkeDis_reg[0]_0 (\int_sreCkeDis[0]_i_1_n_0 ),
        .int_zqIss_reg_0(mc_ADR[29]),
        .mc_ADR(mc_ADR[34]),
        .mc_BA(mc_BA[6]),
        .mc_CKE(mc_CKE),
        .mc_CS_n(mc_CS_n),
        .\mc_CS_n7_reg[0] (u_ddr_mc_arb_mux_p_n_9),
        .out(rst_r1),
        .\pend_ref_reg[0][0]_0 (u_ddr_mc_ref_n_16),
        .preIss(preIss),
        .prevCmdAP(prevCmdAP),
        .refReq(refReq),
        .\refSt_reg[0]_0 (\bgr[3].u_ddr_mc_group_n_42 ),
        .\refSt_reg[1]_0 (periodic_config_gap_enable_reg),
        .\refSt_reg[3]_0 ({u_ddr_mc_ref_n_5,u_ddr_mc_ref_n_6,u_ddr_mc_ref_n_7,u_ddr_mc_ref_n_8}),
        .tranSentC(tranSentC),
        .\um_rank_cntr_reg[1]_0 (u_ddr_mc_ref_n_14),
        .um_sreCkeDis(um_sreCkeDis),
        .\um_sreCkeDis_reg[0]_0 (\um_sreCkeDis[0]_i_1_n_0 ),
        .um_sreIss_reg_0(um_sreIss_reg),
        .um_sreIss_reg_1(um_sreIss_reg_0),
        .\um_wait_cntr_reg[7]_0 (\bgr[1].u_ddr_mc_group_n_38 ),
        .\user_fsm_reg[0]_0 (u_ddr_mc_ref_n_18),
        .\user_fsm_reg[3]_0 (u_ddr_mc_ref_n_17),
        .\user_fsm_reg[4]_0 (u_ddr_mc_ref_n_15),
        .\winPort_reg[0] (u_ddr_mc_ref_n_9),
        .winRead(winRead),
        .winWrite(winWrite));
  LUT6 #(
    .INIT(64'h8080FFFF00800000)) 
    \um_sreCkeDis[0]_i_1 
       (.I0(user_fsm),
        .I1(u_ddr_mc_ref_n_17),
        .I2(u_ddr_mc_ref_n_18),
        .I3(u_ddr_mc_ref_n_14),
        .I4(u_ddr_mc_ref_n_15),
        .I5(um_sreCkeDis),
        .O(\um_sreCkeDis[0]_i_1_n_0 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_act_rank" *) 
module ddr4_0_ddr4_v2_2_17_mc_act_rank
   (Q,
    \outstanding_act_slr_reg[0][0]_0 ,
    out,
    \act_shift_slr_reg[0][7]_0 ,
    D);
  output [0:0]Q;
  input \outstanding_act_slr_reg[0][0]_0 ;
  input out;
  input \act_shift_slr_reg[0][7]_0 ;
  input [0:0]D;

  wire [0:0]D;
  wire [0:0]Q;
  wire \act_shift_slr_reg[0][7]_0 ;
  wire [7:0]\act_shift_slr_reg[0]_243 ;
  wire out;
  wire [4:0]\outstanding_act_slr_nxt[0]_278 ;
  wire \outstanding_act_slr_reg[0][0]_0 ;
  wire [3:0]\outstanding_act_slr_reg[0]_244 ;

  FDRE \act_shift_slr_reg[0][0] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(D),
        .Q(\act_shift_slr_reg[0]_243 [0]),
        .R(out));
  FDRE \act_shift_slr_reg[0][1] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(\act_shift_slr_reg[0]_243 [0]),
        .Q(\act_shift_slr_reg[0]_243 [1]),
        .R(out));
  FDRE \act_shift_slr_reg[0][2] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(\act_shift_slr_reg[0]_243 [1]),
        .Q(\act_shift_slr_reg[0]_243 [2]),
        .R(out));
  FDRE \act_shift_slr_reg[0][3] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(\act_shift_slr_reg[0]_243 [2]),
        .Q(\act_shift_slr_reg[0]_243 [3]),
        .R(out));
  FDRE \act_shift_slr_reg[0][4] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(\act_shift_slr_reg[0]_243 [3]),
        .Q(\act_shift_slr_reg[0]_243 [4]),
        .R(out));
  FDRE \act_shift_slr_reg[0][5] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(\act_shift_slr_reg[0]_243 [4]),
        .Q(\act_shift_slr_reg[0]_243 [5]),
        .R(out));
  FDRE \act_shift_slr_reg[0][6] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(\act_shift_slr_reg[0]_243 [5]),
        .Q(\act_shift_slr_reg[0]_243 [6]),
        .R(out));
  FDRE \act_shift_slr_reg[0][7] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(\act_shift_slr_reg[0]_243 [6]),
        .Q(\act_shift_slr_reg[0]_243 [7]),
        .R(out));
  LUT4 #(
    .INIT(16'hA808)) 
    \outstanding_act_slr[0][0]_i_1 
       (.I0(\outstanding_act_slr_reg[0][0]_0 ),
        .I1(\outstanding_act_slr_reg[0]_244 [0]),
        .I2(\act_shift_slr_reg[0]_243 [7]),
        .I3(\outstanding_act_slr_reg[0]_244 [1]),
        .O(\outstanding_act_slr_nxt[0]_278 [0]));
  LUT5 #(
    .INIT(32'hB8F3B8C0)) 
    \outstanding_act_slr[0][1]_i_1 
       (.I0(\outstanding_act_slr_reg[0]_244 [2]),
        .I1(\outstanding_act_slr_reg[0][0]_0 ),
        .I2(\outstanding_act_slr_reg[0]_244 [1]),
        .I3(\act_shift_slr_reg[0]_243 [7]),
        .I4(\outstanding_act_slr_reg[0]_244 [0]),
        .O(\outstanding_act_slr_nxt[0]_278 [1]));
  LUT5 #(
    .INIT(32'hB8F3B8C0)) 
    \outstanding_act_slr[0][2]_i_1 
       (.I0(\outstanding_act_slr_reg[0]_244 [3]),
        .I1(\outstanding_act_slr_reg[0][0]_0 ),
        .I2(\outstanding_act_slr_reg[0]_244 [2]),
        .I3(\act_shift_slr_reg[0]_243 [7]),
        .I4(\outstanding_act_slr_reg[0]_244 [1]),
        .O(\outstanding_act_slr_nxt[0]_278 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2785" *) 
  LUT5 #(
    .INIT(32'hB8F3B8C0)) 
    \outstanding_act_slr[0][3]_i_1 
       (.I0(Q),
        .I1(\outstanding_act_slr_reg[0][0]_0 ),
        .I2(\outstanding_act_slr_reg[0]_244 [3]),
        .I3(\act_shift_slr_reg[0]_243 [7]),
        .I4(\outstanding_act_slr_reg[0]_244 [2]),
        .O(\outstanding_act_slr_nxt[0]_278 [3]));
  (* SOFT_HLUTNM = "soft_lutpair2785" *) 
  LUT4 #(
    .INIT(16'h4D4C)) 
    \outstanding_act_slr[0][4]_i_1 
       (.I0(\outstanding_act_slr_reg[0][0]_0 ),
        .I1(Q),
        .I2(\act_shift_slr_reg[0]_243 [7]),
        .I3(\outstanding_act_slr_reg[0]_244 [3]),
        .O(\outstanding_act_slr_nxt[0]_278 [4]));
  FDSE \outstanding_act_slr_reg[0][0] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(\outstanding_act_slr_nxt[0]_278 [0]),
        .Q(\outstanding_act_slr_reg[0]_244 [0]),
        .S(out));
  FDRE \outstanding_act_slr_reg[0][1] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(\outstanding_act_slr_nxt[0]_278 [1]),
        .Q(\outstanding_act_slr_reg[0]_244 [1]),
        .R(out));
  FDRE \outstanding_act_slr_reg[0][2] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(\outstanding_act_slr_nxt[0]_278 [2]),
        .Q(\outstanding_act_slr_reg[0]_244 [2]),
        .R(out));
  FDRE \outstanding_act_slr_reg[0][3] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(\outstanding_act_slr_nxt[0]_278 [3]),
        .Q(\outstanding_act_slr_reg[0]_244 [3]),
        .R(out));
  FDRE \outstanding_act_slr_reg[0][4] 
       (.C(\act_shift_slr_reg[0][7]_0 ),
        .CE(1'b1),
        .D(\outstanding_act_slr_nxt[0]_278 [4]),
        .Q(Q),
        .R(out));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_act_timer" *) 
module ddr4_0_ddr4_v2_2_17_mc_act_timer
   (Q,
    \outstanding_act_slr_reg[0][0] ,
    out,
    \act_shift_slr_reg[0][7] ,
    D);
  output [0:0]Q;
  input \outstanding_act_slr_reg[0][0] ;
  input out;
  input \act_shift_slr_reg[0][7] ;
  input [0:0]D;

  wire [0:0]D;
  wire [0:0]Q;
  wire \act_shift_slr_reg[0][7] ;
  wire out;
  wire \outstanding_act_slr_reg[0][0] ;

  ddr4_0_ddr4_v2_2_17_mc_act_rank \rr[0].u__ddr_mc_act_rank 
       (.D(D),
        .Q(Q),
        .\act_shift_slr_reg[0][7]_0 (\act_shift_slr_reg[0][7] ),
        .out(out),
        .\outstanding_act_slr_reg[0][0]_0 (\outstanding_act_slr_reg[0][0] ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_arb_a" *) 
module ddr4_0_ddr4_v2_2_17_mc_arb_a
   (winAct_reg_0,
    actReqR_reg,
    Q,
    D,
    \winPort_reg[0]_0 ,
    \winPort_reg[0]_1 ,
    \winPort_reg[0]_2 ,
    \winPort_reg[0]_3 ,
    \winPort_reg[0]_4 ,
    \winPort_reg[0]_5 ,
    \winPort_reg[0]_6 ,
    \winPort_reg[0]_7 ,
    winAct_reg_1,
    mc_ADR,
    \winPort_reg[0]_8 ,
    calDone_reg,
    mc_BA,
    SR,
    rst_r1_reg,
    rst_r1_reg_0,
    rst_r1_reg_1,
    rst_r1_reg_2,
    rst_r1_reg_3,
    rst_r1_reg_4,
    rst_r1_reg_5,
    out,
    \winPort_reg[3]_0 ,
    winAct_reg_2,
    actReqR,
    \mcal_BA_dly_reg[0][4] ,
    \mcal_ADR_dly_reg[0][132] ,
    winBankA,
    winGroupA,
    calDone,
    p_0_in,
    cal_BA,
    \winPort_reg[3]_1 ,
    \winPort_reg[1]_0 ,
    \winPort_reg[2]_0 ,
    actReq,
    \mcal_ADR_dly_reg[0][4] ,
    \mcal_ADR_dly_reg[0][4]_0 ,
    \mcal_ADR_dly_reg[0][12] ,
    \mcal_ADR_dly_reg[0][20] ,
    \mcal_ADR_dly_reg[0][28] ,
    \mcal_ADR_dly_reg[0][36] ,
    \mcal_ADR_dly_reg[0][44] ,
    \mcal_ADR_dly_reg[0][52] ,
    \mcal_ADR_dly_reg[0][60] ,
    \mcal_ADR_dly_reg[0][68] ,
    \mcal_ADR_dly_reg[0][76] ,
    \mcal_ADR_dly_reg[0][84] ,
    \mcal_ADR_dly_reg[0][92] ,
    \mcal_ADR_dly_reg[0][100] ,
    \mcal_ADR_dly_reg[0][108] ,
    \mcal_ADR_dly_reg[0][116] ,
    \mcal_ADR_dly_reg[0][124] ,
    \mcal_ADR_dly_reg[0][132]_0 );
  output winAct_reg_0;
  output actReqR_reg;
  output [3:0]Q;
  output [0:0]D;
  output \winPort_reg[0]_0 ;
  output \winPort_reg[0]_1 ;
  output \winPort_reg[0]_2 ;
  output \winPort_reg[0]_3 ;
  output \winPort_reg[0]_4 ;
  output \winPort_reg[0]_5 ;
  output \winPort_reg[0]_6 ;
  output \winPort_reg[0]_7 ;
  output [0:0]winAct_reg_1;
  output [16:0]mc_ADR;
  output [0:0]\winPort_reg[0]_8 ;
  output calDone_reg;
  output [0:0]mc_BA;
  output [0:0]SR;
  output [0:0]rst_r1_reg;
  output [0:0]rst_r1_reg_0;
  output [0:0]rst_r1_reg_1;
  output [0:0]rst_r1_reg_2;
  output [0:0]rst_r1_reg_3;
  output [0:0]rst_r1_reg_4;
  output [0:0]rst_r1_reg_5;
  input out;
  input \winPort_reg[3]_0 ;
  input winAct_reg_2;
  input actReqR;
  input \mcal_BA_dly_reg[0][4] ;
  input [17:0]\mcal_ADR_dly_reg[0][132] ;
  input [0:0]winBankA;
  input [0:0]winGroupA;
  input calDone;
  input [0:0]p_0_in;
  input [0:0]cal_BA;
  input \winPort_reg[3]_1 ;
  input \winPort_reg[1]_0 ;
  input [0:0]\winPort_reg[2]_0 ;
  input [0:0]actReq;
  input \mcal_ADR_dly_reg[0][4] ;
  input \mcal_ADR_dly_reg[0][4]_0 ;
  input \mcal_ADR_dly_reg[0][12] ;
  input \mcal_ADR_dly_reg[0][20] ;
  input \mcal_ADR_dly_reg[0][28] ;
  input \mcal_ADR_dly_reg[0][36] ;
  input \mcal_ADR_dly_reg[0][44] ;
  input \mcal_ADR_dly_reg[0][52] ;
  input \mcal_ADR_dly_reg[0][60] ;
  input \mcal_ADR_dly_reg[0][68] ;
  input \mcal_ADR_dly_reg[0][76] ;
  input \mcal_ADR_dly_reg[0][84] ;
  input \mcal_ADR_dly_reg[0][92] ;
  input \mcal_ADR_dly_reg[0][100] ;
  input \mcal_ADR_dly_reg[0][108] ;
  input \mcal_ADR_dly_reg[0][116] ;
  input \mcal_ADR_dly_reg[0][124] ;
  input \mcal_ADR_dly_reg[0][132]_0 ;

  wire [0:0]D;
  wire [3:0]Q;
  wire [0:0]SR;
  wire [0:0]actReq;
  wire actReqR;
  wire actReqR_reg;
  wire [3:3]act_winPort_nxt;
  wire calDone;
  wire calDone_reg;
  wire [0:0]cal_BA;
  wire last;
  wire last10_i_1__1_n_0;
  wire last10_reg_n_0;
  wire last32_i_1__0_n_0;
  wire last32_i_2__0_n_0;
  wire last32_reg_n_0;
  wire last_i_1__1_n_0;
  wire [16:0]mc_ADR;
  wire [0:0]mc_BA;
  wire \mcal_ADR_dly_reg[0][100] ;
  wire \mcal_ADR_dly_reg[0][108] ;
  wire \mcal_ADR_dly_reg[0][116] ;
  wire \mcal_ADR_dly_reg[0][124] ;
  wire \mcal_ADR_dly_reg[0][12] ;
  wire [17:0]\mcal_ADR_dly_reg[0][132] ;
  wire \mcal_ADR_dly_reg[0][132]_0 ;
  wire \mcal_ADR_dly_reg[0][20] ;
  wire \mcal_ADR_dly_reg[0][28] ;
  wire \mcal_ADR_dly_reg[0][36] ;
  wire \mcal_ADR_dly_reg[0][44] ;
  wire \mcal_ADR_dly_reg[0][4] ;
  wire \mcal_ADR_dly_reg[0][4]_0 ;
  wire \mcal_ADR_dly_reg[0][52] ;
  wire \mcal_ADR_dly_reg[0][60] ;
  wire \mcal_ADR_dly_reg[0][68] ;
  wire \mcal_ADR_dly_reg[0][76] ;
  wire \mcal_ADR_dly_reg[0][84] ;
  wire \mcal_ADR_dly_reg[0][92] ;
  wire \mcal_BA_dly_reg[0][4] ;
  wire \mcal_PAR_dly[0][4]_i_4_n_0 ;
  wire \mcal_PAR_dly[0][4]_i_5_n_0 ;
  wire \mcal_PAR_dly[0][4]_i_6_n_0 ;
  wire \mcal_PAR_dly[0][4]_i_7_n_0 ;
  wire out;
  wire [0:0]p_0_in;
  wire [0:0]rst_r1_reg;
  wire [0:0]rst_r1_reg_0;
  wire [0:0]rst_r1_reg_1;
  wire [0:0]rst_r1_reg_2;
  wire [0:0]rst_r1_reg_3;
  wire [0:0]rst_r1_reg_4;
  wire [0:0]rst_r1_reg_5;
  wire winAct_i_2_n_0;
  wire winAct_i_3_n_0;
  wire winAct_nxt;
  wire winAct_reg_0;
  wire [0:0]winAct_reg_1;
  wire winAct_reg_2;
  wire [0:0]winBankA;
  wire [0:0]winGroupA;
  wire \winPort[0]_i_1__0_n_0 ;
  wire \winPort[1]_i_1__0_n_0 ;
  wire \winPort[1]_i_2__1_n_0 ;
  wire \winPort[2]_i_1__0_n_0 ;
  wire \winPort[3]_i_2__0_n_0 ;
  wire \winPort[3]_i_3__1_n_0 ;
  wire \winPort_reg[0]_0 ;
  wire \winPort_reg[0]_1 ;
  wire \winPort_reg[0]_2 ;
  wire \winPort_reg[0]_3 ;
  wire \winPort_reg[0]_4 ;
  wire \winPort_reg[0]_5 ;
  wire \winPort_reg[0]_6 ;
  wire \winPort_reg[0]_7 ;
  wire [0:0]\winPort_reg[0]_8 ;
  wire \winPort_reg[1]_0 ;
  wire [0:0]\winPort_reg[2]_0 ;
  wire \winPort_reg[3]_0 ;
  wire \winPort_reg[3]_1 ;

  (* SOFT_HLUTNM = "soft_lutpair2786" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \act_shift_slr[0][0]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(D));
  (* SOFT_HLUTNM = "soft_lutpair2788" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    last10_i_1__1
       (.I0(\winPort[1]_i_2__1_n_0 ),
        .I1(\winPort[3]_i_3__1_n_0 ),
        .I2(last10_reg_n_0),
        .O(last10_i_1__1_n_0));
  FDRE last10_reg
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(last10_i_1__1_n_0),
        .Q(last10_reg_n_0),
        .R(out));
  LUT6 #(
    .INIT(64'h2222FFFFD0D000D0)) 
    last32_i_1__0
       (.I0(last),
        .I1(last32_i_2__0_n_0),
        .I2(actReq),
        .I3(winAct_i_2_n_0),
        .I4(\winPort[3]_i_2__0_n_0 ),
        .I5(last32_reg_n_0),
        .O(last32_i_1__0_n_0));
  LUT5 #(
    .INIT(32'hFFFFD0DD)) 
    last32_i_2__0
       (.I0(winAct_reg_2),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(actReqR),
        .I4(winAct_i_2_n_0),
        .O(last32_i_2__0_n_0));
  FDRE last32_reg
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(last32_i_1__0_n_0),
        .Q(last32_reg_n_0),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2787" *) 
  LUT3 #(
    .INIT(8'hA3)) 
    last_i_1__1
       (.I0(last32_i_2__0_n_0),
        .I1(winAct_i_3_n_0),
        .I2(last),
        .O(last_i_1__1_n_0));
  FDRE last_reg
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(last_i_1__1_n_0),
        .Q(last),
        .R(out));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][100]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][100] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [13]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[12]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][108]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][108] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [14]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[13]));
  LUT4 #(
    .INIT(16'hB8FF)) 
    \mcal_ADR_dly[0][116]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][132] [15]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][116] ),
        .I3(winAct_reg_0),
        .O(mc_ADR[14]));
  LUT4 #(
    .INIT(16'hB8FF)) 
    \mcal_ADR_dly[0][124]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][132] [16]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][124] ),
        .I3(winAct_reg_0),
        .O(mc_ADR[15]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][12]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][12] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [2]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[1]));
  LUT4 #(
    .INIT(16'hB8FF)) 
    \mcal_ADR_dly[0][132]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][132] [17]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132]_0 ),
        .I3(winAct_reg_0),
        .O(mc_ADR[16]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][20]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][20] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [3]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[2]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][28]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][28] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [4]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[3]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][36]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][36] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [5]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[4]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][44]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][44] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [6]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[5]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][4]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][4] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [1]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[0]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][52]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][52] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [7]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[6]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][60]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][60] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [8]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[7]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][68]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][68] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [9]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[8]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][76]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][76] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [10]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[9]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][84]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][84] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [11]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[10]));
  LUT5 #(
    .INIT(32'hE2FFE200)) 
    \mcal_ADR_dly[0][92]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][92] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [12]),
        .I3(winAct_reg_0),
        .I4(\mcal_ADR_dly_reg[0][4]_0 ),
        .O(mc_ADR[11]));
  LUT2 #(
    .INIT(4'hB)) 
    \mcal_BA_dly[0][12]_i_2 
       (.I0(winBankA),
        .I1(winAct_reg_0),
        .O(mc_BA));
  LUT6 #(
    .INIT(64'hE2FFFFFFE2FF0000)) 
    \mcal_BA_dly[0][4]_i_1 
       (.I0(\mcal_BA_dly_reg[0][4] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [0]),
        .I3(winAct_reg_0),
        .I4(calDone),
        .I5(cal_BA),
        .O(\winPort_reg[0]_8 ));
  LUT4 #(
    .INIT(16'hBFB0)) 
    \mcal_BG_dly[0][4]_i_1 
       (.I0(winGroupA),
        .I1(winAct_reg_0),
        .I2(calDone),
        .I3(p_0_in),
        .O(winAct_reg_1));
  LUT6 #(
    .INIT(64'h69969669FFFFFFFF)) 
    \mcal_PAR_dly[0][4]_i_2 
       (.I0(\mcal_PAR_dly[0][4]_i_4_n_0 ),
        .I1(mc_BA),
        .I2(\mcal_PAR_dly[0][4]_i_5_n_0 ),
        .I3(\mcal_PAR_dly[0][4]_i_6_n_0 ),
        .I4(\mcal_PAR_dly[0][4]_i_7_n_0 ),
        .I5(calDone),
        .O(calDone_reg));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][4]_i_4 
       (.I0(mc_ADR[4]),
        .I1(mc_ADR[5]),
        .I2(mc_ADR[1]),
        .I3(mc_ADR[0]),
        .I4(mc_ADR[3]),
        .I5(mc_ADR[2]),
        .O(\mcal_PAR_dly[0][4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h9669699669969669)) 
    \mcal_PAR_dly[0][4]_i_5 
       (.I0(winAct_reg_0),
        .I1(mc_ADR[16]),
        .I2(mc_ADR[13]),
        .I3(mc_ADR[12]),
        .I4(mc_ADR[15]),
        .I5(mc_ADR[14]),
        .O(\mcal_PAR_dly[0][4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][4]_i_6 
       (.I0(mc_ADR[10]),
        .I1(mc_ADR[11]),
        .I2(mc_ADR[7]),
        .I3(mc_ADR[6]),
        .I4(mc_ADR[9]),
        .I5(mc_ADR[8]),
        .O(\mcal_PAR_dly[0][4]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h1D00E200)) 
    \mcal_PAR_dly[0][4]_i_7 
       (.I0(\mcal_BA_dly_reg[0][4] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [0]),
        .I3(winAct_reg_0),
        .I4(winGroupA),
        .O(\mcal_PAR_dly[0][4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAA200A2A2)) 
    \outstanding_act_slr[0][4]_i_2 
       (.I0(winAct_i_3_n_0),
        .I1(winAct_reg_2),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(actReqR),
        .I5(winAct_i_2_n_0),
        .O(actReqR_reg));
  LUT2 #(
    .INIT(4'hE)) 
    \timerRAS[0][0][0][0][2]_i_1 
       (.I0(out),
        .I1(\winPort_reg[0]_1 ),
        .O(rst_r1_reg_4));
  LUT6 #(
    .INIT(64'h0000000000001D00)) 
    \timerRAS[0][0][0][0][2]_i_4 
       (.I0(\mcal_BA_dly_reg[0][4] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [0]),
        .I3(winAct_reg_0),
        .I4(winGroupA),
        .I5(winBankA),
        .O(\winPort_reg[0]_1 ));
  LUT2 #(
    .INIT(4'hE)) 
    \timerRAS[0][0][0][1][2]_i_1 
       (.I0(out),
        .I1(\winPort_reg[0]_3 ),
        .O(rst_r1_reg_2));
  LUT6 #(
    .INIT(64'h000000000000E200)) 
    \timerRAS[0][0][0][1][2]_i_4 
       (.I0(\mcal_BA_dly_reg[0][4] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [0]),
        .I3(winAct_reg_0),
        .I4(winGroupA),
        .I5(winBankA),
        .O(\winPort_reg[0]_3 ));
  LUT2 #(
    .INIT(4'hE)) 
    \timerRAS[0][0][0][2][2]_i_1 
       (.I0(out),
        .I1(\winPort_reg[0]_5 ),
        .O(rst_r1_reg_0));
  LUT6 #(
    .INIT(64'h00001D0000000000)) 
    \timerRAS[0][0][0][2][2]_i_4 
       (.I0(\mcal_BA_dly_reg[0][4] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [0]),
        .I3(winAct_reg_0),
        .I4(winGroupA),
        .I5(winBankA),
        .O(\winPort_reg[0]_5 ));
  LUT2 #(
    .INIT(4'hE)) 
    \timerRAS[0][0][0][3][2]_i_1 
       (.I0(out),
        .I1(\winPort_reg[0]_7 ),
        .O(SR));
  LUT6 #(
    .INIT(64'h0000E20000000000)) 
    \timerRAS[0][0][0][3][2]_i_4 
       (.I0(\mcal_BA_dly_reg[0][4] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [0]),
        .I3(winAct_reg_0),
        .I4(winGroupA),
        .I5(winBankA),
        .O(\winPort_reg[0]_7 ));
  LUT2 #(
    .INIT(4'hE)) 
    \timerRAS[0][0][1][0][2]_i_1 
       (.I0(out),
        .I1(\winPort_reg[0]_0 ),
        .O(rst_r1_reg_5));
  LUT6 #(
    .INIT(64'h00001D0000000000)) 
    \timerRAS[0][0][1][0][2]_i_4 
       (.I0(\mcal_BA_dly_reg[0][4] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [0]),
        .I3(winAct_reg_0),
        .I4(winBankA),
        .I5(winGroupA),
        .O(\winPort_reg[0]_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \timerRAS[0][0][1][1][2]_i_1 
       (.I0(out),
        .I1(\winPort_reg[0]_2 ),
        .O(rst_r1_reg_3));
  LUT6 #(
    .INIT(64'h0000E20000000000)) 
    \timerRAS[0][0][1][1][2]_i_4 
       (.I0(\mcal_BA_dly_reg[0][4] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [0]),
        .I3(winAct_reg_0),
        .I4(winBankA),
        .I5(winGroupA),
        .O(\winPort_reg[0]_2 ));
  LUT2 #(
    .INIT(4'hE)) 
    \timerRAS[0][0][1][2][2]_i_1 
       (.I0(out),
        .I1(\winPort_reg[0]_4 ),
        .O(rst_r1_reg_1));
  LUT6 #(
    .INIT(64'h1D00000000000000)) 
    \timerRAS[0][0][1][2][2]_i_4 
       (.I0(\mcal_BA_dly_reg[0][4] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [0]),
        .I3(winAct_reg_0),
        .I4(winBankA),
        .I5(winGroupA),
        .O(\winPort_reg[0]_4 ));
  LUT2 #(
    .INIT(4'hE)) 
    \timerRAS[0][0][1][3][2]_i_1 
       (.I0(out),
        .I1(\winPort_reg[0]_6 ),
        .O(rst_r1_reg));
  LUT6 #(
    .INIT(64'hE200000000000000)) 
    \timerRAS[0][0][1][3][2]_i_4 
       (.I0(\mcal_BA_dly_reg[0][4] ),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][132] [0]),
        .I3(winAct_reg_0),
        .I4(winBankA),
        .I5(winGroupA),
        .O(\winPort_reg[0]_6 ));
  LUT6 #(
    .INIT(64'h04550404FFFFFFFF)) 
    winAct_i_1
       (.I0(winAct_i_2_n_0),
        .I1(actReqR),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(winAct_reg_2),
        .I5(winAct_i_3_n_0),
        .O(winAct_nxt));
  (* SOFT_HLUTNM = "soft_lutpair2786" *) 
  LUT5 #(
    .INIT(32'hAAABABBE)) 
    winAct_i_2
       (.I0(\winPort_reg[2]_0 ),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(winAct_i_2_n_0));
  LUT5 #(
    .INIT(32'hFDFDF0FD)) 
    winAct_i_3
       (.I0(\winPort_reg[1]_0 ),
        .I1(Q[2]),
        .I2(winAct_i_2_n_0),
        .I3(\winPort_reg[3]_1 ),
        .I4(Q[3]),
        .O(winAct_i_3_n_0));
  FDRE winAct_reg
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(winAct_nxt),
        .Q(winAct_reg_0),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2788" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \winPort[0]_i_1__0 
       (.I0(\winPort[3]_i_3__1_n_0 ),
        .I1(\winPort[1]_i_2__1_n_0 ),
        .O(\winPort[0]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hA8)) 
    \winPort[1]_i_1__0 
       (.I0(\winPort[1]_i_2__1_n_0 ),
        .I1(winAct_i_3_n_0),
        .I2(last),
        .O(\winPort[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0202000202020202)) 
    \winPort[1]_i_2__1 
       (.I0(winAct_reg_2),
        .I1(Q[1]),
        .I2(winAct_i_2_n_0),
        .I3(actReqR),
        .I4(Q[0]),
        .I5(last10_reg_n_0),
        .O(\winPort[1]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h0000FB00)) 
    \winPort[2]_i_1__0 
       (.I0(Q[3]),
        .I1(\winPort_reg[3]_1 ),
        .I2(last32_reg_n_0),
        .I3(\winPort[3]_i_2__0_n_0 ),
        .I4(\winPort[3]_i_3__1_n_0 ),
        .O(\winPort[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000700)) 
    \winPort[3]_i_1__0 
       (.I0(last32_reg_n_0),
        .I1(\winPort[3]_i_2__0_n_0 ),
        .I2(Q[3]),
        .I3(\winPort_reg[3]_1 ),
        .I4(winAct_i_2_n_0),
        .I5(\winPort[3]_i_3__1_n_0 ),
        .O(act_winPort_nxt));
  LUT6 #(
    .INIT(64'h0000000000A80082)) 
    \winPort[3]_i_2__0 
       (.I0(\winPort_reg[1]_0 ),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\winPort_reg[2]_0 ),
        .O(\winPort[3]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2787" *) 
  LUT3 #(
    .INIT(8'h54)) 
    \winPort[3]_i_3__1 
       (.I0(last32_i_2__0_n_0),
        .I1(winAct_i_3_n_0),
        .I2(last),
        .O(\winPort[3]_i_3__1_n_0 ));
  FDRE \winPort_reg[0] 
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(\winPort[0]_i_1__0_n_0 ),
        .Q(Q[0]),
        .R(out));
  FDRE \winPort_reg[1] 
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(\winPort[1]_i_1__0_n_0 ),
        .Q(Q[1]),
        .R(out));
  FDRE \winPort_reg[2] 
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(\winPort[2]_i_1__0_n_0 ),
        .Q(Q[2]),
        .R(out));
  FDRE \winPort_reg[3] 
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(act_winPort_nxt),
        .Q(Q[3]),
        .R(out));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_arb_c" *) 
module ddr4_0_ddr4_v2_2_17_mc_arb_c
   (winRead,
    winWrite,
    win_group_cas,
    D,
    Q,
    \cmd_bank_cas_reg[0] ,
    \cmd_bank_cas_reg[0]_0 ,
    \cmd_bank_cas_reg[0]_1 ,
    \cmd_bank_cas_reg[0]_2 ,
    \cmd_bank_cas_reg[0]_3 ,
    \cmd_bank_cas_reg[0]_4 ,
    \cmd_bank_cas_reg[0]_5 ,
    \cmd_bank_cas_reg[0]_6 ,
    mc_ADR,
    mc_BG,
    mc_BA,
    winRead_reg_0,
    calDone_reg,
    calDone_reg_0,
    calDone_reg_1,
    winWrite_reg_0,
    wrCAS_reg,
    wrCAS_reg_0,
    wrCAS_reg_1,
    wrCAS_reg_2,
    wrCAS_reg_3,
    wrCAS_reg_4,
    wrCAS_reg_5,
    wrCAS_reg_6,
    wrCAS_reg_7,
    wrCAS_reg_8,
    wrCAS_reg_9,
    wrCAS_reg_10,
    wrCAS_reg_11,
    SR,
    clrReq13_out,
    clrReq15_out,
    clrReq17_out,
    clrReq1,
    winWrite_reg_1,
    d_prevGroup,
    mc_ODT,
    winRead_reg_1,
    winRead_reg_2,
    winWrite_reg_2,
    winWrite_reg_3,
    winWrite_reg_4,
    winWrite_reg_5,
    winWrite_reg_6,
    winWrite_reg_7,
    winWrite_reg_8,
    winWrite_reg_9,
    out,
    tranSentC,
    \win_bank_cas_reg[1]_0 ,
    interval_counter_reset,
    cmdInjTxn,
    cmd_bank_cas,
    \timerWTP_reg[0][0][0][3][1] ,
    \timerWTP_reg[0][0][0][3][1]_0 ,
    winGroupC,
    \mcal_ADR_dly_reg[0][74] ,
    \mcal_ADR_dly_reg[0][74]_0 ,
    \wrQ_reg[1][2] ,
    \mcal_ADR_dly_reg[0][74]_1 ,
    \mcal_ADR_dly_reg[0][66] ,
    \mcal_ADR_dly_reg[0][58] ,
    \mcal_ADR_dly_reg[0][50] ,
    \mcal_ADR_dly_reg[0][42] ,
    \mcal_ADR_dly_reg[0][34] ,
    \mcal_ADR_dly_reg[0][26] ,
    \mcal_ODT_dly_reg[0][6] ,
    calDone,
    \mcal_ODT_dly_reg[0][7] ,
    \mcal_PAR_dly_reg[0][5] ,
    \mcal_PAR_dly[0][6]_i_2_0 ,
    \mcal_PAR_dly_reg[0][1] ,
    oe_0_mux_cal,
    oe_fabric,
    \wrQ_reg[0][5]_rep__1 ,
    calWrCAS,
    \wrQ_reg[0][8]_rep__1 ,
    \wrQ_reg[0][6]_rep__1 ,
    \wrQ_reg[0][7]_rep__1 ,
    \wrQ_reg[0][8]_rep__1_0 ,
    cmd_group_cas,
    winWrite_reg_10,
    block_writes,
    rtw_okr,
    winWrite_reg_11,
    wrReqR,
    winWrite_i_5_0,
    block_reads,
    \prevGr_reg[0] ,
    per_cas_block_req,
    wrReqR_reg,
    wtr_oksr,
    wtr_oklr,
    rdReqR,
    winRead_i_4_0,
    \winPort[3]_i_5__0_0 ,
    \winPort[3]_i_6__0_0 ,
    \timerWTP_reg[0][0][0][3][1]_1 ,
    \timerWTP_reg[0][0][1][3][1] ,
    \timerWTP_reg[0][0][0][2][1] ,
    \timerWTP_reg[0][0][1][2][1] ,
    \timerWTP_reg[0][0][0][1][1] ,
    \timerWTP_reg[0][0][1][1][1] ,
    \timerWTP_reg[0][0][0][0][1] ,
    \timerWTP_reg[0][0][1][0][1] );
  output winRead;
  output winWrite;
  output [0:0]win_group_cas;
  output [0:0]D;
  output [3:0]Q;
  output \cmd_bank_cas_reg[0] ;
  output \cmd_bank_cas_reg[0]_0 ;
  output \cmd_bank_cas_reg[0]_1 ;
  output \cmd_bank_cas_reg[0]_2 ;
  output \cmd_bank_cas_reg[0]_3 ;
  output \cmd_bank_cas_reg[0]_4 ;
  output \cmd_bank_cas_reg[0]_5 ;
  output \cmd_bank_cas_reg[0]_6 ;
  output [15:0]mc_ADR;
  output [1:0]mc_BG;
  output [3:0]mc_BA;
  output [1:0]winRead_reg_0;
  output calDone_reg;
  output calDone_reg_0;
  output [4:0]calDone_reg_1;
  output winWrite_reg_0;
  output [3:0]wrCAS_reg;
  output wrCAS_reg_0;
  output wrCAS_reg_1;
  output wrCAS_reg_2;
  output wrCAS_reg_3;
  output wrCAS_reg_4;
  output wrCAS_reg_5;
  output wrCAS_reg_6;
  output wrCAS_reg_7;
  output wrCAS_reg_8;
  output wrCAS_reg_9;
  output wrCAS_reg_10;
  output wrCAS_reg_11;
  output [0:0]SR;
  output clrReq13_out;
  output clrReq15_out;
  output clrReq17_out;
  output clrReq1;
  output winWrite_reg_1;
  output d_prevGroup;
  output [0:0]mc_ODT;
  output winRead_reg_1;
  output [0:0]winRead_reg_2;
  output [1:0]winWrite_reg_2;
  output [1:0]winWrite_reg_3;
  output [1:0]winWrite_reg_4;
  output [1:0]winWrite_reg_5;
  output [1:0]winWrite_reg_6;
  output [1:0]winWrite_reg_7;
  output [1:0]winWrite_reg_8;
  output [1:0]winWrite_reg_9;
  input out;
  input tranSentC;
  input \win_bank_cas_reg[1]_0 ;
  input interval_counter_reset;
  input [0:0]cmdInjTxn;
  input [7:0]cmd_bank_cas;
  input \timerWTP_reg[0][0][0][3][1] ;
  input \timerWTP_reg[0][0][0][3][1]_0 ;
  input [0:0]winGroupC;
  input [6:0]\mcal_ADR_dly_reg[0][74] ;
  input \mcal_ADR_dly_reg[0][74]_0 ;
  input \wrQ_reg[1][2] ;
  input \mcal_ADR_dly_reg[0][74]_1 ;
  input \mcal_ADR_dly_reg[0][66] ;
  input \mcal_ADR_dly_reg[0][58] ;
  input \mcal_ADR_dly_reg[0][50] ;
  input \mcal_ADR_dly_reg[0][42] ;
  input \mcal_ADR_dly_reg[0][34] ;
  input \mcal_ADR_dly_reg[0][26] ;
  input [1:0]\mcal_ODT_dly_reg[0][6] ;
  input calDone;
  input \mcal_ODT_dly_reg[0][7] ;
  input \mcal_PAR_dly_reg[0][5] ;
  input [1:0]\mcal_PAR_dly[0][6]_i_2_0 ;
  input \mcal_PAR_dly_reg[0][1] ;
  input [0:0]oe_0_mux_cal;
  input [0:0]oe_fabric;
  input \wrQ_reg[0][5]_rep__1 ;
  input calWrCAS;
  input [3:0]\wrQ_reg[0][8]_rep__1 ;
  input \wrQ_reg[0][6]_rep__1 ;
  input \wrQ_reg[0][7]_rep__1 ;
  input \wrQ_reg[0][8]_rep__1_0 ;
  input [3:0]cmd_group_cas;
  input winWrite_reg_10;
  input block_writes;
  input rtw_okr;
  input winWrite_reg_11;
  input wrReqR;
  input winWrite_i_5_0;
  input block_reads;
  input \prevGr_reg[0] ;
  input per_cas_block_req;
  input wrReqR_reg;
  input wtr_oksr;
  input wtr_oklr;
  input rdReqR;
  input winRead_i_4_0;
  input \winPort[3]_i_5__0_0 ;
  input \winPort[3]_i_6__0_0 ;
  input [1:0]\timerWTP_reg[0][0][0][3][1]_1 ;
  input [1:0]\timerWTP_reg[0][0][1][3][1] ;
  input [1:0]\timerWTP_reg[0][0][0][2][1] ;
  input [1:0]\timerWTP_reg[0][0][1][2][1] ;
  input [1:0]\timerWTP_reg[0][0][0][1][1] ;
  input [1:0]\timerWTP_reg[0][0][1][1][1] ;
  input [1:0]\timerWTP_reg[0][0][0][0][1] ;
  input [1:0]\timerWTP_reg[0][0][1][0][1] ;

  wire [0:0]D;
  wire [3:0]Q;
  wire [0:0]SR;
  wire block_reads;
  wire block_writes;
  wire calDone;
  wire calDone_reg;
  wire calDone_reg_0;
  wire [4:0]calDone_reg_1;
  wire calWrCAS;
  wire clrReq1;
  wire clrReq13_out;
  wire clrReq15_out;
  wire clrReq17_out;
  wire [0:0]cmdInjTxn;
  wire [7:0]cmd_bank_cas;
  wire \cmd_bank_cas_reg[0] ;
  wire \cmd_bank_cas_reg[0]_0 ;
  wire \cmd_bank_cas_reg[0]_1 ;
  wire \cmd_bank_cas_reg[0]_2 ;
  wire \cmd_bank_cas_reg[0]_3 ;
  wire \cmd_bank_cas_reg[0]_4 ;
  wire \cmd_bank_cas_reg[0]_5 ;
  wire \cmd_bank_cas_reg[0]_6 ;
  wire [3:0]cmd_group_cas;
  wire d_prevGroup;
  wire interval_counter_reset;
  wire last10_i_1__0_n_0;
  wire last10_reg_n_0;
  wire last32_i_1_n_0;
  wire last32_reg_n_0;
  wire last_i_1__0_n_0;
  wire last_reg_n_0;
  wire [15:0]mc_ADR;
  wire [3:0]mc_BA;
  wire [1:0]mc_BG;
  wire [0:0]mc_ODT;
  wire \mcal_ADR_dly_reg[0][26] ;
  wire \mcal_ADR_dly_reg[0][34] ;
  wire \mcal_ADR_dly_reg[0][42] ;
  wire \mcal_ADR_dly_reg[0][50] ;
  wire \mcal_ADR_dly_reg[0][58] ;
  wire \mcal_ADR_dly_reg[0][66] ;
  wire [6:0]\mcal_ADR_dly_reg[0][74] ;
  wire \mcal_ADR_dly_reg[0][74]_0 ;
  wire \mcal_ADR_dly_reg[0][74]_1 ;
  wire [1:0]\mcal_ODT_dly_reg[0][6] ;
  wire \mcal_ODT_dly_reg[0][7] ;
  wire \mcal_PAR_dly[0][2]_i_4_n_0 ;
  wire \mcal_PAR_dly[0][2]_i_6_n_0 ;
  wire [1:0]\mcal_PAR_dly[0][6]_i_2_0 ;
  wire \mcal_PAR_dly[0][6]_i_4_n_0 ;
  wire \mcal_PAR_dly[0][6]_i_6_n_0 ;
  wire \mcal_PAR_dly_reg[0][1] ;
  wire \mcal_PAR_dly_reg[0][5] ;
  wire [0:0]oe_0_mux_cal;
  wire [0:0]oe_fabric;
  wire out;
  wire per_cas_block_req;
  wire \prevGr_reg[0] ;
  wire [3:0]rdReq;
  wire rdReqR;
  wire rtw_okr;
  wire [1:0]\timerWTP_reg[0][0][0][0][1] ;
  wire [1:0]\timerWTP_reg[0][0][0][1][1] ;
  wire [1:0]\timerWTP_reg[0][0][0][2][1] ;
  wire \timerWTP_reg[0][0][0][3][1] ;
  wire \timerWTP_reg[0][0][0][3][1]_0 ;
  wire [1:0]\timerWTP_reg[0][0][0][3][1]_1 ;
  wire [1:0]\timerWTP_reg[0][0][1][0][1] ;
  wire [1:0]\timerWTP_reg[0][0][1][1][1] ;
  wire [1:0]\timerWTP_reg[0][0][1][2][1] ;
  wire [1:0]\timerWTP_reg[0][0][1][3][1] ;
  wire tranSentC;
  wire [3:3]win3210;
  wire [0:0]winGroupC;
  wire \winPort[0]_i_1_n_0 ;
  wire \winPort[0]_i_2_n_0 ;
  wire \winPort[1]_i_1_n_0 ;
  wire \winPort[1]_i_2__0_n_0 ;
  wire \winPort[2]_i_1_n_0 ;
  wire \winPort[3]_i_11_n_0 ;
  wire \winPort[3]_i_12_n_0 ;
  wire \winPort[3]_i_3__0_n_0 ;
  wire \winPort[3]_i_4__0_n_0 ;
  wire \winPort[3]_i_5__0_0 ;
  wire \winPort[3]_i_5__0_n_0 ;
  wire \winPort[3]_i_6__0_0 ;
  wire \winPort[3]_i_6__0_n_0 ;
  wire \winPort[3]_i_7__0_n_0 ;
  wire \winPort[3]_i_8__0_n_0 ;
  wire \winPort[3]_i_9_n_0 ;
  wire winRead;
  wire winRead_3;
  wire winRead_i_2_n_0;
  wire winRead_i_3_n_0;
  wire winRead_i_4_0;
  wire winRead_i_4_n_0;
  wire [1:0]winRead_reg_0;
  wire winRead_reg_1;
  wire [0:0]winRead_reg_2;
  wire winWrite;
  wire winWrite_0;
  wire winWrite_i_2_n_0;
  wire winWrite_i_3_n_0;
  wire winWrite_i_4_n_0;
  wire winWrite_i_5_0;
  wire winWrite_i_5_n_0;
  wire winWrite_i_6_n_0;
  wire winWrite_i_7_n_0;
  wire winWrite_reg_0;
  wire winWrite_reg_1;
  wire winWrite_reg_10;
  wire winWrite_reg_11;
  wire [1:0]winWrite_reg_2;
  wire [1:0]winWrite_reg_3;
  wire [1:0]winWrite_reg_4;
  wire [1:0]winWrite_reg_5;
  wire [1:0]winWrite_reg_6;
  wire [1:0]winWrite_reg_7;
  wire [1:0]winWrite_reg_8;
  wire [1:0]winWrite_reg_9;
  wire [1:0]win_bank_cas;
  wire \win_bank_cas[0]_i_2_n_0 ;
  wire \win_bank_cas[0]_i_3_n_0 ;
  wire \win_bank_cas[1]_i_2_n_0 ;
  wire \win_bank_cas[1]_i_3_n_0 ;
  wire [1:0]win_bank_cas_1;
  wire \win_bank_cas_reg[1]_0 ;
  wire [0:0]win_group_cas;
  wire \win_group_cas[0]_i_2_n_0 ;
  wire \win_group_cas[0]_i_3_n_0 ;
  wire [0:0]win_group_cas_2;
  wire [3:0]wrCAS_reg;
  wire wrCAS_reg_0;
  wire wrCAS_reg_1;
  wire wrCAS_reg_10;
  wire wrCAS_reg_11;
  wire wrCAS_reg_2;
  wire wrCAS_reg_3;
  wire wrCAS_reg_4;
  wire wrCAS_reg_5;
  wire wrCAS_reg_6;
  wire wrCAS_reg_7;
  wire wrCAS_reg_8;
  wire wrCAS_reg_9;
  wire \wrQ_reg[0][5]_rep__1 ;
  wire \wrQ_reg[0][6]_rep__1 ;
  wire \wrQ_reg[0][7]_rep__1 ;
  wire [3:0]\wrQ_reg[0][8]_rep__1 ;
  wire \wrQ_reg[0][8]_rep__1_0 ;
  wire \wrQ_reg[1][2] ;
  wire wrReqR;
  wire wrReqR_reg;
  wire wtr_oklr;
  wire wtr_oksr;

  LUT5 #(
    .INIT(32'hBF250000)) 
    \FSM_sequential_gr_cas_state[2]_i_4 
       (.I0(winWrite),
        .I1(per_cas_block_req),
        .I2(winRead),
        .I3(wrReqR_reg),
        .I4(Q[0]),
        .O(clrReq13_out));
  LUT5 #(
    .INIT(32'hBF250000)) 
    \FSM_sequential_gr_cas_state[2]_i_4__0 
       (.I0(winWrite),
        .I1(per_cas_block_req),
        .I2(winRead),
        .I3(wrReqR_reg),
        .I4(Q[1]),
        .O(clrReq15_out));
  LUT5 #(
    .INIT(32'hBF250000)) 
    \FSM_sequential_gr_cas_state[2]_i_4__1 
       (.I0(winWrite),
        .I1(per_cas_block_req),
        .I2(winRead),
        .I3(wrReqR_reg),
        .I4(Q[2]),
        .O(clrReq17_out));
  LUT5 #(
    .INIT(32'hBF250000)) 
    \FSM_sequential_gr_cas_state[2]_i_4__2 
       (.I0(winWrite),
        .I1(per_cas_block_req),
        .I2(winRead),
        .I3(wrReqR_reg),
        .I4(Q[3]),
        .O(clrReq1));
  LUT5 #(
    .INIT(32'h40555555)) 
    \gap_pipe[0]_i_1 
       (.I0(interval_counter_reset),
        .I1(cmdInjTxn),
        .I2(Q[0]),
        .I3(tranSentC),
        .I4(winRead),
        .O(D));
  LUT4 #(
    .INIT(16'hF520)) 
    last10_i_1__0
       (.I0(tranSentC),
        .I1(\winPort[1]_i_2__0_n_0 ),
        .I2(\winPort[0]_i_2_n_0 ),
        .I3(last10_reg_n_0),
        .O(last10_i_1__0_n_0));
  FDRE last10_reg
       (.C(\win_bank_cas_reg[1]_0 ),
        .CE(1'b1),
        .D(last10_i_1__0_n_0),
        .Q(last10_reg_n_0),
        .R(out));
  LUT4 #(
    .INIT(16'hF704)) 
    last32_i_1
       (.I0(\winPort[3]_i_3__0_n_0 ),
        .I1(tranSentC),
        .I2(\winPort[3]_i_4__0_n_0 ),
        .I3(last32_reg_n_0),
        .O(last32_i_1_n_0));
  FDRE last32_reg
       (.C(\win_bank_cas_reg[1]_0 ),
        .CE(1'b1),
        .D(last32_i_1_n_0),
        .Q(last32_reg_n_0),
        .R(out));
  LUT5 #(
    .INIT(32'hC0FF4000)) 
    last_i_1__0
       (.I0(\winPort[3]_i_4__0_n_0 ),
        .I1(\winPort[0]_i_2_n_0 ),
        .I2(\winPort[1]_i_2__0_n_0 ),
        .I3(tranSentC),
        .I4(last_reg_n_0),
        .O(last_i_1__0_n_0));
  FDRE last_reg
       (.C(\win_bank_cas_reg[1]_0 ),
        .CE(1'b1),
        .D(last_i_1__0_n_0),
        .Q(last_reg_n_0),
        .R(out));
  LUT2 #(
    .INIT(4'h6)) 
    \mc_ADR7[14]_i_2 
       (.I0(winWrite),
        .I1(winRead),
        .O(d_prevGroup));
  (* SOFT_HLUTNM = "soft_lutpair2811" *) 
  LUT4 #(
    .INIT(16'hFF40)) 
    \mc_ODT7[0]_i_1 
       (.I0(winRead),
        .I1(winWrite),
        .I2(tranSentC),
        .I3(\mcal_ODT_dly_reg[0][6] [0]),
        .O(mc_ODT));
  (* SOFT_HLUTNM = "soft_lutpair2793" *) 
  LUT5 #(
    .INIT(32'hFFFF00B8)) 
    \mcal_ADR_dly[0][26]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [0]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][26] ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[2]));
  LUT6 #(
    .INIT(64'hD7FFD7D7D7D7D7D7)) 
    \mcal_ADR_dly[0][2]_i_2 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(\wrQ_reg[1][2] ),
        .I4(cmdInjTxn),
        .I5(Q[0]),
        .O(mc_ADR[0]));
  (* SOFT_HLUTNM = "soft_lutpair2793" *) 
  LUT5 #(
    .INIT(32'hFFFFB800)) 
    \mcal_ADR_dly[0][30]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [0]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][26] ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[3]));
  (* SOFT_HLUTNM = "soft_lutpair2797" *) 
  LUT5 #(
    .INIT(32'hFFFF00B8)) 
    \mcal_ADR_dly[0][34]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [1]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][34] ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[4]));
  (* SOFT_HLUTNM = "soft_lutpair2797" *) 
  LUT5 #(
    .INIT(32'hFFFFB800)) 
    \mcal_ADR_dly[0][38]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [1]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][34] ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[5]));
  (* SOFT_HLUTNM = "soft_lutpair2795" *) 
  LUT5 #(
    .INIT(32'hFFFF00B8)) 
    \mcal_ADR_dly[0][42]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [2]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][42] ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[6]));
  (* SOFT_HLUTNM = "soft_lutpair2795" *) 
  LUT5 #(
    .INIT(32'hFFFFB800)) 
    \mcal_ADR_dly[0][46]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [2]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][42] ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[7]));
  (* SOFT_HLUTNM = "soft_lutpair2796" *) 
  LUT5 #(
    .INIT(32'hFFFF00B8)) 
    \mcal_ADR_dly[0][50]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [3]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][50] ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[8]));
  (* SOFT_HLUTNM = "soft_lutpair2796" *) 
  LUT5 #(
    .INIT(32'hFFFFB800)) 
    \mcal_ADR_dly[0][54]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [3]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][50] ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[9]));
  (* SOFT_HLUTNM = "soft_lutpair2794" *) 
  LUT5 #(
    .INIT(32'hFFFF00B8)) 
    \mcal_ADR_dly[0][58]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [4]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][58] ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[10]));
  (* SOFT_HLUTNM = "soft_lutpair2794" *) 
  LUT5 #(
    .INIT(32'hFFFFB800)) 
    \mcal_ADR_dly[0][62]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [4]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][58] ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[11]));
  (* SOFT_HLUTNM = "soft_lutpair2799" *) 
  LUT5 #(
    .INIT(32'hFFFF00B8)) 
    \mcal_ADR_dly[0][66]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [5]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][66] ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[12]));
  LUT6 #(
    .INIT(64'hFFD7D7D7D7D7D7D7)) 
    \mcal_ADR_dly[0][6]_i_2 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(\wrQ_reg[1][2] ),
        .I4(cmdInjTxn),
        .I5(Q[0]),
        .O(mc_ADR[1]));
  (* SOFT_HLUTNM = "soft_lutpair2799" *) 
  LUT5 #(
    .INIT(32'hFFFFB800)) 
    \mcal_ADR_dly[0][70]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [5]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][66] ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[13]));
  (* SOFT_HLUTNM = "soft_lutpair2798" *) 
  LUT5 #(
    .INIT(32'hFFFF00B8)) 
    \mcal_ADR_dly[0][74]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [6]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][74]_0 ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[14]));
  (* SOFT_HLUTNM = "soft_lutpair2798" *) 
  LUT5 #(
    .INIT(32'hFFFFB800)) 
    \mcal_ADR_dly[0][78]_i_2 
       (.I0(\mcal_ADR_dly_reg[0][74] [6]),
        .I1(Q[0]),
        .I2(\mcal_ADR_dly_reg[0][74]_0 ),
        .I3(\wrQ_reg[1][2] ),
        .I4(\mcal_ADR_dly_reg[0][74]_1 ),
        .O(mc_ADR[15]));
  (* SOFT_HLUTNM = "soft_lutpair2789" *) 
  LUT5 #(
    .INIT(32'hFFFFFFD7)) 
    \mcal_BA_dly[0][10]_i_2 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(\wrQ_reg[1][2] ),
        .I4(win_bank_cas[1]),
        .O(mc_BA[2]));
  (* SOFT_HLUTNM = "soft_lutpair2789" *) 
  LUT5 #(
    .INIT(32'hFFFFD7FF)) 
    \mcal_BA_dly[0][14]_i_2 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(\wrQ_reg[1][2] ),
        .I4(win_bank_cas[1]),
        .O(mc_BA[3]));
  (* SOFT_HLUTNM = "soft_lutpair2801" *) 
  LUT5 #(
    .INIT(32'hFFFFFFD7)) 
    \mcal_BA_dly[0][2]_i_2 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(\wrQ_reg[1][2] ),
        .I4(win_bank_cas[0]),
        .O(mc_BA[0]));
  (* SOFT_HLUTNM = "soft_lutpair2801" *) 
  LUT5 #(
    .INIT(32'hFFFFD7FF)) 
    \mcal_BA_dly[0][6]_i_2 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(\wrQ_reg[1][2] ),
        .I4(win_bank_cas[0]),
        .O(mc_BA[1]));
  (* SOFT_HLUTNM = "soft_lutpair2800" *) 
  LUT5 #(
    .INIT(32'hFFFFFFD7)) 
    \mcal_BG_dly[0][2]_i_2 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(\wrQ_reg[1][2] ),
        .I4(win_group_cas),
        .O(mc_BG[0]));
  (* SOFT_HLUTNM = "soft_lutpair2800" *) 
  LUT5 #(
    .INIT(32'hFFFFD7FF)) 
    \mcal_BG_dly[0][6]_i_2 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(\wrQ_reg[1][2] ),
        .I4(win_group_cas),
        .O(mc_BG[1]));
  LUT6 #(
    .INIT(64'hFF40FFFFFF400000)) 
    \mcal_ODT_dly[0][6]_i_1 
       (.I0(winRead),
        .I1(winWrite),
        .I2(tranSentC),
        .I3(\mcal_ODT_dly_reg[0][6] [1]),
        .I4(calDone),
        .I5(\mcal_ODT_dly_reg[0][7] ),
        .O(winRead_reg_0[0]));
  LUT6 #(
    .INIT(64'hFF40FFFFFF400000)) 
    \mcal_ODT_dly[0][7]_i_1 
       (.I0(winRead),
        .I1(winWrite),
        .I2(tranSentC),
        .I3(\mcal_ODT_dly_reg[0][6] [0]),
        .I4(calDone),
        .I5(\mcal_ODT_dly_reg[0][7] ),
        .O(winRead_reg_0[1]));
  LUT6 #(
    .INIT(64'h69969669FFFFFFFF)) 
    \mcal_PAR_dly[0][2]_i_2 
       (.I0(\mcal_PAR_dly[0][2]_i_4_n_0 ),
        .I1(\mcal_PAR_dly_reg[0][1] ),
        .I2(\mcal_PAR_dly[0][2]_i_6_n_0 ),
        .I3(mc_BG[0]),
        .I4(mc_BA[0]),
        .I5(calDone),
        .O(calDone_reg_0));
  LUT5 #(
    .INIT(32'h96696996)) 
    \mcal_PAR_dly[0][2]_i_4 
       (.I0(mc_BA[2]),
        .I1(mc_ADR[2]),
        .I2(mc_ADR[0]),
        .I3(mc_ADR[6]),
        .I4(mc_ADR[4]),
        .O(\mcal_PAR_dly[0][2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][2]_i_6 
       (.I0(\mcal_PAR_dly[0][6]_i_2_0 [0]),
        .I1(\mcal_ADR_dly_reg[0][74]_1 ),
        .I2(mc_ADR[10]),
        .I3(mc_ADR[8]),
        .I4(mc_ADR[14]),
        .I5(mc_ADR[12]),
        .O(\mcal_PAR_dly[0][2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h69969669FFFFFFFF)) 
    \mcal_PAR_dly[0][6]_i_2 
       (.I0(\mcal_PAR_dly[0][6]_i_4_n_0 ),
        .I1(\mcal_PAR_dly_reg[0][5] ),
        .I2(\mcal_PAR_dly[0][6]_i_6_n_0 ),
        .I3(mc_BG[1]),
        .I4(mc_BA[1]),
        .I5(calDone),
        .O(calDone_reg));
  LUT5 #(
    .INIT(32'h96696996)) 
    \mcal_PAR_dly[0][6]_i_4 
       (.I0(mc_BA[3]),
        .I1(mc_ADR[3]),
        .I2(mc_ADR[1]),
        .I3(mc_ADR[7]),
        .I4(mc_ADR[5]),
        .O(\mcal_PAR_dly[0][6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    \mcal_PAR_dly[0][6]_i_6 
       (.I0(\mcal_PAR_dly[0][6]_i_2_0 [1]),
        .I1(\mcal_ADR_dly_reg[0][74]_1 ),
        .I2(mc_ADR[11]),
        .I3(mc_ADR[9]),
        .I4(mc_ADR[15]),
        .I5(mc_ADR[13]),
        .O(\mcal_PAR_dly[0][6]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2811" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \odt_shift[0][20]_i_1__0 
       (.I0(winRead),
        .I1(winWrite),
        .I2(tranSentC),
        .O(winRead_reg_2));
  (* SOFT_HLUTNM = "soft_lutpair2810" *) 
  LUT4 #(
    .INIT(16'hBF80)) 
    \prevGr[0]_i_1 
       (.I0(winGroupC),
        .I1(winWrite),
        .I2(tranSentC),
        .I3(\prevGr_reg[0] ),
        .O(winWrite_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair2792" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    prevSlot2_i_3
       (.I0(winRead),
        .I1(per_cas_block_req),
        .I2(winWrite),
        .O(winRead_reg_1));
  LUT3 #(
    .INIT(8'hEA)) 
    \rtw[2]_i_1 
       (.I0(out),
        .I1(winRead),
        .I2(tranSentC),
        .O(SR));
  (* SOFT_HLUTNM = "soft_lutpair2808" *) 
  LUT3 #(
    .INIT(8'h3B)) 
    \timerWTP[0][0][0][0][0]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][0][1] [0]),
        .I2(\cmd_bank_cas_reg[0]_5 ),
        .O(winWrite_reg_8[0]));
  (* SOFT_HLUTNM = "soft_lutpair2808" *) 
  LUT4 #(
    .INIT(16'hC3EB)) 
    \timerWTP[0][0][0][0][1]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][0][1] [0]),
        .I2(\timerWTP_reg[0][0][0][0][1] [1]),
        .I3(\cmd_bank_cas_reg[0]_5 ),
        .O(winWrite_reg_8[1]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFBBFCB8)) 
    \timerWTP[0][0][0][0][3]_i_3 
       (.I0(cmd_bank_cas[0]),
        .I1(Q[0]),
        .I2(\timerWTP_reg[0][0][0][3][1] ),
        .I3(cmd_bank_cas[1]),
        .I4(\timerWTP_reg[0][0][0][3][1]_0 ),
        .I5(winGroupC),
        .O(\cmd_bank_cas_reg[0]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair2806" *) 
  LUT3 #(
    .INIT(8'h3B)) 
    \timerWTP[0][0][0][1][0]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][1][1] [0]),
        .I2(\cmd_bank_cas_reg[0]_3 ),
        .O(winWrite_reg_6[0]));
  (* SOFT_HLUTNM = "soft_lutpair2806" *) 
  LUT4 #(
    .INIT(16'hC3EB)) 
    \timerWTP[0][0][0][1][1]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][1][1] [0]),
        .I2(\timerWTP_reg[0][0][0][1][1] [1]),
        .I3(\cmd_bank_cas_reg[0]_3 ),
        .O(winWrite_reg_6[1]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF77CF47)) 
    \timerWTP[0][0][0][1][3]_i_3 
       (.I0(cmd_bank_cas[0]),
        .I1(Q[0]),
        .I2(\timerWTP_reg[0][0][0][3][1] ),
        .I3(cmd_bank_cas[1]),
        .I4(\timerWTP_reg[0][0][0][3][1]_0 ),
        .I5(winGroupC),
        .O(\cmd_bank_cas_reg[0]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair2804" *) 
  LUT3 #(
    .INIT(8'h3B)) 
    \timerWTP[0][0][0][2][0]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][2][1] [0]),
        .I2(\cmd_bank_cas_reg[0]_1 ),
        .O(winWrite_reg_4[0]));
  (* SOFT_HLUTNM = "soft_lutpair2804" *) 
  LUT4 #(
    .INIT(16'hC3EB)) 
    \timerWTP[0][0][0][2][1]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][2][1] [0]),
        .I2(\timerWTP_reg[0][0][0][2][1] [1]),
        .I3(\cmd_bank_cas_reg[0]_1 ),
        .O(winWrite_reg_4[1]));
  LUT6 #(
    .INIT(64'hFFFFFFFFB8FCBBFF)) 
    \timerWTP[0][0][0][2][3]_i_3 
       (.I0(cmd_bank_cas[0]),
        .I1(Q[0]),
        .I2(\timerWTP_reg[0][0][0][3][1] ),
        .I3(cmd_bank_cas[1]),
        .I4(\timerWTP_reg[0][0][0][3][1]_0 ),
        .I5(winGroupC),
        .O(\cmd_bank_cas_reg[0]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair2802" *) 
  LUT3 #(
    .INIT(8'h3B)) 
    \timerWTP[0][0][0][3][0]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][3][1]_1 [0]),
        .I2(\cmd_bank_cas_reg[0] ),
        .O(winWrite_reg_2[0]));
  (* SOFT_HLUTNM = "soft_lutpair2802" *) 
  LUT4 #(
    .INIT(16'hC3EB)) 
    \timerWTP[0][0][0][3][1]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][3][1]_1 [0]),
        .I2(\timerWTP_reg[0][0][0][3][1]_1 [1]),
        .I3(\cmd_bank_cas_reg[0] ),
        .O(winWrite_reg_2[1]));
  LUT6 #(
    .INIT(64'hFFFFFFFF47CF77FF)) 
    \timerWTP[0][0][0][3][3]_i_3 
       (.I0(cmd_bank_cas[0]),
        .I1(Q[0]),
        .I2(\timerWTP_reg[0][0][0][3][1] ),
        .I3(cmd_bank_cas[1]),
        .I4(\timerWTP_reg[0][0][0][3][1]_0 ),
        .I5(winGroupC),
        .O(\cmd_bank_cas_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair2809" *) 
  LUT3 #(
    .INIT(8'h3B)) 
    \timerWTP[0][0][1][0][0]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][0][1] [0]),
        .I2(\cmd_bank_cas_reg[0]_6 ),
        .O(winWrite_reg_9[0]));
  (* SOFT_HLUTNM = "soft_lutpair2809" *) 
  LUT4 #(
    .INIT(16'hC3EB)) 
    \timerWTP[0][0][1][0][1]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][0][1] [0]),
        .I2(\timerWTP_reg[0][0][1][0][1] [1]),
        .I3(\cmd_bank_cas_reg[0]_6 ),
        .O(winWrite_reg_9[1]));
  LUT6 #(
    .INIT(64'hFFBBFCB8FFFFFFFF)) 
    \timerWTP[0][0][1][0][3]_i_3 
       (.I0(cmd_bank_cas[0]),
        .I1(Q[0]),
        .I2(\timerWTP_reg[0][0][0][3][1] ),
        .I3(cmd_bank_cas[1]),
        .I4(\timerWTP_reg[0][0][0][3][1]_0 ),
        .I5(winGroupC),
        .O(\cmd_bank_cas_reg[0]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair2807" *) 
  LUT3 #(
    .INIT(8'h3B)) 
    \timerWTP[0][0][1][1][0]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][1][1] [0]),
        .I2(\cmd_bank_cas_reg[0]_4 ),
        .O(winWrite_reg_7[0]));
  (* SOFT_HLUTNM = "soft_lutpair2807" *) 
  LUT4 #(
    .INIT(16'hC3EB)) 
    \timerWTP[0][0][1][1][1]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][1][1] [0]),
        .I2(\timerWTP_reg[0][0][1][1][1] [1]),
        .I3(\cmd_bank_cas_reg[0]_4 ),
        .O(winWrite_reg_7[1]));
  LUT6 #(
    .INIT(64'hFF77CF47FFFFFFFF)) 
    \timerWTP[0][0][1][1][3]_i_3 
       (.I0(cmd_bank_cas[0]),
        .I1(Q[0]),
        .I2(\timerWTP_reg[0][0][0][3][1] ),
        .I3(cmd_bank_cas[1]),
        .I4(\timerWTP_reg[0][0][0][3][1]_0 ),
        .I5(winGroupC),
        .O(\cmd_bank_cas_reg[0]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair2805" *) 
  LUT3 #(
    .INIT(8'h3B)) 
    \timerWTP[0][0][1][2][0]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][2][1] [0]),
        .I2(\cmd_bank_cas_reg[0]_2 ),
        .O(winWrite_reg_5[0]));
  (* SOFT_HLUTNM = "soft_lutpair2805" *) 
  LUT4 #(
    .INIT(16'hC3EB)) 
    \timerWTP[0][0][1][2][1]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][2][1] [0]),
        .I2(\timerWTP_reg[0][0][1][2][1] [1]),
        .I3(\cmd_bank_cas_reg[0]_2 ),
        .O(winWrite_reg_5[1]));
  LUT6 #(
    .INIT(64'hB8FCBBFFFFFFFFFF)) 
    \timerWTP[0][0][1][2][3]_i_3 
       (.I0(cmd_bank_cas[0]),
        .I1(Q[0]),
        .I2(\timerWTP_reg[0][0][0][3][1] ),
        .I3(cmd_bank_cas[1]),
        .I4(\timerWTP_reg[0][0][0][3][1]_0 ),
        .I5(winGroupC),
        .O(\cmd_bank_cas_reg[0]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair2803" *) 
  LUT3 #(
    .INIT(8'h3B)) 
    \timerWTP[0][0][1][3][0]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][3][1] [0]),
        .I2(\cmd_bank_cas_reg[0]_0 ),
        .O(winWrite_reg_3[0]));
  (* SOFT_HLUTNM = "soft_lutpair2803" *) 
  LUT4 #(
    .INIT(16'hC3EB)) 
    \timerWTP[0][0][1][3][1]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][3][1] [0]),
        .I2(\timerWTP_reg[0][0][1][3][1] [1]),
        .I3(\cmd_bank_cas_reg[0]_0 ),
        .O(winWrite_reg_3[1]));
  LUT6 #(
    .INIT(64'h47CF77FFFFFFFFFF)) 
    \timerWTP[0][0][1][3][3]_i_3 
       (.I0(cmd_bank_cas[0]),
        .I1(Q[0]),
        .I2(\timerWTP_reg[0][0][0][3][1] ),
        .I3(cmd_bank_cas[1]),
        .I4(\timerWTP_reg[0][0][0][3][1]_0 ),
        .I5(winGroupC),
        .O(\cmd_bank_cas_reg[0]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \winPort[0]_i_1 
       (.I0(\winPort[0]_i_2_n_0 ),
        .O(\winPort[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2791" *) 
  LUT5 #(
    .INIT(32'hFF11FF1F)) 
    \winPort[0]_i_2 
       (.I0(\winPort[3]_i_7__0_n_0 ),
        .I1(last_reg_n_0),
        .I2(\winPort[3]_i_9_n_0 ),
        .I3(\winPort[3]_i_8__0_n_0 ),
        .I4(last10_reg_n_0),
        .O(\winPort[0]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \winPort[1]_i_1 
       (.I0(\winPort[1]_i_2__0_n_0 ),
        .O(\winPort[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2791" *) 
  LUT5 #(
    .INIT(32'hFFFF11F1)) 
    \winPort[1]_i_2__0 
       (.I0(\winPort[3]_i_7__0_n_0 ),
        .I1(last_reg_n_0),
        .I2(last10_reg_n_0),
        .I3(\winPort[3]_i_8__0_n_0 ),
        .I4(\winPort[3]_i_9_n_0 ),
        .O(\winPort[1]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \winPort[2]_i_1 
       (.I0(\winPort[3]_i_3__0_n_0 ),
        .I1(\winPort[3]_i_4__0_n_0 ),
        .O(\winPort[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h2A2A222AAA222A22)) 
    \winPort[3]_i_10 
       (.I0(\winPort[3]_i_5__0_0 ),
        .I1(Q[2]),
        .I2(wrReqR_reg),
        .I3(winRead),
        .I4(per_cas_block_req),
        .I5(winWrite),
        .O(rdReq[2]));
  (* SOFT_HLUTNM = "soft_lutpair2792" *) 
  LUT5 #(
    .INIT(32'hF400FFFF)) 
    \winPort[3]_i_11 
       (.I0(per_cas_block_req),
        .I1(winRead),
        .I2(wrReqR_reg),
        .I3(winWrite),
        .I4(wtr_oksr),
        .O(\winPort[3]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hF400FFFF)) 
    \winPort[3]_i_12 
       (.I0(per_cas_block_req),
        .I1(winRead),
        .I2(wrReqR_reg),
        .I3(winWrite),
        .I4(wtr_oklr),
        .O(\winPort[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h2A2A222AAA222A22)) 
    \winPort[3]_i_13 
       (.I0(\winPort[3]_i_6__0_0 ),
        .I1(Q[3]),
        .I2(wrReqR_reg),
        .I3(winRead),
        .I4(per_cas_block_req),
        .I5(winWrite),
        .O(rdReq[3]));
  LUT2 #(
    .INIT(4'h1)) 
    \winPort[3]_i_2 
       (.I0(\winPort[3]_i_3__0_n_0 ),
        .I1(\winPort[3]_i_4__0_n_0 ),
        .O(win3210));
  LUT6 #(
    .INIT(64'hE0E0E0EEC0CCC0CC)) 
    \winPort[3]_i_3__0 
       (.I0(winWrite_i_4_n_0),
        .I1(\winPort[3]_i_5__0_n_0 ),
        .I2(last32_reg_n_0),
        .I3(\winPort[3]_i_6__0_n_0 ),
        .I4(winWrite_i_3_n_0),
        .I5(winRead_i_2_n_0),
        .O(\winPort[3]_i_3__0_n_0 ));
  LUT4 #(
    .INIT(16'hBFAA)) 
    \winPort[3]_i_4__0 
       (.I0(\winPort[3]_i_7__0_n_0 ),
        .I1(\winPort[3]_i_8__0_n_0 ),
        .I2(\winPort[3]_i_9_n_0 ),
        .I3(last_reg_n_0),
        .O(\winPort[3]_i_4__0_n_0 ));
  LUT6 #(
    .INIT(64'h0004040044040444)) 
    \winPort[3]_i_5__0 
       (.I0(block_reads),
        .I1(rdReq[2]),
        .I2(\winPort[3]_i_11_n_0 ),
        .I3(cmd_group_cas[2]),
        .I4(\prevGr_reg[0] ),
        .I5(\winPort[3]_i_12_n_0 ),
        .O(\winPort[3]_i_5__0_n_0 ));
  LUT6 #(
    .INIT(64'h0004040044040444)) 
    \winPort[3]_i_6__0 
       (.I0(block_reads),
        .I1(rdReq[3]),
        .I2(\winPort[3]_i_11_n_0 ),
        .I3(cmd_group_cas[3]),
        .I4(\prevGr_reg[0] ),
        .I5(\winPort[3]_i_12_n_0 ),
        .O(\winPort[3]_i_6__0_n_0 ));
  LUT6 #(
    .INIT(64'h0030003300310033)) 
    \winPort[3]_i_7__0 
       (.I0(winWrite_i_4_n_0),
        .I1(\winPort[3]_i_5__0_n_0 ),
        .I2(winRead_i_4_n_0),
        .I3(\winPort[3]_i_6__0_n_0 ),
        .I4(winRead_i_3_n_0),
        .I5(winWrite_i_3_n_0),
        .O(\winPort[3]_i_7__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2790" *) 
  LUT5 #(
    .INIT(32'hAAA8AAAA)) 
    \winPort[3]_i_8__0 
       (.I0(winRead_i_3_n_0),
        .I1(\winPort[3]_i_5__0_n_0 ),
        .I2(winRead_i_4_n_0),
        .I3(\winPort[3]_i_6__0_n_0 ),
        .I4(winWrite_i_6_n_0),
        .O(\winPort[3]_i_8__0_n_0 ));
  LUT5 #(
    .INIT(32'h00FF00F7)) 
    \winPort[3]_i_9 
       (.I0(winWrite_i_7_n_0),
        .I1(winRead_i_3_n_0),
        .I2(\winPort[3]_i_6__0_n_0 ),
        .I3(winRead_i_4_n_0),
        .I4(\winPort[3]_i_5__0_n_0 ),
        .O(\winPort[3]_i_9_n_0 ));
  FDRE \winPort_reg[0] 
       (.C(\win_bank_cas_reg[1]_0 ),
        .CE(tranSentC),
        .D(\winPort[0]_i_1_n_0 ),
        .Q(Q[0]),
        .R(out));
  FDRE \winPort_reg[1] 
       (.C(\win_bank_cas_reg[1]_0 ),
        .CE(tranSentC),
        .D(\winPort[1]_i_1_n_0 ),
        .Q(Q[1]),
        .R(out));
  FDRE \winPort_reg[2] 
       (.C(\win_bank_cas_reg[1]_0 ),
        .CE(tranSentC),
        .D(\winPort[2]_i_1_n_0 ),
        .Q(Q[2]),
        .R(out));
  FDRE \winPort_reg[3] 
       (.C(\win_bank_cas_reg[1]_0 ),
        .CE(tranSentC),
        .D(win3210),
        .Q(Q[3]),
        .R(out));
  LUT1 #(
    .INIT(2'h1)) 
    winRead_i_1
       (.I0(winRead_i_2_n_0),
        .O(winRead_3));
  (* SOFT_HLUTNM = "soft_lutpair2790" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    winRead_i_2
       (.I0(winRead_i_3_n_0),
        .I1(\winPort[3]_i_6__0_n_0 ),
        .I2(winRead_i_4_n_0),
        .I3(\winPort[3]_i_5__0_n_0 ),
        .O(winRead_i_2_n_0));
  LUT6 #(
    .INIT(64'hFDFFFFFDFDDDDDFD)) 
    winRead_i_3
       (.I0(rdReq[0]),
        .I1(block_reads),
        .I2(\winPort[3]_i_12_n_0 ),
        .I3(\prevGr_reg[0] ),
        .I4(cmd_group_cas[0]),
        .I5(\winPort[3]_i_11_n_0 ),
        .O(winRead_i_3_n_0));
  LUT6 #(
    .INIT(64'h0004040044040444)) 
    winRead_i_4
       (.I0(block_reads),
        .I1(rdReq[1]),
        .I2(\winPort[3]_i_11_n_0 ),
        .I3(cmd_group_cas[1]),
        .I4(\prevGr_reg[0] ),
        .I5(\winPort[3]_i_12_n_0 ),
        .O(winRead_i_4_n_0));
  LUT6 #(
    .INIT(64'h2A2A222AAA222A22)) 
    winRead_i_5
       (.I0(rdReqR),
        .I1(Q[0]),
        .I2(wrReqR_reg),
        .I3(winRead),
        .I4(per_cas_block_req),
        .I5(winWrite),
        .O(rdReq[0]));
  LUT6 #(
    .INIT(64'h2A2A222AAA222A22)) 
    winRead_i_6
       (.I0(winRead_i_4_0),
        .I1(Q[1]),
        .I2(wrReqR_reg),
        .I3(winRead),
        .I4(per_cas_block_req),
        .I5(winWrite),
        .O(rdReq[1]));
  FDRE winRead_reg
       (.C(\win_bank_cas_reg[1]_0 ),
        .CE(tranSentC),
        .D(winRead_3),
        .Q(winRead),
        .R(out));
  LUT6 #(
    .INIT(64'hFFFFFFFFAFAEAAAE)) 
    winWrite_i_1
       (.I0(winWrite_i_2_n_0),
        .I1(winWrite_i_3_n_0),
        .I2(\winPort[3]_i_4__0_n_0 ),
        .I3(\winPort[3]_i_3__0_n_0 ),
        .I4(winWrite_i_4_n_0),
        .I5(winWrite_i_5_n_0),
        .O(winWrite_0));
  LUT6 #(
    .INIT(64'h0A080A080A080000)) 
    winWrite_i_2
       (.I0(winWrite_i_6_n_0),
        .I1(last10_reg_n_0),
        .I2(\winPort[3]_i_8__0_n_0 ),
        .I3(\winPort[3]_i_9_n_0 ),
        .I4(last_reg_n_0),
        .I5(\winPort[3]_i_7__0_n_0 ),
        .O(winWrite_i_2_n_0));
  LUT6 #(
    .INIT(64'h00000C0004000C00)) 
    winWrite_i_3
       (.I0(Q[3]),
        .I1(winWrite_reg_11),
        .I2(block_writes),
        .I3(rtw_okr),
        .I4(tranSentC),
        .I5(winRead),
        .O(winWrite_i_3_n_0));
  LUT6 #(
    .INIT(64'h00000C0004000C00)) 
    winWrite_i_4
       (.I0(Q[2]),
        .I1(winWrite_reg_10),
        .I2(block_writes),
        .I3(rtw_okr),
        .I4(tranSentC),
        .I5(winRead),
        .O(winWrite_i_4_n_0));
  LUT6 #(
    .INIT(64'h2022202220220000)) 
    winWrite_i_5
       (.I0(winWrite_i_7_n_0),
        .I1(\winPort[3]_i_9_n_0 ),
        .I2(\winPort[3]_i_8__0_n_0 ),
        .I3(last10_reg_n_0),
        .I4(last_reg_n_0),
        .I5(\winPort[3]_i_7__0_n_0 ),
        .O(winWrite_i_5_n_0));
  LUT6 #(
    .INIT(64'h00000C0004000C00)) 
    winWrite_i_6
       (.I0(Q[0]),
        .I1(wrReqR),
        .I2(block_writes),
        .I3(rtw_okr),
        .I4(tranSentC),
        .I5(winRead),
        .O(winWrite_i_6_n_0));
  LUT6 #(
    .INIT(64'h00000C0004000C00)) 
    winWrite_i_7
       (.I0(Q[1]),
        .I1(winWrite_i_5_0),
        .I2(block_writes),
        .I3(rtw_okr),
        .I4(tranSentC),
        .I5(winRead),
        .O(winWrite_i_7_n_0));
  FDRE winWrite_reg
       (.C(\win_bank_cas_reg[1]_0 ),
        .CE(tranSentC),
        .D(winWrite_0),
        .Q(winWrite),
        .R(out));
  LUT6 #(
    .INIT(64'hEEEEFEFFEEEEFEEE)) 
    \win_bank_cas[0]_i_1 
       (.I0(\win_bank_cas[0]_i_2_n_0 ),
        .I1(\win_bank_cas[0]_i_3_n_0 ),
        .I2(cmd_bank_cas[4]),
        .I3(\winPort[3]_i_3__0_n_0 ),
        .I4(\winPort[3]_i_4__0_n_0 ),
        .I5(cmd_bank_cas[6]),
        .O(win_bank_cas_1[0]));
  LUT6 #(
    .INIT(64'h0A080A080A080000)) 
    \win_bank_cas[0]_i_2 
       (.I0(cmd_bank_cas[0]),
        .I1(last10_reg_n_0),
        .I2(\winPort[3]_i_8__0_n_0 ),
        .I3(\winPort[3]_i_9_n_0 ),
        .I4(last_reg_n_0),
        .I5(\winPort[3]_i_7__0_n_0 ),
        .O(\win_bank_cas[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2022202220220000)) 
    \win_bank_cas[0]_i_3 
       (.I0(cmd_bank_cas[2]),
        .I1(\winPort[3]_i_9_n_0 ),
        .I2(\winPort[3]_i_8__0_n_0 ),
        .I3(last10_reg_n_0),
        .I4(last_reg_n_0),
        .I5(\winPort[3]_i_7__0_n_0 ),
        .O(\win_bank_cas[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEFAAEA)) 
    \win_bank_cas[1]_i_1 
       (.I0(\win_bank_cas[1]_i_2_n_0 ),
        .I1(cmd_bank_cas[5]),
        .I2(\winPort[3]_i_3__0_n_0 ),
        .I3(\winPort[3]_i_4__0_n_0 ),
        .I4(cmd_bank_cas[7]),
        .I5(\win_bank_cas[1]_i_3_n_0 ),
        .O(win_bank_cas_1[1]));
  LUT6 #(
    .INIT(64'h0A080A080A080000)) 
    \win_bank_cas[1]_i_2 
       (.I0(cmd_bank_cas[1]),
        .I1(last10_reg_n_0),
        .I2(\winPort[3]_i_8__0_n_0 ),
        .I3(\winPort[3]_i_9_n_0 ),
        .I4(last_reg_n_0),
        .I5(\winPort[3]_i_7__0_n_0 ),
        .O(\win_bank_cas[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2022202220220000)) 
    \win_bank_cas[1]_i_3 
       (.I0(cmd_bank_cas[3]),
        .I1(\winPort[3]_i_9_n_0 ),
        .I2(\winPort[3]_i_8__0_n_0 ),
        .I3(last10_reg_n_0),
        .I4(last_reg_n_0),
        .I5(\winPort[3]_i_7__0_n_0 ),
        .O(\win_bank_cas[1]_i_3_n_0 ));
  FDRE \win_bank_cas_reg[0] 
       (.C(\win_bank_cas_reg[1]_0 ),
        .CE(tranSentC),
        .D(win_bank_cas_1[0]),
        .Q(win_bank_cas[0]),
        .R(out));
  FDRE \win_bank_cas_reg[1] 
       (.C(\win_bank_cas_reg[1]_0 ),
        .CE(tranSentC),
        .D(win_bank_cas_1[1]),
        .Q(win_bank_cas[1]),
        .R(out));
  LUT6 #(
    .INIT(64'hEEEEFEFFEEEEFEEE)) 
    \win_group_cas[0]_i_1 
       (.I0(\win_group_cas[0]_i_2_n_0 ),
        .I1(\win_group_cas[0]_i_3_n_0 ),
        .I2(cmd_group_cas[2]),
        .I3(\winPort[3]_i_3__0_n_0 ),
        .I4(\winPort[3]_i_4__0_n_0 ),
        .I5(cmd_group_cas[3]),
        .O(win_group_cas_2));
  LUT6 #(
    .INIT(64'h0A080A080A080000)) 
    \win_group_cas[0]_i_2 
       (.I0(cmd_group_cas[0]),
        .I1(last10_reg_n_0),
        .I2(\winPort[3]_i_8__0_n_0 ),
        .I3(\winPort[3]_i_9_n_0 ),
        .I4(last_reg_n_0),
        .I5(\winPort[3]_i_7__0_n_0 ),
        .O(\win_group_cas[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2022202220220000)) 
    \win_group_cas[0]_i_3 
       (.I0(cmd_group_cas[1]),
        .I1(\winPort[3]_i_9_n_0 ),
        .I2(\winPort[3]_i_8__0_n_0 ),
        .I3(last10_reg_n_0),
        .I4(last_reg_n_0),
        .I5(\winPort[3]_i_7__0_n_0 ),
        .O(\win_group_cas[0]_i_3_n_0 ));
  FDRE \win_group_cas_reg[0] 
       (.C(\win_bank_cas_reg[1]_0 ),
        .CE(tranSentC),
        .D(win_group_cas_2),
        .Q(win_group_cas),
        .R(out));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][5]_i_1 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][5]_rep__1 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [0]),
        .O(wrCAS_reg[0]));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][5]_rep_i_1 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][5]_rep__1 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [0]),
        .O(wrCAS_reg_3));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][5]_rep_i_1__0 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][5]_rep__1 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [0]),
        .O(wrCAS_reg_4));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][5]_rep_i_1__1 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][5]_rep__1 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [0]),
        .O(wrCAS_reg_5));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][6]_i_1 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][6]_rep__1 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [1]),
        .O(wrCAS_reg[1]));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][6]_rep_i_1 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][6]_rep__1 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [1]),
        .O(wrCAS_reg_6));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][6]_rep_i_1__0 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][6]_rep__1 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [1]),
        .O(wrCAS_reg_7));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][6]_rep_i_1__1 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][6]_rep__1 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [1]),
        .O(wrCAS_reg_8));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][7]_i_1 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][7]_rep__1 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [2]),
        .O(wrCAS_reg[2]));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][7]_rep_i_1 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][7]_rep__1 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [2]),
        .O(wrCAS_reg_0));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][7]_rep_i_1__0 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][7]_rep__1 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [2]),
        .O(wrCAS_reg_1));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][7]_rep_i_1__1 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][7]_rep__1 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [2]),
        .O(wrCAS_reg_2));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][8]_i_1 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][8]_rep__1_0 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [3]),
        .O(wrCAS_reg[3]));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][8]_rep_i_1 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][8]_rep__1_0 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [3]),
        .O(wrCAS_reg_9));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][8]_rep_i_1__0 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][8]_rep__1_0 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [3]),
        .O(wrCAS_reg_10));
  LUT6 #(
    .INIT(64'hFDFDFCFD20203020)) 
    \wrQ[0][8]_rep_i_1__1 
       (.I0(winWrite_reg_0),
        .I1(oe_fabric),
        .I2(\wrQ_reg[0][8]_rep__1_0 ),
        .I3(calWrCAS),
        .I4(calDone),
        .I5(\wrQ_reg[0][8]_rep__1 [3]),
        .O(wrCAS_reg_11));
  LUT3 #(
    .INIT(8'h20)) 
    \wrQ[1][2]_i_1 
       (.I0(winWrite_reg_0),
        .I1(\wrQ_reg[1][2] ),
        .I2(oe_0_mux_cal),
        .O(calDone_reg_1[0]));
  LUT6 #(
    .INIT(64'hBA00BA00BA000000)) 
    \wrQ[1][5]_i_1 
       (.I0(winWrite_reg_0),
        .I1(calDone),
        .I2(calWrCAS),
        .I3(\wrQ_reg[0][5]_rep__1 ),
        .I4(\wrQ_reg[1][2] ),
        .I5(oe_0_mux_cal),
        .O(calDone_reg_1[1]));
  LUT6 #(
    .INIT(64'hBA00BA00BA000000)) 
    \wrQ[1][6]_i_1 
       (.I0(winWrite_reg_0),
        .I1(calDone),
        .I2(calWrCAS),
        .I3(\wrQ_reg[0][6]_rep__1 ),
        .I4(\wrQ_reg[1][2] ),
        .I5(oe_0_mux_cal),
        .O(calDone_reg_1[2]));
  LUT6 #(
    .INIT(64'hBA00BA00BA000000)) 
    \wrQ[1][7]_i_1 
       (.I0(winWrite_reg_0),
        .I1(calDone),
        .I2(calWrCAS),
        .I3(\wrQ_reg[0][7]_rep__1 ),
        .I4(\wrQ_reg[1][2] ),
        .I5(oe_0_mux_cal),
        .O(calDone_reg_1[3]));
  LUT6 #(
    .INIT(64'hBA00BA00BA000000)) 
    \wrQ[1][8]_i_1 
       (.I0(winWrite_reg_0),
        .I1(calDone),
        .I2(calWrCAS),
        .I3(\wrQ_reg[0][8]_rep__1_0 ),
        .I4(\wrQ_reg[1][2] ),
        .I5(oe_0_mux_cal),
        .O(calDone_reg_1[4]));
  (* SOFT_HLUTNM = "soft_lutpair2810" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wrQ[1][8]_i_2 
       (.I0(winWrite),
        .I1(tranSentC),
        .O(winWrite_reg_0));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_arb_mux_p" *) 
module ddr4_0_ddr4_v2_2_17_mc_arb_mux_p
   (calDone_reg,
    mc_BG,
    mc_BA,
    mc_ADR,
    winPort,
    \winPort_reg[1] ,
    Q,
    \timerWTP_reg[0][0][1][3][1]_0 ,
    \timerWTP_reg[0][0][0][2][1]_0 ,
    \timerWTP_reg[0][0][1][2][1]_0 ,
    \timerWTP_reg[0][0][0][1][1]_0 ,
    \timerWTP_reg[0][0][1][1][1]_0 ,
    \timerWTP_reg[0][0][0][0][1]_0 ,
    \timerWTP_reg[0][0][1][0][1]_0 ,
    out,
    \winPort_reg[3] ,
    \mcal_PAR_dly_reg[0][7] ,
    calDone,
    \mc_ADR7_reg[13] ,
    cmdGroupP,
    d_prevGroup,
    preIss,
    cmdBankP,
    D,
    winWrite,
    \timerWTP_reg[0][0][0][3][2]_0 ,
    \timerWTP_reg[0][0][1][3][1]_1 ,
    \timerWTP_reg[0][0][1][3][2]_0 ,
    \timerWTP_reg[0][0][0][2][1]_1 ,
    \timerWTP_reg[0][0][0][2][2]_0 ,
    \timerWTP_reg[0][0][1][2][1]_1 ,
    \timerWTP_reg[0][0][1][2][2]_0 ,
    \timerWTP_reg[0][0][0][1][1]_1 ,
    \timerWTP_reg[0][0][0][1][2]_0 ,
    \timerWTP_reg[0][0][1][1][1]_1 ,
    \timerWTP_reg[0][0][1][1][2]_0 ,
    \timerWTP_reg[0][0][0][0][1]_1 ,
    \timerWTP_reg[0][0][0][0][2]_0 ,
    \timerWTP_reg[0][0][1][0][1]_1 ,
    \timerWTP_reg[0][0][1][0][2]_0 ,
    SR,
    \timerRAS_reg[0][0][1][3][3]_0 ,
    \timerRAS_reg[0][0][0][3][0]_0 ,
    \timerRAS_reg[0][0][0][3][3]_0 ,
    \timerRAS_reg[0][0][1][2][0]_0 ,
    \timerRAS_reg[0][0][1][2][3]_0 ,
    \timerRAS_reg[0][0][0][2][0]_0 ,
    \timerRAS_reg[0][0][0][2][3]_0 ,
    \timerRAS_reg[0][0][1][1][0]_0 ,
    \timerRAS_reg[0][0][1][1][3]_0 ,
    \timerRAS_reg[0][0][0][1][0]_0 ,
    \timerRAS_reg[0][0][0][1][3]_0 ,
    \timerRAS_reg[0][0][1][0][0]_0 ,
    \timerRAS_reg[0][0][1][0][3]_0 ,
    \timerRAS_reg[0][0][0][0][0]_0 ,
    \timerRAS_reg[0][0][0][0][3]_0 ,
    \winPort_reg[0] ,
    \winPort_reg[0]_0 ,
    \winPort_reg[0]_1 ,
    preReqR);
  output calDone_reg;
  output [0:0]mc_BG;
  output [1:0]mc_BA;
  output [0:0]mc_ADR;
  output [3:0]winPort;
  output \winPort_reg[1] ;
  output [1:0]Q;
  output [1:0]\timerWTP_reg[0][0][1][3][1]_0 ;
  output [1:0]\timerWTP_reg[0][0][0][2][1]_0 ;
  output [1:0]\timerWTP_reg[0][0][1][2][1]_0 ;
  output [1:0]\timerWTP_reg[0][0][0][1][1]_0 ;
  output [1:0]\timerWTP_reg[0][0][1][1][1]_0 ;
  output [1:0]\timerWTP_reg[0][0][0][0][1]_0 ;
  output [1:0]\timerWTP_reg[0][0][1][0][1]_0 ;
  input out;
  input \winPort_reg[3] ;
  input \mcal_PAR_dly_reg[0][7] ;
  input calDone;
  input \mc_ADR7_reg[13] ;
  input [3:0]cmdGroupP;
  input d_prevGroup;
  input preIss;
  input [7:0]cmdBankP;
  input [1:0]D;
  input winWrite;
  input \timerWTP_reg[0][0][0][3][2]_0 ;
  input [1:0]\timerWTP_reg[0][0][1][3][1]_1 ;
  input \timerWTP_reg[0][0][1][3][2]_0 ;
  input [1:0]\timerWTP_reg[0][0][0][2][1]_1 ;
  input \timerWTP_reg[0][0][0][2][2]_0 ;
  input [1:0]\timerWTP_reg[0][0][1][2][1]_1 ;
  input \timerWTP_reg[0][0][1][2][2]_0 ;
  input [1:0]\timerWTP_reg[0][0][0][1][1]_1 ;
  input \timerWTP_reg[0][0][0][1][2]_0 ;
  input [1:0]\timerWTP_reg[0][0][1][1][1]_1 ;
  input \timerWTP_reg[0][0][1][1][2]_0 ;
  input [1:0]\timerWTP_reg[0][0][0][0][1]_1 ;
  input \timerWTP_reg[0][0][0][0][2]_0 ;
  input [1:0]\timerWTP_reg[0][0][1][0][1]_1 ;
  input \timerWTP_reg[0][0][1][0][2]_0 ;
  input [0:0]SR;
  input \timerRAS_reg[0][0][1][3][3]_0 ;
  input [0:0]\timerRAS_reg[0][0][0][3][0]_0 ;
  input \timerRAS_reg[0][0][0][3][3]_0 ;
  input [0:0]\timerRAS_reg[0][0][1][2][0]_0 ;
  input \timerRAS_reg[0][0][1][2][3]_0 ;
  input [0:0]\timerRAS_reg[0][0][0][2][0]_0 ;
  input \timerRAS_reg[0][0][0][2][3]_0 ;
  input [0:0]\timerRAS_reg[0][0][1][1][0]_0 ;
  input \timerRAS_reg[0][0][1][1][3]_0 ;
  input [0:0]\timerRAS_reg[0][0][0][1][0]_0 ;
  input \timerRAS_reg[0][0][0][1][3]_0 ;
  input [0:0]\timerRAS_reg[0][0][1][0][0]_0 ;
  input \timerRAS_reg[0][0][1][0][3]_0 ;
  input [0:0]\timerRAS_reg[0][0][0][0][0]_0 ;
  input \timerRAS_reg[0][0][0][0][3]_0 ;
  input \winPort_reg[0] ;
  input \winPort_reg[0]_0 ;
  input \winPort_reg[0]_1 ;
  input preReqR;

  wire [1:0]D;
  wire [1:0]Q;
  wire [0:0]SR;
  wire calDone;
  wire calDone_reg;
  wire [7:0]cmdBankP;
  wire [3:0]cmdGroupP;
  wire d_prevGroup;
  wire [0:0]mc_ADR;
  wire \mc_ADR7_reg[13] ;
  wire [1:0]mc_BA;
  wire [0:0]mc_BG;
  wire \mcal_PAR_dly_reg[0][7] ;
  wire out;
  wire [3:2]p_0_in__10;
  wire [3:2]p_0_in__14;
  wire [3:2]p_0_in__26;
  wire [3:2]p_0_in__30;
  wire [3:2]p_0_in__42;
  wire [3:2]p_0_in__46;
  wire [3:2]p_0_in__58;
  wire [3:2]p_0_in__62;
  wire p_227_out;
  wire p_231_out;
  wire p_235_out;
  wire p_239_out;
  wire p_243_out;
  wire p_247_out;
  wire p_251_out;
  wire p_255_out;
  wire preIss;
  wire preReqR;
  wire \pre_safe_reg_n_0_[0][0][0][0] ;
  wire \pre_safe_reg_n_0_[0][0][0][1] ;
  wire \pre_safe_reg_n_0_[0][0][0][2] ;
  wire \pre_safe_reg_n_0_[0][0][0][3] ;
  wire \pre_safe_reg_n_0_[0][0][1][0] ;
  wire \pre_safe_reg_n_0_[0][0][1][1] ;
  wire \pre_safe_reg_n_0_[0][0][1][2] ;
  wire \pre_safe_reg_n_0_[0][0][1][3] ;
  wire \timerRAS[0][0][0][0][0]_i_1_n_0 ;
  wire \timerRAS[0][0][0][0][1]_i_1_n_0 ;
  wire \timerRAS[0][0][0][0][2]_i_2_n_0 ;
  wire \timerRAS[0][0][0][0][2]_i_3_n_0 ;
  wire \timerRAS[0][0][0][0][3]_i_1_n_0 ;
  wire \timerRAS[0][0][0][1][0]_i_1_n_0 ;
  wire \timerRAS[0][0][0][1][1]_i_1_n_0 ;
  wire \timerRAS[0][0][0][1][2]_i_2_n_0 ;
  wire \timerRAS[0][0][0][1][2]_i_3_n_0 ;
  wire \timerRAS[0][0][0][1][3]_i_1_n_0 ;
  wire \timerRAS[0][0][0][2][0]_i_1_n_0 ;
  wire \timerRAS[0][0][0][2][1]_i_1_n_0 ;
  wire \timerRAS[0][0][0][2][2]_i_2_n_0 ;
  wire \timerRAS[0][0][0][2][2]_i_3_n_0 ;
  wire \timerRAS[0][0][0][2][3]_i_1_n_0 ;
  wire \timerRAS[0][0][0][3][0]_i_1_n_0 ;
  wire \timerRAS[0][0][0][3][1]_i_1_n_0 ;
  wire \timerRAS[0][0][0][3][2]_i_2_n_0 ;
  wire \timerRAS[0][0][0][3][2]_i_3_n_0 ;
  wire \timerRAS[0][0][0][3][3]_i_1_n_0 ;
  wire \timerRAS[0][0][1][0][0]_i_1_n_0 ;
  wire \timerRAS[0][0][1][0][1]_i_1_n_0 ;
  wire \timerRAS[0][0][1][0][2]_i_2_n_0 ;
  wire \timerRAS[0][0][1][0][2]_i_3_n_0 ;
  wire \timerRAS[0][0][1][0][3]_i_1_n_0 ;
  wire \timerRAS[0][0][1][1][0]_i_1_n_0 ;
  wire \timerRAS[0][0][1][1][1]_i_1_n_0 ;
  wire \timerRAS[0][0][1][1][2]_i_2_n_0 ;
  wire \timerRAS[0][0][1][1][2]_i_3_n_0 ;
  wire \timerRAS[0][0][1][1][3]_i_1_n_0 ;
  wire \timerRAS[0][0][1][2][0]_i_1_n_0 ;
  wire \timerRAS[0][0][1][2][1]_i_1_n_0 ;
  wire \timerRAS[0][0][1][2][2]_i_2_n_0 ;
  wire \timerRAS[0][0][1][2][2]_i_3_n_0 ;
  wire \timerRAS[0][0][1][2][3]_i_1_n_0 ;
  wire \timerRAS[0][0][1][3][0]_i_1_n_0 ;
  wire \timerRAS[0][0][1][3][1]_i_1_n_0 ;
  wire \timerRAS[0][0][1][3][2]_i_2_n_0 ;
  wire \timerRAS[0][0][1][3][2]_i_3_n_0 ;
  wire \timerRAS[0][0][1][3][3]_i_1_n_0 ;
  wire [0:0]\timerRAS_reg[0][0][0][0][0]_0 ;
  wire \timerRAS_reg[0][0][0][0][3]_0 ;
  wire [0:0]\timerRAS_reg[0][0][0][1][0]_0 ;
  wire \timerRAS_reg[0][0][0][1][3]_0 ;
  wire [0:0]\timerRAS_reg[0][0][0][2][0]_0 ;
  wire \timerRAS_reg[0][0][0][2][3]_0 ;
  wire [0:0]\timerRAS_reg[0][0][0][3][0]_0 ;
  wire \timerRAS_reg[0][0][0][3][3]_0 ;
  wire [0:0]\timerRAS_reg[0][0][1][0][0]_0 ;
  wire \timerRAS_reg[0][0][1][0][3]_0 ;
  wire [0:0]\timerRAS_reg[0][0][1][1][0]_0 ;
  wire \timerRAS_reg[0][0][1][1][3]_0 ;
  wire [0:0]\timerRAS_reg[0][0][1][2][0]_0 ;
  wire \timerRAS_reg[0][0][1][2][3]_0 ;
  wire \timerRAS_reg[0][0][1][3][3]_0 ;
  wire \timerRAS_reg_n_0_[0][0][0][0][0] ;
  wire \timerRAS_reg_n_0_[0][0][0][0][1] ;
  wire \timerRAS_reg_n_0_[0][0][0][0][2] ;
  wire \timerRAS_reg_n_0_[0][0][0][0][3] ;
  wire \timerRAS_reg_n_0_[0][0][0][1][0] ;
  wire \timerRAS_reg_n_0_[0][0][0][1][1] ;
  wire \timerRAS_reg_n_0_[0][0][0][1][2] ;
  wire \timerRAS_reg_n_0_[0][0][0][1][3] ;
  wire \timerRAS_reg_n_0_[0][0][0][2][0] ;
  wire \timerRAS_reg_n_0_[0][0][0][2][1] ;
  wire \timerRAS_reg_n_0_[0][0][0][2][2] ;
  wire \timerRAS_reg_n_0_[0][0][0][2][3] ;
  wire \timerRAS_reg_n_0_[0][0][0][3][0] ;
  wire \timerRAS_reg_n_0_[0][0][0][3][1] ;
  wire \timerRAS_reg_n_0_[0][0][0][3][2] ;
  wire \timerRAS_reg_n_0_[0][0][0][3][3] ;
  wire \timerRAS_reg_n_0_[0][0][1][0][0] ;
  wire \timerRAS_reg_n_0_[0][0][1][0][1] ;
  wire \timerRAS_reg_n_0_[0][0][1][0][2] ;
  wire \timerRAS_reg_n_0_[0][0][1][0][3] ;
  wire \timerRAS_reg_n_0_[0][0][1][1][0] ;
  wire \timerRAS_reg_n_0_[0][0][1][1][1] ;
  wire \timerRAS_reg_n_0_[0][0][1][1][2] ;
  wire \timerRAS_reg_n_0_[0][0][1][1][3] ;
  wire \timerRAS_reg_n_0_[0][0][1][2][0] ;
  wire \timerRAS_reg_n_0_[0][0][1][2][1] ;
  wire \timerRAS_reg_n_0_[0][0][1][2][2] ;
  wire \timerRAS_reg_n_0_[0][0][1][2][3] ;
  wire \timerRAS_reg_n_0_[0][0][1][3][0] ;
  wire \timerRAS_reg_n_0_[0][0][1][3][1] ;
  wire \timerRAS_reg_n_0_[0][0][1][3][2] ;
  wire \timerRAS_reg_n_0_[0][0][1][3][3] ;
  wire \timerWTP[0][0][0][0][3]_i_1_n_0 ;
  wire \timerWTP[0][0][0][1][3]_i_1_n_0 ;
  wire \timerWTP[0][0][0][2][3]_i_1_n_0 ;
  wire \timerWTP[0][0][0][3][3]_i_1_n_0 ;
  wire \timerWTP[0][0][1][0][3]_i_1_n_0 ;
  wire \timerWTP[0][0][1][1][3]_i_1_n_0 ;
  wire \timerWTP[0][0][1][2][3]_i_1_n_0 ;
  wire \timerWTP[0][0][1][3][3]_i_1_n_0 ;
  wire [1:0]\timerWTP_reg[0][0][0][0][1]_0 ;
  wire [1:0]\timerWTP_reg[0][0][0][0][1]_1 ;
  wire \timerWTP_reg[0][0][0][0][2]_0 ;
  wire [3:2]\timerWTP_reg[0][0][0][0]_234 ;
  wire [1:0]\timerWTP_reg[0][0][0][1][1]_0 ;
  wire [1:0]\timerWTP_reg[0][0][0][1][1]_1 ;
  wire \timerWTP_reg[0][0][0][1][2]_0 ;
  wire [3:2]\timerWTP_reg[0][0][0][1]_232 ;
  wire [1:0]\timerWTP_reg[0][0][0][2][1]_0 ;
  wire [1:0]\timerWTP_reg[0][0][0][2][1]_1 ;
  wire \timerWTP_reg[0][0][0][2][2]_0 ;
  wire [3:2]\timerWTP_reg[0][0][0][2]_230 ;
  wire \timerWTP_reg[0][0][0][3][2]_0 ;
  wire [3:2]\timerWTP_reg[0][0][0][3]_228 ;
  wire [1:0]\timerWTP_reg[0][0][1][0][1]_0 ;
  wire [1:0]\timerWTP_reg[0][0][1][0][1]_1 ;
  wire \timerWTP_reg[0][0][1][0][2]_0 ;
  wire [3:2]\timerWTP_reg[0][0][1][0]_233 ;
  wire [1:0]\timerWTP_reg[0][0][1][1][1]_0 ;
  wire [1:0]\timerWTP_reg[0][0][1][1][1]_1 ;
  wire \timerWTP_reg[0][0][1][1][2]_0 ;
  wire [3:2]\timerWTP_reg[0][0][1][1]_231 ;
  wire [1:0]\timerWTP_reg[0][0][1][2][1]_0 ;
  wire [1:0]\timerWTP_reg[0][0][1][2][1]_1 ;
  wire \timerWTP_reg[0][0][1][2][2]_0 ;
  wire [3:2]\timerWTP_reg[0][0][1][2]_229 ;
  wire [1:0]\timerWTP_reg[0][0][1][3][1]_0 ;
  wire [1:0]\timerWTP_reg[0][0][1][3][1]_1 ;
  wire \timerWTP_reg[0][0][1][3][2]_0 ;
  wire [3:2]\timerWTP_reg[0][0][1][3]_227 ;
  wire [3:0]winPort;
  wire \winPort_reg[0] ;
  wire \winPort_reg[0]_0 ;
  wire \winPort_reg[0]_1 ;
  wire \winPort_reg[1] ;
  wire \winPort_reg[3] ;
  wire winWrite;

  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \pre_safe[0][0][0][0]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][0][3] ),
        .I1(\timerWTP_reg[0][0][0][0][1]_0 [1]),
        .I2(\timerRAS_reg_n_0_[0][0][0][0][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][0][0][2] ),
        .I4(\timerWTP_reg[0][0][0][0]_234 [3]),
        .I5(\timerWTP_reg[0][0][0][0]_234 [2]),
        .O(p_255_out));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \pre_safe[0][0][0][1]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][1][3] ),
        .I1(\timerWTP_reg[0][0][0][1][1]_0 [1]),
        .I2(\timerRAS_reg_n_0_[0][0][0][1][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][0][1][2] ),
        .I4(\timerWTP_reg[0][0][0][1]_232 [3]),
        .I5(\timerWTP_reg[0][0][0][1]_232 [2]),
        .O(p_251_out));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \pre_safe[0][0][0][2]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][2][3] ),
        .I1(\timerWTP_reg[0][0][0][2][1]_0 [1]),
        .I2(\timerRAS_reg_n_0_[0][0][0][2][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][0][2][2] ),
        .I4(\timerWTP_reg[0][0][0][2]_230 [3]),
        .I5(\timerWTP_reg[0][0][0][2]_230 [2]),
        .O(p_247_out));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \pre_safe[0][0][0][3]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][3][3] ),
        .I1(Q[1]),
        .I2(\timerRAS_reg_n_0_[0][0][0][3][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][0][3][2] ),
        .I4(\timerWTP_reg[0][0][0][3]_228 [3]),
        .I5(\timerWTP_reg[0][0][0][3]_228 [2]),
        .O(p_243_out));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \pre_safe[0][0][1][0]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][0][3] ),
        .I1(\timerWTP_reg[0][0][1][0][1]_0 [1]),
        .I2(\timerRAS_reg_n_0_[0][0][1][0][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][1][0][2] ),
        .I4(\timerWTP_reg[0][0][1][0]_233 [3]),
        .I5(\timerWTP_reg[0][0][1][0]_233 [2]),
        .O(p_239_out));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \pre_safe[0][0][1][1]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][1][3] ),
        .I1(\timerWTP_reg[0][0][1][1][1]_0 [1]),
        .I2(\timerRAS_reg_n_0_[0][0][1][1][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][1][1][2] ),
        .I4(\timerWTP_reg[0][0][1][1]_231 [3]),
        .I5(\timerWTP_reg[0][0][1][1]_231 [2]),
        .O(p_235_out));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \pre_safe[0][0][1][2]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][2][3] ),
        .I1(\timerWTP_reg[0][0][1][2][1]_0 [1]),
        .I2(\timerRAS_reg_n_0_[0][0][1][2][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][1][2][2] ),
        .I4(\timerWTP_reg[0][0][1][2]_229 [3]),
        .I5(\timerWTP_reg[0][0][1][2]_229 [2]),
        .O(p_231_out));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \pre_safe[0][0][1][3]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][3][3] ),
        .I1(\timerWTP_reg[0][0][1][3][1]_0 [1]),
        .I2(\timerRAS_reg_n_0_[0][0][1][3][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][1][3][2] ),
        .I4(\timerWTP_reg[0][0][1][3]_227 [3]),
        .I5(\timerWTP_reg[0][0][1][3]_227 [2]),
        .O(p_227_out));
  FDRE \pre_safe_reg[0][0][0][0] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(p_255_out),
        .Q(\pre_safe_reg_n_0_[0][0][0][0] ),
        .R(out));
  FDRE \pre_safe_reg[0][0][0][1] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(p_251_out),
        .Q(\pre_safe_reg_n_0_[0][0][0][1] ),
        .R(out));
  FDRE \pre_safe_reg[0][0][0][2] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(p_247_out),
        .Q(\pre_safe_reg_n_0_[0][0][0][2] ),
        .R(out));
  FDRE \pre_safe_reg[0][0][0][3] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(p_243_out),
        .Q(\pre_safe_reg_n_0_[0][0][0][3] ),
        .R(out));
  FDRE \pre_safe_reg[0][0][1][0] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(p_239_out),
        .Q(\pre_safe_reg_n_0_[0][0][1][0] ),
        .R(out));
  FDRE \pre_safe_reg[0][0][1][1] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(p_235_out),
        .Q(\pre_safe_reg_n_0_[0][0][1][1] ),
        .R(out));
  FDRE \pre_safe_reg[0][0][1][2] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(p_231_out),
        .Q(\pre_safe_reg_n_0_[0][0][1][2] ),
        .R(out));
  FDRE \pre_safe_reg[0][0][1][3] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(p_227_out),
        .Q(\pre_safe_reg_n_0_[0][0][1][3] ),
        .R(out));
  LUT1 #(
    .INIT(2'h1)) 
    \timerRAS[0][0][0][0][0]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][0][0] ),
        .O(\timerRAS[0][0][0][0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2822" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \timerRAS[0][0][0][0][1]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][0][0] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][0][1] ),
        .O(\timerRAS[0][0][0][0][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \timerRAS[0][0][0][0][2]_i_2 
       (.I0(\timerRAS_reg_n_0_[0][0][0][0][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][0][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][0][0][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][0][0][3] ),
        .O(\timerRAS[0][0][0][0][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2822" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \timerRAS[0][0][0][0][2]_i_3 
       (.I0(\timerRAS_reg_n_0_[0][0][0][0][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][0][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][0][0][1] ),
        .O(\timerRAS[0][0][0][0][2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFAAA8)) 
    \timerRAS[0][0][0][0][3]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][0][3] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][0][1] ),
        .I2(\timerRAS_reg_n_0_[0][0][0][0][0] ),
        .I3(\timerRAS_reg_n_0_[0][0][0][0][2] ),
        .I4(\timerRAS_reg[0][0][0][0][3]_0 ),
        .O(\timerRAS[0][0][0][0][3]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \timerRAS[0][0][0][1][0]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][1][0] ),
        .O(\timerRAS[0][0][0][1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2820" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \timerRAS[0][0][0][1][1]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][1][0] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][1][1] ),
        .O(\timerRAS[0][0][0][1][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \timerRAS[0][0][0][1][2]_i_2 
       (.I0(\timerRAS_reg_n_0_[0][0][0][1][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][1][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][0][1][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][0][1][3] ),
        .O(\timerRAS[0][0][0][1][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2820" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \timerRAS[0][0][0][1][2]_i_3 
       (.I0(\timerRAS_reg_n_0_[0][0][0][1][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][1][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][0][1][1] ),
        .O(\timerRAS[0][0][0][1][2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFAAA8)) 
    \timerRAS[0][0][0][1][3]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][1][3] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][1][1] ),
        .I2(\timerRAS_reg_n_0_[0][0][0][1][0] ),
        .I3(\timerRAS_reg_n_0_[0][0][0][1][2] ),
        .I4(\timerRAS_reg[0][0][0][1][3]_0 ),
        .O(\timerRAS[0][0][0][1][3]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \timerRAS[0][0][0][2][0]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][2][0] ),
        .O(\timerRAS[0][0][0][2][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2818" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \timerRAS[0][0][0][2][1]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][2][0] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][2][1] ),
        .O(\timerRAS[0][0][0][2][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \timerRAS[0][0][0][2][2]_i_2 
       (.I0(\timerRAS_reg_n_0_[0][0][0][2][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][2][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][0][2][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][0][2][3] ),
        .O(\timerRAS[0][0][0][2][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2818" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \timerRAS[0][0][0][2][2]_i_3 
       (.I0(\timerRAS_reg_n_0_[0][0][0][2][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][2][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][0][2][1] ),
        .O(\timerRAS[0][0][0][2][2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFAAA8)) 
    \timerRAS[0][0][0][2][3]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][2][3] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][2][1] ),
        .I2(\timerRAS_reg_n_0_[0][0][0][2][0] ),
        .I3(\timerRAS_reg_n_0_[0][0][0][2][2] ),
        .I4(\timerRAS_reg[0][0][0][2][3]_0 ),
        .O(\timerRAS[0][0][0][2][3]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \timerRAS[0][0][0][3][0]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][3][0] ),
        .O(\timerRAS[0][0][0][3][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2816" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \timerRAS[0][0][0][3][1]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][3][0] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][3][1] ),
        .O(\timerRAS[0][0][0][3][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \timerRAS[0][0][0][3][2]_i_2 
       (.I0(\timerRAS_reg_n_0_[0][0][0][3][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][3][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][0][3][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][0][3][3] ),
        .O(\timerRAS[0][0][0][3][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2816" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \timerRAS[0][0][0][3][2]_i_3 
       (.I0(\timerRAS_reg_n_0_[0][0][0][3][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][3][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][0][3][1] ),
        .O(\timerRAS[0][0][0][3][2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFAAA8)) 
    \timerRAS[0][0][0][3][3]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][0][3][3] ),
        .I1(\timerRAS_reg_n_0_[0][0][0][3][1] ),
        .I2(\timerRAS_reg_n_0_[0][0][0][3][0] ),
        .I3(\timerRAS_reg_n_0_[0][0][0][3][2] ),
        .I4(\timerRAS_reg[0][0][0][3][3]_0 ),
        .O(\timerRAS[0][0][0][3][3]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \timerRAS[0][0][1][0][0]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][0][0] ),
        .O(\timerRAS[0][0][1][0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2821" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \timerRAS[0][0][1][0][1]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][0][0] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][0][1] ),
        .O(\timerRAS[0][0][1][0][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \timerRAS[0][0][1][0][2]_i_2 
       (.I0(\timerRAS_reg_n_0_[0][0][1][0][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][0][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][1][0][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][1][0][3] ),
        .O(\timerRAS[0][0][1][0][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2821" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \timerRAS[0][0][1][0][2]_i_3 
       (.I0(\timerRAS_reg_n_0_[0][0][1][0][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][0][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][1][0][1] ),
        .O(\timerRAS[0][0][1][0][2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFAAA8)) 
    \timerRAS[0][0][1][0][3]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][0][3] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][0][1] ),
        .I2(\timerRAS_reg_n_0_[0][0][1][0][0] ),
        .I3(\timerRAS_reg_n_0_[0][0][1][0][2] ),
        .I4(\timerRAS_reg[0][0][1][0][3]_0 ),
        .O(\timerRAS[0][0][1][0][3]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \timerRAS[0][0][1][1][0]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][1][0] ),
        .O(\timerRAS[0][0][1][1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2819" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \timerRAS[0][0][1][1][1]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][1][0] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][1][1] ),
        .O(\timerRAS[0][0][1][1][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \timerRAS[0][0][1][1][2]_i_2 
       (.I0(\timerRAS_reg_n_0_[0][0][1][1][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][1][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][1][1][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][1][1][3] ),
        .O(\timerRAS[0][0][1][1][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2819" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \timerRAS[0][0][1][1][2]_i_3 
       (.I0(\timerRAS_reg_n_0_[0][0][1][1][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][1][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][1][1][1] ),
        .O(\timerRAS[0][0][1][1][2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFAAA8)) 
    \timerRAS[0][0][1][1][3]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][1][3] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][1][1] ),
        .I2(\timerRAS_reg_n_0_[0][0][1][1][0] ),
        .I3(\timerRAS_reg_n_0_[0][0][1][1][2] ),
        .I4(\timerRAS_reg[0][0][1][1][3]_0 ),
        .O(\timerRAS[0][0][1][1][3]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \timerRAS[0][0][1][2][0]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][2][0] ),
        .O(\timerRAS[0][0][1][2][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2817" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \timerRAS[0][0][1][2][1]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][2][0] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][2][1] ),
        .O(\timerRAS[0][0][1][2][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \timerRAS[0][0][1][2][2]_i_2 
       (.I0(\timerRAS_reg_n_0_[0][0][1][2][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][2][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][1][2][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][1][2][3] ),
        .O(\timerRAS[0][0][1][2][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2817" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \timerRAS[0][0][1][2][2]_i_3 
       (.I0(\timerRAS_reg_n_0_[0][0][1][2][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][2][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][1][2][1] ),
        .O(\timerRAS[0][0][1][2][2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFAAA8)) 
    \timerRAS[0][0][1][2][3]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][2][3] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][2][1] ),
        .I2(\timerRAS_reg_n_0_[0][0][1][2][0] ),
        .I3(\timerRAS_reg_n_0_[0][0][1][2][2] ),
        .I4(\timerRAS_reg[0][0][1][2][3]_0 ),
        .O(\timerRAS[0][0][1][2][3]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \timerRAS[0][0][1][3][0]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][3][0] ),
        .O(\timerRAS[0][0][1][3][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2815" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \timerRAS[0][0][1][3][1]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][3][0] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][3][1] ),
        .O(\timerRAS[0][0][1][3][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \timerRAS[0][0][1][3][2]_i_2 
       (.I0(\timerRAS_reg_n_0_[0][0][1][3][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][3][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][1][3][1] ),
        .I3(\timerRAS_reg_n_0_[0][0][1][3][3] ),
        .O(\timerRAS[0][0][1][3][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2815" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \timerRAS[0][0][1][3][2]_i_3 
       (.I0(\timerRAS_reg_n_0_[0][0][1][3][2] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][3][0] ),
        .I2(\timerRAS_reg_n_0_[0][0][1][3][1] ),
        .O(\timerRAS[0][0][1][3][2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFAAA8)) 
    \timerRAS[0][0][1][3][3]_i_1 
       (.I0(\timerRAS_reg_n_0_[0][0][1][3][3] ),
        .I1(\timerRAS_reg_n_0_[0][0][1][3][1] ),
        .I2(\timerRAS_reg_n_0_[0][0][1][3][0] ),
        .I3(\timerRAS_reg_n_0_[0][0][1][3][2] ),
        .I4(\timerRAS_reg[0][0][1][3][3]_0 ),
        .O(\timerRAS[0][0][1][3][3]_i_1_n_0 ));
  FDRE \timerRAS_reg[0][0][0][0][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][0][0][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][0][0][0]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][0][0] ),
        .R(\timerRAS_reg[0][0][0][0][0]_0 ));
  FDRE \timerRAS_reg[0][0][0][0][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][0][0][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][0][0][1]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][0][1] ),
        .R(\timerRAS_reg[0][0][0][0][0]_0 ));
  FDRE \timerRAS_reg[0][0][0][0][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][0][0][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][0][0][2]_i_3_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][0][2] ),
        .R(\timerRAS_reg[0][0][0][0][0]_0 ));
  FDRE \timerRAS_reg[0][0][0][0][3] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(\timerRAS[0][0][0][0][3]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][0][3] ),
        .R(out));
  FDRE \timerRAS_reg[0][0][0][1][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][0][1][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][0][1][0]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][1][0] ),
        .R(\timerRAS_reg[0][0][0][1][0]_0 ));
  FDRE \timerRAS_reg[0][0][0][1][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][0][1][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][0][1][1]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][1][1] ),
        .R(\timerRAS_reg[0][0][0][1][0]_0 ));
  FDRE \timerRAS_reg[0][0][0][1][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][0][1][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][0][1][2]_i_3_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][1][2] ),
        .R(\timerRAS_reg[0][0][0][1][0]_0 ));
  FDRE \timerRAS_reg[0][0][0][1][3] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(\timerRAS[0][0][0][1][3]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][1][3] ),
        .R(out));
  FDRE \timerRAS_reg[0][0][0][2][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][0][2][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][0][2][0]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][2][0] ),
        .R(\timerRAS_reg[0][0][0][2][0]_0 ));
  FDRE \timerRAS_reg[0][0][0][2][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][0][2][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][0][2][1]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][2][1] ),
        .R(\timerRAS_reg[0][0][0][2][0]_0 ));
  FDRE \timerRAS_reg[0][0][0][2][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][0][2][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][0][2][2]_i_3_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][2][2] ),
        .R(\timerRAS_reg[0][0][0][2][0]_0 ));
  FDRE \timerRAS_reg[0][0][0][2][3] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(\timerRAS[0][0][0][2][3]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][2][3] ),
        .R(out));
  FDRE \timerRAS_reg[0][0][0][3][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][0][3][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][0][3][0]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][3][0] ),
        .R(\timerRAS_reg[0][0][0][3][0]_0 ));
  FDRE \timerRAS_reg[0][0][0][3][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][0][3][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][0][3][1]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][3][1] ),
        .R(\timerRAS_reg[0][0][0][3][0]_0 ));
  FDRE \timerRAS_reg[0][0][0][3][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][0][3][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][0][3][2]_i_3_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][3][2] ),
        .R(\timerRAS_reg[0][0][0][3][0]_0 ));
  FDRE \timerRAS_reg[0][0][0][3][3] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(\timerRAS[0][0][0][3][3]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][0][3][3] ),
        .R(out));
  FDRE \timerRAS_reg[0][0][1][0][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][1][0][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][1][0][0]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][0][0] ),
        .R(\timerRAS_reg[0][0][1][0][0]_0 ));
  FDRE \timerRAS_reg[0][0][1][0][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][1][0][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][1][0][1]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][0][1] ),
        .R(\timerRAS_reg[0][0][1][0][0]_0 ));
  FDRE \timerRAS_reg[0][0][1][0][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][1][0][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][1][0][2]_i_3_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][0][2] ),
        .R(\timerRAS_reg[0][0][1][0][0]_0 ));
  FDRE \timerRAS_reg[0][0][1][0][3] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(\timerRAS[0][0][1][0][3]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][0][3] ),
        .R(out));
  FDRE \timerRAS_reg[0][0][1][1][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][1][1][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][1][1][0]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][1][0] ),
        .R(\timerRAS_reg[0][0][1][1][0]_0 ));
  FDRE \timerRAS_reg[0][0][1][1][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][1][1][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][1][1][1]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][1][1] ),
        .R(\timerRAS_reg[0][0][1][1][0]_0 ));
  FDRE \timerRAS_reg[0][0][1][1][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][1][1][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][1][1][2]_i_3_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][1][2] ),
        .R(\timerRAS_reg[0][0][1][1][0]_0 ));
  FDRE \timerRAS_reg[0][0][1][1][3] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(\timerRAS[0][0][1][1][3]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][1][3] ),
        .R(out));
  FDRE \timerRAS_reg[0][0][1][2][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][1][2][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][1][2][0]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][2][0] ),
        .R(\timerRAS_reg[0][0][1][2][0]_0 ));
  FDRE \timerRAS_reg[0][0][1][2][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][1][2][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][1][2][1]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][2][1] ),
        .R(\timerRAS_reg[0][0][1][2][0]_0 ));
  FDRE \timerRAS_reg[0][0][1][2][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][1][2][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][1][2][2]_i_3_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][2][2] ),
        .R(\timerRAS_reg[0][0][1][2][0]_0 ));
  FDRE \timerRAS_reg[0][0][1][2][3] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(\timerRAS[0][0][1][2][3]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][2][3] ),
        .R(out));
  FDRE \timerRAS_reg[0][0][1][3][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][1][3][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][1][3][0]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][3][0] ),
        .R(SR));
  FDRE \timerRAS_reg[0][0][1][3][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][1][3][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][1][3][1]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][3][1] ),
        .R(SR));
  FDRE \timerRAS_reg[0][0][1][3][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerRAS[0][0][1][3][2]_i_2_n_0 ),
        .D(\timerRAS[0][0][1][3][2]_i_3_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][3][2] ),
        .R(SR));
  FDRE \timerRAS_reg[0][0][1][3][3] 
       (.C(\winPort_reg[3] ),
        .CE(1'b1),
        .D(\timerRAS[0][0][1][3][3]_i_1_n_0 ),
        .Q(\timerRAS_reg_n_0_[0][0][1][3][3] ),
        .R(out));
  LUT5 #(
    .INIT(32'hCCC3EEEB)) 
    \timerWTP[0][0][0][0][2]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][0]_234 [2]),
        .I2(\timerWTP_reg[0][0][0][0][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][0][0][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][0][0][2]_0 ),
        .O(p_0_in__62[2]));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFFFFFE)) 
    \timerWTP[0][0][0][0][3]_i_1 
       (.I0(\timerWTP_reg[0][0][0][0]_234 [3]),
        .I1(\timerWTP_reg[0][0][0][0][1]_0 [1]),
        .I2(\timerWTP_reg[0][0][0][0][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][0][0]_234 [2]),
        .I4(winWrite),
        .I5(\timerWTP_reg[0][0][0][0][2]_0 ),
        .O(\timerWTP[0][0][0][0][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0D0D00D)) 
    \timerWTP[0][0][0][0][3]_i_2 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][0][2]_0 ),
        .I2(\timerWTP_reg[0][0][0][0]_234 [3]),
        .I3(\timerWTP_reg[0][0][0][0][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][0][0][1]_0 [0]),
        .I5(\timerWTP_reg[0][0][0][0]_234 [2]),
        .O(p_0_in__62[3]));
  LUT5 #(
    .INIT(32'hCCC3EEEB)) 
    \timerWTP[0][0][0][1][2]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][1]_232 [2]),
        .I2(\timerWTP_reg[0][0][0][1][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][0][1][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][0][1][2]_0 ),
        .O(p_0_in__46[2]));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFFFFFE)) 
    \timerWTP[0][0][0][1][3]_i_1 
       (.I0(\timerWTP_reg[0][0][0][1]_232 [3]),
        .I1(\timerWTP_reg[0][0][0][1][1]_0 [1]),
        .I2(\timerWTP_reg[0][0][0][1][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][0][1]_232 [2]),
        .I4(winWrite),
        .I5(\timerWTP_reg[0][0][0][1][2]_0 ),
        .O(\timerWTP[0][0][0][1][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0D0D00D)) 
    \timerWTP[0][0][0][1][3]_i_2 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][1][2]_0 ),
        .I2(\timerWTP_reg[0][0][0][1]_232 [3]),
        .I3(\timerWTP_reg[0][0][0][1][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][0][1][1]_0 [0]),
        .I5(\timerWTP_reg[0][0][0][1]_232 [2]),
        .O(p_0_in__46[3]));
  LUT5 #(
    .INIT(32'hCCC3EEEB)) 
    \timerWTP[0][0][0][2][2]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][2]_230 [2]),
        .I2(\timerWTP_reg[0][0][0][2][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][0][2][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][0][2][2]_0 ),
        .O(p_0_in__30[2]));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFFFFFE)) 
    \timerWTP[0][0][0][2][3]_i_1 
       (.I0(\timerWTP_reg[0][0][0][2]_230 [3]),
        .I1(\timerWTP_reg[0][0][0][2][1]_0 [1]),
        .I2(\timerWTP_reg[0][0][0][2][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][0][2]_230 [2]),
        .I4(winWrite),
        .I5(\timerWTP_reg[0][0][0][2][2]_0 ),
        .O(\timerWTP[0][0][0][2][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0D0D00D)) 
    \timerWTP[0][0][0][2][3]_i_2 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][2][2]_0 ),
        .I2(\timerWTP_reg[0][0][0][2]_230 [3]),
        .I3(\timerWTP_reg[0][0][0][2][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][0][2][1]_0 [0]),
        .I5(\timerWTP_reg[0][0][0][2]_230 [2]),
        .O(p_0_in__30[3]));
  LUT5 #(
    .INIT(32'hCCC3EEEB)) 
    \timerWTP[0][0][0][3][2]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][3]_228 [2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(\timerWTP_reg[0][0][0][3][2]_0 ),
        .O(p_0_in__14[2]));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFFFFFE)) 
    \timerWTP[0][0][0][3][3]_i_1 
       (.I0(\timerWTP_reg[0][0][0][3]_228 [3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\timerWTP_reg[0][0][0][3]_228 [2]),
        .I4(winWrite),
        .I5(\timerWTP_reg[0][0][0][3][2]_0 ),
        .O(\timerWTP[0][0][0][3][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0D0D00D)) 
    \timerWTP[0][0][0][3][3]_i_2 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][0][3][2]_0 ),
        .I2(\timerWTP_reg[0][0][0][3]_228 [3]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\timerWTP_reg[0][0][0][3]_228 [2]),
        .O(p_0_in__14[3]));
  LUT5 #(
    .INIT(32'hCCC3EEEB)) 
    \timerWTP[0][0][1][0][2]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][0]_233 [2]),
        .I2(\timerWTP_reg[0][0][1][0][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][1][0][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][1][0][2]_0 ),
        .O(p_0_in__58[2]));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFFFFFE)) 
    \timerWTP[0][0][1][0][3]_i_1 
       (.I0(\timerWTP_reg[0][0][1][0]_233 [3]),
        .I1(\timerWTP_reg[0][0][1][0][1]_0 [1]),
        .I2(\timerWTP_reg[0][0][1][0][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][1][0]_233 [2]),
        .I4(winWrite),
        .I5(\timerWTP_reg[0][0][1][0][2]_0 ),
        .O(\timerWTP[0][0][1][0][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0D0D00D)) 
    \timerWTP[0][0][1][0][3]_i_2 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][0][2]_0 ),
        .I2(\timerWTP_reg[0][0][1][0]_233 [3]),
        .I3(\timerWTP_reg[0][0][1][0][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][1][0][1]_0 [0]),
        .I5(\timerWTP_reg[0][0][1][0]_233 [2]),
        .O(p_0_in__58[3]));
  LUT5 #(
    .INIT(32'hCCC3EEEB)) 
    \timerWTP[0][0][1][1][2]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][1]_231 [2]),
        .I2(\timerWTP_reg[0][0][1][1][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][1][1][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][1][1][2]_0 ),
        .O(p_0_in__42[2]));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFFFFFE)) 
    \timerWTP[0][0][1][1][3]_i_1 
       (.I0(\timerWTP_reg[0][0][1][1]_231 [3]),
        .I1(\timerWTP_reg[0][0][1][1][1]_0 [1]),
        .I2(\timerWTP_reg[0][0][1][1][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][1][1]_231 [2]),
        .I4(winWrite),
        .I5(\timerWTP_reg[0][0][1][1][2]_0 ),
        .O(\timerWTP[0][0][1][1][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0D0D00D)) 
    \timerWTP[0][0][1][1][3]_i_2 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][1][2]_0 ),
        .I2(\timerWTP_reg[0][0][1][1]_231 [3]),
        .I3(\timerWTP_reg[0][0][1][1][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][1][1][1]_0 [0]),
        .I5(\timerWTP_reg[0][0][1][1]_231 [2]),
        .O(p_0_in__42[3]));
  LUT5 #(
    .INIT(32'hCCC3EEEB)) 
    \timerWTP[0][0][1][2][2]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][2]_229 [2]),
        .I2(\timerWTP_reg[0][0][1][2][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][1][2][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][1][2][2]_0 ),
        .O(p_0_in__26[2]));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFFFFFE)) 
    \timerWTP[0][0][1][2][3]_i_1 
       (.I0(\timerWTP_reg[0][0][1][2]_229 [3]),
        .I1(\timerWTP_reg[0][0][1][2][1]_0 [1]),
        .I2(\timerWTP_reg[0][0][1][2][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][1][2]_229 [2]),
        .I4(winWrite),
        .I5(\timerWTP_reg[0][0][1][2][2]_0 ),
        .O(\timerWTP[0][0][1][2][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0D0D00D)) 
    \timerWTP[0][0][1][2][3]_i_2 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][2][2]_0 ),
        .I2(\timerWTP_reg[0][0][1][2]_229 [3]),
        .I3(\timerWTP_reg[0][0][1][2][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][1][2][1]_0 [0]),
        .I5(\timerWTP_reg[0][0][1][2]_229 [2]),
        .O(p_0_in__26[3]));
  LUT5 #(
    .INIT(32'hCCC3EEEB)) 
    \timerWTP[0][0][1][3][2]_i_1 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][3]_227 [2]),
        .I2(\timerWTP_reg[0][0][1][3][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][1][3][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][1][3][2]_0 ),
        .O(p_0_in__10[2]));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFFFFFE)) 
    \timerWTP[0][0][1][3][3]_i_1 
       (.I0(\timerWTP_reg[0][0][1][3]_227 [3]),
        .I1(\timerWTP_reg[0][0][1][3][1]_0 [1]),
        .I2(\timerWTP_reg[0][0][1][3][1]_0 [0]),
        .I3(\timerWTP_reg[0][0][1][3]_227 [2]),
        .I4(winWrite),
        .I5(\timerWTP_reg[0][0][1][3][2]_0 ),
        .O(\timerWTP[0][0][1][3][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0D0D00D)) 
    \timerWTP[0][0][1][3][3]_i_2 
       (.I0(winWrite),
        .I1(\timerWTP_reg[0][0][1][3][2]_0 ),
        .I2(\timerWTP_reg[0][0][1][3]_227 [3]),
        .I3(\timerWTP_reg[0][0][1][3][1]_0 [1]),
        .I4(\timerWTP_reg[0][0][1][3][1]_0 [0]),
        .I5(\timerWTP_reg[0][0][1][3]_227 [2]),
        .O(p_0_in__10[3]));
  FDRE \timerWTP_reg[0][0][0][0][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][0][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][0][0][1]_1 [0]),
        .Q(\timerWTP_reg[0][0][0][0][1]_0 [0]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][0][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][0][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][0][0][1]_1 [1]),
        .Q(\timerWTP_reg[0][0][0][0][1]_0 [1]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][0][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][0][3]_i_1_n_0 ),
        .D(p_0_in__62[2]),
        .Q(\timerWTP_reg[0][0][0][0]_234 [2]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][0][3] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][0][3]_i_1_n_0 ),
        .D(p_0_in__62[3]),
        .Q(\timerWTP_reg[0][0][0][0]_234 [3]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][1][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][1][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][0][1][1]_1 [0]),
        .Q(\timerWTP_reg[0][0][0][1][1]_0 [0]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][1][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][1][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][0][1][1]_1 [1]),
        .Q(\timerWTP_reg[0][0][0][1][1]_0 [1]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][1][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][1][3]_i_1_n_0 ),
        .D(p_0_in__46[2]),
        .Q(\timerWTP_reg[0][0][0][1]_232 [2]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][1][3] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][1][3]_i_1_n_0 ),
        .D(p_0_in__46[3]),
        .Q(\timerWTP_reg[0][0][0][1]_232 [3]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][2][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][2][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][0][2][1]_1 [0]),
        .Q(\timerWTP_reg[0][0][0][2][1]_0 [0]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][2][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][2][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][0][2][1]_1 [1]),
        .Q(\timerWTP_reg[0][0][0][2][1]_0 [1]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][2][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][2][3]_i_1_n_0 ),
        .D(p_0_in__30[2]),
        .Q(\timerWTP_reg[0][0][0][2]_230 [2]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][2][3] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][2][3]_i_1_n_0 ),
        .D(p_0_in__30[3]),
        .Q(\timerWTP_reg[0][0][0][2]_230 [3]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][3][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][3][3]_i_1_n_0 ),
        .D(D[0]),
        .Q(Q[0]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][3][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][3][3]_i_1_n_0 ),
        .D(D[1]),
        .Q(Q[1]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][3][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][3][3]_i_1_n_0 ),
        .D(p_0_in__14[2]),
        .Q(\timerWTP_reg[0][0][0][3]_228 [2]),
        .R(out));
  FDRE \timerWTP_reg[0][0][0][3][3] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][0][3][3]_i_1_n_0 ),
        .D(p_0_in__14[3]),
        .Q(\timerWTP_reg[0][0][0][3]_228 [3]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][0][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][0][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][1][0][1]_1 [0]),
        .Q(\timerWTP_reg[0][0][1][0][1]_0 [0]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][0][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][0][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][1][0][1]_1 [1]),
        .Q(\timerWTP_reg[0][0][1][0][1]_0 [1]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][0][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][0][3]_i_1_n_0 ),
        .D(p_0_in__58[2]),
        .Q(\timerWTP_reg[0][0][1][0]_233 [2]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][0][3] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][0][3]_i_1_n_0 ),
        .D(p_0_in__58[3]),
        .Q(\timerWTP_reg[0][0][1][0]_233 [3]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][1][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][1][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][1][1][1]_1 [0]),
        .Q(\timerWTP_reg[0][0][1][1][1]_0 [0]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][1][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][1][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][1][1][1]_1 [1]),
        .Q(\timerWTP_reg[0][0][1][1][1]_0 [1]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][1][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][1][3]_i_1_n_0 ),
        .D(p_0_in__42[2]),
        .Q(\timerWTP_reg[0][0][1][1]_231 [2]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][1][3] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][1][3]_i_1_n_0 ),
        .D(p_0_in__42[3]),
        .Q(\timerWTP_reg[0][0][1][1]_231 [3]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][2][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][2][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][1][2][1]_1 [0]),
        .Q(\timerWTP_reg[0][0][1][2][1]_0 [0]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][2][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][2][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][1][2][1]_1 [1]),
        .Q(\timerWTP_reg[0][0][1][2][1]_0 [1]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][2][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][2][3]_i_1_n_0 ),
        .D(p_0_in__26[2]),
        .Q(\timerWTP_reg[0][0][1][2]_229 [2]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][2][3] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][2][3]_i_1_n_0 ),
        .D(p_0_in__26[3]),
        .Q(\timerWTP_reg[0][0][1][2]_229 [3]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][3][0] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][3][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][1][3][1]_1 [0]),
        .Q(\timerWTP_reg[0][0][1][3][1]_0 [0]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][3][1] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][3][3]_i_1_n_0 ),
        .D(\timerWTP_reg[0][0][1][3][1]_1 [1]),
        .Q(\timerWTP_reg[0][0][1][3][1]_0 [1]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][3][2] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][3][3]_i_1_n_0 ),
        .D(p_0_in__10[2]),
        .Q(\timerWTP_reg[0][0][1][3]_227 [2]),
        .R(out));
  FDRE \timerWTP_reg[0][0][1][3][3] 
       (.C(\winPort_reg[3] ),
        .CE(\timerWTP[0][0][1][3][3]_i_1_n_0 ),
        .D(p_0_in__10[3]),
        .Q(\timerWTP_reg[0][0][1][3]_227 [3]),
        .R(out));
  ddr4_0_ddr4_v2_2_17_mc_arb_p u_ddr_mc_arb_p
       (.Q(winPort),
        .calDone(calDone),
        .calDone_reg(calDone_reg),
        .cmdBankP(cmdBankP),
        .cmdGroupP(cmdGroupP),
        .d_prevGroup(d_prevGroup),
        .mc_ADR(mc_ADR),
        .\mc_ADR7_reg[13] (\mc_ADR7_reg[13] ),
        .mc_BA(mc_BA),
        .mc_BG(mc_BG),
        .\mcal_PAR_dly_reg[0][7] (\mcal_PAR_dly_reg[0][7] ),
        .out(out),
        .preIss(preIss),
        .preReqR(preReqR),
        .\winPort[1]_i_2_0 (\pre_safe_reg_n_0_[0][0][1][3] ),
        .\winPort[1]_i_2_1 (\pre_safe_reg_n_0_[0][0][0][3] ),
        .\winPort[1]_i_2_2 (\pre_safe_reg_n_0_[0][0][1][1] ),
        .\winPort[1]_i_2_3 (\pre_safe_reg_n_0_[0][0][0][1] ),
        .\winPort[1]_i_2_4 (\pre_safe_reg_n_0_[0][0][1][2] ),
        .\winPort[1]_i_2_5 (\pre_safe_reg_n_0_[0][0][0][2] ),
        .\winPort[1]_i_2_6 (\pre_safe_reg_n_0_[0][0][1][0] ),
        .\winPort[1]_i_2_7 (\pre_safe_reg_n_0_[0][0][0][0] ),
        .\winPort_reg[0]_0 (\winPort_reg[0] ),
        .\winPort_reg[0]_1 (\winPort_reg[0]_0 ),
        .\winPort_reg[0]_2 (\winPort_reg[0]_1 ),
        .\winPort_reg[1]_0 (\winPort_reg[1] ),
        .\winPort_reg[3]_0 (\winPort_reg[3] ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_arb_p" *) 
module ddr4_0_ddr4_v2_2_17_mc_arb_p
   (calDone_reg,
    mc_BG,
    mc_BA,
    mc_ADR,
    Q,
    \winPort_reg[1]_0 ,
    \mcal_PAR_dly_reg[0][7] ,
    calDone,
    \mc_ADR7_reg[13] ,
    cmdGroupP,
    d_prevGroup,
    preIss,
    cmdBankP,
    out,
    \winPort_reg[3]_0 ,
    \winPort_reg[0]_0 ,
    \winPort[1]_i_2_0 ,
    \winPort[1]_i_2_1 ,
    \winPort[1]_i_2_2 ,
    \winPort[1]_i_2_3 ,
    \winPort[1]_i_2_4 ,
    \winPort[1]_i_2_5 ,
    \winPort[1]_i_2_6 ,
    \winPort[1]_i_2_7 ,
    \winPort_reg[0]_1 ,
    \winPort_reg[0]_2 ,
    preReqR);
  output calDone_reg;
  output [0:0]mc_BG;
  output [1:0]mc_BA;
  output [0:0]mc_ADR;
  output [3:0]Q;
  output \winPort_reg[1]_0 ;
  input \mcal_PAR_dly_reg[0][7] ;
  input calDone;
  input \mc_ADR7_reg[13] ;
  input [3:0]cmdGroupP;
  input d_prevGroup;
  input preIss;
  input [7:0]cmdBankP;
  input out;
  input \winPort_reg[3]_0 ;
  input \winPort_reg[0]_0 ;
  input \winPort[1]_i_2_0 ;
  input \winPort[1]_i_2_1 ;
  input \winPort[1]_i_2_2 ;
  input \winPort[1]_i_2_3 ;
  input \winPort[1]_i_2_4 ;
  input \winPort[1]_i_2_5 ;
  input \winPort[1]_i_2_6 ;
  input \winPort[1]_i_2_7 ;
  input \winPort_reg[0]_1 ;
  input \winPort_reg[0]_2 ;
  input preReqR;

  wire [3:0]Q;
  wire calDone;
  wire calDone_reg;
  wire [7:0]cmdBankP;
  wire [3:0]cmdGroupP;
  wire d_prevGroup;
  wire last;
  wire last10_i_1_n_0;
  wire last10_reg_n_0;
  wire last32_i_1__1_n_0;
  wire last32_i_2_n_0;
  wire last32_reg_n_0;
  wire last_i_1_n_0;
  wire [0:0]mc_ADR;
  wire \mc_ADR7_reg[13] ;
  wire [1:0]mc_BA;
  wire \mc_BA7[0]_i_2_n_0 ;
  wire \mc_BA7[1]_i_2_n_0 ;
  wire [0:0]mc_BG;
  wire \mc_BG7[0]_i_2_n_0 ;
  wire \mcal_PAR_dly_reg[0][7] ;
  wire out;
  wire preIss;
  wire preReqR;
  wire [3:3]win3210;
  wire \winPort[0]_i_1__1_n_0 ;
  wire \winPort[1]_i_1__1_n_0 ;
  wire \winPort[1]_i_2_0 ;
  wire \winPort[1]_i_2_1 ;
  wire \winPort[1]_i_2_2 ;
  wire \winPort[1]_i_2_3 ;
  wire \winPort[1]_i_2_4 ;
  wire \winPort[1]_i_2_5 ;
  wire \winPort[1]_i_2_6 ;
  wire \winPort[1]_i_2_7 ;
  wire \winPort[1]_i_2_n_0 ;
  wire \winPort[1]_i_3_n_0 ;
  wire \winPort[1]_i_4_n_0 ;
  wire \winPort[1]_i_5_n_0 ;
  wire \winPort[1]_i_6_n_0 ;
  wire \winPort[1]_i_7_n_0 ;
  wire \winPort[2]_i_1__1_n_0 ;
  wire \winPort[3]_i_2__1_n_0 ;
  wire \winPort[3]_i_3_n_0 ;
  wire \winPort[3]_i_4_n_0 ;
  wire \winPort[3]_i_5_n_0 ;
  wire \winPort[3]_i_6_n_0 ;
  wire \winPort[3]_i_7_n_0 ;
  wire \winPort[3]_i_8_n_0 ;
  wire \winPort_reg[0]_0 ;
  wire \winPort_reg[0]_1 ;
  wire \winPort_reg[0]_2 ;
  wire \winPort_reg[1]_0 ;
  wire \winPort_reg[3]_0 ;

  LUT6 #(
    .INIT(64'h3232FFFFCD00CD00)) 
    last10_i_1
       (.I0(\winPort[3]_i_4_n_0 ),
        .I1(last),
        .I2(\winPort[3]_i_3_n_0 ),
        .I3(\winPort[1]_i_3_n_0 ),
        .I4(\winPort[1]_i_2_n_0 ),
        .I5(last10_reg_n_0),
        .O(last10_i_1_n_0));
  FDRE last10_reg
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(last10_i_1_n_0),
        .Q(last10_reg_n_0),
        .R(out));
  LUT6 #(
    .INIT(64'hC4C4FFFFBB80BB00)) 
    last32_i_1__1
       (.I0(\winPort[3]_i_2__1_n_0 ),
        .I1(last),
        .I2(last32_i_2_n_0),
        .I3(\winPort[3]_i_4_n_0 ),
        .I4(\winPort[3]_i_3_n_0 ),
        .I5(last32_reg_n_0),
        .O(last32_i_1__1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    last32_i_2
       (.I0(\winPort[1]_i_3_n_0 ),
        .I1(\winPort[1]_i_2_n_0 ),
        .O(last32_i_2_n_0));
  FDRE last32_reg
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(last32_i_1__1_n_0),
        .Q(last32_reg_n_0),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2814" *) 
  LUT5 #(
    .INIT(32'h0303FFAA)) 
    last_i_1
       (.I0(\winPort[3]_i_3_n_0 ),
        .I1(\winPort[1]_i_3_n_0 ),
        .I2(\winPort[1]_i_2_n_0 ),
        .I3(\winPort[3]_i_4_n_0 ),
        .I4(last),
        .O(last_i_1_n_0));
  FDRE last_reg
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(last_i_1_n_0),
        .Q(last),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2812" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    \mc_ADR7[13]_i_1 
       (.I0(\mc_ADR7_reg[13] ),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(mc_ADR));
  (* SOFT_HLUTNM = "soft_lutpair2812" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \mc_ADR7[16]_i_2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(\winPort_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hE2FFE200E2FFE2FF)) 
    \mc_BA7[0]_i_1 
       (.I0(\mc_BA7[0]_i_2_n_0 ),
        .I1(Q[0]),
        .I2(cmdBankP[0]),
        .I3(\winPort_reg[1]_0 ),
        .I4(d_prevGroup),
        .I5(preIss),
        .O(mc_BA[0]));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \mc_BA7[0]_i_2 
       (.I0(cmdBankP[2]),
        .I1(cmdBankP[6]),
        .I2(cmdBankP[4]),
        .I3(Q[1]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\mc_BA7[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hE2FFE200E2FFE2FF)) 
    \mc_BA7[1]_i_1 
       (.I0(\mc_BA7[1]_i_2_n_0 ),
        .I1(Q[0]),
        .I2(cmdBankP[1]),
        .I3(\winPort_reg[1]_0 ),
        .I4(d_prevGroup),
        .I5(preIss),
        .O(mc_BA[1]));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \mc_BA7[1]_i_2 
       (.I0(cmdBankP[3]),
        .I1(cmdBankP[7]),
        .I2(cmdBankP[5]),
        .I3(Q[1]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\mc_BA7[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hE2FFE200E2FFE2FF)) 
    \mc_BG7[0]_i_1 
       (.I0(\mc_BG7[0]_i_2_n_0 ),
        .I1(Q[0]),
        .I2(cmdGroupP[0]),
        .I3(\winPort_reg[1]_0 ),
        .I4(d_prevGroup),
        .I5(preIss),
        .O(mc_BG));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \mc_BG7[0]_i_2 
       (.I0(cmdGroupP[1]),
        .I1(cmdGroupP[3]),
        .I2(cmdGroupP[2]),
        .I3(Q[1]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(\mc_BG7[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h69FF)) 
    \mcal_PAR_dly[0][7]_i_2 
       (.I0(\mcal_PAR_dly_reg[0][7] ),
        .I1(mc_BG),
        .I2(mc_BA[0]),
        .I3(calDone),
        .O(calDone_reg));
  LUT6 #(
    .INIT(64'hD0D00000D0D000D0)) 
    \winPort[0]_i_1__1 
       (.I0(\winPort[1]_i_3_n_0 ),
        .I1(last10_reg_n_0),
        .I2(\winPort[1]_i_2_n_0 ),
        .I3(\winPort[3]_i_4_n_0 ),
        .I4(last),
        .I5(\winPort[3]_i_3_n_0 ),
        .O(\winPort[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h7070000070700070)) 
    \winPort[1]_i_1__1 
       (.I0(last10_reg_n_0),
        .I1(\winPort[1]_i_2_n_0 ),
        .I2(\winPort[1]_i_3_n_0 ),
        .I3(\winPort[3]_i_4_n_0 ),
        .I4(last),
        .I5(\winPort[3]_i_3_n_0 ),
        .O(\winPort[1]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00E20000)) 
    \winPort[1]_i_2 
       (.I0(\winPort[1]_i_4_n_0 ),
        .I1(cmdBankP[0]),
        .I2(\winPort[1]_i_5_n_0 ),
        .I3(Q[0]),
        .I4(preReqR),
        .O(\winPort[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00E20000)) 
    \winPort[1]_i_3 
       (.I0(\winPort[1]_i_6_n_0 ),
        .I1(cmdBankP[2]),
        .I2(\winPort[1]_i_7_n_0 ),
        .I3(Q[1]),
        .I4(\winPort_reg[0]_2 ),
        .O(\winPort[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \winPort[1]_i_4 
       (.I0(\winPort[1]_i_2_4 ),
        .I1(\winPort[1]_i_2_5 ),
        .I2(cmdBankP[1]),
        .I3(\winPort[1]_i_2_6 ),
        .I4(cmdGroupP[0]),
        .I5(\winPort[1]_i_2_7 ),
        .O(\winPort[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \winPort[1]_i_5 
       (.I0(\winPort[1]_i_2_0 ),
        .I1(\winPort[1]_i_2_1 ),
        .I2(cmdBankP[1]),
        .I3(\winPort[1]_i_2_2 ),
        .I4(cmdGroupP[0]),
        .I5(\winPort[1]_i_2_3 ),
        .O(\winPort[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \winPort[1]_i_6 
       (.I0(\winPort[1]_i_2_4 ),
        .I1(\winPort[1]_i_2_5 ),
        .I2(cmdBankP[3]),
        .I3(\winPort[1]_i_2_6 ),
        .I4(cmdGroupP[1]),
        .I5(\winPort[1]_i_2_7 ),
        .O(\winPort[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \winPort[1]_i_7 
       (.I0(\winPort[1]_i_2_0 ),
        .I1(\winPort[1]_i_2_1 ),
        .I2(cmdBankP[3]),
        .I3(\winPort[1]_i_2_2 ),
        .I4(cmdGroupP[1]),
        .I5(\winPort[1]_i_2_3 ),
        .O(\winPort[1]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2813" *) 
  LUT5 #(
    .INIT(32'hB000B0B0)) 
    \winPort[2]_i_1__1 
       (.I0(\winPort[3]_i_2__1_n_0 ),
        .I1(last),
        .I2(\winPort[3]_i_3_n_0 ),
        .I3(last32_reg_n_0),
        .I4(\winPort[3]_i_4_n_0 ),
        .O(\winPort[2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2813" *) 
  LUT5 #(
    .INIT(32'h0BBB0000)) 
    \winPort[3]_i_1__1 
       (.I0(\winPort[3]_i_2__1_n_0 ),
        .I1(last),
        .I2(last32_reg_n_0),
        .I3(\winPort[3]_i_3_n_0 ),
        .I4(\winPort[3]_i_4_n_0 ),
        .O(win3210));
  (* SOFT_HLUTNM = "soft_lutpair2814" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \winPort[3]_i_2__1 
       (.I0(\winPort[1]_i_3_n_0 ),
        .I1(\winPort[1]_i_2_n_0 ),
        .O(\winPort[3]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00E20000)) 
    \winPort[3]_i_3 
       (.I0(\winPort[3]_i_5_n_0 ),
        .I1(cmdBankP[4]),
        .I2(\winPort[3]_i_6_n_0 ),
        .I3(Q[2]),
        .I4(\winPort_reg[0]_1 ),
        .O(\winPort[3]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00E20000)) 
    \winPort[3]_i_4 
       (.I0(\winPort[3]_i_7_n_0 ),
        .I1(cmdBankP[6]),
        .I2(\winPort[3]_i_8_n_0 ),
        .I3(Q[3]),
        .I4(\winPort_reg[0]_0 ),
        .O(\winPort[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \winPort[3]_i_5 
       (.I0(\winPort[1]_i_2_4 ),
        .I1(\winPort[1]_i_2_5 ),
        .I2(cmdBankP[5]),
        .I3(\winPort[1]_i_2_6 ),
        .I4(cmdGroupP[2]),
        .I5(\winPort[1]_i_2_7 ),
        .O(\winPort[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \winPort[3]_i_6 
       (.I0(\winPort[1]_i_2_0 ),
        .I1(\winPort[1]_i_2_1 ),
        .I2(cmdBankP[5]),
        .I3(\winPort[1]_i_2_2 ),
        .I4(cmdGroupP[2]),
        .I5(\winPort[1]_i_2_3 ),
        .O(\winPort[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \winPort[3]_i_7 
       (.I0(\winPort[1]_i_2_4 ),
        .I1(\winPort[1]_i_2_5 ),
        .I2(cmdBankP[7]),
        .I3(\winPort[1]_i_2_6 ),
        .I4(cmdGroupP[3]),
        .I5(\winPort[1]_i_2_7 ),
        .O(\winPort[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \winPort[3]_i_8 
       (.I0(\winPort[1]_i_2_0 ),
        .I1(\winPort[1]_i_2_1 ),
        .I2(cmdBankP[7]),
        .I3(\winPort[1]_i_2_2 ),
        .I4(cmdGroupP[3]),
        .I5(\winPort[1]_i_2_3 ),
        .O(\winPort[3]_i_8_n_0 ));
  FDRE \winPort_reg[0] 
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(\winPort[0]_i_1__1_n_0 ),
        .Q(Q[0]),
        .R(out));
  FDRE \winPort_reg[1] 
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(\winPort[1]_i_1__1_n_0 ),
        .Q(Q[1]),
        .R(out));
  FDRE \winPort_reg[2] 
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(\winPort[2]_i_1__1_n_0 ),
        .Q(Q[2]),
        .R(out));
  FDRE \winPort_reg[3] 
       (.C(\winPort_reg[3]_0 ),
        .CE(1'b1),
        .D(win3210),
        .Q(Q[3]),
        .R(out));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_cmd_mux_ap" *) 
module ddr4_0_ddr4_v2_2_17_mc_cmd_mux_ap
   (\txn_fifo_output_reg[0] ,
    winBankA,
    winGroupA,
    \txn_fifo_output_reg[24] ,
    \txn_fifo_output_reg[25] ,
    \txn_fifo_output_reg[26] ,
    \txn_fifo_output_reg[27] ,
    \txn_fifo_output_reg[28] ,
    \txn_fifo_output_reg[29] ,
    \txn_fifo_output_reg[30] ,
    \txn_fifo_output_reg[31] ,
    \txn_fifo_output_reg[32] ,
    \txn_fifo_output_reg[33] ,
    \txn_fifo_output_reg[34] ,
    \txn_fifo_output_reg[35] ,
    \txn_fifo_output_reg[36] ,
    \txn_fifo_output_reg[37] ,
    \txn_fifo_output_reg[38] ,
    \txn_fifo_output_reg[39] ,
    \txn_fifo_output_reg[40] ,
    Q,
    \mcal_ADR_dly[0][132]_i_2 ,
    \mcal_ADR_dly[0][132]_i_2_0 ,
    \mcal_BA_dly_reg[0][4] ,
    \mcal_BG_dly_reg[0][4] );
  output \txn_fifo_output_reg[0] ;
  output [0:0]winBankA;
  output [0:0]winGroupA;
  output \txn_fifo_output_reg[24] ;
  output \txn_fifo_output_reg[25] ;
  output \txn_fifo_output_reg[26] ;
  output \txn_fifo_output_reg[27] ;
  output \txn_fifo_output_reg[28] ;
  output \txn_fifo_output_reg[29] ;
  output \txn_fifo_output_reg[30] ;
  output \txn_fifo_output_reg[31] ;
  output \txn_fifo_output_reg[32] ;
  output \txn_fifo_output_reg[33] ;
  output \txn_fifo_output_reg[34] ;
  output \txn_fifo_output_reg[35] ;
  output \txn_fifo_output_reg[36] ;
  output \txn_fifo_output_reg[37] ;
  output \txn_fifo_output_reg[38] ;
  output \txn_fifo_output_reg[39] ;
  output \txn_fifo_output_reg[40] ;
  input [19:0]Q;
  input [19:0]\mcal_ADR_dly[0][132]_i_2 ;
  input [19:0]\mcal_ADR_dly[0][132]_i_2_0 ;
  input [3:0]\mcal_BA_dly_reg[0][4] ;
  input [1:0]\mcal_BG_dly_reg[0][4] ;

  wire [19:0]Q;
  wire \i_/mcal_BA_dly[0][12]_i_4_n_0 ;
  wire \i_/mcal_BG_dly[0][4]_i_3_n_0 ;
  wire [19:0]\mcal_ADR_dly[0][132]_i_2 ;
  wire [19:0]\mcal_ADR_dly[0][132]_i_2_0 ;
  wire [3:0]\mcal_BA_dly_reg[0][4] ;
  wire [1:0]\mcal_BG_dly_reg[0][4] ;
  wire \txn_fifo_output_reg[0] ;
  wire \txn_fifo_output_reg[24] ;
  wire \txn_fifo_output_reg[25] ;
  wire \txn_fifo_output_reg[26] ;
  wire \txn_fifo_output_reg[27] ;
  wire \txn_fifo_output_reg[28] ;
  wire \txn_fifo_output_reg[29] ;
  wire \txn_fifo_output_reg[30] ;
  wire \txn_fifo_output_reg[31] ;
  wire \txn_fifo_output_reg[32] ;
  wire \txn_fifo_output_reg[33] ;
  wire \txn_fifo_output_reg[34] ;
  wire \txn_fifo_output_reg[35] ;
  wire \txn_fifo_output_reg[36] ;
  wire \txn_fifo_output_reg[37] ;
  wire \txn_fifo_output_reg[38] ;
  wire \txn_fifo_output_reg[39] ;
  wire \txn_fifo_output_reg[40] ;
  wire [0:0]winBankA;
  wire [0:0]winGroupA;

  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][100]_i_3 
       (.I0(Q[15]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [15]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [15]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[36] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][108]_i_3 
       (.I0(Q[16]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [16]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [16]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[37] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][116]_i_4 
       (.I0(Q[17]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [17]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [17]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[38] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][124]_i_4 
       (.I0(Q[18]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [18]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [18]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[39] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][12]_i_3 
       (.I0(Q[4]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [4]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [4]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[25] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][132]_i_4 
       (.I0(Q[19]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [19]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [19]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[40] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][20]_i_3 
       (.I0(Q[5]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [5]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [5]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[26] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][28]_i_3 
       (.I0(Q[6]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [6]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [6]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[27] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][36]_i_3 
       (.I0(Q[7]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [7]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [7]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[28] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][44]_i_3 
       (.I0(Q[8]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [8]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [8]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[29] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][4]_i_3 
       (.I0(Q[3]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [3]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [3]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[24] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][52]_i_3 
       (.I0(Q[9]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [9]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [9]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[30] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][60]_i_3 
       (.I0(Q[10]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [10]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [10]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[31] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][68]_i_3 
       (.I0(Q[11]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [11]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [11]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[32] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][76]_i_3 
       (.I0(Q[12]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [12]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [12]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[33] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][84]_i_3 
       (.I0(Q[13]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [13]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [13]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[34] ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_ADR_dly[0][92]_i_3 
       (.I0(Q[14]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [14]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [14]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[35] ));
  LUT3 #(
    .INIT(8'hE2)) 
    \i_/mcal_BA_dly[0][12]_i_3 
       (.I0(\i_/mcal_BA_dly[0][12]_i_4_n_0 ),
        .I1(\mcal_BA_dly_reg[0][4] [0]),
        .I2(\mcal_BG_dly_reg[0][4] [0]),
        .O(winBankA));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_BA_dly[0][12]_i_4 
       (.I0(Q[1]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [1]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [1]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\i_/mcal_BA_dly[0][12]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_BA_dly[0][4]_i_2 
       (.I0(Q[0]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [0]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [0]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\txn_fifo_output_reg[0] ));
  LUT3 #(
    .INIT(8'hE2)) 
    \i_/mcal_BG_dly[0][4]_i_2 
       (.I0(\i_/mcal_BG_dly[0][4]_i_3_n_0 ),
        .I1(\mcal_BA_dly_reg[0][4] [0]),
        .I2(\mcal_BG_dly_reg[0][4] [1]),
        .O(winGroupA));
  LUT6 #(
    .INIT(64'hAAF0AAF0AACCAA00)) 
    \i_/mcal_BG_dly[0][4]_i_3 
       (.I0(Q[2]),
        .I1(\mcal_ADR_dly[0][132]_i_2 [2]),
        .I2(\mcal_ADR_dly[0][132]_i_2_0 [2]),
        .I3(\mcal_BA_dly_reg[0][4] [1]),
        .I4(\mcal_BA_dly_reg[0][4] [3]),
        .I5(\mcal_BA_dly_reg[0][4] [2]),
        .O(\i_/mcal_BG_dly[0][4]_i_3_n_0 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_cmd_mux_c" *) 
module ddr4_0_ddr4_v2_2_17_mc_cmd_mux_c
   (\cmd_bank_cas_reg[1] ,
    \cmd_bank_cas_reg[0] ,
    cmdInjTxn_reg,
    winAP,
    \cmdCol_reg[9] ,
    \cmdCol_reg[8] ,
    \cmdCol_reg[7] ,
    \cmdCol_reg[6] ,
    \cmdCol_reg[5] ,
    \cmdCol_reg[4] ,
    \cmdCol_reg[3] ,
    winGroupC,
    cmd_bank_cas,
    Q,
    cmdBuf,
    \read_lat_fifo_in_reg[5] ,
    \read_lat_fifo_in_reg[5]_0 ,
    \read_lat_fifo_in_reg[5]_1 ,
    \read_lat_fifo_in_reg[5]_2 ,
    cmdAP,
    cmdCol,
    cmd_group_cas,
    cmdInjTxn);
  output \cmd_bank_cas_reg[1] ;
  output \cmd_bank_cas_reg[0] ;
  output [6:0]cmdInjTxn_reg;
  output winAP;
  output \cmdCol_reg[9] ;
  output \cmdCol_reg[8] ;
  output \cmdCol_reg[7] ;
  output \cmdCol_reg[6] ;
  output \cmdCol_reg[5] ;
  output \cmdCol_reg[4] ;
  output \cmdCol_reg[3] ;
  output [0:0]winGroupC;
  input [5:0]cmd_bank_cas;
  input [3:0]Q;
  input [19:0]cmdBuf;
  input \read_lat_fifo_in_reg[5] ;
  input \read_lat_fifo_in_reg[5]_0 ;
  input \read_lat_fifo_in_reg[5]_1 ;
  input \read_lat_fifo_in_reg[5]_2 ;
  input [3:0]cmdAP;
  input [20:0]cmdCol;
  input [3:0]cmd_group_cas;
  input [0:0]cmdInjTxn;

  wire [3:0]Q;
  wire [3:0]cmdAP;
  wire [19:0]cmdBuf;
  wire [20:0]cmdCol;
  wire \cmdCol_reg[3] ;
  wire \cmdCol_reg[4] ;
  wire \cmdCol_reg[5] ;
  wire \cmdCol_reg[6] ;
  wire \cmdCol_reg[7] ;
  wire \cmdCol_reg[8] ;
  wire \cmdCol_reg[9] ;
  wire [0:0]cmdInjTxn;
  wire [6:0]cmdInjTxn_reg;
  wire [5:0]cmd_bank_cas;
  wire \cmd_bank_cas_reg[0] ;
  wire \cmd_bank_cas_reg[1] ;
  wire [3:0]cmd_group_cas;
  wire \i_/prevCmdAP_i_2_n_0 ;
  wire \i_/prevCmdAP_i_3_n_0 ;
  wire \i_/prevGr[0]_i_3_n_0 ;
  wire \i_/read_lat_fifo_in[0]_i_2_n_0 ;
  wire \i_/read_lat_fifo_in[1]_i_2_n_0 ;
  wire \i_/read_lat_fifo_in[2]_i_2_n_0 ;
  wire \i_/read_lat_fifo_in[3]_i_2_n_0 ;
  wire \i_/read_lat_fifo_in[4]_i_2_n_0 ;
  wire \i_/read_lat_fifo_in[5]_i_2_n_0 ;
  wire \read_lat_fifo_in_reg[5] ;
  wire \read_lat_fifo_in_reg[5]_0 ;
  wire \read_lat_fifo_in_reg[5]_1 ;
  wire \read_lat_fifo_in_reg[5]_2 ;
  wire winAP;
  wire [0:0]winGroupC;

  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/mcal_ADR_dly[0][30]_i_3 
       (.I0(cmdCol[0]),
        .I1(Q[1]),
        .I2(cmdCol[7]),
        .I3(Q[2]),
        .I4(cmdCol[14]),
        .I5(Q[3]),
        .O(\cmdCol_reg[3] ));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/mcal_ADR_dly[0][38]_i_3 
       (.I0(cmdCol[1]),
        .I1(Q[1]),
        .I2(cmdCol[8]),
        .I3(Q[2]),
        .I4(cmdCol[15]),
        .I5(Q[3]),
        .O(\cmdCol_reg[4] ));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/mcal_ADR_dly[0][46]_i_3 
       (.I0(cmdCol[2]),
        .I1(Q[1]),
        .I2(cmdCol[9]),
        .I3(Q[2]),
        .I4(cmdCol[16]),
        .I5(Q[3]),
        .O(\cmdCol_reg[5] ));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/mcal_ADR_dly[0][54]_i_3 
       (.I0(cmdCol[3]),
        .I1(Q[1]),
        .I2(cmdCol[10]),
        .I3(Q[2]),
        .I4(cmdCol[17]),
        .I5(Q[3]),
        .O(\cmdCol_reg[6] ));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/mcal_ADR_dly[0][62]_i_3 
       (.I0(cmdCol[4]),
        .I1(Q[1]),
        .I2(cmdCol[11]),
        .I3(Q[2]),
        .I4(cmdCol[18]),
        .I5(Q[3]),
        .O(\cmdCol_reg[7] ));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/mcal_ADR_dly[0][70]_i_3 
       (.I0(cmdCol[5]),
        .I1(Q[1]),
        .I2(cmdCol[12]),
        .I3(Q[2]),
        .I4(cmdCol[19]),
        .I5(Q[3]),
        .O(\cmdCol_reg[8] ));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/mcal_ADR_dly[0][78]_i_3 
       (.I0(cmdCol[6]),
        .I1(Q[1]),
        .I2(cmdCol[13]),
        .I3(Q[2]),
        .I4(cmdCol[20]),
        .I5(Q[3]),
        .O(\cmdCol_reg[9] ));
  LUT6 #(
    .INIT(64'h2F202F2F2F202020)) 
    \i_/prevCmdAP_i_1 
       (.I0(cmdAP[0]),
        .I1(\read_lat_fifo_in_reg[5] ),
        .I2(Q[0]),
        .I3(\i_/prevCmdAP_i_2_n_0 ),
        .I4(Q[1]),
        .I5(\i_/prevCmdAP_i_3_n_0 ),
        .O(winAP));
  LUT2 #(
    .INIT(4'h2)) 
    \i_/prevCmdAP_i_2 
       (.I0(cmdAP[1]),
        .I1(\read_lat_fifo_in_reg[5]_0 ),
        .O(\i_/prevCmdAP_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0C550C000C000C00)) 
    \i_/prevCmdAP_i_3 
       (.I0(\read_lat_fifo_in_reg[5]_1 ),
        .I1(cmdAP[2]),
        .I2(\read_lat_fifo_in_reg[5]_2 ),
        .I3(Q[2]),
        .I4(cmdAP[3]),
        .I5(Q[3]),
        .O(\i_/prevCmdAP_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \i_/prevGr[0]_i_2 
       (.I0(cmd_group_cas[0]),
        .I1(Q[0]),
        .I2(\i_/prevGr[0]_i_3_n_0 ),
        .O(winGroupC));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/prevGr[0]_i_3 
       (.I0(cmd_group_cas[1]),
        .I1(Q[1]),
        .I2(cmd_group_cas[2]),
        .I3(Q[2]),
        .I4(cmd_group_cas[3]),
        .I5(Q[3]),
        .O(\i_/prevGr[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2824" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \i_/read_lat_fifo_in[0]_i_1 
       (.I0(cmdBuf[0]),
        .I1(Q[0]),
        .I2(\i_/read_lat_fifo_in[0]_i_2_n_0 ),
        .O(cmdInjTxn_reg[0]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/read_lat_fifo_in[0]_i_2 
       (.I0(cmdBuf[5]),
        .I1(Q[1]),
        .I2(cmdBuf[10]),
        .I3(Q[2]),
        .I4(cmdBuf[15]),
        .I5(Q[3]),
        .O(\i_/read_lat_fifo_in[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2824" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \i_/read_lat_fifo_in[1]_i_1 
       (.I0(cmdBuf[1]),
        .I1(Q[0]),
        .I2(\i_/read_lat_fifo_in[1]_i_2_n_0 ),
        .O(cmdInjTxn_reg[1]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/read_lat_fifo_in[1]_i_2 
       (.I0(cmdBuf[6]),
        .I1(Q[1]),
        .I2(cmdBuf[11]),
        .I3(Q[2]),
        .I4(cmdBuf[16]),
        .I5(Q[3]),
        .O(\i_/read_lat_fifo_in[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2823" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \i_/read_lat_fifo_in[2]_i_1 
       (.I0(cmdBuf[2]),
        .I1(Q[0]),
        .I2(\i_/read_lat_fifo_in[2]_i_2_n_0 ),
        .O(cmdInjTxn_reg[2]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/read_lat_fifo_in[2]_i_2 
       (.I0(cmdBuf[7]),
        .I1(Q[1]),
        .I2(cmdBuf[12]),
        .I3(Q[2]),
        .I4(cmdBuf[17]),
        .I5(Q[3]),
        .O(\i_/read_lat_fifo_in[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2823" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \i_/read_lat_fifo_in[3]_i_1 
       (.I0(cmdBuf[3]),
        .I1(Q[0]),
        .I2(\i_/read_lat_fifo_in[3]_i_2_n_0 ),
        .O(cmdInjTxn_reg[3]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/read_lat_fifo_in[3]_i_2 
       (.I0(cmdBuf[8]),
        .I1(Q[1]),
        .I2(cmdBuf[13]),
        .I3(Q[2]),
        .I4(cmdBuf[18]),
        .I5(Q[3]),
        .O(\i_/read_lat_fifo_in[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2825" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \i_/read_lat_fifo_in[4]_i_1 
       (.I0(cmdBuf[4]),
        .I1(Q[0]),
        .I2(\i_/read_lat_fifo_in[4]_i_2_n_0 ),
        .O(cmdInjTxn_reg[4]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/read_lat_fifo_in[4]_i_2 
       (.I0(cmdBuf[9]),
        .I1(Q[1]),
        .I2(cmdBuf[14]),
        .I3(Q[2]),
        .I4(cmdBuf[19]),
        .I5(Q[3]),
        .O(\i_/read_lat_fifo_in[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2825" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \i_/read_lat_fifo_in[5]_i_1 
       (.I0(\read_lat_fifo_in_reg[5] ),
        .I1(Q[0]),
        .I2(\i_/read_lat_fifo_in[5]_i_2_n_0 ),
        .O(cmdInjTxn_reg[5]));
  LUT6 #(
    .INIT(64'hBBBB8888B888B888)) 
    \i_/read_lat_fifo_in[5]_i_2 
       (.I0(\read_lat_fifo_in_reg[5]_0 ),
        .I1(Q[1]),
        .I2(Q[3]),
        .I3(\read_lat_fifo_in_reg[5]_1 ),
        .I4(\read_lat_fifo_in_reg[5]_2 ),
        .I5(Q[2]),
        .O(\i_/read_lat_fifo_in[5]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \i_/read_lat_fifo_in[6]_i_1 
       (.I0(cmdInjTxn),
        .I1(Q[0]),
        .O(cmdInjTxn_reg[6]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/timerWTP[0][0][1][3][3]_i_4 
       (.I0(cmd_bank_cas[0]),
        .I1(Q[1]),
        .I2(cmd_bank_cas[2]),
        .I3(Q[2]),
        .I4(cmd_bank_cas[4]),
        .I5(Q[3]),
        .O(\cmd_bank_cas_reg[0] ));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \i_/timerWTP[0][0][1][3][3]_i_5 
       (.I0(cmd_bank_cas[1]),
        .I1(Q[1]),
        .I2(cmd_bank_cas[3]),
        .I3(Q[2]),
        .I4(cmd_bank_cas[5]),
        .I5(Q[3]),
        .O(\cmd_bank_cas_reg[1] ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_ctl" *) 
module ddr4_0_ddr4_v2_2_17_mc_ctl
   (prevCAS_reg_0,
    prevCmdAP,
    prevGroup,
    D,
    tranSentC,
    mc_ADR,
    mcRdCAS,
    winRead_reg,
    winRead_reg_0,
    winRead_reg_1,
    winRead_reg_2,
    oe_fabric,
    mc_ODT,
    \odt_shift_reg[0][18] ,
    prevCAS_reg_1,
    out,
    \odt_shift_reg[0][20] ,
    winAP,
    \prevGroup_reg[0]_0 ,
    winWrite,
    Q,
    winRead,
    per_cas_block_req,
    calDone,
    \mcal_ADR_dly_reg[0][126] ,
    cal_CS_n,
    oe_0_mux_cal,
    win_group_cas,
    prevSlot2_reg_0,
    \odt_shift_reg[0][20]_0 );
  output prevCAS_reg_0;
  output prevCmdAP;
  output prevGroup;
  output [0:0]D;
  output tranSentC;
  output [2:0]mc_ADR;
  output mcRdCAS;
  output [7:0]winRead_reg;
  output [3:0]winRead_reg_0;
  output winRead_reg_1;
  output winRead_reg_2;
  output [0:0]oe_fabric;
  output [0:0]mc_ODT;
  output [1:0]\odt_shift_reg[0][18] ;
  output prevCAS_reg_1;
  input out;
  input \odt_shift_reg[0][20] ;
  input winAP;
  input \prevGroup_reg[0]_0 ;
  input winWrite;
  input [0:0]Q;
  input winRead;
  input per_cas_block_req;
  input calDone;
  input [7:0]\mcal_ADR_dly_reg[0][126] ;
  input [3:0]cal_CS_n;
  input [0:0]oe_0_mux_cal;
  input [0:0]win_group_cas;
  input prevSlot2_reg_0;
  input [0:0]\odt_shift_reg[0][20]_0 ;

  wire [0:0]D;
  wire [0:0]Q;
  wire b2b_cas_not_allowed;
  wire calDone;
  wire [3:0]cal_CS_n;
  wire d_prevCmdAP;
  wire mcRdCAS;
  wire [2:0]mc_ADR;
  wire [0:0]mc_ODT;
  wire [7:0]\mcal_ADR_dly_reg[0][126] ;
  wire [1:0]\odt_shift_reg[0][18] ;
  wire \odt_shift_reg[0][20] ;
  wire [0:0]\odt_shift_reg[0][20]_0 ;
  wire [0:0]oe_0_mux_cal;
  wire [0:0]oe_fabric;
  wire out;
  wire per_cas_block_req;
  wire prevCAS_reg_0;
  wire prevCAS_reg_1;
  wire prevCAS_reg_n_0;
  wire prevCmdAP;
  wire prevGroup;
  wire \prevGroup_reg[0]_0 ;
  wire prevSlot2;
  wire prevSlot2_reg_0;
  wire tranSentC;
  wire winAP;
  wire winRead;
  wire [7:0]winRead_reg;
  wire [3:0]winRead_reg_0;
  wire winRead_reg_1;
  wire winRead_reg_2;
  wire winWrite;
  wire [0:0]win_group_cas;

  (* SOFT_HLUTNM = "soft_lutpair2827" *) 
  LUT4 #(
    .INIT(16'h7FF7)) 
    \FSM_sequential_gr_cas_state[2]_i_8 
       (.I0(prevCAS_reg_n_0),
        .I1(prevSlot2),
        .I2(prevGroup),
        .I3(win_group_cas),
        .O(prevCAS_reg_1));
  LUT6 #(
    .INIT(64'hFF80FF80FFFF80FF)) 
    \mc_ADR7[13]_i_2 
       (.I0(prevCAS_reg_n_0),
        .I1(prevSlot2),
        .I2(b2b_cas_not_allowed),
        .I3(winRead),
        .I4(per_cas_block_req),
        .I5(winWrite),
        .O(mc_ADR[2]));
  LUT6 #(
    .INIT(64'hFFDFFFFFFFDF0000)) 
    \mcal_ADR_dly[0][113]_i_1 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(calDone),
        .I5(\mcal_ADR_dly_reg[0][126] [0]),
        .O(winRead_reg[0]));
  LUT6 #(
    .INIT(64'hFFDFFFFFFFDF0000)) 
    \mcal_ADR_dly[0][114]_i_1 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(calDone),
        .I5(\mcal_ADR_dly_reg[0][126] [1]),
        .O(winRead_reg[1]));
  LUT6 #(
    .INIT(64'hDFFFFFFFDFFF0000)) 
    \mcal_ADR_dly[0][117]_i_1 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(calDone),
        .I5(\mcal_ADR_dly_reg[0][126] [2]),
        .O(winRead_reg[2]));
  LUT6 #(
    .INIT(64'hDFFFFFFFDFFF0000)) 
    \mcal_ADR_dly[0][118]_i_1 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(calDone),
        .I5(\mcal_ADR_dly_reg[0][126] [3]),
        .O(winRead_reg[3]));
  LUT6 #(
    .INIT(64'hFFD7FFFFFFD70000)) 
    \mcal_ADR_dly[0][121]_i_1 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(calDone),
        .I5(\mcal_ADR_dly_reg[0][126] [4]),
        .O(winRead_reg[4]));
  LUT6 #(
    .INIT(64'hFFD7FFFFFFD70000)) 
    \mcal_ADR_dly[0][122]_i_1 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(calDone),
        .I5(\mcal_ADR_dly_reg[0][126] [5]),
        .O(winRead_reg[5]));
  LUT6 #(
    .INIT(64'hD7FFFFFFD7FF0000)) 
    \mcal_ADR_dly[0][125]_i_1 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(calDone),
        .I5(\mcal_ADR_dly_reg[0][126] [6]),
        .O(winRead_reg[6]));
  LUT6 #(
    .INIT(64'hD7FFFFFFD7FF0000)) 
    \mcal_ADR_dly[0][126]_i_1 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(calDone),
        .I5(\mcal_ADR_dly_reg[0][126] [7]),
        .O(winRead_reg[7]));
  (* SOFT_HLUTNM = "soft_lutpair2828" *) 
  LUT5 #(
    .INIT(32'hD7FFD7D7)) 
    \mcal_ADR_dly[0][82]_i_2 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(winAP),
        .O(mc_ADR[0]));
  (* SOFT_HLUTNM = "soft_lutpair2828" *) 
  LUT5 #(
    .INIT(32'hFFD7D7D7)) 
    \mcal_ADR_dly[0][86]_i_2 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(winAP),
        .O(mc_ADR[1]));
  LUT6 #(
    .INIT(64'hFFD7FFFFFFD70000)) 
    \mcal_CS_n_dly[0][1]_i_1 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(calDone),
        .I5(cal_CS_n[0]),
        .O(winRead_reg_0[0]));
  LUT6 #(
    .INIT(64'hFFD7FFFFFFD70000)) 
    \mcal_CS_n_dly[0][2]_i_1 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(calDone),
        .I5(cal_CS_n[1]),
        .O(winRead_reg_0[1]));
  LUT6 #(
    .INIT(64'hD7FFFFFFD7FF0000)) 
    \mcal_CS_n_dly[0][5]_i_1 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(calDone),
        .I5(cal_CS_n[2]),
        .O(winRead_reg_0[2]));
  LUT6 #(
    .INIT(64'hD7FFFFFFD7FF0000)) 
    \mcal_CS_n_dly[0][6]_i_1 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .I4(calDone),
        .I5(cal_CS_n[3]),
        .O(winRead_reg_0[3]));
  (* SOFT_HLUTNM = "soft_lutpair2829" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    \mcal_PAR_dly[0][2]_i_5 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .O(winRead_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair2829" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    \mcal_PAR_dly[0][6]_i_5 
       (.I0(tranSentC),
        .I1(winRead),
        .I2(winWrite),
        .I3(prevCAS_reg_0),
        .O(winRead_reg_2));
  FDRE prevCAS_reg
       (.C(\odt_shift_reg[0][20] ),
        .CE(1'b1),
        .D(d_prevCmdAP),
        .Q(prevCAS_reg_n_0),
        .R(out));
  FDRE prevCmdAP_reg
       (.C(\odt_shift_reg[0][20] ),
        .CE(d_prevCmdAP),
        .D(winAP),
        .Q(prevCmdAP),
        .R(out));
  FDRE \prevGroup_reg[0] 
       (.C(\odt_shift_reg[0][20] ),
        .CE(1'b1),
        .D(\prevGroup_reg[0]_0 ),
        .Q(prevGroup),
        .R(out));
  LUT1 #(
    .INIT(2'h1)) 
    prevSlot2_i_1
       (.I0(mc_ADR[2]),
        .O(d_prevCmdAP));
  (* SOFT_HLUTNM = "soft_lutpair2827" *) 
  LUT5 #(
    .INIT(32'h08808008)) 
    prevSlot2_i_2
       (.I0(prevCAS_reg_n_0),
        .I1(prevSlot2_reg_0),
        .I2(prevGroup),
        .I3(win_group_cas),
        .I4(prevSlot2),
        .O(prevCAS_reg_0));
  FDRE prevSlot2_reg
       (.C(\odt_shift_reg[0][20] ),
        .CE(d_prevCmdAP),
        .D(prevCAS_reg_0),
        .Q(prevSlot2),
        .R(out));
  LUT6 #(
    .INIT(64'h7F00FF0000007F00)) 
    rdCAS_nxt_i_1
       (.I0(prevCAS_reg_n_0),
        .I1(prevSlot2),
        .I2(b2b_cas_not_allowed),
        .I3(winRead),
        .I4(per_cas_block_req),
        .I5(winWrite),
        .O(mcRdCAS));
  LUT2 #(
    .INIT(4'h9)) 
    rdCAS_nxt_i_2
       (.I0(prevGroup),
        .I1(win_group_cas),
        .O(b2b_cas_not_allowed));
  ddr4_0_ddr4_v2_2_17_cal_mc_odt u_ddr_mc_odt
       (.mc_ODT(mc_ODT),
        .\odt_shift_reg[0][18]_0 (\odt_shift_reg[0][18] ),
        .\odt_shift_reg[0][18]_1 (prevCAS_reg_0),
        .\odt_shift_reg[0][18]_2 (tranSentC),
        .\odt_shift_reg[0][20]_0 (\odt_shift_reg[0][20]_0 ),
        .\odt_shift_reg[0][20]_1 (\odt_shift_reg[0][20] ),
        .out(out),
        .winRead(winRead),
        .winWrite(winWrite));
  LUT6 #(
    .INIT(64'h7F7FFF7F00FF7FFF)) 
    \winPort[3]_i_1 
       (.I0(prevCAS_reg_n_0),
        .I1(prevSlot2),
        .I2(b2b_cas_not_allowed),
        .I3(winRead),
        .I4(per_cas_block_req),
        .I5(winWrite),
        .O(tranSentC));
  LUT2 #(
    .INIT(4'hE)) 
    \wrQ[0][8]_i_2 
       (.I0(prevCAS_reg_0),
        .I1(oe_0_mux_cal),
        .O(oe_fabric));
  LUT3 #(
    .INIT(8'h8F)) 
    \wtrl[0]_i_1 
       (.I0(tranSentC),
        .I1(winWrite),
        .I2(Q),
        .O(D));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_group" *) 
module ddr4_0_ddr4_v2_2_17_mc_group
   (ref_req_dly4,
    Q,
    cmdAP,
    wrReqR,
    refOK,
    grAccept_ns,
    actReqR,
    preReqR,
    rdReqR,
    cmdInjTxn,
    cmdRmw_reg_0,
    cmd_group_cas,
    cmdGroupP,
    per_rd_accept_0,
    \cmd_bank_cas_reg[1]_0 ,
    ref_req_dly4_reg_0,
    cmdBuf,
    \cmdBankP_reg[1]_0 ,
    \cmdCol_reg[9]_0 ,
    ref_req_dly4_reg_1,
    per_rd_accept_reg_0,
    SR,
    underfill_done_nxt,
    clrReq13_out,
    \cas_fifo_rptr_reg[0]_0 ,
    tranSentC,
    \txn_fifo_wptr_reg[0]_0 ,
    useAdr,
    \FSM_sequential_grSt_reg[0]_0 ,
    per_rd_req,
    cmd,
    row_mc_phy,
    col,
    group,
    bank,
    actReqR_reg_0,
    dBufAdr,
    refReq);
  output ref_req_dly4;
  output [19:0]Q;
  output [0:0]cmdAP;
  output wrReqR;
  output [0:0]refOK;
  output [0:0]grAccept_ns;
  output actReqR;
  output preReqR;
  output rdReqR;
  output [0:0]cmdInjTxn;
  output cmdRmw_reg_0;
  output [0:0]cmd_group_cas;
  output [0:0]cmdGroupP;
  output per_rd_accept_0;
  output [1:0]\cmd_bank_cas_reg[1]_0 ;
  output ref_req_dly4_reg_0;
  output [4:0]cmdBuf;
  output [1:0]\cmdBankP_reg[1]_0 ;
  output [6:0]\cmdCol_reg[9]_0 ;
  input ref_req_dly4_reg_1;
  input per_rd_accept_reg_0;
  input [0:0]SR;
  input underfill_done_nxt;
  input clrReq13_out;
  input [0:0]\cas_fifo_rptr_reg[0]_0 ;
  input tranSentC;
  input \txn_fifo_wptr_reg[0]_0 ;
  input useAdr;
  input [0:0]\FSM_sequential_grSt_reg[0]_0 ;
  input per_rd_req;
  input [2:0]cmd;
  input [16:0]row_mc_phy;
  input [6:0]col;
  input [0:0]group;
  input [1:0]bank;
  input [0:0]actReqR_reg_0;
  input [4:0]dBufAdr;
  input refReq;

  wire \FSM_sequential_grSt[0]_i_1_n_0 ;
  wire \FSM_sequential_grSt[0]_i_2_n_0 ;
  wire \FSM_sequential_grSt[0]_i_3__0_n_0 ;
  wire \FSM_sequential_grSt[1]_i_1_n_0 ;
  wire \FSM_sequential_grSt[1]_i_2__2_n_0 ;
  wire \FSM_sequential_grSt[1]_i_3_n_0 ;
  wire \FSM_sequential_grSt[2]_i_10_n_0 ;
  wire \FSM_sequential_grSt[2]_i_11_n_0 ;
  wire \FSM_sequential_grSt[2]_i_12_n_0 ;
  wire \FSM_sequential_grSt[2]_i_13_n_0 ;
  wire \FSM_sequential_grSt[2]_i_14_n_0 ;
  wire \FSM_sequential_grSt[2]_i_15_n_0 ;
  wire \FSM_sequential_grSt[2]_i_1_n_0 ;
  wire \FSM_sequential_grSt[2]_i_2__2_n_0 ;
  wire \FSM_sequential_grSt[2]_i_3_n_0 ;
  wire \FSM_sequential_grSt[2]_i_4__0_n_0 ;
  wire \FSM_sequential_grSt[2]_i_5_n_0 ;
  wire \FSM_sequential_grSt[2]_i_6__2_n_0 ;
  wire \FSM_sequential_grSt[2]_i_7_n_0 ;
  wire \FSM_sequential_grSt[2]_i_8__0_n_0 ;
  wire \FSM_sequential_grSt[2]_i_9_n_0 ;
  wire [0:0]\FSM_sequential_grSt_reg[0]_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_1_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_3__1_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_5__1_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_6_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_7__1_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_9_n_0 ;
  wire [19:0]Q;
  wire [0:0]SR;
  wire accept_reg_n_0;
  wire actReqR;
  wire [0:0]actReqR_reg_0;
  wire act_req_nxt;
  wire \ap_cntr[0][0][0][4]_i_2_n_0 ;
  wire \ap_cntr[0][0][0][4]_i_3_n_0 ;
  wire \ap_cntr[0][0][1][4]_i_2_n_0 ;
  wire \ap_cntr[0][0][1][4]_i_3_n_0 ;
  wire \ap_cntr[0][0][2][4]_i_2_n_0 ;
  wire \ap_cntr[0][0][3][4]_i_2_n_0 ;
  wire \ap_cntr[0][0][3][4]_i_3_n_0 ;
  wire \ap_cntr_expired_nxt[0][0][0]_2 ;
  wire \ap_cntr_expired_nxt[0][0][1]_1 ;
  wire \ap_cntr_expired_nxt[0][0][2]_251 ;
  wire \ap_cntr_expired_nxt[0][0][3]_0 ;
  wire [4:0]\ap_cntr_nxt[0][0][0]_257 ;
  wire [4:0]\ap_cntr_nxt[0][0][1]_255 ;
  wire [4:0]\ap_cntr_nxt[0][0][2]_253 ;
  wire [4:0]\ap_cntr_nxt[0][0][3]_250 ;
  wire [4:0]\ap_cntr_reg[0][0][0]_222 ;
  wire [4:0]\ap_cntr_reg[0][0][1]_220 ;
  wire [4:0]\ap_cntr_reg[0][0][2]_218 ;
  wire [4:0]\ap_cntr_reg[0][0][3]_216 ;
  wire \ap_cntr_zero[0][0][0]_i_2_n_0 ;
  wire \ap_cntr_zero[0][0][2]_i_2_n_0 ;
  wire \ap_cntr_zero[0][0][2]_i_3_n_0 ;
  wire \ap_cntr_zero[0][0][2]_i_4_n_0 ;
  wire \ap_cntr_zero_nxt[0][0][0]_256 ;
  wire \ap_cntr_zero_nxt[0][0][1]_254 ;
  wire \ap_cntr_zero_nxt[0][0][2]_252 ;
  wire \ap_cntr_zero_nxt[0][0][3]_249 ;
  wire \ap_cntr_zero_reg[0][0][0]_221 ;
  wire \ap_cntr_zero_reg[0][0][1]_219 ;
  wire \ap_cntr_zero_reg[0][0][2]_217 ;
  wire \ap_cntr_zero_reg[0][0][3]_215 ;
  wire [3:0]ap_load_value;
  wire \ap_load_value[0]_i_1_n_0 ;
  wire \ap_load_value[0]_i_2_n_0 ;
  wire \ap_load_value[1]_i_1_n_0 ;
  wire \ap_load_value[2]_i_1_n_0 ;
  wire \ap_load_value[3]_i_2_n_0 ;
  wire \ap_load_value[3]_i_3_n_0 ;
  wire [3:3]ap_load_value_nxt;
  wire [1:0]bank;
  wire \buf_fifo[0][0]_i_2__2_n_0 ;
  wire \buf_fifo[0][0]_i_3_n_0 ;
  wire \buf_fifo[0][1]_i_2__2_n_0 ;
  wire \buf_fifo[0][1]_i_3_n_0 ;
  wire \buf_fifo[0][2]_i_2__2_n_0 ;
  wire \buf_fifo[0][2]_i_3_n_0 ;
  wire \buf_fifo[0][3]_i_2__2_n_0 ;
  wire \buf_fifo[0][3]_i_3_n_0 ;
  wire \buf_fifo[0][4]_i_2__2_n_0 ;
  wire \buf_fifo[0][4]_i_3_n_0 ;
  wire [4:0]\buf_fifo_nxt[0]_259 ;
  wire [4:0]\buf_fifo_nxt[1]_262 ;
  wire [4:0]\buf_fifo_nxt[2]_261 ;
  wire [4:0]\buf_fifo_nxt[3]_260 ;
  wire [4:0]\buf_fifo_reg[0]_195 ;
  wire [4:0]\buf_fifo_reg[1]_196 ;
  wire [4:0]\buf_fifo_reg[2]_197 ;
  wire [4:0]\buf_fifo_reg[3]_198 ;
  wire [4:0]cas_dbuf_fifo_input;
  wire \cas_dbuf_fifo_nxt_reg[0]_276 ;
  wire \cas_dbuf_fifo_nxt_reg[1]_258 ;
  wire \cas_dbuf_fifo_nxt_reg[2]_275 ;
  wire \cas_dbuf_fifo_nxt_reg[3]_277 ;
  wire [4:0]\cas_dbuf_fifo_reg[0]_199 ;
  wire [4:0]\cas_dbuf_fifo_reg[1]_200 ;
  wire [4:0]\cas_dbuf_fifo_reg[2]_201 ;
  wire [4:0]\cas_dbuf_fifo_reg[3]_202 ;
  wire cas_fifo_empty_nxt;
  wire cas_fifo_empty_reg_n_0;
  wire cas_fifo_full;
  wire cas_fifo_full_nxt;
  wire [1:0]cas_fifo_rptr;
  wire \cas_fifo_rptr[1]_i_2_n_0 ;
  wire [1:0]cas_fifo_rptr_nxt;
  wire [0:0]\cas_fifo_rptr_reg[0]_0 ;
  wire [3:0]cas_fifo_valid;
  wire \cas_fifo_valid[0]_i_2_n_0 ;
  wire \cas_fifo_valid[1]_i_2_n_0 ;
  wire \cas_fifo_valid[2]_i_2_n_0 ;
  wire \cas_fifo_valid[3]_i_2_n_0 ;
  wire [3:0]cas_fifo_valid_nxt;
  wire [1:0]cas_fifo_wptr;
  wire \cas_fifo_wptr[1]_i_2_n_0 ;
  wire [1:0]cas_fifo_wptr_nxt;
  wire [47:0]\cas_pend_fifo_reg[0]_194 ;
  wire [48:48]\cas_pend_fifo_reg[0]__0 ;
  wire \cas_pend_fifo_reg_n_0_[1][11] ;
  wire \cas_pend_fifo_reg_n_0_[1][12] ;
  wire \cas_pend_fifo_reg_n_0_[1][13] ;
  wire \cas_pend_fifo_reg_n_0_[1][14] ;
  wire \cas_pend_fifo_reg_n_0_[1][15] ;
  wire \cas_pend_fifo_reg_n_0_[1][16] ;
  wire \cas_pend_fifo_reg_n_0_[1][17] ;
  wire \cas_pend_fifo_reg_n_0_[1][24] ;
  wire \cas_pend_fifo_reg_n_0_[1][25] ;
  wire \cas_pend_fifo_reg_n_0_[1][26] ;
  wire \cas_pend_fifo_reg_n_0_[1][27] ;
  wire \cas_pend_fifo_reg_n_0_[1][28] ;
  wire \cas_pend_fifo_reg_n_0_[1][29] ;
  wire \cas_pend_fifo_reg_n_0_[1][2] ;
  wire \cas_pend_fifo_reg_n_0_[1][30] ;
  wire \cas_pend_fifo_reg_n_0_[1][31] ;
  wire \cas_pend_fifo_reg_n_0_[1][32] ;
  wire \cas_pend_fifo_reg_n_0_[1][33] ;
  wire \cas_pend_fifo_reg_n_0_[1][34] ;
  wire \cas_pend_fifo_reg_n_0_[1][35] ;
  wire \cas_pend_fifo_reg_n_0_[1][36] ;
  wire \cas_pend_fifo_reg_n_0_[1][37] ;
  wire \cas_pend_fifo_reg_n_0_[1][38] ;
  wire \cas_pend_fifo_reg_n_0_[1][39] ;
  wire \cas_pend_fifo_reg_n_0_[1][40] ;
  wire \cas_pend_fifo_reg_n_0_[1][44] ;
  wire \cas_pend_fifo_reg_n_0_[1][45] ;
  wire \cas_pend_fifo_reg_n_0_[1][46] ;
  wire \cas_pend_fifo_reg_n_0_[1][47] ;
  wire \cas_pend_fifo_reg_n_0_[1][48] ;
  wire \cas_pend_fifo_reg_n_0_[2][11] ;
  wire \cas_pend_fifo_reg_n_0_[2][12] ;
  wire \cas_pend_fifo_reg_n_0_[2][13] ;
  wire \cas_pend_fifo_reg_n_0_[2][14] ;
  wire \cas_pend_fifo_reg_n_0_[2][15] ;
  wire \cas_pend_fifo_reg_n_0_[2][16] ;
  wire \cas_pend_fifo_reg_n_0_[2][17] ;
  wire \cas_pend_fifo_reg_n_0_[2][24] ;
  wire \cas_pend_fifo_reg_n_0_[2][25] ;
  wire \cas_pend_fifo_reg_n_0_[2][26] ;
  wire \cas_pend_fifo_reg_n_0_[2][27] ;
  wire \cas_pend_fifo_reg_n_0_[2][28] ;
  wire \cas_pend_fifo_reg_n_0_[2][29] ;
  wire \cas_pend_fifo_reg_n_0_[2][2] ;
  wire \cas_pend_fifo_reg_n_0_[2][30] ;
  wire \cas_pend_fifo_reg_n_0_[2][31] ;
  wire \cas_pend_fifo_reg_n_0_[2][32] ;
  wire \cas_pend_fifo_reg_n_0_[2][33] ;
  wire \cas_pend_fifo_reg_n_0_[2][34] ;
  wire \cas_pend_fifo_reg_n_0_[2][35] ;
  wire \cas_pend_fifo_reg_n_0_[2][36] ;
  wire \cas_pend_fifo_reg_n_0_[2][37] ;
  wire \cas_pend_fifo_reg_n_0_[2][38] ;
  wire \cas_pend_fifo_reg_n_0_[2][39] ;
  wire \cas_pend_fifo_reg_n_0_[2][40] ;
  wire \cas_pend_fifo_reg_n_0_[2][44] ;
  wire \cas_pend_fifo_reg_n_0_[2][45] ;
  wire \cas_pend_fifo_reg_n_0_[2][46] ;
  wire \cas_pend_fifo_reg_n_0_[2][47] ;
  wire \cas_pend_fifo_reg_n_0_[2][48] ;
  wire \cas_pend_fifo_reg_n_0_[3][11] ;
  wire \cas_pend_fifo_reg_n_0_[3][12] ;
  wire \cas_pend_fifo_reg_n_0_[3][13] ;
  wire \cas_pend_fifo_reg_n_0_[3][14] ;
  wire \cas_pend_fifo_reg_n_0_[3][15] ;
  wire \cas_pend_fifo_reg_n_0_[3][16] ;
  wire \cas_pend_fifo_reg_n_0_[3][17] ;
  wire \cas_pend_fifo_reg_n_0_[3][24] ;
  wire \cas_pend_fifo_reg_n_0_[3][25] ;
  wire \cas_pend_fifo_reg_n_0_[3][26] ;
  wire \cas_pend_fifo_reg_n_0_[3][27] ;
  wire \cas_pend_fifo_reg_n_0_[3][28] ;
  wire \cas_pend_fifo_reg_n_0_[3][29] ;
  wire \cas_pend_fifo_reg_n_0_[3][2] ;
  wire \cas_pend_fifo_reg_n_0_[3][30] ;
  wire \cas_pend_fifo_reg_n_0_[3][31] ;
  wire \cas_pend_fifo_reg_n_0_[3][32] ;
  wire \cas_pend_fifo_reg_n_0_[3][33] ;
  wire \cas_pend_fifo_reg_n_0_[3][34] ;
  wire \cas_pend_fifo_reg_n_0_[3][35] ;
  wire \cas_pend_fifo_reg_n_0_[3][36] ;
  wire \cas_pend_fifo_reg_n_0_[3][37] ;
  wire \cas_pend_fifo_reg_n_0_[3][38] ;
  wire \cas_pend_fifo_reg_n_0_[3][39] ;
  wire \cas_pend_fifo_reg_n_0_[3][40] ;
  wire \cas_pend_fifo_reg_n_0_[3][44] ;
  wire \cas_pend_fifo_reg_n_0_[3][45] ;
  wire \cas_pend_fifo_reg_n_0_[3][46] ;
  wire \cas_pend_fifo_reg_n_0_[3][47] ;
  wire \cas_pend_fifo_reg_n_0_[3][48] ;
  wire [9:3]cas_pend_output_col;
  wire [16:0]cas_pend_output_row;
  wire clrReq13_out;
  wire [2:0]cmd;
  wire [0:0]cmdAP;
  wire cmdAP_i_2_n_0;
  wire [1:0]\cmdBankP_reg[1]_0 ;
  wire [4:0]cmdBuf;
  wire \cmdCol[3]_i_2_n_0 ;
  wire \cmdCol[4]_i_2_n_0 ;
  wire \cmdCol[5]_i_2_n_0 ;
  wire \cmdCol[6]_i_2_n_0 ;
  wire \cmdCol[7]_i_2_n_0 ;
  wire \cmdCol[8]_i_2_n_0 ;
  wire \cmdCol[9]_i_2_n_0 ;
  wire [6:0]\cmdCol_reg[9]_0 ;
  wire [0:0]cmdGroupP;
  wire [0:0]cmdInjTxn;
  wire cmdInjTxn_i_2_n_0;
  wire cmdRmw_i_2_n_0;
  wire cmdRmw_reg_0;
  wire cmd_ap_nxt;
  wire \cmd_bank_cas[0]_i_1_n_0 ;
  wire \cmd_bank_cas[0]_i_2_n_0 ;
  wire \cmd_bank_cas[1]_i_1_n_0 ;
  wire \cmd_bank_cas[1]_i_2_n_0 ;
  wire [1:0]\cmd_bank_cas_reg[1]_0 ;
  wire [4:0]cmd_buf_nxt;
  wire [0:0]cmd_group_cas;
  wire \cmd_group_cas[0]_i_2_n_0 ;
  wire [0:0]cmd_group_cas_nxt;
  wire cmd_inj_txn_nxt;
  wire \cmd_row_cas[0]_i_2_n_0 ;
  wire \cmd_row_cas[10]_i_2_n_0 ;
  wire \cmd_row_cas[11]_i_2_n_0 ;
  wire \cmd_row_cas[12]_i_2_n_0 ;
  wire \cmd_row_cas[13]_i_2_n_0 ;
  wire \cmd_row_cas[14]_i_2_n_0 ;
  wire \cmd_row_cas[15]_i_2_n_0 ;
  wire \cmd_row_cas[16]_i_2_n_0 ;
  wire \cmd_row_cas[1]_i_2_n_0 ;
  wire \cmd_row_cas[2]_i_2_n_0 ;
  wire \cmd_row_cas[3]_i_2_n_0 ;
  wire \cmd_row_cas[4]_i_2_n_0 ;
  wire \cmd_row_cas[5]_i_2_n_0 ;
  wire \cmd_row_cas[6]_i_2_n_0 ;
  wire \cmd_row_cas[7]_i_2_n_0 ;
  wire \cmd_row_cas[8]_i_2_n_0 ;
  wire \cmd_row_cas[9]_i_2_n_0 ;
  wire [6:0]col;
  wire [4:0]dBufAdr;
  wire [18:2]data0;
  wire [0:0]grAccept_ns;
  wire [2:0]grSt;
  wire [2:0]gr_cas_state;
  wire [2:0]gr_cas_state_nxt;
  wire [0:0]group;
  wire i__carry_i_10_n_0;
  wire i__carry_i_11_n_0;
  wire i__carry_i_12_n_0;
  wire i__carry_i_13_n_0;
  wire i__carry_i_14_n_0;
  wire i__carry_i_15_n_0;
  wire i__carry_i_16_n_0;
  wire i__carry_i_17_n_0;
  wire i__carry_i_18_n_0;
  wire i__carry_i_19_n_0;
  wire i__carry_i_1_n_0;
  wire i__carry_i_20_n_0;
  wire i__carry_i_21_n_0;
  wire i__carry_i_22_n_0;
  wire i__carry_i_23_n_0;
  wire i__carry_i_2_n_0;
  wire i__carry_i_3_n_0;
  wire i__carry_i_4_n_0;
  wire i__carry_i_5_n_0;
  wire i__carry_i_6_n_0;
  wire i__carry_i_7_n_0;
  wire i__carry_i_8_n_0;
  wire i__carry_i_9_n_0;
  wire issue_cas3215_in;
  wire \issue_cas3_inferred__0/i__carry_n_3 ;
  wire \issue_cas3_inferred__0/i__carry_n_4 ;
  wire \issue_cas3_inferred__0/i__carry_n_5 ;
  wire \issue_cas3_inferred__0/i__carry_n_6 ;
  wire \issue_cas3_inferred__0/i__carry_n_7 ;
  wire [1:0]p_0_in0_in__0;
  wire [1:0]p_0_in2_in;
  wire [1:0]p_0_in4_in;
  wire p_219_in;
  wire \pageInfo[0][0][0][0]_i_1_n_0 ;
  wire \pageInfo[0][0][0][0]_i_2_n_0 ;
  wire \pageInfo[0][0][0][0]_i_3_n_0 ;
  wire \pageInfo[0][0][0][10]_i_1_n_0 ;
  wire \pageInfo[0][0][0][11]_i_1_n_0 ;
  wire \pageInfo[0][0][0][12]_i_1_n_0 ;
  wire \pageInfo[0][0][0][13]_i_1_n_0 ;
  wire \pageInfo[0][0][0][14]_i_1_n_0 ;
  wire \pageInfo[0][0][0][15]_i_1_n_0 ;
  wire \pageInfo[0][0][0][16]_i_1_n_0 ;
  wire \pageInfo[0][0][0][17]_i_1_n_0 ;
  wire \pageInfo[0][0][0][18]_i_1_n_0 ;
  wire \pageInfo[0][0][0][18]_i_2_n_0 ;
  wire \pageInfo[0][0][0][1]_i_1_n_0 ;
  wire \pageInfo[0][0][0][2]_i_1_n_0 ;
  wire \pageInfo[0][0][0][3]_i_1_n_0 ;
  wire \pageInfo[0][0][0][4]_i_1_n_0 ;
  wire \pageInfo[0][0][0][5]_i_1_n_0 ;
  wire \pageInfo[0][0][0][6]_i_1_n_0 ;
  wire \pageInfo[0][0][0][7]_i_1_n_0 ;
  wire \pageInfo[0][0][0][8]_i_1_n_0 ;
  wire \pageInfo[0][0][0][9]_i_1_n_0 ;
  wire \pageInfo[0][0][1][0]_i_1_n_0 ;
  wire \pageInfo[0][0][1][0]_i_2_n_0 ;
  wire \pageInfo[0][0][1][0]_i_3_n_0 ;
  wire \pageInfo[0][0][1][10]_i_1_n_0 ;
  wire \pageInfo[0][0][1][11]_i_1_n_0 ;
  wire \pageInfo[0][0][1][12]_i_1_n_0 ;
  wire \pageInfo[0][0][1][13]_i_1_n_0 ;
  wire \pageInfo[0][0][1][14]_i_1_n_0 ;
  wire \pageInfo[0][0][1][15]_i_1_n_0 ;
  wire \pageInfo[0][0][1][16]_i_1_n_0 ;
  wire \pageInfo[0][0][1][17]_i_1_n_0 ;
  wire \pageInfo[0][0][1][18]_i_1_n_0 ;
  wire \pageInfo[0][0][1][18]_i_2_n_0 ;
  wire \pageInfo[0][0][1][1]_i_1_n_0 ;
  wire \pageInfo[0][0][1][2]_i_1_n_0 ;
  wire \pageInfo[0][0][1][3]_i_1_n_0 ;
  wire \pageInfo[0][0][1][4]_i_1_n_0 ;
  wire \pageInfo[0][0][1][5]_i_1_n_0 ;
  wire \pageInfo[0][0][1][6]_i_1_n_0 ;
  wire \pageInfo[0][0][1][7]_i_1_n_0 ;
  wire \pageInfo[0][0][1][8]_i_1_n_0 ;
  wire \pageInfo[0][0][1][9]_i_1_n_0 ;
  wire \pageInfo[0][0][2][0]_i_1_n_0 ;
  wire \pageInfo[0][0][2][0]_i_2_n_0 ;
  wire \pageInfo[0][0][2][0]_i_3_n_0 ;
  wire \pageInfo[0][0][2][10]_i_1_n_0 ;
  wire \pageInfo[0][0][2][11]_i_1_n_0 ;
  wire \pageInfo[0][0][2][12]_i_1_n_0 ;
  wire \pageInfo[0][0][2][13]_i_1_n_0 ;
  wire \pageInfo[0][0][2][14]_i_1_n_0 ;
  wire \pageInfo[0][0][2][15]_i_1_n_0 ;
  wire \pageInfo[0][0][2][16]_i_1_n_0 ;
  wire \pageInfo[0][0][2][17]_i_1_n_0 ;
  wire \pageInfo[0][0][2][18]_i_1_n_0 ;
  wire \pageInfo[0][0][2][18]_i_2_n_0 ;
  wire \pageInfo[0][0][2][1]_i_1_n_0 ;
  wire \pageInfo[0][0][2][2]_i_1_n_0 ;
  wire \pageInfo[0][0][2][3]_i_1_n_0 ;
  wire \pageInfo[0][0][2][4]_i_1_n_0 ;
  wire \pageInfo[0][0][2][5]_i_1_n_0 ;
  wire \pageInfo[0][0][2][6]_i_1_n_0 ;
  wire \pageInfo[0][0][2][7]_i_1_n_0 ;
  wire \pageInfo[0][0][2][8]_i_1_n_0 ;
  wire \pageInfo[0][0][2][9]_i_1_n_0 ;
  wire \pageInfo[0][0][3][0]_i_1_n_0 ;
  wire \pageInfo[0][0][3][0]_i_2_n_0 ;
  wire \pageInfo[0][0][3][10]_i_1_n_0 ;
  wire \pageInfo[0][0][3][11]_i_1_n_0 ;
  wire \pageInfo[0][0][3][12]_i_1_n_0 ;
  wire \pageInfo[0][0][3][13]_i_1_n_0 ;
  wire \pageInfo[0][0][3][14]_i_1_n_0 ;
  wire \pageInfo[0][0][3][15]_i_1_n_0 ;
  wire \pageInfo[0][0][3][16]_i_1_n_0 ;
  wire \pageInfo[0][0][3][17]_i_1_n_0 ;
  wire \pageInfo[0][0][3][18]_i_1_n_0 ;
  wire \pageInfo[0][0][3][18]_i_2_n_0 ;
  wire \pageInfo[0][0][3][18]_i_3_n_0 ;
  wire \pageInfo[0][0][3][1]_i_1_n_0 ;
  wire \pageInfo[0][0][3][2]_i_1_n_0 ;
  wire \pageInfo[0][0][3][3]_i_1_n_0 ;
  wire \pageInfo[0][0][3][4]_i_1_n_0 ;
  wire \pageInfo[0][0][3][5]_i_1_n_0 ;
  wire \pageInfo[0][0][3][6]_i_1_n_0 ;
  wire \pageInfo[0][0][3][7]_i_1_n_0 ;
  wire \pageInfo[0][0][3][8]_i_1_n_0 ;
  wire \pageInfo[0][0][3][9]_i_1_n_0 ;
  wire [18:0]\pageInfo_reg[0][0][0]_226 ;
  wire [18:0]\pageInfo_reg[0][0][1]_225 ;
  wire [18:0]\pageInfo_reg[0][0][2]_224 ;
  wire [18:0]\pageInfo_reg[0][0][3]_223 ;
  wire per_rd_accept_0;
  wire per_rd_accept_reg_0;
  wire per_rd_req;
  wire \periodic_read_address[40]_i_2_n_0 ;
  wire \periodic_read_address[40]_i_3_n_0 ;
  wire \periodic_read_address[44]_i_1_n_0 ;
  wire \periodic_read_address_reg_n_0_[0] ;
  wire \periodic_read_address_reg_n_0_[11] ;
  wire \periodic_read_address_reg_n_0_[12] ;
  wire \periodic_read_address_reg_n_0_[13] ;
  wire \periodic_read_address_reg_n_0_[14] ;
  wire \periodic_read_address_reg_n_0_[15] ;
  wire \periodic_read_address_reg_n_0_[16] ;
  wire \periodic_read_address_reg_n_0_[17] ;
  wire \periodic_read_address_reg_n_0_[1] ;
  wire \periodic_read_address_reg_n_0_[24] ;
  wire \periodic_read_address_reg_n_0_[25] ;
  wire \periodic_read_address_reg_n_0_[26] ;
  wire \periodic_read_address_reg_n_0_[27] ;
  wire \periodic_read_address_reg_n_0_[28] ;
  wire \periodic_read_address_reg_n_0_[29] ;
  wire \periodic_read_address_reg_n_0_[2] ;
  wire \periodic_read_address_reg_n_0_[30] ;
  wire \periodic_read_address_reg_n_0_[31] ;
  wire \periodic_read_address_reg_n_0_[32] ;
  wire \periodic_read_address_reg_n_0_[33] ;
  wire \periodic_read_address_reg_n_0_[34] ;
  wire \periodic_read_address_reg_n_0_[35] ;
  wire \periodic_read_address_reg_n_0_[36] ;
  wire \periodic_read_address_reg_n_0_[37] ;
  wire \periodic_read_address_reg_n_0_[38] ;
  wire \periodic_read_address_reg_n_0_[39] ;
  wire \periodic_read_address_reg_n_0_[40] ;
  wire \periodic_read_address_reg_n_0_[44] ;
  wire periodic_read_block;
  wire periodic_read_block_dly1;
  wire periodic_read_block_dly1_nxt;
  wire periodic_read_block_dly2;
  wire periodic_read_block_dly2_nxt;
  wire periodic_read_block_dly3;
  wire periodic_read_block_dly3_nxt;
  wire periodic_read_block_nxt;
  wire periodic_read_or_ref_block;
  wire periodic_read_or_ref_block_nxt;
  wire periodic_read_push_safe;
  wire preReqR;
  wire pre_req_nxt;
  wire rdReqR;
  wire rdReqR_i_2_n_0;
  wire rd_req_nxt;
  wire rd_rmw_nxt;
  wire [0:0]refOK;
  wire refReq;
  wire ref_ok_nxt;
  wire ref_req_dly3_reg_srl2_n_0;
  wire ref_req_dly4;
  wire ref_req_dly4_reg_0;
  wire ref_req_dly4_reg_1;
  wire [16:0]row_mc_phy;
  (* RTL_KEEP = "true" *) wire rst_r1;
  wire [1:1]sel0__10;
  wire [1:1]sel0__14;
  wire [1:1]sel0__2;
  wire [1:1]sel0__6;
  wire select_periodic_read;
  wire select_periodic_read_nxt;
  wire set_act_req;
  wire set_pre_req;
  wire tranSentC;
  wire [2:0]\tras_cntr_rb_nxt[0][0][0]_269 ;
  wire [2:0]\tras_cntr_rb_nxt[0][0][1]_266 ;
  wire [2:0]\tras_cntr_rb_nxt[0][0][2]_263 ;
  wire [2:0]\tras_cntr_rb_nxt[0][0][3]_272 ;
  wire [2:0]\tras_cntr_rb_reg[0][0][0]_211 ;
  wire [2:0]\tras_cntr_rb_reg[0][0][1]_212 ;
  wire [2:0]\tras_cntr_rb_reg[0][0][2]_213 ;
  wire [2:0]\tras_cntr_rb_reg[0][0][3]_214 ;
  wire \trcd_cntr[0][0][0][2]_i_2_n_0 ;
  wire \trcd_cntr[0][0][1][2]_i_2_n_0 ;
  wire \trcd_cntr[0][0][2][2]_i_2_n_0 ;
  wire \trcd_cntr[0][0][3][2]_i_2_n_0 ;
  wire \trcd_cntr_is_zero[0][0][0]_i_2_n_0 ;
  wire \trcd_cntr_is_zero[0][0][1]_i_2_n_0 ;
  wire \trcd_cntr_is_zero[0][0][2]_i_2_n_0 ;
  wire \trcd_cntr_is_zero[0][0][3]_i_2_n_0 ;
  wire \trcd_cntr_is_zero_nxt[0][0][0]_271 ;
  wire \trcd_cntr_is_zero_nxt[0][0][1]_268 ;
  wire \trcd_cntr_is_zero_nxt[0][0][2]_265 ;
  wire \trcd_cntr_is_zero_nxt[0][0][3]_274 ;
  wire \trcd_cntr_is_zero_reg[0][0][0]_203 ;
  wire \trcd_cntr_is_zero_reg[0][0][1]_205 ;
  wire \trcd_cntr_is_zero_reg[0][0][2]_207 ;
  wire \trcd_cntr_is_zero_reg[0][0][3]_209 ;
  wire [3:0]\trcd_cntr_nxt[0][0][0]_270 ;
  wire [3:0]\trcd_cntr_nxt[0][0][1]_267 ;
  wire [3:0]\trcd_cntr_nxt[0][0][2]_264 ;
  wire [3:0]\trcd_cntr_nxt[0][0][3]_273 ;
  wire [3:0]\trcd_cntr_reg[0][0][0]_204 ;
  wire [3:0]\trcd_cntr_reg[0][0][1]_206 ;
  wire [3:0]\trcd_cntr_reg[0][0][2]_208 ;
  wire [3:0]\trcd_cntr_reg[0][0][3]_210 ;
  wire [4:0]trp_cntr;
  wire \trp_cntr[0]_i_1_n_0 ;
  wire \trp_cntr[0]_i_2_n_0 ;
  wire \trp_cntr[1]_i_1_n_0 ;
  wire \trp_cntr[1]_i_2_n_0 ;
  wire \trp_cntr[1]_i_3_n_0 ;
  wire \trp_cntr[2]_i_1_n_0 ;
  wire \trp_cntr[2]_i_2_n_0 ;
  wire \trp_cntr[2]_i_3_n_0 ;
  wire \trp_cntr[3]_i_1_n_0 ;
  wire \trp_cntr[3]_i_2_n_0 ;
  wire \trp_cntr[3]_i_3_n_0 ;
  wire \trp_cntr[4]_i_1_n_0 ;
  wire \trp_cntr[4]_i_2_n_0 ;
  wire \trp_cntr[4]_i_3_n_0 ;
  wire trp_cntr_is_zero;
  wire trp_cntr_is_zero_nxt;
  wire \txn_fifo[0][48]_i_2_n_0 ;
  wire \txn_fifo[1][48]_i_2_n_0 ;
  wire \txn_fifo[2][48]_i_2_n_0 ;
  wire \txn_fifo[3][48]_i_2_n_0 ;
  wire txn_fifo_empty_i_2__2_n_0;
  wire txn_fifo_empty_nxt;
  wire txn_fifo_empty_reg_n_0;
  wire txn_fifo_full;
  wire txn_fifo_full_nxt;
  wire [48:0]\txn_fifo_nxt[0]_248 ;
  wire [48:0]\txn_fifo_nxt[1]_247 ;
  wire [48:0]\txn_fifo_nxt[2]_246 ;
  wire [48:0]\txn_fifo_nxt[3]_245 ;
  wire \txn_fifo_output[0]_i_2_n_0 ;
  wire \txn_fifo_output[0]_i_3_n_0 ;
  wire \txn_fifo_output[11]_i_2_n_0 ;
  wire \txn_fifo_output[11]_i_3_n_0 ;
  wire \txn_fifo_output[12]_i_2_n_0 ;
  wire \txn_fifo_output[12]_i_3_n_0 ;
  wire \txn_fifo_output[13]_i_2_n_0 ;
  wire \txn_fifo_output[13]_i_3_n_0 ;
  wire \txn_fifo_output[14]_i_2_n_0 ;
  wire \txn_fifo_output[14]_i_3_n_0 ;
  wire \txn_fifo_output[15]_i_2_n_0 ;
  wire \txn_fifo_output[15]_i_3_n_0 ;
  wire \txn_fifo_output[16]_i_2_n_0 ;
  wire \txn_fifo_output[16]_i_3_n_0 ;
  wire \txn_fifo_output[17]_i_2_n_0 ;
  wire \txn_fifo_output[17]_i_3_n_0 ;
  wire \txn_fifo_output[1]_i_2_n_0 ;
  wire \txn_fifo_output[1]_i_3_n_0 ;
  wire \txn_fifo_output[24]_i_2_n_0 ;
  wire \txn_fifo_output[24]_i_3_n_0 ;
  wire \txn_fifo_output[25]_i_2_n_0 ;
  wire \txn_fifo_output[25]_i_3_n_0 ;
  wire \txn_fifo_output[26]_i_2_n_0 ;
  wire \txn_fifo_output[26]_i_3_n_0 ;
  wire \txn_fifo_output[27]_i_2_n_0 ;
  wire \txn_fifo_output[27]_i_3_n_0 ;
  wire \txn_fifo_output[28]_i_2_n_0 ;
  wire \txn_fifo_output[28]_i_3_n_0 ;
  wire \txn_fifo_output[29]_i_2_n_0 ;
  wire \txn_fifo_output[29]_i_3_n_0 ;
  wire \txn_fifo_output[2]_i_2_n_0 ;
  wire \txn_fifo_output[2]_i_3_n_0 ;
  wire \txn_fifo_output[30]_i_2_n_0 ;
  wire \txn_fifo_output[30]_i_3_n_0 ;
  wire \txn_fifo_output[31]_i_2_n_0 ;
  wire \txn_fifo_output[31]_i_3_n_0 ;
  wire \txn_fifo_output[32]_i_2_n_0 ;
  wire \txn_fifo_output[32]_i_3_n_0 ;
  wire \txn_fifo_output[33]_i_2_n_0 ;
  wire \txn_fifo_output[33]_i_3_n_0 ;
  wire \txn_fifo_output[34]_i_2_n_0 ;
  wire \txn_fifo_output[34]_i_3_n_0 ;
  wire \txn_fifo_output[35]_i_2_n_0 ;
  wire \txn_fifo_output[35]_i_3_n_0 ;
  wire \txn_fifo_output[36]_i_2_n_0 ;
  wire \txn_fifo_output[36]_i_3_n_0 ;
  wire \txn_fifo_output[37]_i_2_n_0 ;
  wire \txn_fifo_output[37]_i_3_n_0 ;
  wire \txn_fifo_output[38]_i_2_n_0 ;
  wire \txn_fifo_output[38]_i_3_n_0 ;
  wire \txn_fifo_output[39]_i_2_n_0 ;
  wire \txn_fifo_output[39]_i_3_n_0 ;
  wire \txn_fifo_output[40]_i_2_n_0 ;
  wire \txn_fifo_output[40]_i_3_n_0 ;
  wire \txn_fifo_output[44]_i_2_n_0 ;
  wire \txn_fifo_output[44]_i_3_n_0 ;
  wire \txn_fifo_output[45]_i_2_n_0 ;
  wire \txn_fifo_output[45]_i_3_n_0 ;
  wire \txn_fifo_output[46]_i_2_n_0 ;
  wire \txn_fifo_output[46]_i_3_n_0 ;
  wire \txn_fifo_output[47]_i_2_n_0 ;
  wire \txn_fifo_output[47]_i_3_n_0 ;
  wire \txn_fifo_output[48]_i_2_n_0 ;
  wire \txn_fifo_output[48]_i_3_n_0 ;
  wire \txn_fifo_output[48]_i_4_n_0 ;
  wire \txn_fifo_output[48]_i_5_n_0 ;
  wire [48:0]txn_fifo_output_nxt;
  wire \txn_fifo_output_reg_n_0_[11] ;
  wire \txn_fifo_output_reg_n_0_[12] ;
  wire \txn_fifo_output_reg_n_0_[13] ;
  wire \txn_fifo_output_reg_n_0_[14] ;
  wire \txn_fifo_output_reg_n_0_[15] ;
  wire \txn_fifo_output_reg_n_0_[16] ;
  wire \txn_fifo_output_reg_n_0_[17] ;
  wire \txn_fifo_output_reg_n_0_[44] ;
  wire \txn_fifo_output_reg_n_0_[45] ;
  wire \txn_fifo_output_reg_n_0_[46] ;
  wire \txn_fifo_output_reg_n_0_[47] ;
  wire \txn_fifo_output_reg_n_0_[48] ;
  wire [48:0]\txn_fifo_reg[0]_190 ;
  wire [48:0]\txn_fifo_reg[1]_191 ;
  wire [48:0]\txn_fifo_reg[2]_192 ;
  wire [48:0]\txn_fifo_reg[3]_193 ;
  wire [1:0]txn_fifo_rptr;
  wire \txn_fifo_rptr[1]_i_2_n_0 ;
  wire [1:0]txn_fifo_rptr_nxt;
  wire [1:0]txn_fifo_wptr;
  wire \txn_fifo_wptr[0]_i_1__2_n_0 ;
  wire [1:1]txn_fifo_wptr_nxt;
  wire \txn_fifo_wptr_reg[0]_0 ;
  wire underfill_done;
  wire underfill_done_nxt;
  wire useAdr;
  wire wrReqR;
  wire wrReqR_i_1_n_0;
  wire wrReqR_i_2_n_0;
  wire wrReqR_i_3_n_0;
  wire wrReqR_i_4_n_0;
  wire wrReqR_i_5_n_0;
  wire wrReqR_i_6_n_0;
  wire wrReqR_i_7_n_0;
  wire [7:6]\NLW_issue_cas3_inferred__0/i__carry_CO_UNCONNECTED ;
  wire [7:0]\NLW_issue_cas3_inferred__0/i__carry_O_UNCONNECTED ;

  LUT5 #(
    .INIT(32'h0E0E000E)) 
    \FSM_sequential_grSt[0]_i_1 
       (.I0(\FSM_sequential_grSt[0]_i_2_n_0 ),
        .I1(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I2(\FSM_sequential_grSt[0]_i_3__0_n_0 ),
        .I3(grSt[2]),
        .I4(grSt[1]),
        .O(\FSM_sequential_grSt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0FFFFFFF08FAFAFA)) 
    \FSM_sequential_grSt[0]_i_2 
       (.I0(issue_cas3215_in),
        .I1(\periodic_read_address[40]_i_3_n_0 ),
        .I2(\FSM_sequential_grSt[2]_i_5_n_0 ),
        .I3(ref_req_dly4),
        .I4(txn_fifo_empty_reg_n_0),
        .I5(\FSM_sequential_grSt[2]_i_4__0_n_0 ),
        .O(\FSM_sequential_grSt[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h8088)) 
    \FSM_sequential_grSt[0]_i_3__0 
       (.I0(grSt[1]),
        .I1(grSt[0]),
        .I2(cas_fifo_full),
        .I3(actReqR_reg_0),
        .O(\FSM_sequential_grSt[0]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h0A200A200A20AAAA)) 
    \FSM_sequential_grSt[1]_i_1 
       (.I0(\FSM_sequential_grSt[1]_i_2__2_n_0 ),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .I4(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I5(\FSM_sequential_grSt[2]_i_7_n_0 ),
        .O(\FSM_sequential_grSt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF222FFFFFFFF)) 
    \FSM_sequential_grSt[1]_i_2__2 
       (.I0(\FSM_sequential_grSt[2]_i_4__0_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_5_n_0 ),
        .I2(txn_fifo_empty_reg_n_0),
        .I3(ref_req_dly4),
        .I4(grSt[2]),
        .I5(grSt[0]),
        .O(\FSM_sequential_grSt[1]_i_2__2_n_0 ));
  LUT4 #(
    .INIT(16'hDFDD)) 
    \FSM_sequential_grSt[1]_i_3 
       (.I0(grSt[0]),
        .I1(grSt[1]),
        .I2(\FSM_sequential_grSt[2]_i_14_n_0 ),
        .I3(\FSM_sequential_grSt[2]_i_15_n_0 ),
        .O(\FSM_sequential_grSt[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF55C444C4)) 
    \FSM_sequential_grSt[2]_i_1 
       (.I0(grSt[1]),
        .I1(grSt[0]),
        .I2(actReqR_reg_0),
        .I3(grSt[2]),
        .I4(\FSM_sequential_grSt_reg[0]_0 ),
        .I5(\FSM_sequential_grSt[2]_i_3_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2AAA)) 
    \FSM_sequential_grSt[2]_i_10 
       (.I0(txn_fifo_empty_reg_n_0),
        .I1(useAdr),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(accept_reg_n_0),
        .O(\FSM_sequential_grSt[2]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'h6FF6FFFF)) 
    \FSM_sequential_grSt[2]_i_11 
       (.I0(Q[1]),
        .I1(p_0_in4_in[1]),
        .I2(Q[0]),
        .I3(p_0_in4_in[0]),
        .I4(cas_fifo_valid[3]),
        .O(\FSM_sequential_grSt[2]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'h6FF6FFFF)) 
    \FSM_sequential_grSt[2]_i_12 
       (.I0(Q[1]),
        .I1(p_0_in0_in__0[1]),
        .I2(Q[0]),
        .I3(p_0_in0_in__0[0]),
        .I4(cas_fifo_valid[1]),
        .O(\FSM_sequential_grSt[2]_i_12_n_0 ));
  LUT5 #(
    .INIT(32'h6FF6FFFF)) 
    \FSM_sequential_grSt[2]_i_13 
       (.I0(\cas_pend_fifo_reg[0]_194 [1]),
        .I1(Q[1]),
        .I2(\cas_pend_fifo_reg[0]_194 [0]),
        .I3(Q[0]),
        .I4(cas_fifo_valid[0]),
        .O(\FSM_sequential_grSt[2]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hFFEFFFEFFFFFFFEF)) 
    \FSM_sequential_grSt[2]_i_14 
       (.I0(\FSM_sequential_grSt[2]_i_4__0_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_10_n_0 ),
        .I2(issue_cas3215_in),
        .I3(cas_fifo_full),
        .I4(\cas_pend_fifo_reg[0]_194 [47]),
        .I5(\FSM_sequential_grSt[2]_i_13_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hDD0DDD0D0000DD0D)) 
    \FSM_sequential_grSt[2]_i_15 
       (.I0(\cas_pend_fifo_reg_n_0_[3][47] ),
        .I1(\FSM_sequential_grSt[2]_i_11_n_0 ),
        .I2(\cas_pend_fifo_reg_n_0_[2][47] ),
        .I3(\FSM_sequential_grSt[2]_i_9_n_0 ),
        .I4(\cas_pend_fifo_reg_n_0_[1][47] ),
        .I5(\FSM_sequential_grSt[2]_i_12_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hF0D0F000F000F000)) 
    \FSM_sequential_grSt[2]_i_2__2 
       (.I0(\FSM_sequential_grSt[2]_i_4__0_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_5_n_0 ),
        .I2(\FSM_sequential_grSt[2]_i_6__2_n_0 ),
        .I3(\FSM_sequential_grSt[2]_i_7_n_0 ),
        .I4(ref_req_dly4),
        .I5(txn_fifo_empty_reg_n_0),
        .O(\FSM_sequential_grSt[2]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hAAABAAABBBABAAAB)) 
    \FSM_sequential_grSt[2]_i_3 
       (.I0(\FSM_sequential_grSt[2]_i_8__0_n_0 ),
        .I1(grSt[2]),
        .I2(cas_fifo_full),
        .I3(grSt[1]),
        .I4(trp_cntr_is_zero),
        .I5(grSt[0]),
        .O(\FSM_sequential_grSt[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h30053F0530F53FF5)) 
    \FSM_sequential_grSt[2]_i_4__0 
       (.I0(\pageInfo_reg[0][0][0]_226 [0]),
        .I1(\pageInfo_reg[0][0][3]_223 [0]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(\pageInfo_reg[0][0][2]_224 [0]),
        .I5(\pageInfo_reg[0][0][1]_225 [0]),
        .O(\FSM_sequential_grSt[2]_i_4__0_n_0 ));
  LUT5 #(
    .INIT(32'hDFFFFFFF)) 
    \FSM_sequential_grSt[2]_i_5 
       (.I0(\FSM_sequential_grSt[2]_i_9_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_10_n_0 ),
        .I2(\FSM_sequential_grSt[2]_i_11_n_0 ),
        .I3(\FSM_sequential_grSt[2]_i_12_n_0 ),
        .I4(\FSM_sequential_grSt[2]_i_13_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h00002022)) 
    \FSM_sequential_grSt[2]_i_6__2 
       (.I0(grSt[0]),
        .I1(grSt[1]),
        .I2(\FSM_sequential_grSt[2]_i_14_n_0 ),
        .I3(\FSM_sequential_grSt[2]_i_15_n_0 ),
        .I4(grSt[2]),
        .O(\FSM_sequential_grSt[2]_i_6__2_n_0 ));
  LUT4 #(
    .INIT(16'h00AB)) 
    \FSM_sequential_grSt[2]_i_7 
       (.I0(\periodic_read_address[40]_i_3_n_0 ),
        .I1(issue_cas3215_in),
        .I2(\FSM_sequential_grSt[2]_i_4__0_n_0 ),
        .I3(\FSM_sequential_grSt[2]_i_5_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0057000000000000)) 
    \FSM_sequential_grSt[2]_i_8__0 
       (.I0(txn_fifo_empty_reg_n_0),
        .I1(group),
        .I2(bank[0]),
        .I3(ref_req_dly4_reg_0),
        .I4(grSt[1]),
        .I5(grSt[2]),
        .O(\FSM_sequential_grSt[2]_i_8__0_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_grSt[2]_i_8__1 
       (.I0(ref_req_dly4),
        .I1(\txn_fifo_wptr_reg[0]_0 ),
        .O(ref_req_dly4_reg_0));
  LUT5 #(
    .INIT(32'h7DFFFF7D)) 
    \FSM_sequential_grSt[2]_i_9 
       (.I0(cas_fifo_valid[2]),
        .I1(p_0_in2_in[0]),
        .I2(Q[0]),
        .I3(p_0_in2_in[1]),
        .I4(Q[1]),
        .O(\FSM_sequential_grSt[2]_i_9_n_0 ));
  (* FSM_ENCODED_STATES = "grACT:010,grPREWAIT:100,grAUTOPRE:101,grACTWAIT:011,grIDLE:110,grCASFSM:000,grACCEPT:001" *) 
  FDRE \FSM_sequential_grSt_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(\FSM_sequential_grSt[2]_i_1_n_0 ),
        .D(\FSM_sequential_grSt[0]_i_1_n_0 ),
        .Q(grSt[0]),
        .R(rst_r1));
  (* FSM_ENCODED_STATES = "grACT:010,grPREWAIT:100,grAUTOPRE:101,grACTWAIT:011,grIDLE:110,grCASFSM:000,grACCEPT:001" *) 
  FDSE \FSM_sequential_grSt_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(\FSM_sequential_grSt[2]_i_1_n_0 ),
        .D(\FSM_sequential_grSt[1]_i_1_n_0 ),
        .Q(grSt[1]),
        .S(rst_r1));
  (* FSM_ENCODED_STATES = "grACT:010,grPREWAIT:100,grAUTOPRE:101,grACTWAIT:011,grIDLE:110,grCASFSM:000,grACCEPT:001" *) 
  FDSE \FSM_sequential_grSt_reg[2] 
       (.C(per_rd_accept_reg_0),
        .CE(\FSM_sequential_grSt[2]_i_1_n_0 ),
        .D(\FSM_sequential_grSt[2]_i_2__2_n_0 ),
        .Q(grSt[2]),
        .S(rst_r1));
  LUT5 #(
    .INIT(32'h11111000)) 
    \FSM_sequential_gr_cas_state[0]_i_1 
       (.I0(gr_cas_state[2]),
        .I1(gr_cas_state[0]),
        .I2(\FSM_sequential_gr_cas_state[2]_i_6_n_0 ),
        .I3(\FSM_sequential_gr_cas_state[2]_i_5__1_n_0 ),
        .I4(gr_cas_state[1]),
        .O(gr_cas_state_nxt[0]));
  (* SOFT_HLUTNM = "soft_lutpair2506" *) 
  LUT3 #(
    .INIT(8'h12)) 
    \FSM_sequential_gr_cas_state[1]_i_1 
       (.I0(gr_cas_state[0]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[1]),
        .O(gr_cas_state_nxt[1]));
  LUT6 #(
    .INIT(64'h0030F0DD0030F011)) 
    \FSM_sequential_gr_cas_state[2]_i_1 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_3__1_n_0 ),
        .I1(gr_cas_state[1]),
        .I2(clrReq13_out),
        .I3(gr_cas_state[0]),
        .I4(gr_cas_state[2]),
        .I5(underfill_done),
        .O(\FSM_sequential_gr_cas_state[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00010101)) 
    \FSM_sequential_gr_cas_state[2]_i_2 
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(\FSM_sequential_gr_cas_state[2]_i_5__1_n_0 ),
        .I4(\FSM_sequential_gr_cas_state[2]_i_6_n_0 ),
        .O(gr_cas_state_nxt[2]));
  LUT4 #(
    .INIT(16'hFFD0)) 
    \FSM_sequential_gr_cas_state[2]_i_3__1 
       (.I0(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I1(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I2(cas_fifo_empty_reg_n_0),
        .I3(\FSM_sequential_gr_cas_state[2]_i_7__1_n_0 ),
        .O(\FSM_sequential_gr_cas_state[2]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000015110000)) 
    \FSM_sequential_gr_cas_state[2]_i_5__1 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_7__1_n_0 ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(wrReqR_i_5_n_0),
        .I5(wrReqR_i_4_n_0),
        .O(\FSM_sequential_gr_cas_state[2]_i_5__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2526" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \FSM_sequential_gr_cas_state[2]_i_6 
       (.I0(\txn_fifo_output_reg_n_0_[45] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\FSM_sequential_gr_cas_state[2]_i_9_n_0 ),
        .O(\FSM_sequential_gr_cas_state[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h5050303F5F5F303F)) 
    \FSM_sequential_gr_cas_state[2]_i_7__1 
       (.I0(\trcd_cntr_is_zero_reg[0][0][3]_209 ),
        .I1(\trcd_cntr_is_zero_reg[0][0][2]_207 ),
        .I2(\cmd_bank_cas[1]_i_1_n_0 ),
        .I3(\trcd_cntr_is_zero_reg[0][0][0]_203 ),
        .I4(\cmd_bank_cas[0]_i_1_n_0 ),
        .I5(\trcd_cntr_is_zero_reg[0][0][1]_205 ),
        .O(\FSM_sequential_gr_cas_state[2]_i_7__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \FSM_sequential_gr_cas_state[2]_i_9 
       (.I0(\cas_pend_fifo_reg_n_0_[2][45] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][45] ),
        .I2(\cas_pend_fifo_reg[0]_194 [45]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][45] ),
        .O(\FSM_sequential_gr_cas_state[2]_i_9_n_0 ));
  (* FSM_ENCODED_STATES = "CAS_IDLE:000,RMW_DATAWAIT:010,RMW_WRWAIT:011,CAS_WAIT:100,RMW_RDWAIT:001" *) 
  FDRE \FSM_sequential_gr_cas_state_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(\FSM_sequential_gr_cas_state[2]_i_1_n_0 ),
        .D(gr_cas_state_nxt[0]),
        .Q(gr_cas_state[0]),
        .R(rst_r1));
  (* FSM_ENCODED_STATES = "CAS_IDLE:000,RMW_DATAWAIT:010,RMW_WRWAIT:011,CAS_WAIT:100,RMW_RDWAIT:001" *) 
  FDRE \FSM_sequential_gr_cas_state_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(\FSM_sequential_gr_cas_state[2]_i_1_n_0 ),
        .D(gr_cas_state_nxt[1]),
        .Q(gr_cas_state[1]),
        .R(rst_r1));
  (* FSM_ENCODED_STATES = "CAS_IDLE:000,RMW_DATAWAIT:010,RMW_WRWAIT:011,CAS_WAIT:100,RMW_RDWAIT:001" *) 
  FDRE \FSM_sequential_gr_cas_state_reg[2] 
       (.C(per_rd_accept_reg_0),
        .CE(\FSM_sequential_gr_cas_state[2]_i_1_n_0 ),
        .D(gr_cas_state_nxt[2]),
        .Q(gr_cas_state[2]),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h00000002)) 
    accept_i_1__2
       (.I0(\txn_fifo_wptr_reg[0]_0 ),
        .I1(periodic_read_or_ref_block),
        .I2(group),
        .I3(bank[0]),
        .I4(txn_fifo_full_nxt),
        .O(grAccept_ns));
  FDRE accept_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(grAccept_ns),
        .Q(accept_reg_n_0),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h0E)) 
    actReqR_i_1
       (.I0(set_act_req),
        .I1(actReqR),
        .I2(actReqR_reg_0),
        .O(act_req_nxt));
  FDRE actReqR_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(act_req_nxt),
        .Q(actReqR),
        .R(rst_r1));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][0][0]_i_1 
       (.I0(ap_load_value[0]),
        .I1(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I2(\ap_cntr_zero_reg[0][0][0]_221 ),
        .I3(\ap_cntr_reg[0][0][0]_222 [0]),
        .O(\ap_cntr_nxt[0][0][0]_257 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2501" *) 
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][0][1]_i_1 
       (.I0(ap_load_value[1]),
        .I1(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I2(\ap_cntr_reg[0][0][0]_222 [1]),
        .I3(\ap_cntr_zero_reg[0][0][0]_221 ),
        .I4(\ap_cntr_reg[0][0][0]_222 [0]),
        .O(\ap_cntr_nxt[0][0][0]_257 [1]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][0][2]_i_1 
       (.I0(ap_load_value[2]),
        .I1(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I2(\ap_cntr_reg[0][0][0]_222 [2]),
        .I3(\ap_cntr_reg[0][0][0]_222 [1]),
        .I4(\ap_cntr_reg[0][0][0]_222 [0]),
        .I5(\ap_cntr_zero_reg[0][0][0]_221 ),
        .O(\ap_cntr_nxt[0][0][0]_257 [2]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][0][3]_i_1 
       (.I0(ap_load_value[3]),
        .I1(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I2(\ap_cntr_reg[0][0][0]_222 [3]),
        .I3(\ap_cntr_reg[0][0][0]_222 [2]),
        .I4(\ap_cntr[0][0][0][4]_i_2_n_0 ),
        .I5(\ap_cntr_reg[0][0][0]_222 [1]),
        .O(\ap_cntr_nxt[0][0][0]_257 [3]));
  LUT6 #(
    .INIT(64'h00000000FFFB0004)) 
    \ap_cntr[0][0][0][4]_i_1 
       (.I0(\ap_cntr_reg[0][0][0]_222 [2]),
        .I1(\ap_cntr[0][0][0][4]_i_2_n_0 ),
        .I2(\ap_cntr_reg[0][0][0]_222 [1]),
        .I3(\ap_cntr_reg[0][0][0]_222 [3]),
        .I4(\ap_cntr_reg[0][0][0]_222 [4]),
        .I5(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .O(\ap_cntr_nxt[0][0][0]_257 [4]));
  (* SOFT_HLUTNM = "soft_lutpair2501" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][0][4]_i_2 
       (.I0(\ap_cntr_reg[0][0][0]_222 [0]),
        .I1(\ap_cntr_zero_reg[0][0][0]_221 ),
        .O(\ap_cntr[0][0][0][4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000001800)) 
    \ap_cntr[0][0][0][4]_i_3 
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(cmdAP),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\cmd_bank_cas_reg[1]_0 [1]),
        .O(\ap_cntr[0][0][0][4]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][1][0]_i_1 
       (.I0(ap_load_value[0]),
        .I1(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I2(\ap_cntr_zero_reg[0][0][1]_219 ),
        .I3(\ap_cntr_reg[0][0][1]_220 [0]),
        .O(\ap_cntr_nxt[0][0][1]_255 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2500" *) 
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][1][1]_i_1 
       (.I0(ap_load_value[1]),
        .I1(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I2(\ap_cntr_reg[0][0][1]_220 [1]),
        .I3(\ap_cntr_zero_reg[0][0][1]_219 ),
        .I4(\ap_cntr_reg[0][0][1]_220 [0]),
        .O(\ap_cntr_nxt[0][0][1]_255 [1]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][1][2]_i_1 
       (.I0(ap_load_value[2]),
        .I1(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I2(\ap_cntr_reg[0][0][1]_220 [2]),
        .I3(\ap_cntr_reg[0][0][1]_220 [1]),
        .I4(\ap_cntr_reg[0][0][1]_220 [0]),
        .I5(\ap_cntr_zero_reg[0][0][1]_219 ),
        .O(\ap_cntr_nxt[0][0][1]_255 [2]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][1][3]_i_1 
       (.I0(ap_load_value[3]),
        .I1(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I2(\ap_cntr_reg[0][0][1]_220 [3]),
        .I3(\ap_cntr_reg[0][0][1]_220 [2]),
        .I4(\ap_cntr[0][0][1][4]_i_2_n_0 ),
        .I5(\ap_cntr_reg[0][0][1]_220 [1]),
        .O(\ap_cntr_nxt[0][0][1]_255 [3]));
  LUT6 #(
    .INIT(64'h00000000FFFB0004)) 
    \ap_cntr[0][0][1][4]_i_1 
       (.I0(\ap_cntr_reg[0][0][1]_220 [2]),
        .I1(\ap_cntr[0][0][1][4]_i_2_n_0 ),
        .I2(\ap_cntr_reg[0][0][1]_220 [1]),
        .I3(\ap_cntr_reg[0][0][1]_220 [3]),
        .I4(\ap_cntr_reg[0][0][1]_220 [4]),
        .I5(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .O(\ap_cntr_nxt[0][0][1]_255 [4]));
  (* SOFT_HLUTNM = "soft_lutpair2500" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][1][4]_i_2 
       (.I0(\ap_cntr_reg[0][0][1]_220 [0]),
        .I1(\ap_cntr_zero_reg[0][0][1]_219 ),
        .O(\ap_cntr[0][0][1][4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000018000000)) 
    \ap_cntr[0][0][1][4]_i_3 
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(cmdAP),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\cmd_bank_cas_reg[1]_0 [1]),
        .O(\ap_cntr[0][0][1][4]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][2][0]_i_1 
       (.I0(ap_load_value[0]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(\ap_cntr_zero_reg[0][0][2]_217 ),
        .I3(\ap_cntr_reg[0][0][2]_218 [0]),
        .O(\ap_cntr_nxt[0][0][2]_253 [0]));
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][2][1]_i_1 
       (.I0(ap_load_value[1]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(\ap_cntr_reg[0][0][2]_218 [1]),
        .I3(\ap_cntr_zero_reg[0][0][2]_217 ),
        .I4(\ap_cntr_reg[0][0][2]_218 [0]),
        .O(\ap_cntr_nxt[0][0][2]_253 [1]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][2][2]_i_1 
       (.I0(ap_load_value[2]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(\ap_cntr_reg[0][0][2]_218 [2]),
        .I3(\ap_cntr_reg[0][0][2]_218 [1]),
        .I4(\ap_cntr_reg[0][0][2]_218 [0]),
        .I5(\ap_cntr_zero_reg[0][0][2]_217 ),
        .O(\ap_cntr_nxt[0][0][2]_253 [2]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][2][3]_i_1 
       (.I0(ap_load_value[3]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(\ap_cntr_reg[0][0][2]_218 [3]),
        .I3(\ap_cntr_reg[0][0][2]_218 [2]),
        .I4(\ap_cntr[0][0][2][4]_i_2_n_0 ),
        .I5(\ap_cntr_reg[0][0][2]_218 [1]),
        .O(\ap_cntr_nxt[0][0][2]_253 [3]));
  LUT6 #(
    .INIT(64'h00000000FFFB0004)) 
    \ap_cntr[0][0][2][4]_i_1 
       (.I0(\ap_cntr_reg[0][0][2]_218 [2]),
        .I1(\ap_cntr[0][0][2][4]_i_2_n_0 ),
        .I2(\ap_cntr_reg[0][0][2]_218 [1]),
        .I3(\ap_cntr_reg[0][0][2]_218 [3]),
        .I4(\ap_cntr_reg[0][0][2]_218 [4]),
        .I5(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .O(\ap_cntr_nxt[0][0][2]_253 [4]));
  (* SOFT_HLUTNM = "soft_lutpair2518" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][2][4]_i_2 
       (.I0(\ap_cntr_reg[0][0][2]_218 [0]),
        .I1(\ap_cntr_zero_reg[0][0][2]_217 ),
        .O(\ap_cntr[0][0][2][4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][3][0]_i_1 
       (.I0(ap_load_value[0]),
        .I1(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I2(\ap_cntr_zero_reg[0][0][3]_215 ),
        .I3(\ap_cntr_reg[0][0][3]_216 [0]),
        .O(\ap_cntr_nxt[0][0][3]_250 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2496" *) 
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][3][1]_i_1 
       (.I0(ap_load_value[1]),
        .I1(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I2(\ap_cntr_reg[0][0][3]_216 [1]),
        .I3(\ap_cntr_zero_reg[0][0][3]_215 ),
        .I4(\ap_cntr_reg[0][0][3]_216 [0]),
        .O(\ap_cntr_nxt[0][0][3]_250 [1]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][3][2]_i_1 
       (.I0(ap_load_value[2]),
        .I1(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I2(\ap_cntr_reg[0][0][3]_216 [2]),
        .I3(\ap_cntr_reg[0][0][3]_216 [1]),
        .I4(\ap_cntr_reg[0][0][3]_216 [0]),
        .I5(\ap_cntr_zero_reg[0][0][3]_215 ),
        .O(\ap_cntr_nxt[0][0][3]_250 [2]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][3][3]_i_1 
       (.I0(ap_load_value[3]),
        .I1(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I2(\ap_cntr_reg[0][0][3]_216 [3]),
        .I3(\ap_cntr_reg[0][0][3]_216 [2]),
        .I4(\ap_cntr[0][0][3][4]_i_2_n_0 ),
        .I5(\ap_cntr_reg[0][0][3]_216 [1]),
        .O(\ap_cntr_nxt[0][0][3]_250 [3]));
  LUT6 #(
    .INIT(64'h00000000FFFB0004)) 
    \ap_cntr[0][0][3][4]_i_1 
       (.I0(\ap_cntr_reg[0][0][3]_216 [2]),
        .I1(\ap_cntr[0][0][3][4]_i_2_n_0 ),
        .I2(\ap_cntr_reg[0][0][3]_216 [1]),
        .I3(\ap_cntr_reg[0][0][3]_216 [3]),
        .I4(\ap_cntr_reg[0][0][3]_216 [4]),
        .I5(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .O(\ap_cntr_nxt[0][0][3]_250 [4]));
  (* SOFT_HLUTNM = "soft_lutpair2496" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][3][4]_i_2 
       (.I0(\ap_cntr_reg[0][0][3]_216 [0]),
        .I1(\ap_cntr_zero_reg[0][0][3]_215 ),
        .O(\ap_cntr[0][0][3][4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0008800000000000)) 
    \ap_cntr[0][0][3][4]_i_3 
       (.I0(\cmd_bank_cas_reg[1]_0 [0]),
        .I1(\cmd_bank_cas_reg[1]_0 [1]),
        .I2(gr_cas_state[1]),
        .I3(gr_cas_state[0]),
        .I4(gr_cas_state[2]),
        .I5(cmdAP),
        .O(\ap_cntr[0][0][3][4]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_expired[0][0][0]_i_1__0 
       (.I0(\ap_cntr_nxt[0][0][0]_257 [2]),
        .I1(\ap_cntr_nxt[0][0][0]_257 [4]),
        .I2(\ap_cntr_zero[0][0][0]_i_2_n_0 ),
        .I3(\ap_cntr_nxt[0][0][0]_257 [3]),
        .I4(\ap_cntr_zero_reg[0][0][0]_221 ),
        .O(\ap_cntr_expired_nxt[0][0][0]_2 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_cntr_expired[0][0][1]_i_1__0 
       (.I0(\ap_cntr_nxt[0][0][1]_255 [4]),
        .I1(\ap_cntr_nxt[0][0][1]_255 [0]),
        .I2(\ap_cntr_nxt[0][0][1]_255 [3]),
        .I3(\ap_cntr_nxt[0][0][1]_255 [2]),
        .I4(\ap_cntr_nxt[0][0][1]_255 [1]),
        .I5(\ap_cntr_zero_reg[0][0][1]_219 ),
        .O(\ap_cntr_expired_nxt[0][0][1]_1 ));
  LUT2 #(
    .INIT(4'h2)) 
    \ap_cntr_expired[0][0][2]_i_1 
       (.I0(\ap_cntr_zero_nxt[0][0][2]_252 ),
        .I1(\ap_cntr_zero_reg[0][0][2]_217 ),
        .O(\ap_cntr_expired_nxt[0][0][2]_251 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_cntr_expired[0][0][3]_i_1 
       (.I0(\ap_cntr_nxt[0][0][3]_250 [4]),
        .I1(\ap_cntr_nxt[0][0][3]_250 [0]),
        .I2(\ap_cntr_nxt[0][0][3]_250 [1]),
        .I3(\ap_cntr_nxt[0][0][3]_250 [2]),
        .I4(\ap_cntr_nxt[0][0][3]_250 [3]),
        .I5(\ap_cntr_zero_reg[0][0][3]_215 ),
        .O(\ap_cntr_expired_nxt[0][0][3]_0 ));
  FDRE \ap_cntr_expired_reg[0][0][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_expired_nxt[0][0][0]_2 ),
        .Q(sel0__14),
        .R(1'b0));
  FDRE \ap_cntr_expired_reg[0][0][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_expired_nxt[0][0][1]_1 ),
        .Q(sel0__10),
        .R(1'b0));
  FDRE \ap_cntr_expired_reg[0][0][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_expired_nxt[0][0][2]_251 ),
        .Q(sel0__6),
        .R(1'b0));
  FDRE \ap_cntr_expired_reg[0][0][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_expired_nxt[0][0][3]_0 ),
        .Q(sel0__2),
        .R(1'b0));
  FDRE \ap_cntr_reg[0][0][0][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][0]_257 [0]),
        .Q(\ap_cntr_reg[0][0][0]_222 [0]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][0]_257 [1]),
        .Q(\ap_cntr_reg[0][0][0]_222 [1]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][0]_257 [2]),
        .Q(\ap_cntr_reg[0][0][0]_222 [2]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][0]_257 [3]),
        .Q(\ap_cntr_reg[0][0][0]_222 [3]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][4] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][0]_257 [4]),
        .Q(\ap_cntr_reg[0][0][0]_222 [4]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][1]_255 [0]),
        .Q(\ap_cntr_reg[0][0][1]_220 [0]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][1]_255 [1]),
        .Q(\ap_cntr_reg[0][0][1]_220 [1]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][1]_255 [2]),
        .Q(\ap_cntr_reg[0][0][1]_220 [2]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][1]_255 [3]),
        .Q(\ap_cntr_reg[0][0][1]_220 [3]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][4] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][1]_255 [4]),
        .Q(\ap_cntr_reg[0][0][1]_220 [4]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][2]_253 [0]),
        .Q(\ap_cntr_reg[0][0][2]_218 [0]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][2]_253 [1]),
        .Q(\ap_cntr_reg[0][0][2]_218 [1]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][2]_253 [2]),
        .Q(\ap_cntr_reg[0][0][2]_218 [2]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][2]_253 [3]),
        .Q(\ap_cntr_reg[0][0][2]_218 [3]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][4] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][2]_253 [4]),
        .Q(\ap_cntr_reg[0][0][2]_218 [4]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][3]_250 [0]),
        .Q(\ap_cntr_reg[0][0][3]_216 [0]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][3]_250 [1]),
        .Q(\ap_cntr_reg[0][0][3]_216 [1]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][3]_250 [2]),
        .Q(\ap_cntr_reg[0][0][3]_216 [2]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][3]_250 [3]),
        .Q(\ap_cntr_reg[0][0][3]_216 [3]),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][4] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_nxt[0][0][3]_250 [4]),
        .Q(\ap_cntr_reg[0][0][3]_216 [4]),
        .R(rst_r1));
  LUT4 #(
    .INIT(16'h0001)) 
    \ap_cntr_zero[0][0][0]_i_1 
       (.I0(\ap_cntr_nxt[0][0][0]_257 [2]),
        .I1(\ap_cntr_nxt[0][0][0]_257 [4]),
        .I2(\ap_cntr_zero[0][0][0]_i_2_n_0 ),
        .I3(\ap_cntr_nxt[0][0][0]_257 [3]),
        .O(\ap_cntr_zero_nxt[0][0][0]_256 ));
  LUT6 #(
    .INIT(64'hFFFFFAAFCCCCFAAF)) 
    \ap_cntr_zero[0][0][0]_i_2 
       (.I0(\ap_cntr_reg[0][0][0]_222 [1]),
        .I1(ap_load_value[1]),
        .I2(\ap_cntr_reg[0][0][0]_222 [0]),
        .I3(\ap_cntr_zero_reg[0][0][0]_221 ),
        .I4(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I5(ap_load_value[0]),
        .O(\ap_cntr_zero[0][0][0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_zero[0][0][1]_i_1 
       (.I0(\ap_cntr_nxt[0][0][1]_255 [4]),
        .I1(\ap_cntr_nxt[0][0][1]_255 [0]),
        .I2(\ap_cntr_nxt[0][0][1]_255 [3]),
        .I3(\ap_cntr_nxt[0][0][1]_255 [2]),
        .I4(\ap_cntr_nxt[0][0][1]_255 [1]),
        .O(\ap_cntr_zero_nxt[0][0][1]_254 ));
  LUT6 #(
    .INIT(64'h0000000044447447)) 
    \ap_cntr_zero[0][0][2]_i_1 
       (.I0(ap_load_value[3]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(\ap_cntr_reg[0][0][2]_218 [3]),
        .I3(\ap_cntr_zero[0][0][2]_i_3_n_0 ),
        .I4(\ap_cntr_reg[0][0][2]_218 [4]),
        .I5(\ap_cntr_zero[0][0][2]_i_4_n_0 ),
        .O(\ap_cntr_zero_nxt[0][0][2]_252 ));
  LUT6 #(
    .INIT(64'h0000000018000000)) 
    \ap_cntr_zero[0][0][2]_i_2 
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(cmdAP),
        .I4(\cmd_bank_cas_reg[1]_0 [1]),
        .I5(\cmd_bank_cas_reg[1]_0 [0]),
        .O(\ap_cntr_zero[0][0][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2518" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \ap_cntr_zero[0][0][2]_i_3 
       (.I0(\ap_cntr_reg[0][0][2]_218 [1]),
        .I1(\ap_cntr_reg[0][0][2]_218 [0]),
        .I2(\ap_cntr_zero_reg[0][0][2]_217 ),
        .I3(\ap_cntr_reg[0][0][2]_218 [2]),
        .O(\ap_cntr_zero[0][0][2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEFEAEAEF)) 
    \ap_cntr_zero[0][0][2]_i_4 
       (.I0(\ap_cntr_nxt[0][0][2]_253 [2]),
        .I1(ap_load_value[0]),
        .I2(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I3(\ap_cntr_zero_reg[0][0][2]_217 ),
        .I4(\ap_cntr_reg[0][0][2]_218 [0]),
        .I5(\ap_cntr_nxt[0][0][2]_253 [1]),
        .O(\ap_cntr_zero[0][0][2]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_zero[0][0][3]_i_1 
       (.I0(\ap_cntr_nxt[0][0][3]_250 [4]),
        .I1(\ap_cntr_nxt[0][0][3]_250 [0]),
        .I2(\ap_cntr_nxt[0][0][3]_250 [1]),
        .I3(\ap_cntr_nxt[0][0][3]_250 [2]),
        .I4(\ap_cntr_nxt[0][0][3]_250 [3]),
        .O(\ap_cntr_zero_nxt[0][0][3]_249 ));
  FDRE \ap_cntr_zero_reg[0][0][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_zero_nxt[0][0][0]_256 ),
        .Q(\ap_cntr_zero_reg[0][0][0]_221 ),
        .R(rst_r1));
  FDRE \ap_cntr_zero_reg[0][0][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_zero_nxt[0][0][1]_254 ),
        .Q(\ap_cntr_zero_reg[0][0][1]_219 ),
        .R(rst_r1));
  FDRE \ap_cntr_zero_reg[0][0][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_zero_nxt[0][0][2]_252 ),
        .Q(\ap_cntr_zero_reg[0][0][2]_217 ),
        .R(rst_r1));
  FDRE \ap_cntr_zero_reg[0][0][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_zero_nxt[0][0][3]_249 ),
        .Q(\ap_cntr_zero_reg[0][0][3]_215 ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2528" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \ap_load_value[0]_i_1 
       (.I0(wrReqR),
        .I1(\ap_load_value[0]_i_2_n_0 ),
        .I2(\ap_load_value[3]_i_3_n_0 ),
        .O(\ap_load_value[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h030503F5F305F3F5)) 
    \ap_load_value[0]_i_2 
       (.I0(\tras_cntr_rb_reg[0][0][0]_211 [0]),
        .I1(\tras_cntr_rb_reg[0][0][2]_213 [0]),
        .I2(\cmd_bank_cas_reg[1]_0 [0]),
        .I3(\cmd_bank_cas_reg[1]_0 [1]),
        .I4(\tras_cntr_rb_reg[0][0][1]_212 [0]),
        .I5(\tras_cntr_rb_reg[0][0][3]_214 [0]),
        .O(\ap_load_value[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2527" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \ap_load_value[1]_i_1 
       (.I0(\ap_load_value[3]_i_2_n_0 ),
        .I1(\ap_load_value[3]_i_3_n_0 ),
        .I2(wrReqR),
        .O(\ap_load_value[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2527" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \ap_load_value[2]_i_1 
       (.I0(\ap_load_value[3]_i_2_n_0 ),
        .I1(\ap_load_value[3]_i_3_n_0 ),
        .I2(wrReqR),
        .O(\ap_load_value[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2528" *) 
  LUT3 #(
    .INIT(8'hF1)) 
    \ap_load_value[3]_i_1 
       (.I0(\ap_load_value[3]_i_2_n_0 ),
        .I1(\ap_load_value[3]_i_3_n_0 ),
        .I2(wrReqR),
        .O(ap_load_value_nxt));
  LUT6 #(
    .INIT(64'h0053F0530F53FF53)) 
    \ap_load_value[3]_i_2 
       (.I0(\tras_cntr_rb_reg[0][0][1]_212 [1]),
        .I1(\tras_cntr_rb_reg[0][0][0]_211 [1]),
        .I2(\cmd_bank_cas_reg[1]_0 [0]),
        .I3(\cmd_bank_cas_reg[1]_0 [1]),
        .I4(\tras_cntr_rb_reg[0][0][3]_214 [1]),
        .I5(\tras_cntr_rb_reg[0][0][2]_213 [1]),
        .O(\ap_load_value[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h530053F0530F53FF)) 
    \ap_load_value[3]_i_3 
       (.I0(\tras_cntr_rb_reg[0][0][3]_214 [2]),
        .I1(\tras_cntr_rb_reg[0][0][2]_213 [2]),
        .I2(\cmd_bank_cas_reg[1]_0 [0]),
        .I3(\cmd_bank_cas_reg[1]_0 [1]),
        .I4(\tras_cntr_rb_reg[0][0][1]_212 [2]),
        .I5(\tras_cntr_rb_reg[0][0][0]_211 [2]),
        .O(\ap_load_value[3]_i_3_n_0 ));
  FDRE \ap_load_value_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_load_value[0]_i_1_n_0 ),
        .Q(ap_load_value[0]),
        .R(1'b0));
  FDRE \ap_load_value_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_load_value[1]_i_1_n_0 ),
        .Q(ap_load_value[1]),
        .R(1'b0));
  FDRE \ap_load_value_reg[2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\ap_load_value[2]_i_1_n_0 ),
        .Q(ap_load_value[2]),
        .R(1'b0));
  FDRE \ap_load_value_reg[3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(ap_load_value_nxt),
        .Q(ap_load_value[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2513" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][0]_i_1__2 
       (.I0(\buf_fifo_reg[0]_195 [0]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][0]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[0]_259 [0]));
  LUT6 #(
    .INIT(64'hFEEEEEEE02222222)) 
    \buf_fifo[0][0]_i_2__2 
       (.I0(\buf_fifo[0][0]_i_3_n_0 ),
        .I1(select_periodic_read),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg[0]_0 ),
        .I4(accept_reg_n_0),
        .I5(dBufAdr[0]),
        .O(\buf_fifo[0][0]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hF0CCAAFFF0CCAA00)) 
    \buf_fifo[0][0]_i_3 
       (.I0(\buf_fifo_reg[1]_196 [0]),
        .I1(\buf_fifo_reg[2]_197 [0]),
        .I2(\buf_fifo_reg[3]_198 [0]),
        .I3(txn_fifo_wptr[0]),
        .I4(txn_fifo_wptr[1]),
        .I5(\buf_fifo_reg[0]_195 [0]),
        .O(\buf_fifo[0][0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2515" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][1]_i_1__2 
       (.I0(\buf_fifo_reg[0]_195 [1]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][1]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[0]_259 [1]));
  LUT6 #(
    .INIT(64'hFEEEEEEE02222222)) 
    \buf_fifo[0][1]_i_2__2 
       (.I0(\buf_fifo[0][1]_i_3_n_0 ),
        .I1(select_periodic_read),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg[0]_0 ),
        .I4(accept_reg_n_0),
        .I5(dBufAdr[1]),
        .O(\buf_fifo[0][1]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \buf_fifo[0][1]_i_3 
       (.I0(\buf_fifo_reg[1]_196 [1]),
        .I1(\buf_fifo_reg[3]_198 [1]),
        .I2(\buf_fifo_reg[2]_197 [1]),
        .I3(txn_fifo_wptr[1]),
        .I4(txn_fifo_wptr[0]),
        .I5(\buf_fifo_reg[0]_195 [1]),
        .O(\buf_fifo[0][1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2512" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][2]_i_1__2 
       (.I0(\buf_fifo_reg[0]_195 [2]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][2]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[0]_259 [2]));
  LUT6 #(
    .INIT(64'hFEEEEEEE02222222)) 
    \buf_fifo[0][2]_i_2__2 
       (.I0(\buf_fifo[0][2]_i_3_n_0 ),
        .I1(select_periodic_read),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg[0]_0 ),
        .I4(accept_reg_n_0),
        .I5(dBufAdr[2]),
        .O(\buf_fifo[0][2]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    \buf_fifo[0][2]_i_3 
       (.I0(\buf_fifo_reg[1]_196 [2]),
        .I1(\buf_fifo_reg[2]_197 [2]),
        .I2(\buf_fifo_reg[0]_195 [2]),
        .I3(txn_fifo_wptr[0]),
        .I4(txn_fifo_wptr[1]),
        .I5(\buf_fifo_reg[3]_198 [2]),
        .O(\buf_fifo[0][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2514" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][3]_i_1__2 
       (.I0(\buf_fifo_reg[0]_195 [3]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][3]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[0]_259 [3]));
  LUT6 #(
    .INIT(64'hFEEEEEEE02222222)) 
    \buf_fifo[0][3]_i_2__2 
       (.I0(\buf_fifo[0][3]_i_3_n_0 ),
        .I1(select_periodic_read),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg[0]_0 ),
        .I4(accept_reg_n_0),
        .I5(dBufAdr[3]),
        .O(\buf_fifo[0][3]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \buf_fifo[0][3]_i_3 
       (.I0(\buf_fifo_reg[1]_196 [3]),
        .I1(\buf_fifo_reg[3]_198 [3]),
        .I2(\buf_fifo_reg[2]_197 [3]),
        .I3(txn_fifo_wptr[1]),
        .I4(txn_fifo_wptr[0]),
        .I5(\buf_fifo_reg[0]_195 [3]),
        .O(\buf_fifo[0][3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2517" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][4]_i_1__2 
       (.I0(\buf_fifo_reg[0]_195 [4]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][4]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[0]_259 [4]));
  LUT6 #(
    .INIT(64'hFEEEEEEE02222222)) 
    \buf_fifo[0][4]_i_2__2 
       (.I0(\buf_fifo[0][4]_i_3_n_0 ),
        .I1(select_periodic_read),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg[0]_0 ),
        .I4(accept_reg_n_0),
        .I5(dBufAdr[4]),
        .O(\buf_fifo[0][4]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \buf_fifo[0][4]_i_3 
       (.I0(\buf_fifo_reg[1]_196 [4]),
        .I1(\buf_fifo_reg[3]_198 [4]),
        .I2(\buf_fifo_reg[2]_197 [4]),
        .I3(txn_fifo_wptr[1]),
        .I4(txn_fifo_wptr[0]),
        .I5(\buf_fifo_reg[0]_195 [4]),
        .O(\buf_fifo[0][4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2513" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][0]_i_1__2 
       (.I0(\buf_fifo_reg[1]_196 [0]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][0]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[1]_262 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2515" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][1]_i_1__2 
       (.I0(\buf_fifo_reg[1]_196 [1]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][1]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[1]_262 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2512" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][2]_i_1__2 
       (.I0(\buf_fifo_reg[1]_196 [2]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][2]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[1]_262 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2514" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][3]_i_1__2 
       (.I0(\buf_fifo_reg[1]_196 [3]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][3]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[1]_262 [3]));
  (* SOFT_HLUTNM = "soft_lutpair2517" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][4]_i_1__2 
       (.I0(\buf_fifo_reg[1]_196 [4]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][4]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[1]_262 [4]));
  (* SOFT_HLUTNM = "soft_lutpair2509" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][0]_i_1__2 
       (.I0(\buf_fifo_reg[2]_197 [0]),
        .I1(txn_fifo_wptr[0]),
        .I2(txn_fifo_wptr[1]),
        .I3(\buf_fifo[0][0]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[2]_261 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2511" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][1]_i_1__2 
       (.I0(\buf_fifo_reg[2]_197 [1]),
        .I1(txn_fifo_wptr[0]),
        .I2(txn_fifo_wptr[1]),
        .I3(\buf_fifo[0][1]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[2]_261 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2508" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][2]_i_1__2 
       (.I0(\buf_fifo_reg[2]_197 [2]),
        .I1(txn_fifo_wptr[0]),
        .I2(txn_fifo_wptr[1]),
        .I3(\buf_fifo[0][2]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[2]_261 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2510" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][3]_i_1__2 
       (.I0(\buf_fifo_reg[2]_197 [3]),
        .I1(txn_fifo_wptr[0]),
        .I2(txn_fifo_wptr[1]),
        .I3(\buf_fifo[0][3]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[2]_261 [3]));
  (* SOFT_HLUTNM = "soft_lutpair2516" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][4]_i_1__2 
       (.I0(\buf_fifo_reg[2]_197 [4]),
        .I1(txn_fifo_wptr[0]),
        .I2(txn_fifo_wptr[1]),
        .I3(\buf_fifo[0][4]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[2]_261 [4]));
  (* SOFT_HLUTNM = "soft_lutpair2509" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][0]_i_1__2 
       (.I0(\buf_fifo_reg[3]_198 [0]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][0]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[3]_260 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2511" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][1]_i_1__2 
       (.I0(\buf_fifo_reg[3]_198 [1]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][1]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[3]_260 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2508" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][2]_i_1__2 
       (.I0(\buf_fifo_reg[3]_198 [2]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][2]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[3]_260 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2510" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][3]_i_1__2 
       (.I0(\buf_fifo_reg[3]_198 [3]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][3]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[3]_260 [3]));
  (* SOFT_HLUTNM = "soft_lutpair2516" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][4]_i_1__2 
       (.I0(\buf_fifo_reg[3]_198 [4]),
        .I1(txn_fifo_wptr[1]),
        .I2(txn_fifo_wptr[0]),
        .I3(\buf_fifo[0][4]_i_2__2_n_0 ),
        .O(\buf_fifo_nxt[3]_260 [4]));
  FDRE \buf_fifo_reg[0][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[0]_259 [0]),
        .Q(\buf_fifo_reg[0]_195 [0]),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[0]_259 [1]),
        .Q(\buf_fifo_reg[0]_195 [1]),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[0]_259 [2]),
        .Q(\buf_fifo_reg[0]_195 [2]),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[0]_259 [3]),
        .Q(\buf_fifo_reg[0]_195 [3]),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][4] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[0]_259 [4]),
        .Q(\buf_fifo_reg[0]_195 [4]),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[1]_262 [0]),
        .Q(\buf_fifo_reg[1]_196 [0]),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[1]_262 [1]),
        .Q(\buf_fifo_reg[1]_196 [1]),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[1]_262 [2]),
        .Q(\buf_fifo_reg[1]_196 [2]),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[1]_262 [3]),
        .Q(\buf_fifo_reg[1]_196 [3]),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][4] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[1]_262 [4]),
        .Q(\buf_fifo_reg[1]_196 [4]),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[2]_261 [0]),
        .Q(\buf_fifo_reg[2]_197 [0]),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[2]_261 [1]),
        .Q(\buf_fifo_reg[2]_197 [1]),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[2]_261 [2]),
        .Q(\buf_fifo_reg[2]_197 [2]),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[2]_261 [3]),
        .Q(\buf_fifo_reg[2]_197 [3]),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][4] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[2]_261 [4]),
        .Q(\buf_fifo_reg[2]_197 [4]),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[3]_260 [0]),
        .Q(\buf_fifo_reg[3]_198 [0]),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[3]_260 [1]),
        .Q(\buf_fifo_reg[3]_198 [1]),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[3]_260 [2]),
        .Q(\buf_fifo_reg[3]_198 [2]),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[3]_260 [3]),
        .Q(\buf_fifo_reg[3]_198 [3]),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][4] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\buf_fifo_nxt[3]_260 [4]),
        .Q(\buf_fifo_reg[3]_198 [4]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][0]_i_1__2 
       (.I0(\buf_fifo_nxt[3]_260 [0]),
        .I1(\buf_fifo_nxt[2]_261 [0]),
        .I2(\buf_fifo_nxt[1]_262 [0]),
        .I3(txn_fifo_rptr[0]),
        .I4(txn_fifo_rptr[1]),
        .I5(\buf_fifo_nxt[0]_259 [0]),
        .O(cas_dbuf_fifo_input[0]));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][1]_i_1__2 
       (.I0(\buf_fifo_nxt[3]_260 [1]),
        .I1(\buf_fifo_nxt[2]_261 [1]),
        .I2(\buf_fifo_nxt[1]_262 [1]),
        .I3(txn_fifo_rptr[0]),
        .I4(txn_fifo_rptr[1]),
        .I5(\buf_fifo_nxt[0]_259 [1]),
        .O(cas_dbuf_fifo_input[1]));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][2]_i_1__2 
       (.I0(\buf_fifo_nxt[3]_260 [2]),
        .I1(\buf_fifo_nxt[2]_261 [2]),
        .I2(\buf_fifo_nxt[1]_262 [2]),
        .I3(txn_fifo_rptr[0]),
        .I4(txn_fifo_rptr[1]),
        .I5(\buf_fifo_nxt[0]_259 [2]),
        .O(cas_dbuf_fifo_input[2]));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][3]_i_1__2 
       (.I0(\buf_fifo_nxt[3]_260 [3]),
        .I1(\buf_fifo_nxt[2]_261 [3]),
        .I2(\buf_fifo_nxt[1]_262 [3]),
        .I3(txn_fifo_rptr[0]),
        .I4(txn_fifo_rptr[1]),
        .I5(\buf_fifo_nxt[0]_259 [3]),
        .O(cas_dbuf_fifo_input[3]));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][4]_i_1__2 
       (.I0(\buf_fifo_nxt[3]_260 [4]),
        .I1(\buf_fifo_nxt[2]_261 [4]),
        .I2(\buf_fifo_nxt[1]_262 [4]),
        .I3(txn_fifo_rptr[0]),
        .I4(txn_fifo_rptr[1]),
        .I5(\buf_fifo_nxt[0]_259 [4]),
        .O(cas_dbuf_fifo_input[4]));
  FDRE \cas_dbuf_fifo_reg[0][0] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(cas_dbuf_fifo_input[0]),
        .Q(\cas_dbuf_fifo_reg[0]_199 [0]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][1] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(cas_dbuf_fifo_input[1]),
        .Q(\cas_dbuf_fifo_reg[0]_199 [1]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][2] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(cas_dbuf_fifo_input[2]),
        .Q(\cas_dbuf_fifo_reg[0]_199 [2]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][3] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(cas_dbuf_fifo_input[3]),
        .Q(\cas_dbuf_fifo_reg[0]_199 [3]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][4] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(cas_dbuf_fifo_input[4]),
        .Q(\cas_dbuf_fifo_reg[0]_199 [4]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][0] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(cas_dbuf_fifo_input[0]),
        .Q(\cas_dbuf_fifo_reg[1]_200 [0]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][1] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(cas_dbuf_fifo_input[1]),
        .Q(\cas_dbuf_fifo_reg[1]_200 [1]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][2] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(cas_dbuf_fifo_input[2]),
        .Q(\cas_dbuf_fifo_reg[1]_200 [2]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][3] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(cas_dbuf_fifo_input[3]),
        .Q(\cas_dbuf_fifo_reg[1]_200 [3]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][4] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(cas_dbuf_fifo_input[4]),
        .Q(\cas_dbuf_fifo_reg[1]_200 [4]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][0] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(cas_dbuf_fifo_input[0]),
        .Q(\cas_dbuf_fifo_reg[2]_201 [0]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][1] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(cas_dbuf_fifo_input[1]),
        .Q(\cas_dbuf_fifo_reg[2]_201 [1]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][2] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(cas_dbuf_fifo_input[2]),
        .Q(\cas_dbuf_fifo_reg[2]_201 [2]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][3] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(cas_dbuf_fifo_input[3]),
        .Q(\cas_dbuf_fifo_reg[2]_201 [3]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][4] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(cas_dbuf_fifo_input[4]),
        .Q(\cas_dbuf_fifo_reg[2]_201 [4]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][0] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(cas_dbuf_fifo_input[0]),
        .Q(\cas_dbuf_fifo_reg[3]_202 [0]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][1] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(cas_dbuf_fifo_input[1]),
        .Q(\cas_dbuf_fifo_reg[3]_202 [1]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][2] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(cas_dbuf_fifo_input[2]),
        .Q(\cas_dbuf_fifo_reg[3]_202 [2]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][3] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(cas_dbuf_fifo_input[3]),
        .Q(\cas_dbuf_fifo_reg[3]_202 [3]),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][4] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(cas_dbuf_fifo_input[4]),
        .Q(\cas_dbuf_fifo_reg[3]_202 [4]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h1824824182412418)) 
    cas_fifo_empty_i_1
       (.I0(cas_fifo_wptr[1]),
        .I1(cas_fifo_rptr[0]),
        .I2(\cas_fifo_rptr[1]_i_2_n_0 ),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_wptr[0]),
        .I5(\cas_fifo_wptr[1]_i_2_n_0 ),
        .O(cas_fifo_empty_nxt));
  FDRE cas_fifo_empty_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_fifo_empty_nxt),
        .Q(cas_fifo_empty_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h1E78871EE18778E1)) 
    cas_fifo_full_i_1
       (.I0(\cas_fifo_wptr[1]_i_2_n_0 ),
        .I1(cas_fifo_wptr[0]),
        .I2(cas_fifo_rptr[1]),
        .I3(\cas_fifo_rptr[1]_i_2_n_0 ),
        .I4(cas_fifo_rptr[0]),
        .I5(cas_fifo_wptr[1]),
        .O(cas_fifo_full_nxt));
  FDRE cas_fifo_full_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_fifo_full_nxt),
        .Q(cas_fifo_full),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h10FFFFFFEF000000)) 
    \cas_fifo_rptr[0]_i_1 
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[0]),
        .I3(\cas_fifo_rptr_reg[0]_0 ),
        .I4(tranSentC),
        .I5(cas_fifo_rptr[0]),
        .O(cas_fifo_rptr_nxt[0]));
  (* SOFT_HLUTNM = "soft_lutpair2525" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \cas_fifo_rptr[1]_i_1 
       (.I0(cas_fifo_rptr[1]),
        .I1(\cas_fifo_rptr[1]_i_2_n_0 ),
        .I2(cas_fifo_rptr[0]),
        .O(cas_fifo_rptr_nxt[1]));
  (* SOFT_HLUTNM = "soft_lutpair2495" *) 
  LUT5 #(
    .INIT(32'h10FFFFFF)) 
    \cas_fifo_rptr[1]_i_2 
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[0]),
        .I3(\cas_fifo_rptr_reg[0]_0 ),
        .I4(tranSentC),
        .O(\cas_fifo_rptr[1]_i_2_n_0 ));
  FDRE \cas_fifo_rptr_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_fifo_rptr_nxt[0]),
        .Q(cas_fifo_rptr[0]),
        .R(rst_r1));
  FDRE \cas_fifo_rptr_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_fifo_rptr_nxt[1]),
        .Q(cas_fifo_rptr[1]),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hFF10FF10FF100000)) 
    \cas_fifo_valid[0]_i_1 
       (.I0(cas_fifo_wptr[0]),
        .I1(cas_fifo_wptr[1]),
        .I2(\cas_fifo_wptr[1]_i_2_n_0 ),
        .I3(cas_fifo_valid[0]),
        .I4(\cas_fifo_rptr[1]_i_2_n_0 ),
        .I5(\cas_fifo_valid[0]_i_2_n_0 ),
        .O(cas_fifo_valid_nxt[0]));
  (* SOFT_HLUTNM = "soft_lutpair2525" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \cas_fifo_valid[0]_i_2 
       (.I0(cas_fifo_rptr[0]),
        .I1(cas_fifo_rptr[1]),
        .O(\cas_fifo_valid[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF40FF40FF400000)) 
    \cas_fifo_valid[1]_i_1 
       (.I0(cas_fifo_wptr[1]),
        .I1(cas_fifo_wptr[0]),
        .I2(\cas_fifo_wptr[1]_i_2_n_0 ),
        .I3(cas_fifo_valid[1]),
        .I4(\cas_fifo_rptr[1]_i_2_n_0 ),
        .I5(\cas_fifo_valid[1]_i_2_n_0 ),
        .O(cas_fifo_valid_nxt[1]));
  LUT2 #(
    .INIT(4'hB)) 
    \cas_fifo_valid[1]_i_2 
       (.I0(cas_fifo_rptr[1]),
        .I1(cas_fifo_rptr[0]),
        .O(\cas_fifo_valid[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF40FF40FF400000)) 
    \cas_fifo_valid[2]_i_1 
       (.I0(cas_fifo_wptr[0]),
        .I1(cas_fifo_wptr[1]),
        .I2(\cas_fifo_wptr[1]_i_2_n_0 ),
        .I3(cas_fifo_valid[2]),
        .I4(\cas_fifo_rptr[1]_i_2_n_0 ),
        .I5(\cas_fifo_valid[2]_i_2_n_0 ),
        .O(cas_fifo_valid_nxt[2]));
  (* SOFT_HLUTNM = "soft_lutpair2544" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \cas_fifo_valid[2]_i_2 
       (.I0(cas_fifo_rptr[0]),
        .I1(cas_fifo_rptr[1]),
        .O(\cas_fifo_valid[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF80FF80FF800000)) 
    \cas_fifo_valid[3]_i_1 
       (.I0(\cas_fifo_wptr[1]_i_2_n_0 ),
        .I1(cas_fifo_wptr[0]),
        .I2(cas_fifo_wptr[1]),
        .I3(cas_fifo_valid[3]),
        .I4(\cas_fifo_rptr[1]_i_2_n_0 ),
        .I5(\cas_fifo_valid[3]_i_2_n_0 ),
        .O(cas_fifo_valid_nxt[3]));
  (* SOFT_HLUTNM = "soft_lutpair2544" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \cas_fifo_valid[3]_i_2 
       (.I0(cas_fifo_rptr[0]),
        .I1(cas_fifo_rptr[1]),
        .O(\cas_fifo_valid[3]_i_2_n_0 ));
  FDRE \cas_fifo_valid_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_fifo_valid_nxt[0]),
        .Q(cas_fifo_valid[0]),
        .R(rst_r1));
  FDRE \cas_fifo_valid_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_fifo_valid_nxt[1]),
        .Q(cas_fifo_valid[1]),
        .R(rst_r1));
  FDRE \cas_fifo_valid_reg[2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_fifo_valid_nxt[2]),
        .Q(cas_fifo_valid[2]),
        .R(rst_r1));
  FDRE \cas_fifo_valid_reg[3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_fifo_valid_nxt[3]),
        .Q(cas_fifo_valid[3]),
        .R(rst_r1));
  LUT2 #(
    .INIT(4'h6)) 
    \cas_fifo_wptr[0]_i_1 
       (.I0(cas_fifo_wptr[0]),
        .I1(\cas_fifo_wptr[1]_i_2_n_0 ),
        .O(cas_fifo_wptr_nxt[0]));
  LUT3 #(
    .INIT(8'h6A)) 
    \cas_fifo_wptr[1]_i_1 
       (.I0(cas_fifo_wptr[1]),
        .I1(\cas_fifo_wptr[1]_i_2_n_0 ),
        .I2(cas_fifo_wptr[0]),
        .O(cas_fifo_wptr_nxt[1]));
  LUT6 #(
    .INIT(64'h0000000020A22022)) 
    \cas_fifo_wptr[1]_i_2 
       (.I0(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I1(grSt[1]),
        .I2(grSt[0]),
        .I3(cas_fifo_full),
        .I4(actReqR_reg_0),
        .I5(grSt[2]),
        .O(\cas_fifo_wptr[1]_i_2_n_0 ));
  FDRE \cas_fifo_wptr_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_fifo_wptr_nxt[0]),
        .Q(cas_fifo_wptr[0]),
        .R(rst_r1));
  FDRE \cas_fifo_wptr_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_fifo_wptr_nxt[1]),
        .Q(cas_fifo_wptr[1]),
        .R(rst_r1));
  LUT2 #(
    .INIT(4'h1)) 
    \cas_pend_fifo[0][48]_i_1 
       (.I0(cas_fifo_wptr[1]),
        .I1(cas_fifo_wptr[0]),
        .O(\cas_dbuf_fifo_nxt_reg[0]_276 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cas_pend_fifo[1][48]_i_1 
       (.I0(cas_fifo_wptr[0]),
        .I1(cas_fifo_wptr[1]),
        .O(\cas_dbuf_fifo_nxt_reg[1]_258 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cas_pend_fifo[2][48]_i_1 
       (.I0(cas_fifo_wptr[1]),
        .I1(cas_fifo_wptr[0]),
        .O(\cas_dbuf_fifo_nxt_reg[2]_275 ));
  LUT2 #(
    .INIT(4'h8)) 
    \cas_pend_fifo[3][48]_i_1 
       (.I0(cas_fifo_wptr[1]),
        .I1(cas_fifo_wptr[0]),
        .O(\cas_dbuf_fifo_nxt_reg[3]_277 ));
  FDRE \cas_pend_fifo_reg[0][0] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg[0]_194 [0]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][11] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg[0]_194 [11]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][12] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg[0]_194 [12]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][13] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg[0]_194 [13]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][14] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg[0]_194 [14]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][15] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg[0]_194 [15]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][16] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg[0]_194 [16]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][17] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg[0]_194 [17]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][1] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg[0]_194 [1]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][24] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg[0]_194 [24]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][25] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg[0]_194 [25]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][26] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg[0]_194 [26]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][27] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg[0]_194 [27]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][28] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg[0]_194 [28]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][29] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg[0]_194 [29]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][2] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg[0]_194 [2]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][30] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg[0]_194 [30]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][31] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg[0]_194 [31]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][32] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg[0]_194 [32]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][33] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg[0]_194 [33]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][34] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg[0]_194 [34]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][35] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg[0]_194 [35]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][36] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg[0]_194 [36]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][37] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg[0]_194 [37]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][38] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg[0]_194 [38]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][39] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg[0]_194 [39]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][40] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg[0]_194 [40]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][44] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg[0]_194 [44]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][45] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg[0]_194 [45]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][46] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg[0]_194 [46]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][47] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg[0]_194 [47]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][48] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[0]_276 ),
        .D(\txn_fifo_output_reg_n_0_[48] ),
        .Q(\cas_pend_fifo_reg[0]__0 ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][0] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[0]),
        .Q(p_0_in0_in__0[0]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][11] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][12] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][13] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][14] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][15] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][16] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][17] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][1] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[1]),
        .Q(p_0_in0_in__0[1]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][24] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[1][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][25] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[1][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][26] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[1][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][27] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[1][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][28] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[1][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][29] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[1][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][2] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[1][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][30] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[1][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][31] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[1][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][32] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[1][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][33] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[1][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][34] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[1][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][35] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[1][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][36] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[1][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][37] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[1][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][38] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[1][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][39] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[1][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][40] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[1][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][44] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][45] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][46] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][47] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][47] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][48] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[1]_258 ),
        .D(\txn_fifo_output_reg_n_0_[48] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][48] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][0] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[0]),
        .Q(p_0_in2_in[0]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][11] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][12] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][13] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][14] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][15] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][16] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][17] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][1] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[1]),
        .Q(p_0_in2_in[1]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][24] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[2][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][25] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[2][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][26] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[2][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][27] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[2][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][28] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[2][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][29] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[2][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][2] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[2][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][30] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[2][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][31] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[2][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][32] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[2][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][33] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[2][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][34] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[2][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][35] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[2][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][36] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[2][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][37] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[2][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][38] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[2][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][39] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[2][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][40] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[2][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][44] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][45] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][46] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][47] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][47] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][48] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[2]_275 ),
        .D(\txn_fifo_output_reg_n_0_[48] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][48] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][0] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[0]),
        .Q(p_0_in4_in[0]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][11] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][12] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][13] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][14] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][15] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][16] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][17] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][1] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[1]),
        .Q(p_0_in4_in[1]),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][24] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[3][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][25] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[3][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][26] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[3][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][27] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[3][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][28] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[3][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][29] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[3][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][2] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[3][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][30] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[3][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][31] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[3][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][32] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[3][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][33] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[3][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][34] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[3][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][35] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[3][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][36] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[3][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][37] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[3][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][38] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[3][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][39] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[3][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][40] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[3][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][44] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][45] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][46] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][47] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][47] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][48] 
       (.C(per_rd_accept_reg_0),
        .CE(\cas_dbuf_fifo_nxt_reg[3]_277 ),
        .D(\txn_fifo_output_reg_n_0_[48] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][48] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2526" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    cmdAP_i_1
       (.I0(\txn_fifo_output_reg_n_0_[47] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(cmdAP_i_2_n_0),
        .O(cmd_ap_nxt));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    cmdAP_i_2
       (.I0(\cas_pend_fifo_reg_n_0_[2][47] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][47] ),
        .I2(\cas_pend_fifo_reg[0]_194 [47]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][47] ),
        .O(cmdAP_i_2_n_0));
  FDRE cmdAP_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cmd_ap_nxt),
        .Q(cmdAP),
        .R(rst_r1));
  LUT4 #(
    .INIT(16'h0100)) 
    \cmdBankP[1]_i_1 
       (.I0(\FSM_sequential_grSt[2]_i_5_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_4__0_n_0 ),
        .I2(issue_cas3215_in),
        .I3(\FSM_sequential_grSt[2]_i_6__2_n_0 ),
        .O(set_pre_req));
  FDRE \cmdBankP_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(set_pre_req),
        .D(Q[0]),
        .Q(\cmdBankP_reg[1]_0 [0]),
        .R(rst_r1));
  FDRE \cmdBankP_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(set_pre_req),
        .D(Q[1]),
        .Q(\cmdBankP_reg[1]_0 [1]),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hFFAACCF000AACCF0)) 
    \cmdBuf[0]_i_1 
       (.I0(\cas_dbuf_fifo_reg[1]_200 [0]),
        .I1(\cas_dbuf_fifo_reg[2]_201 [0]),
        .I2(\cas_dbuf_fifo_reg[0]_199 [0]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_dbuf_fifo_reg[3]_202 [0]),
        .O(cmd_buf_nxt[0]));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmdBuf[1]_i_1 
       (.I0(\cas_dbuf_fifo_reg[2]_201 [1]),
        .I1(\cas_dbuf_fifo_reg[3]_202 [1]),
        .I2(\cas_dbuf_fifo_reg[1]_200 [1]),
        .I3(cas_fifo_rptr[0]),
        .I4(cas_fifo_rptr[1]),
        .I5(\cas_dbuf_fifo_reg[0]_199 [1]),
        .O(cmd_buf_nxt[1]));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmdBuf[2]_i_1 
       (.I0(\cas_dbuf_fifo_reg[2]_201 [2]),
        .I1(\cas_dbuf_fifo_reg[3]_202 [2]),
        .I2(\cas_dbuf_fifo_reg[1]_200 [2]),
        .I3(cas_fifo_rptr[0]),
        .I4(cas_fifo_rptr[1]),
        .I5(\cas_dbuf_fifo_reg[0]_199 [2]),
        .O(cmd_buf_nxt[2]));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmdBuf[3]_i_1 
       (.I0(\cas_dbuf_fifo_reg[2]_201 [3]),
        .I1(\cas_dbuf_fifo_reg[3]_202 [3]),
        .I2(\cas_dbuf_fifo_reg[1]_200 [3]),
        .I3(cas_fifo_rptr[0]),
        .I4(cas_fifo_rptr[1]),
        .I5(\cas_dbuf_fifo_reg[0]_199 [3]),
        .O(cmd_buf_nxt[3]));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmdBuf[4]_i_1 
       (.I0(\cas_dbuf_fifo_reg[2]_201 [4]),
        .I1(\cas_dbuf_fifo_reg[3]_202 [4]),
        .I2(\cas_dbuf_fifo_reg[1]_200 [4]),
        .I3(cas_fifo_rptr[0]),
        .I4(cas_fifo_rptr[1]),
        .I5(\cas_dbuf_fifo_reg[0]_199 [4]),
        .O(cmd_buf_nxt[4]));
  FDRE \cmdBuf_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cmd_buf_nxt[0]),
        .Q(cmdBuf[0]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cmd_buf_nxt[1]),
        .Q(cmdBuf[1]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cmd_buf_nxt[2]),
        .Q(cmdBuf[2]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cmd_buf_nxt[3]),
        .Q(cmdBuf[3]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[4] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cmd_buf_nxt[4]),
        .Q(cmdBuf[4]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2529" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[3]_i_1 
       (.I0(\txn_fifo_output_reg_n_0_[11] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[3]_i_2_n_0 ),
        .O(cas_pend_output_col[3]));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmdCol[3]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][11] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][11] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][11] ),
        .I3(cas_fifo_rptr[0]),
        .I4(cas_fifo_rptr[1]),
        .I5(\cas_pend_fifo_reg[0]_194 [11]),
        .O(\cmdCol[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2530" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[4]_i_1 
       (.I0(\txn_fifo_output_reg_n_0_[12] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[4]_i_2_n_0 ),
        .O(cas_pend_output_col[4]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[4]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][12] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][12] ),
        .I2(\cas_pend_fifo_reg[0]_194 [12]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][12] ),
        .O(\cmdCol[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2530" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[5]_i_1 
       (.I0(\txn_fifo_output_reg_n_0_[13] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[5]_i_2_n_0 ),
        .O(cas_pend_output_col[5]));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmdCol[5]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][13] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][13] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][13] ),
        .I3(cas_fifo_rptr[0]),
        .I4(cas_fifo_rptr[1]),
        .I5(\cas_pend_fifo_reg[0]_194 [13]),
        .O(\cmdCol[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2531" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[6]_i_1 
       (.I0(\txn_fifo_output_reg_n_0_[14] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[6]_i_2_n_0 ),
        .O(cas_pend_output_col[6]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[6]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][14] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][14] ),
        .I2(\cas_pend_fifo_reg[0]_194 [14]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][14] ),
        .O(\cmdCol[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2531" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[7]_i_1 
       (.I0(\txn_fifo_output_reg_n_0_[15] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[7]_i_2_n_0 ),
        .O(cas_pend_output_col[7]));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmdCol[7]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][15] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][15] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][15] ),
        .I3(cas_fifo_rptr[0]),
        .I4(cas_fifo_rptr[1]),
        .I5(\cas_pend_fifo_reg[0]_194 [15]),
        .O(\cmdCol[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2532" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[8]_i_1 
       (.I0(\txn_fifo_output_reg_n_0_[16] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[8]_i_2_n_0 ),
        .O(cas_pend_output_col[8]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[8]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][16] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][16] ),
        .I2(\cas_pend_fifo_reg[0]_194 [16]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][16] ),
        .O(\cmdCol[8]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2532" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[9]_i_1 
       (.I0(\txn_fifo_output_reg_n_0_[17] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[9]_i_2_n_0 ),
        .O(cas_pend_output_col[9]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[9]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][17] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][17] ),
        .I2(\cas_pend_fifo_reg[0]_194 [17]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][17] ),
        .O(\cmdCol[9]_i_2_n_0 ));
  FDRE \cmdCol_reg[3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_col[3]),
        .Q(\cmdCol_reg[9]_0 [0]),
        .R(rst_r1));
  FDRE \cmdCol_reg[4] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_col[4]),
        .Q(\cmdCol_reg[9]_0 [1]),
        .R(rst_r1));
  FDRE \cmdCol_reg[5] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_col[5]),
        .Q(\cmdCol_reg[9]_0 [2]),
        .R(rst_r1));
  FDRE \cmdCol_reg[6] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_col[6]),
        .Q(\cmdCol_reg[9]_0 [3]),
        .R(rst_r1));
  FDRE \cmdCol_reg[7] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_col[7]),
        .Q(\cmdCol_reg[9]_0 [4]),
        .R(rst_r1));
  FDRE \cmdCol_reg[8] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_col[8]),
        .Q(\cmdCol_reg[9]_0 [5]),
        .R(rst_r1));
  FDRE \cmdCol_reg[9] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_col[9]),
        .Q(\cmdCol_reg[9]_0 [6]),
        .R(rst_r1));
  FDRE \cmdGroupP_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(set_pre_req),
        .D(Q[2]),
        .Q(cmdGroupP),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2541" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    cmdInjTxn_i_1
       (.I0(\txn_fifo_output_reg_n_0_[48] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(cmdInjTxn_i_2_n_0),
        .O(cmd_inj_txn_nxt));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    cmdInjTxn_i_2
       (.I0(\cas_pend_fifo_reg_n_0_[2][48] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][48] ),
        .I2(\cas_pend_fifo_reg[0]__0 ),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][48] ),
        .O(cmdInjTxn_i_2_n_0));
  FDRE cmdInjTxn_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cmd_inj_txn_nxt),
        .Q(cmdInjTxn),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'h3F2A2A2A2A2A2A2A)) 
    cmdRmw_i_1
       (.I0(cmdRmw_reg_0),
        .I1(\cas_fifo_rptr_reg[0]_0 ),
        .I2(tranSentC),
        .I3(cmdRmw_i_2_n_0),
        .I4(\FSM_sequential_gr_cas_state[2]_i_6_n_0 ),
        .I5(\FSM_sequential_gr_cas_state[2]_i_5__1_n_0 ),
        .O(rd_rmw_nxt));
  (* SOFT_HLUTNM = "soft_lutpair2495" *) 
  LUT3 #(
    .INIT(8'h01)) 
    cmdRmw_i_2
       (.I0(gr_cas_state[2]),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[1]),
        .O(cmdRmw_i_2_n_0));
  FDRE cmdRmw_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(rd_rmw_nxt),
        .Q(cmdRmw_reg_0),
        .R(rst_r1));
  LUT3 #(
    .INIT(8'hE2)) 
    \cmd_bank_cas[0]_i_1 
       (.I0(\cmd_bank_cas[0]_i_2_n_0 ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(Q[0]),
        .O(\cmd_bank_cas[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCF0AA00CCF0AA)) 
    \cmd_bank_cas[0]_i_2 
       (.I0(\cas_pend_fifo_reg[0]_194 [0]),
        .I1(p_0_in0_in__0[0]),
        .I2(p_0_in2_in[0]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(p_0_in4_in[0]),
        .O(\cmd_bank_cas[0]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hC5)) 
    \cmd_bank_cas[1]_i_1 
       (.I0(\cmd_bank_cas[1]_i_2_n_0 ),
        .I1(Q[1]),
        .I2(cas_fifo_empty_reg_n_0),
        .O(\cmd_bank_cas[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    \cmd_bank_cas[1]_i_2 
       (.I0(p_0_in0_in__0[1]),
        .I1(\cas_pend_fifo_reg[0]_194 [1]),
        .I2(p_0_in2_in[1]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(p_0_in4_in[1]),
        .O(\cmd_bank_cas[1]_i_2_n_0 ));
  FDRE \cmd_bank_cas_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\cmd_bank_cas[0]_i_1_n_0 ),
        .Q(\cmd_bank_cas_reg[1]_0 [0]),
        .R(rst_r1));
  FDRE \cmd_bank_cas_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\cmd_bank_cas[1]_i_1_n_0 ),
        .Q(\cmd_bank_cas_reg[1]_0 [1]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2529" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_group_cas[0]_i_1 
       (.I0(Q[2]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_group_cas[0]_i_2_n_0 ),
        .O(cmd_group_cas_nxt));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_group_cas[0]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][2] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][2] ),
        .I2(\cas_pend_fifo_reg[0]_194 [2]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][2] ),
        .O(\cmd_group_cas[0]_i_2_n_0 ));
  FDRE \cmd_group_cas_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cmd_group_cas_nxt),
        .Q(cmd_group_cas),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2533" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[0]_i_1 
       (.I0(Q[3]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[0]_i_2_n_0 ),
        .O(cas_pend_output_row[0]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[0]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][24] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][24] ),
        .I2(\cas_pend_fifo_reg[0]_194 [24]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][24] ),
        .O(\cmd_row_cas[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2538" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[10]_i_1 
       (.I0(Q[13]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[10]_i_2_n_0 ),
        .O(cas_pend_output_row[10]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[10]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][34] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][34] ),
        .I2(\cas_pend_fifo_reg[0]_194 [34]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][34] ),
        .O(\cmd_row_cas[10]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2538" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[11]_i_1 
       (.I0(Q[14]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[11]_i_2_n_0 ),
        .O(cas_pend_output_row[11]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[11]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][35] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][35] ),
        .I2(\cas_pend_fifo_reg[0]_194 [35]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][35] ),
        .O(\cmd_row_cas[11]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2539" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[12]_i_1 
       (.I0(Q[15]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[12]_i_2_n_0 ),
        .O(cas_pend_output_row[12]));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmd_row_cas[12]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][36] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][36] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][36] ),
        .I3(cas_fifo_rptr[0]),
        .I4(cas_fifo_rptr[1]),
        .I5(\cas_pend_fifo_reg[0]_194 [36]),
        .O(\cmd_row_cas[12]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2539" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[13]_i_1 
       (.I0(Q[16]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[13]_i_2_n_0 ),
        .O(cas_pend_output_row[13]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[13]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][37] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][37] ),
        .I2(\cas_pend_fifo_reg[0]_194 [37]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][37] ),
        .O(\cmd_row_cas[13]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2540" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[14]_i_1 
       (.I0(Q[17]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[14]_i_2_n_0 ),
        .O(cas_pend_output_row[14]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[14]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][38] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][38] ),
        .I2(\cas_pend_fifo_reg[0]_194 [38]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][38] ),
        .O(\cmd_row_cas[14]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2540" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[15]_i_1 
       (.I0(Q[18]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[15]_i_2_n_0 ),
        .O(cas_pend_output_row[15]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[15]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][39] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][39] ),
        .I2(\cas_pend_fifo_reg[0]_194 [39]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][39] ),
        .O(\cmd_row_cas[15]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2541" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[16]_i_1 
       (.I0(Q[19]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[16]_i_2_n_0 ),
        .O(cas_pend_output_row[16]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[16]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][40] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][40] ),
        .I2(\cas_pend_fifo_reg[0]_194 [40]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][40] ),
        .O(\cmd_row_cas[16]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2533" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[1]_i_1 
       (.I0(Q[4]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[1]_i_2_n_0 ),
        .O(cas_pend_output_row[1]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[1]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][25] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][25] ),
        .I2(\cas_pend_fifo_reg[0]_194 [25]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][25] ),
        .O(\cmd_row_cas[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2534" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[2]_i_1 
       (.I0(Q[5]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[2]_i_2_n_0 ),
        .O(cas_pend_output_row[2]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[2]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][26] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][26] ),
        .I2(\cas_pend_fifo_reg[0]_194 [26]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][26] ),
        .O(\cmd_row_cas[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2534" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[3]_i_1 
       (.I0(Q[6]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[3]_i_2_n_0 ),
        .O(cas_pend_output_row[3]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[3]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][27] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][27] ),
        .I2(\cas_pend_fifo_reg[0]_194 [27]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][27] ),
        .O(\cmd_row_cas[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2535" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[4]_i_1 
       (.I0(Q[7]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[4]_i_2_n_0 ),
        .O(cas_pend_output_row[4]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[4]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][28] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][28] ),
        .I2(\cas_pend_fifo_reg[0]_194 [28]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][28] ),
        .O(\cmd_row_cas[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2535" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[5]_i_1 
       (.I0(Q[8]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[5]_i_2_n_0 ),
        .O(cas_pend_output_row[5]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[5]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][29] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][29] ),
        .I2(\cas_pend_fifo_reg[0]_194 [29]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][29] ),
        .O(\cmd_row_cas[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2536" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[6]_i_1 
       (.I0(Q[9]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[6]_i_2_n_0 ),
        .O(cas_pend_output_row[6]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[6]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][30] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][30] ),
        .I2(\cas_pend_fifo_reg[0]_194 [30]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][30] ),
        .O(\cmd_row_cas[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2536" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[7]_i_1 
       (.I0(Q[10]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[7]_i_2_n_0 ),
        .O(cas_pend_output_row[7]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[7]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][31] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][31] ),
        .I2(\cas_pend_fifo_reg[0]_194 [31]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][31] ),
        .O(\cmd_row_cas[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2537" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[8]_i_1 
       (.I0(Q[11]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[8]_i_2_n_0 ),
        .O(cas_pend_output_row[8]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[8]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][32] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][32] ),
        .I2(\cas_pend_fifo_reg[0]_194 [32]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][32] ),
        .O(\cmd_row_cas[8]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2537" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[9]_i_1 
       (.I0(Q[12]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[9]_i_2_n_0 ),
        .O(cas_pend_output_row[9]));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[9]_i_2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][33] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][33] ),
        .I2(\cas_pend_fifo_reg[0]_194 [33]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][33] ),
        .O(\cmd_row_cas[9]_i_2_n_0 ));
  FDRE \cmd_row_cas_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[0]),
        .Q(data0[2]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[10] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[10]),
        .Q(data0[12]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[11] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[11]),
        .Q(data0[13]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[12] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[12]),
        .Q(data0[14]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[13] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[13]),
        .Q(data0[15]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[14] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[14]),
        .Q(data0[16]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[15] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[15]),
        .Q(data0[17]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[16] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[16]),
        .Q(data0[18]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[1]),
        .Q(data0[3]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[2]),
        .Q(data0[4]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[3]),
        .Q(data0[5]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[4] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[4]),
        .Q(data0[6]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[5] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[5]),
        .Q(data0[7]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[6] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[6]),
        .Q(data0[8]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[7] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[7]),
        .Q(data0[9]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[8] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[8]),
        .Q(data0[10]),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[9] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(cas_pend_output_row[9]),
        .Q(data0[11]),
        .R(rst_r1));
  LUT4 #(
    .INIT(16'h6006)) 
    i__carry_i_1
       (.I0(i__carry_i_7_n_0),
        .I1(Q[18]),
        .I2(i__carry_i_8_n_0),
        .I3(Q[19]),
        .O(i__carry_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFACF0AC0FAC00AC)) 
    i__carry_i_10
       (.I0(\pageInfo_reg[0][0][1]_225 [16]),
        .I1(\pageInfo_reg[0][0][0]_226 [16]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(\pageInfo_reg[0][0][2]_224 [16]),
        .I5(\pageInfo_reg[0][0][3]_223 [16]),
        .O(i__carry_i_10_n_0));
  LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
    i__carry_i_11
       (.I0(\pageInfo_reg[0][0][2]_224 [14]),
        .I1(\pageInfo_reg[0][0][3]_223 [14]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][0]_226 [14]),
        .I5(\pageInfo_reg[0][0][1]_225 [14]),
        .O(i__carry_i_11_n_0));
  LUT6 #(
    .INIT(64'h0035F0350F35FF35)) 
    i__carry_i_12
       (.I0(\pageInfo_reg[0][0][0]_226 [13]),
        .I1(\pageInfo_reg[0][0][2]_224 [13]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][3]_223 [13]),
        .I5(\pageInfo_reg[0][0][1]_225 [13]),
        .O(i__carry_i_12_n_0));
  LUT6 #(
    .INIT(64'hFCFA0CFAFC0A0C0A)) 
    i__carry_i_13
       (.I0(\pageInfo_reg[0][0][0]_226 [11]),
        .I1(\pageInfo_reg[0][0][1]_225 [11]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][3]_223 [11]),
        .I5(\pageInfo_reg[0][0][2]_224 [11]),
        .O(i__carry_i_13_n_0));
  LUT6 #(
    .INIT(64'hCFAFC0AFCFA0C0A0)) 
    i__carry_i_14
       (.I0(\pageInfo_reg[0][0][2]_224 [12]),
        .I1(\pageInfo_reg[0][0][3]_223 [12]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][1]_225 [12]),
        .I5(\pageInfo_reg[0][0][0]_226 [12]),
        .O(i__carry_i_14_n_0));
  LUT6 #(
    .INIT(64'h0350035FF350F35F)) 
    i__carry_i_15
       (.I0(\pageInfo_reg[0][0][2]_224 [10]),
        .I1(\pageInfo_reg[0][0][1]_225 [10]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][0]_226 [10]),
        .I5(\pageInfo_reg[0][0][3]_223 [10]),
        .O(i__carry_i_15_n_0));
  LUT6 #(
    .INIT(64'hCFAFC0AFCFA0C0A0)) 
    i__carry_i_16
       (.I0(\pageInfo_reg[0][0][2]_224 [9]),
        .I1(\pageInfo_reg[0][0][3]_223 [9]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][1]_225 [9]),
        .I5(\pageInfo_reg[0][0][0]_226 [9]),
        .O(i__carry_i_16_n_0));
  LUT6 #(
    .INIT(64'hFFCA0FCAF0CA00CA)) 
    i__carry_i_17
       (.I0(\pageInfo_reg[0][0][0]_226 [8]),
        .I1(\pageInfo_reg[0][0][2]_224 [8]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][3]_223 [8]),
        .I5(\pageInfo_reg[0][0][1]_225 [8]),
        .O(i__carry_i_17_n_0));
  LUT6 #(
    .INIT(64'h30503F50305F3F5F)) 
    i__carry_i_18
       (.I0(\pageInfo_reg[0][0][2]_224 [7]),
        .I1(\pageInfo_reg[0][0][3]_223 [7]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][1]_225 [7]),
        .I5(\pageInfo_reg[0][0][0]_226 [7]),
        .O(i__carry_i_18_n_0));
  LUT6 #(
    .INIT(64'hCFAFC0AFCFA0C0A0)) 
    i__carry_i_19
       (.I0(\pageInfo_reg[0][0][2]_224 [6]),
        .I1(\pageInfo_reg[0][0][3]_223 [6]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][1]_225 [6]),
        .I5(\pageInfo_reg[0][0][0]_226 [6]),
        .O(i__carry_i_19_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_2
       (.I0(i__carry_i_9_n_0),
        .I1(Q[16]),
        .I2(Q[17]),
        .I3(i__carry_i_10_n_0),
        .I4(Q[15]),
        .I5(i__carry_i_11_n_0),
        .O(i__carry_i_2_n_0));
  LUT6 #(
    .INIT(64'hFACF0ACFFAC00AC0)) 
    i__carry_i_20
       (.I0(\pageInfo_reg[0][0][1]_225 [5]),
        .I1(\pageInfo_reg[0][0][2]_224 [5]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][3]_223 [5]),
        .I5(\pageInfo_reg[0][0][0]_226 [5]),
        .O(i__carry_i_20_n_0));
  LUT6 #(
    .INIT(64'h00530F53F053FF53)) 
    i__carry_i_21
       (.I0(\pageInfo_reg[0][0][2]_224 [4]),
        .I1(\pageInfo_reg[0][0][0]_226 [4]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][1]_225 [4]),
        .I5(\pageInfo_reg[0][0][3]_223 [4]),
        .O(i__carry_i_21_n_0));
  LUT6 #(
    .INIT(64'hFFACF0AC0FAC00AC)) 
    i__carry_i_22
       (.I0(\pageInfo_reg[0][0][2]_224 [2]),
        .I1(\pageInfo_reg[0][0][0]_226 [2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][1]_225 [2]),
        .I5(\pageInfo_reg[0][0][3]_223 [2]),
        .O(i__carry_i_22_n_0));
  LUT6 #(
    .INIT(64'hAFCFA0CFAFC0A0C0)) 
    i__carry_i_23
       (.I0(\pageInfo_reg[0][0][3]_223 [3]),
        .I1(\pageInfo_reg[0][0][2]_224 [3]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][1]_225 [3]),
        .I5(\pageInfo_reg[0][0][0]_226 [3]),
        .O(i__carry_i_23_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_3
       (.I0(i__carry_i_12_n_0),
        .I1(Q[14]),
        .I2(Q[12]),
        .I3(i__carry_i_13_n_0),
        .I4(Q[13]),
        .I5(i__carry_i_14_n_0),
        .O(i__carry_i_3_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_4
       (.I0(i__carry_i_15_n_0),
        .I1(Q[11]),
        .I2(Q[10]),
        .I3(i__carry_i_16_n_0),
        .I4(Q[9]),
        .I5(i__carry_i_17_n_0),
        .O(i__carry_i_4_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_5
       (.I0(i__carry_i_18_n_0),
        .I1(Q[8]),
        .I2(Q[7]),
        .I3(i__carry_i_19_n_0),
        .I4(Q[6]),
        .I5(i__carry_i_20_n_0),
        .O(i__carry_i_5_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_6
       (.I0(i__carry_i_21_n_0),
        .I1(Q[5]),
        .I2(Q[3]),
        .I3(i__carry_i_22_n_0),
        .I4(Q[4]),
        .I5(i__carry_i_23_n_0),
        .O(i__carry_i_6_n_0));
  LUT6 #(
    .INIT(64'h0305F30503F5F3F5)) 
    i__carry_i_7
       (.I0(\pageInfo_reg[0][0][0]_226 [17]),
        .I1(\pageInfo_reg[0][0][1]_225 [17]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][3]_223 [17]),
        .I5(\pageInfo_reg[0][0][2]_224 [17]),
        .O(i__carry_i_7_n_0));
  LUT6 #(
    .INIT(64'hACFFACF0AC0FAC00)) 
    i__carry_i_8
       (.I0(\pageInfo_reg[0][0][3]_223 [18]),
        .I1(\pageInfo_reg[0][0][1]_225 [18]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][0]_226 [18]),
        .I5(\pageInfo_reg[0][0][2]_224 [18]),
        .O(i__carry_i_8_n_0));
  LUT6 #(
    .INIT(64'h00530F53F053FF53)) 
    i__carry_i_9
       (.I0(\pageInfo_reg[0][0][2]_224 [15]),
        .I1(\pageInfo_reg[0][0][0]_226 [15]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][1]_225 [15]),
        .I5(\pageInfo_reg[0][0][3]_223 [15]),
        .O(i__carry_i_9_n_0));
  CARRY8 \issue_cas3_inferred__0/i__carry 
       (.CI(1'b1),
        .CI_TOP(1'b0),
        .CO({\NLW_issue_cas3_inferred__0/i__carry_CO_UNCONNECTED [7:6],issue_cas3215_in,\issue_cas3_inferred__0/i__carry_n_3 ,\issue_cas3_inferred__0/i__carry_n_4 ,\issue_cas3_inferred__0/i__carry_n_5 ,\issue_cas3_inferred__0/i__carry_n_6 ,\issue_cas3_inferred__0/i__carry_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O(\NLW_issue_cas3_inferred__0/i__carry_O_UNCONNECTED [7:0]),
        .S({1'b0,1'b0,i__carry_i_1_n_0,i__carry_i_2_n_0,i__carry_i_3_n_0,i__carry_i_4_n_0,i__carry_i_5_n_0,i__carry_i_6_n_0}));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \pageInfo[0][0][0][0]_i_1 
       (.I0(\pageInfo[0][0][0][0]_i_2_n_0 ),
        .I1(\pageInfo[0][0][0][0]_i_3_n_0 ),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .I4(grSt[0]),
        .I5(sel0__14),
        .O(\pageInfo[0][0][0][0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][0][0]_i_2 
       (.I0(rst_r1),
        .I1(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .O(\pageInfo[0][0][0][0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2543" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][0][0]_i_3 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\pageInfo[0][0][0][0]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][10]_i_1 
       (.I0(data0[10]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[11]),
        .O(\pageInfo[0][0][0][10]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][11]_i_1 
       (.I0(data0[11]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][0][11]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][12]_i_1 
       (.I0(data0[12]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][0][12]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][13]_i_1 
       (.I0(data0[13]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][0][13]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][14]_i_1 
       (.I0(data0[14]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][0][14]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][15]_i_1 
       (.I0(data0[15]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][0][15]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][16]_i_1 
       (.I0(data0[16]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[17]),
        .O(\pageInfo[0][0][0][16]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][17]_i_1 
       (.I0(data0[17]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][0][17]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][0][18]_i_1 
       (.I0(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I1(sel0__14),
        .I2(\trcd_cntr[0][0][0][2]_i_2_n_0 ),
        .I3(\pageInfo[0][0][3][18]_i_3_n_0 ),
        .O(\pageInfo[0][0][0][18]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][18]_i_2 
       (.I0(data0[18]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][0][18]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][0][1]_i_1 
       (.I0(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][0][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][2]_i_1 
       (.I0(data0[2]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[3]),
        .O(\pageInfo[0][0][0][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][3]_i_1 
       (.I0(data0[3]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][0][3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][4]_i_1 
       (.I0(data0[4]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[5]),
        .O(\pageInfo[0][0][0][4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][5]_i_1 
       (.I0(data0[5]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[6]),
        .O(\pageInfo[0][0][0][5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][6]_i_1 
       (.I0(data0[6]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[7]),
        .O(\pageInfo[0][0][0][6]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][7]_i_1 
       (.I0(data0[7]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[8]),
        .O(\pageInfo[0][0][0][7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][8]_i_1 
       (.I0(data0[8]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][0][8]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][9]_i_1 
       (.I0(data0[9]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][0][9]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \pageInfo[0][0][1][0]_i_1 
       (.I0(\pageInfo[0][0][1][0]_i_2_n_0 ),
        .I1(\pageInfo[0][0][1][0]_i_3_n_0 ),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .I4(grSt[0]),
        .I5(sel0__10),
        .O(\pageInfo[0][0][1][0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][1][0]_i_2 
       (.I0(rst_r1),
        .I1(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .O(\pageInfo[0][0][1][0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2542" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][1][0]_i_3 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\pageInfo[0][0][1][0]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][10]_i_1 
       (.I0(data0[10]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[11]),
        .O(\pageInfo[0][0][1][10]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][11]_i_1 
       (.I0(data0[11]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][1][11]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][12]_i_1 
       (.I0(data0[12]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][1][12]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][13]_i_1 
       (.I0(data0[13]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][1][13]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][14]_i_1 
       (.I0(data0[14]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][1][14]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][15]_i_1 
       (.I0(data0[15]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][1][15]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][16]_i_1 
       (.I0(data0[16]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[17]),
        .O(\pageInfo[0][0][1][16]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][17]_i_1 
       (.I0(data0[17]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][1][17]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][1][18]_i_1 
       (.I0(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I1(sel0__10),
        .I2(\trcd_cntr[0][0][1][2]_i_2_n_0 ),
        .I3(\pageInfo[0][0][3][18]_i_3_n_0 ),
        .O(\pageInfo[0][0][1][18]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][18]_i_2 
       (.I0(data0[18]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][1][18]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][1][1]_i_1 
       (.I0(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][1][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][2]_i_1 
       (.I0(data0[2]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[3]),
        .O(\pageInfo[0][0][1][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][3]_i_1 
       (.I0(data0[3]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][1][3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][4]_i_1 
       (.I0(data0[4]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[5]),
        .O(\pageInfo[0][0][1][4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][5]_i_1 
       (.I0(data0[5]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[6]),
        .O(\pageInfo[0][0][1][5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][6]_i_1 
       (.I0(data0[6]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[7]),
        .O(\pageInfo[0][0][1][6]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][7]_i_1 
       (.I0(data0[7]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[8]),
        .O(\pageInfo[0][0][1][7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][8]_i_1 
       (.I0(data0[8]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][1][8]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][9]_i_1 
       (.I0(data0[9]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][1][9]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \pageInfo[0][0][2][0]_i_1 
       (.I0(\pageInfo[0][0][2][0]_i_2_n_0 ),
        .I1(\pageInfo[0][0][2][0]_i_3_n_0 ),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .I4(grSt[0]),
        .I5(sel0__6),
        .O(\pageInfo[0][0][2][0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][2][0]_i_2 
       (.I0(rst_r1),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .O(\pageInfo[0][0][2][0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2543" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][2][0]_i_3 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\pageInfo[0][0][2][0]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][10]_i_1 
       (.I0(Q[11]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(rst_r1),
        .I3(data0[10]),
        .O(\pageInfo[0][0][2][10]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][11]_i_1 
       (.I0(data0[11]),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][2][11]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][12]_i_1 
       (.I0(data0[12]),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][2][12]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][13]_i_1 
       (.I0(data0[13]),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][2][13]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][14]_i_1 
       (.I0(Q[15]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(rst_r1),
        .I3(data0[14]),
        .O(\pageInfo[0][0][2][14]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][15]_i_1 
       (.I0(Q[16]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(rst_r1),
        .I3(data0[15]),
        .O(\pageInfo[0][0][2][15]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][16]_i_1 
       (.I0(data0[16]),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I3(Q[17]),
        .O(\pageInfo[0][0][2][16]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][17]_i_1 
       (.I0(data0[17]),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][2][17]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][2][18]_i_1 
       (.I0(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I1(sel0__6),
        .I2(\trcd_cntr[0][0][2][2]_i_2_n_0 ),
        .I3(\pageInfo[0][0][3][18]_i_3_n_0 ),
        .O(\pageInfo[0][0][2][18]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][18]_i_2 
       (.I0(Q[19]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(rst_r1),
        .I3(data0[18]),
        .O(\pageInfo[0][0][2][18]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][2][1]_i_1 
       (.I0(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][2][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][2]_i_1 
       (.I0(Q[3]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(rst_r1),
        .I3(data0[2]),
        .O(\pageInfo[0][0][2][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][3]_i_1 
       (.I0(Q[4]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(rst_r1),
        .I3(data0[3]),
        .O(\pageInfo[0][0][2][3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][4]_i_1 
       (.I0(data0[4]),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I3(Q[5]),
        .O(\pageInfo[0][0][2][4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][5]_i_1 
       (.I0(Q[6]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(rst_r1),
        .I3(data0[5]),
        .O(\pageInfo[0][0][2][5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][6]_i_1 
       (.I0(Q[7]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(rst_r1),
        .I3(data0[6]),
        .O(\pageInfo[0][0][2][6]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][7]_i_1 
       (.I0(Q[8]),
        .I1(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I2(rst_r1),
        .I3(data0[7]),
        .O(\pageInfo[0][0][2][7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][8]_i_1 
       (.I0(data0[8]),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][2][8]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][9]_i_1 
       (.I0(data0[9]),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][2]_i_2_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][2][9]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \pageInfo[0][0][3][0]_i_1 
       (.I0(\pageInfo[0][0][3][0]_i_2_n_0 ),
        .I1(\trp_cntr[1]_i_2_n_0 ),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .I4(grSt[0]),
        .I5(sel0__2),
        .O(\pageInfo[0][0][3][0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][3][0]_i_2 
       (.I0(rst_r1),
        .I1(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .O(\pageInfo[0][0][3][0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][10]_i_1 
       (.I0(data0[10]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[11]),
        .O(\pageInfo[0][0][3][10]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][11]_i_1 
       (.I0(data0[11]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][3][11]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][12]_i_1 
       (.I0(data0[12]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][3][12]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][13]_i_1 
       (.I0(data0[13]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][3][13]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][14]_i_1 
       (.I0(data0[14]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][3][14]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][15]_i_1 
       (.I0(data0[15]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][3][15]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][16]_i_1 
       (.I0(data0[16]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[17]),
        .O(\pageInfo[0][0][3][16]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][17]_i_1 
       (.I0(data0[17]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][3][17]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][3][18]_i_1 
       (.I0(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I1(sel0__2),
        .I2(\trcd_cntr[0][0][3][2]_i_2_n_0 ),
        .I3(\pageInfo[0][0][3][18]_i_3_n_0 ),
        .O(\pageInfo[0][0][3][18]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][18]_i_2 
       (.I0(data0[18]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][3][18]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAEAAAAAAAAAAAAA)) 
    \pageInfo[0][0][3][18]_i_3 
       (.I0(rst_r1),
        .I1(refOK),
        .I2(refReq),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(grSt[1]),
        .O(\pageInfo[0][0][3][18]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][3][1]_i_1 
       (.I0(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][3][1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][2]_i_1 
       (.I0(data0[2]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[3]),
        .O(\pageInfo[0][0][3][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][3]_i_1 
       (.I0(data0[3]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][3][3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][4]_i_1 
       (.I0(data0[4]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[5]),
        .O(\pageInfo[0][0][3][4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][5]_i_1 
       (.I0(data0[5]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[6]),
        .O(\pageInfo[0][0][3][5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][6]_i_1 
       (.I0(data0[6]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[7]),
        .O(\pageInfo[0][0][3][6]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][7]_i_1 
       (.I0(data0[7]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[8]),
        .O(\pageInfo[0][0][3][7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][8]_i_1 
       (.I0(data0[8]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][3][8]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][9]_i_1 
       (.I0(data0[9]),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][3][9]_i_1_n_0 ));
  FDRE \pageInfo_reg[0][0][0][0] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][0]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [0]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][10] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][10]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [10]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][11] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][11]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [11]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][12] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][12]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [12]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][13] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][13]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [13]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][14] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][14]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [14]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][15] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][15]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [15]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][16] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][16]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [16]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][17] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][17]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [17]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][18] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][18]_i_2_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [18]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][1] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][1]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [1]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][2] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][2]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [2]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][3] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][3]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [3]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][4] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][4]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [4]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][5] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][5]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [5]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][6] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][6]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [6]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][7] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][7]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [7]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][8] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][8]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [8]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][9] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][0][9]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][0]_226 [9]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][0] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][0]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [0]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][10] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][10]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [10]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][11] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][11]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [11]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][12] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][12]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [12]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][13] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][13]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [13]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][14] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][14]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [14]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][15] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][15]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [15]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][16] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][16]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [16]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][17] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][17]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [17]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][18] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][18]_i_2_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [18]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][1] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][1]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [1]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][2] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][2]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [2]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][3] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][3]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [3]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][4] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][4]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [4]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][5] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][5]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [5]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][6] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][6]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [6]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][7] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][7]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [7]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][8] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][8]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [8]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][9] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][1][9]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][1]_225 [9]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][0] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][0]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [0]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][10] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][10]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [10]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][11] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][11]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [11]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][12] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][12]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [12]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][13] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][13]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [13]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][14] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][14]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [14]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][15] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][15]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [15]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][16] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][16]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [16]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][17] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][17]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [17]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][18] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][18]_i_2_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [18]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][1] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][1]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [1]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][2] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][2]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [2]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][3] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][3]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [3]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][4] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][4]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [4]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][5] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][5]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [5]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][6] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][6]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [6]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][7] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][7]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [7]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][8] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][8]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [8]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][9] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][2][9]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][2]_224 [9]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][0] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][0]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [0]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][10] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][10]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [10]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][11] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][11]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [11]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][12] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][12]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [12]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][13] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][13]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [13]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][14] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][14]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [14]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][15] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][15]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [15]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][16] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][16]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [16]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][17] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][17]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [17]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][18] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][18]_i_2_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [18]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][1] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][1]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [1]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][2] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][2]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [2]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][3] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][3]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [3]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][4] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][4]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [4]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][5] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][5]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [5]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][6] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][6]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [6]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][7] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][7]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [7]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][8] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][8]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [8]),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][9] 
       (.C(per_rd_accept_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1_n_0 ),
        .D(\pageInfo[0][0][3][9]_i_1_n_0 ),
        .Q(\pageInfo_reg[0][0][3]_223 [9]),
        .R(1'b0));
  FDRE per_rd_accept_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(select_periodic_read),
        .Q(per_rd_accept_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hF0F0F0F0F0F0F0F2)) 
    \periodic_read_address[40]_i_1 
       (.I0(\FSM_sequential_grSt[2]_i_4__0_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_5_n_0 ),
        .I2(\periodic_read_address[40]_i_2_n_0 ),
        .I3(\periodic_read_address[40]_i_3_n_0 ),
        .I4(grSt[2]),
        .I5(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .O(set_act_req));
  LUT4 #(
    .INIT(16'h0020)) 
    \periodic_read_address[40]_i_2 
       (.I0(trp_cntr_is_zero),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .O(\periodic_read_address[40]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFCA0FCAF0CA00CA)) 
    \periodic_read_address[40]_i_3 
       (.I0(\pageInfo_reg[0][0][0]_226 [1]),
        .I1(\pageInfo_reg[0][0][2]_224 [1]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\pageInfo_reg[0][0][3]_223 [1]),
        .I5(\pageInfo_reg[0][0][1]_225 [1]),
        .O(\periodic_read_address[40]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \periodic_read_address[44]_i_1 
       (.I0(rst_r1),
        .I1(\periodic_read_address_reg_n_0_[44] ),
        .I2(set_act_req),
        .O(\periodic_read_address[44]_i_1_n_0 ));
  FDRE \periodic_read_address_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[0]),
        .Q(\periodic_read_address_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[11] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\periodic_read_address_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[12] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\periodic_read_address_reg_n_0_[12] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[13] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\periodic_read_address_reg_n_0_[13] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[14] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\periodic_read_address_reg_n_0_[14] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[15] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\periodic_read_address_reg_n_0_[15] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[16] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\periodic_read_address_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[17] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\periodic_read_address_reg_n_0_[17] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[1]),
        .Q(\periodic_read_address_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[24] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[3]),
        .Q(\periodic_read_address_reg_n_0_[24] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[25] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[4]),
        .Q(\periodic_read_address_reg_n_0_[25] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[26] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[5]),
        .Q(\periodic_read_address_reg_n_0_[26] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[27] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[6]),
        .Q(\periodic_read_address_reg_n_0_[27] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[28] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[7]),
        .Q(\periodic_read_address_reg_n_0_[28] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[29] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[8]),
        .Q(\periodic_read_address_reg_n_0_[29] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[2] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[2]),
        .Q(\periodic_read_address_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[30] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[9]),
        .Q(\periodic_read_address_reg_n_0_[30] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[31] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[10]),
        .Q(\periodic_read_address_reg_n_0_[31] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[32] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[11]),
        .Q(\periodic_read_address_reg_n_0_[32] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[33] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[12]),
        .Q(\periodic_read_address_reg_n_0_[33] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[34] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[13]),
        .Q(\periodic_read_address_reg_n_0_[34] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[35] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[14]),
        .Q(\periodic_read_address_reg_n_0_[35] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[36] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[15]),
        .Q(\periodic_read_address_reg_n_0_[36] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[37] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[16]),
        .Q(\periodic_read_address_reg_n_0_[37] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[38] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[17]),
        .Q(\periodic_read_address_reg_n_0_[38] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[39] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[18]),
        .Q(\periodic_read_address_reg_n_0_[39] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[40] 
       (.C(per_rd_accept_reg_0),
        .CE(set_act_req),
        .D(Q[19]),
        .Q(\periodic_read_address_reg_n_0_[40] ),
        .R(rst_r1));
  FDRE \periodic_read_address_reg[44] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\periodic_read_address[44]_i_1_n_0 ),
        .Q(\periodic_read_address_reg_n_0_[44] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2523" *) 
  LUT2 #(
    .INIT(4'h2)) 
    periodic_read_block_dly1_i_1
       (.I0(periodic_read_block),
        .I1(select_periodic_read),
        .O(periodic_read_block_dly1_nxt));
  FDRE periodic_read_block_dly1_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(periodic_read_block_dly1_nxt),
        .Q(periodic_read_block_dly1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2545" *) 
  LUT2 #(
    .INIT(4'h2)) 
    periodic_read_block_dly2_i_1
       (.I0(periodic_read_block_dly1),
        .I1(select_periodic_read),
        .O(periodic_read_block_dly2_nxt));
  FDRE periodic_read_block_dly2_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(periodic_read_block_dly2_nxt),
        .Q(periodic_read_block_dly2),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2545" *) 
  LUT2 #(
    .INIT(4'h2)) 
    periodic_read_block_dly3_i_1
       (.I0(periodic_read_block_dly2),
        .I1(select_periodic_read),
        .O(periodic_read_block_dly3_nxt));
  FDRE periodic_read_block_dly3_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(periodic_read_block_dly3_nxt),
        .Q(periodic_read_block_dly3),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h32)) 
    periodic_read_block_i_1
       (.I0(periodic_read_block),
        .I1(select_periodic_read),
        .I2(per_rd_req),
        .O(periodic_read_block_nxt));
  FDRE periodic_read_block_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(periodic_read_block_nxt),
        .Q(periodic_read_block),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2523" *) 
  LUT4 #(
    .INIT(16'hFFF4)) 
    periodic_read_or_ref_block_i_1
       (.I0(select_periodic_read),
        .I1(per_rd_req),
        .I2(refReq),
        .I3(periodic_read_block),
        .O(periodic_read_or_ref_block_nxt));
  FDRE periodic_read_or_ref_block_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(periodic_read_or_ref_block_nxt),
        .Q(periodic_read_or_ref_block),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    periodic_read_push_safe_i_1
       (.I0(periodic_read_block_dly3),
        .I1(txn_fifo_full),
        .O(p_219_in));
  FDRE periodic_read_push_safe_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(p_219_in),
        .Q(periodic_read_push_safe),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFF0100)) 
    preReqR_i_1__2
       (.I0(\FSM_sequential_grSt[2]_i_5_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_4__0_n_0 ),
        .I2(issue_cas3215_in),
        .I3(\FSM_sequential_grSt[2]_i_6__2_n_0 ),
        .I4(preReqR),
        .I5(\FSM_sequential_grSt_reg[0]_0 ),
        .O(pre_req_nxt));
  FDRE preReqR_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(pre_req_nxt),
        .Q(preReqR),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'h00FFFFFF00404040)) 
    rdReqR_i_1
       (.I0(gr_cas_state[1]),
        .I1(rdReqR_i_2_n_0),
        .I2(\FSM_sequential_gr_cas_state[2]_i_5__1_n_0 ),
        .I3(tranSentC),
        .I4(\cas_fifo_rptr_reg[0]_0 ),
        .I5(rdReqR),
        .O(rd_req_nxt));
  LUT2 #(
    .INIT(4'h1)) 
    rdReqR_i_2
       (.I0(gr_cas_state[0]),
        .I1(gr_cas_state[2]),
        .O(rdReqR_i_2_n_0));
  FDRE rdReqR_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(rd_req_nxt),
        .Q(rdReqR),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h08000000)) 
    refOK_i_1
       (.I0(grSt[1]),
        .I1(grSt[2]),
        .I2(grSt[0]),
        .I3(ref_req_dly4),
        .I4(cas_fifo_empty_reg_n_0),
        .O(ref_ok_nxt));
  FDRE refOK_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(ref_ok_nxt),
        .Q(refOK),
        .R(1'b0));
  SRL16E ref_req_dly3_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(per_rd_accept_reg_0),
        .D(ref_req_dly4_reg_1),
        .Q(ref_req_dly3_reg_srl2_n_0));
  FDRE ref_req_dly4_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(ref_req_dly3_reg_srl2_n_0),
        .Q(ref_req_dly4),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE rst_r1_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(SR),
        .Q(rst_r1),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h04)) 
    select_periodic_read_i_1
       (.I0(txn_fifo_full),
        .I1(periodic_read_block_dly3),
        .I2(periodic_read_push_safe),
        .O(select_periodic_read_nxt));
  FDRE select_periodic_read_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(select_periodic_read_nxt),
        .Q(select_periodic_read),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2521" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][0][0]_i_1 
       (.I0(\trcd_cntr[0][0][0][2]_i_2_n_0 ),
        .I1(\tras_cntr_rb_reg[0][0][0]_211 [0]),
        .I2(\tras_cntr_rb_reg[0][0][0]_211 [1]),
        .I3(\tras_cntr_rb_reg[0][0][0]_211 [2]),
        .O(\tras_cntr_rb_nxt[0][0][0]_269 [0]));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][0][1]_i_1 
       (.I0(\tras_cntr_rb_reg[0][0][0]_211 [2]),
        .I1(\tras_cntr_rb_reg[0][0][0]_211 [1]),
        .I2(\tras_cntr_rb_reg[0][0][0]_211 [0]),
        .I3(\trcd_cntr[0][0][0][2]_i_2_n_0 ),
        .O(\tras_cntr_rb_nxt[0][0][0]_269 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2521" *) 
  LUT4 #(
    .INIT(16'hFAEA)) 
    \tras_cntr_rb[0][0][0][2]_i_1 
       (.I0(\trcd_cntr[0][0][0][2]_i_2_n_0 ),
        .I1(\tras_cntr_rb_reg[0][0][0]_211 [0]),
        .I2(\tras_cntr_rb_reg[0][0][0]_211 [2]),
        .I3(\tras_cntr_rb_reg[0][0][0]_211 [1]),
        .O(\tras_cntr_rb_nxt[0][0][0]_269 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2520" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][1][0]_i_1 
       (.I0(\trcd_cntr[0][0][1][2]_i_2_n_0 ),
        .I1(\tras_cntr_rb_reg[0][0][1]_212 [0]),
        .I2(\tras_cntr_rb_reg[0][0][1]_212 [1]),
        .I3(\tras_cntr_rb_reg[0][0][1]_212 [2]),
        .O(\tras_cntr_rb_nxt[0][0][1]_266 [0]));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][1][1]_i_1 
       (.I0(\tras_cntr_rb_reg[0][0][1]_212 [2]),
        .I1(\tras_cntr_rb_reg[0][0][1]_212 [1]),
        .I2(\tras_cntr_rb_reg[0][0][1]_212 [0]),
        .I3(\trcd_cntr[0][0][1][2]_i_2_n_0 ),
        .O(\tras_cntr_rb_nxt[0][0][1]_266 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2520" *) 
  LUT4 #(
    .INIT(16'hFEAA)) 
    \tras_cntr_rb[0][0][1][2]_i_1 
       (.I0(\trcd_cntr[0][0][1][2]_i_2_n_0 ),
        .I1(\tras_cntr_rb_reg[0][0][1]_212 [0]),
        .I2(\tras_cntr_rb_reg[0][0][1]_212 [1]),
        .I3(\tras_cntr_rb_reg[0][0][1]_212 [2]),
        .O(\tras_cntr_rb_nxt[0][0][1]_266 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2519" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][2][0]_i_1 
       (.I0(\trcd_cntr[0][0][2][2]_i_2_n_0 ),
        .I1(\tras_cntr_rb_reg[0][0][2]_213 [0]),
        .I2(\tras_cntr_rb_reg[0][0][2]_213 [1]),
        .I3(\tras_cntr_rb_reg[0][0][2]_213 [2]),
        .O(\tras_cntr_rb_nxt[0][0][2]_263 [0]));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][2][1]_i_1 
       (.I0(\tras_cntr_rb_reg[0][0][2]_213 [2]),
        .I1(\tras_cntr_rb_reg[0][0][2]_213 [1]),
        .I2(\tras_cntr_rb_reg[0][0][2]_213 [0]),
        .I3(\trcd_cntr[0][0][2][2]_i_2_n_0 ),
        .O(\tras_cntr_rb_nxt[0][0][2]_263 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2519" *) 
  LUT4 #(
    .INIT(16'hFAEA)) 
    \tras_cntr_rb[0][0][2][2]_i_1 
       (.I0(\trcd_cntr[0][0][2][2]_i_2_n_0 ),
        .I1(\tras_cntr_rb_reg[0][0][2]_213 [0]),
        .I2(\tras_cntr_rb_reg[0][0][2]_213 [2]),
        .I3(\tras_cntr_rb_reg[0][0][2]_213 [1]),
        .O(\tras_cntr_rb_nxt[0][0][2]_263 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2522" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][3][0]_i_1 
       (.I0(\trcd_cntr[0][0][3][2]_i_2_n_0 ),
        .I1(\tras_cntr_rb_reg[0][0][3]_214 [0]),
        .I2(\tras_cntr_rb_reg[0][0][3]_214 [1]),
        .I3(\tras_cntr_rb_reg[0][0][3]_214 [2]),
        .O(\tras_cntr_rb_nxt[0][0][3]_272 [0]));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][3][1]_i_1 
       (.I0(\tras_cntr_rb_reg[0][0][3]_214 [2]),
        .I1(\tras_cntr_rb_reg[0][0][3]_214 [1]),
        .I2(\tras_cntr_rb_reg[0][0][3]_214 [0]),
        .I3(\trcd_cntr[0][0][3][2]_i_2_n_0 ),
        .O(\tras_cntr_rb_nxt[0][0][3]_272 [1]));
  (* SOFT_HLUTNM = "soft_lutpair2522" *) 
  LUT4 #(
    .INIT(16'hFAEA)) 
    \tras_cntr_rb[0][0][3][2]_i_1 
       (.I0(\trcd_cntr[0][0][3][2]_i_2_n_0 ),
        .I1(\tras_cntr_rb_reg[0][0][3]_214 [0]),
        .I2(\tras_cntr_rb_reg[0][0][3]_214 [2]),
        .I3(\tras_cntr_rb_reg[0][0][3]_214 [1]),
        .O(\tras_cntr_rb_nxt[0][0][3]_272 [2]));
  FDRE \tras_cntr_rb_reg[0][0][0][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb_nxt[0][0][0]_269 [0]),
        .Q(\tras_cntr_rb_reg[0][0][0]_211 [0]),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][0][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb_nxt[0][0][0]_269 [1]),
        .Q(\tras_cntr_rb_reg[0][0][0]_211 [1]),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][0][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb_nxt[0][0][0]_269 [2]),
        .Q(\tras_cntr_rb_reg[0][0][0]_211 [2]),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][1][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb_nxt[0][0][1]_266 [0]),
        .Q(\tras_cntr_rb_reg[0][0][1]_212 [0]),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][1][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb_nxt[0][0][1]_266 [1]),
        .Q(\tras_cntr_rb_reg[0][0][1]_212 [1]),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][1][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb_nxt[0][0][1]_266 [2]),
        .Q(\tras_cntr_rb_reg[0][0][1]_212 [2]),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][2][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb_nxt[0][0][2]_263 [0]),
        .Q(\tras_cntr_rb_reg[0][0][2]_213 [0]),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][2][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb_nxt[0][0][2]_263 [1]),
        .Q(\tras_cntr_rb_reg[0][0][2]_213 [1]),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][2][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb_nxt[0][0][2]_263 [2]),
        .Q(\tras_cntr_rb_reg[0][0][2]_213 [2]),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][3][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb_nxt[0][0][3]_272 [0]),
        .Q(\tras_cntr_rb_reg[0][0][3]_214 [0]),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][3][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb_nxt[0][0][3]_272 [1]),
        .Q(\tras_cntr_rb_reg[0][0][3]_214 [1]),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][3][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb_nxt[0][0][3]_272 [2]),
        .Q(\tras_cntr_rb_reg[0][0][3]_214 [2]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2504" *) 
  LUT4 #(
    .INIT(16'hF44F)) 
    \trcd_cntr[0][0][0][0]_i_1 
       (.I0(actReqR_reg_0),
        .I1(\trcd_cntr[0][0][0][2]_i_2_n_0 ),
        .I2(\trcd_cntr_is_zero_reg[0][0][0]_203 ),
        .I3(\trcd_cntr_reg[0][0][0]_204 [0]),
        .O(\trcd_cntr_nxt[0][0][0]_270 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2504" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][0][1]_i_1 
       (.I0(actReqR_reg_0),
        .I1(\trcd_cntr[0][0][0][2]_i_2_n_0 ),
        .I2(\trcd_cntr_reg[0][0][0]_204 [0]),
        .I3(\trcd_cntr_is_zero_reg[0][0][0]_203 ),
        .I4(\trcd_cntr_reg[0][0][0]_204 [1]),
        .O(\trcd_cntr_nxt[0][0][0]_270 [1]));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][0][2]_i_1 
       (.I0(\trcd_cntr_is_zero_reg[0][0][0]_203 ),
        .I1(\trcd_cntr_reg[0][0][0]_204 [0]),
        .I2(\trcd_cntr_reg[0][0][0]_204 [1]),
        .I3(\trcd_cntr_reg[0][0][0]_204 [2]),
        .I4(actReqR_reg_0),
        .I5(\trcd_cntr[0][0][0][2]_i_2_n_0 ),
        .O(\trcd_cntr_nxt[0][0][0]_270 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2498" *) 
  LUT5 #(
    .INIT(32'h00100000)) 
    \trcd_cntr[0][0][0][2]_i_2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .I4(grSt[0]),
        .O(\trcd_cntr[0][0][0][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h5555555400000001)) 
    \trcd_cntr[0][0][0][3]_i_1 
       (.I0(\trcd_cntr_is_zero[0][0][0]_i_2_n_0 ),
        .I1(\trcd_cntr_reg[0][0][0]_204 [2]),
        .I2(\trcd_cntr_reg[0][0][0]_204 [1]),
        .I3(\trcd_cntr_reg[0][0][0]_204 [0]),
        .I4(\trcd_cntr_is_zero_reg[0][0][0]_203 ),
        .I5(\trcd_cntr_reg[0][0][0]_204 [3]),
        .O(\trcd_cntr_nxt[0][0][0]_270 [3]));
  (* SOFT_HLUTNM = "soft_lutpair2503" *) 
  LUT4 #(
    .INIT(16'hF44F)) 
    \trcd_cntr[0][0][1][0]_i_1 
       (.I0(actReqR_reg_0),
        .I1(\trcd_cntr[0][0][1][2]_i_2_n_0 ),
        .I2(\trcd_cntr_is_zero_reg[0][0][1]_205 ),
        .I3(\trcd_cntr_reg[0][0][1]_206 [0]),
        .O(\trcd_cntr_nxt[0][0][1]_267 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2503" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][1][1]_i_1 
       (.I0(actReqR_reg_0),
        .I1(\trcd_cntr[0][0][1][2]_i_2_n_0 ),
        .I2(\trcd_cntr_reg[0][0][1]_206 [0]),
        .I3(\trcd_cntr_is_zero_reg[0][0][1]_205 ),
        .I4(\trcd_cntr_reg[0][0][1]_206 [1]),
        .O(\trcd_cntr_nxt[0][0][1]_267 [1]));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][1][2]_i_1 
       (.I0(\trcd_cntr_is_zero_reg[0][0][1]_205 ),
        .I1(\trcd_cntr_reg[0][0][1]_206 [0]),
        .I2(\trcd_cntr_reg[0][0][1]_206 [1]),
        .I3(\trcd_cntr_reg[0][0][1]_206 [2]),
        .I4(actReqR_reg_0),
        .I5(\trcd_cntr[0][0][1][2]_i_2_n_0 ),
        .O(\trcd_cntr_nxt[0][0][1]_267 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2497" *) 
  LUT5 #(
    .INIT(32'h00400000)) 
    \trcd_cntr[0][0][1][2]_i_2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .I4(grSt[0]),
        .O(\trcd_cntr[0][0][1][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0001)) 
    \trcd_cntr[0][0][1][3]_i_1 
       (.I0(\trcd_cntr_reg[0][0][1]_206 [1]),
        .I1(\trcd_cntr_reg[0][0][1]_206 [0]),
        .I2(\trcd_cntr_is_zero_reg[0][0][1]_205 ),
        .I3(\trcd_cntr_reg[0][0][1]_206 [2]),
        .I4(\trcd_cntr_reg[0][0][1]_206 [3]),
        .I5(\trcd_cntr_is_zero[0][0][1]_i_2_n_0 ),
        .O(\trcd_cntr_nxt[0][0][1]_267 [3]));
  (* SOFT_HLUTNM = "soft_lutpair2502" *) 
  LUT4 #(
    .INIT(16'hF44F)) 
    \trcd_cntr[0][0][2][0]_i_1 
       (.I0(actReqR_reg_0),
        .I1(\trcd_cntr[0][0][2][2]_i_2_n_0 ),
        .I2(\trcd_cntr_is_zero_reg[0][0][2]_207 ),
        .I3(\trcd_cntr_reg[0][0][2]_208 [0]),
        .O(\trcd_cntr_nxt[0][0][2]_264 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2502" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][2][1]_i_1 
       (.I0(actReqR_reg_0),
        .I1(\trcd_cntr[0][0][2][2]_i_2_n_0 ),
        .I2(\trcd_cntr_reg[0][0][2]_208 [0]),
        .I3(\trcd_cntr_is_zero_reg[0][0][2]_207 ),
        .I4(\trcd_cntr_reg[0][0][2]_208 [1]),
        .O(\trcd_cntr_nxt[0][0][2]_264 [1]));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][2][2]_i_1 
       (.I0(\trcd_cntr_is_zero_reg[0][0][2]_207 ),
        .I1(\trcd_cntr_reg[0][0][2]_208 [0]),
        .I2(\trcd_cntr_reg[0][0][2]_208 [1]),
        .I3(\trcd_cntr_reg[0][0][2]_208 [2]),
        .I4(actReqR_reg_0),
        .I5(\trcd_cntr[0][0][2][2]_i_2_n_0 ),
        .O(\trcd_cntr_nxt[0][0][2]_264 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2497" *) 
  LUT5 #(
    .INIT(32'h00400000)) 
    \trcd_cntr[0][0][2][2]_i_2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .I4(grSt[0]),
        .O(\trcd_cntr[0][0][2][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0001)) 
    \trcd_cntr[0][0][2][3]_i_1 
       (.I0(\trcd_cntr_reg[0][0][2]_208 [1]),
        .I1(\trcd_cntr_reg[0][0][2]_208 [0]),
        .I2(\trcd_cntr_is_zero_reg[0][0][2]_207 ),
        .I3(\trcd_cntr_reg[0][0][2]_208 [2]),
        .I4(\trcd_cntr_reg[0][0][2]_208 [3]),
        .I5(\trcd_cntr_is_zero[0][0][2]_i_2_n_0 ),
        .O(\trcd_cntr_nxt[0][0][2]_264 [3]));
  (* SOFT_HLUTNM = "soft_lutpair2505" *) 
  LUT4 #(
    .INIT(16'hF44F)) 
    \trcd_cntr[0][0][3][0]_i_1 
       (.I0(actReqR_reg_0),
        .I1(\trcd_cntr[0][0][3][2]_i_2_n_0 ),
        .I2(\trcd_cntr_is_zero_reg[0][0][3]_209 ),
        .I3(\trcd_cntr_reg[0][0][3]_210 [0]),
        .O(\trcd_cntr_nxt[0][0][3]_273 [0]));
  (* SOFT_HLUTNM = "soft_lutpair2505" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][3][1]_i_1 
       (.I0(actReqR_reg_0),
        .I1(\trcd_cntr[0][0][3][2]_i_2_n_0 ),
        .I2(\trcd_cntr_reg[0][0][3]_210 [0]),
        .I3(\trcd_cntr_is_zero_reg[0][0][3]_209 ),
        .I4(\trcd_cntr_reg[0][0][3]_210 [1]),
        .O(\trcd_cntr_nxt[0][0][3]_273 [1]));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][3][2]_i_1 
       (.I0(\trcd_cntr_is_zero_reg[0][0][3]_209 ),
        .I1(\trcd_cntr_reg[0][0][3]_210 [0]),
        .I2(\trcd_cntr_reg[0][0][3]_210 [1]),
        .I3(\trcd_cntr_reg[0][0][3]_210 [2]),
        .I4(actReqR_reg_0),
        .I5(\trcd_cntr[0][0][3][2]_i_2_n_0 ),
        .O(\trcd_cntr_nxt[0][0][3]_273 [2]));
  (* SOFT_HLUTNM = "soft_lutpair2498" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \trcd_cntr[0][0][3][2]_i_2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .I4(grSt[0]),
        .O(\trcd_cntr[0][0][3][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h5555555400000001)) 
    \trcd_cntr[0][0][3][3]_i_1 
       (.I0(\trcd_cntr_is_zero[0][0][3]_i_2_n_0 ),
        .I1(\trcd_cntr_reg[0][0][3]_210 [2]),
        .I2(\trcd_cntr_reg[0][0][3]_210 [1]),
        .I3(\trcd_cntr_reg[0][0][3]_210 [0]),
        .I4(\trcd_cntr_is_zero_reg[0][0][3]_209 ),
        .I5(\trcd_cntr_reg[0][0][3]_210 [3]),
        .O(\trcd_cntr_nxt[0][0][3]_273 [3]));
  LUT6 #(
    .INIT(64'h0000000000000014)) 
    \trcd_cntr_is_zero[0][0][0]_i_1 
       (.I0(\trcd_cntr_reg[0][0][0]_204 [3]),
        .I1(\trcd_cntr_is_zero_reg[0][0][0]_203 ),
        .I2(\trcd_cntr_reg[0][0][0]_204 [0]),
        .I3(\trcd_cntr_reg[0][0][0]_204 [1]),
        .I4(\trcd_cntr_reg[0][0][0]_204 [2]),
        .I5(\trcd_cntr_is_zero[0][0][0]_i_2_n_0 ),
        .O(\trcd_cntr_is_zero_nxt[0][0][0]_271 ));
  LUT6 #(
    .INIT(64'h0000000000000020)) 
    \trcd_cntr_is_zero[0][0][0]_i_2 
       (.I0(grSt[0]),
        .I1(grSt[2]),
        .I2(grSt[1]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(actReqR_reg_0),
        .O(\trcd_cntr_is_zero[0][0][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010000)) 
    \trcd_cntr_is_zero[0][0][1]_i_1 
       (.I0(\trcd_cntr_reg[0][0][1]_206 [3]),
        .I1(\trcd_cntr_is_zero[0][0][1]_i_2_n_0 ),
        .I2(\trcd_cntr_reg[0][0][1]_206 [2]),
        .I3(\trcd_cntr_reg[0][0][1]_206 [1]),
        .I4(\trcd_cntr_reg[0][0][1]_206 [0]),
        .I5(\trcd_cntr_is_zero_reg[0][0][1]_205 ),
        .O(\trcd_cntr_is_zero_nxt[0][0][1]_268 ));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \trcd_cntr_is_zero[0][0][1]_i_2 
       (.I0(grSt[0]),
        .I1(grSt[2]),
        .I2(grSt[1]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(actReqR_reg_0),
        .O(\trcd_cntr_is_zero[0][0][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010000)) 
    \trcd_cntr_is_zero[0][0][2]_i_1 
       (.I0(\trcd_cntr_reg[0][0][2]_208 [3]),
        .I1(\trcd_cntr_is_zero[0][0][2]_i_2_n_0 ),
        .I2(\trcd_cntr_reg[0][0][2]_208 [2]),
        .I3(\trcd_cntr_reg[0][0][2]_208 [1]),
        .I4(\trcd_cntr_reg[0][0][2]_208 [0]),
        .I5(\trcd_cntr_is_zero_reg[0][0][2]_207 ),
        .O(\trcd_cntr_is_zero_nxt[0][0][2]_265 ));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \trcd_cntr_is_zero[0][0][2]_i_2 
       (.I0(grSt[0]),
        .I1(grSt[2]),
        .I2(grSt[1]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(actReqR_reg_0),
        .O(\trcd_cntr_is_zero[0][0][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000014)) 
    \trcd_cntr_is_zero[0][0][3]_i_1 
       (.I0(\trcd_cntr_reg[0][0][3]_210 [3]),
        .I1(\trcd_cntr_is_zero_reg[0][0][3]_209 ),
        .I2(\trcd_cntr_reg[0][0][3]_210 [0]),
        .I3(\trcd_cntr_reg[0][0][3]_210 [1]),
        .I4(\trcd_cntr_reg[0][0][3]_210 [2]),
        .I5(\trcd_cntr_is_zero[0][0][3]_i_2_n_0 ),
        .O(\trcd_cntr_is_zero_nxt[0][0][3]_274 ));
  LUT6 #(
    .INIT(64'h0000000020000000)) 
    \trcd_cntr_is_zero[0][0][3]_i_2 
       (.I0(grSt[0]),
        .I1(grSt[2]),
        .I2(grSt[1]),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(actReqR_reg_0),
        .O(\trcd_cntr_is_zero[0][0][3]_i_2_n_0 ));
  FDRE \trcd_cntr_is_zero_reg[0][0][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero_nxt[0][0][0]_271 ),
        .Q(\trcd_cntr_is_zero_reg[0][0][0]_203 ),
        .R(1'b0));
  FDRE \trcd_cntr_is_zero_reg[0][0][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero_nxt[0][0][1]_268 ),
        .Q(\trcd_cntr_is_zero_reg[0][0][1]_205 ),
        .R(1'b0));
  FDRE \trcd_cntr_is_zero_reg[0][0][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero_nxt[0][0][2]_265 ),
        .Q(\trcd_cntr_is_zero_reg[0][0][2]_207 ),
        .R(1'b0));
  FDRE \trcd_cntr_is_zero_reg[0][0][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero_nxt[0][0][3]_274 ),
        .Q(\trcd_cntr_is_zero_reg[0][0][3]_209 ),
        .R(1'b0));
  FDRE \trcd_cntr_reg[0][0][0][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][0]_270 [0]),
        .Q(\trcd_cntr_reg[0][0][0]_204 [0]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][0][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][0]_270 [1]),
        .Q(\trcd_cntr_reg[0][0][0]_204 [1]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][0][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][0]_270 [2]),
        .Q(\trcd_cntr_reg[0][0][0]_204 [2]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][0][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][0]_270 [3]),
        .Q(\trcd_cntr_reg[0][0][0]_204 [3]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][1]_267 [0]),
        .Q(\trcd_cntr_reg[0][0][1]_206 [0]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][1]_267 [1]),
        .Q(\trcd_cntr_reg[0][0][1]_206 [1]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][1]_267 [2]),
        .Q(\trcd_cntr_reg[0][0][1]_206 [2]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][1]_267 [3]),
        .Q(\trcd_cntr_reg[0][0][1]_206 [3]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][2]_264 [0]),
        .Q(\trcd_cntr_reg[0][0][2]_208 [0]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][2]_264 [1]),
        .Q(\trcd_cntr_reg[0][0][2]_208 [1]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][2]_264 [2]),
        .Q(\trcd_cntr_reg[0][0][2]_208 [2]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][2]_264 [3]),
        .Q(\trcd_cntr_reg[0][0][2]_208 [3]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][3]_273 [0]),
        .Q(\trcd_cntr_reg[0][0][3]_210 [0]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][3]_273 [1]),
        .Q(\trcd_cntr_reg[0][0][3]_210 [1]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][3]_273 [2]),
        .Q(\trcd_cntr_reg[0][0][3]_210 [2]),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_nxt[0][0][3]_273 [3]),
        .Q(\trcd_cntr_reg[0][0][3]_210 [3]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2499" *) 
  LUT5 #(
    .INIT(32'h53555055)) 
    \trp_cntr[0]_i_1 
       (.I0(trp_cntr[0]),
        .I1(\trp_cntr[0]_i_2_n_0 ),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .I4(grSt[0]),
        .O(\trp_cntr[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00350F35F035FF35)) 
    \trp_cntr[0]_i_2 
       (.I0(\ap_cntr_reg[0][0][0]_222 [0]),
        .I1(\ap_cntr_reg[0][0][1]_220 [0]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(\ap_cntr_reg[0][0][2]_218 [0]),
        .I5(\ap_cntr_reg[0][0][3]_216 [0]),
        .O(\trp_cntr[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF8FFF800F800F8FF)) 
    \trp_cntr[1]_i_1 
       (.I0(\ap_cntr_reg[0][0][3]_216 [1]),
        .I1(\trp_cntr[1]_i_2_n_0 ),
        .I2(\trp_cntr[1]_i_3_n_0 ),
        .I3(\trp_cntr[2]_i_3_n_0 ),
        .I4(trp_cntr[0]),
        .I5(trp_cntr[1]),
        .O(\trp_cntr[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2542" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \trp_cntr[1]_i_2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\trp_cntr[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h5FDF55DF5FD555D5)) 
    \trp_cntr[1]_i_3 
       (.I0(grSt[0]),
        .I1(\ap_cntr_reg[0][0][2]_218 [1]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\ap_cntr_reg[0][0][1]_220 [1]),
        .I5(\ap_cntr_reg[0][0][0]_222 [1]),
        .O(\trp_cntr[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00FFA9A90000A9A9)) 
    \trp_cntr[2]_i_1 
       (.I0(trp_cntr[2]),
        .I1(trp_cntr[1]),
        .I2(trp_cntr[0]),
        .I3(\trp_cntr[2]_i_2_n_0 ),
        .I4(\trp_cntr[2]_i_3_n_0 ),
        .I5(grSt[0]),
        .O(\trp_cntr[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h50305F30503F5F3F)) 
    \trp_cntr[2]_i_2 
       (.I0(\ap_cntr_reg[0][0][3]_216 [2]),
        .I1(\ap_cntr_reg[0][0][2]_218 [2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\ap_cntr_reg[0][0][1]_220 [2]),
        .I5(\ap_cntr_reg[0][0][0]_222 [2]),
        .O(\trp_cntr[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2499" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \trp_cntr[2]_i_3 
       (.I0(grSt[2]),
        .I1(grSt[1]),
        .O(\trp_cntr[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h660F666666006666)) 
    \trp_cntr[3]_i_1 
       (.I0(trp_cntr[3]),
        .I1(\trp_cntr[3]_i_2_n_0 ),
        .I2(\trp_cntr[3]_i_3_n_0 ),
        .I3(grSt[1]),
        .I4(grSt[2]),
        .I5(grSt[0]),
        .O(\trp_cntr[3]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \trp_cntr[3]_i_2 
       (.I0(trp_cntr[1]),
        .I1(trp_cntr[0]),
        .I2(trp_cntr[2]),
        .O(\trp_cntr[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h50305F30503F5F3F)) 
    \trp_cntr[3]_i_3 
       (.I0(\ap_cntr_reg[0][0][3]_216 [3]),
        .I1(\ap_cntr_reg[0][0][1]_220 [3]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(\ap_cntr_reg[0][0][2]_218 [3]),
        .I5(\ap_cntr_reg[0][0][0]_222 [3]),
        .O(\trp_cntr[3]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \trp_cntr[4]_i_1 
       (.I0(\trp_cntr[4]_i_2_n_0 ),
        .O(\trp_cntr[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBB0F0FF00F)) 
    \trp_cntr[4]_i_2 
       (.I0(\trp_cntr[4]_i_3_n_0 ),
        .I1(grSt[0]),
        .I2(trp_cntr[4]),
        .I3(\trp_cntr[3]_i_2_n_0 ),
        .I4(trp_cntr[3]),
        .I5(\trp_cntr[2]_i_3_n_0 ),
        .O(\trp_cntr[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0530F530053FF53F)) 
    \trp_cntr[4]_i_3 
       (.I0(\ap_cntr_reg[0][0][1]_220 [4]),
        .I1(\ap_cntr_reg[0][0][2]_218 [4]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\ap_cntr_reg[0][0][3]_216 [4]),
        .I5(\ap_cntr_reg[0][0][0]_222 [4]),
        .O(\trp_cntr[4]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00000004)) 
    trp_cntr_is_zero_i_1
       (.I0(\trp_cntr[0]_i_1_n_0 ),
        .I1(\trp_cntr[4]_i_2_n_0 ),
        .I2(\trp_cntr[2]_i_1_n_0 ),
        .I3(\trp_cntr[3]_i_1_n_0 ),
        .I4(\trp_cntr[1]_i_1_n_0 ),
        .O(trp_cntr_is_zero_nxt));
  FDRE trp_cntr_is_zero_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(trp_cntr_is_zero_nxt),
        .Q(trp_cntr_is_zero),
        .R(1'b0));
  FDRE \trp_cntr_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trp_cntr[0]_i_1_n_0 ),
        .Q(trp_cntr[0]),
        .R(rst_r1));
  FDRE \trp_cntr_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trp_cntr[1]_i_1_n_0 ),
        .Q(trp_cntr[1]),
        .R(rst_r1));
  FDRE \trp_cntr_reg[2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trp_cntr[2]_i_1_n_0 ),
        .Q(trp_cntr[2]),
        .R(rst_r1));
  FDRE \trp_cntr_reg[3] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trp_cntr[3]_i_1_n_0 ),
        .Q(trp_cntr[3]),
        .R(rst_r1));
  FDRE \trp_cntr_reg[4] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\trp_cntr[4]_i_1_n_0 ),
        .Q(trp_cntr[4]),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][0]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [0]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[0] ),
        .I3(select_periodic_read_nxt),
        .I4(bank[0]),
        .O(\txn_fifo_nxt[0]_248 [0]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][11]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [11]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[11] ),
        .I3(select_periodic_read_nxt),
        .I4(col[0]),
        .O(\txn_fifo_nxt[0]_248 [11]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][12]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [12]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[12] ),
        .I3(select_periodic_read_nxt),
        .I4(col[1]),
        .O(\txn_fifo_nxt[0]_248 [12]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][13]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [13]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[13] ),
        .I3(select_periodic_read_nxt),
        .I4(col[2]),
        .O(\txn_fifo_nxt[0]_248 [13]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][14]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [14]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[14] ),
        .I3(select_periodic_read_nxt),
        .I4(col[3]),
        .O(\txn_fifo_nxt[0]_248 [14]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][15]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [15]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[15] ),
        .I3(select_periodic_read_nxt),
        .I4(col[4]),
        .O(\txn_fifo_nxt[0]_248 [15]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][16]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [16]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[16] ),
        .I3(select_periodic_read_nxt),
        .I4(col[5]),
        .O(\txn_fifo_nxt[0]_248 [16]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][17]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [17]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[17] ),
        .I3(select_periodic_read_nxt),
        .I4(col[6]),
        .O(\txn_fifo_nxt[0]_248 [17]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][1]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [1]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[1] ),
        .I3(select_periodic_read_nxt),
        .I4(bank[1]),
        .O(\txn_fifo_nxt[0]_248 [1]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][24]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [24]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[24] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[0]),
        .O(\txn_fifo_nxt[0]_248 [24]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][25]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [25]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[25] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[1]),
        .O(\txn_fifo_nxt[0]_248 [25]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][26]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [26]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[26] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[2]),
        .O(\txn_fifo_nxt[0]_248 [26]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][27]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [27]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[27] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[3]),
        .O(\txn_fifo_nxt[0]_248 [27]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][28]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [28]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[28] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[4]),
        .O(\txn_fifo_nxt[0]_248 [28]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][29]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [29]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[29] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[5]),
        .O(\txn_fifo_nxt[0]_248 [29]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][2]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [2]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[2] ),
        .I3(select_periodic_read_nxt),
        .I4(group),
        .O(\txn_fifo_nxt[0]_248 [2]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][30]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [30]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[30] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[6]),
        .O(\txn_fifo_nxt[0]_248 [30]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][31]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [31]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[31] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[7]),
        .O(\txn_fifo_nxt[0]_248 [31]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][32]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [32]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[32] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[8]),
        .O(\txn_fifo_nxt[0]_248 [32]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][33]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [33]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[33] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[9]),
        .O(\txn_fifo_nxt[0]_248 [33]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][34]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [34]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[34] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[10]),
        .O(\txn_fifo_nxt[0]_248 [34]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][35]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [35]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[35] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[11]),
        .O(\txn_fifo_nxt[0]_248 [35]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][36]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [36]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[36] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[12]),
        .O(\txn_fifo_nxt[0]_248 [36]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][37]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [37]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[37] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[13]),
        .O(\txn_fifo_nxt[0]_248 [37]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][38]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [38]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[38] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[14]),
        .O(\txn_fifo_nxt[0]_248 [38]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][39]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [39]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[39] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[15]),
        .O(\txn_fifo_nxt[0]_248 [39]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][40]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [40]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[40] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[16]),
        .O(\txn_fifo_nxt[0]_248 [40]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[0][44]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [44]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[44] ),
        .I3(select_periodic_read_nxt),
        .I4(cmd[0]),
        .O(\txn_fifo_nxt[0]_248 [44]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \txn_fifo[0][45]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [45]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(cmd[1]),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[0]_248 [45]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \txn_fifo[0][46]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [46]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(cmd[2]),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[0]_248 [46]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \txn_fifo[0][47]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [47]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(1'b0),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[0]_248 [47]));
  LUT6 #(
    .INIT(64'h8888888888B88888)) 
    \txn_fifo[0][48]_i_1 
       (.I0(\txn_fifo_reg[0]_190 [48]),
        .I1(\txn_fifo[0][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[44] ),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[0]_248 [48]));
  LUT6 #(
    .INIT(64'h57777777FEEEEEEE)) 
    \txn_fifo[0][48]_i_2 
       (.I0(txn_fifo_wptr[1]),
        .I1(select_periodic_read),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg[0]_0 ),
        .I4(accept_reg_n_0),
        .I5(txn_fifo_wptr[0]),
        .O(\txn_fifo[0][48]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][0]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [0]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[0] ),
        .I3(select_periodic_read_nxt),
        .I4(bank[0]),
        .O(\txn_fifo_nxt[1]_247 [0]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][11]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [11]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[11] ),
        .I3(select_periodic_read_nxt),
        .I4(col[0]),
        .O(\txn_fifo_nxt[1]_247 [11]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][12]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [12]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[12] ),
        .I3(select_periodic_read_nxt),
        .I4(col[1]),
        .O(\txn_fifo_nxt[1]_247 [12]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][13]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [13]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[13] ),
        .I3(select_periodic_read_nxt),
        .I4(col[2]),
        .O(\txn_fifo_nxt[1]_247 [13]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][14]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [14]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[14] ),
        .I3(select_periodic_read_nxt),
        .I4(col[3]),
        .O(\txn_fifo_nxt[1]_247 [14]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][15]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [15]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[15] ),
        .I3(select_periodic_read_nxt),
        .I4(col[4]),
        .O(\txn_fifo_nxt[1]_247 [15]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][16]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [16]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[16] ),
        .I3(select_periodic_read_nxt),
        .I4(col[5]),
        .O(\txn_fifo_nxt[1]_247 [16]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][17]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [17]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[17] ),
        .I3(select_periodic_read_nxt),
        .I4(col[6]),
        .O(\txn_fifo_nxt[1]_247 [17]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][1]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [1]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[1] ),
        .I3(select_periodic_read_nxt),
        .I4(bank[1]),
        .O(\txn_fifo_nxt[1]_247 [1]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][24]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [24]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[24] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[0]),
        .O(\txn_fifo_nxt[1]_247 [24]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][25]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [25]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[25] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[1]),
        .O(\txn_fifo_nxt[1]_247 [25]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][26]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [26]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[26] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[2]),
        .O(\txn_fifo_nxt[1]_247 [26]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][27]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [27]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[27] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[3]),
        .O(\txn_fifo_nxt[1]_247 [27]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][28]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [28]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[28] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[4]),
        .O(\txn_fifo_nxt[1]_247 [28]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][29]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [29]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[29] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[5]),
        .O(\txn_fifo_nxt[1]_247 [29]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][2]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [2]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[2] ),
        .I3(select_periodic_read_nxt),
        .I4(group),
        .O(\txn_fifo_nxt[1]_247 [2]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][30]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [30]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[30] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[6]),
        .O(\txn_fifo_nxt[1]_247 [30]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][31]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [31]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[31] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[7]),
        .O(\txn_fifo_nxt[1]_247 [31]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][32]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [32]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[32] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[8]),
        .O(\txn_fifo_nxt[1]_247 [32]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][33]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [33]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[33] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[9]),
        .O(\txn_fifo_nxt[1]_247 [33]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][34]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [34]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[34] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[10]),
        .O(\txn_fifo_nxt[1]_247 [34]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][35]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [35]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[35] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[11]),
        .O(\txn_fifo_nxt[1]_247 [35]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][36]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [36]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[36] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[12]),
        .O(\txn_fifo_nxt[1]_247 [36]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][37]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [37]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[37] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[13]),
        .O(\txn_fifo_nxt[1]_247 [37]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][38]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [38]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[38] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[14]),
        .O(\txn_fifo_nxt[1]_247 [38]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][39]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [39]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[39] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[15]),
        .O(\txn_fifo_nxt[1]_247 [39]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][40]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [40]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[40] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[16]),
        .O(\txn_fifo_nxt[1]_247 [40]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[1][44]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [44]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[44] ),
        .I3(select_periodic_read_nxt),
        .I4(cmd[0]),
        .O(\txn_fifo_nxt[1]_247 [44]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \txn_fifo[1][45]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [45]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(cmd[1]),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[1]_247 [45]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \txn_fifo[1][46]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [46]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(cmd[2]),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[1]_247 [46]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \txn_fifo[1][47]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [47]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(1'b0),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[1]_247 [47]));
  LUT6 #(
    .INIT(64'h8888888888B88888)) 
    \txn_fifo[1][48]_i_1 
       (.I0(\txn_fifo_reg[1]_191 [48]),
        .I1(\txn_fifo[1][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[44] ),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[1]_247 [48]));
  LUT6 #(
    .INIT(64'hFEEEEEEEABBBBBBB)) 
    \txn_fifo[1][48]_i_2 
       (.I0(txn_fifo_wptr[1]),
        .I1(select_periodic_read),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg[0]_0 ),
        .I4(accept_reg_n_0),
        .I5(txn_fifo_wptr[0]),
        .O(\txn_fifo[1][48]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][0]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [0]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[0] ),
        .I3(select_periodic_read_nxt),
        .I4(bank[0]),
        .O(\txn_fifo_nxt[2]_246 [0]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][11]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [11]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[11] ),
        .I3(select_periodic_read_nxt),
        .I4(col[0]),
        .O(\txn_fifo_nxt[2]_246 [11]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][12]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [12]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[12] ),
        .I3(select_periodic_read_nxt),
        .I4(col[1]),
        .O(\txn_fifo_nxt[2]_246 [12]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][13]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [13]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[13] ),
        .I3(select_periodic_read_nxt),
        .I4(col[2]),
        .O(\txn_fifo_nxt[2]_246 [13]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][14]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [14]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[14] ),
        .I3(select_periodic_read_nxt),
        .I4(col[3]),
        .O(\txn_fifo_nxt[2]_246 [14]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][15]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [15]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[15] ),
        .I3(select_periodic_read_nxt),
        .I4(col[4]),
        .O(\txn_fifo_nxt[2]_246 [15]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][16]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [16]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[16] ),
        .I3(select_periodic_read_nxt),
        .I4(col[5]),
        .O(\txn_fifo_nxt[2]_246 [16]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][17]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [17]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[17] ),
        .I3(select_periodic_read_nxt),
        .I4(col[6]),
        .O(\txn_fifo_nxt[2]_246 [17]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][1]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [1]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[1] ),
        .I3(select_periodic_read_nxt),
        .I4(bank[1]),
        .O(\txn_fifo_nxt[2]_246 [1]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][24]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [24]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[24] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[0]),
        .O(\txn_fifo_nxt[2]_246 [24]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][25]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [25]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[25] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[1]),
        .O(\txn_fifo_nxt[2]_246 [25]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][26]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [26]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[26] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[2]),
        .O(\txn_fifo_nxt[2]_246 [26]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][27]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [27]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[27] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[3]),
        .O(\txn_fifo_nxt[2]_246 [27]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][28]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [28]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[28] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[4]),
        .O(\txn_fifo_nxt[2]_246 [28]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][29]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [29]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[29] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[5]),
        .O(\txn_fifo_nxt[2]_246 [29]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][2]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [2]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[2] ),
        .I3(select_periodic_read_nxt),
        .I4(group),
        .O(\txn_fifo_nxt[2]_246 [2]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][30]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [30]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[30] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[6]),
        .O(\txn_fifo_nxt[2]_246 [30]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][31]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [31]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[31] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[7]),
        .O(\txn_fifo_nxt[2]_246 [31]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][32]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [32]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[32] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[8]),
        .O(\txn_fifo_nxt[2]_246 [32]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][33]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [33]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[33] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[9]),
        .O(\txn_fifo_nxt[2]_246 [33]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][34]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [34]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[34] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[10]),
        .O(\txn_fifo_nxt[2]_246 [34]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][35]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [35]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[35] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[11]),
        .O(\txn_fifo_nxt[2]_246 [35]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][36]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [36]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[36] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[12]),
        .O(\txn_fifo_nxt[2]_246 [36]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][37]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [37]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[37] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[13]),
        .O(\txn_fifo_nxt[2]_246 [37]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][38]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [38]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[38] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[14]),
        .O(\txn_fifo_nxt[2]_246 [38]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][39]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [39]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[39] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[15]),
        .O(\txn_fifo_nxt[2]_246 [39]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][40]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [40]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[40] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[16]),
        .O(\txn_fifo_nxt[2]_246 [40]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[2][44]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [44]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[44] ),
        .I3(select_periodic_read_nxt),
        .I4(cmd[0]),
        .O(\txn_fifo_nxt[2]_246 [44]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \txn_fifo[2][45]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [45]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(cmd[1]),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[2]_246 [45]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \txn_fifo[2][46]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [46]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(cmd[2]),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[2]_246 [46]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \txn_fifo[2][47]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [47]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(1'b0),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[2]_246 [47]));
  LUT6 #(
    .INIT(64'h8888888888B88888)) 
    \txn_fifo[2][48]_i_1 
       (.I0(\txn_fifo_reg[2]_192 [48]),
        .I1(\txn_fifo[2][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[44] ),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[2]_246 [48]));
  LUT6 #(
    .INIT(64'hFFFFEAAA55557FFF)) 
    \txn_fifo[2][48]_i_2 
       (.I0(txn_fifo_wptr[0]),
        .I1(accept_reg_n_0),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(useAdr),
        .I4(select_periodic_read),
        .I5(txn_fifo_wptr[1]),
        .O(\txn_fifo[2][48]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][0]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [0]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[0] ),
        .I3(select_periodic_read_nxt),
        .I4(bank[0]),
        .O(\txn_fifo_nxt[3]_245 [0]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][11]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [11]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[11] ),
        .I3(select_periodic_read_nxt),
        .I4(col[0]),
        .O(\txn_fifo_nxt[3]_245 [11]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][12]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [12]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[12] ),
        .I3(select_periodic_read_nxt),
        .I4(col[1]),
        .O(\txn_fifo_nxt[3]_245 [12]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][13]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [13]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[13] ),
        .I3(select_periodic_read_nxt),
        .I4(col[2]),
        .O(\txn_fifo_nxt[3]_245 [13]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][14]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [14]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[14] ),
        .I3(select_periodic_read_nxt),
        .I4(col[3]),
        .O(\txn_fifo_nxt[3]_245 [14]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][15]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [15]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[15] ),
        .I3(select_periodic_read_nxt),
        .I4(col[4]),
        .O(\txn_fifo_nxt[3]_245 [15]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][16]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [16]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[16] ),
        .I3(select_periodic_read_nxt),
        .I4(col[5]),
        .O(\txn_fifo_nxt[3]_245 [16]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][17]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [17]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[17] ),
        .I3(select_periodic_read_nxt),
        .I4(col[6]),
        .O(\txn_fifo_nxt[3]_245 [17]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][1]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [1]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[1] ),
        .I3(select_periodic_read_nxt),
        .I4(bank[1]),
        .O(\txn_fifo_nxt[3]_245 [1]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][24]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [24]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[24] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[0]),
        .O(\txn_fifo_nxt[3]_245 [24]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][25]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [25]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[25] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[1]),
        .O(\txn_fifo_nxt[3]_245 [25]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][26]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [26]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[26] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[2]),
        .O(\txn_fifo_nxt[3]_245 [26]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][27]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [27]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[27] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[3]),
        .O(\txn_fifo_nxt[3]_245 [27]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][28]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [28]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[28] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[4]),
        .O(\txn_fifo_nxt[3]_245 [28]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][29]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [29]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[29] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[5]),
        .O(\txn_fifo_nxt[3]_245 [29]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][2]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [2]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[2] ),
        .I3(select_periodic_read_nxt),
        .I4(group),
        .O(\txn_fifo_nxt[3]_245 [2]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][30]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [30]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[30] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[6]),
        .O(\txn_fifo_nxt[3]_245 [30]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][31]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [31]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[31] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[7]),
        .O(\txn_fifo_nxt[3]_245 [31]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][32]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [32]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[32] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[8]),
        .O(\txn_fifo_nxt[3]_245 [32]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][33]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [33]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[33] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[9]),
        .O(\txn_fifo_nxt[3]_245 [33]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][34]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [34]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[34] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[10]),
        .O(\txn_fifo_nxt[3]_245 [34]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][35]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [35]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[35] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[11]),
        .O(\txn_fifo_nxt[3]_245 [35]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][36]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [36]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[36] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[12]),
        .O(\txn_fifo_nxt[3]_245 [36]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][37]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [37]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[37] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[13]),
        .O(\txn_fifo_nxt[3]_245 [37]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][38]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [38]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[38] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[14]),
        .O(\txn_fifo_nxt[3]_245 [38]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][39]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [39]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[39] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[15]),
        .O(\txn_fifo_nxt[3]_245 [39]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][40]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [40]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[40] ),
        .I3(select_periodic_read_nxt),
        .I4(row_mc_phy[16]),
        .O(\txn_fifo_nxt[3]_245 [40]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \txn_fifo[3][44]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [44]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[44] ),
        .I3(select_periodic_read_nxt),
        .I4(cmd[0]),
        .O(\txn_fifo_nxt[3]_245 [44]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \txn_fifo[3][45]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [45]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(cmd[1]),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[3]_245 [45]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \txn_fifo[3][46]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [46]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(cmd[2]),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[3]_245 [46]));
  LUT6 #(
    .INIT(64'hB8B8B8B8B888B8B8)) 
    \txn_fifo[3][47]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [47]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(1'b0),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[3]_245 [47]));
  LUT6 #(
    .INIT(64'h8888888888B88888)) 
    \txn_fifo[3][48]_i_1 
       (.I0(\txn_fifo_reg[3]_193 [48]),
        .I1(\txn_fifo[3][48]_i_2_n_0 ),
        .I2(\periodic_read_address_reg_n_0_[44] ),
        .I3(periodic_read_push_safe),
        .I4(periodic_read_block_dly3),
        .I5(txn_fifo_full),
        .O(\txn_fifo_nxt[3]_245 [48]));
  LUT6 #(
    .INIT(64'hFDDDDDDD57777777)) 
    \txn_fifo[3][48]_i_2 
       (.I0(txn_fifo_wptr[1]),
        .I1(select_periodic_read),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg[0]_0 ),
        .I4(accept_reg_n_0),
        .I5(txn_fifo_wptr[0]),
        .O(\txn_fifo[3][48]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h2418824182411824)) 
    txn_fifo_empty_i_1
       (.I0(txn_fifo_wptr[1]),
        .I1(txn_fifo_empty_i_2__2_n_0),
        .I2(txn_fifo_wptr[0]),
        .I3(txn_fifo_rptr[1]),
        .I4(txn_fifo_rptr[0]),
        .I5(\cas_fifo_wptr[1]_i_2_n_0 ),
        .O(txn_fifo_empty_nxt));
  (* SOFT_HLUTNM = "soft_lutpair2507" *) 
  LUT4 #(
    .INIT(16'h1555)) 
    txn_fifo_empty_i_2__2
       (.I0(select_periodic_read),
        .I1(useAdr),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(accept_reg_n_0),
        .O(txn_fifo_empty_i_2__2_n_0));
  FDRE txn_fifo_empty_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_empty_nxt),
        .Q(txn_fifo_empty_reg_n_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4BB4)) 
    txn_fifo_full_i_1
       (.I0(txn_fifo_wptr[0]),
        .I1(txn_fifo_rptr[0]),
        .I2(txn_fifo_wptr[1]),
        .I3(txn_fifo_rptr[1]),
        .O(txn_fifo_full_nxt));
  FDRE txn_fifo_full_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_full_nxt),
        .Q(txn_fifo_full),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[0]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [0]),
        .I2(\txn_fifo_output[0]_i_2_n_0 ),
        .I3(\txn_fifo_output[0]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [0]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[0]));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[0]_i_2 
       (.I0(\txn_fifo_nxt[1]_247 [0]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[0]_i_3 
       (.I0(\txn_fifo_nxt[3]_245 [0]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[11]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [11]),
        .I2(\txn_fifo_output[11]_i_2_n_0 ),
        .I3(\txn_fifo_output[11]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [11]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[11]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[11]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [11]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[11]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[11]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [11]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[12]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [12]),
        .I2(\txn_fifo_output[12]_i_2_n_0 ),
        .I3(\txn_fifo_output[12]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [12]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[12]));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[12]_i_2 
       (.I0(\txn_fifo_nxt[1]_247 [12]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[12]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[12]_i_3 
       (.I0(\txn_fifo_nxt[3]_245 [12]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[12]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[13]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [13]),
        .I2(\txn_fifo_output[13]_i_2_n_0 ),
        .I3(\txn_fifo_output[13]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [13]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[13]));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[13]_i_2 
       (.I0(\txn_fifo_nxt[1]_247 [13]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[13]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[13]_i_3 
       (.I0(\txn_fifo_nxt[3]_245 [13]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[14]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [14]),
        .I2(\txn_fifo_output[14]_i_2_n_0 ),
        .I3(\txn_fifo_output[14]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [14]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[14]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[14]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [14]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[14]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[14]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [14]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[15]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [15]),
        .I2(\txn_fifo_output[15]_i_2_n_0 ),
        .I3(\txn_fifo_output[15]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [15]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[15]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[15]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [15]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[15]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[15]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [15]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[16]_i_1 
       (.I0(\txn_fifo_output[48]_i_5_n_0 ),
        .I1(\txn_fifo_nxt[2]_246 [16]),
        .I2(\txn_fifo_output[16]_i_2_n_0 ),
        .I3(\txn_fifo_output[16]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[0]_248 [16]),
        .I5(\txn_fifo_output[48]_i_2_n_0 ),
        .O(txn_fifo_output_nxt[16]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[16]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [16]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[16]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[16]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [16]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[16]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[17]_i_1 
       (.I0(\txn_fifo_output[48]_i_5_n_0 ),
        .I1(\txn_fifo_nxt[2]_246 [17]),
        .I2(\txn_fifo_output[17]_i_2_n_0 ),
        .I3(\txn_fifo_output[17]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[0]_248 [17]),
        .I5(\txn_fifo_output[48]_i_2_n_0 ),
        .O(txn_fifo_output_nxt[17]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[17]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [17]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[17]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[17]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [17]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[17]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[1]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [1]),
        .I2(\txn_fifo_output[1]_i_2_n_0 ),
        .I3(\txn_fifo_output[1]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [1]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[1]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[1]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [1]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[1]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [1]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[24]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [24]),
        .I2(\txn_fifo_output[24]_i_2_n_0 ),
        .I3(\txn_fifo_output[24]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [24]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[24]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[24]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [24]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[24]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[24]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [24]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[24]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[25]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [25]),
        .I2(\txn_fifo_output[25]_i_2_n_0 ),
        .I3(\txn_fifo_output[25]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [25]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[25]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[25]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [25]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[25]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[25]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [25]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[25]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[26]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [26]),
        .I2(\txn_fifo_output[26]_i_2_n_0 ),
        .I3(\txn_fifo_output[26]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [26]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[26]));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[26]_i_2 
       (.I0(\txn_fifo_nxt[1]_247 [26]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[26]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[26]_i_3 
       (.I0(\txn_fifo_nxt[3]_245 [26]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[26]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[27]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [27]),
        .I2(\txn_fifo_output[27]_i_2_n_0 ),
        .I3(\txn_fifo_output[27]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [27]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[27]));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[27]_i_2 
       (.I0(\txn_fifo_nxt[1]_247 [27]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[27]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[27]_i_3 
       (.I0(\txn_fifo_nxt[3]_245 [27]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[27]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[28]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [28]),
        .I2(\txn_fifo_output[28]_i_2_n_0 ),
        .I3(\txn_fifo_output[28]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [28]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[28]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[28]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [28]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[28]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[28]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [28]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[28]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[29]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [29]),
        .I2(\txn_fifo_output[29]_i_2_n_0 ),
        .I3(\txn_fifo_output[29]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [29]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[29]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[29]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [29]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[29]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[29]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [29]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[29]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[2]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [2]),
        .I2(\txn_fifo_output[2]_i_2_n_0 ),
        .I3(\txn_fifo_output[2]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [2]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[2]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[2]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [2]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[2]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [2]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[30]_i_1 
       (.I0(\txn_fifo_output[48]_i_5_n_0 ),
        .I1(\txn_fifo_nxt[2]_246 [30]),
        .I2(\txn_fifo_output[30]_i_2_n_0 ),
        .I3(\txn_fifo_output[30]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[0]_248 [30]),
        .I5(\txn_fifo_output[48]_i_2_n_0 ),
        .O(txn_fifo_output_nxt[30]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[30]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [30]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[30]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[30]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [30]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[30]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[31]_i_1 
       (.I0(\txn_fifo_output[48]_i_5_n_0 ),
        .I1(\txn_fifo_nxt[2]_246 [31]),
        .I2(\txn_fifo_output[31]_i_2_n_0 ),
        .I3(\txn_fifo_output[31]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[0]_248 [31]),
        .I5(\txn_fifo_output[48]_i_2_n_0 ),
        .O(txn_fifo_output_nxt[31]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[31]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [31]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[31]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[31]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [31]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[31]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[32]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [32]),
        .I2(\txn_fifo_output[32]_i_2_n_0 ),
        .I3(\txn_fifo_output[32]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [32]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[32]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[32]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [32]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[32]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[32]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [32]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[32]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[33]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [33]),
        .I2(\txn_fifo_output[33]_i_2_n_0 ),
        .I3(\txn_fifo_output[33]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [33]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[33]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[33]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [33]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[33]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[33]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [33]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[33]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[34]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [34]),
        .I2(\txn_fifo_output[34]_i_2_n_0 ),
        .I3(\txn_fifo_output[34]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [34]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[34]));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[34]_i_2 
       (.I0(\txn_fifo_nxt[1]_247 [34]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[34]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[34]_i_3 
       (.I0(\txn_fifo_nxt[3]_245 [34]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[34]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[35]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [35]),
        .I2(\txn_fifo_output[35]_i_2_n_0 ),
        .I3(\txn_fifo_output[35]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [35]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[35]));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[35]_i_2 
       (.I0(\txn_fifo_nxt[1]_247 [35]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[35]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[35]_i_3 
       (.I0(\txn_fifo_nxt[3]_245 [35]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[35]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[36]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [36]),
        .I2(\txn_fifo_output[36]_i_2_n_0 ),
        .I3(\txn_fifo_output[36]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [36]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[36]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[36]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [36]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[36]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[36]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [36]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[36]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[37]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [37]),
        .I2(\txn_fifo_output[37]_i_2_n_0 ),
        .I3(\txn_fifo_output[37]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [37]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[37]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[37]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [37]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[37]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[37]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [37]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[37]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[38]_i_1 
       (.I0(\txn_fifo_output[48]_i_5_n_0 ),
        .I1(\txn_fifo_nxt[2]_246 [38]),
        .I2(\txn_fifo_output[38]_i_2_n_0 ),
        .I3(\txn_fifo_output[38]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[0]_248 [38]),
        .I5(\txn_fifo_output[48]_i_2_n_0 ),
        .O(txn_fifo_output_nxt[38]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[38]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [38]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[38]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[38]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [38]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[38]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[39]_i_1 
       (.I0(\txn_fifo_output[48]_i_5_n_0 ),
        .I1(\txn_fifo_nxt[2]_246 [39]),
        .I2(\txn_fifo_output[39]_i_2_n_0 ),
        .I3(\txn_fifo_output[39]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[0]_248 [39]),
        .I5(\txn_fifo_output[48]_i_2_n_0 ),
        .O(txn_fifo_output_nxt[39]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[39]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [39]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[39]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[39]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [39]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[39]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[40]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [40]),
        .I2(\txn_fifo_output[40]_i_2_n_0 ),
        .I3(\txn_fifo_output[40]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [40]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[40]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[40]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [40]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[40]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[40]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [40]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[40]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[44]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [44]),
        .I2(\txn_fifo_output[44]_i_2_n_0 ),
        .I3(\txn_fifo_output[44]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [44]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[44]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[44]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [44]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[44]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[44]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [44]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[44]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[45]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [45]),
        .I2(\txn_fifo_output[45]_i_2_n_0 ),
        .I3(\txn_fifo_output[45]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [45]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[45]));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[45]_i_2 
       (.I0(\txn_fifo_nxt[1]_247 [45]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[45]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[45]_i_3 
       (.I0(\txn_fifo_nxt[3]_245 [45]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[45]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[46]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [46]),
        .I2(\txn_fifo_output[46]_i_2_n_0 ),
        .I3(\txn_fifo_output[46]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [46]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[46]));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[46]_i_2 
       (.I0(\txn_fifo_nxt[1]_247 [46]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[46]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[46]_i_3 
       (.I0(\txn_fifo_nxt[3]_245 [46]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[46]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[47]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [47]),
        .I2(\txn_fifo_output[47]_i_2_n_0 ),
        .I3(\txn_fifo_output[47]_i_3_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [47]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[47]));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[47]_i_2 
       (.I0(\txn_fifo_nxt[3]_245 [47]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[47]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[47]_i_3 
       (.I0(\txn_fifo_nxt[1]_247 [47]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[47]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[48]_i_1 
       (.I0(\txn_fifo_output[48]_i_2_n_0 ),
        .I1(\txn_fifo_nxt[0]_248 [48]),
        .I2(\txn_fifo_output[48]_i_3_n_0 ),
        .I3(\txn_fifo_output[48]_i_4_n_0 ),
        .I4(\txn_fifo_nxt[2]_246 [48]),
        .I5(\txn_fifo_output[48]_i_5_n_0 ),
        .O(txn_fifo_output_nxt[48]));
  LUT4 #(
    .INIT(16'hF7AE)) 
    \txn_fifo_output[48]_i_2 
       (.I0(txn_fifo_rptr[1]),
        .I1(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(txn_fifo_rptr[0]),
        .O(\txn_fifo_output[48]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h82880000)) 
    \txn_fifo_output[48]_i_3 
       (.I0(\txn_fifo_nxt[3]_245 [48]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[48]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[48]_i_4 
       (.I0(\txn_fifo_nxt[1]_247 [48]),
        .I1(txn_fifo_rptr[0]),
        .I2(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I4(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[48]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hF4BF)) 
    \txn_fifo_output[48]_i_5 
       (.I0(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I1(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I2(txn_fifo_rptr[0]),
        .I3(txn_fifo_rptr[1]),
        .O(\txn_fifo_output[48]_i_5_n_0 ));
  FDRE \txn_fifo_output_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[11] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[11]),
        .Q(\txn_fifo_output_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[12] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[12]),
        .Q(\txn_fifo_output_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[13] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[13]),
        .Q(\txn_fifo_output_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[14] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[14]),
        .Q(\txn_fifo_output_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[15] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[15]),
        .Q(\txn_fifo_output_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[16] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[16]),
        .Q(\txn_fifo_output_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[17] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[17]),
        .Q(\txn_fifo_output_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[24] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[24]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[25] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[25]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[26] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[26]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[27] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[27]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[28] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[28]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[29] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[29]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[30] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[30]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[31] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[31]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[32] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[32]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[33] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[33]),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[34] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[34]),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[35] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[35]),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[36] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[36]),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[37] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[37]),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[38] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[38]),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[39] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[39]),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[40] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[40]),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[44] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[44]),
        .Q(\txn_fifo_output_reg_n_0_[44] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[45] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[45]),
        .Q(\txn_fifo_output_reg_n_0_[45] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[46] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[46]),
        .Q(\txn_fifo_output_reg_n_0_[46] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[47] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[47]),
        .Q(\txn_fifo_output_reg_n_0_[47] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[48] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_output_nxt[48]),
        .Q(\txn_fifo_output_reg_n_0_[48] ),
        .R(1'b0));
  FDRE \txn_fifo_reg[0][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [0]),
        .Q(\txn_fifo_reg[0]_190 [0]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][11] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [11]),
        .Q(\txn_fifo_reg[0]_190 [11]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][12] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [12]),
        .Q(\txn_fifo_reg[0]_190 [12]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][13] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [13]),
        .Q(\txn_fifo_reg[0]_190 [13]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][14] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [14]),
        .Q(\txn_fifo_reg[0]_190 [14]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][15] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [15]),
        .Q(\txn_fifo_reg[0]_190 [15]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][16] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [16]),
        .Q(\txn_fifo_reg[0]_190 [16]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][17] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [17]),
        .Q(\txn_fifo_reg[0]_190 [17]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [1]),
        .Q(\txn_fifo_reg[0]_190 [1]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][24] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [24]),
        .Q(\txn_fifo_reg[0]_190 [24]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][25] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [25]),
        .Q(\txn_fifo_reg[0]_190 [25]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][26] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [26]),
        .Q(\txn_fifo_reg[0]_190 [26]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][27] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [27]),
        .Q(\txn_fifo_reg[0]_190 [27]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][28] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [28]),
        .Q(\txn_fifo_reg[0]_190 [28]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][29] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [29]),
        .Q(\txn_fifo_reg[0]_190 [29]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [2]),
        .Q(\txn_fifo_reg[0]_190 [2]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][30] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [30]),
        .Q(\txn_fifo_reg[0]_190 [30]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][31] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [31]),
        .Q(\txn_fifo_reg[0]_190 [31]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][32] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [32]),
        .Q(\txn_fifo_reg[0]_190 [32]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][33] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [33]),
        .Q(\txn_fifo_reg[0]_190 [33]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][34] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [34]),
        .Q(\txn_fifo_reg[0]_190 [34]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][35] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [35]),
        .Q(\txn_fifo_reg[0]_190 [35]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][36] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [36]),
        .Q(\txn_fifo_reg[0]_190 [36]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][37] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [37]),
        .Q(\txn_fifo_reg[0]_190 [37]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][38] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [38]),
        .Q(\txn_fifo_reg[0]_190 [38]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][39] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [39]),
        .Q(\txn_fifo_reg[0]_190 [39]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][40] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [40]),
        .Q(\txn_fifo_reg[0]_190 [40]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][44] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [44]),
        .Q(\txn_fifo_reg[0]_190 [44]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][45] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [45]),
        .Q(\txn_fifo_reg[0]_190 [45]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][46] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [46]),
        .Q(\txn_fifo_reg[0]_190 [46]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][47] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [47]),
        .Q(\txn_fifo_reg[0]_190 [47]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][48] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[0]_248 [48]),
        .Q(\txn_fifo_reg[0]_190 [48]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [0]),
        .Q(\txn_fifo_reg[1]_191 [0]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][11] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [11]),
        .Q(\txn_fifo_reg[1]_191 [11]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][12] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [12]),
        .Q(\txn_fifo_reg[1]_191 [12]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][13] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [13]),
        .Q(\txn_fifo_reg[1]_191 [13]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][14] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [14]),
        .Q(\txn_fifo_reg[1]_191 [14]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][15] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [15]),
        .Q(\txn_fifo_reg[1]_191 [15]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][16] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [16]),
        .Q(\txn_fifo_reg[1]_191 [16]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][17] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [17]),
        .Q(\txn_fifo_reg[1]_191 [17]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [1]),
        .Q(\txn_fifo_reg[1]_191 [1]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][24] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [24]),
        .Q(\txn_fifo_reg[1]_191 [24]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][25] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [25]),
        .Q(\txn_fifo_reg[1]_191 [25]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][26] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [26]),
        .Q(\txn_fifo_reg[1]_191 [26]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][27] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [27]),
        .Q(\txn_fifo_reg[1]_191 [27]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][28] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [28]),
        .Q(\txn_fifo_reg[1]_191 [28]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][29] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [29]),
        .Q(\txn_fifo_reg[1]_191 [29]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [2]),
        .Q(\txn_fifo_reg[1]_191 [2]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][30] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [30]),
        .Q(\txn_fifo_reg[1]_191 [30]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][31] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [31]),
        .Q(\txn_fifo_reg[1]_191 [31]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][32] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [32]),
        .Q(\txn_fifo_reg[1]_191 [32]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][33] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [33]),
        .Q(\txn_fifo_reg[1]_191 [33]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][34] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [34]),
        .Q(\txn_fifo_reg[1]_191 [34]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][35] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [35]),
        .Q(\txn_fifo_reg[1]_191 [35]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][36] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [36]),
        .Q(\txn_fifo_reg[1]_191 [36]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][37] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [37]),
        .Q(\txn_fifo_reg[1]_191 [37]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][38] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [38]),
        .Q(\txn_fifo_reg[1]_191 [38]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][39] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [39]),
        .Q(\txn_fifo_reg[1]_191 [39]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][40] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [40]),
        .Q(\txn_fifo_reg[1]_191 [40]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][44] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [44]),
        .Q(\txn_fifo_reg[1]_191 [44]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][45] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [45]),
        .Q(\txn_fifo_reg[1]_191 [45]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][46] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [46]),
        .Q(\txn_fifo_reg[1]_191 [46]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][47] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [47]),
        .Q(\txn_fifo_reg[1]_191 [47]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][48] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[1]_247 [48]),
        .Q(\txn_fifo_reg[1]_191 [48]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [0]),
        .Q(\txn_fifo_reg[2]_192 [0]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][11] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [11]),
        .Q(\txn_fifo_reg[2]_192 [11]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][12] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [12]),
        .Q(\txn_fifo_reg[2]_192 [12]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][13] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [13]),
        .Q(\txn_fifo_reg[2]_192 [13]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][14] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [14]),
        .Q(\txn_fifo_reg[2]_192 [14]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][15] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [15]),
        .Q(\txn_fifo_reg[2]_192 [15]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][16] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [16]),
        .Q(\txn_fifo_reg[2]_192 [16]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][17] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [17]),
        .Q(\txn_fifo_reg[2]_192 [17]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [1]),
        .Q(\txn_fifo_reg[2]_192 [1]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][24] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [24]),
        .Q(\txn_fifo_reg[2]_192 [24]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][25] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [25]),
        .Q(\txn_fifo_reg[2]_192 [25]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][26] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [26]),
        .Q(\txn_fifo_reg[2]_192 [26]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][27] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [27]),
        .Q(\txn_fifo_reg[2]_192 [27]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][28] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [28]),
        .Q(\txn_fifo_reg[2]_192 [28]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][29] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [29]),
        .Q(\txn_fifo_reg[2]_192 [29]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [2]),
        .Q(\txn_fifo_reg[2]_192 [2]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][30] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [30]),
        .Q(\txn_fifo_reg[2]_192 [30]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][31] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [31]),
        .Q(\txn_fifo_reg[2]_192 [31]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][32] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [32]),
        .Q(\txn_fifo_reg[2]_192 [32]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][33] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [33]),
        .Q(\txn_fifo_reg[2]_192 [33]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][34] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [34]),
        .Q(\txn_fifo_reg[2]_192 [34]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][35] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [35]),
        .Q(\txn_fifo_reg[2]_192 [35]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][36] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [36]),
        .Q(\txn_fifo_reg[2]_192 [36]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][37] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [37]),
        .Q(\txn_fifo_reg[2]_192 [37]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][38] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [38]),
        .Q(\txn_fifo_reg[2]_192 [38]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][39] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [39]),
        .Q(\txn_fifo_reg[2]_192 [39]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][40] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [40]),
        .Q(\txn_fifo_reg[2]_192 [40]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][44] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [44]),
        .Q(\txn_fifo_reg[2]_192 [44]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][45] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [45]),
        .Q(\txn_fifo_reg[2]_192 [45]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][46] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [46]),
        .Q(\txn_fifo_reg[2]_192 [46]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][47] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [47]),
        .Q(\txn_fifo_reg[2]_192 [47]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][48] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[2]_246 [48]),
        .Q(\txn_fifo_reg[2]_192 [48]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [0]),
        .Q(\txn_fifo_reg[3]_193 [0]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][11] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [11]),
        .Q(\txn_fifo_reg[3]_193 [11]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][12] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [12]),
        .Q(\txn_fifo_reg[3]_193 [12]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][13] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [13]),
        .Q(\txn_fifo_reg[3]_193 [13]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][14] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [14]),
        .Q(\txn_fifo_reg[3]_193 [14]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][15] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [15]),
        .Q(\txn_fifo_reg[3]_193 [15]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][16] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [16]),
        .Q(\txn_fifo_reg[3]_193 [16]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][17] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [17]),
        .Q(\txn_fifo_reg[3]_193 [17]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [1]),
        .Q(\txn_fifo_reg[3]_193 [1]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][24] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [24]),
        .Q(\txn_fifo_reg[3]_193 [24]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][25] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [25]),
        .Q(\txn_fifo_reg[3]_193 [25]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][26] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [26]),
        .Q(\txn_fifo_reg[3]_193 [26]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][27] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [27]),
        .Q(\txn_fifo_reg[3]_193 [27]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][28] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [28]),
        .Q(\txn_fifo_reg[3]_193 [28]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][29] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [29]),
        .Q(\txn_fifo_reg[3]_193 [29]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][2] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [2]),
        .Q(\txn_fifo_reg[3]_193 [2]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][30] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [30]),
        .Q(\txn_fifo_reg[3]_193 [30]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][31] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [31]),
        .Q(\txn_fifo_reg[3]_193 [31]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][32] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [32]),
        .Q(\txn_fifo_reg[3]_193 [32]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][33] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [33]),
        .Q(\txn_fifo_reg[3]_193 [33]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][34] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [34]),
        .Q(\txn_fifo_reg[3]_193 [34]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][35] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [35]),
        .Q(\txn_fifo_reg[3]_193 [35]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][36] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [36]),
        .Q(\txn_fifo_reg[3]_193 [36]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][37] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [37]),
        .Q(\txn_fifo_reg[3]_193 [37]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][38] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [38]),
        .Q(\txn_fifo_reg[3]_193 [38]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][39] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [39]),
        .Q(\txn_fifo_reg[3]_193 [39]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][40] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [40]),
        .Q(\txn_fifo_reg[3]_193 [40]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][44] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [44]),
        .Q(\txn_fifo_reg[3]_193 [44]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][45] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [45]),
        .Q(\txn_fifo_reg[3]_193 [45]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][46] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [46]),
        .Q(\txn_fifo_reg[3]_193 [46]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][47] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [47]),
        .Q(\txn_fifo_reg[3]_193 [47]),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][48] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_nxt[3]_245 [48]),
        .Q(\txn_fifo_reg[3]_193 [48]),
        .R(rst_r1));
  LUT3 #(
    .INIT(8'h9A)) 
    \txn_fifo_rptr[0]_i_1 
       (.I0(txn_fifo_rptr[0]),
        .I1(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I2(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .O(txn_fifo_rptr_nxt[0]));
  LUT4 #(
    .INIT(16'hAA6A)) 
    \txn_fifo_rptr[1]_i_1 
       (.I0(txn_fifo_rptr[1]),
        .I1(txn_fifo_rptr[0]),
        .I2(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .I3(\txn_fifo_rptr[1]_i_2_n_0 ),
        .O(txn_fifo_rptr_nxt[1]));
  LUT5 #(
    .INIT(32'hFBFFAAFA)) 
    \txn_fifo_rptr[1]_i_2 
       (.I0(grSt[2]),
        .I1(actReqR_reg_0),
        .I2(cas_fifo_full),
        .I3(grSt[0]),
        .I4(grSt[1]),
        .O(\txn_fifo_rptr[1]_i_2_n_0 ));
  FDRE \txn_fifo_rptr_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_rptr_nxt[0]),
        .Q(txn_fifo_rptr[0]),
        .R(rst_r1));
  FDRE \txn_fifo_rptr_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_rptr_nxt[1]),
        .Q(txn_fifo_rptr[1]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2507" *) 
  LUT5 #(
    .INIT(32'h55556AAA)) 
    \txn_fifo_wptr[0]_i_1__2 
       (.I0(txn_fifo_wptr[0]),
        .I1(accept_reg_n_0),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(useAdr),
        .I4(select_periodic_read),
        .O(\txn_fifo_wptr[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h56666666AAAAAAAA)) 
    \txn_fifo_wptr[1]_i_1__2 
       (.I0(txn_fifo_wptr[1]),
        .I1(select_periodic_read),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg[0]_0 ),
        .I4(accept_reg_n_0),
        .I5(txn_fifo_wptr[0]),
        .O(txn_fifo_wptr_nxt));
  FDRE \txn_fifo_wptr_reg[0] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_wptr[0]_i_1__2_n_0 ),
        .Q(txn_fifo_wptr[0]),
        .R(rst_r1));
  FDRE \txn_fifo_wptr_reg[1] 
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(txn_fifo_wptr_nxt),
        .Q(txn_fifo_wptr[1]),
        .R(rst_r1));
  FDRE underfill_done_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(underfill_done_nxt),
        .Q(underfill_done),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'h4444444444444454)) 
    wrReqR_i_1
       (.I0(clrReq13_out),
        .I1(wrReqR_i_2_n_0),
        .I2(wrReqR_i_3_n_0),
        .I3(wrReqR_i_4_n_0),
        .I4(\FSM_sequential_gr_cas_state[2]_i_6_n_0 ),
        .I5(wrReqR_i_5_n_0),
        .O(wrReqR_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2506" *) 
  LUT5 #(
    .INIT(32'hAAAAAAEA)) 
    wrReqR_i_2
       (.I0(wrReqR),
        .I1(gr_cas_state[1]),
        .I2(underfill_done),
        .I3(gr_cas_state[0]),
        .I4(gr_cas_state[2]),
        .O(wrReqR_i_2_n_0));
  LUT6 #(
    .INIT(64'h0004040400040004)) 
    wrReqR_i_3
       (.I0(gr_cas_state[1]),
        .I1(rdReqR_i_2_n_0),
        .I2(\FSM_sequential_gr_cas_state[2]_i_7__1_n_0 ),
        .I3(cas_fifo_empty_reg_n_0),
        .I4(\txn_fifo_rptr[1]_i_2_n_0 ),
        .I5(\FSM_sequential_grSt[1]_i_3_n_0 ),
        .O(wrReqR_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2524" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    wrReqR_i_4
       (.I0(\txn_fifo_output_reg_n_0_[46] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(wrReqR_i_6_n_0),
        .O(wrReqR_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2524" *) 
  LUT3 #(
    .INIT(8'hC5)) 
    wrReqR_i_5
       (.I0(wrReqR_i_7_n_0),
        .I1(\txn_fifo_output_reg_n_0_[44] ),
        .I2(cas_fifo_empty_reg_n_0),
        .O(wrReqR_i_5_n_0));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    wrReqR_i_6
       (.I0(\cas_pend_fifo_reg_n_0_[2][46] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][46] ),
        .I2(\cas_pend_fifo_reg[0]_194 [46]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][46] ),
        .O(wrReqR_i_6_n_0));
  LUT6 #(
    .INIT(64'h3300550F33FF550F)) 
    wrReqR_i_7
       (.I0(\cas_pend_fifo_reg_n_0_[2][44] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][44] ),
        .I2(\cas_pend_fifo_reg[0]_194 [44]),
        .I3(cas_fifo_rptr[1]),
        .I4(cas_fifo_rptr[0]),
        .I5(\cas_pend_fifo_reg_n_0_[1][44] ),
        .O(wrReqR_i_7_n_0));
  FDRE wrReqR_reg
       (.C(per_rd_accept_reg_0),
        .CE(1'b1),
        .D(wrReqR_i_1_n_0),
        .Q(wrReqR),
        .R(rst_r1));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_group" *) 
module ddr4_0_ddr4_v2_2_17_mc_group_10
   (cmdAP,
    refOK_reg_0,
    accept_reg_0,
    wrReqR_reg_0,
    actReqR_reg_0,
    preReqR_reg_0,
    rdReqR_reg_0,
    cmdRmw_reg_0,
    cmd_group_cas,
    cmdGroupP,
    Q,
    \cmd_bank_cas_reg[1]_0 ,
    calDone_gated_reg,
    \buf_fifo_reg[0][0]_0 ,
    \buf_fifo_reg[0][1]_0 ,
    \buf_fifo_reg[2][2]_0 ,
    \buf_fifo_reg[0][3]_0 ,
    \buf_fifo_reg[2][4]_0 ,
    cmdBuf,
    \cmdBankP_reg[1]_0 ,
    \cmdCol_reg[9]_0 ,
    rst_r1_reg_0,
    grAccept_ns,
    underfill_done_reg_0,
    SR,
    clrReq17_out,
    \cas_fifo_rptr_reg[0]_0 ,
    tranSentC,
    useAdr,
    \txn_fifo_wptr_reg[0]_0 ,
    \buf_fifo_reg[1][0]_0 ,
    \buf_fifo_reg[1][1]_0 ,
    \buf_fifo_reg[1][2]_0 ,
    \buf_fifo_reg[1][3]_0 ,
    \buf_fifo_reg[1][4]_0 ,
    cmd,
    row_mc_phy,
    col,
    group,
    bank,
    \FSM_sequential_grSt_reg[0]_0 ,
    ref_req_dly4,
    preReqR_reg_1,
    \FSM_sequential_grSt_reg[0]_1 ,
    refReq);
  output [0:0]cmdAP;
  output [0:0]refOK_reg_0;
  output accept_reg_0;
  output wrReqR_reg_0;
  output actReqR_reg_0;
  output preReqR_reg_0;
  output rdReqR_reg_0;
  output cmdRmw_reg_0;
  output [0:0]cmd_group_cas;
  output [0:0]cmdGroupP;
  output [19:0]Q;
  output [1:0]\cmd_bank_cas_reg[1]_0 ;
  output calDone_gated_reg;
  output \buf_fifo_reg[0][0]_0 ;
  output \buf_fifo_reg[0][1]_0 ;
  output \buf_fifo_reg[2][2]_0 ;
  output \buf_fifo_reg[0][3]_0 ;
  output \buf_fifo_reg[2][4]_0 ;
  output [4:0]cmdBuf;
  output [1:0]\cmdBankP_reg[1]_0 ;
  output [6:0]\cmdCol_reg[9]_0 ;
  input rst_r1_reg_0;
  input [0:0]grAccept_ns;
  input underfill_done_reg_0;
  input [0:0]SR;
  input clrReq17_out;
  input [0:0]\cas_fifo_rptr_reg[0]_0 ;
  input tranSentC;
  input useAdr;
  input \txn_fifo_wptr_reg[0]_0 ;
  input \buf_fifo_reg[1][0]_0 ;
  input \buf_fifo_reg[1][1]_0 ;
  input \buf_fifo_reg[1][2]_0 ;
  input \buf_fifo_reg[1][3]_0 ;
  input \buf_fifo_reg[1][4]_0 ;
  input [2:0]cmd;
  input [16:0]row_mc_phy;
  input [6:0]col;
  input [0:0]group;
  input [1:0]bank;
  input [0:0]\FSM_sequential_grSt_reg[0]_0 ;
  input ref_req_dly4;
  input [0:0]preReqR_reg_1;
  input \FSM_sequential_grSt_reg[0]_1 ;
  input refReq;

  wire \FSM_sequential_grSt[0]_i_1__1_n_0 ;
  wire \FSM_sequential_grSt[0]_i_2__1_n_0 ;
  wire \FSM_sequential_grSt[1]_i_1__1_n_0 ;
  wire \FSM_sequential_grSt[1]_i_2__0_n_0 ;
  wire \FSM_sequential_grSt[1]_i_3__1_n_0 ;
  wire \FSM_sequential_grSt[1]_i_4__0_n_0 ;
  wire \FSM_sequential_grSt[1]_i_5_n_0 ;
  wire \FSM_sequential_grSt[1]_i_6__1_n_0 ;
  wire \FSM_sequential_grSt[2]_i_1__0_n_0 ;
  wire \FSM_sequential_grSt[2]_i_2__0_n_0 ;
  wire \FSM_sequential_grSt[2]_i_3__0_n_0 ;
  wire \FSM_sequential_grSt[2]_i_4__2_n_0 ;
  wire \FSM_sequential_grSt[2]_i_5__2_n_0 ;
  wire \FSM_sequential_grSt[2]_i_6__0_n_0 ;
  wire \FSM_sequential_grSt[2]_i_7__1_n_0 ;
  wire [0:0]\FSM_sequential_grSt_reg[0]_0 ;
  wire \FSM_sequential_grSt_reg[0]_1 ;
  wire \FSM_sequential_gr_cas_state[2]_i_1__1_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_3_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_5_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_6__1_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_8__2_n_0 ;
  wire [19:0]Q;
  wire [0:0]SR;
  wire accept_reg_0;
  wire actReqR_i_1__1_n_0;
  wire actReqR_i_2__0_n_0;
  wire actReqR_i_3_n_0;
  wire actReqR_i_4_n_0;
  wire actReqR_reg_0;
  wire \ap_cntr[0][0][0][0]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][0][1]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][0][2]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][0][3]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][0][4]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][0][4]_i_2__1_n_0 ;
  wire \ap_cntr[0][0][0][4]_i_3__1_n_0 ;
  wire \ap_cntr[0][0][1][0]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][1][1]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][1][2]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][1][3]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][1][4]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][1][4]_i_2__1_n_0 ;
  wire \ap_cntr[0][0][2][0]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][2][1]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][2][2]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][2][3]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][2][4]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][2][4]_i_2__1_n_0 ;
  wire \ap_cntr[0][0][2][4]_i_3__0_n_0 ;
  wire \ap_cntr[0][0][3][0]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][3][1]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][3][2]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][3][3]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][3][4]_i_1__1_n_0 ;
  wire \ap_cntr[0][0][3][4]_i_2__1_n_0 ;
  wire \ap_cntr[0][0][3][4]_i_3__1_n_0 ;
  wire \ap_cntr_expired[0][0][0]_i_1__2_n_0 ;
  wire \ap_cntr_expired[0][0][1]_i_1_n_0 ;
  wire \ap_cntr_expired[0][0][2]_i_1__1_n_0 ;
  wire \ap_cntr_expired[0][0][3]_i_1__1_n_0 ;
  wire \ap_cntr_reg_n_0_[0][0][0][0] ;
  wire \ap_cntr_reg_n_0_[0][0][0][1] ;
  wire \ap_cntr_reg_n_0_[0][0][0][2] ;
  wire \ap_cntr_reg_n_0_[0][0][0][3] ;
  wire \ap_cntr_reg_n_0_[0][0][0][4] ;
  wire \ap_cntr_reg_n_0_[0][0][1][0] ;
  wire \ap_cntr_reg_n_0_[0][0][1][1] ;
  wire \ap_cntr_reg_n_0_[0][0][1][2] ;
  wire \ap_cntr_reg_n_0_[0][0][1][3] ;
  wire \ap_cntr_reg_n_0_[0][0][1][4] ;
  wire \ap_cntr_reg_n_0_[0][0][2][0] ;
  wire \ap_cntr_reg_n_0_[0][0][2][1] ;
  wire \ap_cntr_reg_n_0_[0][0][2][2] ;
  wire \ap_cntr_reg_n_0_[0][0][2][3] ;
  wire \ap_cntr_reg_n_0_[0][0][2][4] ;
  wire \ap_cntr_reg_n_0_[0][0][3][0] ;
  wire \ap_cntr_reg_n_0_[0][0][3][1] ;
  wire \ap_cntr_reg_n_0_[0][0][3][2] ;
  wire \ap_cntr_reg_n_0_[0][0][3][3] ;
  wire \ap_cntr_reg_n_0_[0][0][3][4] ;
  wire \ap_cntr_zero[0][0][0]_i_1__1_n_0 ;
  wire \ap_cntr_zero[0][0][1]_i_1__1_n_0 ;
  wire \ap_cntr_zero[0][0][1]_i_2_n_0 ;
  wire \ap_cntr_zero[0][0][1]_i_3_n_0 ;
  wire \ap_cntr_zero[0][0][1]_i_4_n_0 ;
  wire \ap_cntr_zero[0][0][2]_i_1__1_n_0 ;
  wire \ap_cntr_zero[0][0][3]_i_1__1_n_0 ;
  wire \ap_cntr_zero[0][0][3]_i_2_n_0 ;
  wire \ap_cntr_zero_reg_n_0_[0][0][0] ;
  wire \ap_cntr_zero_reg_n_0_[0][0][1] ;
  wire \ap_cntr_zero_reg_n_0_[0][0][2] ;
  wire \ap_cntr_zero_reg_n_0_[0][0][3] ;
  wire \ap_load_value[0]_i_1__1_n_0 ;
  wire \ap_load_value[0]_i_2__1_n_0 ;
  wire \ap_load_value[1]_i_1__1_n_0 ;
  wire \ap_load_value[2]_i_1__1_n_0 ;
  wire \ap_load_value[3]_i_1__1_n_0 ;
  wire \ap_load_value[3]_i_2__1_n_0 ;
  wire \ap_load_value[3]_i_3__1_n_0 ;
  wire \ap_load_value_reg_n_0_[0] ;
  wire \ap_load_value_reg_n_0_[1] ;
  wire \ap_load_value_reg_n_0_[2] ;
  wire \ap_load_value_reg_n_0_[3] ;
  wire [1:0]bank;
  wire \buf_fifo[0][0]_i_1__0_n_0 ;
  wire \buf_fifo[0][1]_i_1__0_n_0 ;
  wire \buf_fifo[0][2]_i_1__0_n_0 ;
  wire \buf_fifo[0][3]_i_1__0_n_0 ;
  wire \buf_fifo[0][4]_i_1__0_n_0 ;
  wire \buf_fifo[1][0]_i_1__0_n_0 ;
  wire \buf_fifo[1][1]_i_1__0_n_0 ;
  wire \buf_fifo[1][2]_i_1__0_n_0 ;
  wire \buf_fifo[1][3]_i_1__0_n_0 ;
  wire \buf_fifo[1][4]_i_1__0_n_0 ;
  wire \buf_fifo[2][0]_i_1__0_n_0 ;
  wire \buf_fifo[2][1]_i_1__0_n_0 ;
  wire \buf_fifo[2][2]_i_1__0_n_0 ;
  wire \buf_fifo[2][3]_i_1__0_n_0 ;
  wire \buf_fifo[2][4]_i_1__0_n_0 ;
  wire \buf_fifo[3][0]_i_1__0_n_0 ;
  wire \buf_fifo[3][1]_i_1__0_n_0 ;
  wire \buf_fifo[3][2]_i_1__0_n_0 ;
  wire \buf_fifo[3][3]_i_1__0_n_0 ;
  wire \buf_fifo[3][4]_i_1__0_n_0 ;
  wire \buf_fifo_reg[0][0]_0 ;
  wire \buf_fifo_reg[0][1]_0 ;
  wire \buf_fifo_reg[0][3]_0 ;
  wire \buf_fifo_reg[1][0]_0 ;
  wire \buf_fifo_reg[1][1]_0 ;
  wire \buf_fifo_reg[1][2]_0 ;
  wire \buf_fifo_reg[1][3]_0 ;
  wire \buf_fifo_reg[1][4]_0 ;
  wire \buf_fifo_reg[2][2]_0 ;
  wire \buf_fifo_reg[2][4]_0 ;
  wire \buf_fifo_reg_n_0_[0][0] ;
  wire \buf_fifo_reg_n_0_[0][1] ;
  wire \buf_fifo_reg_n_0_[0][2] ;
  wire \buf_fifo_reg_n_0_[0][3] ;
  wire \buf_fifo_reg_n_0_[0][4] ;
  wire \buf_fifo_reg_n_0_[1][0] ;
  wire \buf_fifo_reg_n_0_[1][1] ;
  wire \buf_fifo_reg_n_0_[1][2] ;
  wire \buf_fifo_reg_n_0_[1][3] ;
  wire \buf_fifo_reg_n_0_[1][4] ;
  wire \buf_fifo_reg_n_0_[2][0] ;
  wire \buf_fifo_reg_n_0_[2][1] ;
  wire \buf_fifo_reg_n_0_[2][2] ;
  wire \buf_fifo_reg_n_0_[2][3] ;
  wire \buf_fifo_reg_n_0_[2][4] ;
  wire \buf_fifo_reg_n_0_[3][0] ;
  wire \buf_fifo_reg_n_0_[3][1] ;
  wire \buf_fifo_reg_n_0_[3][2] ;
  wire \buf_fifo_reg_n_0_[3][3] ;
  wire \buf_fifo_reg_n_0_[3][4] ;
  wire calDone_gated_reg;
  wire \cas_dbuf_fifo[0][0]_i_1__0_n_0 ;
  wire \cas_dbuf_fifo[0][1]_i_1__0_n_0 ;
  wire \cas_dbuf_fifo[0][2]_i_1__0_n_0 ;
  wire \cas_dbuf_fifo[0][3]_i_1__0_n_0 ;
  wire \cas_dbuf_fifo[0][4]_i_1__0_n_0 ;
  wire \cas_dbuf_fifo_reg_n_0_[0][0] ;
  wire \cas_dbuf_fifo_reg_n_0_[0][1] ;
  wire \cas_dbuf_fifo_reg_n_0_[0][2] ;
  wire \cas_dbuf_fifo_reg_n_0_[0][3] ;
  wire \cas_dbuf_fifo_reg_n_0_[0][4] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][0] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][1] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][2] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][3] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][4] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][0] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][1] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][2] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][3] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][4] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][0] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][1] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][2] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][3] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][4] ;
  wire cas_fifo_empty_i_1__1_n_0;
  wire cas_fifo_empty_reg_n_0;
  wire cas_fifo_full_i_1__1_n_0;
  wire cas_fifo_full_reg_n_0;
  wire \cas_fifo_rptr[0]_i_1__1_n_0 ;
  wire \cas_fifo_rptr[1]_i_1__1_n_0 ;
  wire \cas_fifo_rptr[1]_i_2__1_n_0 ;
  wire [0:0]\cas_fifo_rptr_reg[0]_0 ;
  wire \cas_fifo_rptr_reg_n_0_[0] ;
  wire \cas_fifo_rptr_reg_n_0_[1] ;
  wire \cas_fifo_valid[0]_i_1__1_n_0 ;
  wire \cas_fifo_valid[0]_i_2__1_n_0 ;
  wire \cas_fifo_valid[1]_i_1__1_n_0 ;
  wire \cas_fifo_valid[1]_i_2__1_n_0 ;
  wire \cas_fifo_valid[2]_i_1__1_n_0 ;
  wire \cas_fifo_valid[2]_i_2__1_n_0 ;
  wire \cas_fifo_valid[3]_i_1__1_n_0 ;
  wire \cas_fifo_valid[3]_i_2__1_n_0 ;
  wire \cas_fifo_valid_reg_n_0_[0] ;
  wire \cas_fifo_valid_reg_n_0_[1] ;
  wire \cas_fifo_valid_reg_n_0_[2] ;
  wire \cas_fifo_valid_reg_n_0_[3] ;
  wire \cas_fifo_wptr[0]_i_1__1_n_0 ;
  wire \cas_fifo_wptr[1]_i_1__1_n_0 ;
  wire \cas_fifo_wptr_reg_n_0_[0] ;
  wire \cas_fifo_wptr_reg_n_0_[1] ;
  wire \cas_pend_fifo[0][47]_i_1__0_n_0 ;
  wire \cas_pend_fifo[1][47]_i_1__0_n_0 ;
  wire \cas_pend_fifo[2][47]_i_1__0_n_0 ;
  wire \cas_pend_fifo[3][47]_i_1__0_n_0 ;
  wire \cas_pend_fifo_reg_n_0_[0][0] ;
  wire \cas_pend_fifo_reg_n_0_[0][11] ;
  wire \cas_pend_fifo_reg_n_0_[0][12] ;
  wire \cas_pend_fifo_reg_n_0_[0][13] ;
  wire \cas_pend_fifo_reg_n_0_[0][14] ;
  wire \cas_pend_fifo_reg_n_0_[0][15] ;
  wire \cas_pend_fifo_reg_n_0_[0][16] ;
  wire \cas_pend_fifo_reg_n_0_[0][17] ;
  wire \cas_pend_fifo_reg_n_0_[0][1] ;
  wire \cas_pend_fifo_reg_n_0_[0][24] ;
  wire \cas_pend_fifo_reg_n_0_[0][25] ;
  wire \cas_pend_fifo_reg_n_0_[0][26] ;
  wire \cas_pend_fifo_reg_n_0_[0][27] ;
  wire \cas_pend_fifo_reg_n_0_[0][28] ;
  wire \cas_pend_fifo_reg_n_0_[0][29] ;
  wire \cas_pend_fifo_reg_n_0_[0][2] ;
  wire \cas_pend_fifo_reg_n_0_[0][30] ;
  wire \cas_pend_fifo_reg_n_0_[0][31] ;
  wire \cas_pend_fifo_reg_n_0_[0][32] ;
  wire \cas_pend_fifo_reg_n_0_[0][33] ;
  wire \cas_pend_fifo_reg_n_0_[0][34] ;
  wire \cas_pend_fifo_reg_n_0_[0][35] ;
  wire \cas_pend_fifo_reg_n_0_[0][36] ;
  wire \cas_pend_fifo_reg_n_0_[0][37] ;
  wire \cas_pend_fifo_reg_n_0_[0][38] ;
  wire \cas_pend_fifo_reg_n_0_[0][39] ;
  wire \cas_pend_fifo_reg_n_0_[0][40] ;
  wire \cas_pend_fifo_reg_n_0_[0][44] ;
  wire \cas_pend_fifo_reg_n_0_[0][45] ;
  wire \cas_pend_fifo_reg_n_0_[0][46] ;
  wire \cas_pend_fifo_reg_n_0_[0][47] ;
  wire \cas_pend_fifo_reg_n_0_[1][0] ;
  wire \cas_pend_fifo_reg_n_0_[1][11] ;
  wire \cas_pend_fifo_reg_n_0_[1][12] ;
  wire \cas_pend_fifo_reg_n_0_[1][13] ;
  wire \cas_pend_fifo_reg_n_0_[1][14] ;
  wire \cas_pend_fifo_reg_n_0_[1][15] ;
  wire \cas_pend_fifo_reg_n_0_[1][16] ;
  wire \cas_pend_fifo_reg_n_0_[1][17] ;
  wire \cas_pend_fifo_reg_n_0_[1][1] ;
  wire \cas_pend_fifo_reg_n_0_[1][24] ;
  wire \cas_pend_fifo_reg_n_0_[1][25] ;
  wire \cas_pend_fifo_reg_n_0_[1][26] ;
  wire \cas_pend_fifo_reg_n_0_[1][27] ;
  wire \cas_pend_fifo_reg_n_0_[1][28] ;
  wire \cas_pend_fifo_reg_n_0_[1][29] ;
  wire \cas_pend_fifo_reg_n_0_[1][2] ;
  wire \cas_pend_fifo_reg_n_0_[1][30] ;
  wire \cas_pend_fifo_reg_n_0_[1][31] ;
  wire \cas_pend_fifo_reg_n_0_[1][32] ;
  wire \cas_pend_fifo_reg_n_0_[1][33] ;
  wire \cas_pend_fifo_reg_n_0_[1][34] ;
  wire \cas_pend_fifo_reg_n_0_[1][35] ;
  wire \cas_pend_fifo_reg_n_0_[1][36] ;
  wire \cas_pend_fifo_reg_n_0_[1][37] ;
  wire \cas_pend_fifo_reg_n_0_[1][38] ;
  wire \cas_pend_fifo_reg_n_0_[1][39] ;
  wire \cas_pend_fifo_reg_n_0_[1][40] ;
  wire \cas_pend_fifo_reg_n_0_[1][44] ;
  wire \cas_pend_fifo_reg_n_0_[1][45] ;
  wire \cas_pend_fifo_reg_n_0_[1][46] ;
  wire \cas_pend_fifo_reg_n_0_[1][47] ;
  wire \cas_pend_fifo_reg_n_0_[2][0] ;
  wire \cas_pend_fifo_reg_n_0_[2][11] ;
  wire \cas_pend_fifo_reg_n_0_[2][12] ;
  wire \cas_pend_fifo_reg_n_0_[2][13] ;
  wire \cas_pend_fifo_reg_n_0_[2][14] ;
  wire \cas_pend_fifo_reg_n_0_[2][15] ;
  wire \cas_pend_fifo_reg_n_0_[2][16] ;
  wire \cas_pend_fifo_reg_n_0_[2][17] ;
  wire \cas_pend_fifo_reg_n_0_[2][1] ;
  wire \cas_pend_fifo_reg_n_0_[2][24] ;
  wire \cas_pend_fifo_reg_n_0_[2][25] ;
  wire \cas_pend_fifo_reg_n_0_[2][26] ;
  wire \cas_pend_fifo_reg_n_0_[2][27] ;
  wire \cas_pend_fifo_reg_n_0_[2][28] ;
  wire \cas_pend_fifo_reg_n_0_[2][29] ;
  wire \cas_pend_fifo_reg_n_0_[2][2] ;
  wire \cas_pend_fifo_reg_n_0_[2][30] ;
  wire \cas_pend_fifo_reg_n_0_[2][31] ;
  wire \cas_pend_fifo_reg_n_0_[2][32] ;
  wire \cas_pend_fifo_reg_n_0_[2][33] ;
  wire \cas_pend_fifo_reg_n_0_[2][34] ;
  wire \cas_pend_fifo_reg_n_0_[2][35] ;
  wire \cas_pend_fifo_reg_n_0_[2][36] ;
  wire \cas_pend_fifo_reg_n_0_[2][37] ;
  wire \cas_pend_fifo_reg_n_0_[2][38] ;
  wire \cas_pend_fifo_reg_n_0_[2][39] ;
  wire \cas_pend_fifo_reg_n_0_[2][40] ;
  wire \cas_pend_fifo_reg_n_0_[2][44] ;
  wire \cas_pend_fifo_reg_n_0_[2][45] ;
  wire \cas_pend_fifo_reg_n_0_[2][46] ;
  wire \cas_pend_fifo_reg_n_0_[2][47] ;
  wire \cas_pend_fifo_reg_n_0_[3][0] ;
  wire \cas_pend_fifo_reg_n_0_[3][11] ;
  wire \cas_pend_fifo_reg_n_0_[3][12] ;
  wire \cas_pend_fifo_reg_n_0_[3][13] ;
  wire \cas_pend_fifo_reg_n_0_[3][14] ;
  wire \cas_pend_fifo_reg_n_0_[3][15] ;
  wire \cas_pend_fifo_reg_n_0_[3][16] ;
  wire \cas_pend_fifo_reg_n_0_[3][17] ;
  wire \cas_pend_fifo_reg_n_0_[3][1] ;
  wire \cas_pend_fifo_reg_n_0_[3][24] ;
  wire \cas_pend_fifo_reg_n_0_[3][25] ;
  wire \cas_pend_fifo_reg_n_0_[3][26] ;
  wire \cas_pend_fifo_reg_n_0_[3][27] ;
  wire \cas_pend_fifo_reg_n_0_[3][28] ;
  wire \cas_pend_fifo_reg_n_0_[3][29] ;
  wire \cas_pend_fifo_reg_n_0_[3][2] ;
  wire \cas_pend_fifo_reg_n_0_[3][30] ;
  wire \cas_pend_fifo_reg_n_0_[3][31] ;
  wire \cas_pend_fifo_reg_n_0_[3][32] ;
  wire \cas_pend_fifo_reg_n_0_[3][33] ;
  wire \cas_pend_fifo_reg_n_0_[3][34] ;
  wire \cas_pend_fifo_reg_n_0_[3][35] ;
  wire \cas_pend_fifo_reg_n_0_[3][36] ;
  wire \cas_pend_fifo_reg_n_0_[3][37] ;
  wire \cas_pend_fifo_reg_n_0_[3][38] ;
  wire \cas_pend_fifo_reg_n_0_[3][39] ;
  wire \cas_pend_fifo_reg_n_0_[3][40] ;
  wire \cas_pend_fifo_reg_n_0_[3][44] ;
  wire \cas_pend_fifo_reg_n_0_[3][45] ;
  wire \cas_pend_fifo_reg_n_0_[3][46] ;
  wire \cas_pend_fifo_reg_n_0_[3][47] ;
  wire clrReq17_out;
  wire [2:0]cmd;
  wire [0:0]cmdAP;
  wire cmdAP_i_1__1_n_0;
  wire cmdAP_i_2__1_n_0;
  wire \cmdBankP[1]_i_1__2_n_0 ;
  wire \cmdBankP[1]_i_2__0_n_0 ;
  wire \cmdBankP[1]_i_3_n_0 ;
  wire \cmdBankP[1]_i_4__0_n_0 ;
  wire \cmdBankP[1]_i_5__0_n_0 ;
  wire \cmdBankP[1]_i_6__0_n_0 ;
  wire [1:0]\cmdBankP_reg[1]_0 ;
  wire [4:0]cmdBuf;
  wire \cmdBuf[0]_i_1__1_n_0 ;
  wire \cmdBuf[1]_i_1__1_n_0 ;
  wire \cmdBuf[2]_i_1__1_n_0 ;
  wire \cmdBuf[3]_i_1__1_n_0 ;
  wire \cmdBuf[4]_i_1__1_n_0 ;
  wire \cmdCol[3]_i_1__1_n_0 ;
  wire \cmdCol[3]_i_2__1_n_0 ;
  wire \cmdCol[4]_i_1__1_n_0 ;
  wire \cmdCol[4]_i_2__1_n_0 ;
  wire \cmdCol[5]_i_1__1_n_0 ;
  wire \cmdCol[5]_i_2__1_n_0 ;
  wire \cmdCol[6]_i_1__1_n_0 ;
  wire \cmdCol[6]_i_2__1_n_0 ;
  wire \cmdCol[7]_i_1__1_n_0 ;
  wire \cmdCol[7]_i_2__1_n_0 ;
  wire \cmdCol[8]_i_1__1_n_0 ;
  wire \cmdCol[8]_i_2__1_n_0 ;
  wire \cmdCol[9]_i_1__1_n_0 ;
  wire \cmdCol[9]_i_2__1_n_0 ;
  wire [6:0]\cmdCol_reg[9]_0 ;
  wire [0:0]cmdGroupP;
  wire cmdRmw_i_1__1_n_0;
  wire cmdRmw_reg_0;
  wire \cmd_bank_cas[0]_i_1__1_n_0 ;
  wire \cmd_bank_cas[0]_i_2__1_n_0 ;
  wire \cmd_bank_cas[1]_i_1__1_n_0 ;
  wire \cmd_bank_cas[1]_i_2__1_n_0 ;
  wire [1:0]\cmd_bank_cas_reg[1]_0 ;
  wire [0:0]cmd_group_cas;
  wire \cmd_group_cas[0]_i_1__1_n_0 ;
  wire \cmd_group_cas[0]_i_2__1_n_0 ;
  wire \cmd_row_cas[0]_i_1__1_n_0 ;
  wire \cmd_row_cas[0]_i_2__1_n_0 ;
  wire \cmd_row_cas[10]_i_1__1_n_0 ;
  wire \cmd_row_cas[10]_i_2__1_n_0 ;
  wire \cmd_row_cas[11]_i_1__1_n_0 ;
  wire \cmd_row_cas[11]_i_2__1_n_0 ;
  wire \cmd_row_cas[12]_i_1__1_n_0 ;
  wire \cmd_row_cas[12]_i_2__1_n_0 ;
  wire \cmd_row_cas[13]_i_1__1_n_0 ;
  wire \cmd_row_cas[13]_i_2__1_n_0 ;
  wire \cmd_row_cas[14]_i_1__1_n_0 ;
  wire \cmd_row_cas[14]_i_2__1_n_0 ;
  wire \cmd_row_cas[15]_i_1__1_n_0 ;
  wire \cmd_row_cas[15]_i_2__1_n_0 ;
  wire \cmd_row_cas[16]_i_1__1_n_0 ;
  wire \cmd_row_cas[16]_i_2__1_n_0 ;
  wire \cmd_row_cas[1]_i_1__1_n_0 ;
  wire \cmd_row_cas[1]_i_2__1_n_0 ;
  wire \cmd_row_cas[2]_i_1__1_n_0 ;
  wire \cmd_row_cas[2]_i_2__1_n_0 ;
  wire \cmd_row_cas[3]_i_1__1_n_0 ;
  wire \cmd_row_cas[3]_i_2__1_n_0 ;
  wire \cmd_row_cas[4]_i_1__1_n_0 ;
  wire \cmd_row_cas[4]_i_2__1_n_0 ;
  wire \cmd_row_cas[5]_i_1__1_n_0 ;
  wire \cmd_row_cas[5]_i_2__1_n_0 ;
  wire \cmd_row_cas[6]_i_1__1_n_0 ;
  wire \cmd_row_cas[6]_i_2__1_n_0 ;
  wire \cmd_row_cas[7]_i_1__1_n_0 ;
  wire \cmd_row_cas[7]_i_2__1_n_0 ;
  wire \cmd_row_cas[8]_i_1__1_n_0 ;
  wire \cmd_row_cas[8]_i_2__1_n_0 ;
  wire \cmd_row_cas[9]_i_1__1_n_0 ;
  wire \cmd_row_cas[9]_i_2__1_n_0 ;
  wire \cmd_row_cas_reg_n_0_[0] ;
  wire \cmd_row_cas_reg_n_0_[10] ;
  wire \cmd_row_cas_reg_n_0_[11] ;
  wire \cmd_row_cas_reg_n_0_[12] ;
  wire \cmd_row_cas_reg_n_0_[13] ;
  wire \cmd_row_cas_reg_n_0_[14] ;
  wire \cmd_row_cas_reg_n_0_[15] ;
  wire \cmd_row_cas_reg_n_0_[16] ;
  wire \cmd_row_cas_reg_n_0_[1] ;
  wire \cmd_row_cas_reg_n_0_[2] ;
  wire \cmd_row_cas_reg_n_0_[3] ;
  wire \cmd_row_cas_reg_n_0_[4] ;
  wire \cmd_row_cas_reg_n_0_[5] ;
  wire \cmd_row_cas_reg_n_0_[6] ;
  wire \cmd_row_cas_reg_n_0_[7] ;
  wire \cmd_row_cas_reg_n_0_[8] ;
  wire \cmd_row_cas_reg_n_0_[9] ;
  wire [6:0]col;
  wire [0:0]grAccept_ns;
  wire [2:0]grSt;
  wire [2:0]gr_cas_state;
  wire [2:0]gr_cas_state_nxt;
  wire [0:0]group;
  wire i__carry_i_10__1_n_0;
  wire i__carry_i_11__1_n_0;
  wire i__carry_i_12__1_n_0;
  wire i__carry_i_13__1_n_0;
  wire i__carry_i_14__1_n_0;
  wire i__carry_i_15__1_n_0;
  wire i__carry_i_16__1_n_0;
  wire i__carry_i_17__1_n_0;
  wire i__carry_i_18__1_n_0;
  wire i__carry_i_19__1_n_0;
  wire i__carry_i_1__1_n_0;
  wire i__carry_i_20__1_n_0;
  wire i__carry_i_21__1_n_0;
  wire i__carry_i_22__1_n_0;
  wire i__carry_i_23__1_n_0;
  wire i__carry_i_2__1_n_0;
  wire i__carry_i_3__1_n_0;
  wire i__carry_i_4__1_n_0;
  wire i__carry_i_5__1_n_0;
  wire i__carry_i_6__1_n_0;
  wire i__carry_i_7__1_n_0;
  wire i__carry_i_8__1_n_0;
  wire i__carry_i_9__1_n_0;
  wire \issue_cas3_inferred__0/i__carry_n_2 ;
  wire \issue_cas3_inferred__0/i__carry_n_3 ;
  wire \issue_cas3_inferred__0/i__carry_n_4 ;
  wire \issue_cas3_inferred__0/i__carry_n_5 ;
  wire \issue_cas3_inferred__0/i__carry_n_6 ;
  wire \issue_cas3_inferred__0/i__carry_n_7 ;
  wire \pageInfo[0][0][0][0]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][0]_i_2__1_n_0 ;
  wire \pageInfo[0][0][0][0]_i_3__1_n_0 ;
  wire \pageInfo[0][0][0][10]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][11]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][12]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][13]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][14]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][15]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][16]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][17]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][18]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][18]_i_2__1_n_0 ;
  wire \pageInfo[0][0][0][1]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][2]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][3]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][4]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][5]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][6]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][7]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][8]_i_1__1_n_0 ;
  wire \pageInfo[0][0][0][9]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][0]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][0]_i_2__1_n_0 ;
  wire \pageInfo[0][0][1][0]_i_3__1_n_0 ;
  wire \pageInfo[0][0][1][10]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][11]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][12]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][13]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][14]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][15]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][16]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][17]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][18]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][18]_i_2__1_n_0 ;
  wire \pageInfo[0][0][1][1]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][2]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][3]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][4]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][5]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][6]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][7]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][8]_i_1__1_n_0 ;
  wire \pageInfo[0][0][1][9]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][0]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][0]_i_2__0_n_0 ;
  wire \pageInfo[0][0][2][0]_i_3__0_n_0 ;
  wire \pageInfo[0][0][2][10]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][11]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][12]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][13]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][14]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][15]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][16]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][17]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][18]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][18]_i_2__1_n_0 ;
  wire \pageInfo[0][0][2][1]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][2]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][3]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][4]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][5]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][6]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][7]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][8]_i_1__1_n_0 ;
  wire \pageInfo[0][0][2][9]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][0]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][0]_i_2__1_n_0 ;
  wire \pageInfo[0][0][3][10]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][11]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][12]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][13]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][14]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][15]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][16]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][17]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][18]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][18]_i_2__1_n_0 ;
  wire \pageInfo[0][0][3][18]_i_3__1_n_0 ;
  wire \pageInfo[0][0][3][1]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][2]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][3]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][4]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][5]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][6]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][7]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][8]_i_1__1_n_0 ;
  wire \pageInfo[0][0][3][9]_i_1__1_n_0 ;
  wire \pageInfo_reg_n_0_[0][0][0][0] ;
  wire \pageInfo_reg_n_0_[0][0][0][10] ;
  wire \pageInfo_reg_n_0_[0][0][0][11] ;
  wire \pageInfo_reg_n_0_[0][0][0][12] ;
  wire \pageInfo_reg_n_0_[0][0][0][13] ;
  wire \pageInfo_reg_n_0_[0][0][0][14] ;
  wire \pageInfo_reg_n_0_[0][0][0][15] ;
  wire \pageInfo_reg_n_0_[0][0][0][16] ;
  wire \pageInfo_reg_n_0_[0][0][0][17] ;
  wire \pageInfo_reg_n_0_[0][0][0][18] ;
  wire \pageInfo_reg_n_0_[0][0][0][1] ;
  wire \pageInfo_reg_n_0_[0][0][0][2] ;
  wire \pageInfo_reg_n_0_[0][0][0][3] ;
  wire \pageInfo_reg_n_0_[0][0][0][4] ;
  wire \pageInfo_reg_n_0_[0][0][0][5] ;
  wire \pageInfo_reg_n_0_[0][0][0][6] ;
  wire \pageInfo_reg_n_0_[0][0][0][7] ;
  wire \pageInfo_reg_n_0_[0][0][0][8] ;
  wire \pageInfo_reg_n_0_[0][0][0][9] ;
  wire \pageInfo_reg_n_0_[0][0][1][0] ;
  wire \pageInfo_reg_n_0_[0][0][1][10] ;
  wire \pageInfo_reg_n_0_[0][0][1][11] ;
  wire \pageInfo_reg_n_0_[0][0][1][12] ;
  wire \pageInfo_reg_n_0_[0][0][1][13] ;
  wire \pageInfo_reg_n_0_[0][0][1][14] ;
  wire \pageInfo_reg_n_0_[0][0][1][15] ;
  wire \pageInfo_reg_n_0_[0][0][1][16] ;
  wire \pageInfo_reg_n_0_[0][0][1][17] ;
  wire \pageInfo_reg_n_0_[0][0][1][18] ;
  wire \pageInfo_reg_n_0_[0][0][1][1] ;
  wire \pageInfo_reg_n_0_[0][0][1][2] ;
  wire \pageInfo_reg_n_0_[0][0][1][3] ;
  wire \pageInfo_reg_n_0_[0][0][1][4] ;
  wire \pageInfo_reg_n_0_[0][0][1][5] ;
  wire \pageInfo_reg_n_0_[0][0][1][6] ;
  wire \pageInfo_reg_n_0_[0][0][1][7] ;
  wire \pageInfo_reg_n_0_[0][0][1][8] ;
  wire \pageInfo_reg_n_0_[0][0][1][9] ;
  wire \pageInfo_reg_n_0_[0][0][2][0] ;
  wire \pageInfo_reg_n_0_[0][0][2][10] ;
  wire \pageInfo_reg_n_0_[0][0][2][11] ;
  wire \pageInfo_reg_n_0_[0][0][2][12] ;
  wire \pageInfo_reg_n_0_[0][0][2][13] ;
  wire \pageInfo_reg_n_0_[0][0][2][14] ;
  wire \pageInfo_reg_n_0_[0][0][2][15] ;
  wire \pageInfo_reg_n_0_[0][0][2][16] ;
  wire \pageInfo_reg_n_0_[0][0][2][17] ;
  wire \pageInfo_reg_n_0_[0][0][2][18] ;
  wire \pageInfo_reg_n_0_[0][0][2][1] ;
  wire \pageInfo_reg_n_0_[0][0][2][2] ;
  wire \pageInfo_reg_n_0_[0][0][2][3] ;
  wire \pageInfo_reg_n_0_[0][0][2][4] ;
  wire \pageInfo_reg_n_0_[0][0][2][5] ;
  wire \pageInfo_reg_n_0_[0][0][2][6] ;
  wire \pageInfo_reg_n_0_[0][0][2][7] ;
  wire \pageInfo_reg_n_0_[0][0][2][8] ;
  wire \pageInfo_reg_n_0_[0][0][2][9] ;
  wire \pageInfo_reg_n_0_[0][0][3][0] ;
  wire \pageInfo_reg_n_0_[0][0][3][10] ;
  wire \pageInfo_reg_n_0_[0][0][3][11] ;
  wire \pageInfo_reg_n_0_[0][0][3][12] ;
  wire \pageInfo_reg_n_0_[0][0][3][13] ;
  wire \pageInfo_reg_n_0_[0][0][3][14] ;
  wire \pageInfo_reg_n_0_[0][0][3][15] ;
  wire \pageInfo_reg_n_0_[0][0][3][16] ;
  wire \pageInfo_reg_n_0_[0][0][3][17] ;
  wire \pageInfo_reg_n_0_[0][0][3][18] ;
  wire \pageInfo_reg_n_0_[0][0][3][1] ;
  wire \pageInfo_reg_n_0_[0][0][3][2] ;
  wire \pageInfo_reg_n_0_[0][0][3][3] ;
  wire \pageInfo_reg_n_0_[0][0][3][4] ;
  wire \pageInfo_reg_n_0_[0][0][3][5] ;
  wire \pageInfo_reg_n_0_[0][0][3][6] ;
  wire \pageInfo_reg_n_0_[0][0][3][7] ;
  wire \pageInfo_reg_n_0_[0][0][3][8] ;
  wire \pageInfo_reg_n_0_[0][0][3][9] ;
  wire preReqR_i_1__0_n_0;
  wire preReqR_i_2__0_n_0;
  wire preReqR_reg_0;
  wire [0:0]preReqR_reg_1;
  wire rdReqR_i_1__1_n_0;
  wire rdReqR_i_2__1_n_0;
  wire rdReqR_reg_0;
  wire refOK_i_1__1_n_0;
  wire [0:0]refOK_reg_0;
  wire refReq;
  wire ref_req_dly4;
  wire [16:0]row_mc_phy;
  (* RTL_KEEP = "true" *) wire rst_r1;
  wire rst_r1_reg_0;
  wire [1:1]sel0__34;
  wire [1:1]sel0__38;
  wire [1:1]sel0__42;
  wire [1:1]sel0__46;
  wire tranSentC;
  wire \tras_cntr_rb[0][0][0][0]_i_1__1_n_0 ;
  wire \tras_cntr_rb[0][0][0][1]_i_1__1_n_0 ;
  wire \tras_cntr_rb[0][0][0][2]_i_1__1_n_0 ;
  wire \tras_cntr_rb[0][0][1][0]_i_1__1_n_0 ;
  wire \tras_cntr_rb[0][0][1][1]_i_1__1_n_0 ;
  wire \tras_cntr_rb[0][0][1][2]_i_1__1_n_0 ;
  wire \tras_cntr_rb[0][0][2][0]_i_1__1_n_0 ;
  wire \tras_cntr_rb[0][0][2][1]_i_1__1_n_0 ;
  wire \tras_cntr_rb[0][0][2][2]_i_1__1_n_0 ;
  wire \tras_cntr_rb[0][0][3][0]_i_1__1_n_0 ;
  wire \tras_cntr_rb[0][0][3][1]_i_1__1_n_0 ;
  wire \tras_cntr_rb[0][0][3][2]_i_1__1_n_0 ;
  wire \tras_cntr_rb_reg_n_0_[0][0][0][0] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][0][1] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][0][2] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][1][0] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][1][1] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][1][2] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][2][0] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][2][1] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][2][2] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][3][0] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][3][1] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][3][2] ;
  wire \trcd_cntr[0][0][0][0]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][0][1]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][0][2]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][0][2]_i_2__1_n_0 ;
  wire \trcd_cntr[0][0][0][3]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][1][0]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][1][1]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][1][2]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][1][2]_i_2__1_n_0 ;
  wire \trcd_cntr[0][0][1][3]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][2][0]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][2][1]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][2][2]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][2][2]_i_2__1_n_0 ;
  wire \trcd_cntr[0][0][2][3]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][3][0]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][3][1]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][3][2]_i_1__1_n_0 ;
  wire \trcd_cntr[0][0][3][2]_i_2__1_n_0 ;
  wire \trcd_cntr[0][0][3][3]_i_1__1_n_0 ;
  wire \trcd_cntr_is_zero[0][0][0]_i_1__1_n_0 ;
  wire \trcd_cntr_is_zero[0][0][0]_i_2__1_n_0 ;
  wire \trcd_cntr_is_zero[0][0][1]_i_1__1_n_0 ;
  wire \trcd_cntr_is_zero[0][0][1]_i_2__1_n_0 ;
  wire \trcd_cntr_is_zero[0][0][2]_i_1__1_n_0 ;
  wire \trcd_cntr_is_zero[0][0][2]_i_2__1_n_0 ;
  wire \trcd_cntr_is_zero[0][0][3]_i_1__1_n_0 ;
  wire \trcd_cntr_is_zero[0][0][3]_i_2__1_n_0 ;
  wire \trcd_cntr_is_zero_reg_n_0_[0][0][0] ;
  wire \trcd_cntr_is_zero_reg_n_0_[0][0][1] ;
  wire \trcd_cntr_is_zero_reg_n_0_[0][0][2] ;
  wire \trcd_cntr_is_zero_reg_n_0_[0][0][3] ;
  wire \trcd_cntr_reg_n_0_[0][0][0][0] ;
  wire \trcd_cntr_reg_n_0_[0][0][0][1] ;
  wire \trcd_cntr_reg_n_0_[0][0][0][2] ;
  wire \trcd_cntr_reg_n_0_[0][0][0][3] ;
  wire \trcd_cntr_reg_n_0_[0][0][1][0] ;
  wire \trcd_cntr_reg_n_0_[0][0][1][1] ;
  wire \trcd_cntr_reg_n_0_[0][0][1][2] ;
  wire \trcd_cntr_reg_n_0_[0][0][1][3] ;
  wire \trcd_cntr_reg_n_0_[0][0][2][0] ;
  wire \trcd_cntr_reg_n_0_[0][0][2][1] ;
  wire \trcd_cntr_reg_n_0_[0][0][2][2] ;
  wire \trcd_cntr_reg_n_0_[0][0][2][3] ;
  wire \trcd_cntr_reg_n_0_[0][0][3][0] ;
  wire \trcd_cntr_reg_n_0_[0][0][3][1] ;
  wire \trcd_cntr_reg_n_0_[0][0][3][2] ;
  wire \trcd_cntr_reg_n_0_[0][0][3][3] ;
  wire \trp_cntr[0]_i_1__1_n_0 ;
  wire \trp_cntr[0]_i_2__1_n_0 ;
  wire \trp_cntr[1]_i_1__1_n_0 ;
  wire \trp_cntr[1]_i_2__1_n_0 ;
  wire \trp_cntr[1]_i_3__1_n_0 ;
  wire \trp_cntr[1]_i_4_n_0 ;
  wire \trp_cntr[2]_i_1__1_n_0 ;
  wire \trp_cntr[2]_i_2__1_n_0 ;
  wire \trp_cntr[2]_i_3__0_n_0 ;
  wire \trp_cntr[3]_i_1__1_n_0 ;
  wire \trp_cntr[3]_i_2__1_n_0 ;
  wire \trp_cntr[3]_i_3__1_n_0 ;
  wire \trp_cntr[4]_i_1__1_n_0 ;
  wire \trp_cntr[4]_i_2__1_n_0 ;
  wire \trp_cntr[4]_i_3__1_n_0 ;
  wire \trp_cntr[4]_i_4_n_0 ;
  wire trp_cntr_is_zero_i_1__1_n_0;
  wire trp_cntr_is_zero_reg_n_0;
  wire \trp_cntr_reg_n_0_[0] ;
  wire \trp_cntr_reg_n_0_[1] ;
  wire \trp_cntr_reg_n_0_[2] ;
  wire \trp_cntr_reg_n_0_[3] ;
  wire \trp_cntr_reg_n_0_[4] ;
  wire \txn_fifo[0][0]_i_1__1_n_0 ;
  wire \txn_fifo[0][11]_i_1__1_n_0 ;
  wire \txn_fifo[0][12]_i_1__1_n_0 ;
  wire \txn_fifo[0][13]_i_1__1_n_0 ;
  wire \txn_fifo[0][14]_i_1__1_n_0 ;
  wire \txn_fifo[0][15]_i_1__1_n_0 ;
  wire \txn_fifo[0][16]_i_1__1_n_0 ;
  wire \txn_fifo[0][17]_i_1__1_n_0 ;
  wire \txn_fifo[0][1]_i_1__1_n_0 ;
  wire \txn_fifo[0][24]_i_1__1_n_0 ;
  wire \txn_fifo[0][25]_i_1__1_n_0 ;
  wire \txn_fifo[0][26]_i_1__1_n_0 ;
  wire \txn_fifo[0][27]_i_1__1_n_0 ;
  wire \txn_fifo[0][28]_i_1__1_n_0 ;
  wire \txn_fifo[0][29]_i_1__1_n_0 ;
  wire \txn_fifo[0][2]_i_1__1_n_0 ;
  wire \txn_fifo[0][30]_i_1__1_n_0 ;
  wire \txn_fifo[0][31]_i_1__1_n_0 ;
  wire \txn_fifo[0][32]_i_1__1_n_0 ;
  wire \txn_fifo[0][33]_i_1__1_n_0 ;
  wire \txn_fifo[0][34]_i_1__1_n_0 ;
  wire \txn_fifo[0][35]_i_1__1_n_0 ;
  wire \txn_fifo[0][36]_i_1__1_n_0 ;
  wire \txn_fifo[0][37]_i_1__1_n_0 ;
  wire \txn_fifo[0][38]_i_1__1_n_0 ;
  wire \txn_fifo[0][39]_i_1__1_n_0 ;
  wire \txn_fifo[0][40]_i_1__1_n_0 ;
  wire \txn_fifo[0][44]_i_1__1_n_0 ;
  wire \txn_fifo[0][45]_i_1__1_n_0 ;
  wire \txn_fifo[0][46]_i_1__1_n_0 ;
  wire \txn_fifo[0][47]_i_1__1_n_0 ;
  wire \txn_fifo[0][47]_i_2__0_n_0 ;
  wire \txn_fifo[1][0]_i_1__1_n_0 ;
  wire \txn_fifo[1][11]_i_1__1_n_0 ;
  wire \txn_fifo[1][12]_i_1__1_n_0 ;
  wire \txn_fifo[1][13]_i_1__1_n_0 ;
  wire \txn_fifo[1][14]_i_1__1_n_0 ;
  wire \txn_fifo[1][15]_i_1__1_n_0 ;
  wire \txn_fifo[1][16]_i_1__1_n_0 ;
  wire \txn_fifo[1][17]_i_1__1_n_0 ;
  wire \txn_fifo[1][1]_i_1__1_n_0 ;
  wire \txn_fifo[1][24]_i_1__1_n_0 ;
  wire \txn_fifo[1][25]_i_1__1_n_0 ;
  wire \txn_fifo[1][26]_i_1__1_n_0 ;
  wire \txn_fifo[1][27]_i_1__1_n_0 ;
  wire \txn_fifo[1][28]_i_1__1_n_0 ;
  wire \txn_fifo[1][29]_i_1__1_n_0 ;
  wire \txn_fifo[1][2]_i_1__1_n_0 ;
  wire \txn_fifo[1][30]_i_1__1_n_0 ;
  wire \txn_fifo[1][31]_i_1__1_n_0 ;
  wire \txn_fifo[1][32]_i_1__1_n_0 ;
  wire \txn_fifo[1][33]_i_1__1_n_0 ;
  wire \txn_fifo[1][34]_i_1__1_n_0 ;
  wire \txn_fifo[1][35]_i_1__1_n_0 ;
  wire \txn_fifo[1][36]_i_1__1_n_0 ;
  wire \txn_fifo[1][37]_i_1__1_n_0 ;
  wire \txn_fifo[1][38]_i_1__1_n_0 ;
  wire \txn_fifo[1][39]_i_1__1_n_0 ;
  wire \txn_fifo[1][40]_i_1__1_n_0 ;
  wire \txn_fifo[1][44]_i_1__1_n_0 ;
  wire \txn_fifo[1][45]_i_1__1_n_0 ;
  wire \txn_fifo[1][46]_i_1__1_n_0 ;
  wire \txn_fifo[1][47]_i_1__1_n_0 ;
  wire \txn_fifo[1][47]_i_2__0_n_0 ;
  wire \txn_fifo[2][0]_i_1__1_n_0 ;
  wire \txn_fifo[2][11]_i_1__1_n_0 ;
  wire \txn_fifo[2][12]_i_1__1_n_0 ;
  wire \txn_fifo[2][13]_i_1__1_n_0 ;
  wire \txn_fifo[2][14]_i_1__1_n_0 ;
  wire \txn_fifo[2][15]_i_1__1_n_0 ;
  wire \txn_fifo[2][16]_i_1__1_n_0 ;
  wire \txn_fifo[2][17]_i_1__1_n_0 ;
  wire \txn_fifo[2][1]_i_1__1_n_0 ;
  wire \txn_fifo[2][24]_i_1__1_n_0 ;
  wire \txn_fifo[2][25]_i_1__1_n_0 ;
  wire \txn_fifo[2][26]_i_1__1_n_0 ;
  wire \txn_fifo[2][27]_i_1__1_n_0 ;
  wire \txn_fifo[2][28]_i_1__1_n_0 ;
  wire \txn_fifo[2][29]_i_1__1_n_0 ;
  wire \txn_fifo[2][2]_i_1__1_n_0 ;
  wire \txn_fifo[2][30]_i_1__1_n_0 ;
  wire \txn_fifo[2][31]_i_1__1_n_0 ;
  wire \txn_fifo[2][32]_i_1__1_n_0 ;
  wire \txn_fifo[2][33]_i_1__1_n_0 ;
  wire \txn_fifo[2][34]_i_1__1_n_0 ;
  wire \txn_fifo[2][35]_i_1__1_n_0 ;
  wire \txn_fifo[2][36]_i_1__1_n_0 ;
  wire \txn_fifo[2][37]_i_1__1_n_0 ;
  wire \txn_fifo[2][38]_i_1__1_n_0 ;
  wire \txn_fifo[2][39]_i_1__1_n_0 ;
  wire \txn_fifo[2][40]_i_1__1_n_0 ;
  wire \txn_fifo[2][44]_i_1__1_n_0 ;
  wire \txn_fifo[2][45]_i_1__1_n_0 ;
  wire \txn_fifo[2][46]_i_1__1_n_0 ;
  wire \txn_fifo[2][47]_i_1__1_n_0 ;
  wire \txn_fifo[2][47]_i_2__1_n_0 ;
  wire \txn_fifo[3][0]_i_1__1_n_0 ;
  wire \txn_fifo[3][11]_i_1__1_n_0 ;
  wire \txn_fifo[3][12]_i_1__1_n_0 ;
  wire \txn_fifo[3][13]_i_1__1_n_0 ;
  wire \txn_fifo[3][14]_i_1__1_n_0 ;
  wire \txn_fifo[3][15]_i_1__1_n_0 ;
  wire \txn_fifo[3][16]_i_1__1_n_0 ;
  wire \txn_fifo[3][17]_i_1__1_n_0 ;
  wire \txn_fifo[3][1]_i_1__1_n_0 ;
  wire \txn_fifo[3][24]_i_1__1_n_0 ;
  wire \txn_fifo[3][25]_i_1__1_n_0 ;
  wire \txn_fifo[3][26]_i_1__1_n_0 ;
  wire \txn_fifo[3][27]_i_1__1_n_0 ;
  wire \txn_fifo[3][28]_i_1__1_n_0 ;
  wire \txn_fifo[3][29]_i_1__1_n_0 ;
  wire \txn_fifo[3][2]_i_1__1_n_0 ;
  wire \txn_fifo[3][30]_i_1__1_n_0 ;
  wire \txn_fifo[3][31]_i_1__1_n_0 ;
  wire \txn_fifo[3][32]_i_1__1_n_0 ;
  wire \txn_fifo[3][33]_i_1__1_n_0 ;
  wire \txn_fifo[3][34]_i_1__1_n_0 ;
  wire \txn_fifo[3][35]_i_1__1_n_0 ;
  wire \txn_fifo[3][36]_i_1__1_n_0 ;
  wire \txn_fifo[3][37]_i_1__1_n_0 ;
  wire \txn_fifo[3][38]_i_1__1_n_0 ;
  wire \txn_fifo[3][39]_i_1__1_n_0 ;
  wire \txn_fifo[3][40]_i_1__1_n_0 ;
  wire \txn_fifo[3][44]_i_1__1_n_0 ;
  wire \txn_fifo[3][45]_i_1__1_n_0 ;
  wire \txn_fifo[3][46]_i_1__1_n_0 ;
  wire \txn_fifo[3][47]_i_1__1_n_0 ;
  wire \txn_fifo[3][47]_i_2__0_n_0 ;
  wire txn_fifo_empty_i_1__1_n_0;
  wire txn_fifo_empty_i_2__0_n_0;
  wire txn_fifo_empty_reg_n_0;
  wire \txn_fifo_output[0]_i_1__1_n_0 ;
  wire \txn_fifo_output[0]_i_2__1_n_0 ;
  wire \txn_fifo_output[0]_i_3__1_n_0 ;
  wire \txn_fifo_output[11]_i_1__1_n_0 ;
  wire \txn_fifo_output[11]_i_2__1_n_0 ;
  wire \txn_fifo_output[11]_i_3__1_n_0 ;
  wire \txn_fifo_output[12]_i_1__1_n_0 ;
  wire \txn_fifo_output[12]_i_2__1_n_0 ;
  wire \txn_fifo_output[12]_i_3__1_n_0 ;
  wire \txn_fifo_output[13]_i_1__1_n_0 ;
  wire \txn_fifo_output[13]_i_2__1_n_0 ;
  wire \txn_fifo_output[13]_i_3__1_n_0 ;
  wire \txn_fifo_output[14]_i_1__1_n_0 ;
  wire \txn_fifo_output[14]_i_2__1_n_0 ;
  wire \txn_fifo_output[14]_i_3__1_n_0 ;
  wire \txn_fifo_output[15]_i_1__1_n_0 ;
  wire \txn_fifo_output[15]_i_2__1_n_0 ;
  wire \txn_fifo_output[15]_i_3__1_n_0 ;
  wire \txn_fifo_output[16]_i_1__1_n_0 ;
  wire \txn_fifo_output[16]_i_2__1_n_0 ;
  wire \txn_fifo_output[16]_i_3__1_n_0 ;
  wire \txn_fifo_output[17]_i_1__1_n_0 ;
  wire \txn_fifo_output[17]_i_2__1_n_0 ;
  wire \txn_fifo_output[17]_i_3__1_n_0 ;
  wire \txn_fifo_output[1]_i_1__1_n_0 ;
  wire \txn_fifo_output[1]_i_2__1_n_0 ;
  wire \txn_fifo_output[1]_i_3__1_n_0 ;
  wire \txn_fifo_output[24]_i_1__1_n_0 ;
  wire \txn_fifo_output[24]_i_2__1_n_0 ;
  wire \txn_fifo_output[24]_i_3__1_n_0 ;
  wire \txn_fifo_output[25]_i_1__1_n_0 ;
  wire \txn_fifo_output[25]_i_2__1_n_0 ;
  wire \txn_fifo_output[25]_i_3__1_n_0 ;
  wire \txn_fifo_output[26]_i_1__1_n_0 ;
  wire \txn_fifo_output[26]_i_2__1_n_0 ;
  wire \txn_fifo_output[26]_i_3__1_n_0 ;
  wire \txn_fifo_output[27]_i_1__1_n_0 ;
  wire \txn_fifo_output[27]_i_2__1_n_0 ;
  wire \txn_fifo_output[27]_i_3__1_n_0 ;
  wire \txn_fifo_output[28]_i_1__1_n_0 ;
  wire \txn_fifo_output[28]_i_2__1_n_0 ;
  wire \txn_fifo_output[28]_i_3__1_n_0 ;
  wire \txn_fifo_output[29]_i_1__1_n_0 ;
  wire \txn_fifo_output[29]_i_2__1_n_0 ;
  wire \txn_fifo_output[29]_i_3__1_n_0 ;
  wire \txn_fifo_output[2]_i_1__1_n_0 ;
  wire \txn_fifo_output[2]_i_2__1_n_0 ;
  wire \txn_fifo_output[2]_i_3__1_n_0 ;
  wire \txn_fifo_output[30]_i_1__1_n_0 ;
  wire \txn_fifo_output[30]_i_2__1_n_0 ;
  wire \txn_fifo_output[30]_i_3__1_n_0 ;
  wire \txn_fifo_output[31]_i_1__1_n_0 ;
  wire \txn_fifo_output[31]_i_2__1_n_0 ;
  wire \txn_fifo_output[31]_i_3__1_n_0 ;
  wire \txn_fifo_output[32]_i_1__1_n_0 ;
  wire \txn_fifo_output[32]_i_2__1_n_0 ;
  wire \txn_fifo_output[32]_i_3__1_n_0 ;
  wire \txn_fifo_output[33]_i_1__1_n_0 ;
  wire \txn_fifo_output[33]_i_2__1_n_0 ;
  wire \txn_fifo_output[33]_i_3__1_n_0 ;
  wire \txn_fifo_output[34]_i_1__1_n_0 ;
  wire \txn_fifo_output[34]_i_2__1_n_0 ;
  wire \txn_fifo_output[34]_i_3__1_n_0 ;
  wire \txn_fifo_output[35]_i_1__1_n_0 ;
  wire \txn_fifo_output[35]_i_2__1_n_0 ;
  wire \txn_fifo_output[35]_i_3__1_n_0 ;
  wire \txn_fifo_output[36]_i_1__1_n_0 ;
  wire \txn_fifo_output[36]_i_2__1_n_0 ;
  wire \txn_fifo_output[36]_i_3__1_n_0 ;
  wire \txn_fifo_output[37]_i_1__1_n_0 ;
  wire \txn_fifo_output[37]_i_2__1_n_0 ;
  wire \txn_fifo_output[37]_i_3__1_n_0 ;
  wire \txn_fifo_output[38]_i_1__1_n_0 ;
  wire \txn_fifo_output[38]_i_2__1_n_0 ;
  wire \txn_fifo_output[38]_i_3__1_n_0 ;
  wire \txn_fifo_output[39]_i_1__1_n_0 ;
  wire \txn_fifo_output[39]_i_2__1_n_0 ;
  wire \txn_fifo_output[39]_i_3__1_n_0 ;
  wire \txn_fifo_output[40]_i_1__1_n_0 ;
  wire \txn_fifo_output[40]_i_2__1_n_0 ;
  wire \txn_fifo_output[40]_i_3__1_n_0 ;
  wire \txn_fifo_output[44]_i_1__1_n_0 ;
  wire \txn_fifo_output[44]_i_2__1_n_0 ;
  wire \txn_fifo_output[44]_i_3__1_n_0 ;
  wire \txn_fifo_output[45]_i_1__1_n_0 ;
  wire \txn_fifo_output[45]_i_2__1_n_0 ;
  wire \txn_fifo_output[45]_i_3__1_n_0 ;
  wire \txn_fifo_output[46]_i_1__1_n_0 ;
  wire \txn_fifo_output[46]_i_2__1_n_0 ;
  wire \txn_fifo_output[46]_i_3__1_n_0 ;
  wire \txn_fifo_output[47]_i_1__1_n_0 ;
  wire \txn_fifo_output[47]_i_2__1_n_0 ;
  wire \txn_fifo_output[47]_i_3__1_n_0 ;
  wire \txn_fifo_output[47]_i_4__0_n_0 ;
  wire \txn_fifo_output[47]_i_5__0_n_0 ;
  wire \txn_fifo_output_reg_n_0_[11] ;
  wire \txn_fifo_output_reg_n_0_[12] ;
  wire \txn_fifo_output_reg_n_0_[13] ;
  wire \txn_fifo_output_reg_n_0_[14] ;
  wire \txn_fifo_output_reg_n_0_[15] ;
  wire \txn_fifo_output_reg_n_0_[16] ;
  wire \txn_fifo_output_reg_n_0_[17] ;
  wire \txn_fifo_output_reg_n_0_[44] ;
  wire \txn_fifo_output_reg_n_0_[45] ;
  wire \txn_fifo_output_reg_n_0_[46] ;
  wire \txn_fifo_output_reg_n_0_[47] ;
  wire \txn_fifo_reg_n_0_[0][0] ;
  wire \txn_fifo_reg_n_0_[0][11] ;
  wire \txn_fifo_reg_n_0_[0][12] ;
  wire \txn_fifo_reg_n_0_[0][13] ;
  wire \txn_fifo_reg_n_0_[0][14] ;
  wire \txn_fifo_reg_n_0_[0][15] ;
  wire \txn_fifo_reg_n_0_[0][16] ;
  wire \txn_fifo_reg_n_0_[0][17] ;
  wire \txn_fifo_reg_n_0_[0][1] ;
  wire \txn_fifo_reg_n_0_[0][24] ;
  wire \txn_fifo_reg_n_0_[0][25] ;
  wire \txn_fifo_reg_n_0_[0][26] ;
  wire \txn_fifo_reg_n_0_[0][27] ;
  wire \txn_fifo_reg_n_0_[0][28] ;
  wire \txn_fifo_reg_n_0_[0][29] ;
  wire \txn_fifo_reg_n_0_[0][2] ;
  wire \txn_fifo_reg_n_0_[0][30] ;
  wire \txn_fifo_reg_n_0_[0][31] ;
  wire \txn_fifo_reg_n_0_[0][32] ;
  wire \txn_fifo_reg_n_0_[0][33] ;
  wire \txn_fifo_reg_n_0_[0][34] ;
  wire \txn_fifo_reg_n_0_[0][35] ;
  wire \txn_fifo_reg_n_0_[0][36] ;
  wire \txn_fifo_reg_n_0_[0][37] ;
  wire \txn_fifo_reg_n_0_[0][38] ;
  wire \txn_fifo_reg_n_0_[0][39] ;
  wire \txn_fifo_reg_n_0_[0][40] ;
  wire \txn_fifo_reg_n_0_[0][44] ;
  wire \txn_fifo_reg_n_0_[0][45] ;
  wire \txn_fifo_reg_n_0_[0][46] ;
  wire \txn_fifo_reg_n_0_[0][47] ;
  wire \txn_fifo_reg_n_0_[1][0] ;
  wire \txn_fifo_reg_n_0_[1][11] ;
  wire \txn_fifo_reg_n_0_[1][12] ;
  wire \txn_fifo_reg_n_0_[1][13] ;
  wire \txn_fifo_reg_n_0_[1][14] ;
  wire \txn_fifo_reg_n_0_[1][15] ;
  wire \txn_fifo_reg_n_0_[1][16] ;
  wire \txn_fifo_reg_n_0_[1][17] ;
  wire \txn_fifo_reg_n_0_[1][1] ;
  wire \txn_fifo_reg_n_0_[1][24] ;
  wire \txn_fifo_reg_n_0_[1][25] ;
  wire \txn_fifo_reg_n_0_[1][26] ;
  wire \txn_fifo_reg_n_0_[1][27] ;
  wire \txn_fifo_reg_n_0_[1][28] ;
  wire \txn_fifo_reg_n_0_[1][29] ;
  wire \txn_fifo_reg_n_0_[1][2] ;
  wire \txn_fifo_reg_n_0_[1][30] ;
  wire \txn_fifo_reg_n_0_[1][31] ;
  wire \txn_fifo_reg_n_0_[1][32] ;
  wire \txn_fifo_reg_n_0_[1][33] ;
  wire \txn_fifo_reg_n_0_[1][34] ;
  wire \txn_fifo_reg_n_0_[1][35] ;
  wire \txn_fifo_reg_n_0_[1][36] ;
  wire \txn_fifo_reg_n_0_[1][37] ;
  wire \txn_fifo_reg_n_0_[1][38] ;
  wire \txn_fifo_reg_n_0_[1][39] ;
  wire \txn_fifo_reg_n_0_[1][40] ;
  wire \txn_fifo_reg_n_0_[1][44] ;
  wire \txn_fifo_reg_n_0_[1][45] ;
  wire \txn_fifo_reg_n_0_[1][46] ;
  wire \txn_fifo_reg_n_0_[1][47] ;
  wire \txn_fifo_reg_n_0_[2][0] ;
  wire \txn_fifo_reg_n_0_[2][11] ;
  wire \txn_fifo_reg_n_0_[2][12] ;
  wire \txn_fifo_reg_n_0_[2][13] ;
  wire \txn_fifo_reg_n_0_[2][14] ;
  wire \txn_fifo_reg_n_0_[2][15] ;
  wire \txn_fifo_reg_n_0_[2][16] ;
  wire \txn_fifo_reg_n_0_[2][17] ;
  wire \txn_fifo_reg_n_0_[2][1] ;
  wire \txn_fifo_reg_n_0_[2][24] ;
  wire \txn_fifo_reg_n_0_[2][25] ;
  wire \txn_fifo_reg_n_0_[2][26] ;
  wire \txn_fifo_reg_n_0_[2][27] ;
  wire \txn_fifo_reg_n_0_[2][28] ;
  wire \txn_fifo_reg_n_0_[2][29] ;
  wire \txn_fifo_reg_n_0_[2][2] ;
  wire \txn_fifo_reg_n_0_[2][30] ;
  wire \txn_fifo_reg_n_0_[2][31] ;
  wire \txn_fifo_reg_n_0_[2][32] ;
  wire \txn_fifo_reg_n_0_[2][33] ;
  wire \txn_fifo_reg_n_0_[2][34] ;
  wire \txn_fifo_reg_n_0_[2][35] ;
  wire \txn_fifo_reg_n_0_[2][36] ;
  wire \txn_fifo_reg_n_0_[2][37] ;
  wire \txn_fifo_reg_n_0_[2][38] ;
  wire \txn_fifo_reg_n_0_[2][39] ;
  wire \txn_fifo_reg_n_0_[2][40] ;
  wire \txn_fifo_reg_n_0_[2][44] ;
  wire \txn_fifo_reg_n_0_[2][45] ;
  wire \txn_fifo_reg_n_0_[2][46] ;
  wire \txn_fifo_reg_n_0_[2][47] ;
  wire \txn_fifo_reg_n_0_[3][0] ;
  wire \txn_fifo_reg_n_0_[3][11] ;
  wire \txn_fifo_reg_n_0_[3][12] ;
  wire \txn_fifo_reg_n_0_[3][13] ;
  wire \txn_fifo_reg_n_0_[3][14] ;
  wire \txn_fifo_reg_n_0_[3][15] ;
  wire \txn_fifo_reg_n_0_[3][16] ;
  wire \txn_fifo_reg_n_0_[3][17] ;
  wire \txn_fifo_reg_n_0_[3][1] ;
  wire \txn_fifo_reg_n_0_[3][24] ;
  wire \txn_fifo_reg_n_0_[3][25] ;
  wire \txn_fifo_reg_n_0_[3][26] ;
  wire \txn_fifo_reg_n_0_[3][27] ;
  wire \txn_fifo_reg_n_0_[3][28] ;
  wire \txn_fifo_reg_n_0_[3][29] ;
  wire \txn_fifo_reg_n_0_[3][2] ;
  wire \txn_fifo_reg_n_0_[3][30] ;
  wire \txn_fifo_reg_n_0_[3][31] ;
  wire \txn_fifo_reg_n_0_[3][32] ;
  wire \txn_fifo_reg_n_0_[3][33] ;
  wire \txn_fifo_reg_n_0_[3][34] ;
  wire \txn_fifo_reg_n_0_[3][35] ;
  wire \txn_fifo_reg_n_0_[3][36] ;
  wire \txn_fifo_reg_n_0_[3][37] ;
  wire \txn_fifo_reg_n_0_[3][38] ;
  wire \txn_fifo_reg_n_0_[3][39] ;
  wire \txn_fifo_reg_n_0_[3][40] ;
  wire \txn_fifo_reg_n_0_[3][44] ;
  wire \txn_fifo_reg_n_0_[3][45] ;
  wire \txn_fifo_reg_n_0_[3][46] ;
  wire \txn_fifo_reg_n_0_[3][47] ;
  wire \txn_fifo_rptr[0]_i_1__1_n_0 ;
  wire \txn_fifo_rptr[1]_i_1__1_n_0 ;
  wire \txn_fifo_rptr[1]_i_2__0_n_0 ;
  wire \txn_fifo_rptr_reg_n_0_[0] ;
  wire \txn_fifo_rptr_reg_n_0_[1] ;
  wire \txn_fifo_wptr[0]_i_1__0_n_0 ;
  wire \txn_fifo_wptr[1]_i_1__0_n_0 ;
  wire \txn_fifo_wptr_reg[0]_0 ;
  wire \txn_fifo_wptr_reg_n_0_[0] ;
  wire \txn_fifo_wptr_reg_n_0_[1] ;
  wire underfill_done_reg_0;
  wire underfill_done_reg_n_0;
  wire useAdr;
  wire wrReqR_i_1__1_n_0;
  wire wrReqR_i_2__1_n_0;
  wire wrReqR_i_3__0_n_0;
  wire wrReqR_i_4__0_n_0;
  wire wrReqR_i_5__0_n_0;
  wire wrReqR_i_6__0_n_0;
  wire wrReqR_i_7__0_n_0;
  wire wrReqR_i_8_n_0;
  wire wrReqR_reg_0;
  wire [7:6]\NLW_issue_cas3_inferred__0/i__carry_CO_UNCONNECTED ;
  wire [7:0]\NLW_issue_cas3_inferred__0/i__carry_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h08AA000008AAAAAA)) 
    \FSM_sequential_grSt[0]_i_1__1 
       (.I0(\FSM_sequential_grSt[0]_i_2__1_n_0 ),
        .I1(\FSM_sequential_grSt_reg[0]_0 ),
        .I2(cas_fifo_full_reg_n_0),
        .I3(grSt[0]),
        .I4(grSt[1]),
        .I5(grSt[2]),
        .O(\FSM_sequential_grSt[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFEFFFAAAAAAAA)) 
    \FSM_sequential_grSt[0]_i_2__1 
       (.I0(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I1(actReqR_i_2__0_n_0),
        .I2(ref_req_dly4),
        .I3(txn_fifo_empty_reg_n_0),
        .I4(\FSM_sequential_grSt[2]_i_7__1_n_0 ),
        .I5(preReqR_i_2__0_n_0),
        .O(\FSM_sequential_grSt[0]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000262626FF)) 
    \FSM_sequential_grSt[1]_i_1__1 
       (.I0(grSt[2]),
        .I1(grSt[1]),
        .I2(grSt[0]),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[2]_i_6__0_n_0 ),
        .I5(\FSM_sequential_grSt[1]_i_3__1_n_0 ),
        .O(\FSM_sequential_grSt[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBBBBBBBFFF)) 
    \FSM_sequential_grSt[1]_i_2__0 
       (.I0(grSt[1]),
        .I1(grSt[0]),
        .I2(\FSM_sequential_grSt[1]_i_4__0_n_0 ),
        .I3(\cas_pend_fifo_reg_n_0_[1][47] ),
        .I4(\FSM_sequential_grSt[1]_i_5_n_0 ),
        .I5(\FSM_sequential_grSt[1]_i_6__1_n_0 ),
        .O(\FSM_sequential_grSt[1]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00000700)) 
    \FSM_sequential_grSt[1]_i_3__1 
       (.I0(ref_req_dly4),
        .I1(txn_fifo_empty_reg_n_0),
        .I2(grSt[2]),
        .I3(grSt[0]),
        .I4(\FSM_sequential_grSt[2]_i_7__1_n_0 ),
        .O(\FSM_sequential_grSt[1]_i_3__1_n_0 ));
  LUT5 #(
    .INIT(32'h90000090)) 
    \FSM_sequential_grSt[1]_i_4__0 
       (.I0(\cas_pend_fifo_reg_n_0_[1][1] ),
        .I1(Q[1]),
        .I2(\cas_fifo_valid_reg_n_0_[1] ),
        .I3(Q[0]),
        .I4(\cas_pend_fifo_reg_n_0_[1][0] ),
        .O(\FSM_sequential_grSt[1]_i_4__0_n_0 ));
  LUT5 #(
    .INIT(32'hEFEFFFEF)) 
    \FSM_sequential_grSt[1]_i_5 
       (.I0(\cmdBankP[1]_i_3_n_0 ),
        .I1(cas_fifo_full_reg_n_0),
        .I2(\issue_cas3_inferred__0/i__carry_n_2 ),
        .I3(txn_fifo_empty_reg_n_0),
        .I4(txn_fifo_empty_i_2__0_n_0),
        .O(\FSM_sequential_grSt[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF88F888F888F8)) 
    \FSM_sequential_grSt[1]_i_6__1 
       (.I0(\cmdBankP[1]_i_5__0_n_0 ),
        .I1(\cas_pend_fifo_reg_n_0_[3][47] ),
        .I2(\cas_pend_fifo_reg_n_0_[2][47] ),
        .I3(\cmdBankP[1]_i_6__0_n_0 ),
        .I4(\cas_pend_fifo_reg_n_0_[0][47] ),
        .I5(\cmdBankP[1]_i_4__0_n_0 ),
        .O(\FSM_sequential_grSt[1]_i_6__1_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEEEEEFEEEEE)) 
    \FSM_sequential_grSt[2]_i_1__0 
       (.I0(\FSM_sequential_grSt[2]_i_3__0_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_4__2_n_0 ),
        .I2(trp_cntr_is_zero_reg_n_0),
        .I3(grSt[2]),
        .I4(grSt[1]),
        .I5(grSt[0]),
        .O(\FSM_sequential_grSt[2]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h8A888888)) 
    \FSM_sequential_grSt[2]_i_2__0 
       (.I0(\FSM_sequential_grSt[2]_i_5__2_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_6__0_n_0 ),
        .I2(\FSM_sequential_grSt[2]_i_7__1_n_0 ),
        .I3(txn_fifo_empty_reg_n_0),
        .I4(ref_req_dly4),
        .O(\FSM_sequential_grSt[2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h00FFCCFF00F00055)) 
    \FSM_sequential_grSt[2]_i_3__0 
       (.I0(cas_fifo_full_reg_n_0),
        .I1(\FSM_sequential_grSt_reg[0]_0 ),
        .I2(preReqR_reg_1),
        .I3(grSt[1]),
        .I4(grSt[2]),
        .I5(grSt[0]),
        .O(\FSM_sequential_grSt[2]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h005D000000000000)) 
    \FSM_sequential_grSt[2]_i_4__2 
       (.I0(txn_fifo_empty_reg_n_0),
        .I1(group),
        .I2(bank[0]),
        .I3(\FSM_sequential_grSt_reg[0]_1 ),
        .I4(grSt[1]),
        .I5(grSt[2]),
        .O(\FSM_sequential_grSt[2]_i_4__2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_sequential_grSt[2]_i_5__2 
       (.I0(grSt[2]),
        .I1(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_5__2_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_grSt[2]_i_6__0 
       (.I0(actReqR_i_2__0_n_0),
        .I1(preReqR_i_2__0_n_0),
        .O(\FSM_sequential_grSt[2]_i_6__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_grSt[2]_i_7__1 
       (.I0(\cmdBankP[1]_i_3_n_0 ),
        .I1(\cmdBankP[1]_i_2__0_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_7__1_n_0 ));
  (* FSM_ENCODED_STATES = "grACT:010,grPREWAIT:100,grAUTOPRE:101,grACTWAIT:011,grIDLE:110,grCASFSM:000,grACCEPT:001" *) 
  FDRE \FSM_sequential_grSt_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(\FSM_sequential_grSt[2]_i_1__0_n_0 ),
        .D(\FSM_sequential_grSt[0]_i_1__1_n_0 ),
        .Q(grSt[0]),
        .R(rst_r1));
  (* FSM_ENCODED_STATES = "grACT:010,grPREWAIT:100,grAUTOPRE:101,grACTWAIT:011,grIDLE:110,grCASFSM:000,grACCEPT:001" *) 
  FDSE \FSM_sequential_grSt_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(\FSM_sequential_grSt[2]_i_1__0_n_0 ),
        .D(\FSM_sequential_grSt[1]_i_1__1_n_0 ),
        .Q(grSt[1]),
        .S(rst_r1));
  (* FSM_ENCODED_STATES = "grACT:010,grPREWAIT:100,grAUTOPRE:101,grACTWAIT:011,grIDLE:110,grCASFSM:000,grACCEPT:001" *) 
  FDSE \FSM_sequential_grSt_reg[2] 
       (.C(rst_r1_reg_0),
        .CE(\FSM_sequential_grSt[2]_i_1__0_n_0 ),
        .D(\FSM_sequential_grSt[2]_i_2__0_n_0 ),
        .Q(grSt[2]),
        .S(rst_r1));
  LUT6 #(
    .INIT(64'hAAAAAAAA00002022)) 
    \FSM_sequential_gr_cas_state[0]_i_1__1 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_5_n_0 ),
        .I1(\FSM_sequential_gr_cas_state[2]_i_8__2_n_0 ),
        .I2(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ),
        .I3(cas_fifo_empty_reg_n_0),
        .I4(\FSM_sequential_gr_cas_state[2]_i_6__1_n_0 ),
        .I5(gr_cas_state[1]),
        .O(gr_cas_state_nxt[0]));
  (* SOFT_HLUTNM = "soft_lutpair2625" *) 
  LUT3 #(
    .INIT(8'h12)) 
    \FSM_sequential_gr_cas_state[1]_i_1__1 
       (.I0(gr_cas_state[0]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[1]),
        .O(gr_cas_state_nxt[1]));
  LUT6 #(
    .INIT(64'hAABAFAEEAABAFAAA)) 
    \FSM_sequential_gr_cas_state[2]_i_1__1 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_3_n_0 ),
        .I1(gr_cas_state[1]),
        .I2(clrReq17_out),
        .I3(gr_cas_state[0]),
        .I4(gr_cas_state[2]),
        .I5(underfill_done_reg_n_0),
        .O(\FSM_sequential_gr_cas_state[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h2222222220202220)) 
    \FSM_sequential_gr_cas_state[2]_i_2__1 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_5_n_0 ),
        .I1(gr_cas_state[1]),
        .I2(\FSM_sequential_gr_cas_state[2]_i_6__1_n_0 ),
        .I3(cas_fifo_empty_reg_n_0),
        .I4(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ),
        .I5(\FSM_sequential_gr_cas_state[2]_i_8__2_n_0 ),
        .O(gr_cas_state_nxt[2]));
  LUT6 #(
    .INIT(64'h0000000010550000)) 
    \FSM_sequential_gr_cas_state[2]_i_3 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_8__2_n_0 ),
        .I1(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I2(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I3(cas_fifo_empty_reg_n_0),
        .I4(\FSM_sequential_gr_cas_state[2]_i_5_n_0 ),
        .I5(gr_cas_state[1]),
        .O(\FSM_sequential_gr_cas_state[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2635" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_sequential_gr_cas_state[2]_i_5 
       (.I0(gr_cas_state[0]),
        .I1(gr_cas_state[2]),
        .O(\FSM_sequential_gr_cas_state[2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_gr_cas_state[2]_i_6__1 
       (.I0(rdReqR_i_2__1_n_0),
        .I1(wrReqR_i_4__0_n_0),
        .O(\FSM_sequential_gr_cas_state[2]_i_6__1_n_0 ));
  LUT6 #(
    .INIT(64'h000000002A220202)) 
    \FSM_sequential_gr_cas_state[2]_i_7__0 
       (.I0(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I1(grSt[1]),
        .I2(cas_fifo_full_reg_n_0),
        .I3(\FSM_sequential_grSt_reg[0]_0 ),
        .I4(grSt[0]),
        .I5(grSt[2]),
        .O(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ));
  LUT6 #(
    .INIT(64'h050305F3F503F5F3)) 
    \FSM_sequential_gr_cas_state[2]_i_8__2 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I1(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I2(\cmd_bank_cas[1]_i_1__1_n_0 ),
        .I3(\cmd_bank_cas[0]_i_1__1_n_0 ),
        .I4(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I5(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .O(\FSM_sequential_gr_cas_state[2]_i_8__2_n_0 ));
  (* FSM_ENCODED_STATES = "CAS_IDLE:000,RMW_DATAWAIT:010,RMW_WRWAIT:011,CAS_WAIT:100,RMW_RDWAIT:001" *) 
  FDRE \FSM_sequential_gr_cas_state_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(\FSM_sequential_gr_cas_state[2]_i_1__1_n_0 ),
        .D(gr_cas_state_nxt[0]),
        .Q(gr_cas_state[0]),
        .R(rst_r1));
  (* FSM_ENCODED_STATES = "CAS_IDLE:000,RMW_DATAWAIT:010,RMW_WRWAIT:011,CAS_WAIT:100,RMW_RDWAIT:001" *) 
  FDRE \FSM_sequential_gr_cas_state_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(\FSM_sequential_gr_cas_state[2]_i_1__1_n_0 ),
        .D(gr_cas_state_nxt[1]),
        .Q(gr_cas_state[1]),
        .R(rst_r1));
  (* FSM_ENCODED_STATES = "CAS_IDLE:000,RMW_DATAWAIT:010,RMW_WRWAIT:011,CAS_WAIT:100,RMW_RDWAIT:001" *) 
  FDRE \FSM_sequential_gr_cas_state_reg[2] 
       (.C(rst_r1_reg_0),
        .CE(\FSM_sequential_gr_cas_state[2]_i_1__1_n_0 ),
        .D(gr_cas_state_nxt[2]),
        .Q(gr_cas_state[2]),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h7DD77D7D)) 
    accept_i_2__1
       (.I0(\txn_fifo_wptr_reg[0]_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[0] ),
        .O(calDone_gated_reg));
  FDRE accept_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(grAccept_ns),
        .Q(accept_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFFFF20)) 
    actReqR_i_1__1
       (.I0(\FSM_sequential_grSt[2]_i_5__2_n_0 ),
        .I1(actReqR_i_2__0_n_0),
        .I2(\FSM_sequential_grSt[2]_i_7__1_n_0 ),
        .I3(actReqR_reg_0),
        .I4(actReqR_i_3_n_0),
        .I5(\FSM_sequential_grSt_reg[0]_0 ),
        .O(actReqR_i_1__1_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    actReqR_i_2__0
       (.I0(\cmdBankP[1]_i_2__0_n_0 ),
        .I1(actReqR_i_4_n_0),
        .O(actReqR_i_2__0_n_0));
  LUT4 #(
    .INIT(16'h0020)) 
    actReqR_i_3
       (.I0(trp_cntr_is_zero_reg_n_0),
        .I1(grSt[2]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .O(actReqR_i_3_n_0));
  LUT6 #(
    .INIT(64'h55000F3355FF0F33)) 
    actReqR_i_4
       (.I0(\pageInfo_reg_n_0_[0][0][3][1] ),
        .I1(\pageInfo_reg_n_0_[0][0][0][1] ),
        .I2(\pageInfo_reg_n_0_[0][0][2][1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\pageInfo_reg_n_0_[0][0][1][1] ),
        .O(actReqR_i_4_n_0));
  FDRE actReqR_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(actReqR_i_1__1_n_0),
        .Q(actReqR_reg_0),
        .R(rst_r1));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][0][0]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .O(\ap_cntr[0][0][0][0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][0][1]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[1] ),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .I4(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .O(\ap_cntr[0][0][0][1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][0][2]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[2] ),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .O(\ap_cntr[0][0][0][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2648" *) 
  LUT4 #(
    .INIT(16'h8BB8)) 
    \ap_cntr[0][0][0][3]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .I3(\ap_cntr[0][0][0][4]_i_2__1_n_0 ),
        .O(\ap_cntr[0][0][0][3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2648" *) 
  LUT4 #(
    .INIT(16'h00D2)) 
    \ap_cntr[0][0][0][4]_i_1__1 
       (.I0(\ap_cntr[0][0][0][4]_i_2__1_n_0 ),
        .I1(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][4] ),
        .I3(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .O(\ap_cntr[0][0][0][4]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \ap_cntr[0][0][0][4]_i_2__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I1(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .I3(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .O(\ap_cntr[0][0][0][4]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000820)) 
    \ap_cntr[0][0][0][4]_i_3__1 
       (.I0(cmdAP),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(gr_cas_state[1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\cmd_bank_cas_reg[1]_0 [1]),
        .O(\ap_cntr[0][0][0][4]_i_3__1_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][1][0]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .O(\ap_cntr[0][0][1][0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][1][1]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[1] ),
        .I1(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .O(\ap_cntr[0][0][1][1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][1][2]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[2] ),
        .I1(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .O(\ap_cntr[0][0][1][2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][1][3]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .I4(\ap_cntr[0][0][1][4]_i_2__1_n_0 ),
        .I5(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .O(\ap_cntr[0][0][1][3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFB0004)) 
    \ap_cntr[0][0][1][4]_i_1__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .I1(\ap_cntr[0][0][1][4]_i_2__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .I4(\ap_cntr_reg_n_0_[0][0][1][4] ),
        .I5(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .O(\ap_cntr[0][0][1][4]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2649" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][1][4]_i_2__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .I1(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .O(\ap_cntr[0][0][1][4]_i_2__1_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][2][0]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .O(\ap_cntr[0][0][2][0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2626" *) 
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][2][1]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[1] ),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .I4(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .O(\ap_cntr[0][0][2][1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][2][2]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[2] ),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .O(\ap_cntr[0][0][2][2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][2][3]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][2][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .I4(\ap_cntr[0][0][2][4]_i_2__1_n_0 ),
        .I5(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .O(\ap_cntr[0][0][2][3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFB0004)) 
    \ap_cntr[0][0][2][4]_i_1__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .I1(\ap_cntr[0][0][2][4]_i_2__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .I3(\ap_cntr_reg_n_0_[0][0][2][3] ),
        .I4(\ap_cntr_reg_n_0_[0][0][2][4] ),
        .I5(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .O(\ap_cntr[0][0][2][4]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2626" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][2][4]_i_2__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .I1(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .O(\ap_cntr[0][0][2][4]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000008200000)) 
    \ap_cntr[0][0][2][4]_i_3__0 
       (.I0(cmdAP),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(gr_cas_state[1]),
        .I4(\cmd_bank_cas_reg[1]_0 [1]),
        .I5(\cmd_bank_cas_reg[1]_0 [0]),
        .O(\ap_cntr[0][0][2][4]_i_3__0_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][3][0]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .O(\ap_cntr[0][0][3][0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2630" *) 
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][3][1]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[1] ),
        .I1(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .I4(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .O(\ap_cntr[0][0][3][1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][3][2]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[2] ),
        .I1(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .O(\ap_cntr[0][0][3][2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][3][3]_i_1__1 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .I4(\ap_cntr[0][0][3][4]_i_2__1_n_0 ),
        .I5(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .O(\ap_cntr[0][0][3][3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFB0004)) 
    \ap_cntr[0][0][3][4]_i_1__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .I1(\ap_cntr[0][0][3][4]_i_2__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I3(\ap_cntr_reg_n_0_[0][0][3][3] ),
        .I4(\ap_cntr_reg_n_0_[0][0][3][4] ),
        .I5(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .O(\ap_cntr[0][0][3][4]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2630" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][3][4]_i_2__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .I1(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .O(\ap_cntr[0][0][3][4]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h0820000000000000)) 
    \ap_cntr[0][0][3][4]_i_3__1 
       (.I0(cmdAP),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(gr_cas_state[1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\cmd_bank_cas_reg[1]_0 [1]),
        .O(\ap_cntr[0][0][3][4]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_cntr_expired[0][0][0]_i_1__2 
       (.I0(\ap_cntr[0][0][0][4]_i_1__1_n_0 ),
        .I1(\ap_cntr[0][0][0][0]_i_1__1_n_0 ),
        .I2(\ap_cntr[0][0][0][2]_i_1__1_n_0 ),
        .I3(\ap_cntr[0][0][0][1]_i_1__1_n_0 ),
        .I4(\ap_cntr[0][0][0][3]_i_1__1_n_0 ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .O(\ap_cntr_expired[0][0][0]_i_1__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \ap_cntr_expired[0][0][1]_i_1 
       (.I0(\ap_cntr_zero[0][0][1]_i_1__1_n_0 ),
        .I1(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .O(\ap_cntr_expired[0][0][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_cntr_expired[0][0][2]_i_1__1 
       (.I0(\ap_cntr[0][0][2][1]_i_1__1_n_0 ),
        .I1(\ap_cntr[0][0][2][4]_i_1__1_n_0 ),
        .I2(\ap_cntr[0][0][2][0]_i_1__1_n_0 ),
        .I3(\ap_cntr[0][0][2][2]_i_1__1_n_0 ),
        .I4(\ap_cntr[0][0][2][3]_i_1__1_n_0 ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .O(\ap_cntr_expired[0][0][2]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_expired[0][0][3]_i_1__1 
       (.I0(\ap_cntr[0][0][3][4]_i_1__1_n_0 ),
        .I1(\ap_cntr[0][0][3][2]_i_1__1_n_0 ),
        .I2(\ap_cntr_zero[0][0][3]_i_2_n_0 ),
        .I3(\ap_cntr[0][0][3][3]_i_1__1_n_0 ),
        .I4(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .O(\ap_cntr_expired[0][0][3]_i_1__1_n_0 ));
  FDRE \ap_cntr_expired_reg[0][0][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_expired[0][0][0]_i_1__2_n_0 ),
        .Q(sel0__46),
        .R(1'b0));
  FDRE \ap_cntr_expired_reg[0][0][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_expired[0][0][1]_i_1_n_0 ),
        .Q(sel0__42),
        .R(1'b0));
  FDRE \ap_cntr_expired_reg[0][0][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_expired[0][0][2]_i_1__1_n_0 ),
        .Q(sel0__38),
        .R(1'b0));
  FDRE \ap_cntr_expired_reg[0][0][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_expired[0][0][3]_i_1__1_n_0 ),
        .Q(sel0__34),
        .R(1'b0));
  FDRE \ap_cntr_reg[0][0][0][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][0]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][1]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][2]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][3]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][4] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][4]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][4] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][0]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][1]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][2]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][3]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][4] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][4]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][4] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][0]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][1]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][2]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][3]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][3] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][4] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][4]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][4] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][0]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][1]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][2]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][3]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][3] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][4] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][4]_i_1__1_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][4] ),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_zero[0][0][0]_i_1__1 
       (.I0(\ap_cntr[0][0][0][4]_i_1__1_n_0 ),
        .I1(\ap_cntr[0][0][0][0]_i_1__1_n_0 ),
        .I2(\ap_cntr[0][0][0][2]_i_1__1_n_0 ),
        .I3(\ap_cntr[0][0][0][1]_i_1__1_n_0 ),
        .I4(\ap_cntr[0][0][0][3]_i_1__1_n_0 ),
        .O(\ap_cntr_zero[0][0][0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000009FF09)) 
    \ap_cntr_zero[0][0][1]_i_1__1 
       (.I0(\ap_cntr_zero[0][0][1]_i_2_n_0 ),
        .I1(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][4] ),
        .I3(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I4(\ap_load_value_reg_n_0_[3] ),
        .I5(\ap_cntr_zero[0][0][1]_i_4_n_0 ),
        .O(\ap_cntr_zero[0][0][1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2649" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \ap_cntr_zero[0][0][1]_i_2 
       (.I0(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .I1(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .O(\ap_cntr_zero[0][0][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000008200000)) 
    \ap_cntr_zero[0][0][1]_i_3 
       (.I0(cmdAP),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(gr_cas_state[1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\cmd_bank_cas_reg[1]_0 [1]),
        .O(\ap_cntr_zero[0][0][1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFFEEEFEEEFEFF)) 
    \ap_cntr_zero[0][0][1]_i_4 
       (.I0(\ap_cntr[0][0][1][2]_i_1__1_n_0 ),
        .I1(\ap_cntr[0][0][1][1]_i_1__1_n_0 ),
        .I2(\ap_load_value_reg_n_0_[0] ),
        .I3(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I4(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .I5(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .O(\ap_cntr_zero[0][0][1]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_zero[0][0][2]_i_1__1 
       (.I0(\ap_cntr[0][0][2][1]_i_1__1_n_0 ),
        .I1(\ap_cntr[0][0][2][4]_i_1__1_n_0 ),
        .I2(\ap_cntr[0][0][2][0]_i_1__1_n_0 ),
        .I3(\ap_cntr[0][0][2][2]_i_1__1_n_0 ),
        .I4(\ap_cntr[0][0][2][3]_i_1__1_n_0 ),
        .O(\ap_cntr_zero[0][0][2]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \ap_cntr_zero[0][0][3]_i_1__1 
       (.I0(\ap_cntr[0][0][3][4]_i_1__1_n_0 ),
        .I1(\ap_cntr[0][0][3][2]_i_1__1_n_0 ),
        .I2(\ap_cntr_zero[0][0][3]_i_2_n_0 ),
        .I3(\ap_cntr[0][0][3][3]_i_1__1_n_0 ),
        .O(\ap_cntr_zero[0][0][3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFC3AAAAFFC3)) 
    \ap_cntr_zero[0][0][3]_i_2 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I4(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I5(\ap_load_value_reg_n_0_[1] ),
        .O(\ap_cntr_zero[0][0][3]_i_2_n_0 ));
  FDRE \ap_cntr_zero_reg[0][0][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_zero[0][0][0]_i_1__1_n_0 ),
        .Q(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_zero_reg[0][0][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_zero[0][0][1]_i_1__1_n_0 ),
        .Q(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_zero_reg[0][0][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_zero[0][0][2]_i_1__1_n_0 ),
        .Q(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_zero_reg[0][0][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_cntr_zero[0][0][3]_i_1__1_n_0 ),
        .Q(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2688" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \ap_load_value[0]_i_1__1 
       (.I0(wrReqR_reg_0),
        .I1(\ap_load_value[0]_i_2__1_n_0 ),
        .I2(\ap_load_value[3]_i_3__1_n_0 ),
        .O(\ap_load_value[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0F3300550F33FF55)) 
    \ap_load_value[0]_i_2__1 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .I3(\cmd_bank_cas_reg[1]_0 [0]),
        .I4(\cmd_bank_cas_reg[1]_0 [1]),
        .I5(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .O(\ap_load_value[0]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2687" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \ap_load_value[1]_i_1__1 
       (.I0(\ap_load_value[3]_i_2__1_n_0 ),
        .I1(\ap_load_value[3]_i_3__1_n_0 ),
        .I2(wrReqR_reg_0),
        .O(\ap_load_value[1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2687" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \ap_load_value[2]_i_1__1 
       (.I0(\ap_load_value[3]_i_2__1_n_0 ),
        .I1(\ap_load_value[3]_i_3__1_n_0 ),
        .I2(wrReqR_reg_0),
        .O(\ap_load_value[2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2688" *) 
  LUT3 #(
    .INIT(8'hF1)) 
    \ap_load_value[3]_i_1__1 
       (.I0(\ap_load_value[3]_i_2__1_n_0 ),
        .I1(\ap_load_value[3]_i_3__1_n_0 ),
        .I2(wrReqR_reg_0),
        .O(\ap_load_value[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0033550FFF33550F)) 
    \ap_load_value[3]_i_2__1 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .I3(\cmd_bank_cas_reg[1]_0 [0]),
        .I4(\cmd_bank_cas_reg[1]_0 [1]),
        .I5(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .O(\ap_load_value[3]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    \ap_load_value[3]_i_3__1 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .I3(\cmd_bank_cas_reg[1]_0 [1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .O(\ap_load_value[3]_i_3__1_n_0 ));
  FDRE \ap_load_value_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_load_value[0]_i_1__1_n_0 ),
        .Q(\ap_load_value_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \ap_load_value_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_load_value[1]_i_1__1_n_0 ),
        .Q(\ap_load_value_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \ap_load_value_reg[2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_load_value[2]_i_1__1_n_0 ),
        .Q(\ap_load_value_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \ap_load_value_reg[3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\ap_load_value[3]_i_1__1_n_0 ),
        .Q(\ap_load_value_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2638" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][0]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[0][0] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][0]_0 ),
        .O(\buf_fifo[0][0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \buf_fifo[0][0]_i_3__1 
       (.I0(\buf_fifo_reg_n_0_[0][0] ),
        .I1(\buf_fifo_reg_n_0_[1][0] ),
        .I2(\buf_fifo_reg_n_0_[3][0] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[2][0] ),
        .O(\buf_fifo_reg[0][0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2644" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][1]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[0][1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][1]_0 ),
        .O(\buf_fifo[0][1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \buf_fifo[0][1]_i_3__1 
       (.I0(\buf_fifo_reg_n_0_[0][1] ),
        .I1(\buf_fifo_reg_n_0_[1][1] ),
        .I2(\buf_fifo_reg_n_0_[3][1] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[2][1] ),
        .O(\buf_fifo_reg[0][1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2643" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][2]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[0][2] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][2]_0 ),
        .O(\buf_fifo[0][2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAFFF0CCAA00F0)) 
    \buf_fifo[0][2]_i_3__1 
       (.I0(\buf_fifo_reg_n_0_[2][2] ),
        .I1(\buf_fifo_reg_n_0_[3][2] ),
        .I2(\buf_fifo_reg_n_0_[0][2] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[1][2] ),
        .O(\buf_fifo_reg[2][2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2645" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][3]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[0][3] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][3]_0 ),
        .O(\buf_fifo[0][3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \buf_fifo[0][3]_i_3__1 
       (.I0(\buf_fifo_reg_n_0_[0][3] ),
        .I1(\buf_fifo_reg_n_0_[1][3] ),
        .I2(\buf_fifo_reg_n_0_[3][3] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[2][3] ),
        .O(\buf_fifo_reg[0][3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2647" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][4]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[0][4] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][4]_0 ),
        .O(\buf_fifo[0][4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAFFF0CCAA00F0)) 
    \buf_fifo[0][4]_i_3__1 
       (.I0(\buf_fifo_reg_n_0_[2][4] ),
        .I1(\buf_fifo_reg_n_0_[3][4] ),
        .I2(\buf_fifo_reg_n_0_[0][4] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[1][4] ),
        .O(\buf_fifo_reg[2][4]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2642" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][0]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[1][0] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][0]_0 ),
        .O(\buf_fifo[1][0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2644" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][1]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[1][1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][1]_0 ),
        .O(\buf_fifo[1][1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2643" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][2]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[1][2] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][2]_0 ),
        .O(\buf_fifo[1][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2645" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][3]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[1][3] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][3]_0 ),
        .O(\buf_fifo[1][3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2647" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][4]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[1][4] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][4]_0 ),
        .O(\buf_fifo[1][4]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2642" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][0]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[2][0] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][0]_0 ),
        .O(\buf_fifo[2][0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2640" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][1]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[2][1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][1]_0 ),
        .O(\buf_fifo[2][1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2639" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][2]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[2][2] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][2]_0 ),
        .O(\buf_fifo[2][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2641" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][3]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[2][3] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][3]_0 ),
        .O(\buf_fifo[2][3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2646" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][4]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[2][4] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][4]_0 ),
        .O(\buf_fifo[2][4]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2638" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][0]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[3][0] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][0]_0 ),
        .O(\buf_fifo[3][0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2640" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][1]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[3][1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][1]_0 ),
        .O(\buf_fifo[3][1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2639" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][2]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[3][2] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][2]_0 ),
        .O(\buf_fifo[3][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2641" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][3]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[3][3] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][3]_0 ),
        .O(\buf_fifo[3][3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2646" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][4]_i_1__0 
       (.I0(\buf_fifo_reg_n_0_[3][4] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][4]_0 ),
        .O(\buf_fifo[3][4]_i_1__0_n_0 ));
  FDRE \buf_fifo_reg[0][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[0][0]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][0] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[0][1]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][1] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[0][2]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][2] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[0][3]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][3] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][4] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[0][4]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][4] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[1][0]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][0] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[1][1]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][1] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[1][2]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][2] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[1][3]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][3] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][4] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[1][4]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][4] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[2][0]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][0] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[2][1]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][1] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[2][2]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][2] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[2][3]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][3] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][4] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[2][4]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][4] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[3][0]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][0] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[3][1]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][1] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[3][2]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][2] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[3][3]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][3] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][4] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\buf_fifo[3][4]_i_1__0_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hCCFFF0AACC00F0AA)) 
    \cas_dbuf_fifo[0][0]_i_1__0 
       (.I0(\buf_fifo[0][0]_i_1__0_n_0 ),
        .I1(\buf_fifo[3][0]_i_1__0_n_0 ),
        .I2(\buf_fifo[1][0]_i_1__0_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[2][0]_i_1__0_n_0 ),
        .O(\cas_dbuf_fifo[0][0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][1]_i_1__0 
       (.I0(\buf_fifo[3][1]_i_1__0_n_0 ),
        .I1(\buf_fifo[2][1]_i_1__0_n_0 ),
        .I2(\buf_fifo[1][1]_i_1__0_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][1]_i_1__0_n_0 ),
        .O(\cas_dbuf_fifo[0][1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][2]_i_1__0 
       (.I0(\buf_fifo[3][2]_i_1__0_n_0 ),
        .I1(\buf_fifo[2][2]_i_1__0_n_0 ),
        .I2(\buf_fifo[1][2]_i_1__0_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][2]_i_1__0_n_0 ),
        .O(\cas_dbuf_fifo[0][2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][3]_i_1__0 
       (.I0(\buf_fifo[3][3]_i_1__0_n_0 ),
        .I1(\buf_fifo[2][3]_i_1__0_n_0 ),
        .I2(\buf_fifo[1][3]_i_1__0_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][3]_i_1__0_n_0 ),
        .O(\cas_dbuf_fifo[0][3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][4]_i_1__0 
       (.I0(\buf_fifo[3][4]_i_1__0_n_0 ),
        .I1(\buf_fifo[2][4]_i_1__0_n_0 ),
        .I2(\buf_fifo[1][4]_i_1__0_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][4]_i_1__0_n_0 ),
        .O(\cas_dbuf_fifo[0][4]_i_1__0_n_0 ));
  FDRE \cas_dbuf_fifo_reg[0][0] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][0]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][0] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][1] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][1]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][1] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][2] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][2]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][2] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][3] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][3]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][3] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][4] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][4]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][4] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][0] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][0]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][0] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][1] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][1]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][1] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][2] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][2]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][2] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][3] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][3]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][3] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][4] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][4]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][4] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][0] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][0]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][0] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][1] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][1]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][1] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][2] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][2]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][2] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][3] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][3]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][3] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][4] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][4]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][4] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][0] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][0]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][0] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][1] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][1]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][1] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][2] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][2]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][2] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][3] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][3]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][3] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][4] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\cas_dbuf_fifo[0][4]_i_1__0_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h1824824182412418)) 
    cas_fifo_empty_i_1__1
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_rptr_reg_n_0_[0] ),
        .I2(\cas_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_wptr_reg_n_0_[0] ),
        .I5(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ),
        .O(cas_fifo_empty_i_1__1_n_0));
  FDRE cas_fifo_empty_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(cas_fifo_empty_i_1__1_n_0),
        .Q(cas_fifo_empty_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h6669699996666669)) 
    cas_fifo_full_i_1__1
       (.I0(\cas_fifo_rptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[1] ),
        .I2(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ),
        .I3(\cas_fifo_wptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr[1]_i_2__1_n_0 ),
        .I5(\cas_fifo_rptr_reg_n_0_[0] ),
        .O(cas_fifo_full_i_1__1_n_0));
  FDRE cas_fifo_full_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(cas_fifo_full_i_1__1_n_0),
        .Q(cas_fifo_full_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h10FFFFFFEF000000)) 
    \cas_fifo_rptr[0]_i_1__1 
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[0]),
        .I3(\cas_fifo_rptr_reg[0]_0 ),
        .I4(tranSentC),
        .I5(\cas_fifo_rptr_reg_n_0_[0] ),
        .O(\cas_fifo_rptr[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2685" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \cas_fifo_rptr[1]_i_1__1 
       (.I0(\cas_fifo_rptr_reg_n_0_[1] ),
        .I1(\cas_fifo_rptr[1]_i_2__1_n_0 ),
        .I2(\cas_fifo_rptr_reg_n_0_[0] ),
        .O(\cas_fifo_rptr[1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2625" *) 
  LUT5 #(
    .INIT(32'h10FFFFFF)) 
    \cas_fifo_rptr[1]_i_2__1 
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[0]),
        .I3(\cas_fifo_rptr_reg[0]_0 ),
        .I4(tranSentC),
        .O(\cas_fifo_rptr[1]_i_2__1_n_0 ));
  FDRE \cas_fifo_rptr_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cas_fifo_rptr[0]_i_1__1_n_0 ),
        .Q(\cas_fifo_rptr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cas_fifo_rptr_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cas_fifo_rptr[1]_i_1__1_n_0 ),
        .Q(\cas_fifo_rptr_reg_n_0_[1] ),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hFF10FF10FF100000)) 
    \cas_fifo_valid[0]_i_1__1 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr_reg_n_0_[1] ),
        .I2(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ),
        .I3(\cas_fifo_valid_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr[1]_i_2__1_n_0 ),
        .I5(\cas_fifo_valid[0]_i_2__1_n_0 ),
        .O(\cas_fifo_valid[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2685" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \cas_fifo_valid[0]_i_2__1 
       (.I0(\cas_fifo_rptr_reg_n_0_[0] ),
        .I1(\cas_fifo_rptr_reg_n_0_[1] ),
        .O(\cas_fifo_valid[0]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hFF40FF40FF400000)) 
    \cas_fifo_valid[1]_i_1__1 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .I2(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ),
        .I3(\cas_fifo_valid_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr[1]_i_2__1_n_0 ),
        .I5(\cas_fifo_valid[1]_i_2__1_n_0 ),
        .O(\cas_fifo_valid[1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2704" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \cas_fifo_valid[1]_i_2__1 
       (.I0(\cas_fifo_rptr_reg_n_0_[1] ),
        .I1(\cas_fifo_rptr_reg_n_0_[0] ),
        .O(\cas_fifo_valid[1]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hFF40FF40FF400000)) 
    \cas_fifo_valid[2]_i_1__1 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr_reg_n_0_[1] ),
        .I2(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ),
        .I3(\cas_fifo_valid_reg_n_0_[2] ),
        .I4(\cas_fifo_rptr[1]_i_2__1_n_0 ),
        .I5(\cas_fifo_valid[2]_i_2__1_n_0 ),
        .O(\cas_fifo_valid[2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2704" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \cas_fifo_valid[2]_i_2__1 
       (.I0(\cas_fifo_rptr_reg_n_0_[0] ),
        .I1(\cas_fifo_rptr_reg_n_0_[1] ),
        .O(\cas_fifo_valid[2]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hFF80FF80FF800000)) 
    \cas_fifo_valid[3]_i_1__1 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .I2(\cas_fifo_wptr_reg_n_0_[1] ),
        .I3(\cas_fifo_valid_reg_n_0_[3] ),
        .I4(\cas_fifo_rptr[1]_i_2__1_n_0 ),
        .I5(\cas_fifo_valid[3]_i_2__1_n_0 ),
        .O(\cas_fifo_valid[3]_i_1__1_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \cas_fifo_valid[3]_i_2__1 
       (.I0(\cas_fifo_rptr_reg_n_0_[0] ),
        .I1(\cas_fifo_rptr_reg_n_0_[1] ),
        .O(\cas_fifo_valid[3]_i_2__1_n_0 ));
  FDRE \cas_fifo_valid_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cas_fifo_valid[0]_i_1__1_n_0 ),
        .Q(\cas_fifo_valid_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cas_fifo_valid_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cas_fifo_valid[1]_i_1__1_n_0 ),
        .Q(\cas_fifo_valid_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \cas_fifo_valid_reg[2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cas_fifo_valid[2]_i_1__1_n_0 ),
        .Q(\cas_fifo_valid_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \cas_fifo_valid_reg[3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cas_fifo_valid[3]_i_1__1_n_0 ),
        .Q(\cas_fifo_valid_reg_n_0_[3] ),
        .R(rst_r1));
  LUT2 #(
    .INIT(4'h6)) 
    \cas_fifo_wptr[0]_i_1__1 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ),
        .O(\cas_fifo_wptr[0]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'h6A)) 
    \cas_fifo_wptr[1]_i_1__1 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ),
        .I2(\cas_fifo_wptr_reg_n_0_[0] ),
        .O(\cas_fifo_wptr[1]_i_1__1_n_0 ));
  FDRE \cas_fifo_wptr_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cas_fifo_wptr[0]_i_1__1_n_0 ),
        .Q(\cas_fifo_wptr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cas_fifo_wptr_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cas_fifo_wptr[1]_i_1__1_n_0 ),
        .Q(\cas_fifo_wptr_reg_n_0_[1] ),
        .R(rst_r1));
  LUT2 #(
    .INIT(4'h1)) 
    \cas_pend_fifo[0][47]_i_1__0 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .O(\cas_pend_fifo[0][47]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cas_pend_fifo[1][47]_i_1__0 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr_reg_n_0_[1] ),
        .O(\cas_pend_fifo[1][47]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cas_pend_fifo[2][47]_i_1__0 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .O(\cas_pend_fifo[2][47]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \cas_pend_fifo[3][47]_i_1__0 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .O(\cas_pend_fifo[3][47]_i_1__0_n_0 ));
  FDRE \cas_pend_fifo_reg[0][0] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg_n_0_[0][0] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][11] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][12] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][13] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][14] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][15] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][16] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][17] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][1] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg_n_0_[0][1] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][24] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[0][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][25] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[0][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][26] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[0][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][27] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[0][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][28] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[0][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][29] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[0][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][2] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[0][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][30] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[0][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][31] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[0][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][32] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[0][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][33] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[0][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][34] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[0][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][35] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[0][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][36] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[0][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][37] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[0][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][38] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[0][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][39] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[0][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][40] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[0][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][44] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][45] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][46] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][47] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[0][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][47] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][0] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg_n_0_[1][0] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][11] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][12] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][13] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][14] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][15] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][16] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][17] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][1] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg_n_0_[1][1] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][24] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[1][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][25] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[1][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][26] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[1][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][27] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[1][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][28] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[1][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][29] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[1][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][2] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[1][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][30] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[1][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][31] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[1][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][32] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[1][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][33] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[1][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][34] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[1][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][35] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[1][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][36] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[1][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][37] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[1][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][38] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[1][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][39] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[1][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][40] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[1][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][44] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][45] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][46] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][47] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[1][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][47] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][0] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg_n_0_[2][0] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][11] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][12] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][13] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][14] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][15] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][16] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][17] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][1] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg_n_0_[2][1] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][24] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[2][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][25] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[2][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][26] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[2][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][27] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[2][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][28] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[2][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][29] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[2][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][2] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[2][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][30] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[2][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][31] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[2][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][32] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[2][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][33] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[2][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][34] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[2][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][35] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[2][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][36] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[2][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][37] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[2][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][38] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[2][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][39] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[2][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][40] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[2][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][44] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][45] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][46] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][47] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[2][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][47] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][0] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg_n_0_[3][0] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][11] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][12] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][13] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][14] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][15] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][16] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][17] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][1] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg_n_0_[3][1] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][24] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[3][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][25] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[3][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][26] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[3][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][27] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[3][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][28] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[3][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][29] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[3][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][2] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[3][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][30] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[3][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][31] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[3][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][32] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[3][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][33] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[3][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][34] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[3][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][35] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[3][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][36] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[3][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][37] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[3][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][38] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[3][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][39] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[3][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][40] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[3][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][44] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][45] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][46] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][47] 
       (.C(rst_r1_reg_0),
        .CE(\cas_pend_fifo[3][47]_i_1__0_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][47] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2689" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    cmdAP_i_1__1
       (.I0(\txn_fifo_output_reg_n_0_[47] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(cmdAP_i_2__1_n_0),
        .O(cmdAP_i_1__1_n_0));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    cmdAP_i_2__1
       (.I0(\cas_pend_fifo_reg_n_0_[2][47] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][47] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][47] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_pend_fifo_reg_n_0_[0][47] ),
        .O(cmdAP_i_2__1_n_0));
  FDRE cmdAP_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(cmdAP_i_1__1_n_0),
        .Q(cmdAP),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h00000001)) 
    \cmdBankP[1]_i_1__2 
       (.I0(grSt[2]),
        .I1(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I2(\cmdBankP[1]_i_2__0_n_0 ),
        .I3(\cmdBankP[1]_i_3_n_0 ),
        .I4(\issue_cas3_inferred__0/i__carry_n_2 ),
        .O(\cmdBankP[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFAEFFFFFFFF)) 
    \cmdBankP[1]_i_2__0 
       (.I0(\cmdBankP[1]_i_4__0_n_0 ),
        .I1(txn_fifo_empty_reg_n_0),
        .I2(txn_fifo_empty_i_2__0_n_0),
        .I3(\FSM_sequential_grSt[1]_i_4__0_n_0 ),
        .I4(\cmdBankP[1]_i_5__0_n_0 ),
        .I5(\cmdBankP[1]_i_6__0_n_0 ),
        .O(\cmdBankP[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0F3300550F33FF55)) 
    \cmdBankP[1]_i_3 
       (.I0(\pageInfo_reg_n_0_[0][0][0][0] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][0] ),
        .I2(\pageInfo_reg_n_0_[0][0][3][0] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][1][0] ),
        .O(\cmdBankP[1]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h82000082)) 
    \cmdBankP[1]_i_4__0 
       (.I0(\cas_fifo_valid_reg_n_0_[0] ),
        .I1(Q[0]),
        .I2(\cas_pend_fifo_reg_n_0_[0][0] ),
        .I3(Q[1]),
        .I4(\cas_pend_fifo_reg_n_0_[0][1] ),
        .O(\cmdBankP[1]_i_4__0_n_0 ));
  LUT5 #(
    .INIT(32'h82000082)) 
    \cmdBankP[1]_i_5__0 
       (.I0(\cas_fifo_valid_reg_n_0_[3] ),
        .I1(Q[0]),
        .I2(\cas_pend_fifo_reg_n_0_[3][0] ),
        .I3(Q[1]),
        .I4(\cas_pend_fifo_reg_n_0_[3][1] ),
        .O(\cmdBankP[1]_i_5__0_n_0 ));
  LUT5 #(
    .INIT(32'h6FF6FFFF)) 
    \cmdBankP[1]_i_6__0 
       (.I0(Q[0]),
        .I1(\cas_pend_fifo_reg_n_0_[2][0] ),
        .I2(Q[1]),
        .I3(\cas_pend_fifo_reg_n_0_[2][1] ),
        .I4(\cas_fifo_valid_reg_n_0_[2] ),
        .O(\cmdBankP[1]_i_6__0_n_0 ));
  FDRE \cmdBankP_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(\cmdBankP[1]_i_1__2_n_0 ),
        .D(Q[0]),
        .Q(\cmdBankP_reg[1]_0 [0]),
        .R(rst_r1));
  FDRE \cmdBankP_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(\cmdBankP[1]_i_1__2_n_0 ),
        .D(Q[1]),
        .Q(\cmdBankP_reg[1]_0 [1]),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    \cmdBuf[0]_i_1__1 
       (.I0(\cas_dbuf_fifo_reg_n_0_[2][0] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[1][0] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[0][0] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[3][0] ),
        .O(\cmdBuf[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0AACCFFF0AACC00)) 
    \cmdBuf[1]_i_1__1 
       (.I0(\cas_dbuf_fifo_reg_n_0_[1][1] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[2][1] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[3][1] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[0][1] ),
        .O(\cmdBuf[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmdBuf[2]_i_1__1 
       (.I0(\cas_dbuf_fifo_reg_n_0_[2][2] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[3][2] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[1][2] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[0][2] ),
        .O(\cmdBuf[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFAAF0CC00AAF0CC)) 
    \cmdBuf[3]_i_1__1 
       (.I0(\cas_dbuf_fifo_reg_n_0_[2][3] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[0][3] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[1][3] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[3][3] ),
        .O(\cmdBuf[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFAACCF000AACCF0)) 
    \cmdBuf[4]_i_1__1 
       (.I0(\cas_dbuf_fifo_reg_n_0_[1][4] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[2][4] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[0][4] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[3][4] ),
        .O(\cmdBuf[4]_i_1__1_n_0 ));
  FDRE \cmdBuf_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmdBuf[0]_i_1__1_n_0 ),
        .Q(cmdBuf[0]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmdBuf[1]_i_1__1_n_0 ),
        .Q(cmdBuf[1]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmdBuf[2]_i_1__1_n_0 ),
        .Q(cmdBuf[2]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmdBuf[3]_i_1__1_n_0 ),
        .Q(cmdBuf[3]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[4] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmdBuf[4]_i_1__1_n_0 ),
        .Q(cmdBuf[4]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2690" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[3]_i_1__1 
       (.I0(\txn_fifo_output_reg_n_0_[11] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[3]_i_2__1_n_0 ),
        .O(\cmdCol[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[3]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][11] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][11] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][11] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][11] ),
        .O(\cmdCol[3]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2690" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[4]_i_1__1 
       (.I0(\txn_fifo_output_reg_n_0_[12] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[4]_i_2__1_n_0 ),
        .O(\cmdCol[4]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[4]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][12] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][12] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][12] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][12] ),
        .O(\cmdCol[4]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2691" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[5]_i_1__1 
       (.I0(\txn_fifo_output_reg_n_0_[13] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[5]_i_2__1_n_0 ),
        .O(\cmdCol[5]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[5]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][13] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][13] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][13] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][13] ),
        .O(\cmdCol[5]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2691" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[6]_i_1__1 
       (.I0(\txn_fifo_output_reg_n_0_[14] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[6]_i_2__1_n_0 ),
        .O(\cmdCol[6]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[6]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][14] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][14] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][14] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][14] ),
        .O(\cmdCol[6]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2692" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[7]_i_1__1 
       (.I0(\txn_fifo_output_reg_n_0_[15] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[7]_i_2__1_n_0 ),
        .O(\cmdCol[7]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[7]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][15] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][15] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][15] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][15] ),
        .O(\cmdCol[7]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2692" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[8]_i_1__1 
       (.I0(\txn_fifo_output_reg_n_0_[16] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[8]_i_2__1_n_0 ),
        .O(\cmdCol[8]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[8]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][16] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][16] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][16] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][16] ),
        .O(\cmdCol[8]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2693" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[9]_i_1__1 
       (.I0(\txn_fifo_output_reg_n_0_[17] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[9]_i_2__1_n_0 ),
        .O(\cmdCol[9]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[9]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][17] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][17] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][17] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][17] ),
        .O(\cmdCol[9]_i_2__1_n_0 ));
  FDRE \cmdCol_reg[3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmdCol[3]_i_1__1_n_0 ),
        .Q(\cmdCol_reg[9]_0 [0]),
        .R(rst_r1));
  FDRE \cmdCol_reg[4] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmdCol[4]_i_1__1_n_0 ),
        .Q(\cmdCol_reg[9]_0 [1]),
        .R(rst_r1));
  FDRE \cmdCol_reg[5] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmdCol[5]_i_1__1_n_0 ),
        .Q(\cmdCol_reg[9]_0 [2]),
        .R(rst_r1));
  FDRE \cmdCol_reg[6] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmdCol[6]_i_1__1_n_0 ),
        .Q(\cmdCol_reg[9]_0 [3]),
        .R(rst_r1));
  FDRE \cmdCol_reg[7] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmdCol[7]_i_1__1_n_0 ),
        .Q(\cmdCol_reg[9]_0 [4]),
        .R(rst_r1));
  FDRE \cmdCol_reg[8] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmdCol[8]_i_1__1_n_0 ),
        .Q(\cmdCol_reg[9]_0 [5]),
        .R(rst_r1));
  FDRE \cmdCol_reg[9] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmdCol[9]_i_1__1_n_0 ),
        .Q(\cmdCol_reg[9]_0 [6]),
        .R(rst_r1));
  FDRE \cmdGroupP_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(\cmdBankP[1]_i_1__2_n_0 ),
        .D(Q[2]),
        .Q(cmdGroupP),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h70777070)) 
    cmdRmw_i_1__1
       (.I0(\cas_fifo_rptr_reg[0]_0 ),
        .I1(tranSentC),
        .I2(cmdRmw_reg_0),
        .I3(\FSM_sequential_gr_cas_state[2]_i_6__1_n_0 ),
        .I4(\FSM_sequential_gr_cas_state[2]_i_3_n_0 ),
        .O(cmdRmw_i_1__1_n_0));
  FDRE cmdRmw_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(cmdRmw_i_1__1_n_0),
        .Q(cmdRmw_reg_0),
        .R(rst_r1));
  LUT3 #(
    .INIT(8'hE2)) 
    \cmd_bank_cas[0]_i_1__1 
       (.I0(\cmd_bank_cas[0]_i_2__1_n_0 ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(Q[0]),
        .O(\cmd_bank_cas[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hAAFFCCF0AA00CCF0)) 
    \cmd_bank_cas[0]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[3][0] ),
        .I1(\cas_pend_fifo_reg_n_0_[2][0] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][0] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][0] ),
        .O(\cmd_bank_cas[0]_i_2__1_n_0 ));
  LUT3 #(
    .INIT(8'hC5)) 
    \cmd_bank_cas[1]_i_1__1 
       (.I0(\cmd_bank_cas[1]_i_2__1_n_0 ),
        .I1(Q[1]),
        .I2(cas_fifo_empty_reg_n_0),
        .O(\cmd_bank_cas[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h3300550F33FF550F)) 
    \cmd_bank_cas[1]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][1] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][1] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][1] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][1] ),
        .O(\cmd_bank_cas[1]_i_2__1_n_0 ));
  FDRE \cmd_bank_cas_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_bank_cas[0]_i_1__1_n_0 ),
        .Q(\cmd_bank_cas_reg[1]_0 [0]),
        .R(rst_r1));
  FDRE \cmd_bank_cas_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_bank_cas[1]_i_1__1_n_0 ),
        .Q(\cmd_bank_cas_reg[1]_0 [1]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2689" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_group_cas[0]_i_1__1 
       (.I0(Q[2]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_group_cas[0]_i_2__1_n_0 ),
        .O(\cmd_group_cas[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_group_cas[0]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][2] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][2] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][2] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][2] ),
        .O(\cmd_group_cas[0]_i_2__1_n_0 ));
  FDRE \cmd_group_cas_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_group_cas[0]_i_1__1_n_0 ),
        .Q(cmd_group_cas),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2693" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[0]_i_1__1 
       (.I0(Q[3]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[0]_i_2__1_n_0 ),
        .O(\cmd_row_cas[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[0]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][24] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][24] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][24] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][24] ),
        .O(\cmd_row_cas[0]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2698" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[10]_i_1__1 
       (.I0(Q[13]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[10]_i_2__1_n_0 ),
        .O(\cmd_row_cas[10]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[10]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][34] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][34] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][34] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][34] ),
        .O(\cmd_row_cas[10]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2699" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[11]_i_1__1 
       (.I0(Q[14]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[11]_i_2__1_n_0 ),
        .O(\cmd_row_cas[11]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmd_row_cas[11]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][35] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][35] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][35] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_pend_fifo_reg_n_0_[0][35] ),
        .O(\cmd_row_cas[11]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2699" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[12]_i_1__1 
       (.I0(Q[15]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[12]_i_2__1_n_0 ),
        .O(\cmd_row_cas[12]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[12]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][36] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][36] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][36] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][36] ),
        .O(\cmd_row_cas[12]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2700" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[13]_i_1__1 
       (.I0(Q[16]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[13]_i_2__1_n_0 ),
        .O(\cmd_row_cas[13]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[13]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][37] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][37] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][37] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][37] ),
        .O(\cmd_row_cas[13]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2700" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[14]_i_1__1 
       (.I0(Q[17]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[14]_i_2__1_n_0 ),
        .O(\cmd_row_cas[14]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[14]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][38] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][38] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][38] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][38] ),
        .O(\cmd_row_cas[14]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2701" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[15]_i_1__1 
       (.I0(Q[18]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[15]_i_2__1_n_0 ),
        .O(\cmd_row_cas[15]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[15]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][39] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][39] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][39] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][39] ),
        .O(\cmd_row_cas[15]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2701" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[16]_i_1__1 
       (.I0(Q[19]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[16]_i_2__1_n_0 ),
        .O(\cmd_row_cas[16]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[16]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][40] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][40] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][40] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][40] ),
        .O(\cmd_row_cas[16]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2694" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[1]_i_1__1 
       (.I0(Q[4]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[1]_i_2__1_n_0 ),
        .O(\cmd_row_cas[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[1]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][25] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][25] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][25] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][25] ),
        .O(\cmd_row_cas[1]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2694" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[2]_i_1__1 
       (.I0(Q[5]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[2]_i_2__1_n_0 ),
        .O(\cmd_row_cas[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[2]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][26] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][26] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][26] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][26] ),
        .O(\cmd_row_cas[2]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2695" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[3]_i_1__1 
       (.I0(Q[6]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[3]_i_2__1_n_0 ),
        .O(\cmd_row_cas[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmd_row_cas[3]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][27] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][27] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][27] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_pend_fifo_reg_n_0_[0][27] ),
        .O(\cmd_row_cas[3]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2695" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[4]_i_1__1 
       (.I0(Q[7]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[4]_i_2__1_n_0 ),
        .O(\cmd_row_cas[4]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[4]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][28] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][28] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][28] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][28] ),
        .O(\cmd_row_cas[4]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2696" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[5]_i_1__1 
       (.I0(Q[8]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[5]_i_2__1_n_0 ),
        .O(\cmd_row_cas[5]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[5]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][29] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][29] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][29] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][29] ),
        .O(\cmd_row_cas[5]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2696" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[6]_i_1__1 
       (.I0(Q[9]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[6]_i_2__1_n_0 ),
        .O(\cmd_row_cas[6]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[6]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][30] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][30] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][30] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][30] ),
        .O(\cmd_row_cas[6]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2697" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[7]_i_1__1 
       (.I0(Q[10]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[7]_i_2__1_n_0 ),
        .O(\cmd_row_cas[7]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[7]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][31] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][31] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][31] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][31] ),
        .O(\cmd_row_cas[7]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2697" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[8]_i_1__1 
       (.I0(Q[11]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[8]_i_2__1_n_0 ),
        .O(\cmd_row_cas[8]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[8]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][32] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][32] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][32] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][32] ),
        .O(\cmd_row_cas[8]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2698" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[9]_i_1__1 
       (.I0(Q[12]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[9]_i_2__1_n_0 ),
        .O(\cmd_row_cas[9]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[9]_i_2__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][33] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][33] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][33] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][33] ),
        .O(\cmd_row_cas[9]_i_2__1_n_0 ));
  FDRE \cmd_row_cas_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[0]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[10] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[10]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[11] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[11]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[12] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[12]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[12] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[13] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[13]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[13] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[14] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[14]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[14] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[15] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[15]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[15] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[16] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[16]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[1]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[2]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[3]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[3] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[4] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[4]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[5] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[5]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[6] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[6]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[6] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[7] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[7]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[7] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[8] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[8]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[8] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[9] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\cmd_row_cas[9]_i_1__1_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[9] ),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    i__carry_i_10__1
       (.I0(\pageInfo_reg_n_0_[0][0][1][15] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][15] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][15] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][3][15] ),
        .O(i__carry_i_10__1_n_0));
  LUT6 #(
    .INIT(64'hAACCFFF0AACC00F0)) 
    i__carry_i_11__1
       (.I0(\pageInfo_reg_n_0_[0][0][3][14] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][14] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][14] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][1][14] ),
        .O(i__carry_i_11__1_n_0));
  LUT6 #(
    .INIT(64'h33000F5533FF0F55)) 
    i__carry_i_12__1
       (.I0(\pageInfo_reg_n_0_[0][0][0][13] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][13] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][13] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][13] ),
        .O(i__carry_i_12__1_n_0));
  LUT6 #(
    .INIT(64'hCCFFF0AACC00F0AA)) 
    i__carry_i_13__1
       (.I0(\pageInfo_reg_n_0_[0][0][0][11] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][11] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][11] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][11] ),
        .O(i__carry_i_13__1_n_0));
  LUT6 #(
    .INIT(64'hCCFFF0AACC00F0AA)) 
    i__carry_i_14__1
       (.I0(\pageInfo_reg_n_0_[0][0][0][12] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][12] ),
        .I2(\pageInfo_reg_n_0_[0][0][2][12] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\pageInfo_reg_n_0_[0][0][1][12] ),
        .O(i__carry_i_14__1_n_0));
  LUT6 #(
    .INIT(64'h5500330F55FF330F)) 
    i__carry_i_15__1
       (.I0(\pageInfo_reg_n_0_[0][0][3][9] ),
        .I1(\pageInfo_reg_n_0_[0][0][1][9] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][9] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][9] ),
        .O(i__carry_i_15__1_n_0));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    i__carry_i_16__1
       (.I0(\pageInfo_reg_n_0_[0][0][1][8] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][8] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][8] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][3][8] ),
        .O(i__carry_i_16__1_n_0));
  LUT6 #(
    .INIT(64'hCCFFF0AACC00F0AA)) 
    i__carry_i_17__1
       (.I0(\pageInfo_reg_n_0_[0][0][0][10] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][10] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][10] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][10] ),
        .O(i__carry_i_17__1_n_0));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    i__carry_i_18__1
       (.I0(\pageInfo_reg_n_0_[0][0][1][6] ),
        .I1(\pageInfo_reg_n_0_[0][0][0][6] ),
        .I2(\pageInfo_reg_n_0_[0][0][2][6] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\pageInfo_reg_n_0_[0][0][3][6] ),
        .O(i__carry_i_18__1_n_0));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    i__carry_i_19__1
       (.I0(\pageInfo_reg_n_0_[0][0][1][5] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][5] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][5] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][5] ),
        .O(i__carry_i_19__1_n_0));
  LUT4 #(
    .INIT(16'h6006)) 
    i__carry_i_1__1
       (.I0(i__carry_i_7__1_n_0),
        .I1(Q[18]),
        .I2(i__carry_i_8__1_n_0),
        .I3(Q[19]),
        .O(i__carry_i_1__1_n_0));
  LUT6 #(
    .INIT(64'hCCFFF0AACC00F0AA)) 
    i__carry_i_20__1
       (.I0(\pageInfo_reg_n_0_[0][0][0][7] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][7] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][7] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][7] ),
        .O(i__carry_i_20__1_n_0));
  LUT6 #(
    .INIT(64'h5500330F55FF330F)) 
    i__carry_i_21__1
       (.I0(\pageInfo_reg_n_0_[0][0][3][2] ),
        .I1(\pageInfo_reg_n_0_[0][0][1][2] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][2] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][2] ),
        .O(i__carry_i_21__1_n_0));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    i__carry_i_22__1
       (.I0(\pageInfo_reg_n_0_[0][0][1][4] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][4] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][4] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][4] ),
        .O(i__carry_i_22__1_n_0));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    i__carry_i_23__1
       (.I0(\pageInfo_reg_n_0_[0][0][1][3] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][3] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][3] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][3][3] ),
        .O(i__carry_i_23__1_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_2__1
       (.I0(i__carry_i_9__1_n_0),
        .I1(Q[17]),
        .I2(Q[16]),
        .I3(i__carry_i_10__1_n_0),
        .I4(Q[15]),
        .I5(i__carry_i_11__1_n_0),
        .O(i__carry_i_2__1_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_3__1
       (.I0(i__carry_i_12__1_n_0),
        .I1(Q[14]),
        .I2(Q[12]),
        .I3(i__carry_i_13__1_n_0),
        .I4(Q[13]),
        .I5(i__carry_i_14__1_n_0),
        .O(i__carry_i_3__1_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_4__1
       (.I0(i__carry_i_15__1_n_0),
        .I1(Q[10]),
        .I2(Q[9]),
        .I3(i__carry_i_16__1_n_0),
        .I4(Q[11]),
        .I5(i__carry_i_17__1_n_0),
        .O(i__carry_i_4__1_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_5__1
       (.I0(i__carry_i_18__1_n_0),
        .I1(Q[7]),
        .I2(Q[6]),
        .I3(i__carry_i_19__1_n_0),
        .I4(Q[8]),
        .I5(i__carry_i_20__1_n_0),
        .O(i__carry_i_5__1_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_6__1
       (.I0(i__carry_i_21__1_n_0),
        .I1(Q[3]),
        .I2(Q[5]),
        .I3(i__carry_i_22__1_n_0),
        .I4(Q[4]),
        .I5(i__carry_i_23__1_n_0),
        .O(i__carry_i_6__1_n_0));
  LUT6 #(
    .INIT(64'h33000F5533FF0F55)) 
    i__carry_i_7__1
       (.I0(\pageInfo_reg_n_0_[0][0][0][17] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][17] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][17] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][17] ),
        .O(i__carry_i_7__1_n_0));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    i__carry_i_8__1
       (.I0(\pageInfo_reg_n_0_[0][0][1][18] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][18] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][18] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][18] ),
        .O(i__carry_i_8__1_n_0));
  LUT6 #(
    .INIT(64'h55000F3355FF0F33)) 
    i__carry_i_9__1
       (.I0(\pageInfo_reg_n_0_[0][0][3][16] ),
        .I1(\pageInfo_reg_n_0_[0][0][0][16] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][16] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][16] ),
        .O(i__carry_i_9__1_n_0));
  CARRY8 \issue_cas3_inferred__0/i__carry 
       (.CI(1'b1),
        .CI_TOP(1'b0),
        .CO({\NLW_issue_cas3_inferred__0/i__carry_CO_UNCONNECTED [7:6],\issue_cas3_inferred__0/i__carry_n_2 ,\issue_cas3_inferred__0/i__carry_n_3 ,\issue_cas3_inferred__0/i__carry_n_4 ,\issue_cas3_inferred__0/i__carry_n_5 ,\issue_cas3_inferred__0/i__carry_n_6 ,\issue_cas3_inferred__0/i__carry_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O(\NLW_issue_cas3_inferred__0/i__carry_O_UNCONNECTED [7:0]),
        .S({1'b0,1'b0,i__carry_i_1__1_n_0,i__carry_i_2__1_n_0,i__carry_i_3__1_n_0,i__carry_i_4__1_n_0,i__carry_i_5__1_n_0,i__carry_i_6__1_n_0}));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \pageInfo[0][0][0][0]_i_1__1 
       (.I0(\pageInfo[0][0][0][0]_i_2__1_n_0 ),
        .I1(grSt[2]),
        .I2(grSt[0]),
        .I3(grSt[1]),
        .I4(\pageInfo[0][0][0][0]_i_3__1_n_0 ),
        .I5(sel0__46),
        .O(\pageInfo[0][0][0][0]_i_1__1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][0][0]_i_2__1 
       (.I0(rst_r1),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .O(\pageInfo[0][0][0][0]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2702" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \pageInfo[0][0][0][0]_i_3__1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\pageInfo[0][0][0][0]_i_3__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][0][10]_i_1__1 
       (.I0(Q[11]),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[8] ),
        .O(\pageInfo[0][0][0][10]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][0][11]_i_1__1 
       (.I0(Q[12]),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[9] ),
        .O(\pageInfo[0][0][0][11]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][0][12]_i_1__1 
       (.I0(Q[13]),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[10] ),
        .O(\pageInfo[0][0][0][12]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][13]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[11] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][0][13]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][14]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[12] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][0][14]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][15]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[13] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][0][15]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][0][16]_i_1__1 
       (.I0(Q[17]),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[14] ),
        .O(\pageInfo[0][0][0][16]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][17]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[15] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][0][17]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][0][18]_i_1__1 
       (.I0(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I1(sel0__46),
        .I2(\pageInfo[0][0][3][18]_i_3__1_n_0 ),
        .I3(\trcd_cntr[0][0][0][2]_i_2__1_n_0 ),
        .O(\pageInfo[0][0][0][18]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][0][18]_i_2__1 
       (.I0(Q[19]),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[16] ),
        .O(\pageInfo[0][0][0][18]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][0][1]_i_1__1 
       (.I0(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][0][1]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][0][2]_i_1__1 
       (.I0(Q[3]),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[0] ),
        .O(\pageInfo[0][0][0][2]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][3]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[1] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][0][3]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][4]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[2] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I3(Q[5]),
        .O(\pageInfo[0][0][0][4]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][0][5]_i_1__1 
       (.I0(Q[6]),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[3] ),
        .O(\pageInfo[0][0][0][5]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][0][6]_i_1__1 
       (.I0(Q[7]),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[4] ),
        .O(\pageInfo[0][0][0][6]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][0][7]_i_1__1 
       (.I0(Q[8]),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[5] ),
        .O(\pageInfo[0][0][0][7]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][0][8]_i_1__1 
       (.I0(Q[9]),
        .I1(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[6] ),
        .O(\pageInfo[0][0][0][8]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][9]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[7] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__1_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][0][9]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \pageInfo[0][0][1][0]_i_1__1 
       (.I0(\pageInfo[0][0][1][0]_i_2__1_n_0 ),
        .I1(grSt[2]),
        .I2(grSt[0]),
        .I3(grSt[1]),
        .I4(\pageInfo[0][0][1][0]_i_3__1_n_0 ),
        .I5(sel0__42),
        .O(\pageInfo[0][0][1][0]_i_1__1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][1][0]_i_2__1 
       (.I0(rst_r1),
        .I1(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .O(\pageInfo[0][0][1][0]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2703" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \pageInfo[0][0][1][0]_i_3__1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\pageInfo[0][0][1][0]_i_3__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][10]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[8] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[11]),
        .O(\pageInfo[0][0][1][10]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][11]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[9] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][1][11]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][12]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[10] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][1][12]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][13]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[11] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][1][13]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][14]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[12] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][1][14]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][15]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[13] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][1][15]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][16]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[14] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[17]),
        .O(\pageInfo[0][0][1][16]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][17]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[15] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][1][17]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][1][18]_i_1__1 
       (.I0(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I1(sel0__42),
        .I2(\pageInfo[0][0][3][18]_i_3__1_n_0 ),
        .I3(\trcd_cntr[0][0][1][2]_i_2__1_n_0 ),
        .O(\pageInfo[0][0][1][18]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][18]_i_2__1 
       (.I0(\cmd_row_cas_reg_n_0_[16] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][1][18]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][1][1]_i_1__1 
       (.I0(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][1][1]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][2]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[0] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[3]),
        .O(\pageInfo[0][0][1][2]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][3]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[1] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][1][3]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][4]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[2] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[5]),
        .O(\pageInfo[0][0][1][4]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][5]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[3] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[6]),
        .O(\pageInfo[0][0][1][5]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][6]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[4] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[7]),
        .O(\pageInfo[0][0][1][6]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][7]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[5] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[8]),
        .O(\pageInfo[0][0][1][7]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][8]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[6] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][1][8]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][9]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[7] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][1]_i_3_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][1][9]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \pageInfo[0][0][2][0]_i_1__1 
       (.I0(\pageInfo[0][0][2][0]_i_2__0_n_0 ),
        .I1(grSt[2]),
        .I2(grSt[0]),
        .I3(grSt[1]),
        .I4(\pageInfo[0][0][2][0]_i_3__0_n_0 ),
        .I5(sel0__38),
        .O(\pageInfo[0][0][2][0]_i_1__1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][2][0]_i_2__0 
       (.I0(rst_r1),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .O(\pageInfo[0][0][2][0]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2703" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \pageInfo[0][0][2][0]_i_3__0 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\pageInfo[0][0][2][0]_i_3__0_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][10]_i_1__1 
       (.I0(Q[11]),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[8] ),
        .O(\pageInfo[0][0][2][10]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][11]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[9] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][2][11]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][12]_i_1__1 
       (.I0(Q[13]),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[10] ),
        .O(\pageInfo[0][0][2][12]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][13]_i_1__1 
       (.I0(Q[14]),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[11] ),
        .O(\pageInfo[0][0][2][13]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][14]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[12] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][2][14]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][15]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[13] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][2][15]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][16]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[14] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I3(Q[17]),
        .O(\pageInfo[0][0][2][16]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][17]_i_1__1 
       (.I0(Q[18]),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[15] ),
        .O(\pageInfo[0][0][2][17]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][2][18]_i_1__1 
       (.I0(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I1(sel0__38),
        .I2(\pageInfo[0][0][3][18]_i_3__1_n_0 ),
        .I3(\trcd_cntr[0][0][2][2]_i_2__1_n_0 ),
        .O(\pageInfo[0][0][2][18]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][18]_i_2__1 
       (.I0(Q[19]),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[16] ),
        .O(\pageInfo[0][0][2][18]_i_2__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][2][1]_i_1__1 
       (.I0(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][2][1]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][2]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[0] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I3(Q[3]),
        .O(\pageInfo[0][0][2][2]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][3]_i_1__1 
       (.I0(Q[4]),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[1] ),
        .O(\pageInfo[0][0][2][3]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][4]_i_1__1 
       (.I0(Q[5]),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[2] ),
        .O(\pageInfo[0][0][2][4]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][5]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[3] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I3(Q[6]),
        .O(\pageInfo[0][0][2][5]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][6]_i_1__1 
       (.I0(Q[7]),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[4] ),
        .O(\pageInfo[0][0][2][6]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][7]_i_1__1 
       (.I0(Q[8]),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[5] ),
        .O(\pageInfo[0][0][2][7]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][8]_i_1__1 
       (.I0(Q[9]),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[6] ),
        .O(\pageInfo[0][0][2][8]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][9]_i_1__1 
       (.I0(Q[10]),
        .I1(\ap_cntr[0][0][2][4]_i_3__0_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[7] ),
        .O(\pageInfo[0][0][2][9]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \pageInfo[0][0][3][0]_i_1__1 
       (.I0(\pageInfo[0][0][3][0]_i_2__1_n_0 ),
        .I1(grSt[2]),
        .I2(grSt[0]),
        .I3(grSt[1]),
        .I4(\trp_cntr[1]_i_2__1_n_0 ),
        .I5(sel0__34),
        .O(\pageInfo[0][0][3][0]_i_1__1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][3][0]_i_2__1 
       (.I0(rst_r1),
        .I1(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .O(\pageInfo[0][0][3][0]_i_2__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][10]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[8] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I3(Q[11]),
        .O(\pageInfo[0][0][3][10]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][11]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[9] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][3][11]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][12]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[10] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][3][12]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][13]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[11] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][3][13]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][14]_i_1__1 
       (.I0(Q[15]),
        .I1(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[12] ),
        .O(\pageInfo[0][0][3][14]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][15]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[13] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][3][15]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][16]_i_1__1 
       (.I0(Q[17]),
        .I1(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[14] ),
        .O(\pageInfo[0][0][3][16]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][17]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[15] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][3][17]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][3][18]_i_1__1 
       (.I0(\pageInfo[0][0][3][18]_i_3__1_n_0 ),
        .I1(sel0__34),
        .I2(\trcd_cntr[0][0][3][2]_i_2__1_n_0 ),
        .I3(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .O(\pageInfo[0][0][3][18]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][18]_i_2__1 
       (.I0(\cmd_row_cas_reg_n_0_[16] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][3][18]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAEAAAAAAAAAAA)) 
    \pageInfo[0][0][3][18]_i_3__1 
       (.I0(rst_r1),
        .I1(refOK_reg_0),
        .I2(grSt[2]),
        .I3(grSt[1]),
        .I4(grSt[0]),
        .I5(refReq),
        .O(\pageInfo[0][0][3][18]_i_3__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][3][1]_i_1__1 
       (.I0(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][3][1]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][2]_i_1__1 
       (.I0(Q[3]),
        .I1(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[0] ),
        .O(\pageInfo[0][0][3][2]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][3]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[1] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][3][3]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][4]_i_1__1 
       (.I0(Q[5]),
        .I1(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[2] ),
        .O(\pageInfo[0][0][3][4]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][5]_i_1__1 
       (.I0(Q[6]),
        .I1(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[3] ),
        .O(\pageInfo[0][0][3][5]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][6]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[4] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I3(Q[7]),
        .O(\pageInfo[0][0][3][6]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][7]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[5] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I3(Q[8]),
        .O(\pageInfo[0][0][3][7]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][8]_i_1__1 
       (.I0(\cmd_row_cas_reg_n_0_[6] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][3][8]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][9]_i_1__1 
       (.I0(Q[10]),
        .I1(\ap_cntr[0][0][3][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[7] ),
        .O(\pageInfo[0][0][3][9]_i_1__1_n_0 ));
  FDRE \pageInfo_reg[0][0][0][0] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][0]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][0] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][10] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][10]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][10] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][11] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][11]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][11] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][12] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][12]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][12] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][13] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][13]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][13] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][14] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][14]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][14] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][15] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][15]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][15] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][16] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][16]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][16] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][17] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][17]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][17] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][18] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][18]_i_2__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][18] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][1] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][1]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][1] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][2] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][2]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][2] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][3] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][3]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][3] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][4] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][4]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][4] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][5] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][5]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][5] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][6] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][6]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][6] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][7] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][7]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][7] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][8] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][8]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][8] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][9] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][0][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][0][9]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][9] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][0] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][0]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][0] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][10] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][10]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][10] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][11] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][11]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][11] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][12] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][12]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][12] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][13] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][13]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][13] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][14] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][14]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][14] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][15] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][15]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][15] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][16] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][16]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][16] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][17] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][17]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][17] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][18] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][18]_i_2__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][18] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][1] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][1]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][1] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][2] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][2]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][2] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][3] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][3]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][3] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][4] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][4]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][4] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][5] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][5]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][5] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][6] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][6]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][6] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][7] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][7]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][7] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][8] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][8]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][8] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][9] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][1][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][1][9]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][9] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][0] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][0]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][0] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][10] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][10]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][10] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][11] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][11]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][11] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][12] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][12]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][12] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][13] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][13]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][13] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][14] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][14]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][14] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][15] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][15]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][15] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][16] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][16]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][16] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][17] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][17]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][17] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][18] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][18]_i_2__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][18] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][1] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][1]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][1] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][2] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][2]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][2] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][3] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][3]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][3] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][4] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][4]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][4] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][5] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][5]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][5] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][6] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][6]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][6] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][7] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][7]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][7] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][8] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][8]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][8] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][9] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][2][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][2][9]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][9] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][0] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][0]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][0] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][10] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][10]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][10] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][11] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][11]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][11] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][12] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][12]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][12] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][13] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][13]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][13] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][14] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][14]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][14] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][15] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][15]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][15] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][16] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][16]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][16] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][17] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][17]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][17] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][18] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][18]_i_2__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][18] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][1] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][1]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][1] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][2] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][2]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][2] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][3] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][3]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][3] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][4] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][4]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][4] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][5] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][5]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][5] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][6] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][6]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][6] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][7] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][7]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][7] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][8] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][8]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][8] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][9] 
       (.C(rst_r1_reg_0),
        .CE(\pageInfo[0][0][3][18]_i_1__1_n_0 ),
        .D(\pageInfo[0][0][3][9]_i_1__1_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][9] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00F2)) 
    preReqR_i_1__0
       (.I0(\FSM_sequential_grSt[2]_i_5__2_n_0 ),
        .I1(preReqR_i_2__0_n_0),
        .I2(preReqR_reg_0),
        .I3(preReqR_reg_1),
        .O(preReqR_i_1__0_n_0));
  LUT3 #(
    .INIT(8'hFE)) 
    preReqR_i_2__0
       (.I0(\cmdBankP[1]_i_2__0_n_0 ),
        .I1(\cmdBankP[1]_i_3_n_0 ),
        .I2(\issue_cas3_inferred__0/i__carry_n_2 ),
        .O(preReqR_i_2__0_n_0));
  FDRE preReqR_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(preReqR_i_1__0_n_0),
        .Q(preReqR_reg_0),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h2A3F2A2A)) 
    rdReqR_i_1__1
       (.I0(rdReqR_reg_0),
        .I1(\cas_fifo_rptr_reg[0]_0 ),
        .I2(tranSentC),
        .I3(rdReqR_i_2__1_n_0),
        .I4(\FSM_sequential_gr_cas_state[2]_i_3_n_0 ),
        .O(rdReqR_i_1__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2624" *) 
  LUT5 #(
    .INIT(32'hCFFFCAFA)) 
    rdReqR_i_2__1
       (.I0(wrReqR_i_8_n_0),
        .I1(\txn_fifo_output_reg_n_0_[46] ),
        .I2(cas_fifo_empty_reg_n_0),
        .I3(\txn_fifo_output_reg_n_0_[44] ),
        .I4(wrReqR_i_6__0_n_0),
        .O(rdReqR_i_2__1_n_0));
  FDRE rdReqR_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(rdReqR_i_1__1_n_0),
        .Q(rdReqR_reg_0),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2637" *) 
  LUT5 #(
    .INIT(32'h08000000)) 
    refOK_i_1__1
       (.I0(grSt[2]),
        .I1(grSt[1]),
        .I2(grSt[0]),
        .I3(cas_fifo_empty_reg_n_0),
        .I4(ref_req_dly4),
        .O(refOK_i_1__1_n_0));
  FDRE refOK_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(refOK_i_1__1_n_0),
        .Q(refOK_reg_0),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE rst_r1_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(SR),
        .Q(rst_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2650" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][0][0]_i_1__1 
       (.I0(\trcd_cntr[0][0][0][2]_i_2__1_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .O(\tras_cntr_rb[0][0][0][0]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][0][1]_i_1__1 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .I3(\trcd_cntr[0][0][0][2]_i_2__1_n_0 ),
        .O(\tras_cntr_rb[0][0][0][1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2650" *) 
  LUT4 #(
    .INIT(16'hFEAA)) 
    \tras_cntr_rb[0][0][0][2]_i_1__1 
       (.I0(\trcd_cntr[0][0][0][2]_i_2__1_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .O(\tras_cntr_rb[0][0][0][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2653" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][1][0]_i_1__1 
       (.I0(\trcd_cntr[0][0][1][2]_i_2__1_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .O(\tras_cntr_rb[0][0][1][0]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][1][1]_i_1__1 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .I3(\trcd_cntr[0][0][1][2]_i_2__1_n_0 ),
        .O(\tras_cntr_rb[0][0][1][1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2653" *) 
  LUT4 #(
    .INIT(16'hFEAA)) 
    \tras_cntr_rb[0][0][1][2]_i_1__1 
       (.I0(\trcd_cntr[0][0][1][2]_i_2__1_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .O(\tras_cntr_rb[0][0][1][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2652" *) 
  LUT4 #(
    .INIT(16'hAAFE)) 
    \tras_cntr_rb[0][0][2][0]_i_1__1 
       (.I0(\trcd_cntr[0][0][2][2]_i_2__1_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .O(\tras_cntr_rb[0][0][2][0]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h00A4)) 
    \tras_cntr_rb[0][0][2][1]_i_1__1 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .I3(\trcd_cntr[0][0][2][2]_i_2__1_n_0 ),
        .O(\tras_cntr_rb[0][0][2][1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2652" *) 
  LUT4 #(
    .INIT(16'hFEAA)) 
    \tras_cntr_rb[0][0][2][2]_i_1__1 
       (.I0(\trcd_cntr[0][0][2][2]_i_2__1_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .O(\tras_cntr_rb[0][0][2][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2651" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][3][0]_i_1__1 
       (.I0(\trcd_cntr[0][0][3][2]_i_2__1_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .O(\tras_cntr_rb[0][0][3][0]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][3][1]_i_1__1 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .I3(\trcd_cntr[0][0][3][2]_i_2__1_n_0 ),
        .O(\tras_cntr_rb[0][0][3][1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2651" *) 
  LUT4 #(
    .INIT(16'hFEAA)) 
    \tras_cntr_rb[0][0][3][2]_i_1__1 
       (.I0(\trcd_cntr[0][0][3][2]_i_2__1_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .O(\tras_cntr_rb[0][0][3][2]_i_1__1_n_0 ));
  FDRE \tras_cntr_rb_reg[0][0][0][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][0][0]_i_1__1_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][0][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][0][1]_i_1__1_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][0][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][0][2]_i_1__1_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][1][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][1][0]_i_1__1_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][1][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][1][1]_i_1__1_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][1][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][1][2]_i_1__1_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][2][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][2][0]_i_1__1_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][2][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][2][1]_i_1__1_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][2][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][2][2]_i_1__1_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][3][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][3][0]_i_1__1_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][3][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][3][1]_i_1__1_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][3][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][3][2]_i_1__1_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2631" *) 
  LUT4 #(
    .INIT(16'h99F9)) 
    \trcd_cntr[0][0][0][0]_i_1__1 
       (.I0(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I1(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I2(\trcd_cntr[0][0][0][2]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr[0][0][0][0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2631" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][0][1]_i_1__1 
       (.I0(\FSM_sequential_grSt_reg[0]_0 ),
        .I1(\trcd_cntr[0][0][0][2]_i_2__1_n_0 ),
        .I2(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .O(\trcd_cntr[0][0][0][1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][0][2]_i_1__1 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][0][2] ),
        .I4(\FSM_sequential_grSt_reg[0]_0 ),
        .I5(\trcd_cntr[0][0][0][2]_i_2__1_n_0 ),
        .O(\trcd_cntr[0][0][0][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2627" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \trcd_cntr[0][0][0][2]_i_2__1 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\trcd_cntr[0][0][0][2]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0001)) 
    \trcd_cntr[0][0][0][3]_i_1__1 
       (.I0(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][0][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][0][3] ),
        .I5(\trcd_cntr_is_zero[0][0][0]_i_2__1_n_0 ),
        .O(\trcd_cntr[0][0][0][3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2634" *) 
  LUT4 #(
    .INIT(16'hF44F)) 
    \trcd_cntr[0][0][1][0]_i_1__1 
       (.I0(\FSM_sequential_grSt_reg[0]_0 ),
        .I1(\trcd_cntr[0][0][1][2]_i_2__1_n_0 ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .O(\trcd_cntr[0][0][1][0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2634" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][1][1]_i_1__1 
       (.I0(\FSM_sequential_grSt_reg[0]_0 ),
        .I1(\trcd_cntr[0][0][1][2]_i_2__1_n_0 ),
        .I2(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .O(\trcd_cntr[0][0][1][1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][1][2]_i_1__1 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][1][2] ),
        .I4(\FSM_sequential_grSt_reg[0]_0 ),
        .I5(\trcd_cntr[0][0][1][2]_i_2__1_n_0 ),
        .O(\trcd_cntr[0][0][1][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2628" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \trcd_cntr[0][0][1][2]_i_2__1 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\trcd_cntr[0][0][1][2]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h5555555400000001)) 
    \trcd_cntr[0][0][1][3]_i_1__1 
       (.I0(\trcd_cntr_is_zero[0][0][1]_i_2__1_n_0 ),
        .I1(\trcd_cntr_reg_n_0_[0][0][1][2] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I4(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I5(\trcd_cntr_reg_n_0_[0][0][1][3] ),
        .O(\trcd_cntr[0][0][1][3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2633" *) 
  LUT4 #(
    .INIT(16'h99F9)) 
    \trcd_cntr[0][0][2][0]_i_1__1 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I2(\trcd_cntr[0][0][2][2]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr[0][0][2][0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2633" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][2][1]_i_1__1 
       (.I0(\FSM_sequential_grSt_reg[0]_0 ),
        .I1(\trcd_cntr[0][0][2][2]_i_2__1_n_0 ),
        .I2(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .O(\trcd_cntr[0][0][2][1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][2][2]_i_1__1 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][2][2] ),
        .I4(\FSM_sequential_grSt_reg[0]_0 ),
        .I5(\trcd_cntr[0][0][2][2]_i_2__1_n_0 ),
        .O(\trcd_cntr[0][0][2][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2628" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \trcd_cntr[0][0][2][2]_i_2__1 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\trcd_cntr[0][0][2][2]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0001)) 
    \trcd_cntr[0][0][2][3]_i_1__1 
       (.I0(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][2][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][2][3] ),
        .I5(\trcd_cntr_is_zero[0][0][2]_i_2__1_n_0 ),
        .O(\trcd_cntr[0][0][2][3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2632" *) 
  LUT4 #(
    .INIT(16'hF44F)) 
    \trcd_cntr[0][0][3][0]_i_1__1 
       (.I0(\FSM_sequential_grSt_reg[0]_0 ),
        .I1(\trcd_cntr[0][0][3][2]_i_2__1_n_0 ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .O(\trcd_cntr[0][0][3][0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2632" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][3][1]_i_1__1 
       (.I0(\FSM_sequential_grSt_reg[0]_0 ),
        .I1(\trcd_cntr[0][0][3][2]_i_2__1_n_0 ),
        .I2(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .O(\trcd_cntr[0][0][3][1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][3][2]_i_1__1 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][3][2] ),
        .I4(\FSM_sequential_grSt_reg[0]_0 ),
        .I5(\trcd_cntr[0][0][3][2]_i_2__1_n_0 ),
        .O(\trcd_cntr[0][0][3][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2627" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    \trcd_cntr[0][0][3][2]_i_2__1 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\trcd_cntr[0][0][3][2]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0001)) 
    \trcd_cntr[0][0][3][3]_i_1__1 
       (.I0(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][3][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][3][3] ),
        .I5(\trcd_cntr_is_zero[0][0][3]_i_2__1_n_0 ),
        .O(\trcd_cntr[0][0][3][3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010000)) 
    \trcd_cntr_is_zero[0][0][0]_i_1__1 
       (.I0(\trcd_cntr_is_zero[0][0][0]_i_2__1_n_0 ),
        .I1(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][0][3] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][0][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I5(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .O(\trcd_cntr_is_zero[0][0][0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    \trcd_cntr_is_zero[0][0][0]_i_2__1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr_is_zero[0][0][0]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000014)) 
    \trcd_cntr_is_zero[0][0][1]_i_1__1 
       (.I0(\trcd_cntr_reg_n_0_[0][0][1][3] ),
        .I1(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][1][2] ),
        .I5(\trcd_cntr_is_zero[0][0][1]_i_2__1_n_0 ),
        .O(\trcd_cntr_is_zero[0][0][1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \trcd_cntr_is_zero[0][0][1]_i_2__1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr_is_zero[0][0][1]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010000)) 
    \trcd_cntr_is_zero[0][0][2]_i_1__1 
       (.I0(\trcd_cntr_is_zero[0][0][2]_i_2__1_n_0 ),
        .I1(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][2][3] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][2][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I5(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .O(\trcd_cntr_is_zero[0][0][2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \trcd_cntr_is_zero[0][0][2]_i_2__1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr_is_zero[0][0][2]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010100)) 
    \trcd_cntr_is_zero[0][0][3]_i_1__1 
       (.I0(\trcd_cntr_reg_n_0_[0][0][3][2] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][3][3] ),
        .I2(\trcd_cntr_is_zero[0][0][3]_i_2__1_n_0 ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .I5(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .O(\trcd_cntr_is_zero[0][0][3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \trcd_cntr_is_zero[0][0][3]_i_2__1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr_is_zero[0][0][3]_i_2__1_n_0 ));
  FDRE \trcd_cntr_is_zero_reg[0][0][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero[0][0][0]_i_1__1_n_0 ),
        .Q(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .R(1'b0));
  FDRE \trcd_cntr_is_zero_reg[0][0][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero[0][0][1]_i_1__1_n_0 ),
        .Q(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .R(1'b0));
  FDRE \trcd_cntr_is_zero_reg[0][0][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero[0][0][2]_i_1__1_n_0 ),
        .Q(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .R(1'b0));
  FDRE \trcd_cntr_is_zero_reg[0][0][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero[0][0][3]_i_1__1_n_0 ),
        .Q(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .R(1'b0));
  FDRE \trcd_cntr_reg[0][0][0][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][0][0]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][0][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][0][1]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][0][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][0][2]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][0][2] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][0][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][0][3]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][0][3] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][1][0]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][1][1]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][1][2]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][1][2] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][1][3]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][1][3] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][2][0]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][2][1]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][2][2]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][2][2] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][2][3]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][2][3] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][3][0]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][3][1]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][3][2]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][3][2] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][3][3]_i_1__1_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][3][3] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2629" *) 
  LUT5 #(
    .INIT(32'h53505555)) 
    \trp_cntr[0]_i_1__1 
       (.I0(\trp_cntr_reg_n_0_[0] ),
        .I1(\trp_cntr[0]_i_2__1_n_0 ),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .O(\trp_cntr[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    \trp_cntr[0]_i_2__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .I1(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .O(\trp_cntr[0]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hF4FFF400F400F4FF)) 
    \trp_cntr[1]_i_1__1 
       (.I0(\trp_cntr[1]_i_2__1_n_0 ),
        .I1(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I2(\trp_cntr[1]_i_3__1_n_0 ),
        .I3(\trp_cntr[1]_i_4_n_0 ),
        .I4(\trp_cntr_reg_n_0_[0] ),
        .I5(\trp_cntr_reg_n_0_[1] ),
        .O(\trp_cntr[1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2702" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \trp_cntr[1]_i_2__1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\trp_cntr[1]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h33BBFFF333BB33F3)) 
    \trp_cntr[1]_i_3__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .I1(grSt[0]),
        .I2(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .O(\trp_cntr[1]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2637" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \trp_cntr[1]_i_4 
       (.I0(grSt[2]),
        .I1(grSt[1]),
        .O(\trp_cntr[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0040FF4FFF4F0040)) 
    \trp_cntr[2]_i_1__1 
       (.I0(\trp_cntr[2]_i_2__1_n_0 ),
        .I1(grSt[0]),
        .I2(grSt[2]),
        .I3(grSt[1]),
        .I4(\trp_cntr_reg_n_0_[2] ),
        .I5(\trp_cntr[2]_i_3__0_n_0 ),
        .O(\trp_cntr[2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h3300550F33FF550F)) 
    \trp_cntr[2]_i_2__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .I1(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .O(\trp_cntr[2]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2686" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \trp_cntr[2]_i_3__0 
       (.I0(\trp_cntr_reg_n_0_[1] ),
        .I1(\trp_cntr_reg_n_0_[0] ),
        .O(\trp_cntr[2]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h0FF00FF044440FF0)) 
    \trp_cntr[3]_i_1__1 
       (.I0(\trp_cntr[3]_i_2__1_n_0 ),
        .I1(grSt[0]),
        .I2(\trp_cntr_reg_n_0_[3] ),
        .I3(\trp_cntr[3]_i_3__1_n_0 ),
        .I4(grSt[2]),
        .I5(grSt[1]),
        .O(\trp_cntr[3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0F5500330F55FF33)) 
    \trp_cntr[3]_i_2__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][2][3] ),
        .I1(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][3] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .O(\trp_cntr[3]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2686" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \trp_cntr[3]_i_3__1 
       (.I0(\trp_cntr_reg_n_0_[0] ),
        .I1(\trp_cntr_reg_n_0_[1] ),
        .I2(\trp_cntr_reg_n_0_[2] ),
        .O(\trp_cntr[3]_i_3__1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \trp_cntr[4]_i_1__1 
       (.I0(\trp_cntr[4]_i_2__1_n_0 ),
        .O(\trp_cntr[4]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBB0B0BB00B)) 
    \trp_cntr[4]_i_2__1 
       (.I0(\trp_cntr[4]_i_3__1_n_0 ),
        .I1(\trp_cntr[4]_i_4_n_0 ),
        .I2(\trp_cntr_reg_n_0_[4] ),
        .I3(\trp_cntr[3]_i_3__1_n_0 ),
        .I4(\trp_cntr_reg_n_0_[3] ),
        .I5(\trp_cntr[1]_i_4_n_0 ),
        .O(\trp_cntr[4]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h55000F3355FF0F33)) 
    \trp_cntr[4]_i_3__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][3][4] ),
        .I1(\ap_cntr_reg_n_0_[0][0][0][4] ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][4] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\ap_cntr_reg_n_0_[0][0][2][4] ),
        .O(\trp_cntr[4]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2629" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \trp_cntr[4]_i_4 
       (.I0(grSt[1]),
        .I1(grSt[0]),
        .I2(grSt[2]),
        .O(\trp_cntr[4]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h00000100)) 
    trp_cntr_is_zero_i_1__1
       (.I0(\trp_cntr[2]_i_1__1_n_0 ),
        .I1(\trp_cntr[3]_i_1__1_n_0 ),
        .I2(\trp_cntr[0]_i_1__1_n_0 ),
        .I3(\trp_cntr[4]_i_2__1_n_0 ),
        .I4(\trp_cntr[1]_i_1__1_n_0 ),
        .O(trp_cntr_is_zero_i_1__1_n_0));
  FDRE trp_cntr_is_zero_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(trp_cntr_is_zero_i_1__1_n_0),
        .Q(trp_cntr_is_zero_reg_n_0),
        .R(1'b0));
  FDRE \trp_cntr_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trp_cntr[0]_i_1__1_n_0 ),
        .Q(\trp_cntr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \trp_cntr_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trp_cntr[1]_i_1__1_n_0 ),
        .Q(\trp_cntr_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \trp_cntr_reg[2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trp_cntr[2]_i_1__1_n_0 ),
        .Q(\trp_cntr_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \trp_cntr_reg[3] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trp_cntr[3]_i_1__1_n_0 ),
        .Q(\trp_cntr_reg_n_0_[3] ),
        .R(rst_r1));
  FDRE \trp_cntr_reg[4] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\trp_cntr[4]_i_1__1_n_0 ),
        .Q(\trp_cntr_reg_n_0_[4] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2676" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][0]_i_1__1 
       (.I0(bank[0]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][0] ),
        .O(\txn_fifo[0][0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2674" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][11]_i_1__1 
       (.I0(col[0]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][11] ),
        .O(\txn_fifo[0][11]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2673" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][12]_i_1__1 
       (.I0(col[1]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][12] ),
        .O(\txn_fifo[0][12]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2672" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][13]_i_1__1 
       (.I0(col[2]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][13] ),
        .O(\txn_fifo[0][13]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2671" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][14]_i_1__1 
       (.I0(col[3]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][14] ),
        .O(\txn_fifo[0][14]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2670" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][15]_i_1__1 
       (.I0(col[4]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][15] ),
        .O(\txn_fifo[0][15]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2678" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][16]_i_1__1 
       (.I0(col[5]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][16] ),
        .O(\txn_fifo[0][16]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2669" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][17]_i_1__1 
       (.I0(col[6]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][17] ),
        .O(\txn_fifo[0][17]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2677" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][1]_i_1__1 
       (.I0(bank[1]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][1] ),
        .O(\txn_fifo[0][1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2668" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][24]_i_1__1 
       (.I0(row_mc_phy[0]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][24] ),
        .O(\txn_fifo[0][24]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2667" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][25]_i_1__1 
       (.I0(row_mc_phy[1]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][25] ),
        .O(\txn_fifo[0][25]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2679" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][26]_i_1__1 
       (.I0(row_mc_phy[2]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][26] ),
        .O(\txn_fifo[0][26]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2680" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][27]_i_1__1 
       (.I0(row_mc_phy[3]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][27] ),
        .O(\txn_fifo[0][27]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2681" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][28]_i_1__1 
       (.I0(row_mc_phy[4]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][28] ),
        .O(\txn_fifo[0][28]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2666" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][29]_i_1__1 
       (.I0(row_mc_phy[5]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][29] ),
        .O(\txn_fifo[0][29]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2675" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][2]_i_1__1 
       (.I0(group),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][2] ),
        .O(\txn_fifo[0][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2665" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][30]_i_1__1 
       (.I0(row_mc_phy[6]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][30] ),
        .O(\txn_fifo[0][30]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2664" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][31]_i_1__1 
       (.I0(row_mc_phy[7]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][31] ),
        .O(\txn_fifo[0][31]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2663" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][32]_i_1__1 
       (.I0(row_mc_phy[8]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][32] ),
        .O(\txn_fifo[0][32]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2682" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][33]_i_1__1 
       (.I0(row_mc_phy[9]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][33] ),
        .O(\txn_fifo[0][33]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2662" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][34]_i_1__1 
       (.I0(row_mc_phy[10]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][34] ),
        .O(\txn_fifo[0][34]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2661" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][35]_i_1__1 
       (.I0(row_mc_phy[11]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][35] ),
        .O(\txn_fifo[0][35]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2660" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][36]_i_1__1 
       (.I0(row_mc_phy[12]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][36] ),
        .O(\txn_fifo[0][36]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2659" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][37]_i_1__1 
       (.I0(row_mc_phy[13]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][37] ),
        .O(\txn_fifo[0][37]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2683" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][38]_i_1__1 
       (.I0(row_mc_phy[14]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][38] ),
        .O(\txn_fifo[0][38]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2658" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][39]_i_1__1 
       (.I0(row_mc_phy[15]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][39] ),
        .O(\txn_fifo[0][39]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2657" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][40]_i_1__1 
       (.I0(row_mc_phy[16]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][40] ),
        .O(\txn_fifo[0][40]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2656" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][44]_i_1__1 
       (.I0(cmd[0]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][44] ),
        .O(\txn_fifo[0][44]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2655" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][45]_i_1__1 
       (.I0(cmd[1]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][45] ),
        .O(\txn_fifo[0][45]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2654" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][46]_i_1__1 
       (.I0(cmd[2]),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][46] ),
        .O(\txn_fifo[0][46]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][47]_i_1__1 
       (.I0(1'b0),
        .I1(\txn_fifo[0][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][47] ),
        .O(\txn_fifo[0][47]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80001555)) 
    \txn_fifo[0][47]_i_2__0 
       (.I0(\txn_fifo_wptr_reg_n_0_[1] ),
        .I1(accept_reg_0),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(useAdr),
        .I4(\txn_fifo_wptr_reg_n_0_[0] ),
        .O(\txn_fifo[0][47]_i_2__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][0]_i_1__1 
       (.I0(bank[0]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][0] ),
        .O(\txn_fifo[1][0]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][11]_i_1__1 
       (.I0(col[0]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][11] ),
        .O(\txn_fifo[1][11]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][12]_i_1__1 
       (.I0(col[1]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][12] ),
        .O(\txn_fifo[1][12]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][13]_i_1__1 
       (.I0(col[2]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][13] ),
        .O(\txn_fifo[1][13]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][14]_i_1__1 
       (.I0(col[3]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][14] ),
        .O(\txn_fifo[1][14]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][15]_i_1__1 
       (.I0(col[4]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][15] ),
        .O(\txn_fifo[1][15]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][16]_i_1__1 
       (.I0(col[5]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][16] ),
        .O(\txn_fifo[1][16]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][17]_i_1__1 
       (.I0(col[6]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][17] ),
        .O(\txn_fifo[1][17]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][1]_i_1__1 
       (.I0(bank[1]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][1] ),
        .O(\txn_fifo[1][1]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][24]_i_1__1 
       (.I0(row_mc_phy[0]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][24] ),
        .O(\txn_fifo[1][24]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][25]_i_1__1 
       (.I0(row_mc_phy[1]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][25] ),
        .O(\txn_fifo[1][25]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][26]_i_1__1 
       (.I0(row_mc_phy[2]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][26] ),
        .O(\txn_fifo[1][26]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][27]_i_1__1 
       (.I0(row_mc_phy[3]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][27] ),
        .O(\txn_fifo[1][27]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][28]_i_1__1 
       (.I0(row_mc_phy[4]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][28] ),
        .O(\txn_fifo[1][28]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][29]_i_1__1 
       (.I0(row_mc_phy[5]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][29] ),
        .O(\txn_fifo[1][29]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][2]_i_1__1 
       (.I0(group),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][2] ),
        .O(\txn_fifo[1][2]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][30]_i_1__1 
       (.I0(row_mc_phy[6]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][30] ),
        .O(\txn_fifo[1][30]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][31]_i_1__1 
       (.I0(row_mc_phy[7]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][31] ),
        .O(\txn_fifo[1][31]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][32]_i_1__1 
       (.I0(row_mc_phy[8]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][32] ),
        .O(\txn_fifo[1][32]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][33]_i_1__1 
       (.I0(row_mc_phy[9]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][33] ),
        .O(\txn_fifo[1][33]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][34]_i_1__1 
       (.I0(row_mc_phy[10]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][34] ),
        .O(\txn_fifo[1][34]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][35]_i_1__1 
       (.I0(row_mc_phy[11]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][35] ),
        .O(\txn_fifo[1][35]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][36]_i_1__1 
       (.I0(row_mc_phy[12]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][36] ),
        .O(\txn_fifo[1][36]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][37]_i_1__1 
       (.I0(row_mc_phy[13]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][37] ),
        .O(\txn_fifo[1][37]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][38]_i_1__1 
       (.I0(row_mc_phy[14]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][38] ),
        .O(\txn_fifo[1][38]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][39]_i_1__1 
       (.I0(row_mc_phy[15]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][39] ),
        .O(\txn_fifo[1][39]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][40]_i_1__1 
       (.I0(row_mc_phy[16]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][40] ),
        .O(\txn_fifo[1][40]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][44]_i_1__1 
       (.I0(cmd[0]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][44] ),
        .O(\txn_fifo[1][44]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][45]_i_1__1 
       (.I0(cmd[1]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][45] ),
        .O(\txn_fifo[1][45]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][46]_i_1__1 
       (.I0(cmd[2]),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][46] ),
        .O(\txn_fifo[1][46]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][47]_i_1__1 
       (.I0(1'b0),
        .I1(\txn_fifo[1][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][47] ),
        .O(\txn_fifo[1][47]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00007F80)) 
    \txn_fifo[1][47]_i_2__0 
       (.I0(accept_reg_0),
        .I1(\txn_fifo_wptr_reg[0]_0 ),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .O(\txn_fifo[1][47]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2676" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][0]_i_1__1 
       (.I0(bank[0]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][0] ),
        .O(\txn_fifo[2][0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2674" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][11]_i_1__1 
       (.I0(col[0]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][11] ),
        .O(\txn_fifo[2][11]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2673" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][12]_i_1__1 
       (.I0(col[1]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][12] ),
        .O(\txn_fifo[2][12]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2672" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][13]_i_1__1 
       (.I0(col[2]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][13] ),
        .O(\txn_fifo[2][13]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2671" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][14]_i_1__1 
       (.I0(col[3]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][14] ),
        .O(\txn_fifo[2][14]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2670" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][15]_i_1__1 
       (.I0(col[4]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][15] ),
        .O(\txn_fifo[2][15]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2678" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][16]_i_1__1 
       (.I0(col[5]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][16] ),
        .O(\txn_fifo[2][16]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2669" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][17]_i_1__1 
       (.I0(col[6]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][17] ),
        .O(\txn_fifo[2][17]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2677" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][1]_i_1__1 
       (.I0(bank[1]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][1] ),
        .O(\txn_fifo[2][1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2668" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][24]_i_1__1 
       (.I0(row_mc_phy[0]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][24] ),
        .O(\txn_fifo[2][24]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2667" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][25]_i_1__1 
       (.I0(row_mc_phy[1]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][25] ),
        .O(\txn_fifo[2][25]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2679" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][26]_i_1__1 
       (.I0(row_mc_phy[2]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][26] ),
        .O(\txn_fifo[2][26]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2680" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][27]_i_1__1 
       (.I0(row_mc_phy[3]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][27] ),
        .O(\txn_fifo[2][27]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2681" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][28]_i_1__1 
       (.I0(row_mc_phy[4]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][28] ),
        .O(\txn_fifo[2][28]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2666" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][29]_i_1__1 
       (.I0(row_mc_phy[5]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][29] ),
        .O(\txn_fifo[2][29]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2675" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][2]_i_1__1 
       (.I0(group),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][2] ),
        .O(\txn_fifo[2][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2665" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][30]_i_1__1 
       (.I0(row_mc_phy[6]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][30] ),
        .O(\txn_fifo[2][30]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2664" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][31]_i_1__1 
       (.I0(row_mc_phy[7]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][31] ),
        .O(\txn_fifo[2][31]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2663" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][32]_i_1__1 
       (.I0(row_mc_phy[8]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][32] ),
        .O(\txn_fifo[2][32]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2682" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][33]_i_1__1 
       (.I0(row_mc_phy[9]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][33] ),
        .O(\txn_fifo[2][33]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2662" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][34]_i_1__1 
       (.I0(row_mc_phy[10]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][34] ),
        .O(\txn_fifo[2][34]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2661" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][35]_i_1__1 
       (.I0(row_mc_phy[11]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][35] ),
        .O(\txn_fifo[2][35]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2660" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][36]_i_1__1 
       (.I0(row_mc_phy[12]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][36] ),
        .O(\txn_fifo[2][36]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2659" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][37]_i_1__1 
       (.I0(row_mc_phy[13]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][37] ),
        .O(\txn_fifo[2][37]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2683" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][38]_i_1__1 
       (.I0(row_mc_phy[14]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][38] ),
        .O(\txn_fifo[2][38]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2658" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][39]_i_1__1 
       (.I0(row_mc_phy[15]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][39] ),
        .O(\txn_fifo[2][39]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2657" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][40]_i_1__1 
       (.I0(row_mc_phy[16]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][40] ),
        .O(\txn_fifo[2][40]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2656" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][44]_i_1__1 
       (.I0(cmd[0]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][44] ),
        .O(\txn_fifo[2][44]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2655" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][45]_i_1__1 
       (.I0(cmd[1]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][45] ),
        .O(\txn_fifo[2][45]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2654" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][46]_i_1__1 
       (.I0(cmd[2]),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][46] ),
        .O(\txn_fifo[2][46]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][47]_i_1__1 
       (.I0(1'b0),
        .I1(\txn_fifo[2][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][47] ),
        .O(\txn_fifo[2][47]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h15558000)) 
    \txn_fifo[2][47]_i_2__1 
       (.I0(\txn_fifo_wptr_reg_n_0_[0] ),
        .I1(useAdr),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(accept_reg_0),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .O(\txn_fifo[2][47]_i_2__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][0]_i_1__1 
       (.I0(bank[0]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][0] ),
        .O(\txn_fifo[3][0]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][11]_i_1__1 
       (.I0(col[0]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][11] ),
        .O(\txn_fifo[3][11]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][12]_i_1__1 
       (.I0(col[1]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][12] ),
        .O(\txn_fifo[3][12]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][13]_i_1__1 
       (.I0(col[2]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][13] ),
        .O(\txn_fifo[3][13]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][14]_i_1__1 
       (.I0(col[3]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][14] ),
        .O(\txn_fifo[3][14]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][15]_i_1__1 
       (.I0(col[4]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][15] ),
        .O(\txn_fifo[3][15]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][16]_i_1__1 
       (.I0(col[5]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][16] ),
        .O(\txn_fifo[3][16]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][17]_i_1__1 
       (.I0(col[6]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][17] ),
        .O(\txn_fifo[3][17]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][1]_i_1__1 
       (.I0(bank[1]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][1] ),
        .O(\txn_fifo[3][1]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][24]_i_1__1 
       (.I0(row_mc_phy[0]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][24] ),
        .O(\txn_fifo[3][24]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][25]_i_1__1 
       (.I0(row_mc_phy[1]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][25] ),
        .O(\txn_fifo[3][25]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][26]_i_1__1 
       (.I0(row_mc_phy[2]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][26] ),
        .O(\txn_fifo[3][26]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][27]_i_1__1 
       (.I0(row_mc_phy[3]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][27] ),
        .O(\txn_fifo[3][27]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][28]_i_1__1 
       (.I0(row_mc_phy[4]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][28] ),
        .O(\txn_fifo[3][28]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][29]_i_1__1 
       (.I0(row_mc_phy[5]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][29] ),
        .O(\txn_fifo[3][29]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][2]_i_1__1 
       (.I0(group),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][2] ),
        .O(\txn_fifo[3][2]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][30]_i_1__1 
       (.I0(row_mc_phy[6]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][30] ),
        .O(\txn_fifo[3][30]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][31]_i_1__1 
       (.I0(row_mc_phy[7]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][31] ),
        .O(\txn_fifo[3][31]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][32]_i_1__1 
       (.I0(row_mc_phy[8]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][32] ),
        .O(\txn_fifo[3][32]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][33]_i_1__1 
       (.I0(row_mc_phy[9]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][33] ),
        .O(\txn_fifo[3][33]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][34]_i_1__1 
       (.I0(row_mc_phy[10]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][34] ),
        .O(\txn_fifo[3][34]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][35]_i_1__1 
       (.I0(row_mc_phy[11]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][35] ),
        .O(\txn_fifo[3][35]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][36]_i_1__1 
       (.I0(row_mc_phy[12]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][36] ),
        .O(\txn_fifo[3][36]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][37]_i_1__1 
       (.I0(row_mc_phy[13]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][37] ),
        .O(\txn_fifo[3][37]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][38]_i_1__1 
       (.I0(row_mc_phy[14]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][38] ),
        .O(\txn_fifo[3][38]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][39]_i_1__1 
       (.I0(row_mc_phy[15]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][39] ),
        .O(\txn_fifo[3][39]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][40]_i_1__1 
       (.I0(row_mc_phy[16]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][40] ),
        .O(\txn_fifo[3][40]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][44]_i_1__1 
       (.I0(cmd[0]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][44] ),
        .O(\txn_fifo[3][44]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][45]_i_1__1 
       (.I0(cmd[1]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][45] ),
        .O(\txn_fifo[3][45]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][46]_i_1__1 
       (.I0(cmd[2]),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][46] ),
        .O(\txn_fifo[3][46]_i_1__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][47]_i_1__1 
       (.I0(1'b0),
        .I1(\txn_fifo[3][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][47] ),
        .O(\txn_fifo[3][47]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h7F800000)) 
    \txn_fifo[3][47]_i_2__0 
       (.I0(accept_reg_0),
        .I1(\txn_fifo_wptr_reg[0]_0 ),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .O(\txn_fifo[3][47]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h9006099009906009)) 
    txn_fifo_empty_i_1__1
       (.I0(\txn_fifo_wptr_reg_n_0_[1] ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(txn_fifo_empty_i_2__0_n_0),
        .I4(\txn_fifo_rptr_reg_n_0_[0] ),
        .I5(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ),
        .O(txn_fifo_empty_i_1__1_n_0));
  LUT3 #(
    .INIT(8'h80)) 
    txn_fifo_empty_i_2__0
       (.I0(accept_reg_0),
        .I1(\txn_fifo_wptr_reg[0]_0 ),
        .I2(useAdr),
        .O(txn_fifo_empty_i_2__0_n_0));
  FDRE txn_fifo_empty_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(txn_fifo_empty_i_1__1_n_0),
        .Q(txn_fifo_empty_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[0]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_2__1_n_0 ),
        .I1(\txn_fifo[0][0]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[0]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[0]_i_3__1_n_0 ),
        .I4(\txn_fifo[2][0]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_5__0_n_0 ),
        .O(\txn_fifo_output[0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[0]_i_2__1 
       (.I0(\txn_fifo[3][0]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[0]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[0]_i_3__1 
       (.I0(\txn_fifo[1][0]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[0]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[11]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][11]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[11]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[11]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][11]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[11]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[11]_i_2__1 
       (.I0(\txn_fifo[3][11]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[11]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[11]_i_3__1 
       (.I0(\txn_fifo[1][11]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[11]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[12]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][12]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[12]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[12]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][12]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[12]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[12]_i_2__1 
       (.I0(\txn_fifo[3][12]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[12]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[12]_i_3__1 
       (.I0(\txn_fifo[1][12]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[12]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[13]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][13]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[13]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[13]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][13]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[13]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[13]_i_2__1 
       (.I0(\txn_fifo[3][13]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[13]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[13]_i_3__1 
       (.I0(\txn_fifo[1][13]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[13]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[14]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][14]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[14]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[14]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][14]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[14]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[14]_i_2__1 
       (.I0(\txn_fifo[3][14]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[14]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[14]_i_3__1 
       (.I0(\txn_fifo[1][14]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[14]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[15]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][15]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[15]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[15]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][15]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[15]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[15]_i_2__1 
       (.I0(\txn_fifo[1][15]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[15]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[15]_i_3__1 
       (.I0(\txn_fifo[3][15]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[15]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[16]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_2__1_n_0 ),
        .I1(\txn_fifo[0][16]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[16]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[16]_i_3__1_n_0 ),
        .I4(\txn_fifo[2][16]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_5__0_n_0 ),
        .O(\txn_fifo_output[16]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[16]_i_2__1 
       (.I0(\txn_fifo[3][16]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[16]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[16]_i_3__1 
       (.I0(\txn_fifo[1][16]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[16]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[17]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][17]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[17]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[17]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][17]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[17]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[17]_i_2__1 
       (.I0(\txn_fifo[3][17]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[17]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[17]_i_3__1 
       (.I0(\txn_fifo[1][17]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[17]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[1]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_2__1_n_0 ),
        .I1(\txn_fifo[0][1]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[1]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[1]_i_3__1_n_0 ),
        .I4(\txn_fifo[2][1]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_5__0_n_0 ),
        .O(\txn_fifo_output[1]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[1]_i_2__1 
       (.I0(\txn_fifo[1][1]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[1]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[1]_i_3__1 
       (.I0(\txn_fifo[3][1]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[1]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[24]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][24]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[24]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[24]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][24]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[24]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[24]_i_2__1 
       (.I0(\txn_fifo[3][24]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[24]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[24]_i_3__1 
       (.I0(\txn_fifo[1][24]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[24]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[25]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][25]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[25]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[25]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][25]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[25]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[25]_i_2__1 
       (.I0(\txn_fifo[3][25]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[25]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[25]_i_3__1 
       (.I0(\txn_fifo[1][25]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[25]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[26]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_2__1_n_0 ),
        .I1(\txn_fifo[0][26]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[26]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[26]_i_3__1_n_0 ),
        .I4(\txn_fifo[2][26]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_5__0_n_0 ),
        .O(\txn_fifo_output[26]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[26]_i_2__1 
       (.I0(\txn_fifo[3][26]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[26]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[26]_i_3__1 
       (.I0(\txn_fifo[1][26]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[26]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[27]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_2__1_n_0 ),
        .I1(\txn_fifo[0][27]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[27]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[27]_i_3__1_n_0 ),
        .I4(\txn_fifo[2][27]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_5__0_n_0 ),
        .O(\txn_fifo_output[27]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[27]_i_2__1 
       (.I0(\txn_fifo[3][27]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[27]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[27]_i_3__1 
       (.I0(\txn_fifo[1][27]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[27]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[28]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_2__1_n_0 ),
        .I1(\txn_fifo[0][28]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[28]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[28]_i_3__1_n_0 ),
        .I4(\txn_fifo[2][28]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_5__0_n_0 ),
        .O(\txn_fifo_output[28]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[28]_i_2__1 
       (.I0(\txn_fifo[3][28]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[28]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[28]_i_3__1 
       (.I0(\txn_fifo[1][28]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[28]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[29]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][29]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[29]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[29]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][29]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[29]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[29]_i_2__1 
       (.I0(\txn_fifo[1][29]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[29]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[29]_i_3__1 
       (.I0(\txn_fifo[3][29]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[29]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[2]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][2]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[2]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[2]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][2]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[2]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[2]_i_2__1 
       (.I0(\txn_fifo[3][2]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[2]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[2]_i_3__1 
       (.I0(\txn_fifo[1][2]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[2]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[30]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][30]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[30]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[30]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][30]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[30]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[30]_i_2__1 
       (.I0(\txn_fifo[3][30]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[30]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[30]_i_3__1 
       (.I0(\txn_fifo[1][30]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[30]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[31]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][31]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[31]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[31]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][31]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[31]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[31]_i_2__1 
       (.I0(\txn_fifo[3][31]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[31]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[31]_i_3__1 
       (.I0(\txn_fifo[1][31]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[31]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[32]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][32]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[32]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[32]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][32]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[32]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[32]_i_2__1 
       (.I0(\txn_fifo[3][32]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[32]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[32]_i_3__1 
       (.I0(\txn_fifo[1][32]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[32]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[33]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_2__1_n_0 ),
        .I1(\txn_fifo[0][33]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[33]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[33]_i_3__1_n_0 ),
        .I4(\txn_fifo[2][33]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_5__0_n_0 ),
        .O(\txn_fifo_output[33]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[33]_i_2__1 
       (.I0(\txn_fifo[1][33]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[33]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[33]_i_3__1 
       (.I0(\txn_fifo[3][33]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[33]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[34]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][34]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[34]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[34]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][34]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[34]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[34]_i_2__1 
       (.I0(\txn_fifo[3][34]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[34]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[34]_i_3__1 
       (.I0(\txn_fifo[1][34]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[34]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[35]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][35]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[35]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[35]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][35]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[35]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[35]_i_2__1 
       (.I0(\txn_fifo[3][35]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[35]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[35]_i_3__1 
       (.I0(\txn_fifo[1][35]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[35]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[36]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][36]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[36]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[36]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][36]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[36]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[36]_i_2__1 
       (.I0(\txn_fifo[3][36]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[36]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[36]_i_3__1 
       (.I0(\txn_fifo[1][36]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[36]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[37]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][37]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[37]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[37]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][37]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[37]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[37]_i_2__1 
       (.I0(\txn_fifo[1][37]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[37]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[37]_i_3__1 
       (.I0(\txn_fifo[3][37]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[37]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[38]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_2__1_n_0 ),
        .I1(\txn_fifo[0][38]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[38]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[38]_i_3__1_n_0 ),
        .I4(\txn_fifo[2][38]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_5__0_n_0 ),
        .O(\txn_fifo_output[38]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[38]_i_2__1 
       (.I0(\txn_fifo[3][38]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[38]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[38]_i_3__1 
       (.I0(\txn_fifo[1][38]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[38]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[39]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][39]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[39]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[39]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][39]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[39]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[39]_i_2__1 
       (.I0(\txn_fifo[3][39]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[39]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[39]_i_3__1 
       (.I0(\txn_fifo[1][39]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[39]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[40]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][40]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[40]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[40]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][40]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[40]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[40]_i_2__1 
       (.I0(\txn_fifo[3][40]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[40]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[40]_i_3__1 
       (.I0(\txn_fifo[1][40]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[40]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[44]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][44]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[44]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[44]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][44]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[44]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[44]_i_2__1 
       (.I0(\txn_fifo[3][44]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[44]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[44]_i_3__1 
       (.I0(\txn_fifo[1][44]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[44]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[45]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][45]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[45]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[45]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][45]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[45]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[45]_i_2__1 
       (.I0(\txn_fifo[3][45]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[45]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[45]_i_3__1 
       (.I0(\txn_fifo[1][45]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[45]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[46]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_5__0_n_0 ),
        .I1(\txn_fifo[2][46]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[46]_i_2__1_n_0 ),
        .I3(\txn_fifo_output[46]_i_3__1_n_0 ),
        .I4(\txn_fifo[0][46]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__1_n_0 ),
        .O(\txn_fifo_output[46]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[46]_i_2__1 
       (.I0(\txn_fifo[3][46]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[46]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[46]_i_3__1 
       (.I0(\txn_fifo[1][46]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[46]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[47]_i_1__1 
       (.I0(\txn_fifo_output[47]_i_2__1_n_0 ),
        .I1(\txn_fifo[0][47]_i_1__1_n_0 ),
        .I2(\txn_fifo_output[47]_i_3__1_n_0 ),
        .I3(\txn_fifo_output[47]_i_4__0_n_0 ),
        .I4(\txn_fifo[2][47]_i_1__1_n_0 ),
        .I5(\txn_fifo_output[47]_i_5__0_n_0 ),
        .O(\txn_fifo_output[47]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hF7AE)) 
    \txn_fifo_output[47]_i_2__1 
       (.I0(\txn_fifo_rptr_reg_n_0_[1] ),
        .I1(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .O(\txn_fifo_output[47]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[47]_i_3__1 
       (.I0(\txn_fifo[3][47]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .O(\txn_fifo_output[47]_i_3__1_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[47]_i_4__0 
       (.I0(\txn_fifo[1][47]_i_1__1_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[47]_i_4__0_n_0 ));
  LUT4 #(
    .INIT(16'hFB5D)) 
    \txn_fifo_output[47]_i_5__0 
       (.I0(\txn_fifo_rptr_reg_n_0_[1] ),
        .I1(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I2(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .O(\txn_fifo_output[47]_i_5__0_n_0 ));
  FDRE \txn_fifo_output_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[0]_i_1__1_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[11] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[11]_i_1__1_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[12] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[12]_i_1__1_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[13] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[13]_i_1__1_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[14] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[14]_i_1__1_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[15] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[15]_i_1__1_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[16] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[16]_i_1__1_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[17] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[17]_i_1__1_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[1]_i_1__1_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[24] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[24]_i_1__1_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[25] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[25]_i_1__1_n_0 ),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[26] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[26]_i_1__1_n_0 ),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[27] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[27]_i_1__1_n_0 ),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[28] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[28]_i_1__1_n_0 ),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[29] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[29]_i_1__1_n_0 ),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[2]_i_1__1_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[30] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[30]_i_1__1_n_0 ),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[31] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[31]_i_1__1_n_0 ),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[32] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[32]_i_1__1_n_0 ),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[33] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[33]_i_1__1_n_0 ),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[34] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[34]_i_1__1_n_0 ),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[35] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[35]_i_1__1_n_0 ),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[36] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[36]_i_1__1_n_0 ),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[37] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[37]_i_1__1_n_0 ),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[38] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[38]_i_1__1_n_0 ),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[39] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[39]_i_1__1_n_0 ),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[40] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[40]_i_1__1_n_0 ),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[44] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[44]_i_1__1_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[44] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[45] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[45]_i_1__1_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[45] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[46] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[46]_i_1__1_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[46] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[47] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_output[47]_i_1__1_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[47] ),
        .R(1'b0));
  FDRE \txn_fifo_reg[0][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][0]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][0] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][11] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][11]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][11] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][12] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][12]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][12] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][13] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][13]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][13] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][14] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][14]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][14] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][15] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][15]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][15] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][16] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][16]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][16] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][17] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][17]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][17] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][1]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][1] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][24] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][24]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][24] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][25] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][25]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][25] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][26] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][26]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][26] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][27] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][27]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][27] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][28] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][28]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][28] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][29] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][29]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][29] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][2]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][2] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][30] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][30]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][30] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][31] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][31]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][31] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][32] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][32]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][32] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][33] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][33]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][33] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][34] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][34]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][34] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][35] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][35]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][35] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][36] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][36]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][36] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][37] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][37]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][37] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][38] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][38]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][38] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][39] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][39]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][39] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][40] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][40]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][40] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][44] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][44]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][44] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][45] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][45]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][45] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][46] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][46]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][46] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][47] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[0][47]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][47] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][0]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][0] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][11] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][11]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][11] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][12] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][12]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][12] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][13] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][13]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][13] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][14] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][14]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][14] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][15] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][15]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][15] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][16] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][16]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][16] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][17] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][17]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][17] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][1]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][1] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][24] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][24]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][24] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][25] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][25]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][25] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][26] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][26]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][26] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][27] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][27]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][27] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][28] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][28]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][28] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][29] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][29]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][29] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][2]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][2] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][30] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][30]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][30] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][31] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][31]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][31] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][32] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][32]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][32] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][33] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][33]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][33] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][34] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][34]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][34] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][35] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][35]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][35] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][36] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][36]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][36] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][37] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][37]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][37] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][38] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][38]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][38] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][39] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][39]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][39] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][40] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][40]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][40] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][44] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][44]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][44] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][45] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][45]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][45] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][46] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][46]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][46] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][47] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[1][47]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][47] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][0]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][0] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][11] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][11]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][11] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][12] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][12]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][12] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][13] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][13]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][13] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][14] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][14]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][14] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][15] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][15]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][15] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][16] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][16]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][16] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][17] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][17]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][17] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][1]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][1] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][24] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][24]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][24] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][25] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][25]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][25] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][26] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][26]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][26] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][27] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][27]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][27] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][28] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][28]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][28] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][29] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][29]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][29] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][2]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][2] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][30] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][30]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][30] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][31] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][31]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][31] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][32] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][32]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][32] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][33] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][33]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][33] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][34] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][34]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][34] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][35] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][35]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][35] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][36] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][36]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][36] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][37] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][37]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][37] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][38] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][38]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][38] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][39] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][39]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][39] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][40] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][40]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][40] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][44] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][44]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][44] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][45] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][45]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][45] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][46] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][46]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][46] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][47] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[2][47]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][47] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][0]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][0] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][11] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][11]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][11] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][12] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][12]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][12] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][13] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][13]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][13] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][14] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][14]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][14] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][15] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][15]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][15] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][16] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][16]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][16] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][17] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][17]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][17] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][1]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][1] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][24] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][24]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][24] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][25] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][25]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][25] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][26] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][26]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][26] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][27] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][27]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][27] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][28] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][28]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][28] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][29] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][29]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][29] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][2] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][2]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][2] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][30] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][30]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][30] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][31] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][31]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][31] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][32] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][32]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][32] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][33] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][33]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][33] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][34] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][34]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][34] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][35] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][35]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][35] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][36] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][36]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][36] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][37] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][37]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][37] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][38] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][38]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][38] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][39] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][39]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][39] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][40] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][40]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][40] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][44] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][44]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][44] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][45] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][45]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][45] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][46] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][46]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][46] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][47] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo[3][47]_i_1__1_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][47] ),
        .R(rst_r1));
  LUT2 #(
    .INIT(4'h6)) 
    \txn_fifo_rptr[0]_i_1__1 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_7__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .O(\txn_fifo_rptr[0]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hAA6A)) 
    \txn_fifo_rptr[1]_i_1__1 
       (.I0(\txn_fifo_rptr_reg_n_0_[1] ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\FSM_sequential_grSt[1]_i_2__0_n_0 ),
        .I3(\txn_fifo_rptr[1]_i_2__0_n_0 ),
        .O(\txn_fifo_rptr[1]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFBFBBAA)) 
    \txn_fifo_rptr[1]_i_2__0 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(\FSM_sequential_grSt_reg[0]_0 ),
        .I3(cas_fifo_full_reg_n_0),
        .I4(grSt[1]),
        .O(\txn_fifo_rptr[1]_i_2__0_n_0 ));
  FDRE \txn_fifo_rptr_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_rptr[0]_i_1__1_n_0 ),
        .Q(\txn_fifo_rptr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \txn_fifo_rptr_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_rptr[1]_i_1__1_n_0 ),
        .Q(\txn_fifo_rptr_reg_n_0_[1] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2636" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \txn_fifo_wptr[0]_i_1__0 
       (.I0(\txn_fifo_wptr_reg_n_0_[0] ),
        .I1(useAdr),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(accept_reg_0),
        .O(\txn_fifo_wptr[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2636" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \txn_fifo_wptr[1]_i_1__0 
       (.I0(\txn_fifo_wptr_reg_n_0_[0] ),
        .I1(useAdr),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(accept_reg_0),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .O(\txn_fifo_wptr[1]_i_1__0_n_0 ));
  FDRE \txn_fifo_wptr_reg[0] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_wptr[0]_i_1__0_n_0 ),
        .Q(\txn_fifo_wptr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \txn_fifo_wptr_reg[1] 
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(\txn_fifo_wptr[1]_i_1__0_n_0 ),
        .Q(\txn_fifo_wptr_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE underfill_done_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(underfill_done_reg_0),
        .Q(underfill_done_reg_n_0),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'h4444444444444454)) 
    wrReqR_i_1__1
       (.I0(clrReq17_out),
        .I1(wrReqR_i_2__1_n_0),
        .I2(\FSM_sequential_gr_cas_state[2]_i_3_n_0 ),
        .I3(wrReqR_i_3__0_n_0),
        .I4(wrReqR_i_4__0_n_0),
        .I5(wrReqR_i_5__0_n_0),
        .O(wrReqR_i_1__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2635" *) 
  LUT5 #(
    .INIT(32'hAAAAAAEA)) 
    wrReqR_i_2__1
       (.I0(wrReqR_reg_0),
        .I1(gr_cas_state[1]),
        .I2(underfill_done_reg_n_0),
        .I3(gr_cas_state[0]),
        .I4(gr_cas_state[2]),
        .O(wrReqR_i_2__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2684" *) 
  LUT3 #(
    .INIT(8'hC5)) 
    wrReqR_i_3__0
       (.I0(wrReqR_i_6__0_n_0),
        .I1(\txn_fifo_output_reg_n_0_[44] ),
        .I2(cas_fifo_empty_reg_n_0),
        .O(wrReqR_i_3__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2684" *) 
  LUT3 #(
    .INIT(8'hC5)) 
    wrReqR_i_4__0
       (.I0(wrReqR_i_7__0_n_0),
        .I1(\txn_fifo_output_reg_n_0_[45] ),
        .I2(cas_fifo_empty_reg_n_0),
        .O(wrReqR_i_4__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2624" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    wrReqR_i_5__0
       (.I0(\txn_fifo_output_reg_n_0_[46] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(wrReqR_i_8_n_0),
        .O(wrReqR_i_5__0_n_0));
  LUT6 #(
    .INIT(64'h3300550F33FF550F)) 
    wrReqR_i_6__0
       (.I0(\cas_pend_fifo_reg_n_0_[2][44] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][44] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][44] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][44] ),
        .O(wrReqR_i_6__0_n_0));
  LUT6 #(
    .INIT(64'h3300550F33FF550F)) 
    wrReqR_i_7__0
       (.I0(\cas_pend_fifo_reg_n_0_[2][45] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][45] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][45] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][45] ),
        .O(wrReqR_i_7__0_n_0));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    wrReqR_i_8
       (.I0(\cas_pend_fifo_reg_n_0_[2][46] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][46] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][46] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][46] ),
        .O(wrReqR_i_8_n_0));
  FDRE wrReqR_reg
       (.C(rst_r1_reg_0),
        .CE(1'b1),
        .D(wrReqR_i_1__1_n_0),
        .Q(wrReqR_reg_0),
        .R(rst_r1));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_group" *) 
module ddr4_0_ddr4_v2_2_17_mc_group_11
   (cmdAP,
    refOK_reg_0,
    accept_reg_0,
    wrReqR_reg_0,
    periodic_read_or_ref_block_reg_0,
    actReqR_reg_0,
    preReqR_reg_0,
    rdReqR_reg_0,
    cmdRmw_reg_0,
    cmd_group_cas,
    cmdGroupP,
    Q,
    \cmd_bank_cas_reg[1]_0 ,
    accept_ns,
    grAccept_ns,
    \txn_fifo_wptr_reg[0]_0 ,
    actReq,
    \buf_fifo_reg[0][0]_0 ,
    \buf_fifo_reg[0][1]_0 ,
    \buf_fifo_reg[0][2]_0 ,
    \buf_fifo_reg[2][3]_0 ,
    \buf_fifo_reg[0][4]_0 ,
    refOK_reg_1,
    cmdBuf,
    \cmdBankP_reg[1]_0 ,
    \cmdCol_reg[9]_0 ,
    \cmdGroupP_reg[0]_0 ,
    accept_reg_1,
    underfill_done_reg_0,
    refReq,
    SR,
    clrReq1,
    \cas_fifo_rptr_reg[0]_0 ,
    tranSentC,
    useAdr,
    \txn_fifo_wptr_reg[0]_1 ,
    \buf_fifo_reg[1][0]_0 ,
    \buf_fifo_reg[1][1]_0 ,
    \buf_fifo_reg[1][2]_0 ,
    \buf_fifo_reg[1][3]_0 ,
    \buf_fifo_reg[1][4]_0 ,
    cmd,
    row_mc_phy,
    col,
    group,
    bank,
    preReqR_reg_1,
    \FSM_sequential_grSt_reg[0]_0 ,
    ref_req_dly4,
    app_rdy_r_reg,
    \FSM_sequential_grSt_reg[0]_1 ,
    accept_reg_2,
    refOK,
    per_block_ref);
  output [0:0]cmdAP;
  output [0:0]refOK_reg_0;
  output accept_reg_0;
  output wrReqR_reg_0;
  output periodic_read_or_ref_block_reg_0;
  output actReqR_reg_0;
  output preReqR_reg_0;
  output rdReqR_reg_0;
  output cmdRmw_reg_0;
  output [0:0]cmd_group_cas;
  output [0:0]cmdGroupP;
  output [19:0]Q;
  output [1:0]\cmd_bank_cas_reg[1]_0 ;
  output accept_ns;
  output [0:0]grAccept_ns;
  output \txn_fifo_wptr_reg[0]_0 ;
  output [0:0]actReq;
  output \buf_fifo_reg[0][0]_0 ;
  output \buf_fifo_reg[0][1]_0 ;
  output \buf_fifo_reg[0][2]_0 ;
  output \buf_fifo_reg[2][3]_0 ;
  output \buf_fifo_reg[0][4]_0 ;
  output refOK_reg_1;
  output [4:0]cmdBuf;
  output [1:0]\cmdBankP_reg[1]_0 ;
  output [6:0]\cmdCol_reg[9]_0 ;
  input \cmdGroupP_reg[0]_0 ;
  input [0:0]accept_reg_1;
  input underfill_done_reg_0;
  input refReq;
  input [0:0]SR;
  input clrReq1;
  input [0:0]\cas_fifo_rptr_reg[0]_0 ;
  input tranSentC;
  input useAdr;
  input \txn_fifo_wptr_reg[0]_1 ;
  input \buf_fifo_reg[1][0]_0 ;
  input \buf_fifo_reg[1][1]_0 ;
  input \buf_fifo_reg[1][2]_0 ;
  input \buf_fifo_reg[1][3]_0 ;
  input \buf_fifo_reg[1][4]_0 ;
  input [2:0]cmd;
  input [16:0]row_mc_phy;
  input [6:0]col;
  input [0:0]group;
  input [1:0]bank;
  input [0:0]preReqR_reg_1;
  input [0:0]\FSM_sequential_grSt_reg[0]_0 ;
  input ref_req_dly4;
  input [1:0]app_rdy_r_reg;
  input \FSM_sequential_grSt_reg[0]_1 ;
  input accept_reg_2;
  input [2:0]refOK;
  input per_block_ref;

  wire \FSM_sequential_grSt[0]_i_1__0_n_0 ;
  wire \FSM_sequential_grSt[0]_i_2__0_n_0 ;
  wire \FSM_sequential_grSt[1]_i_1__0_n_0 ;
  wire \FSM_sequential_grSt[1]_i_2_n_0 ;
  wire \FSM_sequential_grSt[1]_i_3__0_n_0 ;
  wire \FSM_sequential_grSt[1]_i_4__1_n_0 ;
  wire \FSM_sequential_grSt[1]_i_5__1_n_0 ;
  wire \FSM_sequential_grSt[1]_i_6_n_0 ;
  wire \FSM_sequential_grSt[2]_i_1__1_n_0 ;
  wire \FSM_sequential_grSt[2]_i_2_n_0 ;
  wire \FSM_sequential_grSt[2]_i_3__1_n_0 ;
  wire \FSM_sequential_grSt[2]_i_4__1_n_0 ;
  wire \FSM_sequential_grSt[2]_i_5__1_n_0 ;
  wire \FSM_sequential_grSt[2]_i_6_n_0 ;
  wire \FSM_sequential_grSt[2]_i_7__0_n_0 ;
  wire [0:0]\FSM_sequential_grSt_reg[0]_0 ;
  wire \FSM_sequential_grSt_reg[0]_1 ;
  wire \FSM_sequential_gr_cas_state[2]_i_1__2_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_3__0_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_5__0_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_6__2_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_7_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_8__0_n_0 ;
  wire [19:0]Q;
  wire [0:0]SR;
  wire accept_ns;
  wire accept_reg_0;
  wire [0:0]accept_reg_1;
  wire accept_reg_2;
  wire [0:0]actReq;
  wire actReqR_i_1__0_n_0;
  wire actReqR_i_2_n_0;
  wire actReqR_i_3__0_n_0;
  wire actReqR_i_4__0_n_0;
  wire actReqR_reg_0;
  wire \ap_cntr[0][0][0][0]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][0][1]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][0][2]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][0][3]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][0][4]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][0][4]_i_2__2_n_0 ;
  wire \ap_cntr[0][0][1][0]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][1][1]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][1][2]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][1][3]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][1][4]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][1][4]_i_2__2_n_0 ;
  wire \ap_cntr[0][0][1][4]_i_3__1_n_0 ;
  wire \ap_cntr[0][0][2][0]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][2][1]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][2][2]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][2][3]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][2][4]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][2][4]_i_2__2_n_0 ;
  wire \ap_cntr[0][0][2][4]_i_3__1_n_0 ;
  wire \ap_cntr[0][0][3][0]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][3][1]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][3][2]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][3][3]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][3][4]_i_1__2_n_0 ;
  wire \ap_cntr[0][0][3][4]_i_2__2_n_0 ;
  wire \ap_cntr[0][0][3][4]_i_3__2_n_0 ;
  wire \ap_cntr_expired[0][0][0]_i_1_n_0 ;
  wire \ap_cntr_expired[0][0][1]_i_1__2_n_0 ;
  wire \ap_cntr_expired[0][0][2]_i_1__2_n_0 ;
  wire \ap_cntr_expired[0][0][3]_i_1__2_n_0 ;
  wire \ap_cntr_reg_n_0_[0][0][0][0] ;
  wire \ap_cntr_reg_n_0_[0][0][0][1] ;
  wire \ap_cntr_reg_n_0_[0][0][0][2] ;
  wire \ap_cntr_reg_n_0_[0][0][0][3] ;
  wire \ap_cntr_reg_n_0_[0][0][0][4] ;
  wire \ap_cntr_reg_n_0_[0][0][1][0] ;
  wire \ap_cntr_reg_n_0_[0][0][1][1] ;
  wire \ap_cntr_reg_n_0_[0][0][1][2] ;
  wire \ap_cntr_reg_n_0_[0][0][1][3] ;
  wire \ap_cntr_reg_n_0_[0][0][1][4] ;
  wire \ap_cntr_reg_n_0_[0][0][2][0] ;
  wire \ap_cntr_reg_n_0_[0][0][2][1] ;
  wire \ap_cntr_reg_n_0_[0][0][2][2] ;
  wire \ap_cntr_reg_n_0_[0][0][2][3] ;
  wire \ap_cntr_reg_n_0_[0][0][2][4] ;
  wire \ap_cntr_reg_n_0_[0][0][3][0] ;
  wire \ap_cntr_reg_n_0_[0][0][3][1] ;
  wire \ap_cntr_reg_n_0_[0][0][3][2] ;
  wire \ap_cntr_reg_n_0_[0][0][3][3] ;
  wire \ap_cntr_reg_n_0_[0][0][3][4] ;
  wire \ap_cntr_zero[0][0][0]_i_1__2_n_0 ;
  wire \ap_cntr_zero[0][0][0]_i_2__0_n_0 ;
  wire \ap_cntr_zero[0][0][0]_i_3_n_0 ;
  wire \ap_cntr_zero[0][0][0]_i_4_n_0 ;
  wire \ap_cntr_zero[0][0][1]_i_1__2_n_0 ;
  wire \ap_cntr_zero[0][0][2]_i_1__2_n_0 ;
  wire \ap_cntr_zero[0][0][3]_i_1__2_n_0 ;
  wire \ap_cntr_zero_reg_n_0_[0][0][0] ;
  wire \ap_cntr_zero_reg_n_0_[0][0][1] ;
  wire \ap_cntr_zero_reg_n_0_[0][0][2] ;
  wire \ap_cntr_zero_reg_n_0_[0][0][3] ;
  wire \ap_load_value[0]_i_1__2_n_0 ;
  wire \ap_load_value[0]_i_2__2_n_0 ;
  wire \ap_load_value[1]_i_1__2_n_0 ;
  wire \ap_load_value[2]_i_1__2_n_0 ;
  wire \ap_load_value[3]_i_1__2_n_0 ;
  wire \ap_load_value[3]_i_2__2_n_0 ;
  wire \ap_load_value[3]_i_3__2_n_0 ;
  wire \ap_load_value_reg_n_0_[0] ;
  wire \ap_load_value_reg_n_0_[1] ;
  wire \ap_load_value_reg_n_0_[2] ;
  wire \ap_load_value_reg_n_0_[3] ;
  wire [1:0]app_rdy_r_reg;
  wire [1:0]bank;
  wire \buf_fifo[0][0]_i_1_n_0 ;
  wire \buf_fifo[0][1]_i_1_n_0 ;
  wire \buf_fifo[0][2]_i_1_n_0 ;
  wire \buf_fifo[0][3]_i_1_n_0 ;
  wire \buf_fifo[0][4]_i_1_n_0 ;
  wire \buf_fifo[1][0]_i_1_n_0 ;
  wire \buf_fifo[1][1]_i_1_n_0 ;
  wire \buf_fifo[1][2]_i_1_n_0 ;
  wire \buf_fifo[1][3]_i_1_n_0 ;
  wire \buf_fifo[1][4]_i_1_n_0 ;
  wire \buf_fifo[2][0]_i_1_n_0 ;
  wire \buf_fifo[2][1]_i_1_n_0 ;
  wire \buf_fifo[2][2]_i_1_n_0 ;
  wire \buf_fifo[2][3]_i_1_n_0 ;
  wire \buf_fifo[2][4]_i_1_n_0 ;
  wire \buf_fifo[3][0]_i_1_n_0 ;
  wire \buf_fifo[3][1]_i_1_n_0 ;
  wire \buf_fifo[3][2]_i_1_n_0 ;
  wire \buf_fifo[3][3]_i_1_n_0 ;
  wire \buf_fifo[3][4]_i_1_n_0 ;
  wire \buf_fifo_reg[0][0]_0 ;
  wire \buf_fifo_reg[0][1]_0 ;
  wire \buf_fifo_reg[0][2]_0 ;
  wire \buf_fifo_reg[0][4]_0 ;
  wire \buf_fifo_reg[1][0]_0 ;
  wire \buf_fifo_reg[1][1]_0 ;
  wire \buf_fifo_reg[1][2]_0 ;
  wire \buf_fifo_reg[1][3]_0 ;
  wire \buf_fifo_reg[1][4]_0 ;
  wire \buf_fifo_reg[2][3]_0 ;
  wire \buf_fifo_reg_n_0_[0][0] ;
  wire \buf_fifo_reg_n_0_[0][1] ;
  wire \buf_fifo_reg_n_0_[0][2] ;
  wire \buf_fifo_reg_n_0_[0][3] ;
  wire \buf_fifo_reg_n_0_[0][4] ;
  wire \buf_fifo_reg_n_0_[1][0] ;
  wire \buf_fifo_reg_n_0_[1][1] ;
  wire \buf_fifo_reg_n_0_[1][2] ;
  wire \buf_fifo_reg_n_0_[1][3] ;
  wire \buf_fifo_reg_n_0_[1][4] ;
  wire \buf_fifo_reg_n_0_[2][0] ;
  wire \buf_fifo_reg_n_0_[2][1] ;
  wire \buf_fifo_reg_n_0_[2][2] ;
  wire \buf_fifo_reg_n_0_[2][3] ;
  wire \buf_fifo_reg_n_0_[2][4] ;
  wire \buf_fifo_reg_n_0_[3][0] ;
  wire \buf_fifo_reg_n_0_[3][1] ;
  wire \buf_fifo_reg_n_0_[3][2] ;
  wire \buf_fifo_reg_n_0_[3][3] ;
  wire \buf_fifo_reg_n_0_[3][4] ;
  wire \cas_dbuf_fifo[0][0]_i_1_n_0 ;
  wire \cas_dbuf_fifo[0][1]_i_1_n_0 ;
  wire \cas_dbuf_fifo[0][2]_i_1_n_0 ;
  wire \cas_dbuf_fifo[0][3]_i_1_n_0 ;
  wire \cas_dbuf_fifo[0][4]_i_1_n_0 ;
  wire \cas_dbuf_fifo_reg_n_0_[0][0] ;
  wire \cas_dbuf_fifo_reg_n_0_[0][1] ;
  wire \cas_dbuf_fifo_reg_n_0_[0][2] ;
  wire \cas_dbuf_fifo_reg_n_0_[0][3] ;
  wire \cas_dbuf_fifo_reg_n_0_[0][4] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][0] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][1] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][2] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][3] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][4] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][0] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][1] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][2] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][3] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][4] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][0] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][1] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][2] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][3] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][4] ;
  wire cas_fifo_empty_i_1__2_n_0;
  wire cas_fifo_empty_reg_n_0;
  wire cas_fifo_full_i_1__2_n_0;
  wire cas_fifo_full_reg_n_0;
  wire \cas_fifo_rptr[0]_i_1__2_n_0 ;
  wire \cas_fifo_rptr[1]_i_1__2_n_0 ;
  wire \cas_fifo_rptr[1]_i_2__2_n_0 ;
  wire [0:0]\cas_fifo_rptr_reg[0]_0 ;
  wire \cas_fifo_rptr_reg_n_0_[0] ;
  wire \cas_fifo_rptr_reg_n_0_[1] ;
  wire \cas_fifo_valid[0]_i_1__2_n_0 ;
  wire \cas_fifo_valid[0]_i_2__2_n_0 ;
  wire \cas_fifo_valid[1]_i_1__2_n_0 ;
  wire \cas_fifo_valid[1]_i_2__2_n_0 ;
  wire \cas_fifo_valid[2]_i_1__2_n_0 ;
  wire \cas_fifo_valid[2]_i_2__2_n_0 ;
  wire \cas_fifo_valid[3]_i_1__2_n_0 ;
  wire \cas_fifo_valid[3]_i_2__2_n_0 ;
  wire \cas_fifo_valid_reg_n_0_[0] ;
  wire \cas_fifo_valid_reg_n_0_[1] ;
  wire \cas_fifo_valid_reg_n_0_[2] ;
  wire \cas_fifo_valid_reg_n_0_[3] ;
  wire \cas_fifo_wptr[0]_i_1__0_n_0 ;
  wire \cas_fifo_wptr[1]_i_1__0_n_0 ;
  wire \cas_fifo_wptr_reg_n_0_[0] ;
  wire \cas_fifo_wptr_reg_n_0_[1] ;
  wire \cas_pend_fifo[0][47]_i_1__1_n_0 ;
  wire \cas_pend_fifo[1][47]_i_1__1_n_0 ;
  wire \cas_pend_fifo[2][47]_i_1__1_n_0 ;
  wire \cas_pend_fifo[3][47]_i_1__1_n_0 ;
  wire \cas_pend_fifo_reg_n_0_[0][0] ;
  wire \cas_pend_fifo_reg_n_0_[0][11] ;
  wire \cas_pend_fifo_reg_n_0_[0][12] ;
  wire \cas_pend_fifo_reg_n_0_[0][13] ;
  wire \cas_pend_fifo_reg_n_0_[0][14] ;
  wire \cas_pend_fifo_reg_n_0_[0][15] ;
  wire \cas_pend_fifo_reg_n_0_[0][16] ;
  wire \cas_pend_fifo_reg_n_0_[0][17] ;
  wire \cas_pend_fifo_reg_n_0_[0][1] ;
  wire \cas_pend_fifo_reg_n_0_[0][24] ;
  wire \cas_pend_fifo_reg_n_0_[0][25] ;
  wire \cas_pend_fifo_reg_n_0_[0][26] ;
  wire \cas_pend_fifo_reg_n_0_[0][27] ;
  wire \cas_pend_fifo_reg_n_0_[0][28] ;
  wire \cas_pend_fifo_reg_n_0_[0][29] ;
  wire \cas_pend_fifo_reg_n_0_[0][2] ;
  wire \cas_pend_fifo_reg_n_0_[0][30] ;
  wire \cas_pend_fifo_reg_n_0_[0][31] ;
  wire \cas_pend_fifo_reg_n_0_[0][32] ;
  wire \cas_pend_fifo_reg_n_0_[0][33] ;
  wire \cas_pend_fifo_reg_n_0_[0][34] ;
  wire \cas_pend_fifo_reg_n_0_[0][35] ;
  wire \cas_pend_fifo_reg_n_0_[0][36] ;
  wire \cas_pend_fifo_reg_n_0_[0][37] ;
  wire \cas_pend_fifo_reg_n_0_[0][38] ;
  wire \cas_pend_fifo_reg_n_0_[0][39] ;
  wire \cas_pend_fifo_reg_n_0_[0][40] ;
  wire \cas_pend_fifo_reg_n_0_[0][44] ;
  wire \cas_pend_fifo_reg_n_0_[0][45] ;
  wire \cas_pend_fifo_reg_n_0_[0][46] ;
  wire \cas_pend_fifo_reg_n_0_[0][47] ;
  wire \cas_pend_fifo_reg_n_0_[1][0] ;
  wire \cas_pend_fifo_reg_n_0_[1][11] ;
  wire \cas_pend_fifo_reg_n_0_[1][12] ;
  wire \cas_pend_fifo_reg_n_0_[1][13] ;
  wire \cas_pend_fifo_reg_n_0_[1][14] ;
  wire \cas_pend_fifo_reg_n_0_[1][15] ;
  wire \cas_pend_fifo_reg_n_0_[1][16] ;
  wire \cas_pend_fifo_reg_n_0_[1][17] ;
  wire \cas_pend_fifo_reg_n_0_[1][1] ;
  wire \cas_pend_fifo_reg_n_0_[1][24] ;
  wire \cas_pend_fifo_reg_n_0_[1][25] ;
  wire \cas_pend_fifo_reg_n_0_[1][26] ;
  wire \cas_pend_fifo_reg_n_0_[1][27] ;
  wire \cas_pend_fifo_reg_n_0_[1][28] ;
  wire \cas_pend_fifo_reg_n_0_[1][29] ;
  wire \cas_pend_fifo_reg_n_0_[1][2] ;
  wire \cas_pend_fifo_reg_n_0_[1][30] ;
  wire \cas_pend_fifo_reg_n_0_[1][31] ;
  wire \cas_pend_fifo_reg_n_0_[1][32] ;
  wire \cas_pend_fifo_reg_n_0_[1][33] ;
  wire \cas_pend_fifo_reg_n_0_[1][34] ;
  wire \cas_pend_fifo_reg_n_0_[1][35] ;
  wire \cas_pend_fifo_reg_n_0_[1][36] ;
  wire \cas_pend_fifo_reg_n_0_[1][37] ;
  wire \cas_pend_fifo_reg_n_0_[1][38] ;
  wire \cas_pend_fifo_reg_n_0_[1][39] ;
  wire \cas_pend_fifo_reg_n_0_[1][40] ;
  wire \cas_pend_fifo_reg_n_0_[1][44] ;
  wire \cas_pend_fifo_reg_n_0_[1][45] ;
  wire \cas_pend_fifo_reg_n_0_[1][46] ;
  wire \cas_pend_fifo_reg_n_0_[1][47] ;
  wire \cas_pend_fifo_reg_n_0_[2][0] ;
  wire \cas_pend_fifo_reg_n_0_[2][11] ;
  wire \cas_pend_fifo_reg_n_0_[2][12] ;
  wire \cas_pend_fifo_reg_n_0_[2][13] ;
  wire \cas_pend_fifo_reg_n_0_[2][14] ;
  wire \cas_pend_fifo_reg_n_0_[2][15] ;
  wire \cas_pend_fifo_reg_n_0_[2][16] ;
  wire \cas_pend_fifo_reg_n_0_[2][17] ;
  wire \cas_pend_fifo_reg_n_0_[2][1] ;
  wire \cas_pend_fifo_reg_n_0_[2][24] ;
  wire \cas_pend_fifo_reg_n_0_[2][25] ;
  wire \cas_pend_fifo_reg_n_0_[2][26] ;
  wire \cas_pend_fifo_reg_n_0_[2][27] ;
  wire \cas_pend_fifo_reg_n_0_[2][28] ;
  wire \cas_pend_fifo_reg_n_0_[2][29] ;
  wire \cas_pend_fifo_reg_n_0_[2][2] ;
  wire \cas_pend_fifo_reg_n_0_[2][30] ;
  wire \cas_pend_fifo_reg_n_0_[2][31] ;
  wire \cas_pend_fifo_reg_n_0_[2][32] ;
  wire \cas_pend_fifo_reg_n_0_[2][33] ;
  wire \cas_pend_fifo_reg_n_0_[2][34] ;
  wire \cas_pend_fifo_reg_n_0_[2][35] ;
  wire \cas_pend_fifo_reg_n_0_[2][36] ;
  wire \cas_pend_fifo_reg_n_0_[2][37] ;
  wire \cas_pend_fifo_reg_n_0_[2][38] ;
  wire \cas_pend_fifo_reg_n_0_[2][39] ;
  wire \cas_pend_fifo_reg_n_0_[2][40] ;
  wire \cas_pend_fifo_reg_n_0_[2][44] ;
  wire \cas_pend_fifo_reg_n_0_[2][45] ;
  wire \cas_pend_fifo_reg_n_0_[2][46] ;
  wire \cas_pend_fifo_reg_n_0_[2][47] ;
  wire \cas_pend_fifo_reg_n_0_[3][0] ;
  wire \cas_pend_fifo_reg_n_0_[3][11] ;
  wire \cas_pend_fifo_reg_n_0_[3][12] ;
  wire \cas_pend_fifo_reg_n_0_[3][13] ;
  wire \cas_pend_fifo_reg_n_0_[3][14] ;
  wire \cas_pend_fifo_reg_n_0_[3][15] ;
  wire \cas_pend_fifo_reg_n_0_[3][16] ;
  wire \cas_pend_fifo_reg_n_0_[3][17] ;
  wire \cas_pend_fifo_reg_n_0_[3][1] ;
  wire \cas_pend_fifo_reg_n_0_[3][24] ;
  wire \cas_pend_fifo_reg_n_0_[3][25] ;
  wire \cas_pend_fifo_reg_n_0_[3][26] ;
  wire \cas_pend_fifo_reg_n_0_[3][27] ;
  wire \cas_pend_fifo_reg_n_0_[3][28] ;
  wire \cas_pend_fifo_reg_n_0_[3][29] ;
  wire \cas_pend_fifo_reg_n_0_[3][2] ;
  wire \cas_pend_fifo_reg_n_0_[3][30] ;
  wire \cas_pend_fifo_reg_n_0_[3][31] ;
  wire \cas_pend_fifo_reg_n_0_[3][32] ;
  wire \cas_pend_fifo_reg_n_0_[3][33] ;
  wire \cas_pend_fifo_reg_n_0_[3][34] ;
  wire \cas_pend_fifo_reg_n_0_[3][35] ;
  wire \cas_pend_fifo_reg_n_0_[3][36] ;
  wire \cas_pend_fifo_reg_n_0_[3][37] ;
  wire \cas_pend_fifo_reg_n_0_[3][38] ;
  wire \cas_pend_fifo_reg_n_0_[3][39] ;
  wire \cas_pend_fifo_reg_n_0_[3][40] ;
  wire \cas_pend_fifo_reg_n_0_[3][44] ;
  wire \cas_pend_fifo_reg_n_0_[3][45] ;
  wire \cas_pend_fifo_reg_n_0_[3][46] ;
  wire \cas_pend_fifo_reg_n_0_[3][47] ;
  wire clrReq1;
  wire [2:0]cmd;
  wire [0:0]cmdAP;
  wire cmdAP_i_1__2_n_0;
  wire cmdAP_i_2__2_n_0;
  wire \cmdBankP[1]_i_1__1_n_0 ;
  wire \cmdBankP[1]_i_2_n_0 ;
  wire \cmdBankP[1]_i_3__0_n_0 ;
  wire \cmdBankP[1]_i_4__1_n_0 ;
  wire \cmdBankP[1]_i_5__1_n_0 ;
  wire \cmdBankP[1]_i_6__1_n_0 ;
  wire [1:0]\cmdBankP_reg[1]_0 ;
  wire [4:0]cmdBuf;
  wire \cmdBuf[0]_i_1__2_n_0 ;
  wire \cmdBuf[1]_i_1__2_n_0 ;
  wire \cmdBuf[2]_i_1__2_n_0 ;
  wire \cmdBuf[3]_i_1__2_n_0 ;
  wire \cmdBuf[4]_i_1__2_n_0 ;
  wire \cmdCol[3]_i_1__2_n_0 ;
  wire \cmdCol[3]_i_2__2_n_0 ;
  wire \cmdCol[4]_i_1__2_n_0 ;
  wire \cmdCol[4]_i_2__2_n_0 ;
  wire \cmdCol[5]_i_1__2_n_0 ;
  wire \cmdCol[5]_i_2__2_n_0 ;
  wire \cmdCol[6]_i_1__2_n_0 ;
  wire \cmdCol[6]_i_2__2_n_0 ;
  wire \cmdCol[7]_i_1__2_n_0 ;
  wire \cmdCol[7]_i_2__2_n_0 ;
  wire \cmdCol[8]_i_1__2_n_0 ;
  wire \cmdCol[8]_i_2__2_n_0 ;
  wire \cmdCol[9]_i_1__2_n_0 ;
  wire \cmdCol[9]_i_2__2_n_0 ;
  wire [6:0]\cmdCol_reg[9]_0 ;
  wire [0:0]cmdGroupP;
  wire \cmdGroupP_reg[0]_0 ;
  wire cmdRmw_i_1__2_n_0;
  wire cmdRmw_reg_0;
  wire \cmd_bank_cas[0]_i_1__2_n_0 ;
  wire \cmd_bank_cas[0]_i_2__2_n_0 ;
  wire \cmd_bank_cas[0]_i_3__0_n_0 ;
  wire \cmd_bank_cas[1]_i_1__2_n_0 ;
  wire \cmd_bank_cas[1]_i_2__2_n_0 ;
  wire [1:0]\cmd_bank_cas_reg[1]_0 ;
  wire [0:0]cmd_group_cas;
  wire \cmd_group_cas[0]_i_1__2_n_0 ;
  wire \cmd_group_cas[0]_i_2__2_n_0 ;
  wire \cmd_row_cas[0]_i_1__2_n_0 ;
  wire \cmd_row_cas[0]_i_2__2_n_0 ;
  wire \cmd_row_cas[10]_i_1__2_n_0 ;
  wire \cmd_row_cas[10]_i_2__2_n_0 ;
  wire \cmd_row_cas[11]_i_1__2_n_0 ;
  wire \cmd_row_cas[11]_i_2__2_n_0 ;
  wire \cmd_row_cas[12]_i_1__2_n_0 ;
  wire \cmd_row_cas[12]_i_2__2_n_0 ;
  wire \cmd_row_cas[13]_i_1__2_n_0 ;
  wire \cmd_row_cas[13]_i_2__2_n_0 ;
  wire \cmd_row_cas[14]_i_1__2_n_0 ;
  wire \cmd_row_cas[14]_i_2__2_n_0 ;
  wire \cmd_row_cas[15]_i_1__2_n_0 ;
  wire \cmd_row_cas[15]_i_2__2_n_0 ;
  wire \cmd_row_cas[16]_i_1__2_n_0 ;
  wire \cmd_row_cas[16]_i_2__2_n_0 ;
  wire \cmd_row_cas[1]_i_1__2_n_0 ;
  wire \cmd_row_cas[1]_i_2__2_n_0 ;
  wire \cmd_row_cas[2]_i_1__2_n_0 ;
  wire \cmd_row_cas[2]_i_2__2_n_0 ;
  wire \cmd_row_cas[3]_i_1__2_n_0 ;
  wire \cmd_row_cas[3]_i_2__2_n_0 ;
  wire \cmd_row_cas[4]_i_1__2_n_0 ;
  wire \cmd_row_cas[4]_i_2__2_n_0 ;
  wire \cmd_row_cas[5]_i_1__2_n_0 ;
  wire \cmd_row_cas[5]_i_2__2_n_0 ;
  wire \cmd_row_cas[6]_i_1__2_n_0 ;
  wire \cmd_row_cas[6]_i_2__2_n_0 ;
  wire \cmd_row_cas[7]_i_1__2_n_0 ;
  wire \cmd_row_cas[7]_i_2__2_n_0 ;
  wire \cmd_row_cas[8]_i_1__2_n_0 ;
  wire \cmd_row_cas[8]_i_2__2_n_0 ;
  wire \cmd_row_cas[9]_i_1__2_n_0 ;
  wire \cmd_row_cas[9]_i_2__2_n_0 ;
  wire \cmd_row_cas_reg_n_0_[0] ;
  wire \cmd_row_cas_reg_n_0_[10] ;
  wire \cmd_row_cas_reg_n_0_[11] ;
  wire \cmd_row_cas_reg_n_0_[12] ;
  wire \cmd_row_cas_reg_n_0_[13] ;
  wire \cmd_row_cas_reg_n_0_[14] ;
  wire \cmd_row_cas_reg_n_0_[15] ;
  wire \cmd_row_cas_reg_n_0_[16] ;
  wire \cmd_row_cas_reg_n_0_[1] ;
  wire \cmd_row_cas_reg_n_0_[2] ;
  wire \cmd_row_cas_reg_n_0_[3] ;
  wire \cmd_row_cas_reg_n_0_[4] ;
  wire \cmd_row_cas_reg_n_0_[5] ;
  wire \cmd_row_cas_reg_n_0_[6] ;
  wire \cmd_row_cas_reg_n_0_[7] ;
  wire \cmd_row_cas_reg_n_0_[8] ;
  wire \cmd_row_cas_reg_n_0_[9] ;
  wire [6:0]col;
  wire [0:0]grAccept_ns;
  wire [2:0]grSt;
  wire [2:0]gr_cas_state;
  wire [2:0]gr_cas_state_nxt;
  wire [0:0]group;
  wire i__carry_i_10__2_n_0;
  wire i__carry_i_11__2_n_0;
  wire i__carry_i_12__2_n_0;
  wire i__carry_i_13__2_n_0;
  wire i__carry_i_14__2_n_0;
  wire i__carry_i_15__2_n_0;
  wire i__carry_i_16__2_n_0;
  wire i__carry_i_17__2_n_0;
  wire i__carry_i_18__2_n_0;
  wire i__carry_i_19__2_n_0;
  wire i__carry_i_1__2_n_0;
  wire i__carry_i_20__2_n_0;
  wire i__carry_i_21__2_n_0;
  wire i__carry_i_22__2_n_0;
  wire i__carry_i_23__2_n_0;
  wire i__carry_i_2__2_n_0;
  wire i__carry_i_3__2_n_0;
  wire i__carry_i_4__2_n_0;
  wire i__carry_i_5__2_n_0;
  wire i__carry_i_6__2_n_0;
  wire i__carry_i_7__2_n_0;
  wire i__carry_i_8__2_n_0;
  wire i__carry_i_9__2_n_0;
  wire \issue_cas3_inferred__0/i__carry_n_2 ;
  wire \issue_cas3_inferred__0/i__carry_n_3 ;
  wire \issue_cas3_inferred__0/i__carry_n_4 ;
  wire \issue_cas3_inferred__0/i__carry_n_5 ;
  wire \issue_cas3_inferred__0/i__carry_n_6 ;
  wire \issue_cas3_inferred__0/i__carry_n_7 ;
  wire \pageInfo[0][0][0][0]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][0]_i_2__2_n_0 ;
  wire \pageInfo[0][0][0][0]_i_3__2_n_0 ;
  wire \pageInfo[0][0][0][10]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][11]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][12]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][13]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][14]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][15]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][16]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][17]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][18]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][18]_i_2__2_n_0 ;
  wire \pageInfo[0][0][0][1]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][2]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][3]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][4]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][5]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][6]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][7]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][8]_i_1__2_n_0 ;
  wire \pageInfo[0][0][0][9]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][0]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][0]_i_2__2_n_0 ;
  wire \pageInfo[0][0][1][10]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][11]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][12]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][13]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][14]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][15]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][16]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][17]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][18]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][18]_i_2__2_n_0 ;
  wire \pageInfo[0][0][1][1]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][2]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][3]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][4]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][5]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][6]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][7]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][8]_i_1__2_n_0 ;
  wire \pageInfo[0][0][1][9]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][0]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][0]_i_2__1_n_0 ;
  wire \pageInfo[0][0][2][0]_i_3__1_n_0 ;
  wire \pageInfo[0][0][2][10]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][11]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][12]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][13]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][14]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][15]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][16]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][17]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][18]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][18]_i_2__2_n_0 ;
  wire \pageInfo[0][0][2][1]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][2]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][3]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][4]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][5]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][6]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][7]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][8]_i_1__2_n_0 ;
  wire \pageInfo[0][0][2][9]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][0]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][0]_i_2__2_n_0 ;
  wire \pageInfo[0][0][3][0]_i_3_n_0 ;
  wire \pageInfo[0][0][3][10]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][11]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][12]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][13]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][14]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][15]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][16]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][17]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][18]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][18]_i_2__2_n_0 ;
  wire \pageInfo[0][0][3][18]_i_3__2_n_0 ;
  wire \pageInfo[0][0][3][1]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][2]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][3]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][4]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][5]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][6]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][7]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][8]_i_1__2_n_0 ;
  wire \pageInfo[0][0][3][9]_i_1__2_n_0 ;
  wire \pageInfo_reg_n_0_[0][0][0][0] ;
  wire \pageInfo_reg_n_0_[0][0][0][10] ;
  wire \pageInfo_reg_n_0_[0][0][0][11] ;
  wire \pageInfo_reg_n_0_[0][0][0][12] ;
  wire \pageInfo_reg_n_0_[0][0][0][13] ;
  wire \pageInfo_reg_n_0_[0][0][0][14] ;
  wire \pageInfo_reg_n_0_[0][0][0][15] ;
  wire \pageInfo_reg_n_0_[0][0][0][16] ;
  wire \pageInfo_reg_n_0_[0][0][0][17] ;
  wire \pageInfo_reg_n_0_[0][0][0][18] ;
  wire \pageInfo_reg_n_0_[0][0][0][1] ;
  wire \pageInfo_reg_n_0_[0][0][0][2] ;
  wire \pageInfo_reg_n_0_[0][0][0][3] ;
  wire \pageInfo_reg_n_0_[0][0][0][4] ;
  wire \pageInfo_reg_n_0_[0][0][0][5] ;
  wire \pageInfo_reg_n_0_[0][0][0][6] ;
  wire \pageInfo_reg_n_0_[0][0][0][7] ;
  wire \pageInfo_reg_n_0_[0][0][0][8] ;
  wire \pageInfo_reg_n_0_[0][0][0][9] ;
  wire \pageInfo_reg_n_0_[0][0][1][0] ;
  wire \pageInfo_reg_n_0_[0][0][1][10] ;
  wire \pageInfo_reg_n_0_[0][0][1][11] ;
  wire \pageInfo_reg_n_0_[0][0][1][12] ;
  wire \pageInfo_reg_n_0_[0][0][1][13] ;
  wire \pageInfo_reg_n_0_[0][0][1][14] ;
  wire \pageInfo_reg_n_0_[0][0][1][15] ;
  wire \pageInfo_reg_n_0_[0][0][1][16] ;
  wire \pageInfo_reg_n_0_[0][0][1][17] ;
  wire \pageInfo_reg_n_0_[0][0][1][18] ;
  wire \pageInfo_reg_n_0_[0][0][1][1] ;
  wire \pageInfo_reg_n_0_[0][0][1][2] ;
  wire \pageInfo_reg_n_0_[0][0][1][3] ;
  wire \pageInfo_reg_n_0_[0][0][1][4] ;
  wire \pageInfo_reg_n_0_[0][0][1][5] ;
  wire \pageInfo_reg_n_0_[0][0][1][6] ;
  wire \pageInfo_reg_n_0_[0][0][1][7] ;
  wire \pageInfo_reg_n_0_[0][0][1][8] ;
  wire \pageInfo_reg_n_0_[0][0][1][9] ;
  wire \pageInfo_reg_n_0_[0][0][2][0] ;
  wire \pageInfo_reg_n_0_[0][0][2][10] ;
  wire \pageInfo_reg_n_0_[0][0][2][11] ;
  wire \pageInfo_reg_n_0_[0][0][2][12] ;
  wire \pageInfo_reg_n_0_[0][0][2][13] ;
  wire \pageInfo_reg_n_0_[0][0][2][14] ;
  wire \pageInfo_reg_n_0_[0][0][2][15] ;
  wire \pageInfo_reg_n_0_[0][0][2][16] ;
  wire \pageInfo_reg_n_0_[0][0][2][17] ;
  wire \pageInfo_reg_n_0_[0][0][2][18] ;
  wire \pageInfo_reg_n_0_[0][0][2][1] ;
  wire \pageInfo_reg_n_0_[0][0][2][2] ;
  wire \pageInfo_reg_n_0_[0][0][2][3] ;
  wire \pageInfo_reg_n_0_[0][0][2][4] ;
  wire \pageInfo_reg_n_0_[0][0][2][5] ;
  wire \pageInfo_reg_n_0_[0][0][2][6] ;
  wire \pageInfo_reg_n_0_[0][0][2][7] ;
  wire \pageInfo_reg_n_0_[0][0][2][8] ;
  wire \pageInfo_reg_n_0_[0][0][2][9] ;
  wire \pageInfo_reg_n_0_[0][0][3][0] ;
  wire \pageInfo_reg_n_0_[0][0][3][10] ;
  wire \pageInfo_reg_n_0_[0][0][3][11] ;
  wire \pageInfo_reg_n_0_[0][0][3][12] ;
  wire \pageInfo_reg_n_0_[0][0][3][13] ;
  wire \pageInfo_reg_n_0_[0][0][3][14] ;
  wire \pageInfo_reg_n_0_[0][0][3][15] ;
  wire \pageInfo_reg_n_0_[0][0][3][16] ;
  wire \pageInfo_reg_n_0_[0][0][3][17] ;
  wire \pageInfo_reg_n_0_[0][0][3][18] ;
  wire \pageInfo_reg_n_0_[0][0][3][1] ;
  wire \pageInfo_reg_n_0_[0][0][3][2] ;
  wire \pageInfo_reg_n_0_[0][0][3][3] ;
  wire \pageInfo_reg_n_0_[0][0][3][4] ;
  wire \pageInfo_reg_n_0_[0][0][3][5] ;
  wire \pageInfo_reg_n_0_[0][0][3][6] ;
  wire \pageInfo_reg_n_0_[0][0][3][7] ;
  wire \pageInfo_reg_n_0_[0][0][3][8] ;
  wire \pageInfo_reg_n_0_[0][0][3][9] ;
  wire per_block_ref;
  wire periodic_read_or_ref_block_reg_0;
  wire preReqR_i_1_n_0;
  wire preReqR_i_2_n_0;
  wire preReqR_reg_0;
  wire [0:0]preReqR_reg_1;
  wire rdReqR_i_1__2_n_0;
  wire rdReqR_i_2__2_n_0;
  wire rdReqR_reg_0;
  wire [2:0]refOK;
  wire refOK_i_1__2_n_0;
  wire [0:0]refOK_reg_0;
  wire refOK_reg_1;
  wire refReq;
  wire ref_req_dly4;
  wire [16:0]row_mc_phy;
  (* RTL_KEEP = "true" *) wire rst_r1;
  wire [1:1]sel0__50;
  wire [1:1]sel0__54;
  wire [1:1]sel0__58;
  wire [1:1]sel0__62;
  wire tranSentC;
  wire \tras_cntr_rb[0][0][0][0]_i_1__2_n_0 ;
  wire \tras_cntr_rb[0][0][0][1]_i_1__2_n_0 ;
  wire \tras_cntr_rb[0][0][0][2]_i_1__2_n_0 ;
  wire \tras_cntr_rb[0][0][1][0]_i_1__2_n_0 ;
  wire \tras_cntr_rb[0][0][1][1]_i_1__2_n_0 ;
  wire \tras_cntr_rb[0][0][1][2]_i_1__2_n_0 ;
  wire \tras_cntr_rb[0][0][2][0]_i_1__2_n_0 ;
  wire \tras_cntr_rb[0][0][2][1]_i_1__2_n_0 ;
  wire \tras_cntr_rb[0][0][2][2]_i_1__2_n_0 ;
  wire \tras_cntr_rb[0][0][3][0]_i_1__2_n_0 ;
  wire \tras_cntr_rb[0][0][3][1]_i_1__2_n_0 ;
  wire \tras_cntr_rb[0][0][3][2]_i_1__2_n_0 ;
  wire \tras_cntr_rb_reg_n_0_[0][0][0][0] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][0][1] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][0][2] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][1][0] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][1][1] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][1][2] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][2][0] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][2][1] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][2][2] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][3][0] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][3][1] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][3][2] ;
  wire \trcd_cntr[0][0][0][0]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][0][1]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][0][2]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][0][2]_i_2__2_n_0 ;
  wire \trcd_cntr[0][0][0][3]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][1][0]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][1][1]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][1][2]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][1][2]_i_2__2_n_0 ;
  wire \trcd_cntr[0][0][1][3]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][2][0]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][2][1]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][2][2]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][2][2]_i_2__2_n_0 ;
  wire \trcd_cntr[0][0][2][3]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][3][0]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][3][1]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][3][2]_i_1__2_n_0 ;
  wire \trcd_cntr[0][0][3][2]_i_2__2_n_0 ;
  wire \trcd_cntr[0][0][3][3]_i_1__2_n_0 ;
  wire \trcd_cntr_is_zero[0][0][0]_i_1__2_n_0 ;
  wire \trcd_cntr_is_zero[0][0][0]_i_2__2_n_0 ;
  wire \trcd_cntr_is_zero[0][0][1]_i_1__2_n_0 ;
  wire \trcd_cntr_is_zero[0][0][1]_i_2__2_n_0 ;
  wire \trcd_cntr_is_zero[0][0][2]_i_1__2_n_0 ;
  wire \trcd_cntr_is_zero[0][0][2]_i_2__2_n_0 ;
  wire \trcd_cntr_is_zero[0][0][3]_i_1__2_n_0 ;
  wire \trcd_cntr_is_zero[0][0][3]_i_2__2_n_0 ;
  wire \trcd_cntr_is_zero_reg_n_0_[0][0][0] ;
  wire \trcd_cntr_is_zero_reg_n_0_[0][0][1] ;
  wire \trcd_cntr_is_zero_reg_n_0_[0][0][2] ;
  wire \trcd_cntr_is_zero_reg_n_0_[0][0][3] ;
  wire \trcd_cntr_reg_n_0_[0][0][0][0] ;
  wire \trcd_cntr_reg_n_0_[0][0][0][1] ;
  wire \trcd_cntr_reg_n_0_[0][0][0][2] ;
  wire \trcd_cntr_reg_n_0_[0][0][0][3] ;
  wire \trcd_cntr_reg_n_0_[0][0][1][0] ;
  wire \trcd_cntr_reg_n_0_[0][0][1][1] ;
  wire \trcd_cntr_reg_n_0_[0][0][1][2] ;
  wire \trcd_cntr_reg_n_0_[0][0][1][3] ;
  wire \trcd_cntr_reg_n_0_[0][0][2][0] ;
  wire \trcd_cntr_reg_n_0_[0][0][2][1] ;
  wire \trcd_cntr_reg_n_0_[0][0][2][2] ;
  wire \trcd_cntr_reg_n_0_[0][0][2][3] ;
  wire \trcd_cntr_reg_n_0_[0][0][3][0] ;
  wire \trcd_cntr_reg_n_0_[0][0][3][1] ;
  wire \trcd_cntr_reg_n_0_[0][0][3][2] ;
  wire \trcd_cntr_reg_n_0_[0][0][3][3] ;
  wire \trp_cntr[0]_i_1__2_n_0 ;
  wire \trp_cntr[0]_i_2__2_n_0 ;
  wire \trp_cntr[1]_i_1__2_n_0 ;
  wire \trp_cntr[1]_i_2__2_n_0 ;
  wire \trp_cntr[1]_i_3__2_n_0 ;
  wire \trp_cntr[2]_i_1__2_n_0 ;
  wire \trp_cntr[2]_i_2__2_n_0 ;
  wire \trp_cntr[2]_i_3__1_n_0 ;
  wire \trp_cntr[2]_i_4_n_0 ;
  wire \trp_cntr[3]_i_1__2_n_0 ;
  wire \trp_cntr[3]_i_2__2_n_0 ;
  wire \trp_cntr[3]_i_3__2_n_0 ;
  wire \trp_cntr[4]_i_1__2_n_0 ;
  wire \trp_cntr[4]_i_2__2_n_0 ;
  wire \trp_cntr[4]_i_3__2_n_0 ;
  wire trp_cntr_is_zero_i_1__2_n_0;
  wire trp_cntr_is_zero_reg_n_0;
  wire \trp_cntr_reg_n_0_[0] ;
  wire \trp_cntr_reg_n_0_[1] ;
  wire \trp_cntr_reg_n_0_[2] ;
  wire \trp_cntr_reg_n_0_[3] ;
  wire \trp_cntr_reg_n_0_[4] ;
  wire \txn_fifo[0][0]_i_1__0_n_0 ;
  wire \txn_fifo[0][11]_i_1__0_n_0 ;
  wire \txn_fifo[0][12]_i_1__0_n_0 ;
  wire \txn_fifo[0][13]_i_1__0_n_0 ;
  wire \txn_fifo[0][14]_i_1__0_n_0 ;
  wire \txn_fifo[0][15]_i_1__0_n_0 ;
  wire \txn_fifo[0][16]_i_1__0_n_0 ;
  wire \txn_fifo[0][17]_i_1__0_n_0 ;
  wire \txn_fifo[0][1]_i_1__0_n_0 ;
  wire \txn_fifo[0][24]_i_1__0_n_0 ;
  wire \txn_fifo[0][25]_i_1__0_n_0 ;
  wire \txn_fifo[0][26]_i_1__0_n_0 ;
  wire \txn_fifo[0][27]_i_1__0_n_0 ;
  wire \txn_fifo[0][28]_i_1__0_n_0 ;
  wire \txn_fifo[0][29]_i_1__0_n_0 ;
  wire \txn_fifo[0][2]_i_1__0_n_0 ;
  wire \txn_fifo[0][30]_i_1__0_n_0 ;
  wire \txn_fifo[0][31]_i_1__0_n_0 ;
  wire \txn_fifo[0][32]_i_1__0_n_0 ;
  wire \txn_fifo[0][33]_i_1__0_n_0 ;
  wire \txn_fifo[0][34]_i_1__0_n_0 ;
  wire \txn_fifo[0][35]_i_1__0_n_0 ;
  wire \txn_fifo[0][36]_i_1__0_n_0 ;
  wire \txn_fifo[0][37]_i_1__0_n_0 ;
  wire \txn_fifo[0][38]_i_1__0_n_0 ;
  wire \txn_fifo[0][39]_i_1__0_n_0 ;
  wire \txn_fifo[0][40]_i_1__0_n_0 ;
  wire \txn_fifo[0][44]_i_1__0_n_0 ;
  wire \txn_fifo[0][45]_i_1__0_n_0 ;
  wire \txn_fifo[0][46]_i_1__0_n_0 ;
  wire \txn_fifo[0][47]_i_1__0_n_0 ;
  wire \txn_fifo[0][47]_i_2_n_0 ;
  wire \txn_fifo[1][0]_i_1__0_n_0 ;
  wire \txn_fifo[1][11]_i_1__0_n_0 ;
  wire \txn_fifo[1][12]_i_1__0_n_0 ;
  wire \txn_fifo[1][13]_i_1__0_n_0 ;
  wire \txn_fifo[1][14]_i_1__0_n_0 ;
  wire \txn_fifo[1][15]_i_1__0_n_0 ;
  wire \txn_fifo[1][16]_i_1__0_n_0 ;
  wire \txn_fifo[1][17]_i_1__0_n_0 ;
  wire \txn_fifo[1][1]_i_1__0_n_0 ;
  wire \txn_fifo[1][24]_i_1__0_n_0 ;
  wire \txn_fifo[1][25]_i_1__0_n_0 ;
  wire \txn_fifo[1][26]_i_1__0_n_0 ;
  wire \txn_fifo[1][27]_i_1__0_n_0 ;
  wire \txn_fifo[1][28]_i_1__0_n_0 ;
  wire \txn_fifo[1][29]_i_1__0_n_0 ;
  wire \txn_fifo[1][2]_i_1__0_n_0 ;
  wire \txn_fifo[1][30]_i_1__0_n_0 ;
  wire \txn_fifo[1][31]_i_1__0_n_0 ;
  wire \txn_fifo[1][32]_i_1__0_n_0 ;
  wire \txn_fifo[1][33]_i_1__0_n_0 ;
  wire \txn_fifo[1][34]_i_1__0_n_0 ;
  wire \txn_fifo[1][35]_i_1__0_n_0 ;
  wire \txn_fifo[1][36]_i_1__0_n_0 ;
  wire \txn_fifo[1][37]_i_1__0_n_0 ;
  wire \txn_fifo[1][38]_i_1__0_n_0 ;
  wire \txn_fifo[1][39]_i_1__0_n_0 ;
  wire \txn_fifo[1][40]_i_1__0_n_0 ;
  wire \txn_fifo[1][44]_i_1__0_n_0 ;
  wire \txn_fifo[1][45]_i_1__0_n_0 ;
  wire \txn_fifo[1][46]_i_1__0_n_0 ;
  wire \txn_fifo[1][47]_i_1__0_n_0 ;
  wire \txn_fifo[1][47]_i_2_n_0 ;
  wire \txn_fifo[2][0]_i_1__0_n_0 ;
  wire \txn_fifo[2][11]_i_1__0_n_0 ;
  wire \txn_fifo[2][12]_i_1__0_n_0 ;
  wire \txn_fifo[2][13]_i_1__0_n_0 ;
  wire \txn_fifo[2][14]_i_1__0_n_0 ;
  wire \txn_fifo[2][15]_i_1__0_n_0 ;
  wire \txn_fifo[2][16]_i_1__0_n_0 ;
  wire \txn_fifo[2][17]_i_1__0_n_0 ;
  wire \txn_fifo[2][1]_i_1__0_n_0 ;
  wire \txn_fifo[2][24]_i_1__0_n_0 ;
  wire \txn_fifo[2][25]_i_1__0_n_0 ;
  wire \txn_fifo[2][26]_i_1__0_n_0 ;
  wire \txn_fifo[2][27]_i_1__0_n_0 ;
  wire \txn_fifo[2][28]_i_1__0_n_0 ;
  wire \txn_fifo[2][29]_i_1__0_n_0 ;
  wire \txn_fifo[2][2]_i_1__0_n_0 ;
  wire \txn_fifo[2][30]_i_1__0_n_0 ;
  wire \txn_fifo[2][31]_i_1__0_n_0 ;
  wire \txn_fifo[2][32]_i_1__0_n_0 ;
  wire \txn_fifo[2][33]_i_1__0_n_0 ;
  wire \txn_fifo[2][34]_i_1__0_n_0 ;
  wire \txn_fifo[2][35]_i_1__0_n_0 ;
  wire \txn_fifo[2][36]_i_1__0_n_0 ;
  wire \txn_fifo[2][37]_i_1__0_n_0 ;
  wire \txn_fifo[2][38]_i_1__0_n_0 ;
  wire \txn_fifo[2][39]_i_1__0_n_0 ;
  wire \txn_fifo[2][40]_i_1__0_n_0 ;
  wire \txn_fifo[2][44]_i_1__0_n_0 ;
  wire \txn_fifo[2][45]_i_1__0_n_0 ;
  wire \txn_fifo[2][46]_i_1__0_n_0 ;
  wire \txn_fifo[2][47]_i_1__0_n_0 ;
  wire \txn_fifo[2][47]_i_2__0_n_0 ;
  wire \txn_fifo[3][0]_i_1__0_n_0 ;
  wire \txn_fifo[3][11]_i_1__0_n_0 ;
  wire \txn_fifo[3][12]_i_1__0_n_0 ;
  wire \txn_fifo[3][13]_i_1__0_n_0 ;
  wire \txn_fifo[3][14]_i_1__0_n_0 ;
  wire \txn_fifo[3][15]_i_1__0_n_0 ;
  wire \txn_fifo[3][16]_i_1__0_n_0 ;
  wire \txn_fifo[3][17]_i_1__0_n_0 ;
  wire \txn_fifo[3][1]_i_1__0_n_0 ;
  wire \txn_fifo[3][24]_i_1__0_n_0 ;
  wire \txn_fifo[3][25]_i_1__0_n_0 ;
  wire \txn_fifo[3][26]_i_1__0_n_0 ;
  wire \txn_fifo[3][27]_i_1__0_n_0 ;
  wire \txn_fifo[3][28]_i_1__0_n_0 ;
  wire \txn_fifo[3][29]_i_1__0_n_0 ;
  wire \txn_fifo[3][2]_i_1__0_n_0 ;
  wire \txn_fifo[3][30]_i_1__0_n_0 ;
  wire \txn_fifo[3][31]_i_1__0_n_0 ;
  wire \txn_fifo[3][32]_i_1__0_n_0 ;
  wire \txn_fifo[3][33]_i_1__0_n_0 ;
  wire \txn_fifo[3][34]_i_1__0_n_0 ;
  wire \txn_fifo[3][35]_i_1__0_n_0 ;
  wire \txn_fifo[3][36]_i_1__0_n_0 ;
  wire \txn_fifo[3][37]_i_1__0_n_0 ;
  wire \txn_fifo[3][38]_i_1__0_n_0 ;
  wire \txn_fifo[3][39]_i_1__0_n_0 ;
  wire \txn_fifo[3][40]_i_1__0_n_0 ;
  wire \txn_fifo[3][44]_i_1__0_n_0 ;
  wire \txn_fifo[3][45]_i_1__0_n_0 ;
  wire \txn_fifo[3][46]_i_1__0_n_0 ;
  wire \txn_fifo[3][47]_i_1__0_n_0 ;
  wire \txn_fifo[3][47]_i_2_n_0 ;
  wire txn_fifo_empty_i_1__0_n_0;
  wire txn_fifo_empty_i_2_n_0;
  wire txn_fifo_empty_reg_n_0;
  wire \txn_fifo_output[0]_i_1__0_n_0 ;
  wire \txn_fifo_output[0]_i_2__0_n_0 ;
  wire \txn_fifo_output[0]_i_3__0_n_0 ;
  wire \txn_fifo_output[11]_i_1__0_n_0 ;
  wire \txn_fifo_output[11]_i_2__0_n_0 ;
  wire \txn_fifo_output[11]_i_3__0_n_0 ;
  wire \txn_fifo_output[12]_i_1__0_n_0 ;
  wire \txn_fifo_output[12]_i_2__0_n_0 ;
  wire \txn_fifo_output[12]_i_3__0_n_0 ;
  wire \txn_fifo_output[13]_i_1__0_n_0 ;
  wire \txn_fifo_output[13]_i_2__0_n_0 ;
  wire \txn_fifo_output[13]_i_3__0_n_0 ;
  wire \txn_fifo_output[14]_i_1__0_n_0 ;
  wire \txn_fifo_output[14]_i_2__0_n_0 ;
  wire \txn_fifo_output[14]_i_3__0_n_0 ;
  wire \txn_fifo_output[15]_i_1__0_n_0 ;
  wire \txn_fifo_output[15]_i_2__0_n_0 ;
  wire \txn_fifo_output[15]_i_3__0_n_0 ;
  wire \txn_fifo_output[16]_i_1__0_n_0 ;
  wire \txn_fifo_output[16]_i_2__0_n_0 ;
  wire \txn_fifo_output[16]_i_3__0_n_0 ;
  wire \txn_fifo_output[17]_i_1__0_n_0 ;
  wire \txn_fifo_output[17]_i_2__0_n_0 ;
  wire \txn_fifo_output[17]_i_3__0_n_0 ;
  wire \txn_fifo_output[1]_i_1__0_n_0 ;
  wire \txn_fifo_output[1]_i_2__0_n_0 ;
  wire \txn_fifo_output[1]_i_3__0_n_0 ;
  wire \txn_fifo_output[24]_i_1__0_n_0 ;
  wire \txn_fifo_output[24]_i_2__0_n_0 ;
  wire \txn_fifo_output[24]_i_3__0_n_0 ;
  wire \txn_fifo_output[25]_i_1__0_n_0 ;
  wire \txn_fifo_output[25]_i_2__0_n_0 ;
  wire \txn_fifo_output[25]_i_3__0_n_0 ;
  wire \txn_fifo_output[26]_i_1__0_n_0 ;
  wire \txn_fifo_output[26]_i_2__0_n_0 ;
  wire \txn_fifo_output[26]_i_3__0_n_0 ;
  wire \txn_fifo_output[27]_i_1__0_n_0 ;
  wire \txn_fifo_output[27]_i_2__0_n_0 ;
  wire \txn_fifo_output[27]_i_3__0_n_0 ;
  wire \txn_fifo_output[28]_i_1__0_n_0 ;
  wire \txn_fifo_output[28]_i_2__0_n_0 ;
  wire \txn_fifo_output[28]_i_3__0_n_0 ;
  wire \txn_fifo_output[29]_i_1__0_n_0 ;
  wire \txn_fifo_output[29]_i_2__0_n_0 ;
  wire \txn_fifo_output[29]_i_3__0_n_0 ;
  wire \txn_fifo_output[2]_i_1__0_n_0 ;
  wire \txn_fifo_output[2]_i_2__0_n_0 ;
  wire \txn_fifo_output[2]_i_3__0_n_0 ;
  wire \txn_fifo_output[30]_i_1__0_n_0 ;
  wire \txn_fifo_output[30]_i_2__0_n_0 ;
  wire \txn_fifo_output[30]_i_3__0_n_0 ;
  wire \txn_fifo_output[31]_i_1__0_n_0 ;
  wire \txn_fifo_output[31]_i_2__0_n_0 ;
  wire \txn_fifo_output[31]_i_3__0_n_0 ;
  wire \txn_fifo_output[32]_i_1__0_n_0 ;
  wire \txn_fifo_output[32]_i_2__0_n_0 ;
  wire \txn_fifo_output[32]_i_3__0_n_0 ;
  wire \txn_fifo_output[33]_i_1__0_n_0 ;
  wire \txn_fifo_output[33]_i_2__0_n_0 ;
  wire \txn_fifo_output[33]_i_3__0_n_0 ;
  wire \txn_fifo_output[34]_i_1__0_n_0 ;
  wire \txn_fifo_output[34]_i_2__0_n_0 ;
  wire \txn_fifo_output[34]_i_3__0_n_0 ;
  wire \txn_fifo_output[35]_i_1__0_n_0 ;
  wire \txn_fifo_output[35]_i_2__0_n_0 ;
  wire \txn_fifo_output[35]_i_3__0_n_0 ;
  wire \txn_fifo_output[36]_i_1__0_n_0 ;
  wire \txn_fifo_output[36]_i_2__0_n_0 ;
  wire \txn_fifo_output[36]_i_3__0_n_0 ;
  wire \txn_fifo_output[37]_i_1__0_n_0 ;
  wire \txn_fifo_output[37]_i_2__0_n_0 ;
  wire \txn_fifo_output[37]_i_3__0_n_0 ;
  wire \txn_fifo_output[38]_i_1__0_n_0 ;
  wire \txn_fifo_output[38]_i_2__0_n_0 ;
  wire \txn_fifo_output[38]_i_3__0_n_0 ;
  wire \txn_fifo_output[39]_i_1__0_n_0 ;
  wire \txn_fifo_output[39]_i_2__0_n_0 ;
  wire \txn_fifo_output[39]_i_3__0_n_0 ;
  wire \txn_fifo_output[40]_i_1__0_n_0 ;
  wire \txn_fifo_output[40]_i_2__0_n_0 ;
  wire \txn_fifo_output[40]_i_3__0_n_0 ;
  wire \txn_fifo_output[44]_i_1__0_n_0 ;
  wire \txn_fifo_output[44]_i_2__0_n_0 ;
  wire \txn_fifo_output[44]_i_3__0_n_0 ;
  wire \txn_fifo_output[45]_i_1__0_n_0 ;
  wire \txn_fifo_output[45]_i_2__0_n_0 ;
  wire \txn_fifo_output[45]_i_3__0_n_0 ;
  wire \txn_fifo_output[46]_i_1__0_n_0 ;
  wire \txn_fifo_output[46]_i_2__0_n_0 ;
  wire \txn_fifo_output[46]_i_3__0_n_0 ;
  wire \txn_fifo_output[47]_i_1__0_n_0 ;
  wire \txn_fifo_output[47]_i_2__0_n_0 ;
  wire \txn_fifo_output[47]_i_3__0_n_0 ;
  wire \txn_fifo_output[47]_i_4_n_0 ;
  wire \txn_fifo_output[47]_i_5_n_0 ;
  wire \txn_fifo_output_reg_n_0_[11] ;
  wire \txn_fifo_output_reg_n_0_[12] ;
  wire \txn_fifo_output_reg_n_0_[13] ;
  wire \txn_fifo_output_reg_n_0_[14] ;
  wire \txn_fifo_output_reg_n_0_[15] ;
  wire \txn_fifo_output_reg_n_0_[16] ;
  wire \txn_fifo_output_reg_n_0_[17] ;
  wire \txn_fifo_output_reg_n_0_[44] ;
  wire \txn_fifo_output_reg_n_0_[45] ;
  wire \txn_fifo_output_reg_n_0_[46] ;
  wire \txn_fifo_output_reg_n_0_[47] ;
  wire \txn_fifo_reg_n_0_[0][0] ;
  wire \txn_fifo_reg_n_0_[0][11] ;
  wire \txn_fifo_reg_n_0_[0][12] ;
  wire \txn_fifo_reg_n_0_[0][13] ;
  wire \txn_fifo_reg_n_0_[0][14] ;
  wire \txn_fifo_reg_n_0_[0][15] ;
  wire \txn_fifo_reg_n_0_[0][16] ;
  wire \txn_fifo_reg_n_0_[0][17] ;
  wire \txn_fifo_reg_n_0_[0][1] ;
  wire \txn_fifo_reg_n_0_[0][24] ;
  wire \txn_fifo_reg_n_0_[0][25] ;
  wire \txn_fifo_reg_n_0_[0][26] ;
  wire \txn_fifo_reg_n_0_[0][27] ;
  wire \txn_fifo_reg_n_0_[0][28] ;
  wire \txn_fifo_reg_n_0_[0][29] ;
  wire \txn_fifo_reg_n_0_[0][2] ;
  wire \txn_fifo_reg_n_0_[0][30] ;
  wire \txn_fifo_reg_n_0_[0][31] ;
  wire \txn_fifo_reg_n_0_[0][32] ;
  wire \txn_fifo_reg_n_0_[0][33] ;
  wire \txn_fifo_reg_n_0_[0][34] ;
  wire \txn_fifo_reg_n_0_[0][35] ;
  wire \txn_fifo_reg_n_0_[0][36] ;
  wire \txn_fifo_reg_n_0_[0][37] ;
  wire \txn_fifo_reg_n_0_[0][38] ;
  wire \txn_fifo_reg_n_0_[0][39] ;
  wire \txn_fifo_reg_n_0_[0][40] ;
  wire \txn_fifo_reg_n_0_[0][44] ;
  wire \txn_fifo_reg_n_0_[0][45] ;
  wire \txn_fifo_reg_n_0_[0][46] ;
  wire \txn_fifo_reg_n_0_[0][47] ;
  wire \txn_fifo_reg_n_0_[1][0] ;
  wire \txn_fifo_reg_n_0_[1][11] ;
  wire \txn_fifo_reg_n_0_[1][12] ;
  wire \txn_fifo_reg_n_0_[1][13] ;
  wire \txn_fifo_reg_n_0_[1][14] ;
  wire \txn_fifo_reg_n_0_[1][15] ;
  wire \txn_fifo_reg_n_0_[1][16] ;
  wire \txn_fifo_reg_n_0_[1][17] ;
  wire \txn_fifo_reg_n_0_[1][1] ;
  wire \txn_fifo_reg_n_0_[1][24] ;
  wire \txn_fifo_reg_n_0_[1][25] ;
  wire \txn_fifo_reg_n_0_[1][26] ;
  wire \txn_fifo_reg_n_0_[1][27] ;
  wire \txn_fifo_reg_n_0_[1][28] ;
  wire \txn_fifo_reg_n_0_[1][29] ;
  wire \txn_fifo_reg_n_0_[1][2] ;
  wire \txn_fifo_reg_n_0_[1][30] ;
  wire \txn_fifo_reg_n_0_[1][31] ;
  wire \txn_fifo_reg_n_0_[1][32] ;
  wire \txn_fifo_reg_n_0_[1][33] ;
  wire \txn_fifo_reg_n_0_[1][34] ;
  wire \txn_fifo_reg_n_0_[1][35] ;
  wire \txn_fifo_reg_n_0_[1][36] ;
  wire \txn_fifo_reg_n_0_[1][37] ;
  wire \txn_fifo_reg_n_0_[1][38] ;
  wire \txn_fifo_reg_n_0_[1][39] ;
  wire \txn_fifo_reg_n_0_[1][40] ;
  wire \txn_fifo_reg_n_0_[1][44] ;
  wire \txn_fifo_reg_n_0_[1][45] ;
  wire \txn_fifo_reg_n_0_[1][46] ;
  wire \txn_fifo_reg_n_0_[1][47] ;
  wire \txn_fifo_reg_n_0_[2][0] ;
  wire \txn_fifo_reg_n_0_[2][11] ;
  wire \txn_fifo_reg_n_0_[2][12] ;
  wire \txn_fifo_reg_n_0_[2][13] ;
  wire \txn_fifo_reg_n_0_[2][14] ;
  wire \txn_fifo_reg_n_0_[2][15] ;
  wire \txn_fifo_reg_n_0_[2][16] ;
  wire \txn_fifo_reg_n_0_[2][17] ;
  wire \txn_fifo_reg_n_0_[2][1] ;
  wire \txn_fifo_reg_n_0_[2][24] ;
  wire \txn_fifo_reg_n_0_[2][25] ;
  wire \txn_fifo_reg_n_0_[2][26] ;
  wire \txn_fifo_reg_n_0_[2][27] ;
  wire \txn_fifo_reg_n_0_[2][28] ;
  wire \txn_fifo_reg_n_0_[2][29] ;
  wire \txn_fifo_reg_n_0_[2][2] ;
  wire \txn_fifo_reg_n_0_[2][30] ;
  wire \txn_fifo_reg_n_0_[2][31] ;
  wire \txn_fifo_reg_n_0_[2][32] ;
  wire \txn_fifo_reg_n_0_[2][33] ;
  wire \txn_fifo_reg_n_0_[2][34] ;
  wire \txn_fifo_reg_n_0_[2][35] ;
  wire \txn_fifo_reg_n_0_[2][36] ;
  wire \txn_fifo_reg_n_0_[2][37] ;
  wire \txn_fifo_reg_n_0_[2][38] ;
  wire \txn_fifo_reg_n_0_[2][39] ;
  wire \txn_fifo_reg_n_0_[2][40] ;
  wire \txn_fifo_reg_n_0_[2][44] ;
  wire \txn_fifo_reg_n_0_[2][45] ;
  wire \txn_fifo_reg_n_0_[2][46] ;
  wire \txn_fifo_reg_n_0_[2][47] ;
  wire \txn_fifo_reg_n_0_[3][0] ;
  wire \txn_fifo_reg_n_0_[3][11] ;
  wire \txn_fifo_reg_n_0_[3][12] ;
  wire \txn_fifo_reg_n_0_[3][13] ;
  wire \txn_fifo_reg_n_0_[3][14] ;
  wire \txn_fifo_reg_n_0_[3][15] ;
  wire \txn_fifo_reg_n_0_[3][16] ;
  wire \txn_fifo_reg_n_0_[3][17] ;
  wire \txn_fifo_reg_n_0_[3][1] ;
  wire \txn_fifo_reg_n_0_[3][24] ;
  wire \txn_fifo_reg_n_0_[3][25] ;
  wire \txn_fifo_reg_n_0_[3][26] ;
  wire \txn_fifo_reg_n_0_[3][27] ;
  wire \txn_fifo_reg_n_0_[3][28] ;
  wire \txn_fifo_reg_n_0_[3][29] ;
  wire \txn_fifo_reg_n_0_[3][2] ;
  wire \txn_fifo_reg_n_0_[3][30] ;
  wire \txn_fifo_reg_n_0_[3][31] ;
  wire \txn_fifo_reg_n_0_[3][32] ;
  wire \txn_fifo_reg_n_0_[3][33] ;
  wire \txn_fifo_reg_n_0_[3][34] ;
  wire \txn_fifo_reg_n_0_[3][35] ;
  wire \txn_fifo_reg_n_0_[3][36] ;
  wire \txn_fifo_reg_n_0_[3][37] ;
  wire \txn_fifo_reg_n_0_[3][38] ;
  wire \txn_fifo_reg_n_0_[3][39] ;
  wire \txn_fifo_reg_n_0_[3][40] ;
  wire \txn_fifo_reg_n_0_[3][44] ;
  wire \txn_fifo_reg_n_0_[3][45] ;
  wire \txn_fifo_reg_n_0_[3][46] ;
  wire \txn_fifo_reg_n_0_[3][47] ;
  wire \txn_fifo_rptr[0]_i_1__0_n_0 ;
  wire \txn_fifo_rptr[1]_i_1__0_n_0 ;
  wire \txn_fifo_rptr[1]_i_2__1_n_0 ;
  wire \txn_fifo_rptr_reg_n_0_[0] ;
  wire \txn_fifo_rptr_reg_n_0_[1] ;
  wire \txn_fifo_wptr[0]_i_1_n_0 ;
  wire \txn_fifo_wptr[1]_i_1_n_0 ;
  wire \txn_fifo_wptr_reg[0]_0 ;
  wire \txn_fifo_wptr_reg[0]_1 ;
  wire \txn_fifo_wptr_reg_n_0_[0] ;
  wire \txn_fifo_wptr_reg_n_0_[1] ;
  wire underfill_done_reg_0;
  wire underfill_done_reg_n_0;
  wire useAdr;
  wire wrReqR_i_1__2_n_0;
  wire wrReqR_i_2__2_n_0;
  wire wrReqR_i_3__1_n_0;
  wire wrReqR_i_4__1_n_0;
  wire wrReqR_i_5__1_n_0;
  wire wrReqR_i_6__1_n_0;
  wire wrReqR_i_7__1_n_0;
  wire wrReqR_i_8__0_n_0;
  wire wrReqR_reg_0;
  wire [7:6]\NLW_issue_cas3_inferred__0/i__carry_CO_UNCONNECTED ;
  wire [7:0]\NLW_issue_cas3_inferred__0/i__carry_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h08AA000008AAAAAA)) 
    \FSM_sequential_grSt[0]_i_1__0 
       (.I0(\FSM_sequential_grSt[0]_i_2__0_n_0 ),
        .I1(\FSM_sequential_grSt_reg[0]_0 ),
        .I2(cas_fifo_full_reg_n_0),
        .I3(grSt[0]),
        .I4(grSt[1]),
        .I5(grSt[2]),
        .O(\FSM_sequential_grSt[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAFFFFEFFF)) 
    \FSM_sequential_grSt[0]_i_2__0 
       (.I0(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I1(actReqR_i_2_n_0),
        .I2(ref_req_dly4),
        .I3(txn_fifo_empty_reg_n_0),
        .I4(\FSM_sequential_grSt[2]_i_7__0_n_0 ),
        .I5(preReqR_i_2_n_0),
        .O(\FSM_sequential_grSt[0]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000262626FF)) 
    \FSM_sequential_grSt[1]_i_1__0 
       (.I0(grSt[2]),
        .I1(grSt[1]),
        .I2(grSt[0]),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\FSM_sequential_grSt[2]_i_6_n_0 ),
        .I5(\FSM_sequential_grSt[1]_i_3__0_n_0 ),
        .O(\FSM_sequential_grSt[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0015FFFFFFFF)) 
    \FSM_sequential_grSt[1]_i_2 
       (.I0(\FSM_sequential_grSt[1]_i_4__1_n_0 ),
        .I1(\FSM_sequential_grSt[1]_i_5__1_n_0 ),
        .I2(\cas_pend_fifo_reg_n_0_[2][47] ),
        .I3(\FSM_sequential_grSt[1]_i_6_n_0 ),
        .I4(grSt[1]),
        .I5(grSt[0]),
        .O(\FSM_sequential_grSt[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00000700)) 
    \FSM_sequential_grSt[1]_i_3__0 
       (.I0(ref_req_dly4),
        .I1(txn_fifo_empty_reg_n_0),
        .I2(grSt[2]),
        .I3(grSt[0]),
        .I4(\FSM_sequential_grSt[2]_i_7__0_n_0 ),
        .O(\FSM_sequential_grSt[1]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h88F888F8FFFF88F8)) 
    \FSM_sequential_grSt[1]_i_4__1 
       (.I0(\cmdBankP[1]_i_4__1_n_0 ),
        .I1(\cas_pend_fifo_reg_n_0_[0][47] ),
        .I2(\cas_pend_fifo_reg_n_0_[3][47] ),
        .I3(\cmdBankP[1]_i_5__1_n_0 ),
        .I4(\cas_pend_fifo_reg_n_0_[1][47] ),
        .I5(\cmdBankP[1]_i_6__1_n_0 ),
        .O(\FSM_sequential_grSt[1]_i_4__1_n_0 ));
  LUT5 #(
    .INIT(32'h82000082)) 
    \FSM_sequential_grSt[1]_i_5__1 
       (.I0(\cas_fifo_valid_reg_n_0_[2] ),
        .I1(Q[0]),
        .I2(\cas_pend_fifo_reg_n_0_[2][0] ),
        .I3(Q[1]),
        .I4(\cas_pend_fifo_reg_n_0_[2][1] ),
        .O(\FSM_sequential_grSt[1]_i_5__1_n_0 ));
  LUT5 #(
    .INIT(32'hEFEFFFEF)) 
    \FSM_sequential_grSt[1]_i_6 
       (.I0(\cmdBankP[1]_i_3__0_n_0 ),
        .I1(cas_fifo_full_reg_n_0),
        .I2(\issue_cas3_inferred__0/i__carry_n_2 ),
        .I3(txn_fifo_empty_reg_n_0),
        .I4(txn_fifo_empty_i_2_n_0),
        .O(\FSM_sequential_grSt[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEEEEEFEEEEE)) 
    \FSM_sequential_grSt[2]_i_1__1 
       (.I0(\FSM_sequential_grSt[2]_i_3__1_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_4__1_n_0 ),
        .I2(trp_cntr_is_zero_reg_n_0),
        .I3(grSt[2]),
        .I4(grSt[1]),
        .I5(grSt[0]),
        .O(\FSM_sequential_grSt[2]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h8A888888)) 
    \FSM_sequential_grSt[2]_i_2 
       (.I0(\FSM_sequential_grSt[2]_i_5__1_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_6_n_0 ),
        .I2(\FSM_sequential_grSt[2]_i_7__0_n_0 ),
        .I3(txn_fifo_empty_reg_n_0),
        .I4(ref_req_dly4),
        .O(\FSM_sequential_grSt[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0F0F0A0AFF0F0303)) 
    \FSM_sequential_grSt[2]_i_3__1 
       (.I0(preReqR_reg_1),
        .I1(cas_fifo_full_reg_n_0),
        .I2(grSt[1]),
        .I3(\FSM_sequential_grSt_reg[0]_0 ),
        .I4(grSt[0]),
        .I5(grSt[2]),
        .O(\FSM_sequential_grSt[2]_i_3__1_n_0 ));
  LUT6 #(
    .INIT(64'h00D5000000000000)) 
    \FSM_sequential_grSt[2]_i_4__1 
       (.I0(txn_fifo_empty_reg_n_0),
        .I1(group),
        .I2(bank[0]),
        .I3(\FSM_sequential_grSt_reg[0]_1 ),
        .I4(grSt[1]),
        .I5(grSt[2]),
        .O(\FSM_sequential_grSt[2]_i_4__1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_sequential_grSt[2]_i_5__1 
       (.I0(grSt[2]),
        .I1(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_5__1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_grSt[2]_i_6 
       (.I0(actReqR_i_2_n_0),
        .I1(preReqR_i_2_n_0),
        .O(\FSM_sequential_grSt[2]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_grSt[2]_i_7__0 
       (.I0(\cmdBankP[1]_i_3__0_n_0 ),
        .I1(\cmdBankP[1]_i_2_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_7__0_n_0 ));
  (* FSM_ENCODED_STATES = "grACT:010,grPREWAIT:100,grAUTOPRE:101,grACTWAIT:011,grIDLE:110,grCASFSM:000,grACCEPT:001" *) 
  FDRE \FSM_sequential_grSt_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\FSM_sequential_grSt[2]_i_1__1_n_0 ),
        .D(\FSM_sequential_grSt[0]_i_1__0_n_0 ),
        .Q(grSt[0]),
        .R(rst_r1));
  (* FSM_ENCODED_STATES = "grACT:010,grPREWAIT:100,grAUTOPRE:101,grACTWAIT:011,grIDLE:110,grCASFSM:000,grACCEPT:001" *) 
  FDSE \FSM_sequential_grSt_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\FSM_sequential_grSt[2]_i_1__1_n_0 ),
        .D(\FSM_sequential_grSt[1]_i_1__0_n_0 ),
        .Q(grSt[1]),
        .S(rst_r1));
  (* FSM_ENCODED_STATES = "grACT:010,grPREWAIT:100,grAUTOPRE:101,grACTWAIT:011,grIDLE:110,grCASFSM:000,grACCEPT:001" *) 
  FDSE \FSM_sequential_grSt_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\FSM_sequential_grSt[2]_i_1__1_n_0 ),
        .D(\FSM_sequential_grSt[2]_i_2_n_0 ),
        .Q(grSt[2]),
        .S(rst_r1));
  LUT6 #(
    .INIT(64'hAAAAAAAA00002022)) 
    \FSM_sequential_gr_cas_state[0]_i_1__2 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_5__0_n_0 ),
        .I1(\FSM_sequential_gr_cas_state[2]_i_8__0_n_0 ),
        .I2(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ),
        .I3(cas_fifo_empty_reg_n_0),
        .I4(\FSM_sequential_gr_cas_state[2]_i_6__2_n_0 ),
        .I5(gr_cas_state[1]),
        .O(gr_cas_state_nxt[0]));
  (* SOFT_HLUTNM = "soft_lutpair2706" *) 
  LUT3 #(
    .INIT(8'h12)) 
    \FSM_sequential_gr_cas_state[1]_i_1__2 
       (.I0(gr_cas_state[0]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[1]),
        .O(gr_cas_state_nxt[1]));
  LUT6 #(
    .INIT(64'hAABAFAEEAABAFAAA)) 
    \FSM_sequential_gr_cas_state[2]_i_1__2 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_3__0_n_0 ),
        .I1(gr_cas_state[1]),
        .I2(clrReq1),
        .I3(gr_cas_state[0]),
        .I4(gr_cas_state[2]),
        .I5(underfill_done_reg_n_0),
        .O(\FSM_sequential_gr_cas_state[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h2222222220202220)) 
    \FSM_sequential_gr_cas_state[2]_i_2__2 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_5__0_n_0 ),
        .I1(gr_cas_state[1]),
        .I2(\FSM_sequential_gr_cas_state[2]_i_6__2_n_0 ),
        .I3(cas_fifo_empty_reg_n_0),
        .I4(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ),
        .I5(\FSM_sequential_gr_cas_state[2]_i_8__0_n_0 ),
        .O(gr_cas_state_nxt[2]));
  LUT6 #(
    .INIT(64'h0000000010550000)) 
    \FSM_sequential_gr_cas_state[2]_i_3__0 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_8__0_n_0 ),
        .I1(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I2(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I3(cas_fifo_empty_reg_n_0),
        .I4(\FSM_sequential_gr_cas_state[2]_i_5__0_n_0 ),
        .I5(gr_cas_state[1]),
        .O(\FSM_sequential_gr_cas_state[2]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2716" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_sequential_gr_cas_state[2]_i_5__0 
       (.I0(gr_cas_state[0]),
        .I1(gr_cas_state[2]),
        .O(\FSM_sequential_gr_cas_state[2]_i_5__0_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_gr_cas_state[2]_i_6__2 
       (.I0(rdReqR_i_2__2_n_0),
        .I1(wrReqR_i_4__1_n_0),
        .O(\FSM_sequential_gr_cas_state[2]_i_6__2_n_0 ));
  LUT6 #(
    .INIT(64'h000000002A220202)) 
    \FSM_sequential_gr_cas_state[2]_i_7 
       (.I0(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I1(grSt[1]),
        .I2(cas_fifo_full_reg_n_0),
        .I3(\FSM_sequential_grSt_reg[0]_0 ),
        .I4(grSt[0]),
        .I5(grSt[2]),
        .O(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h050305F3F503F5F3)) 
    \FSM_sequential_gr_cas_state[2]_i_8__0 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I1(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I2(\cmd_bank_cas[1]_i_1__2_n_0 ),
        .I3(\cmd_bank_cas[0]_i_2__2_n_0 ),
        .I4(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I5(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .O(\FSM_sequential_gr_cas_state[2]_i_8__0_n_0 ));
  (* FSM_ENCODED_STATES = "CAS_IDLE:000,RMW_DATAWAIT:010,RMW_WRWAIT:011,CAS_WAIT:100,RMW_RDWAIT:001" *) 
  FDRE \FSM_sequential_gr_cas_state_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\FSM_sequential_gr_cas_state[2]_i_1__2_n_0 ),
        .D(gr_cas_state_nxt[0]),
        .Q(gr_cas_state[0]),
        .R(rst_r1));
  (* FSM_ENCODED_STATES = "CAS_IDLE:000,RMW_DATAWAIT:010,RMW_WRWAIT:011,CAS_WAIT:100,RMW_RDWAIT:001" *) 
  FDRE \FSM_sequential_gr_cas_state_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\FSM_sequential_gr_cas_state[2]_i_1__2_n_0 ),
        .D(gr_cas_state_nxt[1]),
        .Q(gr_cas_state[1]),
        .R(rst_r1));
  (* FSM_ENCODED_STATES = "CAS_IDLE:000,RMW_DATAWAIT:010,RMW_WRWAIT:011,CAS_WAIT:100,RMW_RDWAIT:001" *) 
  FDRE \FSM_sequential_gr_cas_state_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\FSM_sequential_gr_cas_state[2]_i_1__2_n_0 ),
        .D(gr_cas_state_nxt[2]),
        .Q(gr_cas_state[2]),
        .R(rst_r1));
  LUT4 #(
    .INIT(16'h0004)) 
    accept_i_1__1
       (.I0(periodic_read_or_ref_block_reg_0),
        .I1(group),
        .I2(bank[0]),
        .I3(accept_reg_2),
        .O(grAccept_ns));
  LUT4 #(
    .INIT(16'h4BB4)) 
    accept_i_2
       (.I0(\txn_fifo_wptr_reg_n_0_[0] ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_wptr_reg[0]_0 ));
  FDRE accept_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(accept_reg_1),
        .Q(accept_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFFFF20)) 
    actReqR_i_1__0
       (.I0(\FSM_sequential_grSt[2]_i_5__1_n_0 ),
        .I1(actReqR_i_2_n_0),
        .I2(\FSM_sequential_grSt[2]_i_7__0_n_0 ),
        .I3(actReqR_reg_0),
        .I4(actReqR_i_3__0_n_0),
        .I5(\FSM_sequential_grSt_reg[0]_0 ),
        .O(actReqR_i_1__0_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    actReqR_i_2
       (.I0(\cmdBankP[1]_i_2_n_0 ),
        .I1(actReqR_i_4__0_n_0),
        .O(actReqR_i_2_n_0));
  LUT4 #(
    .INIT(16'h0020)) 
    actReqR_i_3__0
       (.I0(trp_cntr_is_zero_reg_n_0),
        .I1(grSt[2]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .O(actReqR_i_3__0_n_0));
  LUT6 #(
    .INIT(64'h55000F3355FF0F33)) 
    actReqR_i_4__0
       (.I0(\pageInfo_reg_n_0_[0][0][3][1] ),
        .I1(\pageInfo_reg_n_0_[0][0][0][1] ),
        .I2(\pageInfo_reg_n_0_[0][0][2][1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\pageInfo_reg_n_0_[0][0][1][1] ),
        .O(actReqR_i_4__0_n_0));
  FDRE actReqR_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(actReqR_i_1__0_n_0),
        .Q(actReqR_reg_0),
        .R(rst_r1));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][0][0]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .I3(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .O(\ap_cntr[0][0][0][0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][0][1]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[1] ),
        .I1(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .I4(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .O(\ap_cntr[0][0][0][1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][0][2]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[2] ),
        .I1(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .O(\ap_cntr[0][0][0][2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][0][3]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .I4(\ap_cntr[0][0][0][4]_i_2__2_n_0 ),
        .I5(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .O(\ap_cntr[0][0][0][3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFB0004)) 
    \ap_cntr[0][0][0][4]_i_1__2 
       (.I0(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .I1(\ap_cntr[0][0][0][4]_i_2__2_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I3(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .I4(\ap_cntr_reg_n_0_[0][0][0][4] ),
        .I5(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .O(\ap_cntr[0][0][0][4]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2730" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][0][4]_i_2__2 
       (.I0(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .I1(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .O(\ap_cntr[0][0][0][4]_i_2__2_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][1][0]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .O(\ap_cntr[0][0][1][0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2707" *) 
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][1][1]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[1] ),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .O(\ap_cntr[0][0][1][1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][1][2]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[2] ),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .O(\ap_cntr[0][0][1][2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][1][3]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .I4(\ap_cntr[0][0][1][4]_i_2__2_n_0 ),
        .I5(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .O(\ap_cntr[0][0][1][3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFB0004)) 
    \ap_cntr[0][0][1][4]_i_1__2 
       (.I0(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .I1(\ap_cntr[0][0][1][4]_i_2__2_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .I4(\ap_cntr_reg_n_0_[0][0][1][4] ),
        .I5(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .O(\ap_cntr[0][0][1][4]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2707" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][1][4]_i_2__2 
       (.I0(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .I1(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .O(\ap_cntr[0][0][1][4]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000008200000)) 
    \ap_cntr[0][0][1][4]_i_3__1 
       (.I0(cmdAP),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(gr_cas_state[1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\cmd_bank_cas_reg[1]_0 [1]),
        .O(\ap_cntr[0][0][1][4]_i_3__1_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][2][0]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .O(\ap_cntr[0][0][2][0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][2][1]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[1] ),
        .I1(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .I4(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .O(\ap_cntr[0][0][2][1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][2][2]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[2] ),
        .I1(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .O(\ap_cntr[0][0][2][2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2729" *) 
  LUT4 #(
    .INIT(16'h8BB8)) 
    \ap_cntr[0][0][2][3]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][2][3] ),
        .I3(\ap_cntr[0][0][2][4]_i_3__1_n_0 ),
        .O(\ap_cntr[0][0][2][3]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2729" *) 
  LUT4 #(
    .INIT(16'h4510)) 
    \ap_cntr[0][0][2][4]_i_1__2 
       (.I0(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I1(\ap_cntr_reg_n_0_[0][0][2][3] ),
        .I2(\ap_cntr[0][0][2][4]_i_3__1_n_0 ),
        .I3(\ap_cntr_reg_n_0_[0][0][2][4] ),
        .O(\ap_cntr[0][0][2][4]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000008200000)) 
    \ap_cntr[0][0][2][4]_i_2__2 
       (.I0(cmdAP),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(gr_cas_state[1]),
        .I4(\cmd_bank_cas_reg[1]_0 [1]),
        .I5(\cmd_bank_cas_reg[1]_0 [0]),
        .O(\ap_cntr[0][0][2][4]_i_2__2_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \ap_cntr[0][0][2][4]_i_3__1 
       (.I0(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .I1(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .O(\ap_cntr[0][0][2][4]_i_3__1_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][3][0]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .O(\ap_cntr[0][0][3][0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2709" *) 
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][3][1]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[1] ),
        .I1(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .I4(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .O(\ap_cntr[0][0][3][1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][3][2]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[2] ),
        .I1(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .O(\ap_cntr[0][0][3][2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][3][3]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .I4(\ap_cntr[0][0][3][4]_i_2__2_n_0 ),
        .I5(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .O(\ap_cntr[0][0][3][3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFB0004)) 
    \ap_cntr[0][0][3][4]_i_1__2 
       (.I0(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .I1(\ap_cntr[0][0][3][4]_i_2__2_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I3(\ap_cntr_reg_n_0_[0][0][3][3] ),
        .I4(\ap_cntr_reg_n_0_[0][0][3][4] ),
        .I5(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .O(\ap_cntr[0][0][3][4]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2709" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][3][4]_i_2__2 
       (.I0(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .I1(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .O(\ap_cntr[0][0][3][4]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h0820000000000000)) 
    \ap_cntr[0][0][3][4]_i_3__2 
       (.I0(cmdAP),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(gr_cas_state[1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\cmd_bank_cas_reg[1]_0 [1]),
        .O(\ap_cntr[0][0][3][4]_i_3__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \ap_cntr_expired[0][0][0]_i_1 
       (.I0(\ap_cntr_zero[0][0][0]_i_1__2_n_0 ),
        .I1(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .O(\ap_cntr_expired[0][0][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_cntr_expired[0][0][1]_i_1__2 
       (.I0(\ap_cntr[0][0][1][1]_i_1__2_n_0 ),
        .I1(\ap_cntr[0][0][1][4]_i_1__2_n_0 ),
        .I2(\ap_cntr[0][0][1][0]_i_1__2_n_0 ),
        .I3(\ap_cntr[0][0][1][2]_i_1__2_n_0 ),
        .I4(\ap_cntr[0][0][1][3]_i_1__2_n_0 ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .O(\ap_cntr_expired[0][0][1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_cntr_expired[0][0][2]_i_1__2 
       (.I0(\ap_cntr[0][0][2][2]_i_1__2_n_0 ),
        .I1(\ap_cntr[0][0][2][4]_i_1__2_n_0 ),
        .I2(\ap_cntr[0][0][2][1]_i_1__2_n_0 ),
        .I3(\ap_cntr[0][0][2][3]_i_1__2_n_0 ),
        .I4(\ap_cntr[0][0][2][0]_i_1__2_n_0 ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .O(\ap_cntr_expired[0][0][2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_cntr_expired[0][0][3]_i_1__2 
       (.I0(\ap_cntr[0][0][3][4]_i_1__2_n_0 ),
        .I1(\ap_cntr[0][0][3][2]_i_1__2_n_0 ),
        .I2(\ap_cntr[0][0][3][0]_i_1__2_n_0 ),
        .I3(\ap_cntr[0][0][3][1]_i_1__2_n_0 ),
        .I4(\ap_cntr[0][0][3][3]_i_1__2_n_0 ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .O(\ap_cntr_expired[0][0][3]_i_1__2_n_0 ));
  FDRE \ap_cntr_expired_reg[0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_expired[0][0][0]_i_1_n_0 ),
        .Q(sel0__62),
        .R(1'b0));
  FDRE \ap_cntr_expired_reg[0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_expired[0][0][1]_i_1__2_n_0 ),
        .Q(sel0__58),
        .R(1'b0));
  FDRE \ap_cntr_expired_reg[0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_expired[0][0][2]_i_1__2_n_0 ),
        .Q(sel0__54),
        .R(1'b0));
  FDRE \ap_cntr_expired_reg[0][0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_expired[0][0][3]_i_1__2_n_0 ),
        .Q(sel0__50),
        .R(1'b0));
  FDRE \ap_cntr_reg[0][0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][0]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][1]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][2]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][3]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][4]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][4] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][0]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][1]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][2]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][3]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][4]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][4] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][0]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][1]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][2]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][3]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][3] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][4]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][4] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][0]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][1]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][2]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][3]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][3] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][4]_i_1__2_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][4] ),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'h0000000044447447)) 
    \ap_cntr_zero[0][0][0]_i_1__2 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .I3(\ap_cntr_zero[0][0][0]_i_3_n_0 ),
        .I4(\ap_cntr_reg_n_0_[0][0][0][4] ),
        .I5(\ap_cntr_zero[0][0][0]_i_4_n_0 ),
        .O(\ap_cntr_zero[0][0][0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000820)) 
    \ap_cntr_zero[0][0][0]_i_2__0 
       (.I0(cmdAP),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(gr_cas_state[1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\cmd_bank_cas_reg[1]_0 [1]),
        .O(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2730" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \ap_cntr_zero[0][0][0]_i_3 
       (.I0(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I1(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .I3(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .O(\ap_cntr_zero[0][0][0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEFEAEAEF)) 
    \ap_cntr_zero[0][0][0]_i_4 
       (.I0(\ap_cntr[0][0][0][1]_i_1__2_n_0 ),
        .I1(\ap_load_value_reg_n_0_[0] ),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .I4(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .I5(\ap_cntr[0][0][0][2]_i_1__2_n_0 ),
        .O(\ap_cntr_zero[0][0][0]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_zero[0][0][1]_i_1__2 
       (.I0(\ap_cntr[0][0][1][1]_i_1__2_n_0 ),
        .I1(\ap_cntr[0][0][1][4]_i_1__2_n_0 ),
        .I2(\ap_cntr[0][0][1][0]_i_1__2_n_0 ),
        .I3(\ap_cntr[0][0][1][2]_i_1__2_n_0 ),
        .I4(\ap_cntr[0][0][1][3]_i_1__2_n_0 ),
        .O(\ap_cntr_zero[0][0][1]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_zero[0][0][2]_i_1__2 
       (.I0(\ap_cntr[0][0][2][2]_i_1__2_n_0 ),
        .I1(\ap_cntr[0][0][2][4]_i_1__2_n_0 ),
        .I2(\ap_cntr[0][0][2][1]_i_1__2_n_0 ),
        .I3(\ap_cntr[0][0][2][3]_i_1__2_n_0 ),
        .I4(\ap_cntr[0][0][2][0]_i_1__2_n_0 ),
        .O(\ap_cntr_zero[0][0][2]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_zero[0][0][3]_i_1__2 
       (.I0(\ap_cntr[0][0][3][4]_i_1__2_n_0 ),
        .I1(\ap_cntr[0][0][3][2]_i_1__2_n_0 ),
        .I2(\ap_cntr[0][0][3][0]_i_1__2_n_0 ),
        .I3(\ap_cntr[0][0][3][1]_i_1__2_n_0 ),
        .I4(\ap_cntr[0][0][3][3]_i_1__2_n_0 ),
        .O(\ap_cntr_zero[0][0][3]_i_1__2_n_0 ));
  FDRE \ap_cntr_zero_reg[0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_zero[0][0][0]_i_1__2_n_0 ),
        .Q(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_zero_reg[0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_zero[0][0][1]_i_1__2_n_0 ),
        .Q(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_zero_reg[0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_zero[0][0][2]_i_1__2_n_0 ),
        .Q(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_zero_reg[0][0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_zero[0][0][3]_i_1__2_n_0 ),
        .Q(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2768" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \ap_load_value[0]_i_1__2 
       (.I0(wrReqR_reg_0),
        .I1(\ap_load_value[0]_i_2__2_n_0 ),
        .I2(\ap_load_value[3]_i_3__2_n_0 ),
        .O(\ap_load_value[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    \ap_load_value[0]_i_2__2 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .I3(\cmd_bank_cas_reg[1]_0 [1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .O(\ap_load_value[0]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2767" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \ap_load_value[1]_i_1__2 
       (.I0(\ap_load_value[3]_i_2__2_n_0 ),
        .I1(\ap_load_value[3]_i_3__2_n_0 ),
        .I2(wrReqR_reg_0),
        .O(\ap_load_value[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2767" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \ap_load_value[2]_i_1__2 
       (.I0(\ap_load_value[3]_i_2__2_n_0 ),
        .I1(\ap_load_value[3]_i_3__2_n_0 ),
        .I2(wrReqR_reg_0),
        .O(\ap_load_value[2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2768" *) 
  LUT3 #(
    .INIT(8'hF1)) 
    \ap_load_value[3]_i_1__2 
       (.I0(\ap_load_value[3]_i_2__2_n_0 ),
        .I1(\ap_load_value[3]_i_3__2_n_0 ),
        .I2(wrReqR_reg_0),
        .O(\ap_load_value[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h33000F5533FF0F55)) 
    \ap_load_value[3]_i_2__2 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .I3(\cmd_bank_cas_reg[1]_0 [0]),
        .I4(\cmd_bank_cas_reg[1]_0 [1]),
        .I5(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .O(\ap_load_value[3]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    \ap_load_value[3]_i_3__2 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .I3(\cmd_bank_cas_reg[1]_0 [1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .O(\ap_load_value[3]_i_3__2_n_0 ));
  FDRE \ap_load_value_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_load_value[0]_i_1__2_n_0 ),
        .Q(\ap_load_value_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \ap_load_value_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_load_value[1]_i_1__2_n_0 ),
        .Q(\ap_load_value_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \ap_load_value_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_load_value[2]_i_1__2_n_0 ),
        .Q(\ap_load_value_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \ap_load_value_reg[3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_load_value[3]_i_1__2_n_0 ),
        .Q(\ap_load_value_reg_n_0_[3] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    app_rdy_r_i_2
       (.I0(grAccept_ns),
        .I1(accept_reg_1),
        .I2(app_rdy_r_reg[0]),
        .I3(app_rdy_r_reg[1]),
        .O(accept_ns));
  (* SOFT_HLUTNM = "soft_lutpair2723" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][0]_i_1 
       (.I0(\buf_fifo_reg_n_0_[0][0] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][0]_0 ),
        .O(\buf_fifo[0][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCF0AA00CCF0AA)) 
    \buf_fifo[0][0]_i_3__2 
       (.I0(\buf_fifo_reg_n_0_[0][0] ),
        .I1(\buf_fifo_reg_n_0_[1][0] ),
        .I2(\buf_fifo_reg_n_0_[2][0] ),
        .I3(\txn_fifo_wptr_reg_n_0_[1] ),
        .I4(\txn_fifo_wptr_reg_n_0_[0] ),
        .I5(\buf_fifo_reg_n_0_[3][0] ),
        .O(\buf_fifo_reg[0][0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2725" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][1]_i_1 
       (.I0(\buf_fifo_reg_n_0_[0][1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][1]_0 ),
        .O(\buf_fifo[0][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \buf_fifo[0][1]_i_3__2 
       (.I0(\buf_fifo_reg_n_0_[0][1] ),
        .I1(\buf_fifo_reg_n_0_[1][1] ),
        .I2(\buf_fifo_reg_n_0_[3][1] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[2][1] ),
        .O(\buf_fifo_reg[0][1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2724" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][2]_i_1 
       (.I0(\buf_fifo_reg_n_0_[0][2] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][2]_0 ),
        .O(\buf_fifo[0][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \buf_fifo[0][2]_i_3__2 
       (.I0(\buf_fifo_reg_n_0_[0][2] ),
        .I1(\buf_fifo_reg_n_0_[1][2] ),
        .I2(\buf_fifo_reg_n_0_[3][2] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[2][2] ),
        .O(\buf_fifo_reg[0][2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2726" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][3]_i_1 
       (.I0(\buf_fifo_reg_n_0_[0][3] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][3]_0 ),
        .O(\buf_fifo[0][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAFFF0CCAA00F0)) 
    \buf_fifo[0][3]_i_3__2 
       (.I0(\buf_fifo_reg_n_0_[2][3] ),
        .I1(\buf_fifo_reg_n_0_[3][3] ),
        .I2(\buf_fifo_reg_n_0_[0][3] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[1][3] ),
        .O(\buf_fifo_reg[2][3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2728" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][4]_i_1 
       (.I0(\buf_fifo_reg_n_0_[0][4] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][4]_0 ),
        .O(\buf_fifo[0][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \buf_fifo[0][4]_i_3__2 
       (.I0(\buf_fifo_reg_n_0_[0][4] ),
        .I1(\buf_fifo_reg_n_0_[1][4] ),
        .I2(\buf_fifo_reg_n_0_[3][4] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[2][4] ),
        .O(\buf_fifo_reg[0][4]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2723" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][0]_i_1 
       (.I0(\buf_fifo_reg_n_0_[1][0] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][0]_0 ),
        .O(\buf_fifo[1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2725" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][1]_i_1 
       (.I0(\buf_fifo_reg_n_0_[1][1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][1]_0 ),
        .O(\buf_fifo[1][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2724" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][2]_i_1 
       (.I0(\buf_fifo_reg_n_0_[1][2] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][2]_0 ),
        .O(\buf_fifo[1][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2726" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][3]_i_1 
       (.I0(\buf_fifo_reg_n_0_[1][3] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][3]_0 ),
        .O(\buf_fifo[1][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2728" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][4]_i_1 
       (.I0(\buf_fifo_reg_n_0_[1][4] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][4]_0 ),
        .O(\buf_fifo[1][4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2719" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][0]_i_1 
       (.I0(\buf_fifo_reg_n_0_[2][0] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][0]_0 ),
        .O(\buf_fifo[2][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2721" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][1]_i_1 
       (.I0(\buf_fifo_reg_n_0_[2][1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][1]_0 ),
        .O(\buf_fifo[2][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2720" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][2]_i_1 
       (.I0(\buf_fifo_reg_n_0_[2][2] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][2]_0 ),
        .O(\buf_fifo[2][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2722" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][3]_i_1 
       (.I0(\buf_fifo_reg_n_0_[2][3] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][3]_0 ),
        .O(\buf_fifo[2][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2727" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][4]_i_1 
       (.I0(\buf_fifo_reg_n_0_[2][4] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][4]_0 ),
        .O(\buf_fifo[2][4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2719" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][0]_i_1 
       (.I0(\buf_fifo_reg_n_0_[3][0] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][0]_0 ),
        .O(\buf_fifo[3][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2721" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][1]_i_1 
       (.I0(\buf_fifo_reg_n_0_[3][1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][1]_0 ),
        .O(\buf_fifo[3][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2720" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][2]_i_1 
       (.I0(\buf_fifo_reg_n_0_[3][2] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][2]_0 ),
        .O(\buf_fifo[3][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2722" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][3]_i_1 
       (.I0(\buf_fifo_reg_n_0_[3][3] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][3]_0 ),
        .O(\buf_fifo[3][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2727" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][4]_i_1 
       (.I0(\buf_fifo_reg_n_0_[3][4] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][4]_0 ),
        .O(\buf_fifo[3][4]_i_1_n_0 ));
  FDRE \buf_fifo_reg[0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[0][0]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][0] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[0][1]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][1] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[0][2]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][2] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[0][3]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][3] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[0][4]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][4] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[1][0]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][0] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[1][1]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][1] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[1][2]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][2] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[1][3]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][3] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[1][4]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][4] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[2][0]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][0] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[2][1]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][1] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[2][2]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][2] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[2][3]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][3] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[2][4]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][4] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[3][0]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][0] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[3][1]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][1] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[3][2]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][2] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[3][3]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][3] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[3][4]_i_1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][0]_i_1 
       (.I0(\buf_fifo[3][0]_i_1_n_0 ),
        .I1(\buf_fifo[2][0]_i_1_n_0 ),
        .I2(\buf_fifo[1][0]_i_1_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][0]_i_1_n_0 ),
        .O(\cas_dbuf_fifo[0][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][1]_i_1 
       (.I0(\buf_fifo[3][1]_i_1_n_0 ),
        .I1(\buf_fifo[2][1]_i_1_n_0 ),
        .I2(\buf_fifo[1][1]_i_1_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][1]_i_1_n_0 ),
        .O(\cas_dbuf_fifo[0][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][2]_i_1 
       (.I0(\buf_fifo[3][2]_i_1_n_0 ),
        .I1(\buf_fifo[2][2]_i_1_n_0 ),
        .I2(\buf_fifo[1][2]_i_1_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][2]_i_1_n_0 ),
        .O(\cas_dbuf_fifo[0][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][3]_i_1 
       (.I0(\buf_fifo[3][3]_i_1_n_0 ),
        .I1(\buf_fifo[2][3]_i_1_n_0 ),
        .I2(\buf_fifo[1][3]_i_1_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][3]_i_1_n_0 ),
        .O(\cas_dbuf_fifo[0][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][4]_i_1 
       (.I0(\buf_fifo[3][4]_i_1_n_0 ),
        .I1(\buf_fifo[2][4]_i_1_n_0 ),
        .I2(\buf_fifo[1][4]_i_1_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][4]_i_1_n_0 ),
        .O(\cas_dbuf_fifo[0][4]_i_1_n_0 ));
  FDRE \cas_dbuf_fifo_reg[0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][0]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][0] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][1]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][1] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][2]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][2] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][3]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][3] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][4]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][4] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][0]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][0] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][1]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][1] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][2]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][2] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][3]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][3] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][4]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][4] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][0]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][0] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][1]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][1] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][2]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][2] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][3]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][3] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][4]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][4] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][0]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][0] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][1]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][1] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][2]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][2] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][3]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][3] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\cas_dbuf_fifo[0][4]_i_1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h1824824182412418)) 
    cas_fifo_empty_i_1__2
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_rptr_reg_n_0_[0] ),
        .I2(\cas_fifo_rptr[1]_i_2__2_n_0 ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ),
        .I5(\cas_fifo_wptr_reg_n_0_[0] ),
        .O(cas_fifo_empty_i_1__2_n_0));
  FDRE cas_fifo_empty_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(cas_fifo_empty_i_1__2_n_0),
        .Q(cas_fifo_empty_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h1E78871EE18778E1)) 
    cas_fifo_full_i_1__2
       (.I0(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .I2(\cas_fifo_rptr_reg_n_0_[1] ),
        .I3(\cas_fifo_rptr[1]_i_2__2_n_0 ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_fifo_wptr_reg_n_0_[1] ),
        .O(cas_fifo_full_i_1__2_n_0));
  FDRE cas_fifo_full_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(cas_fifo_full_i_1__2_n_0),
        .Q(cas_fifo_full_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h10FFFFFFEF000000)) 
    \cas_fifo_rptr[0]_i_1__2 
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[0]),
        .I3(\cas_fifo_rptr_reg[0]_0 ),
        .I4(tranSentC),
        .I5(\cas_fifo_rptr_reg_n_0_[0] ),
        .O(\cas_fifo_rptr[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2766" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \cas_fifo_rptr[1]_i_1__2 
       (.I0(\cas_fifo_rptr_reg_n_0_[1] ),
        .I1(\cas_fifo_rptr[1]_i_2__2_n_0 ),
        .I2(\cas_fifo_rptr_reg_n_0_[0] ),
        .O(\cas_fifo_rptr[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2706" *) 
  LUT5 #(
    .INIT(32'h10FFFFFF)) 
    \cas_fifo_rptr[1]_i_2__2 
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[0]),
        .I3(\cas_fifo_rptr_reg[0]_0 ),
        .I4(tranSentC),
        .O(\cas_fifo_rptr[1]_i_2__2_n_0 ));
  FDRE \cas_fifo_rptr_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_rptr[0]_i_1__2_n_0 ),
        .Q(\cas_fifo_rptr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cas_fifo_rptr_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_rptr[1]_i_1__2_n_0 ),
        .Q(\cas_fifo_rptr_reg_n_0_[1] ),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hFF10FF10FF100000)) 
    \cas_fifo_valid[0]_i_1__2 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr_reg_n_0_[1] ),
        .I2(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ),
        .I3(\cas_fifo_valid_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr[1]_i_2__2_n_0 ),
        .I5(\cas_fifo_valid[0]_i_2__2_n_0 ),
        .O(\cas_fifo_valid[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2766" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \cas_fifo_valid[0]_i_2__2 
       (.I0(\cas_fifo_rptr_reg_n_0_[0] ),
        .I1(\cas_fifo_rptr_reg_n_0_[1] ),
        .O(\cas_fifo_valid[0]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFF40FF40FF400000)) 
    \cas_fifo_valid[1]_i_1__2 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .I2(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ),
        .I3(\cas_fifo_valid_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr[1]_i_2__2_n_0 ),
        .I5(\cas_fifo_valid[1]_i_2__2_n_0 ),
        .O(\cas_fifo_valid[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2784" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \cas_fifo_valid[1]_i_2__2 
       (.I0(\cas_fifo_rptr_reg_n_0_[1] ),
        .I1(\cas_fifo_rptr_reg_n_0_[0] ),
        .O(\cas_fifo_valid[1]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFF40FF40FF400000)) 
    \cas_fifo_valid[2]_i_1__2 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr_reg_n_0_[1] ),
        .I2(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ),
        .I3(\cas_fifo_valid_reg_n_0_[2] ),
        .I4(\cas_fifo_rptr[1]_i_2__2_n_0 ),
        .I5(\cas_fifo_valid[2]_i_2__2_n_0 ),
        .O(\cas_fifo_valid[2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2784" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \cas_fifo_valid[2]_i_2__2 
       (.I0(\cas_fifo_rptr_reg_n_0_[0] ),
        .I1(\cas_fifo_rptr_reg_n_0_[1] ),
        .O(\cas_fifo_valid[2]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFF80FF80FF800000)) 
    \cas_fifo_valid[3]_i_1__2 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .I2(\cas_fifo_wptr_reg_n_0_[1] ),
        .I3(\cas_fifo_valid_reg_n_0_[3] ),
        .I4(\cas_fifo_rptr[1]_i_2__2_n_0 ),
        .I5(\cas_fifo_valid[3]_i_2__2_n_0 ),
        .O(\cas_fifo_valid[3]_i_1__2_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \cas_fifo_valid[3]_i_2__2 
       (.I0(\cas_fifo_rptr_reg_n_0_[0] ),
        .I1(\cas_fifo_rptr_reg_n_0_[1] ),
        .O(\cas_fifo_valid[3]_i_2__2_n_0 ));
  FDRE \cas_fifo_valid_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_valid[0]_i_1__2_n_0 ),
        .Q(\cas_fifo_valid_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cas_fifo_valid_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_valid[1]_i_1__2_n_0 ),
        .Q(\cas_fifo_valid_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \cas_fifo_valid_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_valid[2]_i_1__2_n_0 ),
        .Q(\cas_fifo_valid_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \cas_fifo_valid_reg[3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_valid[3]_i_1__2_n_0 ),
        .Q(\cas_fifo_valid_reg_n_0_[3] ),
        .R(rst_r1));
  LUT2 #(
    .INIT(4'h6)) 
    \cas_fifo_wptr[0]_i_1__0 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ),
        .O(\cas_fifo_wptr[0]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h6A)) 
    \cas_fifo_wptr[1]_i_1__0 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .I2(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ),
        .O(\cas_fifo_wptr[1]_i_1__0_n_0 ));
  FDRE \cas_fifo_wptr_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_wptr[0]_i_1__0_n_0 ),
        .Q(\cas_fifo_wptr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cas_fifo_wptr_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_wptr[1]_i_1__0_n_0 ),
        .Q(\cas_fifo_wptr_reg_n_0_[1] ),
        .R(rst_r1));
  LUT2 #(
    .INIT(4'h1)) 
    \cas_pend_fifo[0][47]_i_1__1 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .O(\cas_pend_fifo[0][47]_i_1__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cas_pend_fifo[1][47]_i_1__1 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr_reg_n_0_[1] ),
        .O(\cas_pend_fifo[1][47]_i_1__1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cas_pend_fifo[2][47]_i_1__1 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .O(\cas_pend_fifo[2][47]_i_1__1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \cas_pend_fifo[3][47]_i_1__1 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .O(\cas_pend_fifo[3][47]_i_1__1_n_0 ));
  FDRE \cas_pend_fifo_reg[0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg_n_0_[0][0] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg_n_0_[0][1] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[0][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[0][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[0][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[0][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[0][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[0][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[0][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[0][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[0][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[0][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[0][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[0][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[0][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[0][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[0][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[0][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[0][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[0][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][47] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg_n_0_[1][0] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg_n_0_[1][1] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[1][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[1][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[1][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[1][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[1][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[1][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[1][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[1][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[1][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[1][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[1][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[1][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[1][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[1][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[1][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[1][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[1][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[1][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][47] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg_n_0_[2][0] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg_n_0_[2][1] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[2][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[2][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[2][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[2][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[2][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[2][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[2][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[2][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[2][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[2][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[2][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[2][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[2][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[2][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[2][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[2][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[2][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[2][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][47] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg_n_0_[3][0] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg_n_0_[3][1] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[3][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[3][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[3][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[3][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[3][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[3][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[3][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[3][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[3][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[3][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[3][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[3][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[3][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[3][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[3][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[3][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[3][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[3][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1__1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][47] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2769" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    cmdAP_i_1__2
       (.I0(\txn_fifo_output_reg_n_0_[47] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(cmdAP_i_2__2_n_0),
        .O(cmdAP_i_1__2_n_0));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    cmdAP_i_2__2
       (.I0(\cas_pend_fifo_reg_n_0_[2][47] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][47] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][47] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][47] ),
        .O(cmdAP_i_2__2_n_0));
  FDRE cmdAP_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(cmdAP_i_1__2_n_0),
        .Q(cmdAP),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h00000001)) 
    \cmdBankP[1]_i_1__1 
       (.I0(grSt[2]),
        .I1(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I2(\cmdBankP[1]_i_2_n_0 ),
        .I3(\cmdBankP[1]_i_3__0_n_0 ),
        .I4(\issue_cas3_inferred__0/i__carry_n_2 ),
        .O(\cmdBankP[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAEFFFFFFFFFF)) 
    \cmdBankP[1]_i_2 
       (.I0(\cmdBankP[1]_i_4__1_n_0 ),
        .I1(txn_fifo_empty_reg_n_0),
        .I2(txn_fifo_empty_i_2_n_0),
        .I3(\cmdBankP[1]_i_5__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_5__1_n_0 ),
        .I5(\cmdBankP[1]_i_6__1_n_0 ),
        .O(\cmdBankP[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0F5500330F55FF33)) 
    \cmdBankP[1]_i_3__0 
       (.I0(\pageInfo_reg_n_0_[0][0][2][0] ),
        .I1(\pageInfo_reg_n_0_[0][0][0][0] ),
        .I2(\pageInfo_reg_n_0_[0][0][3][0] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][1][0] ),
        .O(\cmdBankP[1]_i_3__0_n_0 ));
  LUT5 #(
    .INIT(32'h82000082)) 
    \cmdBankP[1]_i_4__1 
       (.I0(\cas_fifo_valid_reg_n_0_[0] ),
        .I1(Q[0]),
        .I2(\cas_pend_fifo_reg_n_0_[0][0] ),
        .I3(Q[1]),
        .I4(\cas_pend_fifo_reg_n_0_[0][1] ),
        .O(\cmdBankP[1]_i_4__1_n_0 ));
  LUT5 #(
    .INIT(32'h6FFFFF6F)) 
    \cmdBankP[1]_i_5__1 
       (.I0(\cas_pend_fifo_reg_n_0_[3][1] ),
        .I1(Q[1]),
        .I2(\cas_fifo_valid_reg_n_0_[3] ),
        .I3(Q[0]),
        .I4(\cas_pend_fifo_reg_n_0_[3][0] ),
        .O(\cmdBankP[1]_i_5__1_n_0 ));
  LUT5 #(
    .INIT(32'h6FF6FFFF)) 
    \cmdBankP[1]_i_6__1 
       (.I0(Q[0]),
        .I1(\cas_pend_fifo_reg_n_0_[1][0] ),
        .I2(Q[1]),
        .I3(\cas_pend_fifo_reg_n_0_[1][1] ),
        .I4(\cas_fifo_valid_reg_n_0_[1] ),
        .O(\cmdBankP[1]_i_6__1_n_0 ));
  FDRE \cmdBankP_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cmdBankP[1]_i_1__1_n_0 ),
        .D(Q[0]),
        .Q(\cmdBankP_reg[1]_0 [0]),
        .R(rst_r1));
  FDRE \cmdBankP_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cmdBankP[1]_i_1__1_n_0 ),
        .D(Q[1]),
        .Q(\cmdBankP_reg[1]_0 [1]),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdBuf[0]_i_1__2 
       (.I0(\cas_dbuf_fifo_reg_n_0_[2][0] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[3][0] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[0][0] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[1][0] ),
        .O(\cmdBuf[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdBuf[1]_i_1__2 
       (.I0(\cas_dbuf_fifo_reg_n_0_[2][1] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[3][1] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[0][1] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[1][1] ),
        .O(\cmdBuf[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdBuf[2]_i_1__2 
       (.I0(\cas_dbuf_fifo_reg_n_0_[2][2] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[3][2] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[0][2] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[1][2] ),
        .O(\cmdBuf[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cmdBuf[3]_i_1__2 
       (.I0(\cas_dbuf_fifo_reg_n_0_[3][3] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[1][3] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[2][3] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[0][3] ),
        .O(\cmdBuf[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdBuf[4]_i_1__2 
       (.I0(\cas_dbuf_fifo_reg_n_0_[2][4] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[3][4] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[0][4] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[1][4] ),
        .O(\cmdBuf[4]_i_1__2_n_0 ));
  FDRE \cmdBuf_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdBuf[0]_i_1__2_n_0 ),
        .Q(cmdBuf[0]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdBuf[1]_i_1__2_n_0 ),
        .Q(cmdBuf[1]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdBuf[2]_i_1__2_n_0 ),
        .Q(cmdBuf[2]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdBuf[3]_i_1__2_n_0 ),
        .Q(cmdBuf[3]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdBuf[4]_i_1__2_n_0 ),
        .Q(cmdBuf[4]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2770" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[3]_i_1__2 
       (.I0(\txn_fifo_output_reg_n_0_[11] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[3]_i_2__2_n_0 ),
        .O(\cmdCol[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[3]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][11] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][11] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][11] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][11] ),
        .O(\cmdCol[3]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2770" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[4]_i_1__2 
       (.I0(\txn_fifo_output_reg_n_0_[12] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[4]_i_2__2_n_0 ),
        .O(\cmdCol[4]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[4]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][12] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][12] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][12] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][12] ),
        .O(\cmdCol[4]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2771" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[5]_i_1__2 
       (.I0(\txn_fifo_output_reg_n_0_[13] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[5]_i_2__2_n_0 ),
        .O(\cmdCol[5]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[5]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][13] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][13] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][13] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][13] ),
        .O(\cmdCol[5]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2771" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[6]_i_1__2 
       (.I0(\txn_fifo_output_reg_n_0_[14] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[6]_i_2__2_n_0 ),
        .O(\cmdCol[6]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[6]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][14] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][14] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][14] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][14] ),
        .O(\cmdCol[6]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2772" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[7]_i_1__2 
       (.I0(\txn_fifo_output_reg_n_0_[15] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[7]_i_2__2_n_0 ),
        .O(\cmdCol[7]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[7]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][15] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][15] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][15] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][15] ),
        .O(\cmdCol[7]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2772" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[8]_i_1__2 
       (.I0(\txn_fifo_output_reg_n_0_[16] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[8]_i_2__2_n_0 ),
        .O(\cmdCol[8]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[8]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][16] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][16] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][16] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][16] ),
        .O(\cmdCol[8]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2773" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[9]_i_1__2 
       (.I0(\txn_fifo_output_reg_n_0_[17] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[9]_i_2__2_n_0 ),
        .O(\cmdCol[9]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[9]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][17] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][17] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][17] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][17] ),
        .O(\cmdCol[9]_i_2__2_n_0 ));
  FDRE \cmdCol_reg[3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[3]_i_1__2_n_0 ),
        .Q(\cmdCol_reg[9]_0 [0]),
        .R(rst_r1));
  FDRE \cmdCol_reg[4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[4]_i_1__2_n_0 ),
        .Q(\cmdCol_reg[9]_0 [1]),
        .R(rst_r1));
  FDRE \cmdCol_reg[5] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[5]_i_1__2_n_0 ),
        .Q(\cmdCol_reg[9]_0 [2]),
        .R(rst_r1));
  FDRE \cmdCol_reg[6] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[6]_i_1__2_n_0 ),
        .Q(\cmdCol_reg[9]_0 [3]),
        .R(rst_r1));
  FDRE \cmdCol_reg[7] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[7]_i_1__2_n_0 ),
        .Q(\cmdCol_reg[9]_0 [4]),
        .R(rst_r1));
  FDRE \cmdCol_reg[8] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[8]_i_1__2_n_0 ),
        .Q(\cmdCol_reg[9]_0 [5]),
        .R(rst_r1));
  FDRE \cmdCol_reg[9] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[9]_i_1__2_n_0 ),
        .Q(\cmdCol_reg[9]_0 [6]),
        .R(rst_r1));
  FDRE \cmdGroupP_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cmdBankP[1]_i_1__1_n_0 ),
        .D(Q[2]),
        .Q(cmdGroupP),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h70777070)) 
    cmdRmw_i_1__2
       (.I0(\cas_fifo_rptr_reg[0]_0 ),
        .I1(tranSentC),
        .I2(cmdRmw_reg_0),
        .I3(\FSM_sequential_gr_cas_state[2]_i_6__2_n_0 ),
        .I4(\FSM_sequential_gr_cas_state[2]_i_3__0_n_0 ),
        .O(cmdRmw_i_1__2_n_0));
  FDRE cmdRmw_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(cmdRmw_i_1__2_n_0),
        .Q(cmdRmw_reg_0),
        .R(rst_r1));
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_bank_cas[0]_i_1__2 
       (.I0(\cmd_bank_cas[0]_i_2__2_n_0 ),
        .O(\cmd_bank_cas[0]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'h3A)) 
    \cmd_bank_cas[0]_i_2__2 
       (.I0(\cmd_bank_cas[0]_i_3__0_n_0 ),
        .I1(Q[0]),
        .I2(cas_fifo_empty_reg_n_0),
        .O(\cmd_bank_cas[0]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    \cmd_bank_cas[0]_i_3__0 
       (.I0(\cas_pend_fifo_reg_n_0_[1][0] ),
        .I1(\cas_pend_fifo_reg_n_0_[0][0] ),
        .I2(\cas_pend_fifo_reg_n_0_[2][0] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[3][0] ),
        .O(\cmd_bank_cas[0]_i_3__0_n_0 ));
  LUT3 #(
    .INIT(8'hC5)) 
    \cmd_bank_cas[1]_i_1__2 
       (.I0(\cmd_bank_cas[1]_i_2__2_n_0 ),
        .I1(Q[1]),
        .I2(cas_fifo_empty_reg_n_0),
        .O(\cmd_bank_cas[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    \cmd_bank_cas[1]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[1][1] ),
        .I1(\cas_pend_fifo_reg_n_0_[0][1] ),
        .I2(\cas_pend_fifo_reg_n_0_[2][1] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[3][1] ),
        .O(\cmd_bank_cas[1]_i_2__2_n_0 ));
  FDRE \cmd_bank_cas_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_bank_cas[0]_i_1__2_n_0 ),
        .Q(\cmd_bank_cas_reg[1]_0 [0]),
        .R(rst_r1));
  FDRE \cmd_bank_cas_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_bank_cas[1]_i_1__2_n_0 ),
        .Q(\cmd_bank_cas_reg[1]_0 [1]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2769" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_group_cas[0]_i_1__2 
       (.I0(Q[2]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_group_cas[0]_i_2__2_n_0 ),
        .O(\cmd_group_cas[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_group_cas[0]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][2] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][2] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][2] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][2] ),
        .O(\cmd_group_cas[0]_i_2__2_n_0 ));
  FDRE \cmd_group_cas_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_group_cas[0]_i_1__2_n_0 ),
        .Q(cmd_group_cas),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2773" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[0]_i_1__2 
       (.I0(Q[3]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[0]_i_2__2_n_0 ),
        .O(\cmd_row_cas[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[0]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][24] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][24] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][24] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][24] ),
        .O(\cmd_row_cas[0]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2778" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[10]_i_1__2 
       (.I0(Q[13]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[10]_i_2__2_n_0 ),
        .O(\cmd_row_cas[10]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[10]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][34] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][34] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][34] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][34] ),
        .O(\cmd_row_cas[10]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2779" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[11]_i_1__2 
       (.I0(Q[14]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[11]_i_2__2_n_0 ),
        .O(\cmd_row_cas[11]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[11]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][35] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][35] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][35] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][35] ),
        .O(\cmd_row_cas[11]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2779" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[12]_i_1__2 
       (.I0(Q[15]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[12]_i_2__2_n_0 ),
        .O(\cmd_row_cas[12]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[12]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][36] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][36] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][36] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][36] ),
        .O(\cmd_row_cas[12]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2780" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[13]_i_1__2 
       (.I0(Q[16]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[13]_i_2__2_n_0 ),
        .O(\cmd_row_cas[13]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[13]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][37] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][37] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][37] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][37] ),
        .O(\cmd_row_cas[13]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2780" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[14]_i_1__2 
       (.I0(Q[17]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[14]_i_2__2_n_0 ),
        .O(\cmd_row_cas[14]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[14]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][38] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][38] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][38] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][38] ),
        .O(\cmd_row_cas[14]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2781" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[15]_i_1__2 
       (.I0(Q[18]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[15]_i_2__2_n_0 ),
        .O(\cmd_row_cas[15]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[15]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][39] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][39] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][39] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][39] ),
        .O(\cmd_row_cas[15]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2781" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[16]_i_1__2 
       (.I0(Q[19]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[16]_i_2__2_n_0 ),
        .O(\cmd_row_cas[16]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[16]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][40] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][40] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][40] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][40] ),
        .O(\cmd_row_cas[16]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2774" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[1]_i_1__2 
       (.I0(Q[4]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[1]_i_2__2_n_0 ),
        .O(\cmd_row_cas[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[1]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][25] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][25] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][25] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][25] ),
        .O(\cmd_row_cas[1]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2774" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[2]_i_1__2 
       (.I0(Q[5]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[2]_i_2__2_n_0 ),
        .O(\cmd_row_cas[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[2]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][26] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][26] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][26] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][26] ),
        .O(\cmd_row_cas[2]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2775" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[3]_i_1__2 
       (.I0(Q[6]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[3]_i_2__2_n_0 ),
        .O(\cmd_row_cas[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmd_row_cas[3]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][27] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][27] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][27] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_pend_fifo_reg_n_0_[0][27] ),
        .O(\cmd_row_cas[3]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2775" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[4]_i_1__2 
       (.I0(Q[7]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[4]_i_2__2_n_0 ),
        .O(\cmd_row_cas[4]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[4]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][28] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][28] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][28] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][28] ),
        .O(\cmd_row_cas[4]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2776" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[5]_i_1__2 
       (.I0(Q[8]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[5]_i_2__2_n_0 ),
        .O(\cmd_row_cas[5]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[5]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][29] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][29] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][29] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][29] ),
        .O(\cmd_row_cas[5]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2776" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[6]_i_1__2 
       (.I0(Q[9]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[6]_i_2__2_n_0 ),
        .O(\cmd_row_cas[6]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[6]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][30] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][30] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][30] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][30] ),
        .O(\cmd_row_cas[6]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2777" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[7]_i_1__2 
       (.I0(Q[10]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[7]_i_2__2_n_0 ),
        .O(\cmd_row_cas[7]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[7]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][31] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][31] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][31] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][31] ),
        .O(\cmd_row_cas[7]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2777" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[8]_i_1__2 
       (.I0(Q[11]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[8]_i_2__2_n_0 ),
        .O(\cmd_row_cas[8]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[8]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][32] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][32] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][32] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][32] ),
        .O(\cmd_row_cas[8]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2778" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[9]_i_1__2 
       (.I0(Q[12]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[9]_i_2__2_n_0 ),
        .O(\cmd_row_cas[9]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[9]_i_2__2 
       (.I0(\cas_pend_fifo_reg_n_0_[2][33] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][33] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][33] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][33] ),
        .O(\cmd_row_cas[9]_i_2__2_n_0 ));
  FDRE \cmd_row_cas_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[0]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[10] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[10]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[11]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[12]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[12] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[13]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[13] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[14]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[14] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[15]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[15] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[16]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[1]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[2]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[3]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[3] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[4]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[5] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[5]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[6] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[6]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[6] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[7] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[7]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[7] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[8] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[8]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[8] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[9] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[9]_i_1__2_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[9] ),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hF0CCAAFFF0CCAA00)) 
    i__carry_i_10__2
       (.I0(\pageInfo_reg_n_0_[0][0][1][16] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][16] ),
        .I2(\pageInfo_reg_n_0_[0][0][3][16] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][16] ),
        .O(i__carry_i_10__2_n_0));
  LUT6 #(
    .INIT(64'hCCFFF0AACC00F0AA)) 
    i__carry_i_11__2
       (.I0(\pageInfo_reg_n_0_[0][0][0][15] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][15] ),
        .I2(\pageInfo_reg_n_0_[0][0][2][15] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\pageInfo_reg_n_0_[0][0][1][15] ),
        .O(i__carry_i_11__2_n_0));
  LUT6 #(
    .INIT(64'h0055330FFF55330F)) 
    i__carry_i_12__2
       (.I0(\pageInfo_reg_n_0_[0][0][2][11] ),
        .I1(\pageInfo_reg_n_0_[0][0][1][11] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][11] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][3][11] ),
        .O(i__carry_i_12__2_n_0));
  LUT6 #(
    .INIT(64'hF0CCAAFFF0CCAA00)) 
    i__carry_i_13__2
       (.I0(\pageInfo_reg_n_0_[0][0][1][13] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][13] ),
        .I2(\pageInfo_reg_n_0_[0][0][3][13] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][13] ),
        .O(i__carry_i_13__2_n_0));
  LUT6 #(
    .INIT(64'hF0CCAAFFF0CCAA00)) 
    i__carry_i_14__2
       (.I0(\pageInfo_reg_n_0_[0][0][1][12] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][12] ),
        .I2(\pageInfo_reg_n_0_[0][0][3][12] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][12] ),
        .O(i__carry_i_14__2_n_0));
  LUT6 #(
    .INIT(64'h0F0033550FFF3355)) 
    i__carry_i_15__2
       (.I0(\pageInfo_reg_n_0_[0][0][0][9] ),
        .I1(\pageInfo_reg_n_0_[0][0][1][9] ),
        .I2(\pageInfo_reg_n_0_[0][0][3][9] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][9] ),
        .O(i__carry_i_15__2_n_0));
  LUT6 #(
    .INIT(64'hF0CCAAFFF0CCAA00)) 
    i__carry_i_16__2
       (.I0(\pageInfo_reg_n_0_[0][0][1][8] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][8] ),
        .I2(\pageInfo_reg_n_0_[0][0][3][8] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][8] ),
        .O(i__carry_i_16__2_n_0));
  LUT6 #(
    .INIT(64'hFFCCF0AA00CCF0AA)) 
    i__carry_i_17__2
       (.I0(\pageInfo_reg_n_0_[0][0][0][10] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][10] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][10] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][3][10] ),
        .O(i__carry_i_17__2_n_0));
  LUT6 #(
    .INIT(64'h0033550FFF33550F)) 
    i__carry_i_18__2
       (.I0(\pageInfo_reg_n_0_[0][0][1][5] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][5] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][5] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][3][5] ),
        .O(i__carry_i_18__2_n_0));
  LUT6 #(
    .INIT(64'hFFAAF0CC00AAF0CC)) 
    i__carry_i_19__2
       (.I0(\pageInfo_reg_n_0_[0][0][1][7] ),
        .I1(\pageInfo_reg_n_0_[0][0][0][7] ),
        .I2(\pageInfo_reg_n_0_[0][0][2][7] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\pageInfo_reg_n_0_[0][0][3][7] ),
        .O(i__carry_i_19__2_n_0));
  LUT4 #(
    .INIT(16'h6006)) 
    i__carry_i_1__2
       (.I0(i__carry_i_7__2_n_0),
        .I1(Q[18]),
        .I2(i__carry_i_8__2_n_0),
        .I3(Q[19]),
        .O(i__carry_i_1__2_n_0));
  LUT6 #(
    .INIT(64'hFFAAF0CC00AAF0CC)) 
    i__carry_i_20__2
       (.I0(\pageInfo_reg_n_0_[0][0][1][6] ),
        .I1(\pageInfo_reg_n_0_[0][0][0][6] ),
        .I2(\pageInfo_reg_n_0_[0][0][2][6] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\pageInfo_reg_n_0_[0][0][3][6] ),
        .O(i__carry_i_20__2_n_0));
  LUT6 #(
    .INIT(64'h33000F5533FF0F55)) 
    i__carry_i_21__2
       (.I0(\pageInfo_reg_n_0_[0][0][0][3] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][3] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][3] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][3] ),
        .O(i__carry_i_21__2_n_0));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    i__carry_i_22__2
       (.I0(\pageInfo_reg_n_0_[0][0][2][2] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][2] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][2] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][2] ),
        .O(i__carry_i_22__2_n_0));
  LUT6 #(
    .INIT(64'hAACCFFF0AACC00F0)) 
    i__carry_i_23__2
       (.I0(\pageInfo_reg_n_0_[0][0][3][4] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][4] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][4] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][1][4] ),
        .O(i__carry_i_23__2_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_2__2
       (.I0(i__carry_i_9__2_n_0),
        .I1(Q[15]),
        .I2(Q[17]),
        .I3(i__carry_i_10__2_n_0),
        .I4(Q[16]),
        .I5(i__carry_i_11__2_n_0),
        .O(i__carry_i_2__2_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_3__2
       (.I0(i__carry_i_12__2_n_0),
        .I1(Q[12]),
        .I2(Q[14]),
        .I3(i__carry_i_13__2_n_0),
        .I4(Q[13]),
        .I5(i__carry_i_14__2_n_0),
        .O(i__carry_i_3__2_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_4__2
       (.I0(i__carry_i_15__2_n_0),
        .I1(Q[10]),
        .I2(Q[9]),
        .I3(i__carry_i_16__2_n_0),
        .I4(Q[11]),
        .I5(i__carry_i_17__2_n_0),
        .O(i__carry_i_4__2_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_5__2
       (.I0(i__carry_i_18__2_n_0),
        .I1(Q[6]),
        .I2(Q[8]),
        .I3(i__carry_i_19__2_n_0),
        .I4(Q[7]),
        .I5(i__carry_i_20__2_n_0),
        .O(i__carry_i_5__2_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_6__2
       (.I0(i__carry_i_21__2_n_0),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(i__carry_i_22__2_n_0),
        .I4(Q[5]),
        .I5(i__carry_i_23__2_n_0),
        .O(i__carry_i_6__2_n_0));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    i__carry_i_7__2
       (.I0(\pageInfo_reg_n_0_[0][0][1][17] ),
        .I1(\pageInfo_reg_n_0_[0][0][0][17] ),
        .I2(\pageInfo_reg_n_0_[0][0][2][17] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\pageInfo_reg_n_0_[0][0][3][17] ),
        .O(i__carry_i_7__2_n_0));
  LUT6 #(
    .INIT(64'hF0CCAAFFF0CCAA00)) 
    i__carry_i_8__2
       (.I0(\pageInfo_reg_n_0_[0][0][1][18] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][18] ),
        .I2(\pageInfo_reg_n_0_[0][0][3][18] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][18] ),
        .O(i__carry_i_8__2_n_0));
  LUT6 #(
    .INIT(64'h0033550FFF33550F)) 
    i__carry_i_9__2
       (.I0(\pageInfo_reg_n_0_[0][0][1][14] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][14] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][14] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][3][14] ),
        .O(i__carry_i_9__2_n_0));
  CARRY8 \issue_cas3_inferred__0/i__carry 
       (.CI(1'b1),
        .CI_TOP(1'b0),
        .CO({\NLW_issue_cas3_inferred__0/i__carry_CO_UNCONNECTED [7:6],\issue_cas3_inferred__0/i__carry_n_2 ,\issue_cas3_inferred__0/i__carry_n_3 ,\issue_cas3_inferred__0/i__carry_n_4 ,\issue_cas3_inferred__0/i__carry_n_5 ,\issue_cas3_inferred__0/i__carry_n_6 ,\issue_cas3_inferred__0/i__carry_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O(\NLW_issue_cas3_inferred__0/i__carry_O_UNCONNECTED [7:0]),
        .S({1'b0,1'b0,i__carry_i_1__2_n_0,i__carry_i_2__2_n_0,i__carry_i_3__2_n_0,i__carry_i_4__2_n_0,i__carry_i_5__2_n_0,i__carry_i_6__2_n_0}));
  LUT2 #(
    .INIT(4'h2)) 
    last32_i_3
       (.I0(actReqR_reg_0),
        .I1(\FSM_sequential_grSt_reg[0]_0 ),
        .O(actReq));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \pageInfo[0][0][0][0]_i_1__2 
       (.I0(\pageInfo[0][0][0][0]_i_2__2_n_0 ),
        .I1(grSt[2]),
        .I2(grSt[0]),
        .I3(grSt[1]),
        .I4(\pageInfo[0][0][0][0]_i_3__2_n_0 ),
        .I5(sel0__62),
        .O(\pageInfo[0][0][0][0]_i_1__2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][0][0]_i_2__2 
       (.I0(rst_r1),
        .I1(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .O(\pageInfo[0][0][0][0]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2782" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \pageInfo[0][0][0][0]_i_3__2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\pageInfo[0][0][0][0]_i_3__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][10]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[8] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[11]),
        .O(\pageInfo[0][0][0][10]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][11]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[9] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][0][11]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][12]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[10] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][0][12]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][13]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[11] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][0][13]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][14]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[12] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][0][14]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][15]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[13] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][0][15]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][16]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[14] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[17]),
        .O(\pageInfo[0][0][0][16]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][17]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[15] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][0][17]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][0][18]_i_1__2 
       (.I0(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I1(sel0__62),
        .I2(\pageInfo[0][0][3][18]_i_3__2_n_0 ),
        .I3(\trcd_cntr[0][0][0][2]_i_2__2_n_0 ),
        .O(\pageInfo[0][0][0][18]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][18]_i_2__2 
       (.I0(\cmd_row_cas_reg_n_0_[16] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][0][18]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][0][1]_i_1__2 
       (.I0(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][0][1]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][2]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[0] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[3]),
        .O(\pageInfo[0][0][0][2]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][3]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[1] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][0][3]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][4]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[2] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[5]),
        .O(\pageInfo[0][0][0][4]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][5]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[3] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[6]),
        .O(\pageInfo[0][0][0][5]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][6]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[4] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[7]),
        .O(\pageInfo[0][0][0][6]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][7]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[5] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[8]),
        .O(\pageInfo[0][0][0][7]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][8]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[6] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][0][8]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][9]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[7] ),
        .I1(rst_r1),
        .I2(\ap_cntr_zero[0][0][0]_i_2__0_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][0][9]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \pageInfo[0][0][1][0]_i_1__2 
       (.I0(\pageInfo[0][0][1][0]_i_2__2_n_0 ),
        .I1(grSt[2]),
        .I2(grSt[0]),
        .I3(grSt[1]),
        .I4(\trp_cntr[1]_i_2__2_n_0 ),
        .I5(sel0__58),
        .O(\pageInfo[0][0][1][0]_i_1__2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][1][0]_i_2__2 
       (.I0(rst_r1),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .O(\pageInfo[0][0][1][0]_i_2__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][10]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[8] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I3(Q[11]),
        .O(\pageInfo[0][0][1][10]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][1][11]_i_1__2 
       (.I0(Q[12]),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[9] ),
        .O(\pageInfo[0][0][1][11]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][1][12]_i_1__2 
       (.I0(Q[13]),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[10] ),
        .O(\pageInfo[0][0][1][12]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][1][13]_i_1__2 
       (.I0(Q[14]),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[11] ),
        .O(\pageInfo[0][0][1][13]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][14]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[12] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][1][14]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][15]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[13] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][1][15]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][1][16]_i_1__2 
       (.I0(Q[17]),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[14] ),
        .O(\pageInfo[0][0][1][16]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][1][17]_i_1__2 
       (.I0(Q[18]),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[15] ),
        .O(\pageInfo[0][0][1][17]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][1][18]_i_1__2 
       (.I0(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I1(sel0__58),
        .I2(\pageInfo[0][0][3][18]_i_3__2_n_0 ),
        .I3(\trcd_cntr[0][0][1][2]_i_2__2_n_0 ),
        .O(\pageInfo[0][0][1][18]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][18]_i_2__2 
       (.I0(\cmd_row_cas_reg_n_0_[16] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][1][18]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][1][1]_i_1__2 
       (.I0(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][1][1]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][1][2]_i_1__2 
       (.I0(Q[3]),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[0] ),
        .O(\pageInfo[0][0][1][2]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][1][3]_i_1__2 
       (.I0(Q[4]),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[1] ),
        .O(\pageInfo[0][0][1][3]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][4]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[2] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I3(Q[5]),
        .O(\pageInfo[0][0][1][4]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][5]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[3] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I3(Q[6]),
        .O(\pageInfo[0][0][1][5]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][1][6]_i_1__2 
       (.I0(Q[7]),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[4] ),
        .O(\pageInfo[0][0][1][6]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][1][7]_i_1__2 
       (.I0(Q[8]),
        .I1(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[5] ),
        .O(\pageInfo[0][0][1][7]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][8]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[6] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][1][8]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][9]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[7] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__1_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][1][9]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \pageInfo[0][0][2][0]_i_1__2 
       (.I0(\pageInfo[0][0][2][0]_i_2__1_n_0 ),
        .I1(grSt[2]),
        .I2(grSt[0]),
        .I3(grSt[1]),
        .I4(\pageInfo[0][0][2][0]_i_3__1_n_0 ),
        .I5(sel0__54),
        .O(\pageInfo[0][0][2][0]_i_1__2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][2][0]_i_2__1 
       (.I0(rst_r1),
        .I1(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .O(\pageInfo[0][0][2][0]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2783" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \pageInfo[0][0][2][0]_i_3__1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\pageInfo[0][0][2][0]_i_3__1_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][10]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[8] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[11]),
        .O(\pageInfo[0][0][2][10]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][11]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[9] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][2][11]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][12]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[10] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][2][12]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][13]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[11] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][2][13]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][14]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[12] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][2][14]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][15]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[13] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][2][15]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][16]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[14] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[17]),
        .O(\pageInfo[0][0][2][16]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][17]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[15] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][2][17]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][2][18]_i_1__2 
       (.I0(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I1(sel0__54),
        .I2(\pageInfo[0][0][3][18]_i_3__2_n_0 ),
        .I3(\trcd_cntr[0][0][2][2]_i_2__2_n_0 ),
        .O(\pageInfo[0][0][2][18]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][18]_i_2__2 
       (.I0(\cmd_row_cas_reg_n_0_[16] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][2][18]_i_2__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][2][1]_i_1__2 
       (.I0(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][2][1]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][2]_i_1__2 
       (.I0(Q[3]),
        .I1(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[0] ),
        .O(\pageInfo[0][0][2][2]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][3]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[1] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][2][3]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][4]_i_1__2 
       (.I0(Q[5]),
        .I1(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[2] ),
        .O(\pageInfo[0][0][2][4]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][5]_i_1__2 
       (.I0(Q[6]),
        .I1(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[3] ),
        .O(\pageInfo[0][0][2][5]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][2][6]_i_1__2 
       (.I0(Q[7]),
        .I1(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[4] ),
        .O(\pageInfo[0][0][2][6]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][7]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[5] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[8]),
        .O(\pageInfo[0][0][2][7]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][8]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[6] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][2][8]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][9]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[7] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__2_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][2][9]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \pageInfo[0][0][3][0]_i_1__2 
       (.I0(\pageInfo[0][0][3][0]_i_2__2_n_0 ),
        .I1(grSt[2]),
        .I2(grSt[0]),
        .I3(grSt[1]),
        .I4(\pageInfo[0][0][3][0]_i_3_n_0 ),
        .I5(sel0__50),
        .O(\pageInfo[0][0][3][0]_i_1__2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][3][0]_i_2__2 
       (.I0(rst_r1),
        .I1(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .O(\pageInfo[0][0][3][0]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2783" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \pageInfo[0][0][3][0]_i_3 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\pageInfo[0][0][3][0]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][10]_i_1__2 
       (.I0(Q[11]),
        .I1(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[8] ),
        .O(\pageInfo[0][0][3][10]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][11]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[9] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][3][11]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][12]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[10] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][3][12]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][13]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[11] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][3][13]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][14]_i_1__2 
       (.I0(Q[15]),
        .I1(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[12] ),
        .O(\pageInfo[0][0][3][14]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][15]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[13] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][3][15]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][16]_i_1__2 
       (.I0(Q[17]),
        .I1(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[14] ),
        .O(\pageInfo[0][0][3][16]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][17]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[15] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][3][17]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][3][18]_i_1__2 
       (.I0(\pageInfo[0][0][3][18]_i_3__2_n_0 ),
        .I1(sel0__50),
        .I2(\trcd_cntr[0][0][3][2]_i_2__2_n_0 ),
        .I3(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .O(\pageInfo[0][0][3][18]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][18]_i_2__2 
       (.I0(\cmd_row_cas_reg_n_0_[16] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][3][18]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAEAAAAAAAAAAA)) 
    \pageInfo[0][0][3][18]_i_3__2 
       (.I0(rst_r1),
        .I1(refOK_reg_0),
        .I2(grSt[2]),
        .I3(grSt[1]),
        .I4(grSt[0]),
        .I5(refReq),
        .O(\pageInfo[0][0][3][18]_i_3__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][3][1]_i_1__2 
       (.I0(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][3][1]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][2]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[0] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I3(Q[3]),
        .O(\pageInfo[0][0][3][2]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][3]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[1] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][3][3]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][4]_i_1__2 
       (.I0(Q[5]),
        .I1(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[2] ),
        .O(\pageInfo[0][0][3][4]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][5]_i_1__2 
       (.I0(Q[6]),
        .I1(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[3] ),
        .O(\pageInfo[0][0][3][5]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][6]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[4] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I3(Q[7]),
        .O(\pageInfo[0][0][3][6]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][7]_i_1__2 
       (.I0(Q[8]),
        .I1(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[5] ),
        .O(\pageInfo[0][0][3][7]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0E02)) 
    \pageInfo[0][0][3][8]_i_1__2 
       (.I0(Q[9]),
        .I1(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I2(rst_r1),
        .I3(\cmd_row_cas_reg_n_0_[6] ),
        .O(\pageInfo[0][0][3][8]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][9]_i_1__2 
       (.I0(\cmd_row_cas_reg_n_0_[7] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__2_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][3][9]_i_1__2_n_0 ));
  FDRE \pageInfo_reg[0][0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][0]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][0] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][10] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][10]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][10] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][11]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][11] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][12]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][12] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][13]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][13] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][14]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][14] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][15]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][15] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][16]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][16] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][17]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][17] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][18] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][18]_i_2__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][18] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][1]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][1] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][2]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][2] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][3]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][3] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][4]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][4] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][5] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][5]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][5] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][6] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][6]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][6] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][7] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][7]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][7] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][8] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][8]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][8] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][9] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][0][9]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][9] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][0]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][0] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][10] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][10]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][10] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][11]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][11] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][12]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][12] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][13]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][13] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][14]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][14] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][15]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][15] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][16]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][16] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][17]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][17] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][18] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][18]_i_2__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][18] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][1]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][1] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][2]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][2] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][3]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][3] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][4]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][4] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][5] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][5]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][5] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][6] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][6]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][6] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][7] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][7]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][7] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][8] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][8]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][8] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][9] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][1][9]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][9] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][0]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][0] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][10] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][10]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][10] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][11]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][11] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][12]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][12] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][13]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][13] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][14]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][14] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][15]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][15] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][16]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][16] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][17]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][17] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][18] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][18]_i_2__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][18] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][1]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][1] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][2]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][2] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][3]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][3] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][4]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][4] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][5] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][5]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][5] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][6] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][6]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][6] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][7] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][7]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][7] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][8] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][8]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][8] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][9] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][2][9]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][9] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][0]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][0] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][10] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][10]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][10] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][11]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][11] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][12]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][12] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][13]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][13] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][14]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][14] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][15]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][15] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][16]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][16] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][17]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][17] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][18] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][18]_i_2__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][18] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][1]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][1] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][2]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][2] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][3]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][3] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][4]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][4] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][5] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][5]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][5] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][6] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][6]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][6] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][7] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][7]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][7] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][8] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][8]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][8] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][9] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__2_n_0 ),
        .D(\pageInfo[0][0][3][9]_i_1__2_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][9] ),
        .R(1'b0));
  FDRE periodic_read_or_ref_block_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(refReq),
        .Q(periodic_read_or_ref_block_reg_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00F8)) 
    preReqR_i_1
       (.I0(\FSM_sequential_grSt[2]_i_5__1_n_0 ),
        .I1(preReqR_i_2_n_0),
        .I2(preReqR_reg_0),
        .I3(preReqR_reg_1),
        .O(preReqR_i_1_n_0));
  LUT3 #(
    .INIT(8'h01)) 
    preReqR_i_2
       (.I0(\cmdBankP[1]_i_2_n_0 ),
        .I1(\cmdBankP[1]_i_3__0_n_0 ),
        .I2(\issue_cas3_inferred__0/i__carry_n_2 ),
        .O(preReqR_i_2_n_0));
  FDRE preReqR_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(preReqR_i_1_n_0),
        .Q(preReqR_reg_0),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h2A3F2A2A)) 
    rdReqR_i_1__2
       (.I0(rdReqR_reg_0),
        .I1(\cas_fifo_rptr_reg[0]_0 ),
        .I2(tranSentC),
        .I3(rdReqR_i_2__2_n_0),
        .I4(\FSM_sequential_gr_cas_state[2]_i_3__0_n_0 ),
        .O(rdReqR_i_1__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2705" *) 
  LUT5 #(
    .INIT(32'hCFFFCAFA)) 
    rdReqR_i_2__2
       (.I0(wrReqR_i_8__0_n_0),
        .I1(\txn_fifo_output_reg_n_0_[46] ),
        .I2(cas_fifo_empty_reg_n_0),
        .I3(\txn_fifo_output_reg_n_0_[44] ),
        .I4(wrReqR_i_6__1_n_0),
        .O(rdReqR_i_2__2_n_0));
  FDRE rdReqR_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(rdReqR_i_1__2_n_0),
        .Q(rdReqR_reg_0),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2718" *) 
  LUT5 #(
    .INIT(32'h08000000)) 
    refOK_i_1__2
       (.I0(grSt[2]),
        .I1(grSt[1]),
        .I2(grSt[0]),
        .I3(cas_fifo_empty_reg_n_0),
        .I4(ref_req_dly4),
        .O(refOK_i_1__2_n_0));
  FDRE refOK_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(refOK_i_1__2_n_0),
        .Q(refOK_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \refSt[3]_i_7 
       (.I0(refOK_reg_0),
        .I1(refOK[0]),
        .I2(refOK[1]),
        .I3(per_block_ref),
        .I4(refOK[2]),
        .O(refOK_reg_1));
  (* KEEP = "yes" *) 
  FDRE rst_r1_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(SR),
        .Q(rst_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2731" *) 
  LUT4 #(
    .INIT(16'hAAFE)) 
    \tras_cntr_rb[0][0][0][0]_i_1__2 
       (.I0(\trcd_cntr[0][0][0][2]_i_2__2_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .O(\tras_cntr_rb[0][0][0][0]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h00A4)) 
    \tras_cntr_rb[0][0][0][1]_i_1__2 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .I3(\trcd_cntr[0][0][0][2]_i_2__2_n_0 ),
        .O(\tras_cntr_rb[0][0][0][1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2731" *) 
  LUT4 #(
    .INIT(16'hFEAA)) 
    \tras_cntr_rb[0][0][0][2]_i_1__2 
       (.I0(\trcd_cntr[0][0][0][2]_i_2__2_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .O(\tras_cntr_rb[0][0][0][2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2734" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][1][0]_i_1__2 
       (.I0(\trcd_cntr[0][0][1][2]_i_2__2_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .O(\tras_cntr_rb[0][0][1][0]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][1][1]_i_1__2 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .I3(\trcd_cntr[0][0][1][2]_i_2__2_n_0 ),
        .O(\tras_cntr_rb[0][0][1][1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2734" *) 
  LUT4 #(
    .INIT(16'hFEAA)) 
    \tras_cntr_rb[0][0][1][2]_i_1__2 
       (.I0(\trcd_cntr[0][0][1][2]_i_2__2_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .O(\tras_cntr_rb[0][0][1][2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2733" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][2][0]_i_1__2 
       (.I0(\trcd_cntr[0][0][2][2]_i_2__2_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .O(\tras_cntr_rb[0][0][2][0]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][2][1]_i_1__2 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .I3(\trcd_cntr[0][0][2][2]_i_2__2_n_0 ),
        .O(\tras_cntr_rb[0][0][2][1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2733" *) 
  LUT4 #(
    .INIT(16'hFEAA)) 
    \tras_cntr_rb[0][0][2][2]_i_1__2 
       (.I0(\trcd_cntr[0][0][2][2]_i_2__2_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .O(\tras_cntr_rb[0][0][2][2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2732" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][3][0]_i_1__2 
       (.I0(\trcd_cntr[0][0][3][2]_i_2__2_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .O(\tras_cntr_rb[0][0][3][0]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][3][1]_i_1__2 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .I3(\trcd_cntr[0][0][3][2]_i_2__2_n_0 ),
        .O(\tras_cntr_rb[0][0][3][1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2732" *) 
  LUT4 #(
    .INIT(16'hFAEA)) 
    \tras_cntr_rb[0][0][3][2]_i_1__2 
       (.I0(\trcd_cntr[0][0][3][2]_i_2__2_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .O(\tras_cntr_rb[0][0][3][2]_i_1__2_n_0 ));
  FDRE \tras_cntr_rb_reg[0][0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][0][0]_i_1__2_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][0][1]_i_1__2_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][0][2]_i_1__2_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][1][0]_i_1__2_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][1][1]_i_1__2_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][1][2]_i_1__2_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][2][0]_i_1__2_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][2][1]_i_1__2_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][2][2]_i_1__2_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][3][0]_i_1__2_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][3][1]_i_1__2_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][3][2]_i_1__2_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2712" *) 
  LUT4 #(
    .INIT(16'h99F9)) 
    \trcd_cntr[0][0][0][0]_i_1__2 
       (.I0(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I1(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I2(\trcd_cntr[0][0][0][2]_i_2__2_n_0 ),
        .I3(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr[0][0][0][0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2712" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][0][1]_i_1__2 
       (.I0(\FSM_sequential_grSt_reg[0]_0 ),
        .I1(\trcd_cntr[0][0][0][2]_i_2__2_n_0 ),
        .I2(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .O(\trcd_cntr[0][0][0][1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][0][2]_i_1__2 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][0][2] ),
        .I4(\FSM_sequential_grSt_reg[0]_0 ),
        .I5(\trcd_cntr[0][0][0][2]_i_2__2_n_0 ),
        .O(\trcd_cntr[0][0][0][2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2708" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \trcd_cntr[0][0][0][2]_i_2__2 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\trcd_cntr[0][0][0][2]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0001)) 
    \trcd_cntr[0][0][0][3]_i_1__2 
       (.I0(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][0][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][0][3] ),
        .I5(\trcd_cntr_is_zero[0][0][0]_i_2__2_n_0 ),
        .O(\trcd_cntr[0][0][0][3]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2715" *) 
  LUT4 #(
    .INIT(16'h99F9)) 
    \trcd_cntr[0][0][1][0]_i_1__2 
       (.I0(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I1(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I2(\trcd_cntr[0][0][1][2]_i_2__2_n_0 ),
        .I3(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr[0][0][1][0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2715" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][1][1]_i_1__2 
       (.I0(\FSM_sequential_grSt_reg[0]_0 ),
        .I1(\trcd_cntr[0][0][1][2]_i_2__2_n_0 ),
        .I2(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .O(\trcd_cntr[0][0][1][1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][1][2]_i_1__2 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][1][2] ),
        .I4(\FSM_sequential_grSt_reg[0]_0 ),
        .I5(\trcd_cntr[0][0][1][2]_i_2__2_n_0 ),
        .O(\trcd_cntr[0][0][1][2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2710" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \trcd_cntr[0][0][1][2]_i_2__2 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\trcd_cntr[0][0][1][2]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0001)) 
    \trcd_cntr[0][0][1][3]_i_1__2 
       (.I0(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][1][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][1][3] ),
        .I5(\trcd_cntr_is_zero[0][0][1]_i_2__2_n_0 ),
        .O(\trcd_cntr[0][0][1][3]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2714" *) 
  LUT4 #(
    .INIT(16'h99F9)) 
    \trcd_cntr[0][0][2][0]_i_1__2 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I2(\trcd_cntr[0][0][2][2]_i_2__2_n_0 ),
        .I3(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr[0][0][2][0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2714" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][2][1]_i_1__2 
       (.I0(\FSM_sequential_grSt_reg[0]_0 ),
        .I1(\trcd_cntr[0][0][2][2]_i_2__2_n_0 ),
        .I2(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .O(\trcd_cntr[0][0][2][1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][2][2]_i_1__2 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][2][2] ),
        .I4(\FSM_sequential_grSt_reg[0]_0 ),
        .I5(\trcd_cntr[0][0][2][2]_i_2__2_n_0 ),
        .O(\trcd_cntr[0][0][2][2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2710" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \trcd_cntr[0][0][2][2]_i_2__2 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\trcd_cntr[0][0][2][2]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0001)) 
    \trcd_cntr[0][0][2][3]_i_1__2 
       (.I0(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][2][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][2][3] ),
        .I5(\trcd_cntr_is_zero[0][0][2]_i_2__2_n_0 ),
        .O(\trcd_cntr[0][0][2][3]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2713" *) 
  LUT4 #(
    .INIT(16'hF44F)) 
    \trcd_cntr[0][0][3][0]_i_1__2 
       (.I0(\FSM_sequential_grSt_reg[0]_0 ),
        .I1(\trcd_cntr[0][0][3][2]_i_2__2_n_0 ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .O(\trcd_cntr[0][0][3][0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2713" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][3][1]_i_1__2 
       (.I0(\FSM_sequential_grSt_reg[0]_0 ),
        .I1(\trcd_cntr[0][0][3][2]_i_2__2_n_0 ),
        .I2(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .O(\trcd_cntr[0][0][3][1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][3][2]_i_1__2 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][3][2] ),
        .I4(\FSM_sequential_grSt_reg[0]_0 ),
        .I5(\trcd_cntr[0][0][3][2]_i_2__2_n_0 ),
        .O(\trcd_cntr[0][0][3][2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2708" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    \trcd_cntr[0][0][3][2]_i_2__2 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\trcd_cntr[0][0][3][2]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h5555555400000001)) 
    \trcd_cntr[0][0][3][3]_i_1__2 
       (.I0(\trcd_cntr_is_zero[0][0][3]_i_2__2_n_0 ),
        .I1(\trcd_cntr_reg_n_0_[0][0][3][2] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .I4(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I5(\trcd_cntr_reg_n_0_[0][0][3][3] ),
        .O(\trcd_cntr[0][0][3][3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010000)) 
    \trcd_cntr_is_zero[0][0][0]_i_1__2 
       (.I0(\trcd_cntr_is_zero[0][0][0]_i_2__2_n_0 ),
        .I1(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][0][3] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][0][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I5(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .O(\trcd_cntr_is_zero[0][0][0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    \trcd_cntr_is_zero[0][0][0]_i_2__2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr_is_zero[0][0][0]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010000)) 
    \trcd_cntr_is_zero[0][0][1]_i_1__2 
       (.I0(\trcd_cntr_is_zero[0][0][1]_i_2__2_n_0 ),
        .I1(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][1][3] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][1][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I5(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .O(\trcd_cntr_is_zero[0][0][1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \trcd_cntr_is_zero[0][0][1]_i_2__2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr_is_zero[0][0][1]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010000)) 
    \trcd_cntr_is_zero[0][0][2]_i_1__2 
       (.I0(\trcd_cntr_is_zero[0][0][2]_i_2__2_n_0 ),
        .I1(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][2][3] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][2][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I5(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .O(\trcd_cntr_is_zero[0][0][2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \trcd_cntr_is_zero[0][0][2]_i_2__2 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr_is_zero[0][0][2]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000014)) 
    \trcd_cntr_is_zero[0][0][3]_i_1__2 
       (.I0(\trcd_cntr_reg_n_0_[0][0][3][3] ),
        .I1(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][3][2] ),
        .I5(\trcd_cntr_is_zero[0][0][3]_i_2__2_n_0 ),
        .O(\trcd_cntr_is_zero[0][0][3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \trcd_cntr_is_zero[0][0][3]_i_2__2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(\FSM_sequential_grSt_reg[0]_0 ),
        .O(\trcd_cntr_is_zero[0][0][3]_i_2__2_n_0 ));
  FDRE \trcd_cntr_is_zero_reg[0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero[0][0][0]_i_1__2_n_0 ),
        .Q(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .R(1'b0));
  FDRE \trcd_cntr_is_zero_reg[0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero[0][0][1]_i_1__2_n_0 ),
        .Q(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .R(1'b0));
  FDRE \trcd_cntr_is_zero_reg[0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero[0][0][2]_i_1__2_n_0 ),
        .Q(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .R(1'b0));
  FDRE \trcd_cntr_is_zero_reg[0][0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero[0][0][3]_i_1__2_n_0 ),
        .Q(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .R(1'b0));
  FDRE \trcd_cntr_reg[0][0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][0][0]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][0][1]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][0][2]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][0][2] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][0][3]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][0][3] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][1][0]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][1][1]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][1][2]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][1][2] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][1][3]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][1][3] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][2][0]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][2][1]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][2][2]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][2][2] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][2][3]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][2][3] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][3][0]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][3][1]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][3][2]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][3][2] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][3][3]_i_1__2_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][3][3] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2711" *) 
  LUT5 #(
    .INIT(32'h53505555)) 
    \trp_cntr[0]_i_1__2 
       (.I0(\trp_cntr_reg_n_0_[0] ),
        .I1(\trp_cntr[0]_i_2__2_n_0 ),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .O(\trp_cntr[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h0F3355000F3355FF)) 
    \trp_cntr[0]_i_2__2 
       (.I0(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .I1(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .O(\trp_cntr[0]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hF4FFF400F400F4FF)) 
    \trp_cntr[1]_i_1__2 
       (.I0(\trp_cntr[1]_i_2__2_n_0 ),
        .I1(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .I2(\trp_cntr[1]_i_3__2_n_0 ),
        .I3(\trp_cntr[2]_i_4_n_0 ),
        .I4(\trp_cntr_reg_n_0_[1] ),
        .I5(\trp_cntr_reg_n_0_[0] ),
        .O(\trp_cntr[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2782" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \trp_cntr[1]_i_2__2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\trp_cntr[1]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFC0A0C0AFFFFFFFF)) 
    \trp_cntr[1]_i_3__2 
       (.I0(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I1(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I5(grSt[0]),
        .O(\trp_cntr[1]_i_3__2_n_0 ));
  LUT6 #(
    .INIT(64'h4F444F444F44444F)) 
    \trp_cntr[2]_i_1__2 
       (.I0(\trp_cntr[2]_i_2__2_n_0 ),
        .I1(\trp_cntr[2]_i_3__1_n_0 ),
        .I2(\trp_cntr[2]_i_4_n_0 ),
        .I3(\trp_cntr_reg_n_0_[2] ),
        .I4(\trp_cntr_reg_n_0_[0] ),
        .I5(\trp_cntr_reg_n_0_[1] ),
        .O(\trp_cntr[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h55330F0055330FFF)) 
    \trp_cntr[2]_i_2__2 
       (.I0(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .I1(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .I2(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .O(\trp_cntr[2]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2711" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \trp_cntr[2]_i_3__1 
       (.I0(grSt[1]),
        .I1(grSt[0]),
        .I2(grSt[2]),
        .O(\trp_cntr[2]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2718" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \trp_cntr[2]_i_4 
       (.I0(grSt[2]),
        .I1(grSt[1]),
        .O(\trp_cntr[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0FF00FF044440FF0)) 
    \trp_cntr[3]_i_1__2 
       (.I0(\trp_cntr[3]_i_2__2_n_0 ),
        .I1(grSt[0]),
        .I2(\trp_cntr_reg_n_0_[3] ),
        .I3(\trp_cntr[3]_i_3__2_n_0 ),
        .I4(grSt[2]),
        .I5(grSt[1]),
        .O(\trp_cntr[3]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00330F55FF330F55)) 
    \trp_cntr[3]_i_2__2 
       (.I0(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .I1(\ap_cntr_reg_n_0_[0][0][2][3] ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\ap_cntr_reg_n_0_[0][0][3][3] ),
        .O(\trp_cntr[3]_i_2__2_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \trp_cntr[3]_i_3__2 
       (.I0(\trp_cntr_reg_n_0_[0] ),
        .I1(\trp_cntr_reg_n_0_[1] ),
        .I2(\trp_cntr_reg_n_0_[2] ),
        .O(\trp_cntr[3]_i_3__2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \trp_cntr[4]_i_1__2 
       (.I0(\trp_cntr[4]_i_2__2_n_0 ),
        .O(\trp_cntr[4]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBB0B0BB00B)) 
    \trp_cntr[4]_i_2__2 
       (.I0(\trp_cntr[4]_i_3__2_n_0 ),
        .I1(\trp_cntr[2]_i_3__1_n_0 ),
        .I2(\trp_cntr_reg_n_0_[4] ),
        .I3(\trp_cntr[3]_i_3__2_n_0 ),
        .I4(\trp_cntr_reg_n_0_[3] ),
        .I5(\trp_cntr[2]_i_4_n_0 ),
        .O(\trp_cntr[4]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h33000F5533FF0F55)) 
    \trp_cntr[4]_i_3__2 
       (.I0(\ap_cntr_reg_n_0_[0][0][0][4] ),
        .I1(\ap_cntr_reg_n_0_[0][0][3][4] ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][4] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\ap_cntr_reg_n_0_[0][0][2][4] ),
        .O(\trp_cntr[4]_i_3__2_n_0 ));
  LUT5 #(
    .INIT(32'h00000100)) 
    trp_cntr_is_zero_i_1__2
       (.I0(\trp_cntr[2]_i_1__2_n_0 ),
        .I1(\trp_cntr[3]_i_1__2_n_0 ),
        .I2(\trp_cntr[0]_i_1__2_n_0 ),
        .I3(\trp_cntr[4]_i_2__2_n_0 ),
        .I4(\trp_cntr[1]_i_1__2_n_0 ),
        .O(trp_cntr_is_zero_i_1__2_n_0));
  FDRE trp_cntr_is_zero_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(trp_cntr_is_zero_i_1__2_n_0),
        .Q(trp_cntr_is_zero_reg_n_0),
        .R(1'b0));
  FDRE \trp_cntr_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trp_cntr[0]_i_1__2_n_0 ),
        .Q(\trp_cntr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \trp_cntr_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trp_cntr[1]_i_1__2_n_0 ),
        .Q(\trp_cntr_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \trp_cntr_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trp_cntr[2]_i_1__2_n_0 ),
        .Q(\trp_cntr_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \trp_cntr_reg[3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trp_cntr[3]_i_1__2_n_0 ),
        .Q(\trp_cntr_reg_n_0_[3] ),
        .R(rst_r1));
  FDRE \trp_cntr_reg[4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trp_cntr[4]_i_1__2_n_0 ),
        .Q(\trp_cntr_reg_n_0_[4] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2756" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][0]_i_1__0 
       (.I0(bank[0]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][0] ),
        .O(\txn_fifo[0][0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2754" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][11]_i_1__0 
       (.I0(col[0]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][11] ),
        .O(\txn_fifo[0][11]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2753" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][12]_i_1__0 
       (.I0(col[1]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][12] ),
        .O(\txn_fifo[0][12]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2752" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][13]_i_1__0 
       (.I0(col[2]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][13] ),
        .O(\txn_fifo[0][13]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2751" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][14]_i_1__0 
       (.I0(col[3]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][14] ),
        .O(\txn_fifo[0][14]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2750" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][15]_i_1__0 
       (.I0(col[4]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][15] ),
        .O(\txn_fifo[0][15]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2749" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][16]_i_1__0 
       (.I0(col[5]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][16] ),
        .O(\txn_fifo[0][16]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2748" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][17]_i_1__0 
       (.I0(col[6]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][17] ),
        .O(\txn_fifo[0][17]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2755" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][1]_i_1__0 
       (.I0(bank[1]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][1] ),
        .O(\txn_fifo[0][1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2758" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][24]_i_1__0 
       (.I0(row_mc_phy[0]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][24] ),
        .O(\txn_fifo[0][24]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2747" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][25]_i_1__0 
       (.I0(row_mc_phy[1]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][25] ),
        .O(\txn_fifo[0][25]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2746" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][26]_i_1__0 
       (.I0(row_mc_phy[2]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][26] ),
        .O(\txn_fifo[0][26]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2759" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][27]_i_1__0 
       (.I0(row_mc_phy[3]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][27] ),
        .O(\txn_fifo[0][27]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2745" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][28]_i_1__0 
       (.I0(row_mc_phy[4]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][28] ),
        .O(\txn_fifo[0][28]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2744" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][29]_i_1__0 
       (.I0(row_mc_phy[5]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][29] ),
        .O(\txn_fifo[0][29]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2757" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][2]_i_1__0 
       (.I0(group),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][2] ),
        .O(\txn_fifo[0][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2743" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][30]_i_1__0 
       (.I0(row_mc_phy[6]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][30] ),
        .O(\txn_fifo[0][30]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2742" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][31]_i_1__0 
       (.I0(row_mc_phy[7]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][31] ),
        .O(\txn_fifo[0][31]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2760" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][32]_i_1__0 
       (.I0(row_mc_phy[8]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][32] ),
        .O(\txn_fifo[0][32]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2761" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][33]_i_1__0 
       (.I0(row_mc_phy[9]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][33] ),
        .O(\txn_fifo[0][33]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2741" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][34]_i_1__0 
       (.I0(row_mc_phy[10]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][34] ),
        .O(\txn_fifo[0][34]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2740" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][35]_i_1__0 
       (.I0(row_mc_phy[11]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][35] ),
        .O(\txn_fifo[0][35]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2739" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][36]_i_1__0 
       (.I0(row_mc_phy[12]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][36] ),
        .O(\txn_fifo[0][36]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2738" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][37]_i_1__0 
       (.I0(row_mc_phy[13]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][37] ),
        .O(\txn_fifo[0][37]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2737" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][38]_i_1__0 
       (.I0(row_mc_phy[14]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][38] ),
        .O(\txn_fifo[0][38]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2736" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][39]_i_1__0 
       (.I0(row_mc_phy[15]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][39] ),
        .O(\txn_fifo[0][39]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2762" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][40]_i_1__0 
       (.I0(row_mc_phy[16]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][40] ),
        .O(\txn_fifo[0][40]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2763" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][44]_i_1__0 
       (.I0(cmd[0]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][44] ),
        .O(\txn_fifo[0][44]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2735" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][45]_i_1__0 
       (.I0(cmd[1]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][45] ),
        .O(\txn_fifo[0][45]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2764" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][46]_i_1__0 
       (.I0(cmd[2]),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][46] ),
        .O(\txn_fifo[0][46]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][47]_i_1__0 
       (.I0(1'b0),
        .I1(\txn_fifo[0][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][47] ),
        .O(\txn_fifo[0][47]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80001555)) 
    \txn_fifo[0][47]_i_2 
       (.I0(\txn_fifo_wptr_reg_n_0_[1] ),
        .I1(accept_reg_0),
        .I2(\txn_fifo_wptr_reg[0]_1 ),
        .I3(useAdr),
        .I4(\txn_fifo_wptr_reg_n_0_[0] ),
        .O(\txn_fifo[0][47]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][0]_i_1__0 
       (.I0(bank[0]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][0] ),
        .O(\txn_fifo[1][0]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][11]_i_1__0 
       (.I0(col[0]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][11] ),
        .O(\txn_fifo[1][11]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][12]_i_1__0 
       (.I0(col[1]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][12] ),
        .O(\txn_fifo[1][12]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][13]_i_1__0 
       (.I0(col[2]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][13] ),
        .O(\txn_fifo[1][13]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][14]_i_1__0 
       (.I0(col[3]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][14] ),
        .O(\txn_fifo[1][14]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][15]_i_1__0 
       (.I0(col[4]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][15] ),
        .O(\txn_fifo[1][15]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][16]_i_1__0 
       (.I0(col[5]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][16] ),
        .O(\txn_fifo[1][16]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][17]_i_1__0 
       (.I0(col[6]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][17] ),
        .O(\txn_fifo[1][17]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][1]_i_1__0 
       (.I0(bank[1]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][1] ),
        .O(\txn_fifo[1][1]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][24]_i_1__0 
       (.I0(row_mc_phy[0]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][24] ),
        .O(\txn_fifo[1][24]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][25]_i_1__0 
       (.I0(row_mc_phy[1]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][25] ),
        .O(\txn_fifo[1][25]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][26]_i_1__0 
       (.I0(row_mc_phy[2]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][26] ),
        .O(\txn_fifo[1][26]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][27]_i_1__0 
       (.I0(row_mc_phy[3]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][27] ),
        .O(\txn_fifo[1][27]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][28]_i_1__0 
       (.I0(row_mc_phy[4]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][28] ),
        .O(\txn_fifo[1][28]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][29]_i_1__0 
       (.I0(row_mc_phy[5]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][29] ),
        .O(\txn_fifo[1][29]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][2]_i_1__0 
       (.I0(group),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][2] ),
        .O(\txn_fifo[1][2]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][30]_i_1__0 
       (.I0(row_mc_phy[6]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][30] ),
        .O(\txn_fifo[1][30]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][31]_i_1__0 
       (.I0(row_mc_phy[7]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][31] ),
        .O(\txn_fifo[1][31]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][32]_i_1__0 
       (.I0(row_mc_phy[8]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][32] ),
        .O(\txn_fifo[1][32]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][33]_i_1__0 
       (.I0(row_mc_phy[9]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][33] ),
        .O(\txn_fifo[1][33]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][34]_i_1__0 
       (.I0(row_mc_phy[10]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][34] ),
        .O(\txn_fifo[1][34]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][35]_i_1__0 
       (.I0(row_mc_phy[11]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][35] ),
        .O(\txn_fifo[1][35]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][36]_i_1__0 
       (.I0(row_mc_phy[12]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][36] ),
        .O(\txn_fifo[1][36]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][37]_i_1__0 
       (.I0(row_mc_phy[13]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][37] ),
        .O(\txn_fifo[1][37]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][38]_i_1__0 
       (.I0(row_mc_phy[14]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][38] ),
        .O(\txn_fifo[1][38]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][39]_i_1__0 
       (.I0(row_mc_phy[15]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][39] ),
        .O(\txn_fifo[1][39]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][40]_i_1__0 
       (.I0(row_mc_phy[16]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][40] ),
        .O(\txn_fifo[1][40]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][44]_i_1__0 
       (.I0(cmd[0]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][44] ),
        .O(\txn_fifo[1][44]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][45]_i_1__0 
       (.I0(cmd[1]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][45] ),
        .O(\txn_fifo[1][45]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][46]_i_1__0 
       (.I0(cmd[2]),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][46] ),
        .O(\txn_fifo[1][46]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][47]_i_1__0 
       (.I0(1'b0),
        .I1(\txn_fifo[1][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][47] ),
        .O(\txn_fifo[1][47]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00007F80)) 
    \txn_fifo[1][47]_i_2 
       (.I0(accept_reg_0),
        .I1(\txn_fifo_wptr_reg[0]_1 ),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .O(\txn_fifo[1][47]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2756" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][0]_i_1__0 
       (.I0(bank[0]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][0] ),
        .O(\txn_fifo[2][0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2754" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][11]_i_1__0 
       (.I0(col[0]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][11] ),
        .O(\txn_fifo[2][11]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2753" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][12]_i_1__0 
       (.I0(col[1]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][12] ),
        .O(\txn_fifo[2][12]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2752" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][13]_i_1__0 
       (.I0(col[2]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][13] ),
        .O(\txn_fifo[2][13]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2751" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][14]_i_1__0 
       (.I0(col[3]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][14] ),
        .O(\txn_fifo[2][14]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2750" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][15]_i_1__0 
       (.I0(col[4]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][15] ),
        .O(\txn_fifo[2][15]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2749" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][16]_i_1__0 
       (.I0(col[5]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][16] ),
        .O(\txn_fifo[2][16]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2748" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][17]_i_1__0 
       (.I0(col[6]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][17] ),
        .O(\txn_fifo[2][17]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2755" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][1]_i_1__0 
       (.I0(bank[1]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][1] ),
        .O(\txn_fifo[2][1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2758" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][24]_i_1__0 
       (.I0(row_mc_phy[0]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][24] ),
        .O(\txn_fifo[2][24]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2747" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][25]_i_1__0 
       (.I0(row_mc_phy[1]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][25] ),
        .O(\txn_fifo[2][25]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2746" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][26]_i_1__0 
       (.I0(row_mc_phy[2]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][26] ),
        .O(\txn_fifo[2][26]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2759" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][27]_i_1__0 
       (.I0(row_mc_phy[3]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][27] ),
        .O(\txn_fifo[2][27]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2745" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][28]_i_1__0 
       (.I0(row_mc_phy[4]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][28] ),
        .O(\txn_fifo[2][28]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2744" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][29]_i_1__0 
       (.I0(row_mc_phy[5]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][29] ),
        .O(\txn_fifo[2][29]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2757" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][2]_i_1__0 
       (.I0(group),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][2] ),
        .O(\txn_fifo[2][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2743" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][30]_i_1__0 
       (.I0(row_mc_phy[6]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][30] ),
        .O(\txn_fifo[2][30]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2742" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][31]_i_1__0 
       (.I0(row_mc_phy[7]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][31] ),
        .O(\txn_fifo[2][31]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2760" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][32]_i_1__0 
       (.I0(row_mc_phy[8]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][32] ),
        .O(\txn_fifo[2][32]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2761" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][33]_i_1__0 
       (.I0(row_mc_phy[9]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][33] ),
        .O(\txn_fifo[2][33]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2741" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][34]_i_1__0 
       (.I0(row_mc_phy[10]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][34] ),
        .O(\txn_fifo[2][34]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2740" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][35]_i_1__0 
       (.I0(row_mc_phy[11]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][35] ),
        .O(\txn_fifo[2][35]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2739" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][36]_i_1__0 
       (.I0(row_mc_phy[12]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][36] ),
        .O(\txn_fifo[2][36]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2738" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][37]_i_1__0 
       (.I0(row_mc_phy[13]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][37] ),
        .O(\txn_fifo[2][37]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2737" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][38]_i_1__0 
       (.I0(row_mc_phy[14]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][38] ),
        .O(\txn_fifo[2][38]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2736" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][39]_i_1__0 
       (.I0(row_mc_phy[15]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][39] ),
        .O(\txn_fifo[2][39]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2762" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][40]_i_1__0 
       (.I0(row_mc_phy[16]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][40] ),
        .O(\txn_fifo[2][40]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2763" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][44]_i_1__0 
       (.I0(cmd[0]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][44] ),
        .O(\txn_fifo[2][44]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2735" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][45]_i_1__0 
       (.I0(cmd[1]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][45] ),
        .O(\txn_fifo[2][45]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2764" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][46]_i_1__0 
       (.I0(cmd[2]),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][46] ),
        .O(\txn_fifo[2][46]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][47]_i_1__0 
       (.I0(1'b0),
        .I1(\txn_fifo[2][47]_i_2__0_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][47] ),
        .O(\txn_fifo[2][47]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h15558000)) 
    \txn_fifo[2][47]_i_2__0 
       (.I0(\txn_fifo_wptr_reg_n_0_[0] ),
        .I1(useAdr),
        .I2(\txn_fifo_wptr_reg[0]_1 ),
        .I3(accept_reg_0),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .O(\txn_fifo[2][47]_i_2__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][0]_i_1__0 
       (.I0(bank[0]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][0] ),
        .O(\txn_fifo[3][0]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][11]_i_1__0 
       (.I0(col[0]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][11] ),
        .O(\txn_fifo[3][11]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][12]_i_1__0 
       (.I0(col[1]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][12] ),
        .O(\txn_fifo[3][12]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][13]_i_1__0 
       (.I0(col[2]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][13] ),
        .O(\txn_fifo[3][13]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][14]_i_1__0 
       (.I0(col[3]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][14] ),
        .O(\txn_fifo[3][14]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][15]_i_1__0 
       (.I0(col[4]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][15] ),
        .O(\txn_fifo[3][15]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][16]_i_1__0 
       (.I0(col[5]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][16] ),
        .O(\txn_fifo[3][16]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][17]_i_1__0 
       (.I0(col[6]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][17] ),
        .O(\txn_fifo[3][17]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][1]_i_1__0 
       (.I0(bank[1]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][1] ),
        .O(\txn_fifo[3][1]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][24]_i_1__0 
       (.I0(row_mc_phy[0]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][24] ),
        .O(\txn_fifo[3][24]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][25]_i_1__0 
       (.I0(row_mc_phy[1]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][25] ),
        .O(\txn_fifo[3][25]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][26]_i_1__0 
       (.I0(row_mc_phy[2]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][26] ),
        .O(\txn_fifo[3][26]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][27]_i_1__0 
       (.I0(row_mc_phy[3]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][27] ),
        .O(\txn_fifo[3][27]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][28]_i_1__0 
       (.I0(row_mc_phy[4]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][28] ),
        .O(\txn_fifo[3][28]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][29]_i_1__0 
       (.I0(row_mc_phy[5]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][29] ),
        .O(\txn_fifo[3][29]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][2]_i_1__0 
       (.I0(group),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][2] ),
        .O(\txn_fifo[3][2]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][30]_i_1__0 
       (.I0(row_mc_phy[6]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][30] ),
        .O(\txn_fifo[3][30]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][31]_i_1__0 
       (.I0(row_mc_phy[7]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][31] ),
        .O(\txn_fifo[3][31]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][32]_i_1__0 
       (.I0(row_mc_phy[8]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][32] ),
        .O(\txn_fifo[3][32]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][33]_i_1__0 
       (.I0(row_mc_phy[9]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][33] ),
        .O(\txn_fifo[3][33]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][34]_i_1__0 
       (.I0(row_mc_phy[10]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][34] ),
        .O(\txn_fifo[3][34]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][35]_i_1__0 
       (.I0(row_mc_phy[11]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][35] ),
        .O(\txn_fifo[3][35]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][36]_i_1__0 
       (.I0(row_mc_phy[12]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][36] ),
        .O(\txn_fifo[3][36]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][37]_i_1__0 
       (.I0(row_mc_phy[13]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][37] ),
        .O(\txn_fifo[3][37]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][38]_i_1__0 
       (.I0(row_mc_phy[14]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][38] ),
        .O(\txn_fifo[3][38]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][39]_i_1__0 
       (.I0(row_mc_phy[15]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][39] ),
        .O(\txn_fifo[3][39]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][40]_i_1__0 
       (.I0(row_mc_phy[16]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][40] ),
        .O(\txn_fifo[3][40]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][44]_i_1__0 
       (.I0(cmd[0]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][44] ),
        .O(\txn_fifo[3][44]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][45]_i_1__0 
       (.I0(cmd[1]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][45] ),
        .O(\txn_fifo[3][45]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][46]_i_1__0 
       (.I0(cmd[2]),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][46] ),
        .O(\txn_fifo[3][46]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][47]_i_1__0 
       (.I0(1'b0),
        .I1(\txn_fifo[3][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][47] ),
        .O(\txn_fifo[3][47]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h7F800000)) 
    \txn_fifo[3][47]_i_2 
       (.I0(accept_reg_0),
        .I1(\txn_fifo_wptr_reg[0]_1 ),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .O(\txn_fifo[3][47]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9006099009906009)) 
    txn_fifo_empty_i_1__0
       (.I0(\txn_fifo_wptr_reg_n_0_[1] ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(txn_fifo_empty_i_2_n_0),
        .I4(\txn_fifo_rptr_reg_n_0_[0] ),
        .I5(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ),
        .O(txn_fifo_empty_i_1__0_n_0));
  LUT3 #(
    .INIT(8'h80)) 
    txn_fifo_empty_i_2
       (.I0(accept_reg_0),
        .I1(\txn_fifo_wptr_reg[0]_1 ),
        .I2(useAdr),
        .O(txn_fifo_empty_i_2_n_0));
  FDRE txn_fifo_empty_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(txn_fifo_empty_i_1__0_n_0),
        .Q(txn_fifo_empty_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[0]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][0]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[0]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[0]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][0]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[0]_i_2__0 
       (.I0(\txn_fifo[3][0]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[0]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[0]_i_3__0 
       (.I0(\txn_fifo[1][0]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[0]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[11]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][11]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[11]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[11]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][11]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[11]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[11]_i_2__0 
       (.I0(\txn_fifo[1][11]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[11]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[11]_i_3__0 
       (.I0(\txn_fifo[3][11]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[11]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[12]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][12]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[12]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[12]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][12]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[12]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[12]_i_2__0 
       (.I0(\txn_fifo[3][12]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[12]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[12]_i_3__0 
       (.I0(\txn_fifo[1][12]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[12]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[13]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][13]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[13]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[13]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][13]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[13]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[13]_i_2__0 
       (.I0(\txn_fifo[3][13]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[13]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[13]_i_3__0 
       (.I0(\txn_fifo[1][13]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[13]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[14]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][14]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[14]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[14]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][14]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[14]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[14]_i_2__0 
       (.I0(\txn_fifo[3][14]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[14]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[14]_i_3__0 
       (.I0(\txn_fifo[1][14]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[14]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[15]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][15]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[15]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[15]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][15]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[15]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[15]_i_2__0 
       (.I0(\txn_fifo[1][15]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[15]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[15]_i_3__0 
       (.I0(\txn_fifo[3][15]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[15]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[16]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][16]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[16]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[16]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][16]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[16]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[16]_i_2__0 
       (.I0(\txn_fifo[3][16]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[16]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[16]_i_3__0 
       (.I0(\txn_fifo[1][16]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[16]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[17]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][17]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[17]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[17]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][17]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[17]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[17]_i_2__0 
       (.I0(\txn_fifo[3][17]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[17]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[17]_i_3__0 
       (.I0(\txn_fifo[1][17]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[17]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[1]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][1]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[1]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[1]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][1]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[1]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[1]_i_2__0 
       (.I0(\txn_fifo[1][1]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[1]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[1]_i_3__0 
       (.I0(\txn_fifo[3][1]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[1]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[24]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_2__0_n_0 ),
        .I1(\txn_fifo[0][24]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[24]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[24]_i_3__0_n_0 ),
        .I4(\txn_fifo[2][24]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_5_n_0 ),
        .O(\txn_fifo_output[24]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[24]_i_2__0 
       (.I0(\txn_fifo[3][24]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[24]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[24]_i_3__0 
       (.I0(\txn_fifo[1][24]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[24]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[25]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][25]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[25]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[25]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][25]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[25]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[25]_i_2__0 
       (.I0(\txn_fifo[1][25]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[25]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[25]_i_3__0 
       (.I0(\txn_fifo[3][25]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[25]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[26]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][26]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[26]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[26]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][26]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[26]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[26]_i_2__0 
       (.I0(\txn_fifo[3][26]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[26]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[26]_i_3__0 
       (.I0(\txn_fifo[1][26]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[26]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[27]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_2__0_n_0 ),
        .I1(\txn_fifo[0][27]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[27]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[27]_i_3__0_n_0 ),
        .I4(\txn_fifo[2][27]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_5_n_0 ),
        .O(\txn_fifo_output[27]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[27]_i_2__0 
       (.I0(\txn_fifo[3][27]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[27]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[27]_i_3__0 
       (.I0(\txn_fifo[1][27]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[27]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[28]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][28]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[28]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[28]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][28]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[28]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[28]_i_2__0 
       (.I0(\txn_fifo[3][28]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[28]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[28]_i_3__0 
       (.I0(\txn_fifo[1][28]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[28]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[29]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][29]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[29]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[29]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][29]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[29]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[29]_i_2__0 
       (.I0(\txn_fifo[1][29]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[29]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[29]_i_3__0 
       (.I0(\txn_fifo[3][29]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[29]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[2]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_2__0_n_0 ),
        .I1(\txn_fifo[0][2]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[2]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[2]_i_3__0_n_0 ),
        .I4(\txn_fifo[2][2]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_5_n_0 ),
        .O(\txn_fifo_output[2]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[2]_i_2__0 
       (.I0(\txn_fifo[3][2]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[2]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[2]_i_3__0 
       (.I0(\txn_fifo[1][2]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[2]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[30]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][30]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[30]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[30]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][30]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[30]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[30]_i_2__0 
       (.I0(\txn_fifo[3][30]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[30]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[30]_i_3__0 
       (.I0(\txn_fifo[1][30]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[30]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[31]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][31]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[31]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[31]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][31]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[31]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[31]_i_2__0 
       (.I0(\txn_fifo[3][31]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[31]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[31]_i_3__0 
       (.I0(\txn_fifo[1][31]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[31]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[32]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_2__0_n_0 ),
        .I1(\txn_fifo[0][32]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[32]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[32]_i_3__0_n_0 ),
        .I4(\txn_fifo[2][32]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_5_n_0 ),
        .O(\txn_fifo_output[32]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[32]_i_2__0 
       (.I0(\txn_fifo[3][32]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[32]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[32]_i_3__0 
       (.I0(\txn_fifo[1][32]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[32]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[33]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_2__0_n_0 ),
        .I1(\txn_fifo[0][33]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[33]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[33]_i_3__0_n_0 ),
        .I4(\txn_fifo[2][33]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_5_n_0 ),
        .O(\txn_fifo_output[33]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[33]_i_2__0 
       (.I0(\txn_fifo[1][33]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[33]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[33]_i_3__0 
       (.I0(\txn_fifo[3][33]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[33]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[34]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][34]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[34]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[34]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][34]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[34]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[34]_i_2__0 
       (.I0(\txn_fifo[3][34]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[34]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[34]_i_3__0 
       (.I0(\txn_fifo[1][34]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[34]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[35]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][35]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[35]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[35]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][35]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[35]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[35]_i_2__0 
       (.I0(\txn_fifo[3][35]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[35]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[35]_i_3__0 
       (.I0(\txn_fifo[1][35]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[35]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[36]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][36]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[36]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[36]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][36]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[36]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[36]_i_2__0 
       (.I0(\txn_fifo[3][36]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[36]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[36]_i_3__0 
       (.I0(\txn_fifo[1][36]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[36]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[37]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][37]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[37]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[37]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][37]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[37]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[37]_i_2__0 
       (.I0(\txn_fifo[1][37]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[37]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[37]_i_3__0 
       (.I0(\txn_fifo[3][37]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[37]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[38]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][38]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[38]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[38]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][38]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[38]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[38]_i_2__0 
       (.I0(\txn_fifo[3][38]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[38]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[38]_i_3__0 
       (.I0(\txn_fifo[1][38]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[38]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[39]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][39]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[39]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[39]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][39]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[39]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[39]_i_2__0 
       (.I0(\txn_fifo[3][39]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[39]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[39]_i_3__0 
       (.I0(\txn_fifo[1][39]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[39]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[40]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_2__0_n_0 ),
        .I1(\txn_fifo[0][40]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[40]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[40]_i_3__0_n_0 ),
        .I4(\txn_fifo[2][40]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_5_n_0 ),
        .O(\txn_fifo_output[40]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[40]_i_2__0 
       (.I0(\txn_fifo[3][40]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[40]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[40]_i_3__0 
       (.I0(\txn_fifo[1][40]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[40]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[44]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_2__0_n_0 ),
        .I1(\txn_fifo[0][44]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[44]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[44]_i_3__0_n_0 ),
        .I4(\txn_fifo[2][44]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_5_n_0 ),
        .O(\txn_fifo_output[44]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[44]_i_2__0 
       (.I0(\txn_fifo[1][44]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[44]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[44]_i_3__0 
       (.I0(\txn_fifo[3][44]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[44]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[45]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_5_n_0 ),
        .I1(\txn_fifo[2][45]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[45]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[45]_i_3__0_n_0 ),
        .I4(\txn_fifo[0][45]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_2__0_n_0 ),
        .O(\txn_fifo_output[45]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[45]_i_2__0 
       (.I0(\txn_fifo[3][45]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[45]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[45]_i_3__0 
       (.I0(\txn_fifo[1][45]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[45]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[46]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_2__0_n_0 ),
        .I1(\txn_fifo[0][46]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[46]_i_2__0_n_0 ),
        .I3(\txn_fifo_output[46]_i_3__0_n_0 ),
        .I4(\txn_fifo[2][46]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_5_n_0 ),
        .O(\txn_fifo_output[46]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[46]_i_2__0 
       (.I0(\txn_fifo[3][46]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[46]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[46]_i_3__0 
       (.I0(\txn_fifo[1][46]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[46]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \txn_fifo_output[47]_i_1__0 
       (.I0(\txn_fifo_output[47]_i_2__0_n_0 ),
        .I1(\txn_fifo[0][47]_i_1__0_n_0 ),
        .I2(\txn_fifo_output[47]_i_3__0_n_0 ),
        .I3(\txn_fifo_output[47]_i_4_n_0 ),
        .I4(\txn_fifo[2][47]_i_1__0_n_0 ),
        .I5(\txn_fifo_output[47]_i_5_n_0 ),
        .O(\txn_fifo_output[47]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hF7AE)) 
    \txn_fifo_output[47]_i_2__0 
       (.I0(\txn_fifo_rptr_reg_n_0_[1] ),
        .I1(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .O(\txn_fifo_output[47]_i_2__0_n_0 ));
  LUT5 #(
    .INIT(32'h00008288)) 
    \txn_fifo_output[47]_i_3__0 
       (.I0(\txn_fifo[1][47]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .O(\txn_fifo_output[47]_i_3__0_n_0 ));
  LUT5 #(
    .INIT(32'h80088080)) 
    \txn_fifo_output[47]_i_4 
       (.I0(\txn_fifo[3][47]_i_1__0_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[1] ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .O(\txn_fifo_output[47]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hFB5D)) 
    \txn_fifo_output[47]_i_5 
       (.I0(\txn_fifo_rptr_reg_n_0_[1] ),
        .I1(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I2(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .O(\txn_fifo_output[47]_i_5_n_0 ));
  FDRE \txn_fifo_output_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[0]_i_1__0_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[11]_i_1__0_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[12]_i_1__0_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[13]_i_1__0_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[14]_i_1__0_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[15]_i_1__0_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[16]_i_1__0_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[17]_i_1__0_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[1]_i_1__0_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[24]_i_1__0_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[25]_i_1__0_n_0 ),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[26]_i_1__0_n_0 ),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[27]_i_1__0_n_0 ),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[28]_i_1__0_n_0 ),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[29]_i_1__0_n_0 ),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[2]_i_1__0_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[30]_i_1__0_n_0 ),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[31]_i_1__0_n_0 ),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[32]_i_1__0_n_0 ),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[33]_i_1__0_n_0 ),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[34]_i_1__0_n_0 ),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[35]_i_1__0_n_0 ),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[36]_i_1__0_n_0 ),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[37]_i_1__0_n_0 ),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[38]_i_1__0_n_0 ),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[39]_i_1__0_n_0 ),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[40]_i_1__0_n_0 ),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[44]_i_1__0_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[44] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[45]_i_1__0_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[45] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[46]_i_1__0_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[46] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[47]_i_1__0_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[47] ),
        .R(1'b0));
  FDRE \txn_fifo_reg[0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][0]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][0] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][11]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][11] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][12]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][12] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][13]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][13] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][14]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][14] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][15]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][15] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][16]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][16] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][17]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][17] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][1]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][1] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][24]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][24] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][25]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][25] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][26]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][26] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][27]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][27] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][28]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][28] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][29]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][29] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][2]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][2] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][30]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][30] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][31]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][31] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][32]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][32] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][33]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][33] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][34]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][34] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][35]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][35] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][36]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][36] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][37]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][37] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][38]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][38] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][39]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][39] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][40]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][40] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][44]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][44] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][45]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][45] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][46]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][46] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][47]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][47] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][0]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][0] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][11]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][11] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][12]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][12] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][13]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][13] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][14]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][14] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][15]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][15] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][16]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][16] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][17]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][17] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][1]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][1] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][24]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][24] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][25]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][25] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][26]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][26] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][27]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][27] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][28]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][28] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][29]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][29] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][2]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][2] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][30]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][30] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][31]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][31] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][32]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][32] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][33]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][33] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][34]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][34] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][35]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][35] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][36]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][36] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][37]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][37] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][38]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][38] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][39]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][39] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][40]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][40] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][44]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][44] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][45]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][45] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][46]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][46] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][47]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][47] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][0]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][0] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][11]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][11] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][12]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][12] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][13]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][13] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][14]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][14] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][15]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][15] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][16]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][16] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][17]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][17] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][1]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][1] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][24]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][24] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][25]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][25] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][26]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][26] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][27]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][27] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][28]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][28] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][29]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][29] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][2]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][2] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][30]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][30] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][31]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][31] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][32]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][32] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][33]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][33] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][34]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][34] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][35]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][35] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][36]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][36] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][37]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][37] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][38]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][38] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][39]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][39] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][40]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][40] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][44]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][44] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][45]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][45] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][46]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][46] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][47]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][47] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][0]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][0] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][11]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][11] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][12]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][12] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][13]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][13] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][14]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][14] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][15]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][15] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][16]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][16] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][17]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][17] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][1]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][1] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][24]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][24] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][25]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][25] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][26]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][26] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][27]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][27] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][28]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][28] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][29]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][29] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][2]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][2] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][30]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][30] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][31]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][31] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][32]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][32] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][33]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][33] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][34]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][34] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][35]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][35] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][36]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][36] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][37]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][37] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][38]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][38] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][39]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][39] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][40]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][40] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][44]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][44] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][45]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][45] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][46]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][46] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][47]_i_1__0_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][47] ),
        .R(rst_r1));
  LUT2 #(
    .INIT(4'h6)) 
    \txn_fifo_rptr[0]_i_1__0 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_7_n_0 ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .O(\txn_fifo_rptr[0]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hAA6A)) 
    \txn_fifo_rptr[1]_i_1__0 
       (.I0(\txn_fifo_rptr_reg_n_0_[1] ),
        .I1(\txn_fifo_rptr_reg_n_0_[0] ),
        .I2(\FSM_sequential_grSt[1]_i_2_n_0 ),
        .I3(\txn_fifo_rptr[1]_i_2__1_n_0 ),
        .O(\txn_fifo_rptr[1]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFFBFBBAA)) 
    \txn_fifo_rptr[1]_i_2__1 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(\FSM_sequential_grSt_reg[0]_0 ),
        .I3(cas_fifo_full_reg_n_0),
        .I4(grSt[1]),
        .O(\txn_fifo_rptr[1]_i_2__1_n_0 ));
  FDRE \txn_fifo_rptr_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_rptr[0]_i_1__0_n_0 ),
        .Q(\txn_fifo_rptr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \txn_fifo_rptr_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_rptr[1]_i_1__0_n_0 ),
        .Q(\txn_fifo_rptr_reg_n_0_[1] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2717" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \txn_fifo_wptr[0]_i_1 
       (.I0(\txn_fifo_wptr_reg_n_0_[0] ),
        .I1(useAdr),
        .I2(\txn_fifo_wptr_reg[0]_1 ),
        .I3(accept_reg_0),
        .O(\txn_fifo_wptr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2717" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \txn_fifo_wptr[1]_i_1 
       (.I0(\txn_fifo_wptr_reg_n_0_[0] ),
        .I1(useAdr),
        .I2(\txn_fifo_wptr_reg[0]_1 ),
        .I3(accept_reg_0),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .O(\txn_fifo_wptr[1]_i_1_n_0 ));
  FDRE \txn_fifo_wptr_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_wptr[0]_i_1_n_0 ),
        .Q(\txn_fifo_wptr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \txn_fifo_wptr_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_wptr[1]_i_1_n_0 ),
        .Q(\txn_fifo_wptr_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE underfill_done_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(underfill_done_reg_0),
        .Q(underfill_done_reg_n_0),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'h4444444444444454)) 
    wrReqR_i_1__2
       (.I0(clrReq1),
        .I1(wrReqR_i_2__2_n_0),
        .I2(\FSM_sequential_gr_cas_state[2]_i_3__0_n_0 ),
        .I3(wrReqR_i_3__1_n_0),
        .I4(wrReqR_i_4__1_n_0),
        .I5(wrReqR_i_5__1_n_0),
        .O(wrReqR_i_1__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2716" *) 
  LUT5 #(
    .INIT(32'hAAAAAAEA)) 
    wrReqR_i_2__2
       (.I0(wrReqR_reg_0),
        .I1(gr_cas_state[1]),
        .I2(underfill_done_reg_n_0),
        .I3(gr_cas_state[0]),
        .I4(gr_cas_state[2]),
        .O(wrReqR_i_2__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2765" *) 
  LUT3 #(
    .INIT(8'hC5)) 
    wrReqR_i_3__1
       (.I0(wrReqR_i_6__1_n_0),
        .I1(\txn_fifo_output_reg_n_0_[44] ),
        .I2(cas_fifo_empty_reg_n_0),
        .O(wrReqR_i_3__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2765" *) 
  LUT3 #(
    .INIT(8'hC5)) 
    wrReqR_i_4__1
       (.I0(wrReqR_i_7__1_n_0),
        .I1(\txn_fifo_output_reg_n_0_[45] ),
        .I2(cas_fifo_empty_reg_n_0),
        .O(wrReqR_i_4__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2705" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    wrReqR_i_5__1
       (.I0(\txn_fifo_output_reg_n_0_[46] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(wrReqR_i_8__0_n_0),
        .O(wrReqR_i_5__1_n_0));
  LUT6 #(
    .INIT(64'h3300550F33FF550F)) 
    wrReqR_i_6__1
       (.I0(\cas_pend_fifo_reg_n_0_[2][44] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][44] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][44] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][44] ),
        .O(wrReqR_i_6__1_n_0));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    wrReqR_i_7__1
       (.I0(\cas_pend_fifo_reg_n_0_[1][45] ),
        .I1(\cas_pend_fifo_reg_n_0_[0][45] ),
        .I2(\cas_pend_fifo_reg_n_0_[2][45] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[3][45] ),
        .O(wrReqR_i_7__1_n_0));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    wrReqR_i_8__0
       (.I0(\cas_pend_fifo_reg_n_0_[2][46] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][46] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][46] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][46] ),
        .O(wrReqR_i_8__0_n_0));
  FDRE wrReqR_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(wrReqR_i_1__2_n_0),
        .Q(wrReqR_reg_0),
        .R(rst_r1));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_group" *) 
module ddr4_0_ddr4_v2_2_17_mc_group_9
   (cmdAP,
    refOK,
    accept_reg_0,
    grAccept_ns,
    wrReqR_reg_0,
    actReqR_reg_0,
    preReqR_reg_0,
    rdReqR_reg_0,
    cmdRmw_reg_0,
    cmd_group_cas,
    cmdGroupP,
    Q,
    \cmd_bank_cas_reg[1]_0 ,
    \buf_fifo_reg[2][0]_0 ,
    \buf_fifo_reg[2][1]_0 ,
    \buf_fifo_reg[2][2]_0 ,
    \buf_fifo_reg[2][3]_0 ,
    \buf_fifo_reg[0][4]_0 ,
    refOK_reg_0,
    cmdBuf,
    \cmdBankP_reg[1]_0 ,
    \cmdCol_reg[9]_0 ,
    \cmdGroupP_reg[0]_0 ,
    underfill_done_reg_0,
    SR,
    clrReq15_out,
    \cas_fifo_rptr_reg[0]_0 ,
    tranSentC,
    \txn_fifo_wptr_reg[0]_0 ,
    useAdr,
    \buf_fifo_reg[1][0]_0 ,
    \buf_fifo_reg[1][1]_0 ,
    \buf_fifo_reg[1][2]_0 ,
    \buf_fifo_reg[1][3]_0 ,
    \buf_fifo_reg[1][4]_0 ,
    cmd,
    row_mc_phy,
    col,
    group,
    bank,
    ref_req_dly4,
    preReqR_reg_1,
    actReqR_reg_1,
    accept_reg_1,
    refReq,
    \um_wait_cntr[2]_i_3 );
  output [0:0]cmdAP;
  output [0:0]refOK;
  output accept_reg_0;
  output [0:0]grAccept_ns;
  output wrReqR_reg_0;
  output actReqR_reg_0;
  output preReqR_reg_0;
  output rdReqR_reg_0;
  output cmdRmw_reg_0;
  output [0:0]cmd_group_cas;
  output [0:0]cmdGroupP;
  output [19:0]Q;
  output [1:0]\cmd_bank_cas_reg[1]_0 ;
  output \buf_fifo_reg[2][0]_0 ;
  output \buf_fifo_reg[2][1]_0 ;
  output \buf_fifo_reg[2][2]_0 ;
  output \buf_fifo_reg[2][3]_0 ;
  output \buf_fifo_reg[0][4]_0 ;
  output refOK_reg_0;
  output [4:0]cmdBuf;
  output [1:0]\cmdBankP_reg[1]_0 ;
  output [6:0]\cmdCol_reg[9]_0 ;
  input \cmdGroupP_reg[0]_0 ;
  input underfill_done_reg_0;
  input [0:0]SR;
  input clrReq15_out;
  input [0:0]\cas_fifo_rptr_reg[0]_0 ;
  input tranSentC;
  input \txn_fifo_wptr_reg[0]_0 ;
  input useAdr;
  input \buf_fifo_reg[1][0]_0 ;
  input \buf_fifo_reg[1][1]_0 ;
  input \buf_fifo_reg[1][2]_0 ;
  input \buf_fifo_reg[1][3]_0 ;
  input \buf_fifo_reg[1][4]_0 ;
  input [2:0]cmd;
  input [16:0]row_mc_phy;
  input [6:0]col;
  input [0:0]group;
  input [1:0]bank;
  input ref_req_dly4;
  input [0:0]preReqR_reg_1;
  input [0:0]actReqR_reg_1;
  input accept_reg_1;
  input refReq;
  input [2:0]\um_wait_cntr[2]_i_3 ;

  wire \FSM_sequential_grSt[0]_i_1__2_n_0 ;
  wire \FSM_sequential_grSt[0]_i_2__2_n_0 ;
  wire \FSM_sequential_grSt[0]_i_3_n_0 ;
  wire \FSM_sequential_grSt[1]_i_1__2_n_0 ;
  wire \FSM_sequential_grSt[1]_i_2__1_n_0 ;
  wire \FSM_sequential_grSt[1]_i_3__2_n_0 ;
  wire \FSM_sequential_grSt[1]_i_4_n_0 ;
  wire \FSM_sequential_grSt[1]_i_5__0_n_0 ;
  wire \FSM_sequential_grSt[1]_i_6__0_n_0 ;
  wire \FSM_sequential_grSt[2]_i_10__0_n_0 ;
  wire \FSM_sequential_grSt[2]_i_11__0_n_0 ;
  wire \FSM_sequential_grSt[2]_i_1__2_n_0 ;
  wire \FSM_sequential_grSt[2]_i_2__1_n_0 ;
  wire \FSM_sequential_grSt[2]_i_3__2_n_0 ;
  wire \FSM_sequential_grSt[2]_i_4_n_0 ;
  wire \FSM_sequential_grSt[2]_i_5__0_n_0 ;
  wire \FSM_sequential_grSt[2]_i_6__1_n_0 ;
  wire \FSM_sequential_grSt[2]_i_7__2_n_0 ;
  wire \FSM_sequential_grSt[2]_i_8_n_0 ;
  wire \FSM_sequential_grSt[2]_i_9__0_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_10_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_1__0_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_3__2_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_5__2_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_6__0_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_7__2_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_8__1_n_0 ;
  wire \FSM_sequential_gr_cas_state[2]_i_9__0_n_0 ;
  wire [19:0]Q;
  wire [0:0]SR;
  wire accept_reg_0;
  wire accept_reg_1;
  wire actReqR_i_1__2_n_0;
  wire actReqR_i_2__1_n_0;
  wire actReqR_i_3__1_n_0;
  wire actReqR_reg_0;
  wire [0:0]actReqR_reg_1;
  wire \ap_cntr[0][0][0][0]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][0][1]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][0][2]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][0][3]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][0][4]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][0][4]_i_2__0_n_0 ;
  wire \ap_cntr[0][0][0][4]_i_3__0_n_0 ;
  wire \ap_cntr[0][0][1][0]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][1][1]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][1][2]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][1][3]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][1][4]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][1][4]_i_2__0_n_0 ;
  wire \ap_cntr[0][0][1][4]_i_3__0_n_0 ;
  wire \ap_cntr[0][0][2][0]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][2][1]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][2][2]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][2][3]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][2][4]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][2][4]_i_2__0_n_0 ;
  wire \ap_cntr[0][0][2][4]_i_3_n_0 ;
  wire \ap_cntr[0][0][3][0]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][3][1]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][3][2]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][3][3]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][3][4]_i_1__0_n_0 ;
  wire \ap_cntr[0][0][3][4]_i_2__0_n_0 ;
  wire \ap_cntr[0][0][3][4]_i_3__0_n_0 ;
  wire \ap_cntr_expired[0][0][0]_i_1__1_n_0 ;
  wire \ap_cntr_expired[0][0][1]_i_1__1_n_0 ;
  wire \ap_cntr_expired[0][0][2]_i_1__0_n_0 ;
  wire \ap_cntr_expired[0][0][3]_i_1__0_n_0 ;
  wire \ap_cntr_reg_n_0_[0][0][0][0] ;
  wire \ap_cntr_reg_n_0_[0][0][0][1] ;
  wire \ap_cntr_reg_n_0_[0][0][0][2] ;
  wire \ap_cntr_reg_n_0_[0][0][0][3] ;
  wire \ap_cntr_reg_n_0_[0][0][0][4] ;
  wire \ap_cntr_reg_n_0_[0][0][1][0] ;
  wire \ap_cntr_reg_n_0_[0][0][1][1] ;
  wire \ap_cntr_reg_n_0_[0][0][1][2] ;
  wire \ap_cntr_reg_n_0_[0][0][1][3] ;
  wire \ap_cntr_reg_n_0_[0][0][1][4] ;
  wire \ap_cntr_reg_n_0_[0][0][2][0] ;
  wire \ap_cntr_reg_n_0_[0][0][2][1] ;
  wire \ap_cntr_reg_n_0_[0][0][2][2] ;
  wire \ap_cntr_reg_n_0_[0][0][2][3] ;
  wire \ap_cntr_reg_n_0_[0][0][2][4] ;
  wire \ap_cntr_reg_n_0_[0][0][3][0] ;
  wire \ap_cntr_reg_n_0_[0][0][3][1] ;
  wire \ap_cntr_reg_n_0_[0][0][3][2] ;
  wire \ap_cntr_reg_n_0_[0][0][3][3] ;
  wire \ap_cntr_reg_n_0_[0][0][3][4] ;
  wire \ap_cntr_zero[0][0][0]_i_1__0_n_0 ;
  wire \ap_cntr_zero[0][0][1]_i_1__0_n_0 ;
  wire \ap_cntr_zero[0][0][2]_i_1__0_n_0 ;
  wire \ap_cntr_zero[0][0][3]_i_1__0_n_0 ;
  wire \ap_cntr_zero_reg_n_0_[0][0][0] ;
  wire \ap_cntr_zero_reg_n_0_[0][0][1] ;
  wire \ap_cntr_zero_reg_n_0_[0][0][2] ;
  wire \ap_cntr_zero_reg_n_0_[0][0][3] ;
  wire \ap_load_value[0]_i_1__0_n_0 ;
  wire \ap_load_value[0]_i_2__0_n_0 ;
  wire \ap_load_value[1]_i_1__0_n_0 ;
  wire \ap_load_value[2]_i_1__0_n_0 ;
  wire \ap_load_value[3]_i_1__0_n_0 ;
  wire \ap_load_value[3]_i_2__0_n_0 ;
  wire \ap_load_value[3]_i_3__0_n_0 ;
  wire \ap_load_value_reg_n_0_[0] ;
  wire \ap_load_value_reg_n_0_[1] ;
  wire \ap_load_value_reg_n_0_[2] ;
  wire \ap_load_value_reg_n_0_[3] ;
  wire [1:0]bank;
  wire \buf_fifo[0][0]_i_1__1_n_0 ;
  wire \buf_fifo[0][1]_i_1__1_n_0 ;
  wire \buf_fifo[0][2]_i_1__1_n_0 ;
  wire \buf_fifo[0][3]_i_1__1_n_0 ;
  wire \buf_fifo[0][4]_i_1__1_n_0 ;
  wire \buf_fifo[1][0]_i_1__1_n_0 ;
  wire \buf_fifo[1][1]_i_1__1_n_0 ;
  wire \buf_fifo[1][2]_i_1__1_n_0 ;
  wire \buf_fifo[1][3]_i_1__1_n_0 ;
  wire \buf_fifo[1][4]_i_1__1_n_0 ;
  wire \buf_fifo[2][0]_i_1__1_n_0 ;
  wire \buf_fifo[2][1]_i_1__1_n_0 ;
  wire \buf_fifo[2][2]_i_1__1_n_0 ;
  wire \buf_fifo[2][3]_i_1__1_n_0 ;
  wire \buf_fifo[2][4]_i_1__1_n_0 ;
  wire \buf_fifo[3][0]_i_1__1_n_0 ;
  wire \buf_fifo[3][1]_i_1__1_n_0 ;
  wire \buf_fifo[3][2]_i_1__1_n_0 ;
  wire \buf_fifo[3][3]_i_1__1_n_0 ;
  wire \buf_fifo[3][4]_i_1__1_n_0 ;
  wire \buf_fifo_reg[0][4]_0 ;
  wire \buf_fifo_reg[1][0]_0 ;
  wire \buf_fifo_reg[1][1]_0 ;
  wire \buf_fifo_reg[1][2]_0 ;
  wire \buf_fifo_reg[1][3]_0 ;
  wire \buf_fifo_reg[1][4]_0 ;
  wire \buf_fifo_reg[2][0]_0 ;
  wire \buf_fifo_reg[2][1]_0 ;
  wire \buf_fifo_reg[2][2]_0 ;
  wire \buf_fifo_reg[2][3]_0 ;
  wire \buf_fifo_reg_n_0_[0][0] ;
  wire \buf_fifo_reg_n_0_[0][1] ;
  wire \buf_fifo_reg_n_0_[0][2] ;
  wire \buf_fifo_reg_n_0_[0][3] ;
  wire \buf_fifo_reg_n_0_[0][4] ;
  wire \buf_fifo_reg_n_0_[1][0] ;
  wire \buf_fifo_reg_n_0_[1][1] ;
  wire \buf_fifo_reg_n_0_[1][2] ;
  wire \buf_fifo_reg_n_0_[1][3] ;
  wire \buf_fifo_reg_n_0_[1][4] ;
  wire \buf_fifo_reg_n_0_[2][0] ;
  wire \buf_fifo_reg_n_0_[2][1] ;
  wire \buf_fifo_reg_n_0_[2][2] ;
  wire \buf_fifo_reg_n_0_[2][3] ;
  wire \buf_fifo_reg_n_0_[2][4] ;
  wire \buf_fifo_reg_n_0_[3][0] ;
  wire \buf_fifo_reg_n_0_[3][1] ;
  wire \buf_fifo_reg_n_0_[3][2] ;
  wire \buf_fifo_reg_n_0_[3][3] ;
  wire \buf_fifo_reg_n_0_[3][4] ;
  wire \cas_dbuf_fifo[0][0]_i_1__1_n_0 ;
  wire \cas_dbuf_fifo[0][1]_i_1__1_n_0 ;
  wire \cas_dbuf_fifo[0][2]_i_1__1_n_0 ;
  wire \cas_dbuf_fifo[0][3]_i_1__1_n_0 ;
  wire \cas_dbuf_fifo[0][4]_i_1__1_n_0 ;
  wire \cas_dbuf_fifo_reg_n_0_[0][0] ;
  wire \cas_dbuf_fifo_reg_n_0_[0][1] ;
  wire \cas_dbuf_fifo_reg_n_0_[0][2] ;
  wire \cas_dbuf_fifo_reg_n_0_[0][3] ;
  wire \cas_dbuf_fifo_reg_n_0_[0][4] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][0] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][1] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][2] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][3] ;
  wire \cas_dbuf_fifo_reg_n_0_[1][4] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][0] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][1] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][2] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][3] ;
  wire \cas_dbuf_fifo_reg_n_0_[2][4] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][0] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][1] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][2] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][3] ;
  wire \cas_dbuf_fifo_reg_n_0_[3][4] ;
  wire cas_fifo_empty_i_1__0_n_0;
  wire cas_fifo_empty_reg_n_0;
  wire cas_fifo_full_i_1__0_n_0;
  wire cas_fifo_full_reg_n_0;
  wire \cas_fifo_rptr[0]_i_1__0_n_0 ;
  wire \cas_fifo_rptr[1]_i_1__0_n_0 ;
  wire \cas_fifo_rptr[1]_i_2__0_n_0 ;
  wire [0:0]\cas_fifo_rptr_reg[0]_0 ;
  wire \cas_fifo_rptr_reg_n_0_[0] ;
  wire \cas_fifo_rptr_reg_n_0_[1] ;
  wire \cas_fifo_valid[0]_i_1__0_n_0 ;
  wire \cas_fifo_valid[0]_i_2__0_n_0 ;
  wire \cas_fifo_valid[1]_i_1__0_n_0 ;
  wire \cas_fifo_valid[1]_i_2__0_n_0 ;
  wire \cas_fifo_valid[2]_i_1__0_n_0 ;
  wire \cas_fifo_valid[2]_i_2__0_n_0 ;
  wire \cas_fifo_valid[3]_i_1__0_n_0 ;
  wire \cas_fifo_valid[3]_i_2__0_n_0 ;
  wire \cas_fifo_valid_reg_n_0_[0] ;
  wire \cas_fifo_valid_reg_n_0_[1] ;
  wire \cas_fifo_valid_reg_n_0_[2] ;
  wire \cas_fifo_valid_reg_n_0_[3] ;
  wire \cas_fifo_wptr[0]_i_1__2_n_0 ;
  wire \cas_fifo_wptr[1]_i_1__2_n_0 ;
  wire \cas_fifo_wptr[1]_i_2__0_n_0 ;
  wire \cas_fifo_wptr[1]_i_3_n_0 ;
  wire \cas_fifo_wptr[1]_i_4_n_0 ;
  wire \cas_fifo_wptr[1]_i_5_n_0 ;
  wire \cas_fifo_wptr_reg_n_0_[0] ;
  wire \cas_fifo_wptr_reg_n_0_[1] ;
  wire \cas_pend_fifo[0][47]_i_1_n_0 ;
  wire \cas_pend_fifo[1][47]_i_1_n_0 ;
  wire \cas_pend_fifo[2][47]_i_1_n_0 ;
  wire \cas_pend_fifo[3][47]_i_1_n_0 ;
  wire \cas_pend_fifo_reg_n_0_[0][0] ;
  wire \cas_pend_fifo_reg_n_0_[0][11] ;
  wire \cas_pend_fifo_reg_n_0_[0][12] ;
  wire \cas_pend_fifo_reg_n_0_[0][13] ;
  wire \cas_pend_fifo_reg_n_0_[0][14] ;
  wire \cas_pend_fifo_reg_n_0_[0][15] ;
  wire \cas_pend_fifo_reg_n_0_[0][16] ;
  wire \cas_pend_fifo_reg_n_0_[0][17] ;
  wire \cas_pend_fifo_reg_n_0_[0][1] ;
  wire \cas_pend_fifo_reg_n_0_[0][24] ;
  wire \cas_pend_fifo_reg_n_0_[0][25] ;
  wire \cas_pend_fifo_reg_n_0_[0][26] ;
  wire \cas_pend_fifo_reg_n_0_[0][27] ;
  wire \cas_pend_fifo_reg_n_0_[0][28] ;
  wire \cas_pend_fifo_reg_n_0_[0][29] ;
  wire \cas_pend_fifo_reg_n_0_[0][2] ;
  wire \cas_pend_fifo_reg_n_0_[0][30] ;
  wire \cas_pend_fifo_reg_n_0_[0][31] ;
  wire \cas_pend_fifo_reg_n_0_[0][32] ;
  wire \cas_pend_fifo_reg_n_0_[0][33] ;
  wire \cas_pend_fifo_reg_n_0_[0][34] ;
  wire \cas_pend_fifo_reg_n_0_[0][35] ;
  wire \cas_pend_fifo_reg_n_0_[0][36] ;
  wire \cas_pend_fifo_reg_n_0_[0][37] ;
  wire \cas_pend_fifo_reg_n_0_[0][38] ;
  wire \cas_pend_fifo_reg_n_0_[0][39] ;
  wire \cas_pend_fifo_reg_n_0_[0][40] ;
  wire \cas_pend_fifo_reg_n_0_[0][44] ;
  wire \cas_pend_fifo_reg_n_0_[0][45] ;
  wire \cas_pend_fifo_reg_n_0_[0][46] ;
  wire \cas_pend_fifo_reg_n_0_[0][47] ;
  wire \cas_pend_fifo_reg_n_0_[1][0] ;
  wire \cas_pend_fifo_reg_n_0_[1][11] ;
  wire \cas_pend_fifo_reg_n_0_[1][12] ;
  wire \cas_pend_fifo_reg_n_0_[1][13] ;
  wire \cas_pend_fifo_reg_n_0_[1][14] ;
  wire \cas_pend_fifo_reg_n_0_[1][15] ;
  wire \cas_pend_fifo_reg_n_0_[1][16] ;
  wire \cas_pend_fifo_reg_n_0_[1][17] ;
  wire \cas_pend_fifo_reg_n_0_[1][1] ;
  wire \cas_pend_fifo_reg_n_0_[1][24] ;
  wire \cas_pend_fifo_reg_n_0_[1][25] ;
  wire \cas_pend_fifo_reg_n_0_[1][26] ;
  wire \cas_pend_fifo_reg_n_0_[1][27] ;
  wire \cas_pend_fifo_reg_n_0_[1][28] ;
  wire \cas_pend_fifo_reg_n_0_[1][29] ;
  wire \cas_pend_fifo_reg_n_0_[1][2] ;
  wire \cas_pend_fifo_reg_n_0_[1][30] ;
  wire \cas_pend_fifo_reg_n_0_[1][31] ;
  wire \cas_pend_fifo_reg_n_0_[1][32] ;
  wire \cas_pend_fifo_reg_n_0_[1][33] ;
  wire \cas_pend_fifo_reg_n_0_[1][34] ;
  wire \cas_pend_fifo_reg_n_0_[1][35] ;
  wire \cas_pend_fifo_reg_n_0_[1][36] ;
  wire \cas_pend_fifo_reg_n_0_[1][37] ;
  wire \cas_pend_fifo_reg_n_0_[1][38] ;
  wire \cas_pend_fifo_reg_n_0_[1][39] ;
  wire \cas_pend_fifo_reg_n_0_[1][40] ;
  wire \cas_pend_fifo_reg_n_0_[1][44] ;
  wire \cas_pend_fifo_reg_n_0_[1][45] ;
  wire \cas_pend_fifo_reg_n_0_[1][46] ;
  wire \cas_pend_fifo_reg_n_0_[1][47] ;
  wire \cas_pend_fifo_reg_n_0_[2][0] ;
  wire \cas_pend_fifo_reg_n_0_[2][11] ;
  wire \cas_pend_fifo_reg_n_0_[2][12] ;
  wire \cas_pend_fifo_reg_n_0_[2][13] ;
  wire \cas_pend_fifo_reg_n_0_[2][14] ;
  wire \cas_pend_fifo_reg_n_0_[2][15] ;
  wire \cas_pend_fifo_reg_n_0_[2][16] ;
  wire \cas_pend_fifo_reg_n_0_[2][17] ;
  wire \cas_pend_fifo_reg_n_0_[2][1] ;
  wire \cas_pend_fifo_reg_n_0_[2][24] ;
  wire \cas_pend_fifo_reg_n_0_[2][25] ;
  wire \cas_pend_fifo_reg_n_0_[2][26] ;
  wire \cas_pend_fifo_reg_n_0_[2][27] ;
  wire \cas_pend_fifo_reg_n_0_[2][28] ;
  wire \cas_pend_fifo_reg_n_0_[2][29] ;
  wire \cas_pend_fifo_reg_n_0_[2][2] ;
  wire \cas_pend_fifo_reg_n_0_[2][30] ;
  wire \cas_pend_fifo_reg_n_0_[2][31] ;
  wire \cas_pend_fifo_reg_n_0_[2][32] ;
  wire \cas_pend_fifo_reg_n_0_[2][33] ;
  wire \cas_pend_fifo_reg_n_0_[2][34] ;
  wire \cas_pend_fifo_reg_n_0_[2][35] ;
  wire \cas_pend_fifo_reg_n_0_[2][36] ;
  wire \cas_pend_fifo_reg_n_0_[2][37] ;
  wire \cas_pend_fifo_reg_n_0_[2][38] ;
  wire \cas_pend_fifo_reg_n_0_[2][39] ;
  wire \cas_pend_fifo_reg_n_0_[2][40] ;
  wire \cas_pend_fifo_reg_n_0_[2][44] ;
  wire \cas_pend_fifo_reg_n_0_[2][45] ;
  wire \cas_pend_fifo_reg_n_0_[2][46] ;
  wire \cas_pend_fifo_reg_n_0_[2][47] ;
  wire \cas_pend_fifo_reg_n_0_[3][0] ;
  wire \cas_pend_fifo_reg_n_0_[3][11] ;
  wire \cas_pend_fifo_reg_n_0_[3][12] ;
  wire \cas_pend_fifo_reg_n_0_[3][13] ;
  wire \cas_pend_fifo_reg_n_0_[3][14] ;
  wire \cas_pend_fifo_reg_n_0_[3][15] ;
  wire \cas_pend_fifo_reg_n_0_[3][16] ;
  wire \cas_pend_fifo_reg_n_0_[3][17] ;
  wire \cas_pend_fifo_reg_n_0_[3][1] ;
  wire \cas_pend_fifo_reg_n_0_[3][24] ;
  wire \cas_pend_fifo_reg_n_0_[3][25] ;
  wire \cas_pend_fifo_reg_n_0_[3][26] ;
  wire \cas_pend_fifo_reg_n_0_[3][27] ;
  wire \cas_pend_fifo_reg_n_0_[3][28] ;
  wire \cas_pend_fifo_reg_n_0_[3][29] ;
  wire \cas_pend_fifo_reg_n_0_[3][2] ;
  wire \cas_pend_fifo_reg_n_0_[3][30] ;
  wire \cas_pend_fifo_reg_n_0_[3][31] ;
  wire \cas_pend_fifo_reg_n_0_[3][32] ;
  wire \cas_pend_fifo_reg_n_0_[3][33] ;
  wire \cas_pend_fifo_reg_n_0_[3][34] ;
  wire \cas_pend_fifo_reg_n_0_[3][35] ;
  wire \cas_pend_fifo_reg_n_0_[3][36] ;
  wire \cas_pend_fifo_reg_n_0_[3][37] ;
  wire \cas_pend_fifo_reg_n_0_[3][38] ;
  wire \cas_pend_fifo_reg_n_0_[3][39] ;
  wire \cas_pend_fifo_reg_n_0_[3][40] ;
  wire \cas_pend_fifo_reg_n_0_[3][44] ;
  wire \cas_pend_fifo_reg_n_0_[3][45] ;
  wire \cas_pend_fifo_reg_n_0_[3][46] ;
  wire \cas_pend_fifo_reg_n_0_[3][47] ;
  wire clrReq15_out;
  wire [2:0]cmd;
  wire [0:0]cmdAP;
  wire cmdAP_i_1__0_n_0;
  wire cmdAP_i_2__0_n_0;
  wire \cmdBankP[1]_i_1__0_n_0 ;
  wire \cmdBankP[1]_i_2__1_n_0 ;
  wire \cmdBankP[1]_i_3__1_n_0 ;
  wire \cmdBankP[1]_i_4_n_0 ;
  wire \cmdBankP[1]_i_5_n_0 ;
  wire \cmdBankP[1]_i_6_n_0 ;
  wire [1:0]\cmdBankP_reg[1]_0 ;
  wire [4:0]cmdBuf;
  wire \cmdBuf[0]_i_1__0_n_0 ;
  wire \cmdBuf[1]_i_1__0_n_0 ;
  wire \cmdBuf[2]_i_1__0_n_0 ;
  wire \cmdBuf[3]_i_1__0_n_0 ;
  wire \cmdBuf[4]_i_1__0_n_0 ;
  wire \cmdCol[3]_i_1__0_n_0 ;
  wire \cmdCol[3]_i_2__0_n_0 ;
  wire \cmdCol[4]_i_1__0_n_0 ;
  wire \cmdCol[4]_i_2__0_n_0 ;
  wire \cmdCol[5]_i_1__0_n_0 ;
  wire \cmdCol[5]_i_2__0_n_0 ;
  wire \cmdCol[6]_i_1__0_n_0 ;
  wire \cmdCol[6]_i_2__0_n_0 ;
  wire \cmdCol[7]_i_1__0_n_0 ;
  wire \cmdCol[7]_i_2__0_n_0 ;
  wire \cmdCol[8]_i_1__0_n_0 ;
  wire \cmdCol[8]_i_2__0_n_0 ;
  wire \cmdCol[9]_i_1__0_n_0 ;
  wire \cmdCol[9]_i_2__0_n_0 ;
  wire [6:0]\cmdCol_reg[9]_0 ;
  wire [0:0]cmdGroupP;
  wire \cmdGroupP_reg[0]_0 ;
  wire cmdRmw_i_1__0_n_0;
  wire cmdRmw_reg_0;
  wire \cmd_bank_cas[0]_i_1__0_n_0 ;
  wire \cmd_bank_cas[0]_i_2__0_n_0 ;
  wire \cmd_bank_cas[0]_i_3_n_0 ;
  wire \cmd_bank_cas[1]_i_1__0_n_0 ;
  wire \cmd_bank_cas[1]_i_2__0_n_0 ;
  wire [1:0]\cmd_bank_cas_reg[1]_0 ;
  wire [0:0]cmd_group_cas;
  wire \cmd_group_cas[0]_i_1__0_n_0 ;
  wire \cmd_group_cas[0]_i_2__0_n_0 ;
  wire \cmd_row_cas[0]_i_1__0_n_0 ;
  wire \cmd_row_cas[0]_i_2__0_n_0 ;
  wire \cmd_row_cas[10]_i_1__0_n_0 ;
  wire \cmd_row_cas[10]_i_2__0_n_0 ;
  wire \cmd_row_cas[11]_i_1__0_n_0 ;
  wire \cmd_row_cas[11]_i_2__0_n_0 ;
  wire \cmd_row_cas[12]_i_1__0_n_0 ;
  wire \cmd_row_cas[12]_i_2__0_n_0 ;
  wire \cmd_row_cas[13]_i_1__0_n_0 ;
  wire \cmd_row_cas[13]_i_2__0_n_0 ;
  wire \cmd_row_cas[14]_i_1__0_n_0 ;
  wire \cmd_row_cas[14]_i_2__0_n_0 ;
  wire \cmd_row_cas[15]_i_1__0_n_0 ;
  wire \cmd_row_cas[15]_i_2__0_n_0 ;
  wire \cmd_row_cas[16]_i_1__0_n_0 ;
  wire \cmd_row_cas[16]_i_2__0_n_0 ;
  wire \cmd_row_cas[1]_i_1__0_n_0 ;
  wire \cmd_row_cas[1]_i_2__0_n_0 ;
  wire \cmd_row_cas[2]_i_1__0_n_0 ;
  wire \cmd_row_cas[2]_i_2__0_n_0 ;
  wire \cmd_row_cas[3]_i_1__0_n_0 ;
  wire \cmd_row_cas[3]_i_2__0_n_0 ;
  wire \cmd_row_cas[4]_i_1__0_n_0 ;
  wire \cmd_row_cas[4]_i_2__0_n_0 ;
  wire \cmd_row_cas[5]_i_1__0_n_0 ;
  wire \cmd_row_cas[5]_i_2__0_n_0 ;
  wire \cmd_row_cas[6]_i_1__0_n_0 ;
  wire \cmd_row_cas[6]_i_2__0_n_0 ;
  wire \cmd_row_cas[7]_i_1__0_n_0 ;
  wire \cmd_row_cas[7]_i_2__0_n_0 ;
  wire \cmd_row_cas[8]_i_1__0_n_0 ;
  wire \cmd_row_cas[8]_i_2__0_n_0 ;
  wire \cmd_row_cas[9]_i_1__0_n_0 ;
  wire \cmd_row_cas[9]_i_2__0_n_0 ;
  wire \cmd_row_cas_reg_n_0_[0] ;
  wire \cmd_row_cas_reg_n_0_[10] ;
  wire \cmd_row_cas_reg_n_0_[11] ;
  wire \cmd_row_cas_reg_n_0_[12] ;
  wire \cmd_row_cas_reg_n_0_[13] ;
  wire \cmd_row_cas_reg_n_0_[14] ;
  wire \cmd_row_cas_reg_n_0_[15] ;
  wire \cmd_row_cas_reg_n_0_[16] ;
  wire \cmd_row_cas_reg_n_0_[1] ;
  wire \cmd_row_cas_reg_n_0_[2] ;
  wire \cmd_row_cas_reg_n_0_[3] ;
  wire \cmd_row_cas_reg_n_0_[4] ;
  wire \cmd_row_cas_reg_n_0_[5] ;
  wire \cmd_row_cas_reg_n_0_[6] ;
  wire \cmd_row_cas_reg_n_0_[7] ;
  wire \cmd_row_cas_reg_n_0_[8] ;
  wire \cmd_row_cas_reg_n_0_[9] ;
  wire [6:0]col;
  wire [0:0]grAccept_ns;
  wire [2:0]grSt;
  wire [2:0]gr_cas_state;
  wire [2:0]gr_cas_state_nxt;
  wire [0:0]group;
  wire i__carry_i_10__0_n_0;
  wire i__carry_i_11__0_n_0;
  wire i__carry_i_12__0_n_0;
  wire i__carry_i_13__0_n_0;
  wire i__carry_i_14__0_n_0;
  wire i__carry_i_15__0_n_0;
  wire i__carry_i_16__0_n_0;
  wire i__carry_i_17__0_n_0;
  wire i__carry_i_18__0_n_0;
  wire i__carry_i_19__0_n_0;
  wire i__carry_i_1__0_n_0;
  wire i__carry_i_20__0_n_0;
  wire i__carry_i_21__0_n_0;
  wire i__carry_i_22__0_n_0;
  wire i__carry_i_23__0_n_0;
  wire i__carry_i_2__0_n_0;
  wire i__carry_i_3__0_n_0;
  wire i__carry_i_4__0_n_0;
  wire i__carry_i_5__0_n_0;
  wire i__carry_i_6__0_n_0;
  wire i__carry_i_7__0_n_0;
  wire i__carry_i_8__0_n_0;
  wire i__carry_i_9__0_n_0;
  wire \issue_cas3_inferred__0/i__carry_n_2 ;
  wire \issue_cas3_inferred__0/i__carry_n_3 ;
  wire \issue_cas3_inferred__0/i__carry_n_4 ;
  wire \issue_cas3_inferred__0/i__carry_n_5 ;
  wire \issue_cas3_inferred__0/i__carry_n_6 ;
  wire \issue_cas3_inferred__0/i__carry_n_7 ;
  wire \pageInfo[0][0][0][0]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][0]_i_2__0_n_0 ;
  wire \pageInfo[0][0][0][0]_i_3__0_n_0 ;
  wire \pageInfo[0][0][0][10]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][11]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][12]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][13]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][14]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][15]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][16]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][17]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][18]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][18]_i_2__0_n_0 ;
  wire \pageInfo[0][0][0][1]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][2]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][3]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][4]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][5]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][6]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][7]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][8]_i_1__0_n_0 ;
  wire \pageInfo[0][0][0][9]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][0]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][0]_i_2__0_n_0 ;
  wire \pageInfo[0][0][1][0]_i_3__0_n_0 ;
  wire \pageInfo[0][0][1][10]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][11]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][12]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][13]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][14]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][15]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][16]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][17]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][18]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][18]_i_2__0_n_0 ;
  wire \pageInfo[0][0][1][1]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][2]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][3]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][4]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][5]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][6]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][7]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][8]_i_1__0_n_0 ;
  wire \pageInfo[0][0][1][9]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][0]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][10]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][11]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][12]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][13]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][14]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][15]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][16]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][17]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][18]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][18]_i_2__0_n_0 ;
  wire \pageInfo[0][0][2][1]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][2]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][3]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][4]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][5]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][6]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][7]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][8]_i_1__0_n_0 ;
  wire \pageInfo[0][0][2][9]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][0]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][0]_i_2__0_n_0 ;
  wire \pageInfo[0][0][3][10]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][11]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][12]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][13]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][14]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][15]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][16]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][17]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][18]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][18]_i_2__0_n_0 ;
  wire \pageInfo[0][0][3][18]_i_3__0_n_0 ;
  wire \pageInfo[0][0][3][1]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][2]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][3]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][4]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][5]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][6]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][7]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][8]_i_1__0_n_0 ;
  wire \pageInfo[0][0][3][9]_i_1__0_n_0 ;
  wire \pageInfo_reg_n_0_[0][0][0][0] ;
  wire \pageInfo_reg_n_0_[0][0][0][10] ;
  wire \pageInfo_reg_n_0_[0][0][0][11] ;
  wire \pageInfo_reg_n_0_[0][0][0][12] ;
  wire \pageInfo_reg_n_0_[0][0][0][13] ;
  wire \pageInfo_reg_n_0_[0][0][0][14] ;
  wire \pageInfo_reg_n_0_[0][0][0][15] ;
  wire \pageInfo_reg_n_0_[0][0][0][16] ;
  wire \pageInfo_reg_n_0_[0][0][0][17] ;
  wire \pageInfo_reg_n_0_[0][0][0][18] ;
  wire \pageInfo_reg_n_0_[0][0][0][1] ;
  wire \pageInfo_reg_n_0_[0][0][0][2] ;
  wire \pageInfo_reg_n_0_[0][0][0][3] ;
  wire \pageInfo_reg_n_0_[0][0][0][4] ;
  wire \pageInfo_reg_n_0_[0][0][0][5] ;
  wire \pageInfo_reg_n_0_[0][0][0][6] ;
  wire \pageInfo_reg_n_0_[0][0][0][7] ;
  wire \pageInfo_reg_n_0_[0][0][0][8] ;
  wire \pageInfo_reg_n_0_[0][0][0][9] ;
  wire \pageInfo_reg_n_0_[0][0][1][0] ;
  wire \pageInfo_reg_n_0_[0][0][1][10] ;
  wire \pageInfo_reg_n_0_[0][0][1][11] ;
  wire \pageInfo_reg_n_0_[0][0][1][12] ;
  wire \pageInfo_reg_n_0_[0][0][1][13] ;
  wire \pageInfo_reg_n_0_[0][0][1][14] ;
  wire \pageInfo_reg_n_0_[0][0][1][15] ;
  wire \pageInfo_reg_n_0_[0][0][1][16] ;
  wire \pageInfo_reg_n_0_[0][0][1][17] ;
  wire \pageInfo_reg_n_0_[0][0][1][18] ;
  wire \pageInfo_reg_n_0_[0][0][1][1] ;
  wire \pageInfo_reg_n_0_[0][0][1][2] ;
  wire \pageInfo_reg_n_0_[0][0][1][3] ;
  wire \pageInfo_reg_n_0_[0][0][1][4] ;
  wire \pageInfo_reg_n_0_[0][0][1][5] ;
  wire \pageInfo_reg_n_0_[0][0][1][6] ;
  wire \pageInfo_reg_n_0_[0][0][1][7] ;
  wire \pageInfo_reg_n_0_[0][0][1][8] ;
  wire \pageInfo_reg_n_0_[0][0][1][9] ;
  wire \pageInfo_reg_n_0_[0][0][2][0] ;
  wire \pageInfo_reg_n_0_[0][0][2][10] ;
  wire \pageInfo_reg_n_0_[0][0][2][11] ;
  wire \pageInfo_reg_n_0_[0][0][2][12] ;
  wire \pageInfo_reg_n_0_[0][0][2][13] ;
  wire \pageInfo_reg_n_0_[0][0][2][14] ;
  wire \pageInfo_reg_n_0_[0][0][2][15] ;
  wire \pageInfo_reg_n_0_[0][0][2][16] ;
  wire \pageInfo_reg_n_0_[0][0][2][17] ;
  wire \pageInfo_reg_n_0_[0][0][2][18] ;
  wire \pageInfo_reg_n_0_[0][0][2][1] ;
  wire \pageInfo_reg_n_0_[0][0][2][2] ;
  wire \pageInfo_reg_n_0_[0][0][2][3] ;
  wire \pageInfo_reg_n_0_[0][0][2][4] ;
  wire \pageInfo_reg_n_0_[0][0][2][5] ;
  wire \pageInfo_reg_n_0_[0][0][2][6] ;
  wire \pageInfo_reg_n_0_[0][0][2][7] ;
  wire \pageInfo_reg_n_0_[0][0][2][8] ;
  wire \pageInfo_reg_n_0_[0][0][2][9] ;
  wire \pageInfo_reg_n_0_[0][0][3][0] ;
  wire \pageInfo_reg_n_0_[0][0][3][10] ;
  wire \pageInfo_reg_n_0_[0][0][3][11] ;
  wire \pageInfo_reg_n_0_[0][0][3][12] ;
  wire \pageInfo_reg_n_0_[0][0][3][13] ;
  wire \pageInfo_reg_n_0_[0][0][3][14] ;
  wire \pageInfo_reg_n_0_[0][0][3][15] ;
  wire \pageInfo_reg_n_0_[0][0][3][16] ;
  wire \pageInfo_reg_n_0_[0][0][3][17] ;
  wire \pageInfo_reg_n_0_[0][0][3][18] ;
  wire \pageInfo_reg_n_0_[0][0][3][1] ;
  wire \pageInfo_reg_n_0_[0][0][3][2] ;
  wire \pageInfo_reg_n_0_[0][0][3][3] ;
  wire \pageInfo_reg_n_0_[0][0][3][4] ;
  wire \pageInfo_reg_n_0_[0][0][3][5] ;
  wire \pageInfo_reg_n_0_[0][0][3][6] ;
  wire \pageInfo_reg_n_0_[0][0][3][7] ;
  wire \pageInfo_reg_n_0_[0][0][3][8] ;
  wire \pageInfo_reg_n_0_[0][0][3][9] ;
  wire preReqR_i_1__1_n_0;
  wire preReqR_reg_0;
  wire [0:0]preReqR_reg_1;
  wire rdReqR_i_1__0_n_0;
  wire rdReqR_i_2__0_n_0;
  wire rdReqR_reg_0;
  wire [0:0]refOK;
  wire refOK_i_1__0_n_0;
  wire refOK_reg_0;
  wire refReq;
  wire ref_req_dly4;
  wire [16:0]row_mc_phy;
  (* RTL_KEEP = "true" *) wire rst_r1;
  wire [1:1]sel0__18;
  wire [1:1]sel0__22;
  wire [1:1]sel0__26;
  wire [1:1]sel0__30;
  wire tranSentC;
  wire \tras_cntr_rb[0][0][0][0]_i_1__0_n_0 ;
  wire \tras_cntr_rb[0][0][0][1]_i_1__0_n_0 ;
  wire \tras_cntr_rb[0][0][0][2]_i_1__0_n_0 ;
  wire \tras_cntr_rb[0][0][1][0]_i_1__0_n_0 ;
  wire \tras_cntr_rb[0][0][1][1]_i_1__0_n_0 ;
  wire \tras_cntr_rb[0][0][1][2]_i_1__0_n_0 ;
  wire \tras_cntr_rb[0][0][2][0]_i_1__0_n_0 ;
  wire \tras_cntr_rb[0][0][2][1]_i_1__0_n_0 ;
  wire \tras_cntr_rb[0][0][2][2]_i_1__0_n_0 ;
  wire \tras_cntr_rb[0][0][3][0]_i_1__0_n_0 ;
  wire \tras_cntr_rb[0][0][3][1]_i_1__0_n_0 ;
  wire \tras_cntr_rb[0][0][3][2]_i_1__0_n_0 ;
  wire \tras_cntr_rb_reg_n_0_[0][0][0][0] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][0][1] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][0][2] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][1][0] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][1][1] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][1][2] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][2][0] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][2][1] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][2][2] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][3][0] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][3][1] ;
  wire \tras_cntr_rb_reg_n_0_[0][0][3][2] ;
  wire \trcd_cntr[0][0][0][0]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][0][1]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][0][2]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][0][2]_i_2__0_n_0 ;
  wire \trcd_cntr[0][0][0][3]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][1][0]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][1][1]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][1][2]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][1][2]_i_2__0_n_0 ;
  wire \trcd_cntr[0][0][1][3]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][2][0]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][2][1]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][2][2]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][2][2]_i_2__0_n_0 ;
  wire \trcd_cntr[0][0][2][3]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][3][0]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][3][1]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][3][2]_i_1__0_n_0 ;
  wire \trcd_cntr[0][0][3][2]_i_2__0_n_0 ;
  wire \trcd_cntr[0][0][3][3]_i_1__0_n_0 ;
  wire \trcd_cntr_is_zero[0][0][0]_i_1__0_n_0 ;
  wire \trcd_cntr_is_zero[0][0][0]_i_2__0_n_0 ;
  wire \trcd_cntr_is_zero[0][0][1]_i_1__0_n_0 ;
  wire \trcd_cntr_is_zero[0][0][1]_i_2__0_n_0 ;
  wire \trcd_cntr_is_zero[0][0][2]_i_1__0_n_0 ;
  wire \trcd_cntr_is_zero[0][0][2]_i_2__0_n_0 ;
  wire \trcd_cntr_is_zero[0][0][3]_i_1__0_n_0 ;
  wire \trcd_cntr_is_zero[0][0][3]_i_2__0_n_0 ;
  wire \trcd_cntr_is_zero_reg_n_0_[0][0][0] ;
  wire \trcd_cntr_is_zero_reg_n_0_[0][0][1] ;
  wire \trcd_cntr_is_zero_reg_n_0_[0][0][2] ;
  wire \trcd_cntr_is_zero_reg_n_0_[0][0][3] ;
  wire \trcd_cntr_reg_n_0_[0][0][0][0] ;
  wire \trcd_cntr_reg_n_0_[0][0][0][1] ;
  wire \trcd_cntr_reg_n_0_[0][0][0][2] ;
  wire \trcd_cntr_reg_n_0_[0][0][0][3] ;
  wire \trcd_cntr_reg_n_0_[0][0][1][0] ;
  wire \trcd_cntr_reg_n_0_[0][0][1][1] ;
  wire \trcd_cntr_reg_n_0_[0][0][1][2] ;
  wire \trcd_cntr_reg_n_0_[0][0][1][3] ;
  wire \trcd_cntr_reg_n_0_[0][0][2][0] ;
  wire \trcd_cntr_reg_n_0_[0][0][2][1] ;
  wire \trcd_cntr_reg_n_0_[0][0][2][2] ;
  wire \trcd_cntr_reg_n_0_[0][0][2][3] ;
  wire \trcd_cntr_reg_n_0_[0][0][3][0] ;
  wire \trcd_cntr_reg_n_0_[0][0][3][1] ;
  wire \trcd_cntr_reg_n_0_[0][0][3][2] ;
  wire \trcd_cntr_reg_n_0_[0][0][3][3] ;
  wire \trp_cntr[0]_i_1__0_n_0 ;
  wire \trp_cntr[0]_i_2__0_n_0 ;
  wire \trp_cntr[1]_i_1__0_n_0 ;
  wire \trp_cntr[1]_i_2__0_n_0 ;
  wire \trp_cntr[1]_i_3__0_n_0 ;
  wire \trp_cntr[2]_i_1__0_n_0 ;
  wire \trp_cntr[2]_i_2__0_n_0 ;
  wire \trp_cntr[3]_i_1__0_n_0 ;
  wire \trp_cntr[3]_i_2__0_n_0 ;
  wire \trp_cntr[3]_i_3__0_n_0 ;
  wire \trp_cntr[4]_i_1__0_n_0 ;
  wire \trp_cntr[4]_i_2__0_n_0 ;
  wire \trp_cntr[4]_i_3__0_n_0 ;
  wire trp_cntr_is_zero_i_1__0_n_0;
  wire trp_cntr_is_zero_reg_n_0;
  wire \trp_cntr_reg_n_0_[0] ;
  wire \trp_cntr_reg_n_0_[1] ;
  wire \trp_cntr_reg_n_0_[2] ;
  wire \trp_cntr_reg_n_0_[3] ;
  wire \trp_cntr_reg_n_0_[4] ;
  wire \txn_fifo[0][0]_i_1__2_n_0 ;
  wire \txn_fifo[0][11]_i_1__2_n_0 ;
  wire \txn_fifo[0][12]_i_1__2_n_0 ;
  wire \txn_fifo[0][13]_i_1__2_n_0 ;
  wire \txn_fifo[0][14]_i_1__2_n_0 ;
  wire \txn_fifo[0][15]_i_1__2_n_0 ;
  wire \txn_fifo[0][16]_i_1__2_n_0 ;
  wire \txn_fifo[0][17]_i_1__2_n_0 ;
  wire \txn_fifo[0][1]_i_1__2_n_0 ;
  wire \txn_fifo[0][24]_i_1__2_n_0 ;
  wire \txn_fifo[0][25]_i_1__2_n_0 ;
  wire \txn_fifo[0][26]_i_1__2_n_0 ;
  wire \txn_fifo[0][27]_i_1__2_n_0 ;
  wire \txn_fifo[0][28]_i_1__2_n_0 ;
  wire \txn_fifo[0][29]_i_1__2_n_0 ;
  wire \txn_fifo[0][2]_i_1__2_n_0 ;
  wire \txn_fifo[0][30]_i_1__2_n_0 ;
  wire \txn_fifo[0][31]_i_1__2_n_0 ;
  wire \txn_fifo[0][32]_i_1__2_n_0 ;
  wire \txn_fifo[0][33]_i_1__2_n_0 ;
  wire \txn_fifo[0][34]_i_1__2_n_0 ;
  wire \txn_fifo[0][35]_i_1__2_n_0 ;
  wire \txn_fifo[0][36]_i_1__2_n_0 ;
  wire \txn_fifo[0][37]_i_1__2_n_0 ;
  wire \txn_fifo[0][38]_i_1__2_n_0 ;
  wire \txn_fifo[0][39]_i_1__2_n_0 ;
  wire \txn_fifo[0][40]_i_1__2_n_0 ;
  wire \txn_fifo[0][44]_i_1__2_n_0 ;
  wire \txn_fifo[0][45]_i_1__2_n_0 ;
  wire \txn_fifo[0][46]_i_1__2_n_0 ;
  wire \txn_fifo[0][47]_i_1__2_n_0 ;
  wire \txn_fifo[0][47]_i_2__1_n_0 ;
  wire \txn_fifo[1][0]_i_1__2_n_0 ;
  wire \txn_fifo[1][11]_i_1__2_n_0 ;
  wire \txn_fifo[1][12]_i_1__2_n_0 ;
  wire \txn_fifo[1][13]_i_1__2_n_0 ;
  wire \txn_fifo[1][14]_i_1__2_n_0 ;
  wire \txn_fifo[1][15]_i_1__2_n_0 ;
  wire \txn_fifo[1][16]_i_1__2_n_0 ;
  wire \txn_fifo[1][17]_i_1__2_n_0 ;
  wire \txn_fifo[1][1]_i_1__2_n_0 ;
  wire \txn_fifo[1][24]_i_1__2_n_0 ;
  wire \txn_fifo[1][25]_i_1__2_n_0 ;
  wire \txn_fifo[1][26]_i_1__2_n_0 ;
  wire \txn_fifo[1][27]_i_1__2_n_0 ;
  wire \txn_fifo[1][28]_i_1__2_n_0 ;
  wire \txn_fifo[1][29]_i_1__2_n_0 ;
  wire \txn_fifo[1][2]_i_1__2_n_0 ;
  wire \txn_fifo[1][30]_i_1__2_n_0 ;
  wire \txn_fifo[1][31]_i_1__2_n_0 ;
  wire \txn_fifo[1][32]_i_1__2_n_0 ;
  wire \txn_fifo[1][33]_i_1__2_n_0 ;
  wire \txn_fifo[1][34]_i_1__2_n_0 ;
  wire \txn_fifo[1][35]_i_1__2_n_0 ;
  wire \txn_fifo[1][36]_i_1__2_n_0 ;
  wire \txn_fifo[1][37]_i_1__2_n_0 ;
  wire \txn_fifo[1][38]_i_1__2_n_0 ;
  wire \txn_fifo[1][39]_i_1__2_n_0 ;
  wire \txn_fifo[1][40]_i_1__2_n_0 ;
  wire \txn_fifo[1][44]_i_1__2_n_0 ;
  wire \txn_fifo[1][45]_i_1__2_n_0 ;
  wire \txn_fifo[1][46]_i_1__2_n_0 ;
  wire \txn_fifo[1][47]_i_1__2_n_0 ;
  wire \txn_fifo[1][47]_i_2__1_n_0 ;
  wire \txn_fifo[2][0]_i_1__2_n_0 ;
  wire \txn_fifo[2][11]_i_1__2_n_0 ;
  wire \txn_fifo[2][12]_i_1__2_n_0 ;
  wire \txn_fifo[2][13]_i_1__2_n_0 ;
  wire \txn_fifo[2][14]_i_1__2_n_0 ;
  wire \txn_fifo[2][15]_i_1__2_n_0 ;
  wire \txn_fifo[2][16]_i_1__2_n_0 ;
  wire \txn_fifo[2][17]_i_1__2_n_0 ;
  wire \txn_fifo[2][1]_i_1__2_n_0 ;
  wire \txn_fifo[2][24]_i_1__2_n_0 ;
  wire \txn_fifo[2][25]_i_1__2_n_0 ;
  wire \txn_fifo[2][26]_i_1__2_n_0 ;
  wire \txn_fifo[2][27]_i_1__2_n_0 ;
  wire \txn_fifo[2][28]_i_1__2_n_0 ;
  wire \txn_fifo[2][29]_i_1__2_n_0 ;
  wire \txn_fifo[2][2]_i_1__2_n_0 ;
  wire \txn_fifo[2][30]_i_1__2_n_0 ;
  wire \txn_fifo[2][31]_i_1__2_n_0 ;
  wire \txn_fifo[2][32]_i_1__2_n_0 ;
  wire \txn_fifo[2][33]_i_1__2_n_0 ;
  wire \txn_fifo[2][34]_i_1__2_n_0 ;
  wire \txn_fifo[2][35]_i_1__2_n_0 ;
  wire \txn_fifo[2][36]_i_1__2_n_0 ;
  wire \txn_fifo[2][37]_i_1__2_n_0 ;
  wire \txn_fifo[2][38]_i_1__2_n_0 ;
  wire \txn_fifo[2][39]_i_1__2_n_0 ;
  wire \txn_fifo[2][40]_i_1__2_n_0 ;
  wire \txn_fifo[2][44]_i_1__2_n_0 ;
  wire \txn_fifo[2][45]_i_1__2_n_0 ;
  wire \txn_fifo[2][46]_i_1__2_n_0 ;
  wire \txn_fifo[2][47]_i_1__2_n_0 ;
  wire \txn_fifo[2][47]_i_2_n_0 ;
  wire \txn_fifo[3][0]_i_1__2_n_0 ;
  wire \txn_fifo[3][11]_i_1__2_n_0 ;
  wire \txn_fifo[3][12]_i_1__2_n_0 ;
  wire \txn_fifo[3][13]_i_1__2_n_0 ;
  wire \txn_fifo[3][14]_i_1__2_n_0 ;
  wire \txn_fifo[3][15]_i_1__2_n_0 ;
  wire \txn_fifo[3][16]_i_1__2_n_0 ;
  wire \txn_fifo[3][17]_i_1__2_n_0 ;
  wire \txn_fifo[3][1]_i_1__2_n_0 ;
  wire \txn_fifo[3][24]_i_1__2_n_0 ;
  wire \txn_fifo[3][25]_i_1__2_n_0 ;
  wire \txn_fifo[3][26]_i_1__2_n_0 ;
  wire \txn_fifo[3][27]_i_1__2_n_0 ;
  wire \txn_fifo[3][28]_i_1__2_n_0 ;
  wire \txn_fifo[3][29]_i_1__2_n_0 ;
  wire \txn_fifo[3][2]_i_1__2_n_0 ;
  wire \txn_fifo[3][30]_i_1__2_n_0 ;
  wire \txn_fifo[3][31]_i_1__2_n_0 ;
  wire \txn_fifo[3][32]_i_1__2_n_0 ;
  wire \txn_fifo[3][33]_i_1__2_n_0 ;
  wire \txn_fifo[3][34]_i_1__2_n_0 ;
  wire \txn_fifo[3][35]_i_1__2_n_0 ;
  wire \txn_fifo[3][36]_i_1__2_n_0 ;
  wire \txn_fifo[3][37]_i_1__2_n_0 ;
  wire \txn_fifo[3][38]_i_1__2_n_0 ;
  wire \txn_fifo[3][39]_i_1__2_n_0 ;
  wire \txn_fifo[3][40]_i_1__2_n_0 ;
  wire \txn_fifo[3][44]_i_1__2_n_0 ;
  wire \txn_fifo[3][45]_i_1__2_n_0 ;
  wire \txn_fifo[3][46]_i_1__2_n_0 ;
  wire \txn_fifo[3][47]_i_1__2_n_0 ;
  wire \txn_fifo[3][47]_i_2__1_n_0 ;
  wire txn_fifo_empty_i_1__2_n_0;
  wire txn_fifo_empty_i_2__1_n_0;
  wire txn_fifo_empty_reg_n_0;
  wire \txn_fifo_output[0]_i_1__2_n_0 ;
  wire \txn_fifo_output[0]_i_2__2_n_0 ;
  wire \txn_fifo_output[11]_i_1__2_n_0 ;
  wire \txn_fifo_output[11]_i_2__2_n_0 ;
  wire \txn_fifo_output[12]_i_1__2_n_0 ;
  wire \txn_fifo_output[12]_i_2__2_n_0 ;
  wire \txn_fifo_output[13]_i_1__2_n_0 ;
  wire \txn_fifo_output[13]_i_2__2_n_0 ;
  wire \txn_fifo_output[14]_i_1__2_n_0 ;
  wire \txn_fifo_output[14]_i_2__2_n_0 ;
  wire \txn_fifo_output[15]_i_1__2_n_0 ;
  wire \txn_fifo_output[15]_i_2__2_n_0 ;
  wire \txn_fifo_output[16]_i_1__2_n_0 ;
  wire \txn_fifo_output[16]_i_2__2_n_0 ;
  wire \txn_fifo_output[17]_i_1__2_n_0 ;
  wire \txn_fifo_output[17]_i_2__2_n_0 ;
  wire \txn_fifo_output[1]_i_1__2_n_0 ;
  wire \txn_fifo_output[1]_i_2__2_n_0 ;
  wire \txn_fifo_output[24]_i_1__2_n_0 ;
  wire \txn_fifo_output[24]_i_2__2_n_0 ;
  wire \txn_fifo_output[25]_i_1__2_n_0 ;
  wire \txn_fifo_output[25]_i_2__2_n_0 ;
  wire \txn_fifo_output[26]_i_1__2_n_0 ;
  wire \txn_fifo_output[26]_i_2__2_n_0 ;
  wire \txn_fifo_output[27]_i_1__2_n_0 ;
  wire \txn_fifo_output[27]_i_2__2_n_0 ;
  wire \txn_fifo_output[28]_i_1__2_n_0 ;
  wire \txn_fifo_output[28]_i_2__2_n_0 ;
  wire \txn_fifo_output[29]_i_1__2_n_0 ;
  wire \txn_fifo_output[29]_i_2__2_n_0 ;
  wire \txn_fifo_output[2]_i_1__2_n_0 ;
  wire \txn_fifo_output[2]_i_2__2_n_0 ;
  wire \txn_fifo_output[30]_i_1__2_n_0 ;
  wire \txn_fifo_output[30]_i_2__2_n_0 ;
  wire \txn_fifo_output[31]_i_1__2_n_0 ;
  wire \txn_fifo_output[31]_i_2__2_n_0 ;
  wire \txn_fifo_output[32]_i_1__2_n_0 ;
  wire \txn_fifo_output[32]_i_2__2_n_0 ;
  wire \txn_fifo_output[33]_i_1__2_n_0 ;
  wire \txn_fifo_output[33]_i_2__2_n_0 ;
  wire \txn_fifo_output[34]_i_1__2_n_0 ;
  wire \txn_fifo_output[34]_i_2__2_n_0 ;
  wire \txn_fifo_output[35]_i_1__2_n_0 ;
  wire \txn_fifo_output[35]_i_2__2_n_0 ;
  wire \txn_fifo_output[36]_i_1__2_n_0 ;
  wire \txn_fifo_output[36]_i_2__2_n_0 ;
  wire \txn_fifo_output[37]_i_1__2_n_0 ;
  wire \txn_fifo_output[37]_i_2__2_n_0 ;
  wire \txn_fifo_output[38]_i_1__2_n_0 ;
  wire \txn_fifo_output[38]_i_2__2_n_0 ;
  wire \txn_fifo_output[39]_i_1__2_n_0 ;
  wire \txn_fifo_output[39]_i_2__2_n_0 ;
  wire \txn_fifo_output[40]_i_1__2_n_0 ;
  wire \txn_fifo_output[40]_i_2__2_n_0 ;
  wire \txn_fifo_output[44]_i_1__2_n_0 ;
  wire \txn_fifo_output[44]_i_2__2_n_0 ;
  wire \txn_fifo_output[45]_i_1__2_n_0 ;
  wire \txn_fifo_output[45]_i_2__2_n_0 ;
  wire \txn_fifo_output[45]_i_3__2_n_0 ;
  wire \txn_fifo_output[46]_i_1__2_n_0 ;
  wire \txn_fifo_output[46]_i_2__2_n_0 ;
  wire \txn_fifo_output[47]_i_1__2_n_0 ;
  wire \txn_fifo_output[47]_i_2__2_n_0 ;
  wire \txn_fifo_output[47]_i_3__2_n_0 ;
  wire \txn_fifo_output_reg_n_0_[11] ;
  wire \txn_fifo_output_reg_n_0_[12] ;
  wire \txn_fifo_output_reg_n_0_[13] ;
  wire \txn_fifo_output_reg_n_0_[14] ;
  wire \txn_fifo_output_reg_n_0_[15] ;
  wire \txn_fifo_output_reg_n_0_[16] ;
  wire \txn_fifo_output_reg_n_0_[17] ;
  wire \txn_fifo_output_reg_n_0_[44] ;
  wire \txn_fifo_output_reg_n_0_[45] ;
  wire \txn_fifo_output_reg_n_0_[46] ;
  wire \txn_fifo_output_reg_n_0_[47] ;
  wire \txn_fifo_reg_n_0_[0][0] ;
  wire \txn_fifo_reg_n_0_[0][11] ;
  wire \txn_fifo_reg_n_0_[0][12] ;
  wire \txn_fifo_reg_n_0_[0][13] ;
  wire \txn_fifo_reg_n_0_[0][14] ;
  wire \txn_fifo_reg_n_0_[0][15] ;
  wire \txn_fifo_reg_n_0_[0][16] ;
  wire \txn_fifo_reg_n_0_[0][17] ;
  wire \txn_fifo_reg_n_0_[0][1] ;
  wire \txn_fifo_reg_n_0_[0][24] ;
  wire \txn_fifo_reg_n_0_[0][25] ;
  wire \txn_fifo_reg_n_0_[0][26] ;
  wire \txn_fifo_reg_n_0_[0][27] ;
  wire \txn_fifo_reg_n_0_[0][28] ;
  wire \txn_fifo_reg_n_0_[0][29] ;
  wire \txn_fifo_reg_n_0_[0][2] ;
  wire \txn_fifo_reg_n_0_[0][30] ;
  wire \txn_fifo_reg_n_0_[0][31] ;
  wire \txn_fifo_reg_n_0_[0][32] ;
  wire \txn_fifo_reg_n_0_[0][33] ;
  wire \txn_fifo_reg_n_0_[0][34] ;
  wire \txn_fifo_reg_n_0_[0][35] ;
  wire \txn_fifo_reg_n_0_[0][36] ;
  wire \txn_fifo_reg_n_0_[0][37] ;
  wire \txn_fifo_reg_n_0_[0][38] ;
  wire \txn_fifo_reg_n_0_[0][39] ;
  wire \txn_fifo_reg_n_0_[0][40] ;
  wire \txn_fifo_reg_n_0_[0][44] ;
  wire \txn_fifo_reg_n_0_[0][45] ;
  wire \txn_fifo_reg_n_0_[0][46] ;
  wire \txn_fifo_reg_n_0_[0][47] ;
  wire \txn_fifo_reg_n_0_[1][0] ;
  wire \txn_fifo_reg_n_0_[1][11] ;
  wire \txn_fifo_reg_n_0_[1][12] ;
  wire \txn_fifo_reg_n_0_[1][13] ;
  wire \txn_fifo_reg_n_0_[1][14] ;
  wire \txn_fifo_reg_n_0_[1][15] ;
  wire \txn_fifo_reg_n_0_[1][16] ;
  wire \txn_fifo_reg_n_0_[1][17] ;
  wire \txn_fifo_reg_n_0_[1][1] ;
  wire \txn_fifo_reg_n_0_[1][24] ;
  wire \txn_fifo_reg_n_0_[1][25] ;
  wire \txn_fifo_reg_n_0_[1][26] ;
  wire \txn_fifo_reg_n_0_[1][27] ;
  wire \txn_fifo_reg_n_0_[1][28] ;
  wire \txn_fifo_reg_n_0_[1][29] ;
  wire \txn_fifo_reg_n_0_[1][2] ;
  wire \txn_fifo_reg_n_0_[1][30] ;
  wire \txn_fifo_reg_n_0_[1][31] ;
  wire \txn_fifo_reg_n_0_[1][32] ;
  wire \txn_fifo_reg_n_0_[1][33] ;
  wire \txn_fifo_reg_n_0_[1][34] ;
  wire \txn_fifo_reg_n_0_[1][35] ;
  wire \txn_fifo_reg_n_0_[1][36] ;
  wire \txn_fifo_reg_n_0_[1][37] ;
  wire \txn_fifo_reg_n_0_[1][38] ;
  wire \txn_fifo_reg_n_0_[1][39] ;
  wire \txn_fifo_reg_n_0_[1][40] ;
  wire \txn_fifo_reg_n_0_[1][44] ;
  wire \txn_fifo_reg_n_0_[1][45] ;
  wire \txn_fifo_reg_n_0_[1][46] ;
  wire \txn_fifo_reg_n_0_[1][47] ;
  wire \txn_fifo_reg_n_0_[2][0] ;
  wire \txn_fifo_reg_n_0_[2][11] ;
  wire \txn_fifo_reg_n_0_[2][12] ;
  wire \txn_fifo_reg_n_0_[2][13] ;
  wire \txn_fifo_reg_n_0_[2][14] ;
  wire \txn_fifo_reg_n_0_[2][15] ;
  wire \txn_fifo_reg_n_0_[2][16] ;
  wire \txn_fifo_reg_n_0_[2][17] ;
  wire \txn_fifo_reg_n_0_[2][1] ;
  wire \txn_fifo_reg_n_0_[2][24] ;
  wire \txn_fifo_reg_n_0_[2][25] ;
  wire \txn_fifo_reg_n_0_[2][26] ;
  wire \txn_fifo_reg_n_0_[2][27] ;
  wire \txn_fifo_reg_n_0_[2][28] ;
  wire \txn_fifo_reg_n_0_[2][29] ;
  wire \txn_fifo_reg_n_0_[2][2] ;
  wire \txn_fifo_reg_n_0_[2][30] ;
  wire \txn_fifo_reg_n_0_[2][31] ;
  wire \txn_fifo_reg_n_0_[2][32] ;
  wire \txn_fifo_reg_n_0_[2][33] ;
  wire \txn_fifo_reg_n_0_[2][34] ;
  wire \txn_fifo_reg_n_0_[2][35] ;
  wire \txn_fifo_reg_n_0_[2][36] ;
  wire \txn_fifo_reg_n_0_[2][37] ;
  wire \txn_fifo_reg_n_0_[2][38] ;
  wire \txn_fifo_reg_n_0_[2][39] ;
  wire \txn_fifo_reg_n_0_[2][40] ;
  wire \txn_fifo_reg_n_0_[2][44] ;
  wire \txn_fifo_reg_n_0_[2][45] ;
  wire \txn_fifo_reg_n_0_[2][46] ;
  wire \txn_fifo_reg_n_0_[2][47] ;
  wire \txn_fifo_reg_n_0_[3][0] ;
  wire \txn_fifo_reg_n_0_[3][11] ;
  wire \txn_fifo_reg_n_0_[3][12] ;
  wire \txn_fifo_reg_n_0_[3][13] ;
  wire \txn_fifo_reg_n_0_[3][14] ;
  wire \txn_fifo_reg_n_0_[3][15] ;
  wire \txn_fifo_reg_n_0_[3][16] ;
  wire \txn_fifo_reg_n_0_[3][17] ;
  wire \txn_fifo_reg_n_0_[3][1] ;
  wire \txn_fifo_reg_n_0_[3][24] ;
  wire \txn_fifo_reg_n_0_[3][25] ;
  wire \txn_fifo_reg_n_0_[3][26] ;
  wire \txn_fifo_reg_n_0_[3][27] ;
  wire \txn_fifo_reg_n_0_[3][28] ;
  wire \txn_fifo_reg_n_0_[3][29] ;
  wire \txn_fifo_reg_n_0_[3][2] ;
  wire \txn_fifo_reg_n_0_[3][30] ;
  wire \txn_fifo_reg_n_0_[3][31] ;
  wire \txn_fifo_reg_n_0_[3][32] ;
  wire \txn_fifo_reg_n_0_[3][33] ;
  wire \txn_fifo_reg_n_0_[3][34] ;
  wire \txn_fifo_reg_n_0_[3][35] ;
  wire \txn_fifo_reg_n_0_[3][36] ;
  wire \txn_fifo_reg_n_0_[3][37] ;
  wire \txn_fifo_reg_n_0_[3][38] ;
  wire \txn_fifo_reg_n_0_[3][39] ;
  wire \txn_fifo_reg_n_0_[3][40] ;
  wire \txn_fifo_reg_n_0_[3][44] ;
  wire \txn_fifo_reg_n_0_[3][45] ;
  wire \txn_fifo_reg_n_0_[3][46] ;
  wire \txn_fifo_reg_n_0_[3][47] ;
  wire \txn_fifo_rptr[0]_i_1__2_n_0 ;
  wire \txn_fifo_rptr[1]_i_1__2_n_0 ;
  wire \txn_fifo_rptr_reg_n_0_[0] ;
  wire \txn_fifo_rptr_reg_n_0_[1] ;
  wire \txn_fifo_wptr[0]_i_1__1_n_0 ;
  wire \txn_fifo_wptr[1]_i_1__1_n_0 ;
  wire \txn_fifo_wptr_reg[0]_0 ;
  wire \txn_fifo_wptr_reg_n_0_[0] ;
  wire \txn_fifo_wptr_reg_n_0_[1] ;
  wire [2:0]\um_wait_cntr[2]_i_3 ;
  wire underfill_done_reg_0;
  wire underfill_done_reg_n_0;
  wire useAdr;
  wire wrReqR_i_1__0_n_0;
  wire wrReqR_i_2__0_n_0;
  wire wrReqR_i_3__2_n_0;
  wire wrReqR_i_4__2_n_0;
  wire wrReqR_reg_0;
  wire [7:6]\NLW_issue_cas3_inferred__0/i__carry_CO_UNCONNECTED ;
  wire [7:0]\NLW_issue_cas3_inferred__0/i__carry_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h00000000FFFFFD55)) 
    \FSM_sequential_grSt[0]_i_1__2 
       (.I0(\FSM_sequential_grSt[1]_i_4_n_0 ),
        .I1(\issue_cas3_inferred__0/i__carry_n_2 ),
        .I2(\FSM_sequential_grSt[0]_i_2__2_n_0 ),
        .I3(\FSM_sequential_grSt[2]_i_5__0_n_0 ),
        .I4(\FSM_sequential_grSt[2]_i_6__1_n_0 ),
        .I5(\FSM_sequential_grSt[0]_i_3_n_0 ),
        .O(\FSM_sequential_grSt[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    \FSM_sequential_grSt[0]_i_2__2 
       (.I0(\pageInfo_reg_n_0_[0][0][2][0] ),
        .I1(\pageInfo_reg_n_0_[0][0][0][0] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][0] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][3][0] ),
        .O(\FSM_sequential_grSt[0]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2559" *) 
  LUT5 #(
    .INIT(32'hCFAA00AA)) 
    \FSM_sequential_grSt[0]_i_3 
       (.I0(grSt[2]),
        .I1(cas_fifo_full_reg_n_0),
        .I2(actReqR_reg_1),
        .I3(grSt[1]),
        .I4(grSt[0]),
        .O(\FSM_sequential_grSt[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEEEEEFE)) 
    \FSM_sequential_grSt[1]_i_1__2 
       (.I0(\FSM_sequential_grSt[1]_i_2__1_n_0 ),
        .I1(\FSM_sequential_grSt[1]_i_3__2_n_0 ),
        .I2(\FSM_sequential_grSt[1]_i_4_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_5__0_n_0 ),
        .I4(\FSM_sequential_grSt[2]_i_5__0_n_0 ),
        .I5(\FSM_sequential_grSt[1]_i_6__0_n_0 ),
        .O(\FSM_sequential_grSt[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2559" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_grSt[1]_i_2__1 
       (.I0(grSt[2]),
        .I1(grSt[1]),
        .O(\FSM_sequential_grSt[1]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2551" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \FSM_sequential_grSt[1]_i_3__2 
       (.I0(grSt[2]),
        .I1(grSt[1]),
        .I2(grSt[0]),
        .O(\FSM_sequential_grSt[1]_i_3__2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_grSt[1]_i_4 
       (.I0(grSt[0]),
        .I1(\FSM_sequential_grSt[2]_i_8_n_0 ),
        .O(\FSM_sequential_grSt[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2546" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_sequential_grSt[1]_i_5__0 
       (.I0(\cmdBankP[1]_i_2__1_n_0 ),
        .I1(\FSM_sequential_grSt[0]_i_2__2_n_0 ),
        .I2(\issue_cas3_inferred__0/i__carry_n_2 ),
        .O(\FSM_sequential_grSt[1]_i_5__0_n_0 ));
  LUT5 #(
    .INIT(32'h002A0000)) 
    \FSM_sequential_grSt[1]_i_6__0 
       (.I0(actReqR_i_2__1_n_0),
        .I1(ref_req_dly4),
        .I2(txn_fifo_empty_reg_n_0),
        .I3(grSt[2]),
        .I4(grSt[0]),
        .O(\FSM_sequential_grSt[1]_i_6__0_n_0 ));
  LUT6 #(
    .INIT(64'h22F2FFFF22F222F2)) 
    \FSM_sequential_grSt[2]_i_10__0 
       (.I0(\cas_pend_fifo_reg_n_0_[0][47] ),
        .I1(\cmdBankP[1]_i_4_n_0 ),
        .I2(\cas_pend_fifo_reg_n_0_[2][47] ),
        .I3(\cmdBankP[1]_i_6_n_0 ),
        .I4(\cmdBankP[1]_i_5_n_0 ),
        .I5(\cas_pend_fifo_reg_n_0_[1][47] ),
        .O(\FSM_sequential_grSt[2]_i_10__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF7F00FFFF)) 
    \FSM_sequential_grSt[2]_i_11__0 
       (.I0(accept_reg_0),
        .I1(\txn_fifo_wptr_reg[0]_0 ),
        .I2(useAdr),
        .I3(txn_fifo_empty_reg_n_0),
        .I4(\issue_cas3_inferred__0/i__carry_n_2 ),
        .I5(cas_fifo_full_reg_n_0),
        .O(\FSM_sequential_grSt[2]_i_11__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0020002F)) 
    \FSM_sequential_grSt[2]_i_1__2 
       (.I0(trp_cntr_is_zero_reg_n_0),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .I4(cas_fifo_full_reg_n_0),
        .I5(\FSM_sequential_grSt[2]_i_3__2_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'h8A)) 
    \FSM_sequential_grSt[2]_i_2__1 
       (.I0(\FSM_sequential_grSt[2]_i_4_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_5__0_n_0 ),
        .I2(\FSM_sequential_grSt[2]_i_6__1_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'hFF88FCCC0088FCCC)) 
    \FSM_sequential_grSt[2]_i_3__2 
       (.I0(actReqR_reg_1),
        .I1(grSt[0]),
        .I2(preReqR_reg_1),
        .I3(grSt[2]),
        .I4(grSt[1]),
        .I5(\FSM_sequential_grSt[2]_i_7__2_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_3__2_n_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    \FSM_sequential_grSt[2]_i_4 
       (.I0(grSt[0]),
        .I1(grSt[2]),
        .I2(\FSM_sequential_grSt[2]_i_8_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_sequential_grSt[2]_i_5__0 
       (.I0(\cmdBankP[1]_i_2__1_n_0 ),
        .I1(\FSM_sequential_grSt[2]_i_9__0_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_5__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2546" *) 
  LUT5 #(
    .INIT(32'h3FFF3F2A)) 
    \FSM_sequential_grSt[2]_i_6__1 
       (.I0(\issue_cas3_inferred__0/i__carry_n_2 ),
        .I1(ref_req_dly4),
        .I2(txn_fifo_empty_reg_n_0),
        .I3(\cmdBankP[1]_i_2__1_n_0 ),
        .I4(\FSM_sequential_grSt[0]_i_2__2_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_6__1_n_0 ));
  LUT5 #(
    .INIT(32'h00005D00)) 
    \FSM_sequential_grSt[2]_i_7__2 
       (.I0(txn_fifo_empty_reg_n_0),
        .I1(bank[0]),
        .I2(group),
        .I3(\txn_fifo_wptr_reg[0]_0 ),
        .I4(ref_req_dly4),
        .O(\FSM_sequential_grSt[2]_i_7__2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAABBAB)) 
    \FSM_sequential_grSt[2]_i_8 
       (.I0(grSt[1]),
        .I1(\FSM_sequential_grSt[2]_i_10__0_n_0 ),
        .I2(\cas_pend_fifo_reg_n_0_[3][47] ),
        .I3(\cmdBankP[1]_i_3__1_n_0 ),
        .I4(\FSM_sequential_grSt[2]_i_11__0_n_0 ),
        .I5(\FSM_sequential_grSt[0]_i_2__2_n_0 ),
        .O(\FSM_sequential_grSt[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0F5533000F5533FF)) 
    \FSM_sequential_grSt[2]_i_9__0 
       (.I0(\pageInfo_reg_n_0_[0][0][2][1] ),
        .I1(\pageInfo_reg_n_0_[0][0][1][1] ),
        .I2(\pageInfo_reg_n_0_[0][0][3][1] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][1] ),
        .O(\FSM_sequential_grSt[2]_i_9__0_n_0 ));
  (* FSM_ENCODED_STATES = "grACT:010,grPREWAIT:100,grAUTOPRE:101,grACTWAIT:011,grIDLE:110,grCASFSM:000,grACCEPT:001" *) 
  FDRE \FSM_sequential_grSt_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\FSM_sequential_grSt[2]_i_1__2_n_0 ),
        .D(\FSM_sequential_grSt[0]_i_1__2_n_0 ),
        .Q(grSt[0]),
        .R(rst_r1));
  (* FSM_ENCODED_STATES = "grACT:010,grPREWAIT:100,grAUTOPRE:101,grACTWAIT:011,grIDLE:110,grCASFSM:000,grACCEPT:001" *) 
  FDSE \FSM_sequential_grSt_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\FSM_sequential_grSt[2]_i_1__2_n_0 ),
        .D(\FSM_sequential_grSt[1]_i_1__2_n_0 ),
        .Q(grSt[1]),
        .S(rst_r1));
  (* FSM_ENCODED_STATES = "grACT:010,grPREWAIT:100,grAUTOPRE:101,grACTWAIT:011,grIDLE:110,grCASFSM:000,grACCEPT:001" *) 
  FDSE \FSM_sequential_grSt_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\FSM_sequential_grSt[2]_i_1__2_n_0 ),
        .D(\FSM_sequential_grSt[2]_i_2__1_n_0 ),
        .Q(grSt[2]),
        .S(rst_r1));
  LUT6 #(
    .INIT(64'h1111111100001000)) 
    \FSM_sequential_gr_cas_state[0]_i_1__0 
       (.I0(gr_cas_state[2]),
        .I1(gr_cas_state[0]),
        .I2(\FSM_sequential_gr_cas_state[2]_i_3__2_n_0 ),
        .I3(\FSM_sequential_gr_cas_state[2]_i_6__0_n_0 ),
        .I4(\FSM_sequential_gr_cas_state[2]_i_5__2_n_0 ),
        .I5(gr_cas_state[1]),
        .O(gr_cas_state_nxt[0]));
  (* SOFT_HLUTNM = "soft_lutpair2575" *) 
  LUT3 #(
    .INIT(8'h12)) 
    \FSM_sequential_gr_cas_state[1]_i_1__0 
       (.I0(gr_cas_state[0]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[1]),
        .O(gr_cas_state_nxt[1]));
  LUT6 #(
    .INIT(64'h3300550F33FF550F)) 
    \FSM_sequential_gr_cas_state[2]_i_10 
       (.I0(\cas_pend_fifo_reg_n_0_[2][45] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][45] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][45] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][45] ),
        .O(\FSM_sequential_gr_cas_state[2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0030F0EE0030F022)) 
    \FSM_sequential_gr_cas_state[2]_i_1__0 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_3__2_n_0 ),
        .I1(gr_cas_state[1]),
        .I2(clrReq15_out),
        .I3(gr_cas_state[0]),
        .I4(gr_cas_state[2]),
        .I5(underfill_done_reg_n_0),
        .O(\FSM_sequential_gr_cas_state[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0100010101010101)) 
    \FSM_sequential_gr_cas_state[2]_i_2__0 
       (.I0(gr_cas_state[0]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[1]),
        .I3(\FSM_sequential_gr_cas_state[2]_i_5__2_n_0 ),
        .I4(\FSM_sequential_gr_cas_state[2]_i_6__0_n_0 ),
        .I5(\FSM_sequential_gr_cas_state[2]_i_3__2_n_0 ),
        .O(gr_cas_state_nxt[2]));
  LUT3 #(
    .INIT(8'h07)) 
    \FSM_sequential_gr_cas_state[2]_i_3__2 
       (.I0(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\FSM_sequential_gr_cas_state[2]_i_7__2_n_0 ),
        .O(\FSM_sequential_gr_cas_state[2]_i_3__2_n_0 ));
  LUT5 #(
    .INIT(32'hCFFFCAFA)) 
    \FSM_sequential_gr_cas_state[2]_i_5__2 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_8__1_n_0 ),
        .I1(\txn_fifo_output_reg_n_0_[46] ),
        .I2(cas_fifo_empty_reg_n_0),
        .I3(\txn_fifo_output_reg_n_0_[44] ),
        .I4(\FSM_sequential_gr_cas_state[2]_i_9__0_n_0 ),
        .O(\FSM_sequential_gr_cas_state[2]_i_5__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2607" *) 
  LUT3 #(
    .INIT(8'hC5)) 
    \FSM_sequential_gr_cas_state[2]_i_6__0 
       (.I0(\FSM_sequential_gr_cas_state[2]_i_10_n_0 ),
        .I1(\txn_fifo_output_reg_n_0_[45] ),
        .I2(cas_fifo_empty_reg_n_0),
        .O(\FSM_sequential_gr_cas_state[2]_i_6__0_n_0 ));
  LUT6 #(
    .INIT(64'h553355330F000FFF)) 
    \FSM_sequential_gr_cas_state[2]_i_7__2 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I1(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I3(\cmd_bank_cas[0]_i_2__0_n_0 ),
        .I4(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I5(\cmd_bank_cas[1]_i_1__0_n_0 ),
        .O(\FSM_sequential_gr_cas_state[2]_i_7__2_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \FSM_sequential_gr_cas_state[2]_i_8__1 
       (.I0(\cas_pend_fifo_reg_n_0_[2][46] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][46] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][46] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_pend_fifo_reg_n_0_[0][46] ),
        .O(\FSM_sequential_gr_cas_state[2]_i_8__1_n_0 ));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    \FSM_sequential_gr_cas_state[2]_i_9__0 
       (.I0(\cas_pend_fifo_reg_n_0_[1][44] ),
        .I1(\cas_pend_fifo_reg_n_0_[0][44] ),
        .I2(\cas_pend_fifo_reg_n_0_[2][44] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[3][44] ),
        .O(\FSM_sequential_gr_cas_state[2]_i_9__0_n_0 ));
  (* FSM_ENCODED_STATES = "CAS_IDLE:000,RMW_DATAWAIT:010,RMW_WRWAIT:011,CAS_WAIT:100,RMW_RDWAIT:001" *) 
  FDRE \FSM_sequential_gr_cas_state_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\FSM_sequential_gr_cas_state[2]_i_1__0_n_0 ),
        .D(gr_cas_state_nxt[0]),
        .Q(gr_cas_state[0]),
        .R(rst_r1));
  (* FSM_ENCODED_STATES = "CAS_IDLE:000,RMW_DATAWAIT:010,RMW_WRWAIT:011,CAS_WAIT:100,RMW_RDWAIT:001" *) 
  FDRE \FSM_sequential_gr_cas_state_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\FSM_sequential_gr_cas_state[2]_i_1__0_n_0 ),
        .D(gr_cas_state_nxt[1]),
        .Q(gr_cas_state[1]),
        .R(rst_r1));
  (* FSM_ENCODED_STATES = "CAS_IDLE:000,RMW_DATAWAIT:010,RMW_WRWAIT:011,CAS_WAIT:100,RMW_RDWAIT:001" *) 
  FDRE \FSM_sequential_gr_cas_state_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\FSM_sequential_gr_cas_state[2]_i_1__0_n_0 ),
        .D(gr_cas_state_nxt[2]),
        .Q(gr_cas_state[2]),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h00009699)) 
    accept_i_1__0
       (.I0(\txn_fifo_rptr_reg_n_0_[1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(accept_reg_1),
        .O(grAccept_ns));
  FDRE accept_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(grAccept_ns),
        .Q(accept_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFFFF10)) 
    actReqR_i_1__2
       (.I0(\FSM_sequential_grSt[2]_i_5__0_n_0 ),
        .I1(actReqR_i_2__1_n_0),
        .I2(\FSM_sequential_grSt[2]_i_4_n_0 ),
        .I3(actReqR_reg_0),
        .I4(actReqR_i_3__1_n_0),
        .I5(actReqR_reg_1),
        .O(actReqR_i_1__2_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    actReqR_i_2__1
       (.I0(\cmdBankP[1]_i_2__1_n_0 ),
        .I1(\FSM_sequential_grSt[0]_i_2__2_n_0 ),
        .O(actReqR_i_2__1_n_0));
  LUT4 #(
    .INIT(16'h0020)) 
    actReqR_i_3__1
       (.I0(trp_cntr_is_zero_reg_n_0),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .O(actReqR_i_3__1_n_0));
  FDRE actReqR_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(actReqR_i_1__2_n_0),
        .Q(actReqR_reg_0),
        .R(rst_r1));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][0][0]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .I3(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .O(\ap_cntr[0][0][0][0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2550" *) 
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][0][1]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[1] ),
        .I1(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .I4(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .O(\ap_cntr[0][0][0][1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][0][2]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[2] ),
        .I1(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .O(\ap_cntr[0][0][0][2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][0][3]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .I4(\ap_cntr[0][0][0][4]_i_2__0_n_0 ),
        .I5(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .O(\ap_cntr[0][0][0][3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFB0004)) 
    \ap_cntr[0][0][0][4]_i_1__0 
       (.I0(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .I1(\ap_cntr[0][0][0][4]_i_2__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I3(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .I4(\ap_cntr_reg_n_0_[0][0][0][4] ),
        .I5(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .O(\ap_cntr[0][0][0][4]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2550" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][0][4]_i_2__0 
       (.I0(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .I1(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .O(\ap_cntr[0][0][0][4]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000820)) 
    \ap_cntr[0][0][0][4]_i_3__0 
       (.I0(cmdAP),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(gr_cas_state[1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\cmd_bank_cas_reg[1]_0 [1]),
        .O(\ap_cntr[0][0][0][4]_i_3__0_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][1][0]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .O(\ap_cntr[0][0][1][0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2549" *) 
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][1][1]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[1] ),
        .I1(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .O(\ap_cntr[0][0][1][1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][1][2]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[2] ),
        .I1(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .O(\ap_cntr[0][0][1][2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][1][3]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .I4(\ap_cntr[0][0][1][4]_i_2__0_n_0 ),
        .I5(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .O(\ap_cntr[0][0][1][3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFB0004)) 
    \ap_cntr[0][0][1][4]_i_1__0 
       (.I0(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .I1(\ap_cntr[0][0][1][4]_i_2__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .I3(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .I4(\ap_cntr_reg_n_0_[0][0][1][4] ),
        .I5(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .O(\ap_cntr[0][0][1][4]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2549" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][1][4]_i_2__0 
       (.I0(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .I1(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .O(\ap_cntr[0][0][1][4]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000008200000)) 
    \ap_cntr[0][0][1][4]_i_3__0 
       (.I0(cmdAP),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(gr_cas_state[1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\cmd_bank_cas_reg[1]_0 [1]),
        .O(\ap_cntr[0][0][1][4]_i_3__0_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][2][0]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .O(\ap_cntr[0][0][2][0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2548" *) 
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][2][1]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[1] ),
        .I1(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .I4(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .O(\ap_cntr[0][0][2][1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][2][2]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[2] ),
        .I1(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .O(\ap_cntr[0][0][2][2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B88BB8B8)) 
    \ap_cntr[0][0][2][3]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][2][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .I4(\ap_cntr[0][0][2][4]_i_3_n_0 ),
        .I5(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .O(\ap_cntr[0][0][2][3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h5555554500000010)) 
    \ap_cntr[0][0][2][4]_i_1__0 
       (.I0(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I1(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .I2(\ap_cntr[0][0][2][4]_i_3_n_0 ),
        .I3(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][2][3] ),
        .I5(\ap_cntr_reg_n_0_[0][0][2][4] ),
        .O(\ap_cntr[0][0][2][4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000008200000)) 
    \ap_cntr[0][0][2][4]_i_2__0 
       (.I0(cmdAP),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(gr_cas_state[1]),
        .I4(\cmd_bank_cas_reg[1]_0 [1]),
        .I5(\cmd_bank_cas_reg[1]_0 [0]),
        .O(\ap_cntr[0][0][2][4]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2548" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \ap_cntr[0][0][2][4]_i_3 
       (.I0(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .I1(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .O(\ap_cntr[0][0][2][4]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hB88B)) 
    \ap_cntr[0][0][3][0]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[0] ),
        .I1(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .O(\ap_cntr[0][0][3][0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hB8B8B88B)) 
    \ap_cntr[0][0][3][1]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[1] ),
        .I1(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I3(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .I4(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .O(\ap_cntr[0][0][3][1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hB8B8B8B8B8B8B88B)) 
    \ap_cntr[0][0][3][2]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[2] ),
        .I1(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .I3(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I4(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .O(\ap_cntr[0][0][3][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2570" *) 
  LUT4 #(
    .INIT(16'h8BB8)) 
    \ap_cntr[0][0][3][3]_i_1__0 
       (.I0(\ap_load_value_reg_n_0_[3] ),
        .I1(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][3] ),
        .I3(\ap_cntr[0][0][3][4]_i_2__0_n_0 ),
        .O(\ap_cntr[0][0][3][3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2570" *) 
  LUT4 #(
    .INIT(16'h00D2)) 
    \ap_cntr[0][0][3][4]_i_1__0 
       (.I0(\ap_cntr[0][0][3][4]_i_2__0_n_0 ),
        .I1(\ap_cntr_reg_n_0_[0][0][3][3] ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][4] ),
        .I3(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .O(\ap_cntr[0][0][3][4]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \ap_cntr[0][0][3][4]_i_2__0 
       (.I0(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I1(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .I2(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .I3(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .O(\ap_cntr[0][0][3][4]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0820000000000000)) 
    \ap_cntr[0][0][3][4]_i_3__0 
       (.I0(cmdAP),
        .I1(gr_cas_state[0]),
        .I2(gr_cas_state[2]),
        .I3(gr_cas_state[1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\cmd_bank_cas_reg[1]_0 [1]),
        .O(\ap_cntr[0][0][3][4]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_cntr_expired[0][0][0]_i_1__1 
       (.I0(\ap_cntr[0][0][0][2]_i_1__0_n_0 ),
        .I1(\ap_cntr[0][0][0][3]_i_1__0_n_0 ),
        .I2(\ap_cntr[0][0][0][4]_i_1__0_n_0 ),
        .I3(\ap_cntr[0][0][0][1]_i_1__0_n_0 ),
        .I4(\ap_cntr[0][0][0][0]_i_1__0_n_0 ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .O(\ap_cntr_expired[0][0][0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_cntr_expired[0][0][1]_i_1__1 
       (.I0(\ap_cntr[0][0][1][4]_i_1__0_n_0 ),
        .I1(\ap_cntr[0][0][1][1]_i_1__0_n_0 ),
        .I2(\ap_cntr[0][0][1][2]_i_1__0_n_0 ),
        .I3(\ap_cntr[0][0][1][3]_i_1__0_n_0 ),
        .I4(\ap_cntr[0][0][1][0]_i_1__0_n_0 ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .O(\ap_cntr_expired[0][0][1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_cntr_expired[0][0][2]_i_1__0 
       (.I0(\ap_cntr[0][0][2][1]_i_1__0_n_0 ),
        .I1(\ap_cntr[0][0][2][4]_i_1__0_n_0 ),
        .I2(\ap_cntr[0][0][2][0]_i_1__0_n_0 ),
        .I3(\ap_cntr[0][0][2][3]_i_1__0_n_0 ),
        .I4(\ap_cntr[0][0][2][2]_i_1__0_n_0 ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .O(\ap_cntr_expired[0][0][2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_cntr_expired[0][0][3]_i_1__0 
       (.I0(\ap_cntr[0][0][3][2]_i_1__0_n_0 ),
        .I1(\ap_cntr[0][0][3][4]_i_1__0_n_0 ),
        .I2(\ap_cntr[0][0][3][0]_i_1__0_n_0 ),
        .I3(\ap_cntr[0][0][3][3]_i_1__0_n_0 ),
        .I4(\ap_cntr[0][0][3][1]_i_1__0_n_0 ),
        .I5(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .O(\ap_cntr_expired[0][0][3]_i_1__0_n_0 ));
  FDRE \ap_cntr_expired_reg[0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_expired[0][0][0]_i_1__1_n_0 ),
        .Q(sel0__30),
        .R(1'b0));
  FDRE \ap_cntr_expired_reg[0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_expired[0][0][1]_i_1__1_n_0 ),
        .Q(sel0__26),
        .R(1'b0));
  FDRE \ap_cntr_expired_reg[0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_expired[0][0][2]_i_1__0_n_0 ),
        .Q(sel0__22),
        .R(1'b0));
  FDRE \ap_cntr_expired_reg[0][0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_expired[0][0][3]_i_1__0_n_0 ),
        .Q(sel0__18),
        .R(1'b0));
  FDRE \ap_cntr_reg[0][0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][0]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][1]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][2]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][3]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][0][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][0][4]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][0][4] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][0]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][1]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][2]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][3]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][1][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][1][4]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][1][4] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][0]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][1]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][2]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][3]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][3] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][2][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][2][4]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][2][4] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][0]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][1]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][2]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][3]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][3] ),
        .R(rst_r1));
  FDRE \ap_cntr_reg[0][0][3][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr[0][0][3][4]_i_1__0_n_0 ),
        .Q(\ap_cntr_reg_n_0_[0][0][3][4] ),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_zero[0][0][0]_i_1__0 
       (.I0(\ap_cntr[0][0][0][2]_i_1__0_n_0 ),
        .I1(\ap_cntr[0][0][0][3]_i_1__0_n_0 ),
        .I2(\ap_cntr[0][0][0][4]_i_1__0_n_0 ),
        .I3(\ap_cntr[0][0][0][1]_i_1__0_n_0 ),
        .I4(\ap_cntr[0][0][0][0]_i_1__0_n_0 ),
        .O(\ap_cntr_zero[0][0][0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_zero[0][0][1]_i_1__0 
       (.I0(\ap_cntr[0][0][1][4]_i_1__0_n_0 ),
        .I1(\ap_cntr[0][0][1][1]_i_1__0_n_0 ),
        .I2(\ap_cntr[0][0][1][2]_i_1__0_n_0 ),
        .I3(\ap_cntr[0][0][1][3]_i_1__0_n_0 ),
        .I4(\ap_cntr[0][0][1][0]_i_1__0_n_0 ),
        .O(\ap_cntr_zero[0][0][1]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_zero[0][0][2]_i_1__0 
       (.I0(\ap_cntr[0][0][2][1]_i_1__0_n_0 ),
        .I1(\ap_cntr[0][0][2][4]_i_1__0_n_0 ),
        .I2(\ap_cntr[0][0][2][0]_i_1__0_n_0 ),
        .I3(\ap_cntr[0][0][2][3]_i_1__0_n_0 ),
        .I4(\ap_cntr[0][0][2][2]_i_1__0_n_0 ),
        .O(\ap_cntr_zero[0][0][2]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \ap_cntr_zero[0][0][3]_i_1__0 
       (.I0(\ap_cntr[0][0][3][2]_i_1__0_n_0 ),
        .I1(\ap_cntr[0][0][3][4]_i_1__0_n_0 ),
        .I2(\ap_cntr[0][0][3][0]_i_1__0_n_0 ),
        .I3(\ap_cntr[0][0][3][3]_i_1__0_n_0 ),
        .I4(\ap_cntr[0][0][3][1]_i_1__0_n_0 ),
        .O(\ap_cntr_zero[0][0][3]_i_1__0_n_0 ));
  FDRE \ap_cntr_zero_reg[0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_zero[0][0][0]_i_1__0_n_0 ),
        .Q(\ap_cntr_zero_reg_n_0_[0][0][0] ),
        .R(rst_r1));
  FDRE \ap_cntr_zero_reg[0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_zero[0][0][1]_i_1__0_n_0 ),
        .Q(\ap_cntr_zero_reg_n_0_[0][0][1] ),
        .R(rst_r1));
  FDRE \ap_cntr_zero_reg[0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_zero[0][0][2]_i_1__0_n_0 ),
        .Q(\ap_cntr_zero_reg_n_0_[0][0][2] ),
        .R(rst_r1));
  FDRE \ap_cntr_zero_reg[0][0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_cntr_zero[0][0][3]_i_1__0_n_0 ),
        .Q(\ap_cntr_zero_reg_n_0_[0][0][3] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2609" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \ap_load_value[0]_i_1__0 
       (.I0(wrReqR_reg_0),
        .I1(\ap_load_value[0]_i_2__0_n_0 ),
        .I2(\ap_load_value[3]_i_3__0_n_0 ),
        .O(\ap_load_value[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0F0055330FFF5533)) 
    \ap_load_value[0]_i_2__0 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .I3(\cmd_bank_cas_reg[1]_0 [0]),
        .I4(\cmd_bank_cas_reg[1]_0 [1]),
        .I5(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .O(\ap_load_value[0]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2608" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    \ap_load_value[1]_i_1__0 
       (.I0(\ap_load_value[3]_i_2__0_n_0 ),
        .I1(\ap_load_value[3]_i_3__0_n_0 ),
        .I2(wrReqR_reg_0),
        .O(\ap_load_value[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2608" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \ap_load_value[2]_i_1__0 
       (.I0(\ap_load_value[3]_i_2__0_n_0 ),
        .I1(\ap_load_value[3]_i_3__0_n_0 ),
        .I2(wrReqR_reg_0),
        .O(\ap_load_value[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2609" *) 
  LUT3 #(
    .INIT(8'hF1)) 
    \ap_load_value[3]_i_1__0 
       (.I0(\ap_load_value[3]_i_2__0_n_0 ),
        .I1(\ap_load_value[3]_i_3__0_n_0 ),
        .I2(wrReqR_reg_0),
        .O(\ap_load_value[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0033550FFF33550F)) 
    \ap_load_value[3]_i_2__0 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .I3(\cmd_bank_cas_reg[1]_0 [0]),
        .I4(\cmd_bank_cas_reg[1]_0 [1]),
        .I5(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .O(\ap_load_value[3]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    \ap_load_value[3]_i_3__0 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .I3(\cmd_bank_cas_reg[1]_0 [1]),
        .I4(\cmd_bank_cas_reg[1]_0 [0]),
        .I5(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .O(\ap_load_value[3]_i_3__0_n_0 ));
  FDRE \ap_load_value_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_load_value[0]_i_1__0_n_0 ),
        .Q(\ap_load_value_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \ap_load_value_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_load_value[1]_i_1__0_n_0 ),
        .Q(\ap_load_value_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \ap_load_value_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_load_value[2]_i_1__0_n_0 ),
        .Q(\ap_load_value_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \ap_load_value_reg[3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\ap_load_value[3]_i_1__0_n_0 ),
        .Q(\ap_load_value_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2564" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][0]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[0][0] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][0]_0 ),
        .O(\buf_fifo[0][0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \buf_fifo[0][0]_i_3__0 
       (.I0(\buf_fifo_reg_n_0_[2][0] ),
        .I1(\buf_fifo_reg_n_0_[3][0] ),
        .I2(\buf_fifo_reg_n_0_[1][0] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[0][0] ),
        .O(\buf_fifo_reg[2][0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2566" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][1]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[0][1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][1]_0 ),
        .O(\buf_fifo[0][1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAFFF0CCAA00F0)) 
    \buf_fifo[0][1]_i_3__0 
       (.I0(\buf_fifo_reg_n_0_[2][1] ),
        .I1(\buf_fifo_reg_n_0_[3][1] ),
        .I2(\buf_fifo_reg_n_0_[0][1] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[1][1] ),
        .O(\buf_fifo_reg[2][1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2565" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][2]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[0][2] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][2]_0 ),
        .O(\buf_fifo[0][2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAFFF0CCAA00F0)) 
    \buf_fifo[0][2]_i_3__0 
       (.I0(\buf_fifo_reg_n_0_[2][2] ),
        .I1(\buf_fifo_reg_n_0_[3][2] ),
        .I2(\buf_fifo_reg_n_0_[0][2] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[1][2] ),
        .O(\buf_fifo_reg[2][2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2563" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][3]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[0][3] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][3]_0 ),
        .O(\buf_fifo[0][3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAFFF0CCAA00F0)) 
    \buf_fifo[0][3]_i_3__0 
       (.I0(\buf_fifo_reg_n_0_[2][3] ),
        .I1(\buf_fifo_reg_n_0_[3][3] ),
        .I2(\buf_fifo_reg_n_0_[0][3] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[1][3] ),
        .O(\buf_fifo_reg[2][3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2569" *) 
  LUT4 #(
    .INIT(16'hABA8)) 
    \buf_fifo[0][4]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[0][4] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][4]_0 ),
        .O(\buf_fifo[0][4]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    \buf_fifo[0][4]_i_3__0 
       (.I0(\buf_fifo_reg_n_0_[0][4] ),
        .I1(\buf_fifo_reg_n_0_[1][4] ),
        .I2(\buf_fifo_reg_n_0_[3][4] ),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .I5(\buf_fifo_reg_n_0_[2][4] ),
        .O(\buf_fifo_reg[0][4]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2564" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][0]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[1][0] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][0]_0 ),
        .O(\buf_fifo[1][0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2566" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][1]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[1][1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][1]_0 ),
        .O(\buf_fifo[1][1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2565" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][2]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[1][2] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][2]_0 ),
        .O(\buf_fifo[1][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2567" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][3]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[1][3] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][3]_0 ),
        .O(\buf_fifo[1][3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2569" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[1][4]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[1][4] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][4]_0 ),
        .O(\buf_fifo[1][4]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2560" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][0]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[2][0] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][0]_0 ),
        .O(\buf_fifo[2][0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2562" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][1]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[2][1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][1]_0 ),
        .O(\buf_fifo[2][1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2561" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][2]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[2][2] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][2]_0 ),
        .O(\buf_fifo[2][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2567" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][3]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[2][3] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][3]_0 ),
        .O(\buf_fifo[2][3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2568" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \buf_fifo[2][4]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[2][4] ),
        .I1(\txn_fifo_wptr_reg_n_0_[0] ),
        .I2(\txn_fifo_wptr_reg_n_0_[1] ),
        .I3(\buf_fifo_reg[1][4]_0 ),
        .O(\buf_fifo[2][4]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2560" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][0]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[3][0] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][0]_0 ),
        .O(\buf_fifo[3][0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2562" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][1]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[3][1] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][1]_0 ),
        .O(\buf_fifo[3][1]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2561" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][2]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[3][2] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][2]_0 ),
        .O(\buf_fifo[3][2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2563" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][3]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[3][3] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][3]_0 ),
        .O(\buf_fifo[3][3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2568" *) 
  LUT4 #(
    .INIT(16'hEA2A)) 
    \buf_fifo[3][4]_i_1__1 
       (.I0(\buf_fifo_reg_n_0_[3][4] ),
        .I1(\txn_fifo_wptr_reg_n_0_[1] ),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\buf_fifo_reg[1][4]_0 ),
        .O(\buf_fifo[3][4]_i_1__1_n_0 ));
  FDRE \buf_fifo_reg[0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[0][0]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][0] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[0][1]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][1] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[0][2]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][2] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[0][3]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][3] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[0][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[0][4]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[0][4] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[1][0]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][0] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[1][1]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][1] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[1][2]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][2] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[1][3]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][3] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[1][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[1][4]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[1][4] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[2][0]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][0] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[2][1]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][1] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[2][2]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][2] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[2][3]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][3] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[2][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[2][4]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[2][4] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[3][0]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][0] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[3][1]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][1] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[3][2]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][2] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[3][3]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][3] ),
        .R(1'b0));
  FDRE \buf_fifo_reg[3][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\buf_fifo[3][4]_i_1__1_n_0 ),
        .Q(\buf_fifo_reg_n_0_[3][4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][0]_i_1__1 
       (.I0(\buf_fifo[3][0]_i_1__1_n_0 ),
        .I1(\buf_fifo[2][0]_i_1__1_n_0 ),
        .I2(\buf_fifo[1][0]_i_1__1_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][0]_i_1__1_n_0 ),
        .O(\cas_dbuf_fifo[0][0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][1]_i_1__1 
       (.I0(\buf_fifo[3][1]_i_1__1_n_0 ),
        .I1(\buf_fifo[2][1]_i_1__1_n_0 ),
        .I2(\buf_fifo[1][1]_i_1__1_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][1]_i_1__1_n_0 ),
        .O(\cas_dbuf_fifo[0][1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][2]_i_1__1 
       (.I0(\buf_fifo[3][2]_i_1__1_n_0 ),
        .I1(\buf_fifo[2][2]_i_1__1_n_0 ),
        .I2(\buf_fifo[1][2]_i_1__1_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][2]_i_1__1_n_0 ),
        .O(\cas_dbuf_fifo[0][2]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFF0AACC00F0AA)) 
    \cas_dbuf_fifo[0][3]_i_1__1 
       (.I0(\buf_fifo[0][3]_i_1__1_n_0 ),
        .I1(\buf_fifo[3][3]_i_1__1_n_0 ),
        .I2(\buf_fifo[1][3]_i_1__1_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[2][3]_i_1__1_n_0 ),
        .O(\cas_dbuf_fifo[0][3]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    \cas_dbuf_fifo[0][4]_i_1__1 
       (.I0(\buf_fifo[3][4]_i_1__1_n_0 ),
        .I1(\buf_fifo[2][4]_i_1__1_n_0 ),
        .I2(\buf_fifo[1][4]_i_1__1_n_0 ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\buf_fifo[0][4]_i_1__1_n_0 ),
        .O(\cas_dbuf_fifo[0][4]_i_1__1_n_0 ));
  FDRE \cas_dbuf_fifo_reg[0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][0]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][0] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][1]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][1] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][2]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][2] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][3]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][3] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[0][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][4]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[0][4] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][0]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][0] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][1]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][1] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][2]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][2] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][3]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][3] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[1][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][4]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[1][4] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][0]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][0] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][1]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][1] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][2]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][2] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][3]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][3] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[2][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][4]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[2][4] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][0]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][0] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][1]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][1] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][2]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][2] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][3]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][3] ),
        .R(1'b0));
  FDRE \cas_dbuf_fifo_reg[3][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\cas_dbuf_fifo[0][4]_i_1__1_n_0 ),
        .Q(\cas_dbuf_fifo_reg_n_0_[3][4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8241241818248241)) 
    cas_fifo_empty_i_1__0
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_rptr_reg_n_0_[0] ),
        .I2(\cas_fifo_rptr[1]_i_2__0_n_0 ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_wptr_reg_n_0_[0] ),
        .I5(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .O(cas_fifo_empty_i_1__0_n_0));
  FDRE cas_fifo_empty_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(cas_fifo_empty_i_1__0_n_0),
        .Q(cas_fifo_empty_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h6966996966966966)) 
    cas_fifo_full_i_1__0
       (.I0(\cas_fifo_rptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[1] ),
        .I2(\cas_fifo_wptr_reg_n_0_[0] ),
        .I3(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I4(\cas_fifo_rptr[1]_i_2__0_n_0 ),
        .I5(\cas_fifo_rptr_reg_n_0_[0] ),
        .O(cas_fifo_full_i_1__0_n_0));
  FDRE cas_fifo_full_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(cas_fifo_full_i_1__0_n_0),
        .Q(cas_fifo_full_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h10FFFFFFEF000000)) 
    \cas_fifo_rptr[0]_i_1__0 
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[0]),
        .I3(\cas_fifo_rptr_reg[0]_0 ),
        .I4(tranSentC),
        .I5(\cas_fifo_rptr_reg_n_0_[0] ),
        .O(\cas_fifo_rptr[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2606" *) 
  LUT3 #(
    .INIT(8'h9A)) 
    \cas_fifo_rptr[1]_i_1__0 
       (.I0(\cas_fifo_rptr_reg_n_0_[1] ),
        .I1(\cas_fifo_rptr[1]_i_2__0_n_0 ),
        .I2(\cas_fifo_rptr_reg_n_0_[0] ),
        .O(\cas_fifo_rptr[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2547" *) 
  LUT5 #(
    .INIT(32'h10FFFFFF)) 
    \cas_fifo_rptr[1]_i_2__0 
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[0]),
        .I3(\cas_fifo_rptr_reg[0]_0 ),
        .I4(tranSentC),
        .O(\cas_fifo_rptr[1]_i_2__0_n_0 ));
  FDRE \cas_fifo_rptr_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_rptr[0]_i_1__0_n_0 ),
        .Q(\cas_fifo_rptr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cas_fifo_rptr_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_rptr[1]_i_1__0_n_0 ),
        .Q(\cas_fifo_rptr_reg_n_0_[1] ),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hFF01FF01FF010000)) 
    \cas_fifo_valid[0]_i_1__0 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr_reg_n_0_[1] ),
        .I2(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I3(\cas_fifo_valid_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr[1]_i_2__0_n_0 ),
        .I5(\cas_fifo_valid[0]_i_2__0_n_0 ),
        .O(\cas_fifo_valid[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2623" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \cas_fifo_valid[0]_i_2__0 
       (.I0(\cas_fifo_rptr_reg_n_0_[0] ),
        .I1(\cas_fifo_rptr_reg_n_0_[1] ),
        .O(\cas_fifo_valid[0]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFF04FF04FF040000)) 
    \cas_fifo_valid[1]_i_1__0 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .I2(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I3(\cas_fifo_valid_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr[1]_i_2__0_n_0 ),
        .I5(\cas_fifo_valid[1]_i_2__0_n_0 ),
        .O(\cas_fifo_valid[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2606" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \cas_fifo_valid[1]_i_2__0 
       (.I0(\cas_fifo_rptr_reg_n_0_[1] ),
        .I1(\cas_fifo_rptr_reg_n_0_[0] ),
        .O(\cas_fifo_valid[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFF04FF04FF040000)) 
    \cas_fifo_valid[2]_i_1__0 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr_reg_n_0_[1] ),
        .I2(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I3(\cas_fifo_valid_reg_n_0_[2] ),
        .I4(\cas_fifo_rptr[1]_i_2__0_n_0 ),
        .I5(\cas_fifo_valid[2]_i_2__0_n_0 ),
        .O(\cas_fifo_valid[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2623" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \cas_fifo_valid[2]_i_2__0 
       (.I0(\cas_fifo_rptr_reg_n_0_[0] ),
        .I1(\cas_fifo_rptr_reg_n_0_[1] ),
        .O(\cas_fifo_valid[2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFF08FF08FF080000)) 
    \cas_fifo_valid[3]_i_1__0 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr_reg_n_0_[1] ),
        .I2(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I3(\cas_fifo_valid_reg_n_0_[3] ),
        .I4(\cas_fifo_rptr[1]_i_2__0_n_0 ),
        .I5(\cas_fifo_valid[3]_i_2__0_n_0 ),
        .O(\cas_fifo_valid[3]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \cas_fifo_valid[3]_i_2__0 
       (.I0(\cas_fifo_rptr_reg_n_0_[0] ),
        .I1(\cas_fifo_rptr_reg_n_0_[1] ),
        .O(\cas_fifo_valid[3]_i_2__0_n_0 ));
  FDRE \cas_fifo_valid_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_valid[0]_i_1__0_n_0 ),
        .Q(\cas_fifo_valid_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cas_fifo_valid_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_valid[1]_i_1__0_n_0 ),
        .Q(\cas_fifo_valid_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \cas_fifo_valid_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_valid[2]_i_1__0_n_0 ),
        .Q(\cas_fifo_valid_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \cas_fifo_valid_reg[3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_valid[3]_i_1__0_n_0 ),
        .Q(\cas_fifo_valid_reg_n_0_[3] ),
        .R(rst_r1));
  LUT2 #(
    .INIT(4'h9)) 
    \cas_fifo_wptr[0]_i_1__2 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .O(\cas_fifo_wptr[0]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hD2)) 
    \cas_fifo_wptr[1]_i_1__2 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I2(\cas_fifo_wptr_reg_n_0_[1] ),
        .O(\cas_fifo_wptr[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDDCFCFFFFDEFE)) 
    \cas_fifo_wptr[1]_i_2__0 
       (.I0(grSt[0]),
        .I1(grSt[2]),
        .I2(grSt[1]),
        .I3(actReqR_reg_1),
        .I4(cas_fifo_full_reg_n_0),
        .I5(\cas_fifo_wptr[1]_i_3_n_0 ),
        .O(\cas_fifo_wptr[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000100000)) 
    \cas_fifo_wptr[1]_i_3 
       (.I0(\FSM_sequential_grSt[0]_i_2__2_n_0 ),
        .I1(cas_fifo_full_reg_n_0),
        .I2(\issue_cas3_inferred__0/i__carry_n_2 ),
        .I3(\cas_fifo_wptr[1]_i_4_n_0 ),
        .I4(\cas_fifo_wptr[1]_i_5_n_0 ),
        .I5(\FSM_sequential_grSt[2]_i_10__0_n_0 ),
        .O(\cas_fifo_wptr[1]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h2AAA)) 
    \cas_fifo_wptr[1]_i_4 
       (.I0(txn_fifo_empty_reg_n_0),
        .I1(useAdr),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(accept_reg_0),
        .O(\cas_fifo_wptr[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h6FFFFF6FFFFFFFFF)) 
    \cas_fifo_wptr[1]_i_5 
       (.I0(\cas_pend_fifo_reg_n_0_[3][1] ),
        .I1(Q[1]),
        .I2(\cas_fifo_valid_reg_n_0_[3] ),
        .I3(Q[0]),
        .I4(\cas_pend_fifo_reg_n_0_[3][0] ),
        .I5(\cas_pend_fifo_reg_n_0_[3][47] ),
        .O(\cas_fifo_wptr[1]_i_5_n_0 ));
  FDRE \cas_fifo_wptr_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_wptr[0]_i_1__2_n_0 ),
        .Q(\cas_fifo_wptr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cas_fifo_wptr_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cas_fifo_wptr[1]_i_1__2_n_0 ),
        .Q(\cas_fifo_wptr_reg_n_0_[1] ),
        .R(rst_r1));
  LUT2 #(
    .INIT(4'h1)) 
    \cas_pend_fifo[0][47]_i_1 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .O(\cas_pend_fifo[0][47]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cas_pend_fifo[1][47]_i_1 
       (.I0(\cas_fifo_wptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr_reg_n_0_[1] ),
        .O(\cas_pend_fifo[1][47]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \cas_pend_fifo[2][47]_i_1 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .O(\cas_pend_fifo[2][47]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \cas_pend_fifo[3][47]_i_1 
       (.I0(\cas_fifo_wptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr_reg_n_0_[0] ),
        .O(\cas_pend_fifo[3][47]_i_1_n_0 ));
  FDRE \cas_pend_fifo_reg[0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg_n_0_[0][0] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg_n_0_[0][1] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[0][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[0][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[0][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[0][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[0][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[0][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[0][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[0][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[0][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[0][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[0][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[0][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[0][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[0][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[0][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[0][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[0][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[0][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[0][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[0][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[0][47] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg_n_0_[1][0] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg_n_0_[1][1] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[1][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[1][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[1][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[1][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[1][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[1][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[1][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[1][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[1][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[1][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[1][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[1][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[1][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[1][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[1][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[1][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[1][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[1][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[1][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[1][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[1][47] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg_n_0_[2][0] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg_n_0_[2][1] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[2][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[2][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[2][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[2][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[2][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[2][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[2][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[2][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[2][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[2][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[2][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[2][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[2][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[2][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[2][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[2][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[2][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[2][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[2][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[2][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[2][47] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[0]),
        .Q(\cas_pend_fifo_reg_n_0_[3][0] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[11] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][11] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[12] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][12] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[13] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][13] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[14] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][14] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[15] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][15] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[16] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][16] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[17] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][17] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[1]),
        .Q(\cas_pend_fifo_reg_n_0_[3][1] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[3]),
        .Q(\cas_pend_fifo_reg_n_0_[3][24] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[4]),
        .Q(\cas_pend_fifo_reg_n_0_[3][25] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[5]),
        .Q(\cas_pend_fifo_reg_n_0_[3][26] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[6]),
        .Q(\cas_pend_fifo_reg_n_0_[3][27] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[7]),
        .Q(\cas_pend_fifo_reg_n_0_[3][28] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[8]),
        .Q(\cas_pend_fifo_reg_n_0_[3][29] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[2]),
        .Q(\cas_pend_fifo_reg_n_0_[3][2] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[9]),
        .Q(\cas_pend_fifo_reg_n_0_[3][30] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[10]),
        .Q(\cas_pend_fifo_reg_n_0_[3][31] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[11]),
        .Q(\cas_pend_fifo_reg_n_0_[3][32] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[12]),
        .Q(\cas_pend_fifo_reg_n_0_[3][33] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[13]),
        .Q(\cas_pend_fifo_reg_n_0_[3][34] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[14]),
        .Q(\cas_pend_fifo_reg_n_0_[3][35] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[15]),
        .Q(\cas_pend_fifo_reg_n_0_[3][36] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[16]),
        .Q(\cas_pend_fifo_reg_n_0_[3][37] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[17]),
        .Q(\cas_pend_fifo_reg_n_0_[3][38] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[18]),
        .Q(\cas_pend_fifo_reg_n_0_[3][39] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(Q[19]),
        .Q(\cas_pend_fifo_reg_n_0_[3][40] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[44] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][44] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[45] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][45] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[46] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][46] ),
        .R(1'b0));
  FDRE \cas_pend_fifo_reg[3][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cas_pend_fifo[3][47]_i_1_n_0 ),
        .D(\txn_fifo_output_reg_n_0_[47] ),
        .Q(\cas_pend_fifo_reg_n_0_[3][47] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2607" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    cmdAP_i_1__0
       (.I0(\txn_fifo_output_reg_n_0_[47] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(cmdAP_i_2__0_n_0),
        .O(cmdAP_i_1__0_n_0));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    cmdAP_i_2__0
       (.I0(\cas_pend_fifo_reg_n_0_[2][47] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][47] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][47] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][47] ),
        .O(cmdAP_i_2__0_n_0));
  FDRE cmdAP_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(cmdAP_i_1__0_n_0),
        .Q(cmdAP),
        .R(rst_r1));
  LUT4 #(
    .INIT(16'h0100)) 
    \cmdBankP[1]_i_1__0 
       (.I0(\cmdBankP[1]_i_2__1_n_0 ),
        .I1(\FSM_sequential_grSt[0]_i_2__2_n_0 ),
        .I2(\issue_cas3_inferred__0/i__carry_n_2 ),
        .I3(\FSM_sequential_grSt[2]_i_4_n_0 ),
        .O(\cmdBankP[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h5DFFFFFFFFFFFFFF)) 
    \cmdBankP[1]_i_2__1 
       (.I0(\cmdBankP[1]_i_3__1_n_0 ),
        .I1(txn_fifo_empty_reg_n_0),
        .I2(txn_fifo_empty_i_2__1_n_0),
        .I3(\cmdBankP[1]_i_4_n_0 ),
        .I4(\cmdBankP[1]_i_5_n_0 ),
        .I5(\cmdBankP[1]_i_6_n_0 ),
        .O(\cmdBankP[1]_i_2__1_n_0 ));
  LUT5 #(
    .INIT(32'h6FFFFF6F)) 
    \cmdBankP[1]_i_3__1 
       (.I0(\cas_pend_fifo_reg_n_0_[3][0] ),
        .I1(Q[0]),
        .I2(\cas_fifo_valid_reg_n_0_[3] ),
        .I3(Q[1]),
        .I4(\cas_pend_fifo_reg_n_0_[3][1] ),
        .O(\cmdBankP[1]_i_3__1_n_0 ));
  LUT5 #(
    .INIT(32'h6FFFFF6F)) 
    \cmdBankP[1]_i_4 
       (.I0(\cas_pend_fifo_reg_n_0_[0][0] ),
        .I1(Q[0]),
        .I2(\cas_fifo_valid_reg_n_0_[0] ),
        .I3(Q[1]),
        .I4(\cas_pend_fifo_reg_n_0_[0][1] ),
        .O(\cmdBankP[1]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h6FF6FFFF)) 
    \cmdBankP[1]_i_5 
       (.I0(Q[1]),
        .I1(\cas_pend_fifo_reg_n_0_[1][1] ),
        .I2(Q[0]),
        .I3(\cas_pend_fifo_reg_n_0_[1][0] ),
        .I4(\cas_fifo_valid_reg_n_0_[1] ),
        .O(\cmdBankP[1]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h6FFFFF6F)) 
    \cmdBankP[1]_i_6 
       (.I0(\cas_pend_fifo_reg_n_0_[2][0] ),
        .I1(Q[0]),
        .I2(\cas_fifo_valid_reg_n_0_[2] ),
        .I3(Q[1]),
        .I4(\cas_pend_fifo_reg_n_0_[2][1] ),
        .O(\cmdBankP[1]_i_6_n_0 ));
  FDRE \cmdBankP_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cmdBankP[1]_i_1__0_n_0 ),
        .D(Q[0]),
        .Q(\cmdBankP_reg[1]_0 [0]),
        .R(rst_r1));
  FDRE \cmdBankP_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cmdBankP[1]_i_1__0_n_0 ),
        .D(Q[1]),
        .Q(\cmdBankP_reg[1]_0 [1]),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdBuf[0]_i_1__0 
       (.I0(\cas_dbuf_fifo_reg_n_0_[2][0] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[3][0] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[0][0] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[1][0] ),
        .O(\cmdBuf[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmdBuf[1]_i_1__0 
       (.I0(\cas_dbuf_fifo_reg_n_0_[2][1] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[3][1] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[1][1] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[0][1] ),
        .O(\cmdBuf[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAFFF0CCAA00F0CC)) 
    \cmdBuf[2]_i_1__0 
       (.I0(\cas_dbuf_fifo_reg_n_0_[3][2] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[0][2] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[2][2] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[1][2] ),
        .O(\cmdBuf[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFAACCF000AACCF0)) 
    \cmdBuf[3]_i_1__0 
       (.I0(\cas_dbuf_fifo_reg_n_0_[1][3] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[2][3] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[0][3] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[3][3] ),
        .O(\cmdBuf[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFAAF0CC00AAF0CC)) 
    \cmdBuf[4]_i_1__0 
       (.I0(\cas_dbuf_fifo_reg_n_0_[2][4] ),
        .I1(\cas_dbuf_fifo_reg_n_0_[0][4] ),
        .I2(\cas_dbuf_fifo_reg_n_0_[1][4] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_dbuf_fifo_reg_n_0_[3][4] ),
        .O(\cmdBuf[4]_i_1__0_n_0 ));
  FDRE \cmdBuf_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdBuf[0]_i_1__0_n_0 ),
        .Q(cmdBuf[0]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdBuf[1]_i_1__0_n_0 ),
        .Q(cmdBuf[1]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdBuf[2]_i_1__0_n_0 ),
        .Q(cmdBuf[2]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdBuf[3]_i_1__0_n_0 ),
        .Q(cmdBuf[3]),
        .R(rst_r1));
  FDRE \cmdBuf_reg[4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdBuf[4]_i_1__0_n_0 ),
        .Q(cmdBuf[4]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2610" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[3]_i_1__0 
       (.I0(\txn_fifo_output_reg_n_0_[11] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[3]_i_2__0_n_0 ),
        .O(\cmdCol[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[3]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][11] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][11] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][11] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][11] ),
        .O(\cmdCol[3]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2611" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[4]_i_1__0 
       (.I0(\txn_fifo_output_reg_n_0_[12] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[4]_i_2__0_n_0 ),
        .O(\cmdCol[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[4]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][12] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][12] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][12] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][12] ),
        .O(\cmdCol[4]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2611" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[5]_i_1__0 
       (.I0(\txn_fifo_output_reg_n_0_[13] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[5]_i_2__0_n_0 ),
        .O(\cmdCol[5]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmdCol[5]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][13] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][13] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][13] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_pend_fifo_reg_n_0_[0][13] ),
        .O(\cmdCol[5]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2612" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[6]_i_1__0 
       (.I0(\txn_fifo_output_reg_n_0_[14] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[6]_i_2__0_n_0 ),
        .O(\cmdCol[6]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[6]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][14] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][14] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][14] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][14] ),
        .O(\cmdCol[6]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2612" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[7]_i_1__0 
       (.I0(\txn_fifo_output_reg_n_0_[15] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[7]_i_2__0_n_0 ),
        .O(\cmdCol[7]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[7]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][15] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][15] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][15] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][15] ),
        .O(\cmdCol[7]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2613" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[8]_i_1__0 
       (.I0(\txn_fifo_output_reg_n_0_[16] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[8]_i_2__0_n_0 ),
        .O(\cmdCol[8]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmdCol[8]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][16] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][16] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][16] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_pend_fifo_reg_n_0_[0][16] ),
        .O(\cmdCol[8]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2613" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmdCol[9]_i_1__0 
       (.I0(\txn_fifo_output_reg_n_0_[17] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmdCol[9]_i_2__0_n_0 ),
        .O(\cmdCol[9]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmdCol[9]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][17] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][17] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][17] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][17] ),
        .O(\cmdCol[9]_i_2__0_n_0 ));
  FDRE \cmdCol_reg[3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[3]_i_1__0_n_0 ),
        .Q(\cmdCol_reg[9]_0 [0]),
        .R(rst_r1));
  FDRE \cmdCol_reg[4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[4]_i_1__0_n_0 ),
        .Q(\cmdCol_reg[9]_0 [1]),
        .R(rst_r1));
  FDRE \cmdCol_reg[5] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[5]_i_1__0_n_0 ),
        .Q(\cmdCol_reg[9]_0 [2]),
        .R(rst_r1));
  FDRE \cmdCol_reg[6] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[6]_i_1__0_n_0 ),
        .Q(\cmdCol_reg[9]_0 [3]),
        .R(rst_r1));
  FDRE \cmdCol_reg[7] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[7]_i_1__0_n_0 ),
        .Q(\cmdCol_reg[9]_0 [4]),
        .R(rst_r1));
  FDRE \cmdCol_reg[8] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[8]_i_1__0_n_0 ),
        .Q(\cmdCol_reg[9]_0 [5]),
        .R(rst_r1));
  FDRE \cmdCol_reg[9] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmdCol[9]_i_1__0_n_0 ),
        .Q(\cmdCol_reg[9]_0 [6]),
        .R(rst_r1));
  FDRE \cmdGroupP_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\cmdBankP[1]_i_1__0_n_0 ),
        .D(Q[2]),
        .Q(cmdGroupP),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'h0000FFFF00000200)) 
    cmdRmw_i_1__0
       (.I0(\FSM_sequential_gr_cas_state[2]_i_3__2_n_0 ),
        .I1(wrReqR_i_3__2_n_0),
        .I2(\FSM_sequential_gr_cas_state[2]_i_5__2_n_0 ),
        .I3(\FSM_sequential_gr_cas_state[2]_i_6__0_n_0 ),
        .I4(clrReq15_out),
        .I5(cmdRmw_reg_0),
        .O(cmdRmw_i_1__0_n_0));
  FDRE cmdRmw_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(cmdRmw_i_1__0_n_0),
        .Q(cmdRmw_reg_0),
        .R(rst_r1));
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_bank_cas[0]_i_1__0 
       (.I0(\cmd_bank_cas[0]_i_2__0_n_0 ),
        .O(\cmd_bank_cas[0]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h3A)) 
    \cmd_bank_cas[0]_i_2__0 
       (.I0(\cmd_bank_cas[0]_i_3_n_0 ),
        .I1(Q[0]),
        .I2(cas_fifo_empty_reg_n_0),
        .O(\cmd_bank_cas[0]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h00550F33FF550F33)) 
    \cmd_bank_cas[0]_i_3 
       (.I0(\cas_pend_fifo_reg_n_0_[1][0] ),
        .I1(\cas_pend_fifo_reg_n_0_[0][0] ),
        .I2(\cas_pend_fifo_reg_n_0_[2][0] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[3][0] ),
        .O(\cmd_bank_cas[0]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hC5)) 
    \cmd_bank_cas[1]_i_1__0 
       (.I0(\cmd_bank_cas[1]_i_2__0_n_0 ),
        .I1(Q[1]),
        .I2(cas_fifo_empty_reg_n_0),
        .O(\cmd_bank_cas[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h3300550F33FF550F)) 
    \cmd_bank_cas[1]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][1] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][1] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][1] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][1] ),
        .O(\cmd_bank_cas[1]_i_2__0_n_0 ));
  FDRE \cmd_bank_cas_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_bank_cas[0]_i_1__0_n_0 ),
        .Q(\cmd_bank_cas_reg[1]_0 [0]),
        .R(rst_r1));
  FDRE \cmd_bank_cas_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_bank_cas[1]_i_1__0_n_0 ),
        .Q(\cmd_bank_cas_reg[1]_0 [1]),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2610" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_group_cas[0]_i_1__0 
       (.I0(Q[2]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_group_cas[0]_i_2__0_n_0 ),
        .O(\cmd_group_cas[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_group_cas[0]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][2] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][2] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][2] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][2] ),
        .O(\cmd_group_cas[0]_i_2__0_n_0 ));
  FDRE \cmd_group_cas_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_group_cas[0]_i_1__0_n_0 ),
        .Q(cmd_group_cas),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2614" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[0]_i_1__0 
       (.I0(Q[3]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[0]_i_2__0_n_0 ),
        .O(\cmd_row_cas[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[0]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][24] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][24] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][24] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][24] ),
        .O(\cmd_row_cas[0]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2619" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[10]_i_1__0 
       (.I0(Q[13]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[10]_i_2__0_n_0 ),
        .O(\cmd_row_cas[10]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[10]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][34] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][34] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][34] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][34] ),
        .O(\cmd_row_cas[10]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2619" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[11]_i_1__0 
       (.I0(Q[14]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[11]_i_2__0_n_0 ),
        .O(\cmd_row_cas[11]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmd_row_cas[11]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][35] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][35] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][35] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_pend_fifo_reg_n_0_[0][35] ),
        .O(\cmd_row_cas[11]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2620" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[12]_i_1__0 
       (.I0(Q[15]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[12]_i_2__0_n_0 ),
        .O(\cmd_row_cas[12]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[12]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][36] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][36] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][36] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][36] ),
        .O(\cmd_row_cas[12]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2620" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[13]_i_1__0 
       (.I0(Q[16]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[13]_i_2__0_n_0 ),
        .O(\cmd_row_cas[13]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmd_row_cas[13]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][37] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][37] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][37] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_pend_fifo_reg_n_0_[0][37] ),
        .O(\cmd_row_cas[13]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2621" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[14]_i_1__0 
       (.I0(Q[17]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[14]_i_2__0_n_0 ),
        .O(\cmd_row_cas[14]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[14]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][38] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][38] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][38] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][38] ),
        .O(\cmd_row_cas[14]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2621" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[15]_i_1__0 
       (.I0(Q[18]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[15]_i_2__0_n_0 ),
        .O(\cmd_row_cas[15]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[15]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][39] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][39] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][39] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][39] ),
        .O(\cmd_row_cas[15]_i_2__0_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[16]_i_1__0 
       (.I0(Q[19]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[16]_i_2__0_n_0 ),
        .O(\cmd_row_cas[16]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmd_row_cas[16]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][40] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][40] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][40] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_pend_fifo_reg_n_0_[0][40] ),
        .O(\cmd_row_cas[16]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2614" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[1]_i_1__0 
       (.I0(Q[4]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[1]_i_2__0_n_0 ),
        .O(\cmd_row_cas[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[1]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][25] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][25] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][25] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][25] ),
        .O(\cmd_row_cas[1]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2615" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[2]_i_1__0 
       (.I0(Q[5]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[2]_i_2__0_n_0 ),
        .O(\cmd_row_cas[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[2]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][26] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][26] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][26] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][26] ),
        .O(\cmd_row_cas[2]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2615" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[3]_i_1__0 
       (.I0(Q[6]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[3]_i_2__0_n_0 ),
        .O(\cmd_row_cas[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[3]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][27] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][27] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][27] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][27] ),
        .O(\cmd_row_cas[3]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2616" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[4]_i_1__0 
       (.I0(Q[7]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[4]_i_2__0_n_0 ),
        .O(\cmd_row_cas[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[4]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][28] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][28] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][28] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][28] ),
        .O(\cmd_row_cas[4]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2616" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[5]_i_1__0 
       (.I0(Q[8]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[5]_i_2__0_n_0 ),
        .O(\cmd_row_cas[5]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[5]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][29] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][29] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][29] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][29] ),
        .O(\cmd_row_cas[5]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2617" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[6]_i_1__0 
       (.I0(Q[9]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[6]_i_2__0_n_0 ),
        .O(\cmd_row_cas[6]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmd_row_cas[6]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][30] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][30] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][30] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_pend_fifo_reg_n_0_[0][30] ),
        .O(\cmd_row_cas[6]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2617" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[7]_i_1__0 
       (.I0(Q[10]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[7]_i_2__0_n_0 ),
        .O(\cmd_row_cas[7]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    \cmd_row_cas[7]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][31] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][31] ),
        .I2(\cas_pend_fifo_reg_n_0_[1][31] ),
        .I3(\cas_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_rptr_reg_n_0_[1] ),
        .I5(\cas_pend_fifo_reg_n_0_[0][31] ),
        .O(\cmd_row_cas[7]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2618" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[8]_i_1__0 
       (.I0(Q[11]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[8]_i_2__0_n_0 ),
        .O(\cmd_row_cas[8]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[8]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][32] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][32] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][32] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][32] ),
        .O(\cmd_row_cas[8]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2618" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \cmd_row_cas[9]_i_1__0 
       (.I0(Q[12]),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\cmd_row_cas[9]_i_2__0_n_0 ),
        .O(\cmd_row_cas[9]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hCCFFAAF0CC00AAF0)) 
    \cmd_row_cas[9]_i_2__0 
       (.I0(\cas_pend_fifo_reg_n_0_[2][33] ),
        .I1(\cas_pend_fifo_reg_n_0_[3][33] ),
        .I2(\cas_pend_fifo_reg_n_0_[0][33] ),
        .I3(\cas_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_rptr_reg_n_0_[0] ),
        .I5(\cas_pend_fifo_reg_n_0_[1][33] ),
        .O(\cmd_row_cas[9]_i_2__0_n_0 ));
  FDRE \cmd_row_cas_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[0]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[10] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[10]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[10] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[11]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[11] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[12]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[12] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[13]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[13] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[14]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[14] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[15]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[15] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[16]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[16] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[1]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[2]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[3]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[3] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[4]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[4] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[5] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[5]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[5] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[6] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[6]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[6] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[7] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[7]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[7] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[8] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[8]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[8] ),
        .R(rst_r1));
  FDRE \cmd_row_cas_reg[9] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\cmd_row_cas[9]_i_1__0_n_0 ),
        .Q(\cmd_row_cas_reg_n_0_[9] ),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'hCCFFF0AACC00F0AA)) 
    i__carry_i_10__0
       (.I0(\pageInfo_reg_n_0_[0][0][0][15] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][15] ),
        .I2(\pageInfo_reg_n_0_[0][0][2][15] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\pageInfo_reg_n_0_[0][0][1][15] ),
        .O(i__carry_i_10__0_n_0));
  LUT6 #(
    .INIT(64'hCCFFF0AACC00F0AA)) 
    i__carry_i_11__0
       (.I0(\pageInfo_reg_n_0_[0][0][0][16] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][16] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][16] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][16] ),
        .O(i__carry_i_11__0_n_0));
  LUT6 #(
    .INIT(64'h55000F3355FF0F33)) 
    i__carry_i_12__0
       (.I0(\pageInfo_reg_n_0_[0][0][3][12] ),
        .I1(\pageInfo_reg_n_0_[0][0][0][12] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][12] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][12] ),
        .O(i__carry_i_12__0_n_0));
  LUT6 #(
    .INIT(64'hFFCCAAF000CCAAF0)) 
    i__carry_i_13__0
       (.I0(\pageInfo_reg_n_0_[0][0][1][11] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][11] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][11] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][3][11] ),
        .O(i__carry_i_13__0_n_0));
  LUT6 #(
    .INIT(64'hAACCFFF0AACC00F0)) 
    i__carry_i_14__0
       (.I0(\pageInfo_reg_n_0_[0][0][3][13] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][13] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][13] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][1][13] ),
        .O(i__carry_i_14__0_n_0));
  LUT6 #(
    .INIT(64'h0033550FFF33550F)) 
    i__carry_i_15__0
       (.I0(\pageInfo_reg_n_0_[0][0][1][10] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][10] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][10] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][3][10] ),
        .O(i__carry_i_15__0_n_0));
  LUT6 #(
    .INIT(64'hF0FFCCAAF000CCAA)) 
    i__carry_i_16__0
       (.I0(\pageInfo_reg_n_0_[0][0][0][8] ),
        .I1(\pageInfo_reg_n_0_[0][0][1][8] ),
        .I2(\pageInfo_reg_n_0_[0][0][3][8] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][8] ),
        .O(i__carry_i_16__0_n_0));
  LUT6 #(
    .INIT(64'hF0CCAAFFF0CCAA00)) 
    i__carry_i_17__0
       (.I0(\pageInfo_reg_n_0_[0][0][1][9] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][9] ),
        .I2(\pageInfo_reg_n_0_[0][0][3][9] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][9] ),
        .O(i__carry_i_17__0_n_0));
  LUT6 #(
    .INIT(64'h33550F0033550FFF)) 
    i__carry_i_18__0
       (.I0(\pageInfo_reg_n_0_[0][0][2][5] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][5] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][5] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][5] ),
        .O(i__carry_i_18__0_n_0));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    i__carry_i_19__0
       (.I0(\pageInfo_reg_n_0_[0][0][2][7] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][7] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][7] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][7] ),
        .O(i__carry_i_19__0_n_0));
  LUT4 #(
    .INIT(16'h6006)) 
    i__carry_i_1__0
       (.I0(i__carry_i_7__0_n_0),
        .I1(Q[18]),
        .I2(i__carry_i_8__0_n_0),
        .I3(Q[19]),
        .O(i__carry_i_1__0_n_0));
  LUT6 #(
    .INIT(64'hF0CCAAFFF0CCAA00)) 
    i__carry_i_20__0
       (.I0(\pageInfo_reg_n_0_[0][0][1][6] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][6] ),
        .I2(\pageInfo_reg_n_0_[0][0][3][6] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][6] ),
        .O(i__carry_i_20__0_n_0));
  LUT6 #(
    .INIT(64'h0033550FFF33550F)) 
    i__carry_i_21__0
       (.I0(\pageInfo_reg_n_0_[0][0][1][3] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][3] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][3] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][3][3] ),
        .O(i__carry_i_21__0_n_0));
  LUT6 #(
    .INIT(64'hCCAAF0FFCCAAF000)) 
    i__carry_i_22__0
       (.I0(\pageInfo_reg_n_0_[0][0][2][4] ),
        .I1(\pageInfo_reg_n_0_[0][0][3][4] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][4] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][4] ),
        .O(i__carry_i_22__0_n_0));
  LUT6 #(
    .INIT(64'hAACCFFF0AACC00F0)) 
    i__carry_i_23__0
       (.I0(\pageInfo_reg_n_0_[0][0][3][2] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][2] ),
        .I2(\pageInfo_reg_n_0_[0][0][0][2] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][1][2] ),
        .O(i__carry_i_23__0_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_2__0
       (.I0(i__carry_i_9__0_n_0),
        .I1(Q[15]),
        .I2(Q[16]),
        .I3(i__carry_i_10__0_n_0),
        .I4(Q[17]),
        .I5(i__carry_i_11__0_n_0),
        .O(i__carry_i_2__0_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_3__0
       (.I0(i__carry_i_12__0_n_0),
        .I1(Q[13]),
        .I2(Q[12]),
        .I3(i__carry_i_13__0_n_0),
        .I4(Q[14]),
        .I5(i__carry_i_14__0_n_0),
        .O(i__carry_i_3__0_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_4__0
       (.I0(i__carry_i_15__0_n_0),
        .I1(Q[11]),
        .I2(Q[9]),
        .I3(i__carry_i_16__0_n_0),
        .I4(Q[10]),
        .I5(i__carry_i_17__0_n_0),
        .O(i__carry_i_4__0_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_5__0
       (.I0(i__carry_i_18__0_n_0),
        .I1(Q[6]),
        .I2(Q[8]),
        .I3(i__carry_i_19__0_n_0),
        .I4(Q[7]),
        .I5(i__carry_i_20__0_n_0),
        .O(i__carry_i_5__0_n_0));
  LUT6 #(
    .INIT(64'h6006000000006006)) 
    i__carry_i_6__0
       (.I0(i__carry_i_21__0_n_0),
        .I1(Q[4]),
        .I2(Q[5]),
        .I3(i__carry_i_22__0_n_0),
        .I4(Q[3]),
        .I5(i__carry_i_23__0_n_0),
        .O(i__carry_i_6__0_n_0));
  LUT6 #(
    .INIT(64'h55000F3355FF0F33)) 
    i__carry_i_7__0
       (.I0(\pageInfo_reg_n_0_[0][0][3][17] ),
        .I1(\pageInfo_reg_n_0_[0][0][0][17] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][17] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][17] ),
        .O(i__carry_i_7__0_n_0));
  LUT6 #(
    .INIT(64'hAACCF0FFAACCF000)) 
    i__carry_i_8__0
       (.I0(\pageInfo_reg_n_0_[0][0][3][18] ),
        .I1(\pageInfo_reg_n_0_[0][0][2][18] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][18] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][0][18] ),
        .O(i__carry_i_8__0_n_0));
  LUT6 #(
    .INIT(64'h55000F3355FF0F33)) 
    i__carry_i_9__0
       (.I0(\pageInfo_reg_n_0_[0][0][3][14] ),
        .I1(\pageInfo_reg_n_0_[0][0][0][14] ),
        .I2(\pageInfo_reg_n_0_[0][0][1][14] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\pageInfo_reg_n_0_[0][0][2][14] ),
        .O(i__carry_i_9__0_n_0));
  CARRY8 \issue_cas3_inferred__0/i__carry 
       (.CI(1'b1),
        .CI_TOP(1'b0),
        .CO({\NLW_issue_cas3_inferred__0/i__carry_CO_UNCONNECTED [7:6],\issue_cas3_inferred__0/i__carry_n_2 ,\issue_cas3_inferred__0/i__carry_n_3 ,\issue_cas3_inferred__0/i__carry_n_4 ,\issue_cas3_inferred__0/i__carry_n_5 ,\issue_cas3_inferred__0/i__carry_n_6 ,\issue_cas3_inferred__0/i__carry_n_7 }),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O(\NLW_issue_cas3_inferred__0/i__carry_O_UNCONNECTED [7:0]),
        .S({1'b0,1'b0,i__carry_i_1__0_n_0,i__carry_i_2__0_n_0,i__carry_i_3__0_n_0,i__carry_i_4__0_n_0,i__carry_i_5__0_n_0,i__carry_i_6__0_n_0}));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \pageInfo[0][0][0][0]_i_1__0 
       (.I0(\pageInfo[0][0][0][0]_i_2__0_n_0 ),
        .I1(grSt[2]),
        .I2(grSt[0]),
        .I3(grSt[1]),
        .I4(\pageInfo[0][0][0][0]_i_3__0_n_0 ),
        .I5(sel0__30),
        .O(\pageInfo[0][0][0][0]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][0][0]_i_2__0 
       (.I0(rst_r1),
        .I1(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .O(\pageInfo[0][0][0][0]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2622" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \pageInfo[0][0][0][0]_i_3__0 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\pageInfo[0][0][0][0]_i_3__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][10]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[8] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[11]),
        .O(\pageInfo[0][0][0][10]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][11]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[9] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][0][11]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][12]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[10] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][0][12]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][13]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[11] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][0][13]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][14]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[12] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][0][14]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][15]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[13] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][0][15]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][16]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[14] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[17]),
        .O(\pageInfo[0][0][0][16]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][17]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[15] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][0][17]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][0][18]_i_1__0 
       (.I0(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I1(sel0__30),
        .I2(\pageInfo[0][0][3][18]_i_3__0_n_0 ),
        .I3(\trcd_cntr[0][0][0][2]_i_2__0_n_0 ),
        .O(\pageInfo[0][0][0][18]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][18]_i_2__0 
       (.I0(\cmd_row_cas_reg_n_0_[16] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][0][18]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][0][1]_i_1__0 
       (.I0(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][0][1]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][2]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[0] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[3]),
        .O(\pageInfo[0][0][0][2]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][3]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[1] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][0][3]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][4]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[2] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[5]),
        .O(\pageInfo[0][0][0][4]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][5]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[3] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[6]),
        .O(\pageInfo[0][0][0][5]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][6]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[4] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[7]),
        .O(\pageInfo[0][0][0][6]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][7]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[5] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[8]),
        .O(\pageInfo[0][0][0][7]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][8]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[6] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][0][8]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][0][9]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[7] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][0][4]_i_3__0_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][0][9]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
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       (.I0(\pageInfo[0][0][1][0]_i_2__0_n_0 ),
        .I1(grSt[2]),
        .I2(grSt[0]),
        .I3(grSt[1]),
        .I4(\pageInfo[0][0][1][0]_i_3__0_n_0 ),
        .I5(sel0__26),
        .O(\pageInfo[0][0][1][0]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][1][0]_i_2__0 
       (.I0(rst_r1),
        .I1(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .O(\pageInfo[0][0][1][0]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \pageInfo[0][0][1][0]_i_3__0 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\pageInfo[0][0][1][0]_i_3__0_n_0 ));
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    .INIT(16'h2320)) 
    \pageInfo[0][0][1][10]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[8] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[11]),
        .O(\pageInfo[0][0][1][10]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][11]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[9] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][1][11]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][12]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[10] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][1][12]_i_1__0_n_0 ));
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    .INIT(16'h2320)) 
    \pageInfo[0][0][1][13]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[11] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][1][13]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][14]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[12] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][1][14]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][15]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[13] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][1][15]_i_1__0_n_0 ));
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    .INIT(16'h2320)) 
    \pageInfo[0][0][1][16]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[14] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[17]),
        .O(\pageInfo[0][0][1][16]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][17]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[15] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][1][17]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][1][18]_i_1__0 
       (.I0(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I1(sel0__26),
        .I2(\pageInfo[0][0][3][18]_i_3__0_n_0 ),
        .I3(\trcd_cntr[0][0][1][2]_i_2__0_n_0 ),
        .O(\pageInfo[0][0][1][18]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][18]_i_2__0 
       (.I0(\cmd_row_cas_reg_n_0_[16] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][1][18]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][1][1]_i_1__0 
       (.I0(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][1][1]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][2]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[0] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[3]),
        .O(\pageInfo[0][0][1][2]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][3]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[1] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][1][3]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][4]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[2] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[5]),
        .O(\pageInfo[0][0][1][4]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][5]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[3] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[6]),
        .O(\pageInfo[0][0][1][5]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][6]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[4] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[7]),
        .O(\pageInfo[0][0][1][6]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][7]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[5] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[8]),
        .O(\pageInfo[0][0][1][7]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][8]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[6] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][1][8]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][1][9]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[7] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][1][4]_i_3__0_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][1][9]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h0010)) 
    \pageInfo[0][0][2][0]_i_1__0 
       (.I0(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I1(sel0__22),
        .I2(\trcd_cntr[0][0][2][2]_i_2__0_n_0 ),
        .I3(rst_r1),
        .O(\pageInfo[0][0][2][0]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][10]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[8] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[11]),
        .O(\pageInfo[0][0][2][10]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][11]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[9] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][2][11]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][12]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[10] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][2][12]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][13]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[11] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][2][13]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][14]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[12] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][2][14]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][15]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[13] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][2][15]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][16]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[14] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[17]),
        .O(\pageInfo[0][0][2][16]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][17]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[15] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][2][17]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][2][18]_i_1__0 
       (.I0(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I1(sel0__22),
        .I2(\pageInfo[0][0][3][18]_i_3__0_n_0 ),
        .I3(\trcd_cntr[0][0][2][2]_i_2__0_n_0 ),
        .O(\pageInfo[0][0][2][18]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][18]_i_2__0 
       (.I0(\cmd_row_cas_reg_n_0_[16] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][2][18]_i_2__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][2][1]_i_1__0 
       (.I0(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][2][1]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][2]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[0] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[3]),
        .O(\pageInfo[0][0][2][2]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][3]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[1] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][2][3]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][4]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[2] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[5]),
        .O(\pageInfo[0][0][2][4]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][5]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[3] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[6]),
        .O(\pageInfo[0][0][2][5]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][6]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[4] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[7]),
        .O(\pageInfo[0][0][2][6]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][7]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[5] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[8]),
        .O(\pageInfo[0][0][2][7]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][8]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[6] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][2][8]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][2][9]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[7] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][2][4]_i_2__0_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][2][9]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000002000)) 
    \pageInfo[0][0][3][0]_i_1__0 
       (.I0(\pageInfo[0][0][3][0]_i_2__0_n_0 ),
        .I1(grSt[2]),
        .I2(grSt[0]),
        .I3(grSt[1]),
        .I4(\trp_cntr[1]_i_2__0_n_0 ),
        .I5(sel0__18),
        .O(\pageInfo[0][0][3][0]_i_1__0_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \pageInfo[0][0][3][0]_i_2__0 
       (.I0(rst_r1),
        .I1(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .O(\pageInfo[0][0][3][0]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][10]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[8] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[11]),
        .O(\pageInfo[0][0][3][10]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][11]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[9] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[12]),
        .O(\pageInfo[0][0][3][11]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][12]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[10] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[13]),
        .O(\pageInfo[0][0][3][12]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][13]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[11] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[14]),
        .O(\pageInfo[0][0][3][13]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][14]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[12] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[15]),
        .O(\pageInfo[0][0][3][14]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][15]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[13] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[16]),
        .O(\pageInfo[0][0][3][15]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][16]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[14] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[17]),
        .O(\pageInfo[0][0][3][16]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][17]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[15] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[18]),
        .O(\pageInfo[0][0][3][17]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pageInfo[0][0][3][18]_i_1__0 
       (.I0(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I1(sel0__18),
        .I2(\pageInfo[0][0][3][18]_i_3__0_n_0 ),
        .I3(\trcd_cntr[0][0][3][2]_i_2__0_n_0 ),
        .O(\pageInfo[0][0][3][18]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][18]_i_2__0 
       (.I0(\cmd_row_cas_reg_n_0_[16] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[19]),
        .O(\pageInfo[0][0][3][18]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hAAEAAAAAAAAAAAAA)) 
    \pageInfo[0][0][3][18]_i_3__0 
       (.I0(rst_r1),
        .I1(refOK),
        .I2(refReq),
        .I3(grSt[0]),
        .I4(grSt[1]),
        .I5(grSt[2]),
        .O(\pageInfo[0][0][3][18]_i_3__0_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \pageInfo[0][0][3][1]_i_1__0 
       (.I0(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I1(rst_r1),
        .O(\pageInfo[0][0][3][1]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][2]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[0] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[3]),
        .O(\pageInfo[0][0][3][2]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][3]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[1] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[4]),
        .O(\pageInfo[0][0][3][3]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][4]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[2] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[5]),
        .O(\pageInfo[0][0][3][4]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][5]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[3] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[6]),
        .O(\pageInfo[0][0][3][5]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][6]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[4] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[7]),
        .O(\pageInfo[0][0][3][6]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][7]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[5] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[8]),
        .O(\pageInfo[0][0][3][7]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][8]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[6] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[9]),
        .O(\pageInfo[0][0][3][8]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h2320)) 
    \pageInfo[0][0][3][9]_i_1__0 
       (.I0(\cmd_row_cas_reg_n_0_[7] ),
        .I1(rst_r1),
        .I2(\ap_cntr[0][0][3][4]_i_3__0_n_0 ),
        .I3(Q[10]),
        .O(\pageInfo[0][0][3][9]_i_1__0_n_0 ));
  FDRE \pageInfo_reg[0][0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][0]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][0] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][10] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][10]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][10] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][11]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][11] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][12]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][12] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][13]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][13] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][14]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][14] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][15]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][15] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][16]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][16] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][17]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][17] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][18] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][18]_i_2__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][18] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][1]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][1] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][2]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][2] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][3]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][3] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][4]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][4] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][5] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][5]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][5] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][6] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][6]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][6] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][7] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][7]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][7] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][8] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][8]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][8] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][0][9] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][0][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][0][9]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][0][9] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][0]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][0] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][10] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][10]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][10] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][11]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][11] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][12]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][12] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][13]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][13] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][14]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][14] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][15]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][15] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][16]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][16] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][17]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][17] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][18] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][18]_i_2__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][18] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][1]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][1] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][2]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][2] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][3]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][3] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][4]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][4] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][5] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][5]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][5] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][6] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][6]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][6] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][7] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][7]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][7] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][8] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][8]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][8] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][1][9] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][1][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][1][9]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][1][9] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][0]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][0] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][10] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][10]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][10] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][11]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][11] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][12]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][12] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][13]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][13] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][14]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][14] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][15]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][15] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][16]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][16] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][17]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][17] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][18] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][18]_i_2__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][18] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][1]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][1] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][2]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][2] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][3]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][3] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][4]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][4] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][5] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][5]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][5] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][6] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][6]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][6] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][7] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][7]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][7] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][8] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][8]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][8] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][2][9] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][2][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][2][9]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][2][9] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][0]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][0] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][10] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][10]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][10] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][11]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][11] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][12]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][12] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][13]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][13] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][14]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][14] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][15]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][15] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][16]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][16] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][17]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][17] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][18] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][18]_i_2__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][18] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][1]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][1] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][2]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][2] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][3]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][3] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][4]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][4] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][5] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][5]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][5] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][6] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][6]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][6] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][7] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][7]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][7] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][8] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][8]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][8] ),
        .R(1'b0));
  FDRE \pageInfo_reg[0][0][3][9] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(\pageInfo[0][0][3][18]_i_1__0_n_0 ),
        .D(\pageInfo[0][0][3][9]_i_1__0_n_0 ),
        .Q(\pageInfo_reg_n_0_[0][0][3][9] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00F8)) 
    preReqR_i_1__1
       (.I0(\FSM_sequential_grSt[2]_i_4_n_0 ),
        .I1(\FSM_sequential_grSt[1]_i_5__0_n_0 ),
        .I2(preReqR_reg_0),
        .I3(preReqR_reg_1),
        .O(preReqR_i_1__1_n_0));
  FDRE preReqR_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(preReqR_i_1__1_n_0),
        .Q(preReqR_reg_0),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'h2222232222222222)) 
    rdReqR_i_1__0
       (.I0(rdReqR_reg_0),
        .I1(clrReq15_out),
        .I2(\FSM_sequential_gr_cas_state[2]_i_5__2_n_0 ),
        .I3(rdReqR_i_2__0_n_0),
        .I4(gr_cas_state[1]),
        .I5(\FSM_sequential_gr_cas_state[2]_i_3__2_n_0 ),
        .O(rdReqR_i_1__0_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    rdReqR_i_2__0
       (.I0(gr_cas_state[0]),
        .I1(gr_cas_state[2]),
        .O(rdReqR_i_2__0_n_0));
  FDRE rdReqR_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(rdReqR_i_1__0_n_0),
        .Q(rdReqR_reg_0),
        .R(rst_r1));
  LUT5 #(
    .INIT(32'h08000000)) 
    refOK_i_1__0
       (.I0(grSt[2]),
        .I1(grSt[1]),
        .I2(grSt[0]),
        .I3(cas_fifo_empty_reg_n_0),
        .I4(ref_req_dly4),
        .O(refOK_i_1__0_n_0));
  FDRE refOK_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(refOK_i_1__0_n_0),
        .Q(refOK),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8000)) 
    \refSt[3]_i_6 
       (.I0(refOK),
        .I1(\um_wait_cntr[2]_i_3 [0]),
        .I2(\um_wait_cntr[2]_i_3 [1]),
        .I3(\um_wait_cntr[2]_i_3 [2]),
        .O(refOK_reg_0));
  (* KEEP = "yes" *) 
  FDRE rst_r1_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(SR),
        .Q(rst_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2572" *) 
  LUT4 #(
    .INIT(16'hAAFE)) 
    \tras_cntr_rb[0][0][0][0]_i_1__0 
       (.I0(\trcd_cntr[0][0][0][2]_i_2__0_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .O(\tras_cntr_rb[0][0][0][0]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h00A4)) 
    \tras_cntr_rb[0][0][0][1]_i_1__0 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .I3(\trcd_cntr[0][0][0][2]_i_2__0_n_0 ),
        .O(\tras_cntr_rb[0][0][0][1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2572" *) 
  LUT4 #(
    .INIT(16'hEEEA)) 
    \tras_cntr_rb[0][0][0][2]_i_1__0 
       (.I0(\trcd_cntr[0][0][0][2]_i_2__0_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .O(\tras_cntr_rb[0][0][0][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2574" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][1][0]_i_1__0 
       (.I0(\trcd_cntr[0][0][1][2]_i_2__0_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .O(\tras_cntr_rb[0][0][1][0]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][1][1]_i_1__0 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .I3(\trcd_cntr[0][0][1][2]_i_2__0_n_0 ),
        .O(\tras_cntr_rb[0][0][1][1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2574" *) 
  LUT4 #(
    .INIT(16'hFEAA)) 
    \tras_cntr_rb[0][0][1][2]_i_1__0 
       (.I0(\trcd_cntr[0][0][1][2]_i_2__0_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .O(\tras_cntr_rb[0][0][1][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2571" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][2][0]_i_1__0 
       (.I0(\trcd_cntr[0][0][2][2]_i_2__0_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .O(\tras_cntr_rb[0][0][2][0]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][2][1]_i_1__0 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .I3(\trcd_cntr[0][0][2][2]_i_2__0_n_0 ),
        .O(\tras_cntr_rb[0][0][2][1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2571" *) 
  LUT4 #(
    .INIT(16'hFEAA)) 
    \tras_cntr_rb[0][0][2][2]_i_1__0 
       (.I0(\trcd_cntr[0][0][2][2]_i_2__0_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .O(\tras_cntr_rb[0][0][2][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2573" *) 
  LUT4 #(
    .INIT(16'hBBBA)) 
    \tras_cntr_rb[0][0][3][0]_i_1__0 
       (.I0(\trcd_cntr[0][0][3][2]_i_2__0_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .O(\tras_cntr_rb[0][0][3][0]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h00C2)) 
    \tras_cntr_rb[0][0][3][1]_i_1__0 
       (.I0(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .I3(\trcd_cntr[0][0][3][2]_i_2__0_n_0 ),
        .O(\tras_cntr_rb[0][0][3][1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2573" *) 
  LUT4 #(
    .INIT(16'hFEAA)) 
    \tras_cntr_rb[0][0][3][2]_i_1__0 
       (.I0(\trcd_cntr[0][0][3][2]_i_2__0_n_0 ),
        .I1(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .I2(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .I3(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .O(\tras_cntr_rb[0][0][3][2]_i_1__0_n_0 ));
  FDRE \tras_cntr_rb_reg[0][0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][0][0]_i_1__0_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][0][0] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][0][1]_i_1__0_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][0][1] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][0][2]_i_1__0_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][0][2] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][1][0]_i_1__0_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][1][0] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][1][1]_i_1__0_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][1][1] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][1][2]_i_1__0_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][1][2] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][2][0]_i_1__0_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][2][0] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][2][1]_i_1__0_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][2][1] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][2][2]_i_1__0_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][2][2] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][3][0]_i_1__0_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][3][0] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][3][1]_i_1__0_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][3][1] ),
        .R(rst_r1));
  FDRE \tras_cntr_rb_reg[0][0][3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\tras_cntr_rb[0][0][3][2]_i_1__0_n_0 ),
        .Q(\tras_cntr_rb_reg_n_0_[0][0][3][2] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2555" *) 
  LUT4 #(
    .INIT(16'hF44F)) 
    \trcd_cntr[0][0][0][0]_i_1__0 
       (.I0(actReqR_reg_1),
        .I1(\trcd_cntr[0][0][0][2]_i_2__0_n_0 ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .O(\trcd_cntr[0][0][0][0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2555" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][0][1]_i_1__0 
       (.I0(actReqR_reg_1),
        .I1(\trcd_cntr[0][0][0][2]_i_2__0_n_0 ),
        .I2(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .O(\trcd_cntr[0][0][0][1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][0][2]_i_1__0 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][0][2] ),
        .I4(actReqR_reg_1),
        .I5(\trcd_cntr[0][0][0][2]_i_2__0_n_0 ),
        .O(\trcd_cntr[0][0][0][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2552" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \trcd_cntr[0][0][0][2]_i_2__0 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\trcd_cntr[0][0][0][2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h5555555400000001)) 
    \trcd_cntr[0][0][0][3]_i_1__0 
       (.I0(\trcd_cntr_is_zero[0][0][0]_i_2__0_n_0 ),
        .I1(\trcd_cntr_reg_n_0_[0][0][0][2] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I4(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I5(\trcd_cntr_reg_n_0_[0][0][0][3] ),
        .O(\trcd_cntr[0][0][0][3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2557" *) 
  LUT4 #(
    .INIT(16'h99F9)) 
    \trcd_cntr[0][0][1][0]_i_1__0 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I2(\trcd_cntr[0][0][1][2]_i_2__0_n_0 ),
        .I3(actReqR_reg_1),
        .O(\trcd_cntr[0][0][1][0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2557" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][1][1]_i_1__0 
       (.I0(actReqR_reg_1),
        .I1(\trcd_cntr[0][0][1][2]_i_2__0_n_0 ),
        .I2(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .O(\trcd_cntr[0][0][1][1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][1][2]_i_1__0 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][1][2] ),
        .I4(actReqR_reg_1),
        .I5(\trcd_cntr[0][0][1][2]_i_2__0_n_0 ),
        .O(\trcd_cntr[0][0][1][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2553" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \trcd_cntr[0][0][1][2]_i_2__0 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\trcd_cntr[0][0][1][2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0001)) 
    \trcd_cntr[0][0][1][3]_i_1__0 
       (.I0(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][1][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][1][3] ),
        .I5(\trcd_cntr_is_zero[0][0][1]_i_2__0_n_0 ),
        .O(\trcd_cntr[0][0][1][3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2554" *) 
  LUT4 #(
    .INIT(16'h99F9)) 
    \trcd_cntr[0][0][2][0]_i_1__0 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I2(\trcd_cntr[0][0][2][2]_i_2__0_n_0 ),
        .I3(actReqR_reg_1),
        .O(\trcd_cntr[0][0][2][0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2554" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][2][1]_i_1__0 
       (.I0(actReqR_reg_1),
        .I1(\trcd_cntr[0][0][2][2]_i_2__0_n_0 ),
        .I2(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .O(\trcd_cntr[0][0][2][1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][2][2]_i_1__0 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][2][2] ),
        .I4(actReqR_reg_1),
        .I5(\trcd_cntr[0][0][2][2]_i_2__0_n_0 ),
        .O(\trcd_cntr[0][0][2][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2552" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    \trcd_cntr[0][0][2][2]_i_2__0 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\trcd_cntr[0][0][2][2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0001)) 
    \trcd_cntr[0][0][2][3]_i_1__0 
       (.I0(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][2][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][2][3] ),
        .I5(\trcd_cntr_is_zero[0][0][2]_i_2__0_n_0 ),
        .O(\trcd_cntr[0][0][2][3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2556" *) 
  LUT4 #(
    .INIT(16'hF44F)) 
    \trcd_cntr[0][0][3][0]_i_1__0 
       (.I0(actReqR_reg_1),
        .I1(\trcd_cntr[0][0][3][2]_i_2__0_n_0 ),
        .I2(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .O(\trcd_cntr[0][0][3][0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2556" *) 
  LUT5 #(
    .INIT(32'hFFF4444F)) 
    \trcd_cntr[0][0][3][1]_i_1__0 
       (.I0(actReqR_reg_1),
        .I1(\trcd_cntr[0][0][3][2]_i_2__0_n_0 ),
        .I2(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .I3(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .O(\trcd_cntr[0][0][3][1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFE010000FE01FE01)) 
    \trcd_cntr[0][0][3][2]_i_1__0 
       (.I0(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I1(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][3][2] ),
        .I4(actReqR_reg_1),
        .I5(\trcd_cntr[0][0][3][2]_i_2__0_n_0 ),
        .O(\trcd_cntr[0][0][3][2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2553" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    \trcd_cntr[0][0][3][2]_i_2__0 
       (.I0(grSt[2]),
        .I1(grSt[0]),
        .I2(grSt[1]),
        .I3(Q[0]),
        .I4(Q[1]),
        .O(\trcd_cntr[0][0][3][2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h5555555400000001)) 
    \trcd_cntr[0][0][3][3]_i_1__0 
       (.I0(\trcd_cntr_is_zero[0][0][3]_i_2__0_n_0 ),
        .I1(\trcd_cntr_reg_n_0_[0][0][3][2] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .I4(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I5(\trcd_cntr_reg_n_0_[0][0][3][3] ),
        .O(\trcd_cntr[0][0][3][3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000014)) 
    \trcd_cntr_is_zero[0][0][0]_i_1__0 
       (.I0(\trcd_cntr_reg_n_0_[0][0][0][3] ),
        .I1(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][0][2] ),
        .I5(\trcd_cntr_is_zero[0][0][0]_i_2__0_n_0 ),
        .O(\trcd_cntr_is_zero[0][0][0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    \trcd_cntr_is_zero[0][0][0]_i_2__0 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(actReqR_reg_1),
        .O(\trcd_cntr_is_zero[0][0][0]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010000)) 
    \trcd_cntr_is_zero[0][0][1]_i_1__0 
       (.I0(\trcd_cntr_is_zero[0][0][1]_i_2__0_n_0 ),
        .I1(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][1][3] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][1][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .I5(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .O(\trcd_cntr_is_zero[0][0][1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \trcd_cntr_is_zero[0][0][1]_i_2__0 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(actReqR_reg_1),
        .O(\trcd_cntr_is_zero[0][0][1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010000)) 
    \trcd_cntr_is_zero[0][0][2]_i_1__0 
       (.I0(\trcd_cntr_is_zero[0][0][2]_i_2__0_n_0 ),
        .I1(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][2][3] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][2][2] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .I5(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .O(\trcd_cntr_is_zero[0][0][2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \trcd_cntr_is_zero[0][0][2]_i_2__0 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(actReqR_reg_1),
        .O(\trcd_cntr_is_zero[0][0][2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000014)) 
    \trcd_cntr_is_zero[0][0][3]_i_1__0 
       (.I0(\trcd_cntr_reg_n_0_[0][0][3][3] ),
        .I1(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .I2(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .I3(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .I4(\trcd_cntr_reg_n_0_[0][0][3][2] ),
        .I5(\trcd_cntr_is_zero[0][0][3]_i_2__0_n_0 ),
        .O(\trcd_cntr_is_zero[0][0][3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \trcd_cntr_is_zero[0][0][3]_i_2__0 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(grSt[1]),
        .I3(grSt[0]),
        .I4(grSt[2]),
        .I5(actReqR_reg_1),
        .O(\trcd_cntr_is_zero[0][0][3]_i_2__0_n_0 ));
  FDRE \trcd_cntr_is_zero_reg[0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero[0][0][0]_i_1__0_n_0 ),
        .Q(\trcd_cntr_is_zero_reg_n_0_[0][0][0] ),
        .R(1'b0));
  FDRE \trcd_cntr_is_zero_reg[0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero[0][0][1]_i_1__0_n_0 ),
        .Q(\trcd_cntr_is_zero_reg_n_0_[0][0][1] ),
        .R(1'b0));
  FDRE \trcd_cntr_is_zero_reg[0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero[0][0][2]_i_1__0_n_0 ),
        .Q(\trcd_cntr_is_zero_reg_n_0_[0][0][2] ),
        .R(1'b0));
  FDRE \trcd_cntr_is_zero_reg[0][0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr_is_zero[0][0][3]_i_1__0_n_0 ),
        .Q(\trcd_cntr_is_zero_reg_n_0_[0][0][3] ),
        .R(1'b0));
  FDRE \trcd_cntr_reg[0][0][0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][0][0]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][0][0] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][0][1]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][0][1] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][0][2]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][0][2] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][0][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][0][3]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][0][3] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][1][0]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][1][0] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][1][1]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][1][1] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][1][2]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][1][2] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][1][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][1][3]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][1][3] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][2][0]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][2][0] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][2][1]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][2][1] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][2][2]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][2][2] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][2][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][2][3]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][2][3] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][3][0]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][3][0] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][3][1]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][3][1] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][3][2]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][3][2] ),
        .R(rst_r1));
  FDRE \trcd_cntr_reg[0][0][3][3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trcd_cntr[0][0][3][3]_i_1__0_n_0 ),
        .Q(\trcd_cntr_reg_n_0_[0][0][3][3] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2551" *) 
  LUT5 #(
    .INIT(32'h53555055)) 
    \trp_cntr[0]_i_1__0 
       (.I0(\trp_cntr_reg_n_0_[0] ),
        .I1(\trp_cntr[0]_i_2__0_n_0 ),
        .I2(grSt[1]),
        .I3(grSt[2]),
        .I4(grSt[0]),
        .O(\trp_cntr[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h3355000F3355FF0F)) 
    \trp_cntr[0]_i_2__0 
       (.I0(\ap_cntr_reg_n_0_[0][0][2][0] ),
        .I1(\ap_cntr_reg_n_0_[0][0][3][0] ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][0] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\ap_cntr_reg_n_0_[0][0][1][0] ),
        .O(\trp_cntr[0]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hF4FFF400F400F4FF)) 
    \trp_cntr[1]_i_1__0 
       (.I0(\trp_cntr[1]_i_2__0_n_0 ),
        .I1(\ap_cntr_reg_n_0_[0][0][3][1] ),
        .I2(\trp_cntr[1]_i_3__0_n_0 ),
        .I3(\FSM_sequential_grSt[1]_i_2__1_n_0 ),
        .I4(\trp_cntr_reg_n_0_[1] ),
        .I5(\trp_cntr_reg_n_0_[0] ),
        .O(\trp_cntr[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2622" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \trp_cntr[1]_i_2__0 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\trp_cntr[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0F0FAFAFFF0FCFCF)) 
    \trp_cntr[1]_i_3__0 
       (.I0(\ap_cntr_reg_n_0_[0][0][1][1] ),
        .I1(\ap_cntr_reg_n_0_[0][0][0][1] ),
        .I2(grSt[0]),
        .I3(\ap_cntr_reg_n_0_[0][0][2][1] ),
        .I4(Q[1]),
        .I5(Q[0]),
        .O(\trp_cntr[1]_i_3__0_n_0 ));
  LUT6 #(
    .INIT(64'h4F404F404F40404F)) 
    \trp_cntr[2]_i_1__0 
       (.I0(\trp_cntr[2]_i_2__0_n_0 ),
        .I1(grSt[0]),
        .I2(\FSM_sequential_grSt[1]_i_2__1_n_0 ),
        .I3(\trp_cntr_reg_n_0_[2] ),
        .I4(\trp_cntr_reg_n_0_[0] ),
        .I5(\trp_cntr_reg_n_0_[1] ),
        .O(\trp_cntr[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h3300550F33FF550F)) 
    \trp_cntr[2]_i_2__0 
       (.I0(\ap_cntr_reg_n_0_[0][0][1][2] ),
        .I1(\ap_cntr_reg_n_0_[0][0][3][2] ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][2] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\ap_cntr_reg_n_0_[0][0][2][2] ),
        .O(\trp_cntr[2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h0FF00FF044440FF0)) 
    \trp_cntr[3]_i_1__0 
       (.I0(\trp_cntr[3]_i_2__0_n_0 ),
        .I1(grSt[0]),
        .I2(\trp_cntr_reg_n_0_[3] ),
        .I3(\trp_cntr[3]_i_3__0_n_0 ),
        .I4(grSt[2]),
        .I5(grSt[1]),
        .O(\trp_cntr[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h0F0033550FFF3355)) 
    \trp_cntr[3]_i_2__0 
       (.I0(\ap_cntr_reg_n_0_[0][0][0][3] ),
        .I1(\ap_cntr_reg_n_0_[0][0][1][3] ),
        .I2(\ap_cntr_reg_n_0_[0][0][3][3] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\ap_cntr_reg_n_0_[0][0][2][3] ),
        .O(\trp_cntr[3]_i_2__0_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \trp_cntr[3]_i_3__0 
       (.I0(\trp_cntr_reg_n_0_[0] ),
        .I1(\trp_cntr_reg_n_0_[1] ),
        .I2(\trp_cntr_reg_n_0_[2] ),
        .O(\trp_cntr[3]_i_3__0_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \trp_cntr[4]_i_1__0 
       (.I0(\trp_cntr[4]_i_2__0_n_0 ),
        .O(\trp_cntr[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBB0F0FF00F)) 
    \trp_cntr[4]_i_2__0 
       (.I0(\trp_cntr[4]_i_3__0_n_0 ),
        .I1(grSt[0]),
        .I2(\trp_cntr_reg_n_0_[4] ),
        .I3(\trp_cntr[3]_i_3__0_n_0 ),
        .I4(\trp_cntr_reg_n_0_[3] ),
        .I5(\FSM_sequential_grSt[1]_i_2__1_n_0 ),
        .O(\trp_cntr[4]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h5533000F5533FF0F)) 
    \trp_cntr[4]_i_3__0 
       (.I0(\ap_cntr_reg_n_0_[0][0][3][4] ),
        .I1(\ap_cntr_reg_n_0_[0][0][2][4] ),
        .I2(\ap_cntr_reg_n_0_[0][0][0][4] ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\ap_cntr_reg_n_0_[0][0][1][4] ),
        .O(\trp_cntr[4]_i_3__0_n_0 ));
  LUT5 #(
    .INIT(32'h00000100)) 
    trp_cntr_is_zero_i_1__0
       (.I0(\trp_cntr[0]_i_1__0_n_0 ),
        .I1(\trp_cntr[1]_i_1__0_n_0 ),
        .I2(\trp_cntr[3]_i_1__0_n_0 ),
        .I3(\trp_cntr[4]_i_2__0_n_0 ),
        .I4(\trp_cntr[2]_i_1__0_n_0 ),
        .O(trp_cntr_is_zero_i_1__0_n_0));
  FDRE trp_cntr_is_zero_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(trp_cntr_is_zero_i_1__0_n_0),
        .Q(trp_cntr_is_zero_reg_n_0),
        .R(1'b0));
  FDRE \trp_cntr_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trp_cntr[0]_i_1__0_n_0 ),
        .Q(\trp_cntr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \trp_cntr_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trp_cntr[1]_i_1__0_n_0 ),
        .Q(\trp_cntr_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE \trp_cntr_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trp_cntr[2]_i_1__0_n_0 ),
        .Q(\trp_cntr_reg_n_0_[2] ),
        .R(rst_r1));
  FDRE \trp_cntr_reg[3] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trp_cntr[3]_i_1__0_n_0 ),
        .Q(\trp_cntr_reg_n_0_[3] ),
        .R(rst_r1));
  FDRE \trp_cntr_reg[4] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\trp_cntr[4]_i_1__0_n_0 ),
        .Q(\trp_cntr_reg_n_0_[4] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2583" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][0]_i_1__2 
       (.I0(bank[0]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][0] ),
        .O(\txn_fifo[0][0]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][11]_i_1__2 
       (.I0(col[0]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][11] ),
        .O(\txn_fifo[0][11]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][12]_i_1__2 
       (.I0(col[1]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][12] ),
        .O(\txn_fifo[0][12]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2582" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][13]_i_1__2 
       (.I0(col[2]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][13] ),
        .O(\txn_fifo[0][13]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][14]_i_1__2 
       (.I0(col[3]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][14] ),
        .O(\txn_fifo[0][14]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][15]_i_1__2 
       (.I0(col[4]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][15] ),
        .O(\txn_fifo[0][15]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2590" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][16]_i_1__2 
       (.I0(col[5]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][16] ),
        .O(\txn_fifo[0][16]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][17]_i_1__2 
       (.I0(col[6]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][17] ),
        .O(\txn_fifo[0][17]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2584" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][1]_i_1__2 
       (.I0(bank[1]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][1] ),
        .O(\txn_fifo[0][1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2591" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][24]_i_1__2 
       (.I0(row_mc_phy[0]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][24] ),
        .O(\txn_fifo[0][24]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][25]_i_1__2 
       (.I0(row_mc_phy[1]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][25] ),
        .O(\txn_fifo[0][25]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][26]_i_1__2 
       (.I0(row_mc_phy[2]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][26] ),
        .O(\txn_fifo[0][26]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2580" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][27]_i_1__2 
       (.I0(row_mc_phy[3]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][27] ),
        .O(\txn_fifo[0][27]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][28]_i_1__2 
       (.I0(row_mc_phy[4]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][28] ),
        .O(\txn_fifo[0][28]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][29]_i_1__2 
       (.I0(row_mc_phy[5]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][29] ),
        .O(\txn_fifo[0][29]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][2]_i_1__2 
       (.I0(group),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][2] ),
        .O(\txn_fifo[0][2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2596" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][30]_i_1__2 
       (.I0(row_mc_phy[6]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][30] ),
        .O(\txn_fifo[0][30]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2579" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][31]_i_1__2 
       (.I0(row_mc_phy[7]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][31] ),
        .O(\txn_fifo[0][31]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2597" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][32]_i_1__2 
       (.I0(row_mc_phy[8]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][32] ),
        .O(\txn_fifo[0][32]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][33]_i_1__2 
       (.I0(row_mc_phy[9]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][33] ),
        .O(\txn_fifo[0][33]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][34]_i_1__2 
       (.I0(row_mc_phy[10]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][34] ),
        .O(\txn_fifo[0][34]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2578" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][35]_i_1__2 
       (.I0(row_mc_phy[11]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][35] ),
        .O(\txn_fifo[0][35]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][36]_i_1__2 
       (.I0(row_mc_phy[12]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][36] ),
        .O(\txn_fifo[0][36]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][37]_i_1__2 
       (.I0(row_mc_phy[13]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][37] ),
        .O(\txn_fifo[0][37]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2602" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][38]_i_1__2 
       (.I0(row_mc_phy[14]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][38] ),
        .O(\txn_fifo[0][38]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2577" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][39]_i_1__2 
       (.I0(row_mc_phy[15]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][39] ),
        .O(\txn_fifo[0][39]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2603" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][40]_i_1__2 
       (.I0(row_mc_phy[16]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][40] ),
        .O(\txn_fifo[0][40]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][44]_i_1__2 
       (.I0(cmd[0]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][44] ),
        .O(\txn_fifo[0][44]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][45]_i_1__2 
       (.I0(cmd[1]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][45] ),
        .O(\txn_fifo[0][45]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2576" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][46]_i_1__2 
       (.I0(cmd[2]),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][46] ),
        .O(\txn_fifo[0][46]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][47]_i_1__2 
       (.I0(1'b0),
        .I1(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[0][47] ),
        .O(\txn_fifo[0][47]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h80001555)) 
    \txn_fifo[0][47]_i_2__1 
       (.I0(\txn_fifo_wptr_reg_n_0_[1] ),
        .I1(accept_reg_0),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(useAdr),
        .I4(\txn_fifo_wptr_reg_n_0_[0] ),
        .O(\txn_fifo[0][47]_i_2__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][0]_i_1__2 
       (.I0(bank[0]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][0] ),
        .O(\txn_fifo[1][0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2586" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][11]_i_1__2 
       (.I0(col[0]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][11] ),
        .O(\txn_fifo[1][11]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2587" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][12]_i_1__2 
       (.I0(col[1]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][12] ),
        .O(\txn_fifo[1][12]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][13]_i_1__2 
       (.I0(col[2]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][13] ),
        .O(\txn_fifo[1][13]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2588" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][14]_i_1__2 
       (.I0(col[3]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][14] ),
        .O(\txn_fifo[1][14]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2589" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][15]_i_1__2 
       (.I0(col[4]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][15] ),
        .O(\txn_fifo[1][15]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2590" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][16]_i_1__2 
       (.I0(col[5]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][16] ),
        .O(\txn_fifo[1][16]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][17]_i_1__2 
       (.I0(col[6]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][17] ),
        .O(\txn_fifo[1][17]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2584" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][1]_i_1__2 
       (.I0(bank[1]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][1] ),
        .O(\txn_fifo[1][1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2591" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][24]_i_1__2 
       (.I0(row_mc_phy[0]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][24] ),
        .O(\txn_fifo[1][24]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2592" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][25]_i_1__2 
       (.I0(row_mc_phy[1]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][25] ),
        .O(\txn_fifo[1][25]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2593" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][26]_i_1__2 
       (.I0(row_mc_phy[2]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][26] ),
        .O(\txn_fifo[1][26]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][27]_i_1__2 
       (.I0(row_mc_phy[3]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][27] ),
        .O(\txn_fifo[1][27]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2594" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][28]_i_1__2 
       (.I0(row_mc_phy[4]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][28] ),
        .O(\txn_fifo[1][28]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2595" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][29]_i_1__2 
       (.I0(row_mc_phy[5]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][29] ),
        .O(\txn_fifo[1][29]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2585" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][2]_i_1__2 
       (.I0(group),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][2] ),
        .O(\txn_fifo[1][2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2596" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][30]_i_1__2 
       (.I0(row_mc_phy[6]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][30] ),
        .O(\txn_fifo[1][30]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][31]_i_1__2 
       (.I0(row_mc_phy[7]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][31] ),
        .O(\txn_fifo[1][31]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2597" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][32]_i_1__2 
       (.I0(row_mc_phy[8]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][32] ),
        .O(\txn_fifo[1][32]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2598" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][33]_i_1__2 
       (.I0(row_mc_phy[9]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][33] ),
        .O(\txn_fifo[1][33]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2599" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][34]_i_1__2 
       (.I0(row_mc_phy[10]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][34] ),
        .O(\txn_fifo[1][34]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][35]_i_1__2 
       (.I0(row_mc_phy[11]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][35] ),
        .O(\txn_fifo[1][35]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2600" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][36]_i_1__2 
       (.I0(row_mc_phy[12]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][36] ),
        .O(\txn_fifo[1][36]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2601" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][37]_i_1__2 
       (.I0(row_mc_phy[13]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][37] ),
        .O(\txn_fifo[1][37]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2602" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][38]_i_1__2 
       (.I0(row_mc_phy[14]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][38] ),
        .O(\txn_fifo[1][38]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][39]_i_1__2 
       (.I0(row_mc_phy[15]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][39] ),
        .O(\txn_fifo[1][39]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2603" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][40]_i_1__2 
       (.I0(row_mc_phy[16]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][40] ),
        .O(\txn_fifo[1][40]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2604" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][44]_i_1__2 
       (.I0(cmd[0]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][44] ),
        .O(\txn_fifo[1][44]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2605" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][45]_i_1__2 
       (.I0(cmd[1]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][45] ),
        .O(\txn_fifo[1][45]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][46]_i_1__2 
       (.I0(cmd[2]),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][46] ),
        .O(\txn_fifo[1][46]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[1][47]_i_1__2 
       (.I0(1'b0),
        .I1(\txn_fifo[1][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[1][47] ),
        .O(\txn_fifo[1][47]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h00007F80)) 
    \txn_fifo[1][47]_i_2__1 
       (.I0(accept_reg_0),
        .I1(\txn_fifo_wptr_reg[0]_0 ),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .O(\txn_fifo[1][47]_i_2__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][0]_i_1__2 
       (.I0(bank[0]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][0] ),
        .O(\txn_fifo[2][0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2586" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][11]_i_1__2 
       (.I0(col[0]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][11] ),
        .O(\txn_fifo[2][11]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2587" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][12]_i_1__2 
       (.I0(col[1]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][12] ),
        .O(\txn_fifo[2][12]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][13]_i_1__2 
       (.I0(col[2]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][13] ),
        .O(\txn_fifo[2][13]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2588" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][14]_i_1__2 
       (.I0(col[3]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][14] ),
        .O(\txn_fifo[2][14]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2589" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][15]_i_1__2 
       (.I0(col[4]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][15] ),
        .O(\txn_fifo[2][15]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][16]_i_1__2 
       (.I0(col[5]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][16] ),
        .O(\txn_fifo[2][16]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2581" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][17]_i_1__2 
       (.I0(col[6]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][17] ),
        .O(\txn_fifo[2][17]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][1]_i_1__2 
       (.I0(bank[1]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][1] ),
        .O(\txn_fifo[2][1]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][24]_i_1__2 
       (.I0(row_mc_phy[0]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][24] ),
        .O(\txn_fifo[2][24]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2592" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][25]_i_1__2 
       (.I0(row_mc_phy[1]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][25] ),
        .O(\txn_fifo[2][25]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2593" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][26]_i_1__2 
       (.I0(row_mc_phy[2]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][26] ),
        .O(\txn_fifo[2][26]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][27]_i_1__2 
       (.I0(row_mc_phy[3]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][27] ),
        .O(\txn_fifo[2][27]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2594" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][28]_i_1__2 
       (.I0(row_mc_phy[4]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][28] ),
        .O(\txn_fifo[2][28]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2595" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][29]_i_1__2 
       (.I0(row_mc_phy[5]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][29] ),
        .O(\txn_fifo[2][29]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2585" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][2]_i_1__2 
       (.I0(group),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][2] ),
        .O(\txn_fifo[2][2]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][30]_i_1__2 
       (.I0(row_mc_phy[6]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][30] ),
        .O(\txn_fifo[2][30]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][31]_i_1__2 
       (.I0(row_mc_phy[7]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][31] ),
        .O(\txn_fifo[2][31]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][32]_i_1__2 
       (.I0(row_mc_phy[8]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][32] ),
        .O(\txn_fifo[2][32]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2598" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][33]_i_1__2 
       (.I0(row_mc_phy[9]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][33] ),
        .O(\txn_fifo[2][33]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2599" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][34]_i_1__2 
       (.I0(row_mc_phy[10]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][34] ),
        .O(\txn_fifo[2][34]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][35]_i_1__2 
       (.I0(row_mc_phy[11]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][35] ),
        .O(\txn_fifo[2][35]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2600" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][36]_i_1__2 
       (.I0(row_mc_phy[12]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][36] ),
        .O(\txn_fifo[2][36]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2601" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][37]_i_1__2 
       (.I0(row_mc_phy[13]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][37] ),
        .O(\txn_fifo[2][37]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][38]_i_1__2 
       (.I0(row_mc_phy[14]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][38] ),
        .O(\txn_fifo[2][38]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][39]_i_1__2 
       (.I0(row_mc_phy[15]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][39] ),
        .O(\txn_fifo[2][39]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][40]_i_1__2 
       (.I0(row_mc_phy[16]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][40] ),
        .O(\txn_fifo[2][40]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2604" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][44]_i_1__2 
       (.I0(cmd[0]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][44] ),
        .O(\txn_fifo[2][44]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2605" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][45]_i_1__2 
       (.I0(cmd[1]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][45] ),
        .O(\txn_fifo[2][45]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][46]_i_1__2 
       (.I0(cmd[2]),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][46] ),
        .O(\txn_fifo[2][46]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[2][47]_i_1__2 
       (.I0(1'b0),
        .I1(\txn_fifo[2][47]_i_2_n_0 ),
        .I2(\txn_fifo_reg_n_0_[2][47] ),
        .O(\txn_fifo[2][47]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h40002AAA)) 
    \txn_fifo[2][47]_i_2 
       (.I0(\txn_fifo_wptr_reg_n_0_[1] ),
        .I1(accept_reg_0),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(useAdr),
        .I4(\txn_fifo_wptr_reg_n_0_[0] ),
        .O(\txn_fifo[2][47]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2583" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][0]_i_1__2 
       (.I0(bank[0]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][0] ),
        .O(\txn_fifo[3][0]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][11]_i_1__2 
       (.I0(col[0]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][11] ),
        .O(\txn_fifo[3][11]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][12]_i_1__2 
       (.I0(col[1]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][12] ),
        .O(\txn_fifo[3][12]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2582" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][13]_i_1__2 
       (.I0(col[2]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][13] ),
        .O(\txn_fifo[3][13]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][14]_i_1__2 
       (.I0(col[3]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][14] ),
        .O(\txn_fifo[3][14]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][15]_i_1__2 
       (.I0(col[4]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][15] ),
        .O(\txn_fifo[3][15]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][16]_i_1__2 
       (.I0(col[5]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][16] ),
        .O(\txn_fifo[3][16]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2581" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][17]_i_1__2 
       (.I0(col[6]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][17] ),
        .O(\txn_fifo[3][17]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][1]_i_1__2 
       (.I0(bank[1]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][1] ),
        .O(\txn_fifo[3][1]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][24]_i_1__2 
       (.I0(row_mc_phy[0]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][24] ),
        .O(\txn_fifo[3][24]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][25]_i_1__2 
       (.I0(row_mc_phy[1]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][25] ),
        .O(\txn_fifo[3][25]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][26]_i_1__2 
       (.I0(row_mc_phy[2]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][26] ),
        .O(\txn_fifo[3][26]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2580" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][27]_i_1__2 
       (.I0(row_mc_phy[3]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][27] ),
        .O(\txn_fifo[3][27]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][28]_i_1__2 
       (.I0(row_mc_phy[4]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][28] ),
        .O(\txn_fifo[3][28]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][29]_i_1__2 
       (.I0(row_mc_phy[5]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][29] ),
        .O(\txn_fifo[3][29]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][2]_i_1__2 
       (.I0(group),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][2] ),
        .O(\txn_fifo[3][2]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][30]_i_1__2 
       (.I0(row_mc_phy[6]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][30] ),
        .O(\txn_fifo[3][30]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2579" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][31]_i_1__2 
       (.I0(row_mc_phy[7]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][31] ),
        .O(\txn_fifo[3][31]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][32]_i_1__2 
       (.I0(row_mc_phy[8]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][32] ),
        .O(\txn_fifo[3][32]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][33]_i_1__2 
       (.I0(row_mc_phy[9]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][33] ),
        .O(\txn_fifo[3][33]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][34]_i_1__2 
       (.I0(row_mc_phy[10]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][34] ),
        .O(\txn_fifo[3][34]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2578" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][35]_i_1__2 
       (.I0(row_mc_phy[11]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][35] ),
        .O(\txn_fifo[3][35]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][36]_i_1__2 
       (.I0(row_mc_phy[12]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][36] ),
        .O(\txn_fifo[3][36]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][37]_i_1__2 
       (.I0(row_mc_phy[13]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][37] ),
        .O(\txn_fifo[3][37]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][38]_i_1__2 
       (.I0(row_mc_phy[14]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][38] ),
        .O(\txn_fifo[3][38]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2577" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][39]_i_1__2 
       (.I0(row_mc_phy[15]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][39] ),
        .O(\txn_fifo[3][39]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][40]_i_1__2 
       (.I0(row_mc_phy[16]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][40] ),
        .O(\txn_fifo[3][40]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][44]_i_1__2 
       (.I0(cmd[0]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][44] ),
        .O(\txn_fifo[3][44]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][45]_i_1__2 
       (.I0(cmd[1]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][45] ),
        .O(\txn_fifo[3][45]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2576" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][46]_i_1__2 
       (.I0(cmd[2]),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][46] ),
        .O(\txn_fifo[3][46]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[3][47]_i_1__2 
       (.I0(1'b0),
        .I1(\txn_fifo[3][47]_i_2__1_n_0 ),
        .I2(\txn_fifo_reg_n_0_[3][47] ),
        .O(\txn_fifo[3][47]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h7F800000)) 
    \txn_fifo[3][47]_i_2__1 
       (.I0(accept_reg_0),
        .I1(\txn_fifo_wptr_reg[0]_0 ),
        .I2(useAdr),
        .I3(\txn_fifo_wptr_reg_n_0_[0] ),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .O(\txn_fifo[3][47]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h2814814242812814)) 
    txn_fifo_empty_i_1__2
       (.I0(\txn_fifo_wptr_reg_n_0_[1] ),
        .I1(txn_fifo_empty_i_2__1_n_0),
        .I2(\txn_fifo_wptr_reg_n_0_[0] ),
        .I3(\txn_fifo_rptr_reg_n_0_[1] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo_rptr_reg_n_0_[0] ),
        .O(txn_fifo_empty_i_1__2_n_0));
  LUT3 #(
    .INIT(8'h80)) 
    txn_fifo_empty_i_2__1
       (.I0(accept_reg_0),
        .I1(\txn_fifo_wptr_reg[0]_0 ),
        .I2(useAdr),
        .O(txn_fifo_empty_i_2__1_n_0));
  FDRE txn_fifo_empty_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(txn_fifo_empty_i_1__2_n_0),
        .Q(txn_fifo_empty_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[0]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(bank[0]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][0] ),
        .I4(\txn_fifo_output[0]_i_2__2_n_0 ),
        .O(\txn_fifo_output[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFA0FC0AC0A00C0AC)) 
    \txn_fifo_output[0]_i_2__2 
       (.I0(\txn_fifo[2][0]_i_1__2_n_0 ),
        .I1(\txn_fifo[1][0]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\txn_fifo[3][0]_i_1__2_n_0 ),
        .O(\txn_fifo_output[0]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[11]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(col[0]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][11] ),
        .I4(\txn_fifo_output[11]_i_2__2_n_0 ),
        .O(\txn_fifo_output[11]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[11]_i_2__2 
       (.I0(\txn_fifo[0][11]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][11]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][11]_i_1__2_n_0 ),
        .O(\txn_fifo_output[11]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[12]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(col[1]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][12] ),
        .I4(\txn_fifo_output[12]_i_2__2_n_0 ),
        .O(\txn_fifo_output[12]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[12]_i_2__2 
       (.I0(\txn_fifo[0][12]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][12]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][12]_i_1__2_n_0 ),
        .O(\txn_fifo_output[12]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[13]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(col[2]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][13] ),
        .I4(\txn_fifo_output[13]_i_2__2_n_0 ),
        .O(\txn_fifo_output[13]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFA0FC0AC0A00C0AC)) 
    \txn_fifo_output[13]_i_2__2 
       (.I0(\txn_fifo[2][13]_i_1__2_n_0 ),
        .I1(\txn_fifo[1][13]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\txn_fifo[3][13]_i_1__2_n_0 ),
        .O(\txn_fifo_output[13]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[14]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(col[3]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][14] ),
        .I4(\txn_fifo_output[14]_i_2__2_n_0 ),
        .O(\txn_fifo_output[14]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[14]_i_2__2 
       (.I0(\txn_fifo[0][14]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][14]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][14]_i_1__2_n_0 ),
        .O(\txn_fifo_output[14]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[15]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(col[4]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][15] ),
        .I4(\txn_fifo_output[15]_i_2__2_n_0 ),
        .O(\txn_fifo_output[15]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[15]_i_2__2 
       (.I0(\txn_fifo[0][15]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][15]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][15]_i_1__2_n_0 ),
        .O(\txn_fifo_output[15]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[16]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(col[5]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][16] ),
        .I4(\txn_fifo_output[16]_i_2__2_n_0 ),
        .O(\txn_fifo_output[16]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCFA00ACFC0A00AC0)) 
    \txn_fifo_output[16]_i_2__2 
       (.I0(\txn_fifo[2][16]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][16]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][16]_i_1__2_n_0 ),
        .O(\txn_fifo_output[16]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[17]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(col[6]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][17] ),
        .I4(\txn_fifo_output[17]_i_2__2_n_0 ),
        .O(\txn_fifo_output[17]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hF0AFCA0C00A0CA0C)) 
    \txn_fifo_output[17]_i_2__2 
       (.I0(\txn_fifo[0][17]_i_1__2_n_0 ),
        .I1(\txn_fifo[1][17]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\txn_fifo[3][17]_i_1__2_n_0 ),
        .O(\txn_fifo_output[17]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[1]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(bank[1]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][1] ),
        .I4(\txn_fifo_output[1]_i_2__2_n_0 ),
        .O(\txn_fifo_output[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCFA00ACFC0A00AC0)) 
    \txn_fifo_output[1]_i_2__2 
       (.I0(\txn_fifo[2][1]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][1]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][1]_i_1__2_n_0 ),
        .O(\txn_fifo_output[1]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[24]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(row_mc_phy[0]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][24] ),
        .I4(\txn_fifo_output[24]_i_2__2_n_0 ),
        .O(\txn_fifo_output[24]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCFA00ACFC0A00AC0)) 
    \txn_fifo_output[24]_i_2__2 
       (.I0(\txn_fifo[2][24]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][24]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][24]_i_1__2_n_0 ),
        .O(\txn_fifo_output[24]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[25]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(row_mc_phy[1]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][25] ),
        .I4(\txn_fifo_output[25]_i_2__2_n_0 ),
        .O(\txn_fifo_output[25]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[25]_i_2__2 
       (.I0(\txn_fifo[0][25]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][25]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][25]_i_1__2_n_0 ),
        .O(\txn_fifo_output[25]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[26]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(row_mc_phy[2]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][26] ),
        .I4(\txn_fifo_output[26]_i_2__2_n_0 ),
        .O(\txn_fifo_output[26]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[26]_i_2__2 
       (.I0(\txn_fifo[0][26]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][26]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][26]_i_1__2_n_0 ),
        .O(\txn_fifo_output[26]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[27]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(row_mc_phy[3]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][27] ),
        .I4(\txn_fifo_output[27]_i_2__2_n_0 ),
        .O(\txn_fifo_output[27]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFA0FC0AC0A00C0AC)) 
    \txn_fifo_output[27]_i_2__2 
       (.I0(\txn_fifo[2][27]_i_1__2_n_0 ),
        .I1(\txn_fifo[1][27]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\txn_fifo[3][27]_i_1__2_n_0 ),
        .O(\txn_fifo_output[27]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[28]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(row_mc_phy[4]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][28] ),
        .I4(\txn_fifo_output[28]_i_2__2_n_0 ),
        .O(\txn_fifo_output[28]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[28]_i_2__2 
       (.I0(\txn_fifo[0][28]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][28]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][28]_i_1__2_n_0 ),
        .O(\txn_fifo_output[28]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[29]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(row_mc_phy[5]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][29] ),
        .I4(\txn_fifo_output[29]_i_2__2_n_0 ),
        .O(\txn_fifo_output[29]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[29]_i_2__2 
       (.I0(\txn_fifo[0][29]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][29]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][29]_i_1__2_n_0 ),
        .O(\txn_fifo_output[29]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[2]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(group),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][2] ),
        .I4(\txn_fifo_output[2]_i_2__2_n_0 ),
        .O(\txn_fifo_output[2]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[2]_i_2__2 
       (.I0(\txn_fifo[0][2]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][2]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][2]_i_1__2_n_0 ),
        .O(\txn_fifo_output[2]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[30]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(row_mc_phy[6]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][30] ),
        .I4(\txn_fifo_output[30]_i_2__2_n_0 ),
        .O(\txn_fifo_output[30]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCFA00ACFC0A00AC0)) 
    \txn_fifo_output[30]_i_2__2 
       (.I0(\txn_fifo[2][30]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][30]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][30]_i_1__2_n_0 ),
        .O(\txn_fifo_output[30]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[31]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(row_mc_phy[7]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][31] ),
        .I4(\txn_fifo_output[31]_i_2__2_n_0 ),
        .O(\txn_fifo_output[31]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFA0FC0AC0A00C0AC)) 
    \txn_fifo_output[31]_i_2__2 
       (.I0(\txn_fifo[2][31]_i_1__2_n_0 ),
        .I1(\txn_fifo[1][31]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\txn_fifo[3][31]_i_1__2_n_0 ),
        .O(\txn_fifo_output[31]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[32]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(row_mc_phy[8]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][32] ),
        .I4(\txn_fifo_output[32]_i_2__2_n_0 ),
        .O(\txn_fifo_output[32]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCFA00ACFC0A00AC0)) 
    \txn_fifo_output[32]_i_2__2 
       (.I0(\txn_fifo[2][32]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][32]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][32]_i_1__2_n_0 ),
        .O(\txn_fifo_output[32]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[33]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(row_mc_phy[9]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][33] ),
        .I4(\txn_fifo_output[33]_i_2__2_n_0 ),
        .O(\txn_fifo_output[33]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[33]_i_2__2 
       (.I0(\txn_fifo[0][33]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][33]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][33]_i_1__2_n_0 ),
        .O(\txn_fifo_output[33]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[34]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(row_mc_phy[10]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][34] ),
        .I4(\txn_fifo_output[34]_i_2__2_n_0 ),
        .O(\txn_fifo_output[34]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[34]_i_2__2 
       (.I0(\txn_fifo[0][34]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][34]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][34]_i_1__2_n_0 ),
        .O(\txn_fifo_output[34]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[35]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(row_mc_phy[11]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][35] ),
        .I4(\txn_fifo_output[35]_i_2__2_n_0 ),
        .O(\txn_fifo_output[35]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFA0FC0AC0A00C0AC)) 
    \txn_fifo_output[35]_i_2__2 
       (.I0(\txn_fifo[2][35]_i_1__2_n_0 ),
        .I1(\txn_fifo[1][35]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\txn_fifo[3][35]_i_1__2_n_0 ),
        .O(\txn_fifo_output[35]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[36]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(row_mc_phy[12]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][36] ),
        .I4(\txn_fifo_output[36]_i_2__2_n_0 ),
        .O(\txn_fifo_output[36]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[36]_i_2__2 
       (.I0(\txn_fifo[0][36]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][36]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][36]_i_1__2_n_0 ),
        .O(\txn_fifo_output[36]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[37]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(row_mc_phy[13]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][37] ),
        .I4(\txn_fifo_output[37]_i_2__2_n_0 ),
        .O(\txn_fifo_output[37]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[37]_i_2__2 
       (.I0(\txn_fifo[0][37]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][37]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][37]_i_1__2_n_0 ),
        .O(\txn_fifo_output[37]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[38]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(row_mc_phy[14]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][38] ),
        .I4(\txn_fifo_output[38]_i_2__2_n_0 ),
        .O(\txn_fifo_output[38]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCFA00ACFC0A00AC0)) 
    \txn_fifo_output[38]_i_2__2 
       (.I0(\txn_fifo[2][38]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][38]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][38]_i_1__2_n_0 ),
        .O(\txn_fifo_output[38]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[39]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(row_mc_phy[15]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][39] ),
        .I4(\txn_fifo_output[39]_i_2__2_n_0 ),
        .O(\txn_fifo_output[39]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFA0FC0AC0A00C0AC)) 
    \txn_fifo_output[39]_i_2__2 
       (.I0(\txn_fifo[2][39]_i_1__2_n_0 ),
        .I1(\txn_fifo[1][39]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\txn_fifo[3][39]_i_1__2_n_0 ),
        .O(\txn_fifo_output[39]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[40]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(row_mc_phy[16]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][40] ),
        .I4(\txn_fifo_output[40]_i_2__2_n_0 ),
        .O(\txn_fifo_output[40]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCFA00ACFC0A00AC0)) 
    \txn_fifo_output[40]_i_2__2 
       (.I0(\txn_fifo[2][40]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][40]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][40]_i_1__2_n_0 ),
        .O(\txn_fifo_output[40]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[44]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(cmd[0]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][44] ),
        .I4(\txn_fifo_output[44]_i_2__2_n_0 ),
        .O(\txn_fifo_output[44]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[44]_i_2__2 
       (.I0(\txn_fifo[0][44]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][44]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][44]_i_1__2_n_0 ),
        .O(\txn_fifo_output[44]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[45]_i_1__2 
       (.I0(\txn_fifo_output[45]_i_2__2_n_0 ),
        .I1(cmd[1]),
        .I2(\txn_fifo[2][47]_i_2_n_0 ),
        .I3(\txn_fifo_reg_n_0_[2][45] ),
        .I4(\txn_fifo_output[45]_i_3__2_n_0 ),
        .O(\txn_fifo_output[45]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hE7)) 
    \txn_fifo_output[45]_i_2__2 
       (.I0(\txn_fifo_rptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .O(\txn_fifo_output[45]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hCF0AA0CFC00AA0C0)) 
    \txn_fifo_output[45]_i_3__2 
       (.I0(\txn_fifo[0][45]_i_1__2_n_0 ),
        .I1(\txn_fifo[3][45]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[1] ),
        .I3(\txn_fifo_rptr_reg_n_0_[0] ),
        .I4(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I5(\txn_fifo[1][45]_i_1__2_n_0 ),
        .O(\txn_fifo_output[45]_i_3__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[46]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(cmd[2]),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][46] ),
        .I4(\txn_fifo_output[46]_i_2__2_n_0 ),
        .O(\txn_fifo_output[46]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFA0FC0AC0A00C0AC)) 
    \txn_fifo_output[46]_i_2__2 
       (.I0(\txn_fifo[2][46]_i_1__2_n_0 ),
        .I1(\txn_fifo[1][46]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\txn_fifo[3][46]_i_1__2_n_0 ),
        .O(\txn_fifo_output[46]_i_2__2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF4540)) 
    \txn_fifo_output[47]_i_1__2 
       (.I0(\txn_fifo_output[47]_i_2__2_n_0 ),
        .I1(1'b0),
        .I2(\txn_fifo[0][47]_i_2__1_n_0 ),
        .I3(\txn_fifo_reg_n_0_[0][47] ),
        .I4(\txn_fifo_output[47]_i_3__2_n_0 ),
        .O(\txn_fifo_output[47]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'hDB)) 
    \txn_fifo_output[47]_i_2__2 
       (.I0(\txn_fifo_rptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .O(\txn_fifo_output[47]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'hFA0FC0AC0A00C0AC)) 
    \txn_fifo_output[47]_i_3__2 
       (.I0(\txn_fifo[2][47]_i_1__2_n_0 ),
        .I1(\txn_fifo[1][47]_i_1__2_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .I3(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I4(\txn_fifo_rptr_reg_n_0_[1] ),
        .I5(\txn_fifo[3][47]_i_1__2_n_0 ),
        .O(\txn_fifo_output[47]_i_3__2_n_0 ));
  FDRE \txn_fifo_output_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[0]_i_1__2_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[11]_i_1__2_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[11] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[12]_i_1__2_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[13]_i_1__2_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[13] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[14]_i_1__2_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[14] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[15]_i_1__2_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[15] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[16]_i_1__2_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[16] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[17]_i_1__2_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[17] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[1]_i_1__2_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[24]_i_1__2_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[25]_i_1__2_n_0 ),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[26]_i_1__2_n_0 ),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[27]_i_1__2_n_0 ),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[28]_i_1__2_n_0 ),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[29]_i_1__2_n_0 ),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[2]_i_1__2_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[30]_i_1__2_n_0 ),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[31]_i_1__2_n_0 ),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[32]_i_1__2_n_0 ),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[33]_i_1__2_n_0 ),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[34]_i_1__2_n_0 ),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[35]_i_1__2_n_0 ),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[36]_i_1__2_n_0 ),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[37]_i_1__2_n_0 ),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[38]_i_1__2_n_0 ),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[39]_i_1__2_n_0 ),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[40]_i_1__2_n_0 ),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[44]_i_1__2_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[44] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[45]_i_1__2_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[45] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[46]_i_1__2_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[46] ),
        .R(1'b0));
  FDRE \txn_fifo_output_reg[47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_output[47]_i_1__2_n_0 ),
        .Q(\txn_fifo_output_reg_n_0_[47] ),
        .R(1'b0));
  FDRE \txn_fifo_reg[0][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][0]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][0] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][11]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][11] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][12]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][12] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][13]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][13] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][14]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][14] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][15]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][15] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][16]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][16] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][17]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][17] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][1]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][1] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][24]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][24] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][25]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][25] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][26]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][26] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][27]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][27] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][28]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][28] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][29]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][29] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][2]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][2] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][30]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][30] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][31]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][31] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][32]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][32] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][33]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][33] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][34]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][34] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][35]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][35] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][36]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][36] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][37]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][37] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][38]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][38] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][39]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][39] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][40]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][40] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][44]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][44] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][45]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][45] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][46]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][46] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[0][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[0][47]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[0][47] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][0]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][0] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][11]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][11] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][12]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][12] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][13]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][13] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][14]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][14] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][15]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][15] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][16]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][16] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][17]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][17] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][1]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][1] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][24]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][24] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][25]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][25] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][26]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][26] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][27]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][27] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][28]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][28] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][29]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][29] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][2]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][2] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][30]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][30] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][31]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][31] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][32]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][32] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][33]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][33] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][34]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][34] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][35]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][35] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][36]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][36] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][37]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][37] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][38]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][38] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][39]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][39] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][40]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][40] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][44]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][44] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][45]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][45] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][46]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][46] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[1][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[1][47]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[1][47] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][0]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][0] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][11]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][11] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][12]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][12] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][13]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][13] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][14]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][14] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][15]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][15] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][16]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][16] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][17]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][17] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][1]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][1] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][24]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][24] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][25]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][25] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][26]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][26] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][27]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][27] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][28]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][28] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][29]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][29] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][2]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][2] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][30]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][30] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][31]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][31] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][32]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][32] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][33]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][33] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][34]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][34] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][35]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][35] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][36]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][36] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][37]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][37] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][38]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][38] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][39]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][39] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][40]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][40] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][44]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][44] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][45]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][45] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][46]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][46] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[2][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[2][47]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[2][47] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][0]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][0] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][11] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][11]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][11] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][12] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][12]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][12] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][13] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][13]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][13] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][14] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][14]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][14] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][15] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][15]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][15] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][16] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][16]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][16] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][17] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][17]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][17] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][1]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][1] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][24] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][24]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][24] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][25] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][25]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][25] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][26] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][26]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][26] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][27] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][27]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][27] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][28] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][28]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][28] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][29] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][29]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][29] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][2] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][2]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][2] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][30] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][30]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][30] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][31] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][31]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][31] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][32] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][32]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][32] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][33] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][33]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][33] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][34] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][34]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][34] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][35] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][35]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][35] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][36] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][36]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][36] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][37] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][37]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][37] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][38] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][38]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][38] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][39] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][39]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][39] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][40] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][40]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][40] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][44] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][44]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][44] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][45] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][45]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][45] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][46] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][46]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][46] ),
        .R(rst_r1));
  FDRE \txn_fifo_reg[3][47] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo[3][47]_i_1__2_n_0 ),
        .Q(\txn_fifo_reg_n_0_[3][47] ),
        .R(rst_r1));
  LUT2 #(
    .INIT(4'h9)) 
    \txn_fifo_rptr[0]_i_1__2 
       (.I0(\txn_fifo_rptr_reg_n_0_[0] ),
        .I1(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .O(\txn_fifo_rptr[0]_i_1__2_n_0 ));
  LUT3 #(
    .INIT(8'h9A)) 
    \txn_fifo_rptr[1]_i_1__2 
       (.I0(\txn_fifo_rptr_reg_n_0_[1] ),
        .I1(\cas_fifo_wptr[1]_i_2__0_n_0 ),
        .I2(\txn_fifo_rptr_reg_n_0_[0] ),
        .O(\txn_fifo_rptr[1]_i_1__2_n_0 ));
  FDRE \txn_fifo_rptr_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_rptr[0]_i_1__2_n_0 ),
        .Q(\txn_fifo_rptr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \txn_fifo_rptr_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_rptr[1]_i_1__2_n_0 ),
        .Q(\txn_fifo_rptr_reg_n_0_[1] ),
        .R(rst_r1));
  (* SOFT_HLUTNM = "soft_lutpair2558" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \txn_fifo_wptr[0]_i_1__1 
       (.I0(\txn_fifo_wptr_reg_n_0_[0] ),
        .I1(useAdr),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(accept_reg_0),
        .O(\txn_fifo_wptr[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2558" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \txn_fifo_wptr[1]_i_1__1 
       (.I0(\txn_fifo_wptr_reg_n_0_[0] ),
        .I1(useAdr),
        .I2(\txn_fifo_wptr_reg[0]_0 ),
        .I3(accept_reg_0),
        .I4(\txn_fifo_wptr_reg_n_0_[1] ),
        .O(\txn_fifo_wptr[1]_i_1__1_n_0 ));
  FDRE \txn_fifo_wptr_reg[0] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_wptr[0]_i_1__1_n_0 ),
        .Q(\txn_fifo_wptr_reg_n_0_[0] ),
        .R(rst_r1));
  FDRE \txn_fifo_wptr_reg[1] 
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(\txn_fifo_wptr[1]_i_1__1_n_0 ),
        .Q(\txn_fifo_wptr_reg_n_0_[1] ),
        .R(rst_r1));
  FDRE underfill_done_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(underfill_done_reg_0),
        .Q(underfill_done_reg_n_0),
        .R(rst_r1));
  LUT6 #(
    .INIT(64'h5454545454545554)) 
    wrReqR_i_1__0
       (.I0(clrReq15_out),
        .I1(wrReqR_reg_0),
        .I2(wrReqR_i_2__0_n_0),
        .I3(\FSM_sequential_gr_cas_state[2]_i_3__2_n_0 ),
        .I4(wrReqR_i_3__2_n_0),
        .I5(wrReqR_i_4__2_n_0),
        .O(wrReqR_i_1__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2575" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    wrReqR_i_2__0
       (.I0(gr_cas_state[2]),
        .I1(gr_cas_state[0]),
        .I2(underfill_done_reg_n_0),
        .I3(gr_cas_state[1]),
        .O(wrReqR_i_2__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2547" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    wrReqR_i_3__2
       (.I0(gr_cas_state[1]),
        .I1(gr_cas_state[2]),
        .I2(gr_cas_state[0]),
        .O(wrReqR_i_3__2_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFCFFB8BB)) 
    wrReqR_i_4__2
       (.I0(\txn_fifo_output_reg_n_0_[46] ),
        .I1(cas_fifo_empty_reg_n_0),
        .I2(\FSM_sequential_gr_cas_state[2]_i_8__1_n_0 ),
        .I3(\FSM_sequential_gr_cas_state[2]_i_9__0_n_0 ),
        .I4(\txn_fifo_output_reg_n_0_[44] ),
        .I5(\FSM_sequential_gr_cas_state[2]_i_6__0_n_0 ),
        .O(wrReqR_i_4__2_n_0));
  FDRE wrReqR_reg
       (.C(\cmdGroupP_reg[0]_0 ),
        .CE(1'b1),
        .D(wrReqR_i_1__0_n_0),
        .Q(wrReqR_reg_0),
        .R(rst_r1));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_periodic" *) 
module ddr4_0_ddr4_v2_2_17_mc_periodic
   (interval_counter_reset,
    per_rd_req,
    per_cas_block_req,
    per_block_ref,
    gt_data_ready_flag_nxt,
    periodic_config_gap_enable_reg_0,
    per_cas_block_req_reg_0,
    out,
    winRead,
    tranSentC,
    Q,
    cmdInjTxn,
    gt_data_ready_flag,
    gt_data_ready_flag_reg,
    refReq,
    per_rd_accept_0,
    per_rd_done,
    D);
  output interval_counter_reset;
  output per_rd_req;
  output per_cas_block_req;
  output per_block_ref;
  output gt_data_ready_flag_nxt;
  input periodic_config_gap_enable_reg_0;
  input per_cas_block_req_reg_0;
  input out;
  input winRead;
  input tranSentC;
  input [0:0]Q;
  input [0:0]cmdInjTxn;
  input gt_data_ready_flag;
  input gt_data_ready_flag_reg;
  input refReq;
  input per_rd_accept_0;
  input per_rd_done;
  input [0:0]D;

  wire \0 ;
  wire [0:0]D;
  wire \FSM_sequential_inject_state[1]_i_2_n_0 ;
  wire \FSM_sequential_inject_state[3]_i_1_n_0 ;
  wire \FSM_sequential_inject_state[3]_i_2_n_0 ;
  wire \FSM_sequential_inject_state[3]_i_3_n_0 ;
  wire \FSM_sequential_inject_state[3]_i_4_n_0 ;
  wire \FSM_sequential_inject_state[3]_i_5_n_0 ;
  wire \FSM_sequential_inject_state[3]_i_6_n_0 ;
  wire \FSM_sequential_inject_state[3]_i_7_n_0 ;
  wire \FSM_sequential_periodic_state[1]_i_2_n_0 ;
  wire \FSM_sequential_periodic_state[2]_i_2_n_0 ;
  wire \FSM_sequential_periodic_state[3]_i_1_n_0 ;
  wire \FSM_sequential_periodic_state[3]_i_3_n_0 ;
  wire \FSM_sequential_periodic_state[3]_i_4_n_0 ;
  wire [0:0]Q;
  wire [0:0]cmdInjTxn;
  wire gap_accum;
  wire gap_accum_nxt;
  wire [1:0]gap_pipe;
  wire [2:1]gap_pipe_nxt;
  wire \gap_pipe_reg_n_0_[2] ;
  wire [1:0]gap_timer;
  wire \gap_timer[0]_i_1_n_0 ;
  wire \gap_timer[1]_i_1_n_0 ;
  wire gt_data_ready;
  wire gt_data_ready_flag;
  wire gt_data_ready_flag_nxt;
  wire gt_data_ready_flag_reg;
  wire in;
  wire [3:0]inject_state;
  wire [2:0]inject_state_nxt;
  wire inject_state_read_inj;
  wire interval_counter_high;
  wire interval_counter_high0_carry__0_n_1;
  wire interval_counter_high0_carry__0_n_2;
  wire interval_counter_high0_carry__0_n_3;
  wire interval_counter_high0_carry__0_n_4;
  wire interval_counter_high0_carry__0_n_5;
  wire interval_counter_high0_carry__0_n_6;
  wire interval_counter_high0_carry__0_n_7;
  wire interval_counter_high0_carry_i_1_n_0;
  wire interval_counter_high0_carry_n_0;
  wire interval_counter_high0_carry_n_1;
  wire interval_counter_high0_carry_n_2;
  wire interval_counter_high0_carry_n_3;
  wire interval_counter_high0_carry_n_4;
  wire interval_counter_high0_carry_n_5;
  wire interval_counter_high0_carry_n_6;
  wire interval_counter_high0_carry_n_7;
  wire [15:0]interval_counter_high_reg;
  wire interval_counter_low0_carry__0_n_2;
  wire interval_counter_low0_carry__0_n_3;
  wire interval_counter_low0_carry__0_n_4;
  wire interval_counter_low0_carry__0_n_5;
  wire interval_counter_low0_carry__0_n_6;
  wire interval_counter_low0_carry__0_n_7;
  wire interval_counter_low0_carry_n_0;
  wire interval_counter_low0_carry_n_1;
  wire interval_counter_low0_carry_n_2;
  wire interval_counter_low0_carry_n_3;
  wire interval_counter_low0_carry_n_4;
  wire interval_counter_low0_carry_n_5;
  wire interval_counter_low0_carry_n_6;
  wire interval_counter_low0_carry_n_7;
  wire [15:0]interval_counter_low_reg;
  wire interval_counter_low_ro_i_2_n_0;
  wire interval_counter_low_ro_i_3_n_0;
  wire interval_counter_low_ro_i_4_n_0;
  wire interval_counter_low_ro_nxt;
  wire interval_counter_reset;
  wire interval_counter_reset_nxt;
  wire interval_hit_high;
  wire interval_hit_high_i_2_n_0;
  wire interval_hit_high_i_3_n_0;
  wire interval_hit_high_i_4_n_0;
  wire interval_hit_high_nxt;
  wire interval_hit_low;
  wire interval_hit_low_i_2_n_0;
  wire interval_hit_low_i_3_n_0;
  wire interval_hit_low_i_4_n_0;
  wire interval_hit_low_nxt;
  wire out;
  wire [15:0]p_0_in__0;
  wire [15:0]p_0_in__0__0;
  wire per_block_ref;
  wire per_block_ref_i_2_n_0;
  wire per_block_ref_i_3_n_0;
  wire per_block_ref_nxt;
  wire per_cas_block_req;
  wire per_cas_block_req_reg_0;
  wire per_rd_accept_0;
  wire per_rd_done;
  wire per_rd_req;
  wire periodic_config_gap_enable_reg_0;
  wire periodic_config_read_enable;
  wire [3:0]periodic_state;
  wire [2:0]periodic_state_nxt;
  wire read_accum;
  wire read_accum_i_1_n_0;
  wire refReq;
  wire tranSentC;
  wire winRead;
  wire [7:7]NLW_interval_counter_high0_carry__0_CO_UNCONNECTED;
  wire [7:6]NLW_interval_counter_low0_carry__0_CO_UNCONNECTED;
  wire [7:7]NLW_interval_counter_low0_carry__0_O_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair2833" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    \FSM_sequential_inject_state[0]_i_1 
       (.I0(inject_state[0]),
        .I1(inject_state[3]),
        .I2(inject_state[2]),
        .I3(inject_state[1]),
        .O(inject_state_nxt[0]));
  LUT6 #(
    .INIT(64'h0000000000FFCC8B)) 
    \FSM_sequential_inject_state[1]_i_1 
       (.I0(refReq),
        .I1(inject_state[2]),
        .I2(\FSM_sequential_inject_state[1]_i_2_n_0 ),
        .I3(inject_state[1]),
        .I4(inject_state[0]),
        .I5(inject_state[3]),
        .O(inject_state_nxt[1]));
  (* SOFT_HLUTNM = "soft_lutpair2834" *) 
  LUT4 #(
    .INIT(16'h0200)) 
    \FSM_sequential_inject_state[1]_i_2 
       (.I0(periodic_state[2]),
        .I1(periodic_state[1]),
        .I2(periodic_state[3]),
        .I3(periodic_state[0]),
        .O(\FSM_sequential_inject_state[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2832" *) 
  LUT5 #(
    .INIT(32'h00003CC4)) 
    \FSM_sequential_inject_state[2]_i_1 
       (.I0(refReq),
        .I1(inject_state[2]),
        .I2(inject_state[0]),
        .I3(inject_state[1]),
        .I4(inject_state[3]),
        .O(inject_state_nxt[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000020)) 
    \FSM_sequential_inject_state[3]_i_1 
       (.I0(\FSM_sequential_inject_state[3]_i_3_n_0 ),
        .I1(gap_timer[1]),
        .I2(gap_timer[0]),
        .I3(inject_state[3]),
        .I4(inject_state[0]),
        .I5(\FSM_sequential_inject_state[3]_i_4_n_0 ),
        .O(\FSM_sequential_inject_state[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2835" *) 
  LUT4 #(
    .INIT(16'h4004)) 
    \FSM_sequential_inject_state[3]_i_2 
       (.I0(inject_state[3]),
        .I1(inject_state[1]),
        .I2(inject_state[0]),
        .I3(inject_state[2]),
        .O(\FSM_sequential_inject_state[3]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_inject_state[3]_i_3 
       (.I0(inject_state[1]),
        .I1(inject_state[2]),
        .O(\FSM_sequential_inject_state[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF02200000)) 
    \FSM_sequential_inject_state[3]_i_4 
       (.I0(periodic_state[0]),
        .I1(periodic_state[3]),
        .I2(periodic_state[1]),
        .I3(periodic_state[2]),
        .I4(\FSM_sequential_inject_state[3]_i_5_n_0 ),
        .I5(\FSM_sequential_inject_state[3]_i_6_n_0 ),
        .O(\FSM_sequential_inject_state[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2835" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_sequential_inject_state[3]_i_5 
       (.I0(inject_state[2]),
        .I1(inject_state[1]),
        .I2(inject_state[0]),
        .O(\FSM_sequential_inject_state[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAABBEAEE)) 
    \FSM_sequential_inject_state[3]_i_6 
       (.I0(\FSM_sequential_inject_state[3]_i_7_n_0 ),
        .I1(inject_state[2]),
        .I2(per_rd_accept_0),
        .I3(inject_state[1]),
        .I4(inject_state[3]),
        .I5(inject_state[0]),
        .O(\FSM_sequential_inject_state[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h4000444440444444)) 
    \FSM_sequential_inject_state[3]_i_7 
       (.I0(inject_state[3]),
        .I1(inject_state[0]),
        .I2(per_rd_done),
        .I3(inject_state[2]),
        .I4(inject_state[1]),
        .I5(refReq),
        .O(\FSM_sequential_inject_state[3]_i_7_n_0 ));
  (* FSM_ENCODED_STATES = "INJ_BLOCK_NI:0101,INJ_ISSUE_TXN:0110,INJ_BLOCK_REF:0100,INJ_WAIT_REF:0011,IDLE:0000,INJ_WAIT_CAS_BLOCK:0010,INJ_BLOCK_READ_CAS:0001,INJ_DONE:1000,INJ_WAIT_TXN_RETURN:0111" *) 
  FDRE \FSM_sequential_inject_state_reg[0] 
       (.C(per_cas_block_req_reg_0),
        .CE(\FSM_sequential_inject_state[3]_i_1_n_0 ),
        .D(inject_state_nxt[0]),
        .Q(inject_state[0]),
        .R(out));
  (* FSM_ENCODED_STATES = "INJ_BLOCK_NI:0101,INJ_ISSUE_TXN:0110,INJ_BLOCK_REF:0100,INJ_WAIT_REF:0011,IDLE:0000,INJ_WAIT_CAS_BLOCK:0010,INJ_BLOCK_READ_CAS:0001,INJ_DONE:1000,INJ_WAIT_TXN_RETURN:0111" *) 
  FDRE \FSM_sequential_inject_state_reg[1] 
       (.C(per_cas_block_req_reg_0),
        .CE(\FSM_sequential_inject_state[3]_i_1_n_0 ),
        .D(inject_state_nxt[1]),
        .Q(inject_state[1]),
        .R(out));
  (* FSM_ENCODED_STATES = "INJ_BLOCK_NI:0101,INJ_ISSUE_TXN:0110,INJ_BLOCK_REF:0100,INJ_WAIT_REF:0011,IDLE:0000,INJ_WAIT_CAS_BLOCK:0010,INJ_BLOCK_READ_CAS:0001,INJ_DONE:1000,INJ_WAIT_TXN_RETURN:0111" *) 
  FDRE \FSM_sequential_inject_state_reg[2] 
       (.C(per_cas_block_req_reg_0),
        .CE(\FSM_sequential_inject_state[3]_i_1_n_0 ),
        .D(inject_state_nxt[2]),
        .Q(inject_state[2]),
        .R(out));
  (* FSM_ENCODED_STATES = "INJ_BLOCK_NI:0101,INJ_ISSUE_TXN:0110,INJ_BLOCK_REF:0100,INJ_WAIT_REF:0011,IDLE:0000,INJ_WAIT_CAS_BLOCK:0010,INJ_BLOCK_READ_CAS:0001,INJ_DONE:1000,INJ_WAIT_TXN_RETURN:0111" *) 
  FDRE \FSM_sequential_inject_state_reg[3] 
       (.C(per_cas_block_req_reg_0),
        .CE(\FSM_sequential_inject_state[3]_i_1_n_0 ),
        .D(\FSM_sequential_inject_state[3]_i_2_n_0 ),
        .Q(inject_state[3]),
        .R(out));
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_sequential_periodic_state[0]_i_1 
       (.I0(periodic_state[0]),
        .I1(periodic_state[3]),
        .O(periodic_state_nxt[0]));
  LUT6 #(
    .INIT(64'h003302FF003302F0)) 
    \FSM_sequential_periodic_state[1]_i_1 
       (.I0(periodic_config_read_enable),
        .I1(periodic_state[1]),
        .I2(periodic_state[2]),
        .I3(periodic_state[3]),
        .I4(periodic_state[0]),
        .I5(\FSM_sequential_periodic_state[1]_i_2_n_0 ),
        .O(periodic_state_nxt[1]));
  (* SOFT_HLUTNM = "soft_lutpair2831" *) 
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    \FSM_sequential_periodic_state[1]_i_2 
       (.I0(periodic_state[1]),
        .I1(gap_accum),
        .I2(read_accum),
        .I3(interval_hit_high),
        .I4(interval_hit_low),
        .O(\FSM_sequential_periodic_state[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000FFFFD00)) 
    \FSM_sequential_periodic_state[2]_i_1 
       (.I0(\FSM_sequential_periodic_state[2]_i_2_n_0 ),
        .I1(read_accum),
        .I2(periodic_state[0]),
        .I3(periodic_state[1]),
        .I4(periodic_state[2]),
        .I5(periodic_state[3]),
        .O(periodic_state_nxt[2]));
  (* SOFT_HLUTNM = "soft_lutpair2831" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_sequential_periodic_state[2]_i_2 
       (.I0(interval_hit_high),
        .I1(interval_hit_low),
        .O(\FSM_sequential_periodic_state[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h5F5F0E0A)) 
    \FSM_sequential_periodic_state[3]_i_1 
       (.I0(periodic_state[0]),
        .I1(periodic_state[2]),
        .I2(periodic_state[3]),
        .I3(\FSM_sequential_periodic_state[3]_i_3_n_0 ),
        .I4(\FSM_sequential_periodic_state[3]_i_4_n_0 ),
        .O(\FSM_sequential_periodic_state[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2834" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \FSM_sequential_periodic_state[3]_i_2 
       (.I0(periodic_state[3]),
        .I1(periodic_state[2]),
        .I2(periodic_state[1]),
        .I3(periodic_state[0]),
        .O(gt_data_ready));
  (* SOFT_HLUTNM = "soft_lutpair2832" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \FSM_sequential_periodic_state[3]_i_3 
       (.I0(inject_state[0]),
        .I1(inject_state[1]),
        .I2(inject_state[2]),
        .I3(inject_state[3]),
        .O(\FSM_sequential_periodic_state[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000000088FFF0)) 
    \FSM_sequential_periodic_state[3]_i_4 
       (.I0(interval_hit_low),
        .I1(interval_hit_high),
        .I2(periodic_config_read_enable),
        .I3(periodic_state[3]),
        .I4(periodic_state[1]),
        .I5(periodic_state[2]),
        .O(\FSM_sequential_periodic_state[3]_i_4_n_0 ));
  (* FSM_ENCODED_STATES = "READ_INJ:0011,WAIT_READ_INJ:0100,WAIT_INTERVAL:0010,INIT:0001,IDLE:0000,UPDATE_STATUS:0111,WAIT_GAP_INJ:0110,CHECK_ENABLE:1000,GAP_INJ:0101" *) 
  FDRE \FSM_sequential_periodic_state_reg[0] 
       (.C(per_cas_block_req_reg_0),
        .CE(\FSM_sequential_periodic_state[3]_i_1_n_0 ),
        .D(periodic_state_nxt[0]),
        .Q(periodic_state[0]),
        .R(out));
  (* FSM_ENCODED_STATES = "READ_INJ:0011,WAIT_READ_INJ:0100,WAIT_INTERVAL:0010,INIT:0001,IDLE:0000,UPDATE_STATUS:0111,WAIT_GAP_INJ:0110,CHECK_ENABLE:1000,GAP_INJ:0101" *) 
  FDRE \FSM_sequential_periodic_state_reg[1] 
       (.C(per_cas_block_req_reg_0),
        .CE(\FSM_sequential_periodic_state[3]_i_1_n_0 ),
        .D(periodic_state_nxt[1]),
        .Q(periodic_state[1]),
        .R(out));
  (* FSM_ENCODED_STATES = "READ_INJ:0011,WAIT_READ_INJ:0100,WAIT_INTERVAL:0010,INIT:0001,IDLE:0000,UPDATE_STATUS:0111,WAIT_GAP_INJ:0110,CHECK_ENABLE:1000,GAP_INJ:0101" *) 
  FDRE \FSM_sequential_periodic_state_reg[2] 
       (.C(per_cas_block_req_reg_0),
        .CE(\FSM_sequential_periodic_state[3]_i_1_n_0 ),
        .D(periodic_state_nxt[2]),
        .Q(periodic_state[2]),
        .R(out));
  (* FSM_ENCODED_STATES = "READ_INJ:0011,WAIT_READ_INJ:0100,WAIT_INTERVAL:0010,INIT:0001,IDLE:0000,UPDATE_STATUS:0111,WAIT_GAP_INJ:0110,CHECK_ENABLE:1000,GAP_INJ:0101" *) 
  FDRE \FSM_sequential_periodic_state_reg[3] 
       (.C(per_cas_block_req_reg_0),
        .CE(\FSM_sequential_periodic_state[3]_i_1_n_0 ),
        .D(gt_data_ready),
        .Q(periodic_state[3]),
        .R(out));
  LUT5 #(
    .INIT(32'h0000EAAA)) 
    gap_accum_i_1
       (.I0(gap_accum),
        .I1(gap_pipe[1]),
        .I2(\gap_pipe_reg_n_0_[2] ),
        .I3(gap_pipe[0]),
        .I4(interval_counter_reset),
        .O(gap_accum_nxt));
  FDRE gap_accum_reg
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(gap_accum_nxt),
        .Q(gap_accum),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2837" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \gap_pipe[1]_i_1 
       (.I0(gap_pipe[0]),
        .I1(interval_counter_reset),
        .O(gap_pipe_nxt[1]));
  (* SOFT_HLUTNM = "soft_lutpair2837" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \gap_pipe[2]_i_1 
       (.I0(gap_pipe[1]),
        .I1(interval_counter_reset),
        .O(gap_pipe_nxt[2]));
  FDRE \gap_pipe_reg[0] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(D),
        .Q(gap_pipe[0]),
        .R(1'b0));
  FDRE \gap_pipe_reg[1] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(gap_pipe_nxt[1]),
        .Q(gap_pipe[1]),
        .R(1'b0));
  FDRE \gap_pipe_reg[2] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(gap_pipe_nxt[2]),
        .Q(\gap_pipe_reg_n_0_[2] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h44444444444444F4)) 
    \gap_timer[0]_i_1 
       (.I0(gap_timer[0]),
        .I1(gap_timer[1]),
        .I2(inject_state[0]),
        .I3(inject_state[3]),
        .I4(inject_state[1]),
        .I5(inject_state[2]),
        .O(\gap_timer[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888888888F8)) 
    \gap_timer[1]_i_1 
       (.I0(gap_timer[0]),
        .I1(gap_timer[1]),
        .I2(inject_state[0]),
        .I3(inject_state[3]),
        .I4(inject_state[1]),
        .I5(inject_state[2]),
        .O(\gap_timer[1]_i_1_n_0 ));
  FDRE \gap_timer_reg[0] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(\gap_timer[0]_i_1_n_0 ),
        .Q(gap_timer[0]),
        .R(out));
  FDRE \gap_timer_reg[1] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(\gap_timer[1]_i_1_n_0 ),
        .Q(gap_timer[1]),
        .R(out));
  LUT6 #(
    .INIT(64'h00000000FFFF4000)) 
    gt_data_ready_flag_i_1
       (.I0(periodic_state[3]),
        .I1(periodic_state[2]),
        .I2(periodic_state[1]),
        .I3(periodic_state[0]),
        .I4(gt_data_ready_flag),
        .I5(gt_data_ready_flag_reg),
        .O(gt_data_ready_flag_nxt));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 interval_counter_high0_carry
       (.CI(1'b0),
        .CI_TOP(1'b0),
        .CO({interval_counter_high0_carry_n_0,interval_counter_high0_carry_n_1,interval_counter_high0_carry_n_2,interval_counter_high0_carry_n_3,interval_counter_high0_carry_n_4,interval_counter_high0_carry_n_5,interval_counter_high0_carry_n_6,interval_counter_high0_carry_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,interval_counter_high_reg[0]}),
        .O(p_0_in__0__0[7:0]),
        .S({interval_counter_high_reg[7:1],interval_counter_high0_carry_i_1_n_0}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 interval_counter_high0_carry__0
       (.CI(interval_counter_high0_carry_n_0),
        .CI_TOP(1'b0),
        .CO({NLW_interval_counter_high0_carry__0_CO_UNCONNECTED[7],interval_counter_high0_carry__0_n_1,interval_counter_high0_carry__0_n_2,interval_counter_high0_carry__0_n_3,interval_counter_high0_carry__0_n_4,interval_counter_high0_carry__0_n_5,interval_counter_high0_carry__0_n_6,interval_counter_high0_carry__0_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O(p_0_in__0__0[15:8]),
        .S(interval_counter_high_reg[15:8]));
  LUT2 #(
    .INIT(4'h6)) 
    interval_counter_high0_carry_i_1
       (.I0(interval_counter_high_reg[0]),
        .I1(in),
        .O(interval_counter_high0_carry_i_1_n_0));
  FDRE \interval_counter_high_reg[0] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[0]),
        .Q(interval_counter_high_reg[0]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[10] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[10]),
        .Q(interval_counter_high_reg[10]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[11] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[11]),
        .Q(interval_counter_high_reg[11]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[12] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[12]),
        .Q(interval_counter_high_reg[12]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[13] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[13]),
        .Q(interval_counter_high_reg[13]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[14] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[14]),
        .Q(interval_counter_high_reg[14]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[15] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[15]),
        .Q(interval_counter_high_reg[15]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[1] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[1]),
        .Q(interval_counter_high_reg[1]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[2] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[2]),
        .Q(interval_counter_high_reg[2]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[3] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[3]),
        .Q(interval_counter_high_reg[3]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[4] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[4]),
        .Q(interval_counter_high_reg[4]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[5] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[5]),
        .Q(interval_counter_high_reg[5]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[6] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[6]),
        .Q(interval_counter_high_reg[6]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[7] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[7]),
        .Q(interval_counter_high_reg[7]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[8] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[8]),
        .Q(interval_counter_high_reg[8]),
        .R(interval_counter_high));
  FDRE \interval_counter_high_reg[9] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0__0[9]),
        .Q(interval_counter_high_reg[9]),
        .R(interval_counter_high));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 interval_counter_low0_carry
       (.CI(interval_counter_low_reg[0]),
        .CI_TOP(1'b0),
        .CO({interval_counter_low0_carry_n_0,interval_counter_low0_carry_n_1,interval_counter_low0_carry_n_2,interval_counter_low0_carry_n_3,interval_counter_low0_carry_n_4,interval_counter_low0_carry_n_5,interval_counter_low0_carry_n_6,interval_counter_low0_carry_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O(p_0_in__0[8:1]),
        .S(interval_counter_low_reg[8:1]));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 interval_counter_low0_carry__0
       (.CI(interval_counter_low0_carry_n_0),
        .CI_TOP(1'b0),
        .CO({NLW_interval_counter_low0_carry__0_CO_UNCONNECTED[7:6],interval_counter_low0_carry__0_n_2,interval_counter_low0_carry__0_n_3,interval_counter_low0_carry__0_n_4,interval_counter_low0_carry__0_n_5,interval_counter_low0_carry__0_n_6,interval_counter_low0_carry__0_n_7}),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .O({NLW_interval_counter_low0_carry__0_O_UNCONNECTED[7],p_0_in__0[15:9]}),
        .S({1'b0,interval_counter_low_reg[15:9]}));
  (* SOFT_HLUTNM = "soft_lutpair2830" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \interval_counter_low[0]_i_1 
       (.I0(interval_counter_low_reg[0]),
        .O(p_0_in__0[0]));
  LUT2 #(
    .INIT(4'hE)) 
    \interval_counter_low[15]_i_1 
       (.I0(out),
        .I1(interval_counter_reset),
        .O(interval_counter_high));
  FDRE \interval_counter_low_reg[0] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(interval_counter_low_reg[0]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[10] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[10]),
        .Q(interval_counter_low_reg[10]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[11] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[11]),
        .Q(interval_counter_low_reg[11]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[12] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[12]),
        .Q(interval_counter_low_reg[12]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[13] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[13]),
        .Q(interval_counter_low_reg[13]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[14] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[14]),
        .Q(interval_counter_low_reg[14]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[15] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[15]),
        .Q(interval_counter_low_reg[15]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[1] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(interval_counter_low_reg[1]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[2] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(interval_counter_low_reg[2]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[3] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(interval_counter_low_reg[3]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[4] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[4]),
        .Q(interval_counter_low_reg[4]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[5] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[5]),
        .Q(interval_counter_low_reg[5]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[6] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[6]),
        .Q(interval_counter_low_reg[6]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[7] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[7]),
        .Q(interval_counter_low_reg[7]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[8] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[8]),
        .Q(interval_counter_low_reg[8]),
        .R(interval_counter_high));
  FDRE \interval_counter_low_reg[9] 
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[9]),
        .Q(interval_counter_low_reg[9]),
        .R(interval_counter_high));
  LUT6 #(
    .INIT(64'h0000020000000000)) 
    interval_counter_low_ro_i_1
       (.I0(interval_counter_low_ro_i_2_n_0),
        .I1(interval_counter_low_ro_i_3_n_0),
        .I2(interval_counter_low_ro_i_4_n_0),
        .I3(interval_counter_low_reg[12]),
        .I4(interval_counter_reset),
        .I5(interval_counter_low_reg[14]),
        .O(interval_counter_low_ro_nxt));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    interval_counter_low_ro_i_2
       (.I0(interval_counter_low_reg[3]),
        .I1(interval_counter_low_reg[2]),
        .I2(interval_counter_low_reg[1]),
        .I3(interval_counter_low_reg[7]),
        .I4(interval_counter_low_reg[15]),
        .I5(interval_counter_low_reg[13]),
        .O(interval_counter_low_ro_i_2_n_0));
  LUT4 #(
    .INIT(16'hDFFF)) 
    interval_counter_low_ro_i_3
       (.I0(interval_counter_low_reg[8]),
        .I1(interval_counter_low_reg[0]),
        .I2(interval_counter_low_reg[6]),
        .I3(interval_counter_low_reg[4]),
        .O(interval_counter_low_ro_i_3_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    interval_counter_low_ro_i_4
       (.I0(interval_counter_low_reg[10]),
        .I1(interval_counter_low_reg[5]),
        .I2(interval_counter_low_reg[11]),
        .I3(interval_counter_low_reg[9]),
        .O(interval_counter_low_ro_i_4_n_0));
  FDRE interval_counter_low_ro_reg
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(interval_counter_low_ro_nxt),
        .Q(in),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h888888888888888F)) 
    interval_counter_reset_i_1
       (.I0(interval_hit_low),
        .I1(interval_hit_high),
        .I2(periodic_state[0]),
        .I3(periodic_state[3]),
        .I4(periodic_state[1]),
        .I5(periodic_state[2]),
        .O(interval_counter_reset_nxt));
  FDRE interval_counter_reset_reg
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(interval_counter_reset_nxt),
        .Q(interval_counter_reset),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    interval_hit_high_i_1
       (.I0(interval_hit_high_i_2_n_0),
        .I1(interval_counter_high_reg[15]),
        .I2(interval_counter_high_reg[7]),
        .I3(interval_counter_high_reg[10]),
        .I4(interval_counter_high_reg[1]),
        .I5(interval_hit_high_i_3_n_0),
        .O(interval_hit_high_nxt));
  LUT4 #(
    .INIT(16'hFFFE)) 
    interval_hit_high_i_2
       (.I0(interval_counter_high_reg[12]),
        .I1(interval_counter_high_reg[6]),
        .I2(interval_counter_high_reg[2]),
        .I3(interval_counter_high_reg[4]),
        .O(interval_hit_high_i_2_n_0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    interval_hit_high_i_3
       (.I0(interval_counter_high_reg[0]),
        .I1(interval_counter_high_reg[8]),
        .I2(interval_counter_high_reg[5]),
        .I3(interval_counter_high_reg[14]),
        .I4(interval_hit_high_i_4_n_0),
        .O(interval_hit_high_i_3_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    interval_hit_high_i_4
       (.I0(interval_counter_high_reg[13]),
        .I1(interval_counter_high_reg[9]),
        .I2(interval_counter_high_reg[11]),
        .I3(interval_counter_high_reg[3]),
        .O(interval_hit_high_i_4_n_0));
  FDRE interval_hit_high_reg
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(interval_hit_high_nxt),
        .Q(interval_hit_high),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    interval_hit_low_i_1
       (.I0(interval_hit_low_i_2_n_0),
        .I1(interval_counter_low_reg[9]),
        .I2(interval_counter_low_reg[6]),
        .I3(interval_counter_low_reg[7]),
        .I4(interval_counter_low_reg[15]),
        .I5(interval_hit_low_i_3_n_0),
        .O(interval_hit_low_nxt));
  LUT4 #(
    .INIT(16'hF7FF)) 
    interval_hit_low_i_2
       (.I0(interval_counter_low_reg[3]),
        .I1(interval_counter_low_reg[2]),
        .I2(interval_counter_low_reg[4]),
        .I3(interval_counter_low_reg[8]),
        .O(interval_hit_low_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2830" *) 
  LUT5 #(
    .INIT(32'hFFFFEFFF)) 
    interval_hit_low_i_3
       (.I0(interval_counter_low_reg[1]),
        .I1(interval_counter_low_reg[11]),
        .I2(interval_counter_low_reg[0]),
        .I3(interval_counter_low_reg[5]),
        .I4(interval_hit_low_i_4_n_0),
        .O(interval_hit_low_i_3_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    interval_hit_low_i_4
       (.I0(interval_counter_low_reg[12]),
        .I1(interval_counter_low_reg[10]),
        .I2(interval_counter_low_reg[14]),
        .I3(interval_counter_low_reg[13]),
        .O(interval_hit_low_i_4_n_0));
  FDRE interval_hit_low_reg
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(interval_hit_low_nxt),
        .Q(interval_hit_low),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8888CCFC88CCCCCC)) 
    per_block_ref_i_1
       (.I0(per_block_ref_i_2_n_0),
        .I1(per_block_ref),
        .I2(per_block_ref_i_3_n_0),
        .I3(refReq),
        .I4(inject_state[2]),
        .I5(inject_state[1]),
        .O(per_block_ref_nxt));
  (* SOFT_HLUTNM = "soft_lutpair2833" *) 
  LUT4 #(
    .INIT(16'hEEFE)) 
    per_block_ref_i_2
       (.I0(inject_state[0]),
        .I1(inject_state[3]),
        .I2(inject_state[1]),
        .I3(per_rd_accept_0),
        .O(per_block_ref_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2836" *) 
  LUT2 #(
    .INIT(4'h2)) 
    per_block_ref_i_3
       (.I0(inject_state[0]),
        .I1(inject_state[3]),
        .O(per_block_ref_i_3_n_0));
  FDRE per_block_ref_reg
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(per_block_ref_nxt),
        .Q(per_block_ref),
        .R(out));
  LUT2 #(
    .INIT(4'hE)) 
    per_cas_block_req_i_1
       (.I0(gap_timer[1]),
        .I1(gap_timer[0]),
        .O(\0 ));
  FDRE per_cas_block_req_reg
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(\0 ),
        .Q(per_cas_block_req),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2836" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    per_rd_req_i_1
       (.I0(inject_state[3]),
        .I1(inject_state[0]),
        .I2(inject_state[2]),
        .I3(inject_state[1]),
        .O(inject_state_read_inj));
  FDRE per_rd_req_reg
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(inject_state_read_inj),
        .Q(per_rd_req),
        .R(1'b0));
  FDRE periodic_config_gap_enable_reg
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(periodic_config_gap_enable_reg_0),
        .Q(periodic_config_read_enable),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h5555555500404040)) 
    read_accum_i_1
       (.I0(interval_counter_reset),
        .I1(winRead),
        .I2(tranSentC),
        .I3(Q),
        .I4(cmdInjTxn),
        .I5(read_accum),
        .O(read_accum_i_1_n_0));
  FDRE read_accum_reg
       (.C(per_cas_block_req_reg_0),
        .CE(1'b1),
        .D(read_accum_i_1_n_0),
        .Q(read_accum),
        .R(out));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_rd_wr" *) 
module ddr4_0_ddr4_v2_2_17_mc_rd_wr
   (wtr_oksr,
    wtr_oklr,
    block_writes,
    block_reads,
    rtw_okr,
    \prevGr_reg[0] ,
    Q,
    out,
    wtr_oklr_reg,
    \prevGr_reg[0]_0 ,
    winRead,
    tranSentC,
    winWrite,
    \read_req_ff_reg[3]_0 ,
    rdReqR,
    wrReqR,
    \read_req_ff_reg[1]_0 ,
    \write_req_ff_reg[1]_0 ,
    \read_req_ff_reg[2]_0 ,
    \write_req_ff_reg[2]_0 ,
    \read_req_ff_reg[3]_1 ,
    \write_req_ff_reg[3]_0 ,
    D,
    SR);
  output wtr_oksr;
  output wtr_oklr;
  output block_writes;
  output block_reads;
  output rtw_okr;
  output \prevGr_reg[0] ;
  output [0:0]Q;
  input out;
  input wtr_oklr_reg;
  input \prevGr_reg[0]_0 ;
  input winRead;
  input tranSentC;
  input winWrite;
  input [3:0]\read_req_ff_reg[3]_0 ;
  input rdReqR;
  input wrReqR;
  input \read_req_ff_reg[1]_0 ;
  input \write_req_ff_reg[1]_0 ;
  input \read_req_ff_reg[2]_0 ;
  input \write_req_ff_reg[2]_0 ;
  input \read_req_ff_reg[3]_1 ;
  input \write_req_ff_reg[3]_0 ;
  input [0:0]D;
  input [0:0]SR;

  wire [0:0]D;
  wire [0:0]Q;
  wire [0:0]SR;
  wire block_reads;
  wire block_reads_nxt;
  wire block_writes;
  wire block_writes_nxt;
  wire out;
  wire \prevGr_reg[0] ;
  wire \prevGr_reg[0]_0 ;
  wire rdReqR;
  wire \read_req_ff_reg[1]_0 ;
  wire \read_req_ff_reg[2]_0 ;
  wire [3:0]\read_req_ff_reg[3]_0 ;
  wire \read_req_ff_reg[3]_1 ;
  wire \read_req_ff_reg_n_0_[0] ;
  wire \read_req_ff_reg_n_0_[1] ;
  wire \read_req_ff_reg_n_0_[2] ;
  wire \read_req_ff_reg_n_0_[3] ;
  wire [3:0]read_req_nxt;
  wire [3:0]read_req_starve;
  wire read_req_starve0;
  wire [8:0]read_req_starve1;
  wire \read_req_starve[0]_i_1_n_0 ;
  wire \read_req_starve[0]_i_2_n_0 ;
  wire \read_req_starve[1]_i_1_n_0 ;
  wire \read_req_starve[1]_i_2_n_0 ;
  wire \read_req_starve[2]_i_1_n_0 ;
  wire \read_req_starve[2]_i_2_n_0 ;
  wire \read_req_starve[3]_i_2_n_0 ;
  wire \read_req_starve_count[0][4]_i_2_n_0 ;
  wire \read_req_starve_count[0][8]_i_2_n_0 ;
  wire \read_req_starve_count[1][0]_i_1_n_0 ;
  wire \read_req_starve_count[1][1]_i_1_n_0 ;
  wire \read_req_starve_count[1][2]_i_1_n_0 ;
  wire \read_req_starve_count[1][3]_i_1_n_0 ;
  wire \read_req_starve_count[1][4]_i_1_n_0 ;
  wire \read_req_starve_count[1][4]_i_2_n_0 ;
  wire \read_req_starve_count[1][5]_i_1_n_0 ;
  wire \read_req_starve_count[1][6]_i_1_n_0 ;
  wire \read_req_starve_count[1][7]_i_1_n_0 ;
  wire \read_req_starve_count[1][8]_i_1_n_0 ;
  wire \read_req_starve_count[1][8]_i_2_n_0 ;
  wire \read_req_starve_count[2][0]_i_1_n_0 ;
  wire \read_req_starve_count[2][1]_i_1_n_0 ;
  wire \read_req_starve_count[2][2]_i_1_n_0 ;
  wire \read_req_starve_count[2][3]_i_1_n_0 ;
  wire \read_req_starve_count[2][4]_i_1_n_0 ;
  wire \read_req_starve_count[2][4]_i_2_n_0 ;
  wire \read_req_starve_count[2][5]_i_1_n_0 ;
  wire \read_req_starve_count[2][6]_i_1_n_0 ;
  wire \read_req_starve_count[2][7]_i_1_n_0 ;
  wire \read_req_starve_count[2][8]_i_1_n_0 ;
  wire \read_req_starve_count[2][8]_i_2_n_0 ;
  wire \read_req_starve_count[3][0]_i_1_n_0 ;
  wire \read_req_starve_count[3][1]_i_1_n_0 ;
  wire \read_req_starve_count[3][2]_i_1_n_0 ;
  wire \read_req_starve_count[3][3]_i_1_n_0 ;
  wire \read_req_starve_count[3][4]_i_1_n_0 ;
  wire \read_req_starve_count[3][4]_i_2_n_0 ;
  wire \read_req_starve_count[3][5]_i_1_n_0 ;
  wire \read_req_starve_count[3][6]_i_1_n_0 ;
  wire \read_req_starve_count[3][7]_i_1_n_0 ;
  wire \read_req_starve_count[3][8]_i_1_n_0 ;
  wire \read_req_starve_count[3][8]_i_2_n_0 ;
  wire [8:0]\read_req_starve_count_reg[0]_236 ;
  wire [8:0]\read_req_starve_count_reg[1]_237 ;
  wire [8:0]\read_req_starve_count_reg[2]_238 ;
  wire [8:0]\read_req_starve_count_reg[3]_239 ;
  wire [0:0]rtw0;
  wire \rtw[1]_i_1_n_0 ;
  wire \rtw[2]_i_2_n_0 ;
  wire \rtw[2]_i_3_n_0 ;
  wire rtw_okr;
  wire rtw_okr_i_1_n_0;
  wire \rtw_reg_n_0_[0] ;
  wire \rtw_reg_n_0_[1] ;
  wire \rtw_reg_n_0_[2] ;
  wire tranSentC;
  wire winRead;
  wire winWrite;
  wire wrReqR;
  wire \write_req_ff_reg[1]_0 ;
  wire \write_req_ff_reg[2]_0 ;
  wire \write_req_ff_reg[3]_0 ;
  wire \write_req_ff_reg_n_0_[0] ;
  wire \write_req_ff_reg_n_0_[1] ;
  wire \write_req_ff_reg_n_0_[2] ;
  wire \write_req_ff_reg_n_0_[3] ;
  wire [3:0]write_req_nxt;
  wire [3:0]write_req_starve;
  wire write_req_starve0;
  wire [8:0]write_req_starve1;
  wire \write_req_starve[0]_i_1_n_0 ;
  wire \write_req_starve[0]_i_2_n_0 ;
  wire \write_req_starve[1]_i_1_n_0 ;
  wire \write_req_starve[1]_i_2_n_0 ;
  wire \write_req_starve[2]_i_1_n_0 ;
  wire \write_req_starve[2]_i_2_n_0 ;
  wire \write_req_starve[3]_i_2_n_0 ;
  wire \write_req_starve_count[0][4]_i_2_n_0 ;
  wire \write_req_starve_count[0][8]_i_2_n_0 ;
  wire \write_req_starve_count[1][0]_i_1_n_0 ;
  wire \write_req_starve_count[1][1]_i_1_n_0 ;
  wire \write_req_starve_count[1][2]_i_1_n_0 ;
  wire \write_req_starve_count[1][3]_i_1_n_0 ;
  wire \write_req_starve_count[1][4]_i_1_n_0 ;
  wire \write_req_starve_count[1][4]_i_2_n_0 ;
  wire \write_req_starve_count[1][5]_i_1_n_0 ;
  wire \write_req_starve_count[1][6]_i_1_n_0 ;
  wire \write_req_starve_count[1][7]_i_1_n_0 ;
  wire \write_req_starve_count[1][8]_i_1_n_0 ;
  wire \write_req_starve_count[1][8]_i_2_n_0 ;
  wire \write_req_starve_count[2][0]_i_1_n_0 ;
  wire \write_req_starve_count[2][1]_i_1_n_0 ;
  wire \write_req_starve_count[2][2]_i_1_n_0 ;
  wire \write_req_starve_count[2][3]_i_1_n_0 ;
  wire \write_req_starve_count[2][4]_i_1_n_0 ;
  wire \write_req_starve_count[2][4]_i_2_n_0 ;
  wire \write_req_starve_count[2][5]_i_1_n_0 ;
  wire \write_req_starve_count[2][6]_i_1_n_0 ;
  wire \write_req_starve_count[2][7]_i_1_n_0 ;
  wire \write_req_starve_count[2][8]_i_1_n_0 ;
  wire \write_req_starve_count[2][8]_i_2_n_0 ;
  wire \write_req_starve_count[3][0]_i_1_n_0 ;
  wire \write_req_starve_count[3][1]_i_1_n_0 ;
  wire \write_req_starve_count[3][2]_i_1_n_0 ;
  wire \write_req_starve_count[3][3]_i_1_n_0 ;
  wire \write_req_starve_count[3][4]_i_1_n_0 ;
  wire \write_req_starve_count[3][4]_i_2_n_0 ;
  wire \write_req_starve_count[3][5]_i_1_n_0 ;
  wire \write_req_starve_count[3][6]_i_1_n_0 ;
  wire \write_req_starve_count[3][7]_i_1_n_0 ;
  wire \write_req_starve_count[3][8]_i_1_n_0 ;
  wire \write_req_starve_count[3][8]_i_2_n_0 ;
  wire [8:0]\write_req_starve_count_reg[0]_235 ;
  wire [8:0]\write_req_starve_count_reg[1]_240 ;
  wire [8:0]\write_req_starve_count_reg[2]_241 ;
  wire [8:0]\write_req_starve_count_reg[3]_242 ;
  wire wtr_oklr;
  wire wtr_oklr_reg;
  wire wtr_oksr;

  LUT4 #(
    .INIT(16'hFFFE)) 
    block_reads_i_1
       (.I0(write_req_starve[1]),
        .I1(write_req_starve[0]),
        .I2(write_req_starve[3]),
        .I3(write_req_starve[2]),
        .O(block_reads_nxt));
  FDRE block_reads_reg
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(block_reads_nxt),
        .Q(block_reads),
        .R(out));
  LUT4 #(
    .INIT(16'hFFFE)) 
    block_writes_i_1
       (.I0(read_req_starve[1]),
        .I1(read_req_starve[0]),
        .I2(read_req_starve[3]),
        .I3(read_req_starve[2]),
        .O(block_writes_nxt));
  FDRE block_writes_reg
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(block_writes_nxt),
        .Q(block_writes),
        .R(out));
  LUT5 #(
    .INIT(32'h00707070)) 
    \read_req_ff[0]_i_1 
       (.I0(tranSentC),
        .I1(\read_req_ff_reg[3]_0 [0]),
        .I2(rdReqR),
        .I3(block_reads),
        .I4(block_writes),
        .O(read_req_nxt[0]));
  LUT5 #(
    .INIT(32'h00707070)) 
    \read_req_ff[1]_i_1 
       (.I0(tranSentC),
        .I1(\read_req_ff_reg[3]_0 [1]),
        .I2(\read_req_ff_reg[1]_0 ),
        .I3(block_reads),
        .I4(block_writes),
        .O(read_req_nxt[1]));
  LUT5 #(
    .INIT(32'h00707070)) 
    \read_req_ff[2]_i_1 
       (.I0(tranSentC),
        .I1(\read_req_ff_reg[3]_0 [2]),
        .I2(\read_req_ff_reg[2]_0 ),
        .I3(block_reads),
        .I4(block_writes),
        .O(read_req_nxt[2]));
  LUT5 #(
    .INIT(32'h00707070)) 
    \read_req_ff[3]_i_1 
       (.I0(tranSentC),
        .I1(\read_req_ff_reg[3]_0 [3]),
        .I2(\read_req_ff_reg[3]_1 ),
        .I3(block_reads),
        .I4(block_writes),
        .O(read_req_nxt[3]));
  FDRE \read_req_ff_reg[0] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_nxt[0]),
        .Q(\read_req_ff_reg_n_0_[0] ),
        .R(out));
  FDRE \read_req_ff_reg[1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_nxt[1]),
        .Q(\read_req_ff_reg_n_0_[1] ),
        .R(out));
  FDRE \read_req_ff_reg[2] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_nxt[2]),
        .Q(\read_req_ff_reg_n_0_[2] ),
        .R(out));
  FDRE \read_req_ff_reg[3] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_nxt[3]),
        .Q(\read_req_ff_reg_n_0_[3] ),
        .R(out));
  LUT6 #(
    .INIT(64'h9000000000000000)) 
    \read_req_starve[0]_i_1 
       (.I0(\read_req_starve_count_reg[0]_236 [0]),
        .I1(read_req_starve[0]),
        .I2(\read_req_starve_count_reg[0]_236 [3]),
        .I3(\read_req_starve_count_reg[0]_236 [2]),
        .I4(\read_req_starve_count_reg[0]_236 [1]),
        .I5(\read_req_starve[0]_i_2_n_0 ),
        .O(\read_req_starve[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \read_req_starve[0]_i_2 
       (.I0(\read_req_starve_count_reg[0]_236 [6]),
        .I1(\read_req_starve_count_reg[0]_236 [7]),
        .I2(\read_req_starve_count_reg[0]_236 [4]),
        .I3(\read_req_starve_count_reg[0]_236 [5]),
        .I4(\read_req_ff_reg_n_0_[0] ),
        .I5(\read_req_starve_count_reg[0]_236 [8]),
        .O(\read_req_starve[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9000000000000000)) 
    \read_req_starve[1]_i_1 
       (.I0(\read_req_starve_count_reg[1]_237 [0]),
        .I1(read_req_starve[1]),
        .I2(\read_req_starve_count_reg[1]_237 [3]),
        .I3(\read_req_starve_count_reg[1]_237 [2]),
        .I4(\read_req_starve_count_reg[1]_237 [1]),
        .I5(\read_req_starve[1]_i_2_n_0 ),
        .O(\read_req_starve[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \read_req_starve[1]_i_2 
       (.I0(\read_req_starve_count_reg[1]_237 [6]),
        .I1(\read_req_starve_count_reg[1]_237 [7]),
        .I2(\read_req_starve_count_reg[1]_237 [4]),
        .I3(\read_req_starve_count_reg[1]_237 [5]),
        .I4(\read_req_ff_reg_n_0_[1] ),
        .I5(\read_req_starve_count_reg[1]_237 [8]),
        .O(\read_req_starve[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9000000000000000)) 
    \read_req_starve[2]_i_1 
       (.I0(\read_req_starve_count_reg[2]_238 [0]),
        .I1(read_req_starve[2]),
        .I2(\read_req_starve_count_reg[2]_238 [3]),
        .I3(\read_req_starve_count_reg[2]_238 [2]),
        .I4(\read_req_starve_count_reg[2]_238 [1]),
        .I5(\read_req_starve[2]_i_2_n_0 ),
        .O(\read_req_starve[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \read_req_starve[2]_i_2 
       (.I0(\read_req_starve_count_reg[2]_238 [6]),
        .I1(\read_req_starve_count_reg[2]_238 [7]),
        .I2(\read_req_starve_count_reg[2]_238 [4]),
        .I3(\read_req_starve_count_reg[2]_238 [5]),
        .I4(\read_req_ff_reg_n_0_[2] ),
        .I5(\read_req_starve_count_reg[2]_238 [8]),
        .O(\read_req_starve[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9000000000000000)) 
    \read_req_starve[3]_i_1 
       (.I0(\read_req_starve_count_reg[3]_239 [0]),
        .I1(read_req_starve[3]),
        .I2(\read_req_starve_count_reg[3]_239 [3]),
        .I3(\read_req_starve_count_reg[3]_239 [2]),
        .I4(\read_req_starve_count_reg[3]_239 [1]),
        .I5(\read_req_starve[3]_i_2_n_0 ),
        .O(read_req_starve0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \read_req_starve[3]_i_2 
       (.I0(\read_req_starve_count_reg[3]_239 [6]),
        .I1(\read_req_starve_count_reg[3]_239 [7]),
        .I2(\read_req_starve_count_reg[3]_239 [4]),
        .I3(\read_req_starve_count_reg[3]_239 [5]),
        .I4(\read_req_ff_reg_n_0_[3] ),
        .I5(\read_req_starve_count_reg[3]_239 [8]),
        .O(\read_req_starve[3]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h90)) 
    \read_req_starve_count[0][0]_i_1 
       (.I0(read_req_starve[0]),
        .I1(\read_req_starve_count_reg[0]_236 [0]),
        .I2(\read_req_ff_reg_n_0_[0] ),
        .O(read_req_starve1[0]));
  (* SOFT_HLUTNM = "soft_lutpair2848" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \read_req_starve_count[0][1]_i_1 
       (.I0(read_req_starve[0]),
        .I1(\read_req_starve_count_reg[0]_236 [0]),
        .I2(\read_req_ff_reg_n_0_[0] ),
        .I3(\read_req_starve_count_reg[0]_236 [1]),
        .O(read_req_starve1[1]));
  (* SOFT_HLUTNM = "soft_lutpair2848" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \read_req_starve_count[0][2]_i_1 
       (.I0(\read_req_starve_count_reg[0]_236 [0]),
        .I1(read_req_starve[0]),
        .I2(\read_req_starve_count_reg[0]_236 [1]),
        .I3(\read_req_ff_reg_n_0_[0] ),
        .I4(\read_req_starve_count_reg[0]_236 [2]),
        .O(read_req_starve1[2]));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \read_req_starve_count[0][3]_i_1 
       (.I0(\read_req_starve_count_reg[0]_236 [1]),
        .I1(read_req_starve[0]),
        .I2(\read_req_starve_count_reg[0]_236 [0]),
        .I3(\read_req_starve_count_reg[0]_236 [2]),
        .I4(\read_req_ff_reg_n_0_[0] ),
        .I5(\read_req_starve_count_reg[0]_236 [3]),
        .O(read_req_starve1[3]));
  (* SOFT_HLUTNM = "soft_lutpair2856" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \read_req_starve_count[0][4]_i_1 
       (.I0(\read_req_starve_count[0][4]_i_2_n_0 ),
        .I1(\read_req_ff_reg_n_0_[0] ),
        .I2(\read_req_starve_count_reg[0]_236 [4]),
        .O(read_req_starve1[4]));
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \read_req_starve_count[0][4]_i_2 
       (.I0(\read_req_starve_count_reg[0]_236 [2]),
        .I1(\read_req_starve_count_reg[0]_236 [0]),
        .I2(read_req_starve[0]),
        .I3(\read_req_starve_count_reg[0]_236 [1]),
        .I4(\read_req_starve_count_reg[0]_236 [3]),
        .O(\read_req_starve_count[0][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2856" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \read_req_starve_count[0][5]_i_1 
       (.I0(\read_req_starve_count[0][8]_i_2_n_0 ),
        .I1(\read_req_ff_reg_n_0_[0] ),
        .I2(\read_req_starve_count_reg[0]_236 [5]),
        .O(read_req_starve1[5]));
  (* SOFT_HLUTNM = "soft_lutpair2840" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \read_req_starve_count[0][6]_i_1 
       (.I0(\read_req_starve_count[0][8]_i_2_n_0 ),
        .I1(\read_req_starve_count_reg[0]_236 [5]),
        .I2(\read_req_ff_reg_n_0_[0] ),
        .I3(\read_req_starve_count_reg[0]_236 [6]),
        .O(read_req_starve1[6]));
  (* SOFT_HLUTNM = "soft_lutpair2840" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \read_req_starve_count[0][7]_i_1 
       (.I0(\read_req_starve_count_reg[0]_236 [5]),
        .I1(\read_req_starve_count[0][8]_i_2_n_0 ),
        .I2(\read_req_starve_count_reg[0]_236 [6]),
        .I3(\read_req_ff_reg_n_0_[0] ),
        .I4(\read_req_starve_count_reg[0]_236 [7]),
        .O(read_req_starve1[7]));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \read_req_starve_count[0][8]_i_1 
       (.I0(\read_req_starve_count_reg[0]_236 [6]),
        .I1(\read_req_starve_count[0][8]_i_2_n_0 ),
        .I2(\read_req_starve_count_reg[0]_236 [5]),
        .I3(\read_req_starve_count_reg[0]_236 [7]),
        .I4(\read_req_ff_reg_n_0_[0] ),
        .I5(\read_req_starve_count_reg[0]_236 [8]),
        .O(read_req_starve1[8]));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \read_req_starve_count[0][8]_i_2 
       (.I0(\read_req_starve_count_reg[0]_236 [3]),
        .I1(\read_req_starve_count_reg[0]_236 [1]),
        .I2(read_req_starve[0]),
        .I3(\read_req_starve_count_reg[0]_236 [0]),
        .I4(\read_req_starve_count_reg[0]_236 [2]),
        .I5(\read_req_starve_count_reg[0]_236 [4]),
        .O(\read_req_starve_count[0][8]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h90)) 
    \read_req_starve_count[1][0]_i_1 
       (.I0(read_req_starve[1]),
        .I1(\read_req_starve_count_reg[1]_237 [0]),
        .I2(\read_req_ff_reg_n_0_[1] ),
        .O(\read_req_starve_count[1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2849" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \read_req_starve_count[1][1]_i_1 
       (.I0(read_req_starve[1]),
        .I1(\read_req_starve_count_reg[1]_237 [0]),
        .I2(\read_req_ff_reg_n_0_[1] ),
        .I3(\read_req_starve_count_reg[1]_237 [1]),
        .O(\read_req_starve_count[1][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2849" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \read_req_starve_count[1][2]_i_1 
       (.I0(\read_req_starve_count_reg[1]_237 [0]),
        .I1(read_req_starve[1]),
        .I2(\read_req_starve_count_reg[1]_237 [1]),
        .I3(\read_req_ff_reg_n_0_[1] ),
        .I4(\read_req_starve_count_reg[1]_237 [2]),
        .O(\read_req_starve_count[1][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \read_req_starve_count[1][3]_i_1 
       (.I0(\read_req_starve_count_reg[1]_237 [1]),
        .I1(read_req_starve[1]),
        .I2(\read_req_starve_count_reg[1]_237 [0]),
        .I3(\read_req_starve_count_reg[1]_237 [2]),
        .I4(\read_req_ff_reg_n_0_[1] ),
        .I5(\read_req_starve_count_reg[1]_237 [3]),
        .O(\read_req_starve_count[1][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2857" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \read_req_starve_count[1][4]_i_1 
       (.I0(\read_req_starve_count[1][4]_i_2_n_0 ),
        .I1(\read_req_ff_reg_n_0_[1] ),
        .I2(\read_req_starve_count_reg[1]_237 [4]),
        .O(\read_req_starve_count[1][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \read_req_starve_count[1][4]_i_2 
       (.I0(\read_req_starve_count_reg[1]_237 [2]),
        .I1(\read_req_starve_count_reg[1]_237 [0]),
        .I2(read_req_starve[1]),
        .I3(\read_req_starve_count_reg[1]_237 [1]),
        .I4(\read_req_starve_count_reg[1]_237 [3]),
        .O(\read_req_starve_count[1][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2857" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \read_req_starve_count[1][5]_i_1 
       (.I0(\read_req_starve_count[1][8]_i_2_n_0 ),
        .I1(\read_req_ff_reg_n_0_[1] ),
        .I2(\read_req_starve_count_reg[1]_237 [5]),
        .O(\read_req_starve_count[1][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2841" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \read_req_starve_count[1][6]_i_1 
       (.I0(\read_req_starve_count[1][8]_i_2_n_0 ),
        .I1(\read_req_starve_count_reg[1]_237 [5]),
        .I2(\read_req_ff_reg_n_0_[1] ),
        .I3(\read_req_starve_count_reg[1]_237 [6]),
        .O(\read_req_starve_count[1][6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2841" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \read_req_starve_count[1][7]_i_1 
       (.I0(\read_req_starve_count_reg[1]_237 [5]),
        .I1(\read_req_starve_count[1][8]_i_2_n_0 ),
        .I2(\read_req_starve_count_reg[1]_237 [6]),
        .I3(\read_req_ff_reg_n_0_[1] ),
        .I4(\read_req_starve_count_reg[1]_237 [7]),
        .O(\read_req_starve_count[1][7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \read_req_starve_count[1][8]_i_1 
       (.I0(\read_req_starve_count_reg[1]_237 [6]),
        .I1(\read_req_starve_count[1][8]_i_2_n_0 ),
        .I2(\read_req_starve_count_reg[1]_237 [5]),
        .I3(\read_req_starve_count_reg[1]_237 [7]),
        .I4(\read_req_ff_reg_n_0_[1] ),
        .I5(\read_req_starve_count_reg[1]_237 [8]),
        .O(\read_req_starve_count[1][8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \read_req_starve_count[1][8]_i_2 
       (.I0(\read_req_starve_count_reg[1]_237 [3]),
        .I1(\read_req_starve_count_reg[1]_237 [1]),
        .I2(read_req_starve[1]),
        .I3(\read_req_starve_count_reg[1]_237 [0]),
        .I4(\read_req_starve_count_reg[1]_237 [2]),
        .I5(\read_req_starve_count_reg[1]_237 [4]),
        .O(\read_req_starve_count[1][8]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h90)) 
    \read_req_starve_count[2][0]_i_1 
       (.I0(read_req_starve[2]),
        .I1(\read_req_starve_count_reg[2]_238 [0]),
        .I2(\read_req_ff_reg_n_0_[2] ),
        .O(\read_req_starve_count[2][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2850" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \read_req_starve_count[2][1]_i_1 
       (.I0(read_req_starve[2]),
        .I1(\read_req_starve_count_reg[2]_238 [0]),
        .I2(\read_req_ff_reg_n_0_[2] ),
        .I3(\read_req_starve_count_reg[2]_238 [1]),
        .O(\read_req_starve_count[2][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2850" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \read_req_starve_count[2][2]_i_1 
       (.I0(\read_req_starve_count_reg[2]_238 [0]),
        .I1(read_req_starve[2]),
        .I2(\read_req_starve_count_reg[2]_238 [1]),
        .I3(\read_req_ff_reg_n_0_[2] ),
        .I4(\read_req_starve_count_reg[2]_238 [2]),
        .O(\read_req_starve_count[2][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \read_req_starve_count[2][3]_i_1 
       (.I0(\read_req_starve_count_reg[2]_238 [1]),
        .I1(read_req_starve[2]),
        .I2(\read_req_starve_count_reg[2]_238 [0]),
        .I3(\read_req_starve_count_reg[2]_238 [2]),
        .I4(\read_req_ff_reg_n_0_[2] ),
        .I5(\read_req_starve_count_reg[2]_238 [3]),
        .O(\read_req_starve_count[2][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2858" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \read_req_starve_count[2][4]_i_1 
       (.I0(\read_req_starve_count[2][4]_i_2_n_0 ),
        .I1(\read_req_ff_reg_n_0_[2] ),
        .I2(\read_req_starve_count_reg[2]_238 [4]),
        .O(\read_req_starve_count[2][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \read_req_starve_count[2][4]_i_2 
       (.I0(\read_req_starve_count_reg[2]_238 [2]),
        .I1(\read_req_starve_count_reg[2]_238 [0]),
        .I2(read_req_starve[2]),
        .I3(\read_req_starve_count_reg[2]_238 [1]),
        .I4(\read_req_starve_count_reg[2]_238 [3]),
        .O(\read_req_starve_count[2][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2858" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \read_req_starve_count[2][5]_i_1 
       (.I0(\read_req_starve_count[2][8]_i_2_n_0 ),
        .I1(\read_req_ff_reg_n_0_[2] ),
        .I2(\read_req_starve_count_reg[2]_238 [5]),
        .O(\read_req_starve_count[2][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2842" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \read_req_starve_count[2][6]_i_1 
       (.I0(\read_req_starve_count[2][8]_i_2_n_0 ),
        .I1(\read_req_starve_count_reg[2]_238 [5]),
        .I2(\read_req_ff_reg_n_0_[2] ),
        .I3(\read_req_starve_count_reg[2]_238 [6]),
        .O(\read_req_starve_count[2][6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2842" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \read_req_starve_count[2][7]_i_1 
       (.I0(\read_req_starve_count_reg[2]_238 [5]),
        .I1(\read_req_starve_count[2][8]_i_2_n_0 ),
        .I2(\read_req_starve_count_reg[2]_238 [6]),
        .I3(\read_req_ff_reg_n_0_[2] ),
        .I4(\read_req_starve_count_reg[2]_238 [7]),
        .O(\read_req_starve_count[2][7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \read_req_starve_count[2][8]_i_1 
       (.I0(\read_req_starve_count_reg[2]_238 [6]),
        .I1(\read_req_starve_count[2][8]_i_2_n_0 ),
        .I2(\read_req_starve_count_reg[2]_238 [5]),
        .I3(\read_req_starve_count_reg[2]_238 [7]),
        .I4(\read_req_ff_reg_n_0_[2] ),
        .I5(\read_req_starve_count_reg[2]_238 [8]),
        .O(\read_req_starve_count[2][8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \read_req_starve_count[2][8]_i_2 
       (.I0(\read_req_starve_count_reg[2]_238 [3]),
        .I1(\read_req_starve_count_reg[2]_238 [1]),
        .I2(read_req_starve[2]),
        .I3(\read_req_starve_count_reg[2]_238 [0]),
        .I4(\read_req_starve_count_reg[2]_238 [2]),
        .I5(\read_req_starve_count_reg[2]_238 [4]),
        .O(\read_req_starve_count[2][8]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h90)) 
    \read_req_starve_count[3][0]_i_1 
       (.I0(read_req_starve[3]),
        .I1(\read_req_starve_count_reg[3]_239 [0]),
        .I2(\read_req_ff_reg_n_0_[3] ),
        .O(\read_req_starve_count[3][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2851" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \read_req_starve_count[3][1]_i_1 
       (.I0(read_req_starve[3]),
        .I1(\read_req_starve_count_reg[3]_239 [0]),
        .I2(\read_req_ff_reg_n_0_[3] ),
        .I3(\read_req_starve_count_reg[3]_239 [1]),
        .O(\read_req_starve_count[3][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2851" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \read_req_starve_count[3][2]_i_1 
       (.I0(\read_req_starve_count_reg[3]_239 [0]),
        .I1(read_req_starve[3]),
        .I2(\read_req_starve_count_reg[3]_239 [1]),
        .I3(\read_req_ff_reg_n_0_[3] ),
        .I4(\read_req_starve_count_reg[3]_239 [2]),
        .O(\read_req_starve_count[3][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \read_req_starve_count[3][3]_i_1 
       (.I0(\read_req_starve_count_reg[3]_239 [1]),
        .I1(read_req_starve[3]),
        .I2(\read_req_starve_count_reg[3]_239 [0]),
        .I3(\read_req_starve_count_reg[3]_239 [2]),
        .I4(\read_req_ff_reg_n_0_[3] ),
        .I5(\read_req_starve_count_reg[3]_239 [3]),
        .O(\read_req_starve_count[3][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2859" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \read_req_starve_count[3][4]_i_1 
       (.I0(\read_req_starve_count[3][4]_i_2_n_0 ),
        .I1(\read_req_ff_reg_n_0_[3] ),
        .I2(\read_req_starve_count_reg[3]_239 [4]),
        .O(\read_req_starve_count[3][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \read_req_starve_count[3][4]_i_2 
       (.I0(\read_req_starve_count_reg[3]_239 [2]),
        .I1(\read_req_starve_count_reg[3]_239 [0]),
        .I2(read_req_starve[3]),
        .I3(\read_req_starve_count_reg[3]_239 [1]),
        .I4(\read_req_starve_count_reg[3]_239 [3]),
        .O(\read_req_starve_count[3][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2859" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \read_req_starve_count[3][5]_i_1 
       (.I0(\read_req_starve_count[3][8]_i_2_n_0 ),
        .I1(\read_req_ff_reg_n_0_[3] ),
        .I2(\read_req_starve_count_reg[3]_239 [5]),
        .O(\read_req_starve_count[3][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2843" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \read_req_starve_count[3][6]_i_1 
       (.I0(\read_req_starve_count[3][8]_i_2_n_0 ),
        .I1(\read_req_starve_count_reg[3]_239 [5]),
        .I2(\read_req_ff_reg_n_0_[3] ),
        .I3(\read_req_starve_count_reg[3]_239 [6]),
        .O(\read_req_starve_count[3][6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2843" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \read_req_starve_count[3][7]_i_1 
       (.I0(\read_req_starve_count_reg[3]_239 [5]),
        .I1(\read_req_starve_count[3][8]_i_2_n_0 ),
        .I2(\read_req_starve_count_reg[3]_239 [6]),
        .I3(\read_req_ff_reg_n_0_[3] ),
        .I4(\read_req_starve_count_reg[3]_239 [7]),
        .O(\read_req_starve_count[3][7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \read_req_starve_count[3][8]_i_1 
       (.I0(\read_req_starve_count_reg[3]_239 [6]),
        .I1(\read_req_starve_count[3][8]_i_2_n_0 ),
        .I2(\read_req_starve_count_reg[3]_239 [5]),
        .I3(\read_req_starve_count_reg[3]_239 [7]),
        .I4(\read_req_ff_reg_n_0_[3] ),
        .I5(\read_req_starve_count_reg[3]_239 [8]),
        .O(\read_req_starve_count[3][8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \read_req_starve_count[3][8]_i_2 
       (.I0(\read_req_starve_count_reg[3]_239 [3]),
        .I1(\read_req_starve_count_reg[3]_239 [1]),
        .I2(read_req_starve[3]),
        .I3(\read_req_starve_count_reg[3]_239 [0]),
        .I4(\read_req_starve_count_reg[3]_239 [2]),
        .I5(\read_req_starve_count_reg[3]_239 [4]),
        .O(\read_req_starve_count[3][8]_i_2_n_0 ));
  FDRE \read_req_starve_count_reg[0][0] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_starve1[0]),
        .Q(\read_req_starve_count_reg[0]_236 [0]),
        .R(out));
  FDRE \read_req_starve_count_reg[0][1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_starve1[1]),
        .Q(\read_req_starve_count_reg[0]_236 [1]),
        .R(out));
  FDRE \read_req_starve_count_reg[0][2] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_starve1[2]),
        .Q(\read_req_starve_count_reg[0]_236 [2]),
        .R(out));
  FDRE \read_req_starve_count_reg[0][3] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_starve1[3]),
        .Q(\read_req_starve_count_reg[0]_236 [3]),
        .R(out));
  FDRE \read_req_starve_count_reg[0][4] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_starve1[4]),
        .Q(\read_req_starve_count_reg[0]_236 [4]),
        .R(out));
  FDRE \read_req_starve_count_reg[0][5] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_starve1[5]),
        .Q(\read_req_starve_count_reg[0]_236 [5]),
        .R(out));
  FDRE \read_req_starve_count_reg[0][6] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_starve1[6]),
        .Q(\read_req_starve_count_reg[0]_236 [6]),
        .R(out));
  FDRE \read_req_starve_count_reg[0][7] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_starve1[7]),
        .Q(\read_req_starve_count_reg[0]_236 [7]),
        .R(out));
  FDRE \read_req_starve_count_reg[0][8] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_starve1[8]),
        .Q(\read_req_starve_count_reg[0]_236 [8]),
        .R(out));
  FDRE \read_req_starve_count_reg[1][0] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[1][0]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[1]_237 [0]),
        .R(out));
  FDRE \read_req_starve_count_reg[1][1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[1][1]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[1]_237 [1]),
        .R(out));
  FDRE \read_req_starve_count_reg[1][2] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[1][2]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[1]_237 [2]),
        .R(out));
  FDRE \read_req_starve_count_reg[1][3] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[1][3]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[1]_237 [3]),
        .R(out));
  FDRE \read_req_starve_count_reg[1][4] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[1][4]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[1]_237 [4]),
        .R(out));
  FDRE \read_req_starve_count_reg[1][5] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[1][5]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[1]_237 [5]),
        .R(out));
  FDRE \read_req_starve_count_reg[1][6] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[1][6]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[1]_237 [6]),
        .R(out));
  FDRE \read_req_starve_count_reg[1][7] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[1][7]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[1]_237 [7]),
        .R(out));
  FDRE \read_req_starve_count_reg[1][8] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[1][8]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[1]_237 [8]),
        .R(out));
  FDRE \read_req_starve_count_reg[2][0] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[2][0]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[2]_238 [0]),
        .R(out));
  FDRE \read_req_starve_count_reg[2][1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[2][1]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[2]_238 [1]),
        .R(out));
  FDRE \read_req_starve_count_reg[2][2] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[2][2]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[2]_238 [2]),
        .R(out));
  FDRE \read_req_starve_count_reg[2][3] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[2][3]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[2]_238 [3]),
        .R(out));
  FDRE \read_req_starve_count_reg[2][4] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[2][4]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[2]_238 [4]),
        .R(out));
  FDRE \read_req_starve_count_reg[2][5] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[2][5]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[2]_238 [5]),
        .R(out));
  FDRE \read_req_starve_count_reg[2][6] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[2][6]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[2]_238 [6]),
        .R(out));
  FDRE \read_req_starve_count_reg[2][7] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[2][7]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[2]_238 [7]),
        .R(out));
  FDRE \read_req_starve_count_reg[2][8] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[2][8]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[2]_238 [8]),
        .R(out));
  FDRE \read_req_starve_count_reg[3][0] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[3][0]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[3]_239 [0]),
        .R(out));
  FDRE \read_req_starve_count_reg[3][1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[3][1]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[3]_239 [1]),
        .R(out));
  FDRE \read_req_starve_count_reg[3][2] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[3][2]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[3]_239 [2]),
        .R(out));
  FDRE \read_req_starve_count_reg[3][3] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[3][3]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[3]_239 [3]),
        .R(out));
  FDRE \read_req_starve_count_reg[3][4] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[3][4]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[3]_239 [4]),
        .R(out));
  FDRE \read_req_starve_count_reg[3][5] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[3][5]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[3]_239 [5]),
        .R(out));
  FDRE \read_req_starve_count_reg[3][6] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[3][6]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[3]_239 [6]),
        .R(out));
  FDRE \read_req_starve_count_reg[3][7] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[3][7]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[3]_239 [7]),
        .R(out));
  FDRE \read_req_starve_count_reg[3][8] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve_count[3][8]_i_1_n_0 ),
        .Q(\read_req_starve_count_reg[3]_239 [8]),
        .R(out));
  FDRE \read_req_starve_reg[0] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve[0]_i_1_n_0 ),
        .Q(read_req_starve[0]),
        .R(out));
  FDRE \read_req_starve_reg[1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve[1]_i_1_n_0 ),
        .Q(read_req_starve[1]),
        .R(out));
  FDRE \read_req_starve_reg[2] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\read_req_starve[2]_i_1_n_0 ),
        .Q(read_req_starve[2]),
        .R(out));
  FDRE \read_req_starve_reg[3] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(read_req_starve0),
        .Q(read_req_starve[3]),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2864" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rtw0_inferred__1/i_ 
       (.I0(\rtw_reg_n_0_[0] ),
        .O(rtw0));
  LUT5 #(
    .INIT(32'hFFA4A4A4)) 
    \rtw[1]_i_1 
       (.I0(\rtw_reg_n_0_[1] ),
        .I1(\rtw_reg_n_0_[2] ),
        .I2(\rtw_reg_n_0_[0] ),
        .I3(winRead),
        .I4(tranSentC),
        .O(\rtw[1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \rtw[2]_i_2 
       (.I0(\rtw_reg_n_0_[0] ),
        .I1(\rtw_reg_n_0_[2] ),
        .I2(\rtw_reg_n_0_[1] ),
        .O(\rtw[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2864" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \rtw[2]_i_3 
       (.I0(\rtw_reg_n_0_[1] ),
        .I1(\rtw_reg_n_0_[0] ),
        .I2(\rtw_reg_n_0_[2] ),
        .O(\rtw[2]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h0111)) 
    rtw_okr_i_1
       (.I0(\rtw_reg_n_0_[2] ),
        .I1(\rtw_reg_n_0_[1] ),
        .I2(winRead),
        .I3(tranSentC),
        .O(rtw_okr_i_1_n_0));
  FDSE rtw_okr_reg
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(rtw_okr_i_1_n_0),
        .Q(rtw_okr),
        .S(out));
  FDRE \rtw_reg[0] 
       (.C(wtr_oklr_reg),
        .CE(\rtw[2]_i_2_n_0 ),
        .D(rtw0),
        .Q(\rtw_reg_n_0_[0] ),
        .R(SR));
  FDRE \rtw_reg[1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\rtw[1]_i_1_n_0 ),
        .Q(\rtw_reg_n_0_[1] ),
        .R(out));
  FDRE \rtw_reg[2] 
       (.C(wtr_oklr_reg),
        .CE(\rtw[2]_i_2_n_0 ),
        .D(\rtw[2]_i_3_n_0 ),
        .Q(\rtw_reg_n_0_[2] ),
        .R(SR));
  LUT5 #(
    .INIT(32'h00707070)) 
    \write_req_ff[0]_i_1 
       (.I0(tranSentC),
        .I1(\read_req_ff_reg[3]_0 [0]),
        .I2(wrReqR),
        .I3(block_reads),
        .I4(block_writes),
        .O(write_req_nxt[0]));
  LUT5 #(
    .INIT(32'h00707070)) 
    \write_req_ff[1]_i_1 
       (.I0(tranSentC),
        .I1(\read_req_ff_reg[3]_0 [1]),
        .I2(\write_req_ff_reg[1]_0 ),
        .I3(block_reads),
        .I4(block_writes),
        .O(write_req_nxt[1]));
  LUT5 #(
    .INIT(32'h00707070)) 
    \write_req_ff[2]_i_1 
       (.I0(tranSentC),
        .I1(\read_req_ff_reg[3]_0 [2]),
        .I2(\write_req_ff_reg[2]_0 ),
        .I3(block_reads),
        .I4(block_writes),
        .O(write_req_nxt[2]));
  LUT5 #(
    .INIT(32'h00707070)) 
    \write_req_ff[3]_i_1 
       (.I0(tranSentC),
        .I1(\read_req_ff_reg[3]_0 [3]),
        .I2(\write_req_ff_reg[3]_0 ),
        .I3(block_reads),
        .I4(block_writes),
        .O(write_req_nxt[3]));
  FDRE \write_req_ff_reg[0] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_nxt[0]),
        .Q(\write_req_ff_reg_n_0_[0] ),
        .R(out));
  FDRE \write_req_ff_reg[1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_nxt[1]),
        .Q(\write_req_ff_reg_n_0_[1] ),
        .R(out));
  FDRE \write_req_ff_reg[2] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_nxt[2]),
        .Q(\write_req_ff_reg_n_0_[2] ),
        .R(out));
  FDRE \write_req_ff_reg[3] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_nxt[3]),
        .Q(\write_req_ff_reg_n_0_[3] ),
        .R(out));
  LUT6 #(
    .INIT(64'h9000000000000000)) 
    \write_req_starve[0]_i_1 
       (.I0(\write_req_starve_count_reg[0]_235 [0]),
        .I1(write_req_starve[0]),
        .I2(\write_req_starve_count_reg[0]_235 [3]),
        .I3(\write_req_starve_count_reg[0]_235 [2]),
        .I4(\write_req_starve_count_reg[0]_235 [1]),
        .I5(\write_req_starve[0]_i_2_n_0 ),
        .O(\write_req_starve[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \write_req_starve[0]_i_2 
       (.I0(\write_req_starve_count_reg[0]_235 [6]),
        .I1(\write_req_starve_count_reg[0]_235 [7]),
        .I2(\write_req_starve_count_reg[0]_235 [4]),
        .I3(\write_req_starve_count_reg[0]_235 [5]),
        .I4(\write_req_ff_reg_n_0_[0] ),
        .I5(\write_req_starve_count_reg[0]_235 [8]),
        .O(\write_req_starve[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9000000000000000)) 
    \write_req_starve[1]_i_1 
       (.I0(\write_req_starve_count_reg[1]_240 [0]),
        .I1(write_req_starve[1]),
        .I2(\write_req_starve_count_reg[1]_240 [3]),
        .I3(\write_req_starve_count_reg[1]_240 [2]),
        .I4(\write_req_starve_count_reg[1]_240 [1]),
        .I5(\write_req_starve[1]_i_2_n_0 ),
        .O(\write_req_starve[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \write_req_starve[1]_i_2 
       (.I0(\write_req_starve_count_reg[1]_240 [6]),
        .I1(\write_req_starve_count_reg[1]_240 [7]),
        .I2(\write_req_starve_count_reg[1]_240 [4]),
        .I3(\write_req_starve_count_reg[1]_240 [5]),
        .I4(\write_req_ff_reg_n_0_[1] ),
        .I5(\write_req_starve_count_reg[1]_240 [8]),
        .O(\write_req_starve[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9000000000000000)) 
    \write_req_starve[2]_i_1 
       (.I0(\write_req_starve_count_reg[2]_241 [0]),
        .I1(write_req_starve[2]),
        .I2(\write_req_starve_count_reg[2]_241 [3]),
        .I3(\write_req_starve_count_reg[2]_241 [2]),
        .I4(\write_req_starve_count_reg[2]_241 [1]),
        .I5(\write_req_starve[2]_i_2_n_0 ),
        .O(\write_req_starve[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \write_req_starve[2]_i_2 
       (.I0(\write_req_starve_count_reg[2]_241 [6]),
        .I1(\write_req_starve_count_reg[2]_241 [7]),
        .I2(\write_req_starve_count_reg[2]_241 [4]),
        .I3(\write_req_starve_count_reg[2]_241 [5]),
        .I4(\write_req_ff_reg_n_0_[2] ),
        .I5(\write_req_starve_count_reg[2]_241 [8]),
        .O(\write_req_starve[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9000000000000000)) 
    \write_req_starve[3]_i_1 
       (.I0(\write_req_starve_count_reg[3]_242 [0]),
        .I1(write_req_starve[3]),
        .I2(\write_req_starve_count_reg[3]_242 [3]),
        .I3(\write_req_starve_count_reg[3]_242 [2]),
        .I4(\write_req_starve_count_reg[3]_242 [1]),
        .I5(\write_req_starve[3]_i_2_n_0 ),
        .O(write_req_starve0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \write_req_starve[3]_i_2 
       (.I0(\write_req_starve_count_reg[3]_242 [6]),
        .I1(\write_req_starve_count_reg[3]_242 [7]),
        .I2(\write_req_starve_count_reg[3]_242 [4]),
        .I3(\write_req_starve_count_reg[3]_242 [5]),
        .I4(\write_req_ff_reg_n_0_[3] ),
        .I5(\write_req_starve_count_reg[3]_242 [8]),
        .O(\write_req_starve[3]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h90)) 
    \write_req_starve_count[0][0]_i_1 
       (.I0(write_req_starve[0]),
        .I1(\write_req_starve_count_reg[0]_235 [0]),
        .I2(\write_req_ff_reg_n_0_[0] ),
        .O(write_req_starve1[0]));
  (* SOFT_HLUTNM = "soft_lutpair2852" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \write_req_starve_count[0][1]_i_1 
       (.I0(write_req_starve[0]),
        .I1(\write_req_starve_count_reg[0]_235 [0]),
        .I2(\write_req_ff_reg_n_0_[0] ),
        .I3(\write_req_starve_count_reg[0]_235 [1]),
        .O(write_req_starve1[1]));
  (* SOFT_HLUTNM = "soft_lutpair2852" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \write_req_starve_count[0][2]_i_1 
       (.I0(\write_req_starve_count_reg[0]_235 [0]),
        .I1(write_req_starve[0]),
        .I2(\write_req_starve_count_reg[0]_235 [1]),
        .I3(\write_req_ff_reg_n_0_[0] ),
        .I4(\write_req_starve_count_reg[0]_235 [2]),
        .O(write_req_starve1[2]));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \write_req_starve_count[0][3]_i_1 
       (.I0(\write_req_starve_count_reg[0]_235 [1]),
        .I1(write_req_starve[0]),
        .I2(\write_req_starve_count_reg[0]_235 [0]),
        .I3(\write_req_starve_count_reg[0]_235 [2]),
        .I4(\write_req_ff_reg_n_0_[0] ),
        .I5(\write_req_starve_count_reg[0]_235 [3]),
        .O(write_req_starve1[3]));
  (* SOFT_HLUTNM = "soft_lutpair2860" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \write_req_starve_count[0][4]_i_1 
       (.I0(\write_req_starve_count[0][4]_i_2_n_0 ),
        .I1(\write_req_ff_reg_n_0_[0] ),
        .I2(\write_req_starve_count_reg[0]_235 [4]),
        .O(write_req_starve1[4]));
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \write_req_starve_count[0][4]_i_2 
       (.I0(\write_req_starve_count_reg[0]_235 [2]),
        .I1(\write_req_starve_count_reg[0]_235 [0]),
        .I2(write_req_starve[0]),
        .I3(\write_req_starve_count_reg[0]_235 [1]),
        .I4(\write_req_starve_count_reg[0]_235 [3]),
        .O(\write_req_starve_count[0][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2860" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \write_req_starve_count[0][5]_i_1 
       (.I0(\write_req_starve_count[0][8]_i_2_n_0 ),
        .I1(\write_req_ff_reg_n_0_[0] ),
        .I2(\write_req_starve_count_reg[0]_235 [5]),
        .O(write_req_starve1[5]));
  (* SOFT_HLUTNM = "soft_lutpair2844" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \write_req_starve_count[0][6]_i_1 
       (.I0(\write_req_starve_count[0][8]_i_2_n_0 ),
        .I1(\write_req_starve_count_reg[0]_235 [5]),
        .I2(\write_req_ff_reg_n_0_[0] ),
        .I3(\write_req_starve_count_reg[0]_235 [6]),
        .O(write_req_starve1[6]));
  (* SOFT_HLUTNM = "soft_lutpair2844" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \write_req_starve_count[0][7]_i_1 
       (.I0(\write_req_starve_count_reg[0]_235 [5]),
        .I1(\write_req_starve_count[0][8]_i_2_n_0 ),
        .I2(\write_req_starve_count_reg[0]_235 [6]),
        .I3(\write_req_ff_reg_n_0_[0] ),
        .I4(\write_req_starve_count_reg[0]_235 [7]),
        .O(write_req_starve1[7]));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \write_req_starve_count[0][8]_i_1 
       (.I0(\write_req_starve_count_reg[0]_235 [6]),
        .I1(\write_req_starve_count[0][8]_i_2_n_0 ),
        .I2(\write_req_starve_count_reg[0]_235 [5]),
        .I3(\write_req_starve_count_reg[0]_235 [7]),
        .I4(\write_req_ff_reg_n_0_[0] ),
        .I5(\write_req_starve_count_reg[0]_235 [8]),
        .O(write_req_starve1[8]));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \write_req_starve_count[0][8]_i_2 
       (.I0(\write_req_starve_count_reg[0]_235 [3]),
        .I1(\write_req_starve_count_reg[0]_235 [1]),
        .I2(write_req_starve[0]),
        .I3(\write_req_starve_count_reg[0]_235 [0]),
        .I4(\write_req_starve_count_reg[0]_235 [2]),
        .I5(\write_req_starve_count_reg[0]_235 [4]),
        .O(\write_req_starve_count[0][8]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h90)) 
    \write_req_starve_count[1][0]_i_1 
       (.I0(write_req_starve[1]),
        .I1(\write_req_starve_count_reg[1]_240 [0]),
        .I2(\write_req_ff_reg_n_0_[1] ),
        .O(\write_req_starve_count[1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2853" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \write_req_starve_count[1][1]_i_1 
       (.I0(write_req_starve[1]),
        .I1(\write_req_starve_count_reg[1]_240 [0]),
        .I2(\write_req_ff_reg_n_0_[1] ),
        .I3(\write_req_starve_count_reg[1]_240 [1]),
        .O(\write_req_starve_count[1][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2853" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \write_req_starve_count[1][2]_i_1 
       (.I0(\write_req_starve_count_reg[1]_240 [0]),
        .I1(write_req_starve[1]),
        .I2(\write_req_starve_count_reg[1]_240 [1]),
        .I3(\write_req_ff_reg_n_0_[1] ),
        .I4(\write_req_starve_count_reg[1]_240 [2]),
        .O(\write_req_starve_count[1][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \write_req_starve_count[1][3]_i_1 
       (.I0(\write_req_starve_count_reg[1]_240 [1]),
        .I1(write_req_starve[1]),
        .I2(\write_req_starve_count_reg[1]_240 [0]),
        .I3(\write_req_starve_count_reg[1]_240 [2]),
        .I4(\write_req_ff_reg_n_0_[1] ),
        .I5(\write_req_starve_count_reg[1]_240 [3]),
        .O(\write_req_starve_count[1][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2861" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \write_req_starve_count[1][4]_i_1 
       (.I0(\write_req_starve_count[1][4]_i_2_n_0 ),
        .I1(\write_req_ff_reg_n_0_[1] ),
        .I2(\write_req_starve_count_reg[1]_240 [4]),
        .O(\write_req_starve_count[1][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \write_req_starve_count[1][4]_i_2 
       (.I0(\write_req_starve_count_reg[1]_240 [2]),
        .I1(\write_req_starve_count_reg[1]_240 [0]),
        .I2(write_req_starve[1]),
        .I3(\write_req_starve_count_reg[1]_240 [1]),
        .I4(\write_req_starve_count_reg[1]_240 [3]),
        .O(\write_req_starve_count[1][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2861" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \write_req_starve_count[1][5]_i_1 
       (.I0(\write_req_starve_count[1][8]_i_2_n_0 ),
        .I1(\write_req_ff_reg_n_0_[1] ),
        .I2(\write_req_starve_count_reg[1]_240 [5]),
        .O(\write_req_starve_count[1][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2845" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \write_req_starve_count[1][6]_i_1 
       (.I0(\write_req_starve_count[1][8]_i_2_n_0 ),
        .I1(\write_req_starve_count_reg[1]_240 [5]),
        .I2(\write_req_ff_reg_n_0_[1] ),
        .I3(\write_req_starve_count_reg[1]_240 [6]),
        .O(\write_req_starve_count[1][6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2845" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \write_req_starve_count[1][7]_i_1 
       (.I0(\write_req_starve_count_reg[1]_240 [5]),
        .I1(\write_req_starve_count[1][8]_i_2_n_0 ),
        .I2(\write_req_starve_count_reg[1]_240 [6]),
        .I3(\write_req_ff_reg_n_0_[1] ),
        .I4(\write_req_starve_count_reg[1]_240 [7]),
        .O(\write_req_starve_count[1][7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \write_req_starve_count[1][8]_i_1 
       (.I0(\write_req_starve_count_reg[1]_240 [6]),
        .I1(\write_req_starve_count[1][8]_i_2_n_0 ),
        .I2(\write_req_starve_count_reg[1]_240 [5]),
        .I3(\write_req_starve_count_reg[1]_240 [7]),
        .I4(\write_req_ff_reg_n_0_[1] ),
        .I5(\write_req_starve_count_reg[1]_240 [8]),
        .O(\write_req_starve_count[1][8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \write_req_starve_count[1][8]_i_2 
       (.I0(\write_req_starve_count_reg[1]_240 [3]),
        .I1(\write_req_starve_count_reg[1]_240 [1]),
        .I2(write_req_starve[1]),
        .I3(\write_req_starve_count_reg[1]_240 [0]),
        .I4(\write_req_starve_count_reg[1]_240 [2]),
        .I5(\write_req_starve_count_reg[1]_240 [4]),
        .O(\write_req_starve_count[1][8]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h90)) 
    \write_req_starve_count[2][0]_i_1 
       (.I0(write_req_starve[2]),
        .I1(\write_req_starve_count_reg[2]_241 [0]),
        .I2(\write_req_ff_reg_n_0_[2] ),
        .O(\write_req_starve_count[2][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2854" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \write_req_starve_count[2][1]_i_1 
       (.I0(write_req_starve[2]),
        .I1(\write_req_starve_count_reg[2]_241 [0]),
        .I2(\write_req_ff_reg_n_0_[2] ),
        .I3(\write_req_starve_count_reg[2]_241 [1]),
        .O(\write_req_starve_count[2][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2854" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \write_req_starve_count[2][2]_i_1 
       (.I0(\write_req_starve_count_reg[2]_241 [0]),
        .I1(write_req_starve[2]),
        .I2(\write_req_starve_count_reg[2]_241 [1]),
        .I3(\write_req_ff_reg_n_0_[2] ),
        .I4(\write_req_starve_count_reg[2]_241 [2]),
        .O(\write_req_starve_count[2][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \write_req_starve_count[2][3]_i_1 
       (.I0(\write_req_starve_count_reg[2]_241 [1]),
        .I1(write_req_starve[2]),
        .I2(\write_req_starve_count_reg[2]_241 [0]),
        .I3(\write_req_starve_count_reg[2]_241 [2]),
        .I4(\write_req_ff_reg_n_0_[2] ),
        .I5(\write_req_starve_count_reg[2]_241 [3]),
        .O(\write_req_starve_count[2][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2862" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \write_req_starve_count[2][4]_i_1 
       (.I0(\write_req_starve_count[2][4]_i_2_n_0 ),
        .I1(\write_req_ff_reg_n_0_[2] ),
        .I2(\write_req_starve_count_reg[2]_241 [4]),
        .O(\write_req_starve_count[2][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \write_req_starve_count[2][4]_i_2 
       (.I0(\write_req_starve_count_reg[2]_241 [2]),
        .I1(\write_req_starve_count_reg[2]_241 [0]),
        .I2(write_req_starve[2]),
        .I3(\write_req_starve_count_reg[2]_241 [1]),
        .I4(\write_req_starve_count_reg[2]_241 [3]),
        .O(\write_req_starve_count[2][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2862" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \write_req_starve_count[2][5]_i_1 
       (.I0(\write_req_starve_count[2][8]_i_2_n_0 ),
        .I1(\write_req_ff_reg_n_0_[2] ),
        .I2(\write_req_starve_count_reg[2]_241 [5]),
        .O(\write_req_starve_count[2][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2846" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \write_req_starve_count[2][6]_i_1 
       (.I0(\write_req_starve_count[2][8]_i_2_n_0 ),
        .I1(\write_req_starve_count_reg[2]_241 [5]),
        .I2(\write_req_ff_reg_n_0_[2] ),
        .I3(\write_req_starve_count_reg[2]_241 [6]),
        .O(\write_req_starve_count[2][6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2846" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \write_req_starve_count[2][7]_i_1 
       (.I0(\write_req_starve_count_reg[2]_241 [5]),
        .I1(\write_req_starve_count[2][8]_i_2_n_0 ),
        .I2(\write_req_starve_count_reg[2]_241 [6]),
        .I3(\write_req_ff_reg_n_0_[2] ),
        .I4(\write_req_starve_count_reg[2]_241 [7]),
        .O(\write_req_starve_count[2][7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \write_req_starve_count[2][8]_i_1 
       (.I0(\write_req_starve_count_reg[2]_241 [6]),
        .I1(\write_req_starve_count[2][8]_i_2_n_0 ),
        .I2(\write_req_starve_count_reg[2]_241 [5]),
        .I3(\write_req_starve_count_reg[2]_241 [7]),
        .I4(\write_req_ff_reg_n_0_[2] ),
        .I5(\write_req_starve_count_reg[2]_241 [8]),
        .O(\write_req_starve_count[2][8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \write_req_starve_count[2][8]_i_2 
       (.I0(\write_req_starve_count_reg[2]_241 [3]),
        .I1(\write_req_starve_count_reg[2]_241 [1]),
        .I2(write_req_starve[2]),
        .I3(\write_req_starve_count_reg[2]_241 [0]),
        .I4(\write_req_starve_count_reg[2]_241 [2]),
        .I5(\write_req_starve_count_reg[2]_241 [4]),
        .O(\write_req_starve_count[2][8]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h90)) 
    \write_req_starve_count[3][0]_i_1 
       (.I0(write_req_starve[3]),
        .I1(\write_req_starve_count_reg[3]_242 [0]),
        .I2(\write_req_ff_reg_n_0_[3] ),
        .O(\write_req_starve_count[3][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2855" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \write_req_starve_count[3][1]_i_1 
       (.I0(write_req_starve[3]),
        .I1(\write_req_starve_count_reg[3]_242 [0]),
        .I2(\write_req_ff_reg_n_0_[3] ),
        .I3(\write_req_starve_count_reg[3]_242 [1]),
        .O(\write_req_starve_count[3][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2855" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \write_req_starve_count[3][2]_i_1 
       (.I0(\write_req_starve_count_reg[3]_242 [0]),
        .I1(write_req_starve[3]),
        .I2(\write_req_starve_count_reg[3]_242 [1]),
        .I3(\write_req_ff_reg_n_0_[3] ),
        .I4(\write_req_starve_count_reg[3]_242 [2]),
        .O(\write_req_starve_count[3][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \write_req_starve_count[3][3]_i_1 
       (.I0(\write_req_starve_count_reg[3]_242 [1]),
        .I1(write_req_starve[3]),
        .I2(\write_req_starve_count_reg[3]_242 [0]),
        .I3(\write_req_starve_count_reg[3]_242 [2]),
        .I4(\write_req_ff_reg_n_0_[3] ),
        .I5(\write_req_starve_count_reg[3]_242 [3]),
        .O(\write_req_starve_count[3][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2863" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \write_req_starve_count[3][4]_i_1 
       (.I0(\write_req_starve_count[3][4]_i_2_n_0 ),
        .I1(\write_req_ff_reg_n_0_[3] ),
        .I2(\write_req_starve_count_reg[3]_242 [4]),
        .O(\write_req_starve_count[3][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \write_req_starve_count[3][4]_i_2 
       (.I0(\write_req_starve_count_reg[3]_242 [2]),
        .I1(\write_req_starve_count_reg[3]_242 [0]),
        .I2(write_req_starve[3]),
        .I3(\write_req_starve_count_reg[3]_242 [1]),
        .I4(\write_req_starve_count_reg[3]_242 [3]),
        .O(\write_req_starve_count[3][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2863" *) 
  LUT3 #(
    .INIT(8'h84)) 
    \write_req_starve_count[3][5]_i_1 
       (.I0(\write_req_starve_count[3][8]_i_2_n_0 ),
        .I1(\write_req_ff_reg_n_0_[3] ),
        .I2(\write_req_starve_count_reg[3]_242 [5]),
        .O(\write_req_starve_count[3][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2847" *) 
  LUT4 #(
    .INIT(16'hB040)) 
    \write_req_starve_count[3][6]_i_1 
       (.I0(\write_req_starve_count[3][8]_i_2_n_0 ),
        .I1(\write_req_starve_count_reg[3]_242 [5]),
        .I2(\write_req_ff_reg_n_0_[3] ),
        .I3(\write_req_starve_count_reg[3]_242 [6]),
        .O(\write_req_starve_count[3][6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2847" *) 
  LUT5 #(
    .INIT(32'hDF002000)) 
    \write_req_starve_count[3][7]_i_1 
       (.I0(\write_req_starve_count_reg[3]_242 [5]),
        .I1(\write_req_starve_count[3][8]_i_2_n_0 ),
        .I2(\write_req_starve_count_reg[3]_242 [6]),
        .I3(\write_req_ff_reg_n_0_[3] ),
        .I4(\write_req_starve_count_reg[3]_242 [7]),
        .O(\write_req_starve_count[3][7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFF000020000000)) 
    \write_req_starve_count[3][8]_i_1 
       (.I0(\write_req_starve_count_reg[3]_242 [6]),
        .I1(\write_req_starve_count[3][8]_i_2_n_0 ),
        .I2(\write_req_starve_count_reg[3]_242 [5]),
        .I3(\write_req_starve_count_reg[3]_242 [7]),
        .I4(\write_req_ff_reg_n_0_[3] ),
        .I5(\write_req_starve_count_reg[3]_242 [8]),
        .O(\write_req_starve_count[3][8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF7FFFFFFFFFFFFFF)) 
    \write_req_starve_count[3][8]_i_2 
       (.I0(\write_req_starve_count_reg[3]_242 [3]),
        .I1(\write_req_starve_count_reg[3]_242 [1]),
        .I2(write_req_starve[3]),
        .I3(\write_req_starve_count_reg[3]_242 [0]),
        .I4(\write_req_starve_count_reg[3]_242 [2]),
        .I5(\write_req_starve_count_reg[3]_242 [4]),
        .O(\write_req_starve_count[3][8]_i_2_n_0 ));
  FDRE \write_req_starve_count_reg[0][0] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_starve1[0]),
        .Q(\write_req_starve_count_reg[0]_235 [0]),
        .R(out));
  FDRE \write_req_starve_count_reg[0][1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_starve1[1]),
        .Q(\write_req_starve_count_reg[0]_235 [1]),
        .R(out));
  FDRE \write_req_starve_count_reg[0][2] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_starve1[2]),
        .Q(\write_req_starve_count_reg[0]_235 [2]),
        .R(out));
  FDRE \write_req_starve_count_reg[0][3] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_starve1[3]),
        .Q(\write_req_starve_count_reg[0]_235 [3]),
        .R(out));
  FDRE \write_req_starve_count_reg[0][4] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_starve1[4]),
        .Q(\write_req_starve_count_reg[0]_235 [4]),
        .R(out));
  FDRE \write_req_starve_count_reg[0][5] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_starve1[5]),
        .Q(\write_req_starve_count_reg[0]_235 [5]),
        .R(out));
  FDRE \write_req_starve_count_reg[0][6] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_starve1[6]),
        .Q(\write_req_starve_count_reg[0]_235 [6]),
        .R(out));
  FDRE \write_req_starve_count_reg[0][7] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_starve1[7]),
        .Q(\write_req_starve_count_reg[0]_235 [7]),
        .R(out));
  FDRE \write_req_starve_count_reg[0][8] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_starve1[8]),
        .Q(\write_req_starve_count_reg[0]_235 [8]),
        .R(out));
  FDRE \write_req_starve_count_reg[1][0] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[1][0]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[1]_240 [0]),
        .R(out));
  FDRE \write_req_starve_count_reg[1][1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[1][1]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[1]_240 [1]),
        .R(out));
  FDRE \write_req_starve_count_reg[1][2] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[1][2]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[1]_240 [2]),
        .R(out));
  FDRE \write_req_starve_count_reg[1][3] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[1][3]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[1]_240 [3]),
        .R(out));
  FDRE \write_req_starve_count_reg[1][4] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[1][4]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[1]_240 [4]),
        .R(out));
  FDRE \write_req_starve_count_reg[1][5] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[1][5]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[1]_240 [5]),
        .R(out));
  FDRE \write_req_starve_count_reg[1][6] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[1][6]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[1]_240 [6]),
        .R(out));
  FDRE \write_req_starve_count_reg[1][7] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[1][7]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[1]_240 [7]),
        .R(out));
  FDRE \write_req_starve_count_reg[1][8] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[1][8]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[1]_240 [8]),
        .R(out));
  FDRE \write_req_starve_count_reg[2][0] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[2][0]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[2]_241 [0]),
        .R(out));
  FDRE \write_req_starve_count_reg[2][1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[2][1]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[2]_241 [1]),
        .R(out));
  FDRE \write_req_starve_count_reg[2][2] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[2][2]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[2]_241 [2]),
        .R(out));
  FDRE \write_req_starve_count_reg[2][3] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[2][3]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[2]_241 [3]),
        .R(out));
  FDRE \write_req_starve_count_reg[2][4] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[2][4]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[2]_241 [4]),
        .R(out));
  FDRE \write_req_starve_count_reg[2][5] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[2][5]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[2]_241 [5]),
        .R(out));
  FDRE \write_req_starve_count_reg[2][6] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[2][6]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[2]_241 [6]),
        .R(out));
  FDRE \write_req_starve_count_reg[2][7] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[2][7]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[2]_241 [7]),
        .R(out));
  FDRE \write_req_starve_count_reg[2][8] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[2][8]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[2]_241 [8]),
        .R(out));
  FDRE \write_req_starve_count_reg[3][0] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[3][0]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[3]_242 [0]),
        .R(out));
  FDRE \write_req_starve_count_reg[3][1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[3][1]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[3]_242 [1]),
        .R(out));
  FDRE \write_req_starve_count_reg[3][2] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[3][2]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[3]_242 [2]),
        .R(out));
  FDRE \write_req_starve_count_reg[3][3] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[3][3]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[3]_242 [3]),
        .R(out));
  FDRE \write_req_starve_count_reg[3][4] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[3][4]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[3]_242 [4]),
        .R(out));
  FDRE \write_req_starve_count_reg[3][5] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[3][5]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[3]_242 [5]),
        .R(out));
  FDRE \write_req_starve_count_reg[3][6] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[3][6]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[3]_242 [6]),
        .R(out));
  FDRE \write_req_starve_count_reg[3][7] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[3][7]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[3]_242 [7]),
        .R(out));
  FDRE \write_req_starve_count_reg[3][8] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve_count[3][8]_i_1_n_0 ),
        .Q(\write_req_starve_count_reg[3]_242 [8]),
        .R(out));
  FDRE \write_req_starve_reg[0] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve[0]_i_1_n_0 ),
        .Q(write_req_starve[0]),
        .R(out));
  FDRE \write_req_starve_reg[1] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve[1]_i_1_n_0 ),
        .Q(write_req_starve[1]),
        .R(out));
  FDRE \write_req_starve_reg[2] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(\write_req_starve[2]_i_1_n_0 ),
        .Q(write_req_starve[2]),
        .R(out));
  FDRE \write_req_starve_reg[3] 
       (.C(wtr_oklr_reg),
        .CE(1'b1),
        .D(write_req_starve0),
        .Q(write_req_starve[3]),
        .R(out));
  ddr4_0_ddr4_v2_2_17_mc_wtr \wtrs[0].u_ddr_mc_wtr 
       (.D(D),
        .Q(Q),
        .out(out),
        .\prevGr_reg[0]_0 (\prevGr_reg[0] ),
        .\prevGr_reg[0]_1 (\prevGr_reg[0]_0 ),
        .tranSentC(tranSentC),
        .winWrite(winWrite),
        .wtr_oklr(wtr_oklr),
        .wtr_oklr_reg_0(wtr_oklr_reg),
        .wtr_oksr(wtr_oksr));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_ref" *) 
module ddr4_0_ddr4_v2_2_17_mc_ref
   (preIss,
    um_sreCkeDis,
    int_sreCkeDis,
    refReq,
    Q,
    \refSt_reg[3]_0 ,
    \winPort_reg[0] ,
    um_sreIss_reg_0,
    int_zqIss_reg_0,
    \um_rank_cntr_reg[1]_0 ,
    \user_fsm_reg[4]_0 ,
    \pend_ref_reg[0][0]_0 ,
    \user_fsm_reg[3]_0 ,
    \user_fsm_reg[0]_0 ,
    mc_CKE,
    mc_CS_n,
    out,
    um_sreIss_reg_1,
    \um_sreCkeDis_reg[0]_0 ,
    \int_sreCkeDis_reg[0]_0 ,
    int_refReq_reg_0,
    \um_wait_cntr_reg[7]_0 ,
    mc_BA,
    mc_ADR,
    \refSt_reg[1]_0 ,
    prevCmdAP,
    \refSt_reg[0]_0 ,
    d_prevGroup,
    \mc_CS_n7_reg[0] ,
    winWrite,
    winRead,
    tranSentC);
  output preIss;
  output um_sreCkeDis;
  output int_sreCkeDis;
  output refReq;
  output [0:0]Q;
  output [3:0]\refSt_reg[3]_0 ;
  output \winPort_reg[0] ;
  output [2:0]um_sreIss_reg_0;
  output [0:0]int_zqIss_reg_0;
  output \um_rank_cntr_reg[1]_0 ;
  output \user_fsm_reg[4]_0 ;
  output \pend_ref_reg[0][0]_0 ;
  output \user_fsm_reg[3]_0 ;
  output \user_fsm_reg[0]_0 ;
  output [1:0]mc_CKE;
  output [0:0]mc_CS_n;
  input out;
  input um_sreIss_reg_1;
  input \um_sreCkeDis_reg[0]_0 ;
  input \int_sreCkeDis_reg[0]_0 ;
  input int_refReq_reg_0;
  input \um_wait_cntr_reg[7]_0 ;
  input [0:0]mc_BA;
  input [0:0]mc_ADR;
  input \refSt_reg[1]_0 ;
  input prevCmdAP;
  input \refSt_reg[0]_0 ;
  input d_prevGroup;
  input \mc_CS_n7_reg[0] ;
  input winWrite;
  input winRead;
  input tranSentC;

  wire [0:0]Q;
  wire [7:0]cntr;
  wire \cntr[1]_i_2_n_0 ;
  wire \cntr[2]_i_2_n_0 ;
  wire \cntr[2]_i_3_n_0 ;
  wire \cntr[3]_i_2_n_0 ;
  wire \cntr[3]_i_3_n_0 ;
  wire \cntr[3]_i_4_n_0 ;
  wire \cntr[3]_i_5_n_0 ;
  wire \cntr[5]_i_1__0_n_0 ;
  wire \cntr[5]_i_2_n_0 ;
  wire \cntr[6]_i_2_n_0 ;
  wire \cntr[7]_i_2_n_0 ;
  wire \cntr[7]_i_3_n_0 ;
  wire \cntr[8]_i_1__0_n_0 ;
  wire \cntr[9]_i_1__0_n_0 ;
  wire \cntr[9]_i_2_n_0 ;
  wire \cntr[9]_i_3_n_0 ;
  wire \cntr[9]_i_4_n_0 ;
  wire \cntr[9]_i_5_n_0 ;
  wire \cntr[9]_i_6_n_0 ;
  wire \cntr[9]_i_7_n_0 ;
  wire \cntr_reg_n_0_[0] ;
  wire \cntr_reg_n_0_[1] ;
  wire \cntr_reg_n_0_[2] ;
  wire \cntr_reg_n_0_[3] ;
  wire \cntr_reg_n_0_[4] ;
  wire \cntr_reg_n_0_[5] ;
  wire \cntr_reg_n_0_[6] ;
  wire \cntr_reg_n_0_[7] ;
  wire \cntr_reg_n_0_[8] ;
  wire \cntr_reg_n_0_[9] ;
  wire d_prevGroup;
  wire inc_pend_ref;
  wire inc_pend_ref_nxt;
  wire int_preIss_i_1_n_0;
  wire int_refIss_i_1_n_0;
  wire int_refReq_reg_0;
  wire int_sreCkeDis;
  wire \int_sreCkeDis_reg[0]_0 ;
  wire int_sreIss;
  wire int_srxIss;
  wire int_srxIss_i_1_n_0;
  wire int_zqIss_i_1_n_0;
  wire [0:0]int_zqIss_reg_0;
  wire [0:0]mc_ADR;
  wire \mc_ADR7[10]_i_2_n_0 ;
  wire [0:0]mc_BA;
  wire [1:0]mc_CKE;
  wire [0:0]mc_CS_n;
  wire \mc_CS_n7[0]_i_2_n_0 ;
  wire \mc_CS_n7_reg[0] ;
  wire out;
  wire [14:0]p_0_out;
  wire p_4_out;
  wire [0:0]pend_ref;
  wire \pend_ref[0][0]_i_1_n_0 ;
  wire \pend_ref[0][1]_i_1_n_0 ;
  wire \pend_ref[0][2]_i_1_n_0 ;
  wire \pend_ref[0][3]_i_2_n_0 ;
  wire \pend_ref_reg[0][0]_0 ;
  wire \pend_ref_reg_n_0_[0][0] ;
  wire \pend_ref_reg_n_0_[0][1] ;
  wire \pend_ref_reg_n_0_[0][2] ;
  wire \pend_ref_reg_n_0_[0][3] ;
  wire preIss;
  wire prevCmdAP;
  wire refIss;
  wire refReq;
  wire \refSt[0]_i_1_n_0 ;
  wire \refSt[1]_i_1_n_0 ;
  wire \refSt[1]_i_2_n_0 ;
  wire \refSt[2]_i_1_n_0 ;
  wire \refSt[3]_i_1_n_0 ;
  wire \refSt[3]_i_2_n_0 ;
  wire \refSt[3]_i_3_n_0 ;
  wire \refSt[3]_i_4_n_0 ;
  wire \refSt_reg[0]_0 ;
  wire \refSt_reg[1]_0 ;
  wire [3:0]\refSt_reg[3]_0 ;
  wire \refi[0][10]_i_1_n_0 ;
  wire \refi[0][10]_i_2_n_0 ;
  wire \refi[0][12]_i_1_n_0 ;
  wire \refi[0][13]_i_1_n_0 ;
  wire \refi[0][14]_i_2_n_0 ;
  wire \refi[0][14]_i_3_n_0 ;
  wire \refi[0][14]_i_4_n_0 ;
  wire \refi[0][14]_i_5_n_0 ;
  wire \refi[0][14]_i_6_n_0 ;
  wire \refi[0][4]_i_1_n_0 ;
  wire \refi[0][4]_i_2_n_0 ;
  wire \refi[0][5]_i_1_n_0 ;
  wire \refi[0][6]_i_1_n_0 ;
  wire \refi[0][6]_i_2_n_0 ;
  wire \refi[0][7]_i_1_n_0 ;
  wire \refi[0][8]_i_1_n_0 ;
  wire \refi[0][9]_i_1_n_0 ;
  wire \refi_reg_n_0_[0][0] ;
  wire \refi_reg_n_0_[0][10] ;
  wire \refi_reg_n_0_[0][11] ;
  wire \refi_reg_n_0_[0][12] ;
  wire \refi_reg_n_0_[0][13] ;
  wire \refi_reg_n_0_[0][14] ;
  wire \refi_reg_n_0_[0][1] ;
  wire \refi_reg_n_0_[0][2] ;
  wire \refi_reg_n_0_[0][3] ;
  wire \refi_reg_n_0_[0][4] ;
  wire \refi_reg_n_0_[0][5] ;
  wire \refi_reg_n_0_[0][6] ;
  wire \refi_reg_n_0_[0][7] ;
  wire \refi_reg_n_0_[0][8] ;
  wire \refi_reg_n_0_[0][9] ;
  wire \refs[0]_i_1_n_0 ;
  wire \refs[1]_i_1_n_0 ;
  wire \refs[2]_i_1_n_0 ;
  wire \refs[3]_i_1_n_0 ;
  wire \refs[3]_i_2_n_0 ;
  wire \refs_reg_n_0_[0] ;
  wire \refs_reg_n_0_[1] ;
  wire \refs_reg_n_0_[2] ;
  wire \refs_reg_n_0_[3] ;
  wire [3:0]retSt;
  wire \retSt[0]_i_1__0_n_0 ;
  wire \retSt[1]_i_1__0_n_0 ;
  wire \retSt[1]_i_2_n_0 ;
  wire \retSt[2]_i_1__0_n_0 ;
  wire \retSt[3]_i_1__0_n_0 ;
  wire \retSt[3]_i_2__0_n_0 ;
  wire tranSentC;
  wire [1:0]um_rank_cntr;
  wire \um_rank_cntr[0]_i_1_n_0 ;
  wire \um_rank_cntr[1]_i_1_n_0 ;
  wire \um_rank_cntr[1]_i_2_n_0 ;
  wire \um_rank_cntr_reg[1]_0 ;
  wire um_sreCkeDis;
  wire \um_sreCkeDis_reg[0]_0 ;
  wire um_sreIss_i_1_n_0;
  wire [2:0]um_sreIss_reg_0;
  wire um_sreIss_reg_1;
  wire [8:0]um_wait_cntr;
  wire \um_wait_cntr[1]_i_2_n_0 ;
  wire \um_wait_cntr[1]_i_3_n_0 ;
  wire \um_wait_cntr[1]_i_4_n_0 ;
  wire \um_wait_cntr[2]_i_2_n_0 ;
  wire \um_wait_cntr[2]_i_3_n_0 ;
  wire \um_wait_cntr[3]_i_2_n_0 ;
  wire \um_wait_cntr[3]_i_3_n_0 ;
  wire \um_wait_cntr[4]_i_2_n_0 ;
  wire \um_wait_cntr[5]_i_2_n_0 ;
  wire \um_wait_cntr[5]_i_3_n_0 ;
  wire \um_wait_cntr[6]_i_2_n_0 ;
  wire \um_wait_cntr[6]_i_3_n_0 ;
  wire \um_wait_cntr[6]_i_4_n_0 ;
  wire \um_wait_cntr[8]_i_1_n_0 ;
  wire \um_wait_cntr[8]_i_2_n_0 ;
  wire \um_wait_cntr[8]_i_3_n_0 ;
  wire [7:0]um_wait_cntr_nxt;
  wire \um_wait_cntr_reg[7]_0 ;
  wire [3:0]user_fsm;
  wire \user_fsm[0]_i_1_n_0 ;
  wire \user_fsm[0]_i_2_n_0 ;
  wire \user_fsm[0]_i_3_n_0 ;
  wire \user_fsm[0]_i_4_n_0 ;
  wire \user_fsm[1]_i_1_n_0 ;
  wire \user_fsm[1]_i_2_n_0 ;
  wire \user_fsm[1]_i_3_n_0 ;
  wire \user_fsm[2]_i_1_n_0 ;
  wire \user_fsm[2]_i_2_n_0 ;
  wire \user_fsm[2]_i_3_n_0 ;
  wire \user_fsm[2]_i_4_n_0 ;
  wire \user_fsm[3]_i_1_n_0 ;
  wire \user_fsm[3]_i_2_n_0 ;
  wire \user_fsm[3]_i_3_n_0 ;
  wire \user_fsm[4]_i_1_n_0 ;
  wire \user_fsm[4]_i_2_n_0 ;
  wire \user_fsm[4]_i_3_n_0 ;
  wire \user_fsm[4]_i_4_n_0 ;
  wire \user_fsm[4]_i_5_n_0 ;
  wire \user_fsm[4]_i_6_n_0 ;
  wire \user_fsm_reg[0]_0 ;
  wire \user_fsm_reg[3]_0 ;
  wire \user_fsm_reg[4]_0 ;
  wire \winPort_reg[0] ;
  wire winRead;
  wire winWrite;
  wire zqIss;
  wire [15:0]zq_intvl_count;
  wire [15:0]zq_intvl_count0;
  wire \zq_intvl_count[15]_i_10_n_0 ;
  wire \zq_intvl_count[15]_i_1_n_0 ;
  wire \zq_intvl_count[15]_i_3_n_0 ;
  wire \zq_intvl_count[15]_i_4_n_0 ;
  wire \zq_intvl_count[15]_i_5_n_0 ;
  wire \zq_intvl_count[15]_i_6_n_0 ;
  wire \zq_intvl_count[15]_i_7_n_0 ;
  wire \zq_intvl_count[15]_i_8_n_0 ;
  wire \zq_intvl_count[15]_i_9_n_0 ;
  wire \zq_intvl_count[7]_i_2_n_0 ;
  wire \zq_intvl_count[7]_i_3_n_0 ;
  wire \zq_intvl_count[7]_i_4_n_0 ;
  wire \zq_intvl_count[7]_i_5_n_0 ;
  wire \zq_intvl_count[7]_i_6_n_0 ;
  wire \zq_intvl_count[7]_i_7_n_0 ;
  wire \zq_intvl_count[7]_i_8_n_0 ;
  wire \zq_intvl_count[7]_i_9_n_0 ;
  wire \zq_intvl_count_reg[15]_i_2_n_1 ;
  wire \zq_intvl_count_reg[15]_i_2_n_2 ;
  wire \zq_intvl_count_reg[15]_i_2_n_3 ;
  wire \zq_intvl_count_reg[15]_i_2_n_4 ;
  wire \zq_intvl_count_reg[15]_i_2_n_5 ;
  wire \zq_intvl_count_reg[15]_i_2_n_6 ;
  wire \zq_intvl_count_reg[15]_i_2_n_7 ;
  wire \zq_intvl_count_reg[7]_i_1_n_0 ;
  wire \zq_intvl_count_reg[7]_i_1_n_1 ;
  wire \zq_intvl_count_reg[7]_i_1_n_2 ;
  wire \zq_intvl_count_reg[7]_i_1_n_3 ;
  wire \zq_intvl_count_reg[7]_i_1_n_4 ;
  wire \zq_intvl_count_reg[7]_i_1_n_5 ;
  wire \zq_intvl_count_reg[7]_i_1_n_6 ;
  wire \zq_intvl_count_reg[7]_i_1_n_7 ;
  wire zq_pending;
  wire \zq_pending[0]_i_2_n_0 ;
  wire \zq_pending[0]_i_3_n_0 ;
  wire \zq_pending[0]_i_4_n_0 ;
  wire \zq_pending[0]_i_5_n_0 ;
  wire zq_pending_nxt;
  wire [1:0]zq_rank;
  wire \zq_rank[0]_i_1_n_0 ;
  wire \zq_rank[1]_i_1_n_0 ;
  wire \zq_rank[1]_i_2_n_0 ;
  wire [7:7]\NLW_zq_intvl_count_reg[15]_i_2_CO_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h510F505555555F05)) 
    \cntr[0]_i_1__0 
       (.I0(\cntr_reg_n_0_[0] ),
        .I1(zq_pending),
        .I2(\refSt_reg[3]_0 [3]),
        .I3(\refSt_reg[3]_0 [2]),
        .I4(\refSt_reg[3]_0 [1]),
        .I5(\refSt_reg[3]_0 [0]),
        .O(cntr[0]));
  LUT6 #(
    .INIT(64'h08B0FEF70830FEF7)) 
    \cntr[1]_i_1__0 
       (.I0(\refSt_reg[3]_0 [0]),
        .I1(\refSt_reg[3]_0 [1]),
        .I2(\refSt_reg[3]_0 [2]),
        .I3(\refSt_reg[3]_0 [3]),
        .I4(\cntr[1]_i_2_n_0 ),
        .I5(zq_pending),
        .O(cntr[1]));
  LUT2 #(
    .INIT(4'h6)) 
    \cntr[1]_i_2 
       (.I0(\cntr_reg_n_0_[1] ),
        .I1(\cntr_reg_n_0_[0] ),
        .O(\cntr[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h90FF909090909090)) 
    \cntr[2]_i_1__0 
       (.I0(\cntr_reg_n_0_[2] ),
        .I1(\cntr[2]_i_2_n_0 ),
        .I2(\cntr[7]_i_2_n_0 ),
        .I3(prevCmdAP),
        .I4(\cntr[2]_i_3_n_0 ),
        .I5(\cntr[9]_i_5_n_0 ),
        .O(cntr[2]));
  (* SOFT_HLUTNM = "soft_lutpair2894" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \cntr[2]_i_2 
       (.I0(\cntr_reg_n_0_[1] ),
        .I1(\cntr_reg_n_0_[0] ),
        .O(\cntr[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2885" *) 
  LUT4 #(
    .INIT(16'hF64F)) 
    \cntr[2]_i_3 
       (.I0(\refSt_reg[3]_0 [0]),
        .I1(\refSt_reg[3]_0 [1]),
        .I2(\refSt_reg[3]_0 [2]),
        .I3(\refSt_reg[3]_0 [3]),
        .O(\cntr[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h8F8F8F888F888F8F)) 
    \cntr[3]_i_1__0 
       (.I0(prevCmdAP),
        .I1(\cntr[3]_i_2_n_0 ),
        .I2(\cntr[3]_i_3_n_0 ),
        .I3(\cntr[3]_i_4_n_0 ),
        .I4(\cntr[3]_i_5_n_0 ),
        .I5(\cntr_reg_n_0_[3] ),
        .O(cntr[3]));
  (* SOFT_HLUTNM = "soft_lutpair2884" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    \cntr[3]_i_2 
       (.I0(\refSt_reg[3]_0 [0]),
        .I1(\refSt_reg[3]_0 [1]),
        .I2(\refSt_reg[3]_0 [3]),
        .I3(\refSt_reg[3]_0 [2]),
        .O(\cntr[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2871" *) 
  LUT5 #(
    .INIT(32'h000703C0)) 
    \cntr[3]_i_3 
       (.I0(\retSt[1]_i_2_n_0 ),
        .I1(\refSt_reg[3]_0 [0]),
        .I2(\refSt_reg[3]_0 [1]),
        .I3(\refSt_reg[3]_0 [3]),
        .I4(\refSt_reg[3]_0 [2]),
        .O(\cntr[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2877" *) 
  LUT5 #(
    .INIT(32'h09B00820)) 
    \cntr[3]_i_4 
       (.I0(\refSt_reg[3]_0 [0]),
        .I1(\refSt_reg[3]_0 [1]),
        .I2(\refSt_reg[3]_0 [2]),
        .I3(\refSt_reg[3]_0 [3]),
        .I4(zq_pending),
        .O(\cntr[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2894" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \cntr[3]_i_5 
       (.I0(\cntr_reg_n_0_[2] ),
        .I1(\cntr_reg_n_0_[0] ),
        .I2(\cntr_reg_n_0_[1] ),
        .O(\cntr[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFE000100000000)) 
    \cntr[4]_i_1__0 
       (.I0(\cntr_reg_n_0_[3] ),
        .I1(\cntr_reg_n_0_[1] ),
        .I2(\cntr_reg_n_0_[0] ),
        .I3(\cntr_reg_n_0_[2] ),
        .I4(\cntr_reg_n_0_[4] ),
        .I5(\cntr[7]_i_2_n_0 ),
        .O(cntr[4]));
  LUT6 #(
    .INIT(64'h51005F55555550F5)) 
    \cntr[5]_i_1__0 
       (.I0(\cntr[5]_i_2_n_0 ),
        .I1(zq_pending),
        .I2(\refSt_reg[3]_0 [3]),
        .I3(\refSt_reg[3]_0 [2]),
        .I4(\refSt_reg[3]_0 [1]),
        .I5(\refSt_reg[3]_0 [0]),
        .O(\cntr[5]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555555556)) 
    \cntr[5]_i_2 
       (.I0(\cntr_reg_n_0_[5] ),
        .I1(\cntr_reg_n_0_[3] ),
        .I2(\cntr_reg_n_0_[1] ),
        .I3(\cntr_reg_n_0_[0] ),
        .I4(\cntr_reg_n_0_[2] ),
        .I5(\cntr_reg_n_0_[4] ),
        .O(\cntr[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2876" *) 
  LUT5 #(
    .INIT(32'hAAAAAAEB)) 
    \cntr[6]_i_1__0 
       (.I0(int_refIss_i_1_n_0),
        .I1(\cntr_reg_n_0_[6] ),
        .I2(\cntr[7]_i_3_n_0 ),
        .I3(\cntr[9]_i_5_n_0 ),
        .I4(\cntr[6]_i_2_n_0 ),
        .O(cntr[6]));
  (* SOFT_HLUTNM = "soft_lutpair2877" *) 
  LUT5 #(
    .INIT(32'h2C20003C)) 
    \cntr[6]_i_2 
       (.I0(zq_pending),
        .I1(\refSt_reg[3]_0 [3]),
        .I2(\refSt_reg[3]_0 [2]),
        .I3(\refSt_reg[3]_0 [1]),
        .I4(\refSt_reg[3]_0 [0]),
        .O(\cntr[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2881" *) 
  LUT4 #(
    .INIT(16'hA802)) 
    \cntr[7]_i_1__0 
       (.I0(\cntr[7]_i_2_n_0 ),
        .I1(\cntr_reg_n_0_[6] ),
        .I2(\cntr[7]_i_3_n_0 ),
        .I3(\cntr_reg_n_0_[7] ),
        .O(cntr[7]));
  (* SOFT_HLUTNM = "soft_lutpair2873" *) 
  LUT5 #(
    .INIT(32'hD0CFFFC3)) 
    \cntr[7]_i_2 
       (.I0(zq_pending),
        .I1(\refSt_reg[3]_0 [3]),
        .I2(\refSt_reg[3]_0 [2]),
        .I3(\refSt_reg[3]_0 [1]),
        .I4(\refSt_reg[3]_0 [0]),
        .O(\cntr[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \cntr[7]_i_3 
       (.I0(\cntr_reg_n_0_[5] ),
        .I1(\cntr_reg_n_0_[3] ),
        .I2(\cntr_reg_n_0_[1] ),
        .I3(\cntr_reg_n_0_[0] ),
        .I4(\cntr_reg_n_0_[2] ),
        .I5(\cntr_reg_n_0_[4] ),
        .O(\cntr[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5555555544040040)) 
    \cntr[8]_i_1__0 
       (.I0(\cntr[9]_i_5_n_0 ),
        .I1(\cntr[9]_i_6_n_0 ),
        .I2(\cntr[9]_i_4_n_0 ),
        .I3(\cntr_reg_n_0_[7] ),
        .I4(\cntr_reg_n_0_[8] ),
        .I5(int_srxIss_i_1_n_0),
        .O(\cntr[8]_i_1__0_n_0 ));
  LUT3 #(
    .INIT(8'h45)) 
    \cntr[9]_i_1__0 
       (.I0(out),
        .I1(\cntr[9]_i_3_n_0 ),
        .I2(\cntr[9]_i_4_n_0 ),
        .O(\cntr[9]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h55550440)) 
    \cntr[9]_i_2 
       (.I0(\cntr[9]_i_5_n_0 ),
        .I1(\cntr[9]_i_6_n_0 ),
        .I2(\refSt[3]_i_3_n_0 ),
        .I3(\cntr_reg_n_0_[9] ),
        .I4(int_srxIss_i_1_n_0),
        .O(\cntr[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAEBEBEFAFEAEA)) 
    \cntr[9]_i_3 
       (.I0(\cntr[9]_i_7_n_0 ),
        .I1(\refSt_reg[3]_0 [0]),
        .I2(\refSt_reg[3]_0 [1]),
        .I3(zq_pending),
        .I4(\refSt_reg[3]_0 [2]),
        .I5(\refSt_reg[3]_0 [3]),
        .O(\cntr[9]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2876" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \cntr[9]_i_4 
       (.I0(\cntr_reg_n_0_[6] ),
        .I1(\cntr[7]_i_3_n_0 ),
        .O(\cntr[9]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2884" *) 
  LUT4 #(
    .INIT(16'h0018)) 
    \cntr[9]_i_5 
       (.I0(\refSt_reg[3]_0 [0]),
        .I1(\refSt_reg[3]_0 [1]),
        .I2(\refSt_reg[3]_0 [2]),
        .I3(\refSt_reg[3]_0 [3]),
        .O(\cntr[9]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2873" *) 
  LUT5 #(
    .INIT(32'hF64FF6CF)) 
    \cntr[9]_i_6 
       (.I0(\refSt_reg[3]_0 [0]),
        .I1(\refSt_reg[3]_0 [1]),
        .I2(\refSt_reg[3]_0 [2]),
        .I3(\refSt_reg[3]_0 [3]),
        .I4(zq_pending),
        .O(\cntr[9]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \cntr[9]_i_7 
       (.I0(\cntr_reg_n_0_[8] ),
        .I1(\cntr_reg_n_0_[9] ),
        .I2(\cntr_reg_n_0_[7] ),
        .O(\cntr[9]_i_7_n_0 ));
  FDRE \cntr_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(\cntr[9]_i_1__0_n_0 ),
        .D(cntr[0]),
        .Q(\cntr_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \cntr_reg[1] 
       (.C(um_sreIss_reg_1),
        .CE(\cntr[9]_i_1__0_n_0 ),
        .D(cntr[1]),
        .Q(\cntr_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cntr_reg[2] 
       (.C(um_sreIss_reg_1),
        .CE(\cntr[9]_i_1__0_n_0 ),
        .D(cntr[2]),
        .Q(\cntr_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \cntr_reg[3] 
       (.C(um_sreIss_reg_1),
        .CE(\cntr[9]_i_1__0_n_0 ),
        .D(cntr[3]),
        .Q(\cntr_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \cntr_reg[4] 
       (.C(um_sreIss_reg_1),
        .CE(\cntr[9]_i_1__0_n_0 ),
        .D(cntr[4]),
        .Q(\cntr_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \cntr_reg[5] 
       (.C(um_sreIss_reg_1),
        .CE(\cntr[9]_i_1__0_n_0 ),
        .D(\cntr[5]_i_1__0_n_0 ),
        .Q(\cntr_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \cntr_reg[6] 
       (.C(um_sreIss_reg_1),
        .CE(\cntr[9]_i_1__0_n_0 ),
        .D(cntr[6]),
        .Q(\cntr_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \cntr_reg[7] 
       (.C(um_sreIss_reg_1),
        .CE(\cntr[9]_i_1__0_n_0 ),
        .D(cntr[7]),
        .Q(\cntr_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \cntr_reg[8] 
       (.C(um_sreIss_reg_1),
        .CE(\cntr[9]_i_1__0_n_0 ),
        .D(\cntr[8]_i_1__0_n_0 ),
        .Q(\cntr_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \cntr_reg[9] 
       (.C(um_sreIss_reg_1),
        .CE(\cntr[9]_i_1__0_n_0 ),
        .D(\cntr[9]_i_2_n_0 ),
        .Q(\cntr_reg_n_0_[9] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    \inc_pend_ref[0]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\pend_ref_reg_n_0_[0][0] ),
        .I2(\pend_ref_reg_n_0_[0][3] ),
        .I3(\pend_ref_reg_n_0_[0][2] ),
        .I4(\pend_ref_reg_n_0_[0][1] ),
        .O(inc_pend_ref_nxt));
  FDRE \inc_pend_ref_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(inc_pend_ref_nxt),
        .Q(inc_pend_ref),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2889" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    int_preIss_i_1
       (.I0(\refSt_reg[3]_0 [0]),
        .I1(\refSt_reg[3]_0 [3]),
        .I2(\refSt_reg[3]_0 [2]),
        .I3(\refSt_reg[3]_0 [1]),
        .O(int_preIss_i_1_n_0));
  FDRE int_preIss_reg
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(int_preIss_i_1_n_0),
        .Q(preIss),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2885" *) 
  LUT4 #(
    .INIT(16'h2400)) 
    int_refIss_i_1
       (.I0(\refSt_reg[3]_0 [3]),
        .I1(\refSt_reg[3]_0 [2]),
        .I2(\refSt_reg[3]_0 [1]),
        .I3(\refSt_reg[3]_0 [0]),
        .O(int_refIss_i_1_n_0));
  FDRE int_refIss_reg
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(int_refIss_i_1_n_0),
        .Q(refIss),
        .R(out));
  FDRE int_refReq_reg
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(int_refReq_reg_0),
        .Q(refReq),
        .R(out));
  FDRE \int_sreCkeDis_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\int_sreCkeDis_reg[0]_0 ),
        .Q(int_sreCkeDis),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2887" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    int_srxIss_i_1
       (.I0(\refSt_reg[3]_0 [2]),
        .I1(\refSt_reg[3]_0 [3]),
        .I2(\refSt_reg[3]_0 [0]),
        .I3(\refSt_reg[3]_0 [1]),
        .O(int_srxIss_i_1_n_0));
  FDRE int_srxIss_reg
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(int_srxIss_i_1_n_0),
        .Q(int_srxIss),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2889" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    int_zqIss_i_1
       (.I0(\refSt_reg[3]_0 [2]),
        .I1(\refSt_reg[3]_0 [3]),
        .I2(\refSt_reg[3]_0 [0]),
        .I3(\refSt_reg[3]_0 [1]),
        .O(int_zqIss_i_1_n_0));
  FDRE int_zqIss_reg
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(int_zqIss_i_1_n_0),
        .Q(zqIss),
        .R(out));
  LUT6 #(
    .INIT(64'h00000000BB0F0FBB)) 
    \mc_ADR7[10]_i_1 
       (.I0(\mc_ADR7[10]_i_2_n_0 ),
        .I1(zqIss),
        .I2(tranSentC),
        .I3(winRead),
        .I4(winWrite),
        .I5(\mc_CS_n7_reg[0] ),
        .O(int_zqIss_reg_0));
  LUT3 #(
    .INIT(8'hFE)) 
    \mc_ADR7[10]_i_2 
       (.I0(int_sreIss),
        .I1(refIss),
        .I2(preIss),
        .O(\mc_ADR7[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00AA00FE00AA00FF)) 
    \mc_ADR7[14]_i_1 
       (.I0(d_prevGroup),
        .I1(int_sreIss),
        .I2(refIss),
        .I3(\mc_CS_n7_reg[0] ),
        .I4(preIss),
        .I5(zqIss),
        .O(um_sreIss_reg_0[0]));
  LUT6 #(
    .INIT(64'hEFFEEFFEEFFEFFFF)) 
    \mc_ADR7[15]_i_1 
       (.I0(\mc_CS_n7_reg[0] ),
        .I1(preIss),
        .I2(winWrite),
        .I3(winRead),
        .I4(int_sreIss),
        .I5(refIss),
        .O(um_sreIss_reg_0[1]));
  LUT6 #(
    .INIT(64'h000100FF00FF0001)) 
    \mc_ADR7[16]_i_1 
       (.I0(int_sreIss),
        .I1(refIss),
        .I2(preIss),
        .I3(\mc_CS_n7_reg[0] ),
        .I4(winWrite),
        .I5(winRead),
        .O(um_sreIss_reg_0[2]));
  (* SOFT_HLUTNM = "soft_lutpair2888" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \mc_CKE7[0]_i_1 
       (.I0(int_sreIss),
        .I1(int_sreCkeDis),
        .I2(um_sreCkeDis),
        .O(mc_CKE[1]));
  LUT6 #(
    .INIT(64'h00000000FFFF080B)) 
    \mc_CS_n7[0]_i_1 
       (.I0(int_srxIss),
        .I1(\mc_CS_n7[0]_i_2_n_0 ),
        .I2(preIss),
        .I3(zqIss),
        .I4(d_prevGroup),
        .I5(\mc_CS_n7_reg[0] ),
        .O(mc_CS_n));
  LUT2 #(
    .INIT(4'hE)) 
    \mc_CS_n7[0]_i_2 
       (.I0(refIss),
        .I1(int_sreIss),
        .O(\mc_CS_n7[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2888" *) 
  LUT4 #(
    .INIT(16'hFF01)) 
    \mcal_CKE_dly[0][6]_i_2 
       (.I0(um_sreCkeDis),
        .I1(int_sreCkeDis),
        .I2(int_srxIss),
        .I3(int_sreIss),
        .O(mc_CKE[0]));
  LUT6 #(
    .INIT(64'h9669699669969669)) 
    \mcal_PAR_dly[0][7]_i_5 
       (.I0(mc_BA),
        .I1(um_sreIss_reg_0[2]),
        .I2(um_sreIss_reg_0[0]),
        .I3(um_sreIss_reg_0[1]),
        .I4(mc_ADR),
        .I5(int_zqIss_reg_0),
        .O(\winPort_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair2879" *) 
  LUT3 #(
    .INIT(8'h96)) 
    \pend_ref[0][0]_i_1 
       (.I0(preIss),
        .I1(inc_pend_ref),
        .I2(\pend_ref_reg_n_0_[0][0] ),
        .O(\pend_ref[0][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFA96A)) 
    \pend_ref[0][1]_i_1 
       (.I0(\pend_ref_reg_n_0_[0][1] ),
        .I1(inc_pend_ref),
        .I2(\pend_ref_reg_n_0_[0][0] ),
        .I3(preIss),
        .I4(p_4_out),
        .O(\pend_ref[0][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2887" *) 
  LUT4 #(
    .INIT(16'h0220)) 
    \pend_ref[0][1]_i_2 
       (.I0(\refSt_reg[3]_0 [3]),
        .I1(\refSt_reg[3]_0 [2]),
        .I2(\refSt_reg[3]_0 [0]),
        .I3(\refSt_reg[3]_0 [1]),
        .O(p_4_out));
  (* SOFT_HLUTNM = "soft_lutpair2879" *) 
  LUT5 #(
    .INIT(32'hBFFD4002)) 
    \pend_ref[0][2]_i_1 
       (.I0(preIss),
        .I1(inc_pend_ref),
        .I2(\pend_ref_reg_n_0_[0][0] ),
        .I3(\pend_ref_reg_n_0_[0][1] ),
        .I4(\pend_ref_reg_n_0_[0][2] ),
        .O(\pend_ref[0][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAABEAAAA)) 
    \pend_ref[0][3]_i_1 
       (.I0(out),
        .I1(\refSt_reg[3]_0 [1]),
        .I2(\refSt_reg[3]_0 [0]),
        .I3(\refSt_reg[3]_0 [2]),
        .I4(\refSt_reg[3]_0 [3]),
        .O(pend_ref));
  LUT6 #(
    .INIT(64'hAA6AAAAAAAAAA9AA)) 
    \pend_ref[0][3]_i_2 
       (.I0(\pend_ref_reg_n_0_[0][3] ),
        .I1(\pend_ref_reg_n_0_[0][2] ),
        .I2(\pend_ref_reg_n_0_[0][1] ),
        .I3(preIss),
        .I4(inc_pend_ref),
        .I5(\pend_ref_reg_n_0_[0][0] ),
        .O(\pend_ref[0][3]_i_2_n_0 ));
  FDRE \pend_ref_reg[0][0] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\pend_ref[0][0]_i_1_n_0 ),
        .Q(\pend_ref_reg_n_0_[0][0] ),
        .R(pend_ref));
  FDRE \pend_ref_reg[0][1] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\pend_ref[0][1]_i_1_n_0 ),
        .Q(\pend_ref_reg_n_0_[0][1] ),
        .R(out));
  FDRE \pend_ref_reg[0][2] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\pend_ref[0][2]_i_1_n_0 ),
        .Q(\pend_ref_reg_n_0_[0][2] ),
        .R(pend_ref));
  FDRE \pend_ref_reg[0][3] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\pend_ref[0][3]_i_2_n_0 ),
        .Q(\pend_ref_reg_n_0_[0][3] ),
        .R(pend_ref));
  LUT6 #(
    .INIT(64'hFFCFF00FF0FAFFF0)) 
    \refSt[0]_i_1 
       (.I0(retSt[0]),
        .I1(zq_pending),
        .I2(\refSt_reg[3]_0 [2]),
        .I3(\refSt_reg[3]_0 [3]),
        .I4(\refSt_reg[3]_0 [0]),
        .I5(\refSt_reg[3]_0 [1]),
        .O(\refSt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000BFFBBFBB)) 
    \refSt[1]_i_1 
       (.I0(\refSt_reg[3]_0 [2]),
        .I1(\refSt_reg[3]_0 [3]),
        .I2(\refSt_reg[3]_0 [1]),
        .I3(\refSt_reg[3]_0 [0]),
        .I4(\refSt_reg[1]_0 ),
        .I5(\refSt[1]_i_2_n_0 ),
        .O(\refSt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000088FFCC0C)) 
    \refSt[1]_i_2 
       (.I0(zq_pending),
        .I1(\refSt_reg[3]_0 [0]),
        .I2(retSt[1]),
        .I3(\refSt_reg[3]_0 [1]),
        .I4(\refSt_reg[3]_0 [2]),
        .I5(\refSt_reg[3]_0 [3]),
        .O(\refSt[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAA00AA40EE00AA40)) 
    \refSt[2]_i_1 
       (.I0(\refSt_reg[3]_0 [3]),
        .I1(\refSt_reg[3]_0 [0]),
        .I2(retSt[2]),
        .I3(\refSt_reg[3]_0 [2]),
        .I4(\refSt_reg[3]_0 [1]),
        .I5(zq_pending),
        .O(\refSt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFF4F0F0F0F4F0)) 
    \refSt[3]_i_1 
       (.I0(\cntr_reg_n_0_[9] ),
        .I1(\refSt[3]_i_3_n_0 ),
        .I2(\refSt[3]_i_4_n_0 ),
        .I3(\refSt_reg[3]_0 [0]),
        .I4(\refSt_reg[3]_0 [1]),
        .I5(\pend_ref_reg[0][0]_0 ),
        .O(\refSt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCC08CCF0CC08CCC0)) 
    \refSt[3]_i_2 
       (.I0(\refSt_reg[1]_0 ),
        .I1(\refSt_reg[3]_0 [3]),
        .I2(\refSt_reg[3]_0 [0]),
        .I3(\refSt_reg[3]_0 [2]),
        .I4(\refSt_reg[3]_0 [1]),
        .I5(retSt[3]),
        .O(\refSt[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2881" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \refSt[3]_i_3 
       (.I0(\cntr_reg_n_0_[7] ),
        .I1(\cntr_reg_n_0_[6] ),
        .I2(\cntr[7]_i_3_n_0 ),
        .I3(\cntr_reg_n_0_[8] ),
        .O(\refSt[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFA00C)) 
    \refSt[3]_i_4 
       (.I0(\um_wait_cntr_reg[7]_0 ),
        .I1(\refSt_reg[1]_0 ),
        .I2(\refSt_reg[3]_0 [0]),
        .I3(\refSt_reg[3]_0 [1]),
        .I4(\refSt_reg[3]_0 [2]),
        .I5(\refSt_reg[3]_0 [3]),
        .O(\refSt[3]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h0000FFFE)) 
    \refSt[3]_i_5 
       (.I0(\pend_ref_reg_n_0_[0][0] ),
        .I1(\pend_ref_reg_n_0_[0][3] ),
        .I2(\pend_ref_reg_n_0_[0][2] ),
        .I3(\pend_ref_reg_n_0_[0][1] ),
        .I4(\refSt_reg[0]_0 ),
        .O(\pend_ref_reg[0][0]_0 ));
  FDRE \refSt_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(\refSt[3]_i_1_n_0 ),
        .D(\refSt[0]_i_1_n_0 ),
        .Q(\refSt_reg[3]_0 [0]),
        .R(out));
  FDRE \refSt_reg[1] 
       (.C(um_sreIss_reg_1),
        .CE(\refSt[3]_i_1_n_0 ),
        .D(\refSt[1]_i_1_n_0 ),
        .Q(\refSt_reg[3]_0 [1]),
        .R(out));
  FDRE \refSt_reg[2] 
       (.C(um_sreIss_reg_1),
        .CE(\refSt[3]_i_1_n_0 ),
        .D(\refSt[2]_i_1_n_0 ),
        .Q(\refSt_reg[3]_0 [2]),
        .R(out));
  FDRE \refSt_reg[3] 
       (.C(um_sreIss_reg_1),
        .CE(\refSt[3]_i_1_n_0 ),
        .D(\refSt[3]_i_2_n_0 ),
        .Q(\refSt_reg[3]_0 [3]),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2883" *) 
  LUT3 #(
    .INIT(8'hBE)) 
    \refi[0][0]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi_reg_n_0_[0][0] ),
        .I2(\refSt_reg[1]_0 ),
        .O(p_0_out[0]));
  LUT6 #(
    .INIT(64'h5555555400000001)) 
    \refi[0][10]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi_reg_n_0_[0][9] ),
        .I2(\refi_reg_n_0_[0][7] ),
        .I3(\refi[0][10]_i_2_n_0 ),
        .I4(\refi_reg_n_0_[0][8] ),
        .I5(\refi_reg_n_0_[0][10] ),
        .O(\refi[0][10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2882" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \refi[0][10]_i_2 
       (.I0(\refi_reg_n_0_[0][6] ),
        .I1(\refi[0][6]_i_2_n_0 ),
        .I2(\refi_reg_n_0_[0][5] ),
        .O(\refi[0][10]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2891" *) 
  LUT3 #(
    .INIT(8'hEB)) 
    \refi[0][11]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi[0][14]_i_2_n_0 ),
        .I2(\refi_reg_n_0_[0][11] ),
        .O(p_0_out[11]));
  (* SOFT_HLUTNM = "soft_lutpair2868" *) 
  LUT4 #(
    .INIT(16'h4441)) 
    \refi[0][12]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi_reg_n_0_[0][12] ),
        .I2(\refi[0][14]_i_2_n_0 ),
        .I3(\refi_reg_n_0_[0][11] ),
        .O(\refi[0][12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2868" *) 
  LUT5 #(
    .INIT(32'h55540001)) 
    \refi[0][13]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi[0][14]_i_2_n_0 ),
        .I2(\refi_reg_n_0_[0][12] ),
        .I3(\refi_reg_n_0_[0][11] ),
        .I4(\refi_reg_n_0_[0][13] ),
        .O(\refi[0][13]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAAA9)) 
    \refi[0][14]_i_1 
       (.I0(\refi_reg_n_0_[0][14] ),
        .I1(\refi[0][14]_i_2_n_0 ),
        .I2(\refi_reg_n_0_[0][12] ),
        .I3(\refi_reg_n_0_[0][11] ),
        .I4(\refi_reg_n_0_[0][13] ),
        .I5(\refi[0][14]_i_3_n_0 ),
        .O(p_0_out[14]));
  (* SOFT_HLUTNM = "soft_lutpair2867" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \refi[0][14]_i_2 
       (.I0(\refi_reg_n_0_[0][7] ),
        .I1(\refi_reg_n_0_[0][10] ),
        .I2(\refi_reg_n_0_[0][8] ),
        .I3(\refi_reg_n_0_[0][9] ),
        .I4(\refi[0][10]_i_2_n_0 ),
        .O(\refi[0][14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    \refi[0][14]_i_3 
       (.I0(\refi[0][14]_i_4_n_0 ),
        .I1(\refi[0][14]_i_5_n_0 ),
        .I2(\refi_reg_n_0_[0][14] ),
        .I3(\refi_reg_n_0_[0][6] ),
        .I4(\refi_reg_n_0_[0][0] ),
        .I5(\refi[0][14]_i_6_n_0 ),
        .O(\refi[0][14]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \refi[0][14]_i_4 
       (.I0(\refi_reg_n_0_[0][12] ),
        .I1(\refi_reg_n_0_[0][11] ),
        .I2(\refi_reg_n_0_[0][5] ),
        .I3(\refi_reg_n_0_[0][2] ),
        .O(\refi[0][14]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \refi[0][14]_i_5 
       (.I0(\refi_reg_n_0_[0][4] ),
        .I1(\refi_reg_n_0_[0][1] ),
        .I2(\refi_reg_n_0_[0][13] ),
        .I3(\refi_reg_n_0_[0][3] ),
        .O(\refi[0][14]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2867" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \refi[0][14]_i_6 
       (.I0(\refi_reg_n_0_[0][9] ),
        .I1(\refi_reg_n_0_[0][8] ),
        .I2(\refi_reg_n_0_[0][10] ),
        .I3(\refi_reg_n_0_[0][7] ),
        .O(\refi[0][14]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2883" *) 
  LUT4 #(
    .INIT(16'hEFBA)) 
    \refi[0][1]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi_reg_n_0_[0][0] ),
        .I2(\refSt_reg[1]_0 ),
        .I3(\refi_reg_n_0_[0][1] ),
        .O(p_0_out[1]));
  LUT5 #(
    .INIT(32'h55450010)) 
    \refi[0][2]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi_reg_n_0_[0][1] ),
        .I2(\refSt_reg[1]_0 ),
        .I3(\refi_reg_n_0_[0][0] ),
        .I4(\refi_reg_n_0_[0][2] ),
        .O(p_0_out[2]));
  LUT6 #(
    .INIT(64'h5555545500000100)) 
    \refi[0][3]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi_reg_n_0_[0][2] ),
        .I2(\refi_reg_n_0_[0][0] ),
        .I3(\refSt_reg[1]_0 ),
        .I4(\refi_reg_n_0_[0][1] ),
        .I5(\refi_reg_n_0_[0][3] ),
        .O(p_0_out[3]));
  LUT3 #(
    .INIT(8'h41)) 
    \refi[0][4]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi[0][4]_i_2_n_0 ),
        .I2(\refi_reg_n_0_[0][4] ),
        .O(\refi[0][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFEF)) 
    \refi[0][4]_i_2 
       (.I0(\refi_reg_n_0_[0][3] ),
        .I1(\refi_reg_n_0_[0][1] ),
        .I2(\refSt_reg[1]_0 ),
        .I3(\refi_reg_n_0_[0][0] ),
        .I4(\refi_reg_n_0_[0][2] ),
        .O(\refi[0][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2891" *) 
  LUT3 #(
    .INIT(8'hEB)) 
    \refi[0][5]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi[0][6]_i_2_n_0 ),
        .I2(\refi_reg_n_0_[0][5] ),
        .O(\refi[0][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2882" *) 
  LUT4 #(
    .INIT(16'h5401)) 
    \refi[0][6]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi_reg_n_0_[0][5] ),
        .I2(\refi[0][6]_i_2_n_0 ),
        .I3(\refi_reg_n_0_[0][6] ),
        .O(\refi[0][6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \refi[0][6]_i_2 
       (.I0(\refi_reg_n_0_[0][4] ),
        .I1(\refi_reg_n_0_[0][2] ),
        .I2(\refi_reg_n_0_[0][0] ),
        .I3(\refSt_reg[1]_0 ),
        .I4(\refi_reg_n_0_[0][1] ),
        .I5(\refi_reg_n_0_[0][3] ),
        .O(\refi[0][6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2869" *) 
  LUT3 #(
    .INIT(8'h41)) 
    \refi[0][7]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi[0][10]_i_2_n_0 ),
        .I2(\refi_reg_n_0_[0][7] ),
        .O(\refi[0][7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFEAB)) 
    \refi[0][8]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi_reg_n_0_[0][7] ),
        .I2(\refi[0][10]_i_2_n_0 ),
        .I3(\refi_reg_n_0_[0][8] ),
        .O(\refi[0][8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2869" *) 
  LUT5 #(
    .INIT(32'h55540001)) 
    \refi[0][9]_i_1 
       (.I0(\refi[0][14]_i_3_n_0 ),
        .I1(\refi_reg_n_0_[0][8] ),
        .I2(\refi[0][10]_i_2_n_0 ),
        .I3(\refi_reg_n_0_[0][7] ),
        .I4(\refi_reg_n_0_[0][9] ),
        .O(\refi[0][9]_i_1_n_0 ));
  FDRE \refi_reg[0][0] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(p_0_out[0]),
        .Q(\refi_reg_n_0_[0][0] ),
        .R(out));
  FDRE \refi_reg[0][10] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\refi[0][10]_i_1_n_0 ),
        .Q(\refi_reg_n_0_[0][10] ),
        .R(out));
  FDSE \refi_reg[0][11] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(p_0_out[11]),
        .Q(\refi_reg_n_0_[0][11] ),
        .S(out));
  FDRE \refi_reg[0][12] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\refi[0][12]_i_1_n_0 ),
        .Q(\refi_reg_n_0_[0][12] ),
        .R(out));
  FDRE \refi_reg[0][13] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\refi[0][13]_i_1_n_0 ),
        .Q(\refi_reg_n_0_[0][13] ),
        .R(out));
  FDRE \refi_reg[0][14] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(p_0_out[14]),
        .Q(\refi_reg_n_0_[0][14] ),
        .R(out));
  FDRE \refi_reg[0][1] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(p_0_out[1]),
        .Q(\refi_reg_n_0_[0][1] ),
        .R(out));
  FDSE \refi_reg[0][2] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(p_0_out[2]),
        .Q(\refi_reg_n_0_[0][2] ),
        .S(out));
  FDRE \refi_reg[0][3] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(p_0_out[3]),
        .Q(\refi_reg_n_0_[0][3] ),
        .R(out));
  FDRE \refi_reg[0][4] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\refi[0][4]_i_1_n_0 ),
        .Q(\refi_reg_n_0_[0][4] ),
        .R(out));
  FDSE \refi_reg[0][5] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\refi[0][5]_i_1_n_0 ),
        .Q(\refi_reg_n_0_[0][5] ),
        .S(out));
  FDRE \refi_reg[0][6] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\refi[0][6]_i_1_n_0 ),
        .Q(\refi_reg_n_0_[0][6] ),
        .R(out));
  FDRE \refi_reg[0][7] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\refi[0][7]_i_1_n_0 ),
        .Q(\refi_reg_n_0_[0][7] ),
        .R(out));
  FDSE \refi_reg[0][8] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\refi[0][8]_i_1_n_0 ),
        .Q(\refi_reg_n_0_[0][8] ),
        .S(out));
  FDRE \refi_reg[0][9] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\refi[0][9]_i_1_n_0 ),
        .Q(\refi_reg_n_0_[0][9] ),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2895" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \refs[0]_i_1 
       (.I0(\refs_reg_n_0_[0] ),
        .I1(\refSt_reg[3]_0 [1]),
        .I2(\refSt_reg[3]_0 [0]),
        .O(\refs[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2878" *) 
  LUT4 #(
    .INIT(16'h0090)) 
    \refs[1]_i_1 
       (.I0(\refs_reg_n_0_[0] ),
        .I1(\refs_reg_n_0_[1] ),
        .I2(\refSt_reg[3]_0 [0]),
        .I3(\refSt_reg[3]_0 [3]),
        .O(\refs[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2878" *) 
  LUT5 #(
    .INIT(32'h44400004)) 
    \refs[2]_i_1 
       (.I0(\refSt_reg[3]_0 [3]),
        .I1(\refSt_reg[3]_0 [0]),
        .I2(\refs_reg_n_0_[0] ),
        .I3(\refs_reg_n_0_[1] ),
        .I4(\refs_reg_n_0_[2] ),
        .O(\refs[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h10000404)) 
    \refs[3]_i_1 
       (.I0(out),
        .I1(\refSt_reg[3]_0 [2]),
        .I2(\refSt_reg[3]_0 [3]),
        .I3(\refSt_reg[3]_0 [0]),
        .I4(\refSt_reg[3]_0 [1]),
        .O(\refs[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4040404040404004)) 
    \refs[3]_i_2 
       (.I0(\refSt_reg[3]_0 [3]),
        .I1(\refSt_reg[3]_0 [0]),
        .I2(\refs_reg_n_0_[3] ),
        .I3(\refs_reg_n_0_[0] ),
        .I4(\refs_reg_n_0_[1] ),
        .I5(\refs_reg_n_0_[2] ),
        .O(\refs[3]_i_2_n_0 ));
  FDRE \refs_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(\refs[3]_i_1_n_0 ),
        .D(\refs[0]_i_1_n_0 ),
        .Q(\refs_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \refs_reg[1] 
       (.C(um_sreIss_reg_1),
        .CE(\refs[3]_i_1_n_0 ),
        .D(\refs[1]_i_1_n_0 ),
        .Q(\refs_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \refs_reg[2] 
       (.C(um_sreIss_reg_1),
        .CE(\refs[3]_i_1_n_0 ),
        .D(\refs[2]_i_1_n_0 ),
        .Q(\refs_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \refs_reg[3] 
       (.C(um_sreIss_reg_1),
        .CE(\refs[3]_i_1_n_0 ),
        .D(\refs[3]_i_2_n_0 ),
        .Q(\refs_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2897" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \retSt[0]_i_1__0 
       (.I0(\refSt_reg[3]_0 [3]),
        .I1(\refSt_reg[3]_0 [1]),
        .O(\retSt[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2871" *) 
  LUT4 #(
    .INIT(16'h0A3A)) 
    \retSt[1]_i_1__0 
       (.I0(\refSt_reg[3]_0 [3]),
        .I1(\retSt[1]_i_2_n_0 ),
        .I2(\refSt_reg[3]_0 [0]),
        .I3(\refSt_reg[3]_0 [1]),
        .O(\retSt[1]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \retSt[1]_i_2 
       (.I0(\refs_reg_n_0_[0] ),
        .I1(\refs_reg_n_0_[1] ),
        .I2(\refs_reg_n_0_[3] ),
        .I3(\refs_reg_n_0_[2] ),
        .O(\retSt[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2895" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \retSt[2]_i_1__0 
       (.I0(\refSt_reg[3]_0 [1]),
        .I1(\refSt_reg[3]_0 [2]),
        .O(\retSt[2]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h09B80938)) 
    \retSt[3]_i_1__0 
       (.I0(\refSt_reg[3]_0 [0]),
        .I1(\refSt_reg[3]_0 [1]),
        .I2(\refSt_reg[3]_0 [2]),
        .I3(\refSt_reg[3]_0 [3]),
        .I4(zq_pending),
        .O(\retSt[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2897" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \retSt[3]_i_2__0 
       (.I0(\refSt_reg[3]_0 [2]),
        .I1(\refSt_reg[3]_0 [1]),
        .O(\retSt[3]_i_2__0_n_0 ));
  FDRE \retSt_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(\retSt[3]_i_1__0_n_0 ),
        .D(\retSt[0]_i_1__0_n_0 ),
        .Q(retSt[0]),
        .R(1'b0));
  FDRE \retSt_reg[1] 
       (.C(um_sreIss_reg_1),
        .CE(\retSt[3]_i_1__0_n_0 ),
        .D(\retSt[1]_i_1__0_n_0 ),
        .Q(retSt[1]),
        .R(1'b0));
  FDRE \retSt_reg[2] 
       (.C(um_sreIss_reg_1),
        .CE(\retSt[3]_i_1__0_n_0 ),
        .D(\retSt[2]_i_1__0_n_0 ),
        .Q(retSt[2]),
        .R(1'b0));
  FDRE \retSt_reg[3] 
       (.C(um_sreIss_reg_1),
        .CE(\retSt[3]_i_1__0_n_0 ),
        .D(\retSt[3]_i_2__0_n_0 ),
        .Q(retSt[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2892" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \um_rank_cntr[0]_i_1 
       (.I0(um_rank_cntr[0]),
        .I1(\um_rank_cntr[1]_i_2_n_0 ),
        .O(\um_rank_cntr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2892" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \um_rank_cntr[1]_i_1 
       (.I0(um_rank_cntr[1]),
        .I1(\um_rank_cntr[1]_i_2_n_0 ),
        .I2(um_rank_cntr[0]),
        .O(\um_rank_cntr[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0001089000010000)) 
    \um_rank_cntr[1]_i_2 
       (.I0(user_fsm[1]),
        .I1(user_fsm[0]),
        .I2(user_fsm[2]),
        .I3(user_fsm[3]),
        .I4(Q),
        .I5(\um_rank_cntr_reg[1]_0 ),
        .O(\um_rank_cntr[1]_i_2_n_0 ));
  FDRE \um_rank_cntr_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\um_rank_cntr[0]_i_1_n_0 ),
        .Q(um_rank_cntr[0]),
        .R(out));
  FDRE \um_rank_cntr_reg[1] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\um_rank_cntr[1]_i_1_n_0 ),
        .Q(um_rank_cntr[1]),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2866" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \um_sreCkeDis[0]_i_2 
       (.I0(user_fsm[3]),
        .I1(user_fsm[2]),
        .O(\user_fsm_reg[3]_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \um_sreCkeDis[0]_i_3 
       (.I0(user_fsm[0]),
        .I1(user_fsm[1]),
        .O(\user_fsm_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2886" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \um_sreCkeDis[0]_i_4 
       (.I0(um_rank_cntr[1]),
        .I1(um_rank_cntr[0]),
        .O(\um_rank_cntr_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFFFFFFFFFFFFF7F)) 
    \um_sreCkeDis[0]_i_5 
       (.I0(Q),
        .I1(\refSt_reg[1]_0 ),
        .I2(user_fsm[0]),
        .I3(user_fsm[1]),
        .I4(user_fsm[3]),
        .I5(user_fsm[2]),
        .O(\user_fsm_reg[4]_0 ));
  FDRE \um_sreCkeDis_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\um_sreCkeDis_reg[0]_0 ),
        .Q(um_sreCkeDis),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2874" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    um_sreIss_i_1
       (.I0(user_fsm[3]),
        .I1(user_fsm[2]),
        .I2(user_fsm[1]),
        .I3(Q),
        .I4(user_fsm[0]),
        .O(um_sreIss_i_1_n_0));
  FDRE um_sreIss_reg
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(um_sreIss_i_1_n_0),
        .Q(int_sreIss),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hF2F2F2F2FFF2F2F2)) 
    \um_wait_cntr[0]_i_1 
       (.I0(\um_wait_cntr[1]_i_3_n_0 ),
        .I1(\um_wait_cntr[2]_i_3_n_0 ),
        .I2(\um_wait_cntr[1]_i_4_n_0 ),
        .I3(\um_wait_cntr[8]_i_3_n_0 ),
        .I4(\um_wait_cntr[3]_i_2_n_0 ),
        .I5(um_wait_cntr[0]),
        .O(um_wait_cntr_nxt[0]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF606060)) 
    \um_wait_cntr[1]_i_1 
       (.I0(um_wait_cntr[1]),
        .I1(\um_wait_cntr[1]_i_2_n_0 ),
        .I2(\um_wait_cntr[8]_i_3_n_0 ),
        .I3(\um_wait_cntr[1]_i_3_n_0 ),
        .I4(\um_wait_cntr[6]_i_4_n_0 ),
        .I5(\um_wait_cntr[1]_i_4_n_0 ),
        .O(um_wait_cntr_nxt[1]));
  LUT2 #(
    .INIT(4'h2)) 
    \um_wait_cntr[1]_i_2 
       (.I0(\um_wait_cntr[3]_i_2_n_0 ),
        .I1(um_wait_cntr[0]),
        .O(\um_wait_cntr[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0020000200200000)) 
    \um_wait_cntr[1]_i_3 
       (.I0(user_fsm[0]),
        .I1(Q),
        .I2(user_fsm[2]),
        .I3(user_fsm[3]),
        .I4(user_fsm[1]),
        .I5(\um_wait_cntr_reg[7]_0 ),
        .O(\um_wait_cntr[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    \um_wait_cntr[1]_i_4 
       (.I0(user_fsm[1]),
        .I1(user_fsm[2]),
        .I2(user_fsm[3]),
        .I3(\um_rank_cntr_reg[1]_0 ),
        .I4(user_fsm[0]),
        .I5(Q),
        .O(\um_wait_cntr[1]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h90FF9090)) 
    \um_wait_cntr[2]_i_1 
       (.I0(um_wait_cntr[2]),
        .I1(\um_wait_cntr[2]_i_2_n_0 ),
        .I2(\um_wait_cntr[8]_i_3_n_0 ),
        .I3(\um_wait_cntr[2]_i_3_n_0 ),
        .I4(\um_wait_cntr[6]_i_3_n_0 ),
        .O(um_wait_cntr_nxt[2]));
  (* SOFT_HLUTNM = "soft_lutpair2880" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \um_wait_cntr[2]_i_2 
       (.I0(um_wait_cntr[1]),
        .I1(um_wait_cntr[0]),
        .I2(\um_wait_cntr[3]_i_2_n_0 ),
        .O(\um_wait_cntr[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2870" *) 
  LUT5 #(
    .INIT(32'h03FFFF55)) 
    \um_wait_cntr[2]_i_3 
       (.I0(\um_wait_cntr_reg[7]_0 ),
        .I1(um_rank_cntr[1]),
        .I2(um_rank_cntr[0]),
        .I3(user_fsm[1]),
        .I4(user_fsm[2]),
        .O(\um_wait_cntr[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAA8A00000020)) 
    \um_wait_cntr[3]_i_1 
       (.I0(\um_wait_cntr[8]_i_3_n_0 ),
        .I1(um_wait_cntr[2]),
        .I2(\um_wait_cntr[3]_i_2_n_0 ),
        .I3(um_wait_cntr[0]),
        .I4(um_wait_cntr[1]),
        .I5(um_wait_cntr[3]),
        .O(um_wait_cntr_nxt[3]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \um_wait_cntr[3]_i_2 
       (.I0(\um_wait_cntr[3]_i_3_n_0 ),
        .I1(um_wait_cntr[8]),
        .I2(um_wait_cntr[7]),
        .I3(um_wait_cntr[2]),
        .I4(um_wait_cntr[0]),
        .I5(um_wait_cntr[1]),
        .O(\um_wait_cntr[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2865" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \um_wait_cntr[3]_i_3 
       (.I0(um_wait_cntr[4]),
        .I1(um_wait_cntr[3]),
        .I2(um_wait_cntr[6]),
        .I3(um_wait_cntr[5]),
        .O(\um_wait_cntr[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFA900A900A900)) 
    \um_wait_cntr[4]_i_1 
       (.I0(um_wait_cntr[4]),
        .I1(\um_wait_cntr[5]_i_3_n_0 ),
        .I2(um_wait_cntr[3]),
        .I3(\um_wait_cntr[8]_i_3_n_0 ),
        .I4(\um_wait_cntr[4]_i_2_n_0 ),
        .I5(\um_wait_cntr[6]_i_3_n_0 ),
        .O(um_wait_cntr_nxt[4]));
  (* SOFT_HLUTNM = "soft_lutpair2870" *) 
  LUT4 #(
    .INIT(16'h8880)) 
    \um_wait_cntr[4]_i_2 
       (.I0(user_fsm[2]),
        .I1(user_fsm[1]),
        .I2(um_rank_cntr[0]),
        .I3(um_rank_cntr[1]),
        .O(\um_wait_cntr[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEEBAAAAAAAA)) 
    \um_wait_cntr[5]_i_1 
       (.I0(\um_wait_cntr[5]_i_2_n_0 ),
        .I1(um_wait_cntr[5]),
        .I2(\um_wait_cntr[5]_i_3_n_0 ),
        .I3(um_wait_cntr[3]),
        .I4(um_wait_cntr[4]),
        .I5(\um_wait_cntr[8]_i_3_n_0 ),
        .O(um_wait_cntr_nxt[5]));
  (* SOFT_HLUTNM = "soft_lutpair2874" *) 
  LUT5 #(
    .INIT(32'h00680000)) 
    \um_wait_cntr[5]_i_2 
       (.I0(user_fsm[2]),
        .I1(user_fsm[3]),
        .I2(user_fsm[1]),
        .I3(Q),
        .I4(user_fsm[0]),
        .O(\um_wait_cntr[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2880" *) 
  LUT4 #(
    .INIT(16'hFFFB)) 
    \um_wait_cntr[5]_i_3 
       (.I0(um_wait_cntr[2]),
        .I1(\um_wait_cntr[3]_i_2_n_0 ),
        .I2(um_wait_cntr[0]),
        .I3(um_wait_cntr[1]),
        .O(\um_wait_cntr[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF828882888288)) 
    \um_wait_cntr[6]_i_1 
       (.I0(\um_wait_cntr[8]_i_3_n_0 ),
        .I1(um_wait_cntr[6]),
        .I2(um_wait_cntr[5]),
        .I3(\um_wait_cntr[6]_i_2_n_0 ),
        .I4(\um_wait_cntr[6]_i_3_n_0 ),
        .I5(\um_wait_cntr[6]_i_4_n_0 ),
        .O(um_wait_cntr_nxt[6]));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \um_wait_cntr[6]_i_2 
       (.I0(um_wait_cntr[4]),
        .I1(um_wait_cntr[3]),
        .I2(um_wait_cntr[1]),
        .I3(um_wait_cntr[0]),
        .I4(\um_wait_cntr[3]_i_2_n_0 ),
        .I5(um_wait_cntr[2]),
        .O(\um_wait_cntr[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2893" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \um_wait_cntr[6]_i_3 
       (.I0(Q),
        .I1(user_fsm[0]),
        .I2(user_fsm[3]),
        .O(\um_wait_cntr[6]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2886" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \um_wait_cntr[6]_i_4 
       (.I0(um_rank_cntr[1]),
        .I1(um_rank_cntr[0]),
        .I2(user_fsm[1]),
        .I3(user_fsm[2]),
        .O(\um_wait_cntr[6]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h82)) 
    \um_wait_cntr[7]_i_1 
       (.I0(\um_wait_cntr[8]_i_3_n_0 ),
        .I1(\um_wait_cntr[8]_i_2_n_0 ),
        .I2(um_wait_cntr[7]),
        .O(um_wait_cntr_nxt[7]));
  LUT4 #(
    .INIT(16'hE100)) 
    \um_wait_cntr[8]_i_1 
       (.I0(um_wait_cntr[7]),
        .I1(\um_wait_cntr[8]_i_2_n_0 ),
        .I2(um_wait_cntr[8]),
        .I3(\um_wait_cntr[8]_i_3_n_0 ),
        .O(\um_wait_cntr[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2865" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \um_wait_cntr[8]_i_2 
       (.I0(um_wait_cntr[5]),
        .I1(um_wait_cntr[6]),
        .I2(um_wait_cntr[3]),
        .I3(um_wait_cntr[4]),
        .I4(\um_wait_cntr[5]_i_3_n_0 ),
        .O(\um_wait_cntr[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F55F5FF7)) 
    \um_wait_cntr[8]_i_3 
       (.I0(\user_fsm[4]_i_4_n_0 ),
        .I1(\um_wait_cntr_reg[7]_0 ),
        .I2(user_fsm[1]),
        .I3(user_fsm[3]),
        .I4(user_fsm[2]),
        .I5(\um_wait_cntr[1]_i_4_n_0 ),
        .O(\um_wait_cntr[8]_i_3_n_0 ));
  FDRE \um_wait_cntr_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(um_wait_cntr_nxt[0]),
        .Q(um_wait_cntr[0]),
        .R(out));
  FDRE \um_wait_cntr_reg[1] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(um_wait_cntr_nxt[1]),
        .Q(um_wait_cntr[1]),
        .R(out));
  FDRE \um_wait_cntr_reg[2] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(um_wait_cntr_nxt[2]),
        .Q(um_wait_cntr[2]),
        .R(out));
  FDRE \um_wait_cntr_reg[3] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(um_wait_cntr_nxt[3]),
        .Q(um_wait_cntr[3]),
        .R(out));
  FDRE \um_wait_cntr_reg[4] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(um_wait_cntr_nxt[4]),
        .Q(um_wait_cntr[4]),
        .R(out));
  FDRE \um_wait_cntr_reg[5] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(um_wait_cntr_nxt[5]),
        .Q(um_wait_cntr[5]),
        .R(out));
  FDRE \um_wait_cntr_reg[6] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(um_wait_cntr_nxt[6]),
        .Q(um_wait_cntr[6]),
        .R(out));
  FDRE \um_wait_cntr_reg[7] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(um_wait_cntr_nxt[7]),
        .Q(um_wait_cntr[7]),
        .R(out));
  FDRE \um_wait_cntr_reg[8] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\um_wait_cntr[8]_i_1_n_0 ),
        .Q(um_wait_cntr[8]),
        .R(out));
  LUT6 #(
    .INIT(64'hFFFFFFFF005500D5)) 
    \user_fsm[0]_i_1 
       (.I0(\user_fsm[0]_i_2_n_0 ),
        .I1(\user_fsm[0]_i_3_n_0 ),
        .I2(user_fsm[3]),
        .I3(Q),
        .I4(\user_fsm[0]_i_4_n_0 ),
        .I5(\user_fsm[4]_i_5_n_0 ),
        .O(\user_fsm[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFE000FFFFFF0F)) 
    \user_fsm[0]_i_2 
       (.I0(um_rank_cntr[0]),
        .I1(um_rank_cntr[1]),
        .I2(user_fsm[1]),
        .I3(user_fsm[0]),
        .I4(user_fsm[3]),
        .I5(user_fsm[2]),
        .O(\user_fsm[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2890" *) 
  LUT3 #(
    .INIT(8'h15)) 
    \user_fsm[0]_i_3 
       (.I0(user_fsm[2]),
        .I1(user_fsm[1]),
        .I2(user_fsm[0]),
        .O(\user_fsm[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2890" *) 
  LUT3 #(
    .INIT(8'h15)) 
    \user_fsm[0]_i_4 
       (.I0(user_fsm[1]),
        .I1(user_fsm[0]),
        .I2(\um_wait_cntr[3]_i_2_n_0 ),
        .O(\user_fsm[0]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2872" *) 
  LUT5 #(
    .INIT(32'hFFFF0407)) 
    \user_fsm[1]_i_1 
       (.I0(\user_fsm[1]_i_2_n_0 ),
        .I1(user_fsm[3]),
        .I2(Q),
        .I3(\user_fsm[1]_i_3_n_0 ),
        .I4(\user_fsm[3]_i_2_n_0 ),
        .O(\user_fsm[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2875" *) 
  LUT5 #(
    .INIT(32'hFF00A8AA)) 
    \user_fsm[1]_i_2 
       (.I0(user_fsm[0]),
        .I1(um_rank_cntr[1]),
        .I2(um_rank_cntr[0]),
        .I3(user_fsm[1]),
        .I4(user_fsm[2]),
        .O(\user_fsm[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2875" *) 
  LUT5 #(
    .INIT(32'hF0F1F000)) 
    \user_fsm[1]_i_3 
       (.I0(um_rank_cntr[0]),
        .I1(um_rank_cntr[1]),
        .I2(user_fsm[0]),
        .I3(user_fsm[1]),
        .I4(user_fsm[2]),
        .O(\user_fsm[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF4D490000)) 
    \user_fsm[2]_i_1 
       (.I0(user_fsm[2]),
        .I1(user_fsm[0]),
        .I2(user_fsm[1]),
        .I3(\um_wait_cntr[3]_i_2_n_0 ),
        .I4(\user_fsm[2]_i_2_n_0 ),
        .I5(\user_fsm[2]_i_3_n_0 ),
        .O(\user_fsm[2]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \user_fsm[2]_i_2 
       (.I0(user_fsm[3]),
        .I1(Q),
        .O(\user_fsm[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBEEAAAAABFEAAAAA)) 
    \user_fsm[2]_i_3 
       (.I0(\user_fsm[3]_i_2_n_0 ),
        .I1(user_fsm[0]),
        .I2(user_fsm[1]),
        .I3(user_fsm[2]),
        .I4(\user_fsm[2]_i_4_n_0 ),
        .I5(\um_rank_cntr_reg[1]_0 ),
        .O(\user_fsm[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2872" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \user_fsm[2]_i_4 
       (.I0(Q),
        .I1(user_fsm[3]),
        .O(\user_fsm[2]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \user_fsm[3]_i_1 
       (.I0(\user_fsm[3]_i_2_n_0 ),
        .I1(\user_fsm[3]_i_3_n_0 ),
        .O(\user_fsm[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2866" *) 
  LUT5 #(
    .INIT(32'h00010000)) 
    \user_fsm[3]_i_2 
       (.I0(\user_fsm[4]_i_6_n_0 ),
        .I1(user_fsm[2]),
        .I2(user_fsm[3]),
        .I3(user_fsm[1]),
        .I4(Q),
        .O(\user_fsm[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0544540005445000)) 
    \user_fsm[3]_i_3 
       (.I0(Q),
        .I1(user_fsm[0]),
        .I2(user_fsm[1]),
        .I3(user_fsm[3]),
        .I4(user_fsm[2]),
        .I5(\um_wait_cntr[3]_i_2_n_0 ),
        .O(\user_fsm[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hF0F4F0F4FFFFFFF4)) 
    \user_fsm[4]_i_1 
       (.I0(user_fsm[0]),
        .I1(user_fsm[2]),
        .I2(\user_fsm[4]_i_3_n_0 ),
        .I3(user_fsm[3]),
        .I4(user_fsm[1]),
        .I5(\um_wait_cntr[3]_i_2_n_0 ),
        .O(\user_fsm[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF800080008000)) 
    \user_fsm[4]_i_2 
       (.I0(\user_fsm[4]_i_4_n_0 ),
        .I1(user_fsm[1]),
        .I2(user_fsm[2]),
        .I3(user_fsm[3]),
        .I4(\user_fsm[4]_i_5_n_0 ),
        .I5(\user_fsm[4]_i_6_n_0 ),
        .O(\user_fsm[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFEFEEFEEAEAEAAAA)) 
    \user_fsm[4]_i_3 
       (.I0(Q),
        .I1(user_fsm[1]),
        .I2(user_fsm[2]),
        .I3(\um_wait_cntr_reg[7]_0 ),
        .I4(user_fsm[3]),
        .I5(user_fsm[0]),
        .O(\user_fsm[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2893" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \user_fsm[4]_i_4 
       (.I0(user_fsm[0]),
        .I1(Q),
        .O(\user_fsm[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000D00000000)) 
    \user_fsm[4]_i_5 
       (.I0(user_fsm[0]),
        .I1(\refSt_reg[1]_0 ),
        .I2(user_fsm[2]),
        .I3(user_fsm[3]),
        .I4(user_fsm[1]),
        .I5(Q),
        .O(\user_fsm[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFABABFFAB)) 
    \user_fsm[4]_i_6 
       (.I0(um_sreCkeDis),
        .I1(um_rank_cntr[1]),
        .I2(um_rank_cntr[0]),
        .I3(user_fsm[0]),
        .I4(user_fsm[1]),
        .I5(user_fsm[2]),
        .O(\user_fsm[4]_i_6_n_0 ));
  FDRE \user_fsm_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(\user_fsm[4]_i_1_n_0 ),
        .D(\user_fsm[0]_i_1_n_0 ),
        .Q(user_fsm[0]),
        .R(out));
  FDRE \user_fsm_reg[1] 
       (.C(um_sreIss_reg_1),
        .CE(\user_fsm[4]_i_1_n_0 ),
        .D(\user_fsm[1]_i_1_n_0 ),
        .Q(user_fsm[1]),
        .R(out));
  FDRE \user_fsm_reg[2] 
       (.C(um_sreIss_reg_1),
        .CE(\user_fsm[4]_i_1_n_0 ),
        .D(\user_fsm[2]_i_1_n_0 ),
        .Q(user_fsm[2]),
        .R(out));
  FDRE \user_fsm_reg[3] 
       (.C(um_sreIss_reg_1),
        .CE(\user_fsm[4]_i_1_n_0 ),
        .D(\user_fsm[3]_i_1_n_0 ),
        .Q(user_fsm[3]),
        .R(out));
  FDRE \user_fsm_reg[4] 
       (.C(um_sreIss_reg_1),
        .CE(\user_fsm[4]_i_1_n_0 ),
        .D(\user_fsm[4]_i_2_n_0 ),
        .Q(Q),
        .R(out));
  LUT2 #(
    .INIT(4'hE)) 
    \zq_intvl_count[15]_i_1 
       (.I0(out),
        .I1(\zq_pending[0]_i_2_n_0 ),
        .O(\zq_intvl_count[15]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[15]_i_10 
       (.I0(zq_intvl_count[8]),
        .O(\zq_intvl_count[15]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[15]_i_3 
       (.I0(zq_intvl_count[15]),
        .O(\zq_intvl_count[15]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[15]_i_4 
       (.I0(zq_intvl_count[14]),
        .O(\zq_intvl_count[15]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[15]_i_5 
       (.I0(zq_intvl_count[13]),
        .O(\zq_intvl_count[15]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[15]_i_6 
       (.I0(zq_intvl_count[12]),
        .O(\zq_intvl_count[15]_i_6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[15]_i_7 
       (.I0(zq_intvl_count[11]),
        .O(\zq_intvl_count[15]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[15]_i_8 
       (.I0(zq_intvl_count[10]),
        .O(\zq_intvl_count[15]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[15]_i_9 
       (.I0(zq_intvl_count[9]),
        .O(\zq_intvl_count[15]_i_9_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[7]_i_2 
       (.I0(zq_intvl_count[7]),
        .O(\zq_intvl_count[7]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[7]_i_3 
       (.I0(zq_intvl_count[6]),
        .O(\zq_intvl_count[7]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[7]_i_4 
       (.I0(zq_intvl_count[5]),
        .O(\zq_intvl_count[7]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[7]_i_5 
       (.I0(zq_intvl_count[4]),
        .O(\zq_intvl_count[7]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[7]_i_6 
       (.I0(zq_intvl_count[3]),
        .O(\zq_intvl_count[7]_i_6_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[7]_i_7 
       (.I0(zq_intvl_count[2]),
        .O(\zq_intvl_count[7]_i_7_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_intvl_count[7]_i_8 
       (.I0(zq_intvl_count[1]),
        .O(\zq_intvl_count[7]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \zq_intvl_count[7]_i_9 
       (.I0(zq_intvl_count[0]),
        .I1(refIss),
        .O(\zq_intvl_count[7]_i_9_n_0 ));
  FDSE \zq_intvl_count_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[0]),
        .Q(zq_intvl_count[0]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[10] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[10]),
        .Q(zq_intvl_count[10]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[11] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[11]),
        .Q(zq_intvl_count[11]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[12] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[12]),
        .Q(zq_intvl_count[12]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[13] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[13]),
        .Q(zq_intvl_count[13]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[14] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[14]),
        .Q(zq_intvl_count[14]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[15] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[15]),
        .Q(zq_intvl_count[15]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 \zq_intvl_count_reg[15]_i_2 
       (.CI(\zq_intvl_count_reg[7]_i_1_n_0 ),
        .CI_TOP(1'b0),
        .CO({\NLW_zq_intvl_count_reg[15]_i_2_CO_UNCONNECTED [7],\zq_intvl_count_reg[15]_i_2_n_1 ,\zq_intvl_count_reg[15]_i_2_n_2 ,\zq_intvl_count_reg[15]_i_2_n_3 ,\zq_intvl_count_reg[15]_i_2_n_4 ,\zq_intvl_count_reg[15]_i_2_n_5 ,\zq_intvl_count_reg[15]_i_2_n_6 ,\zq_intvl_count_reg[15]_i_2_n_7 }),
        .DI({1'b0,zq_intvl_count[14:8]}),
        .O(zq_intvl_count0[15:8]),
        .S({\zq_intvl_count[15]_i_3_n_0 ,\zq_intvl_count[15]_i_4_n_0 ,\zq_intvl_count[15]_i_5_n_0 ,\zq_intvl_count[15]_i_6_n_0 ,\zq_intvl_count[15]_i_7_n_0 ,\zq_intvl_count[15]_i_8_n_0 ,\zq_intvl_count[15]_i_9_n_0 ,\zq_intvl_count[15]_i_10_n_0 }));
  FDSE \zq_intvl_count_reg[1] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[1]),
        .Q(zq_intvl_count[1]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[2] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[2]),
        .Q(zq_intvl_count[2]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[3] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[3]),
        .Q(zq_intvl_count[3]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[4] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[4]),
        .Q(zq_intvl_count[4]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[5] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[5]),
        .Q(zq_intvl_count[5]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[6] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[6]),
        .Q(zq_intvl_count[6]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[7] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[7]),
        .Q(zq_intvl_count[7]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY8 \zq_intvl_count_reg[7]_i_1 
       (.CI(1'b1),
        .CI_TOP(1'b0),
        .CO({\zq_intvl_count_reg[7]_i_1_n_0 ,\zq_intvl_count_reg[7]_i_1_n_1 ,\zq_intvl_count_reg[7]_i_1_n_2 ,\zq_intvl_count_reg[7]_i_1_n_3 ,\zq_intvl_count_reg[7]_i_1_n_4 ,\zq_intvl_count_reg[7]_i_1_n_5 ,\zq_intvl_count_reg[7]_i_1_n_6 ,\zq_intvl_count_reg[7]_i_1_n_7 }),
        .DI(zq_intvl_count[7:0]),
        .O(zq_intvl_count0[7:0]),
        .S({\zq_intvl_count[7]_i_2_n_0 ,\zq_intvl_count[7]_i_3_n_0 ,\zq_intvl_count[7]_i_4_n_0 ,\zq_intvl_count[7]_i_5_n_0 ,\zq_intvl_count[7]_i_6_n_0 ,\zq_intvl_count[7]_i_7_n_0 ,\zq_intvl_count[7]_i_8_n_0 ,\zq_intvl_count[7]_i_9_n_0 }));
  FDSE \zq_intvl_count_reg[8] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[8]),
        .Q(zq_intvl_count[8]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  FDSE \zq_intvl_count_reg[9] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_intvl_count0[9]),
        .Q(zq_intvl_count[9]),
        .S(\zq_intvl_count[15]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h55550100)) 
    \zq_pending[0]_i_1 
       (.I0(zqIss),
        .I1(zq_rank[0]),
        .I2(zq_rank[1]),
        .I3(\zq_pending[0]_i_2_n_0 ),
        .I4(zq_pending),
        .O(zq_pending_nxt));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \zq_pending[0]_i_2 
       (.I0(\zq_pending[0]_i_3_n_0 ),
        .I1(zq_intvl_count[1]),
        .I2(zq_intvl_count[2]),
        .I3(zq_intvl_count[7]),
        .I4(zq_intvl_count[8]),
        .I5(\zq_pending[0]_i_4_n_0 ),
        .O(\zq_pending[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \zq_pending[0]_i_3 
       (.I0(zq_intvl_count[10]),
        .I1(zq_intvl_count[13]),
        .I2(zq_intvl_count[9]),
        .I3(zq_intvl_count[11]),
        .O(\zq_pending[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \zq_pending[0]_i_4 
       (.I0(zq_intvl_count[3]),
        .I1(zq_intvl_count[15]),
        .I2(zq_intvl_count[5]),
        .I3(zq_intvl_count[4]),
        .I4(\zq_pending[0]_i_5_n_0 ),
        .O(\zq_pending[0]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \zq_pending[0]_i_5 
       (.I0(zq_intvl_count[6]),
        .I1(zq_intvl_count[14]),
        .I2(zq_intvl_count[0]),
        .I3(zq_intvl_count[12]),
        .O(\zq_pending[0]_i_5_n_0 ));
  FDRE \zq_pending_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(zq_pending_nxt),
        .Q(zq_pending),
        .R(out));
  (* SOFT_HLUTNM = "soft_lutpair2896" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \zq_rank[0]_i_1 
       (.I0(zq_rank[0]),
        .I1(zqIss),
        .O(\zq_rank[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hABAA)) 
    \zq_rank[1]_i_1 
       (.I0(out),
        .I1(zq_rank[1]),
        .I2(zq_rank[0]),
        .I3(zqIss),
        .O(\zq_rank[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2896" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \zq_rank[1]_i_2 
       (.I0(zq_rank[1]),
        .I1(zqIss),
        .I2(zq_rank[0]),
        .O(\zq_rank[1]_i_2_n_0 ));
  FDRE \zq_rank_reg[0] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\zq_rank[0]_i_1_n_0 ),
        .Q(zq_rank[0]),
        .R(\zq_rank[1]_i_1_n_0 ));
  FDRE \zq_rank_reg[1] 
       (.C(um_sreIss_reg_1),
        .CE(1'b1),
        .D(\zq_rank[1]_i_2_n_0 ),
        .Q(zq_rank[1]),
        .R(\zq_rank[1]_i_1_n_0 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_mc_wtr" *) 
module ddr4_0_ddr4_v2_2_17_mc_wtr
   (wtr_oksr,
    wtr_oklr,
    \prevGr_reg[0]_0 ,
    Q,
    out,
    wtr_oklr_reg_0,
    \prevGr_reg[0]_1 ,
    tranSentC,
    winWrite,
    D);
  output wtr_oksr;
  output wtr_oklr;
  output \prevGr_reg[0]_0 ;
  output [0:0]Q;
  input out;
  input wtr_oklr_reg_0;
  input \prevGr_reg[0]_1 ;
  input tranSentC;
  input winWrite;
  input [0:0]D;

  wire [0:0]D;
  wire [0:0]Q;
  wire out;
  wire [3:1]p_1_in;
  wire \prevGr_reg[0]_0 ;
  wire \prevGr_reg[0]_1 ;
  wire tranSentC;
  wire winWrite;
  wire wtr_oklr;
  wire wtr_oklr_i_1_n_0;
  wire wtr_oklr_reg_0;
  wire wtr_oksr;
  wire wtr_oksr_i_1_n_0;
  wire [3:1]wtrl;
  wire \wtrl[3]_i_1_n_0 ;
  wire [3:0]wtrs;
  wire \wtrs[0]_i_1_n_0 ;
  wire \wtrs[1]_i_1_n_0 ;
  wire \wtrs[2]_i_1_n_0 ;
  wire \wtrs[3]_i_1_n_0 ;
  wire \wtrs[3]_i_2_n_0 ;

  FDRE \prevGr_reg[0] 
       (.C(wtr_oklr_reg_0),
        .CE(1'b1),
        .D(\prevGr_reg[0]_1 ),
        .Q(\prevGr_reg[0]_0 ),
        .R(out));
  LUT5 #(
    .INIT(32'h00010101)) 
    wtr_oklr_i_1
       (.I0(wtrl[3]),
        .I1(wtrl[2]),
        .I2(wtrl[1]),
        .I3(tranSentC),
        .I4(winWrite),
        .O(wtr_oklr_i_1_n_0));
  FDSE wtr_oklr_reg
       (.C(wtr_oklr_reg_0),
        .CE(1'b1),
        .D(wtr_oklr_i_1_n_0),
        .Q(wtr_oklr),
        .S(out));
  LUT5 #(
    .INIT(32'h00010101)) 
    wtr_oksr_i_1
       (.I0(wtrs[3]),
        .I1(wtrs[2]),
        .I2(wtrs[1]),
        .I3(tranSentC),
        .I4(winWrite),
        .O(wtr_oksr_i_1_n_0));
  FDSE wtr_oksr_reg
       (.C(wtr_oklr_reg_0),
        .CE(1'b1),
        .D(wtr_oksr_i_1_n_0),
        .Q(wtr_oksr),
        .S(out));
  (* SOFT_HLUTNM = "soft_lutpair2838" *) 
  LUT4 #(
    .INIT(16'h0999)) 
    \wtrl[1]_i_1 
       (.I0(Q),
        .I1(wtrl[1]),
        .I2(tranSentC),
        .I3(winWrite),
        .O(p_1_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair2838" *) 
  LUT5 #(
    .INIT(32'hFFF8888F)) 
    \wtrl[2]_i_1 
       (.I0(tranSentC),
        .I1(winWrite),
        .I2(wtrl[1]),
        .I3(Q),
        .I4(wtrl[2]),
        .O(p_1_in[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF8)) 
    \wtrl[3]_i_1 
       (.I0(tranSentC),
        .I1(winWrite),
        .I2(wtrl[1]),
        .I3(Q),
        .I4(wtrl[3]),
        .I5(wtrl[2]),
        .O(\wtrl[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000FE01FE01FE01)) 
    \wtrl[3]_i_2 
       (.I0(Q),
        .I1(wtrl[1]),
        .I2(wtrl[2]),
        .I3(wtrl[3]),
        .I4(tranSentC),
        .I5(winWrite),
        .O(p_1_in[3]));
  FDRE \wtrl_reg[0] 
       (.C(wtr_oklr_reg_0),
        .CE(\wtrl[3]_i_1_n_0 ),
        .D(D),
        .Q(Q),
        .R(out));
  FDRE \wtrl_reg[1] 
       (.C(wtr_oklr_reg_0),
        .CE(\wtrl[3]_i_1_n_0 ),
        .D(p_1_in[1]),
        .Q(wtrl[1]),
        .R(out));
  FDRE \wtrl_reg[2] 
       (.C(wtr_oklr_reg_0),
        .CE(\wtrl[3]_i_1_n_0 ),
        .D(p_1_in[2]),
        .Q(wtrl[2]),
        .R(out));
  FDRE \wtrl_reg[3] 
       (.C(wtr_oklr_reg_0),
        .CE(\wtrl[3]_i_1_n_0 ),
        .D(p_1_in[3]),
        .Q(wtrl[3]),
        .R(out));
  LUT3 #(
    .INIT(8'h15)) 
    \wtrs[0]_i_1 
       (.I0(wtrs[0]),
        .I1(tranSentC),
        .I2(winWrite),
        .O(\wtrs[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2839" *) 
  LUT4 #(
    .INIT(16'h7007)) 
    \wtrs[1]_i_1 
       (.I0(tranSentC),
        .I1(winWrite),
        .I2(wtrs[0]),
        .I3(wtrs[1]),
        .O(\wtrs[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2839" *) 
  LUT5 #(
    .INIT(32'hFFF8888F)) 
    \wtrs[2]_i_1 
       (.I0(tranSentC),
        .I1(winWrite),
        .I2(wtrs[1]),
        .I3(wtrs[0]),
        .I4(wtrs[2]),
        .O(\wtrs[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFEFE)) 
    \wtrs[3]_i_1 
       (.I0(wtrs[3]),
        .I1(wtrs[2]),
        .I2(wtrs[1]),
        .I3(winWrite),
        .I4(tranSentC),
        .I5(wtrs[0]),
        .O(\wtrs[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000FE01FE01FE01)) 
    \wtrs[3]_i_2 
       (.I0(wtrs[0]),
        .I1(wtrs[1]),
        .I2(wtrs[2]),
        .I3(wtrs[3]),
        .I4(tranSentC),
        .I5(winWrite),
        .O(\wtrs[3]_i_2_n_0 ));
  FDRE \wtrs_reg[0] 
       (.C(wtr_oklr_reg_0),
        .CE(\wtrs[3]_i_1_n_0 ),
        .D(\wtrs[0]_i_1_n_0 ),
        .Q(wtrs[0]),
        .R(out));
  FDRE \wtrs_reg[1] 
       (.C(wtr_oklr_reg_0),
        .CE(\wtrs[3]_i_1_n_0 ),
        .D(\wtrs[1]_i_1_n_0 ),
        .Q(wtrs[1]),
        .R(out));
  FDRE \wtrs_reg[2] 
       (.C(wtr_oklr_reg_0),
        .CE(\wtrs[3]_i_1_n_0 ),
        .D(\wtrs[2]_i_1_n_0 ),
        .Q(wtrs[2]),
        .R(out));
  FDRE \wtrs_reg[3] 
       (.C(wtr_oklr_reg_0),
        .CE(\wtrs[3]_i_1_n_0 ),
        .D(\wtrs[3]_i_2_n_0 ),
        .Q(wtrs[3]),
        .R(out));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_ui" *) 
module ddr4_0_ddr4_v2_2_17_ui
   (c0_ddr4_app_wdf_rdy,
    E,
    Q,
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4] ,
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4] ,
    DOA,
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0 ,
    DOB,
    DOC,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ,
    out,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] ,
    c0_ddr4_app_rd_data_valid,
    c0_ddr4_app_rd_data_end,
    \rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4] ,
    accept_reg,
    dBufAdr,
    useAdr,
    accept_reg_0,
    accept_reg_1,
    accept_reg_2,
    accept_reg_3,
    accept_reg_4,
    accept_reg_5,
    accept_reg_6,
    accept_reg_7,
    accept_reg_8,
    accept_reg_9,
    accept_reg_10,
    accept_reg_11,
    accept_reg_12,
    accept_reg_13,
    calDone_gated_reg,
    group,
    bank,
    periodic_read_or_ref_block_reg,
    \wr_buf_out_data_reg[575] ,
    c0_ddr4_app_rd_data,
    cmd,
    row_mc_phy,
    col,
    \rd_data_indx_r_reg[3] ,
    pointer_we,
    \wr_buffer_ram[8].RAM32M0 ,
    \wr_buffer_ram[40].RAM32M0 ,
    ADDRA,
    ADDRC,
    c0_ddr4_app_wdf_wren,
    c0_ddr4_app_wdf_end,
    SR,
    \rd_data_indx_r_reg[3]_0 ,
    D,
    ADDRD,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_2 ,
    in0,
    \not_strict_mode.app_rd_data_end_reg ,
    rd_data_en_phy2mc,
    \not_strict_mode.bypass_cpy2 ,
    match4_13_return,
    match6_13_return,
    match4_14_return,
    match6_14_return,
    match4_15_return,
    match6_15_return,
    match4_16_return,
    match6_16_return,
    match4_17_return,
    match6_17_return,
    match4_18_return,
    match6_18_return,
    match4_19_return,
    match6_19_return,
    match4_110_return,
    match6_110_return,
    match4_111_return,
    match6_111_return,
    match4_112_return,
    match6_112_return,
    match4_113_return,
    match6_113_return,
    match4_114_return,
    match6_114_return,
    match4_115_return,
    match6_115_return,
    match4_116_return,
    match6_116_return,
    match4_117_return,
    match6_117_return,
    match4_118_return,
    match6_118_return,
    match4_119_return,
    match6_119_return,
    match4_120_return,
    match6_120_return,
    match4_121_return,
    match6_121_return,
    match4_122_return,
    match6_122_return,
    match4_123_return,
    match6_123_return,
    match4_124_return,
    match6_124_return,
    match4_125_return,
    match6_125_return,
    match4_126_return,
    match6_126_return,
    match4_127_return,
    match6_127_return,
    match4_128_return,
    match6_128_return,
    match4_129_return,
    match6_129_return,
    match4_130_return,
    match6_130_return,
    match4_131_return,
    match6_131_return,
    match4_132_return,
    match6_132_return,
    match4_133_return,
    match6_133_return,
    match4_134_return,
    match6_134_return,
    match4_135_return,
    match6_135_return,
    match4_136_return,
    match6_136_return,
    match4_137_return,
    match6_137_return,
    match4_138_return,
    match6_138_return,
    match4_139_return,
    match6_139_return,
    match4_140_return,
    match6_140_return,
    match4_141_return,
    match6_141_return,
    match4_142_return,
    match6_142_return,
    match4_143_return,
    match6_143_return,
    match4_144_return,
    match6_144_return,
    match4_145_return,
    match6_145_return,
    match4_146_return,
    match6_146_return,
    match4_147_return,
    match6_147_return,
    match4_148_return,
    match6_148_return,
    match4_149_return,
    match6_149_return,
    match4_150_return,
    match6_150_return,
    match4_151_return,
    match6_151_return,
    match4_152_return,
    match6_152_return,
    match4_153_return,
    match6_153_return,
    match4_154_return,
    match6_154_return,
    match4_155_return,
    match6_155_return,
    match4_156_return,
    match6_156_return,
    match4_157_return,
    match6_157_return,
    match4_158_return,
    match6_158_return,
    match4_159_return,
    match6_159_return,
    match4_160_return,
    match6_160_return,
    match4_161_return,
    match6_161_return,
    match4_162_return,
    match6_162_return,
    match4_163_return,
    match6_163_return,
    match4_164_return,
    match6_164_return,
    match4_165_return,
    match6_165_return,
    match4_166_return,
    match6_166_return,
    match4_167_return,
    match6_167_return,
    match4_168_return,
    match6_168_return,
    match4_169_return,
    match6_169_return,
    match4_170_return,
    match6_170_return,
    match4_171_return,
    match6_171_return,
    match4_172_return,
    match6_172_return,
    match4_173_return,
    match6_173_return,
    match4_174_return,
    match6_174_return,
    match4_175_return,
    match6_175_return,
    match4_176_return,
    match6_176_return,
    match4_177_return,
    match6_177_return,
    match4_178_return,
    match6_178_return,
    match4_179_return,
    match6_179_return,
    match4_180_return,
    match6_180_return,
    match4_181_return,
    match6_181_return,
    match4_182_return,
    match6_182_return,
    match4_183_return,
    match6_183_return,
    match4_184_return,
    match6_184_return,
    match4_185_return,
    match6_185_return,
    match4_186_return,
    match6_186_return,
    match4_187_return,
    match6_187_return,
    match4_188_return,
    match6_188_return,
    match4_1_return,
    match6_1_return,
    match4_10_return,
    match6_10_return,
    match4_11_return,
    match6_11_return,
    match4_12_return,
    match6_12_return,
    \not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[4] ,
    \buf_fifo_reg[1][4] ,
    accept_reg_14,
    \buf_fifo_reg[1][0] ,
    \buf_fifo_reg[1][1] ,
    \buf_fifo_reg[1][2] ,
    \buf_fifo_reg[1][3] ,
    \buf_fifo_reg[1][4]_0 ,
    \buf_fifo_reg[1][4]_1 ,
    \buf_fifo_reg[1][0]_0 ,
    \buf_fifo_reg[1][1]_0 ,
    \buf_fifo_reg[1][2]_0 ,
    \buf_fifo_reg[1][3]_0 ,
    \buf_fifo_reg[1][4]_2 ,
    \buf_fifo_reg[1][4]_3 ,
    \buf_fifo_reg[1][0]_1 ,
    \buf_fifo_reg[1][1]_1 ,
    \buf_fifo_reg[1][2]_1 ,
    \buf_fifo_reg[1][3]_1 ,
    \buf_fifo_reg[1][4]_4 ,
    accept_reg_15,
    accept_reg_16,
    c0_ddr4_app_addr,
    c0_ddr4_app_cmd,
    c0_ddr4_app_wdf_data,
    c0_ddr4_app_wdf_mask,
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ,
    accept_ns,
    c0_ddr4_app_en);
  output c0_ddr4_app_wdf_rdy;
  output [0:0]E;
  output [4:0]Q;
  output [4:0]\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4] ;
  output [4:0]\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4] ;
  output [0:0]DOA;
  output [4:0]\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4] ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0 ;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ;
  output [0:0]out;
  output [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] ;
  output c0_ddr4_app_rd_data_valid;
  output c0_ddr4_app_rd_data_end;
  output [4:0]\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4] ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4] ;
  output accept_reg;
  output [4:0]dBufAdr;
  output useAdr;
  output accept_reg_0;
  output accept_reg_1;
  output accept_reg_2;
  output accept_reg_3;
  output accept_reg_4;
  output accept_reg_5;
  output accept_reg_6;
  output accept_reg_7;
  output accept_reg_8;
  output accept_reg_9;
  output accept_reg_10;
  output accept_reg_11;
  output accept_reg_12;
  output accept_reg_13;
  output [0:0]calDone_gated_reg;
  output [0:0]group;
  output [1:0]bank;
  output periodic_read_or_ref_block_reg;
  output [575:0]\wr_buf_out_data_reg[575] ;
  output [511:0]c0_ddr4_app_rd_data;
  output [2:0]cmd;
  output [16:0]row_mc_phy;
  output [6:0]col;
  input \rd_data_indx_r_reg[3] ;
  input pointer_we;
  input [3:0]\wr_buffer_ram[8].RAM32M0 ;
  input [3:0]\wr_buffer_ram[40].RAM32M0 ;
  input [3:0]ADDRA;
  input [3:0]ADDRC;
  input c0_ddr4_app_wdf_wren;
  input c0_ddr4_app_wdf_end;
  input [0:0]SR;
  input [0:0]\rd_data_indx_r_reg[3]_0 ;
  input [511:0]D;
  input [4:0]ADDRD;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_2 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_2 ;
  input [85:0]in0;
  input \not_strict_mode.app_rd_data_end_reg ;
  input rd_data_en_phy2mc;
  input \not_strict_mode.bypass_cpy2 ;
  input match4_13_return;
  input match6_13_return;
  input match4_14_return;
  input match6_14_return;
  input match4_15_return;
  input match6_15_return;
  input match4_16_return;
  input match6_16_return;
  input match4_17_return;
  input match6_17_return;
  input match4_18_return;
  input match6_18_return;
  input match4_19_return;
  input match6_19_return;
  input match4_110_return;
  input match6_110_return;
  input match4_111_return;
  input match6_111_return;
  input match4_112_return;
  input match6_112_return;
  input match4_113_return;
  input match6_113_return;
  input match4_114_return;
  input match6_114_return;
  input match4_115_return;
  input match6_115_return;
  input match4_116_return;
  input match6_116_return;
  input match4_117_return;
  input match6_117_return;
  input match4_118_return;
  input match6_118_return;
  input match4_119_return;
  input match6_119_return;
  input match4_120_return;
  input match6_120_return;
  input match4_121_return;
  input match6_121_return;
  input match4_122_return;
  input match6_122_return;
  input match4_123_return;
  input match6_123_return;
  input match4_124_return;
  input match6_124_return;
  input match4_125_return;
  input match6_125_return;
  input match4_126_return;
  input match6_126_return;
  input match4_127_return;
  input match6_127_return;
  input match4_128_return;
  input match6_128_return;
  input match4_129_return;
  input match6_129_return;
  input match4_130_return;
  input match6_130_return;
  input match4_131_return;
  input match6_131_return;
  input match4_132_return;
  input match6_132_return;
  input match4_133_return;
  input match6_133_return;
  input match4_134_return;
  input match6_134_return;
  input match4_135_return;
  input match6_135_return;
  input match4_136_return;
  input match6_136_return;
  input match4_137_return;
  input match6_137_return;
  input match4_138_return;
  input match6_138_return;
  input match4_139_return;
  input match6_139_return;
  input match4_140_return;
  input match6_140_return;
  input match4_141_return;
  input match6_141_return;
  input match4_142_return;
  input match6_142_return;
  input match4_143_return;
  input match6_143_return;
  input match4_144_return;
  input match6_144_return;
  input match4_145_return;
  input match6_145_return;
  input match4_146_return;
  input match6_146_return;
  input match4_147_return;
  input match6_147_return;
  input match4_148_return;
  input match6_148_return;
  input match4_149_return;
  input match6_149_return;
  input match4_150_return;
  input match6_150_return;
  input match4_151_return;
  input match6_151_return;
  input match4_152_return;
  input match6_152_return;
  input match4_153_return;
  input match6_153_return;
  input match4_154_return;
  input match6_154_return;
  input match4_155_return;
  input match6_155_return;
  input match4_156_return;
  input match6_156_return;
  input match4_157_return;
  input match6_157_return;
  input match4_158_return;
  input match6_158_return;
  input match4_159_return;
  input match6_159_return;
  input match4_160_return;
  input match6_160_return;
  input match4_161_return;
  input match6_161_return;
  input match4_162_return;
  input match6_162_return;
  input match4_163_return;
  input match6_163_return;
  input match4_164_return;
  input match6_164_return;
  input match4_165_return;
  input match6_165_return;
  input match4_166_return;
  input match6_166_return;
  input match4_167_return;
  input match6_167_return;
  input match4_168_return;
  input match6_168_return;
  input match4_169_return;
  input match6_169_return;
  input match4_170_return;
  input match6_170_return;
  input match4_171_return;
  input match6_171_return;
  input match4_172_return;
  input match6_172_return;
  input match4_173_return;
  input match6_173_return;
  input match4_174_return;
  input match6_174_return;
  input match4_175_return;
  input match6_175_return;
  input match4_176_return;
  input match6_176_return;
  input match4_177_return;
  input match6_177_return;
  input match4_178_return;
  input match6_178_return;
  input match4_179_return;
  input match6_179_return;
  input match4_180_return;
  input match6_180_return;
  input match4_181_return;
  input match6_181_return;
  input match4_182_return;
  input match6_182_return;
  input match4_183_return;
  input match6_183_return;
  input match4_184_return;
  input match6_184_return;
  input match4_185_return;
  input match6_185_return;
  input match4_186_return;
  input match6_186_return;
  input match4_187_return;
  input match6_187_return;
  input match4_188_return;
  input match6_188_return;
  input match4_1_return;
  input match6_1_return;
  input match4_10_return;
  input match6_10_return;
  input match4_11_return;
  input match6_11_return;
  input match4_12_return;
  input match6_12_return;
  input [1:0]\not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[4] ;
  input \buf_fifo_reg[1][4] ;
  input accept_reg_14;
  input \buf_fifo_reg[1][0] ;
  input \buf_fifo_reg[1][1] ;
  input \buf_fifo_reg[1][2] ;
  input \buf_fifo_reg[1][3] ;
  input \buf_fifo_reg[1][4]_0 ;
  input \buf_fifo_reg[1][4]_1 ;
  input \buf_fifo_reg[1][0]_0 ;
  input \buf_fifo_reg[1][1]_0 ;
  input \buf_fifo_reg[1][2]_0 ;
  input \buf_fifo_reg[1][3]_0 ;
  input \buf_fifo_reg[1][4]_2 ;
  input \buf_fifo_reg[1][4]_3 ;
  input \buf_fifo_reg[1][0]_1 ;
  input \buf_fifo_reg[1][1]_1 ;
  input \buf_fifo_reg[1][2]_1 ;
  input \buf_fifo_reg[1][3]_1 ;
  input \buf_fifo_reg[1][4]_4 ;
  input accept_reg_15;
  input accept_reg_16;
  input [26:0]c0_ddr4_app_addr;
  input [2:0]c0_ddr4_app_cmd;
  input [511:0]c0_ddr4_app_wdf_data;
  input [63:0]c0_ddr4_app_wdf_mask;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ;
  input accept_ns;
  input c0_ddr4_app_en;

  wire [3:0]ADDRA;
  wire [3:0]ADDRC;
  wire [4:0]ADDRD;
  wire [511:0]D;
  wire [0:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire [0:0]E;
  wire [4:0]Q;
  wire [0:0]SR;
  wire accept_ns;
  wire accept_reg;
  wire accept_reg_0;
  wire accept_reg_1;
  wire accept_reg_10;
  wire accept_reg_11;
  wire accept_reg_12;
  wire accept_reg_13;
  wire accept_reg_14;
  wire accept_reg_15;
  wire accept_reg_16;
  wire accept_reg_2;
  wire accept_reg_3;
  wire accept_reg_4;
  wire accept_reg_5;
  wire accept_reg_6;
  wire accept_reg_7;
  wire accept_reg_8;
  wire accept_reg_9;
  wire app_rdy_ns;
  wire [1:0]bank;
  wire \buf_fifo_reg[1][0] ;
  wire \buf_fifo_reg[1][0]_0 ;
  wire \buf_fifo_reg[1][0]_1 ;
  wire \buf_fifo_reg[1][1] ;
  wire \buf_fifo_reg[1][1]_0 ;
  wire \buf_fifo_reg[1][1]_1 ;
  wire \buf_fifo_reg[1][2] ;
  wire \buf_fifo_reg[1][2]_0 ;
  wire \buf_fifo_reg[1][2]_1 ;
  wire \buf_fifo_reg[1][3] ;
  wire \buf_fifo_reg[1][3]_0 ;
  wire \buf_fifo_reg[1][3]_1 ;
  wire \buf_fifo_reg[1][4] ;
  wire \buf_fifo_reg[1][4]_0 ;
  wire \buf_fifo_reg[1][4]_1 ;
  wire \buf_fifo_reg[1][4]_2 ;
  wire \buf_fifo_reg[1][4]_3 ;
  wire \buf_fifo_reg[1][4]_4 ;
  wire [26:0]c0_ddr4_app_addr;
  wire [2:0]c0_ddr4_app_cmd;
  wire c0_ddr4_app_en;
  wire [511:0]c0_ddr4_app_rd_data;
  wire c0_ddr4_app_rd_data_end;
  wire c0_ddr4_app_rd_data_valid;
  wire [511:0]c0_ddr4_app_wdf_data;
  wire c0_ddr4_app_wdf_end;
  wire [63:0]c0_ddr4_app_wdf_mask;
  wire c0_ddr4_app_wdf_rdy;
  wire c0_ddr4_app_wdf_wren;
  wire [0:0]calDone_gated_reg;
  wire [2:0]cmd;
  wire [6:0]col;
  wire [4:0]dBufAdr;
  wire [0:0]group;
  wire [85:0]in0;
  wire match4_10_return;
  wire match4_110_return;
  wire match4_111_return;
  wire match4_112_return;
  wire match4_113_return;
  wire match4_114_return;
  wire match4_115_return;
  wire match4_116_return;
  wire match4_117_return;
  wire match4_118_return;
  wire match4_119_return;
  wire match4_11_return;
  wire match4_120_return;
  wire match4_121_return;
  wire match4_122_return;
  wire match4_123_return;
  wire match4_124_return;
  wire match4_125_return;
  wire match4_126_return;
  wire match4_127_return;
  wire match4_128_return;
  wire match4_129_return;
  wire match4_12_return;
  wire match4_130_return;
  wire match4_131_return;
  wire match4_132_return;
  wire match4_133_return;
  wire match4_134_return;
  wire match4_135_return;
  wire match4_136_return;
  wire match4_137_return;
  wire match4_138_return;
  wire match4_139_return;
  wire match4_13_return;
  wire match4_140_return;
  wire match4_141_return;
  wire match4_142_return;
  wire match4_143_return;
  wire match4_144_return;
  wire match4_145_return;
  wire match4_146_return;
  wire match4_147_return;
  wire match4_148_return;
  wire match4_149_return;
  wire match4_14_return;
  wire match4_150_return;
  wire match4_151_return;
  wire match4_152_return;
  wire match4_153_return;
  wire match4_154_return;
  wire match4_155_return;
  wire match4_156_return;
  wire match4_157_return;
  wire match4_158_return;
  wire match4_159_return;
  wire match4_15_return;
  wire match4_160_return;
  wire match4_161_return;
  wire match4_162_return;
  wire match4_163_return;
  wire match4_164_return;
  wire match4_165_return;
  wire match4_166_return;
  wire match4_167_return;
  wire match4_168_return;
  wire match4_169_return;
  wire match4_16_return;
  wire match4_170_return;
  wire match4_171_return;
  wire match4_172_return;
  wire match4_173_return;
  wire match4_174_return;
  wire match4_175_return;
  wire match4_176_return;
  wire match4_177_return;
  wire match4_178_return;
  wire match4_179_return;
  wire match4_17_return;
  wire match4_180_return;
  wire match4_181_return;
  wire match4_182_return;
  wire match4_183_return;
  wire match4_184_return;
  wire match4_185_return;
  wire match4_186_return;
  wire match4_187_return;
  wire match4_188_return;
  wire match4_18_return;
  wire match4_19_return;
  wire match4_1_return;
  wire match6_10_return;
  wire match6_110_return;
  wire match6_111_return;
  wire match6_112_return;
  wire match6_113_return;
  wire match6_114_return;
  wire match6_115_return;
  wire match6_116_return;
  wire match6_117_return;
  wire match6_118_return;
  wire match6_119_return;
  wire match6_11_return;
  wire match6_120_return;
  wire match6_121_return;
  wire match6_122_return;
  wire match6_123_return;
  wire match6_124_return;
  wire match6_125_return;
  wire match6_126_return;
  wire match6_127_return;
  wire match6_128_return;
  wire match6_129_return;
  wire match6_12_return;
  wire match6_130_return;
  wire match6_131_return;
  wire match6_132_return;
  wire match6_133_return;
  wire match6_134_return;
  wire match6_135_return;
  wire match6_136_return;
  wire match6_137_return;
  wire match6_138_return;
  wire match6_139_return;
  wire match6_13_return;
  wire match6_140_return;
  wire match6_141_return;
  wire match6_142_return;
  wire match6_143_return;
  wire match6_144_return;
  wire match6_145_return;
  wire match6_146_return;
  wire match6_147_return;
  wire match6_148_return;
  wire match6_149_return;
  wire match6_14_return;
  wire match6_150_return;
  wire match6_151_return;
  wire match6_152_return;
  wire match6_153_return;
  wire match6_154_return;
  wire match6_155_return;
  wire match6_156_return;
  wire match6_157_return;
  wire match6_158_return;
  wire match6_159_return;
  wire match6_15_return;
  wire match6_160_return;
  wire match6_161_return;
  wire match6_162_return;
  wire match6_163_return;
  wire match6_164_return;
  wire match6_165_return;
  wire match6_166_return;
  wire match6_167_return;
  wire match6_168_return;
  wire match6_169_return;
  wire match6_16_return;
  wire match6_170_return;
  wire match6_171_return;
  wire match6_172_return;
  wire match6_173_return;
  wire match6_174_return;
  wire match6_175_return;
  wire match6_176_return;
  wire match6_177_return;
  wire match6_178_return;
  wire match6_179_return;
  wire match6_17_return;
  wire match6_180_return;
  wire match6_181_return;
  wire match6_182_return;
  wire match6_183_return;
  wire match6_184_return;
  wire match6_185_return;
  wire match6_186_return;
  wire match6_187_return;
  wire match6_188_return;
  wire match6_18_return;
  wire match6_19_return;
  wire match6_1_return;
  wire \not_strict_mode.app_rd_data_end_reg ;
  wire \not_strict_mode.bypass_cpy2 ;
  wire [5:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_2 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_2 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ;
  wire [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4] ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_1 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4] ;
  wire [1:0]\not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[4] ;
  wire [4:0]\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4] ;
  wire [4:0]\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4] ;
  wire [4:0]\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4] ;
  wire [0:0]out;
  wire p_1_in7_in;
  wire periodic_read_or_ref_block_reg;
  wire pointer_we;
  wire [3:0]pointer_wr_addr;
  wire [3:0]pointer_wr_data;
  wire [3:0]ram_init_done_r;
  wire rd_accepted;
  wire rd_buf_full0;
  wire [4:0]\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4] ;
  wire [4:0]rd_data_buf_addr_r;
  wire rd_data_en_phy2mc;
  wire [3:0]rd_data_indx_r_reg;
  wire [0:0]\rd_data_indx_r_reg[3]_0 ;
  wire rd_data_indx_r_reg_3_sn_1;
  wire [16:0]row_mc_phy;
  (* RTL_KEEP = "true" *) wire rst_r1;
  wire u_ddr_ui_cmd_n_1;
  wire u_ddr_ui_cmd_n_2;
  wire u_ddr_ui_cmd_n_3;
  wire u_ddr_ui_cmd_n_30;
  wire u_ddr_ui_cmd_n_31;
  wire u_ddr_ui_cmd_n_32;
  wire u_ddr_ui_rd_data_n_622;
  wire useAdr;
  wire wr_accepted;
  wire [575:0]\wr_buf_out_data_reg[575] ;
  wire [3:0]\wr_buffer_ram[40].RAM32M0 ;
  wire [3:0]\wr_buffer_ram[8].RAM32M0 ;
  wire [3:0]wr_data_buf_addr;
  wire [1:0]wr_req_cnt_r;

  assign rd_data_indx_r_reg_3_sn_1 = \rd_data_indx_r_reg[3] ;
  (* KEEP = "yes" *) 
  FDRE rst_r1_reg
       (.C(rd_data_indx_r_reg_3_sn_1),
        .CE(1'b1),
        .D(SR),
        .Q(rst_r1),
        .R(1'b0));
  ddr4_0_ddr4_v2_2_17_ui_cmd u_ddr_ui_cmd
       (.D(u_ddr_ui_cmd_n_1),
        .E(u_ddr_ui_cmd_n_2),
        .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg [1:0]),
        .accept_reg(accept_reg),
        .accept_reg_0(accept_reg_0),
        .accept_reg_1(accept_reg_1),
        .accept_reg_10(accept_reg_10),
        .accept_reg_11(accept_reg_11),
        .accept_reg_12(accept_reg_12),
        .accept_reg_13(accept_reg_13),
        .accept_reg_14(accept_reg_14),
        .accept_reg_15(accept_reg_15),
        .accept_reg_16(accept_reg_16),
        .accept_reg_2(accept_reg_2),
        .accept_reg_3(accept_reg_3),
        .accept_reg_4(accept_reg_4),
        .accept_reg_5(accept_reg_5),
        .accept_reg_6(accept_reg_6),
        .accept_reg_7(accept_reg_7),
        .accept_reg_8(accept_reg_8),
        .accept_reg_9(accept_reg_9),
        .\app_addr_r1_reg[29]_0 (rst_r1),
        .\app_cmd_r1_reg[2]_0 (rd_data_indx_r_reg_3_sn_1),
        .app_en_r2_reg_0(useAdr),
        .app_rdy_ns(app_rdy_ns),
        .app_rdy_r_reg_0(E),
        .bank(bank),
        .\buf_fifo[0][4]_i_2__2 (rd_data_buf_addr_r),
        .\buf_fifo_reg[1][0] (\buf_fifo_reg[1][0] ),
        .\buf_fifo_reg[1][0]_0 (\buf_fifo_reg[1][0]_0 ),
        .\buf_fifo_reg[1][0]_1 (\buf_fifo_reg[1][0]_1 ),
        .\buf_fifo_reg[1][1] (\buf_fifo_reg[1][1] ),
        .\buf_fifo_reg[1][1]_0 (\buf_fifo_reg[1][1]_0 ),
        .\buf_fifo_reg[1][1]_1 (\buf_fifo_reg[1][1]_1 ),
        .\buf_fifo_reg[1][2] (\buf_fifo_reg[1][2] ),
        .\buf_fifo_reg[1][2]_0 (\buf_fifo_reg[1][2]_0 ),
        .\buf_fifo_reg[1][2]_1 (\buf_fifo_reg[1][2]_1 ),
        .\buf_fifo_reg[1][3] (\buf_fifo_reg[1][3] ),
        .\buf_fifo_reg[1][3]_0 (\buf_fifo_reg[1][3]_0 ),
        .\buf_fifo_reg[1][3]_1 (\buf_fifo_reg[1][3]_1 ),
        .\buf_fifo_reg[1][4] (\buf_fifo_reg[1][4] ),
        .\buf_fifo_reg[1][4]_0 (\buf_fifo_reg[1][4]_0 ),
        .\buf_fifo_reg[1][4]_1 (\buf_fifo_reg[1][4]_1 ),
        .\buf_fifo_reg[1][4]_2 (\buf_fifo_reg[1][4]_2 ),
        .\buf_fifo_reg[1][4]_3 (\buf_fifo_reg[1][4]_3 ),
        .\buf_fifo_reg[1][4]_4 (\buf_fifo_reg[1][4]_4 ),
        .c0_ddr4_app_addr(c0_ddr4_app_addr),
        .c0_ddr4_app_cmd(c0_ddr4_app_cmd),
        .c0_ddr4_app_en(c0_ddr4_app_en),
        .c0_ddr4_app_rd_data_end(c0_ddr4_app_rd_data_end),
        .calDone_gated_reg(calDone_gated_reg),
        .cmd(cmd),
        .col(col),
        .group(group),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] (dBufAdr[4]),
        .\not_strict_mode.occupied_counter.occ_cnt_r_reg[1] (u_ddr_ui_cmd_n_3),
        .out(u_ddr_ui_rd_data_n_622),
        .periodic_read_or_ref_block_reg(periodic_read_or_ref_block_reg),
        .\rams[0].RAM32M0 (dBufAdr[0]),
        .\rams[0].RAM32M0_0 (dBufAdr[1]),
        .\rams[1].RAM32M0 (dBufAdr[2]),
        .\rams[1].RAM32M0_0 (dBufAdr[3]),
        .rd_accepted(rd_accepted),
        .rd_data_upd_indx_r_reg(u_ddr_ui_cmd_n_32),
        .row_mc_phy(row_mc_phy),
        .wr_accepted(wr_accepted),
        .wr_data_buf_addr(wr_data_buf_addr),
        .wr_req_cnt_r(wr_req_cnt_r),
        .\wr_req_cnt_r_reg[0] (u_ddr_ui_cmd_n_30),
        .\wr_req_cnt_r_reg[0]_0 (u_ddr_ui_cmd_n_31),
        .\wr_req_cnt_r_reg[0]_1 (p_1_in7_in));
  ddr4_0_ddr4_v2_2_17_ui_rd_data u_ddr_ui_rd_data
       (.ADDRC(ADDRC),
        .ADDRD(ADDRD),
        .D(D),
        .DOA(DOA),
        .DOB(DOB),
        .DOC(DOC),
        .E(u_ddr_ui_cmd_n_2),
        .Q(Q),
        .c0_ddr4_app_rd_data(c0_ddr4_app_rd_data),
        .c0_ddr4_app_rd_data_end(c0_ddr4_app_rd_data_end),
        .c0_ddr4_app_rd_data_valid(c0_ddr4_app_rd_data_valid),
        .in0(in0),
        .match4_10_return(match4_10_return),
        .match4_110_return(match4_110_return),
        .match4_111_return(match4_111_return),
        .match4_112_return(match4_112_return),
        .match4_113_return(match4_113_return),
        .match4_114_return(match4_114_return),
        .match4_115_return(match4_115_return),
        .match4_116_return(match4_116_return),
        .match4_117_return(match4_117_return),
        .match4_118_return(match4_118_return),
        .match4_119_return(match4_119_return),
        .match4_11_return(match4_11_return),
        .match4_120_return(match4_120_return),
        .match4_121_return(match4_121_return),
        .match4_122_return(match4_122_return),
        .match4_123_return(match4_123_return),
        .match4_124_return(match4_124_return),
        .match4_125_return(match4_125_return),
        .match4_126_return(match4_126_return),
        .match4_127_return(match4_127_return),
        .match4_128_return(match4_128_return),
        .match4_129_return(match4_129_return),
        .match4_12_return(match4_12_return),
        .match4_130_return(match4_130_return),
        .match4_131_return(match4_131_return),
        .match4_132_return(match4_132_return),
        .match4_133_return(match4_133_return),
        .match4_134_return(match4_134_return),
        .match4_135_return(match4_135_return),
        .match4_136_return(match4_136_return),
        .match4_137_return(match4_137_return),
        .match4_138_return(match4_138_return),
        .match4_139_return(match4_139_return),
        .match4_13_return(match4_13_return),
        .match4_140_return(match4_140_return),
        .match4_141_return(match4_141_return),
        .match4_142_return(match4_142_return),
        .match4_143_return(match4_143_return),
        .match4_144_return(match4_144_return),
        .match4_145_return(match4_145_return),
        .match4_146_return(match4_146_return),
        .match4_147_return(match4_147_return),
        .match4_148_return(match4_148_return),
        .match4_149_return(match4_149_return),
        .match4_14_return(match4_14_return),
        .match4_150_return(match4_150_return),
        .match4_151_return(match4_151_return),
        .match4_152_return(match4_152_return),
        .match4_153_return(match4_153_return),
        .match4_154_return(match4_154_return),
        .match4_155_return(match4_155_return),
        .match4_156_return(match4_156_return),
        .match4_157_return(match4_157_return),
        .match4_158_return(match4_158_return),
        .match4_159_return(match4_159_return),
        .match4_15_return(match4_15_return),
        .match4_160_return(match4_160_return),
        .match4_161_return(match4_161_return),
        .match4_162_return(match4_162_return),
        .match4_163_return(match4_163_return),
        .match4_164_return(match4_164_return),
        .match4_165_return(match4_165_return),
        .match4_166_return(match4_166_return),
        .match4_167_return(match4_167_return),
        .match4_168_return(match4_168_return),
        .match4_169_return(match4_169_return),
        .match4_16_return(match4_16_return),
        .match4_170_return(match4_170_return),
        .match4_171_return(match4_171_return),
        .match4_172_return(match4_172_return),
        .match4_173_return(match4_173_return),
        .match4_174_return(match4_174_return),
        .match4_175_return(match4_175_return),
        .match4_176_return(match4_176_return),
        .match4_177_return(match4_177_return),
        .match4_178_return(match4_178_return),
        .match4_179_return(match4_179_return),
        .match4_17_return(match4_17_return),
        .match4_180_return(match4_180_return),
        .match4_181_return(match4_181_return),
        .match4_182_return(match4_182_return),
        .match4_183_return(match4_183_return),
        .match4_184_return(match4_184_return),
        .match4_185_return(match4_185_return),
        .match4_186_return(match4_186_return),
        .match4_187_return(match4_187_return),
        .match4_188_return(match4_188_return),
        .match4_18_return(match4_18_return),
        .match4_19_return(match4_19_return),
        .match4_1_return(match4_1_return),
        .match6_10_return(match6_10_return),
        .match6_110_return(match6_110_return),
        .match6_111_return(match6_111_return),
        .match6_112_return(match6_112_return),
        .match6_113_return(match6_113_return),
        .match6_114_return(match6_114_return),
        .match6_115_return(match6_115_return),
        .match6_116_return(match6_116_return),
        .match6_117_return(match6_117_return),
        .match6_118_return(match6_118_return),
        .match6_119_return(match6_119_return),
        .match6_11_return(match6_11_return),
        .match6_120_return(match6_120_return),
        .match6_121_return(match6_121_return),
        .match6_122_return(match6_122_return),
        .match6_123_return(match6_123_return),
        .match6_124_return(match6_124_return),
        .match6_125_return(match6_125_return),
        .match6_126_return(match6_126_return),
        .match6_127_return(match6_127_return),
        .match6_128_return(match6_128_return),
        .match6_129_return(match6_129_return),
        .match6_12_return(match6_12_return),
        .match6_130_return(match6_130_return),
        .match6_131_return(match6_131_return),
        .match6_132_return(match6_132_return),
        .match6_133_return(match6_133_return),
        .match6_134_return(match6_134_return),
        .match6_135_return(match6_135_return),
        .match6_136_return(match6_136_return),
        .match6_137_return(match6_137_return),
        .match6_138_return(match6_138_return),
        .match6_139_return(match6_139_return),
        .match6_13_return(match6_13_return),
        .match6_140_return(match6_140_return),
        .match6_141_return(match6_141_return),
        .match6_142_return(match6_142_return),
        .match6_143_return(match6_143_return),
        .match6_144_return(match6_144_return),
        .match6_145_return(match6_145_return),
        .match6_146_return(match6_146_return),
        .match6_147_return(match6_147_return),
        .match6_148_return(match6_148_return),
        .match6_149_return(match6_149_return),
        .match6_14_return(match6_14_return),
        .match6_150_return(match6_150_return),
        .match6_151_return(match6_151_return),
        .match6_152_return(match6_152_return),
        .match6_153_return(match6_153_return),
        .match6_154_return(match6_154_return),
        .match6_155_return(match6_155_return),
        .match6_156_return(match6_156_return),
        .match6_157_return(match6_157_return),
        .match6_158_return(match6_158_return),
        .match6_159_return(match6_159_return),
        .match6_15_return(match6_15_return),
        .match6_160_return(match6_160_return),
        .match6_161_return(match6_161_return),
        .match6_162_return(match6_162_return),
        .match6_163_return(match6_163_return),
        .match6_164_return(match6_164_return),
        .match6_165_return(match6_165_return),
        .match6_166_return(match6_166_return),
        .match6_167_return(match6_167_return),
        .match6_168_return(match6_168_return),
        .match6_169_return(match6_169_return),
        .match6_16_return(match6_16_return),
        .match6_170_return(match6_170_return),
        .match6_171_return(match6_171_return),
        .match6_172_return(match6_172_return),
        .match6_173_return(match6_173_return),
        .match6_174_return(match6_174_return),
        .match6_175_return(match6_175_return),
        .match6_176_return(match6_176_return),
        .match6_177_return(match6_177_return),
        .match6_178_return(match6_178_return),
        .match6_179_return(match6_179_return),
        .match6_17_return(match6_17_return),
        .match6_180_return(match6_180_return),
        .match6_181_return(match6_181_return),
        .match6_182_return(match6_182_return),
        .match6_183_return(match6_183_return),
        .match6_184_return(match6_184_return),
        .match6_185_return(match6_185_return),
        .match6_186_return(match6_186_return),
        .match6_187_return(match6_187_return),
        .match6_188_return(match6_188_return),
        .match6_18_return(match6_18_return),
        .match6_19_return(match6_19_return),
        .match6_1_return(match6_1_return),
        .\not_strict_mode.app_rd_data_end_reg_0 (\not_strict_mode.app_rd_data_end_reg ),
        .\not_strict_mode.app_rd_data_valid_cpy_r_reg_0 (u_ddr_ui_rd_data_n_622),
        .\not_strict_mode.bypass_cpy2 (\not_strict_mode.bypass_cpy2 ),
        .\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 (rd_data_buf_addr_r),
        .\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 (u_ddr_ui_cmd_n_1),
        .\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 ({\not_strict_mode.occupied_counter.occ_cnt_r_reg [5],\not_strict_mode.occupied_counter.occ_cnt_r_reg [1:0]}),
        .\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_1 (u_ddr_ui_cmd_n_3),
        .\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 (\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_2 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 (\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_2 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_0 (\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_1 (\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_0 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_2 (\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_1 ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] ),
        .\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 (\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4] ),
        .\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 (rd_data_indx_r_reg_3_sn_1),
        .\not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[4]_0 (\not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[4] ),
        .\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 (\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4] ),
        .\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 (\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4] ),
        .\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 (rst_r1),
        .\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 (\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4] ),
        .out({ram_init_done_r[3],out,ram_init_done_r[0]}),
        .pointer_wr_data(pointer_wr_data),
        .\rams[0].RAM32M0 (rd_data_indx_r_reg),
        .rd_accepted(rd_accepted),
        .rd_buf_full0(rd_buf_full0),
        .\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 (\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4] ),
        .rd_data_en_phy2mc(rd_data_en_phy2mc),
        .\rd_data_indx_r_reg[3] (pointer_wr_addr));
  ddr4_0_ddr4_v2_2_17_ui_wr_data u_ddr_ui_wr_data
       (.ADDRA(ADDRA),
        .ADDRC(ADDRC),
        .D(u_ddr_ui_cmd_n_31),
        .Q(rd_data_indx_r_reg),
        .accept_ns(accept_ns),
        .app_rdy_ns(app_rdy_ns),
        .app_rdy_r_reg(\not_strict_mode.occupied_counter.occ_cnt_r_reg [5]),
        .c0_ddr4_app_wdf_data(c0_ddr4_app_wdf_data),
        .c0_ddr4_app_wdf_end(c0_ddr4_app_wdf_end),
        .c0_ddr4_app_wdf_mask(c0_ddr4_app_wdf_mask),
        .c0_ddr4_app_wdf_rdy(c0_ddr4_app_wdf_rdy),
        .c0_ddr4_app_wdf_wren(c0_ddr4_app_wdf_wren),
        .out(p_1_in7_in),
        .pointer_we(pointer_we),
        .pointer_wr_data(pointer_wr_data),
        .\rams[0].RAM32M0_0 (pointer_wr_addr),
        .rd_buf_full0(rd_buf_full0),
        .\rd_data_indx_r_reg[3]_0 (rd_data_indx_r_reg_3_sn_1),
        .\rd_data_indx_r_reg[3]_1 (\rd_data_indx_r_reg[3]_0 ),
        .wr_accepted(wr_accepted),
        .\wr_buf_out_data_reg[575]_0 (\wr_buf_out_data_reg[575] ),
        .\wr_buffer_ram[40].RAM32M0_0 (\wr_buffer_ram[40].RAM32M0 ),
        .\wr_buffer_ram[8].RAM32M0_0 (\wr_buffer_ram[8].RAM32M0 ),
        .wr_data_buf_addr(wr_data_buf_addr),
        .\wr_data_indx_r_reg[0]_0 ({ram_init_done_r[3],ram_init_done_r[0]}),
        .\wr_data_indx_r_reg[1]_0 (rst_r1),
        .\wr_req_cnt_r_reg[1]_0 (wr_req_cnt_r),
        .\wr_req_cnt_r_reg[3]_0 (u_ddr_ui_cmd_n_30),
        .\wr_req_cnt_r_reg[3]_1 (u_ddr_ui_cmd_n_32));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_ui_cmd" *) 
module ddr4_0_ddr4_v2_2_17_ui_cmd
   (app_rdy_r_reg_0,
    D,
    E,
    \not_strict_mode.occupied_counter.occ_cnt_r_reg[1] ,
    accept_reg,
    \rams[0].RAM32M0 ,
    app_en_r2_reg_0,
    accept_reg_0,
    \rams[0].RAM32M0_0 ,
    accept_reg_1,
    \rams[1].RAM32M0 ,
    accept_reg_2,
    \rams[1].RAM32M0_0 ,
    accept_reg_3,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ,
    accept_reg_4,
    accept_reg_5,
    accept_reg_6,
    accept_reg_7,
    accept_reg_8,
    accept_reg_9,
    accept_reg_10,
    accept_reg_11,
    accept_reg_12,
    accept_reg_13,
    calDone_gated_reg,
    group,
    bank,
    periodic_read_or_ref_block_reg,
    \wr_req_cnt_r_reg[0] ,
    \wr_req_cnt_r_reg[0]_0 ,
    rd_data_upd_indx_r_reg,
    wr_accepted,
    rd_accepted,
    cmd,
    row_mc_phy,
    col,
    app_rdy_ns,
    \app_cmd_r1_reg[2]_0 ,
    Q,
    c0_ddr4_app_rd_data_end,
    out,
    \buf_fifo_reg[1][4] ,
    accept_reg_14,
    \buf_fifo_reg[1][0] ,
    \buf_fifo_reg[1][1] ,
    \buf_fifo_reg[1][2] ,
    \buf_fifo_reg[1][3] ,
    \buf_fifo_reg[1][4]_0 ,
    \buf_fifo_reg[1][4]_1 ,
    \buf_fifo_reg[1][0]_0 ,
    \buf_fifo_reg[1][1]_0 ,
    \buf_fifo_reg[1][2]_0 ,
    \buf_fifo_reg[1][3]_0 ,
    \buf_fifo_reg[1][4]_2 ,
    \buf_fifo_reg[1][4]_3 ,
    \buf_fifo_reg[1][0]_1 ,
    \buf_fifo_reg[1][1]_1 ,
    \buf_fifo_reg[1][2]_1 ,
    \buf_fifo_reg[1][3]_1 ,
    \buf_fifo_reg[1][4]_4 ,
    accept_reg_15,
    accept_reg_16,
    c0_ddr4_app_en,
    \app_addr_r1_reg[29]_0 ,
    wr_req_cnt_r,
    \wr_req_cnt_r_reg[0]_1 ,
    wr_data_buf_addr,
    \buf_fifo[0][4]_i_2__2 ,
    c0_ddr4_app_addr,
    c0_ddr4_app_cmd);
  output app_rdy_r_reg_0;
  output [0:0]D;
  output [0:0]E;
  output \not_strict_mode.occupied_counter.occ_cnt_r_reg[1] ;
  output accept_reg;
  output \rams[0].RAM32M0 ;
  output app_en_r2_reg_0;
  output accept_reg_0;
  output \rams[0].RAM32M0_0 ;
  output accept_reg_1;
  output \rams[1].RAM32M0 ;
  output accept_reg_2;
  output \rams[1].RAM32M0_0 ;
  output accept_reg_3;
  output \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  output accept_reg_4;
  output accept_reg_5;
  output accept_reg_6;
  output accept_reg_7;
  output accept_reg_8;
  output accept_reg_9;
  output accept_reg_10;
  output accept_reg_11;
  output accept_reg_12;
  output accept_reg_13;
  output [0:0]calDone_gated_reg;
  output [0:0]group;
  output [1:0]bank;
  output periodic_read_or_ref_block_reg;
  output \wr_req_cnt_r_reg[0] ;
  output [0:0]\wr_req_cnt_r_reg[0]_0 ;
  output rd_data_upd_indx_r_reg;
  output wr_accepted;
  output rd_accepted;
  output [2:0]cmd;
  output [16:0]row_mc_phy;
  output [6:0]col;
  input app_rdy_ns;
  input \app_cmd_r1_reg[2]_0 ;
  input [1:0]Q;
  input c0_ddr4_app_rd_data_end;
  input out;
  input \buf_fifo_reg[1][4] ;
  input accept_reg_14;
  input \buf_fifo_reg[1][0] ;
  input \buf_fifo_reg[1][1] ;
  input \buf_fifo_reg[1][2] ;
  input \buf_fifo_reg[1][3] ;
  input \buf_fifo_reg[1][4]_0 ;
  input \buf_fifo_reg[1][4]_1 ;
  input \buf_fifo_reg[1][0]_0 ;
  input \buf_fifo_reg[1][1]_0 ;
  input \buf_fifo_reg[1][2]_0 ;
  input \buf_fifo_reg[1][3]_0 ;
  input \buf_fifo_reg[1][4]_2 ;
  input \buf_fifo_reg[1][4]_3 ;
  input \buf_fifo_reg[1][0]_1 ;
  input \buf_fifo_reg[1][1]_1 ;
  input \buf_fifo_reg[1][2]_1 ;
  input \buf_fifo_reg[1][3]_1 ;
  input \buf_fifo_reg[1][4]_4 ;
  input accept_reg_15;
  input accept_reg_16;
  input c0_ddr4_app_en;
  input \app_addr_r1_reg[29]_0 ;
  input [1:0]wr_req_cnt_r;
  input \wr_req_cnt_r_reg[0]_1 ;
  input [3:0]wr_data_buf_addr;
  input [4:0]\buf_fifo[0][4]_i_2__2 ;
  input [26:0]c0_ddr4_app_addr;
  input [2:0]c0_ddr4_app_cmd;

  wire [0:0]D;
  wire [0:0]E;
  wire [1:0]Q;
  wire accept_reg;
  wire accept_reg_0;
  wire accept_reg_1;
  wire accept_reg_10;
  wire accept_reg_11;
  wire accept_reg_12;
  wire accept_reg_13;
  wire accept_reg_14;
  wire accept_reg_15;
  wire accept_reg_16;
  wire accept_reg_2;
  wire accept_reg_3;
  wire accept_reg_4;
  wire accept_reg_5;
  wire accept_reg_6;
  wire accept_reg_7;
  wire accept_reg_8;
  wire accept_reg_9;
  wire [29:3]app_addr_r1;
  wire app_addr_r10;
  wire \app_addr_r1_reg[29]_0 ;
  wire [29:3]app_addr_r2;
  wire [2:0]app_cmd_r1;
  wire \app_cmd_r1_reg[2]_0 ;
  wire [2:0]app_cmd_r2;
  wire app_en_ns1;
  wire app_en_ns2;
  wire app_en_r1;
  wire app_en_r2;
  wire app_en_r2_reg_0;
  wire app_rdy_ns;
  wire app_rdy_r_reg_0;
  wire [1:0]bank;
  wire [4:0]\buf_fifo[0][4]_i_2__2 ;
  wire \buf_fifo_reg[1][0] ;
  wire \buf_fifo_reg[1][0]_0 ;
  wire \buf_fifo_reg[1][0]_1 ;
  wire \buf_fifo_reg[1][1] ;
  wire \buf_fifo_reg[1][1]_0 ;
  wire \buf_fifo_reg[1][1]_1 ;
  wire \buf_fifo_reg[1][2] ;
  wire \buf_fifo_reg[1][2]_0 ;
  wire \buf_fifo_reg[1][2]_1 ;
  wire \buf_fifo_reg[1][3] ;
  wire \buf_fifo_reg[1][3]_0 ;
  wire \buf_fifo_reg[1][3]_1 ;
  wire \buf_fifo_reg[1][4] ;
  wire \buf_fifo_reg[1][4]_0 ;
  wire \buf_fifo_reg[1][4]_1 ;
  wire \buf_fifo_reg[1][4]_2 ;
  wire \buf_fifo_reg[1][4]_3 ;
  wire \buf_fifo_reg[1][4]_4 ;
  wire [26:0]c0_ddr4_app_addr;
  wire [2:0]c0_ddr4_app_cmd;
  wire c0_ddr4_app_en;
  wire c0_ddr4_app_rd_data_end;
  wire [0:0]calDone_gated_reg;
  wire [2:0]cmd;
  wire [6:0]col;
  wire [0:0]group;
  wire \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r_reg[1] ;
  wire out;
  wire periodic_read_or_ref_block_reg;
  wire \rams[0].RAM32M0 ;
  wire \rams[0].RAM32M0_0 ;
  wire \rams[1].RAM32M0 ;
  wire \rams[1].RAM32M0_0 ;
  wire rd_accepted;
  wire rd_data_upd_indx_r_reg;
  wire [16:0]row_mc_phy;
  wire wr_accepted;
  wire [3:0]wr_data_buf_addr;
  wire [1:0]wr_req_cnt_r;
  wire \wr_req_cnt_r_reg[0] ;
  wire [0:0]\wr_req_cnt_r_reg[0]_0 ;
  wire \wr_req_cnt_r_reg[0]_1 ;

  (* SOFT_HLUTNM = "soft_lutpair2898" *) 
  LUT5 #(
    .INIT(32'h00000080)) 
    accept_i_1
       (.I0(group),
        .I1(bank[0]),
        .I2(accept_reg_14),
        .I3(accept_reg_15),
        .I4(accept_reg_16),
        .O(calDone_gated_reg));
  (* SOFT_HLUTNM = "soft_lutpair2898" *) 
  LUT4 #(
    .INIT(16'hFBFF)) 
    accept_i_2__0
       (.I0(accept_reg_15),
        .I1(accept_reg_14),
        .I2(group),
        .I3(bank[0]),
        .O(periodic_read_or_ref_block_reg));
  LUT2 #(
    .INIT(4'h8)) 
    \app_addr_r1[29]_i_1 
       (.I0(app_rdy_r_reg_0),
        .I1(c0_ddr4_app_en),
        .O(app_addr_r10));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[10] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[7]),
        .Q(app_addr_r1[10]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[11] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[8]),
        .Q(app_addr_r1[11]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[12] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[9]),
        .Q(app_addr_r1[12]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[13] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[10]),
        .Q(app_addr_r1[13]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[14] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[11]),
        .Q(app_addr_r1[14]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[15] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[12]),
        .Q(app_addr_r1[15]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[16] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[13]),
        .Q(app_addr_r1[16]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[17] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[14]),
        .Q(app_addr_r1[17]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[18] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[15]),
        .Q(app_addr_r1[18]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[19] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[16]),
        .Q(app_addr_r1[19]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[20] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[17]),
        .Q(app_addr_r1[20]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[21] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[18]),
        .Q(app_addr_r1[21]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[22] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[19]),
        .Q(app_addr_r1[22]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[23] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[20]),
        .Q(app_addr_r1[23]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[24] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[21]),
        .Q(app_addr_r1[24]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[25] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[22]),
        .Q(app_addr_r1[25]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[26] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[23]),
        .Q(app_addr_r1[26]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[27] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[24]),
        .Q(app_addr_r1[27]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[28] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[25]),
        .Q(app_addr_r1[28]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[29] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[26]),
        .Q(app_addr_r1[29]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[3] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[0]),
        .Q(app_addr_r1[3]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[4] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[1]),
        .Q(app_addr_r1[4]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[5] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[2]),
        .Q(app_addr_r1[5]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[6] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[3]),
        .Q(app_addr_r1[6]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[7] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[4]),
        .Q(app_addr_r1[7]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[8] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[5]),
        .Q(app_addr_r1[8]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[9] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_addr_r10),
        .D(c0_ddr4_app_addr[6]),
        .Q(app_addr_r1[9]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[10] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[10]),
        .Q(app_addr_r2[10]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[11] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[11]),
        .Q(app_addr_r2[11]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[12] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[12]),
        .Q(app_addr_r2[12]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[13] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[13]),
        .Q(app_addr_r2[13]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[14] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[14]),
        .Q(app_addr_r2[14]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[15] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[15]),
        .Q(app_addr_r2[15]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[16] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[16]),
        .Q(app_addr_r2[16]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[17] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[17]),
        .Q(app_addr_r2[17]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[18] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[18]),
        .Q(app_addr_r2[18]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[19] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[19]),
        .Q(app_addr_r2[19]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[20] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[20]),
        .Q(app_addr_r2[20]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[21] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[21]),
        .Q(app_addr_r2[21]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[22] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[22]),
        .Q(app_addr_r2[22]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[23] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[23]),
        .Q(app_addr_r2[23]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[24] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[24]),
        .Q(app_addr_r2[24]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[25] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[25]),
        .Q(app_addr_r2[25]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[26] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[26]),
        .Q(app_addr_r2[26]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[27] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[27]),
        .Q(app_addr_r2[27]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[28] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[28]),
        .Q(app_addr_r2[28]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[29] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[29]),
        .Q(app_addr_r2[29]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[3] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[3]),
        .Q(app_addr_r2[3]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[4] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[4]),
        .Q(app_addr_r2[4]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[5] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[5]),
        .Q(app_addr_r2[5]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[6] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[6]),
        .Q(app_addr_r2[6]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[7] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[7]),
        .Q(app_addr_r2[7]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[8] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[8]),
        .Q(app_addr_r2[8]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[9] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_addr_r1[9]),
        .Q(app_addr_r2[9]),
        .R(\app_addr_r1_reg[29]_0 ));
  FDRE \app_cmd_r1_reg[0] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(c0_ddr4_app_cmd[0]),
        .Q(app_cmd_r1[0]),
        .R(1'b0));
  FDRE \app_cmd_r1_reg[1] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(c0_ddr4_app_cmd[1]),
        .Q(app_cmd_r1[1]),
        .R(1'b0));
  FDRE \app_cmd_r1_reg[2] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(c0_ddr4_app_cmd[2]),
        .Q(app_cmd_r1[2]),
        .R(1'b0));
  FDRE \app_cmd_r2_reg[0] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_cmd_r1[0]),
        .Q(app_cmd_r2[0]),
        .R(1'b0));
  FDRE \app_cmd_r2_reg[1] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_cmd_r1[1]),
        .Q(app_cmd_r2[1]),
        .R(1'b0));
  FDRE \app_cmd_r2_reg[2] 
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(app_rdy_r_reg_0),
        .D(app_cmd_r1[2]),
        .Q(app_cmd_r2[2]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2901" *) 
  LUT4 #(
    .INIT(16'h2230)) 
    app_en_r1_i_1
       (.I0(c0_ddr4_app_en),
        .I1(\app_addr_r1_reg[29]_0 ),
        .I2(app_en_r1),
        .I3(app_rdy_r_reg_0),
        .O(app_en_ns1));
  FDRE app_en_r1_reg
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(1'b1),
        .D(app_en_ns1),
        .Q(app_en_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair2901" *) 
  LUT4 #(
    .INIT(16'h2230)) 
    app_en_r2_i_1
       (.I0(app_en_r1),
        .I1(\app_addr_r1_reg[29]_0 ),
        .I2(app_en_r2),
        .I3(app_rdy_r_reg_0),
        .O(app_en_ns2));
  FDRE app_en_r2_reg
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(1'b1),
        .D(app_en_ns2),
        .Q(app_en_r2),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    app_rdy_r_reg
       (.C(\app_cmd_r1_reg[2]_0 ),
        .CE(1'b1),
        .D(app_rdy_ns),
        .Q(app_rdy_r_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][0]_i_2 
       (.I0(\rams[0].RAM32M0 ),
        .I1(\buf_fifo_reg[1][4] ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][0] ),
        .O(accept_reg));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][0]_i_2__0 
       (.I0(\rams[0].RAM32M0 ),
        .I1(\buf_fifo_reg[1][4]_1 ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][0]_0 ),
        .O(accept_reg_4));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][0]_i_2__1 
       (.I0(\rams[0].RAM32M0 ),
        .I1(\buf_fifo_reg[1][4]_3 ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][0]_1 ),
        .O(accept_reg_9));
  LUT4 #(
    .INIT(16'hBE82)) 
    \buf_fifo[0][0]_i_4 
       (.I0(wr_data_buf_addr[0]),
        .I1(app_cmd_r2[1]),
        .I2(app_cmd_r2[0]),
        .I3(\buf_fifo[0][4]_i_2__2 [0]),
        .O(\rams[0].RAM32M0 ));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][1]_i_2 
       (.I0(\rams[0].RAM32M0_0 ),
        .I1(\buf_fifo_reg[1][4] ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][1] ),
        .O(accept_reg_0));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][1]_i_2__0 
       (.I0(\rams[0].RAM32M0_0 ),
        .I1(\buf_fifo_reg[1][4]_1 ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][1]_0 ),
        .O(accept_reg_5));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][1]_i_2__1 
       (.I0(\rams[0].RAM32M0_0 ),
        .I1(\buf_fifo_reg[1][4]_3 ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][1]_1 ),
        .O(accept_reg_10));
  LUT4 #(
    .INIT(16'hBE82)) 
    \buf_fifo[0][1]_i_4 
       (.I0(wr_data_buf_addr[1]),
        .I1(app_cmd_r2[1]),
        .I2(app_cmd_r2[0]),
        .I3(\buf_fifo[0][4]_i_2__2 [1]),
        .O(\rams[0].RAM32M0_0 ));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][2]_i_2 
       (.I0(\rams[1].RAM32M0 ),
        .I1(\buf_fifo_reg[1][4] ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][2] ),
        .O(accept_reg_1));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][2]_i_2__0 
       (.I0(\rams[1].RAM32M0 ),
        .I1(\buf_fifo_reg[1][4]_1 ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][2]_0 ),
        .O(accept_reg_6));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][2]_i_2__1 
       (.I0(\rams[1].RAM32M0 ),
        .I1(\buf_fifo_reg[1][4]_3 ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][2]_1 ),
        .O(accept_reg_11));
  LUT4 #(
    .INIT(16'hBE82)) 
    \buf_fifo[0][2]_i_4 
       (.I0(wr_data_buf_addr[2]),
        .I1(app_cmd_r2[1]),
        .I2(app_cmd_r2[0]),
        .I3(\buf_fifo[0][4]_i_2__2 [2]),
        .O(\rams[1].RAM32M0 ));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][3]_i_2 
       (.I0(\rams[1].RAM32M0_0 ),
        .I1(\buf_fifo_reg[1][4] ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][3] ),
        .O(accept_reg_2));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][3]_i_2__0 
       (.I0(\rams[1].RAM32M0_0 ),
        .I1(\buf_fifo_reg[1][4]_1 ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][3]_0 ),
        .O(accept_reg_7));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][3]_i_2__1 
       (.I0(\rams[1].RAM32M0_0 ),
        .I1(\buf_fifo_reg[1][4]_3 ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][3]_1 ),
        .O(accept_reg_12));
  LUT4 #(
    .INIT(16'hBE82)) 
    \buf_fifo[0][3]_i_4 
       (.I0(wr_data_buf_addr[3]),
        .I1(app_cmd_r2[1]),
        .I2(app_cmd_r2[0]),
        .I3(\buf_fifo[0][4]_i_2__2 [3]),
        .O(\rams[1].RAM32M0_0 ));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][4]_i_2 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .I1(\buf_fifo_reg[1][4] ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][4]_0 ),
        .O(accept_reg_3));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][4]_i_2__0 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .I1(\buf_fifo_reg[1][4]_1 ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][4]_2 ),
        .O(accept_reg_8));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \buf_fifo[0][4]_i_2__1 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ),
        .I1(\buf_fifo_reg[1][4]_3 ),
        .I2(accept_reg_14),
        .I3(app_en_r2_reg_0),
        .I4(\buf_fifo_reg[1][4]_4 ),
        .O(accept_reg_13));
  LUT3 #(
    .INIT(8'h28)) 
    \buf_fifo[0][4]_i_4 
       (.I0(\buf_fifo[0][4]_i_2__2 [4]),
        .I1(app_cmd_r2[0]),
        .I2(app_cmd_r2[1]),
        .O(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] ));
  (* SOFT_HLUTNM = "soft_lutpair2899" *) 
  LUT4 #(
    .INIT(16'h8008)) 
    \data_buf_addr_cnt_r[3]_i_1 
       (.I0(app_rdy_r_reg_0),
        .I1(app_en_r2),
        .I2(app_cmd_r2[0]),
        .I3(app_cmd_r2[1]),
        .O(wr_accepted));
  (* SOFT_HLUTNM = "soft_lutpair2900" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[4]_i_1 
       (.I0(app_cmd_r2[1]),
        .I1(app_cmd_r2[0]),
        .I2(app_rdy_r_reg_0),
        .I3(app_en_r2),
        .O(rd_accepted));
  LUT6 #(
    .INIT(64'h9AAAAAAA65555555)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[1]_i_1 
       (.I0(Q[0]),
        .I1(app_cmd_r2[1]),
        .I2(app_cmd_r2[0]),
        .I3(app_rdy_r_reg_0),
        .I4(app_en_r2),
        .I5(Q[1]),
        .O(D));
  LUT6 #(
    .INIT(64'h8888888878888888)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_1 
       (.I0(c0_ddr4_app_rd_data_end),
        .I1(out),
        .I2(app_en_r2),
        .I3(app_rdy_r_reg_0),
        .I4(app_cmd_r2[0]),
        .I5(app_cmd_r2[1]),
        .O(E));
  LUT6 #(
    .INIT(64'h5555D55500004000)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_3 
       (.I0(Q[1]),
        .I1(app_en_r2),
        .I2(app_rdy_r_reg_0),
        .I3(app_cmd_r2[0]),
        .I4(app_cmd_r2[1]),
        .I5(Q[0]),
        .O(\not_strict_mode.occupied_counter.occ_cnt_r_reg[1] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][0]_i_2 
       (.I0(app_addr_r1[4]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[4]),
        .O(bank[0]));
  (* SOFT_HLUTNM = "soft_lutpair2914" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][11]_i_2 
       (.I0(app_addr_r1[6]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[6]),
        .O(col[0]));
  (* SOFT_HLUTNM = "soft_lutpair2914" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][12]_i_2 
       (.I0(app_addr_r1[7]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[7]),
        .O(col[1]));
  (* SOFT_HLUTNM = "soft_lutpair2913" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][13]_i_2 
       (.I0(app_addr_r1[8]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[8]),
        .O(col[2]));
  (* SOFT_HLUTNM = "soft_lutpair2913" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][14]_i_2 
       (.I0(app_addr_r1[9]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[9]),
        .O(col[3]));
  (* SOFT_HLUTNM = "soft_lutpair2912" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][15]_i_2 
       (.I0(app_addr_r1[10]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[10]),
        .O(col[4]));
  (* SOFT_HLUTNM = "soft_lutpair2912" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][16]_i_2 
       (.I0(app_addr_r1[11]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[11]),
        .O(col[5]));
  (* SOFT_HLUTNM = "soft_lutpair2911" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][17]_i_2 
       (.I0(app_addr_r1[12]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[12]),
        .O(col[6]));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][1]_i_2 
       (.I0(app_addr_r1[5]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[5]),
        .O(bank[1]));
  (* SOFT_HLUTNM = "soft_lutpair2911" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][24]_i_2 
       (.I0(app_addr_r1[13]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[13]),
        .O(row_mc_phy[0]));
  (* SOFT_HLUTNM = "soft_lutpair2910" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][25]_i_2 
       (.I0(app_addr_r1[14]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[14]),
        .O(row_mc_phy[1]));
  (* SOFT_HLUTNM = "soft_lutpair2910" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][26]_i_2 
       (.I0(app_addr_r1[15]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[15]),
        .O(row_mc_phy[2]));
  (* SOFT_HLUTNM = "soft_lutpair2909" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][27]_i_2 
       (.I0(app_addr_r1[16]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[16]),
        .O(row_mc_phy[3]));
  (* SOFT_HLUTNM = "soft_lutpair2909" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][28]_i_2 
       (.I0(app_addr_r1[17]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[17]),
        .O(row_mc_phy[4]));
  (* SOFT_HLUTNM = "soft_lutpair2908" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][29]_i_2 
       (.I0(app_addr_r1[18]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[18]),
        .O(row_mc_phy[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][2]_i_2 
       (.I0(app_addr_r1[3]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[3]),
        .O(group));
  (* SOFT_HLUTNM = "soft_lutpair2908" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][30]_i_2 
       (.I0(app_addr_r1[19]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[19]),
        .O(row_mc_phy[6]));
  (* SOFT_HLUTNM = "soft_lutpair2907" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][31]_i_2 
       (.I0(app_addr_r1[20]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[20]),
        .O(row_mc_phy[7]));
  (* SOFT_HLUTNM = "soft_lutpair2907" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][32]_i_2 
       (.I0(app_addr_r1[21]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[21]),
        .O(row_mc_phy[8]));
  (* SOFT_HLUTNM = "soft_lutpair2906" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][33]_i_2 
       (.I0(app_addr_r1[22]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[22]),
        .O(row_mc_phy[9]));
  (* SOFT_HLUTNM = "soft_lutpair2906" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][34]_i_2 
       (.I0(app_addr_r1[23]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[23]),
        .O(row_mc_phy[10]));
  (* SOFT_HLUTNM = "soft_lutpair2905" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][35]_i_2 
       (.I0(app_addr_r1[24]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[24]),
        .O(row_mc_phy[11]));
  (* SOFT_HLUTNM = "soft_lutpair2905" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][36]_i_2 
       (.I0(app_addr_r1[25]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[25]),
        .O(row_mc_phy[12]));
  (* SOFT_HLUTNM = "soft_lutpair2904" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][37]_i_2 
       (.I0(app_addr_r1[26]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[26]),
        .O(row_mc_phy[13]));
  (* SOFT_HLUTNM = "soft_lutpair2904" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][38]_i_2 
       (.I0(app_addr_r1[27]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[27]),
        .O(row_mc_phy[14]));
  (* SOFT_HLUTNM = "soft_lutpair2903" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][39]_i_2 
       (.I0(app_addr_r1[28]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[28]),
        .O(row_mc_phy[15]));
  (* SOFT_HLUTNM = "soft_lutpair2903" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][40]_i_2 
       (.I0(app_addr_r1[29]),
        .I1(app_rdy_r_reg_0),
        .I2(app_addr_r2[29]),
        .O(row_mc_phy[16]));
  (* SOFT_HLUTNM = "soft_lutpair2902" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][44]_i_2 
       (.I0(app_cmd_r1[0]),
        .I1(app_rdy_r_reg_0),
        .I2(app_cmd_r2[0]),
        .O(cmd[0]));
  (* SOFT_HLUTNM = "soft_lutpair2900" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][45]_i_2 
       (.I0(app_cmd_r1[1]),
        .I1(app_rdy_r_reg_0),
        .I2(app_cmd_r2[1]),
        .O(cmd[1]));
  (* SOFT_HLUTNM = "soft_lutpair2902" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \txn_fifo[0][46]_i_2 
       (.I0(app_cmd_r1[2]),
        .I1(app_rdy_r_reg_0),
        .I2(app_cmd_r2[2]),
        .O(cmd[2]));
  LUT2 #(
    .INIT(4'h8)) 
    \txn_fifo_wptr[1]_i_2 
       (.I0(app_en_r2),
        .I1(app_rdy_r_reg_0),
        .O(app_en_r2_reg_0));
  LUT3 #(
    .INIT(8'h06)) 
    \wr_req_cnt_r[0]_i_1 
       (.I0(rd_data_upd_indx_r_reg),
        .I1(wr_req_cnt_r[0]),
        .I2(\app_addr_r1_reg[29]_0 ),
        .O(\wr_req_cnt_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hB22222222222B222)) 
    \wr_req_cnt_r[3]_i_2 
       (.I0(wr_req_cnt_r[0]),
        .I1(wr_req_cnt_r[1]),
        .I2(app_rdy_r_reg_0),
        .I3(app_en_r2),
        .I4(app_cmd_r2[0]),
        .I5(app_cmd_r2[1]),
        .O(\wr_req_cnt_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair2899" *) 
  LUT5 #(
    .INIT(32'h69AAAAAA)) 
    \wr_req_cnt_r[3]_i_3 
       (.I0(\wr_req_cnt_r_reg[0]_1 ),
        .I1(app_cmd_r2[1]),
        .I2(app_cmd_r2[0]),
        .I3(app_en_r2),
        .I4(app_rdy_r_reg_0),
        .O(rd_data_upd_indx_r_reg));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_ui_rd_data" *) 
module ddr4_0_ddr4_v2_2_17_ui_rd_data
   (Q,
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 ,
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 ,
    DOA,
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_0 ,
    DOB,
    DOC,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_1 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_2 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_0 ,
    out,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85]_0 ,
    \not_strict_mode.app_rd_data_valid_cpy_r_reg_0 ,
    c0_ddr4_app_rd_data_valid,
    c0_ddr4_app_rd_data_end,
    \rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 ,
    \not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 ,
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ,
    rd_buf_full0,
    \rd_data_indx_r_reg[3] ,
    pointer_wr_data,
    c0_ddr4_app_rd_data,
    \not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ,
    D,
    ADDRD,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,
    in0,
    \not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ,
    \not_strict_mode.app_rd_data_end_reg_0 ,
    rd_data_en_phy2mc,
    \not_strict_mode.bypass_cpy2 ,
    match4_13_return,
    match6_13_return,
    match4_14_return,
    match6_14_return,
    match4_15_return,
    match6_15_return,
    match4_16_return,
    match6_16_return,
    match4_17_return,
    match6_17_return,
    match4_18_return,
    match6_18_return,
    match4_19_return,
    match6_19_return,
    match4_110_return,
    match6_110_return,
    match4_111_return,
    match6_111_return,
    match4_112_return,
    match6_112_return,
    match4_113_return,
    match6_113_return,
    match4_114_return,
    match6_114_return,
    match4_115_return,
    match6_115_return,
    match4_116_return,
    match6_116_return,
    match4_117_return,
    match6_117_return,
    match4_118_return,
    match6_118_return,
    match4_119_return,
    match6_119_return,
    match4_120_return,
    match6_120_return,
    match4_121_return,
    match6_121_return,
    match4_122_return,
    match6_122_return,
    match4_123_return,
    match6_123_return,
    match4_124_return,
    match6_124_return,
    match4_125_return,
    match6_125_return,
    match4_126_return,
    match6_126_return,
    match4_127_return,
    match6_127_return,
    match4_128_return,
    match6_128_return,
    match4_129_return,
    match6_129_return,
    match4_130_return,
    match6_130_return,
    match4_131_return,
    match6_131_return,
    match4_132_return,
    match6_132_return,
    match4_133_return,
    match6_133_return,
    match4_134_return,
    match6_134_return,
    match4_135_return,
    match6_135_return,
    match4_136_return,
    match6_136_return,
    match4_137_return,
    match6_137_return,
    match4_138_return,
    match6_138_return,
    match4_139_return,
    match6_139_return,
    match4_140_return,
    match6_140_return,
    match4_141_return,
    match6_141_return,
    match4_142_return,
    match6_142_return,
    match4_143_return,
    match6_143_return,
    match4_144_return,
    match6_144_return,
    match4_145_return,
    match6_145_return,
    match4_146_return,
    match6_146_return,
    match4_147_return,
    match6_147_return,
    match4_148_return,
    match6_148_return,
    match4_149_return,
    match6_149_return,
    match4_150_return,
    match6_150_return,
    match4_151_return,
    match6_151_return,
    match4_152_return,
    match6_152_return,
    match4_153_return,
    match6_153_return,
    match4_154_return,
    match6_154_return,
    match4_155_return,
    match6_155_return,
    match4_156_return,
    match6_156_return,
    match4_157_return,
    match6_157_return,
    match4_158_return,
    match6_158_return,
    match4_159_return,
    match6_159_return,
    match4_160_return,
    match6_160_return,
    match4_161_return,
    match6_161_return,
    match4_162_return,
    match6_162_return,
    match4_163_return,
    match6_163_return,
    match4_164_return,
    match6_164_return,
    match4_165_return,
    match6_165_return,
    match4_166_return,
    match6_166_return,
    match4_167_return,
    match6_167_return,
    match4_168_return,
    match6_168_return,
    match4_169_return,
    match6_169_return,
    match4_170_return,
    match6_170_return,
    match4_171_return,
    match6_171_return,
    match4_172_return,
    match6_172_return,
    match4_173_return,
    match6_173_return,
    match4_174_return,
    match6_174_return,
    match4_175_return,
    match6_175_return,
    match4_176_return,
    match6_176_return,
    match4_177_return,
    match6_177_return,
    match4_178_return,
    match6_178_return,
    match4_179_return,
    match6_179_return,
    match4_180_return,
    match6_180_return,
    match4_181_return,
    match6_181_return,
    match4_182_return,
    match6_182_return,
    match4_183_return,
    match6_183_return,
    match4_184_return,
    match6_184_return,
    match4_185_return,
    match6_185_return,
    match4_186_return,
    match6_186_return,
    match4_187_return,
    match6_187_return,
    match4_188_return,
    match6_188_return,
    \not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_1 ,
    rd_accepted,
    match4_1_return,
    match6_1_return,
    match4_10_return,
    match6_10_return,
    match4_11_return,
    match6_11_return,
    match4_12_return,
    match6_12_return,
    \not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[4]_0 ,
    \rams[0].RAM32M0 ,
    ADDRC,
    \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ,
    \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ,
    E,
    \not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 );
  output [4:0]Q;
  output [4:0]\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 ;
  output [4:0]\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 ;
  output [0:0]DOA;
  output [4:0]\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_0 ;
  output [1:0]DOB;
  output [1:0]DOC;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_0 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_1 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_2 ;
  output [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_0 ;
  output [2:0]out;
  output [85:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85]_0 ;
  output \not_strict_mode.app_rd_data_valid_cpy_r_reg_0 ;
  output c0_ddr4_app_rd_data_valid;
  output c0_ddr4_app_rd_data_end;
  output [4:0]\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 ;
  output [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 ;
  output [2:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 ;
  output [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ;
  output rd_buf_full0;
  output [3:0]\rd_data_indx_r_reg[3] ;
  output [3:0]pointer_wr_data;
  output [511:0]c0_ddr4_app_rd_data;
  input \not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ;
  input [511:0]D;
  input [4:0]ADDRD;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ;
  input [85:0]in0;
  input \not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ;
  input \not_strict_mode.app_rd_data_end_reg_0 ;
  input rd_data_en_phy2mc;
  input \not_strict_mode.bypass_cpy2 ;
  input match4_13_return;
  input match6_13_return;
  input match4_14_return;
  input match6_14_return;
  input match4_15_return;
  input match6_15_return;
  input match4_16_return;
  input match6_16_return;
  input match4_17_return;
  input match6_17_return;
  input match4_18_return;
  input match6_18_return;
  input match4_19_return;
  input match6_19_return;
  input match4_110_return;
  input match6_110_return;
  input match4_111_return;
  input match6_111_return;
  input match4_112_return;
  input match6_112_return;
  input match4_113_return;
  input match6_113_return;
  input match4_114_return;
  input match6_114_return;
  input match4_115_return;
  input match6_115_return;
  input match4_116_return;
  input match6_116_return;
  input match4_117_return;
  input match6_117_return;
  input match4_118_return;
  input match6_118_return;
  input match4_119_return;
  input match6_119_return;
  input match4_120_return;
  input match6_120_return;
  input match4_121_return;
  input match6_121_return;
  input match4_122_return;
  input match6_122_return;
  input match4_123_return;
  input match6_123_return;
  input match4_124_return;
  input match6_124_return;
  input match4_125_return;
  input match6_125_return;
  input match4_126_return;
  input match6_126_return;
  input match4_127_return;
  input match6_127_return;
  input match4_128_return;
  input match6_128_return;
  input match4_129_return;
  input match6_129_return;
  input match4_130_return;
  input match6_130_return;
  input match4_131_return;
  input match6_131_return;
  input match4_132_return;
  input match6_132_return;
  input match4_133_return;
  input match6_133_return;
  input match4_134_return;
  input match6_134_return;
  input match4_135_return;
  input match6_135_return;
  input match4_136_return;
  input match6_136_return;
  input match4_137_return;
  input match6_137_return;
  input match4_138_return;
  input match6_138_return;
  input match4_139_return;
  input match6_139_return;
  input match4_140_return;
  input match6_140_return;
  input match4_141_return;
  input match6_141_return;
  input match4_142_return;
  input match6_142_return;
  input match4_143_return;
  input match6_143_return;
  input match4_144_return;
  input match6_144_return;
  input match4_145_return;
  input match6_145_return;
  input match4_146_return;
  input match6_146_return;
  input match4_147_return;
  input match6_147_return;
  input match4_148_return;
  input match6_148_return;
  input match4_149_return;
  input match6_149_return;
  input match4_150_return;
  input match6_150_return;
  input match4_151_return;
  input match6_151_return;
  input match4_152_return;
  input match6_152_return;
  input match4_153_return;
  input match6_153_return;
  input match4_154_return;
  input match6_154_return;
  input match4_155_return;
  input match6_155_return;
  input match4_156_return;
  input match6_156_return;
  input match4_157_return;
  input match6_157_return;
  input match4_158_return;
  input match6_158_return;
  input match4_159_return;
  input match6_159_return;
  input match4_160_return;
  input match6_160_return;
  input match4_161_return;
  input match6_161_return;
  input match4_162_return;
  input match6_162_return;
  input match4_163_return;
  input match6_163_return;
  input match4_164_return;
  input match6_164_return;
  input match4_165_return;
  input match6_165_return;
  input match4_166_return;
  input match6_166_return;
  input match4_167_return;
  input match6_167_return;
  input match4_168_return;
  input match6_168_return;
  input match4_169_return;
  input match6_169_return;
  input match4_170_return;
  input match6_170_return;
  input match4_171_return;
  input match6_171_return;
  input match4_172_return;
  input match6_172_return;
  input match4_173_return;
  input match6_173_return;
  input match4_174_return;
  input match6_174_return;
  input match4_175_return;
  input match6_175_return;
  input match4_176_return;
  input match6_176_return;
  input match4_177_return;
  input match6_177_return;
  input match4_178_return;
  input match6_178_return;
  input match4_179_return;
  input match6_179_return;
  input match4_180_return;
  input match6_180_return;
  input match4_181_return;
  input match6_181_return;
  input match4_182_return;
  input match6_182_return;
  input match4_183_return;
  input match6_183_return;
  input match4_184_return;
  input match6_184_return;
  input match4_185_return;
  input match6_185_return;
  input match4_186_return;
  input match6_186_return;
  input match4_187_return;
  input match6_187_return;
  input match4_188_return;
  input match6_188_return;
  input \not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_1 ;
  input rd_accepted;
  input match4_1_return;
  input match6_1_return;
  input match4_10_return;
  input match6_10_return;
  input match4_11_return;
  input match6_11_return;
  input match4_12_return;
  input match6_12_return;
  input [1:0]\not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[4]_0 ;
  input [3:0]\rams[0].RAM32M0 ;
  input [3:0]ADDRC;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ;
  input [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ;
  input [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ;
  input [0:0]E;
  input [0:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ;

  wire [4:0]ADDRA0;
  wire [3:0]ADDRC;
  wire [4:0]ADDRD;
  wire [511:0]D;
  wire [0:0]DOA;
  wire [1:0]DOB;
  wire [1:0]DOC;
  wire [0:0]E;
  wire [4:0]Q;
  wire app_rd_data_valid0;
  wire [511:0]c0_ddr4_app_rd_data;
  wire c0_ddr4_app_rd_data_end;
  wire c0_ddr4_app_rd_data_valid;
  wire match4_10_return;
  wire match4_110_return;
  wire match4_111_return;
  wire match4_112_return;
  wire match4_113_return;
  wire match4_114_return;
  wire match4_115_return;
  wire match4_116_return;
  wire match4_117_return;
  wire match4_118_return;
  wire match4_119_return;
  wire match4_11_return;
  wire match4_120_return;
  wire match4_121_return;
  wire match4_122_return;
  wire match4_123_return;
  wire match4_124_return;
  wire match4_125_return;
  wire match4_126_return;
  wire match4_127_return;
  wire match4_128_return;
  wire match4_129_return;
  wire match4_12_return;
  wire match4_130_return;
  wire match4_131_return;
  wire match4_132_return;
  wire match4_133_return;
  wire match4_134_return;
  wire match4_135_return;
  wire match4_136_return;
  wire match4_137_return;
  wire match4_138_return;
  wire match4_139_return;
  wire match4_13_return;
  wire match4_140_return;
  wire match4_141_return;
  wire match4_142_return;
  wire match4_143_return;
  wire match4_144_return;
  wire match4_145_return;
  wire match4_146_return;
  wire match4_147_return;
  wire match4_148_return;
  wire match4_149_return;
  wire match4_14_return;
  wire match4_150_return;
  wire match4_151_return;
  wire match4_152_return;
  wire match4_153_return;
  wire match4_154_return;
  wire match4_155_return;
  wire match4_156_return;
  wire match4_157_return;
  wire match4_158_return;
  wire match4_159_return;
  wire match4_15_return;
  wire match4_160_return;
  wire match4_161_return;
  wire match4_162_return;
  wire match4_163_return;
  wire match4_164_return;
  wire match4_165_return;
  wire match4_166_return;
  wire match4_167_return;
  wire match4_168_return;
  wire match4_169_return;
  wire match4_16_return;
  wire match4_170_return;
  wire match4_171_return;
  wire match4_172_return;
  wire match4_173_return;
  wire match4_174_return;
  wire match4_175_return;
  wire match4_176_return;
  wire match4_177_return;
  wire match4_178_return;
  wire match4_179_return;
  wire match4_17_return;
  wire match4_180_return;
  wire match4_181_return;
  wire match4_182_return;
  wire match4_183_return;
  wire match4_184_return;
  wire match4_185_return;
  wire match4_186_return;
  wire match4_187_return;
  wire match4_188_return;
  wire match4_18_return;
  wire match4_19_return;
  wire match4_1_return;
  wire match6_10_return;
  wire match6_110_return;
  wire match6_111_return;
  wire match6_112_return;
  wire match6_113_return;
  wire match6_114_return;
  wire match6_115_return;
  wire match6_116_return;
  wire match6_117_return;
  wire match6_118_return;
  wire match6_119_return;
  wire match6_11_return;
  wire match6_120_return;
  wire match6_121_return;
  wire match6_122_return;
  wire match6_123_return;
  wire match6_124_return;
  wire match6_125_return;
  wire match6_126_return;
  wire match6_127_return;
  wire match6_128_return;
  wire match6_129_return;
  wire match6_12_return;
  wire match6_130_return;
  wire match6_131_return;
  wire match6_132_return;
  wire match6_133_return;
  wire match6_134_return;
  wire match6_135_return;
  wire match6_136_return;
  wire match6_137_return;
  wire match6_138_return;
  wire match6_139_return;
  wire match6_13_return;
  wire match6_140_return;
  wire match6_141_return;
  wire match6_142_return;
  wire match6_143_return;
  wire match6_144_return;
  wire match6_145_return;
  wire match6_146_return;
  wire match6_147_return;
  wire match6_148_return;
  wire match6_149_return;
  wire match6_14_return;
  wire match6_150_return;
  wire match6_151_return;
  wire match6_152_return;
  wire match6_153_return;
  wire match6_154_return;
  wire match6_155_return;
  wire match6_156_return;
  wire match6_157_return;
  wire match6_158_return;
  wire match6_159_return;
  wire match6_15_return;
  wire match6_160_return;
  wire match6_161_return;
  wire match6_162_return;
  wire match6_163_return;
  wire match6_164_return;
  wire match6_165_return;
  wire match6_166_return;
  wire match6_167_return;
  wire match6_168_return;
  wire match6_169_return;
  wire match6_16_return;
  wire match6_170_return;
  wire match6_171_return;
  wire match6_172_return;
  wire match6_173_return;
  wire match6_174_return;
  wire match6_175_return;
  wire match6_176_return;
  wire match6_177_return;
  wire match6_178_return;
  wire match6_179_return;
  wire match6_17_return;
  wire match6_180_return;
  wire match6_181_return;
  wire match6_182_return;
  wire match6_183_return;
  wire match6_184_return;
  wire match6_185_return;
  wire match6_186_return;
  wire match6_187_return;
  wire match6_188_return;
  wire match6_18_return;
  wire match6_19_return;
  wire match6_1_return;
  wire \not_strict_mode.app_rd_data_end_reg_0 ;
  (* RTL_KEEP = "true" *) wire \not_strict_mode.app_rd_data_valid_cpy_r ;
  wire \not_strict_mode.bypass_cpy2 ;
  wire [4:0]\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 ;
  wire [5:0]\not_strict_mode.occ_cnt_r ;
  wire [4:2]\not_strict_mode.occupied_counter.occ_cnt_r_reg ;
  wire [0:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ;
  wire [2:0]\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 ;
  wire \not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_1 ;
  (* RTL_KEEP = "true" *) wire [3:0]\not_strict_mode.ram_init_done_r_lcl_sts ;
  (* RTL_KEEP = "true" *) wire [85:0]\not_strict_mode.rd_buf.init_done_r ;
  (* RTL_KEEP = "true" *) wire [85:0]\not_strict_mode.rd_buf.rd_buf_we ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[0].init_done_r[0]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[10].init_done_r[10]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[11].init_done_r[11]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[12].init_done_r[12]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[13].init_done_r[13]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[14].init_done_r[14]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[15].init_done_r[15]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[16].init_done_r[16]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[17].init_done_r[17]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[18].init_done_r[18]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[19].init_done_r[19]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[1].init_done_r[1]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[20].init_done_r[20]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[21].init_done_r[21]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[22].init_done_r[22]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[23].init_done_r[23]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[24].init_done_r[24]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[25].init_done_r[25]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[26].init_done_r[26]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[27].init_done_r[27]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[28].init_done_r[28]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[29].init_done_r[29]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[2].init_done_r[2]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[30].init_done_r[30]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[31].init_done_r[31]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[32].init_done_r[32]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[33].init_done_r[33]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[34].init_done_r[34]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[35].init_done_r[35]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[36].init_done_r[36]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[37].init_done_r[37]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[38].init_done_r[38]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[39].init_done_r[39]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[3].init_done_r[3]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[40].init_done_r[40]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[41].init_done_r[41]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[42].init_done_r[42]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[43].init_done_r[43]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[44].init_done_r[44]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[45].init_done_r[45]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[46].init_done_r[46]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[47].init_done_r[47]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[48].init_done_r[48]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[49].init_done_r[49]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[4].init_done_r[4]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[50].init_done_r[50]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[51].init_done_r[51]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[52].init_done_r[52]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[53].init_done_r[53]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[54].init_done_r[54]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[55].init_done_r[55]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[56].init_done_r[56]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[57].init_done_r[57]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[58].init_done_r[58]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[59].init_done_r[59]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_2 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[5].init_done_r[5]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[60].init_done_r[60]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[61].init_done_r[61]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[62].init_done_r[62]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[63].init_done_r[63]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[64].init_done_r[64]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[65].init_done_r[65]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[66].init_done_r[66]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[67].init_done_r[67]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[68].init_done_r[68]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[69].init_done_r[69]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[6].init_done_r[6]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[70].init_done_r[70]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[71].init_done_r[71]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[72].init_done_r[72]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[73].init_done_r[73]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[74].init_done_r[74]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[75].init_done_r[75]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[76].init_done_r[76]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[77].init_done_r[77]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[78].init_done_r[78]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[79].init_done_r[79]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[7].init_done_r[7]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[80].init_done_r[80]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[81].init_done_r[81]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[82].init_done_r[82]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[83].init_done_r[83]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[84].init_done_r[84]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r[85]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[8].init_done_r[8]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_0 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_1 ;
  wire [1:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_2 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4_n_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5_n_0 ;
  wire [5:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 ;
  wire \not_strict_mode.rd_buf.rd_buffer_ram[9].init_done_r[9]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 ;
  (* RTL_KEEP = "true" *) wire [85:0]\not_strict_mode.rd_buf.single_data_buf ;
  wire [85:0]\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy ;
  (* RTL_KEEP = "true" *) wire \not_strict_mode.rd_buf_we_r1 ;
  wire [0:0]\not_strict_mode.rd_status[0]_175 ;
  wire \not_strict_mode.rd_status[1]_168 ;
  wire \not_strict_mode.rd_status[2]_171 ;
  wire \not_strict_mode.rd_status[3]_174 ;
  wire \not_strict_mode.rd_status[4]_167 ;
  wire \not_strict_mode.rd_status[5]_170 ;
  wire \not_strict_mode.rd_status[6]_173 ;
  wire \not_strict_mode.status_ram_0.copies_of_sts_ram[0].rd_buf_we_r[0]_i_1_n_0 ;
  wire \not_strict_mode.status_ram_0.copies_of_sts_ram[1].rd_buf_we_r[1]_i_1_n_0 ;
  wire \not_strict_mode.status_ram_0.copies_of_sts_ram[2].rd_buf_we_r[2]_i_1_n_0 ;
  wire \not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ;
  (* RTL_KEEP = "true" *) wire [2:0]\not_strict_mode.status_ram_0.rd_buf_we_r ;
  wire \not_strict_mode.status_ram_0.rd_buf_we_r1_i_2_n_0 ;
  (* RTL_KEEP = "true" *) wire [4:0]\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_176 ;
  (* RTL_KEEP = "true" *) wire [4:0]\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_180 ;
  (* RTL_KEEP = "true" *) wire [4:0]\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_184 ;
  (* RTL_KEEP = "true" *) wire [4:0]\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[0]_177 ;
  (* RTL_KEEP = "true" *) wire [4:0]\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[1]_181 ;
  (* RTL_KEEP = "true" *) wire [4:0]\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[2]_185 ;
  wire [4:0]\not_strict_mode.status_ram_0.status_ram_wr_addr_ns ;
  wire [4:0]\not_strict_mode.status_ram_0.status_ram_wr_addr_r ;
  wire [1:0]\not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[4]_0 ;
  (* RTL_KEEP = "true" *) wire [1:0]\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 ;
  (* RTL_KEEP = "true" *) wire [1:0]\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 ;
  (* RTL_KEEP = "true" *) wire [1:0]\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 ;
  (* RTL_KEEP = "true" *) wire [1:0]\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[0]_179 ;
  (* RTL_KEEP = "true" *) wire [1:0]\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[1]_183 ;
  (* RTL_KEEP = "true" *) wire [1:0]\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[2]_187 ;
  wire [1:0]\not_strict_mode.status_ram_0.status_ram_wr_data_r ;
  wire \not_strict_mode.status_ram_0.status_ram_wr_data_r[0]_i_1_n_0 ;
  wire \not_strict_mode.status_ram_0.wr_status ;
  wire \not_strict_mode.status_ram_0.wr_status_cpy[0]_166 ;
  wire \not_strict_mode.status_ram_0.wr_status_cpy[1]_169 ;
  wire \not_strict_mode.status_ram_0.wr_status_cpy[2]_172 ;
  (* RTL_KEEP = "true" *) wire [2:0]\not_strict_mode.status_ram_0.wr_status_r ;
  wire \not_strict_mode.status_ram_signals[0].ram_init_done_r_lcl_sts[0]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 ;
  wire \not_strict_mode.status_ram_signals[1].ram_init_done_r_lcl_sts[1]_i_1_n_0 ;
  wire \not_strict_mode.status_ram_signals[2].ram_init_done_r_lcl_sts[2]_i_1_n_0 ;
  wire [4:0]\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 ;
  wire \not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts[3]_i_1_n_0 ;
  wire \not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ;
  wire [4:0]\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 ;
  wire [3:0]\not_strict_mode.upd_rd_buf_indx_sts ;
  wire p_0_in11_in;
  wire p_0_in13_in;
  wire p_0_in14_in;
  wire p_0_in15_in;
  wire p_0_in16_in;
  wire p_0_in17_in;
  wire p_0_in18_in;
  wire p_0_in19_in;
  wire p_0_in1_in;
  wire p_0_in20_in;
  wire p_0_in21_in;
  wire p_0_in22_in;
  wire p_0_in23_in;
  wire p_0_in24_in;
  wire p_0_in25_in;
  wire p_0_in26_in;
  wire p_0_in27_in;
  wire p_0_in28_in;
  wire p_0_in29_in;
  wire p_0_in30_in;
  wire p_0_in31_in;
  wire p_0_in32_in;
  wire p_0_in33_in;
  wire p_0_in34_in;
  wire p_0_in35_in;
  wire p_0_in36_in;
  wire p_0_in37_in;
  wire p_0_in38_in;
  wire p_0_in39_in;
  wire p_0_in3_in;
  wire p_0_in40_in;
  wire p_0_in41_in;
  wire p_0_in42_in;
  wire p_0_in43_in;
  wire p_0_in44_in;
  wire p_0_in45_in;
  wire p_0_in46_in;
  wire p_0_in47_in;
  wire p_0_in48_in;
  wire p_0_in49_in;
  wire p_0_in50_in;
  wire p_0_in51_in;
  wire p_0_in52_in;
  wire p_0_in53_in;
  wire p_0_in54_in;
  wire p_0_in55_in;
  wire p_0_in56_in;
  wire p_0_in57_in;
  wire p_0_in58_in;
  wire p_0_in59_in;
  wire p_0_in5_in;
  wire p_0_in60_in;
  wire p_0_in61_in;
  wire p_0_in62_in;
  wire p_0_in63_in;
  wire p_0_in64_in;
  wire p_0_in65_in;
  wire p_0_in66_in;
  wire p_0_in67_in;
  wire p_0_in68_in;
  wire p_0_in69_in;
  wire p_0_in70_in;
  wire p_0_in71_in;
  wire p_0_in72_in;
  wire p_0_in73_in;
  wire p_0_in74_in;
  wire p_0_in75_in;
  wire p_0_in76_in;
  wire p_0_in77_in;
  wire p_0_in78_in;
  wire p_0_in79_in;
  wire p_0_in7_in;
  wire p_0_in80_in;
  wire p_0_in81_in;
  wire p_0_in82_in;
  wire p_0_in83_in;
  wire p_0_in84_in;
  wire p_0_in85_in;
  wire p_0_in86_in;
  wire p_0_in87_in;
  wire p_0_in88_in;
  wire p_0_in89_in;
  wire p_0_in90_in;
  wire p_0_in91_in;
  wire p_0_in92_in;
  wire p_0_in93_in;
  wire p_0_in94_in;
  wire p_0_in95_in;
  wire p_0_in96_in;
  wire p_0_in9_in;
  wire p_0_in__0;
  wire [5:0]p_0_in__1;
  wire [5:0]p_0_in__10;
  wire [5:0]p_0_in__11;
  wire [5:0]p_0_in__12;
  wire [5:0]p_0_in__13;
  wire [5:0]p_0_in__14;
  wire [5:0]p_0_in__15;
  wire [5:0]p_0_in__16;
  wire [5:0]p_0_in__17;
  wire [5:0]p_0_in__18;
  wire [5:0]p_0_in__19;
  wire [5:0]p_0_in__1__0;
  wire [5:0]p_0_in__2;
  wire [5:0]p_0_in__20;
  wire [5:0]p_0_in__21;
  wire [5:0]p_0_in__22;
  wire [5:0]p_0_in__23;
  wire [5:0]p_0_in__24;
  wire [5:0]p_0_in__25;
  wire [5:0]p_0_in__26;
  wire [5:0]p_0_in__27;
  wire [5:0]p_0_in__28;
  wire [5:0]p_0_in__29;
  wire [5:0]p_0_in__3;
  wire [5:0]p_0_in__30;
  wire [5:0]p_0_in__31;
  wire [5:0]p_0_in__32;
  wire [5:0]p_0_in__33;
  wire [5:0]p_0_in__34;
  wire [5:0]p_0_in__35;
  wire [5:0]p_0_in__36;
  wire [5:0]p_0_in__37;
  wire [5:0]p_0_in__38;
  wire [5:0]p_0_in__39;
  wire [5:0]p_0_in__4;
  wire [5:0]p_0_in__40;
  wire [5:0]p_0_in__41;
  wire [5:0]p_0_in__42;
  wire [5:0]p_0_in__43;
  wire [5:0]p_0_in__44;
  wire [5:0]p_0_in__45;
  wire [5:0]p_0_in__46;
  wire [5:0]p_0_in__47;
  wire [5:0]p_0_in__48;
  wire [5:0]p_0_in__49;
  wire [5:0]p_0_in__5;
  wire [5:0]p_0_in__50;
  wire [5:0]p_0_in__51;
  wire [5:0]p_0_in__52;
  wire [5:0]p_0_in__53;
  wire [5:0]p_0_in__54;
  wire [5:0]p_0_in__55;
  wire [5:0]p_0_in__56;
  wire [5:0]p_0_in__57;
  wire [5:0]p_0_in__58;
  wire [5:0]p_0_in__59;
  wire [5:0]p_0_in__6;
  wire [5:0]p_0_in__60;
  wire [5:0]p_0_in__61;
  wire [5:0]p_0_in__62;
  wire [5:0]p_0_in__63;
  wire [5:0]p_0_in__64;
  wire [5:0]p_0_in__65;
  wire [5:0]p_0_in__66;
  wire [5:0]p_0_in__67;
  wire [5:0]p_0_in__68;
  wire [5:0]p_0_in__69;
  wire [5:0]p_0_in__7;
  wire [5:0]p_0_in__70;
  wire [5:0]p_0_in__71;
  wire [5:0]p_0_in__72;
  wire [5:0]p_0_in__73;
  wire [5:0]p_0_in__74;
  wire [5:0]p_0_in__75;
  wire [5:0]p_0_in__76;
  wire [5:0]p_0_in__77;
  wire [5:0]p_0_in__78;
  wire [5:0]p_0_in__79;
  wire [5:0]p_0_in__8;
  wire [5:0]p_0_in__80;
  wire [5:0]p_0_in__81;
  wire [5:0]p_0_in__82;
  wire [5:0]p_0_in__83;
  wire [5:0]p_0_in__84;
  wire [5:0]p_0_in__85;
  wire [5:0]p_0_in__86;
  wire [4:0]p_0_in__87;
  wire [5:0]p_0_in__88;
  wire [5:0]p_0_in__89;
  wire [5:0]p_0_in__9;
  wire [5:0]p_0_in__90;
  wire [5:0]p_0_in__91;
  wire [3:0]pointer_wr_data;
  (* RTL_KEEP = "true" *) wire [7:0]ram_init_done_r_lcl;
  wire \ram_init_done_r_lcl[7]_i_1_n_0 ;
  wire [3:0]\rams[0].RAM32M0 ;
  wire rd_accepted;
  wire rd_buf_full0;
  wire \rd_buf_index_cpy[0].rd_buf_indx_r[0][5]_i_1_n_0 ;
  wire [4:0]\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 ;
  wire rd_data_en_phy2mc;
  wire [3:0]\rd_data_indx_r_reg[3] ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOB_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.status_ram_0.RAM32M0_DOB_UNCONNECTED ;
  wire [1:1]\NLW_not_strict_mode.status_ram_0.RAM32M0_DOC_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.status_ram_0.RAM32M0_DOD_UNCONNECTED ;
  wire [1:1]\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[0].RAM32M1_DOA_UNCONNECTED ;
  wire [1:1]\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[0].RAM32M1_DOB_UNCONNECTED ;
  wire [1:1]\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[0].RAM32M1_DOC_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[0].RAM32M1_DOD_UNCONNECTED ;
  wire [1:1]\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[1].RAM32M1_DOA_UNCONNECTED ;
  wire [1:1]\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[1].RAM32M1_DOB_UNCONNECTED ;
  wire [1:1]\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[1].RAM32M1_DOC_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[1].RAM32M1_DOD_UNCONNECTED ;
  wire [1:1]\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[2].RAM32M1_DOA_UNCONNECTED ;
  wire [1:1]\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[2].RAM32M1_DOB_UNCONNECTED ;
  wire [1:1]\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[2].RAM32M1_DOC_UNCONNECTED ;
  wire [1:0]\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[2].RAM32M1_DOD_UNCONNECTED ;

  assign \not_strict_mode.app_rd_data_valid_cpy_r_reg_0  = \not_strict_mode.app_rd_data_valid_cpy_r ;
  assign \not_strict_mode.rd_buf.rd_buf_we  = in0[85:0];
  assign \not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85]_0 [85:0] = \not_strict_mode.rd_buf.init_done_r ;
  assign out[2] = ram_init_done_r_lcl[3];
  assign out[1:0] = ram_init_done_r_lcl[1:0];
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    app_rdy_r_i_3
       (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg [2]),
        .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg [4]),
        .I2(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [0]),
        .I3(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [1]),
        .I4(\not_strict_mode.occupied_counter.occ_cnt_r_reg [3]),
        .I5(rd_accepted),
        .O(rd_buf_full0));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [85]));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [84]));
  LUT1 #(
    .INIT(2'h2)) 
    i_10
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [75]));
  LUT1 #(
    .INIT(2'h2)) 
    i_11
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [74]));
  LUT1 #(
    .INIT(2'h2)) 
    i_12
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [73]));
  LUT1 #(
    .INIT(2'h2)) 
    i_13
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [72]));
  LUT1 #(
    .INIT(2'h2)) 
    i_14
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [71]));
  LUT1 #(
    .INIT(2'h2)) 
    i_15
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [70]));
  LUT1 #(
    .INIT(2'h2)) 
    i_16
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [69]));
  LUT1 #(
    .INIT(2'h2)) 
    i_17
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [68]));
  LUT1 #(
    .INIT(2'h2)) 
    i_18
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [67]));
  LUT1 #(
    .INIT(2'h2)) 
    i_19
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [66]));
  LUT1 #(
    .INIT(2'h2)) 
    i_2
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [83]));
  LUT1 #(
    .INIT(2'h2)) 
    i_20
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [65]));
  LUT1 #(
    .INIT(2'h2)) 
    i_21
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [64]));
  LUT1 #(
    .INIT(2'h2)) 
    i_22
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [63]));
  LUT1 #(
    .INIT(2'h2)) 
    i_23
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [62]));
  LUT1 #(
    .INIT(2'h2)) 
    i_24
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [61]));
  LUT1 #(
    .INIT(2'h2)) 
    i_25
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [60]));
  LUT1 #(
    .INIT(2'h2)) 
    i_26
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [59]));
  LUT1 #(
    .INIT(2'h2)) 
    i_27
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [58]));
  LUT1 #(
    .INIT(2'h2)) 
    i_28
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [57]));
  LUT1 #(
    .INIT(2'h2)) 
    i_29
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [56]));
  LUT1 #(
    .INIT(2'h2)) 
    i_3
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [82]));
  LUT1 #(
    .INIT(2'h2)) 
    i_30
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [55]));
  LUT1 #(
    .INIT(2'h2)) 
    i_31
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [54]));
  LUT1 #(
    .INIT(2'h2)) 
    i_32
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [53]));
  LUT1 #(
    .INIT(2'h2)) 
    i_33
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [52]));
  LUT1 #(
    .INIT(2'h2)) 
    i_34
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [51]));
  LUT1 #(
    .INIT(2'h2)) 
    i_35
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [50]));
  LUT1 #(
    .INIT(2'h2)) 
    i_36
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [49]));
  LUT1 #(
    .INIT(2'h2)) 
    i_37
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [48]));
  LUT1 #(
    .INIT(2'h2)) 
    i_38
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [47]));
  LUT1 #(
    .INIT(2'h2)) 
    i_39
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [46]));
  LUT1 #(
    .INIT(2'h2)) 
    i_4
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [81]));
  LUT1 #(
    .INIT(2'h2)) 
    i_40
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [45]));
  LUT1 #(
    .INIT(2'h2)) 
    i_41
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [44]));
  LUT1 #(
    .INIT(2'h2)) 
    i_42
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [43]));
  LUT1 #(
    .INIT(2'h2)) 
    i_43
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [42]));
  LUT1 #(
    .INIT(2'h2)) 
    i_44
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [41]));
  LUT1 #(
    .INIT(2'h2)) 
    i_45
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [40]));
  LUT1 #(
    .INIT(2'h2)) 
    i_46
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [39]));
  LUT1 #(
    .INIT(2'h2)) 
    i_47
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [38]));
  LUT1 #(
    .INIT(2'h2)) 
    i_48
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [37]));
  LUT1 #(
    .INIT(2'h2)) 
    i_49
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [36]));
  LUT1 #(
    .INIT(2'h2)) 
    i_5
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [80]));
  LUT1 #(
    .INIT(2'h2)) 
    i_50
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [35]));
  LUT1 #(
    .INIT(2'h2)) 
    i_51
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [34]));
  LUT1 #(
    .INIT(2'h2)) 
    i_52
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [33]));
  LUT1 #(
    .INIT(2'h2)) 
    i_53
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [32]));
  LUT1 #(
    .INIT(2'h2)) 
    i_54
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [31]));
  LUT1 #(
    .INIT(2'h2)) 
    i_55
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [30]));
  LUT1 #(
    .INIT(2'h2)) 
    i_56
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [29]));
  LUT1 #(
    .INIT(2'h2)) 
    i_57
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [28]));
  LUT1 #(
    .INIT(2'h2)) 
    i_58
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [27]));
  LUT1 #(
    .INIT(2'h2)) 
    i_59
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [26]));
  LUT1 #(
    .INIT(2'h2)) 
    i_6
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [79]));
  LUT1 #(
    .INIT(2'h2)) 
    i_60
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [25]));
  LUT1 #(
    .INIT(2'h2)) 
    i_61
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [24]));
  LUT1 #(
    .INIT(2'h2)) 
    i_62
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [23]));
  LUT1 #(
    .INIT(2'h2)) 
    i_63
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [22]));
  LUT1 #(
    .INIT(2'h2)) 
    i_64
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [21]));
  LUT1 #(
    .INIT(2'h2)) 
    i_65
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [20]));
  LUT1 #(
    .INIT(2'h2)) 
    i_66
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [19]));
  LUT1 #(
    .INIT(2'h2)) 
    i_67
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [18]));
  LUT1 #(
    .INIT(2'h2)) 
    i_68
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [17]));
  LUT1 #(
    .INIT(2'h2)) 
    i_69
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [16]));
  LUT1 #(
    .INIT(2'h2)) 
    i_7
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [78]));
  LUT1 #(
    .INIT(2'h2)) 
    i_70
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [15]));
  LUT1 #(
    .INIT(2'h2)) 
    i_71
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [14]));
  LUT1 #(
    .INIT(2'h2)) 
    i_72
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [13]));
  LUT1 #(
    .INIT(2'h2)) 
    i_73
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [12]));
  LUT1 #(
    .INIT(2'h2)) 
    i_74
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [11]));
  LUT1 #(
    .INIT(2'h2)) 
    i_75
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [10]));
  LUT1 #(
    .INIT(2'h2)) 
    i_76
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [9]));
  LUT1 #(
    .INIT(2'h2)) 
    i_77
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [8]));
  LUT1 #(
    .INIT(2'h2)) 
    i_78
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [7]));
  LUT1 #(
    .INIT(2'h2)) 
    i_79
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [6]));
  LUT1 #(
    .INIT(2'h2)) 
    i_8
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [77]));
  LUT1 #(
    .INIT(2'h2)) 
    i_80
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [5]));
  LUT1 #(
    .INIT(2'h2)) 
    i_81
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [4]));
  LUT1 #(
    .INIT(2'h2)) 
    i_82
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [3]));
  LUT1 #(
    .INIT(2'h2)) 
    i_83
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_84
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_85
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_9
       (.I0(1'b0),
        .O(\not_strict_mode.rd_buf.single_data_buf [76]));
  FDRE \not_strict_mode.app_rd_data_end_reg 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.app_rd_data_end_reg_0 ),
        .Q(c0_ddr4_app_rd_data_end),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.app_rd_data_valid_cpy_r_reg 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(ram_init_done_r_lcl[7]),
        .D(app_rd_data_valid0),
        .Q(\not_strict_mode.app_rd_data_valid_cpy_r ),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT3 #(
    .INIT(8'hEB)) 
    \not_strict_mode.app_rd_data_valid_i_1 
       (.I0(\not_strict_mode.bypass_cpy2 ),
        .I1(\not_strict_mode.rd_status[0]_175 ),
        .I2(p_0_in__0),
        .O(app_rd_data_valid0));
  FDRE \not_strict_mode.app_rd_data_valid_reg 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(ram_init_done_r_lcl[5]),
        .D(app_rd_data_valid0),
        .Q(c0_ddr4_app_rd_data_valid),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[0]_i_1 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),
        .O(p_0_in__87[0]));
  (* SOFT_HLUTNM = "soft_lutpair3099" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[1]_i_1 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),
        .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),
        .O(p_0_in__87[1]));
  (* SOFT_HLUTNM = "soft_lutpair3099" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[2]_i_1 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),
        .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),
        .I2(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),
        .O(p_0_in__87[2]));
  (* SOFT_HLUTNM = "soft_lutpair3007" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[3]_i_1 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),
        .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),
        .I2(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),
        .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]),
        .O(p_0_in__87[3]));
  (* SOFT_HLUTNM = "soft_lutpair3007" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl[4]_i_2 
       (.I0(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),
        .I1(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),
        .I2(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),
        .I3(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]),
        .I4(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [4]),
        .O(p_0_in__87[4]));
  FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(rd_accepted),
        .D(p_0_in__87[0]),
        .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(rd_accepted),
        .D(p_0_in__87[1]),
        .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(rd_accepted),
        .D(p_0_in__87[2]),
        .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(rd_accepted),
        .D(p_0_in__87[3]),
        .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(rd_accepted),
        .D(p_0_in__87[4]),
        .Q(\not_strict_mode.data_buf_addr.rd_data_buf_addr_r_lcl_reg[4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[0]_i_1 
       (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [0]),
        .O(\not_strict_mode.occ_cnt_r [0]));
  (* SOFT_HLUTNM = "soft_lutpair2915" *) 
  LUT4 #(
    .INIT(16'h78E1)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[2]_i_1 
       (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [0]),
        .I1(rd_accepted),
        .I2(\not_strict_mode.occupied_counter.occ_cnt_r_reg [2]),
        .I3(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [1]),
        .O(\not_strict_mode.occ_cnt_r [2]));
  (* SOFT_HLUTNM = "soft_lutpair2915" *) 
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[3]_i_1 
       (.I0(rd_accepted),
        .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [0]),
        .I2(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [1]),
        .I3(\not_strict_mode.occupied_counter.occ_cnt_r_reg [3]),
        .I4(\not_strict_mode.occupied_counter.occ_cnt_r_reg [2]),
        .O(\not_strict_mode.occ_cnt_r [3]));
  LUT6 #(
    .INIT(64'h7FFF8000FFFE0001)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[4]_i_1 
       (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [1]),
        .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [0]),
        .I2(rd_accepted),
        .I3(\not_strict_mode.occupied_counter.occ_cnt_r_reg [2]),
        .I4(\not_strict_mode.occupied_counter.occ_cnt_r_reg [4]),
        .I5(\not_strict_mode.occupied_counter.occ_cnt_r_reg [3]),
        .O(\not_strict_mode.occ_cnt_r [4]));
  LUT6 #(
    .INIT(64'h7FFF8000FFFE0001)) 
    \not_strict_mode.occupied_counter.occ_cnt_r[5]_i_2 
       (.I0(\not_strict_mode.occupied_counter.occ_cnt_r_reg [2]),
        .I1(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_1 ),
        .I2(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [1]),
        .I3(\not_strict_mode.occupied_counter.occ_cnt_r_reg [3]),
        .I4(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [2]),
        .I5(\not_strict_mode.occupied_counter.occ_cnt_r_reg [4]),
        .O(\not_strict_mode.occ_cnt_r [5]));
  FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(E),
        .D(\not_strict_mode.occ_cnt_r [0]),
        .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(E),
        .D(\not_strict_mode.occupied_counter.occ_cnt_r_reg[1]_0 ),
        .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(E),
        .D(\not_strict_mode.occ_cnt_r [2]),
        .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(E),
        .D(\not_strict_mode.occ_cnt_r [3]),
        .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(E),
        .D(\not_strict_mode.occ_cnt_r [4]),
        .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.occupied_counter.occ_cnt_r_reg[5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(E),
        .D(\not_strict_mode.occ_cnt_r [5]),
        .Q(\not_strict_mode.occupied_counter.occ_cnt_r_reg[5]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    \not_strict_mode.ram_init_done_r_lcl_sts_inst 
       (.I0(\not_strict_mode.ram_init_done_r_lcl_sts [3]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 [1]));
  LUT1 #(
    .INIT(2'h2)) 
    \not_strict_mode.ram_init_done_r_lcl_sts_inst__0 
       (.I0(\not_strict_mode.ram_init_done_r_lcl_sts [2]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 [1]));
  LUT1 #(
    .INIT(2'h2)) 
    \not_strict_mode.ram_init_done_r_lcl_sts_inst__1 
       (.I0(\not_strict_mode.ram_init_done_r_lcl_sts [1]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 [1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[40],D[32]}),
        .DIB({D[24],D[16]}),
        .DIC({D[8],D[0]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_0 ),
        .DOB(DOB),
        .DOC(DOC),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [0]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [0]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[0].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [0]),
        .Q(c0_ddr4_app_rd_data[0]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [1]),
        .Q(c0_ddr4_app_rd_data[1]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [2]),
        .Q(c0_ddr4_app_rd_data[2]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [3]),
        .Q(c0_ddr4_app_rd_data[3]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [4]),
        .Q(c0_ddr4_app_rd_data[4]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[0].app_rd_data_ns_reg[5]_0 [5]),
        .Q(c0_ddr4_app_rd_data[5]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].init_done_r[0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [0]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[0].init_done_r[0]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].init_done_r_reg[0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[0].init_done_r[0]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r[0][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .O(p_0_in__1__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair3008" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r[0][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [1]),
        .O(p_0_in__1__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair3008" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r[0][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [2]),
        .O(p_0_in__1__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair2916" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r[0][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [3]),
        .O(p_0_in__1__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair2916" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r[0][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [4]),
        .O(p_0_in__1__0[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r[0][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [0]),
        .I1(match4_13_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_13_return),
        .I4(p_0_in1_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [0]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r[0][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [4]),
        .I5(p_0_in1_in),
        .O(p_0_in__1__0[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [0]),
        .D(p_0_in__1__0[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [0]),
        .D(p_0_in__1__0[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [0]),
        .D(p_0_in__1__0[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [0]),
        .D(p_0_in__1__0[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [0]),
        .D(p_0_in__1__0[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[0].rd_buf_indx_cpy_r_reg[0][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [0]),
        .D(p_0_in__1__0[5]),
        .Q(p_0_in1_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[72],D[64]}),
        .DIB({D[63],D[55]}),
        .DIC({D[47],D[39]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [10]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [10]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [10]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [10]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [10]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [10]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[10].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[60] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [0]),
        .Q(c0_ddr4_app_rd_data[60]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[61] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [1]),
        .Q(c0_ddr4_app_rd_data[61]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[62] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [2]),
        .Q(c0_ddr4_app_rd_data[62]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[63] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [3]),
        .Q(c0_ddr4_app_rd_data[63]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[64] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [4]),
        .Q(c0_ddr4_app_rd_data[64]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[10].app_rd_data_ns_reg[65]_0 [5]),
        .Q(c0_ddr4_app_rd_data[65]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].init_done_r[10]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [10]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[10].init_done_r[10]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].init_done_r_reg[10] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[10].init_done_r[10]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [10]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r[10][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .O(p_0_in__11[0]));
  (* SOFT_HLUTNM = "soft_lutpair3018" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r[10][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [1]),
        .O(p_0_in__11[1]));
  (* SOFT_HLUTNM = "soft_lutpair3018" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r[10][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [2]),
        .O(p_0_in__11[2]));
  (* SOFT_HLUTNM = "soft_lutpair2926" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r[10][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [3]),
        .O(p_0_in__11[3]));
  (* SOFT_HLUTNM = "soft_lutpair2926" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r[10][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [4]),
        .O(p_0_in__11[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r[10][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [10]),
        .I1(match4_113_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_113_return),
        .I4(p_0_in17_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [10]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r[10][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [4]),
        .I5(p_0_in17_in),
        .O(p_0_in__11[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [10]),
        .D(p_0_in__11[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [10]),
        .D(p_0_in__11[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [10]),
        .D(p_0_in__11[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [10]),
        .D(p_0_in__11[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [10]),
        .D(p_0_in__11[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[10].rd_buf_indx_cpy_r_reg[10][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [10]),
        .D(p_0_in__11[5]),
        .Q(p_0_in17_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[120],D[112]}),
        .DIB({D[104],D[96]}),
        .DIC({D[88],D[80]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [11]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [11]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [11]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [11]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [11]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [11]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[11].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[66] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [0]),
        .Q(c0_ddr4_app_rd_data[66]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[67] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [1]),
        .Q(c0_ddr4_app_rd_data[67]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[68] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [2]),
        .Q(c0_ddr4_app_rd_data[68]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[69] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [3]),
        .Q(c0_ddr4_app_rd_data[69]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[70] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [4]),
        .Q(c0_ddr4_app_rd_data[70]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[11].app_rd_data_ns_reg[71]_0 [5]),
        .Q(c0_ddr4_app_rd_data[71]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].init_done_r[11]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [11]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[11].init_done_r[11]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].init_done_r_reg[11] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[11].init_done_r[11]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [11]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r[11][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .O(p_0_in__12[0]));
  (* SOFT_HLUTNM = "soft_lutpair3019" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r[11][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [1]),
        .O(p_0_in__12[1]));
  (* SOFT_HLUTNM = "soft_lutpair3019" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r[11][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [2]),
        .O(p_0_in__12[2]));
  (* SOFT_HLUTNM = "soft_lutpair2927" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r[11][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [3]),
        .O(p_0_in__12[3]));
  (* SOFT_HLUTNM = "soft_lutpair2927" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r[11][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [4]),
        .O(p_0_in__12[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r[11][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [11]),
        .I1(match4_114_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_114_return),
        .I4(p_0_in18_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [11]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r[11][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [4]),
        .I5(p_0_in18_in),
        .O(p_0_in__12[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [11]),
        .D(p_0_in__12[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [11]),
        .D(p_0_in__12[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [11]),
        .D(p_0_in__12[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [11]),
        .D(p_0_in__12[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [11]),
        .D(p_0_in__12[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[11].rd_buf_indx_cpy_r_reg[11][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [11]),
        .D(p_0_in__12[5]),
        .Q(p_0_in18_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[105],D[97]}),
        .DIB({D[89],D[81]}),
        .DIC({D[73],D[65]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [12]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [12]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [12]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [12]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [12]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [12]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[12].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[72] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [0]),
        .Q(c0_ddr4_app_rd_data[72]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[73] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [1]),
        .Q(c0_ddr4_app_rd_data[73]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[74] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [2]),
        .Q(c0_ddr4_app_rd_data[74]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[75] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [3]),
        .Q(c0_ddr4_app_rd_data[75]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[76] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [4]),
        .Q(c0_ddr4_app_rd_data[76]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[12].app_rd_data_ns_reg[77]_0 [5]),
        .Q(c0_ddr4_app_rd_data[77]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].init_done_r[12]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [12]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[12].init_done_r[12]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].init_done_r_reg[12] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[12].init_done_r[12]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [12]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r[12][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .O(p_0_in__13[0]));
  (* SOFT_HLUTNM = "soft_lutpair3020" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r[12][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [1]),
        .O(p_0_in__13[1]));
  (* SOFT_HLUTNM = "soft_lutpair3020" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r[12][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [2]),
        .O(p_0_in__13[2]));
  (* SOFT_HLUTNM = "soft_lutpair2928" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r[12][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [3]),
        .O(p_0_in__13[3]));
  (* SOFT_HLUTNM = "soft_lutpair2928" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r[12][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [4]),
        .O(p_0_in__13[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r[12][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [12]),
        .I1(match4_115_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_115_return),
        .I4(p_0_in19_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [12]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r[12][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [4]),
        .I5(p_0_in19_in),
        .O(p_0_in__13[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [12]),
        .D(p_0_in__13[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [12]),
        .D(p_0_in__13[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [12]),
        .D(p_0_in__13[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [12]),
        .D(p_0_in__13[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [12]),
        .D(p_0_in__13[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[12].rd_buf_indx_cpy_r_reg[12][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [12]),
        .D(p_0_in__13[5]),
        .Q(p_0_in19_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[90],D[82]}),
        .DIB({D[74],D[66]}),
        .DIC({D[121],D[113]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [13]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [13]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [13]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [13]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [13]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [13]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[13].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[78] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [0]),
        .Q(c0_ddr4_app_rd_data[78]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[79] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [1]),
        .Q(c0_ddr4_app_rd_data[79]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[80] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [2]),
        .Q(c0_ddr4_app_rd_data[80]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[81] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [3]),
        .Q(c0_ddr4_app_rd_data[81]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[82] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [4]),
        .Q(c0_ddr4_app_rd_data[82]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[13].app_rd_data_ns_reg[83]_0 [5]),
        .Q(c0_ddr4_app_rd_data[83]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].init_done_r[13]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [13]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[13].init_done_r[13]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].init_done_r_reg[13] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[13].init_done_r[13]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [13]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r[13][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .O(p_0_in__14[0]));
  (* SOFT_HLUTNM = "soft_lutpair3021" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r[13][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [1]),
        .O(p_0_in__14[1]));
  (* SOFT_HLUTNM = "soft_lutpair3021" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r[13][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [2]),
        .O(p_0_in__14[2]));
  (* SOFT_HLUTNM = "soft_lutpair2929" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r[13][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [3]),
        .O(p_0_in__14[3]));
  (* SOFT_HLUTNM = "soft_lutpair2929" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r[13][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [4]),
        .O(p_0_in__14[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r[13][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [13]),
        .I1(match4_116_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_116_return),
        .I4(p_0_in20_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [13]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r[13][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [4]),
        .I5(p_0_in20_in),
        .O(p_0_in__14[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [13]),
        .D(p_0_in__14[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [13]),
        .D(p_0_in__14[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [13]),
        .D(p_0_in__14[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [13]),
        .D(p_0_in__14[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [13]),
        .D(p_0_in__14[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[13].rd_buf_indx_cpy_r_reg[13][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [13]),
        .D(p_0_in__14[5]),
        .Q(p_0_in20_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[75],D[67]}),
        .DIB({D[122],D[114]}),
        .DIC({D[106],D[98]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [14]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [14]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [14]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [14]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [14]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [14]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[14].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[84] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [0]),
        .Q(c0_ddr4_app_rd_data[84]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[85] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [1]),
        .Q(c0_ddr4_app_rd_data[85]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[86] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [2]),
        .Q(c0_ddr4_app_rd_data[86]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[87] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [3]),
        .Q(c0_ddr4_app_rd_data[87]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[88] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [4]),
        .Q(c0_ddr4_app_rd_data[88]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[14].app_rd_data_ns_reg[89]_0 [5]),
        .Q(c0_ddr4_app_rd_data[89]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].init_done_r[14]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [14]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[14].init_done_r[14]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].init_done_r_reg[14] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[14].init_done_r[14]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [14]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r[14][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .O(p_0_in__15[0]));
  (* SOFT_HLUTNM = "soft_lutpair3022" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r[14][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [1]),
        .O(p_0_in__15[1]));
  (* SOFT_HLUTNM = "soft_lutpair3022" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r[14][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [2]),
        .O(p_0_in__15[2]));
  (* SOFT_HLUTNM = "soft_lutpair2930" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r[14][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [3]),
        .O(p_0_in__15[3]));
  (* SOFT_HLUTNM = "soft_lutpair2930" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r[14][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [4]),
        .O(p_0_in__15[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r[14][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [14]),
        .I1(match4_117_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_117_return),
        .I4(p_0_in21_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [14]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r[14][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [4]),
        .I5(p_0_in21_in),
        .O(p_0_in__15[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [14]),
        .D(p_0_in__15[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [14]),
        .D(p_0_in__15[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [14]),
        .D(p_0_in__15[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [14]),
        .D(p_0_in__15[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [14]),
        .D(p_0_in__15[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[14].rd_buf_indx_cpy_r_reg[14][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [14]),
        .D(p_0_in__15[5]),
        .Q(p_0_in21_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[123],D[115]}),
        .DIB({D[107],D[99]}),
        .DIC({D[91],D[83]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [15]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [15]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [15]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [15]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [15]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [15]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[15].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[90] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [0]),
        .Q(c0_ddr4_app_rd_data[90]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[91] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [1]),
        .Q(c0_ddr4_app_rd_data[91]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[92] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [2]),
        .Q(c0_ddr4_app_rd_data[92]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[93] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [3]),
        .Q(c0_ddr4_app_rd_data[93]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[94] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [4]),
        .Q(c0_ddr4_app_rd_data[94]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[15].app_rd_data_ns_reg[95]_0 [5]),
        .Q(c0_ddr4_app_rd_data[95]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].init_done_r[15]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [15]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[15].init_done_r[15]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].init_done_r_reg[15] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[15].init_done_r[15]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [15]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r[15][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .O(p_0_in__16[0]));
  (* SOFT_HLUTNM = "soft_lutpair3023" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r[15][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [1]),
        .O(p_0_in__16[1]));
  (* SOFT_HLUTNM = "soft_lutpair3023" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r[15][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [2]),
        .O(p_0_in__16[2]));
  (* SOFT_HLUTNM = "soft_lutpair2931" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r[15][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [3]),
        .O(p_0_in__16[3]));
  (* SOFT_HLUTNM = "soft_lutpair2931" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r[15][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [4]),
        .O(p_0_in__16[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r[15][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [15]),
        .I1(match4_118_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_118_return),
        .I4(p_0_in22_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [15]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r[15][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [4]),
        .I5(p_0_in22_in),
        .O(p_0_in__16[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [15]),
        .D(p_0_in__16[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [15]),
        .D(p_0_in__16[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [15]),
        .D(p_0_in__16[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [15]),
        .D(p_0_in__16[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [15]),
        .D(p_0_in__16[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[15].rd_buf_indx_cpy_r_reg[15][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [15]),
        .D(p_0_in__16[5]),
        .Q(p_0_in22_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[108],D[100]}),
        .DIB({D[92],D[84]}),
        .DIC({D[76],D[68]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [16]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [16]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [16]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [16]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [16]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [16]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[16].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[100] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [4]),
        .Q(c0_ddr4_app_rd_data[100]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [5]),
        .Q(c0_ddr4_app_rd_data[101]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[96] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [0]),
        .Q(c0_ddr4_app_rd_data[96]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[97] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [1]),
        .Q(c0_ddr4_app_rd_data[97]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[98] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [2]),
        .Q(c0_ddr4_app_rd_data[98]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[99] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[16].app_rd_data_ns_reg[101]_0 [3]),
        .Q(c0_ddr4_app_rd_data[99]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].init_done_r[16]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [16]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[16].init_done_r[16]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].init_done_r_reg[16] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[16].init_done_r[16]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [16]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r[16][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .O(p_0_in__17[0]));
  (* SOFT_HLUTNM = "soft_lutpair3024" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r[16][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [1]),
        .O(p_0_in__17[1]));
  (* SOFT_HLUTNM = "soft_lutpair3024" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r[16][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [2]),
        .O(p_0_in__17[2]));
  (* SOFT_HLUTNM = "soft_lutpair2932" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r[16][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [3]),
        .O(p_0_in__17[3]));
  (* SOFT_HLUTNM = "soft_lutpair2932" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r[16][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [4]),
        .O(p_0_in__17[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r[16][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [16]),
        .I1(match4_119_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_119_return),
        .I4(p_0_in23_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [16]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r[16][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [4]),
        .I5(p_0_in23_in),
        .O(p_0_in__17[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [16]),
        .D(p_0_in__17[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [16]),
        .D(p_0_in__17[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [16]),
        .D(p_0_in__17[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [16]),
        .D(p_0_in__17[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [16]),
        .D(p_0_in__17[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[16].rd_buf_indx_cpy_r_reg[16][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [16]),
        .D(p_0_in__17[5]),
        .Q(p_0_in23_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[93],D[85]}),
        .DIB({D[77],D[69]}),
        .DIC({D[124],D[116]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [17]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [17]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [17]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [17]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [17]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [17]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[17].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[102] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [0]),
        .Q(c0_ddr4_app_rd_data[102]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[103] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [1]),
        .Q(c0_ddr4_app_rd_data[103]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[104] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [2]),
        .Q(c0_ddr4_app_rd_data[104]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[105] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [3]),
        .Q(c0_ddr4_app_rd_data[105]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[106] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [4]),
        .Q(c0_ddr4_app_rd_data[106]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[17].app_rd_data_ns_reg[107]_0 [5]),
        .Q(c0_ddr4_app_rd_data[107]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].init_done_r[17]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [17]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[17].init_done_r[17]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].init_done_r_reg[17] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[17].init_done_r[17]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [17]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r[17][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .O(p_0_in__18[0]));
  (* SOFT_HLUTNM = "soft_lutpair3025" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r[17][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [1]),
        .O(p_0_in__18[1]));
  (* SOFT_HLUTNM = "soft_lutpair3025" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r[17][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [2]),
        .O(p_0_in__18[2]));
  (* SOFT_HLUTNM = "soft_lutpair2933" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r[17][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [3]),
        .O(p_0_in__18[3]));
  (* SOFT_HLUTNM = "soft_lutpair2933" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r[17][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [4]),
        .O(p_0_in__18[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r[17][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [17]),
        .I1(match4_120_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_120_return),
        .I4(p_0_in24_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [17]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r[17][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [4]),
        .I5(p_0_in24_in),
        .O(p_0_in__18[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [17]),
        .D(p_0_in__18[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [17]),
        .D(p_0_in__18[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [17]),
        .D(p_0_in__18[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [17]),
        .D(p_0_in__18[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [17]),
        .D(p_0_in__18[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[17].rd_buf_indx_cpy_r_reg[17][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [17]),
        .D(p_0_in__18[5]),
        .Q(p_0_in24_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[78],D[70]}),
        .DIB({D[125],D[117]}),
        .DIC({D[109],D[101]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [18]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [18]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [18]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [18]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [18]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [18]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[18].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[108] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [0]),
        .Q(c0_ddr4_app_rd_data[108]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[109] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [1]),
        .Q(c0_ddr4_app_rd_data[109]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[110] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [2]),
        .Q(c0_ddr4_app_rd_data[110]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[111] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [3]),
        .Q(c0_ddr4_app_rd_data[111]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[112] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [4]),
        .Q(c0_ddr4_app_rd_data[112]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[18].app_rd_data_ns_reg[113]_0 [5]),
        .Q(c0_ddr4_app_rd_data[113]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].init_done_r[18]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [18]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[18].init_done_r[18]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].init_done_r_reg[18] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[18].init_done_r[18]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [18]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r[18][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .O(p_0_in__19[0]));
  (* SOFT_HLUTNM = "soft_lutpair3026" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r[18][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [1]),
        .O(p_0_in__19[1]));
  (* SOFT_HLUTNM = "soft_lutpair3026" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r[18][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [2]),
        .O(p_0_in__19[2]));
  (* SOFT_HLUTNM = "soft_lutpair2934" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r[18][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [3]),
        .O(p_0_in__19[3]));
  (* SOFT_HLUTNM = "soft_lutpair2934" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r[18][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [4]),
        .O(p_0_in__19[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r[18][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [18]),
        .I1(match4_121_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_121_return),
        .I4(p_0_in25_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [18]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r[18][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [4]),
        .I5(p_0_in25_in),
        .O(p_0_in__19[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [18]),
        .D(p_0_in__19[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [18]),
        .D(p_0_in__19[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [18]),
        .D(p_0_in__19[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [18]),
        .D(p_0_in__19[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [18]),
        .D(p_0_in__19[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[18].rd_buf_indx_cpy_r_reg[18][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [18]),
        .D(p_0_in__19[5]),
        .Q(p_0_in25_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[126],D[118]}),
        .DIB({D[110],D[102]}),
        .DIC({D[94],D[86]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [19]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [19]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [19]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [19]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [19]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [19]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[19].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[114] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [0]),
        .Q(c0_ddr4_app_rd_data[114]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[115] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [1]),
        .Q(c0_ddr4_app_rd_data[115]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[116] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [2]),
        .Q(c0_ddr4_app_rd_data[116]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[117] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [3]),
        .Q(c0_ddr4_app_rd_data[117]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[118] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [4]),
        .Q(c0_ddr4_app_rd_data[118]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[19].app_rd_data_ns_reg[119]_0 [5]),
        .Q(c0_ddr4_app_rd_data[119]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].init_done_r[19]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [19]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[19].init_done_r[19]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].init_done_r_reg[19] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[19].init_done_r[19]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [19]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r[19][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .O(p_0_in__20[0]));
  (* SOFT_HLUTNM = "soft_lutpair3027" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r[19][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [1]),
        .O(p_0_in__20[1]));
  (* SOFT_HLUTNM = "soft_lutpair3027" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r[19][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [2]),
        .O(p_0_in__20[2]));
  (* SOFT_HLUTNM = "soft_lutpair2935" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r[19][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [3]),
        .O(p_0_in__20[3]));
  (* SOFT_HLUTNM = "soft_lutpair2935" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r[19][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [4]),
        .O(p_0_in__20[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r[19][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [19]),
        .I1(match4_122_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_122_return),
        .I4(p_0_in26_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [19]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r[19][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [4]),
        .I5(p_0_in26_in),
        .O(p_0_in__20[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [19]),
        .D(p_0_in__20[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [19]),
        .D(p_0_in__20[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [19]),
        .D(p_0_in__20[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [19]),
        .D(p_0_in__20[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [19]),
        .D(p_0_in__20[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[19].rd_buf_indx_cpy_r_reg[19][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [19]),
        .D(p_0_in__20[5]),
        .Q(p_0_in26_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[25],D[17]}),
        .DIB({D[9],D[1]}),
        .DIC({D[56],D[48]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [1]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[10] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [4]),
        .Q(c0_ddr4_app_rd_data[10]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [5]),
        .Q(c0_ddr4_app_rd_data[11]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[6] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [0]),
        .Q(c0_ddr4_app_rd_data[6]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[7] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [1]),
        .Q(c0_ddr4_app_rd_data[7]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[8] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [2]),
        .Q(c0_ddr4_app_rd_data[8]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[9] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[1].app_rd_data_ns_reg[11]_0 [3]),
        .Q(c0_ddr4_app_rd_data[9]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].init_done_r[1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[1].init_done_r[1]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].init_done_r_reg[1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[1].init_done_r[1]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r[1][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .O(p_0_in__2[0]));
  (* SOFT_HLUTNM = "soft_lutpair3009" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r[1][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [1]),
        .O(p_0_in__2[1]));
  (* SOFT_HLUTNM = "soft_lutpair3009" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r[1][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [2]),
        .O(p_0_in__2[2]));
  (* SOFT_HLUTNM = "soft_lutpair2917" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r[1][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [3]),
        .O(p_0_in__2[3]));
  (* SOFT_HLUTNM = "soft_lutpair2917" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r[1][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [4]),
        .O(p_0_in__2[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r[1][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [1]),
        .I1(match4_14_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_14_return),
        .I4(p_0_in3_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [1]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r[1][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [4]),
        .I5(p_0_in3_in),
        .O(p_0_in__2[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [1]),
        .D(p_0_in__2[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [1]),
        .D(p_0_in__2[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [1]),
        .D(p_0_in__2[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [1]),
        .D(p_0_in__2[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [1]),
        .D(p_0_in__2[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[1].rd_buf_indx_cpy_r_reg[1][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [1]),
        .D(p_0_in__2[5]),
        .Q(p_0_in3_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[111],D[103]}),
        .DIB({D[95],D[87]}),
        .DIC({D[79],D[71]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [20]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [20]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [20]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [20]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [20]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [20]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[20].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[120] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [0]),
        .Q(c0_ddr4_app_rd_data[120]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[121] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [1]),
        .Q(c0_ddr4_app_rd_data[121]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[122] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [2]),
        .Q(c0_ddr4_app_rd_data[122]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[123] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [3]),
        .Q(c0_ddr4_app_rd_data[123]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[124] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [4]),
        .Q(c0_ddr4_app_rd_data[124]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[20].app_rd_data_ns_reg[125]_0 [5]),
        .Q(c0_ddr4_app_rd_data[125]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].init_done_r[20]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [20]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[20].init_done_r[20]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].init_done_r_reg[20] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[20].init_done_r[20]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [20]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r[20][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .O(p_0_in__21[0]));
  (* SOFT_HLUTNM = "soft_lutpair3028" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r[20][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [1]),
        .O(p_0_in__21[1]));
  (* SOFT_HLUTNM = "soft_lutpair3028" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r[20][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [2]),
        .O(p_0_in__21[2]));
  (* SOFT_HLUTNM = "soft_lutpair2936" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r[20][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [3]),
        .O(p_0_in__21[3]));
  (* SOFT_HLUTNM = "soft_lutpair2936" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r[20][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [4]),
        .O(p_0_in__21[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r[20][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [20]),
        .I1(match4_123_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_123_return),
        .I4(p_0_in27_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [20]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r[20][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [4]),
        .I5(p_0_in27_in),
        .O(p_0_in__21[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [20]),
        .D(p_0_in__21[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [20]),
        .D(p_0_in__21[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [20]),
        .D(p_0_in__21[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [20]),
        .D(p_0_in__21[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [20]),
        .D(p_0_in__21[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[20].rd_buf_indx_cpy_r_reg[20][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [20]),
        .D(p_0_in__21[5]),
        .Q(p_0_in27_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[152],D[144]}),
        .DIB({D[136],D[128]}),
        .DIC({D[127],D[119]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [21]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [21]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [21]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [21]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [21]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [21]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[21].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[126] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [0]),
        .Q(c0_ddr4_app_rd_data[126]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[127] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [1]),
        .Q(c0_ddr4_app_rd_data[127]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[128] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [2]),
        .Q(c0_ddr4_app_rd_data[128]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[129] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [3]),
        .Q(c0_ddr4_app_rd_data[129]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[130] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [4]),
        .Q(c0_ddr4_app_rd_data[130]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[21].app_rd_data_ns_reg[131]_0 [5]),
        .Q(c0_ddr4_app_rd_data[131]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].init_done_r[21]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [21]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[21].init_done_r[21]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].init_done_r_reg[21] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[21].init_done_r[21]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [21]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r[21][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .O(p_0_in__22[0]));
  (* SOFT_HLUTNM = "soft_lutpair3029" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r[21][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [1]),
        .O(p_0_in__22[1]));
  (* SOFT_HLUTNM = "soft_lutpair3029" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r[21][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [2]),
        .O(p_0_in__22[2]));
  (* SOFT_HLUTNM = "soft_lutpair2937" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r[21][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [3]),
        .O(p_0_in__22[3]));
  (* SOFT_HLUTNM = "soft_lutpair2937" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r[21][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [4]),
        .O(p_0_in__22[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r[21][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [21]),
        .I1(match4_124_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_124_return),
        .I4(p_0_in28_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [21]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r[21][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [4]),
        .I5(p_0_in28_in),
        .O(p_0_in__22[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [21]),
        .D(p_0_in__22[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [21]),
        .D(p_0_in__22[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [21]),
        .D(p_0_in__22[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [21]),
        .D(p_0_in__22[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [21]),
        .D(p_0_in__22[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[21].rd_buf_indx_cpy_r_reg[21][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [21]),
        .D(p_0_in__22[5]),
        .Q(p_0_in28_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[137],D[129]}),
        .DIB({D[184],D[176]}),
        .DIC({D[168],D[160]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [22]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [22]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [22]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [22]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [22]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [22]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[22].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[132] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [0]),
        .Q(c0_ddr4_app_rd_data[132]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[133] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [1]),
        .Q(c0_ddr4_app_rd_data[133]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[134] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [2]),
        .Q(c0_ddr4_app_rd_data[134]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[135] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [3]),
        .Q(c0_ddr4_app_rd_data[135]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[136] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [4]),
        .Q(c0_ddr4_app_rd_data[136]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[22].app_rd_data_ns_reg[137]_0 [5]),
        .Q(c0_ddr4_app_rd_data[137]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].init_done_r[22]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [22]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[22].init_done_r[22]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].init_done_r_reg[22] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[22].init_done_r[22]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [22]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r[22][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .O(p_0_in__23[0]));
  (* SOFT_HLUTNM = "soft_lutpair3030" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r[22][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [1]),
        .O(p_0_in__23[1]));
  (* SOFT_HLUTNM = "soft_lutpair3030" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r[22][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [2]),
        .O(p_0_in__23[2]));
  (* SOFT_HLUTNM = "soft_lutpair2938" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r[22][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [3]),
        .O(p_0_in__23[3]));
  (* SOFT_HLUTNM = "soft_lutpair2938" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r[22][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [4]),
        .O(p_0_in__23[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r[22][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [22]),
        .I1(match4_125_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_125_return),
        .I4(p_0_in29_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [22]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r[22][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [4]),
        .I5(p_0_in29_in),
        .O(p_0_in__23[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [22]),
        .D(p_0_in__23[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [22]),
        .D(p_0_in__23[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [22]),
        .D(p_0_in__23[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [22]),
        .D(p_0_in__23[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [22]),
        .D(p_0_in__23[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[22].rd_buf_indx_cpy_r_reg[22][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [22]),
        .D(p_0_in__23[5]),
        .Q(p_0_in29_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[185],D[177]}),
        .DIB({D[169],D[161]}),
        .DIC({D[153],D[145]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [23]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [23]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [23]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [23]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [23]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [23]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[23].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[138] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [0]),
        .Q(c0_ddr4_app_rd_data[138]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[139] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [1]),
        .Q(c0_ddr4_app_rd_data[139]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[140] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [2]),
        .Q(c0_ddr4_app_rd_data[140]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[141] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [3]),
        .Q(c0_ddr4_app_rd_data[141]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[142] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [4]),
        .Q(c0_ddr4_app_rd_data[142]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[23].app_rd_data_ns_reg[143]_0 [5]),
        .Q(c0_ddr4_app_rd_data[143]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].init_done_r[23]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [23]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[23].init_done_r[23]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].init_done_r_reg[23] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[23].init_done_r[23]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [23]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r[23][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .O(p_0_in__24[0]));
  (* SOFT_HLUTNM = "soft_lutpair3031" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r[23][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [1]),
        .O(p_0_in__24[1]));
  (* SOFT_HLUTNM = "soft_lutpair3031" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r[23][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [2]),
        .O(p_0_in__24[2]));
  (* SOFT_HLUTNM = "soft_lutpair2939" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r[23][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [3]),
        .O(p_0_in__24[3]));
  (* SOFT_HLUTNM = "soft_lutpair2939" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r[23][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [4]),
        .O(p_0_in__24[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r[23][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [23]),
        .I1(match4_126_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_126_return),
        .I4(p_0_in30_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [23]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r[23][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [4]),
        .I5(p_0_in30_in),
        .O(p_0_in__24[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [23]),
        .D(p_0_in__24[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [23]),
        .D(p_0_in__24[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [23]),
        .D(p_0_in__24[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [23]),
        .D(p_0_in__24[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [23]),
        .D(p_0_in__24[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[23].rd_buf_indx_cpy_r_reg[23][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [23]),
        .D(p_0_in__24[5]),
        .Q(p_0_in30_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[170],D[162]}),
        .DIB({D[154],D[146]}),
        .DIC({D[138],D[130]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [24]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [24]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [24]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [24]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [24]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [24]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[24].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[144] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [0]),
        .Q(c0_ddr4_app_rd_data[144]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[145] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [1]),
        .Q(c0_ddr4_app_rd_data[145]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[146] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [2]),
        .Q(c0_ddr4_app_rd_data[146]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[147] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [3]),
        .Q(c0_ddr4_app_rd_data[147]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[148] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [4]),
        .Q(c0_ddr4_app_rd_data[148]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[24].app_rd_data_ns_reg[149]_0 [5]),
        .Q(c0_ddr4_app_rd_data[149]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].init_done_r[24]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [24]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[24].init_done_r[24]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].init_done_r_reg[24] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[24].init_done_r[24]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [24]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r[24][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .O(p_0_in__25[0]));
  (* SOFT_HLUTNM = "soft_lutpair3032" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r[24][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [1]),
        .O(p_0_in__25[1]));
  (* SOFT_HLUTNM = "soft_lutpair3032" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r[24][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [2]),
        .O(p_0_in__25[2]));
  (* SOFT_HLUTNM = "soft_lutpair2940" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r[24][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [3]),
        .O(p_0_in__25[3]));
  (* SOFT_HLUTNM = "soft_lutpair2940" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r[24][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [4]),
        .O(p_0_in__25[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r[24][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [24]),
        .I1(match4_127_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_127_return),
        .I4(p_0_in31_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [24]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r[24][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [4]),
        .I5(p_0_in31_in),
        .O(p_0_in__25[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [24]),
        .D(p_0_in__25[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [24]),
        .D(p_0_in__25[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [24]),
        .D(p_0_in__25[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [24]),
        .D(p_0_in__25[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [24]),
        .D(p_0_in__25[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[24].rd_buf_indx_cpy_r_reg[24][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [24]),
        .D(p_0_in__25[5]),
        .Q(p_0_in31_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[155],D[147]}),
        .DIB({D[139],D[131]}),
        .DIC({D[186],D[178]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [25]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [25]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [25]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [25]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [25]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [25]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[25].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[150] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [0]),
        .Q(c0_ddr4_app_rd_data[150]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[151] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [1]),
        .Q(c0_ddr4_app_rd_data[151]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[152] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [2]),
        .Q(c0_ddr4_app_rd_data[152]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[153] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [3]),
        .Q(c0_ddr4_app_rd_data[153]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[154] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [4]),
        .Q(c0_ddr4_app_rd_data[154]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[25].app_rd_data_ns_reg[155]_0 [5]),
        .Q(c0_ddr4_app_rd_data[155]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].init_done_r[25]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [25]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[25].init_done_r[25]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].init_done_r_reg[25] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[25].init_done_r[25]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [25]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r[25][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .O(p_0_in__26[0]));
  (* SOFT_HLUTNM = "soft_lutpair3033" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r[25][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [1]),
        .O(p_0_in__26[1]));
  (* SOFT_HLUTNM = "soft_lutpair3033" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r[25][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [2]),
        .O(p_0_in__26[2]));
  (* SOFT_HLUTNM = "soft_lutpair2941" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r[25][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [3]),
        .O(p_0_in__26[3]));
  (* SOFT_HLUTNM = "soft_lutpair2941" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r[25][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [4]),
        .O(p_0_in__26[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r[25][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [25]),
        .I1(match4_128_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_128_return),
        .I4(p_0_in32_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [25]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r[25][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [4]),
        .I5(p_0_in32_in),
        .O(p_0_in__26[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [25]),
        .D(p_0_in__26[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [25]),
        .D(p_0_in__26[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [25]),
        .D(p_0_in__26[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [25]),
        .D(p_0_in__26[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [25]),
        .D(p_0_in__26[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[25].rd_buf_indx_cpy_r_reg[25][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [25]),
        .D(p_0_in__26[5]),
        .Q(p_0_in32_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[140],D[132]}),
        .DIB({D[187],D[179]}),
        .DIC({D[171],D[163]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [26]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [26]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [26]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [26]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [26]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [26]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[26].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[156] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [0]),
        .Q(c0_ddr4_app_rd_data[156]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[157] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [1]),
        .Q(c0_ddr4_app_rd_data[157]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[158] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [2]),
        .Q(c0_ddr4_app_rd_data[158]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[159] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [3]),
        .Q(c0_ddr4_app_rd_data[159]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[160] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [4]),
        .Q(c0_ddr4_app_rd_data[160]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[26].app_rd_data_ns_reg[161]_0 [5]),
        .Q(c0_ddr4_app_rd_data[161]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].init_done_r[26]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [26]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[26].init_done_r[26]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].init_done_r_reg[26] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[26].init_done_r[26]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [26]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r[26][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .O(p_0_in__27[0]));
  (* SOFT_HLUTNM = "soft_lutpair3034" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r[26][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [1]),
        .O(p_0_in__27[1]));
  (* SOFT_HLUTNM = "soft_lutpair3034" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r[26][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [2]),
        .O(p_0_in__27[2]));
  (* SOFT_HLUTNM = "soft_lutpair2942" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r[26][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [3]),
        .O(p_0_in__27[3]));
  (* SOFT_HLUTNM = "soft_lutpair2942" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r[26][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [4]),
        .O(p_0_in__27[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r[26][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [26]),
        .I1(match4_129_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_129_return),
        .I4(p_0_in33_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [26]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r[26][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [4]),
        .I5(p_0_in33_in),
        .O(p_0_in__27[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [26]),
        .D(p_0_in__27[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [26]),
        .D(p_0_in__27[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [26]),
        .D(p_0_in__27[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [26]),
        .D(p_0_in__27[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [26]),
        .D(p_0_in__27[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[26].rd_buf_indx_cpy_r_reg[26][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [26]),
        .D(p_0_in__27[5]),
        .Q(p_0_in33_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[188],D[180]}),
        .DIB({D[172],D[164]}),
        .DIC({D[156],D[148]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [27]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [27]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [27]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [27]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [27]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [27]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[27].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[162] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [0]),
        .Q(c0_ddr4_app_rd_data[162]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[163] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [1]),
        .Q(c0_ddr4_app_rd_data[163]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[164] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [2]),
        .Q(c0_ddr4_app_rd_data[164]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[165] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [3]),
        .Q(c0_ddr4_app_rd_data[165]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[166] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [4]),
        .Q(c0_ddr4_app_rd_data[166]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[27].app_rd_data_ns_reg[167]_0 [5]),
        .Q(c0_ddr4_app_rd_data[167]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].init_done_r[27]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [27]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[27].init_done_r[27]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].init_done_r_reg[27] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[27].init_done_r[27]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [27]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r[27][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .O(p_0_in__28[0]));
  (* SOFT_HLUTNM = "soft_lutpair3035" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r[27][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [1]),
        .O(p_0_in__28[1]));
  (* SOFT_HLUTNM = "soft_lutpair3035" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r[27][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [2]),
        .O(p_0_in__28[2]));
  (* SOFT_HLUTNM = "soft_lutpair2943" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r[27][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [3]),
        .O(p_0_in__28[3]));
  (* SOFT_HLUTNM = "soft_lutpair2943" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r[27][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [4]),
        .O(p_0_in__28[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r[27][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [27]),
        .I1(match4_130_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_130_return),
        .I4(p_0_in34_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [27]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r[27][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [4]),
        .I5(p_0_in34_in),
        .O(p_0_in__28[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [27]),
        .D(p_0_in__28[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [27]),
        .D(p_0_in__28[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [27]),
        .D(p_0_in__28[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [27]),
        .D(p_0_in__28[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [27]),
        .D(p_0_in__28[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[27].rd_buf_indx_cpy_r_reg[27][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [27]),
        .D(p_0_in__28[5]),
        .Q(p_0_in34_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[173],D[165]}),
        .DIB({D[157],D[149]}),
        .DIC({D[141],D[133]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [28]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [28]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [28]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [28]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [28]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [28]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[28].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[168] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [0]),
        .Q(c0_ddr4_app_rd_data[168]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[169] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [1]),
        .Q(c0_ddr4_app_rd_data[169]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[170] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [2]),
        .Q(c0_ddr4_app_rd_data[170]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[171] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [3]),
        .Q(c0_ddr4_app_rd_data[171]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[172] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [4]),
        .Q(c0_ddr4_app_rd_data[172]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[28].app_rd_data_ns_reg[173]_0 [5]),
        .Q(c0_ddr4_app_rd_data[173]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].init_done_r[28]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [28]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[28].init_done_r[28]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].init_done_r_reg[28] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[28].init_done_r[28]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [28]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r[28][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .O(p_0_in__29[0]));
  (* SOFT_HLUTNM = "soft_lutpair3036" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r[28][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [1]),
        .O(p_0_in__29[1]));
  (* SOFT_HLUTNM = "soft_lutpair3036" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r[28][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [2]),
        .O(p_0_in__29[2]));
  (* SOFT_HLUTNM = "soft_lutpair2944" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r[28][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [3]),
        .O(p_0_in__29[3]));
  (* SOFT_HLUTNM = "soft_lutpair2944" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r[28][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [4]),
        .O(p_0_in__29[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r[28][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [28]),
        .I1(match4_131_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_131_return),
        .I4(p_0_in35_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [28]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r[28][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [4]),
        .I5(p_0_in35_in),
        .O(p_0_in__29[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [28]),
        .D(p_0_in__29[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [28]),
        .D(p_0_in__29[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [28]),
        .D(p_0_in__29[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [28]),
        .D(p_0_in__29[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [28]),
        .D(p_0_in__29[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[28].rd_buf_indx_cpy_r_reg[28][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [28]),
        .D(p_0_in__29[5]),
        .Q(p_0_in35_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[158],D[150]}),
        .DIB({D[142],D[134]}),
        .DIC({D[189],D[181]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [29]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [29]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [29]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [29]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [29]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [29]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[29].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[174] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [0]),
        .Q(c0_ddr4_app_rd_data[174]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[175] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [1]),
        .Q(c0_ddr4_app_rd_data[175]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[176] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [2]),
        .Q(c0_ddr4_app_rd_data[176]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[177] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [3]),
        .Q(c0_ddr4_app_rd_data[177]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[178] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [4]),
        .Q(c0_ddr4_app_rd_data[178]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[29].app_rd_data_ns_reg[179]_0 [5]),
        .Q(c0_ddr4_app_rd_data[179]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].init_done_r[29]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [29]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[29].init_done_r[29]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].init_done_r_reg[29] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[29].init_done_r[29]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [29]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r[29][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .O(p_0_in__30[0]));
  (* SOFT_HLUTNM = "soft_lutpair3037" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r[29][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [1]),
        .O(p_0_in__30[1]));
  (* SOFT_HLUTNM = "soft_lutpair3037" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r[29][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [2]),
        .O(p_0_in__30[2]));
  (* SOFT_HLUTNM = "soft_lutpair2945" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r[29][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [3]),
        .O(p_0_in__30[3]));
  (* SOFT_HLUTNM = "soft_lutpair2945" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r[29][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [4]),
        .O(p_0_in__30[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r[29][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [29]),
        .I1(match4_132_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_132_return),
        .I4(p_0_in36_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [29]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r[29][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [4]),
        .I5(p_0_in36_in),
        .O(p_0_in__30[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [29]),
        .D(p_0_in__30[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [29]),
        .D(p_0_in__30[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [29]),
        .D(p_0_in__30[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [29]),
        .D(p_0_in__30[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [29]),
        .D(p_0_in__30[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[29].rd_buf_indx_cpy_r_reg[29][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [29]),
        .D(p_0_in__30[5]),
        .Q(p_0_in36_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[10],D[2]}),
        .DIB({D[57],D[49]}),
        .DIC({D[41],D[33]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [2]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [2]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [2]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[2].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[12] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [0]),
        .Q(c0_ddr4_app_rd_data[12]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[13] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [1]),
        .Q(c0_ddr4_app_rd_data[13]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[14] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [2]),
        .Q(c0_ddr4_app_rd_data[14]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[15] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [3]),
        .Q(c0_ddr4_app_rd_data[15]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[16] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [4]),
        .Q(c0_ddr4_app_rd_data[16]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[2].app_rd_data_ns_reg[17]_0 [5]),
        .Q(c0_ddr4_app_rd_data[17]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].init_done_r[2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[2].init_done_r[2]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].init_done_r_reg[2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[2].init_done_r[2]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r[2][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .O(p_0_in__3[0]));
  (* SOFT_HLUTNM = "soft_lutpair3010" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r[2][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [1]),
        .O(p_0_in__3[1]));
  (* SOFT_HLUTNM = "soft_lutpair3010" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r[2][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [2]),
        .O(p_0_in__3[2]));
  (* SOFT_HLUTNM = "soft_lutpair2918" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r[2][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [3]),
        .O(p_0_in__3[3]));
  (* SOFT_HLUTNM = "soft_lutpair2918" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r[2][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [4]),
        .O(p_0_in__3[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r[2][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [2]),
        .I1(match4_15_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_15_return),
        .I4(p_0_in5_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [2]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r[2][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [4]),
        .I5(p_0_in5_in),
        .O(p_0_in__3[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [2]),
        .D(p_0_in__3[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [2]),
        .D(p_0_in__3[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [2]),
        .D(p_0_in__3[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [2]),
        .D(p_0_in__3[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [2]),
        .D(p_0_in__3[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[2].rd_buf_indx_cpy_r_reg[2][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [2]),
        .D(p_0_in__3[5]),
        .Q(p_0_in5_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[143],D[135]}),
        .DIB({D[190],D[182]}),
        .DIC({D[174],D[166]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [30]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [30]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [30]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [30]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [30]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [30]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[30].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[180] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [0]),
        .Q(c0_ddr4_app_rd_data[180]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[181] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [1]),
        .Q(c0_ddr4_app_rd_data[181]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[182] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [2]),
        .Q(c0_ddr4_app_rd_data[182]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[183] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [3]),
        .Q(c0_ddr4_app_rd_data[183]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[184] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [4]),
        .Q(c0_ddr4_app_rd_data[184]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[30].app_rd_data_ns_reg[185]_0 [5]),
        .Q(c0_ddr4_app_rd_data[185]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].init_done_r[30]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [30]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[30].init_done_r[30]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].init_done_r_reg[30] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[30].init_done_r[30]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [30]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r[30][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .O(p_0_in__31[0]));
  (* SOFT_HLUTNM = "soft_lutpair3038" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r[30][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [1]),
        .O(p_0_in__31[1]));
  (* SOFT_HLUTNM = "soft_lutpair3038" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r[30][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [2]),
        .O(p_0_in__31[2]));
  (* SOFT_HLUTNM = "soft_lutpair2946" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r[30][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [3]),
        .O(p_0_in__31[3]));
  (* SOFT_HLUTNM = "soft_lutpair2946" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r[30][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [4]),
        .O(p_0_in__31[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r[30][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [30]),
        .I1(match4_133_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_133_return),
        .I4(p_0_in37_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [30]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r[30][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [4]),
        .I5(p_0_in37_in),
        .O(p_0_in__31[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [30]),
        .D(p_0_in__31[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [30]),
        .D(p_0_in__31[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [30]),
        .D(p_0_in__31[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [30]),
        .D(p_0_in__31[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [30]),
        .D(p_0_in__31[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[30].rd_buf_indx_cpy_r_reg[30][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [30]),
        .D(p_0_in__31[5]),
        .Q(p_0_in37_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[191],D[183]}),
        .DIB({D[175],D[167]}),
        .DIC({D[159],D[151]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [31]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [31]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [31]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [31]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [31]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [31]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[31].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[186] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [0]),
        .Q(c0_ddr4_app_rd_data[186]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[187] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [1]),
        .Q(c0_ddr4_app_rd_data[187]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[188] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [2]),
        .Q(c0_ddr4_app_rd_data[188]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[189] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [3]),
        .Q(c0_ddr4_app_rd_data[189]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[190] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [4]),
        .Q(c0_ddr4_app_rd_data[190]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[31].app_rd_data_ns_reg[191]_0 [5]),
        .Q(c0_ddr4_app_rd_data[191]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].init_done_r[31]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [31]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[31].init_done_r[31]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].init_done_r_reg[31] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[31].init_done_r[31]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [31]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r[31][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .O(p_0_in__32[0]));
  (* SOFT_HLUTNM = "soft_lutpair3039" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r[31][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [1]),
        .O(p_0_in__32[1]));
  (* SOFT_HLUTNM = "soft_lutpair3039" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r[31][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [2]),
        .O(p_0_in__32[2]));
  (* SOFT_HLUTNM = "soft_lutpair2947" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r[31][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [3]),
        .O(p_0_in__32[3]));
  (* SOFT_HLUTNM = "soft_lutpair2947" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r[31][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [4]),
        .O(p_0_in__32[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r[31][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [31]),
        .I1(match4_134_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_134_return),
        .I4(p_0_in38_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [31]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r[31][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [4]),
        .I5(p_0_in38_in),
        .O(p_0_in__32[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [31]),
        .D(p_0_in__32[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [31]),
        .D(p_0_in__32[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [31]),
        .D(p_0_in__32[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [31]),
        .D(p_0_in__32[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [31]),
        .D(p_0_in__32[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[31].rd_buf_indx_cpy_r_reg[31][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [31]),
        .D(p_0_in__32[5]),
        .Q(p_0_in38_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[232],D[224]}),
        .DIB({D[216],D[208]}),
        .DIC({D[200],D[192]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [32]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [32]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [32]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [32]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [32]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [32]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[32].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[192] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [0]),
        .Q(c0_ddr4_app_rd_data[192]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[193] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [1]),
        .Q(c0_ddr4_app_rd_data[193]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[194] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [2]),
        .Q(c0_ddr4_app_rd_data[194]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[195] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [3]),
        .Q(c0_ddr4_app_rd_data[195]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[196] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [4]),
        .Q(c0_ddr4_app_rd_data[196]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[32].app_rd_data_ns_reg[197]_0 [5]),
        .Q(c0_ddr4_app_rd_data[197]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].init_done_r[32]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [32]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[32].init_done_r[32]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].init_done_r_reg[32] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[32].init_done_r[32]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [32]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r[32][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .O(p_0_in__33[0]));
  (* SOFT_HLUTNM = "soft_lutpair3040" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r[32][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [1]),
        .O(p_0_in__33[1]));
  (* SOFT_HLUTNM = "soft_lutpair3040" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r[32][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [2]),
        .O(p_0_in__33[2]));
  (* SOFT_HLUTNM = "soft_lutpair2948" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r[32][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [3]),
        .O(p_0_in__33[3]));
  (* SOFT_HLUTNM = "soft_lutpair2948" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r[32][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [4]),
        .O(p_0_in__33[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r[32][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [32]),
        .I1(match4_135_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_135_return),
        .I4(p_0_in39_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [32]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r[32][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [4]),
        .I5(p_0_in39_in),
        .O(p_0_in__33[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [32]),
        .D(p_0_in__33[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [32]),
        .D(p_0_in__33[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [32]),
        .D(p_0_in__33[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [32]),
        .D(p_0_in__33[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [32]),
        .D(p_0_in__33[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[32].rd_buf_indx_cpy_r_reg[32][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [32]),
        .D(p_0_in__33[5]),
        .Q(p_0_in39_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[217],D[209]}),
        .DIB({D[201],D[193]}),
        .DIC({D[248],D[240]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [33]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [33]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [33]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [33]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [33]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [33]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[33].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[198] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [0]),
        .Q(c0_ddr4_app_rd_data[198]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[199] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [1]),
        .Q(c0_ddr4_app_rd_data[199]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[200] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [2]),
        .Q(c0_ddr4_app_rd_data[200]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[201] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [3]),
        .Q(c0_ddr4_app_rd_data[201]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[202] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [4]),
        .Q(c0_ddr4_app_rd_data[202]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[33].app_rd_data_ns_reg[203]_0 [5]),
        .Q(c0_ddr4_app_rd_data[203]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].init_done_r[33]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [33]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[33].init_done_r[33]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].init_done_r_reg[33] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[33].init_done_r[33]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [33]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r[33][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .O(p_0_in__34[0]));
  (* SOFT_HLUTNM = "soft_lutpair3041" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r[33][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [1]),
        .O(p_0_in__34[1]));
  (* SOFT_HLUTNM = "soft_lutpair3041" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r[33][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [2]),
        .O(p_0_in__34[2]));
  (* SOFT_HLUTNM = "soft_lutpair2949" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r[33][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [3]),
        .O(p_0_in__34[3]));
  (* SOFT_HLUTNM = "soft_lutpair2949" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r[33][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [4]),
        .O(p_0_in__34[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r[33][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [33]),
        .I1(match4_136_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_136_return),
        .I4(p_0_in40_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [33]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r[33][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [4]),
        .I5(p_0_in40_in),
        .O(p_0_in__34[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [33]),
        .D(p_0_in__34[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [33]),
        .D(p_0_in__34[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [33]),
        .D(p_0_in__34[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [33]),
        .D(p_0_in__34[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [33]),
        .D(p_0_in__34[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[33].rd_buf_indx_cpy_r_reg[33][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [33]),
        .D(p_0_in__34[5]),
        .Q(p_0_in40_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[202],D[194]}),
        .DIB({D[249],D[241]}),
        .DIC({D[233],D[225]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [34]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [34]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [34]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [34]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [34]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [34]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[34].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[204] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [0]),
        .Q(c0_ddr4_app_rd_data[204]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[205] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [1]),
        .Q(c0_ddr4_app_rd_data[205]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[206] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [2]),
        .Q(c0_ddr4_app_rd_data[206]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[207] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [3]),
        .Q(c0_ddr4_app_rd_data[207]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[208] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [4]),
        .Q(c0_ddr4_app_rd_data[208]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[34].app_rd_data_ns_reg[209]_0 [5]),
        .Q(c0_ddr4_app_rd_data[209]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].init_done_r[34]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [34]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[34].init_done_r[34]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].init_done_r_reg[34] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[34].init_done_r[34]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [34]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r[34][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .O(p_0_in__35[0]));
  (* SOFT_HLUTNM = "soft_lutpair3042" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r[34][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [1]),
        .O(p_0_in__35[1]));
  (* SOFT_HLUTNM = "soft_lutpair3042" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r[34][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [2]),
        .O(p_0_in__35[2]));
  (* SOFT_HLUTNM = "soft_lutpair2950" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r[34][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [3]),
        .O(p_0_in__35[3]));
  (* SOFT_HLUTNM = "soft_lutpair2950" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r[34][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [4]),
        .O(p_0_in__35[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r[34][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [34]),
        .I1(match4_137_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_137_return),
        .I4(p_0_in41_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [34]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r[34][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [4]),
        .I5(p_0_in41_in),
        .O(p_0_in__35[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [34]),
        .D(p_0_in__35[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [34]),
        .D(p_0_in__35[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [34]),
        .D(p_0_in__35[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [34]),
        .D(p_0_in__35[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [34]),
        .D(p_0_in__35[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[34].rd_buf_indx_cpy_r_reg[34][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [34]),
        .D(p_0_in__35[5]),
        .Q(p_0_in41_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[250],D[242]}),
        .DIB({D[234],D[226]}),
        .DIC({D[218],D[210]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [35]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [35]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [35]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [35]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [35]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [35]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[35].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[210] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [0]),
        .Q(c0_ddr4_app_rd_data[210]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[211] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [1]),
        .Q(c0_ddr4_app_rd_data[211]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[212] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [2]),
        .Q(c0_ddr4_app_rd_data[212]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[213] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [3]),
        .Q(c0_ddr4_app_rd_data[213]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[214] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [4]),
        .Q(c0_ddr4_app_rd_data[214]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[35].app_rd_data_ns_reg[215]_0 [5]),
        .Q(c0_ddr4_app_rd_data[215]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].init_done_r[35]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [35]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[35].init_done_r[35]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].init_done_r_reg[35] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[35].init_done_r[35]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [35]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r[35][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .O(p_0_in__36[0]));
  (* SOFT_HLUTNM = "soft_lutpair3043" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r[35][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [1]),
        .O(p_0_in__36[1]));
  (* SOFT_HLUTNM = "soft_lutpair3043" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r[35][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [2]),
        .O(p_0_in__36[2]));
  (* SOFT_HLUTNM = "soft_lutpair2951" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r[35][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [3]),
        .O(p_0_in__36[3]));
  (* SOFT_HLUTNM = "soft_lutpair2951" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r[35][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [4]),
        .O(p_0_in__36[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r[35][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [35]),
        .I1(match4_138_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_138_return),
        .I4(p_0_in42_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [35]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r[35][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [4]),
        .I5(p_0_in42_in),
        .O(p_0_in__36[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [35]),
        .D(p_0_in__36[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [35]),
        .D(p_0_in__36[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [35]),
        .D(p_0_in__36[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [35]),
        .D(p_0_in__36[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [35]),
        .D(p_0_in__36[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[35].rd_buf_indx_cpy_r_reg[35][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [35]),
        .D(p_0_in__36[5]),
        .Q(p_0_in42_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[235],D[227]}),
        .DIB({D[219],D[211]}),
        .DIC({D[203],D[195]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [36]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [36]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [36]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [36]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [36]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [36]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[36].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[216] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [0]),
        .Q(c0_ddr4_app_rd_data[216]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[217] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [1]),
        .Q(c0_ddr4_app_rd_data[217]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[218] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [2]),
        .Q(c0_ddr4_app_rd_data[218]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[219] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [3]),
        .Q(c0_ddr4_app_rd_data[219]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[220] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [4]),
        .Q(c0_ddr4_app_rd_data[220]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[36].app_rd_data_ns_reg[221]_0 [5]),
        .Q(c0_ddr4_app_rd_data[221]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].init_done_r[36]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [36]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[36].init_done_r[36]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].init_done_r_reg[36] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[36].init_done_r[36]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [36]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r[36][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .O(p_0_in__37[0]));
  (* SOFT_HLUTNM = "soft_lutpair3044" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r[36][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [1]),
        .O(p_0_in__37[1]));
  (* SOFT_HLUTNM = "soft_lutpair3044" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r[36][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [2]),
        .O(p_0_in__37[2]));
  (* SOFT_HLUTNM = "soft_lutpair2952" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r[36][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [3]),
        .O(p_0_in__37[3]));
  (* SOFT_HLUTNM = "soft_lutpair2952" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r[36][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [4]),
        .O(p_0_in__37[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r[36][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [36]),
        .I1(match4_139_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_139_return),
        .I4(p_0_in43_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [36]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r[36][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [4]),
        .I5(p_0_in43_in),
        .O(p_0_in__37[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [36]),
        .D(p_0_in__37[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [36]),
        .D(p_0_in__37[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [36]),
        .D(p_0_in__37[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [36]),
        .D(p_0_in__37[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [36]),
        .D(p_0_in__37[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[36].rd_buf_indx_cpy_r_reg[36][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [36]),
        .D(p_0_in__37[5]),
        .Q(p_0_in43_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[220],D[212]}),
        .DIB({D[204],D[196]}),
        .DIC({D[251],D[243]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [37]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [37]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [37]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [37]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [37]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [37]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[37].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[222] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [0]),
        .Q(c0_ddr4_app_rd_data[222]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[223] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [1]),
        .Q(c0_ddr4_app_rd_data[223]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[224] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [2]),
        .Q(c0_ddr4_app_rd_data[224]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[225] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [3]),
        .Q(c0_ddr4_app_rd_data[225]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[226] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [4]),
        .Q(c0_ddr4_app_rd_data[226]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[37].app_rd_data_ns_reg[227]_0 [5]),
        .Q(c0_ddr4_app_rd_data[227]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].init_done_r[37]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [37]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[37].init_done_r[37]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].init_done_r_reg[37] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[37].init_done_r[37]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [37]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r[37][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .O(p_0_in__38[0]));
  (* SOFT_HLUTNM = "soft_lutpair3045" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r[37][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [1]),
        .O(p_0_in__38[1]));
  (* SOFT_HLUTNM = "soft_lutpair3045" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r[37][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [2]),
        .O(p_0_in__38[2]));
  (* SOFT_HLUTNM = "soft_lutpair2953" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r[37][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [3]),
        .O(p_0_in__38[3]));
  (* SOFT_HLUTNM = "soft_lutpair2953" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r[37][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [4]),
        .O(p_0_in__38[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r[37][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [37]),
        .I1(match4_140_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_140_return),
        .I4(p_0_in44_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [37]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r[37][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [4]),
        .I5(p_0_in44_in),
        .O(p_0_in__38[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [37]),
        .D(p_0_in__38[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [37]),
        .D(p_0_in__38[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [37]),
        .D(p_0_in__38[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [37]),
        .D(p_0_in__38[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [37]),
        .D(p_0_in__38[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[37].rd_buf_indx_cpy_r_reg[37][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [37]),
        .D(p_0_in__38[5]),
        .Q(p_0_in44_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[205],D[197]}),
        .DIB({D[252],D[244]}),
        .DIC({D[236],D[228]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [38]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [38]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [38]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [38]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [38]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [38]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[38].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[228] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [0]),
        .Q(c0_ddr4_app_rd_data[228]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[229] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [1]),
        .Q(c0_ddr4_app_rd_data[229]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[230] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [2]),
        .Q(c0_ddr4_app_rd_data[230]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[231] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [3]),
        .Q(c0_ddr4_app_rd_data[231]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[232] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [4]),
        .Q(c0_ddr4_app_rd_data[232]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[38].app_rd_data_ns_reg[233]_0 [5]),
        .Q(c0_ddr4_app_rd_data[233]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].init_done_r[38]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [38]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[38].init_done_r[38]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].init_done_r_reg[38] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[38].init_done_r[38]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [38]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r[38][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .O(p_0_in__39[0]));
  (* SOFT_HLUTNM = "soft_lutpair3046" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r[38][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [1]),
        .O(p_0_in__39[1]));
  (* SOFT_HLUTNM = "soft_lutpair3046" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r[38][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [2]),
        .O(p_0_in__39[2]));
  (* SOFT_HLUTNM = "soft_lutpair2954" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r[38][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [3]),
        .O(p_0_in__39[3]));
  (* SOFT_HLUTNM = "soft_lutpair2954" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r[38][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [4]),
        .O(p_0_in__39[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r[38][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [38]),
        .I1(match4_141_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_141_return),
        .I4(p_0_in45_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [38]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r[38][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [4]),
        .I5(p_0_in45_in),
        .O(p_0_in__39[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [38]),
        .D(p_0_in__39[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [38]),
        .D(p_0_in__39[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [38]),
        .D(p_0_in__39[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [38]),
        .D(p_0_in__39[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [38]),
        .D(p_0_in__39[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[38].rd_buf_indx_cpy_r_reg[38][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [38]),
        .D(p_0_in__39[5]),
        .Q(p_0_in45_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[253],D[245]}),
        .DIB({D[237],D[229]}),
        .DIC({D[221],D[213]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [39]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [39]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [39]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [39]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [39]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [39]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[39].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[234] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [0]),
        .Q(c0_ddr4_app_rd_data[234]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[235] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [1]),
        .Q(c0_ddr4_app_rd_data[235]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[236] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [2]),
        .Q(c0_ddr4_app_rd_data[236]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[237] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [3]),
        .Q(c0_ddr4_app_rd_data[237]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[238] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [4]),
        .Q(c0_ddr4_app_rd_data[238]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[39].app_rd_data_ns_reg[239]_0 [5]),
        .Q(c0_ddr4_app_rd_data[239]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].init_done_r[39]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [39]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[39].init_done_r[39]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].init_done_r_reg[39] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[39].init_done_r[39]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [39]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r[39][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .O(p_0_in__40[0]));
  (* SOFT_HLUTNM = "soft_lutpair3047" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r[39][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [1]),
        .O(p_0_in__40[1]));
  (* SOFT_HLUTNM = "soft_lutpair3047" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r[39][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [2]),
        .O(p_0_in__40[2]));
  (* SOFT_HLUTNM = "soft_lutpair2955" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r[39][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [3]),
        .O(p_0_in__40[3]));
  (* SOFT_HLUTNM = "soft_lutpair2955" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r[39][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [4]),
        .O(p_0_in__40[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r[39][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [39]),
        .I1(match4_142_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_142_return),
        .I4(p_0_in46_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [39]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r[39][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [4]),
        .I5(p_0_in46_in),
        .O(p_0_in__40[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [39]),
        .D(p_0_in__40[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [39]),
        .D(p_0_in__40[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [39]),
        .D(p_0_in__40[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [39]),
        .D(p_0_in__40[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [39]),
        .D(p_0_in__40[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[39].rd_buf_indx_cpy_r_reg[39][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [39]),
        .D(p_0_in__40[5]),
        .Q(p_0_in46_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[58],D[50]}),
        .DIB({D[42],D[34]}),
        .DIC({D[26],D[18]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [3]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [3]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [3]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [3]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[3].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[18] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [0]),
        .Q(c0_ddr4_app_rd_data[18]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[19] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [1]),
        .Q(c0_ddr4_app_rd_data[19]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[20] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [2]),
        .Q(c0_ddr4_app_rd_data[20]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[21] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [3]),
        .Q(c0_ddr4_app_rd_data[21]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[22] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [4]),
        .Q(c0_ddr4_app_rd_data[22]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[3].app_rd_data_ns_reg[23]_0 [5]),
        .Q(c0_ddr4_app_rd_data[23]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].init_done_r[3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[3].init_done_r[3]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].init_done_r_reg[3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[3].init_done_r[3]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r[3][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .O(p_0_in__4[0]));
  (* SOFT_HLUTNM = "soft_lutpair3011" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r[3][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [1]),
        .O(p_0_in__4[1]));
  (* SOFT_HLUTNM = "soft_lutpair3011" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r[3][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [2]),
        .O(p_0_in__4[2]));
  (* SOFT_HLUTNM = "soft_lutpair2919" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r[3][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [3]),
        .O(p_0_in__4[3]));
  (* SOFT_HLUTNM = "soft_lutpair2919" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r[3][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [4]),
        .O(p_0_in__4[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r[3][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [3]),
        .I1(match4_16_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_16_return),
        .I4(p_0_in7_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [3]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r[3][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [4]),
        .I5(p_0_in7_in),
        .O(p_0_in__4[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [3]),
        .D(p_0_in__4[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [3]),
        .D(p_0_in__4[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [3]),
        .D(p_0_in__4[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [3]),
        .D(p_0_in__4[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [3]),
        .D(p_0_in__4[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[3].rd_buf_indx_cpy_r_reg[3][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [3]),
        .D(p_0_in__4[5]),
        .Q(p_0_in7_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[238],D[230]}),
        .DIB({D[222],D[214]}),
        .DIC({D[206],D[198]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [40]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [40]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [40]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [40]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [40]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [40]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[40].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[240] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [0]),
        .Q(c0_ddr4_app_rd_data[240]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[241] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [1]),
        .Q(c0_ddr4_app_rd_data[241]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[242] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [2]),
        .Q(c0_ddr4_app_rd_data[242]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[243] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [3]),
        .Q(c0_ddr4_app_rd_data[243]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[244] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [4]),
        .Q(c0_ddr4_app_rd_data[244]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[40].app_rd_data_ns_reg[245]_0 [5]),
        .Q(c0_ddr4_app_rd_data[245]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].init_done_r[40]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [40]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[40].init_done_r[40]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].init_done_r_reg[40] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[40].init_done_r[40]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [40]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r[40][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .O(p_0_in__41[0]));
  (* SOFT_HLUTNM = "soft_lutpair3048" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r[40][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [1]),
        .O(p_0_in__41[1]));
  (* SOFT_HLUTNM = "soft_lutpair3048" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r[40][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [2]),
        .O(p_0_in__41[2]));
  (* SOFT_HLUTNM = "soft_lutpair2956" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r[40][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [3]),
        .O(p_0_in__41[3]));
  (* SOFT_HLUTNM = "soft_lutpair2956" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r[40][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [4]),
        .O(p_0_in__41[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r[40][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [40]),
        .I1(match4_143_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_143_return),
        .I4(p_0_in47_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [40]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r[40][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [4]),
        .I5(p_0_in47_in),
        .O(p_0_in__41[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [40]),
        .D(p_0_in__41[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [40]),
        .D(p_0_in__41[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [40]),
        .D(p_0_in__41[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [40]),
        .D(p_0_in__41[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [40]),
        .D(p_0_in__41[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[40].rd_buf_indx_cpy_r_reg[40][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [40]),
        .D(p_0_in__41[5]),
        .Q(p_0_in47_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[223],D[215]}),
        .DIB({D[207],D[199]}),
        .DIC({D[254],D[246]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [41]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [41]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [41]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [41]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [41]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [41]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[41].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[246] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [0]),
        .Q(c0_ddr4_app_rd_data[246]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[247] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [1]),
        .Q(c0_ddr4_app_rd_data[247]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[248] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [2]),
        .Q(c0_ddr4_app_rd_data[248]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[249] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [3]),
        .Q(c0_ddr4_app_rd_data[249]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[250] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [4]),
        .Q(c0_ddr4_app_rd_data[250]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[41].app_rd_data_ns_reg[251]_0 [5]),
        .Q(c0_ddr4_app_rd_data[251]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].init_done_r[41]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [41]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[41].init_done_r[41]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].init_done_r_reg[41] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[41].init_done_r[41]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [41]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r[41][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .O(p_0_in__42[0]));
  (* SOFT_HLUTNM = "soft_lutpair3049" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r[41][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [1]),
        .O(p_0_in__42[1]));
  (* SOFT_HLUTNM = "soft_lutpair3049" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r[41][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [2]),
        .O(p_0_in__42[2]));
  (* SOFT_HLUTNM = "soft_lutpair2957" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r[41][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [3]),
        .O(p_0_in__42[3]));
  (* SOFT_HLUTNM = "soft_lutpair2957" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r[41][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [4]),
        .O(p_0_in__42[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r[41][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [41]),
        .I1(match4_144_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_144_return),
        .I4(p_0_in48_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [41]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r[41][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [4]),
        .I5(p_0_in48_in),
        .O(p_0_in__42[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [41]),
        .D(p_0_in__42[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [41]),
        .D(p_0_in__42[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [41]),
        .D(p_0_in__42[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [41]),
        .D(p_0_in__42[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [41]),
        .D(p_0_in__42[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[41].rd_buf_indx_cpy_r_reg[41][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [41]),
        .D(p_0_in__42[5]),
        .Q(p_0_in48_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[264],D[256]}),
        .DIB({D[255],D[247]}),
        .DIC({D[239],D[231]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [42]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [42]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [42]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [42]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [42]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [42]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[42].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[252] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [0]),
        .Q(c0_ddr4_app_rd_data[252]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[253] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [1]),
        .Q(c0_ddr4_app_rd_data[253]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[254] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [2]),
        .Q(c0_ddr4_app_rd_data[254]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[255] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [3]),
        .Q(c0_ddr4_app_rd_data[255]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[256] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [4]),
        .Q(c0_ddr4_app_rd_data[256]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[42].app_rd_data_ns_reg[257]_0 [5]),
        .Q(c0_ddr4_app_rd_data[257]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].init_done_r[42]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [42]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[42].init_done_r[42]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].init_done_r_reg[42] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[42].init_done_r[42]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [42]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r[42][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .O(p_0_in__43[0]));
  (* SOFT_HLUTNM = "soft_lutpair3050" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r[42][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [1]),
        .O(p_0_in__43[1]));
  (* SOFT_HLUTNM = "soft_lutpair3050" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r[42][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [2]),
        .O(p_0_in__43[2]));
  (* SOFT_HLUTNM = "soft_lutpair2958" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r[42][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [3]),
        .O(p_0_in__43[3]));
  (* SOFT_HLUTNM = "soft_lutpair2958" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r[42][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [4]),
        .O(p_0_in__43[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r[42][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [42]),
        .I1(match4_145_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_145_return),
        .I4(p_0_in49_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [42]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r[42][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [4]),
        .I5(p_0_in49_in),
        .O(p_0_in__43[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [42]),
        .D(p_0_in__43[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [42]),
        .D(p_0_in__43[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [42]),
        .D(p_0_in__43[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [42]),
        .D(p_0_in__43[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [42]),
        .D(p_0_in__43[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[42].rd_buf_indx_cpy_r_reg[42][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [42]),
        .D(p_0_in__43[5]),
        .Q(p_0_in49_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[312],D[304]}),
        .DIB({D[296],D[288]}),
        .DIC({D[280],D[272]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [43]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [43]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [43]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [43]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [43]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [43]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[43].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[258] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [0]),
        .Q(c0_ddr4_app_rd_data[258]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[259] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [1]),
        .Q(c0_ddr4_app_rd_data[259]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[260] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [2]),
        .Q(c0_ddr4_app_rd_data[260]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[261] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [3]),
        .Q(c0_ddr4_app_rd_data[261]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[262] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [4]),
        .Q(c0_ddr4_app_rd_data[262]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[43].app_rd_data_ns_reg[263]_0 [5]),
        .Q(c0_ddr4_app_rd_data[263]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].init_done_r[43]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [43]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[43].init_done_r[43]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].init_done_r_reg[43] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[43].init_done_r[43]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [43]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r[43][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .O(p_0_in__44[0]));
  (* SOFT_HLUTNM = "soft_lutpair3051" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r[43][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [1]),
        .O(p_0_in__44[1]));
  (* SOFT_HLUTNM = "soft_lutpair3051" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r[43][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [2]),
        .O(p_0_in__44[2]));
  (* SOFT_HLUTNM = "soft_lutpair2959" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r[43][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [3]),
        .O(p_0_in__44[3]));
  (* SOFT_HLUTNM = "soft_lutpair2959" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r[43][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [4]),
        .O(p_0_in__44[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r[43][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [43]),
        .I1(match4_146_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_146_return),
        .I4(p_0_in50_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [43]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r[43][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [4]),
        .I5(p_0_in50_in),
        .O(p_0_in__44[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [43]),
        .D(p_0_in__44[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [43]),
        .D(p_0_in__44[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [43]),
        .D(p_0_in__44[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [43]),
        .D(p_0_in__44[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [43]),
        .D(p_0_in__44[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[43].rd_buf_indx_cpy_r_reg[43][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [43]),
        .D(p_0_in__44[5]),
        .Q(p_0_in50_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[297],D[289]}),
        .DIB({D[281],D[273]}),
        .DIC({D[265],D[257]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [44]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [44]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [44]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [44]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [44]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [44]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[44].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[264] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [0]),
        .Q(c0_ddr4_app_rd_data[264]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[265] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [1]),
        .Q(c0_ddr4_app_rd_data[265]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[266] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [2]),
        .Q(c0_ddr4_app_rd_data[266]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[267] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [3]),
        .Q(c0_ddr4_app_rd_data[267]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[268] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [4]),
        .Q(c0_ddr4_app_rd_data[268]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[44].app_rd_data_ns_reg[269]_0 [5]),
        .Q(c0_ddr4_app_rd_data[269]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].init_done_r[44]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [44]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[44].init_done_r[44]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].init_done_r_reg[44] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[44].init_done_r[44]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [44]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r[44][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .O(p_0_in__45[0]));
  (* SOFT_HLUTNM = "soft_lutpair3052" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r[44][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [1]),
        .O(p_0_in__45[1]));
  (* SOFT_HLUTNM = "soft_lutpair3052" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r[44][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [2]),
        .O(p_0_in__45[2]));
  (* SOFT_HLUTNM = "soft_lutpair2960" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r[44][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [3]),
        .O(p_0_in__45[3]));
  (* SOFT_HLUTNM = "soft_lutpair2960" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r[44][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [4]),
        .O(p_0_in__45[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r[44][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [44]),
        .I1(match4_147_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_147_return),
        .I4(p_0_in51_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [44]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r[44][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [4]),
        .I5(p_0_in51_in),
        .O(p_0_in__45[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [44]),
        .D(p_0_in__45[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [44]),
        .D(p_0_in__45[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [44]),
        .D(p_0_in__45[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [44]),
        .D(p_0_in__45[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [44]),
        .D(p_0_in__45[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[44].rd_buf_indx_cpy_r_reg[44][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [44]),
        .D(p_0_in__45[5]),
        .Q(p_0_in51_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[282],D[274]}),
        .DIB({D[266],D[258]}),
        .DIC({D[313],D[305]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [45]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [45]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [45]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [45]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [45]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [45]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[45].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[270] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [0]),
        .Q(c0_ddr4_app_rd_data[270]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[271] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [1]),
        .Q(c0_ddr4_app_rd_data[271]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[272] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [2]),
        .Q(c0_ddr4_app_rd_data[272]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[273] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [3]),
        .Q(c0_ddr4_app_rd_data[273]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[274] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [4]),
        .Q(c0_ddr4_app_rd_data[274]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[45].app_rd_data_ns_reg[275]_0 [5]),
        .Q(c0_ddr4_app_rd_data[275]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].init_done_r[45]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [45]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[45].init_done_r[45]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].init_done_r_reg[45] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[45].init_done_r[45]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [45]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r[45][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .O(p_0_in__46[0]));
  (* SOFT_HLUTNM = "soft_lutpair3053" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r[45][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [1]),
        .O(p_0_in__46[1]));
  (* SOFT_HLUTNM = "soft_lutpair3053" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r[45][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [2]),
        .O(p_0_in__46[2]));
  (* SOFT_HLUTNM = "soft_lutpair2961" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r[45][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [3]),
        .O(p_0_in__46[3]));
  (* SOFT_HLUTNM = "soft_lutpair2961" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r[45][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [4]),
        .O(p_0_in__46[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r[45][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [45]),
        .I1(match4_148_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_148_return),
        .I4(p_0_in52_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [45]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r[45][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [4]),
        .I5(p_0_in52_in),
        .O(p_0_in__46[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [45]),
        .D(p_0_in__46[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [45]),
        .D(p_0_in__46[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [45]),
        .D(p_0_in__46[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [45]),
        .D(p_0_in__46[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [45]),
        .D(p_0_in__46[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[45].rd_buf_indx_cpy_r_reg[45][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [45]),
        .D(p_0_in__46[5]),
        .Q(p_0_in52_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[267],D[259]}),
        .DIB({D[314],D[306]}),
        .DIC({D[298],D[290]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [46]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [46]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [46]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [46]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [46]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [46]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[46].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[276] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [0]),
        .Q(c0_ddr4_app_rd_data[276]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[277] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [1]),
        .Q(c0_ddr4_app_rd_data[277]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[278] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [2]),
        .Q(c0_ddr4_app_rd_data[278]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[279] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [3]),
        .Q(c0_ddr4_app_rd_data[279]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[280] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [4]),
        .Q(c0_ddr4_app_rd_data[280]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[46].app_rd_data_ns_reg[281]_0 [5]),
        .Q(c0_ddr4_app_rd_data[281]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].init_done_r[46]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [46]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[46].init_done_r[46]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].init_done_r_reg[46] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[46].init_done_r[46]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [46]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r[46][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .O(p_0_in__47[0]));
  (* SOFT_HLUTNM = "soft_lutpair3054" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r[46][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [1]),
        .O(p_0_in__47[1]));
  (* SOFT_HLUTNM = "soft_lutpair3054" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r[46][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [2]),
        .O(p_0_in__47[2]));
  (* SOFT_HLUTNM = "soft_lutpair2962" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r[46][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [3]),
        .O(p_0_in__47[3]));
  (* SOFT_HLUTNM = "soft_lutpair2962" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r[46][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [4]),
        .O(p_0_in__47[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r[46][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [46]),
        .I1(match4_149_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_149_return),
        .I4(p_0_in53_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [46]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r[46][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [4]),
        .I5(p_0_in53_in),
        .O(p_0_in__47[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [46]),
        .D(p_0_in__47[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [46]),
        .D(p_0_in__47[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [46]),
        .D(p_0_in__47[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [46]),
        .D(p_0_in__47[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [46]),
        .D(p_0_in__47[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[46].rd_buf_indx_cpy_r_reg[46][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [46]),
        .D(p_0_in__47[5]),
        .Q(p_0_in53_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[315],D[307]}),
        .DIB({D[299],D[291]}),
        .DIC({D[283],D[275]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [47]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [47]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [47]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [47]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [47]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [47]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[47].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[282] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [0]),
        .Q(c0_ddr4_app_rd_data[282]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[283] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [1]),
        .Q(c0_ddr4_app_rd_data[283]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[284] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [2]),
        .Q(c0_ddr4_app_rd_data[284]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[285] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [3]),
        .Q(c0_ddr4_app_rd_data[285]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[286] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [4]),
        .Q(c0_ddr4_app_rd_data[286]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[47].app_rd_data_ns_reg[287]_0 [5]),
        .Q(c0_ddr4_app_rd_data[287]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].init_done_r[47]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [47]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[47].init_done_r[47]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].init_done_r_reg[47] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[47].init_done_r[47]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [47]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r[47][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .O(p_0_in__48[0]));
  (* SOFT_HLUTNM = "soft_lutpair3055" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r[47][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [1]),
        .O(p_0_in__48[1]));
  (* SOFT_HLUTNM = "soft_lutpair3055" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r[47][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [2]),
        .O(p_0_in__48[2]));
  (* SOFT_HLUTNM = "soft_lutpair2963" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r[47][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [3]),
        .O(p_0_in__48[3]));
  (* SOFT_HLUTNM = "soft_lutpair2963" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r[47][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [4]),
        .O(p_0_in__48[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r[47][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [47]),
        .I1(match4_150_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_150_return),
        .I4(p_0_in54_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [47]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r[47][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [4]),
        .I5(p_0_in54_in),
        .O(p_0_in__48[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [47]),
        .D(p_0_in__48[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [47]),
        .D(p_0_in__48[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [47]),
        .D(p_0_in__48[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [47]),
        .D(p_0_in__48[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [47]),
        .D(p_0_in__48[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[47].rd_buf_indx_cpy_r_reg[47][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [47]),
        .D(p_0_in__48[5]),
        .Q(p_0_in54_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[300],D[292]}),
        .DIB({D[284],D[276]}),
        .DIC({D[268],D[260]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [48]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [48]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [48]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [48]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [48]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [48]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[48].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[288] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [0]),
        .Q(c0_ddr4_app_rd_data[288]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[289] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [1]),
        .Q(c0_ddr4_app_rd_data[289]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[290] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [2]),
        .Q(c0_ddr4_app_rd_data[290]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[291] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [3]),
        .Q(c0_ddr4_app_rd_data[291]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[292] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [4]),
        .Q(c0_ddr4_app_rd_data[292]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[48].app_rd_data_ns_reg[293]_0 [5]),
        .Q(c0_ddr4_app_rd_data[293]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].init_done_r[48]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [48]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[48].init_done_r[48]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].init_done_r_reg[48] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[48].init_done_r[48]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [48]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r[48][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .O(p_0_in__49[0]));
  (* SOFT_HLUTNM = "soft_lutpair3056" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r[48][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [1]),
        .O(p_0_in__49[1]));
  (* SOFT_HLUTNM = "soft_lutpair3056" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r[48][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [2]),
        .O(p_0_in__49[2]));
  (* SOFT_HLUTNM = "soft_lutpair2964" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r[48][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [3]),
        .O(p_0_in__49[3]));
  (* SOFT_HLUTNM = "soft_lutpair2964" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r[48][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [4]),
        .O(p_0_in__49[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r[48][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [48]),
        .I1(match4_151_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_151_return),
        .I4(p_0_in55_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [48]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r[48][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [4]),
        .I5(p_0_in55_in),
        .O(p_0_in__49[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [48]),
        .D(p_0_in__49[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [48]),
        .D(p_0_in__49[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [48]),
        .D(p_0_in__49[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [48]),
        .D(p_0_in__49[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [48]),
        .D(p_0_in__49[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[48].rd_buf_indx_cpy_r_reg[48][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [48]),
        .D(p_0_in__49[5]),
        .Q(p_0_in55_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[285],D[277]}),
        .DIB({D[269],D[261]}),
        .DIC({D[316],D[308]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [49]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [49]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [49]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [49]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [49]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [49]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[49].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[294] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [0]),
        .Q(c0_ddr4_app_rd_data[294]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[295] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [1]),
        .Q(c0_ddr4_app_rd_data[295]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[296] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [2]),
        .Q(c0_ddr4_app_rd_data[296]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[297] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [3]),
        .Q(c0_ddr4_app_rd_data[297]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[298] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [4]),
        .Q(c0_ddr4_app_rd_data[298]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[49].app_rd_data_ns_reg[299]_0 [5]),
        .Q(c0_ddr4_app_rd_data[299]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].init_done_r[49]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [49]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[49].init_done_r[49]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].init_done_r_reg[49] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[49].init_done_r[49]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [49]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r[49][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .O(p_0_in__50[0]));
  (* SOFT_HLUTNM = "soft_lutpair3057" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r[49][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [1]),
        .O(p_0_in__50[1]));
  (* SOFT_HLUTNM = "soft_lutpair3057" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r[49][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [2]),
        .O(p_0_in__50[2]));
  (* SOFT_HLUTNM = "soft_lutpair2965" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r[49][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [3]),
        .O(p_0_in__50[3]));
  (* SOFT_HLUTNM = "soft_lutpair2965" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r[49][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [4]),
        .O(p_0_in__50[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r[49][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [49]),
        .I1(match4_152_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_152_return),
        .I4(p_0_in56_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [49]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r[49][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [4]),
        .I5(p_0_in56_in),
        .O(p_0_in__50[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [49]),
        .D(p_0_in__50[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [49]),
        .D(p_0_in__50[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [49]),
        .D(p_0_in__50[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [49]),
        .D(p_0_in__50[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [49]),
        .D(p_0_in__50[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[49].rd_buf_indx_cpy_r_reg[49][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [49]),
        .D(p_0_in__50[5]),
        .Q(p_0_in56_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[43],D[35]}),
        .DIB({D[27],D[19]}),
        .DIC({D[11],D[3]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [4]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [4]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [4]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [4]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[24] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [0]),
        .Q(c0_ddr4_app_rd_data[24]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[25] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [1]),
        .Q(c0_ddr4_app_rd_data[25]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[26] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [2]),
        .Q(c0_ddr4_app_rd_data[26]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[27] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [3]),
        .Q(c0_ddr4_app_rd_data[27]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[28] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [4]),
        .Q(c0_ddr4_app_rd_data[28]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[4].app_rd_data_ns_reg[29]_0 [5]),
        .Q(c0_ddr4_app_rd_data[29]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].init_done_r[4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[4].init_done_r[4]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].init_done_r_reg[4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[4].init_done_r[4]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r[4][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .O(p_0_in__5[0]));
  (* SOFT_HLUTNM = "soft_lutpair3012" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r[4][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [1]),
        .O(p_0_in__5[1]));
  (* SOFT_HLUTNM = "soft_lutpair3012" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r[4][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [2]),
        .O(p_0_in__5[2]));
  (* SOFT_HLUTNM = "soft_lutpair2920" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r[4][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [3]),
        .O(p_0_in__5[3]));
  (* SOFT_HLUTNM = "soft_lutpair2920" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r[4][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [4]),
        .O(p_0_in__5[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r[4][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [4]),
        .I1(match4_17_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_17_return),
        .I4(p_0_in9_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r[4][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [4]),
        .I5(p_0_in9_in),
        .O(p_0_in__5[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [4]),
        .D(p_0_in__5[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [4]),
        .D(p_0_in__5[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [4]),
        .D(p_0_in__5[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [4]),
        .D(p_0_in__5[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [4]),
        .D(p_0_in__5[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[4].rd_buf_indx_cpy_r_reg[4][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [4]),
        .D(p_0_in__5[5]),
        .Q(p_0_in9_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[270],D[262]}),
        .DIB({D[317],D[309]}),
        .DIC({D[301],D[293]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [50]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [50]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [50]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [50]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [50]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [50]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[50].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[300] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [0]),
        .Q(c0_ddr4_app_rd_data[300]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[301] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [1]),
        .Q(c0_ddr4_app_rd_data[301]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[302] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [2]),
        .Q(c0_ddr4_app_rd_data[302]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[303] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [3]),
        .Q(c0_ddr4_app_rd_data[303]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[304] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [4]),
        .Q(c0_ddr4_app_rd_data[304]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[50].app_rd_data_ns_reg[305]_0 [5]),
        .Q(c0_ddr4_app_rd_data[305]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].init_done_r[50]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [50]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[50].init_done_r[50]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].init_done_r_reg[50] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[50].init_done_r[50]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [50]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r[50][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .O(p_0_in__51[0]));
  (* SOFT_HLUTNM = "soft_lutpair3058" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r[50][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [1]),
        .O(p_0_in__51[1]));
  (* SOFT_HLUTNM = "soft_lutpair3058" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r[50][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [2]),
        .O(p_0_in__51[2]));
  (* SOFT_HLUTNM = "soft_lutpair2966" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r[50][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [3]),
        .O(p_0_in__51[3]));
  (* SOFT_HLUTNM = "soft_lutpair2966" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r[50][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [4]),
        .O(p_0_in__51[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r[50][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [50]),
        .I1(match4_153_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_153_return),
        .I4(p_0_in57_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [50]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r[50][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [4]),
        .I5(p_0_in57_in),
        .O(p_0_in__51[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [50]),
        .D(p_0_in__51[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [50]),
        .D(p_0_in__51[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [50]),
        .D(p_0_in__51[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [50]),
        .D(p_0_in__51[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [50]),
        .D(p_0_in__51[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[50].rd_buf_indx_cpy_r_reg[50][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [50]),
        .D(p_0_in__51[5]),
        .Q(p_0_in57_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[318],D[310]}),
        .DIB({D[302],D[294]}),
        .DIC({D[286],D[278]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [51]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [51]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [51]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [51]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [51]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [51]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[51].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[306] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [0]),
        .Q(c0_ddr4_app_rd_data[306]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[307] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [1]),
        .Q(c0_ddr4_app_rd_data[307]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[308] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [2]),
        .Q(c0_ddr4_app_rd_data[308]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[309] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [3]),
        .Q(c0_ddr4_app_rd_data[309]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[310] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [4]),
        .Q(c0_ddr4_app_rd_data[310]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[51].app_rd_data_ns_reg[311]_0 [5]),
        .Q(c0_ddr4_app_rd_data[311]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].init_done_r[51]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [51]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[51].init_done_r[51]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].init_done_r_reg[51] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[51].init_done_r[51]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [51]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r[51][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .O(p_0_in__52[0]));
  (* SOFT_HLUTNM = "soft_lutpair3059" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r[51][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [1]),
        .O(p_0_in__52[1]));
  (* SOFT_HLUTNM = "soft_lutpair3059" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r[51][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [2]),
        .O(p_0_in__52[2]));
  (* SOFT_HLUTNM = "soft_lutpair2967" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r[51][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [3]),
        .O(p_0_in__52[3]));
  (* SOFT_HLUTNM = "soft_lutpair2967" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r[51][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [4]),
        .O(p_0_in__52[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r[51][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [51]),
        .I1(match4_154_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_154_return),
        .I4(p_0_in58_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [51]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r[51][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [4]),
        .I5(p_0_in58_in),
        .O(p_0_in__52[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [51]),
        .D(p_0_in__52[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [51]),
        .D(p_0_in__52[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [51]),
        .D(p_0_in__52[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [51]),
        .D(p_0_in__52[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [51]),
        .D(p_0_in__52[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[51].rd_buf_indx_cpy_r_reg[51][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [51]),
        .D(p_0_in__52[5]),
        .Q(p_0_in58_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[303],D[295]}),
        .DIB({D[287],D[279]}),
        .DIC({D[271],D[263]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [52]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [52]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [52]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [52]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [52]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [52]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[52].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[312] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [0]),
        .Q(c0_ddr4_app_rd_data[312]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[313] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [1]),
        .Q(c0_ddr4_app_rd_data[313]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[314] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [2]),
        .Q(c0_ddr4_app_rd_data[314]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[315] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [3]),
        .Q(c0_ddr4_app_rd_data[315]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[316] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [4]),
        .Q(c0_ddr4_app_rd_data[316]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[52].app_rd_data_ns_reg[317]_0 [5]),
        .Q(c0_ddr4_app_rd_data[317]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].init_done_r[52]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [52]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[52].init_done_r[52]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].init_done_r_reg[52] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[52].init_done_r[52]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [52]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r[52][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .O(p_0_in__53[0]));
  (* SOFT_HLUTNM = "soft_lutpair3060" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r[52][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [1]),
        .O(p_0_in__53[1]));
  (* SOFT_HLUTNM = "soft_lutpair3060" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r[52][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [2]),
        .O(p_0_in__53[2]));
  (* SOFT_HLUTNM = "soft_lutpair2968" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r[52][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [3]),
        .O(p_0_in__53[3]));
  (* SOFT_HLUTNM = "soft_lutpair2968" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r[52][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [4]),
        .O(p_0_in__53[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r[52][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [52]),
        .I1(match4_155_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_155_return),
        .I4(p_0_in59_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [52]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r[52][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [4]),
        .I5(p_0_in59_in),
        .O(p_0_in__53[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [52]),
        .D(p_0_in__53[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [52]),
        .D(p_0_in__53[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [52]),
        .D(p_0_in__53[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [52]),
        .D(p_0_in__53[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [52]),
        .D(p_0_in__53[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[52].rd_buf_indx_cpy_r_reg[52][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [52]),
        .D(p_0_in__53[5]),
        .Q(p_0_in59_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[344],D[336]}),
        .DIB({D[328],D[320]}),
        .DIC({D[319],D[311]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [53]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [53]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [53]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [53]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [53]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [53]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[53].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[318] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [0]),
        .Q(c0_ddr4_app_rd_data[318]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[319] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [1]),
        .Q(c0_ddr4_app_rd_data[319]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[320] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [2]),
        .Q(c0_ddr4_app_rd_data[320]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[321] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [3]),
        .Q(c0_ddr4_app_rd_data[321]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[322] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [4]),
        .Q(c0_ddr4_app_rd_data[322]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[53].app_rd_data_ns_reg[323]_0 [5]),
        .Q(c0_ddr4_app_rd_data[323]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].init_done_r[53]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [53]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[53].init_done_r[53]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].init_done_r_reg[53] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[53].init_done_r[53]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [53]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r[53][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .O(p_0_in__54[0]));
  (* SOFT_HLUTNM = "soft_lutpair3061" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r[53][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [1]),
        .O(p_0_in__54[1]));
  (* SOFT_HLUTNM = "soft_lutpair3061" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r[53][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [2]),
        .O(p_0_in__54[2]));
  (* SOFT_HLUTNM = "soft_lutpair2969" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r[53][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [3]),
        .O(p_0_in__54[3]));
  (* SOFT_HLUTNM = "soft_lutpair2969" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r[53][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [4]),
        .O(p_0_in__54[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r[53][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [53]),
        .I1(match4_156_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_156_return),
        .I4(p_0_in60_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [53]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r[53][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [4]),
        .I5(p_0_in60_in),
        .O(p_0_in__54[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [53]),
        .D(p_0_in__54[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [53]),
        .D(p_0_in__54[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [53]),
        .D(p_0_in__54[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [53]),
        .D(p_0_in__54[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [53]),
        .D(p_0_in__54[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[53].rd_buf_indx_cpy_r_reg[53][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [53]),
        .D(p_0_in__54[5]),
        .Q(p_0_in60_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[329],D[321]}),
        .DIB({D[376],D[368]}),
        .DIC({D[360],D[352]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [54]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [54]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [54]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [54]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [54]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [54]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[54].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[324] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [0]),
        .Q(c0_ddr4_app_rd_data[324]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[325] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [1]),
        .Q(c0_ddr4_app_rd_data[325]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[326] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [2]),
        .Q(c0_ddr4_app_rd_data[326]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[327] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [3]),
        .Q(c0_ddr4_app_rd_data[327]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[328] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [4]),
        .Q(c0_ddr4_app_rd_data[328]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[54].app_rd_data_ns_reg[329]_0 [5]),
        .Q(c0_ddr4_app_rd_data[329]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].init_done_r[54]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [54]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[54].init_done_r[54]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].init_done_r_reg[54] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[54].init_done_r[54]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [54]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r[54][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .O(p_0_in__55[0]));
  (* SOFT_HLUTNM = "soft_lutpair3062" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r[54][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [1]),
        .O(p_0_in__55[1]));
  (* SOFT_HLUTNM = "soft_lutpair3062" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r[54][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [2]),
        .O(p_0_in__55[2]));
  (* SOFT_HLUTNM = "soft_lutpair2970" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r[54][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [3]),
        .O(p_0_in__55[3]));
  (* SOFT_HLUTNM = "soft_lutpair2970" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r[54][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [4]),
        .O(p_0_in__55[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r[54][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [54]),
        .I1(match4_157_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_157_return),
        .I4(p_0_in61_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [54]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r[54][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [4]),
        .I5(p_0_in61_in),
        .O(p_0_in__55[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [54]),
        .D(p_0_in__55[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [54]),
        .D(p_0_in__55[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [54]),
        .D(p_0_in__55[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [54]),
        .D(p_0_in__55[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [54]),
        .D(p_0_in__55[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[54].rd_buf_indx_cpy_r_reg[54][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [54]),
        .D(p_0_in__55[5]),
        .Q(p_0_in61_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[377],D[369]}),
        .DIB({D[361],D[353]}),
        .DIC({D[345],D[337]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [55]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [55]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [55]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [55]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [55]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [55]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[55].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[330] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [0]),
        .Q(c0_ddr4_app_rd_data[330]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[331] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [1]),
        .Q(c0_ddr4_app_rd_data[331]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[332] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [2]),
        .Q(c0_ddr4_app_rd_data[332]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[333] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [3]),
        .Q(c0_ddr4_app_rd_data[333]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[334] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [4]),
        .Q(c0_ddr4_app_rd_data[334]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[55].app_rd_data_ns_reg[335]_0 [5]),
        .Q(c0_ddr4_app_rd_data[335]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].init_done_r[55]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [55]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[55].init_done_r[55]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].init_done_r_reg[55] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[55].init_done_r[55]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [55]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r[55][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .O(p_0_in__56[0]));
  (* SOFT_HLUTNM = "soft_lutpair3063" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r[55][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [1]),
        .O(p_0_in__56[1]));
  (* SOFT_HLUTNM = "soft_lutpair3063" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r[55][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [2]),
        .O(p_0_in__56[2]));
  (* SOFT_HLUTNM = "soft_lutpair2971" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r[55][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [3]),
        .O(p_0_in__56[3]));
  (* SOFT_HLUTNM = "soft_lutpair2971" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r[55][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [4]),
        .O(p_0_in__56[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r[55][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [55]),
        .I1(match4_158_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_158_return),
        .I4(p_0_in62_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [55]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r[55][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [4]),
        .I5(p_0_in62_in),
        .O(p_0_in__56[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [55]),
        .D(p_0_in__56[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [55]),
        .D(p_0_in__56[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [55]),
        .D(p_0_in__56[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [55]),
        .D(p_0_in__56[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [55]),
        .D(p_0_in__56[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[55].rd_buf_indx_cpy_r_reg[55][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [55]),
        .D(p_0_in__56[5]),
        .Q(p_0_in62_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[362],D[354]}),
        .DIB({D[346],D[338]}),
        .DIC({D[330],D[322]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [56]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [56]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [56]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [56]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [56]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [56]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[56].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[336] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [0]),
        .Q(c0_ddr4_app_rd_data[336]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[337] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [1]),
        .Q(c0_ddr4_app_rd_data[337]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[338] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [2]),
        .Q(c0_ddr4_app_rd_data[338]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[339] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [3]),
        .Q(c0_ddr4_app_rd_data[339]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[340] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [4]),
        .Q(c0_ddr4_app_rd_data[340]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[56].app_rd_data_ns_reg[341]_0 [5]),
        .Q(c0_ddr4_app_rd_data[341]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].init_done_r[56]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [56]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[56].init_done_r[56]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].init_done_r_reg[56] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[56].init_done_r[56]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [56]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r[56][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .O(p_0_in__57[0]));
  (* SOFT_HLUTNM = "soft_lutpair3064" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r[56][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [1]),
        .O(p_0_in__57[1]));
  (* SOFT_HLUTNM = "soft_lutpair3064" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r[56][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [2]),
        .O(p_0_in__57[2]));
  (* SOFT_HLUTNM = "soft_lutpair2972" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r[56][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [3]),
        .O(p_0_in__57[3]));
  (* SOFT_HLUTNM = "soft_lutpair2972" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r[56][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [4]),
        .O(p_0_in__57[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r[56][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [56]),
        .I1(match4_159_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_159_return),
        .I4(p_0_in63_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [56]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r[56][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [4]),
        .I5(p_0_in63_in),
        .O(p_0_in__57[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [56]),
        .D(p_0_in__57[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [56]),
        .D(p_0_in__57[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [56]),
        .D(p_0_in__57[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [56]),
        .D(p_0_in__57[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [56]),
        .D(p_0_in__57[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[56].rd_buf_indx_cpy_r_reg[56][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [56]),
        .D(p_0_in__57[5]),
        .Q(p_0_in63_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[347],D[339]}),
        .DIB({D[331],D[323]}),
        .DIC({D[378],D[370]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [57]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [57]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [57]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [57]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [57]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [57]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[57].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[342] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [0]),
        .Q(c0_ddr4_app_rd_data[342]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[343] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [1]),
        .Q(c0_ddr4_app_rd_data[343]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[344] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [2]),
        .Q(c0_ddr4_app_rd_data[344]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[345] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [3]),
        .Q(c0_ddr4_app_rd_data[345]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[346] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [4]),
        .Q(c0_ddr4_app_rd_data[346]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[57].app_rd_data_ns_reg[347]_0 [5]),
        .Q(c0_ddr4_app_rd_data[347]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].init_done_r[57]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [57]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[57].init_done_r[57]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].init_done_r_reg[57] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[57].init_done_r[57]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [57]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r[57][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .O(p_0_in__58[0]));
  (* SOFT_HLUTNM = "soft_lutpair3065" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r[57][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [1]),
        .O(p_0_in__58[1]));
  (* SOFT_HLUTNM = "soft_lutpair3065" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r[57][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [2]),
        .O(p_0_in__58[2]));
  (* SOFT_HLUTNM = "soft_lutpair2973" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r[57][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [3]),
        .O(p_0_in__58[3]));
  (* SOFT_HLUTNM = "soft_lutpair2973" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r[57][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [4]),
        .O(p_0_in__58[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r[57][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [57]),
        .I1(match4_160_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_160_return),
        .I4(p_0_in64_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [57]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r[57][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [4]),
        .I5(p_0_in64_in),
        .O(p_0_in__58[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [57]),
        .D(p_0_in__58[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [57]),
        .D(p_0_in__58[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [57]),
        .D(p_0_in__58[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [57]),
        .D(p_0_in__58[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [57]),
        .D(p_0_in__58[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[57].rd_buf_indx_cpy_r_reg[57][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [57]),
        .D(p_0_in__58[5]),
        .Q(p_0_in64_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[332],D[324]}),
        .DIB({D[379],D[371]}),
        .DIC({D[363],D[355]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [58]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [58]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [58]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [58]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [58]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [58]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[58].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[348] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [0]),
        .Q(c0_ddr4_app_rd_data[348]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[349] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [1]),
        .Q(c0_ddr4_app_rd_data[349]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[350] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [2]),
        .Q(c0_ddr4_app_rd_data[350]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[351] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [3]),
        .Q(c0_ddr4_app_rd_data[351]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[352] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [4]),
        .Q(c0_ddr4_app_rd_data[352]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[58].app_rd_data_ns_reg[353]_0 [5]),
        .Q(c0_ddr4_app_rd_data[353]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].init_done_r[58]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [58]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[58].init_done_r[58]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].init_done_r_reg[58] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[58].init_done_r[58]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [58]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r[58][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .O(p_0_in__59[0]));
  (* SOFT_HLUTNM = "soft_lutpair3066" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r[58][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [1]),
        .O(p_0_in__59[1]));
  (* SOFT_HLUTNM = "soft_lutpair3066" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r[58][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [2]),
        .O(p_0_in__59[2]));
  (* SOFT_HLUTNM = "soft_lutpair2974" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r[58][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [3]),
        .O(p_0_in__59[3]));
  (* SOFT_HLUTNM = "soft_lutpair2974" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r[58][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [4]),
        .O(p_0_in__59[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r[58][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [58]),
        .I1(match4_161_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_161_return),
        .I4(p_0_in65_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [58]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r[58][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [4]),
        .I5(p_0_in65_in),
        .O(p_0_in__59[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [58]),
        .D(p_0_in__59[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [58]),
        .D(p_0_in__59[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [58]),
        .D(p_0_in__59[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [58]),
        .D(p_0_in__59[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [58]),
        .D(p_0_in__59[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[58].rd_buf_indx_cpy_r_reg[58][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [58]),
        .D(p_0_in__59[5]),
        .Q(p_0_in65_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[380],D[372]}),
        .DIB({D[364],D[356]}),
        .DIC({D[348],D[340]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [59]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [59]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [59]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [59]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [59]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [59]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[59].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[354] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [0]),
        .Q(c0_ddr4_app_rd_data[354]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[355] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [1]),
        .Q(c0_ddr4_app_rd_data[355]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[356] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [2]),
        .Q(c0_ddr4_app_rd_data[356]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[357] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [3]),
        .Q(c0_ddr4_app_rd_data[357]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[358] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [4]),
        .Q(c0_ddr4_app_rd_data[358]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[59].app_rd_data_ns_reg[359]_0 [5]),
        .Q(c0_ddr4_app_rd_data[359]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].init_done_r[59]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [59]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[59].init_done_r[59]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].init_done_r_reg[59] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[59].init_done_r[59]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [59]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r[59][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .O(p_0_in__60[0]));
  (* SOFT_HLUTNM = "soft_lutpair3067" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r[59][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [1]),
        .O(p_0_in__60[1]));
  (* SOFT_HLUTNM = "soft_lutpair3067" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r[59][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [2]),
        .O(p_0_in__60[2]));
  (* SOFT_HLUTNM = "soft_lutpair2975" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r[59][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [3]),
        .O(p_0_in__60[3]));
  (* SOFT_HLUTNM = "soft_lutpair2975" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r[59][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [4]),
        .O(p_0_in__60[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r[59][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [59]),
        .I1(match4_162_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_162_return),
        .I4(p_0_in66_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [59]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r[59][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [4]),
        .I5(p_0_in66_in),
        .O(p_0_in__60[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [59]),
        .D(p_0_in__60[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [59]),
        .D(p_0_in__60[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [59]),
        .D(p_0_in__60[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [59]),
        .D(p_0_in__60[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [59]),
        .D(p_0_in__60[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[59].rd_buf_indx_cpy_r_reg[59][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [59]),
        .D(p_0_in__60[5]),
        .Q(p_0_in66_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[28],D[20]}),
        .DIB({D[12],D[4]}),
        .DIC({D[59],D[51]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [5]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [5]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [5]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [5]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [5]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [5]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[30] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [0]),
        .Q(c0_ddr4_app_rd_data[30]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[31] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [1]),
        .Q(c0_ddr4_app_rd_data[31]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[32] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [2]),
        .Q(c0_ddr4_app_rd_data[32]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[33] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [3]),
        .Q(c0_ddr4_app_rd_data[33]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[34] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [4]),
        .Q(c0_ddr4_app_rd_data[34]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[5].app_rd_data_ns_reg[35]_0 [5]),
        .Q(c0_ddr4_app_rd_data[35]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].init_done_r[5]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [5]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[5].init_done_r[5]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].init_done_r_reg[5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[5].init_done_r[5]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [5]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r[5][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .O(p_0_in__6[0]));
  (* SOFT_HLUTNM = "soft_lutpair3013" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r[5][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [1]),
        .O(p_0_in__6[1]));
  (* SOFT_HLUTNM = "soft_lutpair3013" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r[5][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [2]),
        .O(p_0_in__6[2]));
  (* SOFT_HLUTNM = "soft_lutpair2921" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r[5][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [3]),
        .O(p_0_in__6[3]));
  (* SOFT_HLUTNM = "soft_lutpair2921" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r[5][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [4]),
        .O(p_0_in__6[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r[5][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [5]),
        .I1(match4_18_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_18_return),
        .I4(p_0_in11_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [5]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r[5][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [4]),
        .I5(p_0_in11_in),
        .O(p_0_in__6[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [5]),
        .D(p_0_in__6[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [5]),
        .D(p_0_in__6[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [5]),
        .D(p_0_in__6[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [5]),
        .D(p_0_in__6[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [5]),
        .D(p_0_in__6[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[5].rd_buf_indx_cpy_r_reg[5][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [5]),
        .D(p_0_in__6[5]),
        .Q(p_0_in11_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[365],D[357]}),
        .DIB({D[349],D[341]}),
        .DIC({D[333],D[325]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [60]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [60]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [60]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [60]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [60]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [60]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[60].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[360] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [0]),
        .Q(c0_ddr4_app_rd_data[360]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[361] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [1]),
        .Q(c0_ddr4_app_rd_data[361]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[362] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [2]),
        .Q(c0_ddr4_app_rd_data[362]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[363] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [3]),
        .Q(c0_ddr4_app_rd_data[363]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[364] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [4]),
        .Q(c0_ddr4_app_rd_data[364]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[60].app_rd_data_ns_reg[365]_0 [5]),
        .Q(c0_ddr4_app_rd_data[365]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].init_done_r[60]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [60]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[60].init_done_r[60]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].init_done_r_reg[60] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[60].init_done_r[60]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [60]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r[60][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .O(p_0_in__61[0]));
  (* SOFT_HLUTNM = "soft_lutpair3068" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r[60][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [1]),
        .O(p_0_in__61[1]));
  (* SOFT_HLUTNM = "soft_lutpair3068" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r[60][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [2]),
        .O(p_0_in__61[2]));
  (* SOFT_HLUTNM = "soft_lutpair2976" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r[60][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [3]),
        .O(p_0_in__61[3]));
  (* SOFT_HLUTNM = "soft_lutpair2976" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r[60][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [4]),
        .O(p_0_in__61[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r[60][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [60]),
        .I1(match4_163_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_163_return),
        .I4(p_0_in67_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [60]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r[60][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [4]),
        .I5(p_0_in67_in),
        .O(p_0_in__61[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [60]),
        .D(p_0_in__61[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [60]),
        .D(p_0_in__61[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [60]),
        .D(p_0_in__61[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [60]),
        .D(p_0_in__61[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [60]),
        .D(p_0_in__61[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[60].rd_buf_indx_cpy_r_reg[60][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [60]),
        .D(p_0_in__61[5]),
        .Q(p_0_in67_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[350],D[342]}),
        .DIB({D[334],D[326]}),
        .DIC({D[381],D[373]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [61]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [61]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [61]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [61]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [61]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [61]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[61].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[366] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [0]),
        .Q(c0_ddr4_app_rd_data[366]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[367] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [1]),
        .Q(c0_ddr4_app_rd_data[367]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[368] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [2]),
        .Q(c0_ddr4_app_rd_data[368]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[369] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [3]),
        .Q(c0_ddr4_app_rd_data[369]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[370] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [4]),
        .Q(c0_ddr4_app_rd_data[370]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[61].app_rd_data_ns_reg[371]_0 [5]),
        .Q(c0_ddr4_app_rd_data[371]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].init_done_r[61]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [61]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[61].init_done_r[61]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].init_done_r_reg[61] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[61].init_done_r[61]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [61]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r[61][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .O(p_0_in__62[0]));
  (* SOFT_HLUTNM = "soft_lutpair3069" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r[61][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [1]),
        .O(p_0_in__62[1]));
  (* SOFT_HLUTNM = "soft_lutpair3069" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r[61][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [2]),
        .O(p_0_in__62[2]));
  (* SOFT_HLUTNM = "soft_lutpair2977" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r[61][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [3]),
        .O(p_0_in__62[3]));
  (* SOFT_HLUTNM = "soft_lutpair2977" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r[61][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [4]),
        .O(p_0_in__62[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r[61][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [61]),
        .I1(match4_164_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_164_return),
        .I4(p_0_in68_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [61]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r[61][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [4]),
        .I5(p_0_in68_in),
        .O(p_0_in__62[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [61]),
        .D(p_0_in__62[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [61]),
        .D(p_0_in__62[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [61]),
        .D(p_0_in__62[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [61]),
        .D(p_0_in__62[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [61]),
        .D(p_0_in__62[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[61].rd_buf_indx_cpy_r_reg[61][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [61]),
        .D(p_0_in__62[5]),
        .Q(p_0_in68_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[335],D[327]}),
        .DIB({D[382],D[374]}),
        .DIC({D[366],D[358]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [62]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [62]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [62]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [62]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [62]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [62]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[62].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[372] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [0]),
        .Q(c0_ddr4_app_rd_data[372]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[373] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [1]),
        .Q(c0_ddr4_app_rd_data[373]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[374] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [2]),
        .Q(c0_ddr4_app_rd_data[374]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[375] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [3]),
        .Q(c0_ddr4_app_rd_data[375]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[376] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [4]),
        .Q(c0_ddr4_app_rd_data[376]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[62].app_rd_data_ns_reg[377]_0 [5]),
        .Q(c0_ddr4_app_rd_data[377]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].init_done_r[62]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [62]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[62].init_done_r[62]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].init_done_r_reg[62] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[62].init_done_r[62]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [62]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r[62][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .O(p_0_in__63[0]));
  (* SOFT_HLUTNM = "soft_lutpair3070" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r[62][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [1]),
        .O(p_0_in__63[1]));
  (* SOFT_HLUTNM = "soft_lutpair3070" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r[62][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [2]),
        .O(p_0_in__63[2]));
  (* SOFT_HLUTNM = "soft_lutpair2978" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r[62][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [3]),
        .O(p_0_in__63[3]));
  (* SOFT_HLUTNM = "soft_lutpair2978" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r[62][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [4]),
        .O(p_0_in__63[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r[62][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [62]),
        .I1(match4_165_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_165_return),
        .I4(p_0_in69_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [62]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r[62][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [4]),
        .I5(p_0_in69_in),
        .O(p_0_in__63[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [62]),
        .D(p_0_in__63[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [62]),
        .D(p_0_in__63[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [62]),
        .D(p_0_in__63[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [62]),
        .D(p_0_in__63[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [62]),
        .D(p_0_in__63[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[62].rd_buf_indx_cpy_r_reg[62][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [62]),
        .D(p_0_in__63[5]),
        .Q(p_0_in69_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[383],D[375]}),
        .DIB({D[367],D[359]}),
        .DIC({D[351],D[343]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [63]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [63]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [63]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [63]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [63]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [63]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[63].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[378] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [0]),
        .Q(c0_ddr4_app_rd_data[378]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[379] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [1]),
        .Q(c0_ddr4_app_rd_data[379]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[380] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [2]),
        .Q(c0_ddr4_app_rd_data[380]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[381] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [3]),
        .Q(c0_ddr4_app_rd_data[381]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[382] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [4]),
        .Q(c0_ddr4_app_rd_data[382]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[63].app_rd_data_ns_reg[383]_0 [5]),
        .Q(c0_ddr4_app_rd_data[383]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].init_done_r[63]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [63]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[63].init_done_r[63]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].init_done_r_reg[63] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[63].init_done_r[63]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [63]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r[63][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .O(p_0_in__64[0]));
  (* SOFT_HLUTNM = "soft_lutpair3071" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r[63][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [1]),
        .O(p_0_in__64[1]));
  (* SOFT_HLUTNM = "soft_lutpair3071" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r[63][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [2]),
        .O(p_0_in__64[2]));
  (* SOFT_HLUTNM = "soft_lutpair2979" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r[63][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [3]),
        .O(p_0_in__64[3]));
  (* SOFT_HLUTNM = "soft_lutpair2979" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r[63][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [4]),
        .O(p_0_in__64[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r[63][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [63]),
        .I1(match4_166_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_166_return),
        .I4(p_0_in70_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [63]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r[63][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [4]),
        .I5(p_0_in70_in),
        .O(p_0_in__64[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [63]),
        .D(p_0_in__64[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [63]),
        .D(p_0_in__64[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [63]),
        .D(p_0_in__64[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [63]),
        .D(p_0_in__64[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [63]),
        .D(p_0_in__64[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[63].rd_buf_indx_cpy_r_reg[63][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [63]),
        .D(p_0_in__64[5]),
        .Q(p_0_in70_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[424],D[416]}),
        .DIB({D[408],D[400]}),
        .DIC({D[392],D[384]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [64]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [64]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [64]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [64]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [64]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [64]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[64].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[384] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [0]),
        .Q(c0_ddr4_app_rd_data[384]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[385] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [1]),
        .Q(c0_ddr4_app_rd_data[385]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[386] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [2]),
        .Q(c0_ddr4_app_rd_data[386]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[387] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [3]),
        .Q(c0_ddr4_app_rd_data[387]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[388] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [4]),
        .Q(c0_ddr4_app_rd_data[388]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[64].app_rd_data_ns_reg[389]_0 [5]),
        .Q(c0_ddr4_app_rd_data[389]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].init_done_r[64]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [64]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[64].init_done_r[64]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].init_done_r_reg[64] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[64].init_done_r[64]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [64]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r[64][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .O(p_0_in__65[0]));
  (* SOFT_HLUTNM = "soft_lutpair3072" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r[64][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [1]),
        .O(p_0_in__65[1]));
  (* SOFT_HLUTNM = "soft_lutpair3072" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r[64][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [2]),
        .O(p_0_in__65[2]));
  (* SOFT_HLUTNM = "soft_lutpair2980" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r[64][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [3]),
        .O(p_0_in__65[3]));
  (* SOFT_HLUTNM = "soft_lutpair2980" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r[64][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [4]),
        .O(p_0_in__65[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r[64][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [64]),
        .I1(match4_167_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_167_return),
        .I4(p_0_in71_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [64]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r[64][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [4]),
        .I5(p_0_in71_in),
        .O(p_0_in__65[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [64]),
        .D(p_0_in__65[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [64]),
        .D(p_0_in__65[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [64]),
        .D(p_0_in__65[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [64]),
        .D(p_0_in__65[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [64]),
        .D(p_0_in__65[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[64].rd_buf_indx_cpy_r_reg[64][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [64]),
        .D(p_0_in__65[5]),
        .Q(p_0_in71_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[409],D[401]}),
        .DIB({D[393],D[385]}),
        .DIC({D[440],D[432]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [65]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [65]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [65]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [65]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [65]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [65]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[65].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[390] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [0]),
        .Q(c0_ddr4_app_rd_data[390]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[391] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [1]),
        .Q(c0_ddr4_app_rd_data[391]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[392] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [2]),
        .Q(c0_ddr4_app_rd_data[392]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[393] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [3]),
        .Q(c0_ddr4_app_rd_data[393]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[394] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [4]),
        .Q(c0_ddr4_app_rd_data[394]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[65].app_rd_data_ns_reg[395]_0 [5]),
        .Q(c0_ddr4_app_rd_data[395]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].init_done_r[65]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [65]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[65].init_done_r[65]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].init_done_r_reg[65] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[65].init_done_r[65]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [65]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r[65][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .O(p_0_in__66[0]));
  (* SOFT_HLUTNM = "soft_lutpair3073" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r[65][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [1]),
        .O(p_0_in__66[1]));
  (* SOFT_HLUTNM = "soft_lutpair3073" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r[65][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [2]),
        .O(p_0_in__66[2]));
  (* SOFT_HLUTNM = "soft_lutpair2981" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r[65][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [3]),
        .O(p_0_in__66[3]));
  (* SOFT_HLUTNM = "soft_lutpair2981" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r[65][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [4]),
        .O(p_0_in__66[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r[65][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [65]),
        .I1(match4_168_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_168_return),
        .I4(p_0_in72_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [65]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r[65][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [4]),
        .I5(p_0_in72_in),
        .O(p_0_in__66[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [65]),
        .D(p_0_in__66[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [65]),
        .D(p_0_in__66[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [65]),
        .D(p_0_in__66[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [65]),
        .D(p_0_in__66[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [65]),
        .D(p_0_in__66[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[65].rd_buf_indx_cpy_r_reg[65][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [65]),
        .D(p_0_in__66[5]),
        .Q(p_0_in72_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[394],D[386]}),
        .DIB({D[441],D[433]}),
        .DIC({D[425],D[417]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [66]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [66]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [66]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [66]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [66]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [66]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[66].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[396] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [0]),
        .Q(c0_ddr4_app_rd_data[396]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[397] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [1]),
        .Q(c0_ddr4_app_rd_data[397]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[398] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [2]),
        .Q(c0_ddr4_app_rd_data[398]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[399] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [3]),
        .Q(c0_ddr4_app_rd_data[399]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[400] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [4]),
        .Q(c0_ddr4_app_rd_data[400]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[66].app_rd_data_ns_reg[401]_0 [5]),
        .Q(c0_ddr4_app_rd_data[401]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].init_done_r[66]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [66]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[66].init_done_r[66]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].init_done_r_reg[66] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[66].init_done_r[66]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [66]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r[66][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .O(p_0_in__67[0]));
  (* SOFT_HLUTNM = "soft_lutpair3074" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r[66][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [1]),
        .O(p_0_in__67[1]));
  (* SOFT_HLUTNM = "soft_lutpair3074" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r[66][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [2]),
        .O(p_0_in__67[2]));
  (* SOFT_HLUTNM = "soft_lutpair2982" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r[66][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [3]),
        .O(p_0_in__67[3]));
  (* SOFT_HLUTNM = "soft_lutpair2982" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r[66][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [4]),
        .O(p_0_in__67[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r[66][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [66]),
        .I1(match4_169_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_169_return),
        .I4(p_0_in73_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [66]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r[66][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [4]),
        .I5(p_0_in73_in),
        .O(p_0_in__67[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [66]),
        .D(p_0_in__67[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [66]),
        .D(p_0_in__67[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [66]),
        .D(p_0_in__67[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [66]),
        .D(p_0_in__67[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [66]),
        .D(p_0_in__67[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[66].rd_buf_indx_cpy_r_reg[66][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [66]),
        .D(p_0_in__67[5]),
        .Q(p_0_in73_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[442],D[434]}),
        .DIB({D[426],D[418]}),
        .DIC({D[410],D[402]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [67]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [67]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [67]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [67]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [67]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [67]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[67].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[402] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [0]),
        .Q(c0_ddr4_app_rd_data[402]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[403] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [1]),
        .Q(c0_ddr4_app_rd_data[403]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[404] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [2]),
        .Q(c0_ddr4_app_rd_data[404]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[405] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [3]),
        .Q(c0_ddr4_app_rd_data[405]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[406] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [4]),
        .Q(c0_ddr4_app_rd_data[406]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[67].app_rd_data_ns_reg[407]_0 [5]),
        .Q(c0_ddr4_app_rd_data[407]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].init_done_r[67]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [67]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[67].init_done_r[67]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].init_done_r_reg[67] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[67].init_done_r[67]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [67]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r[67][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .O(p_0_in__68[0]));
  (* SOFT_HLUTNM = "soft_lutpair3075" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r[67][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [1]),
        .O(p_0_in__68[1]));
  (* SOFT_HLUTNM = "soft_lutpair3075" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r[67][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [2]),
        .O(p_0_in__68[2]));
  (* SOFT_HLUTNM = "soft_lutpair2983" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r[67][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [3]),
        .O(p_0_in__68[3]));
  (* SOFT_HLUTNM = "soft_lutpair2983" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r[67][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [4]),
        .O(p_0_in__68[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r[67][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [67]),
        .I1(match4_170_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_170_return),
        .I4(p_0_in74_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [67]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r[67][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [4]),
        .I5(p_0_in74_in),
        .O(p_0_in__68[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [67]),
        .D(p_0_in__68[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [67]),
        .D(p_0_in__68[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [67]),
        .D(p_0_in__68[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [67]),
        .D(p_0_in__68[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [67]),
        .D(p_0_in__68[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[67].rd_buf_indx_cpy_r_reg[67][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [67]),
        .D(p_0_in__68[5]),
        .Q(p_0_in74_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[427],D[419]}),
        .DIB({D[411],D[403]}),
        .DIC({D[395],D[387]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [68]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [68]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [68]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [68]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [68]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [68]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[68].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[408] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [0]),
        .Q(c0_ddr4_app_rd_data[408]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[409] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [1]),
        .Q(c0_ddr4_app_rd_data[409]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[410] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [2]),
        .Q(c0_ddr4_app_rd_data[410]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[411] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [3]),
        .Q(c0_ddr4_app_rd_data[411]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[412] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [4]),
        .Q(c0_ddr4_app_rd_data[412]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[68].app_rd_data_ns_reg[413]_0 [5]),
        .Q(c0_ddr4_app_rd_data[413]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].init_done_r[68]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [68]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[68].init_done_r[68]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].init_done_r_reg[68] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[68].init_done_r[68]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [68]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r[68][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .O(p_0_in__69[0]));
  (* SOFT_HLUTNM = "soft_lutpair3076" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r[68][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [1]),
        .O(p_0_in__69[1]));
  (* SOFT_HLUTNM = "soft_lutpair3076" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r[68][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [2]),
        .O(p_0_in__69[2]));
  (* SOFT_HLUTNM = "soft_lutpair2984" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r[68][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [3]),
        .O(p_0_in__69[3]));
  (* SOFT_HLUTNM = "soft_lutpair2984" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r[68][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [4]),
        .O(p_0_in__69[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r[68][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [68]),
        .I1(match4_171_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_171_return),
        .I4(p_0_in75_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [68]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r[68][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [4]),
        .I5(p_0_in75_in),
        .O(p_0_in__69[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [68]),
        .D(p_0_in__69[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [68]),
        .D(p_0_in__69[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [68]),
        .D(p_0_in__69[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [68]),
        .D(p_0_in__69[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [68]),
        .D(p_0_in__69[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[68].rd_buf_indx_cpy_r_reg[68][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [68]),
        .D(p_0_in__69[5]),
        .Q(p_0_in75_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[412],D[404]}),
        .DIB({D[396],D[388]}),
        .DIC({D[443],D[435]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [69]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [69]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [69]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [69]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [69]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [69]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[69].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[414] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [0]),
        .Q(c0_ddr4_app_rd_data[414]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[415] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [1]),
        .Q(c0_ddr4_app_rd_data[415]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[416] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [2]),
        .Q(c0_ddr4_app_rd_data[416]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[417] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [3]),
        .Q(c0_ddr4_app_rd_data[417]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[418] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [4]),
        .Q(c0_ddr4_app_rd_data[418]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[69].app_rd_data_ns_reg[419]_0 [5]),
        .Q(c0_ddr4_app_rd_data[419]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].init_done_r[69]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [69]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[69].init_done_r[69]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].init_done_r_reg[69] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[69].init_done_r[69]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [69]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r[69][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .O(p_0_in__70[0]));
  (* SOFT_HLUTNM = "soft_lutpair3077" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r[69][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [1]),
        .O(p_0_in__70[1]));
  (* SOFT_HLUTNM = "soft_lutpair3077" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r[69][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [2]),
        .O(p_0_in__70[2]));
  (* SOFT_HLUTNM = "soft_lutpair2985" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r[69][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [3]),
        .O(p_0_in__70[3]));
  (* SOFT_HLUTNM = "soft_lutpair2985" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r[69][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [4]),
        .O(p_0_in__70[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r[69][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [69]),
        .I1(match4_172_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_172_return),
        .I4(p_0_in76_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [69]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r[69][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [4]),
        .I5(p_0_in76_in),
        .O(p_0_in__70[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [69]),
        .D(p_0_in__70[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [69]),
        .D(p_0_in__70[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [69]),
        .D(p_0_in__70[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [69]),
        .D(p_0_in__70[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [69]),
        .D(p_0_in__70[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[69].rd_buf_indx_cpy_r_reg[69][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [69]),
        .D(p_0_in__70[5]),
        .Q(p_0_in76_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[13],D[5]}),
        .DIB({D[60],D[52]}),
        .DIC({D[44],D[36]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [6]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [6]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [6]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [6]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [6]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [6]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[6].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[36] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [0]),
        .Q(c0_ddr4_app_rd_data[36]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[37] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [1]),
        .Q(c0_ddr4_app_rd_data[37]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[38] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [2]),
        .Q(c0_ddr4_app_rd_data[38]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[39] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [3]),
        .Q(c0_ddr4_app_rd_data[39]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[40] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [4]),
        .Q(c0_ddr4_app_rd_data[40]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[6].app_rd_data_ns_reg[41]_0 [5]),
        .Q(c0_ddr4_app_rd_data[41]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].init_done_r[6]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [6]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[6].init_done_r[6]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].init_done_r_reg[6] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[6].init_done_r[6]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [6]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r[6][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .O(p_0_in__7[0]));
  (* SOFT_HLUTNM = "soft_lutpair3014" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r[6][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [1]),
        .O(p_0_in__7[1]));
  (* SOFT_HLUTNM = "soft_lutpair3014" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r[6][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [2]),
        .O(p_0_in__7[2]));
  (* SOFT_HLUTNM = "soft_lutpair2922" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r[6][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [3]),
        .O(p_0_in__7[3]));
  (* SOFT_HLUTNM = "soft_lutpair2922" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r[6][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [4]),
        .O(p_0_in__7[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r[6][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [6]),
        .I1(match4_19_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_19_return),
        .I4(p_0_in13_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [6]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r[6][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [4]),
        .I5(p_0_in13_in),
        .O(p_0_in__7[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [6]),
        .D(p_0_in__7[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [6]),
        .D(p_0_in__7[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [6]),
        .D(p_0_in__7[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [6]),
        .D(p_0_in__7[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [6]),
        .D(p_0_in__7[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[6].rd_buf_indx_cpy_r_reg[6][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [6]),
        .D(p_0_in__7[5]),
        .Q(p_0_in13_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[397],D[389]}),
        .DIB({D[444],D[436]}),
        .DIC({D[428],D[420]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [70]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [70]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [70]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [70]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [70]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [70]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[70].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[420] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [0]),
        .Q(c0_ddr4_app_rd_data[420]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[421] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [1]),
        .Q(c0_ddr4_app_rd_data[421]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[422] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [2]),
        .Q(c0_ddr4_app_rd_data[422]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[423] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [3]),
        .Q(c0_ddr4_app_rd_data[423]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[424] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [4]),
        .Q(c0_ddr4_app_rd_data[424]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[70].app_rd_data_ns_reg[425]_0 [5]),
        .Q(c0_ddr4_app_rd_data[425]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].init_done_r[70]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [70]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[70].init_done_r[70]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].init_done_r_reg[70] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[70].init_done_r[70]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [70]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r[70][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .O(p_0_in__71[0]));
  (* SOFT_HLUTNM = "soft_lutpair3078" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r[70][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [1]),
        .O(p_0_in__71[1]));
  (* SOFT_HLUTNM = "soft_lutpair3078" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r[70][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [2]),
        .O(p_0_in__71[2]));
  (* SOFT_HLUTNM = "soft_lutpair2986" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r[70][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [3]),
        .O(p_0_in__71[3]));
  (* SOFT_HLUTNM = "soft_lutpair2986" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r[70][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [4]),
        .O(p_0_in__71[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r[70][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [70]),
        .I1(match4_173_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_173_return),
        .I4(p_0_in77_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [70]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r[70][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [4]),
        .I5(p_0_in77_in),
        .O(p_0_in__71[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [70]),
        .D(p_0_in__71[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [70]),
        .D(p_0_in__71[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [70]),
        .D(p_0_in__71[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [70]),
        .D(p_0_in__71[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [70]),
        .D(p_0_in__71[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[70].rd_buf_indx_cpy_r_reg[70][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [70]),
        .D(p_0_in__71[5]),
        .Q(p_0_in77_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[445],D[437]}),
        .DIB({D[429],D[421]}),
        .DIC({D[413],D[405]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [71]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [71]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [71]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [71]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [71]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [71]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[71].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[426] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [0]),
        .Q(c0_ddr4_app_rd_data[426]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[427] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [1]),
        .Q(c0_ddr4_app_rd_data[427]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[428] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [2]),
        .Q(c0_ddr4_app_rd_data[428]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[429] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [3]),
        .Q(c0_ddr4_app_rd_data[429]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[430] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [4]),
        .Q(c0_ddr4_app_rd_data[430]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[71].app_rd_data_ns_reg[431]_0 [5]),
        .Q(c0_ddr4_app_rd_data[431]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].init_done_r[71]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [71]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[71].init_done_r[71]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].init_done_r_reg[71] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[71].init_done_r[71]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [71]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r[71][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .O(p_0_in__72[0]));
  (* SOFT_HLUTNM = "soft_lutpair3079" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r[71][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [1]),
        .O(p_0_in__72[1]));
  (* SOFT_HLUTNM = "soft_lutpair3079" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r[71][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [2]),
        .O(p_0_in__72[2]));
  (* SOFT_HLUTNM = "soft_lutpair2987" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r[71][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [3]),
        .O(p_0_in__72[3]));
  (* SOFT_HLUTNM = "soft_lutpair2987" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r[71][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [4]),
        .O(p_0_in__72[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r[71][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [71]),
        .I1(match4_174_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_174_return),
        .I4(p_0_in78_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [71]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r[71][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [4]),
        .I5(p_0_in78_in),
        .O(p_0_in__72[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [71]),
        .D(p_0_in__72[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [71]),
        .D(p_0_in__72[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [71]),
        .D(p_0_in__72[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [71]),
        .D(p_0_in__72[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [71]),
        .D(p_0_in__72[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[71].rd_buf_indx_cpy_r_reg[71][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [71]),
        .D(p_0_in__72[5]),
        .Q(p_0_in78_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[430],D[422]}),
        .DIB({D[414],D[406]}),
        .DIC({D[398],D[390]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [72]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [72]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [72]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [72]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [72]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [72]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[72].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[432] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [0]),
        .Q(c0_ddr4_app_rd_data[432]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[433] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [1]),
        .Q(c0_ddr4_app_rd_data[433]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[434] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [2]),
        .Q(c0_ddr4_app_rd_data[434]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[435] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [3]),
        .Q(c0_ddr4_app_rd_data[435]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[436] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [4]),
        .Q(c0_ddr4_app_rd_data[436]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[72].app_rd_data_ns_reg[437]_0 [5]),
        .Q(c0_ddr4_app_rd_data[437]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].init_done_r[72]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [72]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[72].init_done_r[72]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].init_done_r_reg[72] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[72].init_done_r[72]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [72]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r[72][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .O(p_0_in__73[0]));
  (* SOFT_HLUTNM = "soft_lutpair3080" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r[72][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [1]),
        .O(p_0_in__73[1]));
  (* SOFT_HLUTNM = "soft_lutpair3080" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r[72][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [2]),
        .O(p_0_in__73[2]));
  (* SOFT_HLUTNM = "soft_lutpair2988" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r[72][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [3]),
        .O(p_0_in__73[3]));
  (* SOFT_HLUTNM = "soft_lutpair2988" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r[72][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [4]),
        .O(p_0_in__73[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r[72][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [72]),
        .I1(match4_175_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_175_return),
        .I4(p_0_in79_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [72]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r[72][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [4]),
        .I5(p_0_in79_in),
        .O(p_0_in__73[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [72]),
        .D(p_0_in__73[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [72]),
        .D(p_0_in__73[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [72]),
        .D(p_0_in__73[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [72]),
        .D(p_0_in__73[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [72]),
        .D(p_0_in__73[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[72].rd_buf_indx_cpy_r_reg[72][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [72]),
        .D(p_0_in__73[5]),
        .Q(p_0_in79_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[415],D[407]}),
        .DIB({D[399],D[391]}),
        .DIC({D[446],D[438]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [73]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [73]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [73]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [73]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [73]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [73]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[73].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[438] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [0]),
        .Q(c0_ddr4_app_rd_data[438]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[439] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [1]),
        .Q(c0_ddr4_app_rd_data[439]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[440] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [2]),
        .Q(c0_ddr4_app_rd_data[440]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[441] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [3]),
        .Q(c0_ddr4_app_rd_data[441]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[442] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [4]),
        .Q(c0_ddr4_app_rd_data[442]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[73].app_rd_data_ns_reg[443]_0 [5]),
        .Q(c0_ddr4_app_rd_data[443]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].init_done_r[73]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [73]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[73].init_done_r[73]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].init_done_r_reg[73] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[73].init_done_r[73]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [73]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r[73][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .O(p_0_in__74[0]));
  (* SOFT_HLUTNM = "soft_lutpair3081" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r[73][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [1]),
        .O(p_0_in__74[1]));
  (* SOFT_HLUTNM = "soft_lutpair3081" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r[73][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [2]),
        .O(p_0_in__74[2]));
  (* SOFT_HLUTNM = "soft_lutpair2989" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r[73][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [3]),
        .O(p_0_in__74[3]));
  (* SOFT_HLUTNM = "soft_lutpair2989" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r[73][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [4]),
        .O(p_0_in__74[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r[73][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [73]),
        .I1(match4_176_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_176_return),
        .I4(p_0_in80_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [73]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r[73][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [4]),
        .I5(p_0_in80_in),
        .O(p_0_in__74[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [73]),
        .D(p_0_in__74[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [73]),
        .D(p_0_in__74[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [73]),
        .D(p_0_in__74[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [73]),
        .D(p_0_in__74[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [73]),
        .D(p_0_in__74[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[73].rd_buf_indx_cpy_r_reg[73][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [73]),
        .D(p_0_in__74[5]),
        .Q(p_0_in80_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[456],D[448]}),
        .DIB({D[447],D[439]}),
        .DIC({D[431],D[423]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [74]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [74]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [74]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [74]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [74]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [74]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[74].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[444] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [0]),
        .Q(c0_ddr4_app_rd_data[444]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[445] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [1]),
        .Q(c0_ddr4_app_rd_data[445]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[446] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [2]),
        .Q(c0_ddr4_app_rd_data[446]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[447] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [3]),
        .Q(c0_ddr4_app_rd_data[447]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[448] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [4]),
        .Q(c0_ddr4_app_rd_data[448]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[74].app_rd_data_ns_reg[449]_0 [5]),
        .Q(c0_ddr4_app_rd_data[449]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].init_done_r[74]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [74]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[74].init_done_r[74]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].init_done_r_reg[74] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[74].init_done_r[74]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [74]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r[74][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .O(p_0_in__75[0]));
  (* SOFT_HLUTNM = "soft_lutpair3082" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r[74][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [1]),
        .O(p_0_in__75[1]));
  (* SOFT_HLUTNM = "soft_lutpair3082" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r[74][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [2]),
        .O(p_0_in__75[2]));
  (* SOFT_HLUTNM = "soft_lutpair2990" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r[74][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [3]),
        .O(p_0_in__75[3]));
  (* SOFT_HLUTNM = "soft_lutpair2990" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r[74][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [4]),
        .O(p_0_in__75[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r[74][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [74]),
        .I1(match4_177_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_177_return),
        .I4(p_0_in81_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [74]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r[74][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [4]),
        .I5(p_0_in81_in),
        .O(p_0_in__75[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [74]),
        .D(p_0_in__75[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [74]),
        .D(p_0_in__75[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [74]),
        .D(p_0_in__75[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [74]),
        .D(p_0_in__75[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [74]),
        .D(p_0_in__75[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[74].rd_buf_indx_cpy_r_reg[74][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [74]),
        .D(p_0_in__75[5]),
        .Q(p_0_in81_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[504],D[496]}),
        .DIB({D[488],D[480]}),
        .DIC({D[472],D[464]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [75]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [75]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [75]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [75]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [75]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [75]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[75].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[450] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [0]),
        .Q(c0_ddr4_app_rd_data[450]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[451] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [1]),
        .Q(c0_ddr4_app_rd_data[451]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[452] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [2]),
        .Q(c0_ddr4_app_rd_data[452]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[453] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [3]),
        .Q(c0_ddr4_app_rd_data[453]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[454] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [4]),
        .Q(c0_ddr4_app_rd_data[454]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[75].app_rd_data_ns_reg[455]_0 [5]),
        .Q(c0_ddr4_app_rd_data[455]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].init_done_r[75]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [75]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[75].init_done_r[75]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].init_done_r_reg[75] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[75].init_done_r[75]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [75]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r[75][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .O(p_0_in__76[0]));
  (* SOFT_HLUTNM = "soft_lutpair3083" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r[75][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [1]),
        .O(p_0_in__76[1]));
  (* SOFT_HLUTNM = "soft_lutpair3083" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r[75][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [2]),
        .O(p_0_in__76[2]));
  (* SOFT_HLUTNM = "soft_lutpair2991" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r[75][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [3]),
        .O(p_0_in__76[3]));
  (* SOFT_HLUTNM = "soft_lutpair2991" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r[75][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [4]),
        .O(p_0_in__76[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r[75][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [75]),
        .I1(match4_178_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_178_return),
        .I4(p_0_in82_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [75]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r[75][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [4]),
        .I5(p_0_in82_in),
        .O(p_0_in__76[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [75]),
        .D(p_0_in__76[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [75]),
        .D(p_0_in__76[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [75]),
        .D(p_0_in__76[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [75]),
        .D(p_0_in__76[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [75]),
        .D(p_0_in__76[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[75].rd_buf_indx_cpy_r_reg[75][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [75]),
        .D(p_0_in__76[5]),
        .Q(p_0_in82_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[489],D[481]}),
        .DIB({D[473],D[465]}),
        .DIC({D[457],D[449]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [76]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [76]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [76]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [76]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [76]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [76]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[76].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[456] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [0]),
        .Q(c0_ddr4_app_rd_data[456]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[457] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [1]),
        .Q(c0_ddr4_app_rd_data[457]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[458] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [2]),
        .Q(c0_ddr4_app_rd_data[458]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[459] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [3]),
        .Q(c0_ddr4_app_rd_data[459]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[460] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [4]),
        .Q(c0_ddr4_app_rd_data[460]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[76].app_rd_data_ns_reg[461]_0 [5]),
        .Q(c0_ddr4_app_rd_data[461]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].init_done_r[76]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [76]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[76].init_done_r[76]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].init_done_r_reg[76] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[76].init_done_r[76]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [76]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r[76][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .O(p_0_in__77[0]));
  (* SOFT_HLUTNM = "soft_lutpair3084" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r[76][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [1]),
        .O(p_0_in__77[1]));
  (* SOFT_HLUTNM = "soft_lutpair3084" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r[76][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [2]),
        .O(p_0_in__77[2]));
  (* SOFT_HLUTNM = "soft_lutpair2992" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r[76][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [3]),
        .O(p_0_in__77[3]));
  (* SOFT_HLUTNM = "soft_lutpair2992" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r[76][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [4]),
        .O(p_0_in__77[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r[76][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [76]),
        .I1(match4_179_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_179_return),
        .I4(p_0_in83_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [76]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r[76][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [4]),
        .I5(p_0_in83_in),
        .O(p_0_in__77[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [76]),
        .D(p_0_in__77[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [76]),
        .D(p_0_in__77[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [76]),
        .D(p_0_in__77[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [76]),
        .D(p_0_in__77[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [76]),
        .D(p_0_in__77[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[76].rd_buf_indx_cpy_r_reg[76][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [76]),
        .D(p_0_in__77[5]),
        .Q(p_0_in83_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[474],D[466]}),
        .DIB({D[458],D[450]}),
        .DIC({D[505],D[497]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [77]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [77]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [77]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [77]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [77]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [77]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[77].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[462] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [0]),
        .Q(c0_ddr4_app_rd_data[462]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[463] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [1]),
        .Q(c0_ddr4_app_rd_data[463]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[464] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [2]),
        .Q(c0_ddr4_app_rd_data[464]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[465] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [3]),
        .Q(c0_ddr4_app_rd_data[465]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[466] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [4]),
        .Q(c0_ddr4_app_rd_data[466]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[77].app_rd_data_ns_reg[467]_0 [5]),
        .Q(c0_ddr4_app_rd_data[467]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].init_done_r[77]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [77]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[77].init_done_r[77]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].init_done_r_reg[77] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[77].init_done_r[77]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [77]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r[77][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .O(p_0_in__78[0]));
  (* SOFT_HLUTNM = "soft_lutpair3085" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r[77][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [1]),
        .O(p_0_in__78[1]));
  (* SOFT_HLUTNM = "soft_lutpair3085" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r[77][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [2]),
        .O(p_0_in__78[2]));
  (* SOFT_HLUTNM = "soft_lutpair2993" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r[77][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [3]),
        .O(p_0_in__78[3]));
  (* SOFT_HLUTNM = "soft_lutpair2993" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r[77][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [4]),
        .O(p_0_in__78[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r[77][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [77]),
        .I1(match4_180_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_180_return),
        .I4(p_0_in84_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [77]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r[77][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [4]),
        .I5(p_0_in84_in),
        .O(p_0_in__78[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [77]),
        .D(p_0_in__78[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [77]),
        .D(p_0_in__78[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [77]),
        .D(p_0_in__78[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [77]),
        .D(p_0_in__78[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [77]),
        .D(p_0_in__78[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[77].rd_buf_indx_cpy_r_reg[77][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [77]),
        .D(p_0_in__78[5]),
        .Q(p_0_in84_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[459],D[451]}),
        .DIB({D[506],D[498]}),
        .DIC({D[490],D[482]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [78]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [78]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [78]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [78]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [78]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [78]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[78].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[468] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [0]),
        .Q(c0_ddr4_app_rd_data[468]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[469] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [1]),
        .Q(c0_ddr4_app_rd_data[469]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[470] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [2]),
        .Q(c0_ddr4_app_rd_data[470]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[471] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [3]),
        .Q(c0_ddr4_app_rd_data[471]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[472] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [4]),
        .Q(c0_ddr4_app_rd_data[472]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[78].app_rd_data_ns_reg[473]_0 [5]),
        .Q(c0_ddr4_app_rd_data[473]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].init_done_r[78]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [78]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[78].init_done_r[78]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].init_done_r_reg[78] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[78].init_done_r[78]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [78]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r[78][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .O(p_0_in__79[0]));
  (* SOFT_HLUTNM = "soft_lutpair3086" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r[78][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [1]),
        .O(p_0_in__79[1]));
  (* SOFT_HLUTNM = "soft_lutpair3086" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r[78][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [2]),
        .O(p_0_in__79[2]));
  (* SOFT_HLUTNM = "soft_lutpair2994" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r[78][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [3]),
        .O(p_0_in__79[3]));
  (* SOFT_HLUTNM = "soft_lutpair2994" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r[78][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [4]),
        .O(p_0_in__79[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r[78][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [78]),
        .I1(match4_181_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_181_return),
        .I4(p_0_in85_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [78]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r[78][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [4]),
        .I5(p_0_in85_in),
        .O(p_0_in__79[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [78]),
        .D(p_0_in__79[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [78]),
        .D(p_0_in__79[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [78]),
        .D(p_0_in__79[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [78]),
        .D(p_0_in__79[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [78]),
        .D(p_0_in__79[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[78].rd_buf_indx_cpy_r_reg[78][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [78]),
        .D(p_0_in__79[5]),
        .Q(p_0_in85_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[507],D[499]}),
        .DIB({D[491],D[483]}),
        .DIC({D[475],D[467]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [79]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [79]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [79]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [79]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [79]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [79]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[79].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[474] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [0]),
        .Q(c0_ddr4_app_rd_data[474]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[475] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [1]),
        .Q(c0_ddr4_app_rd_data[475]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[476] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [2]),
        .Q(c0_ddr4_app_rd_data[476]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[477] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [3]),
        .Q(c0_ddr4_app_rd_data[477]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[478] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [4]),
        .Q(c0_ddr4_app_rd_data[478]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[79].app_rd_data_ns_reg[479]_0 [5]),
        .Q(c0_ddr4_app_rd_data[479]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].init_done_r[79]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [79]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[79].init_done_r[79]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].init_done_r_reg[79] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[79].init_done_r[79]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [79]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r[79][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .O(p_0_in__80[0]));
  (* SOFT_HLUTNM = "soft_lutpair3087" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r[79][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [1]),
        .O(p_0_in__80[1]));
  (* SOFT_HLUTNM = "soft_lutpair3087" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r[79][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [2]),
        .O(p_0_in__80[2]));
  (* SOFT_HLUTNM = "soft_lutpair2995" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r[79][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [3]),
        .O(p_0_in__80[3]));
  (* SOFT_HLUTNM = "soft_lutpair2995" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r[79][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [4]),
        .O(p_0_in__80[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r[79][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [79]),
        .I1(match4_182_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_182_return),
        .I4(p_0_in86_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [79]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r[79][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [4]),
        .I5(p_0_in86_in),
        .O(p_0_in__80[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [79]),
        .D(p_0_in__80[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [79]),
        .D(p_0_in__80[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [79]),
        .D(p_0_in__80[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [79]),
        .D(p_0_in__80[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [79]),
        .D(p_0_in__80[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[79].rd_buf_indx_cpy_r_reg[79][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [79]),
        .D(p_0_in__80[5]),
        .Q(p_0_in86_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[61],D[53]}),
        .DIB({D[45],D[37]}),
        .DIC({D[29],D[21]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [7]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [7]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [7]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [7]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [7]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [7]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[7].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[42] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [0]),
        .Q(c0_ddr4_app_rd_data[42]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[43] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [1]),
        .Q(c0_ddr4_app_rd_data[43]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[44] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [2]),
        .Q(c0_ddr4_app_rd_data[44]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[45] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [3]),
        .Q(c0_ddr4_app_rd_data[45]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[46] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [4]),
        .Q(c0_ddr4_app_rd_data[46]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[7].app_rd_data_ns_reg[47]_0 [5]),
        .Q(c0_ddr4_app_rd_data[47]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].init_done_r[7]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [7]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[7].init_done_r[7]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].init_done_r_reg[7] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[7].init_done_r[7]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [7]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r[7][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .O(p_0_in__8[0]));
  (* SOFT_HLUTNM = "soft_lutpair3015" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r[7][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [1]),
        .O(p_0_in__8[1]));
  (* SOFT_HLUTNM = "soft_lutpair3015" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r[7][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [2]),
        .O(p_0_in__8[2]));
  (* SOFT_HLUTNM = "soft_lutpair2923" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r[7][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [3]),
        .O(p_0_in__8[3]));
  (* SOFT_HLUTNM = "soft_lutpair2923" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r[7][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [4]),
        .O(p_0_in__8[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r[7][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [7]),
        .I1(match4_110_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_110_return),
        .I4(p_0_in14_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [7]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r[7][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [4]),
        .I5(p_0_in14_in),
        .O(p_0_in__8[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [7]),
        .D(p_0_in__8[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [7]),
        .D(p_0_in__8[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [7]),
        .D(p_0_in__8[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [7]),
        .D(p_0_in__8[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [7]),
        .D(p_0_in__8[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[7].rd_buf_indx_cpy_r_reg[7][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [7]),
        .D(p_0_in__8[5]),
        .Q(p_0_in14_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[492],D[484]}),
        .DIB({D[476],D[468]}),
        .DIC({D[460],D[452]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [80]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [80]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [80]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [80]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [80]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [80]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[80].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[480] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [0]),
        .Q(c0_ddr4_app_rd_data[480]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[481] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [1]),
        .Q(c0_ddr4_app_rd_data[481]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[482] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [2]),
        .Q(c0_ddr4_app_rd_data[482]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[483] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [3]),
        .Q(c0_ddr4_app_rd_data[483]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[484] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [4]),
        .Q(c0_ddr4_app_rd_data[484]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[80].app_rd_data_ns_reg[485]_0 [5]),
        .Q(c0_ddr4_app_rd_data[485]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].init_done_r[80]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [80]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[80].init_done_r[80]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].init_done_r_reg[80] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[80].init_done_r[80]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [80]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r[80][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .O(p_0_in__81[0]));
  (* SOFT_HLUTNM = "soft_lutpair3088" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r[80][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [1]),
        .O(p_0_in__81[1]));
  (* SOFT_HLUTNM = "soft_lutpair3088" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r[80][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [2]),
        .O(p_0_in__81[2]));
  (* SOFT_HLUTNM = "soft_lutpair2996" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r[80][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [3]),
        .O(p_0_in__81[3]));
  (* SOFT_HLUTNM = "soft_lutpair2996" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r[80][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [4]),
        .O(p_0_in__81[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r[80][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [80]),
        .I1(match4_183_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_183_return),
        .I4(p_0_in87_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [80]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r[80][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [4]),
        .I5(p_0_in87_in),
        .O(p_0_in__81[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [80]),
        .D(p_0_in__81[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [80]),
        .D(p_0_in__81[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [80]),
        .D(p_0_in__81[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [80]),
        .D(p_0_in__81[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [80]),
        .D(p_0_in__81[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[80].rd_buf_indx_cpy_r_reg[80][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [80]),
        .D(p_0_in__81[5]),
        .Q(p_0_in87_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[477],D[469]}),
        .DIB({D[461],D[453]}),
        .DIC({D[508],D[500]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [81]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [81]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [81]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [81]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [81]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [81]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[81].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[486] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [0]),
        .Q(c0_ddr4_app_rd_data[486]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[487] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [1]),
        .Q(c0_ddr4_app_rd_data[487]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[488] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [2]),
        .Q(c0_ddr4_app_rd_data[488]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[489] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [3]),
        .Q(c0_ddr4_app_rd_data[489]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[490] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [4]),
        .Q(c0_ddr4_app_rd_data[490]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[81].app_rd_data_ns_reg[491]_0 [5]),
        .Q(c0_ddr4_app_rd_data[491]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].init_done_r[81]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [81]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[81].init_done_r[81]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].init_done_r_reg[81] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[81].init_done_r[81]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [81]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r[81][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .O(p_0_in__82[0]));
  (* SOFT_HLUTNM = "soft_lutpair3089" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r[81][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [1]),
        .O(p_0_in__82[1]));
  (* SOFT_HLUTNM = "soft_lutpair3089" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r[81][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [2]),
        .O(p_0_in__82[2]));
  (* SOFT_HLUTNM = "soft_lutpair2997" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r[81][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [3]),
        .O(p_0_in__82[3]));
  (* SOFT_HLUTNM = "soft_lutpair2997" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r[81][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [4]),
        .O(p_0_in__82[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r[81][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [81]),
        .I1(match4_184_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_184_return),
        .I4(p_0_in88_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [81]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r[81][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [4]),
        .I5(p_0_in88_in),
        .O(p_0_in__82[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [81]),
        .D(p_0_in__82[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [81]),
        .D(p_0_in__82[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [81]),
        .D(p_0_in__82[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [81]),
        .D(p_0_in__82[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [81]),
        .D(p_0_in__82[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[81].rd_buf_indx_cpy_r_reg[81][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [81]),
        .D(p_0_in__82[5]),
        .Q(p_0_in88_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[462],D[454]}),
        .DIB({D[509],D[501]}),
        .DIC({D[493],D[485]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [82]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [82]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [82]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [82]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [82]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [82]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[82].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[492] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [0]),
        .Q(c0_ddr4_app_rd_data[492]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[493] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [1]),
        .Q(c0_ddr4_app_rd_data[493]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[494] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [2]),
        .Q(c0_ddr4_app_rd_data[494]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[495] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [3]),
        .Q(c0_ddr4_app_rd_data[495]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[496] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [4]),
        .Q(c0_ddr4_app_rd_data[496]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[82].app_rd_data_ns_reg[497]_0 [5]),
        .Q(c0_ddr4_app_rd_data[497]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].init_done_r[82]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [82]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[82].init_done_r[82]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].init_done_r_reg[82] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[82].init_done_r[82]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [82]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r[82][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .O(p_0_in__83[0]));
  (* SOFT_HLUTNM = "soft_lutpair3090" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r[82][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [1]),
        .O(p_0_in__83[1]));
  (* SOFT_HLUTNM = "soft_lutpair3090" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r[82][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [2]),
        .O(p_0_in__83[2]));
  (* SOFT_HLUTNM = "soft_lutpair2998" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r[82][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [3]),
        .O(p_0_in__83[3]));
  (* SOFT_HLUTNM = "soft_lutpair2998" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r[82][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [4]),
        .O(p_0_in__83[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r[82][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [82]),
        .I1(match4_185_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_185_return),
        .I4(p_0_in89_in),
        .I5(\not_strict_mode.rd_status[5]_170 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [82]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r[82][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [4]),
        .I5(p_0_in89_in),
        .O(p_0_in__83[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [82]),
        .D(p_0_in__83[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [82]),
        .D(p_0_in__83[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [82]),
        .D(p_0_in__83[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [82]),
        .D(p_0_in__83[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [82]),
        .D(p_0_in__83[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[82].rd_buf_indx_cpy_r_reg[82][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [82]),
        .D(p_0_in__83[5]),
        .Q(p_0_in89_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[510],D[502]}),
        .DIB({D[494],D[486]}),
        .DIC({D[478],D[470]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [83]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [83]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [83]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [83]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [83]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [83]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[83].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[498] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [0]),
        .Q(c0_ddr4_app_rd_data[498]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[499] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [1]),
        .Q(c0_ddr4_app_rd_data[499]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[500] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [2]),
        .Q(c0_ddr4_app_rd_data[500]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[501] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [3]),
        .Q(c0_ddr4_app_rd_data[501]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[502] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [4]),
        .Q(c0_ddr4_app_rd_data[502]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[83].app_rd_data_ns_reg[503]_0 [5]),
        .Q(c0_ddr4_app_rd_data[503]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].init_done_r[83]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [83]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[83].init_done_r[83]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].init_done_r_reg[83] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[83].init_done_r[83]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [83]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r[83][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .O(p_0_in__84[0]));
  (* SOFT_HLUTNM = "soft_lutpair3091" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r[83][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [1]),
        .O(p_0_in__84[1]));
  (* SOFT_HLUTNM = "soft_lutpair3091" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r[83][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [2]),
        .O(p_0_in__84[2]));
  (* SOFT_HLUTNM = "soft_lutpair2999" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r[83][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [3]),
        .O(p_0_in__84[3]));
  (* SOFT_HLUTNM = "soft_lutpair2999" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r[83][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [4]),
        .O(p_0_in__84[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r[83][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [83]),
        .I1(match4_186_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_186_return),
        .I4(p_0_in90_in),
        .I5(\not_strict_mode.rd_status[6]_173 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [83]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r[83][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [4]),
        .I5(p_0_in90_in),
        .O(p_0_in__84[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [83]),
        .D(p_0_in__84[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [83]),
        .D(p_0_in__84[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [83]),
        .D(p_0_in__84[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [83]),
        .D(p_0_in__84[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [83]),
        .D(p_0_in__84[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[83].rd_buf_indx_cpy_r_reg[83][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [83]),
        .D(p_0_in__84[5]),
        .Q(p_0_in90_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[495],D[487]}),
        .DIB({D[479],D[471]}),
        .DIC({D[463],D[455]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [84]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [84]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [84]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [84]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [84]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [84]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[84].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[504] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [0]),
        .Q(c0_ddr4_app_rd_data[504]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[505] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [1]),
        .Q(c0_ddr4_app_rd_data[505]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[506] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [2]),
        .Q(c0_ddr4_app_rd_data[506]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[507] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [3]),
        .Q(c0_ddr4_app_rd_data[507]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[508] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [4]),
        .Q(c0_ddr4_app_rd_data[508]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[84].app_rd_data_ns_reg[509]_0 [5]),
        .Q(c0_ddr4_app_rd_data[509]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].init_done_r[84]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [84]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[84].init_done_r[84]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].init_done_r_reg[84] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[84].init_done_r[84]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [84]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r[84][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .O(p_0_in__85[0]));
  (* SOFT_HLUTNM = "soft_lutpair3092" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r[84][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [1]),
        .O(p_0_in__85[1]));
  (* SOFT_HLUTNM = "soft_lutpair3092" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r[84][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [2]),
        .O(p_0_in__85[2]));
  (* SOFT_HLUTNM = "soft_lutpair3000" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r[84][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [3]),
        .O(p_0_in__85[3]));
  (* SOFT_HLUTNM = "soft_lutpair3000" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r[84][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [4]),
        .O(p_0_in__85[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r[84][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [84]),
        .I1(match4_187_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_187_return),
        .I4(p_0_in91_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [84]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r[84][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [4]),
        .I5(p_0_in91_in),
        .O(p_0_in__85[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [84]),
        .D(p_0_in__85[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [84]),
        .D(p_0_in__85[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [84]),
        .D(p_0_in__85[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [84]),
        .D(p_0_in__85[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [84]),
        .D(p_0_in__85[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[84].rd_buf_indx_cpy_r_reg[84][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [84]),
        .D(p_0_in__85[5]),
        .Q(p_0_in91_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0 
       (.ADDRA(ADDRA0),
        .ADDRB(ADDRA0),
        .ADDRC(ADDRA0),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({D[511],D[503]}),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOB_UNCONNECTED [1:0]),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_0 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [85]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [85]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [4]),
        .O(ADDRA0[4]));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [85]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [3]),
        .O(ADDRA0[3]));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [85]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [2]),
        .O(ADDRA0[2]));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [85]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [1]),
        .O(ADDRA0[1]));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [85]),
        .O(ADDRA0[0]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[510] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 [0]),
        .Q(c0_ddr4_app_rd_data[510]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[85].app_rd_data_ns_reg[511]_0 [1]),
        .Q(c0_ddr4_app_rd_data[511]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r[85]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [85]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r[85]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r_reg[85] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[85].init_done_r[85]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [85]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r[85][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .O(p_0_in__86[0]));
  (* SOFT_HLUTNM = "soft_lutpair3093" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r[85][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [1]),
        .O(p_0_in__86[1]));
  (* SOFT_HLUTNM = "soft_lutpair3093" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r[85][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [2]),
        .O(p_0_in__86[2]));
  (* SOFT_HLUTNM = "soft_lutpair3001" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r[85][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [3]),
        .O(p_0_in__86[3]));
  (* SOFT_HLUTNM = "soft_lutpair3001" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r[85][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [4]),
        .O(p_0_in__86[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r[85][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [85]),
        .I1(match4_188_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_188_return),
        .I4(p_0_in92_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [85]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r[85][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [4]),
        .I5(p_0_in92_in),
        .O(p_0_in__86[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [85]),
        .D(p_0_in__86[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [85]),
        .D(p_0_in__86[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [85]),
        .D(p_0_in__86[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [85]),
        .D(p_0_in__86[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [85]),
        .D(p_0_in__86[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[85].rd_buf_indx_cpy_r_reg[85][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [85]),
        .D(p_0_in__86[5]),
        .Q(p_0_in92_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5_n_0 }),
        .ADDRD({\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 ,ADDRD[2:0]}),
        .DIA({D[46],D[38]}),
        .DIB({D[30],D[22]}),
        .DIC({D[14],D[6]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [8]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [8]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [8]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [8]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [8]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [8]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[8].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[48] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [0]),
        .Q(c0_ddr4_app_rd_data[48]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[49] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [1]),
        .Q(c0_ddr4_app_rd_data[49]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[50] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [2]),
        .Q(c0_ddr4_app_rd_data[50]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[51] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [3]),
        .Q(c0_ddr4_app_rd_data[51]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[52] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [4]),
        .Q(c0_ddr4_app_rd_data[52]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[8].app_rd_data_ns_reg[53]_0 [5]),
        .Q(c0_ddr4_app_rd_data[53]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].init_done_r[8]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [8]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[8].init_done_r[8]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].init_done_r_reg[8] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[8].init_done_r[8]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [8]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r[8][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .O(p_0_in__9[0]));
  (* SOFT_HLUTNM = "soft_lutpair3016" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r[8][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [1]),
        .O(p_0_in__9[1]));
  (* SOFT_HLUTNM = "soft_lutpair3016" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r[8][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [2]),
        .O(p_0_in__9[2]));
  (* SOFT_HLUTNM = "soft_lutpair2924" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r[8][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [3]),
        .O(p_0_in__9[3]));
  (* SOFT_HLUTNM = "soft_lutpair2924" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r[8][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [4]),
        .O(p_0_in__9[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r[8][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [8]),
        .I1(match4_111_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_111_return),
        .I4(p_0_in15_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [8]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r[8][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [4]),
        .I5(p_0_in15_in),
        .O(p_0_in__9[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [8]),
        .D(p_0_in__9[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [8]),
        .D(p_0_in__9[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [8]),
        .D(p_0_in__9[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [8]),
        .D(p_0_in__9[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [8]),
        .D(p_0_in__9[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[8].rd_buf_indx_cpy_r_reg[8][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [8]),
        .D(p_0_in__9[5]),
        .Q(p_0_in15_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0 
       (.ADDRA({\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5_n_0 }),
        .ADDRB({\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5_n_0 }),
        .ADDRC({\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4_n_0 ,\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5_n_0 }),
        .ADDRD(ADDRD),
        .DIA({D[31],D[23]}),
        .DIB({D[15],D[7]}),
        .DIC({D[62],D[54]}),
        .DID({1'b0,1'b0}),
        .DOA(\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_0 ),
        .DOB(\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_1 ),
        .DOC(\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_2 ),
        .DOD(\NLW_not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf.rd_buf_we [9]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [9]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [1]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [4]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.single_data_buf [9]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [3]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3 
       (.I0(\not_strict_mode.rd_buf.single_data_buf [9]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [2]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [9]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [1]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.single_data_buf [9]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[9].RAM32M0_i_5_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[54] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [0]),
        .Q(c0_ddr4_app_rd_data[54]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[55] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [1]),
        .Q(c0_ddr4_app_rd_data[55]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[56] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [2]),
        .Q(c0_ddr4_app_rd_data[56]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[57] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [3]),
        .Q(c0_ddr4_app_rd_data[57]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[58] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [4]),
        .Q(c0_ddr4_app_rd_data[58]),
        .R(1'b0));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[9].app_rd_data_ns_reg[59]_0 [5]),
        .Q(c0_ddr4_app_rd_data[59]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].init_done_r[9]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [4]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [3]),
        .I5(\not_strict_mode.rd_buf.init_done_r [9]),
        .O(\not_strict_mode.rd_buf.rd_buffer_ram[9].init_done_r[9]_i_1_n_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].init_done_r_reg[9] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.rd_buf.rd_buffer_ram[9].init_done_r[9]_i_1_n_0 ),
        .Q(\not_strict_mode.rd_buf.init_done_r [9]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r[9][0]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .O(p_0_in__10[0]));
  (* SOFT_HLUTNM = "soft_lutpair3017" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r[9][1]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [1]),
        .O(p_0_in__10[1]));
  (* SOFT_HLUTNM = "soft_lutpair3017" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r[9][2]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [2]),
        .O(p_0_in__10[2]));
  (* SOFT_HLUTNM = "soft_lutpair2925" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r[9][3]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [1]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [2]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [3]),
        .O(p_0_in__10[3]));
  (* SOFT_HLUTNM = "soft_lutpair2925" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r[9][4]_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [2]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [1]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [3]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [4]),
        .O(p_0_in__10[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r[9][5]_i_1 
       (.I0(\not_strict_mode.rd_buf.init_done_r [9]),
        .I1(match4_112_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_112_return),
        .I4(p_0_in16_in),
        .I5(\not_strict_mode.rd_status[4]_167 ),
        .O(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [9]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r[9][5]_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [3]),
        .I1(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [1]),
        .I2(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .I3(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [2]),
        .I4(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [4]),
        .I5(p_0_in16_in),
        .O(p_0_in__10[5]));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [9]),
        .D(p_0_in__10[0]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [9]),
        .D(p_0_in__10[1]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [9]),
        .D(p_0_in__10[2]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [9]),
        .D(p_0_in__10[3]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [9]),
        .D(p_0_in__10[4]),
        .Q(\not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.rd_buf.rd_buffer_ram[9].rd_buf_indx_cpy_r_reg[9][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.rd_buf.upd_rd_buf_indx_cpy [9]),
        .D(p_0_in__10[5]),
        .Q(p_0_in16_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.status_ram_0.RAM32M0 
       (.ADDRA(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 ),
        .ADDRB({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ADDRC(\not_strict_mode.status_ram_0.status_ram_wr_addr_ns ),
        .ADDRD(\not_strict_mode.status_ram_0.status_ram_wr_addr_r ),
        .DIA(\not_strict_mode.status_ram_0.status_ram_wr_data_r ),
        .DIB({1'b0,1'b0}),
        .DIC(\not_strict_mode.status_ram_0.status_ram_wr_data_r ),
        .DID(\not_strict_mode.status_ram_0.status_ram_wr_data_r ),
        .DOA({DOA,\not_strict_mode.rd_status[0]_175 }),
        .DOB(\NLW_not_strict_mode.status_ram_0.RAM32M0_DOB_UNCONNECTED [1:0]),
        .DOC({\NLW_not_strict_mode.status_ram_0.RAM32M0_DOC_UNCONNECTED [1],\not_strict_mode.status_ram_0.wr_status }),
        .DOD(\NLW_not_strict_mode.status_ram_0.RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.rd_buf_we_r1 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.RAM32M0_i_1 
       (.I0(\not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[4]_0 [1]),
        .I1(\not_strict_mode.ram_init_done_r_lcl_sts [0]),
        .I2(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [4]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_ns [4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.RAM32M0_i_2 
       (.I0(\not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[4]_0 [0]),
        .I1(\not_strict_mode.ram_init_done_r_lcl_sts [0]),
        .I2(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [3]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_ns [3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.RAM32M0_i_3 
       (.I0(ADDRD[2]),
        .I1(\not_strict_mode.ram_init_done_r_lcl_sts [0]),
        .I2(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [2]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_ns [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.RAM32M0_i_4 
       (.I0(ADDRD[1]),
        .I1(\not_strict_mode.ram_init_done_r_lcl_sts [0]),
        .I2(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [1]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_ns [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.RAM32M0_i_5 
       (.I0(ADDRD[0]),
        .I1(\not_strict_mode.ram_init_done_r_lcl_sts [0]),
        .I2(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [0]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_ns [0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.status_ram_0.copies_of_sts_ram[0].RAM32M1 
       (.ADDRA(Q),
        .ADDRB(Q),
        .ADDRC(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_176 ),
        .ADDRD(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[0]_177 ),
        .DIA(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[0]_179 ),
        .DIB(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[0]_179 ),
        .DIC(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[0]_179 ),
        .DID({1'b0,1'b0}),
        .DOA({\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[0].RAM32M1_DOA_UNCONNECTED [1],\not_strict_mode.rd_status[1]_168 }),
        .DOB({\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[0].RAM32M1_DOB_UNCONNECTED [1],\not_strict_mode.rd_status[4]_167 }),
        .DOC({\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[0].RAM32M1_DOC_UNCONNECTED [1],\not_strict_mode.status_ram_0.wr_status_cpy[0]_166 }),
        .DOD(\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[0].RAM32M1_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.status_ram_0.rd_buf_we_r [0]));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.status_ram_0.copies_of_sts_ram[0].rd_buf_we_r[0]_i_1 
       (.I0(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 [1]),
        .O(\not_strict_mode.status_ram_0.copies_of_sts_ram[0].rd_buf_we_r[0]_i_1_n_0 ));
  FDSE \not_strict_mode.status_ram_0.copies_of_sts_ram[0].rd_buf_we_r_reg[0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.copies_of_sts_ram[0].rd_buf_we_r[0]_i_1_n_0 ),
        .Q(\not_strict_mode.status_ram_0.rd_buf_we_r [0]),
        .S(rd_data_en_phy2mc));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[0].status_ram_wr_addr_cpy_r_reg[0][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_176 [0]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[0]_177 [0]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[0].status_ram_wr_addr_cpy_r_reg[0][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_176 [1]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[0]_177 [1]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[0].status_ram_wr_addr_cpy_r_reg[0][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_176 [2]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[0]_177 [2]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[0].status_ram_wr_addr_cpy_r_reg[0][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_176 [3]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[0]_177 [3]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[0].status_ram_wr_addr_cpy_r_reg[0][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_176 [4]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[0]_177 [4]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[0].status_ram_wr_data_cpy_r_reg[0][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 [0]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[0]_179 [0]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[0].status_ram_wr_data_cpy_r_reg[0][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 [1]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[0]_179 [1]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[0].wr_status_r_reg[0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.wr_status_cpy[0]_166 ),
        .Q(\not_strict_mode.status_ram_0.wr_status_r [0]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.status_ram_0.copies_of_sts_ram[1].RAM32M1 
       (.ADDRA(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 ),
        .ADDRB(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 ),
        .ADDRC(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_180 ),
        .ADDRD(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[1]_181 ),
        .DIA(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[1]_183 ),
        .DIB(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[1]_183 ),
        .DIC(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[1]_183 ),
        .DID({1'b0,1'b0}),
        .DOA({\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[1].RAM32M1_DOA_UNCONNECTED [1],\not_strict_mode.rd_status[2]_171 }),
        .DOB({\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[1].RAM32M1_DOB_UNCONNECTED [1],\not_strict_mode.rd_status[5]_170 }),
        .DOC({\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[1].RAM32M1_DOC_UNCONNECTED [1],\not_strict_mode.status_ram_0.wr_status_cpy[1]_169 }),
        .DOD(\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[1].RAM32M1_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.status_ram_0.rd_buf_we_r [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.status_ram_0.copies_of_sts_ram[1].rd_buf_we_r[1]_i_1 
       (.I0(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 [1]),
        .O(\not_strict_mode.status_ram_0.copies_of_sts_ram[1].rd_buf_we_r[1]_i_1_n_0 ));
  FDSE \not_strict_mode.status_ram_0.copies_of_sts_ram[1].rd_buf_we_r_reg[1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.copies_of_sts_ram[1].rd_buf_we_r[1]_i_1_n_0 ),
        .Q(\not_strict_mode.status_ram_0.rd_buf_we_r [1]),
        .S(rd_data_en_phy2mc));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[1].status_ram_wr_addr_cpy_r_reg[1][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_180 [0]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[1]_181 [0]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[1].status_ram_wr_addr_cpy_r_reg[1][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_180 [1]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[1]_181 [1]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[1].status_ram_wr_addr_cpy_r_reg[1][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_180 [2]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[1]_181 [2]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[1].status_ram_wr_addr_cpy_r_reg[1][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_180 [3]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[1]_181 [3]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[1].status_ram_wr_addr_cpy_r_reg[1][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_180 [4]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[1]_181 [4]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[1].status_ram_wr_data_cpy_r_reg[1][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 [0]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[1]_183 [0]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[1].status_ram_wr_data_cpy_r_reg[1][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 [1]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[1]_183 [1]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[1].wr_status_r_reg[1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.wr_status_cpy[1]_169 ),
        .Q(\not_strict_mode.status_ram_0.wr_status_r [1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \not_strict_mode.status_ram_0.copies_of_sts_ram[2].RAM32M1 
       (.ADDRA(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 ),
        .ADDRB(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 ),
        .ADDRC(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_184 ),
        .ADDRD(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[2]_185 ),
        .DIA(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[2]_187 ),
        .DIB(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[2]_187 ),
        .DIC(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[2]_187 ),
        .DID({1'b0,1'b0}),
        .DOA({\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[2].RAM32M1_DOA_UNCONNECTED [1],\not_strict_mode.rd_status[3]_174 }),
        .DOB({\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[2].RAM32M1_DOB_UNCONNECTED [1],\not_strict_mode.rd_status[6]_173 }),
        .DOC({\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[2].RAM32M1_DOC_UNCONNECTED [1],\not_strict_mode.status_ram_0.wr_status_cpy[2]_172 }),
        .DOD(\NLW_not_strict_mode.status_ram_0.copies_of_sts_ram[2].RAM32M1_DOD_UNCONNECTED [1:0]),
        .WCLK(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .WE(\not_strict_mode.status_ram_0.rd_buf_we_r [2]));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.status_ram_0.copies_of_sts_ram[2].rd_buf_we_r[2]_i_1 
       (.I0(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 [1]),
        .O(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].rd_buf_we_r[2]_i_1_n_0 ));
  FDSE \not_strict_mode.status_ram_0.copies_of_sts_ram[2].rd_buf_we_r_reg[2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].rd_buf_we_r[2]_i_1_n_0 ),
        .Q(\not_strict_mode.status_ram_0.rd_buf_we_r [2]),
        .S(rd_data_en_phy2mc));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_addr_cpy_r_reg[2][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_184 [0]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[2]_185 [0]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_addr_cpy_r_reg[2][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_184 [1]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[2]_185 [1]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_addr_cpy_r_reg[2][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_184 [2]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[2]_185 [2]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_addr_cpy_r_reg[2][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_184 [3]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[2]_185 [3]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_addr_cpy_r_reg[2][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_184 [4]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy_r[2]_185 [4]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 [0]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[2]_187 [0]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 [1]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy_r[2]_187 [1]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram_0.copies_of_sts_ram[2].wr_status_r_reg[2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.wr_status_cpy[2]_172 ),
        .Q(\not_strict_mode.status_ram_0.wr_status_r [2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.status_ram_0.rd_buf_we_r1_i_2 
       (.I0(\not_strict_mode.ram_init_done_r_lcl_sts [0]),
        .O(\not_strict_mode.status_ram_0.rd_buf_we_r1_i_2_n_0 ));
  (* KEEP = "yes" *) 
  FDSE \not_strict_mode.status_ram_0.rd_buf_we_r1_reg 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.rd_buf_we_r1_i_2_n_0 ),
        .Q(\not_strict_mode.rd_buf_we_r1 ),
        .S(rd_data_en_phy2mc));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_inferred_i_1 
       (.I0(ADDRD[4]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 [1]),
        .I2(Q[4]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_176 [4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_inferred_i_2 
       (.I0(ADDRD[3]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 [1]),
        .I2(Q[3]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_176 [3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_inferred_i_3 
       (.I0(ADDRD[2]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 [1]),
        .I2(Q[2]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_176 [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_inferred_i_4 
       (.I0(ADDRD[1]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 [1]),
        .I2(Q[1]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_176 [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_inferred_i_5 
       (.I0(ADDRD[0]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 [1]),
        .I2(Q[0]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[0]_176 [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_inferred_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 [1]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 [1]),
        .I2(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [4]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_180 [4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_inferred_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[4].RAM32M0_3 [0]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 [1]),
        .I2(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [3]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_180 [3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_inferred_i_3 
       (.I0(ADDRD[2]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 [1]),
        .I2(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [2]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_180 [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_inferred_i_4 
       (.I0(ADDRD[1]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 [1]),
        .I2(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [1]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_180 [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_inferred_i_5 
       (.I0(ADDRD[0]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 [1]),
        .I2(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [0]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[1]_180 [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_inferred_i_1 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 [1]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 [1]),
        .I2(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [4]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_184 [4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_inferred_i_2 
       (.I0(\not_strict_mode.rd_buf.rd_buffer_ram[5].RAM32M0_3 [0]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 [1]),
        .I2(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [3]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_184 [3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_inferred_i_3 
       (.I0(ADDRD[2]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 [1]),
        .I2(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [2]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_184 [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_inferred_i_4 
       (.I0(ADDRD[1]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 [1]),
        .I2(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [1]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_184 [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_inferred_i_5 
       (.I0(ADDRD[0]),
        .I1(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 [1]),
        .I2(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [0]),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_addr_cpy[2]_184 [0]));
  FDRE \not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_ns [0]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_r [0]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_ns [1]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_r [1]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_ns [2]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_r [2]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_ns [3]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_r [3]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram_0.status_ram_wr_addr_r_reg[4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_addr_ns [4]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_addr_r [4]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    \not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_inferred_i_1 
       (.I0(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 [1]),
        .I1(\not_strict_mode.status_ram_0.wr_status_cpy[0]_166 ),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 [0]));
  LUT2 #(
    .INIT(4'h2)) 
    \not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_inferred_i_1 
       (.I0(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 [1]),
        .I1(\not_strict_mode.status_ram_0.wr_status_cpy[1]_169 ),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 [0]));
  LUT2 #(
    .INIT(4'h2)) 
    \not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_inferred_i_1 
       (.I0(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 [1]),
        .I1(\not_strict_mode.status_ram_0.wr_status_cpy[2]_172 ),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 [0]));
  LUT2 #(
    .INIT(4'h2)) 
    \not_strict_mode.status_ram_0.status_ram_wr_data_r[0]_i_1 
       (.I0(\not_strict_mode.ram_init_done_r_lcl_sts [0]),
        .I1(\not_strict_mode.status_ram_0.wr_status ),
        .O(\not_strict_mode.status_ram_0.status_ram_wr_data_r[0]_i_1_n_0 ));
  FDRE \not_strict_mode.status_ram_0.status_ram_wr_data_r_reg[0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_0.status_ram_wr_data_r[0]_i_1_n_0 ),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_data_r [0]),
        .R(1'b0));
  FDRE \not_strict_mode.status_ram_0.status_ram_wr_data_r_reg[1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.ram_init_done_r_lcl_sts [0]),
        .Q(\not_strict_mode.status_ram_0.status_ram_wr_data_r [1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.status_ram_signals[0].ram_init_done_r_lcl_sts[0]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [0]),
        .I1(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [1]),
        .I2(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [2]),
        .I3(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [4]),
        .I4(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [3]),
        .I5(\not_strict_mode.ram_init_done_r_lcl_sts [0]),
        .O(\not_strict_mode.status_ram_signals[0].ram_init_done_r_lcl_sts[0]_i_1_n_0 ));
  FDRE \not_strict_mode.status_ram_signals[0].ram_init_done_r_lcl_sts_reg[0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_signals[0].ram_init_done_r_lcl_sts[0]_i_1_n_0 ),
        .Q(\not_strict_mode.ram_init_done_r_lcl_sts [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r[0][0]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [0]),
        .O(p_0_in__88[0]));
  (* SOFT_HLUTNM = "soft_lutpair3095" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r[0][1]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [0]),
        .I1(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [1]),
        .O(p_0_in__88[1]));
  (* SOFT_HLUTNM = "soft_lutpair3095" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r[0][2]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [0]),
        .I1(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [1]),
        .I2(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [2]),
        .O(p_0_in__88[2]));
  (* SOFT_HLUTNM = "soft_lutpair3003" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r[0][3]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [1]),
        .I1(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [0]),
        .I2(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [2]),
        .I3(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [3]),
        .O(p_0_in__88[3]));
  (* SOFT_HLUTNM = "soft_lutpair3003" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r[0][4]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [2]),
        .I1(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [0]),
        .I2(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [1]),
        .I3(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [3]),
        .I4(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [4]),
        .O(p_0_in__88[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r[0][5]_i_1 
       (.I0(\not_strict_mode.ram_init_done_r_lcl_sts [0]),
        .I1(match4_1_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_1_return),
        .I4(p_0_in93_in),
        .I5(\not_strict_mode.rd_status[0]_175 ),
        .O(\not_strict_mode.upd_rd_buf_indx_sts [0]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r[0][5]_i_2 
       (.I0(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [3]),
        .I1(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [1]),
        .I2(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [0]),
        .I3(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [2]),
        .I4(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [4]),
        .I5(p_0_in93_in),
        .O(p_0_in__88[5]));
  FDRE \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [0]),
        .D(p_0_in__88[0]),
        .Q(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [0]),
        .D(p_0_in__88[1]),
        .Q(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [0]),
        .D(p_0_in__88[2]),
        .Q(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [0]),
        .D(p_0_in__88[3]),
        .Q(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [0]),
        .D(p_0_in__88[4]),
        .Q(\not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[0].rd_buf_indx_sts_r_reg[0][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [0]),
        .D(p_0_in__88[5]),
        .Q(p_0_in93_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.status_ram_signals[1].ram_init_done_r_lcl_sts[1]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[4]),
        .I4(Q[3]),
        .I5(\not_strict_mode.ram_init_done_r_lcl_sts [1]),
        .O(\not_strict_mode.status_ram_signals[1].ram_init_done_r_lcl_sts[1]_i_1_n_0 ));
  FDRE \not_strict_mode.status_ram_signals[1].ram_init_done_r_lcl_sts_reg[1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_signals[1].ram_init_done_r_lcl_sts[1]_i_1_n_0 ),
        .Q(\not_strict_mode.ram_init_done_r_lcl_sts [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r[1][0]_i_1 
       (.I0(Q[0]),
        .O(p_0_in__89[0]));
  (* SOFT_HLUTNM = "soft_lutpair3096" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r[1][1]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(p_0_in__89[1]));
  (* SOFT_HLUTNM = "soft_lutpair3096" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r[1][2]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(p_0_in__89[2]));
  (* SOFT_HLUTNM = "soft_lutpair3004" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r[1][3]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(p_0_in__89[3]));
  (* SOFT_HLUTNM = "soft_lutpair3004" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r[1][4]_i_1 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(p_0_in__89[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r[1][5]_i_1 
       (.I0(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[0]_178 [1]),
        .I1(match4_10_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_10_return),
        .I4(p_0_in94_in),
        .I5(\not_strict_mode.rd_status[1]_168 ),
        .O(\not_strict_mode.upd_rd_buf_indx_sts [1]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r[1][5]_i_2 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[4]),
        .I5(p_0_in94_in),
        .O(p_0_in__89[5]));
  FDRE \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [1]),
        .D(p_0_in__89[0]),
        .Q(Q[0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [1]),
        .D(p_0_in__89[1]),
        .Q(Q[1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [1]),
        .D(p_0_in__89[2]),
        .Q(Q[2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [1]),
        .D(p_0_in__89[3]),
        .Q(Q[3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [1]),
        .D(p_0_in__89[4]),
        .Q(Q[4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[1].rd_buf_indx_sts_r_reg[1][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [1]),
        .D(p_0_in__89[5]),
        .Q(p_0_in94_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.status_ram_signals[2].ram_init_done_r_lcl_sts[2]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [0]),
        .I1(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [1]),
        .I2(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [2]),
        .I3(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [4]),
        .I4(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [3]),
        .I5(\not_strict_mode.ram_init_done_r_lcl_sts [2]),
        .O(\not_strict_mode.status_ram_signals[2].ram_init_done_r_lcl_sts[2]_i_1_n_0 ));
  FDRE \not_strict_mode.status_ram_signals[2].ram_init_done_r_lcl_sts_reg[2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_signals[2].ram_init_done_r_lcl_sts[2]_i_1_n_0 ),
        .Q(\not_strict_mode.ram_init_done_r_lcl_sts [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r[2][0]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [0]),
        .O(p_0_in__90[0]));
  (* SOFT_HLUTNM = "soft_lutpair3097" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r[2][1]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [0]),
        .I1(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [1]),
        .O(p_0_in__90[1]));
  (* SOFT_HLUTNM = "soft_lutpair3097" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r[2][2]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [0]),
        .I1(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [1]),
        .I2(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [2]),
        .O(p_0_in__90[2]));
  (* SOFT_HLUTNM = "soft_lutpair3005" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r[2][3]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [1]),
        .I1(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [0]),
        .I2(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [2]),
        .I3(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [3]),
        .O(p_0_in__90[3]));
  (* SOFT_HLUTNM = "soft_lutpair3005" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r[2][4]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [2]),
        .I1(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [0]),
        .I2(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [1]),
        .I3(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [3]),
        .I4(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [4]),
        .O(p_0_in__90[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r[2][5]_i_1 
       (.I0(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[1]_182 [1]),
        .I1(match4_11_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_11_return),
        .I4(p_0_in95_in),
        .I5(\not_strict_mode.rd_status[2]_171 ),
        .O(\not_strict_mode.upd_rd_buf_indx_sts [2]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r[2][5]_i_2 
       (.I0(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [3]),
        .I1(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [1]),
        .I2(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [0]),
        .I3(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [2]),
        .I4(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [4]),
        .I5(p_0_in95_in),
        .O(p_0_in__90[5]));
  FDRE \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [2]),
        .D(p_0_in__90[0]),
        .Q(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [2]),
        .D(p_0_in__90[1]),
        .Q(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [2]),
        .D(p_0_in__90[2]),
        .Q(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [2]),
        .D(p_0_in__90[3]),
        .Q(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [2]),
        .D(p_0_in__90[4]),
        .Q(\not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[2].rd_buf_indx_sts_r_reg[2][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [2]),
        .D(p_0_in__90[5]),
        .Q(p_0_in95_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts[3]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [0]),
        .I1(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [1]),
        .I2(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [2]),
        .I3(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [4]),
        .I4(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [3]),
        .I5(\not_strict_mode.ram_init_done_r_lcl_sts [3]),
        .O(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts[3]_i_1_n_0 ));
  FDRE \not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(1'b1),
        .D(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts[3]_i_1_n_0 ),
        .Q(\not_strict_mode.ram_init_done_r_lcl_sts [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r[3][0]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [0]),
        .O(p_0_in__91[0]));
  (* SOFT_HLUTNM = "soft_lutpair3098" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r[3][1]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [0]),
        .I1(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [1]),
        .O(p_0_in__91[1]));
  (* SOFT_HLUTNM = "soft_lutpair3098" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r[3][2]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [0]),
        .I1(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [1]),
        .I2(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [2]),
        .O(p_0_in__91[2]));
  (* SOFT_HLUTNM = "soft_lutpair3006" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r[3][3]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [1]),
        .I1(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [0]),
        .I2(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [2]),
        .I3(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [3]),
        .O(p_0_in__91[3]));
  (* SOFT_HLUTNM = "soft_lutpair3006" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r[3][4]_i_1 
       (.I0(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [2]),
        .I1(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [0]),
        .I2(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [1]),
        .I3(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [3]),
        .I4(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [4]),
        .O(p_0_in__91[4]));
  LUT6 #(
    .INIT(64'hFFFFD555D555FFFF)) 
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r[3][5]_i_1 
       (.I0(\not_strict_mode.status_ram_0.status_ram_wr_data_cpy[2]_186 [1]),
        .I1(match4_12_return),
        .I2(rd_data_en_phy2mc),
        .I3(match6_12_return),
        .I4(p_0_in96_in),
        .I5(\not_strict_mode.rd_status[3]_174 ),
        .O(\not_strict_mode.upd_rd_buf_indx_sts [3]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r[3][5]_i_2 
       (.I0(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [3]),
        .I1(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [1]),
        .I2(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [0]),
        .I3(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [2]),
        .I4(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [4]),
        .I5(p_0_in96_in),
        .O(p_0_in__91[5]));
  FDRE \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [3]),
        .D(p_0_in__91[0]),
        .Q(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [3]),
        .D(p_0_in__91[1]),
        .Q(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [3]),
        .D(p_0_in__91[2]),
        .Q(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [3]),
        .D(p_0_in__91[3]),
        .Q(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [3]),
        .D(p_0_in__91[4]),
        .Q(\not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \not_strict_mode.status_ram_signals[3].rd_buf_indx_sts_r_reg[3][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\not_strict_mode.upd_rd_buf_indx_sts [3]),
        .D(p_0_in__91[5]),
        .Q(p_0_in96_in),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    \ram_init_done_r_lcl[7]_i_1 
       (.I0(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [3]),
        .I1(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [4]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [2]),
        .I3(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [1]),
        .I4(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [0]),
        .O(\ram_init_done_r_lcl[7]_i_1_n_0 ));
  (* KEEP = "yes" *) 
  FDRE \ram_init_done_r_lcl_reg[0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .D(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .Q(ram_init_done_r_lcl[0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* KEEP = "yes" *) 
  FDRE \ram_init_done_r_lcl_reg[1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .D(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .Q(ram_init_done_r_lcl[1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* KEEP = "yes" *) 
  FDRE \ram_init_done_r_lcl_reg[2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .D(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .Q(ram_init_done_r_lcl[2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* KEEP = "yes" *) 
  FDRE \ram_init_done_r_lcl_reg[3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .D(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .Q(ram_init_done_r_lcl[3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* KEEP = "yes" *) 
  FDRE \ram_init_done_r_lcl_reg[4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .D(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .Q(ram_init_done_r_lcl[4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* KEEP = "yes" *) 
  FDRE \ram_init_done_r_lcl_reg[5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .D(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .Q(ram_init_done_r_lcl[5]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* KEEP = "yes" *) 
  FDRE \ram_init_done_r_lcl_reg[6] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .D(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .Q(ram_init_done_r_lcl[6]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  (* KEEP = "yes" *) 
  FDRE \ram_init_done_r_lcl_reg[7] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .D(\ram_init_done_r_lcl[7]_i_1_n_0 ),
        .Q(ram_init_done_r_lcl[7]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \rams[0].RAM32M0_i_2 
       (.I0(ADDRC[1]),
        .I1(ram_init_done_r_lcl[2]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [1]),
        .O(pointer_wr_data[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \rams[0].RAM32M0_i_3 
       (.I0(ADDRC[0]),
        .I1(ram_init_done_r_lcl[2]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [0]),
        .O(pointer_wr_data[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \rams[0].RAM32M0_i_4 
       (.I0(\rams[0].RAM32M0 [3]),
        .I1(ram_init_done_r_lcl[2]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [3]),
        .O(\rd_data_indx_r_reg[3] [3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \rams[0].RAM32M0_i_5 
       (.I0(\rams[0].RAM32M0 [2]),
        .I1(ram_init_done_r_lcl[2]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [2]),
        .O(\rd_data_indx_r_reg[3] [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \rams[0].RAM32M0_i_6 
       (.I0(\rams[0].RAM32M0 [1]),
        .I1(ram_init_done_r_lcl[2]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [1]),
        .O(\rd_data_indx_r_reg[3] [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \rams[0].RAM32M0_i_7 
       (.I0(\rams[0].RAM32M0 [0]),
        .I1(ram_init_done_r_lcl[2]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [0]),
        .O(\rd_data_indx_r_reg[3] [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \rams[1].RAM32M0_i_1 
       (.I0(ADDRC[3]),
        .I1(ram_init_done_r_lcl[2]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [3]),
        .O(pointer_wr_data[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \rams[1].RAM32M0_i_2 
       (.I0(ADDRC[2]),
        .I1(ram_init_done_r_lcl[2]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [2]),
        .O(pointer_wr_data[2]));
  LUT1 #(
    .INIT(2'h1)) 
    \rd_buf_index_cpy[0].rd_buf_indx_r[0][0]_i_1 
       (.I0(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [0]),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair3094" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_buf_index_cpy[0].rd_buf_indx_r[0][1]_i_1 
       (.I0(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [0]),
        .I1(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [1]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair3094" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rd_buf_index_cpy[0].rd_buf_indx_r[0][2]_i_1 
       (.I0(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [0]),
        .I1(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [1]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [2]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair3002" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \rd_buf_index_cpy[0].rd_buf_indx_r[0][3]_i_1 
       (.I0(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [1]),
        .I1(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [0]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [2]),
        .I3(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [3]),
        .O(p_0_in__1[3]));
  (* SOFT_HLUTNM = "soft_lutpair3002" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \rd_buf_index_cpy[0].rd_buf_indx_r[0][4]_i_1 
       (.I0(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [2]),
        .I1(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [0]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [1]),
        .I3(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [3]),
        .I4(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [4]),
        .O(p_0_in__1[4]));
  LUT4 #(
    .INIT(16'hF9FF)) 
    \rd_buf_index_cpy[0].rd_buf_indx_r[0][5]_i_1 
       (.I0(p_0_in__0),
        .I1(\not_strict_mode.rd_status[0]_175 ),
        .I2(\not_strict_mode.bypass_cpy2 ),
        .I3(ram_init_done_r_lcl[4]),
        .O(\rd_buf_index_cpy[0].rd_buf_indx_r[0][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \rd_buf_index_cpy[0].rd_buf_indx_r[0][5]_i_2 
       (.I0(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [3]),
        .I1(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [1]),
        .I2(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [0]),
        .I3(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [2]),
        .I4(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [4]),
        .I5(p_0_in__0),
        .O(p_0_in__1[5]));
  FDRE \rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][0] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\rd_buf_index_cpy[0].rd_buf_indx_r[0][5]_i_1_n_0 ),
        .D(p_0_in__1[0]),
        .Q(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [0]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][1] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\rd_buf_index_cpy[0].rd_buf_indx_r[0][5]_i_1_n_0 ),
        .D(p_0_in__1[1]),
        .Q(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [1]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][2] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\rd_buf_index_cpy[0].rd_buf_indx_r[0][5]_i_1_n_0 ),
        .D(p_0_in__1[2]),
        .Q(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [2]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][3] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\rd_buf_index_cpy[0].rd_buf_indx_r[0][5]_i_1_n_0 ),
        .D(p_0_in__1[3]),
        .Q(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [3]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\rd_buf_index_cpy[0].rd_buf_indx_r[0][5]_i_1_n_0 ),
        .D(p_0_in__1[4]),
        .Q(\rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][4]_0 [4]),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
  FDRE \rd_buf_index_cpy[0].rd_buf_indx_r_reg[0][5] 
       (.C(\not_strict_mode.status_ram_0.copies_of_sts_ram[2].status_ram_wr_data_cpy_r_reg[2][1]_0 ),
        .CE(\rd_buf_index_cpy[0].rd_buf_indx_r[0][5]_i_1_n_0 ),
        .D(p_0_in__1[5]),
        .Q(p_0_in__0),
        .R(\not_strict_mode.status_ram_signals[3].ram_init_done_r_lcl_sts_reg[3]_0 ));
endmodule

(* ORIG_REF_NAME = "ddr4_v2_2_17_ui_wr_data" *) 
module ddr4_0_ddr4_v2_2_17_ui_wr_data
   (wr_data_buf_addr,
    out,
    c0_ddr4_app_wdf_rdy,
    app_rdy_ns,
    \wr_req_cnt_r_reg[1]_0 ,
    Q,
    \wr_buf_out_data_reg[575]_0 ,
    \rd_data_indx_r_reg[3]_0 ,
    pointer_we,
    pointer_wr_data,
    \rams[0].RAM32M0_0 ,
    \wr_buffer_ram[8].RAM32M0_0 ,
    \wr_buffer_ram[40].RAM32M0_0 ,
    ADDRA,
    ADDRC,
    \wr_data_indx_r_reg[1]_0 ,
    c0_ddr4_app_wdf_wren,
    c0_ddr4_app_wdf_end,
    \rd_data_indx_r_reg[3]_1 ,
    accept_ns,
    rd_buf_full0,
    app_rdy_r_reg,
    wr_accepted,
    \wr_req_cnt_r_reg[3]_0 ,
    \wr_req_cnt_r_reg[3]_1 ,
    \wr_data_indx_r_reg[0]_0 ,
    D,
    c0_ddr4_app_wdf_data,
    c0_ddr4_app_wdf_mask);
  output [3:0]wr_data_buf_addr;
  output out;
  output c0_ddr4_app_wdf_rdy;
  output app_rdy_ns;
  output [1:0]\wr_req_cnt_r_reg[1]_0 ;
  output [3:0]Q;
  output [575:0]\wr_buf_out_data_reg[575]_0 ;
  input \rd_data_indx_r_reg[3]_0 ;
  input pointer_we;
  input [3:0]pointer_wr_data;
  input [3:0]\rams[0].RAM32M0_0 ;
  input [3:0]\wr_buffer_ram[8].RAM32M0_0 ;
  input [3:0]\wr_buffer_ram[40].RAM32M0_0 ;
  input [3:0]ADDRA;
  input [3:0]ADDRC;
  input \wr_data_indx_r_reg[1]_0 ;
  input c0_ddr4_app_wdf_wren;
  input c0_ddr4_app_wdf_end;
  input [0:0]\rd_data_indx_r_reg[3]_1 ;
  input accept_ns;
  input rd_buf_full0;
  input [0:0]app_rdy_r_reg;
  input wr_accepted;
  input \wr_req_cnt_r_reg[3]_0 ;
  input \wr_req_cnt_r_reg[3]_1 ;
  input [1:0]\wr_data_indx_r_reg[0]_0 ;
  input [0:0]D;
  input [511:0]c0_ddr4_app_wdf_data;
  input [63:0]c0_ddr4_app_wdf_mask;

  wire [3:0]ADDRA;
  wire [3:0]ADDRC;
  wire [0:0]D;
  wire [3:0]Q;
  wire accept_ns;
  wire app_rdy_ns;
  wire app_rdy_r_i_4_n_0;
  wire [0:0]app_rdy_r_reg;
  wire [511:0]app_wdf_data_r1;
  wire app_wdf_end_r1;
  wire [63:0]app_wdf_mask_r1;
  (* RTL_KEEP = "true" *) wire app_wdf_rdy_r;
  (* RTL_KEEP = "true" *) wire app_wdf_rdy_r_copy1;
  wire app_wdf_rdy_r_copy1_i_1_n_0;
  (* RTL_KEEP = "true" *) wire app_wdf_rdy_r_copy2;
  (* RTL_KEEP = "true" *) wire app_wdf_rdy_r_copy3;
  (* RTL_KEEP = "true" *) wire app_wdf_rdy_r_copy4;
  (* RTL_KEEP = "true" *) wire app_wdf_rdy_r_copy5;
  (* RTL_KEEP = "true" *) wire app_wdf_rdy_r_copy6;
  (* RTL_KEEP = "true" *) wire app_wdf_rdy_r_copy7;
  wire app_wdf_wren_r1;
  wire [511:0]c0_ddr4_app_wdf_data;
  wire c0_ddr4_app_wdf_end;
  wire [63:0]c0_ddr4_app_wdf_mask;
  wire c0_ddr4_app_wdf_wren;
  wire [3:0]data_buf_addr_cnt_r_reg;
  wire \occ_cnt[15]_i_1_n_0 ;
  wire \occ_cnt_reg_n_0_[0] ;
  wire \occ_cnt_reg_n_0_[10] ;
  wire \occ_cnt_reg_n_0_[11] ;
  wire \occ_cnt_reg_n_0_[12] ;
  wire \occ_cnt_reg_n_0_[13] ;
  wire \occ_cnt_reg_n_0_[1] ;
  wire \occ_cnt_reg_n_0_[2] ;
  wire \occ_cnt_reg_n_0_[3] ;
  wire \occ_cnt_reg_n_0_[4] ;
  wire \occ_cnt_reg_n_0_[5] ;
  wire \occ_cnt_reg_n_0_[6] ;
  wire \occ_cnt_reg_n_0_[7] ;
  wire \occ_cnt_reg_n_0_[8] ;
  wire \occ_cnt_reg_n_0_[9] ;
  wire p_0_in12_in;
  wire p_0_in2_in;
  wire [3:0]p_0_in__0;
  wire [3:0]p_0_in__0__0;
  wire [3:0]p_0_in__1;
  wire p_11_in;
  wire [15:0]p_1_in;
  wire pointer_we;
  wire [3:0]pointer_wr_data;
  wire [3:0]\rams[0].RAM32M0_0 ;
  wire rd_buf_full0;
  wire \rd_data_indx_r_reg[3]_0 ;
  wire [0:0]\rd_data_indx_r_reg[3]_1 ;
  (* RTL_KEEP = "true" *) wire rd_data_upd_indx_cpy_r;
  (* RTL_KEEP = "true" *) wire rd_data_upd_indx_r;
  wire wb_wr_data_addr0_ns;
  wire wb_wr_data_addr0_r;
  wire [4:1]wb_wr_data_addr_r;
  wire [4:1]wb_wr_data_addr_w;
  wire wdf_rdy_ns;
  wire wr_accepted;
  wire [575:0]wr_buf_in_data;
  wire [575:0]\wr_buf_out_data_reg[575]_0 ;
  wire [575:0]wr_buf_out_data_w;
  wire [3:0]\wr_buffer_ram[40].RAM32M0_0 ;
  wire [3:0]\wr_buffer_ram[8].RAM32M0_0 ;
  wire wr_data_addr_le;
  wire [3:0]wr_data_buf_addr;
  wire [3:0]wr_data_indx_r_reg;
  wire [1:0]\wr_data_indx_r_reg[0]_0 ;
  wire \wr_data_indx_r_reg[1]_0 ;
  wire [3:0]wr_data_pntr;
  wire [4:2]wr_req_cnt_r;
  wire \wr_req_cnt_r[1]_i_1_n_0 ;
  wire \wr_req_cnt_r[2]_i_1_n_0 ;
  wire \wr_req_cnt_r[3]_i_1_n_0 ;
  wire \wr_req_cnt_r[4]_i_1_n_0 ;
  wire [1:0]\wr_req_cnt_r_reg[1]_0 ;
  wire \wr_req_cnt_r_reg[3]_0 ;
  wire \wr_req_cnt_r_reg[3]_1 ;
  wire [1:0]\NLW_rams[0].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_rams[0].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_rams[1].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_rams[1].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[48].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[49].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[50].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[51].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[52].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[53].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[54].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[55].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[56].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[57].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[58].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[59].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[60].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[61].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[62].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[63].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[64].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[65].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[66].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[67].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[68].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[69].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[70].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[71].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[72].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[73].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[74].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[75].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[76].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[77].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[78].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[79].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[80].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[81].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[82].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[83].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[84].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[85].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[86].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[87].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[88].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[89].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[90].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[91].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[92].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[93].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[94].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[95].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ;

  assign c0_ddr4_app_wdf_rdy = app_wdf_rdy_r;
  assign out = rd_data_upd_indx_r;
  LUT6 #(
    .INIT(64'h0200020202020202)) 
    app_rdy_r_i_1
       (.I0(accept_ns),
        .I1(rd_buf_full0),
        .I2(app_rdy_r_reg),
        .I3(\wr_req_cnt_r[3]_i_1_n_0 ),
        .I4(app_rdy_r_i_4_n_0),
        .I5(\wr_req_cnt_r[4]_i_1_n_0 ),
        .O(app_rdy_ns));
  LUT6 #(
    .INIT(64'h0001001040000001)) 
    app_rdy_r_i_4
       (.I0(\wr_data_indx_r_reg[1]_0 ),
        .I1(wr_req_cnt_r[2]),
        .I2(wr_accepted),
        .I3(\wr_req_cnt_r_reg[1]_0 [1]),
        .I4(\wr_req_cnt_r_reg[1]_0 [0]),
        .I5(rd_data_upd_indx_r),
        .O(app_rdy_r_i_4_n_0));
  FDRE \app_wdf_data_r1_reg[0] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[0]),
        .Q(app_wdf_data_r1[0]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[100] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[100]),
        .Q(app_wdf_data_r1[100]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[101] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[101]),
        .Q(app_wdf_data_r1[101]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[102] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[102]),
        .Q(app_wdf_data_r1[102]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[103] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[103]),
        .Q(app_wdf_data_r1[103]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[104] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[104]),
        .Q(app_wdf_data_r1[104]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[105] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[105]),
        .Q(app_wdf_data_r1[105]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[106] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[106]),
        .Q(app_wdf_data_r1[106]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[107] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[107]),
        .Q(app_wdf_data_r1[107]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[108] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[108]),
        .Q(app_wdf_data_r1[108]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[109] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[109]),
        .Q(app_wdf_data_r1[109]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[10] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[10]),
        .Q(app_wdf_data_r1[10]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[110] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[110]),
        .Q(app_wdf_data_r1[110]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[111] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[111]),
        .Q(app_wdf_data_r1[111]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[112] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[112]),
        .Q(app_wdf_data_r1[112]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[113] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[113]),
        .Q(app_wdf_data_r1[113]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[114] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[114]),
        .Q(app_wdf_data_r1[114]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[115] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[115]),
        .Q(app_wdf_data_r1[115]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[116] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[116]),
        .Q(app_wdf_data_r1[116]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[117] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[117]),
        .Q(app_wdf_data_r1[117]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[118] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[118]),
        .Q(app_wdf_data_r1[118]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[119] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[119]),
        .Q(app_wdf_data_r1[119]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[11] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[11]),
        .Q(app_wdf_data_r1[11]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[120] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[120]),
        .Q(app_wdf_data_r1[120]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[121] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[121]),
        .Q(app_wdf_data_r1[121]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[122] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[122]),
        .Q(app_wdf_data_r1[122]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[123] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[123]),
        .Q(app_wdf_data_r1[123]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[124] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[124]),
        .Q(app_wdf_data_r1[124]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[125] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[125]),
        .Q(app_wdf_data_r1[125]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[126] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[126]),
        .Q(app_wdf_data_r1[126]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[127] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[127]),
        .Q(app_wdf_data_r1[127]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[128] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[128]),
        .Q(app_wdf_data_r1[128]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[129] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[129]),
        .Q(app_wdf_data_r1[129]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[12] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[12]),
        .Q(app_wdf_data_r1[12]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[130] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[130]),
        .Q(app_wdf_data_r1[130]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[131] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[131]),
        .Q(app_wdf_data_r1[131]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[132] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[132]),
        .Q(app_wdf_data_r1[132]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[133] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[133]),
        .Q(app_wdf_data_r1[133]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[134] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[134]),
        .Q(app_wdf_data_r1[134]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[135] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[135]),
        .Q(app_wdf_data_r1[135]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[136] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[136]),
        .Q(app_wdf_data_r1[136]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[137] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[137]),
        .Q(app_wdf_data_r1[137]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[138] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[138]),
        .Q(app_wdf_data_r1[138]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[139] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[139]),
        .Q(app_wdf_data_r1[139]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[13] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[13]),
        .Q(app_wdf_data_r1[13]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[140] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[140]),
        .Q(app_wdf_data_r1[140]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[141] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[141]),
        .Q(app_wdf_data_r1[141]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[142] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[142]),
        .Q(app_wdf_data_r1[142]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[143] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[143]),
        .Q(app_wdf_data_r1[143]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[144] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[144]),
        .Q(app_wdf_data_r1[144]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[145] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[145]),
        .Q(app_wdf_data_r1[145]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[146] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[146]),
        .Q(app_wdf_data_r1[146]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[147] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[147]),
        .Q(app_wdf_data_r1[147]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[148] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[148]),
        .Q(app_wdf_data_r1[148]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[149] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[149]),
        .Q(app_wdf_data_r1[149]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[14] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[14]),
        .Q(app_wdf_data_r1[14]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[150] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[150]),
        .Q(app_wdf_data_r1[150]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[151] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[151]),
        .Q(app_wdf_data_r1[151]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[152] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[152]),
        .Q(app_wdf_data_r1[152]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[153] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[153]),
        .Q(app_wdf_data_r1[153]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[154] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[154]),
        .Q(app_wdf_data_r1[154]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[155] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[155]),
        .Q(app_wdf_data_r1[155]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[156] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[156]),
        .Q(app_wdf_data_r1[156]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[157] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[157]),
        .Q(app_wdf_data_r1[157]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[158] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[158]),
        .Q(app_wdf_data_r1[158]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[159] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[159]),
        .Q(app_wdf_data_r1[159]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[15] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[15]),
        .Q(app_wdf_data_r1[15]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[160] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[160]),
        .Q(app_wdf_data_r1[160]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[161] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[161]),
        .Q(app_wdf_data_r1[161]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[162] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[162]),
        .Q(app_wdf_data_r1[162]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[163] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[163]),
        .Q(app_wdf_data_r1[163]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[164] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[164]),
        .Q(app_wdf_data_r1[164]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[165] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[165]),
        .Q(app_wdf_data_r1[165]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[166] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[166]),
        .Q(app_wdf_data_r1[166]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[167] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[167]),
        .Q(app_wdf_data_r1[167]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[168] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[168]),
        .Q(app_wdf_data_r1[168]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[169] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[169]),
        .Q(app_wdf_data_r1[169]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[16] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[16]),
        .Q(app_wdf_data_r1[16]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[170] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[170]),
        .Q(app_wdf_data_r1[170]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[171] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[171]),
        .Q(app_wdf_data_r1[171]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[172] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[172]),
        .Q(app_wdf_data_r1[172]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[173] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[173]),
        .Q(app_wdf_data_r1[173]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[174] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[174]),
        .Q(app_wdf_data_r1[174]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[175] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[175]),
        .Q(app_wdf_data_r1[175]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[176] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[176]),
        .Q(app_wdf_data_r1[176]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[177] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[177]),
        .Q(app_wdf_data_r1[177]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[178] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[178]),
        .Q(app_wdf_data_r1[178]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[179] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[179]),
        .Q(app_wdf_data_r1[179]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[17] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[17]),
        .Q(app_wdf_data_r1[17]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[180] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[180]),
        .Q(app_wdf_data_r1[180]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[181] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[181]),
        .Q(app_wdf_data_r1[181]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[182] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[182]),
        .Q(app_wdf_data_r1[182]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[183] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[183]),
        .Q(app_wdf_data_r1[183]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[184] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[184]),
        .Q(app_wdf_data_r1[184]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[185] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[185]),
        .Q(app_wdf_data_r1[185]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[186] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[186]),
        .Q(app_wdf_data_r1[186]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[187] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[187]),
        .Q(app_wdf_data_r1[187]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[188] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[188]),
        .Q(app_wdf_data_r1[188]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[189] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[189]),
        .Q(app_wdf_data_r1[189]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[18] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[18]),
        .Q(app_wdf_data_r1[18]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[190] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[190]),
        .Q(app_wdf_data_r1[190]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[191] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[191]),
        .Q(app_wdf_data_r1[191]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[192] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[192]),
        .Q(app_wdf_data_r1[192]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[193] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[193]),
        .Q(app_wdf_data_r1[193]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[194] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[194]),
        .Q(app_wdf_data_r1[194]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[195] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[195]),
        .Q(app_wdf_data_r1[195]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[196] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[196]),
        .Q(app_wdf_data_r1[196]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[197] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[197]),
        .Q(app_wdf_data_r1[197]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[198] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[198]),
        .Q(app_wdf_data_r1[198]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[199] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[199]),
        .Q(app_wdf_data_r1[199]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[19] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[19]),
        .Q(app_wdf_data_r1[19]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[1] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[1]),
        .Q(app_wdf_data_r1[1]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[200] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[200]),
        .Q(app_wdf_data_r1[200]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[201] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[201]),
        .Q(app_wdf_data_r1[201]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[202] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[202]),
        .Q(app_wdf_data_r1[202]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[203] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[203]),
        .Q(app_wdf_data_r1[203]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[204] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[204]),
        .Q(app_wdf_data_r1[204]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[205] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[205]),
        .Q(app_wdf_data_r1[205]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[206] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[206]),
        .Q(app_wdf_data_r1[206]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[207] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[207]),
        .Q(app_wdf_data_r1[207]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[208] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[208]),
        .Q(app_wdf_data_r1[208]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[209] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[209]),
        .Q(app_wdf_data_r1[209]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[20] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[20]),
        .Q(app_wdf_data_r1[20]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[210] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[210]),
        .Q(app_wdf_data_r1[210]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[211] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[211]),
        .Q(app_wdf_data_r1[211]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[212] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[212]),
        .Q(app_wdf_data_r1[212]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[213] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[213]),
        .Q(app_wdf_data_r1[213]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[214] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[214]),
        .Q(app_wdf_data_r1[214]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[215] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[215]),
        .Q(app_wdf_data_r1[215]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[216] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[216]),
        .Q(app_wdf_data_r1[216]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[217] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[217]),
        .Q(app_wdf_data_r1[217]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[218] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[218]),
        .Q(app_wdf_data_r1[218]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[219] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[219]),
        .Q(app_wdf_data_r1[219]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[21] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[21]),
        .Q(app_wdf_data_r1[21]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[220] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[220]),
        .Q(app_wdf_data_r1[220]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[221] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[221]),
        .Q(app_wdf_data_r1[221]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[222] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[222]),
        .Q(app_wdf_data_r1[222]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[223] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[223]),
        .Q(app_wdf_data_r1[223]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[224] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[224]),
        .Q(app_wdf_data_r1[224]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[225] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[225]),
        .Q(app_wdf_data_r1[225]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[226] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[226]),
        .Q(app_wdf_data_r1[226]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[227] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[227]),
        .Q(app_wdf_data_r1[227]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[228] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[228]),
        .Q(app_wdf_data_r1[228]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[229] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[229]),
        .Q(app_wdf_data_r1[229]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[22] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[22]),
        .Q(app_wdf_data_r1[22]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[230] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[230]),
        .Q(app_wdf_data_r1[230]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[231] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[231]),
        .Q(app_wdf_data_r1[231]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[232] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[232]),
        .Q(app_wdf_data_r1[232]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[233] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[233]),
        .Q(app_wdf_data_r1[233]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[234] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[234]),
        .Q(app_wdf_data_r1[234]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[235] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[235]),
        .Q(app_wdf_data_r1[235]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[236] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[236]),
        .Q(app_wdf_data_r1[236]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[237] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[237]),
        .Q(app_wdf_data_r1[237]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[238] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[238]),
        .Q(app_wdf_data_r1[238]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[239] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[239]),
        .Q(app_wdf_data_r1[239]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[23] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[23]),
        .Q(app_wdf_data_r1[23]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[240] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[240]),
        .Q(app_wdf_data_r1[240]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[241] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[241]),
        .Q(app_wdf_data_r1[241]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[242] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[242]),
        .Q(app_wdf_data_r1[242]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[243] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[243]),
        .Q(app_wdf_data_r1[243]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[244] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[244]),
        .Q(app_wdf_data_r1[244]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[245] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[245]),
        .Q(app_wdf_data_r1[245]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[246] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[246]),
        .Q(app_wdf_data_r1[246]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[247] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[247]),
        .Q(app_wdf_data_r1[247]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[248] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[248]),
        .Q(app_wdf_data_r1[248]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[249] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[249]),
        .Q(app_wdf_data_r1[249]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[24] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[24]),
        .Q(app_wdf_data_r1[24]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[250] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[250]),
        .Q(app_wdf_data_r1[250]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[251] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[251]),
        .Q(app_wdf_data_r1[251]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[252] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[252]),
        .Q(app_wdf_data_r1[252]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[253] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[253]),
        .Q(app_wdf_data_r1[253]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[254] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[254]),
        .Q(app_wdf_data_r1[254]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[255] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[255]),
        .Q(app_wdf_data_r1[255]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[256] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[256]),
        .Q(app_wdf_data_r1[256]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[257] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[257]),
        .Q(app_wdf_data_r1[257]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[258] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[258]),
        .Q(app_wdf_data_r1[258]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[259] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[259]),
        .Q(app_wdf_data_r1[259]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[25] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[25]),
        .Q(app_wdf_data_r1[25]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[260] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[260]),
        .Q(app_wdf_data_r1[260]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[261] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[261]),
        .Q(app_wdf_data_r1[261]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[262] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[262]),
        .Q(app_wdf_data_r1[262]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[263] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[263]),
        .Q(app_wdf_data_r1[263]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[264] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[264]),
        .Q(app_wdf_data_r1[264]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[265] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[265]),
        .Q(app_wdf_data_r1[265]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[266] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[266]),
        .Q(app_wdf_data_r1[266]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[267] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[267]),
        .Q(app_wdf_data_r1[267]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[268] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[268]),
        .Q(app_wdf_data_r1[268]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[269] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[269]),
        .Q(app_wdf_data_r1[269]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[26] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[26]),
        .Q(app_wdf_data_r1[26]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[270] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[270]),
        .Q(app_wdf_data_r1[270]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[271] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[271]),
        .Q(app_wdf_data_r1[271]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[272] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[272]),
        .Q(app_wdf_data_r1[272]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[273] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[273]),
        .Q(app_wdf_data_r1[273]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[274] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[274]),
        .Q(app_wdf_data_r1[274]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[275] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[275]),
        .Q(app_wdf_data_r1[275]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[276] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[276]),
        .Q(app_wdf_data_r1[276]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[277] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[277]),
        .Q(app_wdf_data_r1[277]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[278] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[278]),
        .Q(app_wdf_data_r1[278]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[279] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[279]),
        .Q(app_wdf_data_r1[279]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[27] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[27]),
        .Q(app_wdf_data_r1[27]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[280] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[280]),
        .Q(app_wdf_data_r1[280]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[281] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[281]),
        .Q(app_wdf_data_r1[281]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[282] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[282]),
        .Q(app_wdf_data_r1[282]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[283] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[283]),
        .Q(app_wdf_data_r1[283]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[284] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[284]),
        .Q(app_wdf_data_r1[284]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[285] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[285]),
        .Q(app_wdf_data_r1[285]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[286] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[286]),
        .Q(app_wdf_data_r1[286]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[287] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[287]),
        .Q(app_wdf_data_r1[287]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[288] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[288]),
        .Q(app_wdf_data_r1[288]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[289] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[289]),
        .Q(app_wdf_data_r1[289]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[28] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[28]),
        .Q(app_wdf_data_r1[28]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[290] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[290]),
        .Q(app_wdf_data_r1[290]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[291] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[291]),
        .Q(app_wdf_data_r1[291]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[292] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[292]),
        .Q(app_wdf_data_r1[292]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[293] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[293]),
        .Q(app_wdf_data_r1[293]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[294] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[294]),
        .Q(app_wdf_data_r1[294]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[295] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[295]),
        .Q(app_wdf_data_r1[295]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[296] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[296]),
        .Q(app_wdf_data_r1[296]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[297] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[297]),
        .Q(app_wdf_data_r1[297]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[298] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[298]),
        .Q(app_wdf_data_r1[298]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[299] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[299]),
        .Q(app_wdf_data_r1[299]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[29] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[29]),
        .Q(app_wdf_data_r1[29]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[2] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[2]),
        .Q(app_wdf_data_r1[2]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[300] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[300]),
        .Q(app_wdf_data_r1[300]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[301] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[301]),
        .Q(app_wdf_data_r1[301]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[302] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[302]),
        .Q(app_wdf_data_r1[302]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[303] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[303]),
        .Q(app_wdf_data_r1[303]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[304] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[304]),
        .Q(app_wdf_data_r1[304]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[305] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[305]),
        .Q(app_wdf_data_r1[305]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[306] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[306]),
        .Q(app_wdf_data_r1[306]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[307] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[307]),
        .Q(app_wdf_data_r1[307]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[308] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[308]),
        .Q(app_wdf_data_r1[308]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[309] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[309]),
        .Q(app_wdf_data_r1[309]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[30] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[30]),
        .Q(app_wdf_data_r1[30]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[310] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[310]),
        .Q(app_wdf_data_r1[310]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[311] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[311]),
        .Q(app_wdf_data_r1[311]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[312] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[312]),
        .Q(app_wdf_data_r1[312]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[313] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[313]),
        .Q(app_wdf_data_r1[313]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[314] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[314]),
        .Q(app_wdf_data_r1[314]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[315] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[315]),
        .Q(app_wdf_data_r1[315]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[316] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[316]),
        .Q(app_wdf_data_r1[316]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[317] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[317]),
        .Q(app_wdf_data_r1[317]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[318] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[318]),
        .Q(app_wdf_data_r1[318]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[319] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[319]),
        .Q(app_wdf_data_r1[319]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[31] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[31]),
        .Q(app_wdf_data_r1[31]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[320] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[320]),
        .Q(app_wdf_data_r1[320]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[321] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[321]),
        .Q(app_wdf_data_r1[321]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[322] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[322]),
        .Q(app_wdf_data_r1[322]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[323] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[323]),
        .Q(app_wdf_data_r1[323]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[324] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[324]),
        .Q(app_wdf_data_r1[324]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[325] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[325]),
        .Q(app_wdf_data_r1[325]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[326] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[326]),
        .Q(app_wdf_data_r1[326]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[327] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[327]),
        .Q(app_wdf_data_r1[327]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[328] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[328]),
        .Q(app_wdf_data_r1[328]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[329] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[329]),
        .Q(app_wdf_data_r1[329]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[32] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[32]),
        .Q(app_wdf_data_r1[32]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[330] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[330]),
        .Q(app_wdf_data_r1[330]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[331] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[331]),
        .Q(app_wdf_data_r1[331]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[332] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[332]),
        .Q(app_wdf_data_r1[332]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[333] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[333]),
        .Q(app_wdf_data_r1[333]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[334] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[334]),
        .Q(app_wdf_data_r1[334]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[335] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[335]),
        .Q(app_wdf_data_r1[335]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[336] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[336]),
        .Q(app_wdf_data_r1[336]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[337] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[337]),
        .Q(app_wdf_data_r1[337]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[338] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[338]),
        .Q(app_wdf_data_r1[338]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[339] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[339]),
        .Q(app_wdf_data_r1[339]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[33] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[33]),
        .Q(app_wdf_data_r1[33]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[340] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[340]),
        .Q(app_wdf_data_r1[340]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[341] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[341]),
        .Q(app_wdf_data_r1[341]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[342] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[342]),
        .Q(app_wdf_data_r1[342]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[343] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[343]),
        .Q(app_wdf_data_r1[343]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[344] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[344]),
        .Q(app_wdf_data_r1[344]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[345] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[345]),
        .Q(app_wdf_data_r1[345]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[346] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[346]),
        .Q(app_wdf_data_r1[346]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[347] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[347]),
        .Q(app_wdf_data_r1[347]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[348] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[348]),
        .Q(app_wdf_data_r1[348]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[349] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[349]),
        .Q(app_wdf_data_r1[349]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[34] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[34]),
        .Q(app_wdf_data_r1[34]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[350] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[350]),
        .Q(app_wdf_data_r1[350]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[351] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[351]),
        .Q(app_wdf_data_r1[351]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[352] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[352]),
        .Q(app_wdf_data_r1[352]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[353] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[353]),
        .Q(app_wdf_data_r1[353]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[354] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[354]),
        .Q(app_wdf_data_r1[354]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[355] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[355]),
        .Q(app_wdf_data_r1[355]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[356] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[356]),
        .Q(app_wdf_data_r1[356]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[357] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[357]),
        .Q(app_wdf_data_r1[357]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[358] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[358]),
        .Q(app_wdf_data_r1[358]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[359] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[359]),
        .Q(app_wdf_data_r1[359]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[35] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[35]),
        .Q(app_wdf_data_r1[35]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[360] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[360]),
        .Q(app_wdf_data_r1[360]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[361] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[361]),
        .Q(app_wdf_data_r1[361]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[362] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[362]),
        .Q(app_wdf_data_r1[362]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[363] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[363]),
        .Q(app_wdf_data_r1[363]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[364] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[364]),
        .Q(app_wdf_data_r1[364]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[365] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[365]),
        .Q(app_wdf_data_r1[365]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[366] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[366]),
        .Q(app_wdf_data_r1[366]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[367] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[367]),
        .Q(app_wdf_data_r1[367]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[368] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[368]),
        .Q(app_wdf_data_r1[368]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[369] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[369]),
        .Q(app_wdf_data_r1[369]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[36] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[36]),
        .Q(app_wdf_data_r1[36]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[370] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[370]),
        .Q(app_wdf_data_r1[370]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[371] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[371]),
        .Q(app_wdf_data_r1[371]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[372] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[372]),
        .Q(app_wdf_data_r1[372]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[373] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[373]),
        .Q(app_wdf_data_r1[373]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[374] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[374]),
        .Q(app_wdf_data_r1[374]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[375] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[375]),
        .Q(app_wdf_data_r1[375]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[376] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[376]),
        .Q(app_wdf_data_r1[376]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[377] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[377]),
        .Q(app_wdf_data_r1[377]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[378] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[378]),
        .Q(app_wdf_data_r1[378]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[379] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[379]),
        .Q(app_wdf_data_r1[379]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[37] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[37]),
        .Q(app_wdf_data_r1[37]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[380] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[380]),
        .Q(app_wdf_data_r1[380]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[381] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[381]),
        .Q(app_wdf_data_r1[381]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[382] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[382]),
        .Q(app_wdf_data_r1[382]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[383] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[383]),
        .Q(app_wdf_data_r1[383]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[384] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[384]),
        .Q(app_wdf_data_r1[384]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[385] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[385]),
        .Q(app_wdf_data_r1[385]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[386] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[386]),
        .Q(app_wdf_data_r1[386]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[387] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[387]),
        .Q(app_wdf_data_r1[387]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[388] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[388]),
        .Q(app_wdf_data_r1[388]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[389] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[389]),
        .Q(app_wdf_data_r1[389]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[38] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[38]),
        .Q(app_wdf_data_r1[38]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[390] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[390]),
        .Q(app_wdf_data_r1[390]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[391] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[391]),
        .Q(app_wdf_data_r1[391]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[392] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[392]),
        .Q(app_wdf_data_r1[392]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[393] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[393]),
        .Q(app_wdf_data_r1[393]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[394] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[394]),
        .Q(app_wdf_data_r1[394]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[395] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[395]),
        .Q(app_wdf_data_r1[395]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[396] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[396]),
        .Q(app_wdf_data_r1[396]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[397] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[397]),
        .Q(app_wdf_data_r1[397]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[398] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[398]),
        .Q(app_wdf_data_r1[398]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[399] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[399]),
        .Q(app_wdf_data_r1[399]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[39] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[39]),
        .Q(app_wdf_data_r1[39]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[3] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[3]),
        .Q(app_wdf_data_r1[3]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[400] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[400]),
        .Q(app_wdf_data_r1[400]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[401] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[401]),
        .Q(app_wdf_data_r1[401]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[402] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[402]),
        .Q(app_wdf_data_r1[402]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[403] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[403]),
        .Q(app_wdf_data_r1[403]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[404] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[404]),
        .Q(app_wdf_data_r1[404]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[405] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[405]),
        .Q(app_wdf_data_r1[405]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[406] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[406]),
        .Q(app_wdf_data_r1[406]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[407] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[407]),
        .Q(app_wdf_data_r1[407]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[408] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[408]),
        .Q(app_wdf_data_r1[408]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[409] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[409]),
        .Q(app_wdf_data_r1[409]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[40] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[40]),
        .Q(app_wdf_data_r1[40]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[410] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[410]),
        .Q(app_wdf_data_r1[410]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[411] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[411]),
        .Q(app_wdf_data_r1[411]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[412] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[412]),
        .Q(app_wdf_data_r1[412]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[413] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[413]),
        .Q(app_wdf_data_r1[413]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[414] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[414]),
        .Q(app_wdf_data_r1[414]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[415] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[415]),
        .Q(app_wdf_data_r1[415]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[416] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[416]),
        .Q(app_wdf_data_r1[416]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[417] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[417]),
        .Q(app_wdf_data_r1[417]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[418] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[418]),
        .Q(app_wdf_data_r1[418]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[419] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[419]),
        .Q(app_wdf_data_r1[419]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[41] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[41]),
        .Q(app_wdf_data_r1[41]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[420] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[420]),
        .Q(app_wdf_data_r1[420]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[421] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[421]),
        .Q(app_wdf_data_r1[421]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[422] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[422]),
        .Q(app_wdf_data_r1[422]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[423] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[423]),
        .Q(app_wdf_data_r1[423]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[424] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[424]),
        .Q(app_wdf_data_r1[424]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[425] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[425]),
        .Q(app_wdf_data_r1[425]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[426] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[426]),
        .Q(app_wdf_data_r1[426]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[427] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[427]),
        .Q(app_wdf_data_r1[427]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[428] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[428]),
        .Q(app_wdf_data_r1[428]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[429] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[429]),
        .Q(app_wdf_data_r1[429]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[42] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[42]),
        .Q(app_wdf_data_r1[42]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[430] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[430]),
        .Q(app_wdf_data_r1[430]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[431] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[431]),
        .Q(app_wdf_data_r1[431]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[432] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[432]),
        .Q(app_wdf_data_r1[432]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[433] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[433]),
        .Q(app_wdf_data_r1[433]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[434] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[434]),
        .Q(app_wdf_data_r1[434]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[435] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[435]),
        .Q(app_wdf_data_r1[435]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[436] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[436]),
        .Q(app_wdf_data_r1[436]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[437] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[437]),
        .Q(app_wdf_data_r1[437]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[438] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[438]),
        .Q(app_wdf_data_r1[438]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[439] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[439]),
        .Q(app_wdf_data_r1[439]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[43] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[43]),
        .Q(app_wdf_data_r1[43]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[440] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[440]),
        .Q(app_wdf_data_r1[440]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[441] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[441]),
        .Q(app_wdf_data_r1[441]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[442] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[442]),
        .Q(app_wdf_data_r1[442]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[443] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[443]),
        .Q(app_wdf_data_r1[443]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[444] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[444]),
        .Q(app_wdf_data_r1[444]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[445] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[445]),
        .Q(app_wdf_data_r1[445]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[446] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[446]),
        .Q(app_wdf_data_r1[446]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[447] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[447]),
        .Q(app_wdf_data_r1[447]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[448] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[448]),
        .Q(app_wdf_data_r1[448]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[449] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[449]),
        .Q(app_wdf_data_r1[449]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[44] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[44]),
        .Q(app_wdf_data_r1[44]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[450] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[450]),
        .Q(app_wdf_data_r1[450]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[451] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[451]),
        .Q(app_wdf_data_r1[451]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[452] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[452]),
        .Q(app_wdf_data_r1[452]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[453] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[453]),
        .Q(app_wdf_data_r1[453]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[454] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[454]),
        .Q(app_wdf_data_r1[454]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[455] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[455]),
        .Q(app_wdf_data_r1[455]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[456] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[456]),
        .Q(app_wdf_data_r1[456]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[457] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[457]),
        .Q(app_wdf_data_r1[457]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[458] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[458]),
        .Q(app_wdf_data_r1[458]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[459] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[459]),
        .Q(app_wdf_data_r1[459]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[45] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[45]),
        .Q(app_wdf_data_r1[45]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[460] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[460]),
        .Q(app_wdf_data_r1[460]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[461] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[461]),
        .Q(app_wdf_data_r1[461]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[462] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[462]),
        .Q(app_wdf_data_r1[462]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[463] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[463]),
        .Q(app_wdf_data_r1[463]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[464] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[464]),
        .Q(app_wdf_data_r1[464]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[465] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[465]),
        .Q(app_wdf_data_r1[465]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[466] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[466]),
        .Q(app_wdf_data_r1[466]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[467] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[467]),
        .Q(app_wdf_data_r1[467]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[468] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[468]),
        .Q(app_wdf_data_r1[468]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[469] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[469]),
        .Q(app_wdf_data_r1[469]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[46] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[46]),
        .Q(app_wdf_data_r1[46]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[470] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[470]),
        .Q(app_wdf_data_r1[470]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[471] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[471]),
        .Q(app_wdf_data_r1[471]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[472] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[472]),
        .Q(app_wdf_data_r1[472]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[473] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[473]),
        .Q(app_wdf_data_r1[473]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[474] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[474]),
        .Q(app_wdf_data_r1[474]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[475] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[475]),
        .Q(app_wdf_data_r1[475]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[476] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[476]),
        .Q(app_wdf_data_r1[476]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[477] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[477]),
        .Q(app_wdf_data_r1[477]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[478] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[478]),
        .Q(app_wdf_data_r1[478]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[479] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[479]),
        .Q(app_wdf_data_r1[479]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[47] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[47]),
        .Q(app_wdf_data_r1[47]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[480] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[480]),
        .Q(app_wdf_data_r1[480]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[481] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[481]),
        .Q(app_wdf_data_r1[481]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[482] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[482]),
        .Q(app_wdf_data_r1[482]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[483] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[483]),
        .Q(app_wdf_data_r1[483]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[484] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[484]),
        .Q(app_wdf_data_r1[484]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[485] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[485]),
        .Q(app_wdf_data_r1[485]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[486] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[486]),
        .Q(app_wdf_data_r1[486]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[487] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[487]),
        .Q(app_wdf_data_r1[487]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[488] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[488]),
        .Q(app_wdf_data_r1[488]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[489] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[489]),
        .Q(app_wdf_data_r1[489]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[48] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[48]),
        .Q(app_wdf_data_r1[48]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[490] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[490]),
        .Q(app_wdf_data_r1[490]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[491] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[491]),
        .Q(app_wdf_data_r1[491]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[492] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[492]),
        .Q(app_wdf_data_r1[492]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[493] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[493]),
        .Q(app_wdf_data_r1[493]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[494] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[494]),
        .Q(app_wdf_data_r1[494]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[495] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[495]),
        .Q(app_wdf_data_r1[495]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[496] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[496]),
        .Q(app_wdf_data_r1[496]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[497] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[497]),
        .Q(app_wdf_data_r1[497]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[498] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[498]),
        .Q(app_wdf_data_r1[498]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[499] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[499]),
        .Q(app_wdf_data_r1[499]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[49] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[49]),
        .Q(app_wdf_data_r1[49]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[4] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[4]),
        .Q(app_wdf_data_r1[4]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[500] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[500]),
        .Q(app_wdf_data_r1[500]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[501] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[501]),
        .Q(app_wdf_data_r1[501]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[502] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[502]),
        .Q(app_wdf_data_r1[502]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[503] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[503]),
        .Q(app_wdf_data_r1[503]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[504] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[504]),
        .Q(app_wdf_data_r1[504]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[505] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[505]),
        .Q(app_wdf_data_r1[505]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[506] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[506]),
        .Q(app_wdf_data_r1[506]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[507] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[507]),
        .Q(app_wdf_data_r1[507]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[508] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[508]),
        .Q(app_wdf_data_r1[508]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[509] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[509]),
        .Q(app_wdf_data_r1[509]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[50] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[50]),
        .Q(app_wdf_data_r1[50]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[510] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[510]),
        .Q(app_wdf_data_r1[510]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[511] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[511]),
        .Q(app_wdf_data_r1[511]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[51] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[51]),
        .Q(app_wdf_data_r1[51]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[52] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[52]),
        .Q(app_wdf_data_r1[52]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[53] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[53]),
        .Q(app_wdf_data_r1[53]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[54] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[54]),
        .Q(app_wdf_data_r1[54]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[55] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[55]),
        .Q(app_wdf_data_r1[55]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[56] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[56]),
        .Q(app_wdf_data_r1[56]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[57] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[57]),
        .Q(app_wdf_data_r1[57]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[58] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[58]),
        .Q(app_wdf_data_r1[58]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[59] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[59]),
        .Q(app_wdf_data_r1[59]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[5] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[5]),
        .Q(app_wdf_data_r1[5]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[60] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[60]),
        .Q(app_wdf_data_r1[60]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[61] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[61]),
        .Q(app_wdf_data_r1[61]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[62] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[62]),
        .Q(app_wdf_data_r1[62]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[63] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[63]),
        .Q(app_wdf_data_r1[63]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[64] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[64]),
        .Q(app_wdf_data_r1[64]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[65] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[65]),
        .Q(app_wdf_data_r1[65]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[66] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[66]),
        .Q(app_wdf_data_r1[66]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[67] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[67]),
        .Q(app_wdf_data_r1[67]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[68] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[68]),
        .Q(app_wdf_data_r1[68]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[69] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[69]),
        .Q(app_wdf_data_r1[69]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[6] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[6]),
        .Q(app_wdf_data_r1[6]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[70] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[70]),
        .Q(app_wdf_data_r1[70]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[71] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[71]),
        .Q(app_wdf_data_r1[71]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[72] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[72]),
        .Q(app_wdf_data_r1[72]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[73] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[73]),
        .Q(app_wdf_data_r1[73]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[74] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[74]),
        .Q(app_wdf_data_r1[74]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[75] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[75]),
        .Q(app_wdf_data_r1[75]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[76] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[76]),
        .Q(app_wdf_data_r1[76]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[77] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[77]),
        .Q(app_wdf_data_r1[77]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[78] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[78]),
        .Q(app_wdf_data_r1[78]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[79] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[79]),
        .Q(app_wdf_data_r1[79]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[7] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[7]),
        .Q(app_wdf_data_r1[7]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[80] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[80]),
        .Q(app_wdf_data_r1[80]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[81] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[81]),
        .Q(app_wdf_data_r1[81]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[82] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[82]),
        .Q(app_wdf_data_r1[82]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[83] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[83]),
        .Q(app_wdf_data_r1[83]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[84] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[84]),
        .Q(app_wdf_data_r1[84]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[85] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[85]),
        .Q(app_wdf_data_r1[85]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[86] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[86]),
        .Q(app_wdf_data_r1[86]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[87] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[87]),
        .Q(app_wdf_data_r1[87]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[88] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[88]),
        .Q(app_wdf_data_r1[88]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[89] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[89]),
        .Q(app_wdf_data_r1[89]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[8] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[8]),
        .Q(app_wdf_data_r1[8]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[90] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[90]),
        .Q(app_wdf_data_r1[90]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[91] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[91]),
        .Q(app_wdf_data_r1[91]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[92] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[92]),
        .Q(app_wdf_data_r1[92]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[93] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[93]),
        .Q(app_wdf_data_r1[93]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[94] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[94]),
        .Q(app_wdf_data_r1[94]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[95] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[95]),
        .Q(app_wdf_data_r1[95]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[96] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[96]),
        .Q(app_wdf_data_r1[96]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[97] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[97]),
        .Q(app_wdf_data_r1[97]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[98] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[98]),
        .Q(app_wdf_data_r1[98]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[99] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[99]),
        .Q(app_wdf_data_r1[99]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[9] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(c0_ddr4_app_wdf_data[9]),
        .Q(app_wdf_data_r1[9]),
        .R(1'b0));
  FDRE app_wdf_end_r1_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy7),
        .D(c0_ddr4_app_wdf_end),
        .Q(app_wdf_end_r1),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \app_wdf_mask_r1_reg[0] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[0]),
        .Q(app_wdf_mask_r1[0]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[10] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[10]),
        .Q(app_wdf_mask_r1[10]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[11] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[11]),
        .Q(app_wdf_mask_r1[11]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[12] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[12]),
        .Q(app_wdf_mask_r1[12]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[13] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[13]),
        .Q(app_wdf_mask_r1[13]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[14] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[14]),
        .Q(app_wdf_mask_r1[14]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[15] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[15]),
        .Q(app_wdf_mask_r1[15]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[16] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[16]),
        .Q(app_wdf_mask_r1[16]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[17] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[17]),
        .Q(app_wdf_mask_r1[17]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[18] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[18]),
        .Q(app_wdf_mask_r1[18]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[19] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[19]),
        .Q(app_wdf_mask_r1[19]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[1] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[1]),
        .Q(app_wdf_mask_r1[1]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[20] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[20]),
        .Q(app_wdf_mask_r1[20]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[21] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[21]),
        .Q(app_wdf_mask_r1[21]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[22] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[22]),
        .Q(app_wdf_mask_r1[22]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[23] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[23]),
        .Q(app_wdf_mask_r1[23]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[24] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[24]),
        .Q(app_wdf_mask_r1[24]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[25] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[25]),
        .Q(app_wdf_mask_r1[25]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[26] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[26]),
        .Q(app_wdf_mask_r1[26]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[27] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[27]),
        .Q(app_wdf_mask_r1[27]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[28] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[28]),
        .Q(app_wdf_mask_r1[28]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[29] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[29]),
        .Q(app_wdf_mask_r1[29]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[2] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[2]),
        .Q(app_wdf_mask_r1[2]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[30] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[30]),
        .Q(app_wdf_mask_r1[30]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[31] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[31]),
        .Q(app_wdf_mask_r1[31]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[32] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[32]),
        .Q(app_wdf_mask_r1[32]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[33] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[33]),
        .Q(app_wdf_mask_r1[33]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[34] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[34]),
        .Q(app_wdf_mask_r1[34]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[35] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[35]),
        .Q(app_wdf_mask_r1[35]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[36] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[36]),
        .Q(app_wdf_mask_r1[36]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[37] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[37]),
        .Q(app_wdf_mask_r1[37]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[38] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[38]),
        .Q(app_wdf_mask_r1[38]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[39] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[39]),
        .Q(app_wdf_mask_r1[39]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[3] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[3]),
        .Q(app_wdf_mask_r1[3]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[40] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[40]),
        .Q(app_wdf_mask_r1[40]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[41] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[41]),
        .Q(app_wdf_mask_r1[41]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[42] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[42]),
        .Q(app_wdf_mask_r1[42]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[43] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[43]),
        .Q(app_wdf_mask_r1[43]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[44] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[44]),
        .Q(app_wdf_mask_r1[44]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[45] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[45]),
        .Q(app_wdf_mask_r1[45]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[46] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[46]),
        .Q(app_wdf_mask_r1[46]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[47] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[47]),
        .Q(app_wdf_mask_r1[47]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[48] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[48]),
        .Q(app_wdf_mask_r1[48]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[49] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[49]),
        .Q(app_wdf_mask_r1[49]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[4] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[4]),
        .Q(app_wdf_mask_r1[4]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[50] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[50]),
        .Q(app_wdf_mask_r1[50]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[51] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[51]),
        .Q(app_wdf_mask_r1[51]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[52] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[52]),
        .Q(app_wdf_mask_r1[52]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[53] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[53]),
        .Q(app_wdf_mask_r1[53]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[54] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[54]),
        .Q(app_wdf_mask_r1[54]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[55] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[55]),
        .Q(app_wdf_mask_r1[55]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[56] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[56]),
        .Q(app_wdf_mask_r1[56]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[57] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[57]),
        .Q(app_wdf_mask_r1[57]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[58] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[58]),
        .Q(app_wdf_mask_r1[58]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[59] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[59]),
        .Q(app_wdf_mask_r1[59]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[5] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[5]),
        .Q(app_wdf_mask_r1[5]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[60] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[60]),
        .Q(app_wdf_mask_r1[60]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[61] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[61]),
        .Q(app_wdf_mask_r1[61]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[62] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[62]),
        .Q(app_wdf_mask_r1[62]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[63] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[63]),
        .Q(app_wdf_mask_r1[63]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[6] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[6]),
        .Q(app_wdf_mask_r1[6]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[7] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[7]),
        .Q(app_wdf_mask_r1[7]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[8] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[8]),
        .Q(app_wdf_mask_r1[8]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[9] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy5),
        .D(c0_ddr4_app_wdf_mask[9]),
        .Q(app_wdf_mask_r1[9]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4040404440444044)) 
    app_wdf_rdy_r_copy1_i_1
       (.I0(\wr_data_indx_r_reg[1]_0 ),
        .I1(\wr_data_indx_r_reg[0]_0 [1]),
        .I2(rd_data_upd_indx_r),
        .I3(p_0_in2_in),
        .I4(p_11_in),
        .I5(p_0_in12_in),
        .O(app_wdf_rdy_r_copy1_i_1_n_0));
  (* KEEP = "yes" *) 
  FDRE app_wdf_rdy_r_copy1_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(app_wdf_rdy_r_copy1_i_1_n_0),
        .Q(app_wdf_rdy_r_copy1),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE app_wdf_rdy_r_copy2_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(app_wdf_rdy_r_copy1_i_1_n_0),
        .Q(app_wdf_rdy_r_copy2),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE app_wdf_rdy_r_copy3_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(app_wdf_rdy_r_copy1_i_1_n_0),
        .Q(app_wdf_rdy_r_copy3),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE app_wdf_rdy_r_copy4_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(app_wdf_rdy_r_copy1_i_1_n_0),
        .Q(app_wdf_rdy_r_copy4),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE app_wdf_rdy_r_copy5_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(app_wdf_rdy_r_copy1_i_1_n_0),
        .Q(app_wdf_rdy_r_copy5),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE app_wdf_rdy_r_copy6_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(app_wdf_rdy_r_copy1_i_1_n_0),
        .Q(app_wdf_rdy_r_copy6),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE app_wdf_rdy_r_copy7_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(app_wdf_rdy_r_copy1_i_1_n_0),
        .Q(app_wdf_rdy_r_copy7),
        .R(1'b0));
  (* KEEP = "yes" *) 
  FDRE app_wdf_rdy_r_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(app_wdf_rdy_r_copy1_i_1_n_0),
        .Q(app_wdf_rdy_r),
        .R(1'b0));
  FDRE app_wdf_wren_r1_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(app_wdf_rdy_r_copy6),
        .D(c0_ddr4_app_wdf_wren),
        .Q(app_wdf_wren_r1),
        .R(\wr_data_indx_r_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair3104" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \data_buf_addr_cnt_r[0]_i_1 
       (.I0(data_buf_addr_cnt_r_reg[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair3104" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \data_buf_addr_cnt_r[1]_i_1 
       (.I0(data_buf_addr_cnt_r_reg[0]),
        .I1(data_buf_addr_cnt_r_reg[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair3101" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \data_buf_addr_cnt_r[2]_i_1 
       (.I0(data_buf_addr_cnt_r_reg[0]),
        .I1(data_buf_addr_cnt_r_reg[1]),
        .I2(data_buf_addr_cnt_r_reg[2]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair3101" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \data_buf_addr_cnt_r[3]_i_2 
       (.I0(data_buf_addr_cnt_r_reg[2]),
        .I1(data_buf_addr_cnt_r_reg[1]),
        .I2(data_buf_addr_cnt_r_reg[0]),
        .I3(data_buf_addr_cnt_r_reg[3]),
        .O(p_0_in__0[3]));
  FDRE \data_buf_addr_cnt_r_reg[0] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(wr_accepted),
        .D(p_0_in__0[0]),
        .Q(data_buf_addr_cnt_r_reg[0]),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \data_buf_addr_cnt_r_reg[1] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(wr_accepted),
        .D(p_0_in__0[1]),
        .Q(data_buf_addr_cnt_r_reg[1]),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \data_buf_addr_cnt_r_reg[2] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(wr_accepted),
        .D(p_0_in__0[2]),
        .Q(data_buf_addr_cnt_r_reg[2]),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \data_buf_addr_cnt_r_reg[3] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(wr_accepted),
        .D(p_0_in__0[3]),
        .Q(data_buf_addr_cnt_r_reg[3]),
        .R(\wr_data_indx_r_reg[1]_0 ));
  LUT4 #(
    .INIT(16'hFF80)) 
    \occ_cnt[0]_i_1 
       (.I0(app_wdf_end_r1),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_rdy_r_copy1),
        .I3(\occ_cnt_reg_n_0_[1] ),
        .O(p_1_in[0]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[10]_i_1 
       (.I0(\occ_cnt_reg_n_0_[9] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(\occ_cnt_reg_n_0_[11] ),
        .O(p_1_in[10]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[11]_i_1 
       (.I0(\occ_cnt_reg_n_0_[10] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(\occ_cnt_reg_n_0_[12] ),
        .O(p_1_in[11]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[12]_i_1 
       (.I0(\occ_cnt_reg_n_0_[11] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(\occ_cnt_reg_n_0_[13] ),
        .O(p_1_in[12]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[13]_i_1 
       (.I0(\occ_cnt_reg_n_0_[12] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(p_0_in12_in),
        .O(p_1_in[13]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[14]_i_1 
       (.I0(\occ_cnt_reg_n_0_[13] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(p_0_in2_in),
        .O(p_1_in[14]));
  LUT4 #(
    .INIT(16'h6AAA)) 
    \occ_cnt[15]_i_1 
       (.I0(rd_data_upd_indx_r),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_rdy_r_copy1),
        .O(\occ_cnt[15]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \occ_cnt[15]_i_2 
       (.I0(app_wdf_rdy_r_copy1),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(p_0_in12_in),
        .O(p_1_in[15]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[1]_i_1 
       (.I0(\occ_cnt_reg_n_0_[0] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(\occ_cnt_reg_n_0_[2] ),
        .O(p_1_in[1]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[2]_i_1 
       (.I0(\occ_cnt_reg_n_0_[1] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(\occ_cnt_reg_n_0_[3] ),
        .O(p_1_in[2]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[3]_i_1 
       (.I0(\occ_cnt_reg_n_0_[2] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(\occ_cnt_reg_n_0_[4] ),
        .O(p_1_in[3]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[4]_i_1 
       (.I0(\occ_cnt_reg_n_0_[3] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(\occ_cnt_reg_n_0_[5] ),
        .O(p_1_in[4]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[5]_i_1 
       (.I0(\occ_cnt_reg_n_0_[4] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(\occ_cnt_reg_n_0_[6] ),
        .O(p_1_in[5]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[6]_i_1 
       (.I0(\occ_cnt_reg_n_0_[5] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(\occ_cnt_reg_n_0_[7] ),
        .O(p_1_in[6]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[7]_i_1 
       (.I0(\occ_cnt_reg_n_0_[6] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(\occ_cnt_reg_n_0_[8] ),
        .O(p_1_in[7]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[8]_i_1 
       (.I0(\occ_cnt_reg_n_0_[7] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(\occ_cnt_reg_n_0_[9] ),
        .O(p_1_in[8]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occ_cnt[9]_i_1 
       (.I0(\occ_cnt_reg_n_0_[8] ),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_end_r1),
        .I4(\occ_cnt_reg_n_0_[10] ),
        .O(p_1_in[9]));
  FDRE \occ_cnt_reg[0] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[0]),
        .Q(\occ_cnt_reg_n_0_[0] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[10] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[10]),
        .Q(\occ_cnt_reg_n_0_[10] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[11] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[11]),
        .Q(\occ_cnt_reg_n_0_[11] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[12] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[12]),
        .Q(\occ_cnt_reg_n_0_[12] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[13] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[13]),
        .Q(\occ_cnt_reg_n_0_[13] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[14] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[14]),
        .Q(p_0_in12_in),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[15] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[15]),
        .Q(p_0_in2_in),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[1] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[1]),
        .Q(\occ_cnt_reg_n_0_[1] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[2] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[2]),
        .Q(\occ_cnt_reg_n_0_[2] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[3] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[3]),
        .Q(\occ_cnt_reg_n_0_[3] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[4] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[4]),
        .Q(\occ_cnt_reg_n_0_[4] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[5] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[5]),
        .Q(\occ_cnt_reg_n_0_[5] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[6] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[6]),
        .Q(\occ_cnt_reg_n_0_[6] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[7] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[7]),
        .Q(\occ_cnt_reg_n_0_[7] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[8] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[8]),
        .Q(\occ_cnt_reg_n_0_[8] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \occ_cnt_reg[9] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[9]),
        .Q(\occ_cnt_reg_n_0_[9] ),
        .R(\wr_data_indx_r_reg[1]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \rams[0].RAM32M0 
       (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ADDRB({1'b0,data_buf_addr_cnt_r_reg}),
        .ADDRC({1'b0,wr_data_indx_r_reg}),
        .ADDRD({1'b0,\rams[0].RAM32M0_0 }),
        .DIA({1'b0,1'b0}),
        .DIB(pointer_wr_data[1:0]),
        .DIC(pointer_wr_data[1:0]),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_rams[0].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(wr_data_buf_addr[1:0]),
        .DOC(wr_data_pntr[1:0]),
        .DOD(\NLW_rams[0].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(pointer_we));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \rams[1].RAM32M0 
       (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ADDRB({1'b0,data_buf_addr_cnt_r_reg}),
        .ADDRC({1'b0,wr_data_indx_r_reg}),
        .ADDRD({1'b0,\rams[0].RAM32M0_0 }),
        .DIA({1'b0,1'b0}),
        .DIB(pointer_wr_data[3:2]),
        .DIC(pointer_wr_data[3:2]),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_rams[1].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(wr_data_buf_addr[3:2]),
        .DOC(wr_data_pntr[3:2]),
        .DOD(\NLW_rams[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(pointer_we));
  (* SOFT_HLUTNM = "soft_lutpair3103" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rd_data_indx_r[0]_i_1 
       (.I0(Q[0]),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair3103" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_data_indx_r[1]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair3100" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rd_data_indx_r[2]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair3100" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \rd_data_indx_r[3]_i_2 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(p_0_in__1[3]));
  FDRE \rd_data_indx_r_reg[0] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\rd_data_indx_r_reg[3]_1 ),
        .D(p_0_in__1[0]),
        .Q(Q[0]),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \rd_data_indx_r_reg[1] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\rd_data_indx_r_reg[3]_1 ),
        .D(p_0_in__1[1]),
        .Q(Q[1]),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \rd_data_indx_r_reg[2] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\rd_data_indx_r_reg[3]_1 ),
        .D(p_0_in__1[2]),
        .Q(Q[2]),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \rd_data_indx_r_reg[3] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(\rd_data_indx_r_reg[3]_1 ),
        .D(p_0_in__1[3]),
        .Q(Q[3]),
        .R(\wr_data_indx_r_reg[1]_0 ));
  (* KEEP = "yes" *) 
  FDRE rd_data_upd_indx_cpy_r_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\rd_data_indx_r_reg[3]_1 ),
        .Q(rd_data_upd_indx_cpy_r),
        .R(\wr_data_indx_r_reg[1]_0 ));
  (* KEEP = "yes" *) 
  FDRE rd_data_upd_indx_r_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\rd_data_indx_r_reg[3]_1 ),
        .Q(rd_data_upd_indx_r),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE wb_wr_data_addr0_r_reg
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wb_wr_data_addr0_ns),
        .Q(wb_wr_data_addr0_r),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \wb_wr_data_addr_r_reg[1] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wb_wr_data_addr_w[1]),
        .Q(wb_wr_data_addr_r[1]),
        .R(1'b0));
  FDRE \wb_wr_data_addr_r_reg[2] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wb_wr_data_addr_w[2]),
        .Q(wb_wr_data_addr_r[2]),
        .R(1'b0));
  FDRE \wb_wr_data_addr_r_reg[3] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wb_wr_data_addr_w[3]),
        .Q(wb_wr_data_addr_r[3]),
        .R(1'b0));
  FDRE \wb_wr_data_addr_r_reg[4] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wb_wr_data_addr_w[4]),
        .Q(wb_wr_data_addr_r[4]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[0] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[0]),
        .Q(\wr_buf_out_data_reg[575]_0 [0]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[100] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[100]),
        .Q(\wr_buf_out_data_reg[575]_0 [100]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[101] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[101]),
        .Q(\wr_buf_out_data_reg[575]_0 [101]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[102] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[102]),
        .Q(\wr_buf_out_data_reg[575]_0 [102]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[103] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[103]),
        .Q(\wr_buf_out_data_reg[575]_0 [103]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[104] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[104]),
        .Q(\wr_buf_out_data_reg[575]_0 [104]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[105] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[105]),
        .Q(\wr_buf_out_data_reg[575]_0 [105]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[106] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[106]),
        .Q(\wr_buf_out_data_reg[575]_0 [106]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[107] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[107]),
        .Q(\wr_buf_out_data_reg[575]_0 [107]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[108] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[108]),
        .Q(\wr_buf_out_data_reg[575]_0 [108]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[109] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[109]),
        .Q(\wr_buf_out_data_reg[575]_0 [109]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[10] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[10]),
        .Q(\wr_buf_out_data_reg[575]_0 [10]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[110] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[110]),
        .Q(\wr_buf_out_data_reg[575]_0 [110]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[111] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[111]),
        .Q(\wr_buf_out_data_reg[575]_0 [111]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[112] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[112]),
        .Q(\wr_buf_out_data_reg[575]_0 [112]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[113] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[113]),
        .Q(\wr_buf_out_data_reg[575]_0 [113]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[114] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[114]),
        .Q(\wr_buf_out_data_reg[575]_0 [114]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[115] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[115]),
        .Q(\wr_buf_out_data_reg[575]_0 [115]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[116] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[116]),
        .Q(\wr_buf_out_data_reg[575]_0 [116]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[117] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[117]),
        .Q(\wr_buf_out_data_reg[575]_0 [117]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[118] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[118]),
        .Q(\wr_buf_out_data_reg[575]_0 [118]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[119] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[119]),
        .Q(\wr_buf_out_data_reg[575]_0 [119]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[11] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[11]),
        .Q(\wr_buf_out_data_reg[575]_0 [11]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[120] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[120]),
        .Q(\wr_buf_out_data_reg[575]_0 [120]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[121] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[121]),
        .Q(\wr_buf_out_data_reg[575]_0 [121]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[122] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[122]),
        .Q(\wr_buf_out_data_reg[575]_0 [122]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[123] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[123]),
        .Q(\wr_buf_out_data_reg[575]_0 [123]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[124] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[124]),
        .Q(\wr_buf_out_data_reg[575]_0 [124]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[125] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[125]),
        .Q(\wr_buf_out_data_reg[575]_0 [125]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[126] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[126]),
        .Q(\wr_buf_out_data_reg[575]_0 [126]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[127] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[127]),
        .Q(\wr_buf_out_data_reg[575]_0 [127]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[128] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[128]),
        .Q(\wr_buf_out_data_reg[575]_0 [128]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[129] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[129]),
        .Q(\wr_buf_out_data_reg[575]_0 [129]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[12] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[12]),
        .Q(\wr_buf_out_data_reg[575]_0 [12]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[130] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[130]),
        .Q(\wr_buf_out_data_reg[575]_0 [130]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[131] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[131]),
        .Q(\wr_buf_out_data_reg[575]_0 [131]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[132] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[132]),
        .Q(\wr_buf_out_data_reg[575]_0 [132]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[133] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[133]),
        .Q(\wr_buf_out_data_reg[575]_0 [133]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[134] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[134]),
        .Q(\wr_buf_out_data_reg[575]_0 [134]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[135] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[135]),
        .Q(\wr_buf_out_data_reg[575]_0 [135]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[136] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[136]),
        .Q(\wr_buf_out_data_reg[575]_0 [136]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[137] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[137]),
        .Q(\wr_buf_out_data_reg[575]_0 [137]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[138] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[138]),
        .Q(\wr_buf_out_data_reg[575]_0 [138]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[139] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[139]),
        .Q(\wr_buf_out_data_reg[575]_0 [139]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[13] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[13]),
        .Q(\wr_buf_out_data_reg[575]_0 [13]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[140] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[140]),
        .Q(\wr_buf_out_data_reg[575]_0 [140]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[141] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[141]),
        .Q(\wr_buf_out_data_reg[575]_0 [141]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[142] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[142]),
        .Q(\wr_buf_out_data_reg[575]_0 [142]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[143] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[143]),
        .Q(\wr_buf_out_data_reg[575]_0 [143]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[144] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[144]),
        .Q(\wr_buf_out_data_reg[575]_0 [144]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[145] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[145]),
        .Q(\wr_buf_out_data_reg[575]_0 [145]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[146] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[146]),
        .Q(\wr_buf_out_data_reg[575]_0 [146]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[147] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[147]),
        .Q(\wr_buf_out_data_reg[575]_0 [147]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[148] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[148]),
        .Q(\wr_buf_out_data_reg[575]_0 [148]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[149] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[149]),
        .Q(\wr_buf_out_data_reg[575]_0 [149]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[14] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[14]),
        .Q(\wr_buf_out_data_reg[575]_0 [14]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[150] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[150]),
        .Q(\wr_buf_out_data_reg[575]_0 [150]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[151] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[151]),
        .Q(\wr_buf_out_data_reg[575]_0 [151]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[152] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[152]),
        .Q(\wr_buf_out_data_reg[575]_0 [152]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[153] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[153]),
        .Q(\wr_buf_out_data_reg[575]_0 [153]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[154] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[154]),
        .Q(\wr_buf_out_data_reg[575]_0 [154]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[155] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[155]),
        .Q(\wr_buf_out_data_reg[575]_0 [155]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[156] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[156]),
        .Q(\wr_buf_out_data_reg[575]_0 [156]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[157] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[157]),
        .Q(\wr_buf_out_data_reg[575]_0 [157]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[158] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[158]),
        .Q(\wr_buf_out_data_reg[575]_0 [158]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[159] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[159]),
        .Q(\wr_buf_out_data_reg[575]_0 [159]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[15] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[15]),
        .Q(\wr_buf_out_data_reg[575]_0 [15]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[160] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[160]),
        .Q(\wr_buf_out_data_reg[575]_0 [160]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[161] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[161]),
        .Q(\wr_buf_out_data_reg[575]_0 [161]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[162] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[162]),
        .Q(\wr_buf_out_data_reg[575]_0 [162]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[163] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[163]),
        .Q(\wr_buf_out_data_reg[575]_0 [163]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[164] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[164]),
        .Q(\wr_buf_out_data_reg[575]_0 [164]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[165] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[165]),
        .Q(\wr_buf_out_data_reg[575]_0 [165]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[166] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[166]),
        .Q(\wr_buf_out_data_reg[575]_0 [166]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[167] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[167]),
        .Q(\wr_buf_out_data_reg[575]_0 [167]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[168] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[168]),
        .Q(\wr_buf_out_data_reg[575]_0 [168]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[169] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[169]),
        .Q(\wr_buf_out_data_reg[575]_0 [169]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[16] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[16]),
        .Q(\wr_buf_out_data_reg[575]_0 [16]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[170] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[170]),
        .Q(\wr_buf_out_data_reg[575]_0 [170]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[171] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[171]),
        .Q(\wr_buf_out_data_reg[575]_0 [171]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[172] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[172]),
        .Q(\wr_buf_out_data_reg[575]_0 [172]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[173] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[173]),
        .Q(\wr_buf_out_data_reg[575]_0 [173]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[174] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[174]),
        .Q(\wr_buf_out_data_reg[575]_0 [174]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[175] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[175]),
        .Q(\wr_buf_out_data_reg[575]_0 [175]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[176] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[176]),
        .Q(\wr_buf_out_data_reg[575]_0 [176]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[177] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[177]),
        .Q(\wr_buf_out_data_reg[575]_0 [177]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[178] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[178]),
        .Q(\wr_buf_out_data_reg[575]_0 [178]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[179] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[179]),
        .Q(\wr_buf_out_data_reg[575]_0 [179]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[17] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[17]),
        .Q(\wr_buf_out_data_reg[575]_0 [17]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[180] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[180]),
        .Q(\wr_buf_out_data_reg[575]_0 [180]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[181] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[181]),
        .Q(\wr_buf_out_data_reg[575]_0 [181]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[182] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[182]),
        .Q(\wr_buf_out_data_reg[575]_0 [182]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[183] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[183]),
        .Q(\wr_buf_out_data_reg[575]_0 [183]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[184] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[184]),
        .Q(\wr_buf_out_data_reg[575]_0 [184]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[185] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[185]),
        .Q(\wr_buf_out_data_reg[575]_0 [185]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[186] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[186]),
        .Q(\wr_buf_out_data_reg[575]_0 [186]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[187] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[187]),
        .Q(\wr_buf_out_data_reg[575]_0 [187]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[188] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[188]),
        .Q(\wr_buf_out_data_reg[575]_0 [188]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[189] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[189]),
        .Q(\wr_buf_out_data_reg[575]_0 [189]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[18] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[18]),
        .Q(\wr_buf_out_data_reg[575]_0 [18]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[190] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[190]),
        .Q(\wr_buf_out_data_reg[575]_0 [190]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[191] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[191]),
        .Q(\wr_buf_out_data_reg[575]_0 [191]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[192] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[192]),
        .Q(\wr_buf_out_data_reg[575]_0 [192]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[193] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[193]),
        .Q(\wr_buf_out_data_reg[575]_0 [193]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[194] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[194]),
        .Q(\wr_buf_out_data_reg[575]_0 [194]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[195] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[195]),
        .Q(\wr_buf_out_data_reg[575]_0 [195]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[196] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[196]),
        .Q(\wr_buf_out_data_reg[575]_0 [196]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[197] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[197]),
        .Q(\wr_buf_out_data_reg[575]_0 [197]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[198] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[198]),
        .Q(\wr_buf_out_data_reg[575]_0 [198]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[199] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[199]),
        .Q(\wr_buf_out_data_reg[575]_0 [199]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[19] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[19]),
        .Q(\wr_buf_out_data_reg[575]_0 [19]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[1] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[1]),
        .Q(\wr_buf_out_data_reg[575]_0 [1]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[200] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[200]),
        .Q(\wr_buf_out_data_reg[575]_0 [200]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[201] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[201]),
        .Q(\wr_buf_out_data_reg[575]_0 [201]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[202] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[202]),
        .Q(\wr_buf_out_data_reg[575]_0 [202]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[203] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[203]),
        .Q(\wr_buf_out_data_reg[575]_0 [203]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[204] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[204]),
        .Q(\wr_buf_out_data_reg[575]_0 [204]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[205] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[205]),
        .Q(\wr_buf_out_data_reg[575]_0 [205]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[206] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[206]),
        .Q(\wr_buf_out_data_reg[575]_0 [206]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[207] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[207]),
        .Q(\wr_buf_out_data_reg[575]_0 [207]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[208] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[208]),
        .Q(\wr_buf_out_data_reg[575]_0 [208]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[209] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[209]),
        .Q(\wr_buf_out_data_reg[575]_0 [209]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[20] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[20]),
        .Q(\wr_buf_out_data_reg[575]_0 [20]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[210] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[210]),
        .Q(\wr_buf_out_data_reg[575]_0 [210]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[211] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[211]),
        .Q(\wr_buf_out_data_reg[575]_0 [211]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[212] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[212]),
        .Q(\wr_buf_out_data_reg[575]_0 [212]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[213] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[213]),
        .Q(\wr_buf_out_data_reg[575]_0 [213]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[214] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[214]),
        .Q(\wr_buf_out_data_reg[575]_0 [214]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[215] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[215]),
        .Q(\wr_buf_out_data_reg[575]_0 [215]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[216] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[216]),
        .Q(\wr_buf_out_data_reg[575]_0 [216]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[217] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[217]),
        .Q(\wr_buf_out_data_reg[575]_0 [217]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[218] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[218]),
        .Q(\wr_buf_out_data_reg[575]_0 [218]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[219] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[219]),
        .Q(\wr_buf_out_data_reg[575]_0 [219]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[21] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[21]),
        .Q(\wr_buf_out_data_reg[575]_0 [21]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[220] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[220]),
        .Q(\wr_buf_out_data_reg[575]_0 [220]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[221] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[221]),
        .Q(\wr_buf_out_data_reg[575]_0 [221]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[222] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[222]),
        .Q(\wr_buf_out_data_reg[575]_0 [222]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[223] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[223]),
        .Q(\wr_buf_out_data_reg[575]_0 [223]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[224] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[224]),
        .Q(\wr_buf_out_data_reg[575]_0 [224]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[225] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[225]),
        .Q(\wr_buf_out_data_reg[575]_0 [225]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[226] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[226]),
        .Q(\wr_buf_out_data_reg[575]_0 [226]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[227] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[227]),
        .Q(\wr_buf_out_data_reg[575]_0 [227]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[228] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[228]),
        .Q(\wr_buf_out_data_reg[575]_0 [228]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[229] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[229]),
        .Q(\wr_buf_out_data_reg[575]_0 [229]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[22] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[22]),
        .Q(\wr_buf_out_data_reg[575]_0 [22]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[230] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[230]),
        .Q(\wr_buf_out_data_reg[575]_0 [230]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[231] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[231]),
        .Q(\wr_buf_out_data_reg[575]_0 [231]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[232] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[232]),
        .Q(\wr_buf_out_data_reg[575]_0 [232]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[233] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[233]),
        .Q(\wr_buf_out_data_reg[575]_0 [233]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[234] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[234]),
        .Q(\wr_buf_out_data_reg[575]_0 [234]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[235] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[235]),
        .Q(\wr_buf_out_data_reg[575]_0 [235]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[236] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[236]),
        .Q(\wr_buf_out_data_reg[575]_0 [236]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[237] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[237]),
        .Q(\wr_buf_out_data_reg[575]_0 [237]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[238] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[238]),
        .Q(\wr_buf_out_data_reg[575]_0 [238]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[239] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[239]),
        .Q(\wr_buf_out_data_reg[575]_0 [239]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[23] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[23]),
        .Q(\wr_buf_out_data_reg[575]_0 [23]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[240] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[240]),
        .Q(\wr_buf_out_data_reg[575]_0 [240]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[241] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[241]),
        .Q(\wr_buf_out_data_reg[575]_0 [241]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[242] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[242]),
        .Q(\wr_buf_out_data_reg[575]_0 [242]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[243] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[243]),
        .Q(\wr_buf_out_data_reg[575]_0 [243]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[244] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[244]),
        .Q(\wr_buf_out_data_reg[575]_0 [244]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[245] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[245]),
        .Q(\wr_buf_out_data_reg[575]_0 [245]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[246] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[246]),
        .Q(\wr_buf_out_data_reg[575]_0 [246]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[247] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[247]),
        .Q(\wr_buf_out_data_reg[575]_0 [247]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[248] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[248]),
        .Q(\wr_buf_out_data_reg[575]_0 [248]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[249] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[249]),
        .Q(\wr_buf_out_data_reg[575]_0 [249]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[24] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[24]),
        .Q(\wr_buf_out_data_reg[575]_0 [24]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[250] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[250]),
        .Q(\wr_buf_out_data_reg[575]_0 [250]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[251] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[251]),
        .Q(\wr_buf_out_data_reg[575]_0 [251]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[252] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[252]),
        .Q(\wr_buf_out_data_reg[575]_0 [252]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[253] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[253]),
        .Q(\wr_buf_out_data_reg[575]_0 [253]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[254] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[254]),
        .Q(\wr_buf_out_data_reg[575]_0 [254]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[255] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[255]),
        .Q(\wr_buf_out_data_reg[575]_0 [255]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[256] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[256]),
        .Q(\wr_buf_out_data_reg[575]_0 [256]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[257] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[257]),
        .Q(\wr_buf_out_data_reg[575]_0 [257]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[258] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[258]),
        .Q(\wr_buf_out_data_reg[575]_0 [258]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[259] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[259]),
        .Q(\wr_buf_out_data_reg[575]_0 [259]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[25] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[25]),
        .Q(\wr_buf_out_data_reg[575]_0 [25]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[260] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[260]),
        .Q(\wr_buf_out_data_reg[575]_0 [260]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[261] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[261]),
        .Q(\wr_buf_out_data_reg[575]_0 [261]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[262] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[262]),
        .Q(\wr_buf_out_data_reg[575]_0 [262]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[263] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[263]),
        .Q(\wr_buf_out_data_reg[575]_0 [263]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[264] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[264]),
        .Q(\wr_buf_out_data_reg[575]_0 [264]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[265] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[265]),
        .Q(\wr_buf_out_data_reg[575]_0 [265]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[266] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[266]),
        .Q(\wr_buf_out_data_reg[575]_0 [266]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[267] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[267]),
        .Q(\wr_buf_out_data_reg[575]_0 [267]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[268] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[268]),
        .Q(\wr_buf_out_data_reg[575]_0 [268]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[269] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[269]),
        .Q(\wr_buf_out_data_reg[575]_0 [269]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[26] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[26]),
        .Q(\wr_buf_out_data_reg[575]_0 [26]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[270] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[270]),
        .Q(\wr_buf_out_data_reg[575]_0 [270]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[271] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[271]),
        .Q(\wr_buf_out_data_reg[575]_0 [271]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[272] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[272]),
        .Q(\wr_buf_out_data_reg[575]_0 [272]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[273] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[273]),
        .Q(\wr_buf_out_data_reg[575]_0 [273]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[274] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[274]),
        .Q(\wr_buf_out_data_reg[575]_0 [274]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[275] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[275]),
        .Q(\wr_buf_out_data_reg[575]_0 [275]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[276] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[276]),
        .Q(\wr_buf_out_data_reg[575]_0 [276]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[277] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[277]),
        .Q(\wr_buf_out_data_reg[575]_0 [277]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[278] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[278]),
        .Q(\wr_buf_out_data_reg[575]_0 [278]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[279] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[279]),
        .Q(\wr_buf_out_data_reg[575]_0 [279]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[27] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[27]),
        .Q(\wr_buf_out_data_reg[575]_0 [27]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[280] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[280]),
        .Q(\wr_buf_out_data_reg[575]_0 [280]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[281] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[281]),
        .Q(\wr_buf_out_data_reg[575]_0 [281]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[282] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[282]),
        .Q(\wr_buf_out_data_reg[575]_0 [282]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[283] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[283]),
        .Q(\wr_buf_out_data_reg[575]_0 [283]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[284] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[284]),
        .Q(\wr_buf_out_data_reg[575]_0 [284]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[285] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[285]),
        .Q(\wr_buf_out_data_reg[575]_0 [285]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[286] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[286]),
        .Q(\wr_buf_out_data_reg[575]_0 [286]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[287] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[287]),
        .Q(\wr_buf_out_data_reg[575]_0 [287]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[288] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[288]),
        .Q(\wr_buf_out_data_reg[575]_0 [288]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[289] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[289]),
        .Q(\wr_buf_out_data_reg[575]_0 [289]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[28] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[28]),
        .Q(\wr_buf_out_data_reg[575]_0 [28]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[290] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[290]),
        .Q(\wr_buf_out_data_reg[575]_0 [290]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[291] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[291]),
        .Q(\wr_buf_out_data_reg[575]_0 [291]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[292] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[292]),
        .Q(\wr_buf_out_data_reg[575]_0 [292]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[293] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[293]),
        .Q(\wr_buf_out_data_reg[575]_0 [293]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[294] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[294]),
        .Q(\wr_buf_out_data_reg[575]_0 [294]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[295] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[295]),
        .Q(\wr_buf_out_data_reg[575]_0 [295]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[296] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[296]),
        .Q(\wr_buf_out_data_reg[575]_0 [296]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[297] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[297]),
        .Q(\wr_buf_out_data_reg[575]_0 [297]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[298] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[298]),
        .Q(\wr_buf_out_data_reg[575]_0 [298]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[299] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[299]),
        .Q(\wr_buf_out_data_reg[575]_0 [299]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[29] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[29]),
        .Q(\wr_buf_out_data_reg[575]_0 [29]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[2] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[2]),
        .Q(\wr_buf_out_data_reg[575]_0 [2]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[300] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[300]),
        .Q(\wr_buf_out_data_reg[575]_0 [300]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[301] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[301]),
        .Q(\wr_buf_out_data_reg[575]_0 [301]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[302] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[302]),
        .Q(\wr_buf_out_data_reg[575]_0 [302]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[303] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[303]),
        .Q(\wr_buf_out_data_reg[575]_0 [303]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[304] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[304]),
        .Q(\wr_buf_out_data_reg[575]_0 [304]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[305] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[305]),
        .Q(\wr_buf_out_data_reg[575]_0 [305]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[306] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[306]),
        .Q(\wr_buf_out_data_reg[575]_0 [306]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[307] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[307]),
        .Q(\wr_buf_out_data_reg[575]_0 [307]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[308] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[308]),
        .Q(\wr_buf_out_data_reg[575]_0 [308]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[309] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[309]),
        .Q(\wr_buf_out_data_reg[575]_0 [309]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[30] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[30]),
        .Q(\wr_buf_out_data_reg[575]_0 [30]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[310] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[310]),
        .Q(\wr_buf_out_data_reg[575]_0 [310]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[311] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[311]),
        .Q(\wr_buf_out_data_reg[575]_0 [311]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[312] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[312]),
        .Q(\wr_buf_out_data_reg[575]_0 [312]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[313] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[313]),
        .Q(\wr_buf_out_data_reg[575]_0 [313]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[314] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[314]),
        .Q(\wr_buf_out_data_reg[575]_0 [314]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[315] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[315]),
        .Q(\wr_buf_out_data_reg[575]_0 [315]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[316] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[316]),
        .Q(\wr_buf_out_data_reg[575]_0 [316]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[317] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[317]),
        .Q(\wr_buf_out_data_reg[575]_0 [317]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[318] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[318]),
        .Q(\wr_buf_out_data_reg[575]_0 [318]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[319] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[319]),
        .Q(\wr_buf_out_data_reg[575]_0 [319]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[31] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[31]),
        .Q(\wr_buf_out_data_reg[575]_0 [31]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[320] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[320]),
        .Q(\wr_buf_out_data_reg[575]_0 [320]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[321] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[321]),
        .Q(\wr_buf_out_data_reg[575]_0 [321]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[322] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[322]),
        .Q(\wr_buf_out_data_reg[575]_0 [322]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[323] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[323]),
        .Q(\wr_buf_out_data_reg[575]_0 [323]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[324] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[324]),
        .Q(\wr_buf_out_data_reg[575]_0 [324]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[325] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[325]),
        .Q(\wr_buf_out_data_reg[575]_0 [325]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[326] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[326]),
        .Q(\wr_buf_out_data_reg[575]_0 [326]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[327] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[327]),
        .Q(\wr_buf_out_data_reg[575]_0 [327]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[328] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[328]),
        .Q(\wr_buf_out_data_reg[575]_0 [328]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[329] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[329]),
        .Q(\wr_buf_out_data_reg[575]_0 [329]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[32] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[32]),
        .Q(\wr_buf_out_data_reg[575]_0 [32]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[330] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[330]),
        .Q(\wr_buf_out_data_reg[575]_0 [330]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[331] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[331]),
        .Q(\wr_buf_out_data_reg[575]_0 [331]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[332] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[332]),
        .Q(\wr_buf_out_data_reg[575]_0 [332]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[333] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[333]),
        .Q(\wr_buf_out_data_reg[575]_0 [333]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[334] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[334]),
        .Q(\wr_buf_out_data_reg[575]_0 [334]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[335] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[335]),
        .Q(\wr_buf_out_data_reg[575]_0 [335]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[336] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[336]),
        .Q(\wr_buf_out_data_reg[575]_0 [336]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[337] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[337]),
        .Q(\wr_buf_out_data_reg[575]_0 [337]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[338] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[338]),
        .Q(\wr_buf_out_data_reg[575]_0 [338]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[339] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[339]),
        .Q(\wr_buf_out_data_reg[575]_0 [339]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[33] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[33]),
        .Q(\wr_buf_out_data_reg[575]_0 [33]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[340] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[340]),
        .Q(\wr_buf_out_data_reg[575]_0 [340]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[341] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[341]),
        .Q(\wr_buf_out_data_reg[575]_0 [341]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[342] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[342]),
        .Q(\wr_buf_out_data_reg[575]_0 [342]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[343] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[343]),
        .Q(\wr_buf_out_data_reg[575]_0 [343]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[344] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[344]),
        .Q(\wr_buf_out_data_reg[575]_0 [344]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[345] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[345]),
        .Q(\wr_buf_out_data_reg[575]_0 [345]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[346] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[346]),
        .Q(\wr_buf_out_data_reg[575]_0 [346]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[347] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[347]),
        .Q(\wr_buf_out_data_reg[575]_0 [347]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[348] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[348]),
        .Q(\wr_buf_out_data_reg[575]_0 [348]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[349] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[349]),
        .Q(\wr_buf_out_data_reg[575]_0 [349]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[34] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[34]),
        .Q(\wr_buf_out_data_reg[575]_0 [34]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[350] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[350]),
        .Q(\wr_buf_out_data_reg[575]_0 [350]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[351] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[351]),
        .Q(\wr_buf_out_data_reg[575]_0 [351]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[352] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[352]),
        .Q(\wr_buf_out_data_reg[575]_0 [352]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[353] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[353]),
        .Q(\wr_buf_out_data_reg[575]_0 [353]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[354] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[354]),
        .Q(\wr_buf_out_data_reg[575]_0 [354]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[355] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[355]),
        .Q(\wr_buf_out_data_reg[575]_0 [355]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[356] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[356]),
        .Q(\wr_buf_out_data_reg[575]_0 [356]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[357] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[357]),
        .Q(\wr_buf_out_data_reg[575]_0 [357]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[358] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[358]),
        .Q(\wr_buf_out_data_reg[575]_0 [358]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[359] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[359]),
        .Q(\wr_buf_out_data_reg[575]_0 [359]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[35] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[35]),
        .Q(\wr_buf_out_data_reg[575]_0 [35]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[360] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[360]),
        .Q(\wr_buf_out_data_reg[575]_0 [360]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[361] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[361]),
        .Q(\wr_buf_out_data_reg[575]_0 [361]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[362] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[362]),
        .Q(\wr_buf_out_data_reg[575]_0 [362]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[363] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[363]),
        .Q(\wr_buf_out_data_reg[575]_0 [363]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[364] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[364]),
        .Q(\wr_buf_out_data_reg[575]_0 [364]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[365] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[365]),
        .Q(\wr_buf_out_data_reg[575]_0 [365]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[366] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[366]),
        .Q(\wr_buf_out_data_reg[575]_0 [366]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[367] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[367]),
        .Q(\wr_buf_out_data_reg[575]_0 [367]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[368] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[368]),
        .Q(\wr_buf_out_data_reg[575]_0 [368]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[369] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[369]),
        .Q(\wr_buf_out_data_reg[575]_0 [369]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[36] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[36]),
        .Q(\wr_buf_out_data_reg[575]_0 [36]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[370] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[370]),
        .Q(\wr_buf_out_data_reg[575]_0 [370]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[371] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[371]),
        .Q(\wr_buf_out_data_reg[575]_0 [371]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[372] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[372]),
        .Q(\wr_buf_out_data_reg[575]_0 [372]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[373] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[373]),
        .Q(\wr_buf_out_data_reg[575]_0 [373]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[374] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[374]),
        .Q(\wr_buf_out_data_reg[575]_0 [374]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[375] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[375]),
        .Q(\wr_buf_out_data_reg[575]_0 [375]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[376] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[376]),
        .Q(\wr_buf_out_data_reg[575]_0 [376]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[377] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[377]),
        .Q(\wr_buf_out_data_reg[575]_0 [377]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[378] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[378]),
        .Q(\wr_buf_out_data_reg[575]_0 [378]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[379] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[379]),
        .Q(\wr_buf_out_data_reg[575]_0 [379]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[37] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[37]),
        .Q(\wr_buf_out_data_reg[575]_0 [37]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[380] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[380]),
        .Q(\wr_buf_out_data_reg[575]_0 [380]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[381] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[381]),
        .Q(\wr_buf_out_data_reg[575]_0 [381]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[382] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[382]),
        .Q(\wr_buf_out_data_reg[575]_0 [382]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[383] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[383]),
        .Q(\wr_buf_out_data_reg[575]_0 [383]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[384] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[384]),
        .Q(\wr_buf_out_data_reg[575]_0 [384]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[385] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[385]),
        .Q(\wr_buf_out_data_reg[575]_0 [385]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[386] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[386]),
        .Q(\wr_buf_out_data_reg[575]_0 [386]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[387] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[387]),
        .Q(\wr_buf_out_data_reg[575]_0 [387]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[388] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[388]),
        .Q(\wr_buf_out_data_reg[575]_0 [388]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[389] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[389]),
        .Q(\wr_buf_out_data_reg[575]_0 [389]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[38] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[38]),
        .Q(\wr_buf_out_data_reg[575]_0 [38]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[390] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[390]),
        .Q(\wr_buf_out_data_reg[575]_0 [390]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[391] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[391]),
        .Q(\wr_buf_out_data_reg[575]_0 [391]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[392] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[392]),
        .Q(\wr_buf_out_data_reg[575]_0 [392]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[393] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[393]),
        .Q(\wr_buf_out_data_reg[575]_0 [393]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[394] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[394]),
        .Q(\wr_buf_out_data_reg[575]_0 [394]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[395] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[395]),
        .Q(\wr_buf_out_data_reg[575]_0 [395]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[396] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[396]),
        .Q(\wr_buf_out_data_reg[575]_0 [396]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[397] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[397]),
        .Q(\wr_buf_out_data_reg[575]_0 [397]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[398] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[398]),
        .Q(\wr_buf_out_data_reg[575]_0 [398]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[399] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[399]),
        .Q(\wr_buf_out_data_reg[575]_0 [399]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[39] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[39]),
        .Q(\wr_buf_out_data_reg[575]_0 [39]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[3] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[3]),
        .Q(\wr_buf_out_data_reg[575]_0 [3]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[400] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[400]),
        .Q(\wr_buf_out_data_reg[575]_0 [400]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[401] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[401]),
        .Q(\wr_buf_out_data_reg[575]_0 [401]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[402] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[402]),
        .Q(\wr_buf_out_data_reg[575]_0 [402]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[403] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[403]),
        .Q(\wr_buf_out_data_reg[575]_0 [403]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[404] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[404]),
        .Q(\wr_buf_out_data_reg[575]_0 [404]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[405] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[405]),
        .Q(\wr_buf_out_data_reg[575]_0 [405]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[406] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[406]),
        .Q(\wr_buf_out_data_reg[575]_0 [406]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[407] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[407]),
        .Q(\wr_buf_out_data_reg[575]_0 [407]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[408] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[408]),
        .Q(\wr_buf_out_data_reg[575]_0 [408]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[409] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[409]),
        .Q(\wr_buf_out_data_reg[575]_0 [409]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[40] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[40]),
        .Q(\wr_buf_out_data_reg[575]_0 [40]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[410] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[410]),
        .Q(\wr_buf_out_data_reg[575]_0 [410]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[411] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[411]),
        .Q(\wr_buf_out_data_reg[575]_0 [411]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[412] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[412]),
        .Q(\wr_buf_out_data_reg[575]_0 [412]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[413] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[413]),
        .Q(\wr_buf_out_data_reg[575]_0 [413]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[414] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[414]),
        .Q(\wr_buf_out_data_reg[575]_0 [414]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[415] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[415]),
        .Q(\wr_buf_out_data_reg[575]_0 [415]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[416] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[416]),
        .Q(\wr_buf_out_data_reg[575]_0 [416]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[417] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[417]),
        .Q(\wr_buf_out_data_reg[575]_0 [417]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[418] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[418]),
        .Q(\wr_buf_out_data_reg[575]_0 [418]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[419] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[419]),
        .Q(\wr_buf_out_data_reg[575]_0 [419]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[41] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[41]),
        .Q(\wr_buf_out_data_reg[575]_0 [41]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[420] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[420]),
        .Q(\wr_buf_out_data_reg[575]_0 [420]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[421] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[421]),
        .Q(\wr_buf_out_data_reg[575]_0 [421]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[422] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[422]),
        .Q(\wr_buf_out_data_reg[575]_0 [422]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[423] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[423]),
        .Q(\wr_buf_out_data_reg[575]_0 [423]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[424] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[424]),
        .Q(\wr_buf_out_data_reg[575]_0 [424]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[425] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[425]),
        .Q(\wr_buf_out_data_reg[575]_0 [425]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[426] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[426]),
        .Q(\wr_buf_out_data_reg[575]_0 [426]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[427] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[427]),
        .Q(\wr_buf_out_data_reg[575]_0 [427]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[428] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[428]),
        .Q(\wr_buf_out_data_reg[575]_0 [428]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[429] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[429]),
        .Q(\wr_buf_out_data_reg[575]_0 [429]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[42] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[42]),
        .Q(\wr_buf_out_data_reg[575]_0 [42]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[430] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[430]),
        .Q(\wr_buf_out_data_reg[575]_0 [430]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[431] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[431]),
        .Q(\wr_buf_out_data_reg[575]_0 [431]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[432] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[432]),
        .Q(\wr_buf_out_data_reg[575]_0 [432]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[433] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[433]),
        .Q(\wr_buf_out_data_reg[575]_0 [433]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[434] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[434]),
        .Q(\wr_buf_out_data_reg[575]_0 [434]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[435] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[435]),
        .Q(\wr_buf_out_data_reg[575]_0 [435]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[436] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[436]),
        .Q(\wr_buf_out_data_reg[575]_0 [436]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[437] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[437]),
        .Q(\wr_buf_out_data_reg[575]_0 [437]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[438] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[438]),
        .Q(\wr_buf_out_data_reg[575]_0 [438]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[439] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[439]),
        .Q(\wr_buf_out_data_reg[575]_0 [439]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[43] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[43]),
        .Q(\wr_buf_out_data_reg[575]_0 [43]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[440] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[440]),
        .Q(\wr_buf_out_data_reg[575]_0 [440]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[441] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[441]),
        .Q(\wr_buf_out_data_reg[575]_0 [441]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[442] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[442]),
        .Q(\wr_buf_out_data_reg[575]_0 [442]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[443] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[443]),
        .Q(\wr_buf_out_data_reg[575]_0 [443]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[444] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[444]),
        .Q(\wr_buf_out_data_reg[575]_0 [444]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[445] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[445]),
        .Q(\wr_buf_out_data_reg[575]_0 [445]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[446] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[446]),
        .Q(\wr_buf_out_data_reg[575]_0 [446]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[447] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[447]),
        .Q(\wr_buf_out_data_reg[575]_0 [447]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[448] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[448]),
        .Q(\wr_buf_out_data_reg[575]_0 [448]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[449] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[449]),
        .Q(\wr_buf_out_data_reg[575]_0 [449]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[44] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[44]),
        .Q(\wr_buf_out_data_reg[575]_0 [44]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[450] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[450]),
        .Q(\wr_buf_out_data_reg[575]_0 [450]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[451] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[451]),
        .Q(\wr_buf_out_data_reg[575]_0 [451]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[452] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[452]),
        .Q(\wr_buf_out_data_reg[575]_0 [452]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[453] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[453]),
        .Q(\wr_buf_out_data_reg[575]_0 [453]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[454] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[454]),
        .Q(\wr_buf_out_data_reg[575]_0 [454]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[455] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[455]),
        .Q(\wr_buf_out_data_reg[575]_0 [455]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[456] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[456]),
        .Q(\wr_buf_out_data_reg[575]_0 [456]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[457] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[457]),
        .Q(\wr_buf_out_data_reg[575]_0 [457]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[458] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[458]),
        .Q(\wr_buf_out_data_reg[575]_0 [458]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[459] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[459]),
        .Q(\wr_buf_out_data_reg[575]_0 [459]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[45] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[45]),
        .Q(\wr_buf_out_data_reg[575]_0 [45]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[460] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[460]),
        .Q(\wr_buf_out_data_reg[575]_0 [460]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[461] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[461]),
        .Q(\wr_buf_out_data_reg[575]_0 [461]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[462] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[462]),
        .Q(\wr_buf_out_data_reg[575]_0 [462]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[463] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[463]),
        .Q(\wr_buf_out_data_reg[575]_0 [463]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[464] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[464]),
        .Q(\wr_buf_out_data_reg[575]_0 [464]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[465] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[465]),
        .Q(\wr_buf_out_data_reg[575]_0 [465]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[466] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[466]),
        .Q(\wr_buf_out_data_reg[575]_0 [466]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[467] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[467]),
        .Q(\wr_buf_out_data_reg[575]_0 [467]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[468] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[468]),
        .Q(\wr_buf_out_data_reg[575]_0 [468]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[469] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[469]),
        .Q(\wr_buf_out_data_reg[575]_0 [469]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[46] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[46]),
        .Q(\wr_buf_out_data_reg[575]_0 [46]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[470] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[470]),
        .Q(\wr_buf_out_data_reg[575]_0 [470]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[471] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[471]),
        .Q(\wr_buf_out_data_reg[575]_0 [471]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[472] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[472]),
        .Q(\wr_buf_out_data_reg[575]_0 [472]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[473] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[473]),
        .Q(\wr_buf_out_data_reg[575]_0 [473]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[474] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[474]),
        .Q(\wr_buf_out_data_reg[575]_0 [474]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[475] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[475]),
        .Q(\wr_buf_out_data_reg[575]_0 [475]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[476] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[476]),
        .Q(\wr_buf_out_data_reg[575]_0 [476]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[477] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[477]),
        .Q(\wr_buf_out_data_reg[575]_0 [477]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[478] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[478]),
        .Q(\wr_buf_out_data_reg[575]_0 [478]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[479] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[479]),
        .Q(\wr_buf_out_data_reg[575]_0 [479]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[47] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[47]),
        .Q(\wr_buf_out_data_reg[575]_0 [47]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[480] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[480]),
        .Q(\wr_buf_out_data_reg[575]_0 [480]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[481] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[481]),
        .Q(\wr_buf_out_data_reg[575]_0 [481]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[482] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[482]),
        .Q(\wr_buf_out_data_reg[575]_0 [482]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[483] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[483]),
        .Q(\wr_buf_out_data_reg[575]_0 [483]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[484] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[484]),
        .Q(\wr_buf_out_data_reg[575]_0 [484]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[485] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[485]),
        .Q(\wr_buf_out_data_reg[575]_0 [485]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[486] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[486]),
        .Q(\wr_buf_out_data_reg[575]_0 [486]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[487] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[487]),
        .Q(\wr_buf_out_data_reg[575]_0 [487]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[488] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[488]),
        .Q(\wr_buf_out_data_reg[575]_0 [488]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[489] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[489]),
        .Q(\wr_buf_out_data_reg[575]_0 [489]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[48] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[48]),
        .Q(\wr_buf_out_data_reg[575]_0 [48]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[490] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[490]),
        .Q(\wr_buf_out_data_reg[575]_0 [490]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[491] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[491]),
        .Q(\wr_buf_out_data_reg[575]_0 [491]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[492] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[492]),
        .Q(\wr_buf_out_data_reg[575]_0 [492]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[493] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[493]),
        .Q(\wr_buf_out_data_reg[575]_0 [493]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[494] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[494]),
        .Q(\wr_buf_out_data_reg[575]_0 [494]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[495] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[495]),
        .Q(\wr_buf_out_data_reg[575]_0 [495]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[496] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[496]),
        .Q(\wr_buf_out_data_reg[575]_0 [496]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[497] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[497]),
        .Q(\wr_buf_out_data_reg[575]_0 [497]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[498] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[498]),
        .Q(\wr_buf_out_data_reg[575]_0 [498]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[499] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[499]),
        .Q(\wr_buf_out_data_reg[575]_0 [499]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[49] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[49]),
        .Q(\wr_buf_out_data_reg[575]_0 [49]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[4] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[4]),
        .Q(\wr_buf_out_data_reg[575]_0 [4]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[500] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[500]),
        .Q(\wr_buf_out_data_reg[575]_0 [500]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[501] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[501]),
        .Q(\wr_buf_out_data_reg[575]_0 [501]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[502] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[502]),
        .Q(\wr_buf_out_data_reg[575]_0 [502]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[503] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[503]),
        .Q(\wr_buf_out_data_reg[575]_0 [503]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[504] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[504]),
        .Q(\wr_buf_out_data_reg[575]_0 [504]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[505] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[505]),
        .Q(\wr_buf_out_data_reg[575]_0 [505]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[506] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[506]),
        .Q(\wr_buf_out_data_reg[575]_0 [506]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[507] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[507]),
        .Q(\wr_buf_out_data_reg[575]_0 [507]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[508] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[508]),
        .Q(\wr_buf_out_data_reg[575]_0 [508]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[509] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[509]),
        .Q(\wr_buf_out_data_reg[575]_0 [509]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[50] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[50]),
        .Q(\wr_buf_out_data_reg[575]_0 [50]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[510] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[510]),
        .Q(\wr_buf_out_data_reg[575]_0 [510]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[511] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[511]),
        .Q(\wr_buf_out_data_reg[575]_0 [511]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[512] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[512]),
        .Q(\wr_buf_out_data_reg[575]_0 [512]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[513] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[513]),
        .Q(\wr_buf_out_data_reg[575]_0 [513]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[514] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[514]),
        .Q(\wr_buf_out_data_reg[575]_0 [514]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[515] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[515]),
        .Q(\wr_buf_out_data_reg[575]_0 [515]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[516] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[516]),
        .Q(\wr_buf_out_data_reg[575]_0 [516]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[517] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[517]),
        .Q(\wr_buf_out_data_reg[575]_0 [517]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[518] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[518]),
        .Q(\wr_buf_out_data_reg[575]_0 [518]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[519] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[519]),
        .Q(\wr_buf_out_data_reg[575]_0 [519]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[51] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[51]),
        .Q(\wr_buf_out_data_reg[575]_0 [51]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[520] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[520]),
        .Q(\wr_buf_out_data_reg[575]_0 [520]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[521] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[521]),
        .Q(\wr_buf_out_data_reg[575]_0 [521]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[522] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[522]),
        .Q(\wr_buf_out_data_reg[575]_0 [522]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[523] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[523]),
        .Q(\wr_buf_out_data_reg[575]_0 [523]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[524] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[524]),
        .Q(\wr_buf_out_data_reg[575]_0 [524]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[525] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[525]),
        .Q(\wr_buf_out_data_reg[575]_0 [525]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[526] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[526]),
        .Q(\wr_buf_out_data_reg[575]_0 [526]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[527] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[527]),
        .Q(\wr_buf_out_data_reg[575]_0 [527]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[528] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[528]),
        .Q(\wr_buf_out_data_reg[575]_0 [528]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[529] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[529]),
        .Q(\wr_buf_out_data_reg[575]_0 [529]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[52] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[52]),
        .Q(\wr_buf_out_data_reg[575]_0 [52]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[530] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[530]),
        .Q(\wr_buf_out_data_reg[575]_0 [530]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[531] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[531]),
        .Q(\wr_buf_out_data_reg[575]_0 [531]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[532] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[532]),
        .Q(\wr_buf_out_data_reg[575]_0 [532]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[533] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[533]),
        .Q(\wr_buf_out_data_reg[575]_0 [533]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[534] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[534]),
        .Q(\wr_buf_out_data_reg[575]_0 [534]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[535] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[535]),
        .Q(\wr_buf_out_data_reg[575]_0 [535]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[536] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[536]),
        .Q(\wr_buf_out_data_reg[575]_0 [536]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[537] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[537]),
        .Q(\wr_buf_out_data_reg[575]_0 [537]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[538] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[538]),
        .Q(\wr_buf_out_data_reg[575]_0 [538]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[539] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[539]),
        .Q(\wr_buf_out_data_reg[575]_0 [539]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[53] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[53]),
        .Q(\wr_buf_out_data_reg[575]_0 [53]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[540] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[540]),
        .Q(\wr_buf_out_data_reg[575]_0 [540]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[541] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[541]),
        .Q(\wr_buf_out_data_reg[575]_0 [541]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[542] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[542]),
        .Q(\wr_buf_out_data_reg[575]_0 [542]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[543] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[543]),
        .Q(\wr_buf_out_data_reg[575]_0 [543]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[544] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[544]),
        .Q(\wr_buf_out_data_reg[575]_0 [544]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[545] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[545]),
        .Q(\wr_buf_out_data_reg[575]_0 [545]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[546] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[546]),
        .Q(\wr_buf_out_data_reg[575]_0 [546]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[547] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[547]),
        .Q(\wr_buf_out_data_reg[575]_0 [547]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[548] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[548]),
        .Q(\wr_buf_out_data_reg[575]_0 [548]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[549] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[549]),
        .Q(\wr_buf_out_data_reg[575]_0 [549]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[54] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[54]),
        .Q(\wr_buf_out_data_reg[575]_0 [54]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[550] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[550]),
        .Q(\wr_buf_out_data_reg[575]_0 [550]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[551] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[551]),
        .Q(\wr_buf_out_data_reg[575]_0 [551]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[552] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[552]),
        .Q(\wr_buf_out_data_reg[575]_0 [552]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[553] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[553]),
        .Q(\wr_buf_out_data_reg[575]_0 [553]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[554] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[554]),
        .Q(\wr_buf_out_data_reg[575]_0 [554]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[555] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[555]),
        .Q(\wr_buf_out_data_reg[575]_0 [555]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[556] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[556]),
        .Q(\wr_buf_out_data_reg[575]_0 [556]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[557] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[557]),
        .Q(\wr_buf_out_data_reg[575]_0 [557]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[558] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[558]),
        .Q(\wr_buf_out_data_reg[575]_0 [558]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[559] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[559]),
        .Q(\wr_buf_out_data_reg[575]_0 [559]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[55] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[55]),
        .Q(\wr_buf_out_data_reg[575]_0 [55]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[560] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[560]),
        .Q(\wr_buf_out_data_reg[575]_0 [560]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[561] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[561]),
        .Q(\wr_buf_out_data_reg[575]_0 [561]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[562] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[562]),
        .Q(\wr_buf_out_data_reg[575]_0 [562]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[563] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[563]),
        .Q(\wr_buf_out_data_reg[575]_0 [563]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[564] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[564]),
        .Q(\wr_buf_out_data_reg[575]_0 [564]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[565] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[565]),
        .Q(\wr_buf_out_data_reg[575]_0 [565]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[566] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[566]),
        .Q(\wr_buf_out_data_reg[575]_0 [566]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[567] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[567]),
        .Q(\wr_buf_out_data_reg[575]_0 [567]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[568] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[568]),
        .Q(\wr_buf_out_data_reg[575]_0 [568]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[569] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[569]),
        .Q(\wr_buf_out_data_reg[575]_0 [569]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[56] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[56]),
        .Q(\wr_buf_out_data_reg[575]_0 [56]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[570] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[570]),
        .Q(\wr_buf_out_data_reg[575]_0 [570]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[571] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[571]),
        .Q(\wr_buf_out_data_reg[575]_0 [571]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[572] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[572]),
        .Q(\wr_buf_out_data_reg[575]_0 [572]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[573] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[573]),
        .Q(\wr_buf_out_data_reg[575]_0 [573]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[574] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[574]),
        .Q(\wr_buf_out_data_reg[575]_0 [574]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[575] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[575]),
        .Q(\wr_buf_out_data_reg[575]_0 [575]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[57] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[57]),
        .Q(\wr_buf_out_data_reg[575]_0 [57]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[58] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[58]),
        .Q(\wr_buf_out_data_reg[575]_0 [58]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[59] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[59]),
        .Q(\wr_buf_out_data_reg[575]_0 [59]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[5] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[5]),
        .Q(\wr_buf_out_data_reg[575]_0 [5]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[60] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[60]),
        .Q(\wr_buf_out_data_reg[575]_0 [60]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[61] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[61]),
        .Q(\wr_buf_out_data_reg[575]_0 [61]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[62] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[62]),
        .Q(\wr_buf_out_data_reg[575]_0 [62]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[63] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[63]),
        .Q(\wr_buf_out_data_reg[575]_0 [63]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[64] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[64]),
        .Q(\wr_buf_out_data_reg[575]_0 [64]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[65] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[65]),
        .Q(\wr_buf_out_data_reg[575]_0 [65]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[66] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[66]),
        .Q(\wr_buf_out_data_reg[575]_0 [66]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[67] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[67]),
        .Q(\wr_buf_out_data_reg[575]_0 [67]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[68] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[68]),
        .Q(\wr_buf_out_data_reg[575]_0 [68]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[69] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[69]),
        .Q(\wr_buf_out_data_reg[575]_0 [69]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[6] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[6]),
        .Q(\wr_buf_out_data_reg[575]_0 [6]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[70] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[70]),
        .Q(\wr_buf_out_data_reg[575]_0 [70]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[71] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[71]),
        .Q(\wr_buf_out_data_reg[575]_0 [71]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[72] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[72]),
        .Q(\wr_buf_out_data_reg[575]_0 [72]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[73] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[73]),
        .Q(\wr_buf_out_data_reg[575]_0 [73]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[74] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[74]),
        .Q(\wr_buf_out_data_reg[575]_0 [74]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[75] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[75]),
        .Q(\wr_buf_out_data_reg[575]_0 [75]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[76] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[76]),
        .Q(\wr_buf_out_data_reg[575]_0 [76]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[77] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[77]),
        .Q(\wr_buf_out_data_reg[575]_0 [77]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[78] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[78]),
        .Q(\wr_buf_out_data_reg[575]_0 [78]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[79] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[79]),
        .Q(\wr_buf_out_data_reg[575]_0 [79]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[7] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[7]),
        .Q(\wr_buf_out_data_reg[575]_0 [7]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[80] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[80]),
        .Q(\wr_buf_out_data_reg[575]_0 [80]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[81] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[81]),
        .Q(\wr_buf_out_data_reg[575]_0 [81]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[82] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[82]),
        .Q(\wr_buf_out_data_reg[575]_0 [82]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[83] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[83]),
        .Q(\wr_buf_out_data_reg[575]_0 [83]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[84] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[84]),
        .Q(\wr_buf_out_data_reg[575]_0 [84]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[85] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[85]),
        .Q(\wr_buf_out_data_reg[575]_0 [85]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[86] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[86]),
        .Q(\wr_buf_out_data_reg[575]_0 [86]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[87] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[87]),
        .Q(\wr_buf_out_data_reg[575]_0 [87]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[88] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[88]),
        .Q(\wr_buf_out_data_reg[575]_0 [88]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[89] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[89]),
        .Q(\wr_buf_out_data_reg[575]_0 [89]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[8] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[8]),
        .Q(\wr_buf_out_data_reg[575]_0 [8]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[90] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[90]),
        .Q(\wr_buf_out_data_reg[575]_0 [90]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[91] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[91]),
        .Q(\wr_buf_out_data_reg[575]_0 [91]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[92] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[92]),
        .Q(\wr_buf_out_data_reg[575]_0 [92]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[93] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[93]),
        .Q(\wr_buf_out_data_reg[575]_0 [93]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[94] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[94]),
        .Q(\wr_buf_out_data_reg[575]_0 [94]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[95] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[95]),
        .Q(\wr_buf_out_data_reg[575]_0 [95]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[96] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[96]),
        .Q(\wr_buf_out_data_reg[575]_0 [96]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[97] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[97]),
        .Q(\wr_buf_out_data_reg[575]_0 [97]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[98] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[98]),
        .Q(\wr_buf_out_data_reg[575]_0 [98]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[99] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[99]),
        .Q(\wr_buf_out_data_reg[575]_0 [99]),
        .R(1'b0));
  FDRE \wr_buf_out_data_reg[9] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[9]),
        .Q(\wr_buf_out_data_reg[575]_0 [9]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[0].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[5:4]),
        .DIB(wr_buf_in_data[3:2]),
        .DIC(wr_buf_in_data[1:0]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[5:4]),
        .DOB(wr_buf_out_data_w[3:2]),
        .DOC(wr_buf_out_data_w[1:0]),
        .DOD(\NLW_wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT5 #(
    .INIT(32'hFF150000)) 
    \wr_buffer_ram[0].RAM32M0_i_1 
       (.I0(p_0_in2_in),
        .I1(p_11_in),
        .I2(p_0_in12_in),
        .I3(rd_data_upd_indx_cpy_r),
        .I4(\wr_data_indx_r_reg[0]_0 [0]),
        .O(wdf_rdy_ns));
  LUT4 #(
    .INIT(16'h00AC)) 
    \wr_buffer_ram[0].RAM32M0_i_10 
       (.I0(wr_data_pntr[1]),
        .I1(wb_wr_data_addr_r[2]),
        .I2(wr_data_addr_le),
        .I3(\wr_data_indx_r_reg[1]_0 ),
        .O(wb_wr_data_addr_w[2]));
  LUT4 #(
    .INIT(16'h00AC)) 
    \wr_buffer_ram[0].RAM32M0_i_11 
       (.I0(wr_data_pntr[0]),
        .I1(wb_wr_data_addr_r[1]),
        .I2(wr_data_addr_le),
        .I3(\wr_data_indx_r_reg[1]_0 ),
        .O(wb_wr_data_addr_w[1]));
  LUT4 #(
    .INIT(16'h2F20)) 
    \wr_buffer_ram[0].RAM32M0_i_12 
       (.I0(app_wdf_rdy_r_copy3),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_wren_r1),
        .I3(wb_wr_data_addr0_r),
        .O(wb_wr_data_addr0_ns));
  LUT3 #(
    .INIT(8'h80)) 
    \wr_buffer_ram[0].RAM32M0_i_13 
       (.I0(app_wdf_rdy_r_copy1),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .O(p_11_in));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[0].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[5]),
        .I1(app_wdf_data_r1[5]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[5]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[0].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[4]),
        .I1(app_wdf_data_r1[4]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[4]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[0].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[3]),
        .I1(app_wdf_data_r1[3]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[3]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[0].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[2]),
        .I1(app_wdf_data_r1[2]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[2]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[0].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[1]),
        .I1(app_wdf_data_r1[1]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[1]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[0].RAM32M0_i_7 
       (.I0(c0_ddr4_app_wdf_data[0]),
        .I1(app_wdf_data_r1[0]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[0]));
  LUT4 #(
    .INIT(16'h00AC)) 
    \wr_buffer_ram[0].RAM32M0_i_8 
       (.I0(wr_data_pntr[3]),
        .I1(wb_wr_data_addr_r[4]),
        .I2(wr_data_addr_le),
        .I3(\wr_data_indx_r_reg[1]_0 ),
        .O(wb_wr_data_addr_w[4]));
  LUT4 #(
    .INIT(16'h00AC)) 
    \wr_buffer_ram[0].RAM32M0_i_9 
       (.I0(wr_data_pntr[2]),
        .I1(wb_wr_data_addr_r[3]),
        .I2(wr_data_addr_le),
        .I3(\wr_data_indx_r_reg[1]_0 ),
        .O(wb_wr_data_addr_w[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[10].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[65:64]),
        .DIB(wr_buf_in_data[63:62]),
        .DIC(wr_buf_in_data[61:60]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[65:64]),
        .DOB(wr_buf_out_data_w[63:62]),
        .DOC(wr_buf_out_data_w[61:60]),
        .DOD(\NLW_wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[10].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[65]),
        .I1(app_wdf_data_r1[65]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[65]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[10].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[64]),
        .I1(app_wdf_data_r1[64]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[64]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[10].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[63]),
        .I1(app_wdf_data_r1[63]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[63]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[10].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[62]),
        .I1(app_wdf_data_r1[62]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[62]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[10].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[61]),
        .I1(app_wdf_data_r1[61]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[61]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[10].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[60]),
        .I1(app_wdf_data_r1[60]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[60]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[11].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[71:70]),
        .DIB(wr_buf_in_data[69:68]),
        .DIC(wr_buf_in_data[67:66]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[71:70]),
        .DOB(wr_buf_out_data_w[69:68]),
        .DOC(wr_buf_out_data_w[67:66]),
        .DOD(\NLW_wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[11].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[71]),
        .I1(app_wdf_data_r1[71]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[71]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[11].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[70]),
        .I1(app_wdf_data_r1[70]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[70]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[11].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[69]),
        .I1(app_wdf_data_r1[69]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[69]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[11].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[68]),
        .I1(app_wdf_data_r1[68]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[68]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[11].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[67]),
        .I1(app_wdf_data_r1[67]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[67]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[11].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[66]),
        .I1(app_wdf_data_r1[66]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[66]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[12].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[77:76]),
        .DIB(wr_buf_in_data[75:74]),
        .DIC(wr_buf_in_data[73:72]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[77:76]),
        .DOB(wr_buf_out_data_w[75:74]),
        .DOC(wr_buf_out_data_w[73:72]),
        .DOD(\NLW_wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[12].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[77]),
        .I1(app_wdf_data_r1[77]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[77]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[12].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[76]),
        .I1(app_wdf_data_r1[76]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[76]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[12].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[75]),
        .I1(app_wdf_data_r1[75]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[75]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[12].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[74]),
        .I1(app_wdf_data_r1[74]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[74]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[12].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[73]),
        .I1(app_wdf_data_r1[73]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[73]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[12].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[72]),
        .I1(app_wdf_data_r1[72]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[72]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[13].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[83:82]),
        .DIB(wr_buf_in_data[81:80]),
        .DIC(wr_buf_in_data[79:78]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[83:82]),
        .DOB(wr_buf_out_data_w[81:80]),
        .DOC(wr_buf_out_data_w[79:78]),
        .DOD(\NLW_wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[13].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[83]),
        .I1(app_wdf_data_r1[83]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[83]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[13].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[82]),
        .I1(app_wdf_data_r1[82]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[82]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[13].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[81]),
        .I1(app_wdf_data_r1[81]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[81]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[13].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[80]),
        .I1(app_wdf_data_r1[80]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[80]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[13].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[79]),
        .I1(app_wdf_data_r1[79]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[79]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[13].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[78]),
        .I1(app_wdf_data_r1[78]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[78]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[14].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[89:88]),
        .DIB(wr_buf_in_data[87:86]),
        .DIC(wr_buf_in_data[85:84]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[89:88]),
        .DOB(wr_buf_out_data_w[87:86]),
        .DOC(wr_buf_out_data_w[85:84]),
        .DOD(\NLW_wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[14].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[89]),
        .I1(app_wdf_data_r1[89]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[89]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[14].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[88]),
        .I1(app_wdf_data_r1[88]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[88]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[14].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[87]),
        .I1(app_wdf_data_r1[87]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[87]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[14].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[86]),
        .I1(app_wdf_data_r1[86]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[86]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[14].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[85]),
        .I1(app_wdf_data_r1[85]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[85]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[14].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[84]),
        .I1(app_wdf_data_r1[84]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[84]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[15].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[95:94]),
        .DIB(wr_buf_in_data[93:92]),
        .DIC(wr_buf_in_data[91:90]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[95:94]),
        .DOB(wr_buf_out_data_w[93:92]),
        .DOC(wr_buf_out_data_w[91:90]),
        .DOD(\NLW_wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[15].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[95]),
        .I1(app_wdf_data_r1[95]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[95]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[15].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[94]),
        .I1(app_wdf_data_r1[94]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[94]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[15].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[93]),
        .I1(app_wdf_data_r1[93]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[93]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[15].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[92]),
        .I1(app_wdf_data_r1[92]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[92]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[15].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[91]),
        .I1(app_wdf_data_r1[91]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[91]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[15].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[90]),
        .I1(app_wdf_data_r1[90]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[90]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[16].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[101:100]),
        .DIB(wr_buf_in_data[99:98]),
        .DIC(wr_buf_in_data[97:96]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[101:100]),
        .DOB(wr_buf_out_data_w[99:98]),
        .DOC(wr_buf_out_data_w[97:96]),
        .DOD(\NLW_wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[16].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[101]),
        .I1(app_wdf_data_r1[101]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[101]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[16].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[100]),
        .I1(app_wdf_data_r1[100]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[100]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[16].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[99]),
        .I1(app_wdf_data_r1[99]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[99]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[16].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[98]),
        .I1(app_wdf_data_r1[98]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[98]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[16].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[97]),
        .I1(app_wdf_data_r1[97]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[97]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[16].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[96]),
        .I1(app_wdf_data_r1[96]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[96]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[17].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[107:106]),
        .DIB(wr_buf_in_data[105:104]),
        .DIC(wr_buf_in_data[103:102]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[107:106]),
        .DOB(wr_buf_out_data_w[105:104]),
        .DOC(wr_buf_out_data_w[103:102]),
        .DOD(\NLW_wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[17].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[107]),
        .I1(app_wdf_data_r1[107]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[107]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[17].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[106]),
        .I1(app_wdf_data_r1[106]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[106]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[17].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[105]),
        .I1(app_wdf_data_r1[105]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[105]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[17].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[104]),
        .I1(app_wdf_data_r1[104]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[104]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[17].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[103]),
        .I1(app_wdf_data_r1[103]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[103]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[17].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[102]),
        .I1(app_wdf_data_r1[102]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[102]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[18].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[113:112]),
        .DIB(wr_buf_in_data[111:110]),
        .DIC(wr_buf_in_data[109:108]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[113:112]),
        .DOB(wr_buf_out_data_w[111:110]),
        .DOC(wr_buf_out_data_w[109:108]),
        .DOD(\NLW_wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[18].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[113]),
        .I1(app_wdf_data_r1[113]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[113]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[18].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[112]),
        .I1(app_wdf_data_r1[112]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[112]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[18].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[111]),
        .I1(app_wdf_data_r1[111]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[111]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[18].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[110]),
        .I1(app_wdf_data_r1[110]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[110]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[18].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[109]),
        .I1(app_wdf_data_r1[109]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[109]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[18].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[108]),
        .I1(app_wdf_data_r1[108]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[108]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[19].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[119:118]),
        .DIB(wr_buf_in_data[117:116]),
        .DIC(wr_buf_in_data[115:114]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[119:118]),
        .DOB(wr_buf_out_data_w[117:116]),
        .DOC(wr_buf_out_data_w[115:114]),
        .DOD(\NLW_wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[19].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[119]),
        .I1(app_wdf_data_r1[119]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[119]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[19].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[118]),
        .I1(app_wdf_data_r1[118]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[118]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[19].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[117]),
        .I1(app_wdf_data_r1[117]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[117]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[19].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[116]),
        .I1(app_wdf_data_r1[116]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[116]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[19].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[115]),
        .I1(app_wdf_data_r1[115]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[115]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[19].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[114]),
        .I1(app_wdf_data_r1[114]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[114]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[1].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[11:10]),
        .DIB(wr_buf_in_data[9:8]),
        .DIC(wr_buf_in_data[7:6]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[11:10]),
        .DOB(wr_buf_out_data_w[9:8]),
        .DOC(wr_buf_out_data_w[7:6]),
        .DOD(\NLW_wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[1].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[11]),
        .I1(app_wdf_data_r1[11]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[11]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[1].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[10]),
        .I1(app_wdf_data_r1[10]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[10]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[1].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[9]),
        .I1(app_wdf_data_r1[9]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[9]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[1].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[8]),
        .I1(app_wdf_data_r1[8]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[8]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[1].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[7]),
        .I1(app_wdf_data_r1[7]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[7]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[1].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[6]),
        .I1(app_wdf_data_r1[6]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[20].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[125:124]),
        .DIB(wr_buf_in_data[123:122]),
        .DIC(wr_buf_in_data[121:120]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[125:124]),
        .DOB(wr_buf_out_data_w[123:122]),
        .DOC(wr_buf_out_data_w[121:120]),
        .DOD(\NLW_wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[20].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[125]),
        .I1(app_wdf_data_r1[125]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[125]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[20].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[124]),
        .I1(app_wdf_data_r1[124]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[124]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[20].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[123]),
        .I1(app_wdf_data_r1[123]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[123]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[20].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[122]),
        .I1(app_wdf_data_r1[122]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[122]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[20].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[121]),
        .I1(app_wdf_data_r1[121]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[121]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[20].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[120]),
        .I1(app_wdf_data_r1[120]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[120]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[21].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[131:130]),
        .DIB(wr_buf_in_data[129:128]),
        .DIC(wr_buf_in_data[127:126]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[131:130]),
        .DOB(wr_buf_out_data_w[129:128]),
        .DOC(wr_buf_out_data_w[127:126]),
        .DOD(\NLW_wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[21].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[131]),
        .I1(app_wdf_data_r1[131]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[131]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[21].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[130]),
        .I1(app_wdf_data_r1[130]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[130]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[21].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[129]),
        .I1(app_wdf_data_r1[129]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[129]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[21].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[128]),
        .I1(app_wdf_data_r1[128]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[128]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[21].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[127]),
        .I1(app_wdf_data_r1[127]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[127]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[21].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[126]),
        .I1(app_wdf_data_r1[126]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[126]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[22].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[137:136]),
        .DIB(wr_buf_in_data[135:134]),
        .DIC(wr_buf_in_data[133:132]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[137:136]),
        .DOB(wr_buf_out_data_w[135:134]),
        .DOC(wr_buf_out_data_w[133:132]),
        .DOD(\NLW_wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[22].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[137]),
        .I1(app_wdf_data_r1[137]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[137]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[22].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[136]),
        .I1(app_wdf_data_r1[136]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[136]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[22].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[135]),
        .I1(app_wdf_data_r1[135]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[135]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[22].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[134]),
        .I1(app_wdf_data_r1[134]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[134]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[22].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[133]),
        .I1(app_wdf_data_r1[133]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[133]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[22].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[132]),
        .I1(app_wdf_data_r1[132]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[132]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[23].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[143:142]),
        .DIB(wr_buf_in_data[141:140]),
        .DIC(wr_buf_in_data[139:138]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[143:142]),
        .DOB(wr_buf_out_data_w[141:140]),
        .DOC(wr_buf_out_data_w[139:138]),
        .DOD(\NLW_wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[23].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[143]),
        .I1(app_wdf_data_r1[143]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[143]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[23].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[142]),
        .I1(app_wdf_data_r1[142]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[142]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[23].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[141]),
        .I1(app_wdf_data_r1[141]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[141]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[23].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[140]),
        .I1(app_wdf_data_r1[140]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[140]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[23].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[139]),
        .I1(app_wdf_data_r1[139]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[139]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[23].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[138]),
        .I1(app_wdf_data_r1[138]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[138]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[24].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[149:148]),
        .DIB(wr_buf_in_data[147:146]),
        .DIC(wr_buf_in_data[145:144]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[149:148]),
        .DOB(wr_buf_out_data_w[147:146]),
        .DOC(wr_buf_out_data_w[145:144]),
        .DOD(\NLW_wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[24].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[149]),
        .I1(app_wdf_data_r1[149]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[149]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[24].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[148]),
        .I1(app_wdf_data_r1[148]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[148]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[24].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[147]),
        .I1(app_wdf_data_r1[147]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[147]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[24].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[146]),
        .I1(app_wdf_data_r1[146]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[146]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[24].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[145]),
        .I1(app_wdf_data_r1[145]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[145]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[24].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[144]),
        .I1(app_wdf_data_r1[144]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[144]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[25].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[155:154]),
        .DIB(wr_buf_in_data[153:152]),
        .DIC(wr_buf_in_data[151:150]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[155:154]),
        .DOB(wr_buf_out_data_w[153:152]),
        .DOC(wr_buf_out_data_w[151:150]),
        .DOD(\NLW_wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[25].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[155]),
        .I1(app_wdf_data_r1[155]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[155]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[25].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[154]),
        .I1(app_wdf_data_r1[154]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[154]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[25].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[153]),
        .I1(app_wdf_data_r1[153]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[153]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[25].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[152]),
        .I1(app_wdf_data_r1[152]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[152]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[25].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[151]),
        .I1(app_wdf_data_r1[151]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[151]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[25].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[150]),
        .I1(app_wdf_data_r1[150]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[150]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[26].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[161:160]),
        .DIB(wr_buf_in_data[159:158]),
        .DIC(wr_buf_in_data[157:156]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[161:160]),
        .DOB(wr_buf_out_data_w[159:158]),
        .DOC(wr_buf_out_data_w[157:156]),
        .DOD(\NLW_wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[26].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[161]),
        .I1(app_wdf_data_r1[161]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[161]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[26].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[160]),
        .I1(app_wdf_data_r1[160]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[160]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[26].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[159]),
        .I1(app_wdf_data_r1[159]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[159]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[26].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[158]),
        .I1(app_wdf_data_r1[158]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[158]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[26].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[157]),
        .I1(app_wdf_data_r1[157]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[157]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[26].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[156]),
        .I1(app_wdf_data_r1[156]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[156]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[27].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[167:166]),
        .DIB(wr_buf_in_data[165:164]),
        .DIC(wr_buf_in_data[163:162]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[167:166]),
        .DOB(wr_buf_out_data_w[165:164]),
        .DOC(wr_buf_out_data_w[163:162]),
        .DOD(\NLW_wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[27].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[167]),
        .I1(app_wdf_data_r1[167]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[167]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[27].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[166]),
        .I1(app_wdf_data_r1[166]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[166]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[27].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[165]),
        .I1(app_wdf_data_r1[165]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[165]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[27].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[164]),
        .I1(app_wdf_data_r1[164]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[164]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[27].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[163]),
        .I1(app_wdf_data_r1[163]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[163]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[27].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[162]),
        .I1(app_wdf_data_r1[162]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[162]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[28].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[173:172]),
        .DIB(wr_buf_in_data[171:170]),
        .DIC(wr_buf_in_data[169:168]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[173:172]),
        .DOB(wr_buf_out_data_w[171:170]),
        .DOC(wr_buf_out_data_w[169:168]),
        .DOD(\NLW_wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[28].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[173]),
        .I1(app_wdf_data_r1[173]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[173]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[28].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[172]),
        .I1(app_wdf_data_r1[172]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[172]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[28].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[171]),
        .I1(app_wdf_data_r1[171]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[171]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[28].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[170]),
        .I1(app_wdf_data_r1[170]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[170]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[28].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[169]),
        .I1(app_wdf_data_r1[169]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[169]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[28].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[168]),
        .I1(app_wdf_data_r1[168]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[168]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[29].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[179:178]),
        .DIB(wr_buf_in_data[177:176]),
        .DIC(wr_buf_in_data[175:174]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[179:178]),
        .DOB(wr_buf_out_data_w[177:176]),
        .DOC(wr_buf_out_data_w[175:174]),
        .DOD(\NLW_wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[29].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[179]),
        .I1(app_wdf_data_r1[179]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[179]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[29].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[178]),
        .I1(app_wdf_data_r1[178]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[178]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[29].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[177]),
        .I1(app_wdf_data_r1[177]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[177]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[29].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[176]),
        .I1(app_wdf_data_r1[176]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[176]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[29].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[175]),
        .I1(app_wdf_data_r1[175]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[175]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[29].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[174]),
        .I1(app_wdf_data_r1[174]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[174]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[2].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[17:16]),
        .DIB(wr_buf_in_data[15:14]),
        .DIC(wr_buf_in_data[13:12]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[17:16]),
        .DOB(wr_buf_out_data_w[15:14]),
        .DOC(wr_buf_out_data_w[13:12]),
        .DOD(\NLW_wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[2].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[17]),
        .I1(app_wdf_data_r1[17]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[17]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[2].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[16]),
        .I1(app_wdf_data_r1[16]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[16]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[2].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[15]),
        .I1(app_wdf_data_r1[15]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[15]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[2].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[14]),
        .I1(app_wdf_data_r1[14]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[14]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[2].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[13]),
        .I1(app_wdf_data_r1[13]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[13]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[2].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[12]),
        .I1(app_wdf_data_r1[12]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[12]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[30].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[185:184]),
        .DIB(wr_buf_in_data[183:182]),
        .DIC(wr_buf_in_data[181:180]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[185:184]),
        .DOB(wr_buf_out_data_w[183:182]),
        .DOC(wr_buf_out_data_w[181:180]),
        .DOD(\NLW_wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[30].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[185]),
        .I1(app_wdf_data_r1[185]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[185]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[30].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[184]),
        .I1(app_wdf_data_r1[184]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[184]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[30].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[183]),
        .I1(app_wdf_data_r1[183]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[183]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[30].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[182]),
        .I1(app_wdf_data_r1[182]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[182]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[30].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[181]),
        .I1(app_wdf_data_r1[181]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[181]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[30].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[180]),
        .I1(app_wdf_data_r1[180]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[180]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[31].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[191:190]),
        .DIB(wr_buf_in_data[189:188]),
        .DIC(wr_buf_in_data[187:186]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[191:190]),
        .DOB(wr_buf_out_data_w[189:188]),
        .DOC(wr_buf_out_data_w[187:186]),
        .DOD(\NLW_wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[31].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[191]),
        .I1(app_wdf_data_r1[191]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[191]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[31].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[190]),
        .I1(app_wdf_data_r1[190]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[190]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[31].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[189]),
        .I1(app_wdf_data_r1[189]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[189]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[31].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[188]),
        .I1(app_wdf_data_r1[188]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[188]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[31].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[187]),
        .I1(app_wdf_data_r1[187]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[187]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[31].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[186]),
        .I1(app_wdf_data_r1[186]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[186]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[32].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[197:196]),
        .DIB(wr_buf_in_data[195:194]),
        .DIC(wr_buf_in_data[193:192]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[197:196]),
        .DOB(wr_buf_out_data_w[195:194]),
        .DOC(wr_buf_out_data_w[193:192]),
        .DOD(\NLW_wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[32].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[197]),
        .I1(app_wdf_data_r1[197]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[197]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[32].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[196]),
        .I1(app_wdf_data_r1[196]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[196]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[32].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[195]),
        .I1(app_wdf_data_r1[195]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[195]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[32].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[194]),
        .I1(app_wdf_data_r1[194]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[194]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[32].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[193]),
        .I1(app_wdf_data_r1[193]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[193]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[32].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[192]),
        .I1(app_wdf_data_r1[192]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[192]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[33].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[203:202]),
        .DIB(wr_buf_in_data[201:200]),
        .DIC(wr_buf_in_data[199:198]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[203:202]),
        .DOB(wr_buf_out_data_w[201:200]),
        .DOC(wr_buf_out_data_w[199:198]),
        .DOD(\NLW_wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[33].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[203]),
        .I1(app_wdf_data_r1[203]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[203]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[33].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[202]),
        .I1(app_wdf_data_r1[202]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[202]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[33].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[201]),
        .I1(app_wdf_data_r1[201]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[201]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[33].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[200]),
        .I1(app_wdf_data_r1[200]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[200]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[33].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[199]),
        .I1(app_wdf_data_r1[199]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[199]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[33].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[198]),
        .I1(app_wdf_data_r1[198]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[198]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[34].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[209:208]),
        .DIB(wr_buf_in_data[207:206]),
        .DIC(wr_buf_in_data[205:204]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[209:208]),
        .DOB(wr_buf_out_data_w[207:206]),
        .DOC(wr_buf_out_data_w[205:204]),
        .DOD(\NLW_wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[34].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[209]),
        .I1(app_wdf_data_r1[209]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[209]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[34].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[208]),
        .I1(app_wdf_data_r1[208]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[208]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[34].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[207]),
        .I1(app_wdf_data_r1[207]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[207]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[34].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[206]),
        .I1(app_wdf_data_r1[206]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[206]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[34].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[205]),
        .I1(app_wdf_data_r1[205]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[205]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[34].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[204]),
        .I1(app_wdf_data_r1[204]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[204]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[35].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[215:214]),
        .DIB(wr_buf_in_data[213:212]),
        .DIC(wr_buf_in_data[211:210]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[215:214]),
        .DOB(wr_buf_out_data_w[213:212]),
        .DOC(wr_buf_out_data_w[211:210]),
        .DOD(\NLW_wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[35].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[215]),
        .I1(app_wdf_data_r1[215]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[215]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[35].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[214]),
        .I1(app_wdf_data_r1[214]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[214]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[35].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[213]),
        .I1(app_wdf_data_r1[213]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[213]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[35].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[212]),
        .I1(app_wdf_data_r1[212]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[212]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[35].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[211]),
        .I1(app_wdf_data_r1[211]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[211]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[35].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[210]),
        .I1(app_wdf_data_r1[210]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[210]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[36].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[221:220]),
        .DIB(wr_buf_in_data[219:218]),
        .DIC(wr_buf_in_data[217:216]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[221:220]),
        .DOB(wr_buf_out_data_w[219:218]),
        .DOC(wr_buf_out_data_w[217:216]),
        .DOD(\NLW_wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[36].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[221]),
        .I1(app_wdf_data_r1[221]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[221]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[36].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[220]),
        .I1(app_wdf_data_r1[220]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[220]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[36].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[219]),
        .I1(app_wdf_data_r1[219]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[219]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[36].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[218]),
        .I1(app_wdf_data_r1[218]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[218]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[36].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[217]),
        .I1(app_wdf_data_r1[217]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[217]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[36].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[216]),
        .I1(app_wdf_data_r1[216]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[216]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[37].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[227:226]),
        .DIB(wr_buf_in_data[225:224]),
        .DIC(wr_buf_in_data[223:222]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[227:226]),
        .DOB(wr_buf_out_data_w[225:224]),
        .DOC(wr_buf_out_data_w[223:222]),
        .DOD(\NLW_wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[37].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[227]),
        .I1(app_wdf_data_r1[227]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[227]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[37].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[226]),
        .I1(app_wdf_data_r1[226]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[226]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[37].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[225]),
        .I1(app_wdf_data_r1[225]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[225]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[37].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[224]),
        .I1(app_wdf_data_r1[224]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[224]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[37].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[223]),
        .I1(app_wdf_data_r1[223]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[223]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[37].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[222]),
        .I1(app_wdf_data_r1[222]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[222]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[38].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[233:232]),
        .DIB(wr_buf_in_data[231:230]),
        .DIC(wr_buf_in_data[229:228]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[233:232]),
        .DOB(wr_buf_out_data_w[231:230]),
        .DOC(wr_buf_out_data_w[229:228]),
        .DOD(\NLW_wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[38].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[233]),
        .I1(app_wdf_data_r1[233]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[233]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[38].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[232]),
        .I1(app_wdf_data_r1[232]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[232]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[38].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[231]),
        .I1(app_wdf_data_r1[231]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[231]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[38].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[230]),
        .I1(app_wdf_data_r1[230]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[230]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[38].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[229]),
        .I1(app_wdf_data_r1[229]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[229]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[38].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[228]),
        .I1(app_wdf_data_r1[228]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[228]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[39].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[239:238]),
        .DIB(wr_buf_in_data[237:236]),
        .DIC(wr_buf_in_data[235:234]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[239:238]),
        .DOB(wr_buf_out_data_w[237:236]),
        .DOC(wr_buf_out_data_w[235:234]),
        .DOD(\NLW_wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[39].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[239]),
        .I1(app_wdf_data_r1[239]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[239]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[39].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[238]),
        .I1(app_wdf_data_r1[238]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[238]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[39].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[237]),
        .I1(app_wdf_data_r1[237]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[237]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[39].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[236]),
        .I1(app_wdf_data_r1[236]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[236]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[39].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[235]),
        .I1(app_wdf_data_r1[235]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[235]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[39].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[234]),
        .I1(app_wdf_data_r1[234]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[234]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[3].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[23:22]),
        .DIB(wr_buf_in_data[21:20]),
        .DIC(wr_buf_in_data[19:18]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[23:22]),
        .DOB(wr_buf_out_data_w[21:20]),
        .DOC(wr_buf_out_data_w[19:18]),
        .DOD(\NLW_wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[3].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[23]),
        .I1(app_wdf_data_r1[23]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[23]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[3].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[22]),
        .I1(app_wdf_data_r1[22]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[22]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[3].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[21]),
        .I1(app_wdf_data_r1[21]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[21]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[3].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[20]),
        .I1(app_wdf_data_r1[20]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[20]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[3].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[19]),
        .I1(app_wdf_data_r1[19]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[19]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[3].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[18]),
        .I1(app_wdf_data_r1[18]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[18]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[40].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[245:244]),
        .DIB(wr_buf_in_data[243:242]),
        .DIC(wr_buf_in_data[241:240]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[245:244]),
        .DOB(wr_buf_out_data_w[243:242]),
        .DOC(wr_buf_out_data_w[241:240]),
        .DOD(\NLW_wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[40].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[245]),
        .I1(app_wdf_data_r1[245]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[245]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[40].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[244]),
        .I1(app_wdf_data_r1[244]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[244]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[40].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[243]),
        .I1(app_wdf_data_r1[243]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[243]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[40].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[242]),
        .I1(app_wdf_data_r1[242]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[242]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[40].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[241]),
        .I1(app_wdf_data_r1[241]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[241]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[40].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[240]),
        .I1(app_wdf_data_r1[240]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[240]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[41].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[251:250]),
        .DIB(wr_buf_in_data[249:248]),
        .DIC(wr_buf_in_data[247:246]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[251:250]),
        .DOB(wr_buf_out_data_w[249:248]),
        .DOC(wr_buf_out_data_w[247:246]),
        .DOD(\NLW_wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[41].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[251]),
        .I1(app_wdf_data_r1[251]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[251]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[41].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[250]),
        .I1(app_wdf_data_r1[250]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[250]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[41].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[249]),
        .I1(app_wdf_data_r1[249]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[249]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[41].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[248]),
        .I1(app_wdf_data_r1[248]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[248]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[41].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[247]),
        .I1(app_wdf_data_r1[247]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[247]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[41].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[246]),
        .I1(app_wdf_data_r1[246]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[246]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[42].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[257:256]),
        .DIB(wr_buf_in_data[255:254]),
        .DIC(wr_buf_in_data[253:252]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[257:256]),
        .DOB(wr_buf_out_data_w[255:254]),
        .DOC(wr_buf_out_data_w[253:252]),
        .DOD(\NLW_wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[42].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[257]),
        .I1(app_wdf_data_r1[257]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[257]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[42].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[256]),
        .I1(app_wdf_data_r1[256]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[256]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[42].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[255]),
        .I1(app_wdf_data_r1[255]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[255]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[42].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[254]),
        .I1(app_wdf_data_r1[254]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[254]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[42].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[253]),
        .I1(app_wdf_data_r1[253]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[253]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[42].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[252]),
        .I1(app_wdf_data_r1[252]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[252]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[43].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[263:262]),
        .DIB(wr_buf_in_data[261:260]),
        .DIC(wr_buf_in_data[259:258]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[263:262]),
        .DOB(wr_buf_out_data_w[261:260]),
        .DOC(wr_buf_out_data_w[259:258]),
        .DOD(\NLW_wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[43].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[263]),
        .I1(app_wdf_data_r1[263]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[263]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[43].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[262]),
        .I1(app_wdf_data_r1[262]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[262]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[43].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[261]),
        .I1(app_wdf_data_r1[261]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[261]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[43].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[260]),
        .I1(app_wdf_data_r1[260]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[260]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[43].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[259]),
        .I1(app_wdf_data_r1[259]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[259]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[43].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[258]),
        .I1(app_wdf_data_r1[258]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[258]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[44].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[269:268]),
        .DIB(wr_buf_in_data[267:266]),
        .DIC(wr_buf_in_data[265:264]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[269:268]),
        .DOB(wr_buf_out_data_w[267:266]),
        .DOC(wr_buf_out_data_w[265:264]),
        .DOD(\NLW_wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[44].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[269]),
        .I1(app_wdf_data_r1[269]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[269]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[44].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[268]),
        .I1(app_wdf_data_r1[268]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[268]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[44].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[267]),
        .I1(app_wdf_data_r1[267]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[267]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[44].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[266]),
        .I1(app_wdf_data_r1[266]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[266]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[44].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[265]),
        .I1(app_wdf_data_r1[265]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[265]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[44].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[264]),
        .I1(app_wdf_data_r1[264]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[264]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[45].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[275:274]),
        .DIB(wr_buf_in_data[273:272]),
        .DIC(wr_buf_in_data[271:270]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[275:274]),
        .DOB(wr_buf_out_data_w[273:272]),
        .DOC(wr_buf_out_data_w[271:270]),
        .DOD(\NLW_wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[45].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[275]),
        .I1(app_wdf_data_r1[275]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[275]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[45].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[274]),
        .I1(app_wdf_data_r1[274]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[274]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[45].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[273]),
        .I1(app_wdf_data_r1[273]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[273]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[45].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[272]),
        .I1(app_wdf_data_r1[272]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[272]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[45].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[271]),
        .I1(app_wdf_data_r1[271]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[271]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[45].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[270]),
        .I1(app_wdf_data_r1[270]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[270]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[46].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[281:280]),
        .DIB(wr_buf_in_data[279:278]),
        .DIC(wr_buf_in_data[277:276]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[281:280]),
        .DOB(wr_buf_out_data_w[279:278]),
        .DOC(wr_buf_out_data_w[277:276]),
        .DOD(\NLW_wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[46].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[281]),
        .I1(app_wdf_data_r1[281]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[281]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[46].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[280]),
        .I1(app_wdf_data_r1[280]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[280]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[46].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[279]),
        .I1(app_wdf_data_r1[279]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[279]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[46].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[278]),
        .I1(app_wdf_data_r1[278]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[278]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[46].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[277]),
        .I1(app_wdf_data_r1[277]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[277]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[46].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[276]),
        .I1(app_wdf_data_r1[276]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[276]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[47].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[287:286]),
        .DIB(wr_buf_in_data[285:284]),
        .DIC(wr_buf_in_data[283:282]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[287:286]),
        .DOB(wr_buf_out_data_w[285:284]),
        .DOC(wr_buf_out_data_w[283:282]),
        .DOD(\NLW_wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[47].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[287]),
        .I1(app_wdf_data_r1[287]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[287]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[47].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[286]),
        .I1(app_wdf_data_r1[286]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[286]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[47].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[285]),
        .I1(app_wdf_data_r1[285]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[285]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[47].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[284]),
        .I1(app_wdf_data_r1[284]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[284]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[47].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[283]),
        .I1(app_wdf_data_r1[283]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[283]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[47].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[282]),
        .I1(app_wdf_data_r1[282]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[282]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[48].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[293:292]),
        .DIB(wr_buf_in_data[291:290]),
        .DIC(wr_buf_in_data[289:288]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[293:292]),
        .DOB(wr_buf_out_data_w[291:290]),
        .DOC(wr_buf_out_data_w[289:288]),
        .DOD(\NLW_wr_buffer_ram[48].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[48].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[293]),
        .I1(app_wdf_data_r1[293]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[293]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[48].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[292]),
        .I1(app_wdf_data_r1[292]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[292]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[48].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[291]),
        .I1(app_wdf_data_r1[291]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[291]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[48].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[290]),
        .I1(app_wdf_data_r1[290]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[290]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[48].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[289]),
        .I1(app_wdf_data_r1[289]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[289]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[48].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[288]),
        .I1(app_wdf_data_r1[288]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[288]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[49].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[299:298]),
        .DIB(wr_buf_in_data[297:296]),
        .DIC(wr_buf_in_data[295:294]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[299:298]),
        .DOB(wr_buf_out_data_w[297:296]),
        .DOC(wr_buf_out_data_w[295:294]),
        .DOD(\NLW_wr_buffer_ram[49].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[49].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[299]),
        .I1(app_wdf_data_r1[299]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[299]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[49].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[298]),
        .I1(app_wdf_data_r1[298]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[298]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[49].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[297]),
        .I1(app_wdf_data_r1[297]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[297]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[49].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[296]),
        .I1(app_wdf_data_r1[296]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[296]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[49].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[295]),
        .I1(app_wdf_data_r1[295]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[295]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[49].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[294]),
        .I1(app_wdf_data_r1[294]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[294]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[4].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[29:28]),
        .DIB(wr_buf_in_data[27:26]),
        .DIC(wr_buf_in_data[25:24]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[29:28]),
        .DOB(wr_buf_out_data_w[27:26]),
        .DOC(wr_buf_out_data_w[25:24]),
        .DOD(\NLW_wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[4].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[29]),
        .I1(app_wdf_data_r1[29]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[29]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[4].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[28]),
        .I1(app_wdf_data_r1[28]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[28]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[4].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[27]),
        .I1(app_wdf_data_r1[27]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[27]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[4].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[26]),
        .I1(app_wdf_data_r1[26]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[26]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[4].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[25]),
        .I1(app_wdf_data_r1[25]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[25]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[4].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[24]),
        .I1(app_wdf_data_r1[24]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[24]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[50].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[305:304]),
        .DIB(wr_buf_in_data[303:302]),
        .DIC(wr_buf_in_data[301:300]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[305:304]),
        .DOB(wr_buf_out_data_w[303:302]),
        .DOC(wr_buf_out_data_w[301:300]),
        .DOD(\NLW_wr_buffer_ram[50].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[50].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[305]),
        .I1(app_wdf_data_r1[305]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[305]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[50].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[304]),
        .I1(app_wdf_data_r1[304]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[304]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[50].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[303]),
        .I1(app_wdf_data_r1[303]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[303]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[50].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[302]),
        .I1(app_wdf_data_r1[302]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[302]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[50].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[301]),
        .I1(app_wdf_data_r1[301]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[301]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[50].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[300]),
        .I1(app_wdf_data_r1[300]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[300]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[51].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[311:310]),
        .DIB(wr_buf_in_data[309:308]),
        .DIC(wr_buf_in_data[307:306]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[311:310]),
        .DOB(wr_buf_out_data_w[309:308]),
        .DOC(wr_buf_out_data_w[307:306]),
        .DOD(\NLW_wr_buffer_ram[51].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[51].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[311]),
        .I1(app_wdf_data_r1[311]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[311]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[51].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[310]),
        .I1(app_wdf_data_r1[310]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[310]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[51].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[309]),
        .I1(app_wdf_data_r1[309]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[309]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[51].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[308]),
        .I1(app_wdf_data_r1[308]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[308]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[51].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[307]),
        .I1(app_wdf_data_r1[307]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[307]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[51].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[306]),
        .I1(app_wdf_data_r1[306]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[306]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[52].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[317:316]),
        .DIB(wr_buf_in_data[315:314]),
        .DIC(wr_buf_in_data[313:312]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[317:316]),
        .DOB(wr_buf_out_data_w[315:314]),
        .DOC(wr_buf_out_data_w[313:312]),
        .DOD(\NLW_wr_buffer_ram[52].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[52].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[317]),
        .I1(app_wdf_data_r1[317]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[317]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[52].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[316]),
        .I1(app_wdf_data_r1[316]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[316]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[52].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[315]),
        .I1(app_wdf_data_r1[315]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[315]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[52].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[314]),
        .I1(app_wdf_data_r1[314]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[314]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[52].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[313]),
        .I1(app_wdf_data_r1[313]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[313]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[52].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[312]),
        .I1(app_wdf_data_r1[312]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[312]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[53].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[323:322]),
        .DIB(wr_buf_in_data[321:320]),
        .DIC(wr_buf_in_data[319:318]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[323:322]),
        .DOB(wr_buf_out_data_w[321:320]),
        .DOC(wr_buf_out_data_w[319:318]),
        .DOD(\NLW_wr_buffer_ram[53].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[53].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[323]),
        .I1(app_wdf_data_r1[323]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[323]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[53].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[322]),
        .I1(app_wdf_data_r1[322]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[322]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[53].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[321]),
        .I1(app_wdf_data_r1[321]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[321]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[53].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[320]),
        .I1(app_wdf_data_r1[320]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[320]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[53].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[319]),
        .I1(app_wdf_data_r1[319]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[319]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[53].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[318]),
        .I1(app_wdf_data_r1[318]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[318]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[54].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[329:328]),
        .DIB(wr_buf_in_data[327:326]),
        .DIC(wr_buf_in_data[325:324]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[329:328]),
        .DOB(wr_buf_out_data_w[327:326]),
        .DOC(wr_buf_out_data_w[325:324]),
        .DOD(\NLW_wr_buffer_ram[54].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[54].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[329]),
        .I1(app_wdf_data_r1[329]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[329]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[54].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[328]),
        .I1(app_wdf_data_r1[328]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[328]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[54].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[327]),
        .I1(app_wdf_data_r1[327]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[327]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[54].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[326]),
        .I1(app_wdf_data_r1[326]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[326]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[54].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[325]),
        .I1(app_wdf_data_r1[325]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[325]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[54].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[324]),
        .I1(app_wdf_data_r1[324]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[324]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[55].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[335:334]),
        .DIB(wr_buf_in_data[333:332]),
        .DIC(wr_buf_in_data[331:330]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[335:334]),
        .DOB(wr_buf_out_data_w[333:332]),
        .DOC(wr_buf_out_data_w[331:330]),
        .DOD(\NLW_wr_buffer_ram[55].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[55].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[335]),
        .I1(app_wdf_data_r1[335]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[335]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[55].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[334]),
        .I1(app_wdf_data_r1[334]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[334]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[55].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[333]),
        .I1(app_wdf_data_r1[333]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[333]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[55].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[332]),
        .I1(app_wdf_data_r1[332]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[332]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[55].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[331]),
        .I1(app_wdf_data_r1[331]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[331]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[55].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[330]),
        .I1(app_wdf_data_r1[330]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[330]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[56].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[341:340]),
        .DIB(wr_buf_in_data[339:338]),
        .DIC(wr_buf_in_data[337:336]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[341:340]),
        .DOB(wr_buf_out_data_w[339:338]),
        .DOC(wr_buf_out_data_w[337:336]),
        .DOD(\NLW_wr_buffer_ram[56].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[56].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[341]),
        .I1(app_wdf_data_r1[341]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[341]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[56].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[340]),
        .I1(app_wdf_data_r1[340]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[340]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[56].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[339]),
        .I1(app_wdf_data_r1[339]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[339]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[56].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[338]),
        .I1(app_wdf_data_r1[338]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[338]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[56].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[337]),
        .I1(app_wdf_data_r1[337]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[337]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[56].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[336]),
        .I1(app_wdf_data_r1[336]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[336]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[57].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[347:346]),
        .DIB(wr_buf_in_data[345:344]),
        .DIC(wr_buf_in_data[343:342]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[347:346]),
        .DOB(wr_buf_out_data_w[345:344]),
        .DOC(wr_buf_out_data_w[343:342]),
        .DOD(\NLW_wr_buffer_ram[57].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[57].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[347]),
        .I1(app_wdf_data_r1[347]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[347]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[57].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[346]),
        .I1(app_wdf_data_r1[346]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[346]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[57].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[345]),
        .I1(app_wdf_data_r1[345]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[345]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[57].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[344]),
        .I1(app_wdf_data_r1[344]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[344]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[57].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[343]),
        .I1(app_wdf_data_r1[343]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[343]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[57].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[342]),
        .I1(app_wdf_data_r1[342]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[342]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[58].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[353:352]),
        .DIB(wr_buf_in_data[351:350]),
        .DIC(wr_buf_in_data[349:348]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[353:352]),
        .DOB(wr_buf_out_data_w[351:350]),
        .DOC(wr_buf_out_data_w[349:348]),
        .DOD(\NLW_wr_buffer_ram[58].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[58].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[353]),
        .I1(app_wdf_data_r1[353]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[353]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[58].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[352]),
        .I1(app_wdf_data_r1[352]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[352]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[58].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[351]),
        .I1(app_wdf_data_r1[351]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[351]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[58].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[350]),
        .I1(app_wdf_data_r1[350]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[350]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[58].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[349]),
        .I1(app_wdf_data_r1[349]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[349]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[58].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[348]),
        .I1(app_wdf_data_r1[348]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[348]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[59].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[359:358]),
        .DIB(wr_buf_in_data[357:356]),
        .DIC(wr_buf_in_data[355:354]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[359:358]),
        .DOB(wr_buf_out_data_w[357:356]),
        .DOC(wr_buf_out_data_w[355:354]),
        .DOD(\NLW_wr_buffer_ram[59].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[59].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[359]),
        .I1(app_wdf_data_r1[359]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[359]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[59].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[358]),
        .I1(app_wdf_data_r1[358]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[358]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[59].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[357]),
        .I1(app_wdf_data_r1[357]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[357]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[59].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[356]),
        .I1(app_wdf_data_r1[356]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[356]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[59].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[355]),
        .I1(app_wdf_data_r1[355]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[355]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[59].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[354]),
        .I1(app_wdf_data_r1[354]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[354]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[5].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[35:34]),
        .DIB(wr_buf_in_data[33:32]),
        .DIC(wr_buf_in_data[31:30]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[35:34]),
        .DOB(wr_buf_out_data_w[33:32]),
        .DOC(wr_buf_out_data_w[31:30]),
        .DOD(\NLW_wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[5].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[35]),
        .I1(app_wdf_data_r1[35]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[35]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[5].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[34]),
        .I1(app_wdf_data_r1[34]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[34]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[5].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[33]),
        .I1(app_wdf_data_r1[33]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[33]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[5].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[32]),
        .I1(app_wdf_data_r1[32]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[32]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[5].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[31]),
        .I1(app_wdf_data_r1[31]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[31]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[5].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[30]),
        .I1(app_wdf_data_r1[30]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[30]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[60].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[365:364]),
        .DIB(wr_buf_in_data[363:362]),
        .DIC(wr_buf_in_data[361:360]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[365:364]),
        .DOB(wr_buf_out_data_w[363:362]),
        .DOC(wr_buf_out_data_w[361:360]),
        .DOD(\NLW_wr_buffer_ram[60].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[60].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[365]),
        .I1(app_wdf_data_r1[365]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[365]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[60].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[364]),
        .I1(app_wdf_data_r1[364]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[364]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[60].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[363]),
        .I1(app_wdf_data_r1[363]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[363]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[60].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[362]),
        .I1(app_wdf_data_r1[362]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[362]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[60].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[361]),
        .I1(app_wdf_data_r1[361]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[361]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[60].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[360]),
        .I1(app_wdf_data_r1[360]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[360]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[61].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[371:370]),
        .DIB(wr_buf_in_data[369:368]),
        .DIC(wr_buf_in_data[367:366]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[371:370]),
        .DOB(wr_buf_out_data_w[369:368]),
        .DOC(wr_buf_out_data_w[367:366]),
        .DOD(\NLW_wr_buffer_ram[61].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[61].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[371]),
        .I1(app_wdf_data_r1[371]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[371]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[61].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[370]),
        .I1(app_wdf_data_r1[370]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[370]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[61].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[369]),
        .I1(app_wdf_data_r1[369]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[369]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[61].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[368]),
        .I1(app_wdf_data_r1[368]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[368]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[61].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[367]),
        .I1(app_wdf_data_r1[367]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[367]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[61].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[366]),
        .I1(app_wdf_data_r1[366]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[366]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[62].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[377:376]),
        .DIB(wr_buf_in_data[375:374]),
        .DIC(wr_buf_in_data[373:372]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[377:376]),
        .DOB(wr_buf_out_data_w[375:374]),
        .DOC(wr_buf_out_data_w[373:372]),
        .DOD(\NLW_wr_buffer_ram[62].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[62].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[377]),
        .I1(app_wdf_data_r1[377]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[377]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[62].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[376]),
        .I1(app_wdf_data_r1[376]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[376]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[62].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[375]),
        .I1(app_wdf_data_r1[375]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[375]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[62].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[374]),
        .I1(app_wdf_data_r1[374]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[374]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[62].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[373]),
        .I1(app_wdf_data_r1[373]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[373]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[62].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[372]),
        .I1(app_wdf_data_r1[372]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[372]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[63].RAM32M0 
       (.ADDRA({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[40].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[383:382]),
        .DIB(wr_buf_in_data[381:380]),
        .DIC(wr_buf_in_data[379:378]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[383:382]),
        .DOB(wr_buf_out_data_w[381:380]),
        .DOC(wr_buf_out_data_w[379:378]),
        .DOD(\NLW_wr_buffer_ram[63].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[63].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[383]),
        .I1(app_wdf_data_r1[383]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[383]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[63].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[382]),
        .I1(app_wdf_data_r1[382]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[382]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[63].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[381]),
        .I1(app_wdf_data_r1[381]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[381]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[63].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[380]),
        .I1(app_wdf_data_r1[380]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[380]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[63].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[379]),
        .I1(app_wdf_data_r1[379]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[379]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[63].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[378]),
        .I1(app_wdf_data_r1[378]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[378]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[64].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[389:388]),
        .DIB(wr_buf_in_data[387:386]),
        .DIC(wr_buf_in_data[385:384]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[389:388]),
        .DOB(wr_buf_out_data_w[387:386]),
        .DOC(wr_buf_out_data_w[385:384]),
        .DOD(\NLW_wr_buffer_ram[64].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[64].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[389]),
        .I1(app_wdf_data_r1[389]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[389]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[64].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[388]),
        .I1(app_wdf_data_r1[388]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[388]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[64].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[387]),
        .I1(app_wdf_data_r1[387]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[387]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[64].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[386]),
        .I1(app_wdf_data_r1[386]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[386]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[64].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[385]),
        .I1(app_wdf_data_r1[385]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[385]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[64].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[384]),
        .I1(app_wdf_data_r1[384]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[384]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[65].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[395:394]),
        .DIB(wr_buf_in_data[393:392]),
        .DIC(wr_buf_in_data[391:390]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[395:394]),
        .DOB(wr_buf_out_data_w[393:392]),
        .DOC(wr_buf_out_data_w[391:390]),
        .DOD(\NLW_wr_buffer_ram[65].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[65].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[395]),
        .I1(app_wdf_data_r1[395]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[395]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[65].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[394]),
        .I1(app_wdf_data_r1[394]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[394]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[65].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[393]),
        .I1(app_wdf_data_r1[393]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[393]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[65].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[392]),
        .I1(app_wdf_data_r1[392]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[392]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[65].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[391]),
        .I1(app_wdf_data_r1[391]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[391]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[65].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[390]),
        .I1(app_wdf_data_r1[390]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[390]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[66].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[401:400]),
        .DIB(wr_buf_in_data[399:398]),
        .DIC(wr_buf_in_data[397:396]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[401:400]),
        .DOB(wr_buf_out_data_w[399:398]),
        .DOC(wr_buf_out_data_w[397:396]),
        .DOD(\NLW_wr_buffer_ram[66].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[66].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[401]),
        .I1(app_wdf_data_r1[401]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[401]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[66].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[400]),
        .I1(app_wdf_data_r1[400]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[400]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[66].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[399]),
        .I1(app_wdf_data_r1[399]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[399]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[66].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[398]),
        .I1(app_wdf_data_r1[398]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[398]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[66].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[397]),
        .I1(app_wdf_data_r1[397]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[397]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[66].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[396]),
        .I1(app_wdf_data_r1[396]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[396]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[67].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[407:406]),
        .DIB(wr_buf_in_data[405:404]),
        .DIC(wr_buf_in_data[403:402]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[407:406]),
        .DOB(wr_buf_out_data_w[405:404]),
        .DOC(wr_buf_out_data_w[403:402]),
        .DOD(\NLW_wr_buffer_ram[67].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[67].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[407]),
        .I1(app_wdf_data_r1[407]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[407]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[67].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[406]),
        .I1(app_wdf_data_r1[406]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[406]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[67].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[405]),
        .I1(app_wdf_data_r1[405]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[405]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[67].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[404]),
        .I1(app_wdf_data_r1[404]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[404]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[67].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[403]),
        .I1(app_wdf_data_r1[403]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[403]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[67].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[402]),
        .I1(app_wdf_data_r1[402]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[402]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[68].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[413:412]),
        .DIB(wr_buf_in_data[411:410]),
        .DIC(wr_buf_in_data[409:408]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[413:412]),
        .DOB(wr_buf_out_data_w[411:410]),
        .DOC(wr_buf_out_data_w[409:408]),
        .DOD(\NLW_wr_buffer_ram[68].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[68].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[413]),
        .I1(app_wdf_data_r1[413]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[413]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[68].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[412]),
        .I1(app_wdf_data_r1[412]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[412]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[68].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[411]),
        .I1(app_wdf_data_r1[411]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[411]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[68].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[410]),
        .I1(app_wdf_data_r1[410]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[410]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[68].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[409]),
        .I1(app_wdf_data_r1[409]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[409]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[68].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[408]),
        .I1(app_wdf_data_r1[408]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[408]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[69].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[419:418]),
        .DIB(wr_buf_in_data[417:416]),
        .DIC(wr_buf_in_data[415:414]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[419:418]),
        .DOB(wr_buf_out_data_w[417:416]),
        .DOC(wr_buf_out_data_w[415:414]),
        .DOD(\NLW_wr_buffer_ram[69].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[69].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[419]),
        .I1(app_wdf_data_r1[419]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[419]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[69].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[418]),
        .I1(app_wdf_data_r1[418]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[418]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[69].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[417]),
        .I1(app_wdf_data_r1[417]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[417]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[69].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[416]),
        .I1(app_wdf_data_r1[416]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[416]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[69].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[415]),
        .I1(app_wdf_data_r1[415]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[415]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[69].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[414]),
        .I1(app_wdf_data_r1[414]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[414]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[6].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[41:40]),
        .DIB(wr_buf_in_data[39:38]),
        .DIC(wr_buf_in_data[37:36]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[41:40]),
        .DOB(wr_buf_out_data_w[39:38]),
        .DOC(wr_buf_out_data_w[37:36]),
        .DOD(\NLW_wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[6].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[41]),
        .I1(app_wdf_data_r1[41]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[41]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[6].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[40]),
        .I1(app_wdf_data_r1[40]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[40]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[6].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[39]),
        .I1(app_wdf_data_r1[39]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[39]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[6].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[38]),
        .I1(app_wdf_data_r1[38]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[38]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[6].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[37]),
        .I1(app_wdf_data_r1[37]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[37]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[6].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[36]),
        .I1(app_wdf_data_r1[36]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[36]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[70].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[425:424]),
        .DIB(wr_buf_in_data[423:422]),
        .DIC(wr_buf_in_data[421:420]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[425:424]),
        .DOB(wr_buf_out_data_w[423:422]),
        .DOC(wr_buf_out_data_w[421:420]),
        .DOD(\NLW_wr_buffer_ram[70].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[70].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[425]),
        .I1(app_wdf_data_r1[425]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[425]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[70].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[424]),
        .I1(app_wdf_data_r1[424]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[424]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[70].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[423]),
        .I1(app_wdf_data_r1[423]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[423]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[70].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[422]),
        .I1(app_wdf_data_r1[422]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[422]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[70].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[421]),
        .I1(app_wdf_data_r1[421]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[421]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[70].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[420]),
        .I1(app_wdf_data_r1[420]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[420]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[71].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[431:430]),
        .DIB(wr_buf_in_data[429:428]),
        .DIC(wr_buf_in_data[427:426]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[431:430]),
        .DOB(wr_buf_out_data_w[429:428]),
        .DOC(wr_buf_out_data_w[427:426]),
        .DOD(\NLW_wr_buffer_ram[71].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[71].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[431]),
        .I1(app_wdf_data_r1[431]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[431]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[71].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[430]),
        .I1(app_wdf_data_r1[430]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[430]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[71].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[429]),
        .I1(app_wdf_data_r1[429]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[429]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[71].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[428]),
        .I1(app_wdf_data_r1[428]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[428]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[71].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[427]),
        .I1(app_wdf_data_r1[427]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[427]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[71].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[426]),
        .I1(app_wdf_data_r1[426]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[426]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[72].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[437:436]),
        .DIB(wr_buf_in_data[435:434]),
        .DIC(wr_buf_in_data[433:432]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[437:436]),
        .DOB(wr_buf_out_data_w[435:434]),
        .DOC(wr_buf_out_data_w[433:432]),
        .DOD(\NLW_wr_buffer_ram[72].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[72].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[437]),
        .I1(app_wdf_data_r1[437]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[437]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[72].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[436]),
        .I1(app_wdf_data_r1[436]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[436]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[72].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[435]),
        .I1(app_wdf_data_r1[435]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[435]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[72].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[434]),
        .I1(app_wdf_data_r1[434]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[434]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[72].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[433]),
        .I1(app_wdf_data_r1[433]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[433]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[72].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[432]),
        .I1(app_wdf_data_r1[432]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[432]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[73].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[443:442]),
        .DIB(wr_buf_in_data[441:440]),
        .DIC(wr_buf_in_data[439:438]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[443:442]),
        .DOB(wr_buf_out_data_w[441:440]),
        .DOC(wr_buf_out_data_w[439:438]),
        .DOD(\NLW_wr_buffer_ram[73].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[73].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[443]),
        .I1(app_wdf_data_r1[443]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[443]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[73].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[442]),
        .I1(app_wdf_data_r1[442]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[442]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[73].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[441]),
        .I1(app_wdf_data_r1[441]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[441]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[73].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[440]),
        .I1(app_wdf_data_r1[440]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[440]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[73].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[439]),
        .I1(app_wdf_data_r1[439]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[439]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[73].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[438]),
        .I1(app_wdf_data_r1[438]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[438]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[74].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[449:448]),
        .DIB(wr_buf_in_data[447:446]),
        .DIC(wr_buf_in_data[445:444]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[449:448]),
        .DOB(wr_buf_out_data_w[447:446]),
        .DOC(wr_buf_out_data_w[445:444]),
        .DOD(\NLW_wr_buffer_ram[74].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[74].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[449]),
        .I1(app_wdf_data_r1[449]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[449]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[74].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[448]),
        .I1(app_wdf_data_r1[448]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[448]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[74].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[447]),
        .I1(app_wdf_data_r1[447]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[447]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[74].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[446]),
        .I1(app_wdf_data_r1[446]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[446]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[74].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[445]),
        .I1(app_wdf_data_r1[445]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[445]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[74].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[444]),
        .I1(app_wdf_data_r1[444]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[444]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[75].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[455:454]),
        .DIB(wr_buf_in_data[453:452]),
        .DIC(wr_buf_in_data[451:450]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[455:454]),
        .DOB(wr_buf_out_data_w[453:452]),
        .DOC(wr_buf_out_data_w[451:450]),
        .DOD(\NLW_wr_buffer_ram[75].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[75].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[455]),
        .I1(app_wdf_data_r1[455]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[455]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[75].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[454]),
        .I1(app_wdf_data_r1[454]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[454]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[75].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[453]),
        .I1(app_wdf_data_r1[453]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[453]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[75].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[452]),
        .I1(app_wdf_data_r1[452]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[452]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[75].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[451]),
        .I1(app_wdf_data_r1[451]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[451]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[75].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[450]),
        .I1(app_wdf_data_r1[450]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[450]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[76].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[461:460]),
        .DIB(wr_buf_in_data[459:458]),
        .DIC(wr_buf_in_data[457:456]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[461:460]),
        .DOB(wr_buf_out_data_w[459:458]),
        .DOC(wr_buf_out_data_w[457:456]),
        .DOD(\NLW_wr_buffer_ram[76].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[76].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[461]),
        .I1(app_wdf_data_r1[461]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[461]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[76].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[460]),
        .I1(app_wdf_data_r1[460]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[460]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[76].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[459]),
        .I1(app_wdf_data_r1[459]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[459]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[76].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[458]),
        .I1(app_wdf_data_r1[458]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[458]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[76].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[457]),
        .I1(app_wdf_data_r1[457]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[457]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[76].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[456]),
        .I1(app_wdf_data_r1[456]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[456]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[77].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[467:466]),
        .DIB(wr_buf_in_data[465:464]),
        .DIC(wr_buf_in_data[463:462]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[467:466]),
        .DOB(wr_buf_out_data_w[465:464]),
        .DOC(wr_buf_out_data_w[463:462]),
        .DOD(\NLW_wr_buffer_ram[77].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[77].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[467]),
        .I1(app_wdf_data_r1[467]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[467]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[77].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[466]),
        .I1(app_wdf_data_r1[466]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[466]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[77].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[465]),
        .I1(app_wdf_data_r1[465]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[465]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[77].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[464]),
        .I1(app_wdf_data_r1[464]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[464]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[77].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[463]),
        .I1(app_wdf_data_r1[463]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[463]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[77].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[462]),
        .I1(app_wdf_data_r1[462]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[462]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[78].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[473:472]),
        .DIB(wr_buf_in_data[471:470]),
        .DIC(wr_buf_in_data[469:468]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[473:472]),
        .DOB(wr_buf_out_data_w[471:470]),
        .DOC(wr_buf_out_data_w[469:468]),
        .DOD(\NLW_wr_buffer_ram[78].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[78].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[473]),
        .I1(app_wdf_data_r1[473]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[473]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[78].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[472]),
        .I1(app_wdf_data_r1[472]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[472]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[78].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[471]),
        .I1(app_wdf_data_r1[471]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[471]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[78].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[470]),
        .I1(app_wdf_data_r1[470]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[470]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[78].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[469]),
        .I1(app_wdf_data_r1[469]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[469]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[78].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[468]),
        .I1(app_wdf_data_r1[468]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[468]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[79].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[479:478]),
        .DIB(wr_buf_in_data[477:476]),
        .DIC(wr_buf_in_data[475:474]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[479:478]),
        .DOB(wr_buf_out_data_w[477:476]),
        .DOC(wr_buf_out_data_w[475:474]),
        .DOD(\NLW_wr_buffer_ram[79].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[79].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[479]),
        .I1(app_wdf_data_r1[479]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[479]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[79].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[478]),
        .I1(app_wdf_data_r1[478]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[478]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[79].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[477]),
        .I1(app_wdf_data_r1[477]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[477]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[79].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[476]),
        .I1(app_wdf_data_r1[476]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[476]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[79].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[475]),
        .I1(app_wdf_data_r1[475]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[475]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[79].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[474]),
        .I1(app_wdf_data_r1[474]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[474]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[7].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[47:46]),
        .DIB(wr_buf_in_data[45:44]),
        .DIC(wr_buf_in_data[43:42]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[47:46]),
        .DOB(wr_buf_out_data_w[45:44]),
        .DOC(wr_buf_out_data_w[43:42]),
        .DOD(\NLW_wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[7].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[47]),
        .I1(app_wdf_data_r1[47]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[47]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[7].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[46]),
        .I1(app_wdf_data_r1[46]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[46]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[7].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[45]),
        .I1(app_wdf_data_r1[45]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[45]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[7].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[44]),
        .I1(app_wdf_data_r1[44]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[44]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[7].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[43]),
        .I1(app_wdf_data_r1[43]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[43]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[7].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[42]),
        .I1(app_wdf_data_r1[42]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[42]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[80].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[485:484]),
        .DIB(wr_buf_in_data[483:482]),
        .DIC(wr_buf_in_data[481:480]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[485:484]),
        .DOB(wr_buf_out_data_w[483:482]),
        .DOC(wr_buf_out_data_w[481:480]),
        .DOD(\NLW_wr_buffer_ram[80].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[80].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[485]),
        .I1(app_wdf_data_r1[485]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[485]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[80].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[484]),
        .I1(app_wdf_data_r1[484]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[484]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[80].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[483]),
        .I1(app_wdf_data_r1[483]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[483]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[80].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[482]),
        .I1(app_wdf_data_r1[482]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[482]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[80].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[481]),
        .I1(app_wdf_data_r1[481]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[481]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[80].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[480]),
        .I1(app_wdf_data_r1[480]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[480]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[81].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[491:490]),
        .DIB(wr_buf_in_data[489:488]),
        .DIC(wr_buf_in_data[487:486]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[491:490]),
        .DOB(wr_buf_out_data_w[489:488]),
        .DOC(wr_buf_out_data_w[487:486]),
        .DOD(\NLW_wr_buffer_ram[81].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[81].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[491]),
        .I1(app_wdf_data_r1[491]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[491]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[81].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[490]),
        .I1(app_wdf_data_r1[490]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[490]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[81].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[489]),
        .I1(app_wdf_data_r1[489]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[489]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[81].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[488]),
        .I1(app_wdf_data_r1[488]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[488]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[81].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[487]),
        .I1(app_wdf_data_r1[487]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[487]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[81].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[486]),
        .I1(app_wdf_data_r1[486]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[486]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[82].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[497:496]),
        .DIB(wr_buf_in_data[495:494]),
        .DIC(wr_buf_in_data[493:492]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[497:496]),
        .DOB(wr_buf_out_data_w[495:494]),
        .DOC(wr_buf_out_data_w[493:492]),
        .DOD(\NLW_wr_buffer_ram[82].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[82].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[497]),
        .I1(app_wdf_data_r1[497]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[497]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[82].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[496]),
        .I1(app_wdf_data_r1[496]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[496]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[82].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[495]),
        .I1(app_wdf_data_r1[495]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[495]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[82].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[494]),
        .I1(app_wdf_data_r1[494]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[494]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[82].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[493]),
        .I1(app_wdf_data_r1[493]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[493]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[82].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[492]),
        .I1(app_wdf_data_r1[492]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[492]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[83].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[503:502]),
        .DIB(wr_buf_in_data[501:500]),
        .DIC(wr_buf_in_data[499:498]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[503:502]),
        .DOB(wr_buf_out_data_w[501:500]),
        .DOC(wr_buf_out_data_w[499:498]),
        .DOD(\NLW_wr_buffer_ram[83].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[83].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[503]),
        .I1(app_wdf_data_r1[503]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[503]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[83].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[502]),
        .I1(app_wdf_data_r1[502]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[502]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[83].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[501]),
        .I1(app_wdf_data_r1[501]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[501]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[83].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[500]),
        .I1(app_wdf_data_r1[500]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[500]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[83].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[499]),
        .I1(app_wdf_data_r1[499]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[499]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[83].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[498]),
        .I1(app_wdf_data_r1[498]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[498]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[84].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[509:508]),
        .DIB(wr_buf_in_data[507:506]),
        .DIC(wr_buf_in_data[505:504]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[509:508]),
        .DOB(wr_buf_out_data_w[507:506]),
        .DOC(wr_buf_out_data_w[505:504]),
        .DOD(\NLW_wr_buffer_ram[84].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[84].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[509]),
        .I1(app_wdf_data_r1[509]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[509]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[84].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[508]),
        .I1(app_wdf_data_r1[508]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[508]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[84].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[507]),
        .I1(app_wdf_data_r1[507]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[507]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[84].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[506]),
        .I1(app_wdf_data_r1[506]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[506]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[84].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[505]),
        .I1(app_wdf_data_r1[505]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[505]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[84].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[504]),
        .I1(app_wdf_data_r1[504]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[504]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[85].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[515:514]),
        .DIB(wr_buf_in_data[513:512]),
        .DIC(wr_buf_in_data[511:510]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[515:514]),
        .DOB(wr_buf_out_data_w[513:512]),
        .DOC(wr_buf_out_data_w[511:510]),
        .DOD(\NLW_wr_buffer_ram[85].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[85].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_mask[3]),
        .I1(app_wdf_mask_r1[3]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[515]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[85].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_mask[2]),
        .I1(app_wdf_mask_r1[2]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[514]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[85].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_mask[1]),
        .I1(app_wdf_mask_r1[1]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[513]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[85].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_mask[0]),
        .I1(app_wdf_mask_r1[0]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[512]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[85].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[511]),
        .I1(app_wdf_data_r1[511]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[511]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[85].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[510]),
        .I1(app_wdf_data_r1[510]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[510]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[86].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[521:520]),
        .DIB(wr_buf_in_data[519:518]),
        .DIC(wr_buf_in_data[517:516]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[521:520]),
        .DOB(wr_buf_out_data_w[519:518]),
        .DOC(wr_buf_out_data_w[517:516]),
        .DOD(\NLW_wr_buffer_ram[86].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[86].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_mask[9]),
        .I1(app_wdf_mask_r1[9]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[521]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[86].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_mask[8]),
        .I1(app_wdf_mask_r1[8]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[520]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[86].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_mask[7]),
        .I1(app_wdf_mask_r1[7]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[519]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[86].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_mask[6]),
        .I1(app_wdf_mask_r1[6]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[518]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[86].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_mask[5]),
        .I1(app_wdf_mask_r1[5]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[517]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[86].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_mask[4]),
        .I1(app_wdf_mask_r1[4]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[516]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[87].RAM32M0 
       (.ADDRA({ADDRA,1'b0}),
        .ADDRB({ADDRA,1'b0}),
        .ADDRC({ADDRA,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[527:526]),
        .DIB(wr_buf_in_data[525:524]),
        .DIC(wr_buf_in_data[523:522]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[527:526]),
        .DOB(wr_buf_out_data_w[525:524]),
        .DOC(wr_buf_out_data_w[523:522]),
        .DOD(\NLW_wr_buffer_ram[87].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[87].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_mask[15]),
        .I1(app_wdf_mask_r1[15]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[527]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[87].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_mask[14]),
        .I1(app_wdf_mask_r1[14]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[526]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[87].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_mask[13]),
        .I1(app_wdf_mask_r1[13]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[525]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[87].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_mask[12]),
        .I1(app_wdf_mask_r1[12]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[524]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[87].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_mask[11]),
        .I1(app_wdf_mask_r1[11]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[523]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[87].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_mask[10]),
        .I1(app_wdf_mask_r1[10]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[522]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[88].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[533:532]),
        .DIB(wr_buf_in_data[531:530]),
        .DIC(wr_buf_in_data[529:528]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[533:532]),
        .DOB(wr_buf_out_data_w[531:530]),
        .DOC(wr_buf_out_data_w[529:528]),
        .DOD(\NLW_wr_buffer_ram[88].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[88].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_mask[21]),
        .I1(app_wdf_mask_r1[21]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[533]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[88].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_mask[20]),
        .I1(app_wdf_mask_r1[20]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[532]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[88].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_mask[19]),
        .I1(app_wdf_mask_r1[19]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[531]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[88].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_mask[18]),
        .I1(app_wdf_mask_r1[18]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[530]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[88].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_mask[17]),
        .I1(app_wdf_mask_r1[17]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[529]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[88].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_mask[16]),
        .I1(app_wdf_mask_r1[16]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[528]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[89].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[539:538]),
        .DIB(wr_buf_in_data[537:536]),
        .DIC(wr_buf_in_data[535:534]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[539:538]),
        .DOB(wr_buf_out_data_w[537:536]),
        .DOC(wr_buf_out_data_w[535:534]),
        .DOD(\NLW_wr_buffer_ram[89].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[89].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_mask[27]),
        .I1(app_wdf_mask_r1[27]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[539]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[89].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_mask[26]),
        .I1(app_wdf_mask_r1[26]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[538]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[89].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_mask[25]),
        .I1(app_wdf_mask_r1[25]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[537]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[89].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_mask[24]),
        .I1(app_wdf_mask_r1[24]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[536]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[89].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_mask[23]),
        .I1(app_wdf_mask_r1[23]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[535]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[89].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_mask[22]),
        .I1(app_wdf_mask_r1[22]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[534]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[8].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[53:52]),
        .DIB(wr_buf_in_data[51:50]),
        .DIC(wr_buf_in_data[49:48]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[53:52]),
        .DOB(wr_buf_out_data_w[51:50]),
        .DOC(wr_buf_out_data_w[49:48]),
        .DOD(\NLW_wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[8].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[53]),
        .I1(app_wdf_data_r1[53]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[53]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[8].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[52]),
        .I1(app_wdf_data_r1[52]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[52]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[8].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[51]),
        .I1(app_wdf_data_r1[51]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[51]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[8].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[50]),
        .I1(app_wdf_data_r1[50]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[50]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[8].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[49]),
        .I1(app_wdf_data_r1[49]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[49]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[8].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[48]),
        .I1(app_wdf_data_r1[48]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[48]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[90].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[545:544]),
        .DIB(wr_buf_in_data[543:542]),
        .DIC(wr_buf_in_data[541:540]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[545:544]),
        .DOB(wr_buf_out_data_w[543:542]),
        .DOC(wr_buf_out_data_w[541:540]),
        .DOD(\NLW_wr_buffer_ram[90].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[90].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_mask[33]),
        .I1(app_wdf_mask_r1[33]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[545]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[90].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_mask[32]),
        .I1(app_wdf_mask_r1[32]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[544]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[90].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_mask[31]),
        .I1(app_wdf_mask_r1[31]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[543]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[90].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_mask[30]),
        .I1(app_wdf_mask_r1[30]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[542]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[90].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_mask[29]),
        .I1(app_wdf_mask_r1[29]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[541]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[90].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_mask[28]),
        .I1(app_wdf_mask_r1[28]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[540]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[91].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[551:550]),
        .DIB(wr_buf_in_data[549:548]),
        .DIC(wr_buf_in_data[547:546]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[551:550]),
        .DOB(wr_buf_out_data_w[549:548]),
        .DOC(wr_buf_out_data_w[547:546]),
        .DOD(\NLW_wr_buffer_ram[91].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[91].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_mask[39]),
        .I1(app_wdf_mask_r1[39]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[551]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[91].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_mask[38]),
        .I1(app_wdf_mask_r1[38]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[550]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[91].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_mask[37]),
        .I1(app_wdf_mask_r1[37]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[549]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[91].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_mask[36]),
        .I1(app_wdf_mask_r1[36]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[548]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[91].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_mask[35]),
        .I1(app_wdf_mask_r1[35]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[547]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[91].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_mask[34]),
        .I1(app_wdf_mask_r1[34]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[546]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[92].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[557:556]),
        .DIB(wr_buf_in_data[555:554]),
        .DIC(wr_buf_in_data[553:552]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[557:556]),
        .DOB(wr_buf_out_data_w[555:554]),
        .DOC(wr_buf_out_data_w[553:552]),
        .DOD(\NLW_wr_buffer_ram[92].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[92].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_mask[45]),
        .I1(app_wdf_mask_r1[45]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[557]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[92].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_mask[44]),
        .I1(app_wdf_mask_r1[44]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[556]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[92].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_mask[43]),
        .I1(app_wdf_mask_r1[43]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[555]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[92].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_mask[42]),
        .I1(app_wdf_mask_r1[42]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[554]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[92].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_mask[41]),
        .I1(app_wdf_mask_r1[41]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[553]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[92].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_mask[40]),
        .I1(app_wdf_mask_r1[40]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[552]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[93].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[563:562]),
        .DIB(wr_buf_in_data[561:560]),
        .DIC(wr_buf_in_data[559:558]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[563:562]),
        .DOB(wr_buf_out_data_w[561:560]),
        .DOC(wr_buf_out_data_w[559:558]),
        .DOD(\NLW_wr_buffer_ram[93].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[93].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_mask[51]),
        .I1(app_wdf_mask_r1[51]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[563]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[93].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_mask[50]),
        .I1(app_wdf_mask_r1[50]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[562]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[93].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_mask[49]),
        .I1(app_wdf_mask_r1[49]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[561]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[93].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_mask[48]),
        .I1(app_wdf_mask_r1[48]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[560]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[93].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_mask[47]),
        .I1(app_wdf_mask_r1[47]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[559]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[93].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_mask[46]),
        .I1(app_wdf_mask_r1[46]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[558]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[94].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[569:568]),
        .DIB(wr_buf_in_data[567:566]),
        .DIC(wr_buf_in_data[565:564]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[569:568]),
        .DOB(wr_buf_out_data_w[567:566]),
        .DOC(wr_buf_out_data_w[565:564]),
        .DOD(\NLW_wr_buffer_ram[94].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[94].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_mask[57]),
        .I1(app_wdf_mask_r1[57]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[569]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[94].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_mask[56]),
        .I1(app_wdf_mask_r1[56]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[568]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[94].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_mask[55]),
        .I1(app_wdf_mask_r1[55]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[567]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[94].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_mask[54]),
        .I1(app_wdf_mask_r1[54]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[566]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[94].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_mask[53]),
        .I1(app_wdf_mask_r1[53]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[565]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[94].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_mask[52]),
        .I1(app_wdf_mask_r1[52]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[564]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[95].RAM32M0 
       (.ADDRA({ADDRC,1'b0}),
        .ADDRB({ADDRC,1'b0}),
        .ADDRC({ADDRC,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[575:574]),
        .DIB(wr_buf_in_data[573:572]),
        .DIC(wr_buf_in_data[571:570]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[575:574]),
        .DOB(wr_buf_out_data_w[573:572]),
        .DOC(wr_buf_out_data_w[571:570]),
        .DOD(\NLW_wr_buffer_ram[95].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[95].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_mask[63]),
        .I1(app_wdf_mask_r1[63]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[575]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[95].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_mask[62]),
        .I1(app_wdf_mask_r1[62]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[574]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[95].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_mask[61]),
        .I1(app_wdf_mask_r1[61]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[573]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[95].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_mask[60]),
        .I1(app_wdf_mask_r1[60]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[572]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[95].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_mask[59]),
        .I1(app_wdf_mask_r1[59]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[571]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[95].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_mask[58]),
        .I1(app_wdf_mask_r1[58]),
        .I2(app_wdf_rdy_r_copy5),
        .O(wr_buf_in_data[570]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \wr_buffer_ram[9].RAM32M0 
       (.ADDRA({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRB({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRC({\wr_buffer_ram[8].RAM32M0_0 ,1'b0}),
        .ADDRD({wb_wr_data_addr_w,wb_wr_data_addr0_ns}),
        .DIA(wr_buf_in_data[59:58]),
        .DIB(wr_buf_in_data[57:56]),
        .DIC(wr_buf_in_data[55:54]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[59:58]),
        .DOB(wr_buf_out_data_w[57:56]),
        .DOC(wr_buf_out_data_w[55:54]),
        .DOD(\NLW_wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\rd_data_indx_r_reg[3]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[9].RAM32M0_i_1 
       (.I0(c0_ddr4_app_wdf_data[59]),
        .I1(app_wdf_data_r1[59]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[59]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[9].RAM32M0_i_2 
       (.I0(c0_ddr4_app_wdf_data[58]),
        .I1(app_wdf_data_r1[58]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[58]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[9].RAM32M0_i_3 
       (.I0(c0_ddr4_app_wdf_data[57]),
        .I1(app_wdf_data_r1[57]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[57]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[9].RAM32M0_i_4 
       (.I0(c0_ddr4_app_wdf_data[56]),
        .I1(app_wdf_data_r1[56]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[56]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[9].RAM32M0_i_5 
       (.I0(c0_ddr4_app_wdf_data[55]),
        .I1(app_wdf_data_r1[55]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[55]));
  LUT3 #(
    .INIT(8'hAC)) 
    \wr_buffer_ram[9].RAM32M0_i_6 
       (.I0(c0_ddr4_app_wdf_data[54]),
        .I1(app_wdf_data_r1[54]),
        .I2(app_wdf_rdy_r_copy2),
        .O(wr_buf_in_data[54]));
  LUT1 #(
    .INIT(2'h1)) 
    \wr_data_indx_r[0]_i_1 
       (.I0(wr_data_indx_r_reg[0]),
        .O(p_0_in__0__0[0]));
  LUT2 #(
    .INIT(4'h6)) 
    \wr_data_indx_r[1]_i_1 
       (.I0(wr_data_indx_r_reg[0]),
        .I1(wr_data_indx_r_reg[1]),
        .O(p_0_in__0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair3102" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \wr_data_indx_r[2]_i_1 
       (.I0(wr_data_indx_r_reg[0]),
        .I1(wr_data_indx_r_reg[1]),
        .I2(wr_data_indx_r_reg[2]),
        .O(p_0_in__0__0[2]));
  LUT6 #(
    .INIT(64'hCC00FFFF04000400)) 
    \wr_data_indx_r[3]_i_1 
       (.I0(p_0_in12_in),
        .I1(p_11_in),
        .I2(p_0_in2_in),
        .I3(\wr_data_indx_r_reg[0]_0 [1]),
        .I4(app_wdf_rdy_r_copy4),
        .I5(rd_data_upd_indx_r),
        .O(wr_data_addr_le));
  (* SOFT_HLUTNM = "soft_lutpair3102" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \wr_data_indx_r[3]_i_2 
       (.I0(wr_data_indx_r_reg[2]),
        .I1(wr_data_indx_r_reg[1]),
        .I2(wr_data_indx_r_reg[0]),
        .I3(wr_data_indx_r_reg[3]),
        .O(p_0_in__0__0[3]));
  FDSE \wr_data_indx_r_reg[0] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(wr_data_addr_le),
        .D(p_0_in__0__0[0]),
        .Q(wr_data_indx_r_reg[0]),
        .S(\wr_data_indx_r_reg[1]_0 ));
  FDRE \wr_data_indx_r_reg[1] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(wr_data_addr_le),
        .D(p_0_in__0__0[1]),
        .Q(wr_data_indx_r_reg[1]),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \wr_data_indx_r_reg[2] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(wr_data_addr_le),
        .D(p_0_in__0__0[2]),
        .Q(wr_data_indx_r_reg[2]),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \wr_data_indx_r_reg[3] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(wr_data_addr_le),
        .D(p_0_in__0__0[3]),
        .Q(wr_data_indx_r_reg[3]),
        .R(\wr_data_indx_r_reg[1]_0 ));
  LUT4 #(
    .INIT(16'hE178)) 
    \wr_req_cnt_r[1]_i_1 
       (.I0(wr_accepted),
        .I1(\wr_req_cnt_r_reg[1]_0 [0]),
        .I2(\wr_req_cnt_r_reg[1]_0 [1]),
        .I3(rd_data_upd_indx_r),
        .O(\wr_req_cnt_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAA96AAA)) 
    \wr_req_cnt_r[2]_i_1 
       (.I0(wr_req_cnt_r[2]),
        .I1(wr_accepted),
        .I2(\wr_req_cnt_r_reg[1]_0 [1]),
        .I3(\wr_req_cnt_r_reg[1]_0 [0]),
        .I4(rd_data_upd_indx_r),
        .I5(\wr_data_indx_r_reg[1]_0 ),
        .O(\wr_req_cnt_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000006AA9AAAA)) 
    \wr_req_cnt_r[3]_i_1 
       (.I0(wr_req_cnt_r[3]),
        .I1(\wr_req_cnt_r_reg[1]_0 [1]),
        .I2(\wr_req_cnt_r_reg[3]_0 ),
        .I3(wr_req_cnt_r[2]),
        .I4(\wr_req_cnt_r_reg[3]_1 ),
        .I5(\wr_data_indx_r_reg[1]_0 ),
        .O(\wr_req_cnt_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAA9AAAAAAAA)) 
    \wr_req_cnt_r[4]_i_1 
       (.I0(wr_req_cnt_r[4]),
        .I1(\wr_req_cnt_r_reg[1]_0 [1]),
        .I2(\wr_req_cnt_r_reg[3]_0 ),
        .I3(wr_req_cnt_r[2]),
        .I4(wr_req_cnt_r[3]),
        .I5(\wr_req_cnt_r_reg[3]_1 ),
        .O(\wr_req_cnt_r[4]_i_1_n_0 ));
  FDRE \wr_req_cnt_r_reg[0] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(D),
        .Q(\wr_req_cnt_r_reg[1]_0 [0]),
        .R(1'b0));
  FDRE \wr_req_cnt_r_reg[1] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\wr_req_cnt_r[1]_i_1_n_0 ),
        .Q(\wr_req_cnt_r_reg[1]_0 [1]),
        .R(\wr_data_indx_r_reg[1]_0 ));
  FDRE \wr_req_cnt_r_reg[2] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\wr_req_cnt_r[2]_i_1_n_0 ),
        .Q(wr_req_cnt_r[2]),
        .R(1'b0));
  FDRE \wr_req_cnt_r_reg[3] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\wr_req_cnt_r[3]_i_1_n_0 ),
        .Q(wr_req_cnt_r[3]),
        .R(1'b0));
  FDRE \wr_req_cnt_r_reg[4] 
       (.C(\rd_data_indx_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\wr_req_cnt_r[4]_i_1_n_0 ),
        .Q(wr_req_cnt_r[4]),
        .R(\wr_data_indx_r_reg[1]_0 ));
endmodule

(* C_AVOID_PRIMITIVES = "0" *) (* C_BASEADDR = "64'b0000000000000000000000000000000010000000000000000000000000000000" *) (* C_FAMILY = "kintexu" *) 
(* C_FIT1_INTERRUPT = "0" *) (* C_FIT1_No_CLOCKS = "6216" *) (* C_FIT2_INTERRUPT = "0" *) 
(* C_FIT2_No_CLOCKS = "6216" *) (* C_FIT3_INTERRUPT = "0" *) (* C_FIT3_No_CLOCKS = "6216" *) 
(* C_FIT4_INTERRUPT = "0" *) (* C_FIT4_No_CLOCKS = "6216" *) (* C_FREQ = "100000000" *) 
(* C_GPI1_INTERRUPT = "0" *) (* C_GPI1_SIZE = "32" *) (* C_GPI2_INTERRUPT = "0" *) 
(* C_GPI2_SIZE = "32" *) (* C_GPI3_INTERRUPT = "0" *) (* C_GPI3_SIZE = "32" *) 
(* C_GPI4_INTERRUPT = "0" *) (* C_GPI4_SIZE = "32" *) (* C_GPO1_INIT = "32'b00000000000000000000000000000000" *) 
(* C_GPO1_SIZE = "32" *) (* C_GPO2_INIT = "32'b00000000000000000000000000000000" *) (* C_GPO2_SIZE = "32" *) 
(* C_GPO3_INIT = "32'b00000000000000000000000000000000" *) (* C_GPO3_SIZE = "32" *) (* C_GPO4_INIT = "32'b00000000000000000000000000000000" *) 
(* C_GPO4_SIZE = "32" *) (* C_HIGHADDR = "64'b0000000000000000000000000000000010000000000000001111111111111111" *) (* C_INSTANCE = "iomodule" *) 
(* C_INTC_ADDR_WIDTH = "17" *) (* C_INTC_ASYNC_INTR = "16'b1111111111111111" *) (* C_INTC_BASE_VECTORS = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_INTC_HAS_FAST = "1" *) (* C_INTC_INTR_SIZE = "1" *) (* C_INTC_LEVEL_EDGE = "16'b0000000000000000" *) 
(* C_INTC_NUM_SYNC_FF = "2" *) (* C_INTC_POSITIVE = "16'b1111111111111111" *) (* C_INTC_USE_EXT_INTR = "0" *) 
(* C_IO_BASEADDR = "64'b0000000000000000000000000000000011000000000000000000000000000000" *) (* C_IO_HIGHADDR = "64'b0000000000000000000000000000000011111111111111111111111111111111" *) (* C_IO_MASK = "64'b0000000000000000000000000000000011000000000000000000000000000000" *) 
(* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *) (* C_LMB_PROTOCOL = "0" *) 
(* C_MASK = "64'b0000000000000000000000000000000011000000000000000000000000000000" *) (* C_PIT1_INTERRUPT = "0" *) (* C_PIT1_PRESCALER = "0" *) 
(* C_PIT1_READABLE = "1" *) (* C_PIT1_SIZE = "32" *) (* C_PIT2_INTERRUPT = "0" *) 
(* C_PIT2_PRESCALER = "0" *) (* C_PIT2_READABLE = "1" *) (* C_PIT2_SIZE = "32" *) 
(* C_PIT3_INTERRUPT = "0" *) (* C_PIT3_PRESCALER = "0" *) (* C_PIT3_READABLE = "1" *) 
(* C_PIT3_SIZE = "32" *) (* C_PIT4_INTERRUPT = "0" *) (* C_PIT4_PRESCALER = "0" *) 
(* C_PIT4_READABLE = "1" *) (* C_PIT4_SIZE = "32" *) (* C_TMR = "0" *) 
(* C_UART_ASYNC = "0" *) (* C_UART_BAUDRATE = "9600" *) (* C_UART_DATA_BITS = "8" *) 
(* C_UART_ERROR_INTERRUPT = "0" *) (* C_UART_FREQ = "100000000" *) (* C_UART_NUM_SYNC_FF = "2" *) 
(* C_UART_ODD_PARITY = "0" *) (* C_UART_PROG_BAUDRATE = "0" *) (* C_UART_RX_INTERRUPT = "0" *) 
(* C_UART_TX_INTERRUPT = "0" *) (* C_UART_USE_PARITY = "0" *) (* C_USE_CONFIG_RESET = "0" *) 
(* C_USE_FIT1 = "0" *) (* C_USE_FIT2 = "0" *) (* C_USE_FIT3 = "0" *) 
(* C_USE_FIT4 = "0" *) (* C_USE_GPI1 = "0" *) (* C_USE_GPI2 = "0" *) 
(* C_USE_GPI3 = "0" *) (* C_USE_GPI4 = "0" *) (* C_USE_GPO1 = "0" *) 
(* C_USE_GPO2 = "0" *) (* C_USE_GPO3 = "0" *) (* C_USE_GPO4 = "0" *) 
(* C_USE_IO_BUS = "1" *) (* C_USE_PIT1 = "0" *) (* C_USE_PIT2 = "0" *) 
(* C_USE_PIT3 = "0" *) (* C_USE_PIT4 = "0" *) (* C_USE_TMR_DISABLE = "0" *) 
(* C_USE_UART_RX = "0" *) (* C_USE_UART_TX = "0" *) (* ORIG_REF_NAME = "iomodule" *) 
module ddr4_0_iomodule
   (Clk,
    Rst,
    Config_Reset,
    TMR_Rst,
    TMR_Disable,
    ToVote,
    FromAVote,
    FromBVote,
    IO_Addr_Strobe,
    IO_Read_Strobe,
    IO_Write_Strobe,
    IO_Address,
    IO_Byte_Enable,
    IO_Write_Data,
    IO_Read_Data,
    IO_UE,
    IO_CE,
    IO_Ready,
    UART_Clk,
    UART_Rst,
    UART_Rx,
    UART_Tx,
    UART_Interrupt,
    FIT1_Interrupt,
    FIT1_Toggle,
    FIT2_Interrupt,
    FIT2_Toggle,
    FIT3_Interrupt,
    FIT3_Toggle,
    FIT4_Interrupt,
    FIT4_Toggle,
    PIT1_Enable,
    PIT1_Interrupt,
    PIT1_Toggle,
    PIT2_Enable,
    PIT2_Interrupt,
    PIT2_Toggle,
    PIT3_Enable,
    PIT3_Interrupt,
    PIT3_Toggle,
    PIT4_Enable,
    PIT4_Interrupt,
    PIT4_Toggle,
    GPO1,
    GPO2,
    GPO3,
    GPO4,
    GPI1,
    GPI1_Interrupt,
    GPI2,
    GPI2_Interrupt,
    GPI3,
    GPI3_Interrupt,
    GPI4,
    GPI4_Interrupt,
    INTC_Interrupt,
    INTC_IRQ,
    INTC_Processor_Ack,
    INTC_Interrupt_Address,
    INTC_IRQ_OUT,
    LMB_ABus,
    LMB_WriteDBus,
    LMB_AddrStrobe,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_BE,
    Sl_DBus,
    Sl_Ready,
    Sl_Wait,
    Sl_UE,
    Sl_CE);
  input Clk;
  input Rst;
  input Config_Reset;
  input TMR_Rst;
  input TMR_Disable;
  output [1023:0]ToVote;
  input [1023:0]FromAVote;
  input [1023:0]FromBVote;
  output IO_Addr_Strobe;
  output IO_Read_Strobe;
  output IO_Write_Strobe;
  output [31:0]IO_Address;
  output [3:0]IO_Byte_Enable;
  output [31:0]IO_Write_Data;
  input [31:0]IO_Read_Data;
  input IO_UE;
  input IO_CE;
  input IO_Ready;
  input UART_Clk;
  input UART_Rst;
  input UART_Rx;
  output UART_Tx;
  output UART_Interrupt;
  output FIT1_Interrupt;
  output FIT1_Toggle;
  output FIT2_Interrupt;
  output FIT2_Toggle;
  output FIT3_Interrupt;
  output FIT3_Toggle;
  output FIT4_Interrupt;
  output FIT4_Toggle;
  input PIT1_Enable;
  output PIT1_Interrupt;
  output PIT1_Toggle;
  input PIT2_Enable;
  output PIT2_Interrupt;
  output PIT2_Toggle;
  input PIT3_Enable;
  output PIT3_Interrupt;
  output PIT3_Toggle;
  input PIT4_Enable;
  output PIT4_Interrupt;
  output PIT4_Toggle;
  output [31:0]GPO1;
  output [31:0]GPO2;
  output [31:0]GPO3;
  output [31:0]GPO4;
  input [31:0]GPI1;
  output GPI1_Interrupt;
  input [31:0]GPI2;
  output GPI2_Interrupt;
  input [31:0]GPI3;
  output GPI3_Interrupt;
  input [31:0]GPI4;
  output GPI4_Interrupt;
  input [0:0]INTC_Interrupt;
  output INTC_IRQ;
  input [1:0]INTC_Processor_Ack;
  output [31:0]INTC_Interrupt_Address;
  output INTC_IRQ_OUT;
  input [0:31]LMB_ABus;
  input [0:31]LMB_WriteDBus;
  input LMB_AddrStrobe;
  input LMB_ReadStrobe;
  input LMB_WriteStrobe;
  input [0:3]LMB_BE;
  output [0:31]Sl_DBus;
  output Sl_Ready;
  output Sl_Wait;
  output Sl_UE;
  output Sl_CE;

  wire \<const0> ;
  wire Clk;
  wire IO_Addr_Strobe;
  wire IO_Addr_Strobe00_in;
  wire [29:2]\^IO_Address ;
  wire [31:0]IO_Read_Data;
  wire IO_Read_Strobe__0;
  wire IO_Ready;
  wire [31:0]IO_Write_Data;
  wire IO_Write_Strobe;
  wire IO_Write_Strobe__0;
  wire [0:31]LMB_ABus;
  wire LMB_AddrStrobe;
  wire LMB_ReadStrobe;
  wire [0:31]LMB_WriteDBus;
  wire LMB_WriteStrobe;
  wire Rst;
  wire [0:31]Sl_DBus;
  wire Sl_Ready;
  wire \Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ;
  wire \Using_IO_Bus.io_read_keep ;
  wire \Using_IO_Bus.io_read_keep_reg_n_0 ;
  wire io_ready_Q;
  wire io_ready_Q0;
  wire \lmb_abus_Q_reg_n_0_[2] ;
  wire \lmb_abus_Q_reg_n_0_[3] ;
  wire \lmb_abus_Q_reg_n_0_[4] ;
  wire \lmb_abus_Q_reg_n_0_[5] ;
  wire \lmb_abus_Q_reg_n_0_[6] ;
  wire lmb_io_select_keep;
  wire lmb_reg_read;
  wire lmb_reg_read0;
  wire lmb_reg_read_Q;
  wire lmb_reg_write;
  wire lmb_reg_write0;
  wire p_0_in21_in;
  (* RTL_KEEP = "true" *) wire uart_tx_write;
  wire uart_tx_write_inferred_i_2_n_0;
  (* RTL_KEEP = "true" *) wire [31:0]write_data;

  assign FIT1_Interrupt = \<const0> ;
  assign FIT1_Toggle = \<const0> ;
  assign FIT2_Interrupt = \<const0> ;
  assign FIT2_Toggle = \<const0> ;
  assign FIT3_Interrupt = \<const0> ;
  assign FIT3_Toggle = \<const0> ;
  assign FIT4_Interrupt = \<const0> ;
  assign FIT4_Toggle = \<const0> ;
  assign GPI1_Interrupt = \<const0> ;
  assign GPI2_Interrupt = \<const0> ;
  assign GPI3_Interrupt = \<const0> ;
  assign GPI4_Interrupt = \<const0> ;
  assign GPO1[31] = \<const0> ;
  assign GPO1[30] = \<const0> ;
  assign GPO1[29] = \<const0> ;
  assign GPO1[28] = \<const0> ;
  assign GPO1[27] = \<const0> ;
  assign GPO1[26] = \<const0> ;
  assign GPO1[25] = \<const0> ;
  assign GPO1[24] = \<const0> ;
  assign GPO1[23] = \<const0> ;
  assign GPO1[22] = \<const0> ;
  assign GPO1[21] = \<const0> ;
  assign GPO1[20] = \<const0> ;
  assign GPO1[19] = \<const0> ;
  assign GPO1[18] = \<const0> ;
  assign GPO1[17] = \<const0> ;
  assign GPO1[16] = \<const0> ;
  assign GPO1[15] = \<const0> ;
  assign GPO1[14] = \<const0> ;
  assign GPO1[13] = \<const0> ;
  assign GPO1[12] = \<const0> ;
  assign GPO1[11] = \<const0> ;
  assign GPO1[10] = \<const0> ;
  assign GPO1[9] = \<const0> ;
  assign GPO1[8] = \<const0> ;
  assign GPO1[7] = \<const0> ;
  assign GPO1[6] = \<const0> ;
  assign GPO1[5] = \<const0> ;
  assign GPO1[4] = \<const0> ;
  assign GPO1[3] = \<const0> ;
  assign GPO1[2] = \<const0> ;
  assign GPO1[1] = \<const0> ;
  assign GPO1[0] = \<const0> ;
  assign GPO2[31] = \<const0> ;
  assign GPO2[30] = \<const0> ;
  assign GPO2[29] = \<const0> ;
  assign GPO2[28] = \<const0> ;
  assign GPO2[27] = \<const0> ;
  assign GPO2[26] = \<const0> ;
  assign GPO2[25] = \<const0> ;
  assign GPO2[24] = \<const0> ;
  assign GPO2[23] = \<const0> ;
  assign GPO2[22] = \<const0> ;
  assign GPO2[21] = \<const0> ;
  assign GPO2[20] = \<const0> ;
  assign GPO2[19] = \<const0> ;
  assign GPO2[18] = \<const0> ;
  assign GPO2[17] = \<const0> ;
  assign GPO2[16] = \<const0> ;
  assign GPO2[15] = \<const0> ;
  assign GPO2[14] = \<const0> ;
  assign GPO2[13] = \<const0> ;
  assign GPO2[12] = \<const0> ;
  assign GPO2[11] = \<const0> ;
  assign GPO2[10] = \<const0> ;
  assign GPO2[9] = \<const0> ;
  assign GPO2[8] = \<const0> ;
  assign GPO2[7] = \<const0> ;
  assign GPO2[6] = \<const0> ;
  assign GPO2[5] = \<const0> ;
  assign GPO2[4] = \<const0> ;
  assign GPO2[3] = \<const0> ;
  assign GPO2[2] = \<const0> ;
  assign GPO2[1] = \<const0> ;
  assign GPO2[0] = \<const0> ;
  assign GPO3[31] = \<const0> ;
  assign GPO3[30] = \<const0> ;
  assign GPO3[29] = \<const0> ;
  assign GPO3[28] = \<const0> ;
  assign GPO3[27] = \<const0> ;
  assign GPO3[26] = \<const0> ;
  assign GPO3[25] = \<const0> ;
  assign GPO3[24] = \<const0> ;
  assign GPO3[23] = \<const0> ;
  assign GPO3[22] = \<const0> ;
  assign GPO3[21] = \<const0> ;
  assign GPO3[20] = \<const0> ;
  assign GPO3[19] = \<const0> ;
  assign GPO3[18] = \<const0> ;
  assign GPO3[17] = \<const0> ;
  assign GPO3[16] = \<const0> ;
  assign GPO3[15] = \<const0> ;
  assign GPO3[14] = \<const0> ;
  assign GPO3[13] = \<const0> ;
  assign GPO3[12] = \<const0> ;
  assign GPO3[11] = \<const0> ;
  assign GPO3[10] = \<const0> ;
  assign GPO3[9] = \<const0> ;
  assign GPO3[8] = \<const0> ;
  assign GPO3[7] = \<const0> ;
  assign GPO3[6] = \<const0> ;
  assign GPO3[5] = \<const0> ;
  assign GPO3[4] = \<const0> ;
  assign GPO3[3] = \<const0> ;
  assign GPO3[2] = \<const0> ;
  assign GPO3[1] = \<const0> ;
  assign GPO3[0] = \<const0> ;
  assign GPO4[31] = \<const0> ;
  assign GPO4[30] = \<const0> ;
  assign GPO4[29] = \<const0> ;
  assign GPO4[28] = \<const0> ;
  assign GPO4[27] = \<const0> ;
  assign GPO4[26] = \<const0> ;
  assign GPO4[25] = \<const0> ;
  assign GPO4[24] = \<const0> ;
  assign GPO4[23] = \<const0> ;
  assign GPO4[22] = \<const0> ;
  assign GPO4[21] = \<const0> ;
  assign GPO4[20] = \<const0> ;
  assign GPO4[19] = \<const0> ;
  assign GPO4[18] = \<const0> ;
  assign GPO4[17] = \<const0> ;
  assign GPO4[16] = \<const0> ;
  assign GPO4[15] = \<const0> ;
  assign GPO4[14] = \<const0> ;
  assign GPO4[13] = \<const0> ;
  assign GPO4[12] = \<const0> ;
  assign GPO4[11] = \<const0> ;
  assign GPO4[10] = \<const0> ;
  assign GPO4[9] = \<const0> ;
  assign GPO4[8] = \<const0> ;
  assign GPO4[7] = \<const0> ;
  assign GPO4[6] = \<const0> ;
  assign GPO4[5] = \<const0> ;
  assign GPO4[4] = \<const0> ;
  assign GPO4[3] = \<const0> ;
  assign GPO4[2] = \<const0> ;
  assign GPO4[1] = \<const0> ;
  assign GPO4[0] = \<const0> ;
  assign INTC_IRQ = \<const0> ;
  assign INTC_IRQ_OUT = \<const0> ;
  assign INTC_Interrupt_Address[31] = \<const0> ;
  assign INTC_Interrupt_Address[30] = \<const0> ;
  assign INTC_Interrupt_Address[29] = \<const0> ;
  assign INTC_Interrupt_Address[28] = \<const0> ;
  assign INTC_Interrupt_Address[27] = \<const0> ;
  assign INTC_Interrupt_Address[26] = \<const0> ;
  assign INTC_Interrupt_Address[25] = \<const0> ;
  assign INTC_Interrupt_Address[24] = \<const0> ;
  assign INTC_Interrupt_Address[23] = \<const0> ;
  assign INTC_Interrupt_Address[22] = \<const0> ;
  assign INTC_Interrupt_Address[21] = \<const0> ;
  assign INTC_Interrupt_Address[20] = \<const0> ;
  assign INTC_Interrupt_Address[19] = \<const0> ;
  assign INTC_Interrupt_Address[18] = \<const0> ;
  assign INTC_Interrupt_Address[17] = \<const0> ;
  assign INTC_Interrupt_Address[16] = \<const0> ;
  assign INTC_Interrupt_Address[15] = \<const0> ;
  assign INTC_Interrupt_Address[14] = \<const0> ;
  assign INTC_Interrupt_Address[13] = \<const0> ;
  assign INTC_Interrupt_Address[12] = \<const0> ;
  assign INTC_Interrupt_Address[11] = \<const0> ;
  assign INTC_Interrupt_Address[10] = \<const0> ;
  assign INTC_Interrupt_Address[9] = \<const0> ;
  assign INTC_Interrupt_Address[8] = \<const0> ;
  assign INTC_Interrupt_Address[7] = \<const0> ;
  assign INTC_Interrupt_Address[6] = \<const0> ;
  assign INTC_Interrupt_Address[5] = \<const0> ;
  assign INTC_Interrupt_Address[4] = \<const0> ;
  assign INTC_Interrupt_Address[3] = \<const0> ;
  assign INTC_Interrupt_Address[2] = \<const0> ;
  assign INTC_Interrupt_Address[1] = \<const0> ;
  assign INTC_Interrupt_Address[0] = \<const0> ;
  assign IO_Address[31] = \<const0> ;
  assign IO_Address[30] = \<const0> ;
  assign IO_Address[29:2] = \^IO_Address [29:2];
  assign IO_Address[1] = \<const0> ;
  assign IO_Address[0] = \<const0> ;
  assign IO_Byte_Enable[3] = \<const0> ;
  assign IO_Byte_Enable[2] = \<const0> ;
  assign IO_Byte_Enable[1] = \<const0> ;
  assign IO_Byte_Enable[0] = \<const0> ;
  assign IO_Read_Strobe = \<const0> ;
  assign PIT1_Interrupt = \<const0> ;
  assign PIT1_Toggle = \<const0> ;
  assign PIT2_Interrupt = \<const0> ;
  assign PIT2_Toggle = \<const0> ;
  assign PIT3_Interrupt = \<const0> ;
  assign PIT3_Toggle = \<const0> ;
  assign PIT4_Interrupt = \<const0> ;
  assign PIT4_Toggle = \<const0> ;
  assign Sl_CE = \<const0> ;
  assign Sl_UE = \<const0> ;
  assign Sl_Wait = \<const0> ;
  assign ToVote[1023] = \<const0> ;
  assign ToVote[1022] = \<const0> ;
  assign ToVote[1021] = \<const0> ;
  assign ToVote[1020] = \<const0> ;
  assign ToVote[1019] = \<const0> ;
  assign ToVote[1018] = \<const0> ;
  assign ToVote[1017] = \<const0> ;
  assign ToVote[1016] = \<const0> ;
  assign ToVote[1015] = \<const0> ;
  assign ToVote[1014] = \<const0> ;
  assign ToVote[1013] = \<const0> ;
  assign ToVote[1012] = \<const0> ;
  assign ToVote[1011] = \<const0> ;
  assign ToVote[1010] = \<const0> ;
  assign ToVote[1009] = \<const0> ;
  assign ToVote[1008] = \<const0> ;
  assign ToVote[1007] = \<const0> ;
  assign ToVote[1006] = \<const0> ;
  assign ToVote[1005] = \<const0> ;
  assign ToVote[1004] = \<const0> ;
  assign ToVote[1003] = \<const0> ;
  assign ToVote[1002] = \<const0> ;
  assign ToVote[1001] = \<const0> ;
  assign ToVote[1000] = \<const0> ;
  assign ToVote[999] = \<const0> ;
  assign ToVote[998] = \<const0> ;
  assign ToVote[997] = \<const0> ;
  assign ToVote[996] = \<const0> ;
  assign ToVote[995] = \<const0> ;
  assign ToVote[994] = \<const0> ;
  assign ToVote[993] = \<const0> ;
  assign ToVote[992] = \<const0> ;
  assign ToVote[991] = \<const0> ;
  assign ToVote[990] = \<const0> ;
  assign ToVote[989] = \<const0> ;
  assign ToVote[988] = \<const0> ;
  assign ToVote[987] = \<const0> ;
  assign ToVote[986] = \<const0> ;
  assign ToVote[985] = \<const0> ;
  assign ToVote[984] = \<const0> ;
  assign ToVote[983] = \<const0> ;
  assign ToVote[982] = \<const0> ;
  assign ToVote[981] = \<const0> ;
  assign ToVote[980] = \<const0> ;
  assign ToVote[979] = \<const0> ;
  assign ToVote[978] = \<const0> ;
  assign ToVote[977] = \<const0> ;
  assign ToVote[976] = \<const0> ;
  assign ToVote[975] = \<const0> ;
  assign ToVote[974] = \<const0> ;
  assign ToVote[973] = \<const0> ;
  assign ToVote[972] = \<const0> ;
  assign ToVote[971] = \<const0> ;
  assign ToVote[970] = \<const0> ;
  assign ToVote[969] = \<const0> ;
  assign ToVote[968] = \<const0> ;
  assign ToVote[967] = \<const0> ;
  assign ToVote[966] = \<const0> ;
  assign ToVote[965] = \<const0> ;
  assign ToVote[964] = \<const0> ;
  assign ToVote[963] = \<const0> ;
  assign ToVote[962] = \<const0> ;
  assign ToVote[961] = \<const0> ;
  assign ToVote[960] = \<const0> ;
  assign ToVote[959] = \<const0> ;
  assign ToVote[958] = \<const0> ;
  assign ToVote[957] = \<const0> ;
  assign ToVote[956] = \<const0> ;
  assign ToVote[955] = \<const0> ;
  assign ToVote[954] = \<const0> ;
  assign ToVote[953] = \<const0> ;
  assign ToVote[952] = \<const0> ;
  assign ToVote[951] = \<const0> ;
  assign ToVote[950] = \<const0> ;
  assign ToVote[949] = \<const0> ;
  assign ToVote[948] = \<const0> ;
  assign ToVote[947] = \<const0> ;
  assign ToVote[946] = \<const0> ;
  assign ToVote[945] = \<const0> ;
  assign ToVote[944] = \<const0> ;
  assign ToVote[943] = \<const0> ;
  assign ToVote[942] = \<const0> ;
  assign ToVote[941] = \<const0> ;
  assign ToVote[940] = \<const0> ;
  assign ToVote[939] = \<const0> ;
  assign ToVote[938] = \<const0> ;
  assign ToVote[937] = \<const0> ;
  assign ToVote[936] = \<const0> ;
  assign ToVote[935] = \<const0> ;
  assign ToVote[934] = \<const0> ;
  assign ToVote[933] = \<const0> ;
  assign ToVote[932] = \<const0> ;
  assign ToVote[931] = \<const0> ;
  assign ToVote[930] = \<const0> ;
  assign ToVote[929] = \<const0> ;
  assign ToVote[928] = \<const0> ;
  assign ToVote[927] = \<const0> ;
  assign ToVote[926] = \<const0> ;
  assign ToVote[925] = \<const0> ;
  assign ToVote[924] = \<const0> ;
  assign ToVote[923] = \<const0> ;
  assign ToVote[922] = \<const0> ;
  assign ToVote[921] = \<const0> ;
  assign ToVote[920] = \<const0> ;
  assign ToVote[919] = \<const0> ;
  assign ToVote[918] = \<const0> ;
  assign ToVote[917] = \<const0> ;
  assign ToVote[916] = \<const0> ;
  assign ToVote[915] = \<const0> ;
  assign ToVote[914] = \<const0> ;
  assign ToVote[913] = \<const0> ;
  assign ToVote[912] = \<const0> ;
  assign ToVote[911] = \<const0> ;
  assign ToVote[910] = \<const0> ;
  assign ToVote[909] = \<const0> ;
  assign ToVote[908] = \<const0> ;
  assign ToVote[907] = \<const0> ;
  assign ToVote[906] = \<const0> ;
  assign ToVote[905] = \<const0> ;
  assign ToVote[904] = \<const0> ;
  assign ToVote[903] = \<const0> ;
  assign ToVote[902] = \<const0> ;
  assign ToVote[901] = \<const0> ;
  assign ToVote[900] = \<const0> ;
  assign ToVote[899] = \<const0> ;
  assign ToVote[898] = \<const0> ;
  assign ToVote[897] = \<const0> ;
  assign ToVote[896] = \<const0> ;
  assign ToVote[895] = \<const0> ;
  assign ToVote[894] = \<const0> ;
  assign ToVote[893] = \<const0> ;
  assign ToVote[892] = \<const0> ;
  assign ToVote[891] = \<const0> ;
  assign ToVote[890] = \<const0> ;
  assign ToVote[889] = \<const0> ;
  assign ToVote[888] = \<const0> ;
  assign ToVote[887] = \<const0> ;
  assign ToVote[886] = \<const0> ;
  assign ToVote[885] = \<const0> ;
  assign ToVote[884] = \<const0> ;
  assign ToVote[883] = \<const0> ;
  assign ToVote[882] = \<const0> ;
  assign ToVote[881] = \<const0> ;
  assign ToVote[880] = \<const0> ;
  assign ToVote[879] = \<const0> ;
  assign ToVote[878] = \<const0> ;
  assign ToVote[877] = \<const0> ;
  assign ToVote[876] = \<const0> ;
  assign ToVote[875] = \<const0> ;
  assign ToVote[874] = \<const0> ;
  assign ToVote[873] = \<const0> ;
  assign ToVote[872] = \<const0> ;
  assign ToVote[871] = \<const0> ;
  assign ToVote[870] = \<const0> ;
  assign ToVote[869] = \<const0> ;
  assign ToVote[868] = \<const0> ;
  assign ToVote[867] = \<const0> ;
  assign ToVote[866] = \<const0> ;
  assign ToVote[865] = \<const0> ;
  assign ToVote[864] = \<const0> ;
  assign ToVote[863] = \<const0> ;
  assign ToVote[862] = \<const0> ;
  assign ToVote[861] = \<const0> ;
  assign ToVote[860] = \<const0> ;
  assign ToVote[859] = \<const0> ;
  assign ToVote[858] = \<const0> ;
  assign ToVote[857] = \<const0> ;
  assign ToVote[856] = \<const0> ;
  assign ToVote[855] = \<const0> ;
  assign ToVote[854] = \<const0> ;
  assign ToVote[853] = \<const0> ;
  assign ToVote[852] = \<const0> ;
  assign ToVote[851] = \<const0> ;
  assign ToVote[850] = \<const0> ;
  assign ToVote[849] = \<const0> ;
  assign ToVote[848] = \<const0> ;
  assign ToVote[847] = \<const0> ;
  assign ToVote[846] = \<const0> ;
  assign ToVote[845] = \<const0> ;
  assign ToVote[844] = \<const0> ;
  assign ToVote[843] = \<const0> ;
  assign ToVote[842] = \<const0> ;
  assign ToVote[841] = \<const0> ;
  assign ToVote[840] = \<const0> ;
  assign ToVote[839] = \<const0> ;
  assign ToVote[838] = \<const0> ;
  assign ToVote[837] = \<const0> ;
  assign ToVote[836] = \<const0> ;
  assign ToVote[835] = \<const0> ;
  assign ToVote[834] = \<const0> ;
  assign ToVote[833] = \<const0> ;
  assign ToVote[832] = \<const0> ;
  assign ToVote[831] = \<const0> ;
  assign ToVote[830] = \<const0> ;
  assign ToVote[829] = \<const0> ;
  assign ToVote[828] = \<const0> ;
  assign ToVote[827] = \<const0> ;
  assign ToVote[826] = \<const0> ;
  assign ToVote[825] = \<const0> ;
  assign ToVote[824] = \<const0> ;
  assign ToVote[823] = \<const0> ;
  assign ToVote[822] = \<const0> ;
  assign ToVote[821] = \<const0> ;
  assign ToVote[820] = \<const0> ;
  assign ToVote[819] = \<const0> ;
  assign ToVote[818] = \<const0> ;
  assign ToVote[817] = \<const0> ;
  assign ToVote[816] = \<const0> ;
  assign ToVote[815] = \<const0> ;
  assign ToVote[814] = \<const0> ;
  assign ToVote[813] = \<const0> ;
  assign ToVote[812] = \<const0> ;
  assign ToVote[811] = \<const0> ;
  assign ToVote[810] = \<const0> ;
  assign ToVote[809] = \<const0> ;
  assign ToVote[808] = \<const0> ;
  assign ToVote[807] = \<const0> ;
  assign ToVote[806] = \<const0> ;
  assign ToVote[805] = \<const0> ;
  assign ToVote[804] = \<const0> ;
  assign ToVote[803] = \<const0> ;
  assign ToVote[802] = \<const0> ;
  assign ToVote[801] = \<const0> ;
  assign ToVote[800] = \<const0> ;
  assign ToVote[799] = \<const0> ;
  assign ToVote[798] = \<const0> ;
  assign ToVote[797] = \<const0> ;
  assign ToVote[796] = \<const0> ;
  assign ToVote[795] = \<const0> ;
  assign ToVote[794] = \<const0> ;
  assign ToVote[793] = \<const0> ;
  assign ToVote[792] = \<const0> ;
  assign ToVote[791] = \<const0> ;
  assign ToVote[790] = \<const0> ;
  assign ToVote[789] = \<const0> ;
  assign ToVote[788] = \<const0> ;
  assign ToVote[787] = \<const0> ;
  assign ToVote[786] = \<const0> ;
  assign ToVote[785] = \<const0> ;
  assign ToVote[784] = \<const0> ;
  assign ToVote[783] = \<const0> ;
  assign ToVote[782] = \<const0> ;
  assign ToVote[781] = \<const0> ;
  assign ToVote[780] = \<const0> ;
  assign ToVote[779] = \<const0> ;
  assign ToVote[778] = \<const0> ;
  assign ToVote[777] = \<const0> ;
  assign ToVote[776] = \<const0> ;
  assign ToVote[775] = \<const0> ;
  assign ToVote[774] = \<const0> ;
  assign ToVote[773] = \<const0> ;
  assign ToVote[772] = \<const0> ;
  assign ToVote[771] = \<const0> ;
  assign ToVote[770] = \<const0> ;
  assign ToVote[769] = \<const0> ;
  assign ToVote[768] = \<const0> ;
  assign ToVote[767] = \<const0> ;
  assign ToVote[766] = \<const0> ;
  assign ToVote[765] = \<const0> ;
  assign ToVote[764] = \<const0> ;
  assign ToVote[763] = \<const0> ;
  assign ToVote[762] = \<const0> ;
  assign ToVote[761] = \<const0> ;
  assign ToVote[760] = \<const0> ;
  assign ToVote[759] = \<const0> ;
  assign ToVote[758] = \<const0> ;
  assign ToVote[757] = \<const0> ;
  assign ToVote[756] = \<const0> ;
  assign ToVote[755] = \<const0> ;
  assign ToVote[754] = \<const0> ;
  assign ToVote[753] = \<const0> ;
  assign ToVote[752] = \<const0> ;
  assign ToVote[751] = \<const0> ;
  assign ToVote[750] = \<const0> ;
  assign ToVote[749] = \<const0> ;
  assign ToVote[748] = \<const0> ;
  assign ToVote[747] = \<const0> ;
  assign ToVote[746] = \<const0> ;
  assign ToVote[745] = \<const0> ;
  assign ToVote[744] = \<const0> ;
  assign ToVote[743] = \<const0> ;
  assign ToVote[742] = \<const0> ;
  assign ToVote[741] = \<const0> ;
  assign ToVote[740] = \<const0> ;
  assign ToVote[739] = \<const0> ;
  assign ToVote[738] = \<const0> ;
  assign ToVote[737] = \<const0> ;
  assign ToVote[736] = \<const0> ;
  assign ToVote[735] = \<const0> ;
  assign ToVote[734] = \<const0> ;
  assign ToVote[733] = \<const0> ;
  assign ToVote[732] = \<const0> ;
  assign ToVote[731] = \<const0> ;
  assign ToVote[730] = \<const0> ;
  assign ToVote[729] = \<const0> ;
  assign ToVote[728] = \<const0> ;
  assign ToVote[727] = \<const0> ;
  assign ToVote[726] = \<const0> ;
  assign ToVote[725] = \<const0> ;
  assign ToVote[724] = \<const0> ;
  assign ToVote[723] = \<const0> ;
  assign ToVote[722] = \<const0> ;
  assign ToVote[721] = \<const0> ;
  assign ToVote[720] = \<const0> ;
  assign ToVote[719] = \<const0> ;
  assign ToVote[718] = \<const0> ;
  assign ToVote[717] = \<const0> ;
  assign ToVote[716] = \<const0> ;
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  assign ToVote[706] = \<const0> ;
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  assign ToVote[700] = \<const0> ;
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  assign ToVote[697] = \<const0> ;
  assign ToVote[696] = \<const0> ;
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  assign ToVote[692] = \<const0> ;
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  assign ToVote[689] = \<const0> ;
  assign ToVote[688] = \<const0> ;
  assign ToVote[687] = \<const0> ;
  assign ToVote[686] = \<const0> ;
  assign ToVote[685] = \<const0> ;
  assign ToVote[684] = \<const0> ;
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  assign ToVote[675] = \<const0> ;
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  assign ToVote[659] = \<const0> ;
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  assign ToVote[635] = \<const0> ;
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  assign ToVote[632] = \<const0> ;
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  assign ToVote[624] = \<const0> ;
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  assign ToVote[614] = \<const0> ;
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  assign ToVote[610] = \<const0> ;
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  assign ToVote[604] = \<const0> ;
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  assign ToVote[595] = \<const0> ;
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  assign ToVote[593] = \<const0> ;
  assign ToVote[592] = \<const0> ;
  assign ToVote[591] = \<const0> ;
  assign ToVote[590] = \<const0> ;
  assign ToVote[589] = \<const0> ;
  assign ToVote[588] = \<const0> ;
  assign ToVote[587] = \<const0> ;
  assign ToVote[586] = \<const0> ;
  assign ToVote[585] = \<const0> ;
  assign ToVote[584] = \<const0> ;
  assign ToVote[583] = \<const0> ;
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  assign ToVote[581] = \<const0> ;
  assign ToVote[580] = \<const0> ;
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  assign ToVote[578] = \<const0> ;
  assign ToVote[577] = \<const0> ;
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  assign ToVote[575] = \<const0> ;
  assign ToVote[574] = \<const0> ;
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  assign ToVote[571] = \<const0> ;
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  assign ToVote[565] = \<const0> ;
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  assign ToVote[562] = \<const0> ;
  assign ToVote[561] = \<const0> ;
  assign ToVote[560] = \<const0> ;
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  assign ToVote[558] = \<const0> ;
  assign ToVote[557] = \<const0> ;
  assign ToVote[556] = \<const0> ;
  assign ToVote[555] = \<const0> ;
  assign ToVote[554] = \<const0> ;
  assign ToVote[553] = \<const0> ;
  assign ToVote[552] = \<const0> ;
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  assign ToVote[550] = \<const0> ;
  assign ToVote[549] = \<const0> ;
  assign ToVote[548] = \<const0> ;
  assign ToVote[547] = \<const0> ;
  assign ToVote[546] = \<const0> ;
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  assign ToVote[544] = \<const0> ;
  assign ToVote[543] = \<const0> ;
  assign ToVote[542] = \<const0> ;
  assign ToVote[541] = \<const0> ;
  assign ToVote[540] = \<const0> ;
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  assign ToVote[536] = \<const0> ;
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  assign ToVote[533] = \<const0> ;
  assign ToVote[532] = \<const0> ;
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  assign ToVote[496] = \<const0> ;
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  assign ToVote[488] = \<const0> ;
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  assign ToVote[485] = \<const0> ;
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  assign ToVote[476] = \<const0> ;
  assign ToVote[475] = \<const0> ;
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  assign ToVote[472] = \<const0> ;
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  assign ToVote[463] = \<const0> ;
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  assign ToVote[460] = \<const0> ;
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  assign ToVote[457] = \<const0> ;
  assign ToVote[456] = \<const0> ;
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  assign ToVote[454] = \<const0> ;
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  assign ToVote[451] = \<const0> ;
  assign ToVote[450] = \<const0> ;
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  assign ToVote[447] = \<const0> ;
  assign ToVote[446] = \<const0> ;
  assign ToVote[445] = \<const0> ;
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  assign ToVote[442] = \<const0> ;
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  assign ToVote[405] = \<const0> ;
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  assign ToVote[399] = \<const0> ;
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  assign ToVote[393] = \<const0> ;
  assign ToVote[392] = \<const0> ;
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  assign ToVote[384] = \<const0> ;
  assign ToVote[383] = \<const0> ;
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  assign ToVote[346] = \<const0> ;
  assign ToVote[345] = \<const0> ;
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  assign ToVote[335] = \<const0> ;
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  assign ToVote[325] = \<const0> ;
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  assign ToVote[304] = \<const0> ;
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  assign ToVote[299] = \<const0> ;
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  assign ToVote[294] = \<const0> ;
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  assign ToVote[291] = \<const0> ;
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  assign ToVote[288] = \<const0> ;
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  assign ToVote[285] = \<const0> ;
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  assign ToVote[266] = \<const0> ;
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  assign ToVote[259] = \<const0> ;
  assign ToVote[258] = \<const0> ;
  assign ToVote[257] = \<const0> ;
  assign ToVote[256] = \<const0> ;
  assign ToVote[255] = \<const0> ;
  assign ToVote[254] = \<const0> ;
  assign ToVote[253] = \<const0> ;
  assign ToVote[252] = \<const0> ;
  assign ToVote[251] = \<const0> ;
  assign ToVote[250] = \<const0> ;
  assign ToVote[249] = \<const0> ;
  assign ToVote[248] = \<const0> ;
  assign ToVote[247] = \<const0> ;
  assign ToVote[246] = \<const0> ;
  assign ToVote[245] = \<const0> ;
  assign ToVote[244] = \<const0> ;
  assign ToVote[243] = \<const0> ;
  assign ToVote[242] = \<const0> ;
  assign ToVote[241] = \<const0> ;
  assign ToVote[240] = \<const0> ;
  assign ToVote[239] = \<const0> ;
  assign ToVote[238] = \<const0> ;
  assign ToVote[237] = \<const0> ;
  assign ToVote[236] = \<const0> ;
  assign ToVote[235] = \<const0> ;
  assign ToVote[234] = \<const0> ;
  assign ToVote[233] = \<const0> ;
  assign ToVote[232] = \<const0> ;
  assign ToVote[231] = \<const0> ;
  assign ToVote[230] = \<const0> ;
  assign ToVote[229] = \<const0> ;
  assign ToVote[228] = \<const0> ;
  assign ToVote[227] = \<const0> ;
  assign ToVote[226] = \<const0> ;
  assign ToVote[225] = \<const0> ;
  assign ToVote[224] = \<const0> ;
  assign ToVote[223] = \<const0> ;
  assign ToVote[222] = \<const0> ;
  assign ToVote[221] = \<const0> ;
  assign ToVote[220] = \<const0> ;
  assign ToVote[219] = \<const0> ;
  assign ToVote[218] = \<const0> ;
  assign ToVote[217] = \<const0> ;
  assign ToVote[216] = \<const0> ;
  assign ToVote[215] = \<const0> ;
  assign ToVote[214] = \<const0> ;
  assign ToVote[213] = \<const0> ;
  assign ToVote[212] = \<const0> ;
  assign ToVote[211] = \<const0> ;
  assign ToVote[210] = \<const0> ;
  assign ToVote[209] = \<const0> ;
  assign ToVote[208] = \<const0> ;
  assign ToVote[207] = \<const0> ;
  assign ToVote[206] = \<const0> ;
  assign ToVote[205] = \<const0> ;
  assign ToVote[204] = \<const0> ;
  assign ToVote[203] = \<const0> ;
  assign ToVote[202] = \<const0> ;
  assign ToVote[201] = \<const0> ;
  assign ToVote[200] = \<const0> ;
  assign ToVote[199] = \<const0> ;
  assign ToVote[198] = \<const0> ;
  assign ToVote[197] = \<const0> ;
  assign ToVote[196] = \<const0> ;
  assign ToVote[195] = \<const0> ;
  assign ToVote[194] = \<const0> ;
  assign ToVote[193] = \<const0> ;
  assign ToVote[192] = \<const0> ;
  assign ToVote[191] = \<const0> ;
  assign ToVote[190] = \<const0> ;
  assign ToVote[189] = \<const0> ;
  assign ToVote[188] = \<const0> ;
  assign ToVote[187] = \<const0> ;
  assign ToVote[186] = \<const0> ;
  assign ToVote[185] = \<const0> ;
  assign ToVote[184] = \<const0> ;
  assign ToVote[183] = \<const0> ;
  assign ToVote[182] = \<const0> ;
  assign ToVote[181] = \<const0> ;
  assign ToVote[180] = \<const0> ;
  assign ToVote[179] = \<const0> ;
  assign ToVote[178] = \<const0> ;
  assign ToVote[177] = \<const0> ;
  assign ToVote[176] = \<const0> ;
  assign ToVote[175] = \<const0> ;
  assign ToVote[174] = \<const0> ;
  assign ToVote[173] = \<const0> ;
  assign ToVote[172] = \<const0> ;
  assign ToVote[171] = \<const0> ;
  assign ToVote[170] = \<const0> ;
  assign ToVote[169] = \<const0> ;
  assign ToVote[168] = \<const0> ;
  assign ToVote[167] = \<const0> ;
  assign ToVote[166] = \<const0> ;
  assign ToVote[165] = \<const0> ;
  assign ToVote[164] = \<const0> ;
  assign ToVote[163] = \<const0> ;
  assign ToVote[162] = \<const0> ;
  assign ToVote[161] = \<const0> ;
  assign ToVote[160] = \<const0> ;
  assign ToVote[159] = \<const0> ;
  assign ToVote[158] = \<const0> ;
  assign ToVote[157] = \<const0> ;
  assign ToVote[156] = \<const0> ;
  assign ToVote[155] = \<const0> ;
  assign ToVote[154] = \<const0> ;
  assign ToVote[153] = \<const0> ;
  assign ToVote[152] = \<const0> ;
  assign ToVote[151] = \<const0> ;
  assign ToVote[150] = \<const0> ;
  assign ToVote[149] = \<const0> ;
  assign ToVote[148] = \<const0> ;
  assign ToVote[147] = \<const0> ;
  assign ToVote[146] = \<const0> ;
  assign ToVote[145] = \<const0> ;
  assign ToVote[144] = \<const0> ;
  assign ToVote[143] = \<const0> ;
  assign ToVote[142] = \<const0> ;
  assign ToVote[141] = \<const0> ;
  assign ToVote[140] = \<const0> ;
  assign ToVote[139] = \<const0> ;
  assign ToVote[138] = \<const0> ;
  assign ToVote[137] = \<const0> ;
  assign ToVote[136] = \<const0> ;
  assign ToVote[135] = \<const0> ;
  assign ToVote[134] = \<const0> ;
  assign ToVote[133] = \<const0> ;
  assign ToVote[132] = \<const0> ;
  assign ToVote[131] = \<const0> ;
  assign ToVote[130] = \<const0> ;
  assign ToVote[129] = \<const0> ;
  assign ToVote[128] = \<const0> ;
  assign ToVote[127] = \<const0> ;
  assign ToVote[126] = \<const0> ;
  assign ToVote[125] = \<const0> ;
  assign ToVote[124] = \<const0> ;
  assign ToVote[123] = \<const0> ;
  assign ToVote[122] = \<const0> ;
  assign ToVote[121] = \<const0> ;
  assign ToVote[120] = \<const0> ;
  assign ToVote[119] = \<const0> ;
  assign ToVote[118] = \<const0> ;
  assign ToVote[117] = \<const0> ;
  assign ToVote[116] = \<const0> ;
  assign ToVote[115] = \<const0> ;
  assign ToVote[114] = \<const0> ;
  assign ToVote[113] = \<const0> ;
  assign ToVote[112] = \<const0> ;
  assign ToVote[111] = \<const0> ;
  assign ToVote[110] = \<const0> ;
  assign ToVote[109] = \<const0> ;
  assign ToVote[108] = \<const0> ;
  assign ToVote[107] = \<const0> ;
  assign ToVote[106] = \<const0> ;
  assign ToVote[105] = \<const0> ;
  assign ToVote[104] = \<const0> ;
  assign ToVote[103] = \<const0> ;
  assign ToVote[102] = \<const0> ;
  assign ToVote[101] = \<const0> ;
  assign ToVote[100] = \<const0> ;
  assign ToVote[99] = \<const0> ;
  assign ToVote[98] = \<const0> ;
  assign ToVote[97] = \<const0> ;
  assign ToVote[96] = \<const0> ;
  assign ToVote[95] = \<const0> ;
  assign ToVote[94] = \<const0> ;
  assign ToVote[93] = \<const0> ;
  assign ToVote[92] = \<const0> ;
  assign ToVote[91] = \<const0> ;
  assign ToVote[90] = \<const0> ;
  assign ToVote[89] = \<const0> ;
  assign ToVote[88] = \<const0> ;
  assign ToVote[87] = \<const0> ;
  assign ToVote[86] = \<const0> ;
  assign ToVote[85] = \<const0> ;
  assign ToVote[84] = \<const0> ;
  assign ToVote[83] = \<const0> ;
  assign ToVote[82] = \<const0> ;
  assign ToVote[81] = \<const0> ;
  assign ToVote[80] = \<const0> ;
  assign ToVote[79] = \<const0> ;
  assign ToVote[78] = \<const0> ;
  assign ToVote[77] = \<const0> ;
  assign ToVote[76] = \<const0> ;
  assign ToVote[75] = \<const0> ;
  assign ToVote[74] = \<const0> ;
  assign ToVote[73] = \<const0> ;
  assign ToVote[72] = \<const0> ;
  assign ToVote[71] = \<const0> ;
  assign ToVote[70] = \<const0> ;
  assign ToVote[69] = \<const0> ;
  assign ToVote[68] = \<const0> ;
  assign ToVote[67] = \<const0> ;
  assign ToVote[66] = \<const0> ;
  assign ToVote[65] = \<const0> ;
  assign ToVote[64] = \<const0> ;
  assign ToVote[63] = \<const0> ;
  assign ToVote[62] = \<const0> ;
  assign ToVote[61] = \<const0> ;
  assign ToVote[60] = \<const0> ;
  assign ToVote[59] = \<const0> ;
  assign ToVote[58] = \<const0> ;
  assign ToVote[57] = \<const0> ;
  assign ToVote[56] = \<const0> ;
  assign ToVote[55] = \<const0> ;
  assign ToVote[54] = \<const0> ;
  assign ToVote[53] = \<const0> ;
  assign ToVote[52] = \<const0> ;
  assign ToVote[51] = \<const0> ;
  assign ToVote[50] = \<const0> ;
  assign ToVote[49] = \<const0> ;
  assign ToVote[48] = \<const0> ;
  assign ToVote[47] = \<const0> ;
  assign ToVote[46] = \<const0> ;
  assign ToVote[45] = \<const0> ;
  assign ToVote[44] = \<const0> ;
  assign ToVote[43] = \<const0> ;
  assign ToVote[42] = \<const0> ;
  assign ToVote[41] = \<const0> ;
  assign ToVote[40] = \<const0> ;
  assign ToVote[39] = \<const0> ;
  assign ToVote[38] = \<const0> ;
  assign ToVote[37] = \<const0> ;
  assign ToVote[36] = \<const0> ;
  assign ToVote[35] = \<const0> ;
  assign ToVote[34] = \<const0> ;
  assign ToVote[33] = \<const0> ;
  assign ToVote[32] = \<const0> ;
  assign ToVote[31] = \<const0> ;
  assign ToVote[30] = \<const0> ;
  assign ToVote[29] = \<const0> ;
  assign ToVote[28] = \<const0> ;
  assign ToVote[27] = \<const0> ;
  assign ToVote[26] = \<const0> ;
  assign ToVote[25] = \<const0> ;
  assign ToVote[24] = \<const0> ;
  assign ToVote[23] = \<const0> ;
  assign ToVote[22] = \<const0> ;
  assign ToVote[21] = \<const0> ;
  assign ToVote[20] = \<const0> ;
  assign ToVote[19] = \<const0> ;
  assign ToVote[18] = \<const0> ;
  assign ToVote[17] = \<const0> ;
  assign ToVote[16] = \<const0> ;
  assign ToVote[15] = \<const0> ;
  assign ToVote[14] = \<const0> ;
  assign ToVote[13] = \<const0> ;
  assign ToVote[12] = \<const0> ;
  assign ToVote[11] = \<const0> ;
  assign ToVote[10] = \<const0> ;
  assign ToVote[9] = \<const0> ;
  assign ToVote[8] = \<const0> ;
  assign ToVote[7] = \<const0> ;
  assign ToVote[6] = \<const0> ;
  assign ToVote[5] = \<const0> ;
  assign ToVote[4] = \<const0> ;
  assign ToVote[3] = \<const0> ;
  assign ToVote[2] = \<const0> ;
  assign ToVote[1] = \<const0> ;
  assign ToVote[0] = \<const0> ;
  assign UART_Interrupt = \<const0> ;
  assign UART_Tx = \<const0> ;
  GND GND
       (.G(\<const0> ));
  LUT3 #(
    .INIT(8'hFE)) 
    Sl_Ready_INST_0
       (.I0(lmb_reg_write),
        .I1(lmb_reg_read_Q),
        .I2(io_ready_Q),
        .O(Sl_Ready));
  LUT3 #(
    .INIT(8'h80)) 
    \Using_IO_Bus.IO_Addr_Strobe_i_1 
       (.I0(LMB_ABus[0]),
        .I1(LMB_ABus[1]),
        .I2(LMB_AddrStrobe),
        .O(IO_Addr_Strobe00_in));
  FDRE \Using_IO_Bus.IO_Addr_Strobe_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Addr_Strobe00_in),
        .Q(IO_Addr_Strobe),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[10] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[21]),
        .Q(\^IO_Address [10]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[11] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[20]),
        .Q(\^IO_Address [11]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[12] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[19]),
        .Q(\^IO_Address [12]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[13] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[18]),
        .Q(\^IO_Address [13]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[14] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[17]),
        .Q(\^IO_Address [14]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[15] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[16]),
        .Q(\^IO_Address [15]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[16] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[15]),
        .Q(\^IO_Address [16]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[17] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[14]),
        .Q(\^IO_Address [17]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[18] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[13]),
        .Q(\^IO_Address [18]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[19] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[12]),
        .Q(\^IO_Address [19]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[20] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[11]),
        .Q(\^IO_Address [20]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[21] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[10]),
        .Q(\^IO_Address [21]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[22] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[9]),
        .Q(\^IO_Address [22]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[23] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[8]),
        .Q(\^IO_Address [23]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[24] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[7]),
        .Q(\^IO_Address [24]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[25] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[6]),
        .Q(\^IO_Address [25]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[26] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[5]),
        .Q(\^IO_Address [26]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[27] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[4]),
        .Q(\^IO_Address [27]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[28] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[3]),
        .Q(\^IO_Address [28]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[29] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[2]),
        .Q(\^IO_Address [29]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[2] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[29]),
        .Q(\^IO_Address [2]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[3] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[28]),
        .Q(\^IO_Address [3]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[4] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[27]),
        .Q(\^IO_Address [4]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[5] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[26]),
        .Q(\^IO_Address [5]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[6] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[25]),
        .Q(\^IO_Address [6]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[7] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[24]),
        .Q(\^IO_Address [7]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[8] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[23]),
        .Q(\^IO_Address [8]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Address_reg[9] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_ABus[22]),
        .Q(\^IO_Address [9]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[0] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[31]),
        .Q(IO_Write_Data[0]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[10] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[21]),
        .Q(IO_Write_Data[10]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[11] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[20]),
        .Q(IO_Write_Data[11]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[12] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[19]),
        .Q(IO_Write_Data[12]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[13] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[18]),
        .Q(IO_Write_Data[13]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[14] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[17]),
        .Q(IO_Write_Data[14]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[15] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[16]),
        .Q(IO_Write_Data[15]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[16] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[15]),
        .Q(IO_Write_Data[16]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[17] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[14]),
        .Q(IO_Write_Data[17]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[18] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[13]),
        .Q(IO_Write_Data[18]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[19] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[12]),
        .Q(IO_Write_Data[19]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[1] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[30]),
        .Q(IO_Write_Data[1]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[20] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[11]),
        .Q(IO_Write_Data[20]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[21] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[10]),
        .Q(IO_Write_Data[21]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[22] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[9]),
        .Q(IO_Write_Data[22]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[23] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[8]),
        .Q(IO_Write_Data[23]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[24] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[7]),
        .Q(IO_Write_Data[24]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[25] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[6]),
        .Q(IO_Write_Data[25]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[26] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[5]),
        .Q(IO_Write_Data[26]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[27] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[4]),
        .Q(IO_Write_Data[27]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[28] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[3]),
        .Q(IO_Write_Data[28]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[29] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[2]),
        .Q(IO_Write_Data[29]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[2] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[29]),
        .Q(IO_Write_Data[2]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[30] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[1]),
        .Q(IO_Write_Data[30]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[31] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[0]),
        .Q(IO_Write_Data[31]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[3] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[28]),
        .Q(IO_Write_Data[3]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[4] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[27]),
        .Q(IO_Write_Data[4]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[5] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[26]),
        .Q(IO_Write_Data[5]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[6] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[25]),
        .Q(IO_Write_Data[6]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[7] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[24]),
        .Q(IO_Write_Data[7]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[8] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[23]),
        .Q(IO_Write_Data[8]),
        .R(Rst));
  FDRE \Using_IO_Bus.IO_Write_Data_reg[9] 
       (.C(Clk),
        .CE(IO_Addr_Strobe00_in),
        .D(LMB_WriteDBus[22]),
        .Q(IO_Write_Data[9]),
        .R(Rst));
  LUT4 #(
    .INIT(16'h8000)) 
    \Using_IO_Bus.IO_Write_Strobe_i_1 
       (.I0(LMB_AddrStrobe),
        .I1(LMB_ABus[1]),
        .I2(LMB_ABus[0]),
        .I3(LMB_WriteStrobe),
        .O(IO_Write_Strobe__0));
  FDRE \Using_IO_Bus.IO_Write_Strobe_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Write_Strobe__0),
        .Q(IO_Write_Strobe),
        .R(Rst));
  LUT2 #(
    .INIT(4'h7)) 
    \Using_IO_Bus.io_bus_read_data[31]_i_1 
       (.I0(\Using_IO_Bus.io_read_keep_reg_n_0 ),
        .I1(IO_Ready),
        .O(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[0] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[0]),
        .Q(Sl_DBus[31]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[10] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[10]),
        .Q(Sl_DBus[21]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[11] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[11]),
        .Q(Sl_DBus[20]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[12] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[12]),
        .Q(Sl_DBus[19]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[13] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[13]),
        .Q(Sl_DBus[18]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[14] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[14]),
        .Q(Sl_DBus[17]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[15] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[15]),
        .Q(Sl_DBus[16]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[16] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[16]),
        .Q(Sl_DBus[15]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[17] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[17]),
        .Q(Sl_DBus[14]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[18] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[18]),
        .Q(Sl_DBus[13]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[19] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[19]),
        .Q(Sl_DBus[12]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[1]),
        .Q(Sl_DBus[30]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[20] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[20]),
        .Q(Sl_DBus[11]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[21] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[21]),
        .Q(Sl_DBus[10]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[22] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[22]),
        .Q(Sl_DBus[9]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[23] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[23]),
        .Q(Sl_DBus[8]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[24] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[24]),
        .Q(Sl_DBus[7]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[25] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[25]),
        .Q(Sl_DBus[6]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[26] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[26]),
        .Q(Sl_DBus[5]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[27] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[27]),
        .Q(Sl_DBus[4]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[28] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[28]),
        .Q(Sl_DBus[3]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[29] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[29]),
        .Q(Sl_DBus[2]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[2]),
        .Q(Sl_DBus[29]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[30] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[30]),
        .Q(Sl_DBus[1]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[31] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[31]),
        .Q(Sl_DBus[0]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[3] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[3]),
        .Q(Sl_DBus[28]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[4] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[4]),
        .Q(Sl_DBus[27]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[5] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[5]),
        .Q(Sl_DBus[26]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[6] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[6]),
        .Q(Sl_DBus[25]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[7] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[7]),
        .Q(Sl_DBus[24]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[8] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[8]),
        .Q(Sl_DBus[23]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  FDRE \Using_IO_Bus.io_bus_read_data_reg[9] 
       (.C(Clk),
        .CE(1'b1),
        .D(IO_Read_Data[9]),
        .Q(Sl_DBus[22]),
        .R(\Using_IO_Bus.io_bus_read_data[31]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hEAAA)) 
    \Using_IO_Bus.io_read_keep_i_1 
       (.I0(IO_Ready),
        .I1(LMB_AddrStrobe),
        .I2(LMB_ABus[1]),
        .I3(LMB_ABus[0]),
        .O(\Using_IO_Bus.io_read_keep ));
  LUT4 #(
    .INIT(16'h8000)) 
    \Using_IO_Bus.io_read_keep_i_2 
       (.I0(LMB_ReadStrobe),
        .I1(LMB_AddrStrobe),
        .I2(LMB_ABus[1]),
        .I3(LMB_ABus[0]),
        .O(IO_Read_Strobe__0));
  FDRE \Using_IO_Bus.io_read_keep_reg 
       (.C(Clk),
        .CE(\Using_IO_Bus.io_read_keep ),
        .D(IO_Read_Strobe__0),
        .Q(\Using_IO_Bus.io_read_keep_reg_n_0 ),
        .R(Rst));
  LUT2 #(
    .INIT(4'h8)) 
    \Using_IO_Bus.io_ready_Q_i_1 
       (.I0(lmb_io_select_keep),
        .I1(IO_Ready),
        .O(io_ready_Q0));
  FDRE \Using_IO_Bus.io_ready_Q_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(io_ready_Q0),
        .Q(io_ready_Q),
        .R(1'b0));
  FDRE \Using_IO_Bus.lmb_io_select_keep_reg 
       (.C(Clk),
        .CE(\Using_IO_Bus.io_read_keep ),
        .D(IO_Addr_Strobe00_in),
        .Q(lmb_io_select_keep),
        .R(Rst));
  FDRE \lmb_abus_Q_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_ABus[24]),
        .Q(p_0_in21_in),
        .R(1'b0));
  FDRE \lmb_abus_Q_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_ABus[25]),
        .Q(\lmb_abus_Q_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \lmb_abus_Q_reg[3] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_ABus[26]),
        .Q(\lmb_abus_Q_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \lmb_abus_Q_reg[4] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_ABus[27]),
        .Q(\lmb_abus_Q_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \lmb_abus_Q_reg[5] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_ABus[28]),
        .Q(\lmb_abus_Q_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \lmb_abus_Q_reg[6] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_ABus[29]),
        .Q(\lmb_abus_Q_reg_n_0_[6] ),
        .R(1'b0));
  FDRE lmb_reg_read_Q_reg
       (.C(Clk),
        .CE(1'b1),
        .D(lmb_reg_read),
        .Q(lmb_reg_read_Q),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    lmb_reg_read_i_1
       (.I0(LMB_ABus[0]),
        .I1(LMB_ABus[1]),
        .I2(LMB_AddrStrobe),
        .I3(LMB_ReadStrobe),
        .O(lmb_reg_read0));
  FDRE lmb_reg_read_reg
       (.C(Clk),
        .CE(1'b1),
        .D(lmb_reg_read0),
        .Q(lmb_reg_read),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT4 #(
    .INIT(16'h2000)) 
    lmb_reg_write_i_1
       (.I0(LMB_ABus[0]),
        .I1(LMB_ABus[1]),
        .I2(LMB_AddrStrobe),
        .I3(LMB_WriteStrobe),
        .O(lmb_reg_write0));
  FDRE lmb_reg_write_reg
       (.C(Clk),
        .CE(1'b1),
        .D(lmb_reg_write0),
        .Q(lmb_reg_write),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h40)) 
    uart_tx_write_inferred_i_1
       (.I0(p_0_in21_in),
        .I1(lmb_reg_write),
        .I2(uart_tx_write_inferred_i_2_n_0),
        .O(uart_tx_write));
  LUT5 #(
    .INIT(32'h00000010)) 
    uart_tx_write_inferred_i_2
       (.I0(\lmb_abus_Q_reg_n_0_[3] ),
        .I1(\lmb_abus_Q_reg_n_0_[5] ),
        .I2(\lmb_abus_Q_reg_n_0_[6] ),
        .I3(\lmb_abus_Q_reg_n_0_[2] ),
        .I4(\lmb_abus_Q_reg_n_0_[4] ),
        .O(uart_tx_write_inferred_i_2_n_0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[0] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[31]),
        .Q(write_data[0]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[10] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[21]),
        .Q(write_data[10]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[11] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[20]),
        .Q(write_data[11]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[12] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[19]),
        .Q(write_data[12]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[13] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[18]),
        .Q(write_data[13]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[14] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[17]),
        .Q(write_data[14]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[15] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[16]),
        .Q(write_data[15]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[16] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[15]),
        .Q(write_data[16]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[17] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[14]),
        .Q(write_data[17]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[18] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[13]),
        .Q(write_data[18]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[19] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[12]),
        .Q(write_data[19]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[30]),
        .Q(write_data[1]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[20] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[11]),
        .Q(write_data[20]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[21] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[10]),
        .Q(write_data[21]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[22] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[9]),
        .Q(write_data[22]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[23] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[8]),
        .Q(write_data[23]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[24] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[7]),
        .Q(write_data[24]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[25] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[6]),
        .Q(write_data[25]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[26] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[5]),
        .Q(write_data[26]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[27] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[4]),
        .Q(write_data[27]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[28] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[3]),
        .Q(write_data[28]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[29] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[2]),
        .Q(write_data[29]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[29]),
        .Q(write_data[2]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[30] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[1]),
        .Q(write_data[30]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[31] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[0]),
        .Q(write_data[31]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[3] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[28]),
        .Q(write_data[3]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[4] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[27]),
        .Q(write_data[4]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[5] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[26]),
        .Q(write_data[5]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[6] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[25]),
        .Q(write_data[6]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[7] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[24]),
        .Q(write_data[7]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[8] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[23]),
        .Q(write_data[8]),
        .R(1'b0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE \write_data_reg[9] 
       (.C(Clk),
        .CE(1'b1),
        .D(LMB_WriteDBus[22]),
        .Q(write_data[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "lmb_bram_if_cntlr" *) 
module ddr4_0_lmb_bram_if_cntlr
   (BRAM_WEN_A,
    Sl_Ready,
    LMB_Rst,
    LMB_Clk,
    LMB_AddrStrobe,
    LMB_WriteStrobe,
    LMB_ABus,
    LMB_BE);
  output [0:3]BRAM_WEN_A;
  output Sl_Ready;
  input LMB_Rst;
  input LMB_Clk;
  input LMB_AddrStrobe;
  input LMB_WriteStrobe;
  input [2:0]LMB_ABus;
  input [0:3]LMB_BE;

  wire [0:3]BRAM_WEN_A;
  wire [2:0]LMB_ABus;
  wire LMB_AddrStrobe;
  wire [0:3]LMB_BE;
  wire LMB_Clk;
  wire LMB_Rst;
  wire LMB_WriteStrobe;
  wire Sl_Rdy;
  wire Sl_Ready;
  wire lmb_as;
  wire lmb_select;

  LUT5 #(
    .INIT(32'h00020000)) 
    \BRAM_WEN_A[0]_INST_0 
       (.I0(LMB_WriteStrobe),
        .I1(LMB_ABus[2]),
        .I2(LMB_ABus[1]),
        .I3(LMB_ABus[0]),
        .I4(LMB_BE[0]),
        .O(BRAM_WEN_A[0]));
  LUT5 #(
    .INIT(32'h00020000)) 
    \BRAM_WEN_A[1]_INST_0 
       (.I0(LMB_WriteStrobe),
        .I1(LMB_ABus[2]),
        .I2(LMB_ABus[1]),
        .I3(LMB_ABus[0]),
        .I4(LMB_BE[1]),
        .O(BRAM_WEN_A[1]));
  LUT5 #(
    .INIT(32'h00020000)) 
    \BRAM_WEN_A[2]_INST_0 
       (.I0(LMB_WriteStrobe),
        .I1(LMB_ABus[2]),
        .I2(LMB_ABus[1]),
        .I3(LMB_ABus[0]),
        .I4(LMB_BE[2]),
        .O(BRAM_WEN_A[2]));
  LUT5 #(
    .INIT(32'h00020000)) 
    \BRAM_WEN_A[3]_INST_0 
       (.I0(LMB_WriteStrobe),
        .I1(LMB_ABus[2]),
        .I2(LMB_ABus[1]),
        .I3(LMB_ABus[0]),
        .I4(LMB_BE[3]),
        .O(BRAM_WEN_A[3]));
  FDRE \No_ECC.Sl_Rdy_reg 
       (.C(LMB_Clk),
        .CE(1'b1),
        .D(lmb_select),
        .Q(Sl_Rdy),
        .R(LMB_Rst));
  FDRE \No_ECC.lmb_as_reg 
       (.C(LMB_Clk),
        .CE(1'b1),
        .D(LMB_AddrStrobe),
        .Q(lmb_as),
        .R(LMB_Rst));
  LUT2 #(
    .INIT(4'h8)) 
    Sl_Ready_INST_0
       (.I0(lmb_as),
        .I1(Sl_Rdy),
        .O(Sl_Ready));
  ddr4_0_lmb_mux lmb_mux_I
       (.LMB_ABus(LMB_ABus),
        .lmb_select(lmb_select));
endmodule

(* ORIG_REF_NAME = "lmb_bram_if_cntlr" *) 
module ddr4_0_lmb_bram_if_cntlr__parameterized1
   (Sl_Ready,
    LMB_ABus,
    LMB_Rst,
    LMB_Clk,
    LMB_AddrStrobe);
  output Sl_Ready;
  input [1:0]LMB_ABus;
  input LMB_Rst;
  input LMB_Clk;
  input LMB_AddrStrobe;

  wire [1:0]LMB_ABus;
  wire LMB_AddrStrobe;
  wire LMB_Clk;
  wire LMB_Rst;
  wire Sl_Rdy;
  wire Sl_Ready;
  wire lmb_as;
  wire lmb_select;

  LUT2 #(
    .INIT(4'h1)) 
    \No_ECC.Sl_Rdy_i_1 
       (.I0(LMB_ABus[0]),
        .I1(LMB_ABus[1]),
        .O(lmb_select));
  FDRE \No_ECC.Sl_Rdy_reg 
       (.C(LMB_Clk),
        .CE(1'b1),
        .D(lmb_select),
        .Q(Sl_Rdy),
        .R(LMB_Rst));
  FDRE \No_ECC.lmb_as_reg 
       (.C(LMB_Clk),
        .CE(1'b1),
        .D(LMB_AddrStrobe),
        .Q(lmb_as),
        .R(LMB_Rst));
  LUT2 #(
    .INIT(4'h8)) 
    Sl_Ready_INST_0
       (.I0(lmb_as),
        .I1(Sl_Rdy),
        .O(Sl_Ready));
endmodule

(* ORIG_REF_NAME = "lmb_bram_if_cntlr" *) 
module ddr4_0_lmb_bram_if_cntlr__parameterized3
   (Sl_Ready,
    BRAM_WEN_A,
    LMB_ABus,
    LMB_Rst,
    LMB_Clk,
    LMB_AddrStrobe,
    LMB_WriteStrobe,
    LMB_BE);
  output Sl_Ready;
  output [0:3]BRAM_WEN_A;
  input [2:0]LMB_ABus;
  input LMB_Rst;
  input LMB_Clk;
  input LMB_AddrStrobe;
  input LMB_WriteStrobe;
  input [0:3]LMB_BE;

  wire [0:3]BRAM_WEN_A;
  wire [2:0]LMB_ABus;
  wire LMB_AddrStrobe;
  wire [0:3]LMB_BE;
  wire LMB_Clk;
  wire LMB_Rst;
  wire LMB_WriteStrobe;
  wire \No_ECC.Sl_Rdy_i_1_n_0 ;
  wire Sl_Rdy;
  wire Sl_Ready;
  wire lmb_as;

  LUT5 #(
    .INIT(32'h00080000)) 
    \BRAM_WEN_A[0]_INST_0 
       (.I0(LMB_WriteStrobe),
        .I1(LMB_ABus[0]),
        .I2(LMB_ABus[2]),
        .I3(LMB_ABus[1]),
        .I4(LMB_BE[0]),
        .O(BRAM_WEN_A[0]));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT5 #(
    .INIT(32'h00080000)) 
    \BRAM_WEN_A[1]_INST_0 
       (.I0(LMB_WriteStrobe),
        .I1(LMB_ABus[0]),
        .I2(LMB_ABus[2]),
        .I3(LMB_ABus[1]),
        .I4(LMB_BE[1]),
        .O(BRAM_WEN_A[1]));
  LUT5 #(
    .INIT(32'h00080000)) 
    \BRAM_WEN_A[2]_INST_0 
       (.I0(LMB_WriteStrobe),
        .I1(LMB_ABus[0]),
        .I2(LMB_ABus[2]),
        .I3(LMB_ABus[1]),
        .I4(LMB_BE[2]),
        .O(BRAM_WEN_A[2]));
  LUT5 #(
    .INIT(32'h00080000)) 
    \BRAM_WEN_A[3]_INST_0 
       (.I0(LMB_WriteStrobe),
        .I1(LMB_ABus[0]),
        .I2(LMB_ABus[2]),
        .I3(LMB_ABus[1]),
        .I4(LMB_BE[3]),
        .O(BRAM_WEN_A[3]));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \No_ECC.Sl_Rdy_i_1 
       (.I0(LMB_ABus[0]),
        .I1(LMB_ABus[2]),
        .I2(LMB_ABus[1]),
        .O(\No_ECC.Sl_Rdy_i_1_n_0 ));
  FDRE \No_ECC.Sl_Rdy_reg 
       (.C(LMB_Clk),
        .CE(1'b1),
        .D(\No_ECC.Sl_Rdy_i_1_n_0 ),
        .Q(Sl_Rdy),
        .R(LMB_Rst));
  FDRE \No_ECC.lmb_as_reg 
       (.C(LMB_Clk),
        .CE(1'b1),
        .D(LMB_AddrStrobe),
        .Q(lmb_as),
        .R(LMB_Rst));
  LUT2 #(
    .INIT(4'h8)) 
    Sl_Ready_INST_0
       (.I0(lmb_as),
        .I1(Sl_Rdy),
        .O(Sl_Ready));
endmodule

(* ORIG_REF_NAME = "lmb_bram_if_cntlr" *) 
module ddr4_0_lmb_bram_if_cntlr__parameterized5
   (Sl_Ready,
    LMB_ABus,
    LMB_Rst,
    LMB_Clk,
    LMB_AddrStrobe);
  output Sl_Ready;
  input [1:0]LMB_ABus;
  input LMB_Rst;
  input LMB_Clk;
  input LMB_AddrStrobe;

  wire [1:0]LMB_ABus;
  wire LMB_AddrStrobe;
  wire LMB_Clk;
  wire LMB_Rst;
  wire \No_ECC.Sl_Rdy_i_1_n_0 ;
  wire Sl_Rdy;
  wire Sl_Ready;
  wire lmb_as;

  LUT2 #(
    .INIT(4'h2)) 
    \No_ECC.Sl_Rdy_i_1 
       (.I0(LMB_ABus[0]),
        .I1(LMB_ABus[1]),
        .O(\No_ECC.Sl_Rdy_i_1_n_0 ));
  FDRE \No_ECC.Sl_Rdy_reg 
       (.C(LMB_Clk),
        .CE(1'b1),
        .D(\No_ECC.Sl_Rdy_i_1_n_0 ),
        .Q(Sl_Rdy),
        .R(LMB_Rst));
  FDRE \No_ECC.lmb_as_reg 
       (.C(LMB_Clk),
        .CE(1'b1),
        .D(LMB_AddrStrobe),
        .Q(lmb_as),
        .R(LMB_Rst));
  LUT2 #(
    .INIT(4'h8)) 
    Sl_Ready_INST_0
       (.I0(lmb_as),
        .I1(Sl_Rdy),
        .O(Sl_Ready));
endmodule

(* ORIG_REF_NAME = "lmb_bram_if_cntlr_v4_0_21_pselect_mask" *) 
module ddr4_0_lmb_bram_if_cntlr_v4_0_21_pselect_mask
   (lmb_select,
    LMB_ABus);
  output lmb_select;
  input [2:0]LMB_ABus;

  wire [2:0]LMB_ABus;
  wire lmb_select;

  LUT3 #(
    .INIT(8'h01)) 
    \No_ECC.Sl_Rdy_i_1 
       (.I0(LMB_ABus[2]),
        .I1(LMB_ABus[1]),
        .I2(LMB_ABus[0]),
        .O(lmb_select));
endmodule

(* ORIG_REF_NAME = "lmb_mux" *) 
module ddr4_0_lmb_mux
   (lmb_select,
    LMB_ABus);
  output lmb_select;
  input [2:0]LMB_ABus;

  wire [2:0]LMB_ABus;
  wire lmb_select;

  ddr4_0_lmb_bram_if_cntlr_v4_0_21_pselect_mask \one_lmb.pselect_mask_lmb 
       (.LMB_ABus(LMB_ABus),
        .lmb_select(lmb_select));
endmodule

(* C_EXT_RESET_HIGH = "1" *) (* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *) 
(* C_LMB_NUM_SLAVES = "3" *) (* C_LMB_PROTOCOL = "0" *) (* ORIG_REF_NAME = "lmb_v10" *) 
module ddr4_0_lmb_v10
   (LMB_Clk,
    SYS_Rst,
    LMB_Rst,
    M_ABus,
    M_ReadStrobe,
    M_WriteStrobe,
    M_AddrStrobe,
    M_DBus,
    M_BE,
    Sl_DBus,
    Sl_Ready,
    Sl_Wait,
    Sl_UE,
    Sl_CE,
    LMB_ABus,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_AddrStrobe,
    LMB_ReadDBus,
    LMB_WriteDBus,
    LMB_Ready,
    LMB_Wait,
    LMB_UE,
    LMB_CE,
    LMB_BE);
  input LMB_Clk;
  input SYS_Rst;
  output LMB_Rst;
  input [0:31]M_ABus;
  input M_ReadStrobe;
  input M_WriteStrobe;
  input M_AddrStrobe;
  input [0:31]M_DBus;
  input [0:3]M_BE;
  input [0:95]Sl_DBus;
  input [0:2]Sl_Ready;
  input [0:2]Sl_Wait;
  input [0:2]Sl_UE;
  input [0:2]Sl_CE;
  output [0:31]LMB_ABus;
  output LMB_ReadStrobe;
  output LMB_WriteStrobe;
  output LMB_AddrStrobe;
  output [0:31]LMB_ReadDBus;
  output [0:31]LMB_WriteDBus;
  output LMB_Ready;
  output LMB_Wait;
  output LMB_UE;
  output LMB_CE;
  output [0:3]LMB_BE;

  wire \<const0> ;
  wire [0:31]LMB_ReadDBus;
  wire LMB_Ready;
  wire [0:31]M_ABus;
  wire M_AddrStrobe;
  wire [0:3]M_BE;
  wire [0:31]M_DBus;
  wire M_ReadStrobe;
  wire M_WriteStrobe;
  wire [0:95]Sl_DBus;
  wire [0:2]Sl_Ready;

  assign LMB_ABus[0:29] = M_ABus[0:29];
  assign LMB_ABus[30] = \<const0> ;
  assign LMB_ABus[31] = \<const0> ;
  assign LMB_AddrStrobe = M_AddrStrobe;
  assign LMB_BE[0:3] = M_BE;
  assign LMB_CE = \<const0> ;
  assign LMB_ReadStrobe = M_ReadStrobe;
  assign LMB_Rst = \<const0> ;
  assign LMB_UE = \<const0> ;
  assign LMB_Wait = \<const0> ;
  assign LMB_WriteDBus[0:31] = M_DBus;
  assign LMB_WriteStrobe = M_WriteStrobe;
  GND GND
       (.G(\<const0> ));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[0]_INST_0 
       (.I0(Sl_DBus[0]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[32]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[64]),
        .O(LMB_ReadDBus[0]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[10]_INST_0 
       (.I0(Sl_DBus[10]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[42]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[74]),
        .O(LMB_ReadDBus[10]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[11]_INST_0 
       (.I0(Sl_DBus[11]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[43]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[75]),
        .O(LMB_ReadDBus[11]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[12]_INST_0 
       (.I0(Sl_DBus[12]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[44]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[76]),
        .O(LMB_ReadDBus[12]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[13]_INST_0 
       (.I0(Sl_DBus[13]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[45]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[77]),
        .O(LMB_ReadDBus[13]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[14]_INST_0 
       (.I0(Sl_DBus[14]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[46]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[78]),
        .O(LMB_ReadDBus[14]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[15]_INST_0 
       (.I0(Sl_DBus[15]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[47]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[79]),
        .O(LMB_ReadDBus[15]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[16]_INST_0 
       (.I0(Sl_DBus[16]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[48]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[80]),
        .O(LMB_ReadDBus[16]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[17]_INST_0 
       (.I0(Sl_DBus[17]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[49]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[81]),
        .O(LMB_ReadDBus[17]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[18]_INST_0 
       (.I0(Sl_DBus[18]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[50]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[82]),
        .O(LMB_ReadDBus[18]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[19]_INST_0 
       (.I0(Sl_DBus[19]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[51]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[83]),
        .O(LMB_ReadDBus[19]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[1]_INST_0 
       (.I0(Sl_DBus[1]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[33]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[65]),
        .O(LMB_ReadDBus[1]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[20]_INST_0 
       (.I0(Sl_DBus[20]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[52]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[84]),
        .O(LMB_ReadDBus[20]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[21]_INST_0 
       (.I0(Sl_DBus[21]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[53]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[85]),
        .O(LMB_ReadDBus[21]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[22]_INST_0 
       (.I0(Sl_DBus[22]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[54]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[86]),
        .O(LMB_ReadDBus[22]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[23]_INST_0 
       (.I0(Sl_DBus[23]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[55]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[87]),
        .O(LMB_ReadDBus[23]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[24]_INST_0 
       (.I0(Sl_DBus[24]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[56]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[88]),
        .O(LMB_ReadDBus[24]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[25]_INST_0 
       (.I0(Sl_DBus[25]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[57]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[89]),
        .O(LMB_ReadDBus[25]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[26]_INST_0 
       (.I0(Sl_DBus[26]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[58]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[90]),
        .O(LMB_ReadDBus[26]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[27]_INST_0 
       (.I0(Sl_DBus[27]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[59]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[91]),
        .O(LMB_ReadDBus[27]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[28]_INST_0 
       (.I0(Sl_DBus[28]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[60]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[92]),
        .O(LMB_ReadDBus[28]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[29]_INST_0 
       (.I0(Sl_DBus[29]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[61]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[93]),
        .O(LMB_ReadDBus[29]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[2]_INST_0 
       (.I0(Sl_DBus[2]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[34]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[66]),
        .O(LMB_ReadDBus[2]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[30]_INST_0 
       (.I0(Sl_DBus[30]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[62]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[94]),
        .O(LMB_ReadDBus[30]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[31]_INST_0 
       (.I0(Sl_DBus[31]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[63]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[95]),
        .O(LMB_ReadDBus[31]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[3]_INST_0 
       (.I0(Sl_DBus[3]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[35]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[67]),
        .O(LMB_ReadDBus[3]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[4]_INST_0 
       (.I0(Sl_DBus[4]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[36]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[68]),
        .O(LMB_ReadDBus[4]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[5]_INST_0 
       (.I0(Sl_DBus[5]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[37]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[69]),
        .O(LMB_ReadDBus[5]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[6]_INST_0 
       (.I0(Sl_DBus[6]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[38]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[70]),
        .O(LMB_ReadDBus[6]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[7]_INST_0 
       (.I0(Sl_DBus[7]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[39]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[71]),
        .O(LMB_ReadDBus[7]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[8]_INST_0 
       (.I0(Sl_DBus[8]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[40]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[72]),
        .O(LMB_ReadDBus[8]));
  LUT6 #(
    .INIT(64'hFFFFF888F888F888)) 
    \LMB_ReadDBus[9]_INST_0 
       (.I0(Sl_DBus[9]),
        .I1(Sl_Ready[0]),
        .I2(Sl_Ready[1]),
        .I3(Sl_DBus[41]),
        .I4(Sl_Ready[2]),
        .I5(Sl_DBus[73]),
        .O(LMB_ReadDBus[9]));
  LUT3 #(
    .INIT(8'hFE)) 
    LMB_Ready_INST_0
       (.I0(Sl_Ready[0]),
        .I1(Sl_Ready[1]),
        .I2(Sl_Ready[2]),
        .O(LMB_Ready));
endmodule

(* C_EXT_RESET_HIGH = "1" *) (* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *) 
(* C_LMB_NUM_SLAVES = "2" *) (* C_LMB_PROTOCOL = "0" *) (* ORIG_REF_NAME = "lmb_v10" *) 
module ddr4_0_lmb_v10__parameterized1
   (LMB_Clk,
    SYS_Rst,
    LMB_Rst,
    M_ABus,
    M_ReadStrobe,
    M_WriteStrobe,
    M_AddrStrobe,
    M_DBus,
    M_BE,
    Sl_DBus,
    Sl_Ready,
    Sl_Wait,
    Sl_UE,
    Sl_CE,
    LMB_ABus,
    LMB_ReadStrobe,
    LMB_WriteStrobe,
    LMB_AddrStrobe,
    LMB_ReadDBus,
    LMB_WriteDBus,
    LMB_Ready,
    LMB_Wait,
    LMB_UE,
    LMB_CE,
    LMB_BE);
  input LMB_Clk;
  input SYS_Rst;
  output LMB_Rst;
  input [0:31]M_ABus;
  input M_ReadStrobe;
  input M_WriteStrobe;
  input M_AddrStrobe;
  input [0:31]M_DBus;
  input [0:3]M_BE;
  input [0:63]Sl_DBus;
  input [0:1]Sl_Ready;
  input [0:1]Sl_Wait;
  input [0:1]Sl_UE;
  input [0:1]Sl_CE;
  output [0:31]LMB_ABus;
  output LMB_ReadStrobe;
  output LMB_WriteStrobe;
  output LMB_AddrStrobe;
  output [0:31]LMB_ReadDBus;
  output [0:31]LMB_WriteDBus;
  output LMB_Ready;
  output LMB_Wait;
  output LMB_UE;
  output LMB_CE;
  output [0:3]LMB_BE;

  wire \<const0> ;
  wire [0:31]LMB_ReadDBus;
  wire LMB_Ready;
  wire [0:31]M_ABus;
  wire M_AddrStrobe;
  wire [0:63]Sl_DBus;
  wire [0:1]Sl_Ready;

  assign LMB_ABus[0] = M_ABus[0];
  assign LMB_ABus[1] = \<const0> ;
  assign LMB_ABus[2] = \<const0> ;
  assign LMB_ABus[3] = \<const0> ;
  assign LMB_ABus[4] = \<const0> ;
  assign LMB_ABus[5] = \<const0> ;
  assign LMB_ABus[6] = \<const0> ;
  assign LMB_ABus[7] = \<const0> ;
  assign LMB_ABus[8] = \<const0> ;
  assign LMB_ABus[9] = \<const0> ;
  assign LMB_ABus[10] = \<const0> ;
  assign LMB_ABus[11] = \<const0> ;
  assign LMB_ABus[12] = \<const0> ;
  assign LMB_ABus[13] = \<const0> ;
  assign LMB_ABus[14] = \<const0> ;
  assign LMB_ABus[15:29] = M_ABus[15:29];
  assign LMB_ABus[30] = \<const0> ;
  assign LMB_ABus[31] = \<const0> ;
  assign LMB_AddrStrobe = M_AddrStrobe;
  assign LMB_BE[0] = \<const0> ;
  assign LMB_BE[1] = \<const0> ;
  assign LMB_BE[2] = \<const0> ;
  assign LMB_BE[3] = \<const0> ;
  assign LMB_CE = \<const0> ;
  assign LMB_ReadStrobe = \<const0> ;
  assign LMB_Rst = \<const0> ;
  assign LMB_UE = \<const0> ;
  assign LMB_Wait = \<const0> ;
  assign LMB_WriteDBus[0] = \<const0> ;
  assign LMB_WriteDBus[1] = \<const0> ;
  assign LMB_WriteDBus[2] = \<const0> ;
  assign LMB_WriteDBus[3] = \<const0> ;
  assign LMB_WriteDBus[4] = \<const0> ;
  assign LMB_WriteDBus[5] = \<const0> ;
  assign LMB_WriteDBus[6] = \<const0> ;
  assign LMB_WriteDBus[7] = \<const0> ;
  assign LMB_WriteDBus[8] = \<const0> ;
  assign LMB_WriteDBus[9] = \<const0> ;
  assign LMB_WriteDBus[10] = \<const0> ;
  assign LMB_WriteDBus[11] = \<const0> ;
  assign LMB_WriteDBus[12] = \<const0> ;
  assign LMB_WriteDBus[13] = \<const0> ;
  assign LMB_WriteDBus[14] = \<const0> ;
  assign LMB_WriteDBus[15] = \<const0> ;
  assign LMB_WriteDBus[16] = \<const0> ;
  assign LMB_WriteDBus[17] = \<const0> ;
  assign LMB_WriteDBus[18] = \<const0> ;
  assign LMB_WriteDBus[19] = \<const0> ;
  assign LMB_WriteDBus[20] = \<const0> ;
  assign LMB_WriteDBus[21] = \<const0> ;
  assign LMB_WriteDBus[22] = \<const0> ;
  assign LMB_WriteDBus[23] = \<const0> ;
  assign LMB_WriteDBus[24] = \<const0> ;
  assign LMB_WriteDBus[25] = \<const0> ;
  assign LMB_WriteDBus[26] = \<const0> ;
  assign LMB_WriteDBus[27] = \<const0> ;
  assign LMB_WriteDBus[28] = \<const0> ;
  assign LMB_WriteDBus[29] = \<const0> ;
  assign LMB_WriteDBus[30] = \<const0> ;
  assign LMB_WriteDBus[31] = \<const0> ;
  assign LMB_WriteStrobe = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[0]_INST_0 
       (.I0(Sl_DBus[0]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[32]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[0]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[10]_INST_0 
       (.I0(Sl_DBus[10]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[42]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[10]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[11]_INST_0 
       (.I0(Sl_DBus[11]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[43]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[11]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[12]_INST_0 
       (.I0(Sl_DBus[12]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[44]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[12]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[13]_INST_0 
       (.I0(Sl_DBus[13]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[45]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[13]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[14]_INST_0 
       (.I0(Sl_DBus[14]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[46]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[14]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[15]_INST_0 
       (.I0(Sl_DBus[15]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[47]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[15]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[16]_INST_0 
       (.I0(Sl_DBus[16]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[48]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[16]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[17]_INST_0 
       (.I0(Sl_DBus[17]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[49]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[17]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[18]_INST_0 
       (.I0(Sl_DBus[18]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[50]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[18]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[19]_INST_0 
       (.I0(Sl_DBus[19]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[51]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[19]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[1]_INST_0 
       (.I0(Sl_DBus[1]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[33]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[1]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[20]_INST_0 
       (.I0(Sl_DBus[20]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[52]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[20]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[21]_INST_0 
       (.I0(Sl_DBus[21]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[53]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[21]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[22]_INST_0 
       (.I0(Sl_DBus[22]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[54]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[22]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[23]_INST_0 
       (.I0(Sl_DBus[23]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[55]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[23]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[24]_INST_0 
       (.I0(Sl_DBus[24]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[56]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[24]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[25]_INST_0 
       (.I0(Sl_DBus[25]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[57]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[25]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[26]_INST_0 
       (.I0(Sl_DBus[26]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[58]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[26]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[27]_INST_0 
       (.I0(Sl_DBus[27]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[59]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[27]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[28]_INST_0 
       (.I0(Sl_DBus[28]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[60]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[28]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[29]_INST_0 
       (.I0(Sl_DBus[29]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[61]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[29]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[2]_INST_0 
       (.I0(Sl_DBus[2]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[34]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[2]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[30]_INST_0 
       (.I0(Sl_DBus[30]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[62]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[30]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[31]_INST_0 
       (.I0(Sl_DBus[31]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[63]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[31]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[3]_INST_0 
       (.I0(Sl_DBus[3]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[35]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[3]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[4]_INST_0 
       (.I0(Sl_DBus[4]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[36]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[4]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[5]_INST_0 
       (.I0(Sl_DBus[5]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[37]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[5]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[6]_INST_0 
       (.I0(Sl_DBus[6]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[38]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[6]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[7]_INST_0 
       (.I0(Sl_DBus[7]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[39]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[7]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[8]_INST_0 
       (.I0(Sl_DBus[8]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[40]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[8]));
  LUT4 #(
    .INIT(16'hF888)) 
    \LMB_ReadDBus[9]_INST_0 
       (.I0(Sl_DBus[9]),
        .I1(Sl_Ready[0]),
        .I2(Sl_DBus[41]),
        .I3(Sl_Ready[1]),
        .O(LMB_ReadDBus[9]));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT2 #(
    .INIT(4'hE)) 
    LMB_Ready_INST_0
       (.I0(Sl_Ready[0]),
        .I1(Sl_Ready[1]),
        .O(LMB_Ready));
endmodule

(* ORIG_REF_NAME = "lpf" *) 
module ddr4_0_lpf
   (lpf_int,
    slowest_sync_clk,
    ext_reset_in);
  output lpf_int;
  input slowest_sync_clk;
  input ext_reset_in;

  wire \ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ;
  wire Q;
  wire [0:0]exr_lpf;
  wire ext_reset_in;
  wire lpf_exr;
  wire lpf_int;
  wire lpf_int0;
  wire p_1_in4_in;
  wire p_2_in3_in;
  wire p_3_in6_in;
  wire slowest_sync_clk;

  ddr4_0_cdc_sync \ACTIVE_HIGH_EXT.ACT_HI_EXT 
       (.exr_lpf(exr_lpf),
        .ext_reset_in(ext_reset_in),
        .lpf_exr(lpf_exr),
        .lpf_exr_reg(\ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ),
        .p_1_in4_in(p_1_in4_in),
        .p_2_in3_in(p_2_in3_in),
        .scndry_out(p_3_in6_in),
        .slowest_sync_clk(slowest_sync_clk));
  FDRE #(
    .INIT(1'b0)) 
    \EXT_LPF[1].exr_lpf_reg[1] 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(p_3_in6_in),
        .Q(p_2_in3_in),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \EXT_LPF[2].exr_lpf_reg[2] 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(p_2_in3_in),
        .Q(p_1_in4_in),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \EXT_LPF[3].exr_lpf_reg[3] 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(p_1_in4_in),
        .Q(exr_lpf),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* XILINX_LEGACY_PRIM = "SRL16" *) 
  (* XILINX_TRANSFORM_PINMAP = "VCC:CE" *) 
  (* srl_name = "inst/u_ddr4_mem_intfci_12/\u_ddr_cal_riu/mcs0 /inst/rst_0/U0/\EXT_LPF/POR_SRL_I " *) 
  SRL16E #(
    .INIT(16'hFFFF)) 
    POR_SRL_I
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(slowest_sync_clk),
        .D(1'b0),
        .Q(Q));
  FDRE #(
    .INIT(1'b0)) 
    lpf_exr_reg
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(\ACTIVE_HIGH_EXT.ACT_HI_EXT_n_0 ),
        .Q(lpf_exr),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    lpf_int_i_1
       (.I0(lpf_exr),
        .I1(Q),
        .O(lpf_int0));
  FDRE #(
    .INIT(1'b0)) 
    lpf_int_reg
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(lpf_int0),
        .Q(lpf_int),
        .R(1'b0));
endmodule

(* CHECK_LICENSE_TYPE = "ddr4_0_microblaze_mcs,bd_9054,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "bd_9054,Vivado 2022.2" *) 
module ddr4_0_microblaze_mcs
   (Clk,
    Reset,
    TRACE_data_access,
    TRACE_data_address,
    TRACE_data_byte_enable,
    TRACE_data_read,
    TRACE_data_write,
    TRACE_data_write_value,
    TRACE_dcache_hit,
    TRACE_dcache_rdy,
    TRACE_dcache_read,
    TRACE_dcache_req,
    TRACE_delay_slot,
    TRACE_ex_piperun,
    TRACE_exception_kind,
    TRACE_exception_taken,
    TRACE_icache_hit,
    TRACE_icache_rdy,
    TRACE_icache_req,
    TRACE_instruction,
    TRACE_jump_hit,
    TRACE_jump_taken,
    TRACE_mb_halted,
    TRACE_mem_piperun,
    TRACE_msr_reg,
    TRACE_new_reg_value,
    TRACE_of_piperun,
    TRACE_pc,
    TRACE_pid_reg,
    TRACE_reg_addr,
    TRACE_reg_write,
    TRACE_valid_instr,
    IO_addr_strobe,
    IO_address,
    IO_byte_enable,
    IO_read_data,
    IO_read_strobe,
    IO_ready,
    IO_write_data,
    IO_write_strobe);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.Clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.Clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_9054_Clk, INSERT_VIP 0, ASSOCIATED_ASYNC_RESET Reset, BOARD.ASSOCIATED_PARAM CLK_BOARD_INTERFACE" *) input Clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.Reset RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.Reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE" *) input Reset;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_ACCESS" *) output TRACE_data_access;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_ADDRESS" *) output [0:31]TRACE_data_address;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_BYTE_ENABLE" *) output [0:3]TRACE_data_byte_enable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_READ" *) output TRACE_data_read;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE" *) output TRACE_data_write;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DATA_WRITE_VALUE" *) output [0:31]TRACE_data_write_value;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_HIT" *) output TRACE_dcache_hit;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_RDY" *) output TRACE_dcache_rdy;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_READ" *) output TRACE_dcache_read;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DCACHE_REQ" *) output TRACE_dcache_req;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE DELAY_SLOT" *) output TRACE_delay_slot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EX_PIPERUN" *) output TRACE_ex_piperun;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_KIND" *) output [0:4]TRACE_exception_kind;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE EXCEPTION_TAKEN" *) output TRACE_exception_taken;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_HIT" *) output TRACE_icache_hit;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_RDY" *) output TRACE_icache_rdy;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE ICACHE_REQ" *) output TRACE_icache_req;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE INSTRUCTION" *) output [0:31]TRACE_instruction;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE JUMP_HIT" *) output TRACE_jump_hit;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE JUMP_TAKEN" *) output TRACE_jump_taken;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MB_HALTED" *) output TRACE_mb_halted;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MEM_PIPERUN" *) output TRACE_mem_piperun;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE MSR_REG" *) output [0:14]TRACE_msr_reg;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE NEW_REG_VALUE" *) output [0:31]TRACE_new_reg_value;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE OF_PIPERUN" *) output TRACE_of_piperun;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE PC" *) output [0:31]TRACE_pc;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE PID_REG" *) output [0:7]TRACE_pid_reg;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE REG_ADDR" *) output [0:4]TRACE_reg_addr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE REG_WRITE" *) output TRACE_reg_write;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mbtrace:2.0 TRACE VALID_INSTR" *) output TRACE_valid_instr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO ADDR_STROBE" *) output IO_addr_strobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO ADDRESS" *) output [31:0]IO_address;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO BYTE_ENABLE" *) output [3:0]IO_byte_enable;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READ_DATA" *) input [31:0]IO_read_data;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READ_STROBE" *) output IO_read_strobe;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO READY" *) input IO_ready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO WRITE_DATA" *) output [31:0]IO_write_data;
  (* X_INTERFACE_INFO = "xilinx.com:interface:mcsio_bus:1.0 IO WRITE_STROBE" *) output IO_write_strobe;

  wire \<const0> ;
  wire Clk;
  wire IO_addr_strobe;
  wire [29:2]\^IO_address ;
  wire [31:0]IO_read_data;
  wire IO_ready;
  wire [31:0]IO_write_data;
  wire IO_write_strobe;
  wire Reset;
  wire NLW_inst_IO_read_strobe_UNCONNECTED;
  wire NLW_inst_TRACE_data_access_UNCONNECTED;
  wire NLW_inst_TRACE_data_read_UNCONNECTED;
  wire NLW_inst_TRACE_data_write_UNCONNECTED;
  wire NLW_inst_TRACE_dcache_hit_UNCONNECTED;
  wire NLW_inst_TRACE_dcache_rdy_UNCONNECTED;
  wire NLW_inst_TRACE_dcache_read_UNCONNECTED;
  wire NLW_inst_TRACE_dcache_req_UNCONNECTED;
  wire NLW_inst_TRACE_delay_slot_UNCONNECTED;
  wire NLW_inst_TRACE_ex_piperun_UNCONNECTED;
  wire NLW_inst_TRACE_exception_taken_UNCONNECTED;
  wire NLW_inst_TRACE_icache_hit_UNCONNECTED;
  wire NLW_inst_TRACE_icache_rdy_UNCONNECTED;
  wire NLW_inst_TRACE_icache_req_UNCONNECTED;
  wire NLW_inst_TRACE_jump_hit_UNCONNECTED;
  wire NLW_inst_TRACE_jump_taken_UNCONNECTED;
  wire NLW_inst_TRACE_mb_halted_UNCONNECTED;
  wire NLW_inst_TRACE_mem_piperun_UNCONNECTED;
  wire NLW_inst_TRACE_of_piperun_UNCONNECTED;
  wire NLW_inst_TRACE_reg_write_UNCONNECTED;
  wire NLW_inst_TRACE_valid_instr_UNCONNECTED;
  wire [31:0]NLW_inst_IO_address_UNCONNECTED;
  wire [3:0]NLW_inst_IO_byte_enable_UNCONNECTED;
  wire [0:31]NLW_inst_TRACE_data_address_UNCONNECTED;
  wire [0:3]NLW_inst_TRACE_data_byte_enable_UNCONNECTED;
  wire [0:31]NLW_inst_TRACE_data_write_value_UNCONNECTED;
  wire [0:4]NLW_inst_TRACE_exception_kind_UNCONNECTED;
  wire [0:31]NLW_inst_TRACE_instruction_UNCONNECTED;
  wire [0:14]NLW_inst_TRACE_msr_reg_UNCONNECTED;
  wire [0:31]NLW_inst_TRACE_new_reg_value_UNCONNECTED;
  wire [0:31]NLW_inst_TRACE_pc_UNCONNECTED;
  wire [0:7]NLW_inst_TRACE_pid_reg_UNCONNECTED;
  wire [0:4]NLW_inst_TRACE_reg_addr_UNCONNECTED;

  assign IO_address[31] = \<const0> ;
  assign IO_address[30] = \<const0> ;
  assign IO_address[29:2] = \^IO_address [29:2];
  assign IO_address[1] = \<const0> ;
  assign IO_address[0] = \<const0> ;
  assign IO_byte_enable[3] = \<const0> ;
  assign IO_byte_enable[2] = \<const0> ;
  assign IO_byte_enable[1] = \<const0> ;
  assign IO_byte_enable[0] = \<const0> ;
  assign IO_read_strobe = \<const0> ;
  assign TRACE_data_access = \<const0> ;
  assign TRACE_data_address[0] = \<const0> ;
  assign TRACE_data_address[1] = \<const0> ;
  assign TRACE_data_address[2] = \<const0> ;
  assign TRACE_data_address[3] = \<const0> ;
  assign TRACE_data_address[4] = \<const0> ;
  assign TRACE_data_address[5] = \<const0> ;
  assign TRACE_data_address[6] = \<const0> ;
  assign TRACE_data_address[7] = \<const0> ;
  assign TRACE_data_address[8] = \<const0> ;
  assign TRACE_data_address[9] = \<const0> ;
  assign TRACE_data_address[10] = \<const0> ;
  assign TRACE_data_address[11] = \<const0> ;
  assign TRACE_data_address[12] = \<const0> ;
  assign TRACE_data_address[13] = \<const0> ;
  assign TRACE_data_address[14] = \<const0> ;
  assign TRACE_data_address[15] = \<const0> ;
  assign TRACE_data_address[16] = \<const0> ;
  assign TRACE_data_address[17] = \<const0> ;
  assign TRACE_data_address[18] = \<const0> ;
  assign TRACE_data_address[19] = \<const0> ;
  assign TRACE_data_address[20] = \<const0> ;
  assign TRACE_data_address[21] = \<const0> ;
  assign TRACE_data_address[22] = \<const0> ;
  assign TRACE_data_address[23] = \<const0> ;
  assign TRACE_data_address[24] = \<const0> ;
  assign TRACE_data_address[25] = \<const0> ;
  assign TRACE_data_address[26] = \<const0> ;
  assign TRACE_data_address[27] = \<const0> ;
  assign TRACE_data_address[28] = \<const0> ;
  assign TRACE_data_address[29] = \<const0> ;
  assign TRACE_data_address[30] = \<const0> ;
  assign TRACE_data_address[31] = \<const0> ;
  assign TRACE_data_byte_enable[0] = \<const0> ;
  assign TRACE_data_byte_enable[1] = \<const0> ;
  assign TRACE_data_byte_enable[2] = \<const0> ;
  assign TRACE_data_byte_enable[3] = \<const0> ;
  assign TRACE_data_read = \<const0> ;
  assign TRACE_data_write = \<const0> ;
  assign TRACE_data_write_value[0] = \<const0> ;
  assign TRACE_data_write_value[1] = \<const0> ;
  assign TRACE_data_write_value[2] = \<const0> ;
  assign TRACE_data_write_value[3] = \<const0> ;
  assign TRACE_data_write_value[4] = \<const0> ;
  assign TRACE_data_write_value[5] = \<const0> ;
  assign TRACE_data_write_value[6] = \<const0> ;
  assign TRACE_data_write_value[7] = \<const0> ;
  assign TRACE_data_write_value[8] = \<const0> ;
  assign TRACE_data_write_value[9] = \<const0> ;
  assign TRACE_data_write_value[10] = \<const0> ;
  assign TRACE_data_write_value[11] = \<const0> ;
  assign TRACE_data_write_value[12] = \<const0> ;
  assign TRACE_data_write_value[13] = \<const0> ;
  assign TRACE_data_write_value[14] = \<const0> ;
  assign TRACE_data_write_value[15] = \<const0> ;
  assign TRACE_data_write_value[16] = \<const0> ;
  assign TRACE_data_write_value[17] = \<const0> ;
  assign TRACE_data_write_value[18] = \<const0> ;
  assign TRACE_data_write_value[19] = \<const0> ;
  assign TRACE_data_write_value[20] = \<const0> ;
  assign TRACE_data_write_value[21] = \<const0> ;
  assign TRACE_data_write_value[22] = \<const0> ;
  assign TRACE_data_write_value[23] = \<const0> ;
  assign TRACE_data_write_value[24] = \<const0> ;
  assign TRACE_data_write_value[25] = \<const0> ;
  assign TRACE_data_write_value[26] = \<const0> ;
  assign TRACE_data_write_value[27] = \<const0> ;
  assign TRACE_data_write_value[28] = \<const0> ;
  assign TRACE_data_write_value[29] = \<const0> ;
  assign TRACE_data_write_value[30] = \<const0> ;
  assign TRACE_data_write_value[31] = \<const0> ;
  assign TRACE_dcache_hit = \<const0> ;
  assign TRACE_dcache_rdy = \<const0> ;
  assign TRACE_dcache_read = \<const0> ;
  assign TRACE_dcache_req = \<const0> ;
  assign TRACE_delay_slot = \<const0> ;
  assign TRACE_ex_piperun = \<const0> ;
  assign TRACE_exception_kind[0] = \<const0> ;
  assign TRACE_exception_kind[1] = \<const0> ;
  assign TRACE_exception_kind[2] = \<const0> ;
  assign TRACE_exception_kind[3] = \<const0> ;
  assign TRACE_exception_kind[4] = \<const0> ;
  assign TRACE_exception_taken = \<const0> ;
  assign TRACE_icache_hit = \<const0> ;
  assign TRACE_icache_rdy = \<const0> ;
  assign TRACE_icache_req = \<const0> ;
  assign TRACE_instruction[0] = \<const0> ;
  assign TRACE_instruction[1] = \<const0> ;
  assign TRACE_instruction[2] = \<const0> ;
  assign TRACE_instruction[3] = \<const0> ;
  assign TRACE_instruction[4] = \<const0> ;
  assign TRACE_instruction[5] = \<const0> ;
  assign TRACE_instruction[6] = \<const0> ;
  assign TRACE_instruction[7] = \<const0> ;
  assign TRACE_instruction[8] = \<const0> ;
  assign TRACE_instruction[9] = \<const0> ;
  assign TRACE_instruction[10] = \<const0> ;
  assign TRACE_instruction[11] = \<const0> ;
  assign TRACE_instruction[12] = \<const0> ;
  assign TRACE_instruction[13] = \<const0> ;
  assign TRACE_instruction[14] = \<const0> ;
  assign TRACE_instruction[15] = \<const0> ;
  assign TRACE_instruction[16] = \<const0> ;
  assign TRACE_instruction[17] = \<const0> ;
  assign TRACE_instruction[18] = \<const0> ;
  assign TRACE_instruction[19] = \<const0> ;
  assign TRACE_instruction[20] = \<const0> ;
  assign TRACE_instruction[21] = \<const0> ;
  assign TRACE_instruction[22] = \<const0> ;
  assign TRACE_instruction[23] = \<const0> ;
  assign TRACE_instruction[24] = \<const0> ;
  assign TRACE_instruction[25] = \<const0> ;
  assign TRACE_instruction[26] = \<const0> ;
  assign TRACE_instruction[27] = \<const0> ;
  assign TRACE_instruction[28] = \<const0> ;
  assign TRACE_instruction[29] = \<const0> ;
  assign TRACE_instruction[30] = \<const0> ;
  assign TRACE_instruction[31] = \<const0> ;
  assign TRACE_jump_hit = \<const0> ;
  assign TRACE_jump_taken = \<const0> ;
  assign TRACE_mb_halted = \<const0> ;
  assign TRACE_mem_piperun = \<const0> ;
  assign TRACE_msr_reg[0] = \<const0> ;
  assign TRACE_msr_reg[1] = \<const0> ;
  assign TRACE_msr_reg[2] = \<const0> ;
  assign TRACE_msr_reg[3] = \<const0> ;
  assign TRACE_msr_reg[4] = \<const0> ;
  assign TRACE_msr_reg[5] = \<const0> ;
  assign TRACE_msr_reg[6] = \<const0> ;
  assign TRACE_msr_reg[7] = \<const0> ;
  assign TRACE_msr_reg[8] = \<const0> ;
  assign TRACE_msr_reg[9] = \<const0> ;
  assign TRACE_msr_reg[10] = \<const0> ;
  assign TRACE_msr_reg[11] = \<const0> ;
  assign TRACE_msr_reg[12] = \<const0> ;
  assign TRACE_msr_reg[13] = \<const0> ;
  assign TRACE_msr_reg[14] = \<const0> ;
  assign TRACE_new_reg_value[0] = \<const0> ;
  assign TRACE_new_reg_value[1] = \<const0> ;
  assign TRACE_new_reg_value[2] = \<const0> ;
  assign TRACE_new_reg_value[3] = \<const0> ;
  assign TRACE_new_reg_value[4] = \<const0> ;
  assign TRACE_new_reg_value[5] = \<const0> ;
  assign TRACE_new_reg_value[6] = \<const0> ;
  assign TRACE_new_reg_value[7] = \<const0> ;
  assign TRACE_new_reg_value[8] = \<const0> ;
  assign TRACE_new_reg_value[9] = \<const0> ;
  assign TRACE_new_reg_value[10] = \<const0> ;
  assign TRACE_new_reg_value[11] = \<const0> ;
  assign TRACE_new_reg_value[12] = \<const0> ;
  assign TRACE_new_reg_value[13] = \<const0> ;
  assign TRACE_new_reg_value[14] = \<const0> ;
  assign TRACE_new_reg_value[15] = \<const0> ;
  assign TRACE_new_reg_value[16] = \<const0> ;
  assign TRACE_new_reg_value[17] = \<const0> ;
  assign TRACE_new_reg_value[18] = \<const0> ;
  assign TRACE_new_reg_value[19] = \<const0> ;
  assign TRACE_new_reg_value[20] = \<const0> ;
  assign TRACE_new_reg_value[21] = \<const0> ;
  assign TRACE_new_reg_value[22] = \<const0> ;
  assign TRACE_new_reg_value[23] = \<const0> ;
  assign TRACE_new_reg_value[24] = \<const0> ;
  assign TRACE_new_reg_value[25] = \<const0> ;
  assign TRACE_new_reg_value[26] = \<const0> ;
  assign TRACE_new_reg_value[27] = \<const0> ;
  assign TRACE_new_reg_value[28] = \<const0> ;
  assign TRACE_new_reg_value[29] = \<const0> ;
  assign TRACE_new_reg_value[30] = \<const0> ;
  assign TRACE_new_reg_value[31] = \<const0> ;
  assign TRACE_of_piperun = \<const0> ;
  assign TRACE_pc[0] = \<const0> ;
  assign TRACE_pc[1] = \<const0> ;
  assign TRACE_pc[2] = \<const0> ;
  assign TRACE_pc[3] = \<const0> ;
  assign TRACE_pc[4] = \<const0> ;
  assign TRACE_pc[5] = \<const0> ;
  assign TRACE_pc[6] = \<const0> ;
  assign TRACE_pc[7] = \<const0> ;
  assign TRACE_pc[8] = \<const0> ;
  assign TRACE_pc[9] = \<const0> ;
  assign TRACE_pc[10] = \<const0> ;
  assign TRACE_pc[11] = \<const0> ;
  assign TRACE_pc[12] = \<const0> ;
  assign TRACE_pc[13] = \<const0> ;
  assign TRACE_pc[14] = \<const0> ;
  assign TRACE_pc[15] = \<const0> ;
  assign TRACE_pc[16] = \<const0> ;
  assign TRACE_pc[17] = \<const0> ;
  assign TRACE_pc[18] = \<const0> ;
  assign TRACE_pc[19] = \<const0> ;
  assign TRACE_pc[20] = \<const0> ;
  assign TRACE_pc[21] = \<const0> ;
  assign TRACE_pc[22] = \<const0> ;
  assign TRACE_pc[23] = \<const0> ;
  assign TRACE_pc[24] = \<const0> ;
  assign TRACE_pc[25] = \<const0> ;
  assign TRACE_pc[26] = \<const0> ;
  assign TRACE_pc[27] = \<const0> ;
  assign TRACE_pc[28] = \<const0> ;
  assign TRACE_pc[29] = \<const0> ;
  assign TRACE_pc[30] = \<const0> ;
  assign TRACE_pc[31] = \<const0> ;
  assign TRACE_pid_reg[0] = \<const0> ;
  assign TRACE_pid_reg[1] = \<const0> ;
  assign TRACE_pid_reg[2] = \<const0> ;
  assign TRACE_pid_reg[3] = \<const0> ;
  assign TRACE_pid_reg[4] = \<const0> ;
  assign TRACE_pid_reg[5] = \<const0> ;
  assign TRACE_pid_reg[6] = \<const0> ;
  assign TRACE_pid_reg[7] = \<const0> ;
  assign TRACE_reg_addr[0] = \<const0> ;
  assign TRACE_reg_addr[1] = \<const0> ;
  assign TRACE_reg_addr[2] = \<const0> ;
  assign TRACE_reg_addr[3] = \<const0> ;
  assign TRACE_reg_addr[4] = \<const0> ;
  assign TRACE_reg_write = \<const0> ;
  assign TRACE_valid_instr = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* HW_HANDOFF = "ddr4_0_microblaze_mcs.hwdef" *) 
  ddr4_0_bd_9054 inst
       (.Clk(Clk),
        .IO_addr_strobe(IO_addr_strobe),
        .IO_address({NLW_inst_IO_address_UNCONNECTED[31:30],\^IO_address ,NLW_inst_IO_address_UNCONNECTED[1:0]}),
        .IO_byte_enable(NLW_inst_IO_byte_enable_UNCONNECTED[3:0]),
        .IO_read_data(IO_read_data),
        .IO_read_strobe(NLW_inst_IO_read_strobe_UNCONNECTED),
        .IO_ready(IO_ready),
        .IO_write_data(IO_write_data),
        .IO_write_strobe(IO_write_strobe),
        .Reset(Reset),
        .TRACE_data_access(NLW_inst_TRACE_data_access_UNCONNECTED),
        .TRACE_data_address(NLW_inst_TRACE_data_address_UNCONNECTED[0:31]),
        .TRACE_data_byte_enable(NLW_inst_TRACE_data_byte_enable_UNCONNECTED[0:3]),
        .TRACE_data_read(NLW_inst_TRACE_data_read_UNCONNECTED),
        .TRACE_data_write(NLW_inst_TRACE_data_write_UNCONNECTED),
        .TRACE_data_write_value(NLW_inst_TRACE_data_write_value_UNCONNECTED[0:31]),
        .TRACE_dcache_hit(NLW_inst_TRACE_dcache_hit_UNCONNECTED),
        .TRACE_dcache_rdy(NLW_inst_TRACE_dcache_rdy_UNCONNECTED),
        .TRACE_dcache_read(NLW_inst_TRACE_dcache_read_UNCONNECTED),
        .TRACE_dcache_req(NLW_inst_TRACE_dcache_req_UNCONNECTED),
        .TRACE_delay_slot(NLW_inst_TRACE_delay_slot_UNCONNECTED),
        .TRACE_ex_piperun(NLW_inst_TRACE_ex_piperun_UNCONNECTED),
        .TRACE_exception_kind(NLW_inst_TRACE_exception_kind_UNCONNECTED[0:4]),
        .TRACE_exception_taken(NLW_inst_TRACE_exception_taken_UNCONNECTED),
        .TRACE_icache_hit(NLW_inst_TRACE_icache_hit_UNCONNECTED),
        .TRACE_icache_rdy(NLW_inst_TRACE_icache_rdy_UNCONNECTED),
        .TRACE_icache_req(NLW_inst_TRACE_icache_req_UNCONNECTED),
        .TRACE_instruction(NLW_inst_TRACE_instruction_UNCONNECTED[0:31]),
        .TRACE_jump_hit(NLW_inst_TRACE_jump_hit_UNCONNECTED),
        .TRACE_jump_taken(NLW_inst_TRACE_jump_taken_UNCONNECTED),
        .TRACE_mb_halted(NLW_inst_TRACE_mb_halted_UNCONNECTED),
        .TRACE_mem_piperun(NLW_inst_TRACE_mem_piperun_UNCONNECTED),
        .TRACE_msr_reg(NLW_inst_TRACE_msr_reg_UNCONNECTED[0:14]),
        .TRACE_new_reg_value(NLW_inst_TRACE_new_reg_value_UNCONNECTED[0:31]),
        .TRACE_of_piperun(NLW_inst_TRACE_of_piperun_UNCONNECTED),
        .TRACE_pc(NLW_inst_TRACE_pc_UNCONNECTED[0:31]),
        .TRACE_pid_reg(NLW_inst_TRACE_pid_reg_UNCONNECTED[0:7]),
        .TRACE_reg_addr(NLW_inst_TRACE_reg_addr_UNCONNECTED[0:4]),
        .TRACE_reg_write(NLW_inst_TRACE_reg_write_UNCONNECTED),
        .TRACE_valid_instr(NLW_inst_TRACE_valid_instr_UNCONNECTED));
endmodule

(* CHECK_LICENSE_TYPE = "phy1,dummy_model,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* PROBE_PROHIBIT = "TRUE" *) 
(* dont_touch = "true" *) 
module ddr4_0_phy
   (sys_clk_p,
    sys_clk_n,
    mmcm_lock,
    pllGate,
    div_clk,
    div_clk_rst,
    riu_clk,
    riu_clk_rst,
    pll_lock,
    sys_clk_in,
    mmcm_clk_in,
    ddr4_act_n,
    ddr4_adr,
    ddr4_ba,
    ddr4_bg,
    ddr4_c,
    ddr4_cke,
    ddr4_odt,
    ddr4_cs_n,
    ddr4_ck_t,
    ddr4_ck_c,
    ddr4_reset_n,
    ddr4_dm_dbi_n,
    ddr4_dq,
    ddr4_dqs_c,
    ddr4_dqs_t,
    mcal_CK_t,
    mcal_CK_c,
    mcal_ACT_n,
    mcal_CAS_n,
    mcal_RAS_n,
    mcal_WE_n,
    mcal_ADR,
    mcal_BA,
    mcal_BG,
    mcal_C,
    mcal_CKE,
    mcal_CS_n,
    mcal_ODT,
    mcal_PAR,
    ch0_mcal_DMOut_n,
    ch0_mcal_DQOut,
    ch0_mcal_DQSOut,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_odt_upp,
    ch0_mcal_clb2phy_odt_low,
    ch0_mcal_clb2phy_t_b_low,
    ch0_mcal_clb2phy_t_b_upp,
    mcal_rd_vref_value,
    ch1_mcal_DMOut_n,
    ch1_mcal_DQOut,
    ch1_mcal_DQSOut,
    ch1_mcal_clb2phy_rden_upp,
    ch1_mcal_clb2phy_rden_low,
    ch1_mcal_clb2phy_wrcs0_upp,
    ch1_mcal_clb2phy_wrcs1_upp,
    ch1_mcal_clb2phy_wrcs0_low,
    ch1_mcal_clb2phy_wrcs1_low,
    ch1_mcal_clb2phy_rdcs0_upp,
    ch1_mcal_clb2phy_rdcs1_upp,
    ch1_mcal_clb2phy_rdcs0_low,
    ch1_mcal_clb2phy_rdcs1_low,
    ch1_mcal_clb2phy_odt_upp,
    ch1_mcal_clb2phy_odt_low,
    ch1_mcal_clb2phy_t_b_low,
    ch1_mcal_clb2phy_t_b_upp,
    ch0_mcal_clb2phy_fifo_rden,
    ch1_mcal_clb2phy_fifo_rden,
    mcal_DMIn_n,
    mcal_DQIn,
    phy_ready_riuclk,
    bisc_complete_riuclk,
    phy2clb_rd_dq_bits,
    bisc_byte,
    cal_RESET_n,
    en_vtc_riuclk,
    ub_rst_out_riuclk,
    riu2clb_vld_read_data,
    riu_nibble_8,
    riu_addr_cal,
    riu2clb_valid_riuclk,
    io_addr_strobe_clb2riu_riuclk,
    io_address_riuclk,
    io_write_data_riuclk,
    io_write_strobe_riuclk,
    phy2clb_fixdly_rdy_low_riuclk,
    phy2clb_fixdly_rdy_upp_riuclk,
    phy2clb_phy_rdy_upp_riuclk,
    phy2clb_phy_rdy_low_riuclk,
    dbg_bus);
  input sys_clk_p;
  input sys_clk_n;
  input mmcm_lock;
  input pllGate;
  input div_clk;
  input div_clk_rst;
  input riu_clk;
  input riu_clk_rst;
  output pll_lock;
  output sys_clk_in;
  output mmcm_clk_in;
  output ddr4_act_n;
  output [16:0]ddr4_adr;
  output [1:0]ddr4_ba;
  output [0:0]ddr4_bg;
  output [0:0]ddr4_c;
  output [0:0]ddr4_cke;
  output [0:0]ddr4_odt;
  output [0:0]ddr4_cs_n;
  output [0:0]ddr4_ck_t;
  output [0:0]ddr4_ck_c;
  output ddr4_reset_n;
  inout [7:0]ddr4_dm_dbi_n;
  inout [63:0]ddr4_dq;
  inout [7:0]ddr4_dqs_c;
  inout [7:0]ddr4_dqs_t;
  input [7:0]mcal_CK_t;
  input [7:0]mcal_CK_c;
  input [7:0]mcal_ACT_n;
  input [7:0]mcal_CAS_n;
  input [7:0]mcal_RAS_n;
  input [7:0]mcal_WE_n;
  input [135:0]mcal_ADR;
  input [15:0]mcal_BA;
  input [7:0]mcal_BG;
  input [7:0]mcal_C;
  input [7:0]mcal_CKE;
  input [7:0]mcal_CS_n;
  input [7:0]mcal_ODT;
  input [7:0]mcal_PAR;
  input [63:0]ch0_mcal_DMOut_n;
  input [511:0]ch0_mcal_DQOut;
  input [7:0]ch0_mcal_DQSOut;
  input [31:0]ch0_mcal_clb2phy_rden_upp;
  input [31:0]ch0_mcal_clb2phy_rden_low;
  input [31:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [31:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [31:0]ch0_mcal_clb2phy_wrcs0_low;
  input [31:0]ch0_mcal_clb2phy_wrcs1_low;
  input [31:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [31:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [31:0]ch0_mcal_clb2phy_rdcs0_low;
  input [31:0]ch0_mcal_clb2phy_rdcs1_low;
  input [55:0]ch0_mcal_clb2phy_odt_upp;
  input [55:0]ch0_mcal_clb2phy_odt_low;
  input [31:0]ch0_mcal_clb2phy_t_b_low;
  input [31:0]ch0_mcal_clb2phy_t_b_upp;
  input [55:0]mcal_rd_vref_value;
  input [63:0]ch1_mcal_DMOut_n;
  input [511:0]ch1_mcal_DQOut;
  input [7:0]ch1_mcal_DQSOut;
  input [31:0]ch1_mcal_clb2phy_rden_upp;
  input [31:0]ch1_mcal_clb2phy_rden_low;
  input [31:0]ch1_mcal_clb2phy_wrcs0_upp;
  input [31:0]ch1_mcal_clb2phy_wrcs1_upp;
  input [31:0]ch1_mcal_clb2phy_wrcs0_low;
  input [31:0]ch1_mcal_clb2phy_wrcs1_low;
  input [31:0]ch1_mcal_clb2phy_rdcs0_upp;
  input [31:0]ch1_mcal_clb2phy_rdcs1_upp;
  input [31:0]ch1_mcal_clb2phy_rdcs0_low;
  input [31:0]ch1_mcal_clb2phy_rdcs1_low;
  input [55:0]ch1_mcal_clb2phy_odt_upp;
  input [55:0]ch1_mcal_clb2phy_odt_low;
  input [31:0]ch1_mcal_clb2phy_t_b_low;
  input [31:0]ch1_mcal_clb2phy_t_b_upp;
  input [103:0]ch0_mcal_clb2phy_fifo_rden;
  input [103:0]ch1_mcal_clb2phy_fifo_rden;
  output [63:0]mcal_DMIn_n;
  output [511:0]mcal_DQIn;
  output phy_ready_riuclk;
  output bisc_complete_riuclk;
  output [7:0]phy2clb_rd_dq_bits;
  input [8:0]bisc_byte;
  input [7:0]cal_RESET_n;
  input en_vtc_riuclk;
  input ub_rst_out_riuclk;
  output [15:0]riu2clb_vld_read_data;
  output [7:0]riu_nibble_8;
  output [5:0]riu_addr_cal;
  output [19:0]riu2clb_valid_riuclk;
  input io_addr_strobe_clb2riu_riuclk;
  input [31:0]io_address_riuclk;
  input [31:0]io_write_data_riuclk;
  input io_write_strobe_riuclk;
  output [19:0]phy2clb_fixdly_rdy_low_riuclk;
  output [19:0]phy2clb_fixdly_rdy_upp_riuclk;
  output [19:0]phy2clb_phy_rdy_upp_riuclk;
  output [19:0]phy2clb_phy_rdy_low_riuclk;
  output [511:0]dbg_bus;

  wire \<const0> ;
  wire \<const1> ;
  wire bisc_complete_riuclk;
  wire [7:0]cal_RESET_n;
  wire [63:0]ch0_mcal_DMOut_n;
  wire [511:0]ch0_mcal_DQOut;
  wire [7:0]ch0_mcal_DQSOut;
  wire [103:0]ch0_mcal_clb2phy_fifo_rden;
  wire [31:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [31:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [31:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [31:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [31:0]ch0_mcal_clb2phy_rden_low;
  wire [31:0]ch0_mcal_clb2phy_rden_upp;
  wire [31:0]ch0_mcal_clb2phy_t_b_low;
  wire [31:0]ch0_mcal_clb2phy_t_b_upp;
  wire [31:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [31:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [31:0]ch0_mcal_clb2phy_wrcs1_low;
  wire [31:0]ch0_mcal_clb2phy_wrcs1_upp;
  wire ddr4_act_n;
  wire [16:0]ddr4_adr;
  wire [1:0]ddr4_ba;
  wire [0:0]ddr4_bg;
  wire [0:0]ddr4_ck_c;
  wire [0:0]ddr4_ck_t;
  wire [0:0]ddr4_cke;
  wire [0:0]ddr4_cs_n;
  wire [7:0]ddr4_dm_dbi_n;
  wire [63:0]ddr4_dq;
  wire [7:0]ddr4_dqs_c;
  wire [7:0]ddr4_dqs_t;
  wire [0:0]ddr4_odt;
  wire ddr4_reset_n;
  wire div_clk;
  wire div_clk_rst;
  wire en_vtc_riuclk;
  wire inst_n_13;
  wire inst_n_14;
  wire inst_n_15;
  wire inst_n_16;
  wire inst_n_17;
  wire inst_n_18;
  wire inst_n_19;
  wire inst_n_20;
  wire inst_n_21;
  wire inst_n_22;
  wire inst_n_23;
  wire inst_n_24;
  wire inst_n_25;
  wire inst_n_26;
  wire inst_n_27;
  wire inst_n_28;
  wire inst_n_29;
  wire io_addr_strobe_clb2riu_riuclk;
  wire [31:0]io_address_riuclk;
  wire [31:0]io_write_data_riuclk;
  wire io_write_strobe_riuclk;
  wire [7:0]mcal_ACT_n;
  wire [135:0]mcal_ADR;
  wire [15:0]mcal_BA;
  wire [7:0]mcal_BG;
  wire [7:0]mcal_CKE;
  wire [7:0]mcal_CK_t;
  wire [7:0]mcal_CS_n;
  wire [63:0]mcal_DMIn_n;
  wire [511:0]mcal_DQIn;
  wire [7:0]mcal_ODT;
  wire [55:0]mcal_rd_vref_value;
  wire mmcm_clk_in;
  wire mmcm_lock;
  wire [9:0]\^phy2clb_fixdly_rdy_low_riuclk ;
  wire [9:0]\^phy2clb_fixdly_rdy_upp_riuclk ;
  wire [9:0]\^phy2clb_phy_rdy_low_riuclk ;
  wire [9:0]\^phy2clb_phy_rdy_upp_riuclk ;
  wire phy_ready_riuclk;
  wire pllGate;
  wire pll_lock;
  wire [9:0]\^riu2clb_valid_riuclk ;
  wire [15:0]riu2clb_vld_read_data;
  wire [5:0]riu_addr_cal;
  wire riu_clk;
  wire riu_clk_rst;
  wire [7:0]\^riu_nibble_8 ;
  wire \riu_nibble_8[7]_INST_0_i_18_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_4_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_6_n_0 ;
  wire sys_clk_in;
  wire sys_clk_n;
  wire sys_clk_p;
  wire ub_rst_out_riuclk;

  assign dbg_bus[511] = \<const0> ;
  assign dbg_bus[510] = \<const0> ;
  assign dbg_bus[509] = \<const0> ;
  assign dbg_bus[508] = \<const0> ;
  assign dbg_bus[507] = \<const0> ;
  assign dbg_bus[506] = \<const0> ;
  assign dbg_bus[505] = \<const0> ;
  assign dbg_bus[504] = \<const0> ;
  assign dbg_bus[503] = \<const0> ;
  assign dbg_bus[502] = \<const0> ;
  assign dbg_bus[501] = \<const0> ;
  assign dbg_bus[500] = \<const0> ;
  assign dbg_bus[499] = \<const0> ;
  assign dbg_bus[498] = \<const0> ;
  assign dbg_bus[497] = \<const0> ;
  assign dbg_bus[496] = \<const0> ;
  assign dbg_bus[495] = \<const0> ;
  assign dbg_bus[494] = \<const0> ;
  assign dbg_bus[493] = \<const0> ;
  assign dbg_bus[492] = \<const0> ;
  assign dbg_bus[491] = \<const0> ;
  assign dbg_bus[490] = \<const0> ;
  assign dbg_bus[489] = \<const0> ;
  assign dbg_bus[488] = \<const0> ;
  assign dbg_bus[487] = \<const0> ;
  assign dbg_bus[486] = \<const0> ;
  assign dbg_bus[485] = \<const0> ;
  assign dbg_bus[484] = \<const0> ;
  assign dbg_bus[483] = \<const0> ;
  assign dbg_bus[482] = \<const0> ;
  assign dbg_bus[481] = \<const0> ;
  assign dbg_bus[480] = \<const0> ;
  assign dbg_bus[479] = \<const0> ;
  assign dbg_bus[478] = \<const0> ;
  assign dbg_bus[477] = \<const0> ;
  assign dbg_bus[476] = \<const0> ;
  assign dbg_bus[475] = \<const0> ;
  assign dbg_bus[474] = \<const0> ;
  assign dbg_bus[473] = \<const0> ;
  assign dbg_bus[472] = \<const0> ;
  assign dbg_bus[471] = \<const0> ;
  assign dbg_bus[470] = \<const0> ;
  assign dbg_bus[469] = \<const0> ;
  assign dbg_bus[468] = \<const0> ;
  assign dbg_bus[467] = \<const0> ;
  assign dbg_bus[466] = \<const0> ;
  assign dbg_bus[465] = \<const0> ;
  assign dbg_bus[464] = \<const0> ;
  assign dbg_bus[463] = \<const0> ;
  assign dbg_bus[462] = \<const0> ;
  assign dbg_bus[461] = \<const0> ;
  assign dbg_bus[460] = \<const0> ;
  assign dbg_bus[459] = \<const0> ;
  assign dbg_bus[458] = \<const0> ;
  assign dbg_bus[457] = \<const0> ;
  assign dbg_bus[456] = \<const0> ;
  assign dbg_bus[455] = \<const0> ;
  assign dbg_bus[454] = \<const0> ;
  assign dbg_bus[453] = \<const0> ;
  assign dbg_bus[452] = \<const0> ;
  assign dbg_bus[451] = \<const0> ;
  assign dbg_bus[450] = \<const0> ;
  assign dbg_bus[449] = \<const0> ;
  assign dbg_bus[448] = \<const0> ;
  assign dbg_bus[447] = \<const0> ;
  assign dbg_bus[446] = \<const0> ;
  assign dbg_bus[445] = \<const0> ;
  assign dbg_bus[444] = \<const0> ;
  assign dbg_bus[443] = \<const0> ;
  assign dbg_bus[442] = \<const0> ;
  assign dbg_bus[441] = \<const0> ;
  assign dbg_bus[440] = \<const0> ;
  assign dbg_bus[439] = \<const0> ;
  assign dbg_bus[438] = \<const0> ;
  assign dbg_bus[437] = \<const0> ;
  assign dbg_bus[436] = \<const0> ;
  assign dbg_bus[435] = \<const0> ;
  assign dbg_bus[434] = \<const0> ;
  assign dbg_bus[433] = \<const0> ;
  assign dbg_bus[432] = \<const0> ;
  assign dbg_bus[431] = \<const0> ;
  assign dbg_bus[430] = \<const0> ;
  assign dbg_bus[429] = \<const0> ;
  assign dbg_bus[428] = \<const0> ;
  assign dbg_bus[427] = \<const0> ;
  assign dbg_bus[426] = \<const0> ;
  assign dbg_bus[425] = \<const0> ;
  assign dbg_bus[424] = \<const0> ;
  assign dbg_bus[423] = \<const0> ;
  assign dbg_bus[422] = \<const0> ;
  assign dbg_bus[421] = \<const0> ;
  assign dbg_bus[420] = \<const0> ;
  assign dbg_bus[419] = \<const0> ;
  assign dbg_bus[418] = \<const0> ;
  assign dbg_bus[417] = \<const0> ;
  assign dbg_bus[416] = \<const0> ;
  assign dbg_bus[415] = \<const0> ;
  assign dbg_bus[414] = \<const0> ;
  assign dbg_bus[413] = \<const0> ;
  assign dbg_bus[412] = \<const0> ;
  assign dbg_bus[411] = \<const0> ;
  assign dbg_bus[410] = \<const0> ;
  assign dbg_bus[409] = \<const0> ;
  assign dbg_bus[408] = \<const0> ;
  assign dbg_bus[407] = \<const0> ;
  assign dbg_bus[406] = \<const0> ;
  assign dbg_bus[405] = \<const0> ;
  assign dbg_bus[404] = \<const0> ;
  assign dbg_bus[403] = \<const0> ;
  assign dbg_bus[402] = \<const0> ;
  assign dbg_bus[401] = \<const0> ;
  assign dbg_bus[400] = \<const0> ;
  assign dbg_bus[399] = \<const0> ;
  assign dbg_bus[398] = \<const0> ;
  assign dbg_bus[397] = \<const0> ;
  assign dbg_bus[396] = \<const0> ;
  assign dbg_bus[395] = \<const0> ;
  assign dbg_bus[394] = \<const0> ;
  assign dbg_bus[393] = \<const0> ;
  assign dbg_bus[392] = \<const0> ;
  assign dbg_bus[391] = \<const0> ;
  assign dbg_bus[390] = \<const0> ;
  assign dbg_bus[389] = \<const0> ;
  assign dbg_bus[388] = \<const0> ;
  assign dbg_bus[387] = \<const0> ;
  assign dbg_bus[386] = \<const0> ;
  assign dbg_bus[385] = \<const0> ;
  assign dbg_bus[384] = \<const0> ;
  assign dbg_bus[383] = \<const0> ;
  assign dbg_bus[382] = \<const0> ;
  assign dbg_bus[381] = \<const0> ;
  assign dbg_bus[380] = \<const0> ;
  assign dbg_bus[379] = \<const0> ;
  assign dbg_bus[378] = \<const0> ;
  assign dbg_bus[377] = \<const0> ;
  assign dbg_bus[376] = \<const0> ;
  assign dbg_bus[375] = \<const0> ;
  assign dbg_bus[374] = \<const0> ;
  assign dbg_bus[373] = \<const0> ;
  assign dbg_bus[372] = \<const0> ;
  assign dbg_bus[371] = \<const0> ;
  assign dbg_bus[370] = \<const0> ;
  assign dbg_bus[369] = \<const0> ;
  assign dbg_bus[368] = \<const0> ;
  assign dbg_bus[367] = \<const0> ;
  assign dbg_bus[366] = \<const0> ;
  assign dbg_bus[365] = \<const0> ;
  assign dbg_bus[364] = \<const0> ;
  assign dbg_bus[363] = \<const0> ;
  assign dbg_bus[362] = \<const0> ;
  assign dbg_bus[361] = \<const0> ;
  assign dbg_bus[360] = \<const0> ;
  assign dbg_bus[359] = \<const0> ;
  assign dbg_bus[358] = \<const0> ;
  assign dbg_bus[357] = \<const0> ;
  assign dbg_bus[356] = \<const0> ;
  assign dbg_bus[355] = \<const0> ;
  assign dbg_bus[354] = \<const0> ;
  assign dbg_bus[353] = \<const0> ;
  assign dbg_bus[352] = \<const0> ;
  assign dbg_bus[351] = \<const0> ;
  assign dbg_bus[350] = \<const0> ;
  assign dbg_bus[349] = \<const0> ;
  assign dbg_bus[348] = \<const0> ;
  assign dbg_bus[347] = \<const0> ;
  assign dbg_bus[346] = \<const0> ;
  assign dbg_bus[345] = \<const0> ;
  assign dbg_bus[344] = \<const0> ;
  assign dbg_bus[343] = \<const0> ;
  assign dbg_bus[342] = \<const0> ;
  assign dbg_bus[341] = \<const0> ;
  assign dbg_bus[340] = \<const0> ;
  assign dbg_bus[339] = \<const0> ;
  assign dbg_bus[338] = \<const0> ;
  assign dbg_bus[337] = \<const0> ;
  assign dbg_bus[336] = \<const0> ;
  assign dbg_bus[335] = \<const0> ;
  assign dbg_bus[334] = \<const0> ;
  assign dbg_bus[333] = \<const0> ;
  assign dbg_bus[332] = \<const0> ;
  assign dbg_bus[331] = \<const0> ;
  assign dbg_bus[330] = \<const0> ;
  assign dbg_bus[329] = \<const0> ;
  assign dbg_bus[328] = \<const0> ;
  assign dbg_bus[327] = \<const0> ;
  assign dbg_bus[326] = \<const0> ;
  assign dbg_bus[325] = \<const0> ;
  assign dbg_bus[324] = \<const0> ;
  assign dbg_bus[323] = \<const0> ;
  assign dbg_bus[322] = \<const0> ;
  assign dbg_bus[321] = \<const0> ;
  assign dbg_bus[320] = \<const0> ;
  assign dbg_bus[319] = \<const0> ;
  assign dbg_bus[318] = \<const0> ;
  assign dbg_bus[317] = \<const0> ;
  assign dbg_bus[316] = \<const0> ;
  assign dbg_bus[315] = \<const0> ;
  assign dbg_bus[314] = \<const0> ;
  assign dbg_bus[313] = \<const0> ;
  assign dbg_bus[312] = \<const0> ;
  assign dbg_bus[311] = \<const0> ;
  assign dbg_bus[310] = \<const0> ;
  assign dbg_bus[309] = \<const0> ;
  assign dbg_bus[308] = \<const0> ;
  assign dbg_bus[307] = \<const0> ;
  assign dbg_bus[306] = \<const0> ;
  assign dbg_bus[305] = \<const0> ;
  assign dbg_bus[304] = \<const0> ;
  assign dbg_bus[303] = \<const0> ;
  assign dbg_bus[302] = \<const0> ;
  assign dbg_bus[301] = \<const0> ;
  assign dbg_bus[300] = \<const0> ;
  assign dbg_bus[299] = \<const0> ;
  assign dbg_bus[298] = \<const0> ;
  assign dbg_bus[297] = \<const0> ;
  assign dbg_bus[296] = \<const0> ;
  assign dbg_bus[295] = \<const0> ;
  assign dbg_bus[294] = \<const0> ;
  assign dbg_bus[293] = \<const0> ;
  assign dbg_bus[292] = \<const0> ;
  assign dbg_bus[291] = \<const0> ;
  assign dbg_bus[290] = \<const0> ;
  assign dbg_bus[289] = \<const0> ;
  assign dbg_bus[288] = \<const0> ;
  assign dbg_bus[287] = \<const0> ;
  assign dbg_bus[286] = \<const0> ;
  assign dbg_bus[285] = \<const0> ;
  assign dbg_bus[284] = \<const0> ;
  assign dbg_bus[283] = \<const0> ;
  assign dbg_bus[282] = \<const0> ;
  assign dbg_bus[281] = \<const0> ;
  assign dbg_bus[280] = \<const0> ;
  assign dbg_bus[279] = \<const0> ;
  assign dbg_bus[278] = \<const0> ;
  assign dbg_bus[277] = \<const0> ;
  assign dbg_bus[276] = \<const0> ;
  assign dbg_bus[275] = \<const0> ;
  assign dbg_bus[274] = \<const0> ;
  assign dbg_bus[273] = \<const0> ;
  assign dbg_bus[272] = \<const0> ;
  assign dbg_bus[271] = \<const0> ;
  assign dbg_bus[270] = \<const0> ;
  assign dbg_bus[269] = \<const0> ;
  assign dbg_bus[268] = \<const0> ;
  assign dbg_bus[267] = \<const0> ;
  assign dbg_bus[266] = \<const0> ;
  assign dbg_bus[265] = \<const0> ;
  assign dbg_bus[264] = \<const0> ;
  assign dbg_bus[263] = \<const0> ;
  assign dbg_bus[262] = \<const0> ;
  assign dbg_bus[261] = \<const0> ;
  assign dbg_bus[260] = \<const0> ;
  assign dbg_bus[259] = \<const0> ;
  assign dbg_bus[258] = \<const0> ;
  assign dbg_bus[257] = \<const0> ;
  assign dbg_bus[256] = \<const0> ;
  assign dbg_bus[255] = \<const0> ;
  assign dbg_bus[254] = \<const0> ;
  assign dbg_bus[253] = \<const0> ;
  assign dbg_bus[252] = \<const0> ;
  assign dbg_bus[251] = \<const0> ;
  assign dbg_bus[250] = \<const0> ;
  assign dbg_bus[249] = \<const0> ;
  assign dbg_bus[248] = \<const0> ;
  assign dbg_bus[247] = \<const0> ;
  assign dbg_bus[246] = \<const0> ;
  assign dbg_bus[245] = \<const0> ;
  assign dbg_bus[244] = \<const0> ;
  assign dbg_bus[243] = \<const0> ;
  assign dbg_bus[242] = \<const0> ;
  assign dbg_bus[241] = \<const0> ;
  assign dbg_bus[240] = \<const0> ;
  assign dbg_bus[239] = \<const0> ;
  assign dbg_bus[238] = \<const0> ;
  assign dbg_bus[237] = \<const0> ;
  assign dbg_bus[236] = \<const0> ;
  assign dbg_bus[235] = \<const0> ;
  assign dbg_bus[234] = \<const0> ;
  assign dbg_bus[233] = \<const0> ;
  assign dbg_bus[232] = \<const0> ;
  assign dbg_bus[231] = \<const0> ;
  assign dbg_bus[230] = \<const0> ;
  assign dbg_bus[229] = \<const0> ;
  assign dbg_bus[228] = \<const0> ;
  assign dbg_bus[227] = \<const0> ;
  assign dbg_bus[226] = \<const0> ;
  assign dbg_bus[225] = \<const0> ;
  assign dbg_bus[224] = \<const0> ;
  assign dbg_bus[223] = \<const0> ;
  assign dbg_bus[222] = \<const0> ;
  assign dbg_bus[221] = \<const0> ;
  assign dbg_bus[220] = \<const0> ;
  assign dbg_bus[219] = \<const0> ;
  assign dbg_bus[218] = \<const0> ;
  assign dbg_bus[217] = \<const0> ;
  assign dbg_bus[216] = \<const0> ;
  assign dbg_bus[215] = \<const0> ;
  assign dbg_bus[214] = \<const0> ;
  assign dbg_bus[213] = \<const0> ;
  assign dbg_bus[212] = \<const0> ;
  assign dbg_bus[211] = \<const0> ;
  assign dbg_bus[210] = \<const0> ;
  assign dbg_bus[209] = \<const0> ;
  assign dbg_bus[208] = \<const0> ;
  assign dbg_bus[207] = \<const0> ;
  assign dbg_bus[206] = \<const0> ;
  assign dbg_bus[205] = \<const0> ;
  assign dbg_bus[204] = \<const0> ;
  assign dbg_bus[203] = \<const0> ;
  assign dbg_bus[202] = \<const0> ;
  assign dbg_bus[201] = \<const0> ;
  assign dbg_bus[200] = \<const0> ;
  assign dbg_bus[199] = \<const0> ;
  assign dbg_bus[198] = \<const0> ;
  assign dbg_bus[197] = \<const0> ;
  assign dbg_bus[196] = \<const0> ;
  assign dbg_bus[195] = \<const0> ;
  assign dbg_bus[194] = \<const0> ;
  assign dbg_bus[193] = \<const0> ;
  assign dbg_bus[192] = \<const0> ;
  assign dbg_bus[191] = \<const0> ;
  assign dbg_bus[190] = \<const0> ;
  assign dbg_bus[189] = \<const0> ;
  assign dbg_bus[188] = \<const0> ;
  assign dbg_bus[187] = \<const0> ;
  assign dbg_bus[186] = \<const0> ;
  assign dbg_bus[185] = \<const0> ;
  assign dbg_bus[184] = \<const0> ;
  assign dbg_bus[183] = \<const0> ;
  assign dbg_bus[182] = \<const0> ;
  assign dbg_bus[181] = \<const0> ;
  assign dbg_bus[180] = \<const0> ;
  assign dbg_bus[179] = \<const0> ;
  assign dbg_bus[178] = \<const0> ;
  assign dbg_bus[177] = \<const0> ;
  assign dbg_bus[176] = \<const0> ;
  assign dbg_bus[175] = \<const0> ;
  assign dbg_bus[174] = \<const0> ;
  assign dbg_bus[173] = \<const0> ;
  assign dbg_bus[172] = \<const0> ;
  assign dbg_bus[171] = \<const0> ;
  assign dbg_bus[170] = \<const0> ;
  assign dbg_bus[169] = \<const0> ;
  assign dbg_bus[168] = \<const0> ;
  assign dbg_bus[167] = \<const0> ;
  assign dbg_bus[166] = \<const0> ;
  assign dbg_bus[165] = \<const0> ;
  assign dbg_bus[164] = \<const0> ;
  assign dbg_bus[163] = \<const0> ;
  assign dbg_bus[162] = \<const0> ;
  assign dbg_bus[161] = \<const0> ;
  assign dbg_bus[160] = \<const0> ;
  assign dbg_bus[159] = \<const0> ;
  assign dbg_bus[158] = \<const0> ;
  assign dbg_bus[157] = \<const0> ;
  assign dbg_bus[156] = \<const0> ;
  assign dbg_bus[155] = \<const0> ;
  assign dbg_bus[154] = \<const0> ;
  assign dbg_bus[153] = \<const0> ;
  assign dbg_bus[152] = \<const0> ;
  assign dbg_bus[151] = \<const0> ;
  assign dbg_bus[150] = \<const0> ;
  assign dbg_bus[149] = \<const0> ;
  assign dbg_bus[148] = \<const0> ;
  assign dbg_bus[147] = \<const0> ;
  assign dbg_bus[146] = \<const0> ;
  assign dbg_bus[145] = \<const0> ;
  assign dbg_bus[144] = \<const0> ;
  assign dbg_bus[143] = \<const0> ;
  assign dbg_bus[142] = \<const0> ;
  assign dbg_bus[141] = \<const0> ;
  assign dbg_bus[140] = \<const0> ;
  assign dbg_bus[139] = \<const0> ;
  assign dbg_bus[138] = \<const0> ;
  assign dbg_bus[137] = \<const0> ;
  assign dbg_bus[136] = \<const0> ;
  assign dbg_bus[135] = \<const0> ;
  assign dbg_bus[134] = \<const0> ;
  assign dbg_bus[133] = \<const0> ;
  assign dbg_bus[132] = \<const0> ;
  assign dbg_bus[131] = \<const0> ;
  assign dbg_bus[130] = \<const0> ;
  assign dbg_bus[129] = \<const0> ;
  assign dbg_bus[128] = \<const0> ;
  assign dbg_bus[127] = \<const0> ;
  assign dbg_bus[126] = \<const0> ;
  assign dbg_bus[125] = \<const0> ;
  assign dbg_bus[124] = \<const0> ;
  assign dbg_bus[123] = \<const0> ;
  assign dbg_bus[122] = \<const0> ;
  assign dbg_bus[121] = \<const0> ;
  assign dbg_bus[120] = \<const0> ;
  assign dbg_bus[119] = \<const0> ;
  assign dbg_bus[118] = \<const0> ;
  assign dbg_bus[117] = \<const0> ;
  assign dbg_bus[116] = \<const0> ;
  assign dbg_bus[115] = \<const0> ;
  assign dbg_bus[114] = \<const0> ;
  assign dbg_bus[113] = \<const0> ;
  assign dbg_bus[112] = \<const0> ;
  assign dbg_bus[111] = \<const0> ;
  assign dbg_bus[110] = \<const0> ;
  assign dbg_bus[109] = \<const0> ;
  assign dbg_bus[108] = \<const0> ;
  assign dbg_bus[107] = \<const0> ;
  assign dbg_bus[106] = \<const0> ;
  assign dbg_bus[105] = \<const0> ;
  assign dbg_bus[104] = \<const0> ;
  assign dbg_bus[103] = \<const0> ;
  assign dbg_bus[102] = \<const0> ;
  assign dbg_bus[101] = \<const0> ;
  assign dbg_bus[100] = \<const0> ;
  assign dbg_bus[99] = \<const0> ;
  assign dbg_bus[98] = \<const0> ;
  assign dbg_bus[97] = \<const0> ;
  assign dbg_bus[96] = \<const0> ;
  assign dbg_bus[95] = \<const0> ;
  assign dbg_bus[94] = \<const0> ;
  assign dbg_bus[93] = \<const0> ;
  assign dbg_bus[92] = \<const0> ;
  assign dbg_bus[91] = \<const0> ;
  assign dbg_bus[90] = \<const0> ;
  assign dbg_bus[89] = \<const0> ;
  assign dbg_bus[88] = \<const0> ;
  assign dbg_bus[87] = \<const0> ;
  assign dbg_bus[86] = \<const0> ;
  assign dbg_bus[85] = \<const0> ;
  assign dbg_bus[84] = \<const0> ;
  assign dbg_bus[83] = \<const0> ;
  assign dbg_bus[82] = \<const0> ;
  assign dbg_bus[81] = \<const0> ;
  assign dbg_bus[80] = \<const0> ;
  assign dbg_bus[79] = \<const0> ;
  assign dbg_bus[78] = \<const0> ;
  assign dbg_bus[77] = \<const0> ;
  assign dbg_bus[76] = \<const0> ;
  assign dbg_bus[75] = \<const0> ;
  assign dbg_bus[74] = \<const0> ;
  assign dbg_bus[73] = \<const0> ;
  assign dbg_bus[72] = \<const0> ;
  assign dbg_bus[71] = \<const0> ;
  assign dbg_bus[70] = \<const0> ;
  assign dbg_bus[69] = \<const0> ;
  assign dbg_bus[68] = \<const0> ;
  assign dbg_bus[67] = \<const0> ;
  assign dbg_bus[66] = \<const0> ;
  assign dbg_bus[65] = \<const0> ;
  assign dbg_bus[64] = \<const0> ;
  assign dbg_bus[63] = \<const0> ;
  assign dbg_bus[62] = \<const0> ;
  assign dbg_bus[61] = \<const0> ;
  assign dbg_bus[60] = \<const0> ;
  assign dbg_bus[59] = \<const0> ;
  assign dbg_bus[58] = \<const0> ;
  assign dbg_bus[57] = \<const0> ;
  assign dbg_bus[56] = \<const0> ;
  assign dbg_bus[55] = \<const0> ;
  assign dbg_bus[54] = \<const0> ;
  assign dbg_bus[53] = \<const0> ;
  assign dbg_bus[52] = \<const0> ;
  assign dbg_bus[51] = \<const0> ;
  assign dbg_bus[50] = \<const0> ;
  assign dbg_bus[49] = \<const0> ;
  assign dbg_bus[48] = \<const0> ;
  assign dbg_bus[47] = \<const0> ;
  assign dbg_bus[46] = \<const0> ;
  assign dbg_bus[45] = \<const0> ;
  assign dbg_bus[44] = \<const0> ;
  assign dbg_bus[43] = \<const0> ;
  assign dbg_bus[42] = \<const0> ;
  assign dbg_bus[41] = \<const0> ;
  assign dbg_bus[40] = \<const0> ;
  assign dbg_bus[39] = \<const0> ;
  assign dbg_bus[38] = \<const0> ;
  assign dbg_bus[37] = \<const0> ;
  assign dbg_bus[36] = \<const0> ;
  assign dbg_bus[35] = \<const0> ;
  assign dbg_bus[34] = \<const0> ;
  assign dbg_bus[33] = \<const0> ;
  assign dbg_bus[32] = \<const0> ;
  assign dbg_bus[31] = \<const0> ;
  assign dbg_bus[30] = \<const0> ;
  assign dbg_bus[29] = \<const0> ;
  assign dbg_bus[28] = \<const0> ;
  assign dbg_bus[27] = \<const0> ;
  assign dbg_bus[26] = \<const0> ;
  assign dbg_bus[25] = \<const0> ;
  assign dbg_bus[24] = \<const0> ;
  assign dbg_bus[23] = \<const0> ;
  assign dbg_bus[22] = \<const0> ;
  assign dbg_bus[21] = \<const0> ;
  assign dbg_bus[20] = \<const0> ;
  assign dbg_bus[19] = \<const0> ;
  assign dbg_bus[18] = \<const0> ;
  assign dbg_bus[17] = \<const0> ;
  assign dbg_bus[16] = \<const0> ;
  assign dbg_bus[15] = \<const0> ;
  assign dbg_bus[14] = \<const0> ;
  assign dbg_bus[13] = \<const0> ;
  assign dbg_bus[12] = \<const0> ;
  assign dbg_bus[11] = \<const0> ;
  assign dbg_bus[10] = \<const0> ;
  assign dbg_bus[9] = \<const0> ;
  assign dbg_bus[8] = \<const0> ;
  assign dbg_bus[7] = \<const0> ;
  assign dbg_bus[6] = \<const0> ;
  assign dbg_bus[5] = \<const0> ;
  assign dbg_bus[4] = \<const0> ;
  assign dbg_bus[3] = \<const0> ;
  assign dbg_bus[2] = \<const0> ;
  assign dbg_bus[1] = \<const0> ;
  assign dbg_bus[0] = \<const0> ;
  assign ddr4_c[0] = \<const0> ;
  assign phy2clb_fixdly_rdy_low_riuclk[19] = \<const1> ;
  assign phy2clb_fixdly_rdy_low_riuclk[18] = \<const1> ;
  assign phy2clb_fixdly_rdy_low_riuclk[17] = \<const1> ;
  assign phy2clb_fixdly_rdy_low_riuclk[16] = \<const1> ;
  assign phy2clb_fixdly_rdy_low_riuclk[15] = \<const1> ;
  assign phy2clb_fixdly_rdy_low_riuclk[14] = \<const1> ;
  assign phy2clb_fixdly_rdy_low_riuclk[13] = \<const1> ;
  assign phy2clb_fixdly_rdy_low_riuclk[12] = \<const1> ;
  assign phy2clb_fixdly_rdy_low_riuclk[11] = \<const1> ;
  assign phy2clb_fixdly_rdy_low_riuclk[10] = \<const1> ;
  assign phy2clb_fixdly_rdy_low_riuclk[9:0] = \^phy2clb_fixdly_rdy_low_riuclk [9:0];
  assign phy2clb_fixdly_rdy_upp_riuclk[19] = \<const1> ;
  assign phy2clb_fixdly_rdy_upp_riuclk[18] = \<const1> ;
  assign phy2clb_fixdly_rdy_upp_riuclk[17] = \<const1> ;
  assign phy2clb_fixdly_rdy_upp_riuclk[16] = \<const1> ;
  assign phy2clb_fixdly_rdy_upp_riuclk[15] = \<const1> ;
  assign phy2clb_fixdly_rdy_upp_riuclk[14] = \<const1> ;
  assign phy2clb_fixdly_rdy_upp_riuclk[13] = \<const1> ;
  assign phy2clb_fixdly_rdy_upp_riuclk[12] = \<const1> ;
  assign phy2clb_fixdly_rdy_upp_riuclk[11] = \<const1> ;
  assign phy2clb_fixdly_rdy_upp_riuclk[10] = \<const1> ;
  assign phy2clb_fixdly_rdy_upp_riuclk[9:0] = \^phy2clb_fixdly_rdy_upp_riuclk [9:0];
  assign phy2clb_phy_rdy_low_riuclk[19] = \<const1> ;
  assign phy2clb_phy_rdy_low_riuclk[18] = \<const1> ;
  assign phy2clb_phy_rdy_low_riuclk[17] = \<const1> ;
  assign phy2clb_phy_rdy_low_riuclk[16] = \<const1> ;
  assign phy2clb_phy_rdy_low_riuclk[15] = \<const1> ;
  assign phy2clb_phy_rdy_low_riuclk[14] = \<const1> ;
  assign phy2clb_phy_rdy_low_riuclk[13] = \<const1> ;
  assign phy2clb_phy_rdy_low_riuclk[12] = \<const1> ;
  assign phy2clb_phy_rdy_low_riuclk[11] = \<const1> ;
  assign phy2clb_phy_rdy_low_riuclk[10] = \<const1> ;
  assign phy2clb_phy_rdy_low_riuclk[9:0] = \^phy2clb_phy_rdy_low_riuclk [9:0];
  assign phy2clb_phy_rdy_upp_riuclk[19] = \<const1> ;
  assign phy2clb_phy_rdy_upp_riuclk[18] = \<const1> ;
  assign phy2clb_phy_rdy_upp_riuclk[17] = \<const1> ;
  assign phy2clb_phy_rdy_upp_riuclk[16] = \<const1> ;
  assign phy2clb_phy_rdy_upp_riuclk[15] = \<const1> ;
  assign phy2clb_phy_rdy_upp_riuclk[14] = \<const1> ;
  assign phy2clb_phy_rdy_upp_riuclk[13] = \<const1> ;
  assign phy2clb_phy_rdy_upp_riuclk[12] = \<const1> ;
  assign phy2clb_phy_rdy_upp_riuclk[11] = \<const1> ;
  assign phy2clb_phy_rdy_upp_riuclk[10] = \<const1> ;
  assign phy2clb_phy_rdy_upp_riuclk[9:0] = \^phy2clb_phy_rdy_upp_riuclk [9:0];
  assign phy2clb_rd_dq_bits[7] = \<const0> ;
  assign phy2clb_rd_dq_bits[6] = \<const0> ;
  assign phy2clb_rd_dq_bits[5] = \<const0> ;
  assign phy2clb_rd_dq_bits[4] = \<const0> ;
  assign phy2clb_rd_dq_bits[3] = \<const0> ;
  assign phy2clb_rd_dq_bits[2] = \<const0> ;
  assign phy2clb_rd_dq_bits[1] = \<const0> ;
  assign phy2clb_rd_dq_bits[0] = \<const0> ;
  assign riu2clb_valid_riuclk[19] = \<const1> ;
  assign riu2clb_valid_riuclk[18] = \<const1> ;
  assign riu2clb_valid_riuclk[17] = \<const1> ;
  assign riu2clb_valid_riuclk[16] = \<const1> ;
  assign riu2clb_valid_riuclk[15] = \<const1> ;
  assign riu2clb_valid_riuclk[14] = \<const1> ;
  assign riu2clb_valid_riuclk[13] = \<const1> ;
  assign riu2clb_valid_riuclk[12] = \<const1> ;
  assign riu2clb_valid_riuclk[11] = \<const1> ;
  assign riu2clb_valid_riuclk[10] = \<const1> ;
  assign riu2clb_valid_riuclk[9:0] = \^riu2clb_valid_riuclk [9:0];
  assign riu_nibble_8[7:6] = \^riu_nibble_8 [7:6];
  assign riu_nibble_8[5] = \<const0> ;
  assign riu_nibble_8[4:0] = \^riu_nibble_8 [4:0];
  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
  ddr4_0_phy_ddr4 inst
       (.bisc_complete_riuclk(bisc_complete_riuclk),
        .cal_RESET_n(cal_RESET_n[0]),
        .ch0_mcal_DQOut(ch0_mcal_DQOut),
        .ch0_mcal_clb2phy_fifo_rden({ch0_mcal_clb2phy_fifo_rden[102:99],ch0_mcal_clb2phy_fifo_rden[97:93],ch0_mcal_clb2phy_fifo_rden[91],ch0_mcal_clb2phy_fifo_rden[89:86],ch0_mcal_clb2phy_fifo_rden[84:80],ch0_mcal_clb2phy_fifo_rden[78],ch0_mcal_clb2phy_fifo_rden[76:73],ch0_mcal_clb2phy_fifo_rden[71:67],ch0_mcal_clb2phy_fifo_rden[65],ch0_mcal_clb2phy_fifo_rden[63:60],ch0_mcal_clb2phy_fifo_rden[58:54],ch0_mcal_clb2phy_fifo_rden[52],ch0_mcal_clb2phy_fifo_rden[50:47],ch0_mcal_clb2phy_fifo_rden[45:41],ch0_mcal_clb2phy_fifo_rden[39],ch0_mcal_clb2phy_fifo_rden[37:34],ch0_mcal_clb2phy_fifo_rden[32:28],ch0_mcal_clb2phy_fifo_rden[26],ch0_mcal_clb2phy_fifo_rden[24:21],ch0_mcal_clb2phy_fifo_rden[19:13],ch0_mcal_clb2phy_fifo_rden[11:8],ch0_mcal_clb2phy_fifo_rden[6:0]}),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp),
        .clb2phy_wr_dq0({ch0_mcal_DMOut_n[63:8],mcal_ADR[79:72],mcal_ADR[7:0],ch0_mcal_DMOut_n[7:0]}),
        .clb2phy_wr_dq1({mcal_ACT_n,mcal_ADR[87:80],mcal_ADR[15:8],mcal_ODT}),
        .clb2phy_wr_dq6({ch0_mcal_DQSOut,mcal_ADR[127:120],mcal_CK_t}),
        .ddr4_reset_n(ddr4_reset_n),
        .div_clk(div_clk),
        .div_clk_rst(div_clk_rst),
        .en_vtc_riuclk(en_vtc_riuclk),
        .\genBuf[1].genblk1.OBUF ({ddr4_act_n,ddr4_cke,ddr4_cs_n,ddr4_bg,ddr4_ba,ddr4_adr[16:6],ddr4_ck_c,ddr4_ck_t,ddr4_adr[5:0],ddr4_odt}),
        .io_addr_strobe_clb2riu_riuclk(io_addr_strobe_clb2riu_riuclk),
        .io_address_riuclk(io_address_riuclk[27:0]),
        .\io_address_riuclk_reg[10] (inst_n_16),
        .\io_address_riuclk_reg[12] (inst_n_13),
        .\io_address_riuclk_reg[12]_0 (inst_n_27),
        .\io_address_riuclk_reg[14] (inst_n_14),
        .\io_address_riuclk_reg[14]_0 (inst_n_21),
        .\io_address_riuclk_reg[14]_1 (inst_n_28),
        .\io_address_riuclk_reg[16] (inst_n_20),
        .\io_address_riuclk_reg[16]_0 (inst_n_23),
        .\io_address_riuclk_reg[19] (inst_n_15),
        .\io_address_riuclk_reg[1] (inst_n_18),
        .\io_address_riuclk_reg[26] (inst_n_24),
        .\io_address_riuclk_reg[2] (inst_n_17),
        .\io_address_riuclk_reg[2]_0 (inst_n_29),
        .\io_address_riuclk_reg[3] (inst_n_25),
        .\io_address_riuclk_reg[4] (inst_n_26),
        .\io_address_riuclk_reg[5] (inst_n_22),
        .\io_address_riuclk_reg[9] (inst_n_19),
        .io_write_data_riuclk(io_write_data_riuclk[15:0]),
        .io_write_strobe_riuclk(io_write_strobe_riuclk),
        .iob_pin({ddr4_dq[63:60],ddr4_dqs_c[7],ddr4_dqs_t[7],ddr4_dq[59:56],ddr4_dm_dbi_n[7],ddr4_dq[55:52],ddr4_dqs_c[6],ddr4_dqs_t[6],ddr4_dq[51:48],ddr4_dm_dbi_n[6],ddr4_dq[47:44],ddr4_dqs_c[5],ddr4_dqs_t[5],ddr4_dq[43:40],ddr4_dm_dbi_n[5],ddr4_dq[39:36],ddr4_dqs_c[4],ddr4_dqs_t[4],ddr4_dq[35:32],ddr4_dm_dbi_n[4],ddr4_dq[31:28],ddr4_dqs_c[3],ddr4_dqs_t[3],ddr4_dq[27:24],ddr4_dm_dbi_n[3],ddr4_dq[23:20],ddr4_dqs_c[2],ddr4_dqs_t[2],ddr4_dq[19:16],ddr4_dm_dbi_n[2],ddr4_dq[15:12],ddr4_dqs_c[1],ddr4_dqs_t[1],ddr4_dq[11:8],ddr4_dm_dbi_n[1],ddr4_dq[7:4],ddr4_dqs_c[0],ddr4_dqs_t[0],ddr4_dq[3:0],ddr4_dm_dbi_n[0]}),
        .mcal_ADR({mcal_ADR[135:128],mcal_ADR[119:88],mcal_ADR[71:16]}),
        .mcal_BA(mcal_BA),
        .mcal_BG(mcal_BG),
        .mcal_CKE(mcal_CKE),
        .mcal_CS_n(mcal_CS_n),
        .mcal_DMIn_n(mcal_DMIn_n),
        .mcal_DQIn(mcal_DQIn),
        .mcal_rd_vref_value(mcal_rd_vref_value),
        .mmcm_clk_in(mmcm_clk_in),
        .mmcm_lock(mmcm_lock),
        .phy2clb_fixdly_rdy_low_riuclk(\^phy2clb_fixdly_rdy_low_riuclk ),
        .phy2clb_fixdly_rdy_upp_riuclk(\^phy2clb_fixdly_rdy_upp_riuclk ),
        .phy2clb_phy_rdy_low_riuclk(\^phy2clb_phy_rdy_low_riuclk ),
        .phy2clb_phy_rdy_upp_riuclk(\^phy2clb_phy_rdy_upp_riuclk ),
        .phy_ready_riuclk(phy_ready_riuclk),
        .pllGate(pllGate),
        .pll_lock(pll_lock),
        .riu2clb_valid_riuclk(\^riu2clb_valid_riuclk ),
        .riu2clb_vld_read_data(riu2clb_vld_read_data),
        .riu_addr_cal(riu_addr_cal),
        .riu_clk(riu_clk),
        .riu_clk_rst(riu_clk_rst),
        .riu_nibble_8({\^riu_nibble_8 [6],\^riu_nibble_8 [3:2],\^riu_nibble_8 [0]}),
        .sys_clk_in(sys_clk_in),
        .sys_clk_n(sys_clk_n),
        .sys_clk_p(sys_clk_p),
        .ub_rst_out_riuclk(ub_rst_out_riuclk));
  LUT1 #(
    .INIT(2'h1)) 
    \riu_nibble_8[1]_INST_0 
       (.I0(inst_n_13),
        .O(\^riu_nibble_8 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \riu_nibble_8[4]_INST_0 
       (.I0(inst_n_16),
        .O(\^riu_nibble_8 [4]));
  LUT6 #(
    .INIT(64'h0000000000000200)) 
    \riu_nibble_8[7]_INST_0 
       (.I0(inst_n_21),
        .I1(inst_n_20),
        .I2(inst_n_14),
        .I3(\riu_nibble_8[7]_INST_0_i_4_n_0 ),
        .I4(inst_n_23),
        .I5(\riu_nibble_8[7]_INST_0_i_6_n_0 ),
        .O(\^riu_nibble_8 [7]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFD)) 
    \riu_nibble_8[7]_INST_0_i_18 
       (.I0(inst_n_26),
        .I1(inst_n_17),
        .I2(inst_n_19),
        .I3(inst_n_28),
        .I4(inst_n_27),
        .I5(inst_n_15),
        .O(\riu_nibble_8[7]_INST_0_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFEFFFEEFFEF)) 
    \riu_nibble_8[7]_INST_0_i_4 
       (.I0(inst_n_24),
        .I1(io_address_riuclk[5]),
        .I2(io_address_riuclk[4]),
        .I3(io_address_riuclk[6]),
        .I4(io_address_riuclk[7]),
        .I5(inst_n_29),
        .O(\riu_nibble_8[7]_INST_0_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000004055555555)) 
    \riu_nibble_8[7]_INST_0_i_6 
       (.I0(inst_n_22),
        .I1(inst_n_25),
        .I2(inst_n_18),
        .I3(io_address_riuclk[12]),
        .I4(io_address_riuclk[15]),
        .I5(\riu_nibble_8[7]_INST_0_i_18_n_0 ),
        .O(\riu_nibble_8[7]_INST_0_i_6_n_0 ));
endmodule

module ddr4_0_phy_ddr4
   (ddr4_reset_n,
    phy_ready_riuclk,
    bisc_complete_riuclk,
    riu_addr_cal,
    riu_nibble_8,
    \io_address_riuclk_reg[12] ,
    \io_address_riuclk_reg[14] ,
    \io_address_riuclk_reg[19] ,
    \io_address_riuclk_reg[10] ,
    \io_address_riuclk_reg[2] ,
    \io_address_riuclk_reg[1] ,
    \io_address_riuclk_reg[9] ,
    \io_address_riuclk_reg[16] ,
    \io_address_riuclk_reg[14]_0 ,
    \io_address_riuclk_reg[5] ,
    \io_address_riuclk_reg[16]_0 ,
    \io_address_riuclk_reg[26] ,
    \io_address_riuclk_reg[3] ,
    \io_address_riuclk_reg[4] ,
    \io_address_riuclk_reg[12]_0 ,
    \io_address_riuclk_reg[14]_1 ,
    \io_address_riuclk_reg[2]_0 ,
    phy2clb_phy_rdy_low_riuclk,
    phy2clb_phy_rdy_upp_riuclk,
    phy2clb_fixdly_rdy_upp_riuclk,
    phy2clb_fixdly_rdy_low_riuclk,
    riu2clb_vld_read_data,
    sys_clk_in,
    mmcm_clk_in,
    pll_lock,
    \genBuf[1].genblk1.OBUF ,
    mcal_DMIn_n,
    mcal_DQIn,
    riu2clb_valid_riuclk,
    iob_pin,
    cal_RESET_n,
    riu_clk,
    div_clk_rst,
    div_clk,
    riu_clk_rst,
    io_addr_strobe_clb2riu_riuclk,
    io_write_strobe_riuclk,
    io_address_riuclk,
    io_write_data_riuclk,
    sys_clk_p,
    sys_clk_n,
    pllGate,
    ub_rst_out_riuclk,
    mmcm_lock,
    mcal_rd_vref_value,
    ch0_mcal_clb2phy_fifo_rden,
    clb2phy_wr_dq0,
    clb2phy_wr_dq1,
    ch0_mcal_DQOut,
    clb2phy_wr_dq6,
    en_vtc_riuclk,
    ch0_mcal_clb2phy_rdcs0_low,
    ch0_mcal_clb2phy_rdcs1_low,
    ch0_mcal_clb2phy_rden_low,
    ch0_mcal_clb2phy_wrcs0_low,
    ch0_mcal_clb2phy_wrcs1_low,
    ch0_mcal_clb2phy_t_b_low,
    ch0_mcal_clb2phy_rdcs0_upp,
    ch0_mcal_clb2phy_rdcs1_upp,
    ch0_mcal_clb2phy_rden_upp,
    ch0_mcal_clb2phy_wrcs0_upp,
    ch0_mcal_clb2phy_wrcs1_upp,
    ch0_mcal_clb2phy_t_b_upp,
    mcal_ADR,
    mcal_BA,
    mcal_BG,
    mcal_CS_n,
    mcal_CKE);
  output ddr4_reset_n;
  output phy_ready_riuclk;
  output bisc_complete_riuclk;
  output [5:0]riu_addr_cal;
  output [3:0]riu_nibble_8;
  output \io_address_riuclk_reg[12] ;
  output \io_address_riuclk_reg[14] ;
  output \io_address_riuclk_reg[19] ;
  output \io_address_riuclk_reg[10] ;
  output \io_address_riuclk_reg[2] ;
  output \io_address_riuclk_reg[1] ;
  output \io_address_riuclk_reg[9] ;
  output \io_address_riuclk_reg[16] ;
  output \io_address_riuclk_reg[14]_0 ;
  output \io_address_riuclk_reg[5] ;
  output \io_address_riuclk_reg[16]_0 ;
  output \io_address_riuclk_reg[26] ;
  output \io_address_riuclk_reg[3] ;
  output \io_address_riuclk_reg[4] ;
  output \io_address_riuclk_reg[12]_0 ;
  output \io_address_riuclk_reg[14]_1 ;
  output \io_address_riuclk_reg[2]_0 ;
  output [9:0]phy2clb_phy_rdy_low_riuclk;
  output [9:0]phy2clb_phy_rdy_upp_riuclk;
  output [9:0]phy2clb_fixdly_rdy_upp_riuclk;
  output [9:0]phy2clb_fixdly_rdy_low_riuclk;
  output [15:0]riu2clb_vld_read_data;
  output sys_clk_in;
  output mmcm_clk_in;
  output pll_lock;
  output [25:0]\genBuf[1].genblk1.OBUF ;
  output [63:0]mcal_DMIn_n;
  output [511:0]mcal_DQIn;
  output [9:0]riu2clb_valid_riuclk;
  inout [87:0]iob_pin;
  input [0:0]cal_RESET_n;
  input riu_clk;
  input div_clk_rst;
  input div_clk;
  input riu_clk_rst;
  input io_addr_strobe_clb2riu_riuclk;
  input io_write_strobe_riuclk;
  input [27:0]io_address_riuclk;
  input [15:0]io_write_data_riuclk;
  input sys_clk_p;
  input sys_clk_n;
  input pllGate;
  input ub_rst_out_riuclk;
  input mmcm_lock;
  input [55:0]mcal_rd_vref_value;
  input [81:0]ch0_mcal_clb2phy_fifo_rden;
  input [79:0]clb2phy_wr_dq0;
  input [31:0]clb2phy_wr_dq1;
  input [511:0]ch0_mcal_DQOut;
  input [23:0]clb2phy_wr_dq6;
  input en_vtc_riuclk;
  input [31:0]ch0_mcal_clb2phy_rdcs0_low;
  input [31:0]ch0_mcal_clb2phy_rdcs1_low;
  input [31:0]ch0_mcal_clb2phy_rden_low;
  input [31:0]ch0_mcal_clb2phy_wrcs0_low;
  input [31:0]ch0_mcal_clb2phy_wrcs1_low;
  input [31:0]ch0_mcal_clb2phy_t_b_low;
  input [31:0]ch0_mcal_clb2phy_rdcs0_upp;
  input [31:0]ch0_mcal_clb2phy_rdcs1_upp;
  input [31:0]ch0_mcal_clb2phy_rden_upp;
  input [31:0]ch0_mcal_clb2phy_wrcs0_upp;
  input [31:0]ch0_mcal_clb2phy_wrcs1_upp;
  input [31:0]ch0_mcal_clb2phy_t_b_upp;
  input [95:0]mcal_ADR;
  input [15:0]mcal_BA;
  input [7:0]mcal_BG;
  input [7:0]mcal_CS_n;
  input [7:0]mcal_CKE;

  wire bisc_complete_riuclk;
  wire bisc_complete_riuclk_i_2_n_0;
  wire bisc_complete_riuclk_i_3_n_0;
  wire bisc_complete_riuclk_i_4_n_0;
  wire [0:0]cal_RESET_n;
  wire [511:0]ch0_mcal_DQOut;
  wire [81:0]ch0_mcal_clb2phy_fifo_rden;
  wire [31:0]ch0_mcal_clb2phy_rdcs0_low;
  wire [31:0]ch0_mcal_clb2phy_rdcs0_upp;
  wire [31:0]ch0_mcal_clb2phy_rdcs1_low;
  wire [31:0]ch0_mcal_clb2phy_rdcs1_upp;
  wire [31:0]ch0_mcal_clb2phy_rden_low;
  wire [31:0]ch0_mcal_clb2phy_rden_upp;
  wire [31:0]ch0_mcal_clb2phy_t_b_low;
  wire [31:0]ch0_mcal_clb2phy_t_b_upp;
  wire [31:0]ch0_mcal_clb2phy_wrcs0_low;
  wire [31:0]ch0_mcal_clb2phy_wrcs0_upp;
  wire [31:0]ch0_mcal_clb2phy_wrcs1_low;
  wire [31:0]ch0_mcal_clb2phy_wrcs1_upp;
  (* DONT_TOUCH *) wire [3:0]clb2phy_t_b_addr;
  (* RTL_KEEP = "true" *) (* async_reg = "true" *) wire [1:0]clb2phy_t_b_addr_i;
  (* DONT_TOUCH *) wire clb2phy_t_b_addr_riuclk;
  wire clb2phy_t_b_addr_riuclk_reg0;
  wire [79:0]clb2phy_wr_dq0;
  wire [31:0]clb2phy_wr_dq1;
  wire [23:0]clb2phy_wr_dq6;
  wire [59:54]clb2riu_addr;
  wire [9:0]clb2riu_nibble_sel_low;
  wire [9:0]clb2riu_nibble_sel_upp;
  wire \clb2riu_nibble_sel_upp[9]_i_2_n_0 ;
  wire [159:144]clb2riu_wr_data;
  wire [9:0]clb2riu_wr_en;
  wire \clb2riu_wr_en[7]_i_2_n_0 ;
  wire \clb2riu_wr_en[9]_i_2_n_0 ;
  wire ddr4_reset_n;
  wire div_clk;
  wire div_clk_rst;
  (* RTL_KEEP = "true" *) wire div_clk_rst_r1;
  wire en_vtc_riuclk;
  wire extend_nibble_sel_riu_addr_0;
  wire extend_nibble_sel_riu_addr_0_i_10_n_0;
  wire extend_nibble_sel_riu_addr_0_i_11_n_0;
  wire extend_nibble_sel_riu_addr_0_i_12_n_0;
  wire extend_nibble_sel_riu_addr_0_i_13_n_0;
  wire extend_nibble_sel_riu_addr_0_i_14_n_0;
  wire extend_nibble_sel_riu_addr_0_i_15_n_0;
  wire extend_nibble_sel_riu_addr_0_i_16_n_0;
  wire extend_nibble_sel_riu_addr_0_i_17_n_0;
  wire extend_nibble_sel_riu_addr_0_i_18_n_0;
  wire extend_nibble_sel_riu_addr_0_i_19_n_0;
  wire extend_nibble_sel_riu_addr_0_i_1_n_0;
  wire extend_nibble_sel_riu_addr_0_i_20_n_0;
  wire extend_nibble_sel_riu_addr_0_i_2_n_0;
  wire extend_nibble_sel_riu_addr_0_i_3_n_0;
  wire extend_nibble_sel_riu_addr_0_i_4_n_0;
  wire extend_nibble_sel_riu_addr_0_i_5_n_0;
  wire extend_nibble_sel_riu_addr_0_i_6_n_0;
  wire extend_nibble_sel_riu_addr_0_i_7_n_0;
  wire extend_nibble_sel_riu_addr_0_i_8_n_0;
  wire extend_nibble_sel_riu_addr_0_i_9_n_0;
  wire [25:0]\genBuf[1].genblk1.OBUF ;
  wire io_addr_strobe_clb2riu_riuclk;
  wire [27:0]io_address_riuclk;
  wire \io_address_riuclk_reg[10] ;
  wire \io_address_riuclk_reg[12] ;
  wire \io_address_riuclk_reg[12]_0 ;
  wire \io_address_riuclk_reg[14] ;
  wire \io_address_riuclk_reg[14]_0 ;
  wire \io_address_riuclk_reg[14]_1 ;
  wire \io_address_riuclk_reg[16] ;
  wire \io_address_riuclk_reg[16]_0 ;
  wire \io_address_riuclk_reg[19] ;
  wire \io_address_riuclk_reg[1] ;
  wire \io_address_riuclk_reg[26] ;
  wire \io_address_riuclk_reg[2] ;
  wire \io_address_riuclk_reg[2]_0 ;
  wire \io_address_riuclk_reg[3] ;
  wire \io_address_riuclk_reg[4] ;
  wire \io_address_riuclk_reg[5] ;
  wire \io_address_riuclk_reg[9] ;
  wire [15:0]io_write_data_riuclk;
  wire io_write_strobe_riuclk;
  wire [128:0]iob2phy_d_in_byte;
  wire [87:0]iob_pin;
  wire [95:0]mcal_ADR;
  wire [15:0]mcal_BA;
  wire [7:0]mcal_BG;
  wire [7:0]mcal_CKE;
  wire [7:0]mcal_CS_n;
  wire [63:0]mcal_DMIn_n;
  wire [511:0]mcal_DQIn;
  wire [55:0]mcal_rd_vref_value;
  wire mmcm_clk_in;
  wire mmcm_lock;
  wire [9:0]p_11_out;
  wire [9:0]p_19_out;
  wire [9:0]p_9_out;
  wire [9:0]phy2clb_fixdly_rdy_low_in_riuclk;
  wire [9:0]phy2clb_fixdly_rdy_low_riuclk;
  wire [9:0]phy2clb_fixdly_rdy_upp_in_riuclk;
  wire [9:0]phy2clb_fixdly_rdy_upp_riuclk;
  wire [9:0]phy2clb_phy_rdy_low_in_riuclk;
  wire [9:0]phy2clb_phy_rdy_low_riuclk;
  wire [9:0]phy2clb_phy_rdy_upp_in_riuclk;
  wire [9:0]phy2clb_phy_rdy_upp_riuclk;
  wire [128:0]phy2iob_odt_out_byte;
  wire [128:0]phy2iob_q_out_byte;
  wire [128:0]phy2iob_t;
  wire phy_ready_riuclk;
  wire phy_ready_riuclk0;
  wire phy_ready_riuclk_i_2_n_0;
  wire phy_ready_riuclk_i_3_n_0;
  wire phy_ready_riuclk_i_4_n_0;
  wire pllGate;
  wire [2:0]pll_clk;
  wire pll_lock;
  wire [159:0]riu2clb_rd_data;
  wire [9:0]riu2clb_valid_riuclk;
  wire [15:0]riu2clb_vld_read_data;
  wire \riu2clb_vld_read_data[0]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[0]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[0]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[0]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[0]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[0]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[10]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[10]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[10]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[10]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[10]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[10]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[11]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[11]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[11]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[11]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[11]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[11]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[12]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[12]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[12]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[12]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[12]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[12]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[13]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[13]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[13]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[13]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[13]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[13]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[14]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[14]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[14]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[14]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[14]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[14]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[15]_i_10_n_0 ;
  wire \riu2clb_vld_read_data[15]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[15]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[15]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[15]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[15]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[15]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[15]_i_8_n_0 ;
  wire \riu2clb_vld_read_data[15]_i_9_n_0 ;
  wire \riu2clb_vld_read_data[1]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[1]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[1]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[1]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[1]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[1]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[2]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[2]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[2]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[2]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[2]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[2]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[3]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[3]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[3]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[3]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[3]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[3]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[4]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[4]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[4]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[4]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[4]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[4]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[5]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[5]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[5]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[5]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[5]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[5]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[6]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[6]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[6]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[6]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[6]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[6]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[7]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[7]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[7]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[7]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[7]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[7]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[8]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[8]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[8]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[8]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[8]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[8]_i_7_n_0 ;
  wire \riu2clb_vld_read_data[9]_i_2_n_0 ;
  wire \riu2clb_vld_read_data[9]_i_3_n_0 ;
  wire \riu2clb_vld_read_data[9]_i_4_n_0 ;
  wire \riu2clb_vld_read_data[9]_i_5_n_0 ;
  wire \riu2clb_vld_read_data[9]_i_6_n_0 ;
  wire \riu2clb_vld_read_data[9]_i_7_n_0 ;
  wire \riu2clb_vld_read_data_reg[0]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[10]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[11]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[12]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[13]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[14]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[15]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[1]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[2]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[3]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[4]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[5]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[6]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[7]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[8]_i_1_n_0 ;
  wire \riu2clb_vld_read_data_reg[9]_i_1_n_0 ;
  wire [5:0]riu_addr_cal;
  wire \riu_addr_cal[0]_INST_0_i_10_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_11_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_12_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_13_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_14_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_15_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_1_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_2_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_3_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_4_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_5_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_6_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_7_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_8_n_0 ;
  wire \riu_addr_cal[0]_INST_0_i_9_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_10_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_11_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_12_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_13_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_14_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_15_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_16_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_17_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_18_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_1_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_2_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_3_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_4_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_5_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_6_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_7_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_8_n_0 ;
  wire \riu_addr_cal[1]_INST_0_i_9_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_10_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_11_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_12_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_13_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_14_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_1_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_2_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_3_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_4_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_5_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_6_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_7_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_8_n_0 ;
  wire \riu_addr_cal[2]_INST_0_i_9_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_10_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_11_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_12_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_13_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_14_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_15_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_16_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_17_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_1_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_2_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_3_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_4_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_5_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_6_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_7_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_8_n_0 ;
  wire \riu_addr_cal[3]_INST_0_i_9_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_10_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_11_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_12_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_13_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_14_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_15_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_16_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_17_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_18_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_19_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_1_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_2_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_3_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_4_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_5_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_6_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_7_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_8_n_0 ;
  wire \riu_addr_cal[4]_INST_0_i_9_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_10_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_13_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_14_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_15_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_16_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_1_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_2_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_3_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_5_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_6_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_7_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_8_n_0 ;
  wire \riu_addr_cal[5]_INST_0_i_9_n_0 ;
  wire riu_clk;
  wire riu_clk_rst;
  (* RTL_KEEP = "true" *) wire riu_clk_rst_r1;
  wire [3:0]riu_nibble_8;
  wire \riu_nibble_8[0]_INST_0_i_10_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_11_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_12_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_13_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_14_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_15_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_16_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_1_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_2_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_3_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_4_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_5_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_6_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_7_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_8_n_0 ;
  wire \riu_nibble_8[0]_INST_0_i_9_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_10_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_11_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_12_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_13_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_14_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_15_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_2_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_3_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_4_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_5_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_6_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_7_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_8_n_0 ;
  wire \riu_nibble_8[1]_INST_0_i_9_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_10_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_11_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_12_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_13_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_14_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_15_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_16_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_17_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_18_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_19_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_1_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_20_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_21_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_22_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_2_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_3_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_4_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_5_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_6_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_7_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_8_n_0 ;
  wire \riu_nibble_8[2]_INST_0_i_9_n_0 ;
  wire \riu_nibble_8[3]_INST_0_i_10_n_0 ;
  wire \riu_nibble_8[3]_INST_0_i_11_n_0 ;
  wire \riu_nibble_8[3]_INST_0_i_12_n_0 ;
  wire \riu_nibble_8[3]_INST_0_i_13_n_0 ;
  wire \riu_nibble_8[3]_INST_0_i_1_n_0 ;
  wire \riu_nibble_8[3]_INST_0_i_2_n_0 ;
  wire \riu_nibble_8[3]_INST_0_i_3_n_0 ;
  wire \riu_nibble_8[3]_INST_0_i_5_n_0 ;
  wire \riu_nibble_8[3]_INST_0_i_6_n_0 ;
  wire \riu_nibble_8[3]_INST_0_i_7_n_0 ;
  wire \riu_nibble_8[3]_INST_0_i_8_n_0 ;
  wire \riu_nibble_8[3]_INST_0_i_9_n_0 ;
  wire \riu_nibble_8[4]_INST_0_i_2_n_0 ;
  wire \riu_nibble_8[4]_INST_0_i_3_n_0 ;
  wire \riu_nibble_8[4]_INST_0_i_4_n_0 ;
  wire \riu_nibble_8[4]_INST_0_i_5_n_0 ;
  wire \riu_nibble_8[4]_INST_0_i_6_n_0 ;
  wire \riu_nibble_8[4]_INST_0_i_7_n_0 ;
  wire \riu_nibble_8[4]_INST_0_i_8_n_0 ;
  wire \riu_nibble_8[4]_INST_0_i_9_n_0 ;
  wire \riu_nibble_8[6]_INST_0_i_1_n_0 ;
  wire \riu_nibble_8[6]_INST_0_i_2_n_0 ;
  wire \riu_nibble_8[6]_INST_0_i_3_n_0 ;
  wire \riu_nibble_8[6]_INST_0_i_4_n_0 ;
  wire \riu_nibble_8[6]_INST_0_i_5_n_0 ;
  wire \riu_nibble_8[6]_INST_0_i_6_n_0 ;
  wire \riu_nibble_8[6]_INST_0_i_7_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_10_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_13_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_14_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_15_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_19_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_20_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_21_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_22_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_7_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_8_n_0 ;
  wire \riu_nibble_8[7]_INST_0_i_9_n_0 ;
  wire [159:0]riu_read_data;
  wire sys_clk_in;
  wire sys_clk_n;
  wire sys_clk_p;
  wire ub_rst_out_riuclk;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    OBUF_reset_n
       (.I(cal_RESET_n),
        .O(ddr4_reset_n));
  LUT5 #(
    .INIT(32'h80000000)) 
    bisc_complete_riuclk_i_1
       (.I0(bisc_complete_riuclk_i_2_n_0),
        .I1(bisc_complete_riuclk_i_3_n_0),
        .I2(bisc_complete_riuclk_i_4_n_0),
        .I3(phy2clb_fixdly_rdy_low_riuclk[0]),
        .I4(phy2clb_fixdly_rdy_low_riuclk[1]),
        .O(clb2phy_t_b_addr_riuclk_reg0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    bisc_complete_riuclk_i_2
       (.I0(phy2clb_fixdly_rdy_upp_riuclk[6]),
        .I1(phy2clb_fixdly_rdy_upp_riuclk[7]),
        .I2(phy2clb_fixdly_rdy_upp_riuclk[4]),
        .I3(phy2clb_fixdly_rdy_upp_riuclk[5]),
        .I4(phy2clb_fixdly_rdy_upp_riuclk[9]),
        .I5(phy2clb_fixdly_rdy_upp_riuclk[8]),
        .O(bisc_complete_riuclk_i_2_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    bisc_complete_riuclk_i_3
       (.I0(phy2clb_fixdly_rdy_low_riuclk[4]),
        .I1(phy2clb_fixdly_rdy_low_riuclk[5]),
        .I2(phy2clb_fixdly_rdy_low_riuclk[2]),
        .I3(phy2clb_fixdly_rdy_low_riuclk[3]),
        .I4(phy2clb_fixdly_rdy_low_riuclk[7]),
        .I5(phy2clb_fixdly_rdy_low_riuclk[6]),
        .O(bisc_complete_riuclk_i_3_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    bisc_complete_riuclk_i_4
       (.I0(phy2clb_fixdly_rdy_upp_riuclk[0]),
        .I1(phy2clb_fixdly_rdy_upp_riuclk[1]),
        .I2(phy2clb_fixdly_rdy_low_riuclk[8]),
        .I3(phy2clb_fixdly_rdy_low_riuclk[9]),
        .I4(phy2clb_fixdly_rdy_upp_riuclk[3]),
        .I5(phy2clb_fixdly_rdy_upp_riuclk[2]),
        .O(bisc_complete_riuclk_i_4_n_0));
  FDRE bisc_complete_riuclk_reg
       (.C(riu_clk),
        .CE(1'b1),
        .D(clb2phy_t_b_addr_riuclk_reg0),
        .Q(bisc_complete_riuclk),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \clb2phy_t_b_addr_i_reg[0] 
       (.C(div_clk),
        .CE(1'b1),
        .D(clb2phy_t_b_addr_riuclk),
        .Q(clb2phy_t_b_addr_i[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \clb2phy_t_b_addr_i_reg[1] 
       (.C(div_clk),
        .CE(1'b1),
        .D(clb2phy_t_b_addr_i[0]),
        .Q(clb2phy_t_b_addr_i[1]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \clb2phy_t_b_addr_reg[0] 
       (.C(div_clk),
        .CE(1'b1),
        .D(clb2phy_t_b_addr_i[1]),
        .Q(clb2phy_t_b_addr[0]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \clb2phy_t_b_addr_reg[1] 
       (.C(div_clk),
        .CE(1'b1),
        .D(clb2phy_t_b_addr_i[1]),
        .Q(clb2phy_t_b_addr[1]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \clb2phy_t_b_addr_reg[2] 
       (.C(div_clk),
        .CE(1'b1),
        .D(clb2phy_t_b_addr_i[1]),
        .Q(clb2phy_t_b_addr[2]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE \clb2phy_t_b_addr_reg[3] 
       (.C(div_clk),
        .CE(1'b1),
        .D(clb2phy_t_b_addr_i[1]),
        .Q(clb2phy_t_b_addr[3]),
        .R(1'b0));
  (* DONT_TOUCH *) 
  (* KEEP = "yes" *) 
  FDRE clb2phy_t_b_addr_riuclk_reg
       (.C(riu_clk),
        .CE(1'b1),
        .D(clb2phy_t_b_addr_riuclk_reg0),
        .Q(clb2phy_t_b_addr_riuclk),
        .R(1'b0));
  FDRE \clb2riu_addr_reg[54] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu_addr_cal[0]),
        .Q(clb2riu_addr[54]),
        .R(1'b0));
  FDRE \clb2riu_addr_reg[55] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu_addr_cal[1]),
        .Q(clb2riu_addr[55]),
        .R(1'b0));
  FDRE \clb2riu_addr_reg[56] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu_addr_cal[2]),
        .Q(clb2riu_addr[56]),
        .R(1'b0));
  FDRE \clb2riu_addr_reg[57] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu_addr_cal[3]),
        .Q(clb2riu_addr[57]),
        .R(1'b0));
  FDRE \clb2riu_addr_reg[58] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu_addr_cal[4]),
        .Q(clb2riu_addr[58]),
        .R(1'b0));
  FDRE \clb2riu_addr_reg[59] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu_addr_cal[5]),
        .Q(clb2riu_addr[59]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \clb2riu_nibble_sel_low[0]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(riu_nibble_8[1]),
        .I3(\io_address_riuclk_reg[12] ),
        .I4(riu_nibble_8[0]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_9_out[0]));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \clb2riu_nibble_sel_low[1]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(riu_nibble_8[1]),
        .I3(\io_address_riuclk_reg[12] ),
        .I4(riu_nibble_8[0]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_9_out[1]));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    \clb2riu_nibble_sel_low[2]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(riu_nibble_8[1]),
        .I3(\io_address_riuclk_reg[12] ),
        .I4(riu_nibble_8[0]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_9_out[2]));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \clb2riu_nibble_sel_low[3]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(riu_nibble_8[1]),
        .I3(\io_address_riuclk_reg[12] ),
        .I4(riu_nibble_8[0]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_9_out[3]));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \clb2riu_nibble_sel_low[4]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(riu_nibble_8[1]),
        .I3(\io_address_riuclk_reg[12] ),
        .I4(riu_nibble_8[0]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_9_out[4]));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    \clb2riu_nibble_sel_low[5]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(riu_nibble_8[1]),
        .I3(\io_address_riuclk_reg[12] ),
        .I4(riu_nibble_8[0]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_9_out[5]));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \clb2riu_nibble_sel_low[6]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(riu_nibble_8[1]),
        .I3(\io_address_riuclk_reg[12] ),
        .I4(riu_nibble_8[0]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_9_out[6]));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \clb2riu_nibble_sel_low[7]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(riu_nibble_8[1]),
        .I3(\io_address_riuclk_reg[12] ),
        .I4(riu_nibble_8[0]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_9_out[7]));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \clb2riu_nibble_sel_low[8]_i_1 
       (.I0(riu_nibble_8[3]),
        .I1(\clb2riu_wr_en[9]_i_2_n_0 ),
        .I2(riu_nibble_8[1]),
        .I3(\io_address_riuclk_reg[12] ),
        .I4(riu_nibble_8[0]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_9_out[8]));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \clb2riu_nibble_sel_low[9]_i_1 
       (.I0(riu_nibble_8[3]),
        .I1(\clb2riu_wr_en[9]_i_2_n_0 ),
        .I2(riu_nibble_8[1]),
        .I3(\io_address_riuclk_reg[12] ),
        .I4(riu_nibble_8[0]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_9_out[9]));
  FDRE \clb2riu_nibble_sel_low_reg[0] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_9_out[0]),
        .Q(clb2riu_nibble_sel_low[0]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_low_reg[1] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_9_out[1]),
        .Q(clb2riu_nibble_sel_low[1]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_low_reg[2] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_9_out[2]),
        .Q(clb2riu_nibble_sel_low[2]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_low_reg[3] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_9_out[3]),
        .Q(clb2riu_nibble_sel_low[3]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_low_reg[4] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_9_out[4]),
        .Q(clb2riu_nibble_sel_low[4]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_low_reg[5] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_9_out[5]),
        .Q(clb2riu_nibble_sel_low[5]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_low_reg[6] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_9_out[6]),
        .Q(clb2riu_nibble_sel_low[6]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_low_reg[7] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_9_out[7]),
        .Q(clb2riu_nibble_sel_low[7]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_low_reg[8] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_9_out[8]),
        .Q(clb2riu_nibble_sel_low[8]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_low_reg[9] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_9_out[9]),
        .Q(clb2riu_nibble_sel_low[9]),
        .R(riu_clk_rst_r1));
  LUT6 #(
    .INIT(64'h0000000001000000)) 
    \clb2riu_nibble_sel_upp[0]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(riu_nibble_8[1]),
        .I3(\io_address_riuclk_reg[12] ),
        .I4(riu_nibble_8[0]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_11_out[0]));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \clb2riu_nibble_sel_upp[1]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[0]),
        .I4(riu_nibble_8[1]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_11_out[1]));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    \clb2riu_nibble_sel_upp[2]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[0]),
        .I4(riu_nibble_8[1]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_11_out[2]));
  LUT6 #(
    .INIT(64'h0000000001000000)) 
    \clb2riu_nibble_sel_upp[3]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[0]),
        .I4(riu_nibble_8[1]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_11_out[3]));
  LUT6 #(
    .INIT(64'h0000000004000000)) 
    \clb2riu_nibble_sel_upp[4]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(riu_nibble_8[1]),
        .I3(\io_address_riuclk_reg[12] ),
        .I4(riu_nibble_8[0]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_11_out[4]));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \clb2riu_nibble_sel_upp[5]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[0]),
        .I4(riu_nibble_8[1]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_11_out[5]));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \clb2riu_nibble_sel_upp[6]_i_1 
       (.I0(\io_address_riuclk_reg[12] ),
        .I1(riu_nibble_8[0]),
        .I2(riu_nibble_8[1]),
        .I3(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I4(riu_nibble_8[2]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_11_out[6]));
  LUT6 #(
    .INIT(64'h0000000004000000)) 
    \clb2riu_nibble_sel_upp[7]_i_1 
       (.I0(\clb2riu_wr_en[7]_i_2_n_0 ),
        .I1(riu_nibble_8[2]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[0]),
        .I4(riu_nibble_8[1]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_11_out[7]));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \clb2riu_nibble_sel_upp[8]_i_1 
       (.I0(riu_nibble_8[1]),
        .I1(\io_address_riuclk_reg[12] ),
        .I2(riu_nibble_8[0]),
        .I3(riu_nibble_8[3]),
        .I4(\clb2riu_wr_en[9]_i_2_n_0 ),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_11_out[8]));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \clb2riu_nibble_sel_upp[9]_i_1 
       (.I0(riu_nibble_8[3]),
        .I1(\clb2riu_wr_en[9]_i_2_n_0 ),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[0]),
        .I4(riu_nibble_8[1]),
        .I5(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ),
        .O(p_11_out[9]));
  LUT2 #(
    .INIT(4'h1)) 
    \clb2riu_nibble_sel_upp[9]_i_2 
       (.I0(io_addr_strobe_clb2riu_riuclk),
        .I1(extend_nibble_sel_riu_addr_0),
        .O(\clb2riu_nibble_sel_upp[9]_i_2_n_0 ));
  FDRE \clb2riu_nibble_sel_upp_reg[0] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_11_out[0]),
        .Q(clb2riu_nibble_sel_upp[0]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_upp_reg[1] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_11_out[1]),
        .Q(clb2riu_nibble_sel_upp[1]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_upp_reg[2] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_11_out[2]),
        .Q(clb2riu_nibble_sel_upp[2]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_upp_reg[3] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_11_out[3]),
        .Q(clb2riu_nibble_sel_upp[3]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_upp_reg[4] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_11_out[4]),
        .Q(clb2riu_nibble_sel_upp[4]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_upp_reg[5] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_11_out[5]),
        .Q(clb2riu_nibble_sel_upp[5]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_upp_reg[6] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_11_out[6]),
        .Q(clb2riu_nibble_sel_upp[6]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_upp_reg[7] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_11_out[7]),
        .Q(clb2riu_nibble_sel_upp[7]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_upp_reg[8] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_11_out[8]),
        .Q(clb2riu_nibble_sel_upp[8]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_nibble_sel_upp_reg[9] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_11_out[9]),
        .Q(clb2riu_nibble_sel_upp[9]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_wr_data_reg[144] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[0]),
        .Q(clb2riu_wr_data[144]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[145] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[1]),
        .Q(clb2riu_wr_data[145]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[146] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[2]),
        .Q(clb2riu_wr_data[146]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[147] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[3]),
        .Q(clb2riu_wr_data[147]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[148] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[4]),
        .Q(clb2riu_wr_data[148]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[149] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[5]),
        .Q(clb2riu_wr_data[149]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[150] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[6]),
        .Q(clb2riu_wr_data[150]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[151] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[7]),
        .Q(clb2riu_wr_data[151]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[152] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[8]),
        .Q(clb2riu_wr_data[152]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[153] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[9]),
        .Q(clb2riu_wr_data[153]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[154] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[10]),
        .Q(clb2riu_wr_data[154]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[155] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[11]),
        .Q(clb2riu_wr_data[155]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[156] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[12]),
        .Q(clb2riu_wr_data[156]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[157] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[13]),
        .Q(clb2riu_wr_data[157]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[158] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[14]),
        .Q(clb2riu_wr_data[158]),
        .R(1'b0));
  FDRE \clb2riu_wr_data_reg[159] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(io_write_data_riuclk[15]),
        .Q(clb2riu_wr_data[159]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000080)) 
    \clb2riu_wr_en[0]_i_1 
       (.I0(io_addr_strobe_clb2riu_riuclk),
        .I1(io_write_strobe_riuclk),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[1]),
        .I4(riu_nibble_8[2]),
        .I5(\clb2riu_wr_en[7]_i_2_n_0 ),
        .O(p_19_out[0]));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    \clb2riu_wr_en[1]_i_1 
       (.I0(io_addr_strobe_clb2riu_riuclk),
        .I1(io_write_strobe_riuclk),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[1]),
        .I4(riu_nibble_8[2]),
        .I5(\clb2riu_wr_en[7]_i_2_n_0 ),
        .O(p_19_out[1]));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \clb2riu_wr_en[2]_i_1 
       (.I0(io_addr_strobe_clb2riu_riuclk),
        .I1(io_write_strobe_riuclk),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[1]),
        .I4(riu_nibble_8[2]),
        .I5(\clb2riu_wr_en[7]_i_2_n_0 ),
        .O(p_19_out[2]));
  LUT6 #(
    .INIT(64'h0000000000000800)) 
    \clb2riu_wr_en[3]_i_1 
       (.I0(io_addr_strobe_clb2riu_riuclk),
        .I1(io_write_strobe_riuclk),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[1]),
        .I4(riu_nibble_8[2]),
        .I5(\clb2riu_wr_en[7]_i_2_n_0 ),
        .O(p_19_out[3]));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \clb2riu_wr_en[4]_i_1 
       (.I0(io_addr_strobe_clb2riu_riuclk),
        .I1(io_write_strobe_riuclk),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[1]),
        .I4(riu_nibble_8[2]),
        .I5(\clb2riu_wr_en[7]_i_2_n_0 ),
        .O(p_19_out[4]));
  LUT6 #(
    .INIT(64'h0000000000080000)) 
    \clb2riu_wr_en[5]_i_1 
       (.I0(io_addr_strobe_clb2riu_riuclk),
        .I1(io_write_strobe_riuclk),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[1]),
        .I4(riu_nibble_8[2]),
        .I5(\clb2riu_wr_en[7]_i_2_n_0 ),
        .O(p_19_out[5]));
  LUT6 #(
    .INIT(64'h0000000080000000)) 
    \clb2riu_wr_en[6]_i_1 
       (.I0(io_addr_strobe_clb2riu_riuclk),
        .I1(io_write_strobe_riuclk),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[1]),
        .I4(riu_nibble_8[2]),
        .I5(\clb2riu_wr_en[7]_i_2_n_0 ),
        .O(p_19_out[6]));
  LUT6 #(
    .INIT(64'h0000000008000000)) 
    \clb2riu_wr_en[7]_i_1 
       (.I0(io_addr_strobe_clb2riu_riuclk),
        .I1(io_write_strobe_riuclk),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[1]),
        .I4(riu_nibble_8[2]),
        .I5(\clb2riu_wr_en[7]_i_2_n_0 ),
        .O(p_19_out[7]));
  LUT6 #(
    .INIT(64'h00000100FFFFFFFF)) 
    \clb2riu_wr_en[7]_i_2 
       (.I0(\riu_addr_cal[5]_INST_0_i_1_n_0 ),
        .I1(\io_address_riuclk_reg[16] ),
        .I2(\riu_nibble_8[6]_INST_0_i_2_n_0 ),
        .I3(\io_address_riuclk_reg[14]_0 ),
        .I4(\riu_nibble_8[6]_INST_0_i_1_n_0 ),
        .I5(\io_address_riuclk_reg[10] ),
        .O(\clb2riu_wr_en[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000080)) 
    \clb2riu_wr_en[8]_i_1 
       (.I0(io_addr_strobe_clb2riu_riuclk),
        .I1(io_write_strobe_riuclk),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[1]),
        .I4(\clb2riu_wr_en[9]_i_2_n_0 ),
        .I5(riu_nibble_8[3]),
        .O(p_19_out[8]));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    \clb2riu_wr_en[9]_i_1 
       (.I0(io_addr_strobe_clb2riu_riuclk),
        .I1(io_write_strobe_riuclk),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_nibble_8[1]),
        .I4(\clb2riu_wr_en[9]_i_2_n_0 ),
        .I5(riu_nibble_8[3]),
        .O(p_19_out[9]));
  LUT2 #(
    .INIT(4'hE)) 
    \clb2riu_wr_en[9]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(\io_address_riuclk_reg[10] ),
        .O(\clb2riu_wr_en[9]_i_2_n_0 ));
  FDRE \clb2riu_wr_en_reg[0] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_19_out[0]),
        .Q(clb2riu_wr_en[0]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_wr_en_reg[1] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_19_out[1]),
        .Q(clb2riu_wr_en[1]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_wr_en_reg[2] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_19_out[2]),
        .Q(clb2riu_wr_en[2]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_wr_en_reg[3] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_19_out[3]),
        .Q(clb2riu_wr_en[3]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_wr_en_reg[4] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_19_out[4]),
        .Q(clb2riu_wr_en[4]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_wr_en_reg[5] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_19_out[5]),
        .Q(clb2riu_wr_en[5]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_wr_en_reg[6] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_19_out[6]),
        .Q(clb2riu_wr_en[6]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_wr_en_reg[7] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_19_out[7]),
        .Q(clb2riu_wr_en[7]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_wr_en_reg[8] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_19_out[8]),
        .Q(clb2riu_wr_en[8]),
        .R(riu_clk_rst_r1));
  FDRE \clb2riu_wr_en_reg[9] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(p_19_out[9]),
        .Q(clb2riu_wr_en[9]),
        .R(riu_clk_rst_r1));
  (* KEEP = "yes" *) 
  FDRE div_clk_rst_r1_reg
       (.C(div_clk),
        .CE(1'b1),
        .D(div_clk_rst),
        .Q(div_clk_rst_r1),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0002FFFF00020000)) 
    extend_nibble_sel_riu_addr_0_i_1
       (.I0(extend_nibble_sel_riu_addr_0_i_2_n_0),
        .I1(riu_addr_cal[5]),
        .I2(extend_nibble_sel_riu_addr_0_i_3_n_0),
        .I3(riu_addr_cal[4]),
        .I4(io_addr_strobe_clb2riu_riuclk),
        .I5(extend_nibble_sel_riu_addr_0),
        .O(extend_nibble_sel_riu_addr_0_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT3 #(
    .INIT(8'h01)) 
    extend_nibble_sel_riu_addr_0_i_10
       (.I0(io_address_riuclk[0]),
        .I1(io_address_riuclk[12]),
        .I2(io_address_riuclk[13]),
        .O(extend_nibble_sel_riu_addr_0_i_10_n_0));
  LUT6 #(
    .INIT(64'hFCF8FCFCFCF8FFFC)) 
    extend_nibble_sel_riu_addr_0_i_11
       (.I0(io_address_riuclk[5]),
        .I1(io_address_riuclk[15]),
        .I2(\riu_addr_cal[0]_INST_0_i_12_n_0 ),
        .I3(io_address_riuclk[4]),
        .I4(io_address_riuclk[9]),
        .I5(\riu_nibble_8[0]_INST_0_i_7_n_0 ),
        .O(extend_nibble_sel_riu_addr_0_i_11_n_0));
  LUT6 #(
    .INIT(64'h00000000DD0D0D0D)) 
    extend_nibble_sel_riu_addr_0_i_12
       (.I0(io_address_riuclk[2]),
        .I1(\riu_addr_cal[0]_INST_0_i_4_n_0 ),
        .I2(extend_nibble_sel_riu_addr_0_i_19_n_0),
        .I3(io_address_riuclk[14]),
        .I4(io_address_riuclk[9]),
        .I5(extend_nibble_sel_riu_addr_0_i_20_n_0),
        .O(extend_nibble_sel_riu_addr_0_i_12_n_0));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT5 #(
    .INIT(32'hAAAAAA08)) 
    extend_nibble_sel_riu_addr_0_i_13
       (.I0(io_address_riuclk[1]),
        .I1(io_address_riuclk[5]),
        .I2(io_address_riuclk[9]),
        .I3(io_address_riuclk[10]),
        .I4(io_address_riuclk[6]),
        .O(extend_nibble_sel_riu_addr_0_i_13_n_0));
  LUT6 #(
    .INIT(64'h0000080000080800)) 
    extend_nibble_sel_riu_addr_0_i_14
       (.I0(io_address_riuclk[16]),
        .I1(\riu_nibble_8[7]_INST_0_i_15_n_0 ),
        .I2(io_address_riuclk[6]),
        .I3(io_address_riuclk[4]),
        .I4(io_address_riuclk[7]),
        .I5(\riu_nibble_8[0]_INST_0_i_7_n_0 ),
        .O(extend_nibble_sel_riu_addr_0_i_14_n_0));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT5 #(
    .INIT(32'h55555556)) 
    extend_nibble_sel_riu_addr_0_i_15
       (.I0(io_address_riuclk[5]),
        .I1(io_address_riuclk[6]),
        .I2(io_address_riuclk[7]),
        .I3(io_address_riuclk[11]),
        .I4(io_address_riuclk[10]),
        .O(extend_nibble_sel_riu_addr_0_i_15_n_0));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT5 #(
    .INIT(32'hEEFFEEEF)) 
    extend_nibble_sel_riu_addr_0_i_16
       (.I0(\riu_addr_cal[1]_INST_0_i_8_n_0 ),
        .I1(\riu_addr_cal[1]_INST_0_i_7_n_0 ),
        .I2(io_address_riuclk[16]),
        .I3(io_address_riuclk[14]),
        .I4(io_address_riuclk[8]),
        .O(extend_nibble_sel_riu_addr_0_i_16_n_0));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT4 #(
    .INIT(16'hFEA8)) 
    extend_nibble_sel_riu_addr_0_i_17
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[11]),
        .I3(io_address_riuclk[9]),
        .O(extend_nibble_sel_riu_addr_0_i_17_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    extend_nibble_sel_riu_addr_0_i_18
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[4]),
        .O(extend_nibble_sel_riu_addr_0_i_18_n_0));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT2 #(
    .INIT(4'h6)) 
    extend_nibble_sel_riu_addr_0_i_19
       (.I0(io_address_riuclk[3]),
        .I1(io_address_riuclk[4]),
        .O(extend_nibble_sel_riu_addr_0_i_19_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    extend_nibble_sel_riu_addr_0_i_2
       (.I0(\riu_addr_cal[2]_INST_0_i_2_n_0 ),
        .I1(extend_nibble_sel_riu_addr_0_i_4_n_0),
        .I2(riu_addr_cal[3]),
        .I3(extend_nibble_sel_riu_addr_0_i_5_n_0),
        .I4(\riu_addr_cal[0]_INST_0_i_2_n_0 ),
        .I5(extend_nibble_sel_riu_addr_0_i_6_n_0),
        .O(extend_nibble_sel_riu_addr_0_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT5 #(
    .INIT(32'h8C8C8C88)) 
    extend_nibble_sel_riu_addr_0_i_20
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[16]),
        .I2(io_address_riuclk[4]),
        .I3(io_address_riuclk[1]),
        .I4(io_address_riuclk[2]),
        .O(extend_nibble_sel_riu_addr_0_i_20_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFBABBFFFF)) 
    extend_nibble_sel_riu_addr_0_i_3
       (.I0(\riu_addr_cal[1]_INST_0_i_4_n_0 ),
        .I1(\riu_addr_cal[3]_INST_0_i_3_n_0 ),
        .I2(extend_nibble_sel_riu_addr_0_i_7_n_0),
        .I3(\riu_addr_cal[1]_INST_0_i_1_n_0 ),
        .I4(io_addr_strobe_clb2riu_riuclk),
        .I5(io_write_strobe_riuclk),
        .O(extend_nibble_sel_riu_addr_0_i_3_n_0));
  LUT6 #(
    .INIT(64'hAAAAAAA8AAAAAAAA)) 
    extend_nibble_sel_riu_addr_0_i_4
       (.I0(extend_nibble_sel_riu_addr_0_i_8_n_0),
        .I1(\io_address_riuclk_reg[19] ),
        .I2(\riu_addr_cal[2]_INST_0_i_7_n_0 ),
        .I3(\riu_addr_cal[2]_INST_0_i_6_n_0 ),
        .I4(extend_nibble_sel_riu_addr_0_i_9_n_0),
        .I5(\riu_addr_cal[2]_INST_0_i_3_n_0 ),
        .O(extend_nibble_sel_riu_addr_0_i_4_n_0));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAA8AA)) 
    extend_nibble_sel_riu_addr_0_i_5
       (.I0(extend_nibble_sel_riu_addr_0_i_10_n_0),
        .I1(\riu_addr_cal[0]_INST_0_i_11_n_0 ),
        .I2(extend_nibble_sel_riu_addr_0_i_11_n_0),
        .I3(extend_nibble_sel_riu_addr_0_i_12_n_0),
        .I4(extend_nibble_sel_riu_addr_0_i_13_n_0),
        .I5(\io_address_riuclk_reg[19] ),
        .O(extend_nibble_sel_riu_addr_0_i_5_n_0));
  LUT6 #(
    .INIT(64'hA8A8A8A8A8A8A8AA)) 
    extend_nibble_sel_riu_addr_0_i_6
       (.I0(io_address_riuclk[0]),
        .I1(\io_address_riuclk_reg[19] ),
        .I2(\riu_addr_cal[0]_INST_0_i_10_n_0 ),
        .I3(io_address_riuclk[15]),
        .I4(io_address_riuclk[14]),
        .I5(extend_nibble_sel_riu_addr_0_i_14_n_0),
        .O(extend_nibble_sel_riu_addr_0_i_6_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0444)) 
    extend_nibble_sel_riu_addr_0_i_7
       (.I0(\riu_addr_cal[1]_INST_0_i_12_n_0 ),
        .I1(\riu_nibble_8[7]_INST_0_i_7_n_0 ),
        .I2(extend_nibble_sel_riu_addr_0_i_15_n_0),
        .I3(\riu_addr_cal[1]_INST_0_i_9_n_0 ),
        .I4(extend_nibble_sel_riu_addr_0_i_16_n_0),
        .I5(\riu_addr_cal[1]_INST_0_i_6_n_0 ),
        .O(extend_nibble_sel_riu_addr_0_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT4 #(
    .INIT(16'h4055)) 
    extend_nibble_sel_riu_addr_0_i_8
       (.I0(io_address_riuclk[12]),
        .I1(io_address_riuclk[8]),
        .I2(io_address_riuclk[14]),
        .I3(io_address_riuclk[13]),
        .O(extend_nibble_sel_riu_addr_0_i_8_n_0));
  LUT6 #(
    .INIT(64'hEEEEFEEEFEEEFEEE)) 
    extend_nibble_sel_riu_addr_0_i_9
       (.I0(\riu_addr_cal[2]_INST_0_i_4_n_0 ),
        .I1(extend_nibble_sel_riu_addr_0_i_17_n_0),
        .I2(io_address_riuclk[16]),
        .I3(extend_nibble_sel_riu_addr_0_i_18_n_0),
        .I4(\riu_nibble_8[0]_INST_0_i_15_n_0 ),
        .I5(\io_address_riuclk_reg[1] ),
        .O(extend_nibble_sel_riu_addr_0_i_9_n_0));
  FDRE extend_nibble_sel_riu_addr_0_reg
       (.C(riu_clk),
        .CE(1'b1),
        .D(extend_nibble_sel_riu_addr_0_i_1_n_0),
        .Q(extend_nibble_sel_riu_addr_0),
        .R(riu_clk_rst_r1));
  ddr4_0_ddr4_phy_v2_2_0_xiphy \generate_block1.u_ddr_xiphy 
       (.D(phy2clb_fixdly_rdy_low_in_riuclk),
        .Q(clb2riu_nibble_sel_low),
        .SR(riu_clk_rst_r1),
        .ch0_mcal_DQOut(ch0_mcal_DQOut),
        .ch0_mcal_clb2phy_fifo_rden(ch0_mcal_clb2phy_fifo_rden),
        .ch0_mcal_clb2phy_rdcs0_low(ch0_mcal_clb2phy_rdcs0_low),
        .ch0_mcal_clb2phy_rdcs0_upp(ch0_mcal_clb2phy_rdcs0_upp),
        .ch0_mcal_clb2phy_rdcs1_low(ch0_mcal_clb2phy_rdcs1_low),
        .ch0_mcal_clb2phy_rdcs1_upp(ch0_mcal_clb2phy_rdcs1_upp),
        .ch0_mcal_clb2phy_rden_low(ch0_mcal_clb2phy_rden_low),
        .ch0_mcal_clb2phy_rden_upp(ch0_mcal_clb2phy_rden_upp),
        .ch0_mcal_clb2phy_t_b_low(ch0_mcal_clb2phy_t_b_low),
        .ch0_mcal_clb2phy_t_b_upp(ch0_mcal_clb2phy_t_b_upp),
        .ch0_mcal_clb2phy_wrcs0_low(ch0_mcal_clb2phy_wrcs0_low),
        .ch0_mcal_clb2phy_wrcs0_upp(ch0_mcal_clb2phy_wrcs0_upp),
        .ch0_mcal_clb2phy_wrcs1_low(ch0_mcal_clb2phy_wrcs1_low),
        .ch0_mcal_clb2phy_wrcs1_upp(ch0_mcal_clb2phy_wrcs1_upp),
        .clb2phy_t_b_low(clb2phy_t_b_addr),
        .clb2phy_tristate_odelay_rst(div_clk_rst_r1),
        .clb2phy_wr_dq0(clb2phy_wr_dq0),
        .clb2phy_wr_dq1(clb2phy_wr_dq1),
        .clb2phy_wr_dq6(clb2phy_wr_dq6),
        .div_clk(div_clk),
        .en_vtc_riuclk(en_vtc_riuclk),
        .iob2phy_d_in_byte({iob2phy_d_in_byte[128:125],iob2phy_d_in_byte[123:119],iob2phy_d_in_byte[117],iob2phy_d_in_byte[115:112],iob2phy_d_in_byte[110:106],iob2phy_d_in_byte[104],iob2phy_d_in_byte[102:99],iob2phy_d_in_byte[97:93],iob2phy_d_in_byte[91],iob2phy_d_in_byte[89:86],iob2phy_d_in_byte[84:80],iob2phy_d_in_byte[78],iob2phy_d_in_byte[76:73],iob2phy_d_in_byte[71:67],iob2phy_d_in_byte[65],iob2phy_d_in_byte[63:60],iob2phy_d_in_byte[58:54],iob2phy_d_in_byte[52],iob2phy_d_in_byte[50:47],iob2phy_d_in_byte[45:41],iob2phy_d_in_byte[39],iob2phy_d_in_byte[11:8],iob2phy_d_in_byte[6:2],iob2phy_d_in_byte[0]}),
        .mcal_ADR(mcal_ADR),
        .mcal_BA(mcal_BA),
        .mcal_BG(mcal_BG),
        .mcal_CKE(mcal_CKE),
        .mcal_CS_n(mcal_CS_n),
        .mcal_DMIn_n(mcal_DMIn_n),
        .mcal_DQIn(mcal_DQIn),
        .phy2iob_odt_out_byte({phy2iob_odt_out_byte[128:125],phy2iob_odt_out_byte[122:119],phy2iob_odt_out_byte[117],phy2iob_odt_out_byte[115:112],phy2iob_odt_out_byte[109:106],phy2iob_odt_out_byte[104],phy2iob_odt_out_byte[102:99],phy2iob_odt_out_byte[96:93],phy2iob_odt_out_byte[91],phy2iob_odt_out_byte[89:86],phy2iob_odt_out_byte[83:80],phy2iob_odt_out_byte[78],phy2iob_odt_out_byte[76:73],phy2iob_odt_out_byte[70:67],phy2iob_odt_out_byte[65],phy2iob_odt_out_byte[63:60],phy2iob_odt_out_byte[57:54],phy2iob_odt_out_byte[52],phy2iob_odt_out_byte[50:47],phy2iob_odt_out_byte[44:41],phy2iob_odt_out_byte[39],phy2iob_odt_out_byte[11:8],phy2iob_odt_out_byte[5:2],phy2iob_odt_out_byte[0]}),
        .phy2iob_q_out_byte({phy2iob_q_out_byte[128:125],phy2iob_q_out_byte[123:119],phy2iob_q_out_byte[117],phy2iob_q_out_byte[115:112],phy2iob_q_out_byte[110:106],phy2iob_q_out_byte[104],phy2iob_q_out_byte[102:99],phy2iob_q_out_byte[97:93],phy2iob_q_out_byte[91],phy2iob_q_out_byte[89:86],phy2iob_q_out_byte[84:80],phy2iob_q_out_byte[78],phy2iob_q_out_byte[76:73],phy2iob_q_out_byte[71:67],phy2iob_q_out_byte[65],phy2iob_q_out_byte[63:60],phy2iob_q_out_byte[58:54],phy2iob_q_out_byte[52],phy2iob_q_out_byte[50:47],phy2iob_q_out_byte[45:23],phy2iob_q_out_byte[19:13],phy2iob_q_out_byte[11:8],phy2iob_q_out_byte[6:0]}),
        .phy2iob_t({phy2iob_t[128:125],phy2iob_t[123:119],phy2iob_t[117],phy2iob_t[115:112],phy2iob_t[110:106],phy2iob_t[104],phy2iob_t[102:99],phy2iob_t[97:93],phy2iob_t[91],phy2iob_t[89:86],phy2iob_t[84:80],phy2iob_t[78],phy2iob_t[76:73],phy2iob_t[71:67],phy2iob_t[65],phy2iob_t[63:60],phy2iob_t[58:54],phy2iob_t[52],phy2iob_t[50:47],phy2iob_t[45:41],phy2iob_t[39],phy2iob_t[11:8],phy2iob_t[6:2],phy2iob_t[0]}),
        .pll_clk(pll_clk),
        .riu2clb_valid_riuclk(riu2clb_valid_riuclk),
        .riu_clk(riu_clk),
        .u_lut1_clb2riu_wr_en(clb2riu_wr_en),
        .xiphy_control(phy2clb_phy_rdy_low_in_riuclk),
        .xiphy_control_0(phy2clb_fixdly_rdy_upp_in_riuclk),
        .xiphy_control_1(phy2clb_phy_rdy_upp_in_riuclk),
        .xiphy_control_2(clb2riu_wr_data),
        .xiphy_control_3(clb2riu_addr),
        .xiphy_control_4(clb2riu_nibble_sel_upp),
        .xiphy_riu_or(riu2clb_rd_data));
  FDRE \phy2clb_fixdly_rdy_low_riuclk_int_reg[0] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_in_riuclk[0]),
        .Q(phy2clb_fixdly_rdy_low_riuclk[0]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_low_riuclk_int_reg[1] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_in_riuclk[1]),
        .Q(phy2clb_fixdly_rdy_low_riuclk[1]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_low_riuclk_int_reg[2] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_in_riuclk[2]),
        .Q(phy2clb_fixdly_rdy_low_riuclk[2]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_low_riuclk_int_reg[3] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_in_riuclk[3]),
        .Q(phy2clb_fixdly_rdy_low_riuclk[3]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_low_riuclk_int_reg[4] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_in_riuclk[4]),
        .Q(phy2clb_fixdly_rdy_low_riuclk[4]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_low_riuclk_int_reg[5] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_in_riuclk[5]),
        .Q(phy2clb_fixdly_rdy_low_riuclk[5]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_low_riuclk_int_reg[6] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_in_riuclk[6]),
        .Q(phy2clb_fixdly_rdy_low_riuclk[6]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_low_riuclk_int_reg[7] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_in_riuclk[7]),
        .Q(phy2clb_fixdly_rdy_low_riuclk[7]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_low_riuclk_int_reg[8] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_in_riuclk[8]),
        .Q(phy2clb_fixdly_rdy_low_riuclk[8]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_low_riuclk_int_reg[9] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_low_in_riuclk[9]),
        .Q(phy2clb_fixdly_rdy_low_riuclk[9]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_upp_riuclk_int_reg[0] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_in_riuclk[0]),
        .Q(phy2clb_fixdly_rdy_upp_riuclk[0]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_upp_riuclk_int_reg[1] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_in_riuclk[1]),
        .Q(phy2clb_fixdly_rdy_upp_riuclk[1]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_upp_riuclk_int_reg[2] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_in_riuclk[2]),
        .Q(phy2clb_fixdly_rdy_upp_riuclk[2]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_upp_riuclk_int_reg[3] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_in_riuclk[3]),
        .Q(phy2clb_fixdly_rdy_upp_riuclk[3]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_upp_riuclk_int_reg[4] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_in_riuclk[4]),
        .Q(phy2clb_fixdly_rdy_upp_riuclk[4]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_upp_riuclk_int_reg[5] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_in_riuclk[5]),
        .Q(phy2clb_fixdly_rdy_upp_riuclk[5]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_upp_riuclk_int_reg[6] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_in_riuclk[6]),
        .Q(phy2clb_fixdly_rdy_upp_riuclk[6]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_upp_riuclk_int_reg[7] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_in_riuclk[7]),
        .Q(phy2clb_fixdly_rdy_upp_riuclk[7]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_upp_riuclk_int_reg[8] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_in_riuclk[8]),
        .Q(phy2clb_fixdly_rdy_upp_riuclk[8]),
        .R(1'b0));
  FDRE \phy2clb_fixdly_rdy_upp_riuclk_int_reg[9] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_fixdly_rdy_upp_in_riuclk[9]),
        .Q(phy2clb_fixdly_rdy_upp_riuclk[9]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_low_riuclk_int_reg[0] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_in_riuclk[0]),
        .Q(phy2clb_phy_rdy_low_riuclk[0]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_low_riuclk_int_reg[1] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_in_riuclk[1]),
        .Q(phy2clb_phy_rdy_low_riuclk[1]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_low_riuclk_int_reg[2] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_in_riuclk[2]),
        .Q(phy2clb_phy_rdy_low_riuclk[2]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_low_riuclk_int_reg[3] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_in_riuclk[3]),
        .Q(phy2clb_phy_rdy_low_riuclk[3]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_low_riuclk_int_reg[4] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_in_riuclk[4]),
        .Q(phy2clb_phy_rdy_low_riuclk[4]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_low_riuclk_int_reg[5] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_in_riuclk[5]),
        .Q(phy2clb_phy_rdy_low_riuclk[5]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_low_riuclk_int_reg[6] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_in_riuclk[6]),
        .Q(phy2clb_phy_rdy_low_riuclk[6]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_low_riuclk_int_reg[7] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_in_riuclk[7]),
        .Q(phy2clb_phy_rdy_low_riuclk[7]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_low_riuclk_int_reg[8] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_in_riuclk[8]),
        .Q(phy2clb_phy_rdy_low_riuclk[8]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_low_riuclk_int_reg[9] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_low_in_riuclk[9]),
        .Q(phy2clb_phy_rdy_low_riuclk[9]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_upp_riuclk_int_reg[0] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_in_riuclk[0]),
        .Q(phy2clb_phy_rdy_upp_riuclk[0]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_upp_riuclk_int_reg[1] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_in_riuclk[1]),
        .Q(phy2clb_phy_rdy_upp_riuclk[1]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_upp_riuclk_int_reg[2] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_in_riuclk[2]),
        .Q(phy2clb_phy_rdy_upp_riuclk[2]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_upp_riuclk_int_reg[3] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_in_riuclk[3]),
        .Q(phy2clb_phy_rdy_upp_riuclk[3]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_upp_riuclk_int_reg[4] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_in_riuclk[4]),
        .Q(phy2clb_phy_rdy_upp_riuclk[4]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_upp_riuclk_int_reg[5] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_in_riuclk[5]),
        .Q(phy2clb_phy_rdy_upp_riuclk[5]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_upp_riuclk_int_reg[6] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_in_riuclk[6]),
        .Q(phy2clb_phy_rdy_upp_riuclk[6]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_upp_riuclk_int_reg[7] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_in_riuclk[7]),
        .Q(phy2clb_phy_rdy_upp_riuclk[7]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_upp_riuclk_int_reg[8] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_in_riuclk[8]),
        .Q(phy2clb_phy_rdy_upp_riuclk[8]),
        .R(1'b0));
  FDRE \phy2clb_phy_rdy_upp_riuclk_int_reg[9] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy2clb_phy_rdy_upp_in_riuclk[9]),
        .Q(phy2clb_phy_rdy_upp_riuclk[9]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    phy_ready_riuclk_i_1
       (.I0(phy_ready_riuclk_i_2_n_0),
        .I1(phy_ready_riuclk_i_3_n_0),
        .I2(phy_ready_riuclk_i_4_n_0),
        .I3(phy2clb_phy_rdy_upp_riuclk[0]),
        .I4(phy2clb_phy_rdy_upp_riuclk[1]),
        .O(phy_ready_riuclk0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    phy_ready_riuclk_i_2
       (.I0(phy2clb_phy_rdy_low_riuclk[6]),
        .I1(phy2clb_phy_rdy_low_riuclk[7]),
        .I2(phy2clb_phy_rdy_low_riuclk[4]),
        .I3(phy2clb_phy_rdy_low_riuclk[5]),
        .I4(phy2clb_phy_rdy_low_riuclk[9]),
        .I5(phy2clb_phy_rdy_low_riuclk[8]),
        .O(phy_ready_riuclk_i_2_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    phy_ready_riuclk_i_3
       (.I0(phy2clb_phy_rdy_upp_riuclk[4]),
        .I1(phy2clb_phy_rdy_upp_riuclk[5]),
        .I2(phy2clb_phy_rdy_upp_riuclk[2]),
        .I3(phy2clb_phy_rdy_upp_riuclk[3]),
        .I4(phy2clb_phy_rdy_upp_riuclk[7]),
        .I5(phy2clb_phy_rdy_upp_riuclk[6]),
        .O(phy_ready_riuclk_i_3_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    phy_ready_riuclk_i_4
       (.I0(phy2clb_phy_rdy_low_riuclk[0]),
        .I1(phy2clb_phy_rdy_low_riuclk[1]),
        .I2(phy2clb_phy_rdy_upp_riuclk[8]),
        .I3(phy2clb_phy_rdy_upp_riuclk[9]),
        .I4(phy2clb_phy_rdy_low_riuclk[3]),
        .I5(phy2clb_phy_rdy_low_riuclk[2]),
        .O(phy_ready_riuclk_i_4_n_0));
  FDRE phy_ready_riuclk_reg
       (.C(riu_clk),
        .CE(1'b1),
        .D(phy_ready_riuclk0),
        .Q(phy_ready_riuclk),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[0]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[128]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[144]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[0]_i_3 
       (.I0(\riu2clb_vld_read_data[0]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[0]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[0]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[0]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[0]_i_4 
       (.I0(riu_read_data[96]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[112]),
        .O(\riu2clb_vld_read_data[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[0]_i_5 
       (.I0(riu_read_data[64]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[80]),
        .O(\riu2clb_vld_read_data[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[0]_i_6 
       (.I0(riu_read_data[32]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[48]),
        .O(\riu2clb_vld_read_data[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[0]_i_7 
       (.I0(riu_read_data[0]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[16]),
        .O(\riu2clb_vld_read_data[0]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[10]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[138]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[154]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[10]_i_3 
       (.I0(\riu2clb_vld_read_data[10]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[10]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[10]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[10]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[10]_i_4 
       (.I0(riu_read_data[106]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[122]),
        .O(\riu2clb_vld_read_data[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[10]_i_5 
       (.I0(riu_read_data[74]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[90]),
        .O(\riu2clb_vld_read_data[10]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[10]_i_6 
       (.I0(riu_read_data[42]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[58]),
        .O(\riu2clb_vld_read_data[10]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[10]_i_7 
       (.I0(riu_read_data[10]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[26]),
        .O(\riu2clb_vld_read_data[10]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[11]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[139]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[155]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[11]_i_3 
       (.I0(\riu2clb_vld_read_data[11]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[11]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[11]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[11]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[11]_i_4 
       (.I0(riu_read_data[107]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[123]),
        .O(\riu2clb_vld_read_data[11]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[11]_i_5 
       (.I0(riu_read_data[75]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[91]),
        .O(\riu2clb_vld_read_data[11]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[11]_i_6 
       (.I0(riu_read_data[43]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[59]),
        .O(\riu2clb_vld_read_data[11]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[11]_i_7 
       (.I0(riu_read_data[11]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[27]),
        .O(\riu2clb_vld_read_data[11]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[12]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[140]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[156]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[12]_i_3 
       (.I0(\riu2clb_vld_read_data[12]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[12]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[12]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[12]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[12]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[12]_i_4 
       (.I0(riu_read_data[108]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[124]),
        .O(\riu2clb_vld_read_data[12]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[12]_i_5 
       (.I0(riu_read_data[76]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[92]),
        .O(\riu2clb_vld_read_data[12]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[12]_i_6 
       (.I0(riu_read_data[44]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[60]),
        .O(\riu2clb_vld_read_data[12]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[12]_i_7 
       (.I0(riu_read_data[12]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[28]),
        .O(\riu2clb_vld_read_data[12]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[13]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[141]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[157]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[13]_i_3 
       (.I0(\riu2clb_vld_read_data[13]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[13]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[13]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[13]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[13]_i_4 
       (.I0(riu_read_data[109]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[125]),
        .O(\riu2clb_vld_read_data[13]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[13]_i_5 
       (.I0(riu_read_data[77]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[93]),
        .O(\riu2clb_vld_read_data[13]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[13]_i_6 
       (.I0(riu_read_data[45]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[61]),
        .O(\riu2clb_vld_read_data[13]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[13]_i_7 
       (.I0(riu_read_data[13]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[29]),
        .O(\riu2clb_vld_read_data[13]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[14]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[142]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[158]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[14]_i_3 
       (.I0(\riu2clb_vld_read_data[14]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[14]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[14]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[14]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[14]_i_4 
       (.I0(riu_read_data[110]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[126]),
        .O(\riu2clb_vld_read_data[14]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[14]_i_5 
       (.I0(riu_read_data[78]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[94]),
        .O(\riu2clb_vld_read_data[14]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[14]_i_6 
       (.I0(riu_read_data[46]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[62]),
        .O(\riu2clb_vld_read_data[14]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[14]_i_7 
       (.I0(riu_read_data[14]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[30]),
        .O(\riu2clb_vld_read_data[14]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFAFAF2FA0A0A020A)) 
    \riu2clb_vld_read_data[15]_i_10 
       (.I0(\riu_nibble_8[1]_INST_0_i_11_n_0 ),
        .I1(\riu_addr_cal[1]_INST_0_i_11_n_0 ),
        .I2(io_address_riuclk[9]),
        .I3(io_address_riuclk[0]),
        .I4(\riu_addr_cal[1]_INST_0_i_5_n_0 ),
        .I5(\riu_nibble_8[1]_INST_0_i_15_n_0 ),
        .O(\riu2clb_vld_read_data[15]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[15]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[143]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[159]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[15]_i_3 
       (.I0(\riu2clb_vld_read_data[15]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[15]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[15]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[15]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[15]_i_4 
       (.I0(riu_read_data[111]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[127]),
        .O(\riu2clb_vld_read_data[15]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[15]_i_5 
       (.I0(riu_read_data[79]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[95]),
        .O(\riu2clb_vld_read_data[15]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[15]_i_6 
       (.I0(riu_read_data[47]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[63]),
        .O(\riu2clb_vld_read_data[15]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[15]_i_7 
       (.I0(riu_read_data[15]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[31]),
        .O(\riu2clb_vld_read_data[15]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FF01)) 
    \riu2clb_vld_read_data[15]_i_8 
       (.I0(io_address_riuclk[6]),
        .I1(io_address_riuclk[8]),
        .I2(\riu2clb_vld_read_data[15]_i_10_n_0 ),
        .I3(\riu_nibble_8[1]_INST_0_i_10_n_0 ),
        .I4(\riu_nibble_8[1]_INST_0_i_3_n_0 ),
        .I5(\io_address_riuclk_reg[19] ),
        .O(\riu2clb_vld_read_data[15]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000400000000)) 
    \riu2clb_vld_read_data[15]_i_9 
       (.I0(\io_address_riuclk_reg[19] ),
        .I1(io_address_riuclk[12]),
        .I2(io_address_riuclk[13]),
        .I3(io_address_riuclk[16]),
        .I4(\riu_nibble_8[3]_INST_0_i_5_n_0 ),
        .I5(io_address_riuclk[7]),
        .O(\riu2clb_vld_read_data[15]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[1]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[129]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[145]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[1]_i_3 
       (.I0(\riu2clb_vld_read_data[1]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[1]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[1]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[1]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[1]_i_4 
       (.I0(riu_read_data[97]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[113]),
        .O(\riu2clb_vld_read_data[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[1]_i_5 
       (.I0(riu_read_data[65]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[81]),
        .O(\riu2clb_vld_read_data[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[1]_i_6 
       (.I0(riu_read_data[33]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[49]),
        .O(\riu2clb_vld_read_data[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[1]_i_7 
       (.I0(riu_read_data[1]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[17]),
        .O(\riu2clb_vld_read_data[1]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[2]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[130]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[146]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[2]_i_3 
       (.I0(\riu2clb_vld_read_data[2]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[2]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[2]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[2]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[2]_i_4 
       (.I0(riu_read_data[98]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[114]),
        .O(\riu2clb_vld_read_data[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[2]_i_5 
       (.I0(riu_read_data[66]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[82]),
        .O(\riu2clb_vld_read_data[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[2]_i_6 
       (.I0(riu_read_data[34]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[50]),
        .O(\riu2clb_vld_read_data[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[2]_i_7 
       (.I0(riu_read_data[2]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[18]),
        .O(\riu2clb_vld_read_data[2]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[3]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[131]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[147]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[3]_i_3 
       (.I0(\riu2clb_vld_read_data[3]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[3]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[3]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[3]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[3]_i_4 
       (.I0(riu_read_data[99]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[115]),
        .O(\riu2clb_vld_read_data[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[3]_i_5 
       (.I0(riu_read_data[67]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[83]),
        .O(\riu2clb_vld_read_data[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[3]_i_6 
       (.I0(riu_read_data[35]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[51]),
        .O(\riu2clb_vld_read_data[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[3]_i_7 
       (.I0(riu_read_data[3]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[19]),
        .O(\riu2clb_vld_read_data[3]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[4]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[132]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[148]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[4]_i_3 
       (.I0(\riu2clb_vld_read_data[4]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[4]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[4]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[4]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[4]_i_4 
       (.I0(riu_read_data[100]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[116]),
        .O(\riu2clb_vld_read_data[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[4]_i_5 
       (.I0(riu_read_data[68]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[84]),
        .O(\riu2clb_vld_read_data[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[4]_i_6 
       (.I0(riu_read_data[36]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[52]),
        .O(\riu2clb_vld_read_data[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[4]_i_7 
       (.I0(riu_read_data[4]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[20]),
        .O(\riu2clb_vld_read_data[4]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[5]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[133]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[149]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[5]_i_3 
       (.I0(\riu2clb_vld_read_data[5]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[5]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[5]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[5]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[5]_i_4 
       (.I0(riu_read_data[101]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[117]),
        .O(\riu2clb_vld_read_data[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[5]_i_5 
       (.I0(riu_read_data[69]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[85]),
        .O(\riu2clb_vld_read_data[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[5]_i_6 
       (.I0(riu_read_data[37]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[53]),
        .O(\riu2clb_vld_read_data[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[5]_i_7 
       (.I0(riu_read_data[5]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[21]),
        .O(\riu2clb_vld_read_data[5]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[6]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[134]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[150]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[6]_i_3 
       (.I0(\riu2clb_vld_read_data[6]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[6]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[6]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[6]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[6]_i_4 
       (.I0(riu_read_data[102]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[118]),
        .O(\riu2clb_vld_read_data[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[6]_i_5 
       (.I0(riu_read_data[70]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[86]),
        .O(\riu2clb_vld_read_data[6]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[6]_i_6 
       (.I0(riu_read_data[38]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[54]),
        .O(\riu2clb_vld_read_data[6]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[6]_i_7 
       (.I0(riu_read_data[6]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[22]),
        .O(\riu2clb_vld_read_data[6]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[7]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[135]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[151]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[7]_i_3 
       (.I0(\riu2clb_vld_read_data[7]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[7]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[7]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[7]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[7]_i_4 
       (.I0(riu_read_data[103]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[119]),
        .O(\riu2clb_vld_read_data[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[7]_i_5 
       (.I0(riu_read_data[71]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[87]),
        .O(\riu2clb_vld_read_data[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[7]_i_6 
       (.I0(riu_read_data[39]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[55]),
        .O(\riu2clb_vld_read_data[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[7]_i_7 
       (.I0(riu_read_data[7]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[23]),
        .O(\riu2clb_vld_read_data[7]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[8]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[136]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[152]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[8]_i_3 
       (.I0(\riu2clb_vld_read_data[8]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[8]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[8]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[8]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[8]_i_4 
       (.I0(riu_read_data[104]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[120]),
        .O(\riu2clb_vld_read_data[8]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[8]_i_5 
       (.I0(riu_read_data[72]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[88]),
        .O(\riu2clb_vld_read_data[8]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[8]_i_6 
       (.I0(riu_read_data[40]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[56]),
        .O(\riu2clb_vld_read_data[8]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[8]_i_7 
       (.I0(riu_read_data[8]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[24]),
        .O(\riu2clb_vld_read_data[8]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00004540)) 
    \riu2clb_vld_read_data[9]_i_2 
       (.I0(riu_nibble_8[2]),
        .I1(riu_read_data[137]),
        .I2(\io_address_riuclk_reg[12] ),
        .I3(riu_read_data[153]),
        .I4(riu_nibble_8[1]),
        .O(\riu2clb_vld_read_data[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \riu2clb_vld_read_data[9]_i_3 
       (.I0(\riu2clb_vld_read_data[9]_i_4_n_0 ),
        .I1(\riu2clb_vld_read_data[9]_i_5_n_0 ),
        .I2(riu_nibble_8[2]),
        .I3(\riu2clb_vld_read_data[9]_i_6_n_0 ),
        .I4(riu_nibble_8[1]),
        .I5(\riu2clb_vld_read_data[9]_i_7_n_0 ),
        .O(\riu2clb_vld_read_data[9]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[9]_i_4 
       (.I0(riu_read_data[105]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[121]),
        .O(\riu2clb_vld_read_data[9]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[9]_i_5 
       (.I0(riu_read_data[73]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[89]),
        .O(\riu2clb_vld_read_data[9]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[9]_i_6 
       (.I0(riu_read_data[41]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[57]),
        .O(\riu2clb_vld_read_data[9]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAFB0000AA08)) 
    \riu2clb_vld_read_data[9]_i_7 
       (.I0(riu_read_data[9]),
        .I1(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I2(\riu2clb_vld_read_data[15]_i_8_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(\riu2clb_vld_read_data[15]_i_9_n_0 ),
        .I5(riu_read_data[25]),
        .O(\riu2clb_vld_read_data[9]_i_7_n_0 ));
  FDRE \riu2clb_vld_read_data_reg[0] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[0]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[0]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[0]_i_1 
       (.I0(\riu2clb_vld_read_data[0]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[0]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[0]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[10] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[10]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[10]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[10]_i_1 
       (.I0(\riu2clb_vld_read_data[10]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[10]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[10]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[11] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[11]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[11]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[11]_i_1 
       (.I0(\riu2clb_vld_read_data[11]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[11]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[11]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[12] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[12]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[12]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[12]_i_1 
       (.I0(\riu2clb_vld_read_data[12]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[12]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[12]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[13] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[13]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[13]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[13]_i_1 
       (.I0(\riu2clb_vld_read_data[13]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[13]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[13]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[14] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[14]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[14]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[14]_i_1 
       (.I0(\riu2clb_vld_read_data[14]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[14]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[14]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[15] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[15]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[15]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[15]_i_1 
       (.I0(\riu2clb_vld_read_data[15]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[15]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[15]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[1] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[1]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[1]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[1]_i_1 
       (.I0(\riu2clb_vld_read_data[1]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[1]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[1]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[2] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[2]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[2]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[2]_i_1 
       (.I0(\riu2clb_vld_read_data[2]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[2]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[2]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[3] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[3]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[3]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[3]_i_1 
       (.I0(\riu2clb_vld_read_data[3]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[3]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[3]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[4] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[4]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[4]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[4]_i_1 
       (.I0(\riu2clb_vld_read_data[4]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[4]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[4]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[5] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[5]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[5]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[5]_i_1 
       (.I0(\riu2clb_vld_read_data[5]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[5]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[5]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[6] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[6]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[6]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[6]_i_1 
       (.I0(\riu2clb_vld_read_data[6]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[6]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[6]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[7] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[7]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[7]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[7]_i_1 
       (.I0(\riu2clb_vld_read_data[7]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[7]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[7]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[8] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[8]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[8]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[8]_i_1 
       (.I0(\riu2clb_vld_read_data[8]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[8]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[8]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  FDRE \riu2clb_vld_read_data_reg[9] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(\riu2clb_vld_read_data_reg[9]_i_1_n_0 ),
        .Q(riu2clb_vld_read_data[9]),
        .R(1'b0));
  MUXF7 \riu2clb_vld_read_data_reg[9]_i_1 
       (.I0(\riu2clb_vld_read_data[9]_i_2_n_0 ),
        .I1(\riu2clb_vld_read_data[9]_i_3_n_0 ),
        .O(\riu2clb_vld_read_data_reg[9]_i_1_n_0 ),
        .S(\io_address_riuclk_reg[10] ));
  LUT6 #(
    .INIT(64'hFF00FF01FFFFFF01)) 
    \riu_addr_cal[0]_INST_0 
       (.I0(\riu_addr_cal[0]_INST_0_i_1_n_0 ),
        .I1(io_address_riuclk[12]),
        .I2(io_address_riuclk[13]),
        .I3(\riu_addr_cal[0]_INST_0_i_2_n_0 ),
        .I4(io_address_riuclk[0]),
        .I5(\riu_addr_cal[0]_INST_0_i_3_n_0 ),
        .O(riu_addr_cal[0]));
  LUT6 #(
    .INIT(64'h0000000000004445)) 
    \riu_addr_cal[0]_INST_0_i_1 
       (.I0(\io_address_riuclk_reg[19] ),
        .I1(\riu_addr_cal[0]_INST_0_i_4_n_0 ),
        .I2(io_address_riuclk[1]),
        .I3(io_address_riuclk[2]),
        .I4(\riu_addr_cal[0]_INST_0_i_5_n_0 ),
        .I5(\riu_addr_cal[0]_INST_0_i_6_n_0 ),
        .O(\riu_addr_cal[0]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEFEFEFEFFFFFFFF0)) 
    \riu_addr_cal[0]_INST_0_i_10 
       (.I0(io_address_riuclk[7]),
        .I1(io_address_riuclk[9]),
        .I2(io_address_riuclk[8]),
        .I3(io_address_riuclk[3]),
        .I4(io_address_riuclk[5]),
        .I5(\riu_addr_cal[4]_INST_0_i_12_n_0 ),
        .O(\riu_addr_cal[0]_INST_0_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFEC8FFFEFEC9)) 
    \riu_addr_cal[0]_INST_0_i_11 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[5]),
        .I3(io_address_riuclk[6]),
        .I4(io_address_riuclk[11]),
        .I5(io_address_riuclk[4]),
        .O(\riu_addr_cal[0]_INST_0_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT5 #(
    .INIT(32'hEEEEEEEF)) 
    \riu_addr_cal[0]_INST_0_i_12 
       (.I0(io_address_riuclk[7]),
        .I1(io_address_riuclk[8]),
        .I2(io_address_riuclk[14]),
        .I3(io_address_riuclk[15]),
        .I4(io_address_riuclk[16]),
        .O(\riu_addr_cal[0]_INST_0_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT4 #(
    .INIT(16'hA8AA)) 
    \riu_addr_cal[0]_INST_0_i_13 
       (.I0(io_address_riuclk[15]),
        .I1(io_address_riuclk[4]),
        .I2(io_address_riuclk[5]),
        .I3(io_address_riuclk[9]),
        .O(\riu_addr_cal[0]_INST_0_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \riu_addr_cal[0]_INST_0_i_14 
       (.I0(io_address_riuclk[5]),
        .I1(io_address_riuclk[11]),
        .I2(io_address_riuclk[14]),
        .O(\riu_addr_cal[0]_INST_0_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFCA8A8A8A8)) 
    \riu_addr_cal[0]_INST_0_i_15 
       (.I0(io_address_riuclk[6]),
        .I1(io_address_riuclk[14]),
        .I2(io_address_riuclk[15]),
        .I3(io_address_riuclk[12]),
        .I4(io_address_riuclk[0]),
        .I5(io_address_riuclk[13]),
        .O(\riu_addr_cal[0]_INST_0_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFCFCFCC8)) 
    \riu_addr_cal[0]_INST_0_i_2 
       (.I0(\riu_addr_cal[0]_INST_0_i_7_n_0 ),
        .I1(\riu_nibble_8[3]_INST_0_i_5_n_0 ),
        .I2(io_address_riuclk[12]),
        .I3(\io_address_riuclk_reg[19] ),
        .I4(io_address_riuclk[16]),
        .I5(\riu_addr_cal[0]_INST_0_i_8_n_0 ),
        .O(\riu_addr_cal[0]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FF08)) 
    \riu_addr_cal[0]_INST_0_i_3 
       (.I0(io_address_riuclk[16]),
        .I1(\riu_nibble_8[7]_INST_0_i_15_n_0 ),
        .I2(\riu_addr_cal[0]_INST_0_i_9_n_0 ),
        .I3(\riu_nibble_8[3]_INST_0_i_5_n_0 ),
        .I4(\riu_addr_cal[0]_INST_0_i_10_n_0 ),
        .I5(\io_address_riuclk_reg[19] ),
        .O(\riu_addr_cal[0]_INST_0_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    \riu_addr_cal[0]_INST_0_i_4 
       (.I0(io_address_riuclk[6]),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[9]),
        .I3(io_address_riuclk[5]),
        .O(\riu_addr_cal[0]_INST_0_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hC0C0CFFFCFFFC8C8)) 
    \riu_addr_cal[0]_INST_0_i_5 
       (.I0(\riu_nibble_8[0]_INST_0_i_7_n_0 ),
        .I1(io_address_riuclk[16]),
        .I2(io_address_riuclk[9]),
        .I3(io_address_riuclk[14]),
        .I4(io_address_riuclk[3]),
        .I5(io_address_riuclk[4]),
        .O(\riu_addr_cal[0]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFABAA)) 
    \riu_addr_cal[0]_INST_0_i_6 
       (.I0(\riu_addr_cal[0]_INST_0_i_11_n_0 ),
        .I1(\riu_nibble_8[0]_INST_0_i_7_n_0 ),
        .I2(io_address_riuclk[9]),
        .I3(io_address_riuclk[4]),
        .I4(\riu_addr_cal[0]_INST_0_i_12_n_0 ),
        .I5(\riu_addr_cal[0]_INST_0_i_13_n_0 ),
        .O(\riu_addr_cal[0]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFE2FAFFFFFAFA)) 
    \riu_addr_cal[0]_INST_0_i_7 
       (.I0(io_address_riuclk[15]),
        .I1(io_address_riuclk[9]),
        .I2(io_address_riuclk[11]),
        .I3(\io_address_riuclk_reg[4] ),
        .I4(io_address_riuclk[10]),
        .I5(\riu_addr_cal[0]_INST_0_i_14_n_0 ),
        .O(\riu_addr_cal[0]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF10101000)) 
    \riu_addr_cal[0]_INST_0_i_8 
       (.I0(io_address_riuclk[0]),
        .I1(io_address_riuclk[9]),
        .I2(io_address_riuclk[14]),
        .I3(io_address_riuclk[4]),
        .I4(io_address_riuclk[5]),
        .I5(\riu_addr_cal[0]_INST_0_i_15_n_0 ),
        .O(\riu_addr_cal[0]_INST_0_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT5 #(
    .INIT(32'hFFFFF0EF)) 
    \riu_addr_cal[0]_INST_0_i_9 
       (.I0(io_address_riuclk[2]),
        .I1(io_address_riuclk[1]),
        .I2(io_address_riuclk[7]),
        .I3(io_address_riuclk[4]),
        .I4(io_address_riuclk[6]),
        .O(\riu_addr_cal[0]_INST_0_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF000000FD)) 
    \riu_addr_cal[1]_INST_0 
       (.I0(\riu_addr_cal[1]_INST_0_i_1_n_0 ),
        .I1(\riu_addr_cal[1]_INST_0_i_2_n_0 ),
        .I2(\riu_addr_cal[1]_INST_0_i_3_n_0 ),
        .I3(io_address_riuclk[12]),
        .I4(io_address_riuclk[13]),
        .I5(\riu_addr_cal[1]_INST_0_i_4_n_0 ),
        .O(riu_addr_cal[1]));
  LUT6 #(
    .INIT(64'h777777777777777F)) 
    \riu_addr_cal[1]_INST_0_i_1 
       (.I0(io_address_riuclk[16]),
        .I1(io_address_riuclk[9]),
        .I2(io_address_riuclk[5]),
        .I3(io_address_riuclk[2]),
        .I4(io_address_riuclk[0]),
        .I5(\riu_addr_cal[1]_INST_0_i_5_n_0 ),
        .O(\riu_addr_cal[1]_INST_0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \riu_addr_cal[1]_INST_0_i_10 
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[9]),
        .O(\riu_addr_cal[1]_INST_0_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_addr_cal[1]_INST_0_i_11 
       (.I0(io_address_riuclk[11]),
        .I1(io_address_riuclk[10]),
        .O(\riu_addr_cal[1]_INST_0_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \riu_addr_cal[1]_INST_0_i_12 
       (.I0(io_address_riuclk[4]),
        .I1(\riu_addr_cal[1]_INST_0_i_11_n_0 ),
        .I2(io_address_riuclk[7]),
        .I3(io_address_riuclk[8]),
        .I4(io_address_riuclk[6]),
        .I5(io_address_riuclk[5]),
        .O(\riu_addr_cal[1]_INST_0_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFEEFFAAFFEEFAEE)) 
    \riu_addr_cal[1]_INST_0_i_13 
       (.I0(io_address_riuclk[15]),
        .I1(io_address_riuclk[1]),
        .I2(\riu_nibble_8[0]_INST_0_i_14_n_0 ),
        .I3(io_address_riuclk[14]),
        .I4(io_address_riuclk[13]),
        .I5(io_address_riuclk[16]),
        .O(\riu_addr_cal[1]_INST_0_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h0000010001000100)) 
    \riu_addr_cal[1]_INST_0_i_14 
       (.I0(io_address_riuclk[0]),
        .I1(io_address_riuclk[8]),
        .I2(io_address_riuclk[9]),
        .I3(io_address_riuclk[2]),
        .I4(io_address_riuclk[3]),
        .I5(io_address_riuclk[1]),
        .O(\riu_addr_cal[1]_INST_0_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \riu_addr_cal[1]_INST_0_i_15 
       (.I0(io_address_riuclk[11]),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[6]),
        .I3(io_address_riuclk[0]),
        .I4(io_address_riuclk[8]),
        .I5(io_address_riuclk[9]),
        .O(\riu_addr_cal[1]_INST_0_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \riu_addr_cal[1]_INST_0_i_16 
       (.I0(io_address_riuclk[7]),
        .I1(io_address_riuclk[4]),
        .I2(io_address_riuclk[0]),
        .I3(io_address_riuclk[3]),
        .O(\riu_addr_cal[1]_INST_0_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \riu_addr_cal[1]_INST_0_i_17 
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[11]),
        .O(\riu_addr_cal[1]_INST_0_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \riu_addr_cal[1]_INST_0_i_18 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[3]),
        .I2(io_address_riuclk[0]),
        .I3(io_address_riuclk[4]),
        .I4(io_address_riuclk[6]),
        .I5(io_address_riuclk[7]),
        .O(\riu_addr_cal[1]_INST_0_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFAEAF)) 
    \riu_addr_cal[1]_INST_0_i_2 
       (.I0(\riu_addr_cal[1]_INST_0_i_6_n_0 ),
        .I1(io_address_riuclk[8]),
        .I2(io_address_riuclk[14]),
        .I3(io_address_riuclk[16]),
        .I4(\riu_addr_cal[1]_INST_0_i_7_n_0 ),
        .I5(\riu_addr_cal[1]_INST_0_i_8_n_0 ),
        .O(\riu_addr_cal[1]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000DDDDD0D7)) 
    \riu_addr_cal[1]_INST_0_i_3 
       (.I0(\riu_addr_cal[1]_INST_0_i_9_n_0 ),
        .I1(io_address_riuclk[5]),
        .I2(\riu_nibble_8[3]_INST_0_i_10_n_0 ),
        .I3(\riu_addr_cal[1]_INST_0_i_10_n_0 ),
        .I4(\riu_addr_cal[1]_INST_0_i_11_n_0 ),
        .I5(\riu_addr_cal[1]_INST_0_i_12_n_0 ),
        .O(\riu_addr_cal[1]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFCFCFCFCFEFEFEEE)) 
    \riu_addr_cal[1]_INST_0_i_4 
       (.I0(\io_address_riuclk_reg[19] ),
        .I1(\riu_addr_cal[1]_INST_0_i_13_n_0 ),
        .I2(io_address_riuclk[12]),
        .I3(io_address_riuclk[14]),
        .I4(io_address_riuclk[16]),
        .I5(io_address_riuclk[13]),
        .O(\riu_addr_cal[1]_INST_0_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_addr_cal[1]_INST_0_i_5 
       (.I0(io_address_riuclk[3]),
        .I1(io_address_riuclk[4]),
        .O(\riu_addr_cal[1]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF2300EF00)) 
    \riu_addr_cal[1]_INST_0_i_6 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[8]),
        .I2(io_address_riuclk[4]),
        .I3(io_address_riuclk[1]),
        .I4(io_address_riuclk[0]),
        .I5(\riu_addr_cal[1]_INST_0_i_14_n_0 ),
        .O(\riu_addr_cal[1]_INST_0_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT5 #(
    .INIT(32'h00900000)) 
    \riu_addr_cal[1]_INST_0_i_7 
       (.I0(io_address_riuclk[2]),
        .I1(io_address_riuclk[3]),
        .I2(io_address_riuclk[1]),
        .I3(io_address_riuclk[8]),
        .I4(io_address_riuclk[0]),
        .O(\riu_addr_cal[1]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000540100005400)) 
    \riu_addr_cal[1]_INST_0_i_8 
       (.I0(io_address_riuclk[1]),
        .I1(io_address_riuclk[3]),
        .I2(io_address_riuclk[8]),
        .I3(io_address_riuclk[0]),
        .I4(io_address_riuclk[9]),
        .I5(io_address_riuclk[4]),
        .O(\riu_addr_cal[1]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h111F111F111FFFFF)) 
    \riu_addr_cal[1]_INST_0_i_9 
       (.I0(\riu_addr_cal[1]_INST_0_i_15_n_0 ),
        .I1(\riu_addr_cal[1]_INST_0_i_5_n_0 ),
        .I2(\io_address_riuclk_reg[9] ),
        .I3(\riu_addr_cal[1]_INST_0_i_16_n_0 ),
        .I4(\riu_addr_cal[1]_INST_0_i_17_n_0 ),
        .I5(\riu_addr_cal[1]_INST_0_i_18_n_0 ),
        .O(\riu_addr_cal[1]_INST_0_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF10001111)) 
    \riu_addr_cal[2]_INST_0 
       (.I0(\riu_addr_cal[2]_INST_0_i_1_n_0 ),
        .I1(io_address_riuclk[12]),
        .I2(io_address_riuclk[8]),
        .I3(io_address_riuclk[14]),
        .I4(io_address_riuclk[13]),
        .I5(\riu_addr_cal[2]_INST_0_i_2_n_0 ),
        .O(riu_addr_cal[2]));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \riu_addr_cal[2]_INST_0_i_1 
       (.I0(\riu_addr_cal[2]_INST_0_i_3_n_0 ),
        .I1(\riu_addr_cal[2]_INST_0_i_4_n_0 ),
        .I2(\riu_addr_cal[2]_INST_0_i_5_n_0 ),
        .I3(\riu_addr_cal[2]_INST_0_i_6_n_0 ),
        .I4(\riu_addr_cal[2]_INST_0_i_7_n_0 ),
        .I5(\io_address_riuclk_reg[19] ),
        .O(\riu_addr_cal[2]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEAF)) 
    \riu_addr_cal[2]_INST_0_i_10 
       (.I0(io_address_riuclk[2]),
        .I1(io_address_riuclk[16]),
        .I2(io_address_riuclk[13]),
        .I3(io_address_riuclk[12]),
        .I4(io_address_riuclk[14]),
        .I5(io_address_riuclk[15]),
        .O(\riu_addr_cal[2]_INST_0_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \riu_addr_cal[2]_INST_0_i_11 
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[14]),
        .O(\riu_addr_cal[2]_INST_0_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFE0000)) 
    \riu_addr_cal[2]_INST_0_i_12 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[16]),
        .I2(io_address_riuclk[3]),
        .I3(io_address_riuclk[4]),
        .I4(io_address_riuclk[14]),
        .I5(io_address_riuclk[8]),
        .O(\riu_addr_cal[2]_INST_0_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT4 #(
    .INIT(16'h1404)) 
    \riu_addr_cal[2]_INST_0_i_13 
       (.I0(io_address_riuclk[0]),
        .I1(io_address_riuclk[3]),
        .I2(io_address_riuclk[4]),
        .I3(io_address_riuclk[2]),
        .O(\riu_addr_cal[2]_INST_0_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT5 #(
    .INIT(32'h0000000E)) 
    \riu_addr_cal[2]_INST_0_i_14 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[0]),
        .I3(io_address_riuclk[2]),
        .I4(io_address_riuclk[1]),
        .O(\riu_addr_cal[2]_INST_0_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hD080FFFFD080D080)) 
    \riu_addr_cal[2]_INST_0_i_2 
       (.I0(io_address_riuclk[12]),
        .I1(\io_address_riuclk_reg[19] ),
        .I2(\riu_addr_cal[2]_INST_0_i_8_n_0 ),
        .I3(io_address_riuclk[15]),
        .I4(\riu_addr_cal[2]_INST_0_i_9_n_0 ),
        .I5(\riu_addr_cal[2]_INST_0_i_10_n_0 ),
        .O(\riu_addr_cal[2]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000006F)) 
    \riu_addr_cal[2]_INST_0_i_3 
       (.I0(io_address_riuclk[1]),
        .I1(io_address_riuclk[13]),
        .I2(\riu_addr_cal[2]_INST_0_i_11_n_0 ),
        .I3(\riu_addr_cal[2]_INST_0_i_12_n_0 ),
        .I4(\riu_addr_cal[2]_INST_0_i_13_n_0 ),
        .I5(\riu_addr_cal[3]_INST_0_i_9_n_0 ),
        .O(\riu_addr_cal[2]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFAA0A1FFFEA0A1)) 
    \riu_addr_cal[2]_INST_0_i_4 
       (.I0(io_address_riuclk[10]),
        .I1(io_address_riuclk[8]),
        .I2(io_address_riuclk[11]),
        .I3(io_address_riuclk[9]),
        .I4(io_address_riuclk[4]),
        .I5(io_address_riuclk[0]),
        .O(\riu_addr_cal[2]_INST_0_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF50FF101010)) 
    \riu_addr_cal[2]_INST_0_i_5 
       (.I0(\riu_addr_cal[2]_INST_0_i_14_n_0 ),
        .I1(io_address_riuclk[4]),
        .I2(io_address_riuclk[16]),
        .I3(io_address_riuclk[9]),
        .I4(\riu_addr_cal[1]_INST_0_i_11_n_0 ),
        .I5(io_address_riuclk[8]),
        .O(\riu_addr_cal[2]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00003C0E00000000)) 
    \riu_addr_cal[2]_INST_0_i_6 
       (.I0(io_address_riuclk[0]),
        .I1(io_address_riuclk[1]),
        .I2(io_address_riuclk[2]),
        .I3(io_address_riuclk[3]),
        .I4(io_address_riuclk[8]),
        .I5(io_address_riuclk[4]),
        .O(\riu_addr_cal[2]_INST_0_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'h08088880)) 
    \riu_addr_cal[2]_INST_0_i_7 
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[14]),
        .I2(io_address_riuclk[0]),
        .I3(io_address_riuclk[2]),
        .I4(io_address_riuclk[1]),
        .O(\riu_addr_cal[2]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \riu_addr_cal[2]_INST_0_i_8 
       (.I0(io_address_riuclk[12]),
        .I1(io_address_riuclk[14]),
        .I2(\riu_nibble_8[0]_INST_0_i_14_n_0 ),
        .I3(\riu_addr_cal[1]_INST_0_i_5_n_0 ),
        .I4(io_address_riuclk[10]),
        .I5(io_address_riuclk[16]),
        .O(\riu_addr_cal[2]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0005000700000007)) 
    \riu_addr_cal[2]_INST_0_i_9 
       (.I0(io_address_riuclk[5]),
        .I1(\riu_nibble_8[3]_INST_0_i_8_n_0 ),
        .I2(io_address_riuclk[12]),
        .I3(\riu_nibble_8[3]_INST_0_i_10_n_0 ),
        .I4(io_address_riuclk[13]),
        .I5(\riu_addr_cal[2]_INST_0_i_11_n_0 ),
        .O(\riu_addr_cal[2]_INST_0_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF0D)) 
    \riu_addr_cal[3]_INST_0 
       (.I0(\riu_addr_cal[3]_INST_0_i_1_n_0 ),
        .I1(\riu_addr_cal[3]_INST_0_i_2_n_0 ),
        .I2(\riu_addr_cal[3]_INST_0_i_3_n_0 ),
        .I3(\riu_addr_cal[3]_INST_0_i_4_n_0 ),
        .I4(\riu_addr_cal[3]_INST_0_i_5_n_0 ),
        .I5(\riu_addr_cal[3]_INST_0_i_6_n_0 ),
        .O(riu_addr_cal[3]));
  LUT6 #(
    .INIT(64'h0000000004040004)) 
    \riu_addr_cal[3]_INST_0_i_1 
       (.I0(\riu_addr_cal[3]_INST_0_i_7_n_0 ),
        .I1(\riu_addr_cal[3]_INST_0_i_8_n_0 ),
        .I2(\riu_addr_cal[3]_INST_0_i_9_n_0 ),
        .I3(io_address_riuclk[8]),
        .I4(io_address_riuclk[0]),
        .I5(\riu_addr_cal[3]_INST_0_i_10_n_0 ),
        .O(\riu_addr_cal[3]_INST_0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT5 #(
    .INIT(32'h44444440)) 
    \riu_addr_cal[3]_INST_0_i_10 
       (.I0(io_address_riuclk[4]),
        .I1(io_address_riuclk[16]),
        .I2(io_address_riuclk[0]),
        .I3(io_address_riuclk[2]),
        .I4(io_address_riuclk[1]),
        .O(\riu_addr_cal[3]_INST_0_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT4 #(
    .INIT(16'h4414)) 
    \riu_addr_cal[3]_INST_0_i_11 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[2]),
        .I2(io_address_riuclk[3]),
        .I3(io_address_riuclk[1]),
        .O(\riu_addr_cal[3]_INST_0_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT5 #(
    .INIT(32'hEFFFFFFE)) 
    \riu_addr_cal[3]_INST_0_i_12 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[11]),
        .I2(io_address_riuclk[8]),
        .I3(io_address_riuclk[1]),
        .I4(io_address_riuclk[14]),
        .O(\riu_addr_cal[3]_INST_0_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    \riu_addr_cal[3]_INST_0_i_13 
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[14]),
        .I3(io_address_riuclk[3]),
        .O(\riu_addr_cal[3]_INST_0_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hBABFBEBFBFBFBABF)) 
    \riu_addr_cal[3]_INST_0_i_14 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[0]),
        .I2(io_address_riuclk[3]),
        .I3(io_address_riuclk[2]),
        .I4(io_address_riuclk[9]),
        .I5(io_address_riuclk[4]),
        .O(\riu_addr_cal[3]_INST_0_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_addr_cal[3]_INST_0_i_15 
       (.I0(io_address_riuclk[18]),
        .I1(io_address_riuclk[19]),
        .O(\riu_addr_cal[3]_INST_0_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \riu_addr_cal[3]_INST_0_i_16 
       (.I0(io_address_riuclk[12]),
        .I1(io_address_riuclk[14]),
        .I2(io_address_riuclk[15]),
        .I3(io_address_riuclk[16]),
        .I4(io_address_riuclk[13]),
        .O(\riu_addr_cal[3]_INST_0_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hCC8FCC8FCC8FCC88)) 
    \riu_addr_cal[3]_INST_0_i_17 
       (.I0(io_address_riuclk[16]),
        .I1(io_address_riuclk[14]),
        .I2(io_address_riuclk[12]),
        .I3(io_address_riuclk[13]),
        .I4(io_address_riuclk[6]),
        .I5(io_address_riuclk[7]),
        .O(\riu_addr_cal[3]_INST_0_i_17_n_0 ));
  LUT5 #(
    .INIT(32'h11D1FFFF)) 
    \riu_addr_cal[3]_INST_0_i_2 
       (.I0(\riu_addr_cal[3]_INST_0_i_11_n_0 ),
        .I1(\io_address_riuclk_reg[9] ),
        .I2(\riu_addr_cal[3]_INST_0_i_12_n_0 ),
        .I3(\riu_addr_cal[3]_INST_0_i_13_n_0 ),
        .I4(\riu_addr_cal[3]_INST_0_i_14_n_0 ),
        .O(\riu_addr_cal[3]_INST_0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_addr_cal[3]_INST_0_i_3 
       (.I0(io_address_riuclk[12]),
        .I1(io_address_riuclk[13]),
        .O(\riu_addr_cal[3]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFFFFFE)) 
    \riu_addr_cal[3]_INST_0_i_4 
       (.I0(\riu_nibble_8[3]_INST_0_i_13_n_0 ),
        .I1(io_address_riuclk[17]),
        .I2(io_address_riuclk[20]),
        .I3(\riu_addr_cal[3]_INST_0_i_15_n_0 ),
        .I4(\riu_nibble_8[3]_INST_0_i_12_n_0 ),
        .I5(io_address_riuclk[13]),
        .O(\riu_addr_cal[3]_INST_0_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAAABA)) 
    \riu_addr_cal[3]_INST_0_i_5 
       (.I0(\riu_addr_cal[3]_INST_0_i_16_n_0 ),
        .I1(io_address_riuclk[8]),
        .I2(io_address_riuclk[5]),
        .I3(\riu_addr_cal[3]_INST_0_i_3_n_0 ),
        .I4(\riu_addr_cal[4]_INST_0_i_12_n_0 ),
        .I5(\riu_addr_cal[3]_INST_0_i_17_n_0 ),
        .O(\riu_addr_cal[3]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFCCFDCFFF00FD00)) 
    \riu_addr_cal[3]_INST_0_i_6 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[13]),
        .I2(io_address_riuclk[14]),
        .I3(io_address_riuclk[15]),
        .I4(io_address_riuclk[16]),
        .I5(io_address_riuclk[3]),
        .O(\riu_addr_cal[3]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF0001000100)) 
    \riu_addr_cal[3]_INST_0_i_7 
       (.I0(io_address_riuclk[4]),
        .I1(io_address_riuclk[8]),
        .I2(io_address_riuclk[9]),
        .I3(io_address_riuclk[3]),
        .I4(io_address_riuclk[0]),
        .I5(io_address_riuclk[10]),
        .O(\riu_addr_cal[3]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0F0F0FFF0E0E0F0F)) 
    \riu_addr_cal[3]_INST_0_i_8 
       (.I0(io_address_riuclk[2]),
        .I1(io_address_riuclk[3]),
        .I2(io_address_riuclk[11]),
        .I3(io_address_riuclk[9]),
        .I4(io_address_riuclk[4]),
        .I5(io_address_riuclk[14]),
        .O(\riu_addr_cal[3]_INST_0_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \riu_addr_cal[3]_INST_0_i_9 
       (.I0(io_address_riuclk[16]),
        .I1(io_address_riuclk[15]),
        .I2(io_address_riuclk[14]),
        .O(\riu_addr_cal[3]_INST_0_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFEFFFFFFFE)) 
    \riu_addr_cal[4]_INST_0 
       (.I0(\riu_addr_cal[4]_INST_0_i_1_n_0 ),
        .I1(\riu_addr_cal[4]_INST_0_i_2_n_0 ),
        .I2(\riu_addr_cal[4]_INST_0_i_3_n_0 ),
        .I3(\riu_addr_cal[4]_INST_0_i_4_n_0 ),
        .I4(\riu_addr_cal[4]_INST_0_i_5_n_0 ),
        .I5(\riu_addr_cal[4]_INST_0_i_6_n_0 ),
        .O(riu_addr_cal[4]));
  LUT6 #(
    .INIT(64'h5555551055555555)) 
    \riu_addr_cal[4]_INST_0_i_1 
       (.I0(\riu_addr_cal[3]_INST_0_i_3_n_0 ),
        .I1(\riu_addr_cal[4]_INST_0_i_7_n_0 ),
        .I2(\riu_addr_cal[4]_INST_0_i_8_n_0 ),
        .I3(\riu_addr_cal[4]_INST_0_i_9_n_0 ),
        .I4(\riu_addr_cal[4]_INST_0_i_10_n_0 ),
        .I5(\riu_addr_cal[4]_INST_0_i_11_n_0 ),
        .O(\riu_addr_cal[4]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888000AAAAAAAA)) 
    \riu_addr_cal[4]_INST_0_i_10 
       (.I0(io_address_riuclk[0]),
        .I1(io_address_riuclk[1]),
        .I2(\riu_addr_cal[1]_INST_0_i_5_n_0 ),
        .I3(io_address_riuclk[8]),
        .I4(io_address_riuclk[5]),
        .I5(\riu_addr_cal[4]_INST_0_i_19_n_0 ),
        .O(\riu_addr_cal[4]_INST_0_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT5 #(
    .INIT(32'hFFFFF6FF)) 
    \riu_addr_cal[4]_INST_0_i_11 
       (.I0(io_address_riuclk[2]),
        .I1(io_address_riuclk[1]),
        .I2(io_address_riuclk[0]),
        .I3(io_address_riuclk[3]),
        .I4(io_address_riuclk[8]),
        .O(\riu_addr_cal[4]_INST_0_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \riu_addr_cal[4]_INST_0_i_12 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[11]),
        .O(\riu_addr_cal[4]_INST_0_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \riu_addr_cal[4]_INST_0_i_13 
       (.I0(\riu_nibble_8[3]_INST_0_i_12_n_0 ),
        .I1(\riu_nibble_8[7]_INST_0_i_21_n_0 ),
        .I2(\riu_nibble_8[3]_INST_0_i_13_n_0 ),
        .I3(io_address_riuclk[16]),
        .I4(io_address_riuclk[14]),
        .I5(io_address_riuclk[15]),
        .O(\riu_addr_cal[4]_INST_0_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT4 #(
    .INIT(16'hF9FF)) 
    \riu_addr_cal[4]_INST_0_i_14 
       (.I0(io_address_riuclk[15]),
        .I1(io_address_riuclk[14]),
        .I2(io_address_riuclk[13]),
        .I3(io_address_riuclk[8]),
        .O(\riu_addr_cal[4]_INST_0_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT5 #(
    .INIT(32'hFFFEFFF8)) 
    \riu_addr_cal[4]_INST_0_i_15 
       (.I0(io_address_riuclk[11]),
        .I1(io_address_riuclk[7]),
        .I2(io_address_riuclk[10]),
        .I3(io_address_riuclk[8]),
        .I4(io_address_riuclk[6]),
        .O(\riu_addr_cal[4]_INST_0_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    \riu_addr_cal[4]_INST_0_i_16 
       (.I0(io_address_riuclk[10]),
        .I1(io_address_riuclk[6]),
        .I2(io_address_riuclk[7]),
        .I3(io_address_riuclk[11]),
        .I4(io_address_riuclk[14]),
        .I5(io_address_riuclk[8]),
        .O(\riu_addr_cal[4]_INST_0_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \riu_addr_cal[4]_INST_0_i_17 
       (.I0(io_address_riuclk[10]),
        .I1(io_address_riuclk[11]),
        .I2(io_address_riuclk[7]),
        .I3(io_address_riuclk[8]),
        .O(\riu_addr_cal[4]_INST_0_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT5 #(
    .INIT(32'hFFFCFDFF)) 
    \riu_addr_cal[4]_INST_0_i_18 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[3]),
        .I2(io_address_riuclk[7]),
        .I3(io_address_riuclk[10]),
        .I4(io_address_riuclk[8]),
        .O(\riu_addr_cal[4]_INST_0_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBA)) 
    \riu_addr_cal[4]_INST_0_i_19 
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[2]),
        .I2(io_address_riuclk[4]),
        .I3(io_address_riuclk[3]),
        .I4(io_address_riuclk[10]),
        .I5(io_address_riuclk[7]),
        .O(\riu_addr_cal[4]_INST_0_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAA888888888)) 
    \riu_addr_cal[4]_INST_0_i_2 
       (.I0(io_address_riuclk[14]),
        .I1(\riu_nibble_8[3]_INST_0_i_10_n_0 ),
        .I2(io_address_riuclk[3]),
        .I3(io_address_riuclk[1]),
        .I4(io_address_riuclk[10]),
        .I5(io_address_riuclk[13]),
        .O(\riu_addr_cal[4]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF0EFF0F0F0E0)) 
    \riu_addr_cal[4]_INST_0_i_3 
       (.I0(io_address_riuclk[16]),
        .I1(io_address_riuclk[15]),
        .I2(io_address_riuclk[12]),
        .I3(io_address_riuclk[13]),
        .I4(io_address_riuclk[14]),
        .I5(io_address_riuclk[9]),
        .O(\riu_addr_cal[4]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hA888AAAAA8000000)) 
    \riu_addr_cal[4]_INST_0_i_4 
       (.I0(\riu_addr_cal[4]_INST_0_i_12_n_0 ),
        .I1(io_address_riuclk[13]),
        .I2(io_address_riuclk[1]),
        .I3(io_address_riuclk[0]),
        .I4(io_address_riuclk[8]),
        .I5(io_address_riuclk[4]),
        .O(\riu_addr_cal[4]_INST_0_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFD0FF)) 
    \riu_addr_cal[4]_INST_0_i_5 
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[2]),
        .I2(io_address_riuclk[13]),
        .I3(\riu_addr_cal[4]_INST_0_i_13_n_0 ),
        .I4(io_address_riuclk[11]),
        .I5(io_address_riuclk[5]),
        .O(\riu_addr_cal[4]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h04040404151505FF)) 
    \riu_addr_cal[4]_INST_0_i_6 
       (.I0(\riu_nibble_8[3]_INST_0_i_5_n_0 ),
        .I1(io_address_riuclk[13]),
        .I2(io_address_riuclk[4]),
        .I3(\riu_addr_cal[4]_INST_0_i_14_n_0 ),
        .I4(io_address_riuclk[16]),
        .I5(\io_address_riuclk_reg[19] ),
        .O(\riu_addr_cal[4]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000000001FE)) 
    \riu_addr_cal[4]_INST_0_i_7 
       (.I0(io_address_riuclk[11]),
        .I1(io_address_riuclk[7]),
        .I2(io_address_riuclk[6]),
        .I3(io_address_riuclk[5]),
        .I4(\riu_addr_cal[4]_INST_0_i_15_n_0 ),
        .I5(\io_address_riuclk_reg[2]_0 ),
        .O(\riu_addr_cal[4]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAAA2AAA2AAA2AA80)) 
    \riu_addr_cal[4]_INST_0_i_8 
       (.I0(\riu_addr_cal[4]_INST_0_i_16_n_0 ),
        .I1(io_address_riuclk[4]),
        .I2(\riu_addr_cal[4]_INST_0_i_17_n_0 ),
        .I3(\riu_nibble_8[2]_INST_0_i_22_n_0 ),
        .I4(io_address_riuclk[11]),
        .I5(\riu_addr_cal[4]_INST_0_i_18_n_0 ),
        .O(\riu_addr_cal[4]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h00001111000F1111)) 
    \riu_addr_cal[4]_INST_0_i_9 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[15]),
        .I2(io_address_riuclk[7]),
        .I3(io_address_riuclk[4]),
        .I4(io_address_riuclk[16]),
        .I5(\io_address_riuclk_reg[1] ),
        .O(\riu_addr_cal[4]_INST_0_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h0001000100010000)) 
    \riu_addr_cal[5]_INST_0 
       (.I0(\io_address_riuclk_reg[16] ),
        .I1(\riu_addr_cal[5]_INST_0_i_1_n_0 ),
        .I2(\riu_addr_cal[5]_INST_0_i_2_n_0 ),
        .I3(\riu_addr_cal[5]_INST_0_i_3_n_0 ),
        .I4(\io_address_riuclk_reg[5] ),
        .I5(\riu_addr_cal[5]_INST_0_i_5_n_0 ),
        .O(riu_addr_cal[5]));
  LUT6 #(
    .INIT(64'h010101FF01010101)) 
    \riu_addr_cal[5]_INST_0_i_1 
       (.I0(\io_address_riuclk_reg[26] ),
        .I1(\riu_nibble_8[6]_INST_0_i_7_n_0 ),
        .I2(io_address_riuclk[13]),
        .I3(\riu_addr_cal[5]_INST_0_i_6_n_0 ),
        .I4(\riu_addr_cal[5]_INST_0_i_7_n_0 ),
        .I5(\riu_nibble_8[7]_INST_0_i_9_n_0 ),
        .O(\riu_addr_cal[5]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFFFFFF)) 
    \riu_addr_cal[5]_INST_0_i_10 
       (.I0(\riu_nibble_8[2]_INST_0_i_20_n_0 ),
        .I1(\riu_nibble_8[7]_INST_0_i_13_n_0 ),
        .I2(\riu_nibble_8[7]_INST_0_i_19_n_0 ),
        .I3(\io_address_riuclk_reg[5] ),
        .I4(io_address_riuclk[1]),
        .I5(io_address_riuclk[8]),
        .O(\riu_addr_cal[5]_INST_0_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \riu_addr_cal[5]_INST_0_i_11 
       (.I0(io_address_riuclk[2]),
        .I1(io_address_riuclk[0]),
        .I2(io_address_riuclk[1]),
        .I3(io_address_riuclk[3]),
        .O(\io_address_riuclk_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \riu_addr_cal[5]_INST_0_i_12 
       (.I0(io_address_riuclk[4]),
        .I1(io_address_riuclk[7]),
        .O(\io_address_riuclk_reg[4] ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \riu_addr_cal[5]_INST_0_i_13 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[4]),
        .I2(\riu_nibble_8[7]_INST_0_i_19_n_0 ),
        .I3(io_address_riuclk[6]),
        .I4(io_address_riuclk[7]),
        .O(\riu_addr_cal[5]_INST_0_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \riu_addr_cal[5]_INST_0_i_14 
       (.I0(\riu_addr_cal[5]_INST_0_i_16_n_0 ),
        .I1(io_address_riuclk[1]),
        .I2(io_address_riuclk[13]),
        .I3(\riu_nibble_8[3]_INST_0_i_12_n_0 ),
        .I4(\riu_nibble_8[7]_INST_0_i_21_n_0 ),
        .I5(\riu_nibble_8[3]_INST_0_i_13_n_0 ),
        .O(\riu_addr_cal[5]_INST_0_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_addr_cal[5]_INST_0_i_15 
       (.I0(io_address_riuclk[3]),
        .I1(io_address_riuclk[5]),
        .O(\riu_addr_cal[5]_INST_0_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT5 #(
    .INIT(32'h00000004)) 
    \riu_addr_cal[5]_INST_0_i_16 
       (.I0(io_address_riuclk[2]),
        .I1(io_address_riuclk[16]),
        .I2(io_address_riuclk[12]),
        .I3(io_address_riuclk[15]),
        .I4(io_address_riuclk[0]),
        .O(\riu_addr_cal[5]_INST_0_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000075)) 
    \riu_addr_cal[5]_INST_0_i_2 
       (.I0(\riu_addr_cal[5]_INST_0_i_8_n_0 ),
        .I1(io_address_riuclk[20]),
        .I2(\riu_addr_cal[5]_INST_0_i_9_n_0 ),
        .I3(io_address_riuclk[5]),
        .I4(io_address_riuclk[15]),
        .I5(\riu_nibble_8[6]_INST_0_i_6_n_0 ),
        .O(\riu_addr_cal[5]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000001F000000)) 
    \riu_addr_cal[5]_INST_0_i_3 
       (.I0(\riu_nibble_8[7]_INST_0_i_7_n_0 ),
        .I1(\riu_addr_cal[3]_INST_0_i_3_n_0 ),
        .I2(\riu_addr_cal[5]_INST_0_i_10_n_0 ),
        .I3(\riu_nibble_8[7]_INST_0_i_9_n_0 ),
        .I4(io_address_riuclk[14]),
        .I5(io_address_riuclk[15]),
        .O(\riu_addr_cal[5]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \riu_addr_cal[5]_INST_0_i_4 
       (.I0(io_address_riuclk[5]),
        .I1(io_address_riuclk[9]),
        .I2(io_address_riuclk[11]),
        .I3(io_address_riuclk[8]),
        .I4(io_address_riuclk[10]),
        .I5(io_address_riuclk[6]),
        .O(\io_address_riuclk_reg[5] ));
  LUT6 #(
    .INIT(64'hFFEF0000FFEFFFEF)) 
    \riu_addr_cal[5]_INST_0_i_5 
       (.I0(\io_address_riuclk_reg[26] ),
        .I1(\io_address_riuclk_reg[2] ),
        .I2(\io_address_riuclk_reg[4] ),
        .I3(io_address_riuclk[13]),
        .I4(\riu_addr_cal[5]_INST_0_i_13_n_0 ),
        .I5(\riu_addr_cal[5]_INST_0_i_14_n_0 ),
        .O(\riu_addr_cal[5]_INST_0_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \riu_addr_cal[5]_INST_0_i_6 
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[11]),
        .I2(io_address_riuclk[10]),
        .I3(io_address_riuclk[9]),
        .O(\riu_addr_cal[5]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \riu_addr_cal[5]_INST_0_i_7 
       (.I0(\riu_nibble_8[7]_INST_0_i_13_n_0 ),
        .I1(\riu_addr_cal[1]_INST_0_i_11_n_0 ),
        .I2(\riu_addr_cal[5]_INST_0_i_15_n_0 ),
        .I3(io_address_riuclk[13]),
        .I4(io_address_riuclk[15]),
        .I5(io_address_riuclk[14]),
        .O(\riu_addr_cal[5]_INST_0_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \riu_addr_cal[5]_INST_0_i_8 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[13]),
        .O(\riu_addr_cal[5]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \riu_addr_cal[5]_INST_0_i_9 
       (.I0(io_address_riuclk[17]),
        .I1(\riu_nibble_8[3]_INST_0_i_12_n_0 ),
        .I2(\riu_nibble_8[3]_INST_0_i_13_n_0 ),
        .I3(io_address_riuclk[18]),
        .I4(io_address_riuclk[19]),
        .I5(io_address_riuclk[14]),
        .O(\riu_addr_cal[5]_INST_0_i_9_n_0 ));
  (* KEEP = "yes" *) 
  FDRE riu_clk_rst_r1_reg
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu_clk_rst),
        .Q(riu_clk_rst_r1),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8F888F8F8F888F88)) 
    \riu_nibble_8[0]_INST_0 
       (.I0(io_address_riuclk[6]),
        .I1(\io_address_riuclk_reg[14] ),
        .I2(\riu_nibble_8[0]_INST_0_i_1_n_0 ),
        .I3(io_address_riuclk[15]),
        .I4(\riu_nibble_8[0]_INST_0_i_2_n_0 ),
        .I5(\riu_nibble_8[0]_INST_0_i_3_n_0 ),
        .O(riu_nibble_8[0]));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT4 #(
    .INIT(16'hFFAE)) 
    \riu_nibble_8[0]_INST_0_i_1 
       (.I0(\riu_nibble_8[0]_INST_0_i_4_n_0 ),
        .I1(io_address_riuclk[15]),
        .I2(\riu_nibble_8[0]_INST_0_i_5_n_0 ),
        .I3(\io_address_riuclk_reg[19] ),
        .O(\riu_nibble_8[0]_INST_0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT5 #(
    .INIT(32'hEEEFEFFE)) 
    \riu_nibble_8[0]_INST_0_i_10 
       (.I0(io_address_riuclk[5]),
        .I1(io_address_riuclk[7]),
        .I2(io_address_riuclk[9]),
        .I3(io_address_riuclk[8]),
        .I4(io_address_riuclk[10]),
        .O(\riu_nibble_8[0]_INST_0_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \riu_nibble_8[0]_INST_0_i_11 
       (.I0(io_address_riuclk[11]),
        .I1(io_address_riuclk[6]),
        .O(\riu_nibble_8[0]_INST_0_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \riu_nibble_8[0]_INST_0_i_12 
       (.I0(io_address_riuclk[16]),
        .I1(io_address_riuclk[14]),
        .O(\riu_nibble_8[0]_INST_0_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0000040000000000)) 
    \riu_nibble_8[0]_INST_0_i_13 
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[1]),
        .I2(io_address_riuclk[5]),
        .I3(io_address_riuclk[16]),
        .I4(io_address_riuclk[9]),
        .I5(io_address_riuclk[4]),
        .O(\riu_nibble_8[0]_INST_0_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \riu_nibble_8[0]_INST_0_i_14 
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[9]),
        .O(\riu_nibble_8[0]_INST_0_i_14_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \riu_nibble_8[0]_INST_0_i_15 
       (.I0(io_address_riuclk[10]),
        .I1(io_address_riuclk[9]),
        .O(\riu_nibble_8[0]_INST_0_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'hABFB)) 
    \riu_nibble_8[0]_INST_0_i_16 
       (.I0(io_address_riuclk[4]),
        .I1(io_address_riuclk[16]),
        .I2(io_address_riuclk[13]),
        .I3(io_address_riuclk[14]),
        .O(\riu_nibble_8[0]_INST_0_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h8AAA8A888AAA8AAA)) 
    \riu_nibble_8[0]_INST_0_i_2 
       (.I0(\riu_nibble_8[0]_INST_0_i_6_n_0 ),
        .I1(\riu_nibble_8[0]_INST_0_i_7_n_0 ),
        .I2(\riu_nibble_8[0]_INST_0_i_8_n_0 ),
        .I3(io_address_riuclk[3]),
        .I4(\riu_nibble_8[0]_INST_0_i_9_n_0 ),
        .I5(\riu_nibble_8[0]_INST_0_i_10_n_0 ),
        .O(\riu_nibble_8[0]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFEF00EFEFFFFF)) 
    \riu_nibble_8[0]_INST_0_i_3 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[8]),
        .I2(io_address_riuclk[3]),
        .I3(io_address_riuclk[7]),
        .I4(io_address_riuclk[2]),
        .I5(io_address_riuclk[0]),
        .O(\riu_nibble_8[0]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFBFFF33B)) 
    \riu_nibble_8[0]_INST_0_i_4 
       (.I0(io_address_riuclk[4]),
        .I1(\riu_nibble_8[0]_INST_0_i_11_n_0 ),
        .I2(io_address_riuclk[14]),
        .I3(io_address_riuclk[16]),
        .I4(io_address_riuclk[10]),
        .I5(io_address_riuclk[12]),
        .O(\riu_nibble_8[0]_INST_0_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    \riu_nibble_8[0]_INST_0_i_5 
       (.I0(io_address_riuclk[5]),
        .I1(io_address_riuclk[13]),
        .I2(io_address_riuclk[3]),
        .I3(io_address_riuclk[7]),
        .I4(\riu_addr_cal[1]_INST_0_i_10_n_0 ),
        .I5(\riu_nibble_8[0]_INST_0_i_12_n_0 ),
        .O(\riu_nibble_8[0]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF15FF)) 
    \riu_nibble_8[0]_INST_0_i_6 
       (.I0(\riu_nibble_8[0]_INST_0_i_13_n_0 ),
        .I1(io_address_riuclk[14]),
        .I2(\riu_addr_cal[1]_INST_0_i_10_n_0 ),
        .I3(io_address_riuclk[2]),
        .I4(io_address_riuclk[7]),
        .I5(io_address_riuclk[13]),
        .O(\riu_nibble_8[0]_INST_0_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_nibble_8[0]_INST_0_i_7 
       (.I0(io_address_riuclk[1]),
        .I1(io_address_riuclk[2]),
        .O(\riu_nibble_8[0]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800000000)) 
    \riu_nibble_8[0]_INST_0_i_8 
       (.I0(io_address_riuclk[4]),
        .I1(\riu_nibble_8[0]_INST_0_i_14_n_0 ),
        .I2(io_address_riuclk[7]),
        .I3(io_address_riuclk[5]),
        .I4(io_address_riuclk[13]),
        .I5(io_address_riuclk[16]),
        .O(\riu_nibble_8[0]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFEEEFEF8)) 
    \riu_nibble_8[0]_INST_0_i_9 
       (.I0(io_address_riuclk[5]),
        .I1(io_address_riuclk[7]),
        .I2(io_address_riuclk[13]),
        .I3(\riu_nibble_8[0]_INST_0_i_15_n_0 ),
        .I4(io_address_riuclk[8]),
        .I5(\riu_nibble_8[0]_INST_0_i_16_n_0 ),
        .O(\riu_nibble_8[0]_INST_0_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAAAFF008A8A)) 
    \riu_nibble_8[1]_INST_0_i_1 
       (.I0(\riu_nibble_8[1]_INST_0_i_2_n_0 ),
        .I1(\riu_nibble_8[1]_INST_0_i_3_n_0 ),
        .I2(\riu_nibble_8[1]_INST_0_i_4_n_0 ),
        .I3(\riu_nibble_8[1]_INST_0_i_5_n_0 ),
        .I4(io_address_riuclk[12]),
        .I5(\io_address_riuclk_reg[19] ),
        .O(\io_address_riuclk_reg[12] ));
  LUT6 #(
    .INIT(64'h00000000000F1100)) 
    \riu_nibble_8[1]_INST_0_i_10 
       (.I0(\io_address_riuclk_reg[2] ),
        .I1(\riu_nibble_8[1]_INST_0_i_14_n_0 ),
        .I2(\riu_nibble_8[1]_INST_0_i_15_n_0 ),
        .I3(io_address_riuclk[6]),
        .I4(io_address_riuclk[8]),
        .I5(io_address_riuclk[9]),
        .O(\riu_nibble_8[1]_INST_0_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDFDFDFDFDDD)) 
    \riu_nibble_8[1]_INST_0_i_11 
       (.I0(io_address_riuclk[4]),
        .I1(io_address_riuclk[14]),
        .I2(io_address_riuclk[3]),
        .I3(io_address_riuclk[1]),
        .I4(io_address_riuclk[2]),
        .I5(io_address_riuclk[0]),
        .O(\riu_nibble_8[1]_INST_0_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h00000300A0A00000)) 
    \riu_nibble_8[1]_INST_0_i_12 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[4]),
        .I2(io_address_riuclk[3]),
        .I3(io_address_riuclk[0]),
        .I4(io_address_riuclk[9]),
        .I5(\riu_addr_cal[1]_INST_0_i_11_n_0 ),
        .O(\riu_nibble_8[1]_INST_0_i_12_n_0 ));
  LUT5 #(
    .INIT(32'h00000040)) 
    \riu_nibble_8[1]_INST_0_i_13 
       (.I0(io_address_riuclk[2]),
        .I1(io_address_riuclk[8]),
        .I2(io_address_riuclk[13]),
        .I3(io_address_riuclk[7]),
        .I4(io_address_riuclk[5]),
        .O(\riu_nibble_8[1]_INST_0_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_nibble_8[1]_INST_0_i_14 
       (.I0(io_address_riuclk[4]),
        .I1(io_address_riuclk[14]),
        .O(\riu_nibble_8[1]_INST_0_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT4 #(
    .INIT(16'hFDFF)) 
    \riu_nibble_8[1]_INST_0_i_15 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[11]),
        .I2(io_address_riuclk[10]),
        .I3(io_address_riuclk[3]),
        .O(\riu_nibble_8[1]_INST_0_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h0000DDD0DDDDDDDD)) 
    \riu_nibble_8[1]_INST_0_i_2 
       (.I0(io_address_riuclk[7]),
        .I1(\riu_nibble_8[1]_INST_0_i_6_n_0 ),
        .I2(\riu_nibble_8[1]_INST_0_i_7_n_0 ),
        .I3(\riu_nibble_8[3]_INST_0_i_11_n_0 ),
        .I4(\riu_nibble_8[1]_INST_0_i_8_n_0 ),
        .I5(\riu_nibble_8[7]_INST_0_i_9_n_0 ),
        .O(\riu_nibble_8[1]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFBBBFBB9)) 
    \riu_nibble_8[1]_INST_0_i_3 
       (.I0(io_address_riuclk[16]),
        .I1(io_address_riuclk[14]),
        .I2(io_address_riuclk[10]),
        .I3(io_address_riuclk[11]),
        .I4(io_address_riuclk[5]),
        .I5(\riu_nibble_8[1]_INST_0_i_9_n_0 ),
        .O(\riu_nibble_8[1]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAFFAB)) 
    \riu_nibble_8[1]_INST_0_i_4 
       (.I0(\riu_nibble_8[1]_INST_0_i_10_n_0 ),
        .I1(\riu_nibble_8[1]_INST_0_i_11_n_0 ),
        .I2(io_address_riuclk[9]),
        .I3(\riu_nibble_8[1]_INST_0_i_12_n_0 ),
        .I4(io_address_riuclk[8]),
        .I5(io_address_riuclk[6]),
        .O(\riu_nibble_8[1]_INST_0_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFD)) 
    \riu_nibble_8[1]_INST_0_i_5 
       (.I0(io_address_riuclk[7]),
        .I1(io_address_riuclk[14]),
        .I2(io_address_riuclk[15]),
        .I3(io_address_riuclk[16]),
        .I4(io_address_riuclk[13]),
        .O(\riu_nibble_8[1]_INST_0_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \riu_nibble_8[1]_INST_0_i_6 
       (.I0(io_address_riuclk[15]),
        .I1(io_address_riuclk[14]),
        .I2(io_address_riuclk[13]),
        .O(\riu_nibble_8[1]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFEFFFFFFFFF)) 
    \riu_nibble_8[1]_INST_0_i_7 
       (.I0(\riu_nibble_8[7]_INST_0_i_20_n_0 ),
        .I1(io_address_riuclk[4]),
        .I2(io_address_riuclk[0]),
        .I3(io_address_riuclk[13]),
        .I4(io_address_riuclk[14]),
        .I5(io_address_riuclk[15]),
        .O(\riu_nibble_8[1]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000200000000)) 
    \riu_nibble_8[1]_INST_0_i_8 
       (.I0(\riu_nibble_8[1]_INST_0_i_13_n_0 ),
        .I1(\riu_nibble_8[2]_INST_0_i_14_n_0 ),
        .I2(\riu_nibble_8[2]_INST_0_i_19_n_0 ),
        .I3(io_address_riuclk[0]),
        .I4(io_address_riuclk[9]),
        .I5(io_address_riuclk[14]),
        .O(\riu_nibble_8[1]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFA8)) 
    \riu_nibble_8[1]_INST_0_i_9 
       (.I0(io_address_riuclk[5]),
        .I1(io_address_riuclk[11]),
        .I2(io_address_riuclk[10]),
        .I3(io_address_riuclk[15]),
        .I4(io_address_riuclk[13]),
        .I5(io_address_riuclk[7]),
        .O(\riu_nibble_8[1]_INST_0_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h888F888F8888888F)) 
    \riu_nibble_8[2]_INST_0 
       (.I0(io_address_riuclk[8]),
        .I1(\riu_nibble_8[2]_INST_0_i_1_n_0 ),
        .I2(io_address_riuclk[13]),
        .I3(\io_address_riuclk_reg[19] ),
        .I4(\riu_nibble_8[2]_INST_0_i_2_n_0 ),
        .I5(\riu_nibble_8[2]_INST_0_i_3_n_0 ),
        .O(riu_nibble_8[1]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \riu_nibble_8[2]_INST_0_i_1 
       (.I0(io_address_riuclk[13]),
        .I1(io_address_riuclk[14]),
        .I2(io_address_riuclk[15]),
        .I3(io_address_riuclk[12]),
        .O(\riu_nibble_8[2]_INST_0_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \riu_nibble_8[2]_INST_0_i_10 
       (.I0(\riu_nibble_8[2]_INST_0_i_22_n_0 ),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[9]),
        .I3(\io_address_riuclk_reg[14]_1 ),
        .I4(io_address_riuclk[11]),
        .I5(io_address_riuclk[15]),
        .O(\riu_nibble_8[2]_INST_0_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \riu_nibble_8[2]_INST_0_i_11 
       (.I0(\riu_addr_cal[1]_INST_0_i_5_n_0 ),
        .I1(io_address_riuclk[1]),
        .I2(io_address_riuclk[2]),
        .I3(io_address_riuclk[12]),
        .I4(io_address_riuclk[7]),
        .I5(io_address_riuclk[8]),
        .O(\riu_nibble_8[2]_INST_0_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \riu_nibble_8[2]_INST_0_i_12 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[5]),
        .I3(io_address_riuclk[6]),
        .O(\riu_nibble_8[2]_INST_0_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    \riu_nibble_8[2]_INST_0_i_13 
       (.I0(io_address_riuclk[15]),
        .I1(io_address_riuclk[11]),
        .I2(io_address_riuclk[16]),
        .I3(io_address_riuclk[14]),
        .O(\riu_nibble_8[2]_INST_0_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \riu_nibble_8[2]_INST_0_i_14 
       (.I0(io_address_riuclk[15]),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[11]),
        .O(\riu_nibble_8[2]_INST_0_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT4 #(
    .INIT(16'hEEEF)) 
    \riu_nibble_8[2]_INST_0_i_15 
       (.I0(io_address_riuclk[6]),
        .I1(io_address_riuclk[4]),
        .I2(io_address_riuclk[5]),
        .I3(io_address_riuclk[3]),
        .O(\riu_nibble_8[2]_INST_0_i_15_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \riu_nibble_8[2]_INST_0_i_16 
       (.I0(io_address_riuclk[3]),
        .I1(io_address_riuclk[2]),
        .O(\riu_nibble_8[2]_INST_0_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \riu_nibble_8[2]_INST_0_i_17 
       (.I0(io_address_riuclk[1]),
        .I1(io_address_riuclk[5]),
        .I2(io_address_riuclk[2]),
        .I3(io_address_riuclk[0]),
        .I4(io_address_riuclk[3]),
        .I5(io_address_riuclk[4]),
        .O(\riu_nibble_8[2]_INST_0_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT5 #(
    .INIT(32'hFFFEFED7)) 
    \riu_nibble_8[2]_INST_0_i_18 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[11]),
        .I2(io_address_riuclk[10]),
        .I3(io_address_riuclk[9]),
        .I4(io_address_riuclk[8]),
        .O(\riu_nibble_8[2]_INST_0_i_18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \riu_nibble_8[2]_INST_0_i_19 
       (.I0(io_address_riuclk[6]),
        .I1(io_address_riuclk[4]),
        .I2(io_address_riuclk[1]),
        .I3(io_address_riuclk[3]),
        .O(\riu_nibble_8[2]_INST_0_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hAAAABBABAAAAAAAA)) 
    \riu_nibble_8[2]_INST_0_i_2 
       (.I0(\riu_nibble_8[2]_INST_0_i_4_n_0 ),
        .I1(\riu_nibble_8[2]_INST_0_i_5_n_0 ),
        .I2(\riu_nibble_8[2]_INST_0_i_6_n_0 ),
        .I3(\riu_nibble_8[2]_INST_0_i_7_n_0 ),
        .I4(\riu_nibble_8[2]_INST_0_i_8_n_0 ),
        .I5(\riu_nibble_8[2]_INST_0_i_9_n_0 ),
        .O(\riu_nibble_8[2]_INST_0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_nibble_8[2]_INST_0_i_20 
       (.I0(io_address_riuclk[0]),
        .I1(io_address_riuclk[2]),
        .O(\riu_nibble_8[2]_INST_0_i_20_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \riu_nibble_8[2]_INST_0_i_21 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[15]),
        .O(\riu_nibble_8[2]_INST_0_i_21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_nibble_8[2]_INST_0_i_22 
       (.I0(io_address_riuclk[6]),
        .I1(io_address_riuclk[5]),
        .O(\riu_nibble_8[2]_INST_0_i_22_n_0 ));
  LUT6 #(
    .INIT(64'h4444444444F44444)) 
    \riu_nibble_8[2]_INST_0_i_3 
       (.I0(\riu_nibble_8[2]_INST_0_i_10_n_0 ),
        .I1(\riu_nibble_8[2]_INST_0_i_11_n_0 ),
        .I2(io_address_riuclk[8]),
        .I3(\riu_nibble_8[3]_INST_0_i_5_n_0 ),
        .I4(io_address_riuclk[12]),
        .I5(io_address_riuclk[16]),
        .O(\riu_nibble_8[2]_INST_0_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_nibble_8[2]_INST_0_i_4 
       (.I0(io_address_riuclk[7]),
        .I1(io_address_riuclk[12]),
        .O(\riu_nibble_8[2]_INST_0_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000200000000)) 
    \riu_nibble_8[2]_INST_0_i_5 
       (.I0(io_address_riuclk[4]),
        .I1(io_address_riuclk[8]),
        .I2(\riu_nibble_8[2]_INST_0_i_12_n_0 ),
        .I3(\riu_nibble_8[2]_INST_0_i_13_n_0 ),
        .I4(\io_address_riuclk_reg[1] ),
        .I5(io_address_riuclk[3]),
        .O(\riu_nibble_8[2]_INST_0_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT4 #(
    .INIT(16'h2829)) 
    \riu_nibble_8[2]_INST_0_i_6 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[9]),
        .I2(io_address_riuclk[8]),
        .I3(io_address_riuclk[0]),
        .O(\riu_nibble_8[2]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFF5FFFFFFF5)) 
    \riu_nibble_8[2]_INST_0_i_7 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[1]),
        .I2(\riu_nibble_8[2]_INST_0_i_14_n_0 ),
        .I3(\riu_nibble_8[2]_INST_0_i_15_n_0 ),
        .I4(io_address_riuclk[16]),
        .I5(\riu_nibble_8[2]_INST_0_i_16_n_0 ),
        .O(\riu_nibble_8[2]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000116)) 
    \riu_nibble_8[2]_INST_0_i_8 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[8]),
        .I2(io_address_riuclk[10]),
        .I3(io_address_riuclk[6]),
        .I4(\riu_nibble_8[2]_INST_0_i_17_n_0 ),
        .I5(\riu_nibble_8[2]_INST_0_i_13_n_0 ),
        .O(\riu_nibble_8[2]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \riu_nibble_8[2]_INST_0_i_9 
       (.I0(\riu_nibble_8[2]_INST_0_i_18_n_0 ),
        .I1(\riu_nibble_8[2]_INST_0_i_19_n_0 ),
        .I2(io_address_riuclk[5]),
        .I3(io_address_riuclk[16]),
        .I4(\riu_nibble_8[2]_INST_0_i_20_n_0 ),
        .I5(\riu_nibble_8[2]_INST_0_i_21_n_0 ),
        .O(\riu_nibble_8[2]_INST_0_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h5555555500000040)) 
    \riu_nibble_8[3]_INST_0 
       (.I0(\riu_nibble_8[3]_INST_0_i_1_n_0 ),
        .I1(\riu_nibble_8[3]_INST_0_i_2_n_0 ),
        .I2(\riu_nibble_8[3]_INST_0_i_3_n_0 ),
        .I3(io_address_riuclk[16]),
        .I4(\io_address_riuclk_reg[19] ),
        .I5(io_address_riuclk[13]),
        .O(riu_nibble_8[2]));
  LUT6 #(
    .INIT(64'hFFFFBBBB0000000F)) 
    \riu_nibble_8[3]_INST_0_i_1 
       (.I0(\riu_nibble_8[3]_INST_0_i_5_n_0 ),
        .I1(io_address_riuclk[9]),
        .I2(\riu_nibble_8[3]_INST_0_i_6_n_0 ),
        .I3(\riu_nibble_8[3]_INST_0_i_7_n_0 ),
        .I4(io_address_riuclk[12]),
        .I5(io_address_riuclk[13]),
        .O(\riu_nibble_8[3]_INST_0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_nibble_8[3]_INST_0_i_10 
       (.I0(io_address_riuclk[6]),
        .I1(io_address_riuclk[7]),
        .O(\riu_nibble_8[3]_INST_0_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT4 #(
    .INIT(16'hFEEF)) 
    \riu_nibble_8[3]_INST_0_i_11 
       (.I0(io_address_riuclk[10]),
        .I1(io_address_riuclk[11]),
        .I2(io_address_riuclk[9]),
        .I3(io_address_riuclk[8]),
        .O(\riu_nibble_8[3]_INST_0_i_11_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \riu_nibble_8[3]_INST_0_i_12 
       (.I0(io_address_riuclk[23]),
        .I1(io_address_riuclk[22]),
        .I2(io_address_riuclk[24]),
        .I3(io_address_riuclk[21]),
        .O(\riu_nibble_8[3]_INST_0_i_12_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \riu_nibble_8[3]_INST_0_i_13 
       (.I0(io_address_riuclk[26]),
        .I1(io_address_riuclk[27]),
        .I2(io_address_riuclk[25]),
        .O(\riu_nibble_8[3]_INST_0_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h00CC11DD01CC22EE)) 
    \riu_nibble_8[3]_INST_0_i_2 
       (.I0(io_address_riuclk[4]),
        .I1(io_address_riuclk[12]),
        .I2(io_address_riuclk[3]),
        .I3(\riu_nibble_8[3]_INST_0_i_5_n_0 ),
        .I4(\riu_nibble_8[3]_INST_0_i_8_n_0 ),
        .I5(io_address_riuclk[5]),
        .O(\riu_nibble_8[3]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000F0A0ACCCC)) 
    \riu_nibble_8[3]_INST_0_i_3 
       (.I0(\riu_nibble_8[3]_INST_0_i_9_n_0 ),
        .I1(io_address_riuclk[9]),
        .I2(\riu_nibble_8[3]_INST_0_i_10_n_0 ),
        .I3(\riu_nibble_8[3]_INST_0_i_11_n_0 ),
        .I4(io_address_riuclk[14]),
        .I5(io_address_riuclk[15]),
        .O(\riu_nibble_8[3]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \riu_nibble_8[3]_INST_0_i_4 
       (.I0(\riu_nibble_8[3]_INST_0_i_12_n_0 ),
        .I1(io_address_riuclk[19]),
        .I2(io_address_riuclk[18]),
        .I3(io_address_riuclk[20]),
        .I4(io_address_riuclk[17]),
        .I5(\riu_nibble_8[3]_INST_0_i_13_n_0 ),
        .O(\io_address_riuclk_reg[19] ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_nibble_8[3]_INST_0_i_5 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[15]),
        .O(\riu_nibble_8[3]_INST_0_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \riu_nibble_8[3]_INST_0_i_6 
       (.I0(io_address_riuclk[1]),
        .I1(io_address_riuclk[2]),
        .O(\riu_nibble_8[3]_INST_0_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_nibble_8[3]_INST_0_i_7 
       (.I0(io_address_riuclk[4]),
        .I1(io_address_riuclk[5]),
        .O(\riu_nibble_8[3]_INST_0_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \riu_nibble_8[3]_INST_0_i_8 
       (.I0(io_address_riuclk[10]),
        .I1(io_address_riuclk[11]),
        .I2(io_address_riuclk[14]),
        .O(\riu_nibble_8[3]_INST_0_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT4 #(
    .INIT(16'h0116)) 
    \riu_nibble_8[3]_INST_0_i_9 
       (.I0(io_address_riuclk[11]),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[8]),
        .I3(io_address_riuclk[9]),
        .O(\riu_nibble_8[3]_INST_0_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF1FF11111111)) 
    \riu_nibble_8[4]_INST_0_i_1 
       (.I0(\riu_nibble_8[4]_INST_0_i_2_n_0 ),
        .I1(\riu_nibble_8[4]_INST_0_i_3_n_0 ),
        .I2(\io_address_riuclk_reg[19] ),
        .I3(\riu_nibble_8[4]_INST_0_i_4_n_0 ),
        .I4(\riu_nibble_8[4]_INST_0_i_5_n_0 ),
        .I5(\riu_nibble_8[4]_INST_0_i_6_n_0 ),
        .O(\io_address_riuclk_reg[10] ));
  LUT6 #(
    .INIT(64'h02020202020E0202)) 
    \riu_nibble_8[4]_INST_0_i_2 
       (.I0(io_address_riuclk[10]),
        .I1(io_address_riuclk[15]),
        .I2(io_address_riuclk[14]),
        .I3(\riu_nibble_8[7]_INST_0_i_7_n_0 ),
        .I4(\riu_nibble_8[4]_INST_0_i_7_n_0 ),
        .I5(io_address_riuclk[5]),
        .O(\riu_nibble_8[4]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000004040E000000)) 
    \riu_nibble_8[4]_INST_0_i_3 
       (.I0(\riu_addr_cal[1]_INST_0_i_11_n_0 ),
        .I1(\riu_addr_cal[1]_INST_0_i_10_n_0 ),
        .I2(\riu_nibble_8[4]_INST_0_i_8_n_0 ),
        .I3(io_address_riuclk[2]),
        .I4(\riu_nibble_8[4]_INST_0_i_9_n_0 ),
        .I5(io_address_riuclk[5]),
        .O(\riu_nibble_8[4]_INST_0_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \riu_nibble_8[4]_INST_0_i_4 
       (.I0(io_address_riuclk[16]),
        .I1(io_address_riuclk[13]),
        .O(\riu_nibble_8[4]_INST_0_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hEFEFEF55BBBBEF55)) 
    \riu_nibble_8[4]_INST_0_i_5 
       (.I0(io_address_riuclk[12]),
        .I1(io_address_riuclk[4]),
        .I2(io_address_riuclk[1]),
        .I3(io_address_riuclk[15]),
        .I4(io_address_riuclk[14]),
        .I5(\riu_addr_cal[1]_INST_0_i_11_n_0 ),
        .O(\riu_nibble_8[4]_INST_0_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT5 #(
    .INIT(32'hFFFFFDFF)) 
    \riu_nibble_8[4]_INST_0_i_6 
       (.I0(io_address_riuclk[13]),
        .I1(io_address_riuclk[14]),
        .I2(io_address_riuclk[15]),
        .I3(io_address_riuclk[10]),
        .I4(io_address_riuclk[12]),
        .O(\riu_nibble_8[4]_INST_0_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \riu_nibble_8[4]_INST_0_i_7 
       (.I0(io_address_riuclk[2]),
        .I1(io_address_riuclk[3]),
        .O(\riu_nibble_8[4]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF8FF)) 
    \riu_nibble_8[4]_INST_0_i_8 
       (.I0(io_address_riuclk[10]),
        .I1(io_address_riuclk[11]),
        .I2(io_address_riuclk[15]),
        .I3(io_address_riuclk[14]),
        .I4(io_address_riuclk[6]),
        .I5(io_address_riuclk[7]),
        .O(\riu_nibble_8[4]_INST_0_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \riu_nibble_8[4]_INST_0_i_9 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[3]),
        .I2(io_address_riuclk[8]),
        .O(\riu_nibble_8[4]_INST_0_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    \riu_nibble_8[6]_INST_0 
       (.I0(\riu_nibble_8[6]_INST_0_i_1_n_0 ),
        .I1(\io_address_riuclk_reg[14]_0 ),
        .I2(\riu_nibble_8[6]_INST_0_i_2_n_0 ),
        .I3(\io_address_riuclk_reg[16] ),
        .I4(\io_address_riuclk_reg[16]_0 ),
        .I5(\riu_nibble_8[6]_INST_0_i_3_n_0 ),
        .O(riu_nibble_8[3]));
  LUT6 #(
    .INIT(64'h0404040404040455)) 
    \riu_nibble_8[6]_INST_0_i_1 
       (.I0(\io_address_riuclk_reg[5] ),
        .I1(\io_address_riuclk_reg[3] ),
        .I2(\riu_nibble_8[6]_INST_0_i_4_n_0 ),
        .I3(io_address_riuclk[13]),
        .I4(\io_address_riuclk_reg[26] ),
        .I5(\riu_nibble_8[6]_INST_0_i_5_n_0 ),
        .O(\riu_nibble_8[6]_INST_0_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \riu_nibble_8[6]_INST_0_i_10 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[11]),
        .I2(io_address_riuclk[8]),
        .I3(io_address_riuclk[10]),
        .O(\io_address_riuclk_reg[9] ));
  LUT6 #(
    .INIT(64'h0001000000010011)) 
    \riu_nibble_8[6]_INST_0_i_2 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[15]),
        .I2(io_address_riuclk[11]),
        .I3(\riu_nibble_8[6]_INST_0_i_6_n_0 ),
        .I4(io_address_riuclk[13]),
        .I5(\io_address_riuclk_reg[19] ),
        .O(\riu_nibble_8[6]_INST_0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \riu_nibble_8[6]_INST_0_i_3 
       (.I0(io_address_riuclk[13]),
        .I1(\riu_nibble_8[6]_INST_0_i_7_n_0 ),
        .I2(\io_address_riuclk_reg[19] ),
        .I3(\io_address_riuclk_reg[12]_0 ),
        .I4(\io_address_riuclk_reg[14]_1 ),
        .I5(\io_address_riuclk_reg[9] ),
        .O(\riu_nibble_8[6]_INST_0_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \riu_nibble_8[6]_INST_0_i_4 
       (.I0(io_address_riuclk[13]),
        .I1(io_address_riuclk[1]),
        .I2(io_address_riuclk[12]),
        .I3(io_address_riuclk[15]),
        .I4(io_address_riuclk[0]),
        .I5(io_address_riuclk[2]),
        .O(\riu_nibble_8[6]_INST_0_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \riu_nibble_8[6]_INST_0_i_5 
       (.I0(io_address_riuclk[3]),
        .I1(io_address_riuclk[1]),
        .I2(io_address_riuclk[0]),
        .I3(io_address_riuclk[2]),
        .I4(io_address_riuclk[7]),
        .I5(io_address_riuclk[4]),
        .O(\riu_nibble_8[6]_INST_0_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT3 #(
    .INIT(8'hE3)) 
    \riu_nibble_8[6]_INST_0_i_6 
       (.I0(io_address_riuclk[16]),
        .I1(io_address_riuclk[13]),
        .I2(io_address_riuclk[12]),
        .O(\riu_nibble_8[6]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF0FFEF)) 
    \riu_nibble_8[6]_INST_0_i_7 
       (.I0(\riu_nibble_8[0]_INST_0_i_7_n_0 ),
        .I1(io_address_riuclk[3]),
        .I2(io_address_riuclk[7]),
        .I3(io_address_riuclk[6]),
        .I4(io_address_riuclk[4]),
        .I5(io_address_riuclk[5]),
        .O(\riu_nibble_8[6]_INST_0_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \riu_nibble_8[6]_INST_0_i_8 
       (.I0(io_address_riuclk[12]),
        .I1(io_address_riuclk[15]),
        .O(\io_address_riuclk_reg[12]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \riu_nibble_8[6]_INST_0_i_9 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[16]),
        .O(\io_address_riuclk_reg[14]_1 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFE0FFFFFF)) 
    \riu_nibble_8[7]_INST_0_i_1 
       (.I0(\riu_nibble_8[7]_INST_0_i_7_n_0 ),
        .I1(\riu_addr_cal[3]_INST_0_i_3_n_0 ),
        .I2(\riu_nibble_8[7]_INST_0_i_8_n_0 ),
        .I3(\riu_nibble_8[7]_INST_0_i_9_n_0 ),
        .I4(io_address_riuclk[14]),
        .I5(io_address_riuclk[15]),
        .O(\io_address_riuclk_reg[14]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFE9)) 
    \riu_nibble_8[7]_INST_0_i_10 
       (.I0(io_address_riuclk[8]),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[11]),
        .I3(io_address_riuclk[4]),
        .I4(io_address_riuclk[9]),
        .I5(\riu_nibble_8[7]_INST_0_i_20_n_0 ),
        .O(\riu_nibble_8[7]_INST_0_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \riu_nibble_8[7]_INST_0_i_11 
       (.I0(\riu_nibble_8[3]_INST_0_i_13_n_0 ),
        .I1(\riu_nibble_8[7]_INST_0_i_21_n_0 ),
        .I2(\riu_nibble_8[3]_INST_0_i_12_n_0 ),
        .I3(\io_address_riuclk_reg[12]_0 ),
        .I4(\io_address_riuclk_reg[14]_1 ),
        .I5(\io_address_riuclk_reg[9] ),
        .O(\io_address_riuclk_reg[26] ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \riu_nibble_8[7]_INST_0_i_12 
       (.I0(io_address_riuclk[2]),
        .I1(io_address_riuclk[1]),
        .I2(io_address_riuclk[4]),
        .I3(io_address_riuclk[3]),
        .O(\io_address_riuclk_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \riu_nibble_8[7]_INST_0_i_13 
       (.I0(io_address_riuclk[6]),
        .I1(io_address_riuclk[4]),
        .I2(io_address_riuclk[12]),
        .I3(io_address_riuclk[7]),
        .O(\riu_nibble_8[7]_INST_0_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFB)) 
    \riu_nibble_8[7]_INST_0_i_14 
       (.I0(io_address_riuclk[14]),
        .I1(io_address_riuclk[15]),
        .I2(io_address_riuclk[13]),
        .I3(io_address_riuclk[3]),
        .I4(io_address_riuclk[5]),
        .I5(\riu_addr_cal[1]_INST_0_i_11_n_0 ),
        .O(\riu_nibble_8[7]_INST_0_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \riu_nibble_8[7]_INST_0_i_15 
       (.I0(io_address_riuclk[9]),
        .I1(io_address_riuclk[10]),
        .I2(io_address_riuclk[11]),
        .O(\riu_nibble_8[7]_INST_0_i_15_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \riu_nibble_8[7]_INST_0_i_16 
       (.I0(\riu_nibble_8[7]_INST_0_i_19_n_0 ),
        .I1(\riu_nibble_8[7]_INST_0_i_22_n_0 ),
        .I2(\riu_nibble_8[3]_INST_0_i_12_n_0 ),
        .I3(\riu_nibble_8[7]_INST_0_i_21_n_0 ),
        .I4(\riu_nibble_8[3]_INST_0_i_13_n_0 ),
        .O(\io_address_riuclk_reg[3] ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \riu_nibble_8[7]_INST_0_i_17 
       (.I0(io_address_riuclk[1]),
        .I1(io_address_riuclk[2]),
        .I2(io_address_riuclk[0]),
        .O(\io_address_riuclk_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT5 #(
    .INIT(32'hFFFEFEEA)) 
    \riu_nibble_8[7]_INST_0_i_19 
       (.I0(io_address_riuclk[3]),
        .I1(io_address_riuclk[9]),
        .I2(io_address_riuclk[11]),
        .I3(io_address_riuclk[10]),
        .I4(io_address_riuclk[8]),
        .O(\riu_nibble_8[7]_INST_0_i_19_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \riu_nibble_8[7]_INST_0_i_2 
       (.I0(\riu_addr_cal[3]_INST_0_i_3_n_0 ),
        .I1(\io_address_riuclk_reg[19] ),
        .I2(io_address_riuclk[16]),
        .I3(io_address_riuclk[14]),
        .I4(io_address_riuclk[15]),
        .I5(\riu_nibble_8[7]_INST_0_i_10_n_0 ),
        .O(\io_address_riuclk_reg[16] ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \riu_nibble_8[7]_INST_0_i_20 
       (.I0(io_address_riuclk[7]),
        .I1(io_address_riuclk[6]),
        .I2(io_address_riuclk[5]),
        .I3(io_address_riuclk[3]),
        .O(\riu_nibble_8[7]_INST_0_i_20_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \riu_nibble_8[7]_INST_0_i_21 
       (.I0(io_address_riuclk[19]),
        .I1(io_address_riuclk[18]),
        .I2(io_address_riuclk[20]),
        .I3(io_address_riuclk[17]),
        .O(\riu_nibble_8[7]_INST_0_i_21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    \riu_nibble_8[7]_INST_0_i_22 
       (.I0(io_address_riuclk[6]),
        .I1(io_address_riuclk[4]),
        .I2(io_address_riuclk[14]),
        .I3(io_address_riuclk[16]),
        .I4(io_address_riuclk[7]),
        .O(\riu_nibble_8[7]_INST_0_i_22_n_0 ));
  LUT6 #(
    .INIT(64'h0000000103030000)) 
    \riu_nibble_8[7]_INST_0_i_3 
       (.I0(\io_address_riuclk_reg[19] ),
        .I1(io_address_riuclk[14]),
        .I2(io_address_riuclk[15]),
        .I3(io_address_riuclk[16]),
        .I4(io_address_riuclk[13]),
        .I5(io_address_riuclk[12]),
        .O(\io_address_riuclk_reg[14] ));
  LUT6 #(
    .INIT(64'h0001000000000001)) 
    \riu_nibble_8[7]_INST_0_i_5 
       (.I0(\io_address_riuclk_reg[19] ),
        .I1(io_address_riuclk[16]),
        .I2(\riu_nibble_8[7]_INST_0_i_13_n_0 ),
        .I3(\riu_nibble_8[7]_INST_0_i_14_n_0 ),
        .I4(io_address_riuclk[8]),
        .I5(\riu_nibble_8[7]_INST_0_i_15_n_0 ),
        .O(\io_address_riuclk_reg[16]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEEF)) 
    \riu_nibble_8[7]_INST_0_i_7 
       (.I0(io_address_riuclk[7]),
        .I1(io_address_riuclk[6]),
        .I2(io_address_riuclk[8]),
        .I3(io_address_riuclk[9]),
        .I4(io_address_riuclk[11]),
        .I5(io_address_riuclk[10]),
        .O(\riu_nibble_8[7]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFEF)) 
    \riu_nibble_8[7]_INST_0_i_8 
       (.I0(\io_address_riuclk_reg[5] ),
        .I1(io_address_riuclk[0]),
        .I2(io_address_riuclk[8]),
        .I3(\riu_nibble_8[0]_INST_0_i_7_n_0 ),
        .I4(\riu_nibble_8[7]_INST_0_i_13_n_0 ),
        .I5(\riu_nibble_8[7]_INST_0_i_19_n_0 ),
        .O(\riu_nibble_8[7]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \riu_nibble_8[7]_INST_0_i_9 
       (.I0(io_address_riuclk[16]),
        .I1(\riu_nibble_8[3]_INST_0_i_13_n_0 ),
        .I2(io_address_riuclk[17]),
        .I3(io_address_riuclk[20]),
        .I4(\riu_addr_cal[3]_INST_0_i_15_n_0 ),
        .I5(\riu_nibble_8[3]_INST_0_i_12_n_0 ),
        .O(\riu_nibble_8[7]_INST_0_i_9_n_0 ));
  FDRE \riu_read_data_reg[0] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[0]),
        .Q(riu_read_data[0]),
        .R(1'b0));
  FDRE \riu_read_data_reg[100] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[100]),
        .Q(riu_read_data[100]),
        .R(1'b0));
  FDRE \riu_read_data_reg[101] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[101]),
        .Q(riu_read_data[101]),
        .R(1'b0));
  FDRE \riu_read_data_reg[102] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[102]),
        .Q(riu_read_data[102]),
        .R(1'b0));
  FDRE \riu_read_data_reg[103] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[103]),
        .Q(riu_read_data[103]),
        .R(1'b0));
  FDRE \riu_read_data_reg[104] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[104]),
        .Q(riu_read_data[104]),
        .R(1'b0));
  FDRE \riu_read_data_reg[105] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[105]),
        .Q(riu_read_data[105]),
        .R(1'b0));
  FDRE \riu_read_data_reg[106] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[106]),
        .Q(riu_read_data[106]),
        .R(1'b0));
  FDRE \riu_read_data_reg[107] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[107]),
        .Q(riu_read_data[107]),
        .R(1'b0));
  FDRE \riu_read_data_reg[108] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[108]),
        .Q(riu_read_data[108]),
        .R(1'b0));
  FDRE \riu_read_data_reg[109] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[109]),
        .Q(riu_read_data[109]),
        .R(1'b0));
  FDRE \riu_read_data_reg[10] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[10]),
        .Q(riu_read_data[10]),
        .R(1'b0));
  FDRE \riu_read_data_reg[110] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[110]),
        .Q(riu_read_data[110]),
        .R(1'b0));
  FDRE \riu_read_data_reg[111] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[111]),
        .Q(riu_read_data[111]),
        .R(1'b0));
  FDRE \riu_read_data_reg[112] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[112]),
        .Q(riu_read_data[112]),
        .R(1'b0));
  FDRE \riu_read_data_reg[113] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[113]),
        .Q(riu_read_data[113]),
        .R(1'b0));
  FDRE \riu_read_data_reg[114] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[114]),
        .Q(riu_read_data[114]),
        .R(1'b0));
  FDRE \riu_read_data_reg[115] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[115]),
        .Q(riu_read_data[115]),
        .R(1'b0));
  FDRE \riu_read_data_reg[116] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[116]),
        .Q(riu_read_data[116]),
        .R(1'b0));
  FDRE \riu_read_data_reg[117] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[117]),
        .Q(riu_read_data[117]),
        .R(1'b0));
  FDRE \riu_read_data_reg[118] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[118]),
        .Q(riu_read_data[118]),
        .R(1'b0));
  FDRE \riu_read_data_reg[119] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[119]),
        .Q(riu_read_data[119]),
        .R(1'b0));
  FDRE \riu_read_data_reg[11] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[11]),
        .Q(riu_read_data[11]),
        .R(1'b0));
  FDRE \riu_read_data_reg[120] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[120]),
        .Q(riu_read_data[120]),
        .R(1'b0));
  FDRE \riu_read_data_reg[121] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[121]),
        .Q(riu_read_data[121]),
        .R(1'b0));
  FDRE \riu_read_data_reg[122] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[122]),
        .Q(riu_read_data[122]),
        .R(1'b0));
  FDRE \riu_read_data_reg[123] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[123]),
        .Q(riu_read_data[123]),
        .R(1'b0));
  FDRE \riu_read_data_reg[124] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[124]),
        .Q(riu_read_data[124]),
        .R(1'b0));
  FDRE \riu_read_data_reg[125] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[125]),
        .Q(riu_read_data[125]),
        .R(1'b0));
  FDRE \riu_read_data_reg[126] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[126]),
        .Q(riu_read_data[126]),
        .R(1'b0));
  FDRE \riu_read_data_reg[127] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[127]),
        .Q(riu_read_data[127]),
        .R(1'b0));
  FDRE \riu_read_data_reg[128] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[128]),
        .Q(riu_read_data[128]),
        .R(1'b0));
  FDRE \riu_read_data_reg[129] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[129]),
        .Q(riu_read_data[129]),
        .R(1'b0));
  FDRE \riu_read_data_reg[12] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[12]),
        .Q(riu_read_data[12]),
        .R(1'b0));
  FDRE \riu_read_data_reg[130] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[130]),
        .Q(riu_read_data[130]),
        .R(1'b0));
  FDRE \riu_read_data_reg[131] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[131]),
        .Q(riu_read_data[131]),
        .R(1'b0));
  FDRE \riu_read_data_reg[132] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[132]),
        .Q(riu_read_data[132]),
        .R(1'b0));
  FDRE \riu_read_data_reg[133] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[133]),
        .Q(riu_read_data[133]),
        .R(1'b0));
  FDRE \riu_read_data_reg[134] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[134]),
        .Q(riu_read_data[134]),
        .R(1'b0));
  FDRE \riu_read_data_reg[135] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[135]),
        .Q(riu_read_data[135]),
        .R(1'b0));
  FDRE \riu_read_data_reg[136] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[136]),
        .Q(riu_read_data[136]),
        .R(1'b0));
  FDRE \riu_read_data_reg[137] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[137]),
        .Q(riu_read_data[137]),
        .R(1'b0));
  FDRE \riu_read_data_reg[138] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[138]),
        .Q(riu_read_data[138]),
        .R(1'b0));
  FDRE \riu_read_data_reg[139] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[139]),
        .Q(riu_read_data[139]),
        .R(1'b0));
  FDRE \riu_read_data_reg[13] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[13]),
        .Q(riu_read_data[13]),
        .R(1'b0));
  FDRE \riu_read_data_reg[140] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[140]),
        .Q(riu_read_data[140]),
        .R(1'b0));
  FDRE \riu_read_data_reg[141] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[141]),
        .Q(riu_read_data[141]),
        .R(1'b0));
  FDRE \riu_read_data_reg[142] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[142]),
        .Q(riu_read_data[142]),
        .R(1'b0));
  FDRE \riu_read_data_reg[143] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[143]),
        .Q(riu_read_data[143]),
        .R(1'b0));
  FDRE \riu_read_data_reg[144] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[144]),
        .Q(riu_read_data[144]),
        .R(1'b0));
  FDRE \riu_read_data_reg[145] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[145]),
        .Q(riu_read_data[145]),
        .R(1'b0));
  FDRE \riu_read_data_reg[146] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[146]),
        .Q(riu_read_data[146]),
        .R(1'b0));
  FDRE \riu_read_data_reg[147] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[147]),
        .Q(riu_read_data[147]),
        .R(1'b0));
  FDRE \riu_read_data_reg[148] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[148]),
        .Q(riu_read_data[148]),
        .R(1'b0));
  FDRE \riu_read_data_reg[149] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[149]),
        .Q(riu_read_data[149]),
        .R(1'b0));
  FDRE \riu_read_data_reg[14] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[14]),
        .Q(riu_read_data[14]),
        .R(1'b0));
  FDRE \riu_read_data_reg[150] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[150]),
        .Q(riu_read_data[150]),
        .R(1'b0));
  FDRE \riu_read_data_reg[151] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[151]),
        .Q(riu_read_data[151]),
        .R(1'b0));
  FDRE \riu_read_data_reg[152] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[152]),
        .Q(riu_read_data[152]),
        .R(1'b0));
  FDRE \riu_read_data_reg[153] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[153]),
        .Q(riu_read_data[153]),
        .R(1'b0));
  FDRE \riu_read_data_reg[154] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[154]),
        .Q(riu_read_data[154]),
        .R(1'b0));
  FDRE \riu_read_data_reg[155] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[155]),
        .Q(riu_read_data[155]),
        .R(1'b0));
  FDRE \riu_read_data_reg[156] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[156]),
        .Q(riu_read_data[156]),
        .R(1'b0));
  FDRE \riu_read_data_reg[157] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[157]),
        .Q(riu_read_data[157]),
        .R(1'b0));
  FDRE \riu_read_data_reg[158] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[158]),
        .Q(riu_read_data[158]),
        .R(1'b0));
  FDRE \riu_read_data_reg[159] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[159]),
        .Q(riu_read_data[159]),
        .R(1'b0));
  FDRE \riu_read_data_reg[15] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[15]),
        .Q(riu_read_data[15]),
        .R(1'b0));
  FDRE \riu_read_data_reg[16] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[16]),
        .Q(riu_read_data[16]),
        .R(1'b0));
  FDRE \riu_read_data_reg[17] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[17]),
        .Q(riu_read_data[17]),
        .R(1'b0));
  FDRE \riu_read_data_reg[18] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[18]),
        .Q(riu_read_data[18]),
        .R(1'b0));
  FDRE \riu_read_data_reg[19] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[19]),
        .Q(riu_read_data[19]),
        .R(1'b0));
  FDRE \riu_read_data_reg[1] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[1]),
        .Q(riu_read_data[1]),
        .R(1'b0));
  FDRE \riu_read_data_reg[20] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[20]),
        .Q(riu_read_data[20]),
        .R(1'b0));
  FDRE \riu_read_data_reg[21] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[21]),
        .Q(riu_read_data[21]),
        .R(1'b0));
  FDRE \riu_read_data_reg[22] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[22]),
        .Q(riu_read_data[22]),
        .R(1'b0));
  FDRE \riu_read_data_reg[23] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[23]),
        .Q(riu_read_data[23]),
        .R(1'b0));
  FDRE \riu_read_data_reg[24] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[24]),
        .Q(riu_read_data[24]),
        .R(1'b0));
  FDRE \riu_read_data_reg[25] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[25]),
        .Q(riu_read_data[25]),
        .R(1'b0));
  FDRE \riu_read_data_reg[26] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[26]),
        .Q(riu_read_data[26]),
        .R(1'b0));
  FDRE \riu_read_data_reg[27] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[27]),
        .Q(riu_read_data[27]),
        .R(1'b0));
  FDRE \riu_read_data_reg[28] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[28]),
        .Q(riu_read_data[28]),
        .R(1'b0));
  FDRE \riu_read_data_reg[29] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[29]),
        .Q(riu_read_data[29]),
        .R(1'b0));
  FDRE \riu_read_data_reg[2] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[2]),
        .Q(riu_read_data[2]),
        .R(1'b0));
  FDRE \riu_read_data_reg[30] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[30]),
        .Q(riu_read_data[30]),
        .R(1'b0));
  FDRE \riu_read_data_reg[31] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[31]),
        .Q(riu_read_data[31]),
        .R(1'b0));
  FDRE \riu_read_data_reg[32] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[32]),
        .Q(riu_read_data[32]),
        .R(1'b0));
  FDRE \riu_read_data_reg[33] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[33]),
        .Q(riu_read_data[33]),
        .R(1'b0));
  FDRE \riu_read_data_reg[34] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[34]),
        .Q(riu_read_data[34]),
        .R(1'b0));
  FDRE \riu_read_data_reg[35] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[35]),
        .Q(riu_read_data[35]),
        .R(1'b0));
  FDRE \riu_read_data_reg[36] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[36]),
        .Q(riu_read_data[36]),
        .R(1'b0));
  FDRE \riu_read_data_reg[37] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[37]),
        .Q(riu_read_data[37]),
        .R(1'b0));
  FDRE \riu_read_data_reg[38] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[38]),
        .Q(riu_read_data[38]),
        .R(1'b0));
  FDRE \riu_read_data_reg[39] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[39]),
        .Q(riu_read_data[39]),
        .R(1'b0));
  FDRE \riu_read_data_reg[3] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[3]),
        .Q(riu_read_data[3]),
        .R(1'b0));
  FDRE \riu_read_data_reg[40] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[40]),
        .Q(riu_read_data[40]),
        .R(1'b0));
  FDRE \riu_read_data_reg[41] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[41]),
        .Q(riu_read_data[41]),
        .R(1'b0));
  FDRE \riu_read_data_reg[42] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[42]),
        .Q(riu_read_data[42]),
        .R(1'b0));
  FDRE \riu_read_data_reg[43] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[43]),
        .Q(riu_read_data[43]),
        .R(1'b0));
  FDRE \riu_read_data_reg[44] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[44]),
        .Q(riu_read_data[44]),
        .R(1'b0));
  FDRE \riu_read_data_reg[45] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[45]),
        .Q(riu_read_data[45]),
        .R(1'b0));
  FDRE \riu_read_data_reg[46] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[46]),
        .Q(riu_read_data[46]),
        .R(1'b0));
  FDRE \riu_read_data_reg[47] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[47]),
        .Q(riu_read_data[47]),
        .R(1'b0));
  FDRE \riu_read_data_reg[48] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[48]),
        .Q(riu_read_data[48]),
        .R(1'b0));
  FDRE \riu_read_data_reg[49] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[49]),
        .Q(riu_read_data[49]),
        .R(1'b0));
  FDRE \riu_read_data_reg[4] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[4]),
        .Q(riu_read_data[4]),
        .R(1'b0));
  FDRE \riu_read_data_reg[50] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[50]),
        .Q(riu_read_data[50]),
        .R(1'b0));
  FDRE \riu_read_data_reg[51] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[51]),
        .Q(riu_read_data[51]),
        .R(1'b0));
  FDRE \riu_read_data_reg[52] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[52]),
        .Q(riu_read_data[52]),
        .R(1'b0));
  FDRE \riu_read_data_reg[53] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[53]),
        .Q(riu_read_data[53]),
        .R(1'b0));
  FDRE \riu_read_data_reg[54] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[54]),
        .Q(riu_read_data[54]),
        .R(1'b0));
  FDRE \riu_read_data_reg[55] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[55]),
        .Q(riu_read_data[55]),
        .R(1'b0));
  FDRE \riu_read_data_reg[56] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[56]),
        .Q(riu_read_data[56]),
        .R(1'b0));
  FDRE \riu_read_data_reg[57] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[57]),
        .Q(riu_read_data[57]),
        .R(1'b0));
  FDRE \riu_read_data_reg[58] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[58]),
        .Q(riu_read_data[58]),
        .R(1'b0));
  FDRE \riu_read_data_reg[59] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[59]),
        .Q(riu_read_data[59]),
        .R(1'b0));
  FDRE \riu_read_data_reg[5] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[5]),
        .Q(riu_read_data[5]),
        .R(1'b0));
  FDRE \riu_read_data_reg[60] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[60]),
        .Q(riu_read_data[60]),
        .R(1'b0));
  FDRE \riu_read_data_reg[61] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[61]),
        .Q(riu_read_data[61]),
        .R(1'b0));
  FDRE \riu_read_data_reg[62] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[62]),
        .Q(riu_read_data[62]),
        .R(1'b0));
  FDRE \riu_read_data_reg[63] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[63]),
        .Q(riu_read_data[63]),
        .R(1'b0));
  FDRE \riu_read_data_reg[64] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[64]),
        .Q(riu_read_data[64]),
        .R(1'b0));
  FDRE \riu_read_data_reg[65] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[65]),
        .Q(riu_read_data[65]),
        .R(1'b0));
  FDRE \riu_read_data_reg[66] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[66]),
        .Q(riu_read_data[66]),
        .R(1'b0));
  FDRE \riu_read_data_reg[67] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[67]),
        .Q(riu_read_data[67]),
        .R(1'b0));
  FDRE \riu_read_data_reg[68] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[68]),
        .Q(riu_read_data[68]),
        .R(1'b0));
  FDRE \riu_read_data_reg[69] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[69]),
        .Q(riu_read_data[69]),
        .R(1'b0));
  FDRE \riu_read_data_reg[6] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[6]),
        .Q(riu_read_data[6]),
        .R(1'b0));
  FDRE \riu_read_data_reg[70] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[70]),
        .Q(riu_read_data[70]),
        .R(1'b0));
  FDRE \riu_read_data_reg[71] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[71]),
        .Q(riu_read_data[71]),
        .R(1'b0));
  FDRE \riu_read_data_reg[72] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[72]),
        .Q(riu_read_data[72]),
        .R(1'b0));
  FDRE \riu_read_data_reg[73] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[73]),
        .Q(riu_read_data[73]),
        .R(1'b0));
  FDRE \riu_read_data_reg[74] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[74]),
        .Q(riu_read_data[74]),
        .R(1'b0));
  FDRE \riu_read_data_reg[75] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[75]),
        .Q(riu_read_data[75]),
        .R(1'b0));
  FDRE \riu_read_data_reg[76] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[76]),
        .Q(riu_read_data[76]),
        .R(1'b0));
  FDRE \riu_read_data_reg[77] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[77]),
        .Q(riu_read_data[77]),
        .R(1'b0));
  FDRE \riu_read_data_reg[78] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[78]),
        .Q(riu_read_data[78]),
        .R(1'b0));
  FDRE \riu_read_data_reg[79] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[79]),
        .Q(riu_read_data[79]),
        .R(1'b0));
  FDRE \riu_read_data_reg[7] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[7]),
        .Q(riu_read_data[7]),
        .R(1'b0));
  FDRE \riu_read_data_reg[80] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[80]),
        .Q(riu_read_data[80]),
        .R(1'b0));
  FDRE \riu_read_data_reg[81] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[81]),
        .Q(riu_read_data[81]),
        .R(1'b0));
  FDRE \riu_read_data_reg[82] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[82]),
        .Q(riu_read_data[82]),
        .R(1'b0));
  FDRE \riu_read_data_reg[83] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[83]),
        .Q(riu_read_data[83]),
        .R(1'b0));
  FDRE \riu_read_data_reg[84] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[84]),
        .Q(riu_read_data[84]),
        .R(1'b0));
  FDRE \riu_read_data_reg[85] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[85]),
        .Q(riu_read_data[85]),
        .R(1'b0));
  FDRE \riu_read_data_reg[86] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[86]),
        .Q(riu_read_data[86]),
        .R(1'b0));
  FDRE \riu_read_data_reg[87] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[87]),
        .Q(riu_read_data[87]),
        .R(1'b0));
  FDRE \riu_read_data_reg[88] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[88]),
        .Q(riu_read_data[88]),
        .R(1'b0));
  FDRE \riu_read_data_reg[89] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[89]),
        .Q(riu_read_data[89]),
        .R(1'b0));
  FDRE \riu_read_data_reg[8] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[8]),
        .Q(riu_read_data[8]),
        .R(1'b0));
  FDRE \riu_read_data_reg[90] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[90]),
        .Q(riu_read_data[90]),
        .R(1'b0));
  FDRE \riu_read_data_reg[91] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[91]),
        .Q(riu_read_data[91]),
        .R(1'b0));
  FDRE \riu_read_data_reg[92] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[92]),
        .Q(riu_read_data[92]),
        .R(1'b0));
  FDRE \riu_read_data_reg[93] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[93]),
        .Q(riu_read_data[93]),
        .R(1'b0));
  FDRE \riu_read_data_reg[94] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[94]),
        .Q(riu_read_data[94]),
        .R(1'b0));
  FDRE \riu_read_data_reg[95] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[95]),
        .Q(riu_read_data[95]),
        .R(1'b0));
  FDRE \riu_read_data_reg[96] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[96]),
        .Q(riu_read_data[96]),
        .R(1'b0));
  FDRE \riu_read_data_reg[97] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[97]),
        .Q(riu_read_data[97]),
        .R(1'b0));
  FDRE \riu_read_data_reg[98] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[98]),
        .Q(riu_read_data[98]),
        .R(1'b0));
  FDRE \riu_read_data_reg[99] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[99]),
        .Q(riu_read_data[99]),
        .R(1'b0));
  FDRE \riu_read_data_reg[9] 
       (.C(riu_clk),
        .CE(1'b1),
        .D(riu2clb_rd_data[9]),
        .Q(riu_read_data[9]),
        .R(1'b0));
  ddr4_0_ddr4_phy_v2_2_0_pll u_ddr4_phy_pll
       (.div_clk(div_clk),
        .mmcm_clk_in(mmcm_clk_in),
        .mmcm_lock(mmcm_lock),
        .out(div_clk_rst_r1),
        .pllGate(pllGate),
        .pll_clk(pll_clk),
        .pll_lock(pll_lock),
        .sys_clk_in(sys_clk_in),
        .sys_clk_n(sys_clk_n),
        .sys_clk_p(sys_clk_p),
        .ub_rst_out_riuclk(ub_rst_out_riuclk));
  ddr4_0_ddr4_phy_v2_2_0_iob u_ddr_iob
       (.\genBuf[1].genblk1.OBUF (\genBuf[1].genblk1.OBUF ),
        .iob2phy_d_in_byte({iob2phy_d_in_byte[128:125],iob2phy_d_in_byte[123:119],iob2phy_d_in_byte[117],iob2phy_d_in_byte[115:112],iob2phy_d_in_byte[110:106],iob2phy_d_in_byte[104],iob2phy_d_in_byte[102:99],iob2phy_d_in_byte[97:93],iob2phy_d_in_byte[91],iob2phy_d_in_byte[89:86],iob2phy_d_in_byte[84:80],iob2phy_d_in_byte[78],iob2phy_d_in_byte[76:73],iob2phy_d_in_byte[71:67],iob2phy_d_in_byte[65],iob2phy_d_in_byte[63:60],iob2phy_d_in_byte[58:54],iob2phy_d_in_byte[52],iob2phy_d_in_byte[50:47],iob2phy_d_in_byte[45:41],iob2phy_d_in_byte[39],iob2phy_d_in_byte[11:8],iob2phy_d_in_byte[6:2],iob2phy_d_in_byte[0]}),
        .iob_pin(iob_pin),
        .mcal_rd_vref_value(mcal_rd_vref_value),
        .phy2iob_odt_out_byte({phy2iob_odt_out_byte[128:125],phy2iob_odt_out_byte[122:119],phy2iob_odt_out_byte[117],phy2iob_odt_out_byte[115:112],phy2iob_odt_out_byte[109:106],phy2iob_odt_out_byte[104],phy2iob_odt_out_byte[102:99],phy2iob_odt_out_byte[96:93],phy2iob_odt_out_byte[91],phy2iob_odt_out_byte[89:86],phy2iob_odt_out_byte[83:80],phy2iob_odt_out_byte[78],phy2iob_odt_out_byte[76:73],phy2iob_odt_out_byte[70:67],phy2iob_odt_out_byte[65],phy2iob_odt_out_byte[63:60],phy2iob_odt_out_byte[57:54],phy2iob_odt_out_byte[52],phy2iob_odt_out_byte[50:47],phy2iob_odt_out_byte[44:41],phy2iob_odt_out_byte[39],phy2iob_odt_out_byte[11:8],phy2iob_odt_out_byte[5:2],phy2iob_odt_out_byte[0]}),
        .phy2iob_q_out_byte({phy2iob_q_out_byte[128:125],phy2iob_q_out_byte[123:119],phy2iob_q_out_byte[117],phy2iob_q_out_byte[115:112],phy2iob_q_out_byte[110:106],phy2iob_q_out_byte[104],phy2iob_q_out_byte[102:99],phy2iob_q_out_byte[97:93],phy2iob_q_out_byte[91],phy2iob_q_out_byte[89:86],phy2iob_q_out_byte[84:80],phy2iob_q_out_byte[78],phy2iob_q_out_byte[76:73],phy2iob_q_out_byte[71:67],phy2iob_q_out_byte[65],phy2iob_q_out_byte[63:60],phy2iob_q_out_byte[58:54],phy2iob_q_out_byte[52],phy2iob_q_out_byte[50:47],phy2iob_q_out_byte[45:23],phy2iob_q_out_byte[19:13],phy2iob_q_out_byte[11:8],phy2iob_q_out_byte[6:0]}),
        .phy2iob_t({phy2iob_t[128:125],phy2iob_t[123:119],phy2iob_t[117],phy2iob_t[115:112],phy2iob_t[110:106],phy2iob_t[104],phy2iob_t[102:99],phy2iob_t[97:93],phy2iob_t[91],phy2iob_t[89:86],phy2iob_t[84:80],phy2iob_t[78],phy2iob_t[76:73],phy2iob_t[71:67],phy2iob_t[65],phy2iob_t[63:60],phy2iob_t[58:54],phy2iob_t[52],phy2iob_t[50:47],phy2iob_t[45:41],phy2iob_t[39],phy2iob_t[11:8],phy2iob_t[6:2],phy2iob_t[0]}));
endmodule

(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b1" *) 
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "kintexu" *) (* C_NUM_BUS_RST = "1" *) 
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *) 
(* ORIG_REF_NAME = "proc_sys_reset" *) 
module ddr4_0_proc_sys_reset
   (slowest_sync_clk,
    ext_reset_in,
    aux_reset_in,
    mb_debug_sys_rst,
    dcm_locked,
    mb_reset,
    bus_struct_reset,
    peripheral_reset,
    interconnect_aresetn,
    peripheral_aresetn);
  input slowest_sync_clk;
  input ext_reset_in;
  input aux_reset_in;
  input mb_debug_sys_rst;
  input dcm_locked;
  output mb_reset;
  output [0:0]bus_struct_reset;
  output [0:0]peripheral_reset;
  output [0:0]interconnect_aresetn;
  output [0:0]peripheral_aresetn;

  wire \<const0> ;
  wire Bsr_out;
  wire MB_out;
  wire Pr_out;
  wire [0:0]bus_struct_reset;
  wire ext_reset_in;
  wire lpf_int;
  wire mb_reset;
  wire [0:0]peripheral_reset;
  wire slowest_sync_clk;

  assign interconnect_aresetn[0] = \<const0> ;
  assign peripheral_aresetn[0] = \<const0> ;
  (* BOX_TYPE = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b1),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \BSR_OUT_DFF[0].FDRE_BSR 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(Bsr_out),
        .Q(bus_struct_reset),
        .R(1'b0));
  ddr4_0_lpf EXT_LPF
       (.ext_reset_in(ext_reset_in),
        .lpf_int(lpf_int),
        .slowest_sync_clk(slowest_sync_clk));
  (* BOX_TYPE = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b1),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    FDRE_inst
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(MB_out),
        .Q(mb_reset),
        .R(1'b0));
  GND GND
       (.G(\<const0> ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b1),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \PR_OUT_DFF[0].FDRE_PER 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(Pr_out),
        .Q(peripheral_reset),
        .R(1'b0));
  ddr4_0_sequence_psr SEQ
       (.Bsr_out(Bsr_out),
        .MB_out(MB_out),
        .Pr_out(Pr_out),
        .lpf_int(lpf_int),
        .slowest_sync_clk(slowest_sync_clk));
endmodule

(* ORIG_REF_NAME = "sequence_psr" *) 
module ddr4_0_sequence_psr
   (MB_out,
    Bsr_out,
    Pr_out,
    lpf_int,
    slowest_sync_clk);
  output MB_out;
  output Bsr_out;
  output Pr_out;
  input lpf_int;
  input slowest_sync_clk;

  wire Bsr_out;
  wire Core_i_1_n_0;
  wire MB_out;
  wire Pr_out;
  wire \bsr_dec_reg_n_0_[0] ;
  wire \bsr_dec_reg_n_0_[2] ;
  wire bsr_i_1_n_0;
  wire \core_dec[0]_i_1_n_0 ;
  wire \core_dec[2]_i_1_n_0 ;
  wire \core_dec_reg_n_0_[0] ;
  wire from_sys_i_1_n_0;
  wire lpf_int;
  wire p_0_in;
  wire [2:0]p_3_out;
  wire [2:0]p_5_out;
  wire pr_dec0__0;
  wire \pr_dec_reg_n_0_[0] ;
  wire \pr_dec_reg_n_0_[1] ;
  wire \pr_dec_reg_n_0_[2] ;
  wire pr_i_1_n_0;
  wire seq_clr;
  wire [5:0]seq_cnt;
  wire seq_cnt_en;
  wire slowest_sync_clk;

  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT2 #(
    .INIT(4'h2)) 
    Core_i_1
       (.I0(MB_out),
        .I1(p_0_in),
        .O(Core_i_1_n_0));
  FDSE #(
    .INIT(1'b1)) 
    Core_reg
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(Core_i_1_n_0),
        .Q(MB_out),
        .S(lpf_int));
  ddr4_0_upcnt_n SEQ_COUNTER
       (.Q(seq_cnt),
        .seq_clr(seq_clr),
        .seq_cnt_en(seq_cnt_en),
        .slowest_sync_clk(slowest_sync_clk));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT4 #(
    .INIT(16'h0090)) 
    \bsr_dec[0]_i_1 
       (.I0(seq_cnt_en),
        .I1(seq_cnt[4]),
        .I2(seq_cnt[3]),
        .I3(seq_cnt[5]),
        .O(p_5_out[0]));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \bsr_dec[2]_i_1 
       (.I0(\pr_dec_reg_n_0_[1] ),
        .I1(\bsr_dec_reg_n_0_[0] ),
        .O(p_5_out[2]));
  FDRE #(
    .INIT(1'b0)) 
    \bsr_dec_reg[0] 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(p_5_out[0]),
        .Q(\bsr_dec_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \bsr_dec_reg[2] 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(p_5_out[2]),
        .Q(\bsr_dec_reg_n_0_[2] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    bsr_i_1
       (.I0(Bsr_out),
        .I1(\bsr_dec_reg_n_0_[2] ),
        .O(bsr_i_1_n_0));
  FDSE #(
    .INIT(1'b1)) 
    bsr_reg
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(bsr_i_1_n_0),
        .Q(Bsr_out),
        .S(lpf_int));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT4 #(
    .INIT(16'h9000)) 
    \core_dec[0]_i_1 
       (.I0(seq_cnt_en),
        .I1(seq_cnt[4]),
        .I2(seq_cnt[5]),
        .I3(seq_cnt[3]),
        .O(\core_dec[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \core_dec[2]_i_1 
       (.I0(\pr_dec_reg_n_0_[1] ),
        .I1(\core_dec_reg_n_0_[0] ),
        .O(\core_dec[2]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \core_dec_reg[0] 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(\core_dec[0]_i_1_n_0 ),
        .Q(\core_dec_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \core_dec_reg[2] 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(\core_dec[2]_i_1_n_0 ),
        .Q(p_0_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT2 #(
    .INIT(4'h8)) 
    from_sys_i_1
       (.I0(MB_out),
        .I1(seq_cnt_en),
        .O(from_sys_i_1_n_0));
  FDSE #(
    .INIT(1'b0)) 
    from_sys_reg
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(from_sys_i_1_n_0),
        .Q(seq_cnt_en),
        .S(lpf_int));
  LUT4 #(
    .INIT(16'h0018)) 
    pr_dec0
       (.I0(seq_cnt_en),
        .I1(seq_cnt[0]),
        .I2(seq_cnt[2]),
        .I3(seq_cnt[1]),
        .O(pr_dec0__0));
  LUT4 #(
    .INIT(16'h1080)) 
    \pr_dec[0]_i_1 
       (.I0(seq_cnt_en),
        .I1(seq_cnt[5]),
        .I2(seq_cnt[3]),
        .I3(seq_cnt[4]),
        .O(p_3_out[0]));
  LUT2 #(
    .INIT(4'h8)) 
    \pr_dec[2]_i_1 
       (.I0(\pr_dec_reg_n_0_[1] ),
        .I1(\pr_dec_reg_n_0_[0] ),
        .O(p_3_out[2]));
  FDRE #(
    .INIT(1'b0)) 
    \pr_dec_reg[0] 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(p_3_out[0]),
        .Q(\pr_dec_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \pr_dec_reg[1] 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(pr_dec0__0),
        .Q(\pr_dec_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \pr_dec_reg[2] 
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(p_3_out[2]),
        .Q(\pr_dec_reg_n_0_[2] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    pr_i_1
       (.I0(Pr_out),
        .I1(\pr_dec_reg_n_0_[2] ),
        .O(pr_i_1_n_0));
  FDSE #(
    .INIT(1'b1)) 
    pr_reg
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(pr_i_1_n_0),
        .Q(Pr_out),
        .S(lpf_int));
  FDRE #(
    .INIT(1'b0)) 
    seq_clr_reg
       (.C(slowest_sync_clk),
        .CE(1'b1),
        .D(1'b1),
        .Q(seq_clr),
        .R(lpf_int));
endmodule

(* ORIG_REF_NAME = "upcnt_n" *) 
module ddr4_0_upcnt_n
   (Q,
    seq_clr,
    seq_cnt_en,
    slowest_sync_clk);
  output [5:0]Q;
  input seq_clr;
  input seq_cnt_en;
  input slowest_sync_clk;

  wire [5:0]Q;
  wire clear;
  wire [5:0]q_int0;
  wire seq_clr;
  wire seq_cnt_en;
  wire slowest_sync_clk;

  LUT1 #(
    .INIT(2'h1)) 
    \q_int[0]_i_1 
       (.I0(Q[0]),
        .O(q_int0[0]));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \q_int[1]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(q_int0[1]));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \q_int[2]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(q_int0[2]));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \q_int[3]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .I3(Q[3]),
        .O(q_int0[3]));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \q_int[4]_i_1 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[4]),
        .O(q_int0[4]));
  LUT1 #(
    .INIT(2'h1)) 
    \q_int[5]_i_1 
       (.I0(seq_clr),
        .O(clear));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \q_int[5]_i_2 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[4]),
        .I5(Q[5]),
        .O(q_int0[5]));
  FDRE #(
    .INIT(1'b1)) 
    \q_int_reg[0] 
       (.C(slowest_sync_clk),
        .CE(seq_cnt_en),
        .D(q_int0[0]),
        .Q(Q[0]),
        .R(clear));
  FDRE #(
    .INIT(1'b1)) 
    \q_int_reg[1] 
       (.C(slowest_sync_clk),
        .CE(seq_cnt_en),
        .D(q_int0[1]),
        .Q(Q[1]),
        .R(clear));
  FDRE #(
    .INIT(1'b1)) 
    \q_int_reg[2] 
       (.C(slowest_sync_clk),
        .CE(seq_cnt_en),
        .D(q_int0[2]),
        .Q(Q[2]),
        .R(clear));
  FDRE #(
    .INIT(1'b1)) 
    \q_int_reg[3] 
       (.C(slowest_sync_clk),
        .CE(seq_cnt_en),
        .D(q_int0[3]),
        .Q(Q[3]),
        .R(clear));
  FDRE #(
    .INIT(1'b1)) 
    \q_int_reg[4] 
       (.C(slowest_sync_clk),
        .CE(seq_cnt_en),
        .D(q_int0[4]),
        .Q(Q[4]),
        .R(clear));
  FDRE #(
    .INIT(1'b1)) 
    \q_int_reg[5] 
       (.C(slowest_sync_clk),
        .CE(seq_cnt_en),
        .D(q_int0[5]),
        .Q(Q[5]),
        .R(clear));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2022.2"
`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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2jXzilOBqQ/mh4SLBtL9x2fM7Y6MAa6M5Q4ATAJRbYRyIgi51JCF/lccD3p4H1RtJkMGQLUiVRT7
vZ3m9UR69e+DNfkEtaI=

`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
cZrgPn9hWnGKwTDAY49L72zOZChT1T/u0EKlJOZjIbAe8WTuObJ3IviejUR/XK3HJCPSzCPDSrod
PIQ26Mm31uHr9mcpDthNoooB+WqQtXOXIJ1P8nX3uFX2jay20u9xjeICgwsq98vkVeG4OeYprX0x
UivCF7TCAv+p7DLzPC641UDlpN8oCdaowjDhYKFauR8UvTUo5NeTgQ6P/9rwB0SR1P6D1wfj18Vz
NDTkLXvHjeaTrXYVdd4kncZTXVSXrnDpKobIdOG78tFo41oXhws7lEEjSxwUho/W1cMtoGXvs5Er
NUVMLK8Ow199C21pOn8IqpTfHc2mprbtjMjfmQ==

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
K16qRfAQFh+xCRydvSglWY2SbOuAyQ9SAdvw/RZCVmbv4WzJFZ92VhquV1gnMgZ7K+gbNclgziGU
nMaQl/ztek1j5RhHw2RVzAe4p5rFvOoLclENKAEhtIlrZYJ8hUPkNBmeDf8UU5TY5fYml9wrWHpY
K1w1Bks5Hcf/D1f6mmY=

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
oTcz7rauiSR2FK8AQM+7BXmEZktrv4lwsCic1Txv0z3W+bpwI1SHT5CY0vG61W8rj2EBgJOLOi5E
E9fVQEwMuDJowS5vubjxR1A0pf18QWHaEsbyDylexQKE3UZF8PqpyRqQiJDUQRPcqzl1pedim1+O
0ukcnN9dsgwSIgJN2JPSBCY78jhs6DCJfimiC8KthD55o3XUFeBSN++9qhAN8coK2zv3J0Nmqbop
bsPCBOX4xrBMBaJRxM+EFZiSxdK3U05irjj8Kvk9eVLvtPd53h/QOWcXAOGS9LdbHVObGtttFPf1
qNGE+7fIBUqhc0uKFNMK5AIiDHwpUlSgKh0ppQ==

`pragma protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
XSyIrU29AFlPwK/5enTou/wib82EIoUeFlao/V9nzo2FRomrrAlvpI8RpY5tZwFkPtSDXIyjxs2+
oD4qPCHx8Y/NrQo53/u/9ebYFgclwajpNs9v3xgqW5TdfTmc1Ak+TZ1jz3jFMO1JfGgKUZuzWFMw
0iRBPWz68t5i/BRTP9ouwllRAn4StvDZePQUfpe+k9er2NhPAItm9J2hOHEzjD0nPTndg/za8Ya2
l0FiVt4SlRqkC9lbj5oMooyQqJW+WMtjqVTok8vJdJnHj8b2N4AfjrzewE8rtvND+JTN6mcyTmT9
wdJLflh8+qeNG53hXbmQ/2c+9BkW60s3KKf/cQ==

`pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2021_07", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
kNqMUaUWCio89xKHoSMpYvBpAxP7yW1OQzBtnGdOCgT4j/Bb8tS+E75Oa/AjjcW4BRj/1cH448VP
WmYVf4ZRlwHGn9eyGY8mXvTgsXz5JZ7Jev5kBMr8aNw7R6Hu5CVra1qEBeQdRoucxqTAvi/Yadok
DqZ39+nWm762mv5e92A+71bUSBMllpdfG+8zrPrX0QIoxqN5pZ03wOVwzmCD2PMZEnxvVMAteXCN
/QkzvhJEAVkqPxrKym1tfT/SWF05O8m4t28rhpVW2EHBcPuMARkLF2CJtsjhcM30KhEc0Ccrn9oE
C8mKOcKpS4pWYd2s+7KojvS6DGdSjjDCc6tHEQ==

`pragma protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
ADYZnlkO2rDkI3svgnZNCx0DJ86m1903Po/tR43D1LTmM4WnluT9KLlJbKnl2nRLxXDp4fKMXvMx
C9+EB5csIlhWH9AkrGe488BALk/yN2EV83NQm78d8efjSZPTUPGHj764mCrvN9yD8OIP1TV16zCJ
gw4iTaiusDoFGOAqfgwaN7hvA8bSDC9qNVH4In26FciDaC7PQV2QByHqkcM1eBWEit1hzGF26jiM
TE4cXdBNQPxEgIPJwYWpkQ0lZE/sU3o1BN+4ezPeHKvfRaRTGSHtldqY4XIw9QKBEhFvqF9vdRnq
OBD1sSplSiDb6wUeqlXLrhEIibYp64xOV3E3ww==

`pragma protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`pragma protect key_block
gJJt/qy53yCKOn+EVDHSAKbUqO8GRim9VIy226L0YMBYEQKzMg7Jj8+vvsawBx1hzVc7UVyhFDIF
5HbX1+8Pb7IEpdoR3d3f7KV1BMIMJqv3zP3cK/uniwQX12+mnefPZVVNEZ6ANzXCmLcZRTWhHtnS
ikecH1m5R8W8fy2NiIIT7ktoCMYID4QXKg21tchZx8/eC34/Ch3X5xZzdi3SAJeWLuxicGtLoyGb
inCZDV4e+u1dPhBrTLzovHaFVhwO0uc7xwljwRl4Gzpy4GkG2M7r8bZHvLFBscBB0SLqo+xLuoIJ
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j02fa7VxNNDrYqbzUP0jnjGUa72ZfK9WTCQExCQ14D5rhM7zGMUgOMg18ntfFwPbilZX8xT0VPui
8C5zWlqAJwBihMhHP5ao55n9Zomfjt+7LMW9eZvvpDAz6D2cwmOhgfMt

`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
dB4lPoQhKJ05LXFVyarEGa1JwoDdmKeQ9s/PIxtGc4AiAHb/37EdPN40vOzQp2LGz6Y/vhvX87lL
J+dkoc7Rc0Nzxh0vLiM9mSUL12fVjqt4pFOuNE9ul5eSceXdl/fozdOtZN+ySb60NuKieyB3cjWR
f4fAFiVZODSoTnLwmCP+26Qdu7XjQ1Mo56k8e/3xr0DBfO2tKrSlbCA/J6jBTv4wcXvcDPWFOCEs
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w0273Db7Yu0SOAVPf9i9NB24zNnaX939Xt6Bhg==

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
YUiYqm2DO77JiJz1PWHHnlIKtsg1XFwoaQUDQH8ReBtklfM74uYz0VQ8iOUJXjW6/5z5q8o7sD3q
wNOAsJi/DH8+yxti+H33mHi75NwgQ2VFiH2s2FNruJH6w00E2Fpbf+9hKCps3FbOKfK1d2dAszcU
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HDcqGGiBRtLRgG6YEByhi9jAH6plPGi3PVPGTg==

`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
cyPxojNSqoiabsGQqxfVAUEoAq/M2VKABwjEinnhqGh92S6DrWC6eu/fmYk8YfoO6TmpboMv1TK9
8dUmLnvIHCmfAbcM4B6A/tlUa183NUB1MU2tlnE8a3RUP3YG1iWH7R8Cp+P6mnltH1/QnrKNKHfZ
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EcQCu8fUll6Mzf5gf7o8cPuPx2hOjbh1SHfdHSSunfsWepvOfIRADZ+R0bcSZ7xBoxSUpD6OSMdl
Iibhk8H+6cGlTbQbe8agofSNY0tyWSd2ZFgo7A==

`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 2123728)
`pragma protect data_block
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`pragma protect end_protected
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2022.2"
`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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DbvxoDwPs7z3LunRxsg=

`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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3u6Hsr0S8BwNjcaDpZDnBTygUJd4JSqREnk33w==

`pragma protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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W1UOEN84AZdRTLkVSxamWo/wp8nP9fiGS/ItRw==

`pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2021_07", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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L3N7GGGvLMW2z9NSHbIFX+/eNII9fNJ9nZbgLA==

`pragma protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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1V+FGmrm1ujxmFGXwpfNKByVlfCY0oWhRJCYYQ==

`pragma protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`pragma protect key_block
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`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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BoO27Pw10lgcReGlZBz3BLO7T4ddynCx0+eSnw==

`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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vHwK3a8ZBHpfT1YH+n7wNiNUZwD4SFXm1QVx4g==

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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v04ESDEN31cSUzqUYcayvMFOnI/WNsWbFIa5+Q==

`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 517488)
`pragma protect data_block
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LemJ5TyCEHJ3QYL3A2mtla6BYo41xSDNn1hTaRvyk0lKySmfLk8rO4v53RxrxYfdfoZ+KtOMKOAh
TyagS/KS4AxlYqppCArY4VYar+koUiGOTnu2Ncn7QxAyuR3WgeVnim4+oKEPL1p5QiUrzQBUT2qC
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`pragma protect end_protected
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2022.2"
`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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Ia/zeQ8h9/dtr6QB5YkyW4wlb/LbMgXb+DGIXPSllNl0IMsRQIcQDbcQm1bO/nlhb+2pjxiuaQrl
DbvxoDwPs7z3LunRxsg=

`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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F3fMppz2sBkUd1lciw98ZE/UmNkhqBuMfIYF43j45DEJ55PBhOZNg91Ls4v3qBHyBAaYPFFoMry3
d5Fw1PZyFQSEOSSpwgyds2aN0g6oIwl7zm0LJrM9VDAOxBUE50hk+oHr4jj8J8UhHQJnlEHm1Idm
rvxKygNKRvfSpa90NYxZJFYgqnrMYg+19+9aZA==

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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jIQCgeT6q7PB4dWT6KY=

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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VBsNJqPUdKcd22q523mrdt89mpdosWD+hvZdO7ELhJniY5u9h49FFkubpN2JiUTcIcKEYxVNlds4
wyvaYUqbPVH5v2ooJwDdimS4GVn9HerCOgPwfshvQDNlMTxLcYju4v8BHMc5Rub9Q/ihvpQU74v2
ouZ9XIwA+C6pBLwvaqS8jE7HXOokgqJilaX/W/t+KEgiFry/txRTMU9WMD7tCN7lcfjCydmS3Lq+
3u6Hsr0S8BwNjcaDpZDnBTygUJd4JSqREnk33w==

`pragma protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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tUXg1j4tgIBaCQn9B0q/aG+B3gPLrudp9hLL25mVbsfiTzdekiV2hJMmhuMoavKKPJHC6zyW7kZi
80er82OQy8h+Df/fe6TRjH9xEt3/b80tRKUMbxkLfnnkAyyf1KfOhB6/uyI4mwXuQR+DsAbzybKR
YtXpOiW72tGrXTFlzcwbHamWZefqsilVpBw6V5dh33vYKGx50xwWpj76maAkpQrOpB7zufeldJe4
W1UOEN84AZdRTLkVSxamWo/wp8nP9fiGS/ItRw==

`pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2021_07", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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SghJGF32btaDLzeKm0tQ669sBtQmMIaBrlt7I9QBkNM8zN9GL92qxNC9o3UVWMOYy5BmH8nUPgcE
O6lRubeltlrTuDe7UJQ2nEPHcXjpUJJ8dxktyW+LovBy1OxW8g4GRAsmEJsoOEg0HuDdWcc4IshJ
PvwPJ7LblELAKsdkSt65y9VaklaEm7MlH4ImlgIa74TgRmutLUbWxM1QYhGE5rAzFhGU5i3RJOdx
L3N7GGGvLMW2z9NSHbIFX+/eNII9fNJ9nZbgLA==

`pragma protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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f2oERpSSSTih/ScZneSZmuPE/Zh2BU1Ajv0j+/+0uEWXU+5lLPbDJjnapTmJXih1MYPf0SHpZZmE
BKj2IEBI9MPZlh6bxpa5BWJnyPdAvHf+UNaMXU9+pmbtrzUVebql4mFJu45Z3+ehmFY4FBW3zXMF
44C4TlHACLwL3vHVMCVfeKhgdVDbpE+/IFhTStz7mZ9h9RKGanQcs6YDVM1R+2RKA1QT1fX4FiQc
1V+FGmrm1ujxmFGXwpfNKByVlfCY0oWhRJCYYQ==

`pragma protect key_keyowner="Atrenta", key_keyname="ATR-SG-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=384)
`pragma protect key_block
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OGYxkPnoN6LhjULtB2nTgjcH6NxA4puZ1ZNcndDndVBo8rTW5W1OqHq6InAG0CqPpTIkuqz3ECPl
EysI++MCDfH6tIzlekxJFIJ1McJsTq5rFuLzMMcrmkBxgcayDpOcCFuzZzCczxmt/cCCIKmDybwT
OQXmOcLJoYLP4sFu6R9c6xO8i6p++crv2N3eIxZHKbek9xBBZqQM9EYuEtsbkqAs9XZpa16i5njR
BDFxTKcP6r7JgFALJE89AZhBbate5JXWp0v4ECZD18aEL17CipwcWPutNMdG1apzSPP5y59n7rMG
yxBPz1gKHc3Emkl4WcO0hjICxqmO6dMXoY8JvBSf6ry2l0sH9Ihr3Bq5WWmlhPHnoaNr5jl//vNe
KfToWtn97eoVSt1LnmXXnSpdigbHr0UIg8AdkpdkuNRaWdVicDdgSo49

`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="CDS_RSA_KEY_VER_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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RwYsX1fVoVtXkj1LuZq0k7q9vEe4T8xMjpkeYtIHY9k0Xhy1Lq/xRlfzGAf9fvf9e+f4r7aR/Sb/
uCZxxugG5niTwLENY1n3NthYL0jvo8Fmdw4Qg0nTCGWlVCws+09K0g9/lx6I9EcuHHemcHO3fOZG
lMc4NaPNozKwnyDMoWUkwiVxyFEPFaQLNYqzjvR+CqrWfhFLo96JWhL+eaDoNuZoBVYQtNH5ZwBL
BoO27Pw10lgcReGlZBz3BLO7T4ddynCx0+eSnw==

`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
PiP7AjOQqqouyQMoBQqgWIDhUSViq94rIvGiIJ/UKMDspM/yXw1caE8AhWHTjYckC4yLpPAz5P6s
1Z6flzDPrzVwg4e59X2cc4IMCHhedna0rDO804njcc6amRDTeLsMLTkWfvomB4xwszm2AgT+PRnB
WHd09ZUDVFjiBXT+Oa9AicgGJHrX3w823yBPuAa704kje/SzgtiDpcTU1eLmLhLW7LpEd9KIHd9s
ER7Uk9Orws0Kq9PMTqMX4hMn5K5mFakOeOURiEbUjdv5RiIJ2g/PlQXSItM8fHsBTQa6fOaJwQTI
vHwK3a8ZBHpfT1YH+n7wNiNUZwD4SFXm1QVx4g==

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
Ul5ZfTHJwMctaNhYRortUZizYMPYRef7uYqPSuMkxsArnxI/cjGh+KRMwzV86hyp/6TXSJIjm5ec
2wX2UONdPN+DOJ84jYC4JbgJQrPnTj7ioD8uLX/WlyPcQzyF5keqFgj5eR5s13FskVWCuAWf5m9w
mhFEKFjVXDAr7gVgAJh/hL8P6Psrnf+LGfiM8JhnDepsHEYykGlpD3fzru2BGgqHWqPqFMcnyVGl
vysaIXiJz/eYKvO8RGcgd3DJAM/wPm9A0m/DWcmSnczOgTjoqkHcBg2H5uJMLvufzmjImi6LYEqq
v04ESDEN31cSUzqUYcayvMFOnI/WNsWbFIa5+Q==

`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19728)
`pragma protect data_block
B4OEEMpy+B1fswr8p4o3XZYFyTz7Eq8hBHEwkgoj9NXfJK1QjHlniT6AmUmdscm/6bfYFofsmB5j
OH5P1rDIrxZbLd4S+Pi28eHvyTv4hUkxN30h4zKjy2+flbT0wja1Z0A4+ywYgzoR42VWUhnx5uK7
QldWuVuCpKzOB/lQXmYlj5/crkN31aXrmUiGYRIV9ATMLkKO4goH16CycoJxvu8ss64CUivkXxVW
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
